1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved.
3 * Copyright(c) 2018 Synopsys, Inc. All rights reserved.
6 #ifndef __AXGBE_COMMON_H__
7 #define __AXGBE_COMMON_H__
9 #include "axgbe_logs.h"
13 #include <sys/queue.h>
24 #include <rte_byteorder.h>
25 #include <rte_memory.h>
26 #include <rte_malloc.h>
27 #include <rte_hexdump.h>
29 #include <rte_debug.h>
30 #include <rte_branch_prediction.h>
32 #include <rte_memzone.h>
33 #include <rte_ether.h>
34 #include <rte_ethdev.h>
36 #include <rte_errno.h>
37 #include <rte_ethdev_pci.h>
38 #include <rte_common.h>
39 #include <rte_cycles.h>
42 #define BIT(nr) (1 << (nr))
44 #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
49 /* DMA register offsets */
51 #define DMA_SBMR 0x3004
52 #define DMA_ISR 0x3008
53 #define DMA_AXIARCR 0x3010
54 #define DMA_AXIAWCR 0x3018
55 #define DMA_AXIAWRCR 0x301c
56 #define DMA_DSR0 0x3020
57 #define DMA_DSR1 0x3024
58 #define EDMA_TX_CONTROL 0x3040
59 #define EDMA_RX_CONTROL 0x3044
61 /* DMA register entry bit positions and sizes */
62 #define DMA_AXIARCR_DRC_INDEX 0
63 #define DMA_AXIARCR_DRC_WIDTH 4
64 #define DMA_AXIARCR_DRD_INDEX 4
65 #define DMA_AXIARCR_DRD_WIDTH 2
66 #define DMA_AXIARCR_TEC_INDEX 8
67 #define DMA_AXIARCR_TEC_WIDTH 4
68 #define DMA_AXIARCR_TED_INDEX 12
69 #define DMA_AXIARCR_TED_WIDTH 2
70 #define DMA_AXIARCR_THC_INDEX 16
71 #define DMA_AXIARCR_THC_WIDTH 4
72 #define DMA_AXIARCR_THD_INDEX 20
73 #define DMA_AXIARCR_THD_WIDTH 2
74 #define DMA_AXIAWCR_DWC_INDEX 0
75 #define DMA_AXIAWCR_DWC_WIDTH 4
76 #define DMA_AXIAWCR_DWD_INDEX 4
77 #define DMA_AXIAWCR_DWD_WIDTH 2
78 #define DMA_AXIAWCR_RPC_INDEX 8
79 #define DMA_AXIAWCR_RPC_WIDTH 4
80 #define DMA_AXIAWCR_RPD_INDEX 12
81 #define DMA_AXIAWCR_RPD_WIDTH 2
82 #define DMA_AXIAWCR_RHC_INDEX 16
83 #define DMA_AXIAWCR_RHC_WIDTH 4
84 #define DMA_AXIAWCR_RHD_INDEX 20
85 #define DMA_AXIAWCR_RHD_WIDTH 2
86 #define DMA_AXIAWCR_RDC_INDEX 24
87 #define DMA_AXIAWCR_RDC_WIDTH 4
88 #define DMA_AXIAWCR_RDD_INDEX 28
89 #define DMA_AXIAWCR_RDD_WIDTH 2
90 #define DMA_AXIAWRCR_TDWC_INDEX 0
91 #define DMA_AXIAWRCR_TDWC_WIDTH 4
92 #define DMA_AXIAWRCR_TDWD_INDEX 4
93 #define DMA_AXIAWRCR_TDWD_WIDTH 4
94 #define DMA_AXIAWRCR_RDRC_INDEX 8
95 #define DMA_AXIAWRCR_RDRC_WIDTH 4
96 #define DMA_ISR_MACIS_INDEX 17
97 #define DMA_ISR_MACIS_WIDTH 1
98 #define DMA_ISR_MTLIS_INDEX 16
99 #define DMA_ISR_MTLIS_WIDTH 1
100 #define DMA_MR_INTM_INDEX 12
101 #define DMA_MR_INTM_WIDTH 2
102 #define DMA_MR_SWR_INDEX 0
103 #define DMA_MR_SWR_WIDTH 1
104 #define DMA_SBMR_WR_OSR_INDEX 24
105 #define DMA_SBMR_WR_OSR_WIDTH 6
106 #define DMA_SBMR_RD_OSR_INDEX 16
107 #define DMA_SBMR_RD_OSR_WIDTH 6
108 #define DMA_SBMR_AAL_INDEX 12
109 #define DMA_SBMR_AAL_WIDTH 1
110 #define DMA_SBMR_EAME_INDEX 11
111 #define DMA_SBMR_EAME_WIDTH 1
112 #define DMA_SBMR_BLEN_256_INDEX 7
113 #define DMA_SBMR_BLEN_256_WIDTH 1
114 #define DMA_SBMR_BLEN_32_INDEX 4
115 #define DMA_SBMR_BLEN_32_WIDTH 1
116 #define DMA_SBMR_UNDEF_INDEX 0
117 #define DMA_SBMR_UNDEF_WIDTH 1
119 /* DMA register values */
120 #define DMA_DSR_RPS_WIDTH 4
121 #define DMA_DSR_TPS_WIDTH 4
122 #define DMA_DSR_Q_WIDTH (DMA_DSR_RPS_WIDTH + DMA_DSR_TPS_WIDTH)
123 #define DMA_DSR0_RPS_START 8
124 #define DMA_DSR0_TPS_START 12
125 #define DMA_DSRX_FIRST_QUEUE 3
126 #define DMA_DSRX_INC 4
127 #define DMA_DSRX_QPR 4
128 #define DMA_DSRX_RPS_START 0
129 #define DMA_DSRX_TPS_START 4
130 #define DMA_TPS_STOPPED 0x00
131 #define DMA_TPS_SUSPENDED 0x06
133 /* DMA channel register offsets
134 * Multiple channels can be active. The first channel has registers
135 * that begin at 0x3100. Each subsequent channel has registers that
136 * are accessed using an offset of 0x80 from the previous channel.
138 #define DMA_CH_BASE 0x3100
139 #define DMA_CH_INC 0x80
141 #define DMA_CH_CR 0x00
142 #define DMA_CH_TCR 0x04
143 #define DMA_CH_RCR 0x08
144 #define DMA_CH_TDLR_HI 0x10
145 #define DMA_CH_TDLR_LO 0x14
146 #define DMA_CH_RDLR_HI 0x18
147 #define DMA_CH_RDLR_LO 0x1c
148 #define DMA_CH_TDTR_LO 0x24
149 #define DMA_CH_RDTR_LO 0x2c
150 #define DMA_CH_TDRLR 0x30
151 #define DMA_CH_RDRLR 0x34
152 #define DMA_CH_IER 0x38
153 #define DMA_CH_RIWT 0x3c
154 #define DMA_CH_CATDR_LO 0x44
155 #define DMA_CH_CARDR_LO 0x4c
156 #define DMA_CH_CATBR_HI 0x50
157 #define DMA_CH_CATBR_LO 0x54
158 #define DMA_CH_CARBR_HI 0x58
159 #define DMA_CH_CARBR_LO 0x5c
160 #define DMA_CH_SR 0x60
162 /* DMA channel register entry bit positions and sizes */
163 #define DMA_CH_CR_PBLX8_INDEX 16
164 #define DMA_CH_CR_PBLX8_WIDTH 1
165 #define DMA_CH_CR_SPH_INDEX 24
166 #define DMA_CH_CR_SPH_WIDTH 1
167 #define DMA_CH_IER_AIE_INDEX 14
168 #define DMA_CH_IER_AIE_WIDTH 1
169 #define DMA_CH_IER_FBEE_INDEX 12
170 #define DMA_CH_IER_FBEE_WIDTH 1
171 #define DMA_CH_IER_NIE_INDEX 15
172 #define DMA_CH_IER_NIE_WIDTH 1
173 #define DMA_CH_IER_RBUE_INDEX 7
174 #define DMA_CH_IER_RBUE_WIDTH 1
175 #define DMA_CH_IER_RIE_INDEX 6
176 #define DMA_CH_IER_RIE_WIDTH 1
177 #define DMA_CH_IER_RSE_INDEX 8
178 #define DMA_CH_IER_RSE_WIDTH 1
179 #define DMA_CH_IER_TBUE_INDEX 2
180 #define DMA_CH_IER_TBUE_WIDTH 1
181 #define DMA_CH_IER_TIE_INDEX 0
182 #define DMA_CH_IER_TIE_WIDTH 1
183 #define DMA_CH_IER_TXSE_INDEX 1
184 #define DMA_CH_IER_TXSE_WIDTH 1
185 #define DMA_CH_RCR_PBL_INDEX 16
186 #define DMA_CH_RCR_PBL_WIDTH 6
187 #define DMA_CH_RCR_RBSZ_INDEX 1
188 #define DMA_CH_RCR_RBSZ_WIDTH 14
189 #define DMA_CH_RCR_SR_INDEX 0
190 #define DMA_CH_RCR_SR_WIDTH 1
191 #define DMA_CH_RIWT_RWT_INDEX 0
192 #define DMA_CH_RIWT_RWT_WIDTH 8
193 #define DMA_CH_SR_FBE_INDEX 12
194 #define DMA_CH_SR_FBE_WIDTH 1
195 #define DMA_CH_SR_RBU_INDEX 7
196 #define DMA_CH_SR_RBU_WIDTH 1
197 #define DMA_CH_SR_RI_INDEX 6
198 #define DMA_CH_SR_RI_WIDTH 1
199 #define DMA_CH_SR_RPS_INDEX 8
200 #define DMA_CH_SR_RPS_WIDTH 1
201 #define DMA_CH_SR_TBU_INDEX 2
202 #define DMA_CH_SR_TBU_WIDTH 1
203 #define DMA_CH_SR_TI_INDEX 0
204 #define DMA_CH_SR_TI_WIDTH 1
205 #define DMA_CH_SR_TPS_INDEX 1
206 #define DMA_CH_SR_TPS_WIDTH 1
207 #define DMA_CH_TCR_OSP_INDEX 4
208 #define DMA_CH_TCR_OSP_WIDTH 1
209 #define DMA_CH_TCR_PBL_INDEX 16
210 #define DMA_CH_TCR_PBL_WIDTH 6
211 #define DMA_CH_TCR_ST_INDEX 0
212 #define DMA_CH_TCR_ST_WIDTH 1
213 #define DMA_CH_TCR_TSE_INDEX 12
214 #define DMA_CH_TCR_TSE_WIDTH 1
216 /* DMA channel register values */
217 #define DMA_OSP_DISABLE 0x00
218 #define DMA_OSP_ENABLE 0x01
223 #define DMA_PBL_16 16
224 #define DMA_PBL_32 32
225 #define DMA_PBL_64 64 /* 8 x 8 */
226 #define DMA_PBL_128 128 /* 8 x 16 */
227 #define DMA_PBL_256 256 /* 8 x 32 */
228 #define DMA_PBL_X8_DISABLE 0x00
229 #define DMA_PBL_X8_ENABLE 0x01
231 /* MAC register offsets */
232 #define MAC_TCR 0x0000
233 #define MAC_RCR 0x0004
234 #define MAC_PFR 0x0008
235 #define MAC_WTR 0x000c
236 #define MAC_HTR0 0x0010
237 #define MAC_VLANTR 0x0050
238 #define MAC_VLANHTR 0x0058
239 #define MAC_VLANIR 0x0060
240 #define MAC_IVLANIR 0x0064
241 #define MAC_RETMR 0x006c
242 #define MAC_Q0TFCR 0x0070
243 #define MAC_RFCR 0x0090
244 #define MAC_RQC0R 0x00a0
245 #define MAC_RQC1R 0x00a4
246 #define MAC_RQC2R 0x00a8
247 #define MAC_RQC3R 0x00ac
248 #define MAC_ISR 0x00b0
249 #define MAC_IER 0x00b4
250 #define MAC_RTSR 0x00b8
251 #define MAC_PMTCSR 0x00c0
252 #define MAC_RWKPFR 0x00c4
253 #define MAC_LPICSR 0x00d0
254 #define MAC_LPITCR 0x00d4
255 #define MAC_VR 0x0110
256 #define MAC_DR 0x0114
257 #define MAC_HWF0R 0x011c
258 #define MAC_HWF1R 0x0120
259 #define MAC_HWF2R 0x0124
260 #define MAC_MDIOSCAR 0x0200
261 #define MAC_MDIOSCCDR 0x0204
262 #define MAC_MDIOISR 0x0214
263 #define MAC_MDIOIER 0x0218
264 #define MAC_MDIOCL22R 0x0220
265 #define MAC_GPIOCR 0x0278
266 #define MAC_GPIOSR 0x027c
267 #define MAC_MACA0HR 0x0300
268 #define MAC_MACA0LR 0x0304
269 #define MAC_MACA1HR 0x0308
270 #define MAC_MACA1LR 0x030c
271 #define MAC_RSSCR 0x0c80
272 #define MAC_RSSAR 0x0c88
273 #define MAC_RSSDR 0x0c8c
274 #define MAC_TSCR 0x0d00
275 #define MAC_SSIR 0x0d04
276 #define MAC_STSR 0x0d08
277 #define MAC_STNR 0x0d0c
278 #define MAC_STSUR 0x0d10
279 #define MAC_STNUR 0x0d14
280 #define MAC_TSAR 0x0d18
281 #define MAC_TSSR 0x0d20
282 #define MAC_TXSNR 0x0d30
283 #define MAC_TXSSR 0x0d34
285 #define MAC_QTFCR_INC 4
286 #define MAC_MACA_INC 4
287 #define MAC_HTR_INC 4
289 #define MAC_RQC2_INC 4
290 #define MAC_RQC2_Q_PER_REG 4
292 #define MAC_MACAHR(i) (MAC_MACA0HR + ((i) * 8))
293 #define MAC_MACALR(i) (MAC_MACA0LR + ((i) * 8))
295 #define MAC_HTR(i) (MAC_HTR0 + ((i) * MAC_HTR_INC))
297 /* MAC register entry bit positions and sizes */
298 #define MAC_HWF0R_ADDMACADRSEL_INDEX 18
299 #define MAC_HWF0R_ADDMACADRSEL_WIDTH 5
300 #define MAC_HWF0R_ARPOFFSEL_INDEX 9
301 #define MAC_HWF0R_ARPOFFSEL_WIDTH 1
302 #define MAC_HWF0R_EEESEL_INDEX 13
303 #define MAC_HWF0R_EEESEL_WIDTH 1
304 #define MAC_HWF0R_GMIISEL_INDEX 1
305 #define MAC_HWF0R_GMIISEL_WIDTH 1
306 #define MAC_HWF0R_MGKSEL_INDEX 7
307 #define MAC_HWF0R_MGKSEL_WIDTH 1
308 #define MAC_HWF0R_MMCSEL_INDEX 8
309 #define MAC_HWF0R_MMCSEL_WIDTH 1
310 #define MAC_HWF0R_RWKSEL_INDEX 6
311 #define MAC_HWF0R_RWKSEL_WIDTH 1
312 #define MAC_HWF0R_RXCOESEL_INDEX 16
313 #define MAC_HWF0R_RXCOESEL_WIDTH 1
314 #define MAC_HWF0R_SAVLANINS_INDEX 27
315 #define MAC_HWF0R_SAVLANINS_WIDTH 1
316 #define MAC_HWF0R_SMASEL_INDEX 5
317 #define MAC_HWF0R_SMASEL_WIDTH 1
318 #define MAC_HWF0R_TSSEL_INDEX 12
319 #define MAC_HWF0R_TSSEL_WIDTH 1
320 #define MAC_HWF0R_TSSTSSEL_INDEX 25
321 #define MAC_HWF0R_TSSTSSEL_WIDTH 2
322 #define MAC_HWF0R_TXCOESEL_INDEX 14
323 #define MAC_HWF0R_TXCOESEL_WIDTH 1
324 #define MAC_HWF0R_VLHASH_INDEX 4
325 #define MAC_HWF0R_VLHASH_WIDTH 1
326 #define MAC_HWF1R_ADDR64_INDEX 14
327 #define MAC_HWF1R_ADDR64_WIDTH 2
328 #define MAC_HWF1R_ADVTHWORD_INDEX 13
329 #define MAC_HWF1R_ADVTHWORD_WIDTH 1
330 #define MAC_HWF1R_DBGMEMA_INDEX 19
331 #define MAC_HWF1R_DBGMEMA_WIDTH 1
332 #define MAC_HWF1R_DCBEN_INDEX 16
333 #define MAC_HWF1R_DCBEN_WIDTH 1
334 #define MAC_HWF1R_HASHTBLSZ_INDEX 24
335 #define MAC_HWF1R_HASHTBLSZ_WIDTH 3
336 #define MAC_HWF1R_L3L4FNUM_INDEX 27
337 #define MAC_HWF1R_L3L4FNUM_WIDTH 4
338 #define MAC_HWF1R_NUMTC_INDEX 21
339 #define MAC_HWF1R_NUMTC_WIDTH 3
340 #define MAC_HWF1R_RSSEN_INDEX 20
341 #define MAC_HWF1R_RSSEN_WIDTH 1
342 #define MAC_HWF1R_RXFIFOSIZE_INDEX 0
343 #define MAC_HWF1R_RXFIFOSIZE_WIDTH 5
344 #define MAC_HWF1R_SPHEN_INDEX 17
345 #define MAC_HWF1R_SPHEN_WIDTH 1
346 #define MAC_HWF1R_TSOEN_INDEX 18
347 #define MAC_HWF1R_TSOEN_WIDTH 1
348 #define MAC_HWF1R_TXFIFOSIZE_INDEX 6
349 #define MAC_HWF1R_TXFIFOSIZE_WIDTH 5
350 #define MAC_HWF2R_AUXSNAPNUM_INDEX 28
351 #define MAC_HWF2R_AUXSNAPNUM_WIDTH 3
352 #define MAC_HWF2R_PPSOUTNUM_INDEX 24
353 #define MAC_HWF2R_PPSOUTNUM_WIDTH 3
354 #define MAC_HWF2R_RXCHCNT_INDEX 12
355 #define MAC_HWF2R_RXCHCNT_WIDTH 4
356 #define MAC_HWF2R_RXQCNT_INDEX 0
357 #define MAC_HWF2R_RXQCNT_WIDTH 4
358 #define MAC_HWF2R_TXCHCNT_INDEX 18
359 #define MAC_HWF2R_TXCHCNT_WIDTH 4
360 #define MAC_HWF2R_TXQCNT_INDEX 6
361 #define MAC_HWF2R_TXQCNT_WIDTH 4
362 #define MAC_IER_TSIE_INDEX 12
363 #define MAC_IER_TSIE_WIDTH 1
364 #define MAC_ISR_MMCRXIS_INDEX 9
365 #define MAC_ISR_MMCRXIS_WIDTH 1
366 #define MAC_ISR_MMCTXIS_INDEX 10
367 #define MAC_ISR_MMCTXIS_WIDTH 1
368 #define MAC_ISR_PMTIS_INDEX 4
369 #define MAC_ISR_PMTIS_WIDTH 1
370 #define MAC_ISR_SMI_INDEX 1
371 #define MAC_ISR_SMI_WIDTH 1
372 #define MAC_ISR_LSI_INDEX 0
373 #define MAC_ISR_LSI_WIDTH 1
374 #define MAC_ISR_LS_INDEX 24
375 #define MAC_ISR_LS_WIDTH 2
376 #define MAC_ISR_TSIS_INDEX 12
377 #define MAC_ISR_TSIS_WIDTH 1
378 #define MAC_MACA1HR_AE_INDEX 31
379 #define MAC_MACA1HR_AE_WIDTH 1
380 #define MAC_MDIOIER_SNGLCOMPIE_INDEX 12
381 #define MAC_MDIOIER_SNGLCOMPIE_WIDTH 1
382 #define MAC_MDIOISR_SNGLCOMPINT_INDEX 12
383 #define MAC_MDIOISR_SNGLCOMPINT_WIDTH 1
384 #define MAC_MDIOSCAR_DA_INDEX 21
385 #define MAC_MDIOSCAR_DA_WIDTH 5
386 #define MAC_MDIOSCAR_PA_INDEX 16
387 #define MAC_MDIOSCAR_PA_WIDTH 5
388 #define MAC_MDIOSCAR_RA_INDEX 0
389 #define MAC_MDIOSCAR_RA_WIDTH 16
390 #define MAC_MDIOSCAR_REG_INDEX 0
391 #define MAC_MDIOSCAR_REG_WIDTH 21
392 #define MAC_MDIOSCCDR_BUSY_INDEX 22
393 #define MAC_MDIOSCCDR_BUSY_WIDTH 1
394 #define MAC_MDIOSCCDR_CMD_INDEX 16
395 #define MAC_MDIOSCCDR_CMD_WIDTH 2
396 #define MAC_MDIOSCCDR_CR_INDEX 19
397 #define MAC_MDIOSCCDR_CR_WIDTH 3
398 #define MAC_MDIOSCCDR_DATA_INDEX 0
399 #define MAC_MDIOSCCDR_DATA_WIDTH 16
400 #define MAC_MDIOSCCDR_SADDR_INDEX 18
401 #define MAC_MDIOSCCDR_SADDR_WIDTH 1
402 #define MAC_PFR_HMC_INDEX 2
403 #define MAC_PFR_HMC_WIDTH 1
404 #define MAC_PFR_HPF_INDEX 10
405 #define MAC_PFR_HPF_WIDTH 1
406 #define MAC_PFR_HUC_INDEX 1
407 #define MAC_PFR_HUC_WIDTH 1
408 #define MAC_PFR_PM_INDEX 4
409 #define MAC_PFR_PM_WIDTH 1
410 #define MAC_PFR_PR_INDEX 0
411 #define MAC_PFR_PR_WIDTH 1
412 #define MAC_PFR_VTFE_INDEX 16
413 #define MAC_PFR_VTFE_WIDTH 1
414 #define MAC_PMTCSR_MGKPKTEN_INDEX 1
415 #define MAC_PMTCSR_MGKPKTEN_WIDTH 1
416 #define MAC_PMTCSR_PWRDWN_INDEX 0
417 #define MAC_PMTCSR_PWRDWN_WIDTH 1
418 #define MAC_PMTCSR_RWKFILTRST_INDEX 31
419 #define MAC_PMTCSR_RWKFILTRST_WIDTH 1
420 #define MAC_PMTCSR_RWKPKTEN_INDEX 2
421 #define MAC_PMTCSR_RWKPKTEN_WIDTH 1
422 #define MAC_Q0TFCR_PT_INDEX 16
423 #define MAC_Q0TFCR_PT_WIDTH 16
424 #define MAC_Q0TFCR_TFE_INDEX 1
425 #define MAC_Q0TFCR_TFE_WIDTH 1
426 #define MAC_RCR_ACS_INDEX 1
427 #define MAC_RCR_ACS_WIDTH 1
428 #define MAC_RCR_CST_INDEX 2
429 #define MAC_RCR_CST_WIDTH 1
430 #define MAC_RCR_DCRCC_INDEX 3
431 #define MAC_RCR_DCRCC_WIDTH 1
432 #define MAC_RCR_HDSMS_INDEX 12
433 #define MAC_RCR_HDSMS_WIDTH 3
434 #define MAC_RCR_IPC_INDEX 9
435 #define MAC_RCR_IPC_WIDTH 1
436 #define MAC_RCR_JE_INDEX 8
437 #define MAC_RCR_JE_WIDTH 1
438 #define MAC_RCR_LM_INDEX 10
439 #define MAC_RCR_LM_WIDTH 1
440 #define MAC_RCR_RE_INDEX 0
441 #define MAC_RCR_RE_WIDTH 1
442 #define MAC_RFCR_PFCE_INDEX 8
443 #define MAC_RFCR_PFCE_WIDTH 1
444 #define MAC_RFCR_RFE_INDEX 0
445 #define MAC_RFCR_RFE_WIDTH 1
446 #define MAC_RFCR_UP_INDEX 1
447 #define MAC_RFCR_UP_WIDTH 1
448 #define MAC_RQC0R_RXQ0EN_INDEX 0
449 #define MAC_RQC0R_RXQ0EN_WIDTH 2
450 #define MAC_RSSAR_ADDRT_INDEX 2
451 #define MAC_RSSAR_ADDRT_WIDTH 1
452 #define MAC_RSSAR_CT_INDEX 1
453 #define MAC_RSSAR_CT_WIDTH 1
454 #define MAC_RSSAR_OB_INDEX 0
455 #define MAC_RSSAR_OB_WIDTH 1
456 #define MAC_RSSAR_RSSIA_INDEX 8
457 #define MAC_RSSAR_RSSIA_WIDTH 8
458 #define MAC_RSSCR_IP2TE_INDEX 1
459 #define MAC_RSSCR_IP2TE_WIDTH 1
460 #define MAC_RSSCR_RSSE_INDEX 0
461 #define MAC_RSSCR_RSSE_WIDTH 1
462 #define MAC_RSSCR_TCP4TE_INDEX 2
463 #define MAC_RSSCR_TCP4TE_WIDTH 1
464 #define MAC_RSSCR_UDP4TE_INDEX 3
465 #define MAC_RSSCR_UDP4TE_WIDTH 1
466 #define MAC_RSSDR_DMCH_INDEX 0
467 #define MAC_RSSDR_DMCH_WIDTH 4
468 #define MAC_SSIR_SNSINC_INDEX 8
469 #define MAC_SSIR_SNSINC_WIDTH 8
470 #define MAC_SSIR_SSINC_INDEX 16
471 #define MAC_SSIR_SSINC_WIDTH 8
472 #define MAC_TCR_SS_INDEX 29
473 #define MAC_TCR_SS_WIDTH 2
474 #define MAC_TCR_TE_INDEX 0
475 #define MAC_TCR_TE_WIDTH 1
476 #define MAC_TSCR_AV8021ASMEN_INDEX 28
477 #define MAC_TSCR_AV8021ASMEN_WIDTH 1
478 #define MAC_TSCR_SNAPTYPSEL_INDEX 16
479 #define MAC_TSCR_SNAPTYPSEL_WIDTH 2
480 #define MAC_TSCR_TSADDREG_INDEX 5
481 #define MAC_TSCR_TSADDREG_WIDTH 1
482 #define MAC_TSCR_TSCFUPDT_INDEX 1
483 #define MAC_TSCR_TSCFUPDT_WIDTH 1
484 #define MAC_TSCR_TSCTRLSSR_INDEX 9
485 #define MAC_TSCR_TSCTRLSSR_WIDTH 1
486 #define MAC_TSCR_TSENA_INDEX 0
487 #define MAC_TSCR_TSENA_WIDTH 1
488 #define MAC_TSCR_TSENALL_INDEX 8
489 #define MAC_TSCR_TSENALL_WIDTH 1
490 #define MAC_TSCR_TSEVNTENA_INDEX 14
491 #define MAC_TSCR_TSEVNTENA_WIDTH 1
492 #define MAC_TSCR_TSINIT_INDEX 2
493 #define MAC_TSCR_TSINIT_WIDTH 1
494 #define MAC_TSCR_TSIPENA_INDEX 11
495 #define MAC_TSCR_TSIPENA_WIDTH 1
496 #define MAC_TSCR_TSIPV4ENA_INDEX 13
497 #define MAC_TSCR_TSIPV4ENA_WIDTH 1
498 #define MAC_TSCR_TSIPV6ENA_INDEX 12
499 #define MAC_TSCR_TSIPV6ENA_WIDTH 1
500 #define MAC_TSCR_TSMSTRENA_INDEX 15
501 #define MAC_TSCR_TSMSTRENA_WIDTH 1
502 #define MAC_TSCR_TSVER2ENA_INDEX 10
503 #define MAC_TSCR_TSVER2ENA_WIDTH 1
504 #define MAC_TSCR_TXTSSTSM_INDEX 24
505 #define MAC_TSCR_TXTSSTSM_WIDTH 1
506 #define MAC_TSSR_TXTSC_INDEX 15
507 #define MAC_TSSR_TXTSC_WIDTH 1
508 #define MAC_TXSNR_TXTSSTSMIS_INDEX 31
509 #define MAC_TXSNR_TXTSSTSMIS_WIDTH 1
510 #define MAC_VLANHTR_VLHT_INDEX 0
511 #define MAC_VLANHTR_VLHT_WIDTH 16
512 #define MAC_VLANIR_VLTI_INDEX 20
513 #define MAC_VLANIR_VLTI_WIDTH 1
514 #define MAC_VLANIR_CSVL_INDEX 19
515 #define MAC_VLANIR_CSVL_WIDTH 1
516 #define MAC_VLANTR_DOVLTC_INDEX 20
517 #define MAC_VLANTR_DOVLTC_WIDTH 1
518 #define MAC_VLANTR_ERSVLM_INDEX 19
519 #define MAC_VLANTR_ERSVLM_WIDTH 1
520 #define MAC_VLANTR_ESVL_INDEX 18
521 #define MAC_VLANTR_ESVL_WIDTH 1
522 #define MAC_VLANTR_ETV_INDEX 16
523 #define MAC_VLANTR_ETV_WIDTH 1
524 #define MAC_VLANTR_EVLS_INDEX 21
525 #define MAC_VLANTR_EVLS_WIDTH 2
526 #define MAC_VLANTR_EVLRXS_INDEX 24
527 #define MAC_VLANTR_EVLRXS_WIDTH 1
528 #define MAC_VLANTR_VL_INDEX 0
529 #define MAC_VLANTR_VL_WIDTH 16
530 #define MAC_VLANTR_VTHM_INDEX 25
531 #define MAC_VLANTR_VTHM_WIDTH 1
532 #define MAC_VLANTR_VTIM_INDEX 17
533 #define MAC_VLANTR_VTIM_WIDTH 1
534 #define MAC_VR_DEVID_INDEX 8
535 #define MAC_VR_DEVID_WIDTH 8
536 #define MAC_VR_SNPSVER_INDEX 0
537 #define MAC_VR_SNPSVER_WIDTH 8
538 #define MAC_VR_USERVER_INDEX 16
539 #define MAC_VR_USERVER_WIDTH 8
541 /* MMC register offsets */
542 #define MMC_CR 0x0800
543 #define MMC_RISR 0x0804
544 #define MMC_TISR 0x0808
545 #define MMC_RIER 0x080c
546 #define MMC_TIER 0x0810
547 #define MMC_TXOCTETCOUNT_GB_LO 0x0814
548 #define MMC_TXOCTETCOUNT_GB_HI 0x0818
549 #define MMC_TXFRAMECOUNT_GB_LO 0x081c
550 #define MMC_TXFRAMECOUNT_GB_HI 0x0820
551 #define MMC_TXBROADCASTFRAMES_G_LO 0x0824
552 #define MMC_TXBROADCASTFRAMES_G_HI 0x0828
553 #define MMC_TXMULTICASTFRAMES_G_LO 0x082c
554 #define MMC_TXMULTICASTFRAMES_G_HI 0x0830
555 #define MMC_TX64OCTETS_GB_LO 0x0834
556 #define MMC_TX64OCTETS_GB_HI 0x0838
557 #define MMC_TX65TO127OCTETS_GB_LO 0x083c
558 #define MMC_TX65TO127OCTETS_GB_HI 0x0840
559 #define MMC_TX128TO255OCTETS_GB_LO 0x0844
560 #define MMC_TX128TO255OCTETS_GB_HI 0x0848
561 #define MMC_TX256TO511OCTETS_GB_LO 0x084c
562 #define MMC_TX256TO511OCTETS_GB_HI 0x0850
563 #define MMC_TX512TO1023OCTETS_GB_LO 0x0854
564 #define MMC_TX512TO1023OCTETS_GB_HI 0x0858
565 #define MMC_TX1024TOMAXOCTETS_GB_LO 0x085c
566 #define MMC_TX1024TOMAXOCTETS_GB_HI 0x0860
567 #define MMC_TXUNICASTFRAMES_GB_LO 0x0864
568 #define MMC_TXUNICASTFRAMES_GB_HI 0x0868
569 #define MMC_TXMULTICASTFRAMES_GB_LO 0x086c
570 #define MMC_TXMULTICASTFRAMES_GB_HI 0x0870
571 #define MMC_TXBROADCASTFRAMES_GB_LO 0x0874
572 #define MMC_TXBROADCASTFRAMES_GB_HI 0x0878
573 #define MMC_TXUNDERFLOWERROR_LO 0x087c
574 #define MMC_TXUNDERFLOWERROR_HI 0x0880
575 #define MMC_TXOCTETCOUNT_G_LO 0x0884
576 #define MMC_TXOCTETCOUNT_G_HI 0x0888
577 #define MMC_TXFRAMECOUNT_G_LO 0x088c
578 #define MMC_TXFRAMECOUNT_G_HI 0x0890
579 #define MMC_TXPAUSEFRAMES_LO 0x0894
580 #define MMC_TXPAUSEFRAMES_HI 0x0898
581 #define MMC_TXVLANFRAMES_G_LO 0x089c
582 #define MMC_TXVLANFRAMES_G_HI 0x08a0
583 #define MMC_RXFRAMECOUNT_GB_LO 0x0900
584 #define MMC_RXFRAMECOUNT_GB_HI 0x0904
585 #define MMC_RXOCTETCOUNT_GB_LO 0x0908
586 #define MMC_RXOCTETCOUNT_GB_HI 0x090c
587 #define MMC_RXOCTETCOUNT_G_LO 0x0910
588 #define MMC_RXOCTETCOUNT_G_HI 0x0914
589 #define MMC_RXBROADCASTFRAMES_G_LO 0x0918
590 #define MMC_RXBROADCASTFRAMES_G_HI 0x091c
591 #define MMC_RXMULTICASTFRAMES_G_LO 0x0920
592 #define MMC_RXMULTICASTFRAMES_G_HI 0x0924
593 #define MMC_RXCRCERROR_LO 0x0928
594 #define MMC_RXCRCERROR_HI 0x092c
595 #define MMC_RXRUNTERROR 0x0930
596 #define MMC_RXJABBERERROR 0x0934
597 #define MMC_RXUNDERSIZE_G 0x0938
598 #define MMC_RXOVERSIZE_G 0x093c
599 #define MMC_RX64OCTETS_GB_LO 0x0940
600 #define MMC_RX64OCTETS_GB_HI 0x0944
601 #define MMC_RX65TO127OCTETS_GB_LO 0x0948
602 #define MMC_RX65TO127OCTETS_GB_HI 0x094c
603 #define MMC_RX128TO255OCTETS_GB_LO 0x0950
604 #define MMC_RX128TO255OCTETS_GB_HI 0x0954
605 #define MMC_RX256TO511OCTETS_GB_LO 0x0958
606 #define MMC_RX256TO511OCTETS_GB_HI 0x095c
607 #define MMC_RX512TO1023OCTETS_GB_LO 0x0960
608 #define MMC_RX512TO1023OCTETS_GB_HI 0x0964
609 #define MMC_RX1024TOMAXOCTETS_GB_LO 0x0968
610 #define MMC_RX1024TOMAXOCTETS_GB_HI 0x096c
611 #define MMC_RXUNICASTFRAMES_G_LO 0x0970
612 #define MMC_RXUNICASTFRAMES_G_HI 0x0974
613 #define MMC_RXLENGTHERROR_LO 0x0978
614 #define MMC_RXLENGTHERROR_HI 0x097c
615 #define MMC_RXOUTOFRANGETYPE_LO 0x0980
616 #define MMC_RXOUTOFRANGETYPE_HI 0x0984
617 #define MMC_RXPAUSEFRAMES_LO 0x0988
618 #define MMC_RXPAUSEFRAMES_HI 0x098c
619 #define MMC_RXFIFOOVERFLOW_LO 0x0990
620 #define MMC_RXFIFOOVERFLOW_HI 0x0994
621 #define MMC_RXVLANFRAMES_GB_LO 0x0998
622 #define MMC_RXVLANFRAMES_GB_HI 0x099c
623 #define MMC_RXWATCHDOGERROR 0x09a0
625 /* MMC register entry bit positions and sizes */
626 #define MMC_CR_CR_INDEX 0
627 #define MMC_CR_CR_WIDTH 1
628 #define MMC_CR_CSR_INDEX 1
629 #define MMC_CR_CSR_WIDTH 1
630 #define MMC_CR_ROR_INDEX 2
631 #define MMC_CR_ROR_WIDTH 1
632 #define MMC_CR_MCF_INDEX 3
633 #define MMC_CR_MCF_WIDTH 1
634 #define MMC_CR_MCT_INDEX 4
635 #define MMC_CR_MCT_WIDTH 2
636 #define MMC_RIER_ALL_INTERRUPTS_INDEX 0
637 #define MMC_RIER_ALL_INTERRUPTS_WIDTH 23
638 #define MMC_RISR_RXFRAMECOUNT_GB_INDEX 0
639 #define MMC_RISR_RXFRAMECOUNT_GB_WIDTH 1
640 #define MMC_RISR_RXOCTETCOUNT_GB_INDEX 1
641 #define MMC_RISR_RXOCTETCOUNT_GB_WIDTH 1
642 #define MMC_RISR_RXOCTETCOUNT_G_INDEX 2
643 #define MMC_RISR_RXOCTETCOUNT_G_WIDTH 1
644 #define MMC_RISR_RXBROADCASTFRAMES_G_INDEX 3
645 #define MMC_RISR_RXBROADCASTFRAMES_G_WIDTH 1
646 #define MMC_RISR_RXMULTICASTFRAMES_G_INDEX 4
647 #define MMC_RISR_RXMULTICASTFRAMES_G_WIDTH 1
648 #define MMC_RISR_RXCRCERROR_INDEX 5
649 #define MMC_RISR_RXCRCERROR_WIDTH 1
650 #define MMC_RISR_RXRUNTERROR_INDEX 6
651 #define MMC_RISR_RXRUNTERROR_WIDTH 1
652 #define MMC_RISR_RXJABBERERROR_INDEX 7
653 #define MMC_RISR_RXJABBERERROR_WIDTH 1
654 #define MMC_RISR_RXUNDERSIZE_G_INDEX 8
655 #define MMC_RISR_RXUNDERSIZE_G_WIDTH 1
656 #define MMC_RISR_RXOVERSIZE_G_INDEX 9
657 #define MMC_RISR_RXOVERSIZE_G_WIDTH 1
658 #define MMC_RISR_RX64OCTETS_GB_INDEX 10
659 #define MMC_RISR_RX64OCTETS_GB_WIDTH 1
660 #define MMC_RISR_RX65TO127OCTETS_GB_INDEX 11
661 #define MMC_RISR_RX65TO127OCTETS_GB_WIDTH 1
662 #define MMC_RISR_RX128TO255OCTETS_GB_INDEX 12
663 #define MMC_RISR_RX128TO255OCTETS_GB_WIDTH 1
664 #define MMC_RISR_RX256TO511OCTETS_GB_INDEX 13
665 #define MMC_RISR_RX256TO511OCTETS_GB_WIDTH 1
666 #define MMC_RISR_RX512TO1023OCTETS_GB_INDEX 14
667 #define MMC_RISR_RX512TO1023OCTETS_GB_WIDTH 1
668 #define MMC_RISR_RX1024TOMAXOCTETS_GB_INDEX 15
669 #define MMC_RISR_RX1024TOMAXOCTETS_GB_WIDTH 1
670 #define MMC_RISR_RXUNICASTFRAMES_G_INDEX 16
671 #define MMC_RISR_RXUNICASTFRAMES_G_WIDTH 1
672 #define MMC_RISR_RXLENGTHERROR_INDEX 17
673 #define MMC_RISR_RXLENGTHERROR_WIDTH 1
674 #define MMC_RISR_RXOUTOFRANGETYPE_INDEX 18
675 #define MMC_RISR_RXOUTOFRANGETYPE_WIDTH 1
676 #define MMC_RISR_RXPAUSEFRAMES_INDEX 19
677 #define MMC_RISR_RXPAUSEFRAMES_WIDTH 1
678 #define MMC_RISR_RXFIFOOVERFLOW_INDEX 20
679 #define MMC_RISR_RXFIFOOVERFLOW_WIDTH 1
680 #define MMC_RISR_RXVLANFRAMES_GB_INDEX 21
681 #define MMC_RISR_RXVLANFRAMES_GB_WIDTH 1
682 #define MMC_RISR_RXWATCHDOGERROR_INDEX 22
683 #define MMC_RISR_RXWATCHDOGERROR_WIDTH 1
684 #define MMC_TIER_ALL_INTERRUPTS_INDEX 0
685 #define MMC_TIER_ALL_INTERRUPTS_WIDTH 18
686 #define MMC_TISR_TXOCTETCOUNT_GB_INDEX 0
687 #define MMC_TISR_TXOCTETCOUNT_GB_WIDTH 1
688 #define MMC_TISR_TXFRAMECOUNT_GB_INDEX 1
689 #define MMC_TISR_TXFRAMECOUNT_GB_WIDTH 1
690 #define MMC_TISR_TXBROADCASTFRAMES_G_INDEX 2
691 #define MMC_TISR_TXBROADCASTFRAMES_G_WIDTH 1
692 #define MMC_TISR_TXMULTICASTFRAMES_G_INDEX 3
693 #define MMC_TISR_TXMULTICASTFRAMES_G_WIDTH 1
694 #define MMC_TISR_TX64OCTETS_GB_INDEX 4
695 #define MMC_TISR_TX64OCTETS_GB_WIDTH 1
696 #define MMC_TISR_TX65TO127OCTETS_GB_INDEX 5
697 #define MMC_TISR_TX65TO127OCTETS_GB_WIDTH 1
698 #define MMC_TISR_TX128TO255OCTETS_GB_INDEX 6
699 #define MMC_TISR_TX128TO255OCTETS_GB_WIDTH 1
700 #define MMC_TISR_TX256TO511OCTETS_GB_INDEX 7
701 #define MMC_TISR_TX256TO511OCTETS_GB_WIDTH 1
702 #define MMC_TISR_TX512TO1023OCTETS_GB_INDEX 8
703 #define MMC_TISR_TX512TO1023OCTETS_GB_WIDTH 1
704 #define MMC_TISR_TX1024TOMAXOCTETS_GB_INDEX 9
705 #define MMC_TISR_TX1024TOMAXOCTETS_GB_WIDTH 1
706 #define MMC_TISR_TXUNICASTFRAMES_GB_INDEX 10
707 #define MMC_TISR_TXUNICASTFRAMES_GB_WIDTH 1
708 #define MMC_TISR_TXMULTICASTFRAMES_GB_INDEX 11
709 #define MMC_TISR_TXMULTICASTFRAMES_GB_WIDTH 1
710 #define MMC_TISR_TXBROADCASTFRAMES_GB_INDEX 12
711 #define MMC_TISR_TXBROADCASTFRAMES_GB_WIDTH 1
712 #define MMC_TISR_TXUNDERFLOWERROR_INDEX 13
713 #define MMC_TISR_TXUNDERFLOWERROR_WIDTH 1
714 #define MMC_TISR_TXOCTETCOUNT_G_INDEX 14
715 #define MMC_TISR_TXOCTETCOUNT_G_WIDTH 1
716 #define MMC_TISR_TXFRAMECOUNT_G_INDEX 15
717 #define MMC_TISR_TXFRAMECOUNT_G_WIDTH 1
718 #define MMC_TISR_TXPAUSEFRAMES_INDEX 16
719 #define MMC_TISR_TXPAUSEFRAMES_WIDTH 1
720 #define MMC_TISR_TXVLANFRAMES_G_INDEX 17
721 #define MMC_TISR_TXVLANFRAMES_G_WIDTH 1
723 /* MTL register offsets */
724 #define MTL_OMR 0x1000
725 #define MTL_FDCR 0x1008
726 #define MTL_FDSR 0x100c
727 #define MTL_FDDR 0x1010
728 #define MTL_ISR 0x1020
729 #define MTL_RQDCM0R 0x1030
730 #define MTL_TCPM0R 0x1040
731 #define MTL_TCPM1R 0x1044
733 #define MTL_RQDCM_INC 4
734 #define MTL_RQDCM_Q_PER_REG 4
735 #define MTL_TCPM_INC 4
736 #define MTL_TCPM_TC_PER_REG 4
738 /* MTL register entry bit positions and sizes */
739 #define MTL_OMR_ETSALG_INDEX 5
740 #define MTL_OMR_ETSALG_WIDTH 2
741 #define MTL_OMR_RAA_INDEX 2
742 #define MTL_OMR_RAA_WIDTH 1
744 /* MTL queue register offsets
745 * Multiple queues can be active. The first queue has registers
746 * that begin at 0x1100. Each subsequent queue has registers that
747 * are accessed using an offset of 0x80 from the previous queue.
749 #define MTL_Q_BASE 0x1100
750 #define MTL_Q_INC 0x80
752 #define MTL_Q_TQOMR 0x00
753 #define MTL_Q_TQUR 0x04
754 #define MTL_Q_TQDR 0x08
755 #define MTL_Q_RQOMR 0x40
756 #define MTL_Q_RQMPOCR 0x44
757 #define MTL_Q_RQDR 0x48
758 #define MTL_Q_RQFCR 0x50
759 #define MTL_Q_IER 0x70
760 #define MTL_Q_ISR 0x74
762 /* MTL queue register entry bit positions and sizes */
763 #define MTL_Q_RQDR_PRXQ_INDEX 16
764 #define MTL_Q_RQDR_PRXQ_WIDTH 14
765 #define MTL_Q_RQDR_RXQSTS_INDEX 4
766 #define MTL_Q_RQDR_RXQSTS_WIDTH 2
767 #define MTL_Q_RQFCR_RFA_INDEX 1
768 #define MTL_Q_RQFCR_RFA_WIDTH 6
769 #define MTL_Q_RQFCR_RFD_INDEX 17
770 #define MTL_Q_RQFCR_RFD_WIDTH 6
771 #define MTL_Q_RQOMR_EHFC_INDEX 7
772 #define MTL_Q_RQOMR_EHFC_WIDTH 1
773 #define MTL_Q_RQOMR_RQS_INDEX 16
774 #define MTL_Q_RQOMR_RQS_WIDTH 9
775 #define MTL_Q_RQOMR_RSF_INDEX 5
776 #define MTL_Q_RQOMR_RSF_WIDTH 1
777 #define MTL_Q_RQOMR_RTC_INDEX 0
778 #define MTL_Q_RQOMR_RTC_WIDTH 2
779 #define MTL_Q_TQDR_TRCSTS_INDEX 1
780 #define MTL_Q_TQDR_TRCSTS_WIDTH 2
781 #define MTL_Q_TQDR_TXQSTS_INDEX 4
782 #define MTL_Q_TQDR_TXQSTS_WIDTH 1
783 #define MTL_Q_TQOMR_FTQ_INDEX 0
784 #define MTL_Q_TQOMR_FTQ_WIDTH 1
785 #define MTL_Q_TQOMR_Q2TCMAP_INDEX 8
786 #define MTL_Q_TQOMR_Q2TCMAP_WIDTH 3
787 #define MTL_Q_TQOMR_TQS_INDEX 16
788 #define MTL_Q_TQOMR_TQS_WIDTH 10
789 #define MTL_Q_TQOMR_TSF_INDEX 1
790 #define MTL_Q_TQOMR_TSF_WIDTH 1
791 #define MTL_Q_TQOMR_TTC_INDEX 4
792 #define MTL_Q_TQOMR_TTC_WIDTH 3
793 #define MTL_Q_TQOMR_TXQEN_INDEX 2
794 #define MTL_Q_TQOMR_TXQEN_WIDTH 2
796 /* MTL queue register value */
797 #define MTL_RSF_DISABLE 0x00
798 #define MTL_RSF_ENABLE 0x01
799 #define MTL_TSF_DISABLE 0x00
800 #define MTL_TSF_ENABLE 0x01
802 #define MTL_RX_THRESHOLD_64 0x00
803 #define MTL_RX_THRESHOLD_96 0x02
804 #define MTL_RX_THRESHOLD_128 0x03
805 #define MTL_TX_THRESHOLD_32 0x01
806 #define MTL_TX_THRESHOLD_64 0x00
807 #define MTL_TX_THRESHOLD_96 0x02
808 #define MTL_TX_THRESHOLD_128 0x03
809 #define MTL_TX_THRESHOLD_192 0x04
810 #define MTL_TX_THRESHOLD_256 0x05
811 #define MTL_TX_THRESHOLD_384 0x06
812 #define MTL_TX_THRESHOLD_512 0x07
814 #define MTL_ETSALG_WRR 0x00
815 #define MTL_ETSALG_WFQ 0x01
816 #define MTL_ETSALG_DWRR 0x02
817 #define MTL_RAA_SP 0x00
818 #define MTL_RAA_WSP 0x01
820 #define MTL_Q_DISABLED 0x00
821 #define MTL_Q_ENABLED 0x02
823 /* MTL traffic class register offsets
824 * Multiple traffic classes can be active. The first class has registers
825 * that begin at 0x1100. Each subsequent queue has registers that
826 * are accessed using an offset of 0x80 from the previous queue.
828 #define MTL_TC_BASE MTL_Q_BASE
829 #define MTL_TC_INC MTL_Q_INC
831 #define MTL_TC_ETSCR 0x10
832 #define MTL_TC_ETSSR 0x14
833 #define MTL_TC_QWR 0x18
835 /* MTL traffic class register entry bit positions and sizes */
836 #define MTL_TC_ETSCR_TSA_INDEX 0
837 #define MTL_TC_ETSCR_TSA_WIDTH 2
838 #define MTL_TC_QWR_QW_INDEX 0
839 #define MTL_TC_QWR_QW_WIDTH 21
840 #define MTL_TCPM0R_PSTC0_INDEX 0
841 #define MTL_TCPM0R_PSTC0_WIDTH 8
842 #define MTL_TCPM0R_PSTC1_INDEX 8
843 #define MTL_TCPM0R_PSTC1_WIDTH 8
844 #define MTL_TCPM0R_PSTC2_INDEX 16
845 #define MTL_TCPM0R_PSTC2_WIDTH 8
846 #define MTL_TCPM0R_PSTC3_INDEX 24
847 #define MTL_TCPM0R_PSTC3_WIDTH 8
848 #define MTL_TCPM1R_PSTC4_INDEX 0
849 #define MTL_TCPM1R_PSTC4_WIDTH 8
850 #define MTL_TCPM1R_PSTC5_INDEX 8
851 #define MTL_TCPM1R_PSTC5_WIDTH 8
852 #define MTL_TCPM1R_PSTC6_INDEX 16
853 #define MTL_TCPM1R_PSTC6_WIDTH 8
854 #define MTL_TCPM1R_PSTC7_INDEX 24
855 #define MTL_TCPM1R_PSTC7_WIDTH 8
857 /* MTL traffic class register value */
858 #define MTL_TSA_SP 0x00
859 #define MTL_TSA_ETS 0x02
861 /* PCS register offsets */
862 #define PCS_V1_WINDOW_SELECT 0x03fc
863 #define PCS_V2_WINDOW_DEF 0x9060
864 #define PCS_V2_WINDOW_SELECT 0x9064
865 #define PCS_V2_RV_WINDOW_DEF 0x1060
866 #define PCS_V2_RV_WINDOW_SELECT 0x1064
868 /* PCS register entry bit positions and sizes */
869 #define PCS_V2_WINDOW_DEF_OFFSET_INDEX 6
870 #define PCS_V2_WINDOW_DEF_OFFSET_WIDTH 14
871 #define PCS_V2_WINDOW_DEF_SIZE_INDEX 2
872 #define PCS_V2_WINDOW_DEF_SIZE_WIDTH 4
874 /* SerDes integration register offsets */
875 #define SIR0_KR_RT_1 0x002c
876 #define SIR0_STATUS 0x0040
877 #define SIR1_SPEED 0x0000
879 /* SerDes integration register entry bit positions and sizes */
880 #define SIR0_KR_RT_1_RESET_INDEX 11
881 #define SIR0_KR_RT_1_RESET_WIDTH 1
882 #define SIR0_STATUS_RX_READY_INDEX 0
883 #define SIR0_STATUS_RX_READY_WIDTH 1
884 #define SIR0_STATUS_TX_READY_INDEX 8
885 #define SIR0_STATUS_TX_READY_WIDTH 1
886 #define SIR1_SPEED_CDR_RATE_INDEX 12
887 #define SIR1_SPEED_CDR_RATE_WIDTH 4
888 #define SIR1_SPEED_DATARATE_INDEX 4
889 #define SIR1_SPEED_DATARATE_WIDTH 2
890 #define SIR1_SPEED_PLLSEL_INDEX 3
891 #define SIR1_SPEED_PLLSEL_WIDTH 1
892 #define SIR1_SPEED_RATECHANGE_INDEX 6
893 #define SIR1_SPEED_RATECHANGE_WIDTH 1
894 #define SIR1_SPEED_TXAMP_INDEX 8
895 #define SIR1_SPEED_TXAMP_WIDTH 4
896 #define SIR1_SPEED_WORDMODE_INDEX 0
897 #define SIR1_SPEED_WORDMODE_WIDTH 3
899 /* SerDes RxTx register offsets */
900 #define RXTX_REG6 0x0018
901 #define RXTX_REG20 0x0050
902 #define RXTX_REG22 0x0058
903 #define RXTX_REG114 0x01c8
904 #define RXTX_REG129 0x0204
906 /* SerDes RxTx register entry bit positions and sizes */
907 #define RXTX_REG6_RESETB_RXD_INDEX 8
908 #define RXTX_REG6_RESETB_RXD_WIDTH 1
909 #define RXTX_REG20_BLWC_ENA_INDEX 2
910 #define RXTX_REG20_BLWC_ENA_WIDTH 1
911 #define RXTX_REG114_PQ_REG_INDEX 9
912 #define RXTX_REG114_PQ_REG_WIDTH 7
913 #define RXTX_REG129_RXDFE_CONFIG_INDEX 14
914 #define RXTX_REG129_RXDFE_CONFIG_WIDTH 2
916 /* MAC Control register offsets */
917 #define XP_PROP_0 0x0000
918 #define XP_PROP_1 0x0004
919 #define XP_PROP_2 0x0008
920 #define XP_PROP_3 0x000c
921 #define XP_PROP_4 0x0010
922 #define XP_PROP_5 0x0014
923 #define XP_MAC_ADDR_LO 0x0020
924 #define XP_MAC_ADDR_HI 0x0024
925 #define XP_ECC_ISR 0x0030
926 #define XP_ECC_IER 0x0034
927 #define XP_ECC_CNT0 0x003c
928 #define XP_ECC_CNT1 0x0040
929 #define XP_DRIVER_INT_REQ 0x0060
930 #define XP_DRIVER_INT_RO 0x0064
931 #define XP_DRIVER_SCRATCH_0 0x0068
932 #define XP_DRIVER_SCRATCH_1 0x006c
933 #define XP_INT_EN 0x0078
934 #define XP_I2C_MUTEX 0x0080
935 #define XP_MDIO_MUTEX 0x0084
937 /* MAC Control register entry bit positions and sizes */
938 #define XP_DRIVER_INT_REQ_REQUEST_INDEX 0
939 #define XP_DRIVER_INT_REQ_REQUEST_WIDTH 1
940 #define XP_DRIVER_INT_RO_STATUS_INDEX 0
941 #define XP_DRIVER_INT_RO_STATUS_WIDTH 1
942 #define XP_DRIVER_SCRATCH_0_COMMAND_INDEX 0
943 #define XP_DRIVER_SCRATCH_0_COMMAND_WIDTH 8
944 #define XP_DRIVER_SCRATCH_0_SUB_COMMAND_INDEX 8
945 #define XP_DRIVER_SCRATCH_0_SUB_COMMAND_WIDTH 8
946 #define XP_ECC_CNT0_RX_DED_INDEX 24
947 #define XP_ECC_CNT0_RX_DED_WIDTH 8
948 #define XP_ECC_CNT0_RX_SEC_INDEX 16
949 #define XP_ECC_CNT0_RX_SEC_WIDTH 8
950 #define XP_ECC_CNT0_TX_DED_INDEX 8
951 #define XP_ECC_CNT0_TX_DED_WIDTH 8
952 #define XP_ECC_CNT0_TX_SEC_INDEX 0
953 #define XP_ECC_CNT0_TX_SEC_WIDTH 8
954 #define XP_ECC_CNT1_DESC_DED_INDEX 8
955 #define XP_ECC_CNT1_DESC_DED_WIDTH 8
956 #define XP_ECC_CNT1_DESC_SEC_INDEX 0
957 #define XP_ECC_CNT1_DESC_SEC_WIDTH 8
958 #define XP_ECC_IER_DESC_DED_INDEX 0
959 #define XP_ECC_IER_DESC_DED_WIDTH 1
960 #define XP_ECC_IER_DESC_SEC_INDEX 1
961 #define XP_ECC_IER_DESC_SEC_WIDTH 1
962 #define XP_ECC_IER_RX_DED_INDEX 2
963 #define XP_ECC_IER_RX_DED_WIDTH 1
964 #define XP_ECC_IER_RX_SEC_INDEX 3
965 #define XP_ECC_IER_RX_SEC_WIDTH 1
966 #define XP_ECC_IER_TX_DED_INDEX 4
967 #define XP_ECC_IER_TX_DED_WIDTH 1
968 #define XP_ECC_IER_TX_SEC_INDEX 5
969 #define XP_ECC_IER_TX_SEC_WIDTH 1
970 #define XP_ECC_ISR_DESC_DED_INDEX 0
971 #define XP_ECC_ISR_DESC_DED_WIDTH 1
972 #define XP_ECC_ISR_DESC_SEC_INDEX 1
973 #define XP_ECC_ISR_DESC_SEC_WIDTH 1
974 #define XP_ECC_ISR_RX_DED_INDEX 2
975 #define XP_ECC_ISR_RX_DED_WIDTH 1
976 #define XP_ECC_ISR_RX_SEC_INDEX 3
977 #define XP_ECC_ISR_RX_SEC_WIDTH 1
978 #define XP_ECC_ISR_TX_DED_INDEX 4
979 #define XP_ECC_ISR_TX_DED_WIDTH 1
980 #define XP_ECC_ISR_TX_SEC_INDEX 5
981 #define XP_ECC_ISR_TX_SEC_WIDTH 1
982 #define XP_I2C_MUTEX_BUSY_INDEX 31
983 #define XP_I2C_MUTEX_BUSY_WIDTH 1
984 #define XP_I2C_MUTEX_ID_INDEX 29
985 #define XP_I2C_MUTEX_ID_WIDTH 2
986 #define XP_I2C_MUTEX_ACTIVE_INDEX 0
987 #define XP_I2C_MUTEX_ACTIVE_WIDTH 1
988 #define XP_MAC_ADDR_HI_VALID_INDEX 31
989 #define XP_MAC_ADDR_HI_VALID_WIDTH 1
990 #define XP_PROP_0_CONN_TYPE_INDEX 28
991 #define XP_PROP_0_CONN_TYPE_WIDTH 3
992 #define XP_PROP_0_MDIO_ADDR_INDEX 16
993 #define XP_PROP_0_MDIO_ADDR_WIDTH 5
994 #define XP_PROP_0_PORT_ID_INDEX 0
995 #define XP_PROP_0_PORT_ID_WIDTH 8
996 #define XP_PROP_0_PORT_MODE_INDEX 8
997 #define XP_PROP_0_PORT_MODE_WIDTH 4
998 #define XP_PROP_0_PORT_SPEEDS_INDEX 23
999 #define XP_PROP_0_PORT_SPEEDS_WIDTH 4
1000 #define XP_PROP_1_MAX_RX_DMA_INDEX 24
1001 #define XP_PROP_1_MAX_RX_DMA_WIDTH 5
1002 #define XP_PROP_1_MAX_RX_QUEUES_INDEX 8
1003 #define XP_PROP_1_MAX_RX_QUEUES_WIDTH 5
1004 #define XP_PROP_1_MAX_TX_DMA_INDEX 16
1005 #define XP_PROP_1_MAX_TX_DMA_WIDTH 5
1006 #define XP_PROP_1_MAX_TX_QUEUES_INDEX 0
1007 #define XP_PROP_1_MAX_TX_QUEUES_WIDTH 5
1008 #define XP_PROP_2_RX_FIFO_SIZE_INDEX 16
1009 #define XP_PROP_2_RX_FIFO_SIZE_WIDTH 16
1010 #define XP_PROP_2_TX_FIFO_SIZE_INDEX 0
1011 #define XP_PROP_2_TX_FIFO_SIZE_WIDTH 16
1012 #define XP_PROP_3_GPIO_MASK_INDEX 28
1013 #define XP_PROP_3_GPIO_MASK_WIDTH 4
1014 #define XP_PROP_3_GPIO_MOD_ABS_INDEX 20
1015 #define XP_PROP_3_GPIO_MOD_ABS_WIDTH 4
1016 #define XP_PROP_3_GPIO_RATE_SELECT_INDEX 16
1017 #define XP_PROP_3_GPIO_RATE_SELECT_WIDTH 4
1018 #define XP_PROP_3_GPIO_RX_LOS_INDEX 24
1019 #define XP_PROP_3_GPIO_RX_LOS_WIDTH 4
1020 #define XP_PROP_3_GPIO_TX_FAULT_INDEX 12
1021 #define XP_PROP_3_GPIO_TX_FAULT_WIDTH 4
1022 #define XP_PROP_3_GPIO_ADDR_INDEX 8
1023 #define XP_PROP_3_GPIO_ADDR_WIDTH 3
1024 #define XP_PROP_3_MDIO_RESET_INDEX 0
1025 #define XP_PROP_3_MDIO_RESET_WIDTH 2
1026 #define XP_PROP_3_MDIO_RESET_I2C_ADDR_INDEX 8
1027 #define XP_PROP_3_MDIO_RESET_I2C_ADDR_WIDTH 3
1028 #define XP_PROP_3_MDIO_RESET_I2C_GPIO_INDEX 12
1029 #define XP_PROP_3_MDIO_RESET_I2C_GPIO_WIDTH 4
1030 #define XP_PROP_3_MDIO_RESET_INT_GPIO_INDEX 4
1031 #define XP_PROP_3_MDIO_RESET_INT_GPIO_WIDTH 2
1032 #define XP_PROP_4_MUX_ADDR_HI_INDEX 8
1033 #define XP_PROP_4_MUX_ADDR_HI_WIDTH 5
1034 #define XP_PROP_4_MUX_ADDR_LO_INDEX 0
1035 #define XP_PROP_4_MUX_ADDR_LO_WIDTH 3
1036 #define XP_PROP_4_MUX_CHAN_INDEX 4
1037 #define XP_PROP_4_MUX_CHAN_WIDTH 3
1038 #define XP_PROP_4_REDRV_ADDR_INDEX 16
1039 #define XP_PROP_4_REDRV_ADDR_WIDTH 7
1040 #define XP_PROP_4_REDRV_IF_INDEX 23
1041 #define XP_PROP_4_REDRV_IF_WIDTH 1
1042 #define XP_PROP_4_REDRV_LANE_INDEX 24
1043 #define XP_PROP_4_REDRV_LANE_WIDTH 3
1044 #define XP_PROP_4_REDRV_MODEL_INDEX 28
1045 #define XP_PROP_4_REDRV_MODEL_WIDTH 3
1046 #define XP_PROP_4_REDRV_PRESENT_INDEX 31
1047 #define XP_PROP_4_REDRV_PRESENT_WIDTH 1
1049 /* I2C Control register offsets */
1050 #define IC_CON 0x0000
1051 #define IC_TAR 0x0004
1052 #define IC_DATA_CMD 0x0010
1053 #define IC_INTR_STAT 0x002c
1054 #define IC_INTR_MASK 0x0030
1055 #define IC_RAW_INTR_STAT 0x0034
1056 #define IC_CLR_INTR 0x0040
1057 #define IC_CLR_TX_ABRT 0x0054
1058 #define IC_CLR_STOP_DET 0x0060
1059 #define IC_ENABLE 0x006c
1060 #define IC_TXFLR 0x0074
1061 #define IC_RXFLR 0x0078
1062 #define IC_TX_ABRT_SOURCE 0x0080
1063 #define IC_ENABLE_STATUS 0x009c
1064 #define IC_COMP_PARAM_1 0x00f4
1066 /* I2C Control register entry bit positions and sizes */
1067 #define IC_COMP_PARAM_1_MAX_SPEED_MODE_INDEX 2
1068 #define IC_COMP_PARAM_1_MAX_SPEED_MODE_WIDTH 2
1069 #define IC_COMP_PARAM_1_RX_BUFFER_DEPTH_INDEX 8
1070 #define IC_COMP_PARAM_1_RX_BUFFER_DEPTH_WIDTH 8
1071 #define IC_COMP_PARAM_1_TX_BUFFER_DEPTH_INDEX 16
1072 #define IC_COMP_PARAM_1_TX_BUFFER_DEPTH_WIDTH 8
1073 #define IC_CON_MASTER_MODE_INDEX 0
1074 #define IC_CON_MASTER_MODE_WIDTH 1
1075 #define IC_CON_RESTART_EN_INDEX 5
1076 #define IC_CON_RESTART_EN_WIDTH 1
1077 #define IC_CON_RX_FIFO_FULL_HOLD_INDEX 9
1078 #define IC_CON_RX_FIFO_FULL_HOLD_WIDTH 1
1079 #define IC_CON_SLAVE_DISABLE_INDEX 6
1080 #define IC_CON_SLAVE_DISABLE_WIDTH 1
1081 #define IC_CON_SPEED_INDEX 1
1082 #define IC_CON_SPEED_WIDTH 2
1083 #define IC_DATA_CMD_CMD_INDEX 8
1084 #define IC_DATA_CMD_CMD_WIDTH 1
1085 #define IC_DATA_CMD_STOP_INDEX 9
1086 #define IC_DATA_CMD_STOP_WIDTH 1
1087 #define IC_ENABLE_ABORT_INDEX 1
1088 #define IC_ENABLE_ABORT_WIDTH 1
1089 #define IC_ENABLE_EN_INDEX 0
1090 #define IC_ENABLE_EN_WIDTH 1
1091 #define IC_ENABLE_STATUS_EN_INDEX 0
1092 #define IC_ENABLE_STATUS_EN_WIDTH 1
1093 #define IC_INTR_MASK_TX_EMPTY_INDEX 4
1094 #define IC_INTR_MASK_TX_EMPTY_WIDTH 1
1095 #define IC_RAW_INTR_STAT_RX_FULL_INDEX 2
1096 #define IC_RAW_INTR_STAT_RX_FULL_WIDTH 1
1097 #define IC_RAW_INTR_STAT_STOP_DET_INDEX 9
1098 #define IC_RAW_INTR_STAT_STOP_DET_WIDTH 1
1099 #define IC_RAW_INTR_STAT_TX_ABRT_INDEX 6
1100 #define IC_RAW_INTR_STAT_TX_ABRT_WIDTH 1
1101 #define IC_RAW_INTR_STAT_TX_EMPTY_INDEX 4
1102 #define IC_RAW_INTR_STAT_TX_EMPTY_WIDTH 1
1104 /* I2C Control register value */
1105 #define IC_TX_ABRT_7B_ADDR_NOACK 0x0001
1106 #define IC_TX_ABRT_ARB_LOST 0x1000
1108 /* Descriptor/Packet entry bit positions and sizes */
1109 #define RX_PACKET_ERRORS_CRC_INDEX 2
1110 #define RX_PACKET_ERRORS_CRC_WIDTH 1
1111 #define RX_PACKET_ERRORS_FRAME_INDEX 3
1112 #define RX_PACKET_ERRORS_FRAME_WIDTH 1
1113 #define RX_PACKET_ERRORS_LENGTH_INDEX 0
1114 #define RX_PACKET_ERRORS_LENGTH_WIDTH 1
1115 #define RX_PACKET_ERRORS_OVERRUN_INDEX 1
1116 #define RX_PACKET_ERRORS_OVERRUN_WIDTH 1
1118 #define RX_PACKET_ATTRIBUTES_CSUM_DONE_INDEX 0
1119 #define RX_PACKET_ATTRIBUTES_CSUM_DONE_WIDTH 1
1120 #define RX_PACKET_ATTRIBUTES_VLAN_CTAG_INDEX 1
1121 #define RX_PACKET_ATTRIBUTES_VLAN_CTAG_WIDTH 1
1122 #define RX_PACKET_ATTRIBUTES_INCOMPLETE_INDEX 2
1123 #define RX_PACKET_ATTRIBUTES_INCOMPLETE_WIDTH 1
1124 #define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_INDEX 3
1125 #define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_WIDTH 1
1126 #define RX_PACKET_ATTRIBUTES_CONTEXT_INDEX 4
1127 #define RX_PACKET_ATTRIBUTES_CONTEXT_WIDTH 1
1128 #define RX_PACKET_ATTRIBUTES_RX_TSTAMP_INDEX 5
1129 #define RX_PACKET_ATTRIBUTES_RX_TSTAMP_WIDTH 1
1130 #define RX_PACKET_ATTRIBUTES_RSS_HASH_INDEX 6
1131 #define RX_PACKET_ATTRIBUTES_RSS_HASH_WIDTH 1
1133 #define RX_NORMAL_DESC0_OVT_INDEX 0
1134 #define RX_NORMAL_DESC0_OVT_WIDTH 16
1135 #define RX_NORMAL_DESC2_HL_INDEX 0
1136 #define RX_NORMAL_DESC2_HL_WIDTH 10
1137 #define RX_NORMAL_DESC3_CDA_INDEX 27
1138 #define RX_NORMAL_DESC3_CDA_WIDTH 1
1139 #define RX_NORMAL_DESC3_CTXT_INDEX 30
1140 #define RX_NORMAL_DESC3_CTXT_WIDTH 1
1141 #define RX_NORMAL_DESC3_ES_INDEX 15
1142 #define RX_NORMAL_DESC3_ES_WIDTH 1
1143 #define RX_NORMAL_DESC3_ETLT_INDEX 16
1144 #define RX_NORMAL_DESC3_ETLT_WIDTH 4
1145 #define RX_NORMAL_DESC3_FD_INDEX 29
1146 #define RX_NORMAL_DESC3_FD_WIDTH 1
1147 #define RX_NORMAL_DESC3_INTE_INDEX 30
1148 #define RX_NORMAL_DESC3_INTE_WIDTH 1
1149 #define RX_NORMAL_DESC3_L34T_INDEX 20
1150 #define RX_NORMAL_DESC3_L34T_WIDTH 4
1151 #define RX_NORMAL_DESC3_LD_INDEX 28
1152 #define RX_NORMAL_DESC3_LD_WIDTH 1
1153 #define RX_NORMAL_DESC3_OWN_INDEX 31
1154 #define RX_NORMAL_DESC3_OWN_WIDTH 1
1155 #define RX_NORMAL_DESC3_PL_INDEX 0
1156 #define RX_NORMAL_DESC3_PL_WIDTH 14
1157 #define RX_NORMAL_DESC3_RSV_INDEX 26
1158 #define RX_NORMAL_DESC3_RSV_WIDTH 1
1159 #define RX_NORMAL_DESC3_LD_INDEX 28
1160 #define RX_NORMAL_DESC3_LD_WIDTH 1
1162 #define RX_DESC3_L34T_IPV4_TCP 1
1163 #define RX_DESC3_L34T_IPV4_UDP 2
1164 #define RX_DESC3_L34T_IPV4_ICMP 3
1165 #define RX_DESC3_L34T_IPV6_TCP 9
1166 #define RX_DESC3_L34T_IPV6_UDP 10
1167 #define RX_DESC3_L34T_IPV6_ICMP 11
1169 #define RX_CONTEXT_DESC3_TSA_INDEX 4
1170 #define RX_CONTEXT_DESC3_TSA_WIDTH 1
1171 #define RX_CONTEXT_DESC3_TSD_INDEX 6
1172 #define RX_CONTEXT_DESC3_TSD_WIDTH 1
1174 #define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_INDEX 0
1175 #define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_WIDTH 1
1176 #define TX_PACKET_ATTRIBUTES_TSO_ENABLE_INDEX 1
1177 #define TX_PACKET_ATTRIBUTES_TSO_ENABLE_WIDTH 1
1178 #define TX_PACKET_ATTRIBUTES_VLAN_CTAG_INDEX 2
1179 #define TX_PACKET_ATTRIBUTES_VLAN_CTAG_WIDTH 1
1180 #define TX_PACKET_ATTRIBUTES_PTP_INDEX 3
1181 #define TX_PACKET_ATTRIBUTES_PTP_WIDTH 1
1183 #define TX_CONTEXT_DESC2_MSS_INDEX 0
1184 #define TX_CONTEXT_DESC2_MSS_WIDTH 15
1185 #define TX_CONTEXT_DESC3_CTXT_INDEX 30
1186 #define TX_CONTEXT_DESC3_CTXT_WIDTH 1
1187 #define TX_CONTEXT_DESC3_TCMSSV_INDEX 26
1188 #define TX_CONTEXT_DESC3_TCMSSV_WIDTH 1
1189 #define TX_CONTEXT_DESC3_VLTV_INDEX 16
1190 #define TX_CONTEXT_DESC3_VLTV_WIDTH 1
1191 #define TX_CONTEXT_DESC3_VT_INDEX 0
1192 #define TX_CONTEXT_DESC3_VT_WIDTH 16
1194 #define TX_NORMAL_DESC2_HL_B1L_INDEX 0
1195 #define TX_NORMAL_DESC2_HL_B1L_WIDTH 14
1196 #define TX_NORMAL_DESC2_IC_INDEX 31
1197 #define TX_NORMAL_DESC2_IC_WIDTH 1
1198 #define TX_NORMAL_DESC2_TTSE_INDEX 30
1199 #define TX_NORMAL_DESC2_TTSE_WIDTH 1
1200 #define TX_NORMAL_DESC2_VTIR_INDEX 14
1201 #define TX_NORMAL_DESC2_VTIR_WIDTH 2
1202 #define TX_NORMAL_DESC3_CIC_INDEX 16
1203 #define TX_NORMAL_DESC3_CIC_WIDTH 2
1204 #define TX_NORMAL_DESC3_CPC_INDEX 26
1205 #define TX_NORMAL_DESC3_CPC_WIDTH 2
1206 #define TX_NORMAL_DESC3_CTXT_INDEX 30
1207 #define TX_NORMAL_DESC3_CTXT_WIDTH 1
1208 #define TX_NORMAL_DESC3_FD_INDEX 29
1209 #define TX_NORMAL_DESC3_FD_WIDTH 1
1210 #define TX_NORMAL_DESC3_FL_INDEX 0
1211 #define TX_NORMAL_DESC3_FL_WIDTH 15
1212 #define TX_NORMAL_DESC3_LD_INDEX 28
1213 #define TX_NORMAL_DESC3_LD_WIDTH 1
1214 #define TX_NORMAL_DESC3_OWN_INDEX 31
1215 #define TX_NORMAL_DESC3_OWN_WIDTH 1
1216 #define TX_NORMAL_DESC3_TCPHDRLEN_INDEX 19
1217 #define TX_NORMAL_DESC3_TCPHDRLEN_WIDTH 4
1218 #define TX_NORMAL_DESC3_TCPPL_INDEX 0
1219 #define TX_NORMAL_DESC3_TCPPL_WIDTH 18
1220 #define TX_NORMAL_DESC3_TSE_INDEX 18
1221 #define TX_NORMAL_DESC3_TSE_WIDTH 1
1223 #define TX_NORMAL_DESC2_VLAN_INSERT 0x2
1225 /* MDIO undefined or vendor specific registers */
1226 #ifndef MDIO_PMA_10GBR_PMD_CTRL
1227 #define MDIO_PMA_10GBR_PMD_CTRL 0x0096
1230 #ifndef MDIO_PMA_10GBR_FECCTRL
1231 #define MDIO_PMA_10GBR_FECCTRL 0x00ab
1234 #ifndef MDIO_PCS_DIG_CTRL
1235 #define MDIO_PCS_DIG_CTRL 0x8000
1239 #define MDIO_AN_XNP 0x0016
1243 #define MDIO_AN_LPX 0x0019
1246 #ifndef MDIO_AN_COMP_STAT
1247 #define MDIO_AN_COMP_STAT 0x0030
1250 #ifndef MDIO_AN_INTMASK
1251 #define MDIO_AN_INTMASK 0x8001
1255 #define MDIO_AN_INT 0x8002
1258 #ifndef MDIO_VEND2_AN_ADVERTISE
1259 #define MDIO_VEND2_AN_ADVERTISE 0x0004
1262 #ifndef MDIO_VEND2_AN_LP_ABILITY
1263 #define MDIO_VEND2_AN_LP_ABILITY 0x0005
1266 #ifndef MDIO_VEND2_AN_CTRL
1267 #define MDIO_VEND2_AN_CTRL 0x8001
1270 #ifndef MDIO_VEND2_AN_STAT
1271 #define MDIO_VEND2_AN_STAT 0x8002
1274 #ifndef MDIO_VEND2_PMA_CDR_CONTROL
1275 #define MDIO_VEND2_PMA_CDR_CONTROL 0x8056
1278 #ifndef MDIO_CTRL1_SPEED1G
1279 #define MDIO_CTRL1_SPEED1G (MDIO_CTRL1_SPEED10G & ~BMCR_SPEED100)
1282 #ifndef MDIO_VEND2_CTRL1_AN_ENABLE
1283 #define MDIO_VEND2_CTRL1_AN_ENABLE BIT(12)
1286 #ifndef MDIO_VEND2_CTRL1_AN_RESTART
1287 #define MDIO_VEND2_CTRL1_AN_RESTART BIT(9)
1290 #ifndef MDIO_VEND2_CTRL1_SS6
1291 #define MDIO_VEND2_CTRL1_SS6 BIT(6)
1294 #ifndef MDIO_VEND2_CTRL1_SS13
1295 #define MDIO_VEND2_CTRL1_SS13 BIT(13)
1298 /* MDIO mask values */
1299 #define AXGBE_AN_CL73_INT_CMPLT BIT(0)
1300 #define AXGBE_AN_CL73_INC_LINK BIT(1)
1301 #define AXGBE_AN_CL73_PG_RCV BIT(2)
1302 #define AXGBE_AN_CL73_INT_MASK 0x07
1304 #define AXGBE_XNP_MCF_NULL_MESSAGE 0x001
1305 #define AXGBE_XNP_ACK_PROCESSED BIT(12)
1306 #define AXGBE_XNP_MP_FORMATTED BIT(13)
1307 #define AXGBE_XNP_NP_EXCHANGE BIT(15)
1309 #define AXGBE_KR_TRAINING_START BIT(0)
1310 #define AXGBE_KR_TRAINING_ENABLE BIT(1)
1312 #define AXGBE_PCS_CL37_BP BIT(12)
1314 #define AXGBE_AN_CL37_INT_CMPLT BIT(0)
1315 #define AXGBE_AN_CL37_INT_MASK 0x01
1317 #define AXGBE_AN_CL37_HD_MASK 0x40
1318 #define AXGBE_AN_CL37_FD_MASK 0x20
1320 #define AXGBE_AN_CL37_PCS_MODE_MASK 0x06
1321 #define AXGBE_AN_CL37_PCS_MODE_BASEX 0x00
1322 #define AXGBE_AN_CL37_PCS_MODE_SGMII 0x04
1323 #define AXGBE_AN_CL37_TX_CONFIG_MASK 0x08
1324 #define AXGBE_AN_CL37_MII_CTRL_8BIT 0x0100
1326 #define AXGBE_PMA_CDR_TRACK_EN_MASK 0x01
1327 #define AXGBE_PMA_CDR_TRACK_EN_OFF 0x00
1328 #define AXGBE_PMA_CDR_TRACK_EN_ON 0x01
1333 #define rmb() rte_rmb() /* dpdk rte provided rmb */
1334 #define wmb() rte_wmb() /* dpdk rte provided wmb */
1340 typedef unsigned char u8;
1341 typedef unsigned short u16;
1342 typedef unsigned int u32;
1343 typedef unsigned long long u64;
1344 typedef unsigned long long dma_addr_t;
1346 static inline uint32_t low32_value(uint64_t addr)
1348 return (addr) & 0x0ffffffff;
1351 static inline uint32_t high32_value(uint64_t addr)
1353 return (addr >> 32) & 0x0ffffffff;
1358 /* Bit setting and getting macros
1359 * The get macro will extract the current bit field value from within
1362 * The set macro will clear the current bit field value within the
1363 * variable and then set the bit field of the variable to the
1366 #define GET_BITS(_var, _index, _width) \
1367 (((_var) >> (_index)) & ((0x1 << (_width)) - 1))
1369 #define SET_BITS(_var, _index, _width, _val) \
1371 (_var) &= ~(((0x1 << (_width)) - 1) << (_index)); \
1372 (_var) |= (((_val) & ((0x1 << (_width)) - 1)) << (_index)); \
1375 #define GET_BITS_LE(_var, _index, _width) \
1376 ((rte_le_to_cpu_32((_var)) >> (_index)) & ((0x1 << (_width)) - 1))
1378 #define SET_BITS_LE(_var, _index, _width, _val) \
1380 (_var) &= rte_cpu_to_le_32(~(((0x1U << (_width)) - 1) << (_index)));\
1381 (_var) |= rte_cpu_to_le_32((((_val) & \
1382 ((0x1U << (_width)) - 1)) << (_index))); \
1385 /* Bit setting and getting macros based on register fields
1386 * The get macro uses the bit field definitions formed using the input
1387 * names to extract the current bit field value from within the
1390 * The set macro uses the bit field definitions formed using the input
1391 * names to set the bit field of the variable to the specified value
1393 #define AXGMAC_GET_BITS(_var, _prefix, _field) \
1395 _prefix##_##_field##_INDEX, \
1396 _prefix##_##_field##_WIDTH)
1398 #define AXGMAC_SET_BITS(_var, _prefix, _field, _val) \
1400 _prefix##_##_field##_INDEX, \
1401 _prefix##_##_field##_WIDTH, (_val))
1403 #define AXGMAC_GET_BITS_LE(_var, _prefix, _field) \
1404 GET_BITS_LE((_var), \
1405 _prefix##_##_field##_INDEX, \
1406 _prefix##_##_field##_WIDTH)
1408 #define AXGMAC_SET_BITS_LE(_var, _prefix, _field, _val) \
1409 SET_BITS_LE((_var), \
1410 _prefix##_##_field##_INDEX, \
1411 _prefix##_##_field##_WIDTH, (_val))
1413 /* Macros for reading or writing registers
1414 * The ioread macros will get bit fields or full values using the
1415 * register definitions formed using the input names
1417 * The iowrite macros will set bit fields or full values using the
1418 * register definitions formed using the input names
1420 #define AXGMAC_IOREAD(_pdata, _reg) \
1421 rte_read32((uint8_t *)((_pdata)->xgmac_regs) + (_reg))
1423 #define AXGMAC_IOREAD_BITS(_pdata, _reg, _field) \
1424 GET_BITS(AXGMAC_IOREAD((_pdata), _reg), \
1425 _reg##_##_field##_INDEX, \
1426 _reg##_##_field##_WIDTH)
1428 #define AXGMAC_IOWRITE(_pdata, _reg, _val) \
1429 rte_write32((_val), \
1430 (uint8_t *)((_pdata)->xgmac_regs) + (_reg))
1432 #define AXGMAC_IOWRITE_BITS(_pdata, _reg, _field, _val) \
1434 u32 reg_val = AXGMAC_IOREAD((_pdata), _reg); \
1436 _reg##_##_field##_INDEX, \
1437 _reg##_##_field##_WIDTH, (_val)); \
1438 AXGMAC_IOWRITE((_pdata), _reg, reg_val); \
1441 /* Macros for reading or writing MTL queue or traffic class registers
1442 * Similar to the standard read and write macros except that the
1443 * base register value is calculated by the queue or traffic class number
1445 #define AXGMAC_MTL_IOREAD(_pdata, _n, _reg) \
1446 rte_read32((uint8_t *)((_pdata)->xgmac_regs) + \
1447 MTL_Q_BASE + ((_n) * MTL_Q_INC) + (_reg))
1449 #define AXGMAC_MTL_IOREAD_BITS(_pdata, _n, _reg, _field) \
1450 GET_BITS(AXGMAC_MTL_IOREAD((_pdata), (_n), (_reg)), \
1451 _reg##_##_field##_INDEX, \
1452 _reg##_##_field##_WIDTH)
1454 #define AXGMAC_MTL_IOWRITE(_pdata, _n, _reg, _val) \
1455 rte_write32((_val), (uint8_t *)((_pdata)->xgmac_regs) +\
1456 MTL_Q_BASE + ((_n) * MTL_Q_INC) + (_reg))
1458 #define AXGMAC_MTL_IOWRITE_BITS(_pdata, _n, _reg, _field, _val) \
1460 u32 reg_val = AXGMAC_MTL_IOREAD((_pdata), (_n), _reg); \
1462 _reg##_##_field##_INDEX, \
1463 _reg##_##_field##_WIDTH, (_val)); \
1464 AXGMAC_MTL_IOWRITE((_pdata), (_n), _reg, reg_val); \
1467 /* Macros for reading or writing DMA channel registers
1468 * Similar to the standard read and write macros except that the
1469 * base register value is obtained from the ring
1471 #define AXGMAC_DMA_IOREAD(_channel, _reg) \
1472 rte_read32((uint8_t *)((_channel)->dma_regs) + (_reg))
1474 #define AXGMAC_DMA_IOREAD_BITS(_channel, _reg, _field) \
1475 GET_BITS(AXGMAC_DMA_IOREAD((_channel), _reg), \
1476 _reg##_##_field##_INDEX, \
1477 _reg##_##_field##_WIDTH)
1479 #define AXGMAC_DMA_IOWRITE(_channel, _reg, _val) \
1480 rte_write32((_val), \
1481 (uint8_t *)((_channel)->dma_regs) + (_reg))
1483 #define AXGMAC_DMA_IOWRITE_BITS(_channel, _reg, _field, _val) \
1485 u32 reg_val = AXGMAC_DMA_IOREAD((_channel), _reg); \
1487 _reg##_##_field##_INDEX, \
1488 _reg##_##_field##_WIDTH, (_val)); \
1489 AXGMAC_DMA_IOWRITE((_channel), _reg, reg_val); \
1492 /* Macros for building, reading or writing register values or bits
1493 * within the register values of XPCS registers.
1495 #define XPCS_GET_BITS(_var, _prefix, _field) \
1497 _prefix##_##_field##_INDEX, \
1498 _prefix##_##_field##_WIDTH)
1500 #define XPCS_SET_BITS(_var, _prefix, _field, _val) \
1502 _prefix##_##_field##_INDEX, \
1503 _prefix##_##_field##_WIDTH, (_val))
1505 #define XPCS32_IOWRITE(_pdata, _off, _val) \
1507 (uint8_t *)((_pdata)->xpcs_regs) + (_off))
1509 #define XPCS32_IOREAD(_pdata, _off) \
1510 rte_read32((uint8_t *)((_pdata)->xpcs_regs) + (_off))
1512 #define XPCS16_IOWRITE(_pdata, _off, _val) \
1514 (uint8_t *)((_pdata)->xpcs_regs) + (_off))
1516 #define XPCS16_IOREAD(_pdata, _off) \
1517 rte_read16((uint8_t *)((_pdata)->xpcs_regs) + (_off))
1519 /* Macros for building, reading or writing register values or bits
1520 * within the register values of SerDes integration registers.
1522 #define XSIR_GET_BITS(_var, _prefix, _field) \
1524 _prefix##_##_field##_INDEX, \
1525 _prefix##_##_field##_WIDTH)
1527 #define XSIR_SET_BITS(_var, _prefix, _field, _val) \
1529 _prefix##_##_field##_INDEX, \
1530 _prefix##_##_field##_WIDTH, (_val))
1532 #define XSIR0_IOREAD(_pdata, _reg) \
1533 rte_read16((uint8_t *)((_pdata)->sir0_regs) + (_reg))
1535 #define XSIR0_IOREAD_BITS(_pdata, _reg, _field) \
1536 GET_BITS(XSIR0_IOREAD((_pdata), _reg), \
1537 _reg##_##_field##_INDEX, \
1538 _reg##_##_field##_WIDTH)
1540 #define XSIR0_IOWRITE(_pdata, _reg, _val) \
1541 rte_write16((_val), \
1542 (uint8_t *)((_pdata)->sir0_regs) + (_reg))
1544 #define XSIR0_IOWRITE_BITS(_pdata, _reg, _field, _val) \
1546 u16 reg_val = XSIR0_IOREAD((_pdata), _reg); \
1548 _reg##_##_field##_INDEX, \
1549 _reg##_##_field##_WIDTH, (_val)); \
1550 XSIR0_IOWRITE((_pdata), _reg, reg_val); \
1553 #define XSIR1_IOREAD(_pdata, _reg) \
1554 rte_read16((uint8_t *)((_pdata)->sir1_regs) + _reg)
1556 #define XSIR1_IOREAD_BITS(_pdata, _reg, _field) \
1557 GET_BITS(XSIR1_IOREAD((_pdata), _reg), \
1558 _reg##_##_field##_INDEX, \
1559 _reg##_##_field##_WIDTH)
1561 #define XSIR1_IOWRITE(_pdata, _reg, _val) \
1562 rte_write16((_val), \
1563 (uint8_t *)((_pdata)->sir1_regs) + (_reg))
1565 #define XSIR1_IOWRITE_BITS(_pdata, _reg, _field, _val) \
1567 u16 reg_val = XSIR1_IOREAD((_pdata), _reg); \
1569 _reg##_##_field##_INDEX, \
1570 _reg##_##_field##_WIDTH, (_val)); \
1571 XSIR1_IOWRITE((_pdata), _reg, reg_val); \
1574 /* Macros for building, reading or writing register values or bits
1575 * within the register values of SerDes RxTx registers.
1577 #define XRXTX_IOREAD(_pdata, _reg) \
1578 rte_read16((uint8_t *)((_pdata)->rxtx_regs) + (_reg))
1580 #define XRXTX_IOREAD_BITS(_pdata, _reg, _field) \
1581 GET_BITS(XRXTX_IOREAD((_pdata), _reg), \
1582 _reg##_##_field##_INDEX, \
1583 _reg##_##_field##_WIDTH)
1585 #define XRXTX_IOWRITE(_pdata, _reg, _val) \
1586 rte_write16((_val), \
1587 (uint8_t *)((_pdata)->rxtx_regs) + (_reg))
1589 #define XRXTX_IOWRITE_BITS(_pdata, _reg, _field, _val) \
1591 u16 reg_val = XRXTX_IOREAD((_pdata), _reg); \
1593 _reg##_##_field##_INDEX, \
1594 _reg##_##_field##_WIDTH, (_val)); \
1595 XRXTX_IOWRITE((_pdata), _reg, reg_val); \
1598 /* Macros for building, reading or writing register values or bits
1599 * within the register values of MAC Control registers.
1601 #define XP_GET_BITS(_var, _prefix, _field) \
1603 _prefix##_##_field##_INDEX, \
1604 _prefix##_##_field##_WIDTH)
1606 #define XP_SET_BITS(_var, _prefix, _field, _val) \
1608 _prefix##_##_field##_INDEX, \
1609 _prefix##_##_field##_WIDTH, (_val))
1611 #define XP_IOREAD(_pdata, _reg) \
1612 rte_read32((uint8_t *)((_pdata)->xprop_regs) + (_reg))
1614 #define XP_IOREAD_BITS(_pdata, _reg, _field) \
1615 GET_BITS(XP_IOREAD((_pdata), (_reg)), \
1616 _reg##_##_field##_INDEX, \
1617 _reg##_##_field##_WIDTH)
1619 #define XP_IOWRITE(_pdata, _reg, _val) \
1620 rte_write32((_val), \
1621 (uint8_t *)((_pdata)->xprop_regs) + (_reg))
1623 #define XP_IOWRITE_BITS(_pdata, _reg, _field, _val) \
1625 u32 reg_val = XP_IOREAD((_pdata), (_reg)); \
1627 _reg##_##_field##_INDEX, \
1628 _reg##_##_field##_WIDTH, (_val)); \
1629 XP_IOWRITE((_pdata), (_reg), reg_val); \
1632 /* Macros for building, reading or writing register values or bits
1633 * within the register values of I2C Control registers.
1635 #define XI2C_GET_BITS(_var, _prefix, _field) \
1637 _prefix##_##_field##_INDEX, \
1638 _prefix##_##_field##_WIDTH)
1640 #define XI2C_SET_BITS(_var, _prefix, _field, _val) \
1642 _prefix##_##_field##_INDEX, \
1643 _prefix##_##_field##_WIDTH, (_val))
1645 #define XI2C_IOREAD(_pdata, _reg) \
1646 rte_read32((uint8_t *)((_pdata)->xi2c_regs) + (_reg))
1648 #define XI2C_IOREAD_BITS(_pdata, _reg, _field) \
1649 GET_BITS(XI2C_IOREAD((_pdata), (_reg)), \
1650 _reg##_##_field##_INDEX, \
1651 _reg##_##_field##_WIDTH)
1653 #define XI2C_IOWRITE(_pdata, _reg, _val) \
1654 rte_write32((_val), \
1655 (uint8_t *)((_pdata)->xi2c_regs) + (_reg))
1657 #define XI2C_IOWRITE_BITS(_pdata, _reg, _field, _val) \
1659 u32 reg_val = XI2C_IOREAD((_pdata), (_reg)); \
1661 _reg##_##_field##_INDEX, \
1662 _reg##_##_field##_WIDTH, (_val)); \
1663 XI2C_IOWRITE((_pdata), (_reg), reg_val); \
1666 /* Macros for building, reading or writing register values or bits
1667 * using MDIO. Different from above because of the use of standardized
1668 * Linux include values. No shifting is performed with the bit
1669 * operations, everything works on mask values.
1671 #define XMDIO_READ(_pdata, _mmd, _reg) \
1672 ((_pdata)->hw_if.read_mmd_regs((_pdata), 0, \
1673 MII_ADDR_C45 | ((_mmd) << 16) | ((_reg) & 0xffff)))
1675 #define XMDIO_READ_BITS(_pdata, _mmd, _reg, _mask) \
1676 (XMDIO_READ((_pdata), _mmd, _reg) & _mask)
1678 #define XMDIO_WRITE(_pdata, _mmd, _reg, _val) \
1679 ((_pdata)->hw_if.write_mmd_regs((_pdata), 0, \
1680 MII_ADDR_C45 | ((_mmd) << 16) | ((_reg) & 0xffff), (_val)))
1682 #define XMDIO_WRITE_BITS(_pdata, _mmd, _reg, _mask, _val) \
1684 u32 mmd_val = XMDIO_READ((_pdata), (_mmd), (_reg)); \
1685 mmd_val &= ~(_mask); \
1686 mmd_val |= (_val); \
1687 XMDIO_WRITE((_pdata), (_mmd), (_reg), (mmd_val)); \
1691 * time_after(a,b) returns true if the time a is after time b.
1693 * Do this with "<0" and ">=0" to only test the sign of the result. A
1694 * good compiler would generate better code (and a really good compiler
1695 * wouldn't care). Gcc is currently neither.
1697 #define time_after(a, b) ((long)((b) - (a)) < 0)
1698 #define time_before(a, b) time_after(b, a)
1700 #define time_after_eq(a, b) ((long)((a) - (b)) >= 0)
1701 #define time_before_eq(a, b) time_after_eq(b, a)
1703 /*---bitmap support apis---*/
1704 static inline int axgbe_test_bit(int nr, volatile unsigned long *addr)
1709 res = ((*addr) & (1UL << nr)) != 0;
1714 static inline void axgbe_set_bit(unsigned int nr, volatile unsigned long *addr)
1716 __sync_fetch_and_or(addr, (1UL << nr));
1719 static inline void axgbe_clear_bit(int nr, volatile unsigned long *addr)
1721 __sync_fetch_and_and(addr, ~(1UL << nr));
1724 static inline int axgbe_test_and_clear_bit(int nr, volatile unsigned long *addr)
1726 unsigned long mask = (1UL << nr);
1728 return __sync_fetch_and_and(addr, ~mask) & mask;
1731 static inline unsigned long msecs_to_timer_cycles(unsigned int m)
1733 return rte_get_timer_hz() * (m / 1000);
1736 #endif /* __AXGBE_COMMON_H__ */