1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved.
3 * Copyright(c) 2018 Synopsys, Inc. All rights reserved.
6 #include "axgbe_ethdev.h"
7 #include "axgbe_common.h"
10 static int eth_axgbe_dev_init(struct rte_eth_dev *eth_dev);
11 static int eth_axgbe_dev_uninit(struct rte_eth_dev *eth_dev);
13 /* The set of PCI devices this driver supports */
14 #define AMD_PCI_VENDOR_ID 0x1022
15 #define AMD_PCI_AXGBE_DEVICE_V2A 0x1458
16 #define AMD_PCI_AXGBE_DEVICE_V2B 0x1459
18 int axgbe_logtype_init;
19 int axgbe_logtype_driver;
21 static const struct rte_pci_id pci_id_axgbe_map[] = {
22 {RTE_PCI_DEVICE(AMD_PCI_VENDOR_ID, AMD_PCI_AXGBE_DEVICE_V2A)},
23 {RTE_PCI_DEVICE(AMD_PCI_VENDOR_ID, AMD_PCI_AXGBE_DEVICE_V2B)},
27 static struct axgbe_version_data axgbe_v2a = {
28 .xpcs_access = AXGBE_XPCS_ACCESS_V2,
30 .tx_max_fifo_size = 229376,
31 .rx_max_fifo_size = 229376,
32 .tx_tstamp_workaround = 1,
37 static struct axgbe_version_data axgbe_v2b = {
38 .xpcs_access = AXGBE_XPCS_ACCESS_V2,
40 .tx_max_fifo_size = 65536,
41 .rx_max_fifo_size = 65536,
42 .tx_tstamp_workaround = 1,
47 static void axgbe_get_all_hw_features(struct axgbe_port *pdata)
49 unsigned int mac_hfr0, mac_hfr1, mac_hfr2;
50 struct axgbe_hw_features *hw_feat = &pdata->hw_feat;
52 mac_hfr0 = AXGMAC_IOREAD(pdata, MAC_HWF0R);
53 mac_hfr1 = AXGMAC_IOREAD(pdata, MAC_HWF1R);
54 mac_hfr2 = AXGMAC_IOREAD(pdata, MAC_HWF2R);
56 memset(hw_feat, 0, sizeof(*hw_feat));
58 hw_feat->version = AXGMAC_IOREAD(pdata, MAC_VR);
60 /* Hardware feature register 0 */
61 hw_feat->gmii = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL);
62 hw_feat->vlhash = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH);
63 hw_feat->sma = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SMASEL);
64 hw_feat->rwk = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RWKSEL);
65 hw_feat->mgk = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MGKSEL);
66 hw_feat->mmc = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MMCSEL);
67 hw_feat->aoe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ARPOFFSEL);
68 hw_feat->ts = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSEL);
69 hw_feat->eee = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, EEESEL);
70 hw_feat->tx_coe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TXCOESEL);
71 hw_feat->rx_coe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RXCOESEL);
72 hw_feat->addn_mac = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R,
74 hw_feat->ts_src = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSTSSEL);
75 hw_feat->sa_vlan_ins = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SAVLANINS);
77 /* Hardware feature register 1 */
78 hw_feat->rx_fifo_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
80 hw_feat->tx_fifo_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
82 hw_feat->adv_ts_hi = AXGMAC_GET_BITS(mac_hfr1,
83 MAC_HWF1R, ADVTHWORD);
84 hw_feat->dma_width = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADDR64);
85 hw_feat->dcb = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN);
86 hw_feat->sph = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN);
87 hw_feat->tso = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN);
88 hw_feat->dma_debug = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA);
89 hw_feat->rss = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, RSSEN);
90 hw_feat->tc_cnt = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC);
91 hw_feat->hash_table_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
93 hw_feat->l3l4_filter_num = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
96 /* Hardware feature register 2 */
97 hw_feat->rx_q_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXQCNT);
98 hw_feat->tx_q_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXQCNT);
99 hw_feat->rx_ch_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXCHCNT);
100 hw_feat->tx_ch_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXCHCNT);
101 hw_feat->pps_out_num = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM);
102 hw_feat->aux_snap_num = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R,
105 /* Translate the Hash Table size into actual number */
106 switch (hw_feat->hash_table_size) {
110 hw_feat->hash_table_size = 64;
113 hw_feat->hash_table_size = 128;
116 hw_feat->hash_table_size = 256;
120 /* Translate the address width setting into actual number */
121 switch (hw_feat->dma_width) {
123 hw_feat->dma_width = 32;
126 hw_feat->dma_width = 40;
129 hw_feat->dma_width = 48;
132 hw_feat->dma_width = 32;
135 /* The Queue, Channel and TC counts are zero based so increment them
136 * to get the actual number
140 hw_feat->rx_ch_cnt++;
141 hw_feat->tx_ch_cnt++;
144 /* Translate the fifo sizes into actual numbers */
145 hw_feat->rx_fifo_size = 1 << (hw_feat->rx_fifo_size + 7);
146 hw_feat->tx_fifo_size = 1 << (hw_feat->tx_fifo_size + 7);
149 static void axgbe_init_all_fptrs(struct axgbe_port *pdata)
151 axgbe_init_function_ptrs_dev(&pdata->hw_if);
154 static void axgbe_set_counts(struct axgbe_port *pdata)
156 /* Set all the function pointers */
157 axgbe_init_all_fptrs(pdata);
159 /* Populate the hardware features */
160 axgbe_get_all_hw_features(pdata);
162 /* Set default max values if not provided */
163 if (!pdata->tx_max_channel_count)
164 pdata->tx_max_channel_count = pdata->hw_feat.tx_ch_cnt;
165 if (!pdata->rx_max_channel_count)
166 pdata->rx_max_channel_count = pdata->hw_feat.rx_ch_cnt;
168 if (!pdata->tx_max_q_count)
169 pdata->tx_max_q_count = pdata->hw_feat.tx_q_cnt;
170 if (!pdata->rx_max_q_count)
171 pdata->rx_max_q_count = pdata->hw_feat.rx_q_cnt;
173 /* Calculate the number of Tx and Rx rings to be created
174 * -Tx (DMA) Channels map 1-to-1 to Tx Queues so set
175 * the number of Tx queues to the number of Tx channels
177 * -Rx (DMA) Channels do not map 1-to-1 so use the actual
178 * number of Rx queues or maximum allowed
180 pdata->tx_ring_count = RTE_MIN(pdata->hw_feat.tx_ch_cnt,
181 pdata->tx_max_channel_count);
182 pdata->tx_ring_count = RTE_MIN(pdata->tx_ring_count,
183 pdata->tx_max_q_count);
185 pdata->tx_q_count = pdata->tx_ring_count;
187 pdata->rx_ring_count = RTE_MIN(pdata->hw_feat.rx_ch_cnt,
188 pdata->rx_max_channel_count);
190 pdata->rx_q_count = RTE_MIN(pdata->hw_feat.rx_q_cnt,
191 pdata->rx_max_q_count);
194 static void axgbe_default_config(struct axgbe_port *pdata)
196 pdata->pblx8 = DMA_PBL_X8_ENABLE;
197 pdata->tx_sf_mode = MTL_TSF_ENABLE;
198 pdata->tx_threshold = MTL_TX_THRESHOLD_64;
199 pdata->tx_pbl = DMA_PBL_32;
200 pdata->tx_osp_mode = DMA_OSP_ENABLE;
201 pdata->rx_sf_mode = MTL_RSF_ENABLE;
202 pdata->rx_threshold = MTL_RX_THRESHOLD_64;
203 pdata->rx_pbl = DMA_PBL_32;
204 pdata->pause_autoneg = 1;
207 pdata->phy_speed = SPEED_UNKNOWN;
208 pdata->power_down = 0;
212 * It returns 0 on success.
215 eth_axgbe_dev_init(struct rte_eth_dev *eth_dev)
217 PMD_INIT_FUNC_TRACE();
218 struct axgbe_port *pdata;
219 struct rte_pci_device *pci_dev;
220 uint32_t reg, mac_lo, mac_hi;
224 * For secondary processes, we don't initialise any further as primary
225 * has already done this work.
227 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
230 pdata = (struct axgbe_port *)eth_dev->data->dev_private;
232 axgbe_set_bit(AXGBE_DOWN, &pdata->dev_state);
233 axgbe_set_bit(AXGBE_STOPPED, &pdata->dev_state);
234 pdata->eth_dev = eth_dev;
236 pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
237 pdata->pci_dev = pci_dev;
240 (uint64_t)pci_dev->mem_resource[AXGBE_AXGMAC_BAR].addr;
241 pdata->xprop_regs = pdata->xgmac_regs + AXGBE_MAC_PROP_OFFSET;
242 pdata->xi2c_regs = pdata->xgmac_regs + AXGBE_I2C_CTRL_OFFSET;
243 pdata->xpcs_regs = (uint64_t)pci_dev->mem_resource[AXGBE_XPCS_BAR].addr;
245 /* version specific driver data*/
246 if (pci_dev->id.device_id == AMD_PCI_AXGBE_DEVICE_V2A)
247 pdata->vdata = &axgbe_v2a;
249 pdata->vdata = &axgbe_v2b;
251 /* Configure the PCS indirect addressing support */
252 reg = XPCS32_IOREAD(pdata, PCS_V2_WINDOW_DEF);
253 pdata->xpcs_window = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, OFFSET);
254 pdata->xpcs_window <<= 6;
255 pdata->xpcs_window_size = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, SIZE);
256 pdata->xpcs_window_size = 1 << (pdata->xpcs_window_size + 7);
257 pdata->xpcs_window_mask = pdata->xpcs_window_size - 1;
258 pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF;
259 pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT;
261 "xpcs window :%x, size :%x, mask :%x ", pdata->xpcs_window,
262 pdata->xpcs_window_size, pdata->xpcs_window_mask);
263 XP_IOWRITE(pdata, XP_INT_EN, 0x1fffff);
265 /* Retrieve the MAC address */
266 mac_lo = XP_IOREAD(pdata, XP_MAC_ADDR_LO);
267 mac_hi = XP_IOREAD(pdata, XP_MAC_ADDR_HI);
268 pdata->mac_addr.addr_bytes[0] = mac_lo & 0xff;
269 pdata->mac_addr.addr_bytes[1] = (mac_lo >> 8) & 0xff;
270 pdata->mac_addr.addr_bytes[2] = (mac_lo >> 16) & 0xff;
271 pdata->mac_addr.addr_bytes[3] = (mac_lo >> 24) & 0xff;
272 pdata->mac_addr.addr_bytes[4] = mac_hi & 0xff;
273 pdata->mac_addr.addr_bytes[5] = (mac_hi >> 8) & 0xff;
275 eth_dev->data->mac_addrs = rte_zmalloc("axgbe_mac_addr",
277 if (!eth_dev->data->mac_addrs) {
279 "Failed to alloc %u bytes needed to store MAC addr tbl",
284 if (!is_valid_assigned_ether_addr(&pdata->mac_addr))
285 eth_random_addr(pdata->mac_addr.addr_bytes);
287 /* Copy the permanent MAC address */
288 ether_addr_copy(&pdata->mac_addr, ð_dev->data->mac_addrs[0]);
291 pdata->sysclk_rate = AXGBE_V2_DMA_CLOCK_FREQ;
292 pdata->ptpclk_rate = AXGBE_V2_PTP_CLOCK_FREQ;
294 /* Set the DMA coherency values */
296 pdata->axdomain = AXGBE_DMA_OS_AXDOMAIN;
297 pdata->arcache = AXGBE_DMA_OS_ARCACHE;
298 pdata->awcache = AXGBE_DMA_OS_AWCACHE;
300 /* Set the maximum channels and queues */
301 reg = XP_IOREAD(pdata, XP_PROP_1);
302 pdata->tx_max_channel_count = XP_GET_BITS(reg, XP_PROP_1, MAX_TX_DMA);
303 pdata->rx_max_channel_count = XP_GET_BITS(reg, XP_PROP_1, MAX_RX_DMA);
304 pdata->tx_max_q_count = XP_GET_BITS(reg, XP_PROP_1, MAX_TX_QUEUES);
305 pdata->rx_max_q_count = XP_GET_BITS(reg, XP_PROP_1, MAX_RX_QUEUES);
307 /* Set the hardware channel and queue counts */
308 axgbe_set_counts(pdata);
310 /* Set the maximum fifo amounts */
311 reg = XP_IOREAD(pdata, XP_PROP_2);
312 pdata->tx_max_fifo_size = XP_GET_BITS(reg, XP_PROP_2, TX_FIFO_SIZE);
313 pdata->tx_max_fifo_size *= 16384;
314 pdata->tx_max_fifo_size = RTE_MIN(pdata->tx_max_fifo_size,
315 pdata->vdata->tx_max_fifo_size);
316 pdata->rx_max_fifo_size = XP_GET_BITS(reg, XP_PROP_2, RX_FIFO_SIZE);
317 pdata->rx_max_fifo_size *= 16384;
318 pdata->rx_max_fifo_size = RTE_MIN(pdata->rx_max_fifo_size,
319 pdata->vdata->rx_max_fifo_size);
320 /* Issue software reset to DMA */
321 ret = pdata->hw_if.exit(pdata);
323 PMD_DRV_LOG(ERR, "hw_if->exit EBUSY error\n");
325 /* Set default configuration data */
326 axgbe_default_config(pdata);
328 /* Set default max values if not provided */
329 if (!pdata->tx_max_fifo_size)
330 pdata->tx_max_fifo_size = pdata->hw_feat.tx_fifo_size;
331 if (!pdata->rx_max_fifo_size)
332 pdata->rx_max_fifo_size = pdata->hw_feat.rx_fifo_size;
334 pthread_mutex_init(&pdata->xpcs_mutex, NULL);
335 pthread_mutex_init(&pdata->i2c_mutex, NULL);
336 pthread_mutex_init(&pdata->an_mutex, NULL);
337 pthread_mutex_init(&pdata->phy_mutex, NULL);
339 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
340 eth_dev->data->port_id, pci_dev->id.vendor_id,
341 pci_dev->id.device_id);
347 eth_axgbe_dev_uninit(struct rte_eth_dev *eth_dev)
349 PMD_INIT_FUNC_TRACE();
351 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
355 rte_free(eth_dev->data->mac_addrs);
356 eth_dev->data->mac_addrs = NULL;
361 static int eth_axgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
362 struct rte_pci_device *pci_dev)
364 return rte_eth_dev_pci_generic_probe(pci_dev,
365 sizeof(struct axgbe_port), eth_axgbe_dev_init);
368 static int eth_axgbe_pci_remove(struct rte_pci_device *pci_dev)
370 return rte_eth_dev_pci_generic_remove(pci_dev, eth_axgbe_dev_uninit);
373 static struct rte_pci_driver rte_axgbe_pmd = {
374 .id_table = pci_id_axgbe_map,
375 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
376 .probe = eth_axgbe_pci_probe,
377 .remove = eth_axgbe_pci_remove,
380 RTE_PMD_REGISTER_PCI(net_axgbe, rte_axgbe_pmd);
381 RTE_PMD_REGISTER_PCI_TABLE(net_axgbe, pci_id_axgbe_map);
382 RTE_PMD_REGISTER_KMOD_DEP(net_axgbe, "* igb_uio | uio_pci_generic | vfio-pci");
384 RTE_INIT(axgbe_init_log);
388 axgbe_logtype_init = rte_log_register("pmd.net.axgbe.init");
389 if (axgbe_logtype_init >= 0)
390 rte_log_set_level(axgbe_logtype_init, RTE_LOG_NOTICE);
391 axgbe_logtype_driver = rte_log_register("pmd.net.axgbe.driver");
392 if (axgbe_logtype_driver >= 0)
393 rte_log_set_level(axgbe_logtype_driver, RTE_LOG_NOTICE);