1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved.
3 * Copyright(c) 2018 Synopsys, Inc. All rights reserved.
6 #include "axgbe_rxtx.h"
7 #include "axgbe_ethdev.h"
8 #include "axgbe_common.h"
10 #include "axgbe_regs.h"
13 static int eth_axgbe_dev_init(struct rte_eth_dev *eth_dev);
14 static int axgbe_dev_configure(struct rte_eth_dev *dev);
15 static int axgbe_dev_start(struct rte_eth_dev *dev);
16 static int axgbe_dev_stop(struct rte_eth_dev *dev);
17 static void axgbe_dev_interrupt_handler(void *param);
18 static int axgbe_dev_close(struct rte_eth_dev *dev);
19 static int axgbe_dev_reset(struct rte_eth_dev *dev);
20 static int axgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
21 static int axgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
22 static int axgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
23 static int axgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
24 static int axgbe_dev_mac_addr_set(struct rte_eth_dev *dev,
25 struct rte_ether_addr *mac_addr);
26 static int axgbe_dev_mac_addr_add(struct rte_eth_dev *dev,
27 struct rte_ether_addr *mac_addr,
30 static void axgbe_dev_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
31 static int axgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
32 struct rte_ether_addr *mc_addr_set,
34 static int axgbe_dev_uc_hash_table_set(struct rte_eth_dev *dev,
35 struct rte_ether_addr *mac_addr,
37 static int axgbe_dev_uc_all_hash_table_set(struct rte_eth_dev *dev,
39 static int axgbe_dev_link_update(struct rte_eth_dev *dev,
40 int wait_to_complete);
41 static int axgbe_dev_get_regs(struct rte_eth_dev *dev,
42 struct rte_dev_reg_info *regs);
43 static int axgbe_dev_stats_get(struct rte_eth_dev *dev,
44 struct rte_eth_stats *stats);
45 static int axgbe_dev_stats_reset(struct rte_eth_dev *dev);
46 static int axgbe_dev_xstats_get(struct rte_eth_dev *dev,
47 struct rte_eth_xstat *stats,
50 axgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
51 struct rte_eth_xstat_name *xstats_names,
54 axgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev,
59 axgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev,
61 struct rte_eth_xstat_name *xstats_names,
63 static int axgbe_dev_xstats_reset(struct rte_eth_dev *dev);
64 static int axgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
65 struct rte_eth_rss_reta_entry64 *reta_conf,
67 static int axgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
68 struct rte_eth_rss_reta_entry64 *reta_conf,
70 static int axgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
71 struct rte_eth_rss_conf *rss_conf);
72 static int axgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
73 struct rte_eth_rss_conf *rss_conf);
74 static int axgbe_dev_info_get(struct rte_eth_dev *dev,
75 struct rte_eth_dev_info *dev_info);
76 static int axgbe_flow_ctrl_get(struct rte_eth_dev *dev,
77 struct rte_eth_fc_conf *fc_conf);
78 static int axgbe_flow_ctrl_set(struct rte_eth_dev *dev,
79 struct rte_eth_fc_conf *fc_conf);
80 static int axgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
81 struct rte_eth_pfc_conf *pfc_conf);
82 static void axgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
83 struct rte_eth_rxq_info *qinfo);
84 static void axgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
85 struct rte_eth_txq_info *qinfo);
86 const uint32_t *axgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
87 static int axgb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
90 axgbe_timesync_enable(struct rte_eth_dev *dev);
92 axgbe_timesync_disable(struct rte_eth_dev *dev);
94 axgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
95 struct timespec *timestamp, uint32_t flags);
97 axgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
98 struct timespec *timestamp);
100 axgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
102 axgbe_timesync_read_time(struct rte_eth_dev *dev,
103 struct timespec *timestamp);
105 axgbe_timesync_write_time(struct rte_eth_dev *dev,
106 const struct timespec *timestamp);
108 axgbe_set_tstamp_time(struct axgbe_port *pdata, unsigned int sec,
111 axgbe_update_tstamp_addend(struct axgbe_port *pdata,
112 unsigned int addend);
114 axgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vid, int on);
115 static int axgbe_vlan_tpid_set(struct rte_eth_dev *dev,
116 enum rte_vlan_type vlan_type, uint16_t tpid);
117 static int axgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
119 struct axgbe_xstats {
120 char name[RTE_ETH_XSTATS_NAME_SIZE];
124 #define AXGMAC_MMC_STAT(_string, _var) \
126 offsetof(struct axgbe_mmc_stats, _var), \
129 static const struct axgbe_xstats axgbe_xstats_strings[] = {
130 AXGMAC_MMC_STAT("tx_bytes", txoctetcount_gb),
131 AXGMAC_MMC_STAT("tx_packets", txframecount_gb),
132 AXGMAC_MMC_STAT("tx_unicast_packets", txunicastframes_gb),
133 AXGMAC_MMC_STAT("tx_broadcast_packets", txbroadcastframes_gb),
134 AXGMAC_MMC_STAT("tx_multicast_packets", txmulticastframes_gb),
135 AXGMAC_MMC_STAT("tx_vlan_packets", txvlanframes_g),
136 AXGMAC_MMC_STAT("tx_64_byte_packets", tx64octets_gb),
137 AXGMAC_MMC_STAT("tx_65_to_127_byte_packets", tx65to127octets_gb),
138 AXGMAC_MMC_STAT("tx_128_to_255_byte_packets", tx128to255octets_gb),
139 AXGMAC_MMC_STAT("tx_256_to_511_byte_packets", tx256to511octets_gb),
140 AXGMAC_MMC_STAT("tx_512_to_1023_byte_packets", tx512to1023octets_gb),
141 AXGMAC_MMC_STAT("tx_1024_to_max_byte_packets", tx1024tomaxoctets_gb),
142 AXGMAC_MMC_STAT("tx_underflow_errors", txunderflowerror),
143 AXGMAC_MMC_STAT("tx_pause_frames", txpauseframes),
145 AXGMAC_MMC_STAT("rx_bytes", rxoctetcount_gb),
146 AXGMAC_MMC_STAT("rx_packets", rxframecount_gb),
147 AXGMAC_MMC_STAT("rx_unicast_packets", rxunicastframes_g),
148 AXGMAC_MMC_STAT("rx_broadcast_packets", rxbroadcastframes_g),
149 AXGMAC_MMC_STAT("rx_multicast_packets", rxmulticastframes_g),
150 AXGMAC_MMC_STAT("rx_vlan_packets", rxvlanframes_gb),
151 AXGMAC_MMC_STAT("rx_64_byte_packets", rx64octets_gb),
152 AXGMAC_MMC_STAT("rx_65_to_127_byte_packets", rx65to127octets_gb),
153 AXGMAC_MMC_STAT("rx_128_to_255_byte_packets", rx128to255octets_gb),
154 AXGMAC_MMC_STAT("rx_256_to_511_byte_packets", rx256to511octets_gb),
155 AXGMAC_MMC_STAT("rx_512_to_1023_byte_packets", rx512to1023octets_gb),
156 AXGMAC_MMC_STAT("rx_1024_to_max_byte_packets", rx1024tomaxoctets_gb),
157 AXGMAC_MMC_STAT("rx_undersize_packets", rxundersize_g),
158 AXGMAC_MMC_STAT("rx_oversize_packets", rxoversize_g),
159 AXGMAC_MMC_STAT("rx_crc_errors", rxcrcerror),
160 AXGMAC_MMC_STAT("rx_crc_errors_small_packets", rxrunterror),
161 AXGMAC_MMC_STAT("rx_crc_errors_giant_packets", rxjabbererror),
162 AXGMAC_MMC_STAT("rx_length_errors", rxlengtherror),
163 AXGMAC_MMC_STAT("rx_out_of_range_errors", rxoutofrangetype),
164 AXGMAC_MMC_STAT("rx_fifo_overflow_errors", rxfifooverflow),
165 AXGMAC_MMC_STAT("rx_watchdog_errors", rxwatchdogerror),
166 AXGMAC_MMC_STAT("rx_pause_frames", rxpauseframes),
169 #define AXGBE_XSTATS_COUNT ARRAY_SIZE(axgbe_xstats_strings)
171 /* The set of PCI devices this driver supports */
172 #define AMD_PCI_VENDOR_ID 0x1022
173 #define AMD_PCI_RV_ROOT_COMPLEX_ID 0x15d0
174 #define AMD_PCI_AXGBE_DEVICE_V2A 0x1458
175 #define AMD_PCI_AXGBE_DEVICE_V2B 0x1459
177 static const struct rte_pci_id pci_id_axgbe_map[] = {
178 {RTE_PCI_DEVICE(AMD_PCI_VENDOR_ID, AMD_PCI_AXGBE_DEVICE_V2A)},
179 {RTE_PCI_DEVICE(AMD_PCI_VENDOR_ID, AMD_PCI_AXGBE_DEVICE_V2B)},
183 static struct axgbe_version_data axgbe_v2a = {
184 .init_function_ptrs_phy_impl = axgbe_init_function_ptrs_phy_v2,
185 .xpcs_access = AXGBE_XPCS_ACCESS_V2,
187 .tx_max_fifo_size = 229376,
188 .rx_max_fifo_size = 229376,
189 .tx_tstamp_workaround = 1,
192 .an_cdr_workaround = 1,
195 static struct axgbe_version_data axgbe_v2b = {
196 .init_function_ptrs_phy_impl = axgbe_init_function_ptrs_phy_v2,
197 .xpcs_access = AXGBE_XPCS_ACCESS_V2,
199 .tx_max_fifo_size = 65536,
200 .rx_max_fifo_size = 65536,
201 .tx_tstamp_workaround = 1,
204 .an_cdr_workaround = 1,
207 static const struct rte_eth_desc_lim rx_desc_lim = {
208 .nb_max = AXGBE_MAX_RING_DESC,
209 .nb_min = AXGBE_MIN_RING_DESC,
213 static const struct rte_eth_desc_lim tx_desc_lim = {
214 .nb_max = AXGBE_MAX_RING_DESC,
215 .nb_min = AXGBE_MIN_RING_DESC,
219 static const struct eth_dev_ops axgbe_eth_dev_ops = {
220 .dev_configure = axgbe_dev_configure,
221 .dev_start = axgbe_dev_start,
222 .dev_stop = axgbe_dev_stop,
223 .dev_close = axgbe_dev_close,
224 .dev_reset = axgbe_dev_reset,
225 .promiscuous_enable = axgbe_dev_promiscuous_enable,
226 .promiscuous_disable = axgbe_dev_promiscuous_disable,
227 .allmulticast_enable = axgbe_dev_allmulticast_enable,
228 .allmulticast_disable = axgbe_dev_allmulticast_disable,
229 .mac_addr_set = axgbe_dev_mac_addr_set,
230 .mac_addr_add = axgbe_dev_mac_addr_add,
231 .mac_addr_remove = axgbe_dev_mac_addr_remove,
232 .set_mc_addr_list = axgbe_dev_set_mc_addr_list,
233 .uc_hash_table_set = axgbe_dev_uc_hash_table_set,
234 .uc_all_hash_table_set = axgbe_dev_uc_all_hash_table_set,
235 .link_update = axgbe_dev_link_update,
236 .get_reg = axgbe_dev_get_regs,
237 .stats_get = axgbe_dev_stats_get,
238 .stats_reset = axgbe_dev_stats_reset,
239 .xstats_get = axgbe_dev_xstats_get,
240 .xstats_reset = axgbe_dev_xstats_reset,
241 .xstats_get_names = axgbe_dev_xstats_get_names,
242 .xstats_get_names_by_id = axgbe_dev_xstats_get_names_by_id,
243 .xstats_get_by_id = axgbe_dev_xstats_get_by_id,
244 .reta_update = axgbe_dev_rss_reta_update,
245 .reta_query = axgbe_dev_rss_reta_query,
246 .rss_hash_update = axgbe_dev_rss_hash_update,
247 .rss_hash_conf_get = axgbe_dev_rss_hash_conf_get,
248 .dev_infos_get = axgbe_dev_info_get,
249 .rx_queue_setup = axgbe_dev_rx_queue_setup,
250 .rx_queue_release = axgbe_dev_rx_queue_release,
251 .tx_queue_setup = axgbe_dev_tx_queue_setup,
252 .tx_queue_release = axgbe_dev_tx_queue_release,
253 .flow_ctrl_get = axgbe_flow_ctrl_get,
254 .flow_ctrl_set = axgbe_flow_ctrl_set,
255 .priority_flow_ctrl_set = axgbe_priority_flow_ctrl_set,
256 .rxq_info_get = axgbe_rxq_info_get,
257 .txq_info_get = axgbe_txq_info_get,
258 .dev_supported_ptypes_get = axgbe_dev_supported_ptypes_get,
259 .mtu_set = axgb_mtu_set,
260 .vlan_filter_set = axgbe_vlan_filter_set,
261 .vlan_tpid_set = axgbe_vlan_tpid_set,
262 .vlan_offload_set = axgbe_vlan_offload_set,
263 .timesync_enable = axgbe_timesync_enable,
264 .timesync_disable = axgbe_timesync_disable,
265 .timesync_read_rx_timestamp = axgbe_timesync_read_rx_timestamp,
266 .timesync_read_tx_timestamp = axgbe_timesync_read_tx_timestamp,
267 .timesync_adjust_time = axgbe_timesync_adjust_time,
268 .timesync_read_time = axgbe_timesync_read_time,
269 .timesync_write_time = axgbe_timesync_write_time,
270 .fw_version_get = axgbe_dev_fw_version_get,
273 static int axgbe_phy_reset(struct axgbe_port *pdata)
275 pdata->phy_link = -1;
276 pdata->phy_speed = SPEED_UNKNOWN;
277 return pdata->phy_if.phy_reset(pdata);
281 * Interrupt handler triggered by NIC for handling
282 * specific interrupt.
285 * Pointer to interrupt handle.
287 * The address of parameter (struct rte_eth_dev *) regsitered before.
293 axgbe_dev_interrupt_handler(void *param)
295 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
296 struct axgbe_port *pdata = dev->data->dev_private;
297 unsigned int dma_isr, dma_ch_isr;
299 pdata->phy_if.an_isr(pdata);
300 /*DMA related interrupts*/
301 dma_isr = AXGMAC_IOREAD(pdata, DMA_ISR);
302 PMD_DRV_LOG(DEBUG, "DMA_ISR=%#010x\n", dma_isr);
306 AXGMAC_DMA_IOREAD((struct axgbe_rx_queue *)
309 PMD_DRV_LOG(DEBUG, "DMA_CH0_ISR=%#010x\n", dma_ch_isr);
310 AXGMAC_DMA_IOWRITE((struct axgbe_rx_queue *)
312 DMA_CH_SR, dma_ch_isr);
315 /* Unmask interrupts since disabled after generation */
316 rte_intr_ack(pdata->pci_dev->intr_handle);
320 * Configure device link speed and setup link.
321 * It returns 0 on success.
324 axgbe_dev_configure(struct rte_eth_dev *dev)
326 struct axgbe_port *pdata = dev->data->dev_private;
327 /* Checksum offload to hardware */
328 pdata->rx_csum_enable = dev->data->dev_conf.rxmode.offloads &
329 RTE_ETH_RX_OFFLOAD_CHECKSUM;
334 axgbe_dev_rx_mq_config(struct rte_eth_dev *dev)
336 struct axgbe_port *pdata = dev->data->dev_private;
338 if (dev->data->dev_conf.rxmode.mq_mode == RTE_ETH_MQ_RX_RSS)
339 pdata->rss_enable = 1;
340 else if (dev->data->dev_conf.rxmode.mq_mode == RTE_ETH_MQ_RX_NONE)
341 pdata->rss_enable = 0;
348 axgbe_dev_start(struct rte_eth_dev *dev)
350 struct axgbe_port *pdata = dev->data->dev_private;
352 struct rte_eth_dev_data *dev_data = dev->data;
353 uint16_t max_pkt_len;
355 dev->dev_ops = &axgbe_eth_dev_ops;
357 PMD_INIT_FUNC_TRACE();
360 ret = axgbe_dev_rx_mq_config(dev);
362 PMD_DRV_LOG(ERR, "Unable to config RX MQ\n");
365 ret = axgbe_phy_reset(pdata);
367 PMD_DRV_LOG(ERR, "phy reset failed\n");
370 ret = pdata->hw_if.init(pdata);
372 PMD_DRV_LOG(ERR, "dev_init failed\n");
376 /* enable uio/vfio intr/eventfd mapping */
377 rte_intr_enable(pdata->pci_dev->intr_handle);
380 pdata->phy_if.phy_start(pdata);
381 axgbe_dev_enable_tx(dev);
382 axgbe_dev_enable_rx(dev);
384 rte_bit_relaxed_clear32(AXGBE_STOPPED, &pdata->dev_state);
385 rte_bit_relaxed_clear32(AXGBE_DOWN, &pdata->dev_state);
387 max_pkt_len = dev_data->mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN;
388 if ((dev_data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_SCATTER) ||
389 max_pkt_len > pdata->rx_buf_size)
390 dev_data->scattered_rx = 1;
392 /* Scatter Rx handling */
393 if (dev_data->scattered_rx)
394 dev->rx_pkt_burst = ð_axgbe_recv_scattered_pkts;
396 dev->rx_pkt_burst = &axgbe_recv_pkts;
401 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
403 axgbe_dev_stop(struct rte_eth_dev *dev)
405 struct axgbe_port *pdata = dev->data->dev_private;
407 PMD_INIT_FUNC_TRACE();
409 rte_intr_disable(pdata->pci_dev->intr_handle);
411 if (rte_bit_relaxed_get32(AXGBE_STOPPED, &pdata->dev_state))
414 rte_bit_relaxed_set32(AXGBE_STOPPED, &pdata->dev_state);
415 axgbe_dev_disable_tx(dev);
416 axgbe_dev_disable_rx(dev);
418 pdata->phy_if.phy_stop(pdata);
419 pdata->hw_if.exit(pdata);
420 memset(&dev->data->dev_link, 0, sizeof(struct rte_eth_link));
421 rte_bit_relaxed_set32(AXGBE_DOWN, &pdata->dev_state);
427 axgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
429 struct axgbe_port *pdata = dev->data->dev_private;
431 PMD_INIT_FUNC_TRACE();
433 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, 1);
439 axgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
441 struct axgbe_port *pdata = dev->data->dev_private;
443 PMD_INIT_FUNC_TRACE();
445 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, 0);
451 axgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
453 struct axgbe_port *pdata = dev->data->dev_private;
455 PMD_INIT_FUNC_TRACE();
457 if (AXGMAC_IOREAD_BITS(pdata, MAC_PFR, PM))
459 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, 1);
465 axgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
467 struct axgbe_port *pdata = dev->data->dev_private;
469 PMD_INIT_FUNC_TRACE();
471 if (!AXGMAC_IOREAD_BITS(pdata, MAC_PFR, PM))
473 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, 0);
479 axgbe_dev_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr)
481 struct axgbe_port *pdata = dev->data->dev_private;
483 /* Set Default MAC Addr */
484 axgbe_set_mac_addn_addr(pdata, (u8 *)mac_addr, 0);
490 axgbe_dev_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
491 uint32_t index, uint32_t pool __rte_unused)
493 struct axgbe_port *pdata = dev->data->dev_private;
494 struct axgbe_hw_features *hw_feat = &pdata->hw_feat;
496 if (index > hw_feat->addn_mac) {
497 PMD_DRV_LOG(ERR, "Invalid Index %d\n", index);
500 axgbe_set_mac_addn_addr(pdata, (u8 *)mac_addr, index);
505 axgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
506 struct rte_eth_rss_reta_entry64 *reta_conf,
509 struct axgbe_port *pdata = dev->data->dev_private;
510 unsigned int i, idx, shift;
513 if (!pdata->rss_enable) {
514 PMD_DRV_LOG(ERR, "RSS not enabled\n");
518 if (reta_size == 0 || reta_size > AXGBE_RSS_MAX_TABLE_SIZE) {
519 PMD_DRV_LOG(ERR, "reta_size %d is not supported\n", reta_size);
523 for (i = 0; i < reta_size; i++) {
524 idx = i / RTE_ETH_RETA_GROUP_SIZE;
525 shift = i % RTE_ETH_RETA_GROUP_SIZE;
526 if ((reta_conf[idx].mask & (1ULL << shift)) == 0)
528 pdata->rss_table[i] = reta_conf[idx].reta[shift];
531 /* Program the lookup table */
532 ret = axgbe_write_rss_lookup_table(pdata);
537 axgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
538 struct rte_eth_rss_reta_entry64 *reta_conf,
541 struct axgbe_port *pdata = dev->data->dev_private;
542 unsigned int i, idx, shift;
544 if (!pdata->rss_enable) {
545 PMD_DRV_LOG(ERR, "RSS not enabled\n");
549 if (reta_size == 0 || reta_size > AXGBE_RSS_MAX_TABLE_SIZE) {
550 PMD_DRV_LOG(ERR, "reta_size %d is not supported\n", reta_size);
554 for (i = 0; i < reta_size; i++) {
555 idx = i / RTE_ETH_RETA_GROUP_SIZE;
556 shift = i % RTE_ETH_RETA_GROUP_SIZE;
557 if ((reta_conf[idx].mask & (1ULL << shift)) == 0)
559 reta_conf[idx].reta[shift] = pdata->rss_table[i];
565 axgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
566 struct rte_eth_rss_conf *rss_conf)
568 struct axgbe_port *pdata = dev->data->dev_private;
571 if (!pdata->rss_enable) {
572 PMD_DRV_LOG(ERR, "RSS not enabled\n");
576 if (rss_conf == NULL) {
577 PMD_DRV_LOG(ERR, "rss_conf value isn't valid\n");
581 if (rss_conf->rss_key != NULL &&
582 rss_conf->rss_key_len == AXGBE_RSS_HASH_KEY_SIZE) {
583 rte_memcpy(pdata->rss_key, rss_conf->rss_key,
584 AXGBE_RSS_HASH_KEY_SIZE);
585 /* Program the hash key */
586 ret = axgbe_write_rss_hash_key(pdata);
591 pdata->rss_hf = rss_conf->rss_hf & AXGBE_RSS_OFFLOAD;
593 if (pdata->rss_hf & (RTE_ETH_RSS_IPV4 | RTE_ETH_RSS_IPV6))
594 AXGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, IP2TE, 1);
596 (RTE_ETH_RSS_NONFRAG_IPV4_TCP | RTE_ETH_RSS_NONFRAG_IPV6_TCP))
597 AXGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, TCP4TE, 1);
599 (RTE_ETH_RSS_NONFRAG_IPV4_UDP | RTE_ETH_RSS_NONFRAG_IPV6_UDP))
600 AXGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, UDP4TE, 1);
602 /* Set the RSS options */
603 AXGMAC_IOWRITE(pdata, MAC_RSSCR, pdata->rss_options);
609 axgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
610 struct rte_eth_rss_conf *rss_conf)
612 struct axgbe_port *pdata = dev->data->dev_private;
614 if (!pdata->rss_enable) {
615 PMD_DRV_LOG(ERR, "RSS not enabled\n");
619 if (rss_conf == NULL) {
620 PMD_DRV_LOG(ERR, "rss_conf value isn't valid\n");
624 if (rss_conf->rss_key != NULL &&
625 rss_conf->rss_key_len >= AXGBE_RSS_HASH_KEY_SIZE) {
626 rte_memcpy(rss_conf->rss_key, pdata->rss_key,
627 AXGBE_RSS_HASH_KEY_SIZE);
629 rss_conf->rss_key_len = AXGBE_RSS_HASH_KEY_SIZE;
630 rss_conf->rss_hf = pdata->rss_hf;
635 axgbe_dev_reset(struct rte_eth_dev *dev)
639 ret = axgbe_dev_close(dev);
643 ret = eth_axgbe_dev_init(dev);
649 axgbe_dev_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)
651 struct axgbe_port *pdata = dev->data->dev_private;
652 struct axgbe_hw_features *hw_feat = &pdata->hw_feat;
654 if (index > hw_feat->addn_mac) {
655 PMD_DRV_LOG(ERR, "Invalid Index %d\n", index);
658 axgbe_set_mac_addn_addr(pdata, NULL, index);
662 axgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
663 struct rte_ether_addr *mc_addr_set,
666 struct axgbe_port *pdata = dev->data->dev_private;
667 struct axgbe_hw_features *hw_feat = &pdata->hw_feat;
668 uint32_t index = 1; /* 0 is always default mac */
671 if (nb_mc_addr > hw_feat->addn_mac) {
672 PMD_DRV_LOG(ERR, "Invalid Index %d\n", nb_mc_addr);
676 /* clear unicast addresses */
677 for (i = 1; i < hw_feat->addn_mac; i++) {
678 if (rte_is_zero_ether_addr(&dev->data->mac_addrs[i]))
680 memset(&dev->data->mac_addrs[i], 0,
681 sizeof(struct rte_ether_addr));
685 axgbe_set_mac_addn_addr(pdata, (u8 *)mc_addr_set++, index++);
691 axgbe_dev_uc_hash_table_set(struct rte_eth_dev *dev,
692 struct rte_ether_addr *mac_addr, uint8_t add)
694 struct axgbe_port *pdata = dev->data->dev_private;
695 struct axgbe_hw_features *hw_feat = &pdata->hw_feat;
697 if (!hw_feat->hash_table_size) {
698 PMD_DRV_LOG(ERR, "MAC Hash Table not supported\n");
702 axgbe_set_mac_hash_table(pdata, (u8 *)mac_addr, add);
704 if (pdata->uc_hash_mac_addr > 0) {
705 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1);
706 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1);
708 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 0);
709 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 0);
715 axgbe_dev_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t add)
717 struct axgbe_port *pdata = dev->data->dev_private;
718 struct axgbe_hw_features *hw_feat = &pdata->hw_feat;
721 if (!hw_feat->hash_table_size) {
722 PMD_DRV_LOG(ERR, "MAC Hash Table not supported\n");
726 for (index = 0; index < pdata->hash_table_count; index++) {
728 pdata->uc_hash_table[index] = ~0;
730 pdata->uc_hash_table[index] = 0;
732 PMD_DRV_LOG(DEBUG, "%s MAC hash table at Index %#x\n",
733 add ? "set" : "clear", index);
735 AXGMAC_IOWRITE(pdata, MAC_HTR(index),
736 pdata->uc_hash_table[index]);
740 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1);
741 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1);
743 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 0);
744 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 0);
749 /* return 0 means link status changed, -1 means not changed */
751 axgbe_dev_link_update(struct rte_eth_dev *dev,
752 int wait_to_complete __rte_unused)
754 struct axgbe_port *pdata = dev->data->dev_private;
755 struct rte_eth_link link;
758 PMD_INIT_FUNC_TRACE();
761 pdata->phy_if.phy_status(pdata);
763 memset(&link, 0, sizeof(struct rte_eth_link));
764 link.link_duplex = pdata->phy.duplex;
765 link.link_status = pdata->phy_link;
766 link.link_speed = pdata->phy_speed;
767 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
768 RTE_ETH_LINK_SPEED_FIXED);
769 ret = rte_eth_linkstatus_set(dev, &link);
771 PMD_DRV_LOG(ERR, "No change in link status\n");
777 axgbe_dev_get_regs(struct rte_eth_dev *dev, struct rte_dev_reg_info *regs)
779 struct axgbe_port *pdata = dev->data->dev_private;
781 if (regs->data == NULL) {
782 regs->length = axgbe_regs_get_count(pdata);
783 regs->width = sizeof(uint32_t);
787 /* Only full register dump is supported */
789 regs->length != (uint32_t)axgbe_regs_get_count(pdata))
792 regs->version = pdata->pci_dev->id.vendor_id << 16 |
793 pdata->pci_dev->id.device_id;
794 axgbe_regs_dump(pdata, regs->data);
797 static void axgbe_read_mmc_stats(struct axgbe_port *pdata)
799 struct axgbe_mmc_stats *stats = &pdata->mmc_stats;
801 /* Freeze counters */
802 AXGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 1);
805 stats->txoctetcount_gb +=
806 AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_GB_LO);
807 stats->txoctetcount_gb +=
808 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_GB_HI) << 32);
810 stats->txframecount_gb +=
811 AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_GB_LO);
812 stats->txframecount_gb +=
813 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_GB_HI) << 32);
815 stats->txbroadcastframes_g +=
816 AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_G_LO);
817 stats->txbroadcastframes_g +=
818 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_G_HI) << 32);
820 stats->txmulticastframes_g +=
821 AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_G_LO);
822 stats->txmulticastframes_g +=
823 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_G_HI) << 32);
825 stats->tx64octets_gb +=
826 AXGMAC_IOREAD(pdata, MMC_TX64OCTETS_GB_LO);
827 stats->tx64octets_gb +=
828 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX64OCTETS_GB_HI) << 32);
830 stats->tx65to127octets_gb +=
831 AXGMAC_IOREAD(pdata, MMC_TX65TO127OCTETS_GB_LO);
832 stats->tx65to127octets_gb +=
833 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX65TO127OCTETS_GB_HI) << 32);
835 stats->tx128to255octets_gb +=
836 AXGMAC_IOREAD(pdata, MMC_TX128TO255OCTETS_GB_LO);
837 stats->tx128to255octets_gb +=
838 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX128TO255OCTETS_GB_HI) << 32);
840 stats->tx256to511octets_gb +=
841 AXGMAC_IOREAD(pdata, MMC_TX256TO511OCTETS_GB_LO);
842 stats->tx256to511octets_gb +=
843 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX256TO511OCTETS_GB_HI) << 32);
845 stats->tx512to1023octets_gb +=
846 AXGMAC_IOREAD(pdata, MMC_TX512TO1023OCTETS_GB_LO);
847 stats->tx512to1023octets_gb +=
848 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX512TO1023OCTETS_GB_HI) << 32);
850 stats->tx1024tomaxoctets_gb +=
851 AXGMAC_IOREAD(pdata, MMC_TX1024TOMAXOCTETS_GB_LO);
852 stats->tx1024tomaxoctets_gb +=
853 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX1024TOMAXOCTETS_GB_HI) << 32);
855 stats->txunicastframes_gb +=
856 AXGMAC_IOREAD(pdata, MMC_TXUNICASTFRAMES_GB_LO);
857 stats->txunicastframes_gb +=
858 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXUNICASTFRAMES_GB_HI) << 32);
860 stats->txmulticastframes_gb +=
861 AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_GB_LO);
862 stats->txmulticastframes_gb +=
863 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_GB_HI) << 32);
865 stats->txbroadcastframes_g +=
866 AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_GB_LO);
867 stats->txbroadcastframes_g +=
868 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_GB_HI) << 32);
870 stats->txunderflowerror +=
871 AXGMAC_IOREAD(pdata, MMC_TXUNDERFLOWERROR_LO);
872 stats->txunderflowerror +=
873 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXUNDERFLOWERROR_HI) << 32);
875 stats->txoctetcount_g +=
876 AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_G_LO);
877 stats->txoctetcount_g +=
878 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_G_HI) << 32);
880 stats->txframecount_g +=
881 AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_G_LO);
882 stats->txframecount_g +=
883 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_G_HI) << 32);
885 stats->txpauseframes +=
886 AXGMAC_IOREAD(pdata, MMC_TXPAUSEFRAMES_LO);
887 stats->txpauseframes +=
888 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXPAUSEFRAMES_HI) << 32);
890 stats->txvlanframes_g +=
891 AXGMAC_IOREAD(pdata, MMC_TXVLANFRAMES_G_LO);
892 stats->txvlanframes_g +=
893 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXVLANFRAMES_G_HI) << 32);
896 stats->rxframecount_gb +=
897 AXGMAC_IOREAD(pdata, MMC_RXFRAMECOUNT_GB_LO);
898 stats->rxframecount_gb +=
899 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXFRAMECOUNT_GB_HI) << 32);
901 stats->rxoctetcount_gb +=
902 AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_GB_LO);
903 stats->rxoctetcount_gb +=
904 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_GB_HI) << 32);
906 stats->rxoctetcount_g +=
907 AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_G_LO);
908 stats->rxoctetcount_g +=
909 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_G_HI) << 32);
911 stats->rxbroadcastframes_g +=
912 AXGMAC_IOREAD(pdata, MMC_RXBROADCASTFRAMES_G_LO);
913 stats->rxbroadcastframes_g +=
914 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXBROADCASTFRAMES_G_HI) << 32);
916 stats->rxmulticastframes_g +=
917 AXGMAC_IOREAD(pdata, MMC_RXMULTICASTFRAMES_G_LO);
918 stats->rxmulticastframes_g +=
919 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXMULTICASTFRAMES_G_HI) << 32);
922 AXGMAC_IOREAD(pdata, MMC_RXCRCERROR_LO);
924 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXCRCERROR_HI) << 32);
926 stats->rxrunterror +=
927 AXGMAC_IOREAD(pdata, MMC_RXRUNTERROR);
929 stats->rxjabbererror +=
930 AXGMAC_IOREAD(pdata, MMC_RXJABBERERROR);
932 stats->rxundersize_g +=
933 AXGMAC_IOREAD(pdata, MMC_RXUNDERSIZE_G);
935 stats->rxoversize_g +=
936 AXGMAC_IOREAD(pdata, MMC_RXOVERSIZE_G);
938 stats->rx64octets_gb +=
939 AXGMAC_IOREAD(pdata, MMC_RX64OCTETS_GB_LO);
940 stats->rx64octets_gb +=
941 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX64OCTETS_GB_HI) << 32);
943 stats->rx65to127octets_gb +=
944 AXGMAC_IOREAD(pdata, MMC_RX65TO127OCTETS_GB_LO);
945 stats->rx65to127octets_gb +=
946 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX65TO127OCTETS_GB_HI) << 32);
948 stats->rx128to255octets_gb +=
949 AXGMAC_IOREAD(pdata, MMC_RX128TO255OCTETS_GB_LO);
950 stats->rx128to255octets_gb +=
951 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX128TO255OCTETS_GB_HI) << 32);
953 stats->rx256to511octets_gb +=
954 AXGMAC_IOREAD(pdata, MMC_RX256TO511OCTETS_GB_LO);
955 stats->rx256to511octets_gb +=
956 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX256TO511OCTETS_GB_HI) << 32);
958 stats->rx512to1023octets_gb +=
959 AXGMAC_IOREAD(pdata, MMC_RX512TO1023OCTETS_GB_LO);
960 stats->rx512to1023octets_gb +=
961 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX512TO1023OCTETS_GB_HI) << 32);
963 stats->rx1024tomaxoctets_gb +=
964 AXGMAC_IOREAD(pdata, MMC_RX1024TOMAXOCTETS_GB_LO);
965 stats->rx1024tomaxoctets_gb +=
966 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX1024TOMAXOCTETS_GB_HI) << 32);
968 stats->rxunicastframes_g +=
969 AXGMAC_IOREAD(pdata, MMC_RXUNICASTFRAMES_G_LO);
970 stats->rxunicastframes_g +=
971 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXUNICASTFRAMES_G_HI) << 32);
973 stats->rxlengtherror +=
974 AXGMAC_IOREAD(pdata, MMC_RXLENGTHERROR_LO);
975 stats->rxlengtherror +=
976 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXLENGTHERROR_HI) << 32);
978 stats->rxoutofrangetype +=
979 AXGMAC_IOREAD(pdata, MMC_RXOUTOFRANGETYPE_LO);
980 stats->rxoutofrangetype +=
981 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXOUTOFRANGETYPE_HI) << 32);
983 stats->rxpauseframes +=
984 AXGMAC_IOREAD(pdata, MMC_RXPAUSEFRAMES_LO);
985 stats->rxpauseframes +=
986 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXPAUSEFRAMES_HI) << 32);
988 stats->rxfifooverflow +=
989 AXGMAC_IOREAD(pdata, MMC_RXFIFOOVERFLOW_LO);
990 stats->rxfifooverflow +=
991 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXFIFOOVERFLOW_HI) << 32);
993 stats->rxvlanframes_gb +=
994 AXGMAC_IOREAD(pdata, MMC_RXVLANFRAMES_GB_LO);
995 stats->rxvlanframes_gb +=
996 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXVLANFRAMES_GB_HI) << 32);
998 stats->rxwatchdogerror +=
999 AXGMAC_IOREAD(pdata, MMC_RXWATCHDOGERROR);
1001 /* Un-freeze counters */
1002 AXGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 0);
1006 axgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats,
1009 struct axgbe_port *pdata = dev->data->dev_private;
1015 axgbe_read_mmc_stats(pdata);
1017 for (i = 0; i < n && i < AXGBE_XSTATS_COUNT; i++) {
1019 stats[i].value = *(u64 *)((uint8_t *)&pdata->mmc_stats +
1020 axgbe_xstats_strings[i].offset);
1027 axgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1028 struct rte_eth_xstat_name *xstats_names,
1033 if (n >= AXGBE_XSTATS_COUNT && xstats_names) {
1034 for (i = 0; i < AXGBE_XSTATS_COUNT; ++i) {
1035 snprintf(xstats_names[i].name,
1036 RTE_ETH_XSTATS_NAME_SIZE, "%s",
1037 axgbe_xstats_strings[i].name);
1041 return AXGBE_XSTATS_COUNT;
1045 axgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1046 uint64_t *values, unsigned int n)
1049 uint64_t values_copy[AXGBE_XSTATS_COUNT];
1052 struct axgbe_port *pdata = dev->data->dev_private;
1054 if (n < AXGBE_XSTATS_COUNT)
1055 return AXGBE_XSTATS_COUNT;
1057 axgbe_read_mmc_stats(pdata);
1059 for (i = 0; i < AXGBE_XSTATS_COUNT; i++) {
1060 values[i] = *(u64 *)((uint8_t *)&pdata->mmc_stats +
1061 axgbe_xstats_strings[i].offset);
1067 axgbe_dev_xstats_get_by_id(dev, NULL, values_copy, AXGBE_XSTATS_COUNT);
1069 for (i = 0; i < n; i++) {
1070 if (ids[i] >= AXGBE_XSTATS_COUNT) {
1071 PMD_DRV_LOG(ERR, "id value isn't valid\n");
1074 values[i] = values_copy[ids[i]];
1080 axgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev,
1081 const uint64_t *ids,
1082 struct rte_eth_xstat_name *xstats_names,
1085 struct rte_eth_xstat_name xstats_names_copy[AXGBE_XSTATS_COUNT];
1089 return axgbe_dev_xstats_get_names(dev, xstats_names, size);
1091 axgbe_dev_xstats_get_names(dev, xstats_names_copy, size);
1093 for (i = 0; i < size; i++) {
1094 if (ids[i] >= AXGBE_XSTATS_COUNT) {
1095 PMD_DRV_LOG(ERR, "id value isn't valid\n");
1098 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
1104 axgbe_dev_xstats_reset(struct rte_eth_dev *dev)
1106 struct axgbe_port *pdata = dev->data->dev_private;
1107 struct axgbe_mmc_stats *stats = &pdata->mmc_stats;
1109 /* MMC registers are configured for reset on read */
1110 axgbe_read_mmc_stats(pdata);
1113 memset(stats, 0, sizeof(*stats));
1119 axgbe_dev_stats_get(struct rte_eth_dev *dev,
1120 struct rte_eth_stats *stats)
1122 struct axgbe_rx_queue *rxq;
1123 struct axgbe_tx_queue *txq;
1124 struct axgbe_port *pdata = dev->data->dev_private;
1125 struct axgbe_mmc_stats *mmc_stats = &pdata->mmc_stats;
1128 axgbe_read_mmc_stats(pdata);
1130 stats->imissed = mmc_stats->rxfifooverflow;
1132 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1133 rxq = dev->data->rx_queues[i];
1135 stats->q_ipackets[i] = rxq->pkts;
1136 stats->ipackets += rxq->pkts;
1137 stats->q_ibytes[i] = rxq->bytes;
1138 stats->ibytes += rxq->bytes;
1139 stats->rx_nombuf += rxq->rx_mbuf_alloc_failed;
1140 stats->q_errors[i] = rxq->errors
1141 + rxq->rx_mbuf_alloc_failed;
1142 stats->ierrors += rxq->errors;
1144 PMD_DRV_LOG(DEBUG, "Rx queue not setup for port %d\n",
1145 dev->data->port_id);
1149 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1150 txq = dev->data->tx_queues[i];
1152 stats->q_opackets[i] = txq->pkts;
1153 stats->opackets += txq->pkts;
1154 stats->q_obytes[i] = txq->bytes;
1155 stats->obytes += txq->bytes;
1156 stats->oerrors += txq->errors;
1158 PMD_DRV_LOG(DEBUG, "Tx queue not setup for port %d\n",
1159 dev->data->port_id);
1167 axgbe_dev_stats_reset(struct rte_eth_dev *dev)
1169 struct axgbe_rx_queue *rxq;
1170 struct axgbe_tx_queue *txq;
1173 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1174 rxq = dev->data->rx_queues[i];
1179 rxq->rx_mbuf_alloc_failed = 0;
1181 PMD_DRV_LOG(DEBUG, "Rx queue not setup for port %d\n",
1182 dev->data->port_id);
1185 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1186 txq = dev->data->tx_queues[i];
1192 PMD_DRV_LOG(DEBUG, "Tx queue not setup for port %d\n",
1193 dev->data->port_id);
1201 axgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1203 struct axgbe_port *pdata = dev->data->dev_private;
1205 dev_info->max_rx_queues = pdata->rx_ring_count;
1206 dev_info->max_tx_queues = pdata->tx_ring_count;
1207 dev_info->min_rx_bufsize = AXGBE_RX_MIN_BUF_SIZE;
1208 dev_info->max_rx_pktlen = AXGBE_RX_MAX_BUF_SIZE;
1209 dev_info->max_mac_addrs = pdata->hw_feat.addn_mac + 1;
1210 dev_info->max_hash_mac_addrs = pdata->hw_feat.hash_table_size;
1211 dev_info->speed_capa = RTE_ETH_LINK_SPEED_10G;
1213 dev_info->rx_offload_capa =
1214 RTE_ETH_RX_OFFLOAD_VLAN_STRIP |
1215 RTE_ETH_RX_OFFLOAD_VLAN_FILTER |
1216 RTE_ETH_RX_OFFLOAD_VLAN_EXTEND |
1217 RTE_ETH_RX_OFFLOAD_IPV4_CKSUM |
1218 RTE_ETH_RX_OFFLOAD_UDP_CKSUM |
1219 RTE_ETH_RX_OFFLOAD_TCP_CKSUM |
1220 RTE_ETH_RX_OFFLOAD_SCATTER |
1221 RTE_ETH_RX_OFFLOAD_KEEP_CRC;
1223 dev_info->tx_offload_capa =
1224 RTE_ETH_TX_OFFLOAD_VLAN_INSERT |
1225 RTE_ETH_TX_OFFLOAD_QINQ_INSERT |
1226 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |
1227 RTE_ETH_TX_OFFLOAD_UDP_CKSUM |
1228 RTE_ETH_TX_OFFLOAD_TCP_CKSUM;
1230 if (pdata->hw_feat.rss) {
1231 dev_info->flow_type_rss_offloads = AXGBE_RSS_OFFLOAD;
1232 dev_info->reta_size = pdata->hw_feat.hash_table_size;
1233 dev_info->hash_key_size = AXGBE_RSS_HASH_KEY_SIZE;
1236 dev_info->rx_desc_lim = rx_desc_lim;
1237 dev_info->tx_desc_lim = tx_desc_lim;
1239 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1240 .rx_free_thresh = AXGBE_RX_FREE_THRESH,
1243 dev_info->default_txconf = (struct rte_eth_txconf) {
1244 .tx_free_thresh = AXGBE_TX_FREE_THRESH,
1251 axgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1253 struct axgbe_port *pdata = dev->data->dev_private;
1254 struct xgbe_fc_info fc = pdata->fc;
1255 unsigned int reg, reg_val = 0;
1258 reg_val = AXGMAC_IOREAD(pdata, reg);
1259 fc.low_water[0] = AXGMAC_MTL_IOREAD_BITS(pdata, 0, MTL_Q_RQFCR, RFA);
1260 fc.high_water[0] = AXGMAC_MTL_IOREAD_BITS(pdata, 0, MTL_Q_RQFCR, RFD);
1261 fc.pause_time[0] = AXGMAC_GET_BITS(reg_val, MAC_Q0TFCR, PT);
1262 fc.autoneg = pdata->pause_autoneg;
1264 if (pdata->rx_pause && pdata->tx_pause)
1265 fc.mode = RTE_ETH_FC_FULL;
1266 else if (pdata->rx_pause)
1267 fc.mode = RTE_ETH_FC_RX_PAUSE;
1268 else if (pdata->tx_pause)
1269 fc.mode = RTE_ETH_FC_TX_PAUSE;
1271 fc.mode = RTE_ETH_FC_NONE;
1273 fc_conf->high_water = (1024 + (fc.low_water[0] << 9)) / 1024;
1274 fc_conf->low_water = (1024 + (fc.high_water[0] << 9)) / 1024;
1275 fc_conf->pause_time = fc.pause_time[0];
1276 fc_conf->send_xon = fc.send_xon;
1277 fc_conf->mode = fc.mode;
1283 axgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1285 struct axgbe_port *pdata = dev->data->dev_private;
1286 struct xgbe_fc_info fc = pdata->fc;
1287 unsigned int reg, reg_val = 0;
1290 pdata->pause_autoneg = fc_conf->autoneg;
1291 pdata->phy.pause_autoneg = pdata->pause_autoneg;
1292 fc.send_xon = fc_conf->send_xon;
1293 AXGMAC_MTL_IOWRITE_BITS(pdata, 0, MTL_Q_RQFCR, RFA,
1294 AXGMAC_FLOW_CONTROL_VALUE(1024 * fc_conf->high_water));
1295 AXGMAC_MTL_IOWRITE_BITS(pdata, 0, MTL_Q_RQFCR, RFD,
1296 AXGMAC_FLOW_CONTROL_VALUE(1024 * fc_conf->low_water));
1297 AXGMAC_SET_BITS(reg_val, MAC_Q0TFCR, PT, fc_conf->pause_time);
1298 AXGMAC_IOWRITE(pdata, reg, reg_val);
1299 fc.mode = fc_conf->mode;
1301 if (fc.mode == RTE_ETH_FC_FULL) {
1302 pdata->tx_pause = 1;
1303 pdata->rx_pause = 1;
1304 } else if (fc.mode == RTE_ETH_FC_RX_PAUSE) {
1305 pdata->tx_pause = 0;
1306 pdata->rx_pause = 1;
1307 } else if (fc.mode == RTE_ETH_FC_TX_PAUSE) {
1308 pdata->tx_pause = 1;
1309 pdata->rx_pause = 0;
1311 pdata->tx_pause = 0;
1312 pdata->rx_pause = 0;
1315 if (pdata->tx_pause != (unsigned int)pdata->phy.tx_pause)
1316 pdata->hw_if.config_tx_flow_control(pdata);
1318 if (pdata->rx_pause != (unsigned int)pdata->phy.rx_pause)
1319 pdata->hw_if.config_rx_flow_control(pdata);
1321 pdata->hw_if.config_flow_control(pdata);
1322 pdata->phy.tx_pause = pdata->tx_pause;
1323 pdata->phy.rx_pause = pdata->rx_pause;
1329 axgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
1330 struct rte_eth_pfc_conf *pfc_conf)
1332 struct axgbe_port *pdata = dev->data->dev_private;
1333 struct xgbe_fc_info fc = pdata->fc;
1336 tc_num = pdata->pfc_map[pfc_conf->priority];
1338 if (pfc_conf->priority >= pdata->hw_feat.tc_cnt) {
1339 PMD_INIT_LOG(ERR, "Max supported traffic class: %d\n",
1340 pdata->hw_feat.tc_cnt);
1344 pdata->pause_autoneg = pfc_conf->fc.autoneg;
1345 pdata->phy.pause_autoneg = pdata->pause_autoneg;
1346 fc.send_xon = pfc_conf->fc.send_xon;
1347 AXGMAC_MTL_IOWRITE_BITS(pdata, tc_num, MTL_Q_RQFCR, RFA,
1348 AXGMAC_FLOW_CONTROL_VALUE(1024 * pfc_conf->fc.high_water));
1349 AXGMAC_MTL_IOWRITE_BITS(pdata, tc_num, MTL_Q_RQFCR, RFD,
1350 AXGMAC_FLOW_CONTROL_VALUE(1024 * pfc_conf->fc.low_water));
1354 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R,
1355 PSTC0, pfc_conf->fc.pause_time);
1358 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R,
1359 PSTC1, pfc_conf->fc.pause_time);
1362 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R,
1363 PSTC2, pfc_conf->fc.pause_time);
1366 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R,
1367 PSTC3, pfc_conf->fc.pause_time);
1370 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R,
1371 PSTC4, pfc_conf->fc.pause_time);
1374 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R,
1375 PSTC5, pfc_conf->fc.pause_time);
1378 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R,
1379 PSTC6, pfc_conf->fc.pause_time);
1382 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R,
1383 PSTC7, pfc_conf->fc.pause_time);
1387 fc.mode = pfc_conf->fc.mode;
1389 if (fc.mode == RTE_ETH_FC_FULL) {
1390 pdata->tx_pause = 1;
1391 pdata->rx_pause = 1;
1392 AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 1);
1393 } else if (fc.mode == RTE_ETH_FC_RX_PAUSE) {
1394 pdata->tx_pause = 0;
1395 pdata->rx_pause = 1;
1396 AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 1);
1397 } else if (fc.mode == RTE_ETH_FC_TX_PAUSE) {
1398 pdata->tx_pause = 1;
1399 pdata->rx_pause = 0;
1400 AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 0);
1402 pdata->tx_pause = 0;
1403 pdata->rx_pause = 0;
1404 AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 0);
1407 if (pdata->tx_pause != (unsigned int)pdata->phy.tx_pause)
1408 pdata->hw_if.config_tx_flow_control(pdata);
1410 if (pdata->rx_pause != (unsigned int)pdata->phy.rx_pause)
1411 pdata->hw_if.config_rx_flow_control(pdata);
1412 pdata->hw_if.config_flow_control(pdata);
1413 pdata->phy.tx_pause = pdata->tx_pause;
1414 pdata->phy.rx_pause = pdata->rx_pause;
1420 axgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1421 struct rte_eth_rxq_info *qinfo)
1423 struct axgbe_rx_queue *rxq;
1425 rxq = dev->data->rx_queues[queue_id];
1426 qinfo->mp = rxq->mb_pool;
1427 qinfo->scattered_rx = dev->data->scattered_rx;
1428 qinfo->nb_desc = rxq->nb_desc;
1429 qinfo->conf.rx_free_thresh = rxq->free_thresh;
1433 axgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1434 struct rte_eth_txq_info *qinfo)
1436 struct axgbe_tx_queue *txq;
1438 txq = dev->data->tx_queues[queue_id];
1439 qinfo->nb_desc = txq->nb_desc;
1440 qinfo->conf.tx_free_thresh = txq->free_thresh;
1443 axgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1445 static const uint32_t ptypes[] = {
1447 RTE_PTYPE_L2_ETHER_TIMESYNC,
1448 RTE_PTYPE_L2_ETHER_LLDP,
1449 RTE_PTYPE_L2_ETHER_ARP,
1450 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1451 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1454 RTE_PTYPE_L4_NONFRAG,
1458 RTE_PTYPE_TUNNEL_GRENAT,
1459 RTE_PTYPE_TUNNEL_IP,
1460 RTE_PTYPE_INNER_L2_ETHER,
1461 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1462 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1463 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1464 RTE_PTYPE_INNER_L4_FRAG,
1465 RTE_PTYPE_INNER_L4_ICMP,
1466 RTE_PTYPE_INNER_L4_NONFRAG,
1467 RTE_PTYPE_INNER_L4_SCTP,
1468 RTE_PTYPE_INNER_L4_TCP,
1469 RTE_PTYPE_INNER_L4_UDP,
1473 if (dev->rx_pkt_burst == axgbe_recv_pkts)
1478 static int axgb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1480 struct axgbe_port *pdata = dev->data->dev_private;
1483 /* mtu setting is forbidden if port is start */
1484 if (dev->data->dev_started) {
1485 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
1486 dev->data->port_id);
1489 val = mtu > RTE_ETHER_MTU ? 1 : 0;
1490 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, JE, val);
1496 axgbe_update_tstamp_time(struct axgbe_port *pdata,
1497 unsigned int sec, unsigned int nsec, int addsub)
1499 unsigned int count = 100;
1500 uint32_t sub_val = 0;
1501 uint32_t sub_val_sec = 0xFFFFFFFF;
1502 uint32_t sub_val_nsec = 0x3B9ACA00;
1506 sub_val = sub_val_sec - (sec - 1);
1510 AXGMAC_IOWRITE(pdata, MAC_STSUR, sub_val);
1511 sub_val = sub_val_nsec - nsec;
1512 AXGMAC_IOWRITE(pdata, MAC_STNUR, sub_val);
1513 AXGMAC_IOWRITE_BITS(pdata, MAC_STNUR, ADDSUB, 1);
1515 AXGMAC_IOWRITE(pdata, MAC_STSUR, sec);
1516 AXGMAC_IOWRITE_BITS(pdata, MAC_STNUR, ADDSUB, 0);
1517 AXGMAC_IOWRITE(pdata, MAC_STNUR, nsec);
1519 AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSUPDT, 1);
1520 /* Wait for time update to complete */
1521 while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSUPDT))
1525 static inline uint64_t
1526 div_u64_rem(uint64_t dividend, uint32_t divisor, uint32_t *remainder)
1528 *remainder = dividend % divisor;
1529 return dividend / divisor;
1532 static inline uint64_t
1533 div_u64(uint64_t dividend, uint32_t divisor)
1536 return div_u64_rem(dividend, divisor, &remainder);
1540 axgbe_adjfreq(struct axgbe_port *pdata, int64_t delta)
1543 uint32_t addend, diff;
1544 unsigned int neg_adjust = 0;
1550 adjust = (uint64_t)pdata->tstamp_addend;
1552 diff = (uint32_t)div_u64(adjust, 1000000000UL);
1553 addend = (neg_adjust) ? pdata->tstamp_addend - diff :
1554 pdata->tstamp_addend + diff;
1555 pdata->tstamp_addend = addend;
1556 axgbe_update_tstamp_addend(pdata, addend);
1561 axgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
1563 struct axgbe_port *pdata = dev->data->dev_private;
1564 struct timespec timestamp_delta;
1566 axgbe_adjfreq(pdata, delta);
1567 pdata->systime_tc.nsec += delta;
1571 timestamp_delta = rte_ns_to_timespec(delta);
1572 axgbe_update_tstamp_time(pdata, timestamp_delta.tv_sec,
1573 timestamp_delta.tv_nsec, 1);
1575 timestamp_delta = rte_ns_to_timespec(delta);
1576 axgbe_update_tstamp_time(pdata, timestamp_delta.tv_sec,
1577 timestamp_delta.tv_nsec, 0);
1583 axgbe_timesync_read_time(struct rte_eth_dev *dev,
1584 struct timespec *timestamp)
1587 struct axgbe_port *pdata = dev->data->dev_private;
1589 nsec = AXGMAC_IOREAD(pdata, MAC_STSR);
1590 nsec *= NSEC_PER_SEC;
1591 nsec += AXGMAC_IOREAD(pdata, MAC_STNR);
1592 *timestamp = rte_ns_to_timespec(nsec);
1596 axgbe_timesync_write_time(struct rte_eth_dev *dev,
1597 const struct timespec *timestamp)
1599 unsigned int count = 100;
1600 struct axgbe_port *pdata = dev->data->dev_private;
1602 AXGMAC_IOWRITE(pdata, MAC_STSUR, timestamp->tv_sec);
1603 AXGMAC_IOWRITE(pdata, MAC_STNUR, timestamp->tv_nsec);
1604 AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSUPDT, 1);
1605 /* Wait for time update to complete */
1606 while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSUPDT))
1609 PMD_DRV_LOG(ERR, "Timed out update timestamp\n");
1614 axgbe_update_tstamp_addend(struct axgbe_port *pdata,
1617 unsigned int count = 100;
1619 AXGMAC_IOWRITE(pdata, MAC_TSAR, addend);
1620 AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 1);
1622 /* Wait for addend update to complete */
1623 while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSADDREG))
1626 PMD_DRV_LOG(ERR, "Timed out updating timestamp addend register\n");
1630 axgbe_set_tstamp_time(struct axgbe_port *pdata, unsigned int sec,
1633 unsigned int count = 100;
1635 /*System Time Sec Update*/
1636 AXGMAC_IOWRITE(pdata, MAC_STSUR, sec);
1637 /*System Time nanoSec Update*/
1638 AXGMAC_IOWRITE(pdata, MAC_STNUR, nsec);
1639 /*Initialize Timestamp*/
1640 AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSINIT, 1);
1642 /* Wait for time update to complete */
1643 while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSINIT))
1646 PMD_DRV_LOG(ERR, "Timed out initializing timestamp\n");
1650 axgbe_timesync_enable(struct rte_eth_dev *dev)
1652 struct axgbe_port *pdata = dev->data->dev_private;
1653 unsigned int mac_tscr = 0;
1655 struct timespec timestamp;
1658 /* Set one nano-second accuracy */
1659 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCTRLSSR, 1);
1661 /* Set fine timestamp update */
1662 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 1);
1664 /* Overwrite earlier timestamps */
1665 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TXTSSTSM, 1);
1667 AXGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr);
1669 /* Enabling processing of ptp over eth pkt */
1670 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1671 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1672 /* Enable timestamp for all pkts*/
1673 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 1);
1675 /* enabling timestamp */
1676 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1677 AXGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr);
1679 /* Exit if timestamping is not enabled */
1680 if (!AXGMAC_GET_BITS(mac_tscr, MAC_TSCR, TSENA)) {
1681 PMD_DRV_LOG(ERR, "Exiting as timestamp is not enabled\n");
1685 /* Sub-second Increment Value*/
1686 AXGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SSINC, AXGBE_TSTAMP_SSINC);
1687 /* Sub-nanosecond Increment Value */
1688 AXGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SNSINC, AXGBE_TSTAMP_SNSINC);
1690 pdata->ptpclk_rate = AXGBE_V2_PTP_CLOCK_FREQ;
1691 dividend = 50000000;
1693 pdata->tstamp_addend = div_u64(dividend, pdata->ptpclk_rate);
1695 axgbe_update_tstamp_addend(pdata, pdata->tstamp_addend);
1696 axgbe_set_tstamp_time(pdata, 0, 0);
1698 /* Initialize the timecounter */
1699 memset(&pdata->systime_tc, 0, sizeof(struct rte_timecounter));
1701 pdata->systime_tc.cc_mask = AXGBE_CYCLECOUNTER_MASK;
1702 pdata->systime_tc.cc_shift = 0;
1703 pdata->systime_tc.nsec_mask = 0;
1705 PMD_DRV_LOG(DEBUG, "Initializing system time counter with realtime\n");
1707 /* Updating the counter once with clock real time */
1708 clock_gettime(CLOCK_REALTIME, ×tamp);
1709 nsec = rte_timespec_to_ns(×tamp);
1710 nsec = rte_timecounter_update(&pdata->systime_tc, nsec);
1711 axgbe_set_tstamp_time(pdata, timestamp.tv_sec, timestamp.tv_nsec);
1716 axgbe_timesync_disable(struct rte_eth_dev *dev)
1718 struct axgbe_port *pdata = dev->data->dev_private;
1719 unsigned int mac_tscr = 0;
1721 /*disable timestamp for all pkts*/
1722 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 0);
1723 /*disable the addened register*/
1724 AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 0);
1725 /* disable timestamp update */
1726 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 0);
1727 /*disable time stamp*/
1728 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 0);
1733 axgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
1734 struct timespec *timestamp, uint32_t flags)
1737 volatile union axgbe_rx_desc *desc;
1739 struct axgbe_rx_queue *rxq = *dev->data->rx_queues;
1741 idx = AXGBE_GET_DESC_IDX(rxq, rxq->cur);
1742 desc = &rxq->desc[idx];
1744 while (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, OWN))
1746 if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, CTXT)) {
1747 if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_CONTEXT_DESC3, TSA) &&
1748 !AXGMAC_GET_BITS_LE(desc->write.desc3,
1749 RX_CONTEXT_DESC3, TSD)) {
1750 pmt = AXGMAC_GET_BITS_LE(desc->write.desc3,
1751 RX_CONTEXT_DESC3, PMT);
1752 nsec = rte_le_to_cpu_32(desc->write.desc1);
1753 nsec *= NSEC_PER_SEC;
1754 nsec += rte_le_to_cpu_32(desc->write.desc0);
1755 if (nsec != 0xffffffffffffffffULL) {
1757 *timestamp = rte_ns_to_timespec(nsec);
1759 "flags = 0x%x nsec = %"PRIu64"\n",
1769 axgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
1770 struct timespec *timestamp)
1773 struct axgbe_port *pdata = dev->data->dev_private;
1774 unsigned int tx_snr, tx_ssr;
1777 if (pdata->vdata->tx_tstamp_workaround) {
1778 tx_snr = AXGMAC_IOREAD(pdata, MAC_TXSNR);
1779 tx_ssr = AXGMAC_IOREAD(pdata, MAC_TXSSR);
1782 tx_ssr = AXGMAC_IOREAD(pdata, MAC_TXSSR);
1783 tx_snr = AXGMAC_IOREAD(pdata, MAC_TXSNR);
1785 if (AXGMAC_GET_BITS(tx_snr, MAC_TXSNR, TXTSSTSMIS)) {
1786 PMD_DRV_LOG(DEBUG, "Waiting for TXTSSTSMIS\n");
1790 nsec *= NSEC_PER_SEC;
1792 PMD_DRV_LOG(DEBUG, "nsec = %"PRIu64" tx_ssr = %d tx_snr = %d\n",
1793 nsec, tx_ssr, tx_snr);
1794 *timestamp = rte_ns_to_timespec(nsec);
1799 axgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vid, int on)
1801 struct axgbe_port *pdata = dev->data->dev_private;
1802 unsigned long vid_bit, vid_idx;
1804 vid_bit = VLAN_TABLE_BIT(vid);
1805 vid_idx = VLAN_TABLE_IDX(vid);
1808 PMD_DRV_LOG(DEBUG, "Set VLAN vid=%d for device = %s\n",
1809 vid, pdata->eth_dev->device->name);
1810 pdata->active_vlans[vid_idx] |= vid_bit;
1812 PMD_DRV_LOG(DEBUG, "Reset VLAN vid=%d for device = %s\n",
1813 vid, pdata->eth_dev->device->name);
1814 pdata->active_vlans[vid_idx] &= ~vid_bit;
1816 pdata->hw_if.update_vlan_hash_table(pdata);
1821 axgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1822 enum rte_vlan_type vlan_type,
1825 struct axgbe_port *pdata = dev->data->dev_private;
1829 qinq = AXGMAC_IOREAD_BITS(pdata, MAC_VLANTR, EDVLP);
1830 PMD_DRV_LOG(DEBUG, "EDVLP: qinq = 0x%x\n", qinq);
1832 switch (vlan_type) {
1833 case RTE_ETH_VLAN_TYPE_INNER:
1834 PMD_DRV_LOG(DEBUG, "RTE_ETH_VLAN_TYPE_INNER\n");
1836 if (tpid != 0x8100 && tpid != 0x88a8)
1838 "tag supported 0x8100/0x88A8\n");
1839 PMD_DRV_LOG(DEBUG, "qinq with inner tag\n");
1841 /*Enable Inner VLAN Tag */
1842 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ERIVLT, 1);
1843 reg = AXGMAC_IOREAD_BITS(pdata, MAC_VLANTR, ERIVLT);
1844 PMD_DRV_LOG(DEBUG, "bit ERIVLT = 0x%x\n", reg);
1848 "Inner type not supported in single tag\n");
1851 case RTE_ETH_VLAN_TYPE_OUTER:
1852 PMD_DRV_LOG(DEBUG, "RTE_ETH_VLAN_TYPE_OUTER\n");
1854 PMD_DRV_LOG(DEBUG, "double tagging is enabled\n");
1855 /*Enable outer VLAN tag*/
1856 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ERIVLT, 0);
1857 reg = AXGMAC_IOREAD_BITS(pdata, MAC_VLANTR, ERIVLT);
1858 PMD_DRV_LOG(DEBUG, "bit ERIVLT = 0x%x\n", reg);
1860 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, CSVL, 1);
1861 reg = AXGMAC_IOREAD_BITS(pdata, MAC_VLANIR, CSVL);
1862 PMD_DRV_LOG(DEBUG, "bit CSVL = 0x%x\n", reg);
1864 if (tpid != 0x8100 && tpid != 0x88a8)
1866 "tag supported 0x8100/0x88A8\n");
1869 case RTE_ETH_VLAN_TYPE_MAX:
1870 PMD_DRV_LOG(ERR, "RTE_ETH_VLAN_TYPE_MAX\n");
1872 case RTE_ETH_VLAN_TYPE_UNKNOWN:
1873 PMD_DRV_LOG(ERR, "RTE_ETH_VLAN_TYPE_UNKNOWN\n");
1879 static void axgbe_vlan_extend_enable(struct axgbe_port *pdata)
1883 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EDVLP, 1);
1884 qinq = AXGMAC_IOREAD_BITS(pdata, MAC_VLANTR, EDVLP);
1885 PMD_DRV_LOG(DEBUG, "vlan double tag enabled EDVLP:qinq=0x%x\n", qinq);
1888 static void axgbe_vlan_extend_disable(struct axgbe_port *pdata)
1892 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EDVLP, 0);
1893 qinq = AXGMAC_IOREAD_BITS(pdata, MAC_VLANTR, EDVLP);
1894 PMD_DRV_LOG(DEBUG, "vlan double tag disable EDVLP:qinq=0x%x\n", qinq);
1898 axgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1900 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
1901 struct axgbe_port *pdata = dev->data->dev_private;
1903 /* Indicate that VLAN Tx CTAGs come from context descriptors */
1904 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, CSVL, 0);
1905 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, VLTI, 1);
1907 if (mask & RTE_ETH_VLAN_STRIP_MASK) {
1908 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) {
1909 PMD_DRV_LOG(DEBUG, "Strip ON for device = %s\n",
1910 pdata->eth_dev->device->name);
1911 pdata->hw_if.enable_rx_vlan_stripping(pdata);
1913 PMD_DRV_LOG(DEBUG, "Strip OFF for device = %s\n",
1914 pdata->eth_dev->device->name);
1915 pdata->hw_if.disable_rx_vlan_stripping(pdata);
1918 if (mask & RTE_ETH_VLAN_FILTER_MASK) {
1919 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) {
1920 PMD_DRV_LOG(DEBUG, "Filter ON for device = %s\n",
1921 pdata->eth_dev->device->name);
1922 pdata->hw_if.enable_rx_vlan_filtering(pdata);
1924 PMD_DRV_LOG(DEBUG, "Filter OFF for device = %s\n",
1925 pdata->eth_dev->device->name);
1926 pdata->hw_if.disable_rx_vlan_filtering(pdata);
1929 if (mask & RTE_ETH_VLAN_EXTEND_MASK) {
1930 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_EXTEND) {
1931 PMD_DRV_LOG(DEBUG, "enabling vlan extended mode\n");
1932 axgbe_vlan_extend_enable(pdata);
1933 /* Set global registers with default ethertype*/
1934 axgbe_vlan_tpid_set(dev, RTE_ETH_VLAN_TYPE_OUTER,
1935 RTE_ETHER_TYPE_VLAN);
1936 axgbe_vlan_tpid_set(dev, RTE_ETH_VLAN_TYPE_INNER,
1937 RTE_ETHER_TYPE_VLAN);
1939 PMD_DRV_LOG(DEBUG, "disabling vlan extended mode\n");
1940 axgbe_vlan_extend_disable(pdata);
1946 static void axgbe_get_all_hw_features(struct axgbe_port *pdata)
1948 unsigned int mac_hfr0, mac_hfr1, mac_hfr2, mac_hfr3;
1949 struct axgbe_hw_features *hw_feat = &pdata->hw_feat;
1951 mac_hfr0 = AXGMAC_IOREAD(pdata, MAC_HWF0R);
1952 mac_hfr1 = AXGMAC_IOREAD(pdata, MAC_HWF1R);
1953 mac_hfr2 = AXGMAC_IOREAD(pdata, MAC_HWF2R);
1954 mac_hfr3 = AXGMAC_IOREAD(pdata, MAC_HWF3R);
1956 memset(hw_feat, 0, sizeof(*hw_feat));
1958 hw_feat->version = AXGMAC_IOREAD(pdata, MAC_VR);
1960 /* Hardware feature register 0 */
1961 hw_feat->gmii = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL);
1962 hw_feat->vlhash = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH);
1963 hw_feat->sma = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SMASEL);
1964 hw_feat->rwk = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RWKSEL);
1965 hw_feat->mgk = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MGKSEL);
1966 hw_feat->mmc = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MMCSEL);
1967 hw_feat->aoe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ARPOFFSEL);
1968 hw_feat->ts = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSEL);
1969 hw_feat->eee = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, EEESEL);
1970 hw_feat->tx_coe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TXCOESEL);
1971 hw_feat->rx_coe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RXCOESEL);
1972 hw_feat->addn_mac = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R,
1974 hw_feat->ts_src = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSTSSEL);
1975 hw_feat->sa_vlan_ins = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SAVLANINS);
1977 /* Hardware feature register 1 */
1978 hw_feat->rx_fifo_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
1980 hw_feat->tx_fifo_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
1982 hw_feat->adv_ts_hi = AXGMAC_GET_BITS(mac_hfr1,
1983 MAC_HWF1R, ADVTHWORD);
1984 hw_feat->dma_width = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADDR64);
1985 hw_feat->dcb = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN);
1986 hw_feat->sph = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN);
1987 hw_feat->tso = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN);
1988 hw_feat->dma_debug = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA);
1989 hw_feat->rss = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, RSSEN);
1990 hw_feat->tc_cnt = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC);
1991 hw_feat->hash_table_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
1993 hw_feat->l3l4_filter_num = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
1996 /* Hardware feature register 2 */
1997 hw_feat->rx_q_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXQCNT);
1998 hw_feat->tx_q_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXQCNT);
1999 hw_feat->rx_ch_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXCHCNT);
2000 hw_feat->tx_ch_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXCHCNT);
2001 hw_feat->pps_out_num = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM);
2002 hw_feat->aux_snap_num = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R,
2005 /* Hardware feature register 3 */
2006 hw_feat->tx_q_vlan_tag_ins = AXGMAC_GET_BITS(mac_hfr3,
2007 MAC_HWF3R, CBTISEL);
2008 hw_feat->no_of_vlan_extn = AXGMAC_GET_BITS(mac_hfr3,
2011 /* Translate the Hash Table size into actual number */
2012 switch (hw_feat->hash_table_size) {
2016 hw_feat->hash_table_size = 64;
2019 hw_feat->hash_table_size = 128;
2022 hw_feat->hash_table_size = 256;
2026 /* Translate the address width setting into actual number */
2027 switch (hw_feat->dma_width) {
2029 hw_feat->dma_width = 32;
2032 hw_feat->dma_width = 40;
2035 hw_feat->dma_width = 48;
2038 hw_feat->dma_width = 32;
2041 /* The Queue, Channel and TC counts are zero based so increment them
2042 * to get the actual number
2044 hw_feat->rx_q_cnt++;
2045 hw_feat->tx_q_cnt++;
2046 hw_feat->rx_ch_cnt++;
2047 hw_feat->tx_ch_cnt++;
2050 /* Translate the fifo sizes into actual numbers */
2051 hw_feat->rx_fifo_size = 1 << (hw_feat->rx_fifo_size + 7);
2052 hw_feat->tx_fifo_size = 1 << (hw_feat->tx_fifo_size + 7);
2055 static void axgbe_init_all_fptrs(struct axgbe_port *pdata)
2057 axgbe_init_function_ptrs_dev(&pdata->hw_if);
2058 axgbe_init_function_ptrs_phy(&pdata->phy_if);
2059 axgbe_init_function_ptrs_i2c(&pdata->i2c_if);
2060 pdata->vdata->init_function_ptrs_phy_impl(&pdata->phy_if);
2063 static void axgbe_set_counts(struct axgbe_port *pdata)
2065 /* Set all the function pointers */
2066 axgbe_init_all_fptrs(pdata);
2068 /* Populate the hardware features */
2069 axgbe_get_all_hw_features(pdata);
2071 /* Set default max values if not provided */
2072 if (!pdata->tx_max_channel_count)
2073 pdata->tx_max_channel_count = pdata->hw_feat.tx_ch_cnt;
2074 if (!pdata->rx_max_channel_count)
2075 pdata->rx_max_channel_count = pdata->hw_feat.rx_ch_cnt;
2077 if (!pdata->tx_max_q_count)
2078 pdata->tx_max_q_count = pdata->hw_feat.tx_q_cnt;
2079 if (!pdata->rx_max_q_count)
2080 pdata->rx_max_q_count = pdata->hw_feat.rx_q_cnt;
2082 /* Calculate the number of Tx and Rx rings to be created
2083 * -Tx (DMA) Channels map 1-to-1 to Tx Queues so set
2084 * the number of Tx queues to the number of Tx channels
2086 * -Rx (DMA) Channels do not map 1-to-1 so use the actual
2087 * number of Rx queues or maximum allowed
2089 pdata->tx_ring_count = RTE_MIN(pdata->hw_feat.tx_ch_cnt,
2090 pdata->tx_max_channel_count);
2091 pdata->tx_ring_count = RTE_MIN(pdata->tx_ring_count,
2092 pdata->tx_max_q_count);
2094 pdata->tx_q_count = pdata->tx_ring_count;
2096 pdata->rx_ring_count = RTE_MIN(pdata->hw_feat.rx_ch_cnt,
2097 pdata->rx_max_channel_count);
2099 pdata->rx_q_count = RTE_MIN(pdata->hw_feat.rx_q_cnt,
2100 pdata->rx_max_q_count);
2103 static void axgbe_default_config(struct axgbe_port *pdata)
2105 pdata->pblx8 = DMA_PBL_X8_ENABLE;
2106 pdata->tx_sf_mode = MTL_TSF_ENABLE;
2107 pdata->tx_threshold = MTL_TX_THRESHOLD_64;
2108 pdata->tx_pbl = DMA_PBL_32;
2109 pdata->tx_osp_mode = DMA_OSP_ENABLE;
2110 pdata->rx_sf_mode = MTL_RSF_ENABLE;
2111 pdata->rx_threshold = MTL_RX_THRESHOLD_64;
2112 pdata->rx_pbl = DMA_PBL_32;
2113 pdata->pause_autoneg = 1;
2114 pdata->tx_pause = 0;
2115 pdata->rx_pause = 0;
2116 pdata->phy_speed = SPEED_UNKNOWN;
2117 pdata->power_down = 0;
2121 pci_device_cmp(const struct rte_device *dev, const void *_pci_id)
2123 const struct rte_pci_device *pdev = RTE_DEV_TO_PCI_CONST(dev);
2124 const struct rte_pci_id *pcid = _pci_id;
2126 if (pdev->id.vendor_id == AMD_PCI_VENDOR_ID &&
2127 pdev->id.device_id == pcid->device_id)
2133 pci_search_device(int device_id)
2135 struct rte_bus *pci_bus;
2136 struct rte_pci_id dev_id;
2138 dev_id.device_id = device_id;
2139 pci_bus = rte_bus_find_by_name("pci");
2140 return (pci_bus != NULL) &&
2141 (pci_bus->find_device(NULL, pci_device_cmp, &dev_id) != NULL);
2145 * It returns 0 on success.
2148 eth_axgbe_dev_init(struct rte_eth_dev *eth_dev)
2150 PMD_INIT_FUNC_TRACE();
2151 struct axgbe_port *pdata;
2152 struct rte_pci_device *pci_dev;
2153 uint32_t reg, mac_lo, mac_hi;
2157 eth_dev->dev_ops = &axgbe_eth_dev_ops;
2159 eth_dev->rx_descriptor_status = axgbe_dev_rx_descriptor_status;
2160 eth_dev->tx_descriptor_status = axgbe_dev_tx_descriptor_status;
2163 * For secondary processes, we don't initialise any further as primary
2164 * has already done this work.
2166 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2169 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2171 pdata = eth_dev->data->dev_private;
2173 rte_bit_relaxed_set32(AXGBE_DOWN, &pdata->dev_state);
2174 rte_bit_relaxed_set32(AXGBE_STOPPED, &pdata->dev_state);
2175 pdata->eth_dev = eth_dev;
2177 pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
2178 pdata->pci_dev = pci_dev;
2181 * Use root complex device ID to differentiate RV AXGBE vs SNOWY AXGBE
2183 if (pci_search_device(AMD_PCI_RV_ROOT_COMPLEX_ID)) {
2184 pdata->xpcs_window_def_reg = PCS_V2_RV_WINDOW_DEF;
2185 pdata->xpcs_window_sel_reg = PCS_V2_RV_WINDOW_SELECT;
2187 pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF;
2188 pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT;
2192 (void *)pci_dev->mem_resource[AXGBE_AXGMAC_BAR].addr;
2193 pdata->xprop_regs = (void *)((uint8_t *)pdata->xgmac_regs
2194 + AXGBE_MAC_PROP_OFFSET);
2195 pdata->xi2c_regs = (void *)((uint8_t *)pdata->xgmac_regs
2196 + AXGBE_I2C_CTRL_OFFSET);
2197 pdata->xpcs_regs = (void *)pci_dev->mem_resource[AXGBE_XPCS_BAR].addr;
2199 /* version specific driver data*/
2200 if (pci_dev->id.device_id == AMD_PCI_AXGBE_DEVICE_V2A)
2201 pdata->vdata = &axgbe_v2a;
2203 pdata->vdata = &axgbe_v2b;
2205 /* Configure the PCS indirect addressing support */
2206 reg = XPCS32_IOREAD(pdata, pdata->xpcs_window_def_reg);
2207 pdata->xpcs_window = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, OFFSET);
2208 pdata->xpcs_window <<= 6;
2209 pdata->xpcs_window_size = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, SIZE);
2210 pdata->xpcs_window_size = 1 << (pdata->xpcs_window_size + 7);
2211 pdata->xpcs_window_mask = pdata->xpcs_window_size - 1;
2214 "xpcs window :%x, size :%x, mask :%x ", pdata->xpcs_window,
2215 pdata->xpcs_window_size, pdata->xpcs_window_mask);
2216 XP_IOWRITE(pdata, XP_INT_EN, 0x1fffff);
2218 /* Retrieve the MAC address */
2219 mac_lo = XP_IOREAD(pdata, XP_MAC_ADDR_LO);
2220 mac_hi = XP_IOREAD(pdata, XP_MAC_ADDR_HI);
2221 pdata->mac_addr.addr_bytes[0] = mac_lo & 0xff;
2222 pdata->mac_addr.addr_bytes[1] = (mac_lo >> 8) & 0xff;
2223 pdata->mac_addr.addr_bytes[2] = (mac_lo >> 16) & 0xff;
2224 pdata->mac_addr.addr_bytes[3] = (mac_lo >> 24) & 0xff;
2225 pdata->mac_addr.addr_bytes[4] = mac_hi & 0xff;
2226 pdata->mac_addr.addr_bytes[5] = (mac_hi >> 8) & 0xff;
2228 len = RTE_ETHER_ADDR_LEN * AXGBE_MAX_MAC_ADDRS;
2229 eth_dev->data->mac_addrs = rte_zmalloc("axgbe_mac_addr", len, 0);
2231 if (!eth_dev->data->mac_addrs) {
2233 "Failed to alloc %u bytes needed to "
2234 "store MAC addresses", len);
2238 /* Allocate memory for storing hash filter MAC addresses */
2239 len = RTE_ETHER_ADDR_LEN * AXGBE_MAX_HASH_MAC_ADDRS;
2240 eth_dev->data->hash_mac_addrs = rte_zmalloc("axgbe_hash_mac_addr",
2243 if (eth_dev->data->hash_mac_addrs == NULL) {
2245 "Failed to allocate %d bytes needed to "
2246 "store MAC addresses", len);
2250 if (!rte_is_valid_assigned_ether_addr(&pdata->mac_addr))
2251 rte_eth_random_addr(pdata->mac_addr.addr_bytes);
2253 /* Copy the permanent MAC address */
2254 rte_ether_addr_copy(&pdata->mac_addr, ð_dev->data->mac_addrs[0]);
2256 /* Clock settings */
2257 pdata->sysclk_rate = AXGBE_V2_DMA_CLOCK_FREQ;
2258 pdata->ptpclk_rate = AXGBE_V2_PTP_CLOCK_FREQ;
2260 /* Set the DMA coherency values */
2261 pdata->coherent = 1;
2262 pdata->axdomain = AXGBE_DMA_OS_AXDOMAIN;
2263 pdata->arcache = AXGBE_DMA_OS_ARCACHE;
2264 pdata->awcache = AXGBE_DMA_OS_AWCACHE;
2266 /* Set the maximum channels and queues */
2267 reg = XP_IOREAD(pdata, XP_PROP_1);
2268 pdata->tx_max_channel_count = XP_GET_BITS(reg, XP_PROP_1, MAX_TX_DMA);
2269 pdata->rx_max_channel_count = XP_GET_BITS(reg, XP_PROP_1, MAX_RX_DMA);
2270 pdata->tx_max_q_count = XP_GET_BITS(reg, XP_PROP_1, MAX_TX_QUEUES);
2271 pdata->rx_max_q_count = XP_GET_BITS(reg, XP_PROP_1, MAX_RX_QUEUES);
2273 /* Set the hardware channel and queue counts */
2274 axgbe_set_counts(pdata);
2276 /* Set the maximum fifo amounts */
2277 reg = XP_IOREAD(pdata, XP_PROP_2);
2278 pdata->tx_max_fifo_size = XP_GET_BITS(reg, XP_PROP_2, TX_FIFO_SIZE);
2279 pdata->tx_max_fifo_size *= 16384;
2280 pdata->tx_max_fifo_size = RTE_MIN(pdata->tx_max_fifo_size,
2281 pdata->vdata->tx_max_fifo_size);
2282 pdata->rx_max_fifo_size = XP_GET_BITS(reg, XP_PROP_2, RX_FIFO_SIZE);
2283 pdata->rx_max_fifo_size *= 16384;
2284 pdata->rx_max_fifo_size = RTE_MIN(pdata->rx_max_fifo_size,
2285 pdata->vdata->rx_max_fifo_size);
2286 /* Issue software reset to DMA */
2287 ret = pdata->hw_if.exit(pdata);
2289 PMD_DRV_LOG(ERR, "hw_if->exit EBUSY error\n");
2291 /* Set default configuration data */
2292 axgbe_default_config(pdata);
2294 /* Set default max values if not provided */
2295 if (!pdata->tx_max_fifo_size)
2296 pdata->tx_max_fifo_size = pdata->hw_feat.tx_fifo_size;
2297 if (!pdata->rx_max_fifo_size)
2298 pdata->rx_max_fifo_size = pdata->hw_feat.rx_fifo_size;
2300 pdata->tx_desc_count = AXGBE_MAX_RING_DESC;
2301 pdata->rx_desc_count = AXGBE_MAX_RING_DESC;
2302 pthread_mutex_init(&pdata->xpcs_mutex, NULL);
2303 pthread_mutex_init(&pdata->i2c_mutex, NULL);
2304 pthread_mutex_init(&pdata->an_mutex, NULL);
2305 pthread_mutex_init(&pdata->phy_mutex, NULL);
2307 ret = pdata->phy_if.phy_init(pdata);
2309 rte_free(eth_dev->data->mac_addrs);
2310 eth_dev->data->mac_addrs = NULL;
2314 rte_intr_callback_register(pci_dev->intr_handle,
2315 axgbe_dev_interrupt_handler,
2317 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
2318 eth_dev->data->port_id, pci_dev->id.vendor_id,
2319 pci_dev->id.device_id);
2325 axgbe_dev_close(struct rte_eth_dev *eth_dev)
2327 struct rte_pci_device *pci_dev;
2329 PMD_INIT_FUNC_TRACE();
2331 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2334 pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
2335 axgbe_dev_clear_queues(eth_dev);
2337 /* disable uio intr before callback unregister */
2338 rte_intr_disable(pci_dev->intr_handle);
2339 rte_intr_callback_unregister(pci_dev->intr_handle,
2340 axgbe_dev_interrupt_handler,
2346 static int eth_axgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2347 struct rte_pci_device *pci_dev)
2349 return rte_eth_dev_pci_generic_probe(pci_dev,
2350 sizeof(struct axgbe_port), eth_axgbe_dev_init);
2353 static int eth_axgbe_pci_remove(struct rte_pci_device *pci_dev)
2355 return rte_eth_dev_pci_generic_remove(pci_dev, axgbe_dev_close);
2358 static struct rte_pci_driver rte_axgbe_pmd = {
2359 .id_table = pci_id_axgbe_map,
2360 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
2361 .probe = eth_axgbe_pci_probe,
2362 .remove = eth_axgbe_pci_remove,
2365 RTE_PMD_REGISTER_PCI(net_axgbe, rte_axgbe_pmd);
2366 RTE_PMD_REGISTER_PCI_TABLE(net_axgbe, pci_id_axgbe_map);
2367 RTE_PMD_REGISTER_KMOD_DEP(net_axgbe, "* igb_uio | uio_pci_generic | vfio-pci");
2368 RTE_LOG_REGISTER_SUFFIX(axgbe_logtype_init, init, NOTICE);
2369 RTE_LOG_REGISTER_SUFFIX(axgbe_logtype_driver, driver, NOTICE);