1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved.
3 * Copyright(c) 2018 Synopsys, Inc. All rights reserved.
6 #include "axgbe_rxtx.h"
7 #include "axgbe_ethdev.h"
8 #include "axgbe_common.h"
11 static int eth_axgbe_dev_init(struct rte_eth_dev *eth_dev);
12 static int eth_axgbe_dev_uninit(struct rte_eth_dev *eth_dev);
13 static int axgbe_dev_configure(struct rte_eth_dev *dev);
14 static int axgbe_dev_start(struct rte_eth_dev *dev);
15 static void axgbe_dev_stop(struct rte_eth_dev *dev);
16 static void axgbe_dev_interrupt_handler(void *param);
17 static void axgbe_dev_close(struct rte_eth_dev *dev);
18 static void axgbe_dev_info_get(struct rte_eth_dev *dev,
19 struct rte_eth_dev_info *dev_info);
21 /* The set of PCI devices this driver supports */
22 #define AMD_PCI_VENDOR_ID 0x1022
23 #define AMD_PCI_AXGBE_DEVICE_V2A 0x1458
24 #define AMD_PCI_AXGBE_DEVICE_V2B 0x1459
26 int axgbe_logtype_init;
27 int axgbe_logtype_driver;
29 static const struct rte_pci_id pci_id_axgbe_map[] = {
30 {RTE_PCI_DEVICE(AMD_PCI_VENDOR_ID, AMD_PCI_AXGBE_DEVICE_V2A)},
31 {RTE_PCI_DEVICE(AMD_PCI_VENDOR_ID, AMD_PCI_AXGBE_DEVICE_V2B)},
35 static struct axgbe_version_data axgbe_v2a = {
36 .init_function_ptrs_phy_impl = axgbe_init_function_ptrs_phy_v2,
37 .xpcs_access = AXGBE_XPCS_ACCESS_V2,
39 .tx_max_fifo_size = 229376,
40 .rx_max_fifo_size = 229376,
41 .tx_tstamp_workaround = 1,
46 static struct axgbe_version_data axgbe_v2b = {
47 .init_function_ptrs_phy_impl = axgbe_init_function_ptrs_phy_v2,
48 .xpcs_access = AXGBE_XPCS_ACCESS_V2,
50 .tx_max_fifo_size = 65536,
51 .rx_max_fifo_size = 65536,
52 .tx_tstamp_workaround = 1,
57 static const struct rte_eth_desc_lim rx_desc_lim = {
58 .nb_max = AXGBE_MAX_RING_DESC,
59 .nb_min = AXGBE_MIN_RING_DESC,
63 static const struct rte_eth_desc_lim tx_desc_lim = {
64 .nb_max = AXGBE_MAX_RING_DESC,
65 .nb_min = AXGBE_MIN_RING_DESC,
69 static const struct eth_dev_ops axgbe_eth_dev_ops = {
70 .dev_configure = axgbe_dev_configure,
71 .dev_start = axgbe_dev_start,
72 .dev_stop = axgbe_dev_stop,
73 .dev_close = axgbe_dev_close,
74 .dev_infos_get = axgbe_dev_info_get,
75 .rx_queue_setup = axgbe_dev_rx_queue_setup,
76 .rx_queue_release = axgbe_dev_rx_queue_release,
77 .tx_queue_setup = axgbe_dev_tx_queue_setup,
78 .tx_queue_release = axgbe_dev_tx_queue_release,
81 static int axgbe_phy_reset(struct axgbe_port *pdata)
84 pdata->phy_speed = SPEED_UNKNOWN;
85 return pdata->phy_if.phy_reset(pdata);
89 * Interrupt handler triggered by NIC for handling
93 * Pointer to interrupt handle.
95 * The address of parameter (struct rte_eth_dev *) regsitered before.
101 axgbe_dev_interrupt_handler(void *param)
103 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
104 struct axgbe_port *pdata = dev->data->dev_private;
106 pdata->phy_if.an_isr(pdata);
108 /* Enable interrupts since disabled after generation*/
109 rte_intr_enable(&pdata->pci_dev->intr_handle);
113 * Configure device link speed and setup link.
114 * It returns 0 on success.
117 axgbe_dev_configure(struct rte_eth_dev *dev)
119 struct axgbe_port *pdata = dev->data->dev_private;
120 /* Checksum offload to hardware */
121 pdata->rx_csum_enable = dev->data->dev_conf.rxmode.offloads &
122 DEV_RX_OFFLOAD_CHECKSUM;
127 axgbe_dev_rx_mq_config(struct rte_eth_dev *dev)
129 struct axgbe_port *pdata = (struct axgbe_port *)dev->data->dev_private;
131 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS)
132 pdata->rss_enable = 1;
133 else if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_NONE)
134 pdata->rss_enable = 0;
141 axgbe_dev_start(struct rte_eth_dev *dev)
143 PMD_INIT_FUNC_TRACE();
144 struct axgbe_port *pdata = (struct axgbe_port *)dev->data->dev_private;
148 ret = axgbe_dev_rx_mq_config(dev);
150 PMD_DRV_LOG(ERR, "Unable to config RX MQ\n");
153 ret = axgbe_phy_reset(pdata);
155 PMD_DRV_LOG(ERR, "phy reset failed\n");
158 ret = pdata->hw_if.init(pdata);
160 PMD_DRV_LOG(ERR, "dev_init failed\n");
164 /* enable uio/vfio intr/eventfd mapping */
165 rte_intr_enable(&pdata->pci_dev->intr_handle);
168 pdata->phy_if.phy_start(pdata);
170 axgbe_clear_bit(AXGBE_STOPPED, &pdata->dev_state);
171 axgbe_clear_bit(AXGBE_DOWN, &pdata->dev_state);
175 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
177 axgbe_dev_stop(struct rte_eth_dev *dev)
179 PMD_INIT_FUNC_TRACE();
180 struct axgbe_port *pdata = dev->data->dev_private;
182 rte_intr_disable(&pdata->pci_dev->intr_handle);
184 if (axgbe_test_bit(AXGBE_STOPPED, &pdata->dev_state))
187 axgbe_set_bit(AXGBE_STOPPED, &pdata->dev_state);
189 pdata->phy_if.phy_stop(pdata);
190 pdata->hw_if.exit(pdata);
191 memset(&dev->data->dev_link, 0, sizeof(struct rte_eth_link));
192 axgbe_set_bit(AXGBE_DOWN, &pdata->dev_state);
195 /* Clear all resources like TX/RX queues. */
197 axgbe_dev_close(struct rte_eth_dev *dev)
199 axgbe_dev_clear_queues(dev);
203 axgbe_dev_info_get(struct rte_eth_dev *dev,
204 struct rte_eth_dev_info *dev_info)
206 struct axgbe_port *pdata = dev->data->dev_private;
208 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
209 dev_info->max_rx_queues = pdata->rx_ring_count;
210 dev_info->max_tx_queues = pdata->tx_ring_count;
211 dev_info->min_rx_bufsize = AXGBE_RX_MIN_BUF_SIZE;
212 dev_info->max_rx_pktlen = AXGBE_RX_MAX_BUF_SIZE;
213 dev_info->max_mac_addrs = AXGBE_MAX_MAC_ADDRS;
214 dev_info->speed_capa = ETH_LINK_SPEED_10G;
216 dev_info->rx_offload_capa =
217 DEV_RX_OFFLOAD_IPV4_CKSUM |
218 DEV_RX_OFFLOAD_UDP_CKSUM |
219 DEV_RX_OFFLOAD_TCP_CKSUM;
221 dev_info->tx_offload_capa =
222 DEV_TX_OFFLOAD_IPV4_CKSUM |
223 DEV_TX_OFFLOAD_UDP_CKSUM |
224 DEV_TX_OFFLOAD_TCP_CKSUM;
226 if (pdata->hw_feat.rss) {
227 dev_info->flow_type_rss_offloads = AXGBE_RSS_OFFLOAD;
228 dev_info->reta_size = pdata->hw_feat.hash_table_size;
229 dev_info->hash_key_size = AXGBE_RSS_HASH_KEY_SIZE;
232 dev_info->rx_desc_lim = rx_desc_lim;
233 dev_info->tx_desc_lim = tx_desc_lim;
235 dev_info->default_rxconf = (struct rte_eth_rxconf) {
236 .rx_free_thresh = AXGBE_RX_FREE_THRESH,
239 dev_info->default_txconf = (struct rte_eth_txconf) {
240 .tx_free_thresh = AXGBE_TX_FREE_THRESH,
241 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
242 ETH_TXQ_FLAGS_NOOFFLOADS,
246 static void axgbe_get_all_hw_features(struct axgbe_port *pdata)
248 unsigned int mac_hfr0, mac_hfr1, mac_hfr2;
249 struct axgbe_hw_features *hw_feat = &pdata->hw_feat;
251 mac_hfr0 = AXGMAC_IOREAD(pdata, MAC_HWF0R);
252 mac_hfr1 = AXGMAC_IOREAD(pdata, MAC_HWF1R);
253 mac_hfr2 = AXGMAC_IOREAD(pdata, MAC_HWF2R);
255 memset(hw_feat, 0, sizeof(*hw_feat));
257 hw_feat->version = AXGMAC_IOREAD(pdata, MAC_VR);
259 /* Hardware feature register 0 */
260 hw_feat->gmii = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL);
261 hw_feat->vlhash = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH);
262 hw_feat->sma = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SMASEL);
263 hw_feat->rwk = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RWKSEL);
264 hw_feat->mgk = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MGKSEL);
265 hw_feat->mmc = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MMCSEL);
266 hw_feat->aoe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ARPOFFSEL);
267 hw_feat->ts = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSEL);
268 hw_feat->eee = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, EEESEL);
269 hw_feat->tx_coe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TXCOESEL);
270 hw_feat->rx_coe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RXCOESEL);
271 hw_feat->addn_mac = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R,
273 hw_feat->ts_src = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSTSSEL);
274 hw_feat->sa_vlan_ins = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SAVLANINS);
276 /* Hardware feature register 1 */
277 hw_feat->rx_fifo_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
279 hw_feat->tx_fifo_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
281 hw_feat->adv_ts_hi = AXGMAC_GET_BITS(mac_hfr1,
282 MAC_HWF1R, ADVTHWORD);
283 hw_feat->dma_width = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADDR64);
284 hw_feat->dcb = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN);
285 hw_feat->sph = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN);
286 hw_feat->tso = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN);
287 hw_feat->dma_debug = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA);
288 hw_feat->rss = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, RSSEN);
289 hw_feat->tc_cnt = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC);
290 hw_feat->hash_table_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
292 hw_feat->l3l4_filter_num = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
295 /* Hardware feature register 2 */
296 hw_feat->rx_q_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXQCNT);
297 hw_feat->tx_q_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXQCNT);
298 hw_feat->rx_ch_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXCHCNT);
299 hw_feat->tx_ch_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXCHCNT);
300 hw_feat->pps_out_num = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM);
301 hw_feat->aux_snap_num = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R,
304 /* Translate the Hash Table size into actual number */
305 switch (hw_feat->hash_table_size) {
309 hw_feat->hash_table_size = 64;
312 hw_feat->hash_table_size = 128;
315 hw_feat->hash_table_size = 256;
319 /* Translate the address width setting into actual number */
320 switch (hw_feat->dma_width) {
322 hw_feat->dma_width = 32;
325 hw_feat->dma_width = 40;
328 hw_feat->dma_width = 48;
331 hw_feat->dma_width = 32;
334 /* The Queue, Channel and TC counts are zero based so increment them
335 * to get the actual number
339 hw_feat->rx_ch_cnt++;
340 hw_feat->tx_ch_cnt++;
343 /* Translate the fifo sizes into actual numbers */
344 hw_feat->rx_fifo_size = 1 << (hw_feat->rx_fifo_size + 7);
345 hw_feat->tx_fifo_size = 1 << (hw_feat->tx_fifo_size + 7);
348 static void axgbe_init_all_fptrs(struct axgbe_port *pdata)
350 axgbe_init_function_ptrs_dev(&pdata->hw_if);
351 axgbe_init_function_ptrs_phy(&pdata->phy_if);
352 axgbe_init_function_ptrs_i2c(&pdata->i2c_if);
353 pdata->vdata->init_function_ptrs_phy_impl(&pdata->phy_if);
356 static void axgbe_set_counts(struct axgbe_port *pdata)
358 /* Set all the function pointers */
359 axgbe_init_all_fptrs(pdata);
361 /* Populate the hardware features */
362 axgbe_get_all_hw_features(pdata);
364 /* Set default max values if not provided */
365 if (!pdata->tx_max_channel_count)
366 pdata->tx_max_channel_count = pdata->hw_feat.tx_ch_cnt;
367 if (!pdata->rx_max_channel_count)
368 pdata->rx_max_channel_count = pdata->hw_feat.rx_ch_cnt;
370 if (!pdata->tx_max_q_count)
371 pdata->tx_max_q_count = pdata->hw_feat.tx_q_cnt;
372 if (!pdata->rx_max_q_count)
373 pdata->rx_max_q_count = pdata->hw_feat.rx_q_cnt;
375 /* Calculate the number of Tx and Rx rings to be created
376 * -Tx (DMA) Channels map 1-to-1 to Tx Queues so set
377 * the number of Tx queues to the number of Tx channels
379 * -Rx (DMA) Channels do not map 1-to-1 so use the actual
380 * number of Rx queues or maximum allowed
382 pdata->tx_ring_count = RTE_MIN(pdata->hw_feat.tx_ch_cnt,
383 pdata->tx_max_channel_count);
384 pdata->tx_ring_count = RTE_MIN(pdata->tx_ring_count,
385 pdata->tx_max_q_count);
387 pdata->tx_q_count = pdata->tx_ring_count;
389 pdata->rx_ring_count = RTE_MIN(pdata->hw_feat.rx_ch_cnt,
390 pdata->rx_max_channel_count);
392 pdata->rx_q_count = RTE_MIN(pdata->hw_feat.rx_q_cnt,
393 pdata->rx_max_q_count);
396 static void axgbe_default_config(struct axgbe_port *pdata)
398 pdata->pblx8 = DMA_PBL_X8_ENABLE;
399 pdata->tx_sf_mode = MTL_TSF_ENABLE;
400 pdata->tx_threshold = MTL_TX_THRESHOLD_64;
401 pdata->tx_pbl = DMA_PBL_32;
402 pdata->tx_osp_mode = DMA_OSP_ENABLE;
403 pdata->rx_sf_mode = MTL_RSF_ENABLE;
404 pdata->rx_threshold = MTL_RX_THRESHOLD_64;
405 pdata->rx_pbl = DMA_PBL_32;
406 pdata->pause_autoneg = 1;
409 pdata->phy_speed = SPEED_UNKNOWN;
410 pdata->power_down = 0;
414 * It returns 0 on success.
417 eth_axgbe_dev_init(struct rte_eth_dev *eth_dev)
419 PMD_INIT_FUNC_TRACE();
420 struct axgbe_port *pdata;
421 struct rte_pci_device *pci_dev;
422 uint32_t reg, mac_lo, mac_hi;
425 eth_dev->dev_ops = &axgbe_eth_dev_ops;
428 * For secondary processes, we don't initialise any further as primary
429 * has already done this work.
431 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
434 pdata = (struct axgbe_port *)eth_dev->data->dev_private;
436 axgbe_set_bit(AXGBE_DOWN, &pdata->dev_state);
437 axgbe_set_bit(AXGBE_STOPPED, &pdata->dev_state);
438 pdata->eth_dev = eth_dev;
440 pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
441 pdata->pci_dev = pci_dev;
444 (uint64_t)pci_dev->mem_resource[AXGBE_AXGMAC_BAR].addr;
445 pdata->xprop_regs = pdata->xgmac_regs + AXGBE_MAC_PROP_OFFSET;
446 pdata->xi2c_regs = pdata->xgmac_regs + AXGBE_I2C_CTRL_OFFSET;
447 pdata->xpcs_regs = (uint64_t)pci_dev->mem_resource[AXGBE_XPCS_BAR].addr;
449 /* version specific driver data*/
450 if (pci_dev->id.device_id == AMD_PCI_AXGBE_DEVICE_V2A)
451 pdata->vdata = &axgbe_v2a;
453 pdata->vdata = &axgbe_v2b;
455 /* Configure the PCS indirect addressing support */
456 reg = XPCS32_IOREAD(pdata, PCS_V2_WINDOW_DEF);
457 pdata->xpcs_window = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, OFFSET);
458 pdata->xpcs_window <<= 6;
459 pdata->xpcs_window_size = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, SIZE);
460 pdata->xpcs_window_size = 1 << (pdata->xpcs_window_size + 7);
461 pdata->xpcs_window_mask = pdata->xpcs_window_size - 1;
462 pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF;
463 pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT;
465 "xpcs window :%x, size :%x, mask :%x ", pdata->xpcs_window,
466 pdata->xpcs_window_size, pdata->xpcs_window_mask);
467 XP_IOWRITE(pdata, XP_INT_EN, 0x1fffff);
469 /* Retrieve the MAC address */
470 mac_lo = XP_IOREAD(pdata, XP_MAC_ADDR_LO);
471 mac_hi = XP_IOREAD(pdata, XP_MAC_ADDR_HI);
472 pdata->mac_addr.addr_bytes[0] = mac_lo & 0xff;
473 pdata->mac_addr.addr_bytes[1] = (mac_lo >> 8) & 0xff;
474 pdata->mac_addr.addr_bytes[2] = (mac_lo >> 16) & 0xff;
475 pdata->mac_addr.addr_bytes[3] = (mac_lo >> 24) & 0xff;
476 pdata->mac_addr.addr_bytes[4] = mac_hi & 0xff;
477 pdata->mac_addr.addr_bytes[5] = (mac_hi >> 8) & 0xff;
479 eth_dev->data->mac_addrs = rte_zmalloc("axgbe_mac_addr",
481 if (!eth_dev->data->mac_addrs) {
483 "Failed to alloc %u bytes needed to store MAC addr tbl",
488 if (!is_valid_assigned_ether_addr(&pdata->mac_addr))
489 eth_random_addr(pdata->mac_addr.addr_bytes);
491 /* Copy the permanent MAC address */
492 ether_addr_copy(&pdata->mac_addr, ð_dev->data->mac_addrs[0]);
495 pdata->sysclk_rate = AXGBE_V2_DMA_CLOCK_FREQ;
496 pdata->ptpclk_rate = AXGBE_V2_PTP_CLOCK_FREQ;
498 /* Set the DMA coherency values */
500 pdata->axdomain = AXGBE_DMA_OS_AXDOMAIN;
501 pdata->arcache = AXGBE_DMA_OS_ARCACHE;
502 pdata->awcache = AXGBE_DMA_OS_AWCACHE;
504 /* Set the maximum channels and queues */
505 reg = XP_IOREAD(pdata, XP_PROP_1);
506 pdata->tx_max_channel_count = XP_GET_BITS(reg, XP_PROP_1, MAX_TX_DMA);
507 pdata->rx_max_channel_count = XP_GET_BITS(reg, XP_PROP_1, MAX_RX_DMA);
508 pdata->tx_max_q_count = XP_GET_BITS(reg, XP_PROP_1, MAX_TX_QUEUES);
509 pdata->rx_max_q_count = XP_GET_BITS(reg, XP_PROP_1, MAX_RX_QUEUES);
511 /* Set the hardware channel and queue counts */
512 axgbe_set_counts(pdata);
514 /* Set the maximum fifo amounts */
515 reg = XP_IOREAD(pdata, XP_PROP_2);
516 pdata->tx_max_fifo_size = XP_GET_BITS(reg, XP_PROP_2, TX_FIFO_SIZE);
517 pdata->tx_max_fifo_size *= 16384;
518 pdata->tx_max_fifo_size = RTE_MIN(pdata->tx_max_fifo_size,
519 pdata->vdata->tx_max_fifo_size);
520 pdata->rx_max_fifo_size = XP_GET_BITS(reg, XP_PROP_2, RX_FIFO_SIZE);
521 pdata->rx_max_fifo_size *= 16384;
522 pdata->rx_max_fifo_size = RTE_MIN(pdata->rx_max_fifo_size,
523 pdata->vdata->rx_max_fifo_size);
524 /* Issue software reset to DMA */
525 ret = pdata->hw_if.exit(pdata);
527 PMD_DRV_LOG(ERR, "hw_if->exit EBUSY error\n");
529 /* Set default configuration data */
530 axgbe_default_config(pdata);
532 /* Set default max values if not provided */
533 if (!pdata->tx_max_fifo_size)
534 pdata->tx_max_fifo_size = pdata->hw_feat.tx_fifo_size;
535 if (!pdata->rx_max_fifo_size)
536 pdata->rx_max_fifo_size = pdata->hw_feat.rx_fifo_size;
538 pdata->tx_desc_count = AXGBE_MAX_RING_DESC;
539 pdata->rx_desc_count = AXGBE_MAX_RING_DESC;
540 pthread_mutex_init(&pdata->xpcs_mutex, NULL);
541 pthread_mutex_init(&pdata->i2c_mutex, NULL);
542 pthread_mutex_init(&pdata->an_mutex, NULL);
543 pthread_mutex_init(&pdata->phy_mutex, NULL);
545 ret = pdata->phy_if.phy_init(pdata);
547 rte_free(eth_dev->data->mac_addrs);
551 rte_intr_callback_register(&pci_dev->intr_handle,
552 axgbe_dev_interrupt_handler,
554 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
555 eth_dev->data->port_id, pci_dev->id.vendor_id,
556 pci_dev->id.device_id);
562 eth_axgbe_dev_uninit(struct rte_eth_dev *eth_dev)
564 struct rte_pci_device *pci_dev;
566 PMD_INIT_FUNC_TRACE();
568 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
571 pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
573 rte_free(eth_dev->data->mac_addrs);
574 eth_dev->data->mac_addrs = NULL;
575 eth_dev->dev_ops = NULL;
576 axgbe_dev_clear_queues(eth_dev);
578 /* disable uio intr before callback unregister */
579 rte_intr_disable(&pci_dev->intr_handle);
580 rte_intr_callback_unregister(&pci_dev->intr_handle,
581 axgbe_dev_interrupt_handler,
587 static int eth_axgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
588 struct rte_pci_device *pci_dev)
590 return rte_eth_dev_pci_generic_probe(pci_dev,
591 sizeof(struct axgbe_port), eth_axgbe_dev_init);
594 static int eth_axgbe_pci_remove(struct rte_pci_device *pci_dev)
596 return rte_eth_dev_pci_generic_remove(pci_dev, eth_axgbe_dev_uninit);
599 static struct rte_pci_driver rte_axgbe_pmd = {
600 .id_table = pci_id_axgbe_map,
601 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
602 .probe = eth_axgbe_pci_probe,
603 .remove = eth_axgbe_pci_remove,
606 RTE_PMD_REGISTER_PCI(net_axgbe, rte_axgbe_pmd);
607 RTE_PMD_REGISTER_PCI_TABLE(net_axgbe, pci_id_axgbe_map);
608 RTE_PMD_REGISTER_KMOD_DEP(net_axgbe, "* igb_uio | uio_pci_generic | vfio-pci");
610 RTE_INIT(axgbe_init_log);
614 axgbe_logtype_init = rte_log_register("pmd.net.axgbe.init");
615 if (axgbe_logtype_init >= 0)
616 rte_log_set_level(axgbe_logtype_init, RTE_LOG_NOTICE);
617 axgbe_logtype_driver = rte_log_register("pmd.net.axgbe.driver");
618 if (axgbe_logtype_driver >= 0)
619 rte_log_set_level(axgbe_logtype_driver, RTE_LOG_NOTICE);