1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved.
3 * Copyright(c) 2018 Synopsys, Inc. All rights reserved.
6 #include "axgbe_rxtx.h"
7 #include "axgbe_ethdev.h"
8 #include "axgbe_common.h"
10 #include "axgbe_regs.h"
13 #include "eal_filesystem.h"
15 static int eth_axgbe_dev_init(struct rte_eth_dev *eth_dev);
16 static int axgbe_dev_configure(struct rte_eth_dev *dev);
17 static int axgbe_dev_start(struct rte_eth_dev *dev);
18 static int axgbe_dev_stop(struct rte_eth_dev *dev);
19 static void axgbe_dev_interrupt_handler(void *param);
20 static int axgbe_dev_close(struct rte_eth_dev *dev);
21 static int axgbe_dev_reset(struct rte_eth_dev *dev);
22 static int axgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
23 static int axgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
24 static int axgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
25 static int axgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
26 static int axgbe_dev_mac_addr_set(struct rte_eth_dev *dev,
27 struct rte_ether_addr *mac_addr);
28 static int axgbe_dev_mac_addr_add(struct rte_eth_dev *dev,
29 struct rte_ether_addr *mac_addr,
32 static void axgbe_dev_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
33 static int axgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
34 struct rte_ether_addr *mc_addr_set,
36 static int axgbe_dev_uc_hash_table_set(struct rte_eth_dev *dev,
37 struct rte_ether_addr *mac_addr,
39 static int axgbe_dev_uc_all_hash_table_set(struct rte_eth_dev *dev,
41 static int axgbe_dev_link_update(struct rte_eth_dev *dev,
42 int wait_to_complete);
43 static int axgbe_dev_get_regs(struct rte_eth_dev *dev,
44 struct rte_dev_reg_info *regs);
45 static int axgbe_dev_stats_get(struct rte_eth_dev *dev,
46 struct rte_eth_stats *stats);
47 static int axgbe_dev_stats_reset(struct rte_eth_dev *dev);
48 static int axgbe_dev_xstats_get(struct rte_eth_dev *dev,
49 struct rte_eth_xstat *stats,
52 axgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
53 struct rte_eth_xstat_name *xstats_names,
56 axgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev,
61 axgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev,
63 struct rte_eth_xstat_name *xstats_names,
65 static int axgbe_dev_xstats_reset(struct rte_eth_dev *dev);
66 static int axgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
67 struct rte_eth_rss_reta_entry64 *reta_conf,
69 static int axgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
70 struct rte_eth_rss_reta_entry64 *reta_conf,
72 static int axgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
73 struct rte_eth_rss_conf *rss_conf);
74 static int axgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
75 struct rte_eth_rss_conf *rss_conf);
76 static int axgbe_dev_info_get(struct rte_eth_dev *dev,
77 struct rte_eth_dev_info *dev_info);
78 static int axgbe_flow_ctrl_get(struct rte_eth_dev *dev,
79 struct rte_eth_fc_conf *fc_conf);
80 static int axgbe_flow_ctrl_set(struct rte_eth_dev *dev,
81 struct rte_eth_fc_conf *fc_conf);
82 static int axgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
83 struct rte_eth_pfc_conf *pfc_conf);
84 static void axgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
85 struct rte_eth_rxq_info *qinfo);
86 static void axgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
87 struct rte_eth_txq_info *qinfo);
88 const uint32_t *axgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
89 static int axgb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
92 axgbe_timesync_enable(struct rte_eth_dev *dev);
94 axgbe_timesync_disable(struct rte_eth_dev *dev);
96 axgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
97 struct timespec *timestamp, uint32_t flags);
99 axgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
100 struct timespec *timestamp);
102 axgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
104 axgbe_timesync_read_time(struct rte_eth_dev *dev,
105 struct timespec *timestamp);
107 axgbe_timesync_write_time(struct rte_eth_dev *dev,
108 const struct timespec *timestamp);
110 axgbe_set_tstamp_time(struct axgbe_port *pdata, unsigned int sec,
113 axgbe_update_tstamp_addend(struct axgbe_port *pdata,
114 unsigned int addend);
116 axgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vid, int on);
117 static int axgbe_vlan_tpid_set(struct rte_eth_dev *dev,
118 enum rte_vlan_type vlan_type, uint16_t tpid);
119 static int axgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
121 struct axgbe_xstats {
122 char name[RTE_ETH_XSTATS_NAME_SIZE];
126 #define AXGMAC_MMC_STAT(_string, _var) \
128 offsetof(struct axgbe_mmc_stats, _var), \
131 static const struct axgbe_xstats axgbe_xstats_strings[] = {
132 AXGMAC_MMC_STAT("tx_bytes", txoctetcount_gb),
133 AXGMAC_MMC_STAT("tx_packets", txframecount_gb),
134 AXGMAC_MMC_STAT("tx_unicast_packets", txunicastframes_gb),
135 AXGMAC_MMC_STAT("tx_broadcast_packets", txbroadcastframes_gb),
136 AXGMAC_MMC_STAT("tx_multicast_packets", txmulticastframes_gb),
137 AXGMAC_MMC_STAT("tx_vlan_packets", txvlanframes_g),
138 AXGMAC_MMC_STAT("tx_64_byte_packets", tx64octets_gb),
139 AXGMAC_MMC_STAT("tx_65_to_127_byte_packets", tx65to127octets_gb),
140 AXGMAC_MMC_STAT("tx_128_to_255_byte_packets", tx128to255octets_gb),
141 AXGMAC_MMC_STAT("tx_256_to_511_byte_packets", tx256to511octets_gb),
142 AXGMAC_MMC_STAT("tx_512_to_1023_byte_packets", tx512to1023octets_gb),
143 AXGMAC_MMC_STAT("tx_1024_to_max_byte_packets", tx1024tomaxoctets_gb),
144 AXGMAC_MMC_STAT("tx_underflow_errors", txunderflowerror),
145 AXGMAC_MMC_STAT("tx_pause_frames", txpauseframes),
147 AXGMAC_MMC_STAT("rx_bytes", rxoctetcount_gb),
148 AXGMAC_MMC_STAT("rx_packets", rxframecount_gb),
149 AXGMAC_MMC_STAT("rx_unicast_packets", rxunicastframes_g),
150 AXGMAC_MMC_STAT("rx_broadcast_packets", rxbroadcastframes_g),
151 AXGMAC_MMC_STAT("rx_multicast_packets", rxmulticastframes_g),
152 AXGMAC_MMC_STAT("rx_vlan_packets", rxvlanframes_gb),
153 AXGMAC_MMC_STAT("rx_64_byte_packets", rx64octets_gb),
154 AXGMAC_MMC_STAT("rx_65_to_127_byte_packets", rx65to127octets_gb),
155 AXGMAC_MMC_STAT("rx_128_to_255_byte_packets", rx128to255octets_gb),
156 AXGMAC_MMC_STAT("rx_256_to_511_byte_packets", rx256to511octets_gb),
157 AXGMAC_MMC_STAT("rx_512_to_1023_byte_packets", rx512to1023octets_gb),
158 AXGMAC_MMC_STAT("rx_1024_to_max_byte_packets", rx1024tomaxoctets_gb),
159 AXGMAC_MMC_STAT("rx_undersize_packets", rxundersize_g),
160 AXGMAC_MMC_STAT("rx_oversize_packets", rxoversize_g),
161 AXGMAC_MMC_STAT("rx_crc_errors", rxcrcerror),
162 AXGMAC_MMC_STAT("rx_crc_errors_small_packets", rxrunterror),
163 AXGMAC_MMC_STAT("rx_crc_errors_giant_packets", rxjabbererror),
164 AXGMAC_MMC_STAT("rx_length_errors", rxlengtherror),
165 AXGMAC_MMC_STAT("rx_out_of_range_errors", rxoutofrangetype),
166 AXGMAC_MMC_STAT("rx_fifo_overflow_errors", rxfifooverflow),
167 AXGMAC_MMC_STAT("rx_watchdog_errors", rxwatchdogerror),
168 AXGMAC_MMC_STAT("rx_pause_frames", rxpauseframes),
171 #define AXGBE_XSTATS_COUNT ARRAY_SIZE(axgbe_xstats_strings)
173 /* The set of PCI devices this driver supports */
174 #define AMD_PCI_VENDOR_ID 0x1022
175 #define AMD_PCI_RV_ROOT_COMPLEX_ID 0x15d0
176 #define AMD_PCI_AXGBE_DEVICE_V2A 0x1458
177 #define AMD_PCI_AXGBE_DEVICE_V2B 0x1459
179 static const struct rte_pci_id pci_id_axgbe_map[] = {
180 {RTE_PCI_DEVICE(AMD_PCI_VENDOR_ID, AMD_PCI_AXGBE_DEVICE_V2A)},
181 {RTE_PCI_DEVICE(AMD_PCI_VENDOR_ID, AMD_PCI_AXGBE_DEVICE_V2B)},
185 static struct axgbe_version_data axgbe_v2a = {
186 .init_function_ptrs_phy_impl = axgbe_init_function_ptrs_phy_v2,
187 .xpcs_access = AXGBE_XPCS_ACCESS_V2,
189 .tx_max_fifo_size = 229376,
190 .rx_max_fifo_size = 229376,
191 .tx_tstamp_workaround = 1,
194 .an_cdr_workaround = 1,
197 static struct axgbe_version_data axgbe_v2b = {
198 .init_function_ptrs_phy_impl = axgbe_init_function_ptrs_phy_v2,
199 .xpcs_access = AXGBE_XPCS_ACCESS_V2,
201 .tx_max_fifo_size = 65536,
202 .rx_max_fifo_size = 65536,
203 .tx_tstamp_workaround = 1,
206 .an_cdr_workaround = 1,
209 static const struct rte_eth_desc_lim rx_desc_lim = {
210 .nb_max = AXGBE_MAX_RING_DESC,
211 .nb_min = AXGBE_MIN_RING_DESC,
215 static const struct rte_eth_desc_lim tx_desc_lim = {
216 .nb_max = AXGBE_MAX_RING_DESC,
217 .nb_min = AXGBE_MIN_RING_DESC,
221 static const struct eth_dev_ops axgbe_eth_dev_ops = {
222 .dev_configure = axgbe_dev_configure,
223 .dev_start = axgbe_dev_start,
224 .dev_stop = axgbe_dev_stop,
225 .dev_close = axgbe_dev_close,
226 .dev_reset = axgbe_dev_reset,
227 .promiscuous_enable = axgbe_dev_promiscuous_enable,
228 .promiscuous_disable = axgbe_dev_promiscuous_disable,
229 .allmulticast_enable = axgbe_dev_allmulticast_enable,
230 .allmulticast_disable = axgbe_dev_allmulticast_disable,
231 .mac_addr_set = axgbe_dev_mac_addr_set,
232 .mac_addr_add = axgbe_dev_mac_addr_add,
233 .mac_addr_remove = axgbe_dev_mac_addr_remove,
234 .set_mc_addr_list = axgbe_dev_set_mc_addr_list,
235 .uc_hash_table_set = axgbe_dev_uc_hash_table_set,
236 .uc_all_hash_table_set = axgbe_dev_uc_all_hash_table_set,
237 .link_update = axgbe_dev_link_update,
238 .get_reg = axgbe_dev_get_regs,
239 .stats_get = axgbe_dev_stats_get,
240 .stats_reset = axgbe_dev_stats_reset,
241 .xstats_get = axgbe_dev_xstats_get,
242 .xstats_reset = axgbe_dev_xstats_reset,
243 .xstats_get_names = axgbe_dev_xstats_get_names,
244 .xstats_get_names_by_id = axgbe_dev_xstats_get_names_by_id,
245 .xstats_get_by_id = axgbe_dev_xstats_get_by_id,
246 .reta_update = axgbe_dev_rss_reta_update,
247 .reta_query = axgbe_dev_rss_reta_query,
248 .rss_hash_update = axgbe_dev_rss_hash_update,
249 .rss_hash_conf_get = axgbe_dev_rss_hash_conf_get,
250 .dev_infos_get = axgbe_dev_info_get,
251 .rx_queue_setup = axgbe_dev_rx_queue_setup,
252 .rx_queue_release = axgbe_dev_rx_queue_release,
253 .tx_queue_setup = axgbe_dev_tx_queue_setup,
254 .tx_queue_release = axgbe_dev_tx_queue_release,
255 .flow_ctrl_get = axgbe_flow_ctrl_get,
256 .flow_ctrl_set = axgbe_flow_ctrl_set,
257 .priority_flow_ctrl_set = axgbe_priority_flow_ctrl_set,
258 .rxq_info_get = axgbe_rxq_info_get,
259 .txq_info_get = axgbe_txq_info_get,
260 .dev_supported_ptypes_get = axgbe_dev_supported_ptypes_get,
261 .mtu_set = axgb_mtu_set,
262 .vlan_filter_set = axgbe_vlan_filter_set,
263 .vlan_tpid_set = axgbe_vlan_tpid_set,
264 .vlan_offload_set = axgbe_vlan_offload_set,
265 .timesync_enable = axgbe_timesync_enable,
266 .timesync_disable = axgbe_timesync_disable,
267 .timesync_read_rx_timestamp = axgbe_timesync_read_rx_timestamp,
268 .timesync_read_tx_timestamp = axgbe_timesync_read_tx_timestamp,
269 .timesync_adjust_time = axgbe_timesync_adjust_time,
270 .timesync_read_time = axgbe_timesync_read_time,
271 .timesync_write_time = axgbe_timesync_write_time,
272 .fw_version_get = axgbe_dev_fw_version_get,
275 static int axgbe_phy_reset(struct axgbe_port *pdata)
277 pdata->phy_link = -1;
278 pdata->phy_speed = SPEED_UNKNOWN;
279 return pdata->phy_if.phy_reset(pdata);
283 * Interrupt handler triggered by NIC for handling
284 * specific interrupt.
287 * Pointer to interrupt handle.
289 * The address of parameter (struct rte_eth_dev *) registered before.
295 axgbe_dev_interrupt_handler(void *param)
297 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
298 struct axgbe_port *pdata = dev->data->dev_private;
299 unsigned int dma_isr, dma_ch_isr;
301 pdata->phy_if.an_isr(pdata);
302 /*DMA related interrupts*/
303 dma_isr = AXGMAC_IOREAD(pdata, DMA_ISR);
304 PMD_DRV_LOG(DEBUG, "DMA_ISR=%#010x\n", dma_isr);
308 AXGMAC_DMA_IOREAD((struct axgbe_rx_queue *)
311 PMD_DRV_LOG(DEBUG, "DMA_CH0_ISR=%#010x\n", dma_ch_isr);
312 AXGMAC_DMA_IOWRITE((struct axgbe_rx_queue *)
314 DMA_CH_SR, dma_ch_isr);
317 /* Unmask interrupts since disabled after generation */
318 rte_intr_ack(pdata->pci_dev->intr_handle);
322 * Configure device link speed and setup link.
323 * It returns 0 on success.
326 axgbe_dev_configure(struct rte_eth_dev *dev)
328 struct axgbe_port *pdata = dev->data->dev_private;
329 /* Checksum offload to hardware */
330 pdata->rx_csum_enable = dev->data->dev_conf.rxmode.offloads &
331 RTE_ETH_RX_OFFLOAD_CHECKSUM;
336 axgbe_dev_rx_mq_config(struct rte_eth_dev *dev)
338 struct axgbe_port *pdata = dev->data->dev_private;
340 if (dev->data->dev_conf.rxmode.mq_mode == RTE_ETH_MQ_RX_RSS)
341 pdata->rss_enable = 1;
342 else if (dev->data->dev_conf.rxmode.mq_mode == RTE_ETH_MQ_RX_NONE)
343 pdata->rss_enable = 0;
350 axgbe_dev_start(struct rte_eth_dev *dev)
352 struct axgbe_port *pdata = dev->data->dev_private;
354 struct rte_eth_dev_data *dev_data = dev->data;
355 uint16_t max_pkt_len;
357 dev->dev_ops = &axgbe_eth_dev_ops;
359 PMD_INIT_FUNC_TRACE();
362 ret = axgbe_dev_rx_mq_config(dev);
364 PMD_DRV_LOG(ERR, "Unable to config RX MQ\n");
367 ret = axgbe_phy_reset(pdata);
369 PMD_DRV_LOG(ERR, "phy reset failed\n");
372 ret = pdata->hw_if.init(pdata);
374 PMD_DRV_LOG(ERR, "dev_init failed\n");
378 /* enable uio/vfio intr/eventfd mapping */
379 rte_intr_enable(pdata->pci_dev->intr_handle);
382 pdata->phy_if.phy_start(pdata);
383 axgbe_dev_enable_tx(dev);
384 axgbe_dev_enable_rx(dev);
386 rte_bit_relaxed_clear32(AXGBE_STOPPED, &pdata->dev_state);
387 rte_bit_relaxed_clear32(AXGBE_DOWN, &pdata->dev_state);
389 max_pkt_len = dev_data->mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN;
390 if ((dev_data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_SCATTER) ||
391 max_pkt_len > pdata->rx_buf_size)
392 dev_data->scattered_rx = 1;
394 /* Scatter Rx handling */
395 if (dev_data->scattered_rx)
396 dev->rx_pkt_burst = ð_axgbe_recv_scattered_pkts;
398 dev->rx_pkt_burst = &axgbe_recv_pkts;
403 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
405 axgbe_dev_stop(struct rte_eth_dev *dev)
407 struct axgbe_port *pdata = dev->data->dev_private;
409 PMD_INIT_FUNC_TRACE();
411 rte_intr_disable(pdata->pci_dev->intr_handle);
413 if (rte_bit_relaxed_get32(AXGBE_STOPPED, &pdata->dev_state))
416 rte_bit_relaxed_set32(AXGBE_STOPPED, &pdata->dev_state);
417 axgbe_dev_disable_tx(dev);
418 axgbe_dev_disable_rx(dev);
420 pdata->phy_if.phy_stop(pdata);
421 pdata->hw_if.exit(pdata);
422 memset(&dev->data->dev_link, 0, sizeof(struct rte_eth_link));
423 rte_bit_relaxed_set32(AXGBE_DOWN, &pdata->dev_state);
429 axgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
431 struct axgbe_port *pdata = dev->data->dev_private;
433 PMD_INIT_FUNC_TRACE();
435 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, 1);
441 axgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
443 struct axgbe_port *pdata = dev->data->dev_private;
445 PMD_INIT_FUNC_TRACE();
447 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, 0);
453 axgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
455 struct axgbe_port *pdata = dev->data->dev_private;
457 PMD_INIT_FUNC_TRACE();
459 if (AXGMAC_IOREAD_BITS(pdata, MAC_PFR, PM))
461 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, 1);
467 axgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
469 struct axgbe_port *pdata = dev->data->dev_private;
471 PMD_INIT_FUNC_TRACE();
473 if (!AXGMAC_IOREAD_BITS(pdata, MAC_PFR, PM))
475 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, 0);
481 axgbe_dev_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr)
483 struct axgbe_port *pdata = dev->data->dev_private;
485 /* Set Default MAC Addr */
486 axgbe_set_mac_addn_addr(pdata, (u8 *)mac_addr, 0);
492 axgbe_dev_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
493 uint32_t index, uint32_t pool __rte_unused)
495 struct axgbe_port *pdata = dev->data->dev_private;
496 struct axgbe_hw_features *hw_feat = &pdata->hw_feat;
498 if (index > hw_feat->addn_mac) {
499 PMD_DRV_LOG(ERR, "Invalid Index %d\n", index);
502 axgbe_set_mac_addn_addr(pdata, (u8 *)mac_addr, index);
507 axgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
508 struct rte_eth_rss_reta_entry64 *reta_conf,
511 struct axgbe_port *pdata = dev->data->dev_private;
512 unsigned int i, idx, shift;
515 if (!pdata->rss_enable) {
516 PMD_DRV_LOG(ERR, "RSS not enabled\n");
520 if (reta_size == 0 || reta_size > AXGBE_RSS_MAX_TABLE_SIZE) {
521 PMD_DRV_LOG(ERR, "reta_size %d is not supported\n", reta_size);
525 for (i = 0; i < reta_size; i++) {
526 idx = i / RTE_ETH_RETA_GROUP_SIZE;
527 shift = i % RTE_ETH_RETA_GROUP_SIZE;
528 if ((reta_conf[idx].mask & (1ULL << shift)) == 0)
530 pdata->rss_table[i] = reta_conf[idx].reta[shift];
533 /* Program the lookup table */
534 ret = axgbe_write_rss_lookup_table(pdata);
539 axgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
540 struct rte_eth_rss_reta_entry64 *reta_conf,
543 struct axgbe_port *pdata = dev->data->dev_private;
544 unsigned int i, idx, shift;
546 if (!pdata->rss_enable) {
547 PMD_DRV_LOG(ERR, "RSS not enabled\n");
551 if (reta_size == 0 || reta_size > AXGBE_RSS_MAX_TABLE_SIZE) {
552 PMD_DRV_LOG(ERR, "reta_size %d is not supported\n", reta_size);
556 for (i = 0; i < reta_size; i++) {
557 idx = i / RTE_ETH_RETA_GROUP_SIZE;
558 shift = i % RTE_ETH_RETA_GROUP_SIZE;
559 if ((reta_conf[idx].mask & (1ULL << shift)) == 0)
561 reta_conf[idx].reta[shift] = pdata->rss_table[i];
567 axgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
568 struct rte_eth_rss_conf *rss_conf)
570 struct axgbe_port *pdata = dev->data->dev_private;
573 if (!pdata->rss_enable) {
574 PMD_DRV_LOG(ERR, "RSS not enabled\n");
578 if (rss_conf == NULL) {
579 PMD_DRV_LOG(ERR, "rss_conf value isn't valid\n");
583 if (rss_conf->rss_key != NULL &&
584 rss_conf->rss_key_len == AXGBE_RSS_HASH_KEY_SIZE) {
585 rte_memcpy(pdata->rss_key, rss_conf->rss_key,
586 AXGBE_RSS_HASH_KEY_SIZE);
587 /* Program the hash key */
588 ret = axgbe_write_rss_hash_key(pdata);
593 pdata->rss_hf = rss_conf->rss_hf & AXGBE_RSS_OFFLOAD;
595 if (pdata->rss_hf & (RTE_ETH_RSS_IPV4 | RTE_ETH_RSS_IPV6))
596 AXGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, IP2TE, 1);
598 (RTE_ETH_RSS_NONFRAG_IPV4_TCP | RTE_ETH_RSS_NONFRAG_IPV6_TCP))
599 AXGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, TCP4TE, 1);
601 (RTE_ETH_RSS_NONFRAG_IPV4_UDP | RTE_ETH_RSS_NONFRAG_IPV6_UDP))
602 AXGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, UDP4TE, 1);
604 /* Set the RSS options */
605 AXGMAC_IOWRITE(pdata, MAC_RSSCR, pdata->rss_options);
611 axgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
612 struct rte_eth_rss_conf *rss_conf)
614 struct axgbe_port *pdata = dev->data->dev_private;
616 if (!pdata->rss_enable) {
617 PMD_DRV_LOG(ERR, "RSS not enabled\n");
621 if (rss_conf == NULL) {
622 PMD_DRV_LOG(ERR, "rss_conf value isn't valid\n");
626 if (rss_conf->rss_key != NULL &&
627 rss_conf->rss_key_len >= AXGBE_RSS_HASH_KEY_SIZE) {
628 rte_memcpy(rss_conf->rss_key, pdata->rss_key,
629 AXGBE_RSS_HASH_KEY_SIZE);
631 rss_conf->rss_key_len = AXGBE_RSS_HASH_KEY_SIZE;
632 rss_conf->rss_hf = pdata->rss_hf;
637 axgbe_dev_reset(struct rte_eth_dev *dev)
641 ret = axgbe_dev_close(dev);
645 ret = eth_axgbe_dev_init(dev);
651 axgbe_dev_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)
653 struct axgbe_port *pdata = dev->data->dev_private;
654 struct axgbe_hw_features *hw_feat = &pdata->hw_feat;
656 if (index > hw_feat->addn_mac) {
657 PMD_DRV_LOG(ERR, "Invalid Index %d\n", index);
660 axgbe_set_mac_addn_addr(pdata, NULL, index);
664 axgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
665 struct rte_ether_addr *mc_addr_set,
668 struct axgbe_port *pdata = dev->data->dev_private;
669 struct axgbe_hw_features *hw_feat = &pdata->hw_feat;
670 uint32_t index = 1; /* 0 is always default mac */
673 if (nb_mc_addr > hw_feat->addn_mac) {
674 PMD_DRV_LOG(ERR, "Invalid Index %d\n", nb_mc_addr);
678 /* clear unicast addresses */
679 for (i = 1; i < hw_feat->addn_mac; i++) {
680 if (rte_is_zero_ether_addr(&dev->data->mac_addrs[i]))
682 memset(&dev->data->mac_addrs[i], 0,
683 sizeof(struct rte_ether_addr));
687 axgbe_set_mac_addn_addr(pdata, (u8 *)mc_addr_set++, index++);
693 axgbe_dev_uc_hash_table_set(struct rte_eth_dev *dev,
694 struct rte_ether_addr *mac_addr, uint8_t add)
696 struct axgbe_port *pdata = dev->data->dev_private;
697 struct axgbe_hw_features *hw_feat = &pdata->hw_feat;
699 if (!hw_feat->hash_table_size) {
700 PMD_DRV_LOG(ERR, "MAC Hash Table not supported\n");
704 axgbe_set_mac_hash_table(pdata, (u8 *)mac_addr, add);
706 if (pdata->uc_hash_mac_addr > 0) {
707 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1);
708 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1);
710 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 0);
711 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 0);
717 axgbe_dev_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t add)
719 struct axgbe_port *pdata = dev->data->dev_private;
720 struct axgbe_hw_features *hw_feat = &pdata->hw_feat;
723 if (!hw_feat->hash_table_size) {
724 PMD_DRV_LOG(ERR, "MAC Hash Table not supported\n");
728 for (index = 0; index < pdata->hash_table_count; index++) {
730 pdata->uc_hash_table[index] = ~0;
732 pdata->uc_hash_table[index] = 0;
734 PMD_DRV_LOG(DEBUG, "%s MAC hash table at Index %#x\n",
735 add ? "set" : "clear", index);
737 AXGMAC_IOWRITE(pdata, MAC_HTR(index),
738 pdata->uc_hash_table[index]);
742 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1);
743 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1);
745 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 0);
746 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 0);
751 /* return 0 means link status changed, -1 means not changed */
753 axgbe_dev_link_update(struct rte_eth_dev *dev,
754 int wait_to_complete __rte_unused)
756 struct axgbe_port *pdata = dev->data->dev_private;
757 struct rte_eth_link link;
760 PMD_INIT_FUNC_TRACE();
763 pdata->phy_if.phy_status(pdata);
765 memset(&link, 0, sizeof(struct rte_eth_link));
766 link.link_duplex = pdata->phy.duplex;
767 link.link_status = pdata->phy_link;
768 link.link_speed = pdata->phy_speed;
769 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
770 RTE_ETH_LINK_SPEED_FIXED);
771 ret = rte_eth_linkstatus_set(dev, &link);
773 PMD_DRV_LOG(ERR, "No change in link status\n");
779 axgbe_dev_get_regs(struct rte_eth_dev *dev, struct rte_dev_reg_info *regs)
781 struct axgbe_port *pdata = dev->data->dev_private;
783 if (regs->data == NULL) {
784 regs->length = axgbe_regs_get_count(pdata);
785 regs->width = sizeof(uint32_t);
789 /* Only full register dump is supported */
791 regs->length != (uint32_t)axgbe_regs_get_count(pdata))
794 regs->version = pdata->pci_dev->id.vendor_id << 16 |
795 pdata->pci_dev->id.device_id;
796 axgbe_regs_dump(pdata, regs->data);
799 static void axgbe_read_mmc_stats(struct axgbe_port *pdata)
801 struct axgbe_mmc_stats *stats = &pdata->mmc_stats;
803 /* Freeze counters */
804 AXGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 1);
807 stats->txoctetcount_gb +=
808 AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_GB_LO);
809 stats->txoctetcount_gb +=
810 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_GB_HI) << 32);
812 stats->txframecount_gb +=
813 AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_GB_LO);
814 stats->txframecount_gb +=
815 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_GB_HI) << 32);
817 stats->txbroadcastframes_g +=
818 AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_G_LO);
819 stats->txbroadcastframes_g +=
820 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_G_HI) << 32);
822 stats->txmulticastframes_g +=
823 AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_G_LO);
824 stats->txmulticastframes_g +=
825 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_G_HI) << 32);
827 stats->tx64octets_gb +=
828 AXGMAC_IOREAD(pdata, MMC_TX64OCTETS_GB_LO);
829 stats->tx64octets_gb +=
830 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX64OCTETS_GB_HI) << 32);
832 stats->tx65to127octets_gb +=
833 AXGMAC_IOREAD(pdata, MMC_TX65TO127OCTETS_GB_LO);
834 stats->tx65to127octets_gb +=
835 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX65TO127OCTETS_GB_HI) << 32);
837 stats->tx128to255octets_gb +=
838 AXGMAC_IOREAD(pdata, MMC_TX128TO255OCTETS_GB_LO);
839 stats->tx128to255octets_gb +=
840 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX128TO255OCTETS_GB_HI) << 32);
842 stats->tx256to511octets_gb +=
843 AXGMAC_IOREAD(pdata, MMC_TX256TO511OCTETS_GB_LO);
844 stats->tx256to511octets_gb +=
845 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX256TO511OCTETS_GB_HI) << 32);
847 stats->tx512to1023octets_gb +=
848 AXGMAC_IOREAD(pdata, MMC_TX512TO1023OCTETS_GB_LO);
849 stats->tx512to1023octets_gb +=
850 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX512TO1023OCTETS_GB_HI) << 32);
852 stats->tx1024tomaxoctets_gb +=
853 AXGMAC_IOREAD(pdata, MMC_TX1024TOMAXOCTETS_GB_LO);
854 stats->tx1024tomaxoctets_gb +=
855 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX1024TOMAXOCTETS_GB_HI) << 32);
857 stats->txunicastframes_gb +=
858 AXGMAC_IOREAD(pdata, MMC_TXUNICASTFRAMES_GB_LO);
859 stats->txunicastframes_gb +=
860 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXUNICASTFRAMES_GB_HI) << 32);
862 stats->txmulticastframes_gb +=
863 AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_GB_LO);
864 stats->txmulticastframes_gb +=
865 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_GB_HI) << 32);
867 stats->txbroadcastframes_g +=
868 AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_GB_LO);
869 stats->txbroadcastframes_g +=
870 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_GB_HI) << 32);
872 stats->txunderflowerror +=
873 AXGMAC_IOREAD(pdata, MMC_TXUNDERFLOWERROR_LO);
874 stats->txunderflowerror +=
875 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXUNDERFLOWERROR_HI) << 32);
877 stats->txoctetcount_g +=
878 AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_G_LO);
879 stats->txoctetcount_g +=
880 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_G_HI) << 32);
882 stats->txframecount_g +=
883 AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_G_LO);
884 stats->txframecount_g +=
885 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_G_HI) << 32);
887 stats->txpauseframes +=
888 AXGMAC_IOREAD(pdata, MMC_TXPAUSEFRAMES_LO);
889 stats->txpauseframes +=
890 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXPAUSEFRAMES_HI) << 32);
892 stats->txvlanframes_g +=
893 AXGMAC_IOREAD(pdata, MMC_TXVLANFRAMES_G_LO);
894 stats->txvlanframes_g +=
895 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXVLANFRAMES_G_HI) << 32);
898 stats->rxframecount_gb +=
899 AXGMAC_IOREAD(pdata, MMC_RXFRAMECOUNT_GB_LO);
900 stats->rxframecount_gb +=
901 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXFRAMECOUNT_GB_HI) << 32);
903 stats->rxoctetcount_gb +=
904 AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_GB_LO);
905 stats->rxoctetcount_gb +=
906 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_GB_HI) << 32);
908 stats->rxoctetcount_g +=
909 AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_G_LO);
910 stats->rxoctetcount_g +=
911 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_G_HI) << 32);
913 stats->rxbroadcastframes_g +=
914 AXGMAC_IOREAD(pdata, MMC_RXBROADCASTFRAMES_G_LO);
915 stats->rxbroadcastframes_g +=
916 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXBROADCASTFRAMES_G_HI) << 32);
918 stats->rxmulticastframes_g +=
919 AXGMAC_IOREAD(pdata, MMC_RXMULTICASTFRAMES_G_LO);
920 stats->rxmulticastframes_g +=
921 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXMULTICASTFRAMES_G_HI) << 32);
924 AXGMAC_IOREAD(pdata, MMC_RXCRCERROR_LO);
926 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXCRCERROR_HI) << 32);
928 stats->rxrunterror +=
929 AXGMAC_IOREAD(pdata, MMC_RXRUNTERROR);
931 stats->rxjabbererror +=
932 AXGMAC_IOREAD(pdata, MMC_RXJABBERERROR);
934 stats->rxundersize_g +=
935 AXGMAC_IOREAD(pdata, MMC_RXUNDERSIZE_G);
937 stats->rxoversize_g +=
938 AXGMAC_IOREAD(pdata, MMC_RXOVERSIZE_G);
940 stats->rx64octets_gb +=
941 AXGMAC_IOREAD(pdata, MMC_RX64OCTETS_GB_LO);
942 stats->rx64octets_gb +=
943 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX64OCTETS_GB_HI) << 32);
945 stats->rx65to127octets_gb +=
946 AXGMAC_IOREAD(pdata, MMC_RX65TO127OCTETS_GB_LO);
947 stats->rx65to127octets_gb +=
948 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX65TO127OCTETS_GB_HI) << 32);
950 stats->rx128to255octets_gb +=
951 AXGMAC_IOREAD(pdata, MMC_RX128TO255OCTETS_GB_LO);
952 stats->rx128to255octets_gb +=
953 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX128TO255OCTETS_GB_HI) << 32);
955 stats->rx256to511octets_gb +=
956 AXGMAC_IOREAD(pdata, MMC_RX256TO511OCTETS_GB_LO);
957 stats->rx256to511octets_gb +=
958 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX256TO511OCTETS_GB_HI) << 32);
960 stats->rx512to1023octets_gb +=
961 AXGMAC_IOREAD(pdata, MMC_RX512TO1023OCTETS_GB_LO);
962 stats->rx512to1023octets_gb +=
963 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX512TO1023OCTETS_GB_HI) << 32);
965 stats->rx1024tomaxoctets_gb +=
966 AXGMAC_IOREAD(pdata, MMC_RX1024TOMAXOCTETS_GB_LO);
967 stats->rx1024tomaxoctets_gb +=
968 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX1024TOMAXOCTETS_GB_HI) << 32);
970 stats->rxunicastframes_g +=
971 AXGMAC_IOREAD(pdata, MMC_RXUNICASTFRAMES_G_LO);
972 stats->rxunicastframes_g +=
973 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXUNICASTFRAMES_G_HI) << 32);
975 stats->rxlengtherror +=
976 AXGMAC_IOREAD(pdata, MMC_RXLENGTHERROR_LO);
977 stats->rxlengtherror +=
978 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXLENGTHERROR_HI) << 32);
980 stats->rxoutofrangetype +=
981 AXGMAC_IOREAD(pdata, MMC_RXOUTOFRANGETYPE_LO);
982 stats->rxoutofrangetype +=
983 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXOUTOFRANGETYPE_HI) << 32);
985 stats->rxpauseframes +=
986 AXGMAC_IOREAD(pdata, MMC_RXPAUSEFRAMES_LO);
987 stats->rxpauseframes +=
988 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXPAUSEFRAMES_HI) << 32);
990 stats->rxfifooverflow +=
991 AXGMAC_IOREAD(pdata, MMC_RXFIFOOVERFLOW_LO);
992 stats->rxfifooverflow +=
993 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXFIFOOVERFLOW_HI) << 32);
995 stats->rxvlanframes_gb +=
996 AXGMAC_IOREAD(pdata, MMC_RXVLANFRAMES_GB_LO);
997 stats->rxvlanframes_gb +=
998 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXVLANFRAMES_GB_HI) << 32);
1000 stats->rxwatchdogerror +=
1001 AXGMAC_IOREAD(pdata, MMC_RXWATCHDOGERROR);
1003 /* Un-freeze counters */
1004 AXGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 0);
1008 axgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats,
1011 struct axgbe_port *pdata = dev->data->dev_private;
1017 axgbe_read_mmc_stats(pdata);
1019 for (i = 0; i < n && i < AXGBE_XSTATS_COUNT; i++) {
1021 stats[i].value = *(u64 *)((uint8_t *)&pdata->mmc_stats +
1022 axgbe_xstats_strings[i].offset);
1029 axgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1030 struct rte_eth_xstat_name *xstats_names,
1035 if (n >= AXGBE_XSTATS_COUNT && xstats_names) {
1036 for (i = 0; i < AXGBE_XSTATS_COUNT; ++i) {
1037 snprintf(xstats_names[i].name,
1038 RTE_ETH_XSTATS_NAME_SIZE, "%s",
1039 axgbe_xstats_strings[i].name);
1043 return AXGBE_XSTATS_COUNT;
1047 axgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1048 uint64_t *values, unsigned int n)
1051 uint64_t values_copy[AXGBE_XSTATS_COUNT];
1054 struct axgbe_port *pdata = dev->data->dev_private;
1056 if (n < AXGBE_XSTATS_COUNT)
1057 return AXGBE_XSTATS_COUNT;
1059 axgbe_read_mmc_stats(pdata);
1061 for (i = 0; i < AXGBE_XSTATS_COUNT; i++) {
1062 values[i] = *(u64 *)((uint8_t *)&pdata->mmc_stats +
1063 axgbe_xstats_strings[i].offset);
1069 axgbe_dev_xstats_get_by_id(dev, NULL, values_copy, AXGBE_XSTATS_COUNT);
1071 for (i = 0; i < n; i++) {
1072 if (ids[i] >= AXGBE_XSTATS_COUNT) {
1073 PMD_DRV_LOG(ERR, "id value isn't valid\n");
1076 values[i] = values_copy[ids[i]];
1082 axgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev,
1083 const uint64_t *ids,
1084 struct rte_eth_xstat_name *xstats_names,
1087 struct rte_eth_xstat_name xstats_names_copy[AXGBE_XSTATS_COUNT];
1091 return axgbe_dev_xstats_get_names(dev, xstats_names, size);
1093 axgbe_dev_xstats_get_names(dev, xstats_names_copy, size);
1095 for (i = 0; i < size; i++) {
1096 if (ids[i] >= AXGBE_XSTATS_COUNT) {
1097 PMD_DRV_LOG(ERR, "id value isn't valid\n");
1100 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
1106 axgbe_dev_xstats_reset(struct rte_eth_dev *dev)
1108 struct axgbe_port *pdata = dev->data->dev_private;
1109 struct axgbe_mmc_stats *stats = &pdata->mmc_stats;
1111 /* MMC registers are configured for reset on read */
1112 axgbe_read_mmc_stats(pdata);
1115 memset(stats, 0, sizeof(*stats));
1121 axgbe_dev_stats_get(struct rte_eth_dev *dev,
1122 struct rte_eth_stats *stats)
1124 struct axgbe_rx_queue *rxq;
1125 struct axgbe_tx_queue *txq;
1126 struct axgbe_port *pdata = dev->data->dev_private;
1127 struct axgbe_mmc_stats *mmc_stats = &pdata->mmc_stats;
1130 axgbe_read_mmc_stats(pdata);
1132 stats->imissed = mmc_stats->rxfifooverflow;
1134 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1135 rxq = dev->data->rx_queues[i];
1137 stats->q_ipackets[i] = rxq->pkts;
1138 stats->ipackets += rxq->pkts;
1139 stats->q_ibytes[i] = rxq->bytes;
1140 stats->ibytes += rxq->bytes;
1141 stats->rx_nombuf += rxq->rx_mbuf_alloc_failed;
1142 stats->q_errors[i] = rxq->errors
1143 + rxq->rx_mbuf_alloc_failed;
1144 stats->ierrors += rxq->errors;
1146 PMD_DRV_LOG(DEBUG, "Rx queue not setup for port %d\n",
1147 dev->data->port_id);
1151 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1152 txq = dev->data->tx_queues[i];
1154 stats->q_opackets[i] = txq->pkts;
1155 stats->opackets += txq->pkts;
1156 stats->q_obytes[i] = txq->bytes;
1157 stats->obytes += txq->bytes;
1158 stats->oerrors += txq->errors;
1160 PMD_DRV_LOG(DEBUG, "Tx queue not setup for port %d\n",
1161 dev->data->port_id);
1169 axgbe_dev_stats_reset(struct rte_eth_dev *dev)
1171 struct axgbe_rx_queue *rxq;
1172 struct axgbe_tx_queue *txq;
1175 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1176 rxq = dev->data->rx_queues[i];
1181 rxq->rx_mbuf_alloc_failed = 0;
1183 PMD_DRV_LOG(DEBUG, "Rx queue not setup for port %d\n",
1184 dev->data->port_id);
1187 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1188 txq = dev->data->tx_queues[i];
1194 PMD_DRV_LOG(DEBUG, "Tx queue not setup for port %d\n",
1195 dev->data->port_id);
1203 axgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1205 struct axgbe_port *pdata = dev->data->dev_private;
1207 dev_info->max_rx_queues = pdata->rx_ring_count;
1208 dev_info->max_tx_queues = pdata->tx_ring_count;
1209 dev_info->min_rx_bufsize = AXGBE_RX_MIN_BUF_SIZE;
1210 dev_info->max_rx_pktlen = AXGBE_RX_MAX_BUF_SIZE;
1211 dev_info->max_mac_addrs = pdata->hw_feat.addn_mac + 1;
1212 dev_info->max_hash_mac_addrs = pdata->hw_feat.hash_table_size;
1213 dev_info->speed_capa = RTE_ETH_LINK_SPEED_10G;
1215 dev_info->rx_offload_capa =
1216 RTE_ETH_RX_OFFLOAD_VLAN_STRIP |
1217 RTE_ETH_RX_OFFLOAD_VLAN_FILTER |
1218 RTE_ETH_RX_OFFLOAD_VLAN_EXTEND |
1219 RTE_ETH_RX_OFFLOAD_IPV4_CKSUM |
1220 RTE_ETH_RX_OFFLOAD_UDP_CKSUM |
1221 RTE_ETH_RX_OFFLOAD_TCP_CKSUM |
1222 RTE_ETH_RX_OFFLOAD_SCATTER |
1223 RTE_ETH_RX_OFFLOAD_KEEP_CRC;
1225 dev_info->tx_offload_capa =
1226 RTE_ETH_TX_OFFLOAD_VLAN_INSERT |
1227 RTE_ETH_TX_OFFLOAD_QINQ_INSERT |
1228 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |
1229 RTE_ETH_TX_OFFLOAD_UDP_CKSUM |
1230 RTE_ETH_TX_OFFLOAD_TCP_CKSUM;
1232 if (pdata->hw_feat.rss) {
1233 dev_info->flow_type_rss_offloads = AXGBE_RSS_OFFLOAD;
1234 dev_info->reta_size = pdata->hw_feat.hash_table_size;
1235 dev_info->hash_key_size = AXGBE_RSS_HASH_KEY_SIZE;
1238 dev_info->rx_desc_lim = rx_desc_lim;
1239 dev_info->tx_desc_lim = tx_desc_lim;
1241 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1242 .rx_free_thresh = AXGBE_RX_FREE_THRESH,
1245 dev_info->default_txconf = (struct rte_eth_txconf) {
1246 .tx_free_thresh = AXGBE_TX_FREE_THRESH,
1253 axgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1255 struct axgbe_port *pdata = dev->data->dev_private;
1256 struct xgbe_fc_info fc = pdata->fc;
1257 unsigned int reg, reg_val = 0;
1260 reg_val = AXGMAC_IOREAD(pdata, reg);
1261 fc.low_water[0] = AXGMAC_MTL_IOREAD_BITS(pdata, 0, MTL_Q_RQFCR, RFA);
1262 fc.high_water[0] = AXGMAC_MTL_IOREAD_BITS(pdata, 0, MTL_Q_RQFCR, RFD);
1263 fc.pause_time[0] = AXGMAC_GET_BITS(reg_val, MAC_Q0TFCR, PT);
1264 fc.autoneg = pdata->pause_autoneg;
1266 if (pdata->rx_pause && pdata->tx_pause)
1267 fc.mode = RTE_ETH_FC_FULL;
1268 else if (pdata->rx_pause)
1269 fc.mode = RTE_ETH_FC_RX_PAUSE;
1270 else if (pdata->tx_pause)
1271 fc.mode = RTE_ETH_FC_TX_PAUSE;
1273 fc.mode = RTE_ETH_FC_NONE;
1275 fc_conf->high_water = (1024 + (fc.low_water[0] << 9)) / 1024;
1276 fc_conf->low_water = (1024 + (fc.high_water[0] << 9)) / 1024;
1277 fc_conf->pause_time = fc.pause_time[0];
1278 fc_conf->send_xon = fc.send_xon;
1279 fc_conf->mode = fc.mode;
1285 axgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1287 struct axgbe_port *pdata = dev->data->dev_private;
1288 struct xgbe_fc_info fc = pdata->fc;
1289 unsigned int reg, reg_val = 0;
1292 pdata->pause_autoneg = fc_conf->autoneg;
1293 pdata->phy.pause_autoneg = pdata->pause_autoneg;
1294 fc.send_xon = fc_conf->send_xon;
1295 AXGMAC_MTL_IOWRITE_BITS(pdata, 0, MTL_Q_RQFCR, RFA,
1296 AXGMAC_FLOW_CONTROL_VALUE(1024 * fc_conf->high_water));
1297 AXGMAC_MTL_IOWRITE_BITS(pdata, 0, MTL_Q_RQFCR, RFD,
1298 AXGMAC_FLOW_CONTROL_VALUE(1024 * fc_conf->low_water));
1299 AXGMAC_SET_BITS(reg_val, MAC_Q0TFCR, PT, fc_conf->pause_time);
1300 AXGMAC_IOWRITE(pdata, reg, reg_val);
1301 fc.mode = fc_conf->mode;
1303 if (fc.mode == RTE_ETH_FC_FULL) {
1304 pdata->tx_pause = 1;
1305 pdata->rx_pause = 1;
1306 } else if (fc.mode == RTE_ETH_FC_RX_PAUSE) {
1307 pdata->tx_pause = 0;
1308 pdata->rx_pause = 1;
1309 } else if (fc.mode == RTE_ETH_FC_TX_PAUSE) {
1310 pdata->tx_pause = 1;
1311 pdata->rx_pause = 0;
1313 pdata->tx_pause = 0;
1314 pdata->rx_pause = 0;
1317 if (pdata->tx_pause != (unsigned int)pdata->phy.tx_pause)
1318 pdata->hw_if.config_tx_flow_control(pdata);
1320 if (pdata->rx_pause != (unsigned int)pdata->phy.rx_pause)
1321 pdata->hw_if.config_rx_flow_control(pdata);
1323 pdata->hw_if.config_flow_control(pdata);
1324 pdata->phy.tx_pause = pdata->tx_pause;
1325 pdata->phy.rx_pause = pdata->rx_pause;
1331 axgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
1332 struct rte_eth_pfc_conf *pfc_conf)
1334 struct axgbe_port *pdata = dev->data->dev_private;
1335 struct xgbe_fc_info fc = pdata->fc;
1338 tc_num = pdata->pfc_map[pfc_conf->priority];
1340 if (pfc_conf->priority >= pdata->hw_feat.tc_cnt) {
1341 PMD_INIT_LOG(ERR, "Max supported traffic class: %d\n",
1342 pdata->hw_feat.tc_cnt);
1346 pdata->pause_autoneg = pfc_conf->fc.autoneg;
1347 pdata->phy.pause_autoneg = pdata->pause_autoneg;
1348 fc.send_xon = pfc_conf->fc.send_xon;
1349 AXGMAC_MTL_IOWRITE_BITS(pdata, tc_num, MTL_Q_RQFCR, RFA,
1350 AXGMAC_FLOW_CONTROL_VALUE(1024 * pfc_conf->fc.high_water));
1351 AXGMAC_MTL_IOWRITE_BITS(pdata, tc_num, MTL_Q_RQFCR, RFD,
1352 AXGMAC_FLOW_CONTROL_VALUE(1024 * pfc_conf->fc.low_water));
1356 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R,
1357 PSTC0, pfc_conf->fc.pause_time);
1360 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R,
1361 PSTC1, pfc_conf->fc.pause_time);
1364 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R,
1365 PSTC2, pfc_conf->fc.pause_time);
1368 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R,
1369 PSTC3, pfc_conf->fc.pause_time);
1372 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R,
1373 PSTC4, pfc_conf->fc.pause_time);
1376 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R,
1377 PSTC5, pfc_conf->fc.pause_time);
1380 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R,
1381 PSTC6, pfc_conf->fc.pause_time);
1384 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R,
1385 PSTC7, pfc_conf->fc.pause_time);
1389 fc.mode = pfc_conf->fc.mode;
1391 if (fc.mode == RTE_ETH_FC_FULL) {
1392 pdata->tx_pause = 1;
1393 pdata->rx_pause = 1;
1394 AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 1);
1395 } else if (fc.mode == RTE_ETH_FC_RX_PAUSE) {
1396 pdata->tx_pause = 0;
1397 pdata->rx_pause = 1;
1398 AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 1);
1399 } else if (fc.mode == RTE_ETH_FC_TX_PAUSE) {
1400 pdata->tx_pause = 1;
1401 pdata->rx_pause = 0;
1402 AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 0);
1404 pdata->tx_pause = 0;
1405 pdata->rx_pause = 0;
1406 AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 0);
1409 if (pdata->tx_pause != (unsigned int)pdata->phy.tx_pause)
1410 pdata->hw_if.config_tx_flow_control(pdata);
1412 if (pdata->rx_pause != (unsigned int)pdata->phy.rx_pause)
1413 pdata->hw_if.config_rx_flow_control(pdata);
1414 pdata->hw_if.config_flow_control(pdata);
1415 pdata->phy.tx_pause = pdata->tx_pause;
1416 pdata->phy.rx_pause = pdata->rx_pause;
1422 axgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1423 struct rte_eth_rxq_info *qinfo)
1425 struct axgbe_rx_queue *rxq;
1427 rxq = dev->data->rx_queues[queue_id];
1428 qinfo->mp = rxq->mb_pool;
1429 qinfo->scattered_rx = dev->data->scattered_rx;
1430 qinfo->nb_desc = rxq->nb_desc;
1431 qinfo->conf.rx_free_thresh = rxq->free_thresh;
1435 axgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1436 struct rte_eth_txq_info *qinfo)
1438 struct axgbe_tx_queue *txq;
1440 txq = dev->data->tx_queues[queue_id];
1441 qinfo->nb_desc = txq->nb_desc;
1442 qinfo->conf.tx_free_thresh = txq->free_thresh;
1445 axgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1447 static const uint32_t ptypes[] = {
1449 RTE_PTYPE_L2_ETHER_TIMESYNC,
1450 RTE_PTYPE_L2_ETHER_LLDP,
1451 RTE_PTYPE_L2_ETHER_ARP,
1452 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1453 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1456 RTE_PTYPE_L4_NONFRAG,
1460 RTE_PTYPE_TUNNEL_GRENAT,
1461 RTE_PTYPE_TUNNEL_IP,
1462 RTE_PTYPE_INNER_L2_ETHER,
1463 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1464 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1465 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1466 RTE_PTYPE_INNER_L4_FRAG,
1467 RTE_PTYPE_INNER_L4_ICMP,
1468 RTE_PTYPE_INNER_L4_NONFRAG,
1469 RTE_PTYPE_INNER_L4_SCTP,
1470 RTE_PTYPE_INNER_L4_TCP,
1471 RTE_PTYPE_INNER_L4_UDP,
1475 if (dev->rx_pkt_burst == axgbe_recv_pkts)
1480 static int axgb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1482 struct axgbe_port *pdata = dev->data->dev_private;
1485 /* mtu setting is forbidden if port is start */
1486 if (dev->data->dev_started) {
1487 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
1488 dev->data->port_id);
1491 val = mtu > RTE_ETHER_MTU ? 1 : 0;
1492 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, JE, val);
1498 axgbe_update_tstamp_time(struct axgbe_port *pdata,
1499 unsigned int sec, unsigned int nsec, int addsub)
1501 unsigned int count = 100;
1502 uint32_t sub_val = 0;
1503 uint32_t sub_val_sec = 0xFFFFFFFF;
1504 uint32_t sub_val_nsec = 0x3B9ACA00;
1508 sub_val = sub_val_sec - (sec - 1);
1512 AXGMAC_IOWRITE(pdata, MAC_STSUR, sub_val);
1513 sub_val = sub_val_nsec - nsec;
1514 AXGMAC_IOWRITE(pdata, MAC_STNUR, sub_val);
1515 AXGMAC_IOWRITE_BITS(pdata, MAC_STNUR, ADDSUB, 1);
1517 AXGMAC_IOWRITE(pdata, MAC_STSUR, sec);
1518 AXGMAC_IOWRITE_BITS(pdata, MAC_STNUR, ADDSUB, 0);
1519 AXGMAC_IOWRITE(pdata, MAC_STNUR, nsec);
1521 AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSUPDT, 1);
1522 /* Wait for time update to complete */
1523 while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSUPDT))
1527 static inline uint64_t
1528 div_u64_rem(uint64_t dividend, uint32_t divisor, uint32_t *remainder)
1530 *remainder = dividend % divisor;
1531 return dividend / divisor;
1534 static inline uint64_t
1535 div_u64(uint64_t dividend, uint32_t divisor)
1538 return div_u64_rem(dividend, divisor, &remainder);
1542 axgbe_adjfreq(struct axgbe_port *pdata, int64_t delta)
1545 uint32_t addend, diff;
1546 unsigned int neg_adjust = 0;
1552 adjust = (uint64_t)pdata->tstamp_addend;
1554 diff = (uint32_t)div_u64(adjust, 1000000000UL);
1555 addend = (neg_adjust) ? pdata->tstamp_addend - diff :
1556 pdata->tstamp_addend + diff;
1557 pdata->tstamp_addend = addend;
1558 axgbe_update_tstamp_addend(pdata, addend);
1563 axgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
1565 struct axgbe_port *pdata = dev->data->dev_private;
1566 struct timespec timestamp_delta;
1568 axgbe_adjfreq(pdata, delta);
1569 pdata->systime_tc.nsec += delta;
1573 timestamp_delta = rte_ns_to_timespec(delta);
1574 axgbe_update_tstamp_time(pdata, timestamp_delta.tv_sec,
1575 timestamp_delta.tv_nsec, 1);
1577 timestamp_delta = rte_ns_to_timespec(delta);
1578 axgbe_update_tstamp_time(pdata, timestamp_delta.tv_sec,
1579 timestamp_delta.tv_nsec, 0);
1585 axgbe_timesync_read_time(struct rte_eth_dev *dev,
1586 struct timespec *timestamp)
1589 struct axgbe_port *pdata = dev->data->dev_private;
1591 nsec = AXGMAC_IOREAD(pdata, MAC_STSR);
1592 nsec *= NSEC_PER_SEC;
1593 nsec += AXGMAC_IOREAD(pdata, MAC_STNR);
1594 *timestamp = rte_ns_to_timespec(nsec);
1598 axgbe_timesync_write_time(struct rte_eth_dev *dev,
1599 const struct timespec *timestamp)
1601 unsigned int count = 100;
1602 struct axgbe_port *pdata = dev->data->dev_private;
1604 AXGMAC_IOWRITE(pdata, MAC_STSUR, timestamp->tv_sec);
1605 AXGMAC_IOWRITE(pdata, MAC_STNUR, timestamp->tv_nsec);
1606 AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSUPDT, 1);
1607 /* Wait for time update to complete */
1608 while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSUPDT))
1611 PMD_DRV_LOG(ERR, "Timed out update timestamp\n");
1616 axgbe_update_tstamp_addend(struct axgbe_port *pdata,
1619 unsigned int count = 100;
1621 AXGMAC_IOWRITE(pdata, MAC_TSAR, addend);
1622 AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 1);
1624 /* Wait for addend update to complete */
1625 while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSADDREG))
1628 PMD_DRV_LOG(ERR, "Timed out updating timestamp addend register\n");
1632 axgbe_set_tstamp_time(struct axgbe_port *pdata, unsigned int sec,
1635 unsigned int count = 100;
1637 /*System Time Sec Update*/
1638 AXGMAC_IOWRITE(pdata, MAC_STSUR, sec);
1639 /*System Time nanoSec Update*/
1640 AXGMAC_IOWRITE(pdata, MAC_STNUR, nsec);
1641 /*Initialize Timestamp*/
1642 AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSINIT, 1);
1644 /* Wait for time update to complete */
1645 while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSINIT))
1648 PMD_DRV_LOG(ERR, "Timed out initializing timestamp\n");
1652 axgbe_timesync_enable(struct rte_eth_dev *dev)
1654 struct axgbe_port *pdata = dev->data->dev_private;
1655 unsigned int mac_tscr = 0;
1657 struct timespec timestamp;
1660 /* Set one nano-second accuracy */
1661 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCTRLSSR, 1);
1663 /* Set fine timestamp update */
1664 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 1);
1666 /* Overwrite earlier timestamps */
1667 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TXTSSTSM, 1);
1669 AXGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr);
1671 /* Enabling processing of ptp over eth pkt */
1672 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1673 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1674 /* Enable timestamp for all pkts*/
1675 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 1);
1677 /* enabling timestamp */
1678 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1679 AXGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr);
1681 /* Exit if timestamping is not enabled */
1682 if (!AXGMAC_GET_BITS(mac_tscr, MAC_TSCR, TSENA)) {
1683 PMD_DRV_LOG(ERR, "Exiting as timestamp is not enabled\n");
1687 /* Sub-second Increment Value*/
1688 AXGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SSINC, AXGBE_TSTAMP_SSINC);
1689 /* Sub-nanosecond Increment Value */
1690 AXGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SNSINC, AXGBE_TSTAMP_SNSINC);
1692 pdata->ptpclk_rate = AXGBE_V2_PTP_CLOCK_FREQ;
1693 dividend = 50000000;
1695 pdata->tstamp_addend = div_u64(dividend, pdata->ptpclk_rate);
1697 axgbe_update_tstamp_addend(pdata, pdata->tstamp_addend);
1698 axgbe_set_tstamp_time(pdata, 0, 0);
1700 /* Initialize the timecounter */
1701 memset(&pdata->systime_tc, 0, sizeof(struct rte_timecounter));
1703 pdata->systime_tc.cc_mask = AXGBE_CYCLECOUNTER_MASK;
1704 pdata->systime_tc.cc_shift = 0;
1705 pdata->systime_tc.nsec_mask = 0;
1707 PMD_DRV_LOG(DEBUG, "Initializing system time counter with realtime\n");
1709 /* Updating the counter once with clock real time */
1710 clock_gettime(CLOCK_REALTIME, ×tamp);
1711 nsec = rte_timespec_to_ns(×tamp);
1712 nsec = rte_timecounter_update(&pdata->systime_tc, nsec);
1713 axgbe_set_tstamp_time(pdata, timestamp.tv_sec, timestamp.tv_nsec);
1718 axgbe_timesync_disable(struct rte_eth_dev *dev)
1720 struct axgbe_port *pdata = dev->data->dev_private;
1721 unsigned int mac_tscr = 0;
1723 /*disable timestamp for all pkts*/
1724 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 0);
1725 /*disable the addened register*/
1726 AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 0);
1727 /* disable timestamp update */
1728 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 0);
1729 /*disable time stamp*/
1730 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 0);
1735 axgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
1736 struct timespec *timestamp, uint32_t flags)
1739 volatile union axgbe_rx_desc *desc;
1741 struct axgbe_rx_queue *rxq = *dev->data->rx_queues;
1743 idx = AXGBE_GET_DESC_IDX(rxq, rxq->cur);
1744 desc = &rxq->desc[idx];
1746 while (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, OWN))
1748 if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, CTXT)) {
1749 if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_CONTEXT_DESC3, TSA) &&
1750 !AXGMAC_GET_BITS_LE(desc->write.desc3,
1751 RX_CONTEXT_DESC3, TSD)) {
1752 pmt = AXGMAC_GET_BITS_LE(desc->write.desc3,
1753 RX_CONTEXT_DESC3, PMT);
1754 nsec = rte_le_to_cpu_32(desc->write.desc1);
1755 nsec *= NSEC_PER_SEC;
1756 nsec += rte_le_to_cpu_32(desc->write.desc0);
1757 if (nsec != 0xffffffffffffffffULL) {
1759 *timestamp = rte_ns_to_timespec(nsec);
1761 "flags = 0x%x nsec = %"PRIu64"\n",
1771 axgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
1772 struct timespec *timestamp)
1775 struct axgbe_port *pdata = dev->data->dev_private;
1776 unsigned int tx_snr, tx_ssr;
1779 if (pdata->vdata->tx_tstamp_workaround) {
1780 tx_snr = AXGMAC_IOREAD(pdata, MAC_TXSNR);
1781 tx_ssr = AXGMAC_IOREAD(pdata, MAC_TXSSR);
1784 tx_ssr = AXGMAC_IOREAD(pdata, MAC_TXSSR);
1785 tx_snr = AXGMAC_IOREAD(pdata, MAC_TXSNR);
1787 if (AXGMAC_GET_BITS(tx_snr, MAC_TXSNR, TXTSSTSMIS)) {
1788 PMD_DRV_LOG(DEBUG, "Waiting for TXTSSTSMIS\n");
1792 nsec *= NSEC_PER_SEC;
1794 PMD_DRV_LOG(DEBUG, "nsec = %"PRIu64" tx_ssr = %d tx_snr = %d\n",
1795 nsec, tx_ssr, tx_snr);
1796 *timestamp = rte_ns_to_timespec(nsec);
1801 axgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vid, int on)
1803 struct axgbe_port *pdata = dev->data->dev_private;
1804 unsigned long vid_bit, vid_idx;
1806 vid_bit = VLAN_TABLE_BIT(vid);
1807 vid_idx = VLAN_TABLE_IDX(vid);
1810 PMD_DRV_LOG(DEBUG, "Set VLAN vid=%d for device = %s\n",
1811 vid, pdata->eth_dev->device->name);
1812 pdata->active_vlans[vid_idx] |= vid_bit;
1814 PMD_DRV_LOG(DEBUG, "Reset VLAN vid=%d for device = %s\n",
1815 vid, pdata->eth_dev->device->name);
1816 pdata->active_vlans[vid_idx] &= ~vid_bit;
1818 pdata->hw_if.update_vlan_hash_table(pdata);
1823 axgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1824 enum rte_vlan_type vlan_type,
1827 struct axgbe_port *pdata = dev->data->dev_private;
1831 qinq = AXGMAC_IOREAD_BITS(pdata, MAC_VLANTR, EDVLP);
1832 PMD_DRV_LOG(DEBUG, "EDVLP: qinq = 0x%x\n", qinq);
1834 switch (vlan_type) {
1835 case RTE_ETH_VLAN_TYPE_INNER:
1836 PMD_DRV_LOG(DEBUG, "RTE_ETH_VLAN_TYPE_INNER\n");
1838 if (tpid != 0x8100 && tpid != 0x88a8)
1840 "tag supported 0x8100/0x88A8\n");
1841 PMD_DRV_LOG(DEBUG, "qinq with inner tag\n");
1843 /*Enable Inner VLAN Tag */
1844 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ERIVLT, 1);
1845 reg = AXGMAC_IOREAD_BITS(pdata, MAC_VLANTR, ERIVLT);
1846 PMD_DRV_LOG(DEBUG, "bit ERIVLT = 0x%x\n", reg);
1850 "Inner type not supported in single tag\n");
1853 case RTE_ETH_VLAN_TYPE_OUTER:
1854 PMD_DRV_LOG(DEBUG, "RTE_ETH_VLAN_TYPE_OUTER\n");
1856 PMD_DRV_LOG(DEBUG, "double tagging is enabled\n");
1857 /*Enable outer VLAN tag*/
1858 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ERIVLT, 0);
1859 reg = AXGMAC_IOREAD_BITS(pdata, MAC_VLANTR, ERIVLT);
1860 PMD_DRV_LOG(DEBUG, "bit ERIVLT = 0x%x\n", reg);
1862 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, CSVL, 1);
1863 reg = AXGMAC_IOREAD_BITS(pdata, MAC_VLANIR, CSVL);
1864 PMD_DRV_LOG(DEBUG, "bit CSVL = 0x%x\n", reg);
1866 if (tpid != 0x8100 && tpid != 0x88a8)
1868 "tag supported 0x8100/0x88A8\n");
1871 case RTE_ETH_VLAN_TYPE_MAX:
1872 PMD_DRV_LOG(ERR, "RTE_ETH_VLAN_TYPE_MAX\n");
1874 case RTE_ETH_VLAN_TYPE_UNKNOWN:
1875 PMD_DRV_LOG(ERR, "RTE_ETH_VLAN_TYPE_UNKNOWN\n");
1881 static void axgbe_vlan_extend_enable(struct axgbe_port *pdata)
1885 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EDVLP, 1);
1886 qinq = AXGMAC_IOREAD_BITS(pdata, MAC_VLANTR, EDVLP);
1887 PMD_DRV_LOG(DEBUG, "vlan double tag enabled EDVLP:qinq=0x%x\n", qinq);
1890 static void axgbe_vlan_extend_disable(struct axgbe_port *pdata)
1894 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EDVLP, 0);
1895 qinq = AXGMAC_IOREAD_BITS(pdata, MAC_VLANTR, EDVLP);
1896 PMD_DRV_LOG(DEBUG, "vlan double tag disable EDVLP:qinq=0x%x\n", qinq);
1900 axgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1902 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
1903 struct axgbe_port *pdata = dev->data->dev_private;
1905 /* Indicate that VLAN Tx CTAGs come from context descriptors */
1906 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, CSVL, 0);
1907 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, VLTI, 1);
1909 if (mask & RTE_ETH_VLAN_STRIP_MASK) {
1910 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) {
1911 PMD_DRV_LOG(DEBUG, "Strip ON for device = %s\n",
1912 pdata->eth_dev->device->name);
1913 pdata->hw_if.enable_rx_vlan_stripping(pdata);
1915 PMD_DRV_LOG(DEBUG, "Strip OFF for device = %s\n",
1916 pdata->eth_dev->device->name);
1917 pdata->hw_if.disable_rx_vlan_stripping(pdata);
1920 if (mask & RTE_ETH_VLAN_FILTER_MASK) {
1921 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) {
1922 PMD_DRV_LOG(DEBUG, "Filter ON for device = %s\n",
1923 pdata->eth_dev->device->name);
1924 pdata->hw_if.enable_rx_vlan_filtering(pdata);
1926 PMD_DRV_LOG(DEBUG, "Filter OFF for device = %s\n",
1927 pdata->eth_dev->device->name);
1928 pdata->hw_if.disable_rx_vlan_filtering(pdata);
1931 if (mask & RTE_ETH_VLAN_EXTEND_MASK) {
1932 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_EXTEND) {
1933 PMD_DRV_LOG(DEBUG, "enabling vlan extended mode\n");
1934 axgbe_vlan_extend_enable(pdata);
1935 /* Set global registers with default ethertype*/
1936 axgbe_vlan_tpid_set(dev, RTE_ETH_VLAN_TYPE_OUTER,
1937 RTE_ETHER_TYPE_VLAN);
1938 axgbe_vlan_tpid_set(dev, RTE_ETH_VLAN_TYPE_INNER,
1939 RTE_ETHER_TYPE_VLAN);
1941 PMD_DRV_LOG(DEBUG, "disabling vlan extended mode\n");
1942 axgbe_vlan_extend_disable(pdata);
1948 static void axgbe_get_all_hw_features(struct axgbe_port *pdata)
1950 unsigned int mac_hfr0, mac_hfr1, mac_hfr2, mac_hfr3;
1951 struct axgbe_hw_features *hw_feat = &pdata->hw_feat;
1953 mac_hfr0 = AXGMAC_IOREAD(pdata, MAC_HWF0R);
1954 mac_hfr1 = AXGMAC_IOREAD(pdata, MAC_HWF1R);
1955 mac_hfr2 = AXGMAC_IOREAD(pdata, MAC_HWF2R);
1956 mac_hfr3 = AXGMAC_IOREAD(pdata, MAC_HWF3R);
1958 memset(hw_feat, 0, sizeof(*hw_feat));
1960 hw_feat->version = AXGMAC_IOREAD(pdata, MAC_VR);
1962 /* Hardware feature register 0 */
1963 hw_feat->gmii = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL);
1964 hw_feat->vlhash = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH);
1965 hw_feat->sma = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SMASEL);
1966 hw_feat->rwk = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RWKSEL);
1967 hw_feat->mgk = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MGKSEL);
1968 hw_feat->mmc = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MMCSEL);
1969 hw_feat->aoe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ARPOFFSEL);
1970 hw_feat->ts = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSEL);
1971 hw_feat->eee = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, EEESEL);
1972 hw_feat->tx_coe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TXCOESEL);
1973 hw_feat->rx_coe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RXCOESEL);
1974 hw_feat->addn_mac = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R,
1976 hw_feat->ts_src = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSTSSEL);
1977 hw_feat->sa_vlan_ins = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SAVLANINS);
1979 /* Hardware feature register 1 */
1980 hw_feat->rx_fifo_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
1982 hw_feat->tx_fifo_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
1984 hw_feat->adv_ts_hi = AXGMAC_GET_BITS(mac_hfr1,
1985 MAC_HWF1R, ADVTHWORD);
1986 hw_feat->dma_width = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADDR64);
1987 hw_feat->dcb = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN);
1988 hw_feat->sph = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN);
1989 hw_feat->tso = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN);
1990 hw_feat->dma_debug = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA);
1991 hw_feat->rss = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, RSSEN);
1992 hw_feat->tc_cnt = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC);
1993 hw_feat->hash_table_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
1995 hw_feat->l3l4_filter_num = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
1998 /* Hardware feature register 2 */
1999 hw_feat->rx_q_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXQCNT);
2000 hw_feat->tx_q_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXQCNT);
2001 hw_feat->rx_ch_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXCHCNT);
2002 hw_feat->tx_ch_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXCHCNT);
2003 hw_feat->pps_out_num = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM);
2004 hw_feat->aux_snap_num = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R,
2007 /* Hardware feature register 3 */
2008 hw_feat->tx_q_vlan_tag_ins = AXGMAC_GET_BITS(mac_hfr3,
2009 MAC_HWF3R, CBTISEL);
2010 hw_feat->no_of_vlan_extn = AXGMAC_GET_BITS(mac_hfr3,
2013 /* Translate the Hash Table size into actual number */
2014 switch (hw_feat->hash_table_size) {
2018 hw_feat->hash_table_size = 64;
2021 hw_feat->hash_table_size = 128;
2024 hw_feat->hash_table_size = 256;
2028 /* Translate the address width setting into actual number */
2029 switch (hw_feat->dma_width) {
2031 hw_feat->dma_width = 32;
2034 hw_feat->dma_width = 40;
2037 hw_feat->dma_width = 48;
2040 hw_feat->dma_width = 32;
2043 /* The Queue, Channel and TC counts are zero based so increment them
2044 * to get the actual number
2046 hw_feat->rx_q_cnt++;
2047 hw_feat->tx_q_cnt++;
2048 hw_feat->rx_ch_cnt++;
2049 hw_feat->tx_ch_cnt++;
2052 /* Translate the fifo sizes into actual numbers */
2053 hw_feat->rx_fifo_size = 1 << (hw_feat->rx_fifo_size + 7);
2054 hw_feat->tx_fifo_size = 1 << (hw_feat->tx_fifo_size + 7);
2057 static void axgbe_init_all_fptrs(struct axgbe_port *pdata)
2059 axgbe_init_function_ptrs_dev(&pdata->hw_if);
2060 axgbe_init_function_ptrs_phy(&pdata->phy_if);
2061 axgbe_init_function_ptrs_i2c(&pdata->i2c_if);
2062 pdata->vdata->init_function_ptrs_phy_impl(&pdata->phy_if);
2065 static void axgbe_set_counts(struct axgbe_port *pdata)
2067 /* Set all the function pointers */
2068 axgbe_init_all_fptrs(pdata);
2070 /* Populate the hardware features */
2071 axgbe_get_all_hw_features(pdata);
2073 /* Set default max values if not provided */
2074 if (!pdata->tx_max_channel_count)
2075 pdata->tx_max_channel_count = pdata->hw_feat.tx_ch_cnt;
2076 if (!pdata->rx_max_channel_count)
2077 pdata->rx_max_channel_count = pdata->hw_feat.rx_ch_cnt;
2079 if (!pdata->tx_max_q_count)
2080 pdata->tx_max_q_count = pdata->hw_feat.tx_q_cnt;
2081 if (!pdata->rx_max_q_count)
2082 pdata->rx_max_q_count = pdata->hw_feat.rx_q_cnt;
2084 /* Calculate the number of Tx and Rx rings to be created
2085 * -Tx (DMA) Channels map 1-to-1 to Tx Queues so set
2086 * the number of Tx queues to the number of Tx channels
2088 * -Rx (DMA) Channels do not map 1-to-1 so use the actual
2089 * number of Rx queues or maximum allowed
2091 pdata->tx_ring_count = RTE_MIN(pdata->hw_feat.tx_ch_cnt,
2092 pdata->tx_max_channel_count);
2093 pdata->tx_ring_count = RTE_MIN(pdata->tx_ring_count,
2094 pdata->tx_max_q_count);
2096 pdata->tx_q_count = pdata->tx_ring_count;
2098 pdata->rx_ring_count = RTE_MIN(pdata->hw_feat.rx_ch_cnt,
2099 pdata->rx_max_channel_count);
2101 pdata->rx_q_count = RTE_MIN(pdata->hw_feat.rx_q_cnt,
2102 pdata->rx_max_q_count);
2105 static void axgbe_default_config(struct axgbe_port *pdata)
2107 pdata->pblx8 = DMA_PBL_X8_ENABLE;
2108 pdata->tx_sf_mode = MTL_TSF_ENABLE;
2109 pdata->tx_threshold = MTL_TX_THRESHOLD_64;
2110 pdata->tx_pbl = DMA_PBL_32;
2111 pdata->tx_osp_mode = DMA_OSP_ENABLE;
2112 pdata->rx_sf_mode = MTL_RSF_ENABLE;
2113 pdata->rx_threshold = MTL_RX_THRESHOLD_64;
2114 pdata->rx_pbl = DMA_PBL_32;
2115 pdata->pause_autoneg = 1;
2116 pdata->tx_pause = 0;
2117 pdata->rx_pause = 0;
2118 pdata->phy_speed = SPEED_UNKNOWN;
2119 pdata->power_down = 0;
2123 * Return PCI root complex device id on success else 0
2126 get_pci_rc_devid(void)
2128 char pci_sysfs[PATH_MAX];
2129 const struct rte_pci_addr pci_rc_addr = {0, 0, 0, 0};
2130 unsigned long device_id;
2132 snprintf(pci_sysfs, sizeof(pci_sysfs), "%s/" PCI_PRI_FMT "/device",
2133 rte_pci_get_sysfs_path(), pci_rc_addr.domain,
2134 pci_rc_addr.bus, pci_rc_addr.devid, pci_rc_addr.function);
2137 if (eal_parse_sysfs_value(pci_sysfs, &device_id) < 0) {
2138 PMD_INIT_LOG(ERR, "Error in reading PCI sysfs\n");
2142 return (uint16_t)device_id;
2146 * It returns 0 on success.
2149 eth_axgbe_dev_init(struct rte_eth_dev *eth_dev)
2151 PMD_INIT_FUNC_TRACE();
2152 struct axgbe_port *pdata;
2153 struct rte_pci_device *pci_dev;
2154 uint32_t reg, mac_lo, mac_hi;
2158 eth_dev->dev_ops = &axgbe_eth_dev_ops;
2160 eth_dev->rx_descriptor_status = axgbe_dev_rx_descriptor_status;
2161 eth_dev->tx_descriptor_status = axgbe_dev_tx_descriptor_status;
2164 * For secondary processes, we don't initialise any further as primary
2165 * has already done this work.
2167 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2170 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2172 pdata = eth_dev->data->dev_private;
2174 rte_bit_relaxed_set32(AXGBE_DOWN, &pdata->dev_state);
2175 rte_bit_relaxed_set32(AXGBE_STOPPED, &pdata->dev_state);
2176 pdata->eth_dev = eth_dev;
2178 pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
2179 pdata->pci_dev = pci_dev;
2182 * Use root complex device ID to differentiate RV AXGBE vs SNOWY AXGBE
2184 if ((get_pci_rc_devid()) == AMD_PCI_RV_ROOT_COMPLEX_ID) {
2185 pdata->xpcs_window_def_reg = PCS_V2_RV_WINDOW_DEF;
2186 pdata->xpcs_window_sel_reg = PCS_V2_RV_WINDOW_SELECT;
2188 pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF;
2189 pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT;
2193 (void *)pci_dev->mem_resource[AXGBE_AXGMAC_BAR].addr;
2194 pdata->xprop_regs = (void *)((uint8_t *)pdata->xgmac_regs
2195 + AXGBE_MAC_PROP_OFFSET);
2196 pdata->xi2c_regs = (void *)((uint8_t *)pdata->xgmac_regs
2197 + AXGBE_I2C_CTRL_OFFSET);
2198 pdata->xpcs_regs = (void *)pci_dev->mem_resource[AXGBE_XPCS_BAR].addr;
2200 /* version specific driver data*/
2201 if (pci_dev->id.device_id == AMD_PCI_AXGBE_DEVICE_V2A)
2202 pdata->vdata = &axgbe_v2a;
2204 pdata->vdata = &axgbe_v2b;
2206 /* Configure the PCS indirect addressing support */
2207 reg = XPCS32_IOREAD(pdata, pdata->xpcs_window_def_reg);
2208 pdata->xpcs_window = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, OFFSET);
2209 pdata->xpcs_window <<= 6;
2210 pdata->xpcs_window_size = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, SIZE);
2211 pdata->xpcs_window_size = 1 << (pdata->xpcs_window_size + 7);
2212 pdata->xpcs_window_mask = pdata->xpcs_window_size - 1;
2215 "xpcs window :%x, size :%x, mask :%x ", pdata->xpcs_window,
2216 pdata->xpcs_window_size, pdata->xpcs_window_mask);
2217 XP_IOWRITE(pdata, XP_INT_EN, 0x1fffff);
2219 /* Retrieve the MAC address */
2220 mac_lo = XP_IOREAD(pdata, XP_MAC_ADDR_LO);
2221 mac_hi = XP_IOREAD(pdata, XP_MAC_ADDR_HI);
2222 pdata->mac_addr.addr_bytes[0] = mac_lo & 0xff;
2223 pdata->mac_addr.addr_bytes[1] = (mac_lo >> 8) & 0xff;
2224 pdata->mac_addr.addr_bytes[2] = (mac_lo >> 16) & 0xff;
2225 pdata->mac_addr.addr_bytes[3] = (mac_lo >> 24) & 0xff;
2226 pdata->mac_addr.addr_bytes[4] = mac_hi & 0xff;
2227 pdata->mac_addr.addr_bytes[5] = (mac_hi >> 8) & 0xff;
2229 len = RTE_ETHER_ADDR_LEN * AXGBE_MAX_MAC_ADDRS;
2230 eth_dev->data->mac_addrs = rte_zmalloc("axgbe_mac_addr", len, 0);
2232 if (!eth_dev->data->mac_addrs) {
2234 "Failed to alloc %u bytes needed to "
2235 "store MAC addresses", len);
2239 /* Allocate memory for storing hash filter MAC addresses */
2240 len = RTE_ETHER_ADDR_LEN * AXGBE_MAX_HASH_MAC_ADDRS;
2241 eth_dev->data->hash_mac_addrs = rte_zmalloc("axgbe_hash_mac_addr",
2244 if (eth_dev->data->hash_mac_addrs == NULL) {
2246 "Failed to allocate %d bytes needed to "
2247 "store MAC addresses", len);
2251 if (!rte_is_valid_assigned_ether_addr(&pdata->mac_addr))
2252 rte_eth_random_addr(pdata->mac_addr.addr_bytes);
2254 /* Copy the permanent MAC address */
2255 rte_ether_addr_copy(&pdata->mac_addr, ð_dev->data->mac_addrs[0]);
2257 /* Clock settings */
2258 pdata->sysclk_rate = AXGBE_V2_DMA_CLOCK_FREQ;
2259 pdata->ptpclk_rate = AXGBE_V2_PTP_CLOCK_FREQ;
2261 /* Set the DMA coherency values */
2262 pdata->coherent = 1;
2263 pdata->axdomain = AXGBE_DMA_OS_AXDOMAIN;
2264 pdata->arcache = AXGBE_DMA_OS_ARCACHE;
2265 pdata->awcache = AXGBE_DMA_OS_AWCACHE;
2267 /* Set the maximum channels and queues */
2268 reg = XP_IOREAD(pdata, XP_PROP_1);
2269 pdata->tx_max_channel_count = XP_GET_BITS(reg, XP_PROP_1, MAX_TX_DMA);
2270 pdata->rx_max_channel_count = XP_GET_BITS(reg, XP_PROP_1, MAX_RX_DMA);
2271 pdata->tx_max_q_count = XP_GET_BITS(reg, XP_PROP_1, MAX_TX_QUEUES);
2272 pdata->rx_max_q_count = XP_GET_BITS(reg, XP_PROP_1, MAX_RX_QUEUES);
2274 /* Set the hardware channel and queue counts */
2275 axgbe_set_counts(pdata);
2277 /* Set the maximum fifo amounts */
2278 reg = XP_IOREAD(pdata, XP_PROP_2);
2279 pdata->tx_max_fifo_size = XP_GET_BITS(reg, XP_PROP_2, TX_FIFO_SIZE);
2280 pdata->tx_max_fifo_size *= 16384;
2281 pdata->tx_max_fifo_size = RTE_MIN(pdata->tx_max_fifo_size,
2282 pdata->vdata->tx_max_fifo_size);
2283 pdata->rx_max_fifo_size = XP_GET_BITS(reg, XP_PROP_2, RX_FIFO_SIZE);
2284 pdata->rx_max_fifo_size *= 16384;
2285 pdata->rx_max_fifo_size = RTE_MIN(pdata->rx_max_fifo_size,
2286 pdata->vdata->rx_max_fifo_size);
2287 /* Issue software reset to DMA */
2288 ret = pdata->hw_if.exit(pdata);
2290 PMD_DRV_LOG(ERR, "hw_if->exit EBUSY error\n");
2292 /* Set default configuration data */
2293 axgbe_default_config(pdata);
2295 /* Set default max values if not provided */
2296 if (!pdata->tx_max_fifo_size)
2297 pdata->tx_max_fifo_size = pdata->hw_feat.tx_fifo_size;
2298 if (!pdata->rx_max_fifo_size)
2299 pdata->rx_max_fifo_size = pdata->hw_feat.rx_fifo_size;
2301 pdata->tx_desc_count = AXGBE_MAX_RING_DESC;
2302 pdata->rx_desc_count = AXGBE_MAX_RING_DESC;
2303 pthread_mutex_init(&pdata->xpcs_mutex, NULL);
2304 pthread_mutex_init(&pdata->i2c_mutex, NULL);
2305 pthread_mutex_init(&pdata->an_mutex, NULL);
2306 pthread_mutex_init(&pdata->phy_mutex, NULL);
2308 ret = pdata->phy_if.phy_init(pdata);
2310 rte_free(eth_dev->data->mac_addrs);
2311 eth_dev->data->mac_addrs = NULL;
2315 rte_intr_callback_register(pci_dev->intr_handle,
2316 axgbe_dev_interrupt_handler,
2318 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
2319 eth_dev->data->port_id, pci_dev->id.vendor_id,
2320 pci_dev->id.device_id);
2326 axgbe_dev_close(struct rte_eth_dev *eth_dev)
2328 struct rte_pci_device *pci_dev;
2330 PMD_INIT_FUNC_TRACE();
2332 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2335 pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
2336 axgbe_dev_clear_queues(eth_dev);
2338 /* disable uio intr before callback unregister */
2339 rte_intr_disable(pci_dev->intr_handle);
2340 rte_intr_callback_unregister(pci_dev->intr_handle,
2341 axgbe_dev_interrupt_handler,
2347 static int eth_axgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2348 struct rte_pci_device *pci_dev)
2350 return rte_eth_dev_pci_generic_probe(pci_dev,
2351 sizeof(struct axgbe_port), eth_axgbe_dev_init);
2354 static int eth_axgbe_pci_remove(struct rte_pci_device *pci_dev)
2356 return rte_eth_dev_pci_generic_remove(pci_dev, axgbe_dev_close);
2359 static struct rte_pci_driver rte_axgbe_pmd = {
2360 .id_table = pci_id_axgbe_map,
2361 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
2362 .probe = eth_axgbe_pci_probe,
2363 .remove = eth_axgbe_pci_remove,
2366 RTE_PMD_REGISTER_PCI(net_axgbe, rte_axgbe_pmd);
2367 RTE_PMD_REGISTER_PCI_TABLE(net_axgbe, pci_id_axgbe_map);
2368 RTE_PMD_REGISTER_KMOD_DEP(net_axgbe, "* igb_uio | uio_pci_generic | vfio-pci");
2369 RTE_LOG_REGISTER_SUFFIX(axgbe_logtype_init, init, NOTICE);
2370 RTE_LOG_REGISTER_SUFFIX(axgbe_logtype_driver, driver, NOTICE);