1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved.
3 * Copyright(c) 2018 Synopsys, Inc. All rights reserved.
6 #include "axgbe_rxtx.h"
7 #include "axgbe_ethdev.h"
8 #include "axgbe_common.h"
11 static int eth_axgbe_dev_init(struct rte_eth_dev *eth_dev);
12 static int eth_axgbe_dev_uninit(struct rte_eth_dev *eth_dev);
13 static int axgbe_dev_configure(struct rte_eth_dev *dev);
14 static int axgbe_dev_start(struct rte_eth_dev *dev);
15 static void axgbe_dev_stop(struct rte_eth_dev *dev);
16 static void axgbe_dev_interrupt_handler(void *param);
17 static void axgbe_dev_close(struct rte_eth_dev *dev);
18 static int axgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
19 static int axgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
20 static int axgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
21 static int axgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
22 static int axgbe_dev_link_update(struct rte_eth_dev *dev,
23 int wait_to_complete);
24 static int axgbe_dev_stats_get(struct rte_eth_dev *dev,
25 struct rte_eth_stats *stats);
26 static int axgbe_dev_stats_reset(struct rte_eth_dev *dev);
27 static int axgbe_dev_xstats_get(struct rte_eth_dev *dev,
28 struct rte_eth_xstat *stats,
31 axgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
32 struct rte_eth_xstat_name *xstats_names,
35 axgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev,
40 axgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev,
41 struct rte_eth_xstat_name *xstats_names,
44 static int axgbe_dev_xstats_reset(struct rte_eth_dev *dev);
45 static int axgbe_dev_info_get(struct rte_eth_dev *dev,
46 struct rte_eth_dev_info *dev_info);
49 char name[RTE_ETH_XSTATS_NAME_SIZE];
53 #define AXGMAC_MMC_STAT(_string, _var) \
55 offsetof(struct axgbe_mmc_stats, _var), \
58 static const struct axgbe_xstats axgbe_xstats_strings[] = {
59 AXGMAC_MMC_STAT("tx_bytes", txoctetcount_gb),
60 AXGMAC_MMC_STAT("tx_packets", txframecount_gb),
61 AXGMAC_MMC_STAT("tx_unicast_packets", txunicastframes_gb),
62 AXGMAC_MMC_STAT("tx_broadcast_packets", txbroadcastframes_gb),
63 AXGMAC_MMC_STAT("tx_multicast_packets", txmulticastframes_gb),
64 AXGMAC_MMC_STAT("tx_vlan_packets", txvlanframes_g),
65 AXGMAC_MMC_STAT("tx_64_byte_packets", tx64octets_gb),
66 AXGMAC_MMC_STAT("tx_65_to_127_byte_packets", tx65to127octets_gb),
67 AXGMAC_MMC_STAT("tx_128_to_255_byte_packets", tx128to255octets_gb),
68 AXGMAC_MMC_STAT("tx_256_to_511_byte_packets", tx256to511octets_gb),
69 AXGMAC_MMC_STAT("tx_512_to_1023_byte_packets", tx512to1023octets_gb),
70 AXGMAC_MMC_STAT("tx_1024_to_max_byte_packets", tx1024tomaxoctets_gb),
71 AXGMAC_MMC_STAT("tx_underflow_errors", txunderflowerror),
72 AXGMAC_MMC_STAT("tx_pause_frames", txpauseframes),
74 AXGMAC_MMC_STAT("rx_bytes", rxoctetcount_gb),
75 AXGMAC_MMC_STAT("rx_packets", rxframecount_gb),
76 AXGMAC_MMC_STAT("rx_unicast_packets", rxunicastframes_g),
77 AXGMAC_MMC_STAT("rx_broadcast_packets", rxbroadcastframes_g),
78 AXGMAC_MMC_STAT("rx_multicast_packets", rxmulticastframes_g),
79 AXGMAC_MMC_STAT("rx_vlan_packets", rxvlanframes_gb),
80 AXGMAC_MMC_STAT("rx_64_byte_packets", rx64octets_gb),
81 AXGMAC_MMC_STAT("rx_65_to_127_byte_packets", rx65to127octets_gb),
82 AXGMAC_MMC_STAT("rx_128_to_255_byte_packets", rx128to255octets_gb),
83 AXGMAC_MMC_STAT("rx_256_to_511_byte_packets", rx256to511octets_gb),
84 AXGMAC_MMC_STAT("rx_512_to_1023_byte_packets", rx512to1023octets_gb),
85 AXGMAC_MMC_STAT("rx_1024_to_max_byte_packets", rx1024tomaxoctets_gb),
86 AXGMAC_MMC_STAT("rx_undersize_packets", rxundersize_g),
87 AXGMAC_MMC_STAT("rx_oversize_packets", rxoversize_g),
88 AXGMAC_MMC_STAT("rx_crc_errors", rxcrcerror),
89 AXGMAC_MMC_STAT("rx_crc_errors_small_packets", rxrunterror),
90 AXGMAC_MMC_STAT("rx_crc_errors_giant_packets", rxjabbererror),
91 AXGMAC_MMC_STAT("rx_length_errors", rxlengtherror),
92 AXGMAC_MMC_STAT("rx_out_of_range_errors", rxoutofrangetype),
93 AXGMAC_MMC_STAT("rx_fifo_overflow_errors", rxfifooverflow),
94 AXGMAC_MMC_STAT("rx_watchdog_errors", rxwatchdogerror),
95 AXGMAC_MMC_STAT("rx_pause_frames", rxpauseframes),
98 #define AXGBE_XSTATS_COUNT ARRAY_SIZE(axgbe_xstats_strings)
100 /* The set of PCI devices this driver supports */
101 #define AMD_PCI_VENDOR_ID 0x1022
102 #define AMD_PCI_RV_ROOT_COMPLEX_ID 0x15d0
103 #define AMD_PCI_AXGBE_DEVICE_V2A 0x1458
104 #define AMD_PCI_AXGBE_DEVICE_V2B 0x1459
106 int axgbe_logtype_init;
107 int axgbe_logtype_driver;
109 static const struct rte_pci_id pci_id_axgbe_map[] = {
110 {RTE_PCI_DEVICE(AMD_PCI_VENDOR_ID, AMD_PCI_AXGBE_DEVICE_V2A)},
111 {RTE_PCI_DEVICE(AMD_PCI_VENDOR_ID, AMD_PCI_AXGBE_DEVICE_V2B)},
115 static struct axgbe_version_data axgbe_v2a = {
116 .init_function_ptrs_phy_impl = axgbe_init_function_ptrs_phy_v2,
117 .xpcs_access = AXGBE_XPCS_ACCESS_V2,
119 .tx_max_fifo_size = 229376,
120 .rx_max_fifo_size = 229376,
121 .tx_tstamp_workaround = 1,
124 .an_cdr_workaround = 1,
127 static struct axgbe_version_data axgbe_v2b = {
128 .init_function_ptrs_phy_impl = axgbe_init_function_ptrs_phy_v2,
129 .xpcs_access = AXGBE_XPCS_ACCESS_V2,
131 .tx_max_fifo_size = 65536,
132 .rx_max_fifo_size = 65536,
133 .tx_tstamp_workaround = 1,
136 .an_cdr_workaround = 1,
139 static const struct rte_eth_desc_lim rx_desc_lim = {
140 .nb_max = AXGBE_MAX_RING_DESC,
141 .nb_min = AXGBE_MIN_RING_DESC,
145 static const struct rte_eth_desc_lim tx_desc_lim = {
146 .nb_max = AXGBE_MAX_RING_DESC,
147 .nb_min = AXGBE_MIN_RING_DESC,
151 static const struct eth_dev_ops axgbe_eth_dev_ops = {
152 .dev_configure = axgbe_dev_configure,
153 .dev_start = axgbe_dev_start,
154 .dev_stop = axgbe_dev_stop,
155 .dev_close = axgbe_dev_close,
156 .promiscuous_enable = axgbe_dev_promiscuous_enable,
157 .promiscuous_disable = axgbe_dev_promiscuous_disable,
158 .allmulticast_enable = axgbe_dev_allmulticast_enable,
159 .allmulticast_disable = axgbe_dev_allmulticast_disable,
160 .link_update = axgbe_dev_link_update,
161 .stats_get = axgbe_dev_stats_get,
162 .stats_reset = axgbe_dev_stats_reset,
163 .xstats_get = axgbe_dev_xstats_get,
164 .xstats_reset = axgbe_dev_xstats_reset,
165 .xstats_get_names = axgbe_dev_xstats_get_names,
166 .xstats_get_names_by_id = axgbe_dev_xstats_get_names_by_id,
167 .xstats_get_by_id = axgbe_dev_xstats_get_by_id,
168 .dev_infos_get = axgbe_dev_info_get,
169 .rx_queue_setup = axgbe_dev_rx_queue_setup,
170 .rx_queue_release = axgbe_dev_rx_queue_release,
171 .tx_queue_setup = axgbe_dev_tx_queue_setup,
172 .tx_queue_release = axgbe_dev_tx_queue_release,
175 static int axgbe_phy_reset(struct axgbe_port *pdata)
177 pdata->phy_link = -1;
178 pdata->phy_speed = SPEED_UNKNOWN;
179 return pdata->phy_if.phy_reset(pdata);
183 * Interrupt handler triggered by NIC for handling
184 * specific interrupt.
187 * Pointer to interrupt handle.
189 * The address of parameter (struct rte_eth_dev *) regsitered before.
195 axgbe_dev_interrupt_handler(void *param)
197 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
198 struct axgbe_port *pdata = dev->data->dev_private;
199 unsigned int dma_isr, dma_ch_isr;
201 pdata->phy_if.an_isr(pdata);
202 /*DMA related interrupts*/
203 dma_isr = AXGMAC_IOREAD(pdata, DMA_ISR);
204 PMD_DRV_LOG(DEBUG, "DMA_ISR=%#010x\n", dma_isr);
208 AXGMAC_DMA_IOREAD((struct axgbe_rx_queue *)
211 PMD_DRV_LOG(DEBUG, "DMA_CH0_ISR=%#010x\n", dma_ch_isr);
212 AXGMAC_DMA_IOWRITE((struct axgbe_rx_queue *)
214 DMA_CH_SR, dma_ch_isr);
217 /* Unmask interrupts since disabled after generation */
218 rte_intr_ack(&pdata->pci_dev->intr_handle);
222 * Configure device link speed and setup link.
223 * It returns 0 on success.
226 axgbe_dev_configure(struct rte_eth_dev *dev)
228 struct axgbe_port *pdata = dev->data->dev_private;
229 /* Checksum offload to hardware */
230 pdata->rx_csum_enable = dev->data->dev_conf.rxmode.offloads &
231 DEV_RX_OFFLOAD_CHECKSUM;
236 axgbe_dev_rx_mq_config(struct rte_eth_dev *dev)
238 struct axgbe_port *pdata = dev->data->dev_private;
240 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS)
241 pdata->rss_enable = 1;
242 else if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_NONE)
243 pdata->rss_enable = 0;
250 axgbe_dev_start(struct rte_eth_dev *dev)
252 struct axgbe_port *pdata = dev->data->dev_private;
255 PMD_INIT_FUNC_TRACE();
258 ret = axgbe_dev_rx_mq_config(dev);
260 PMD_DRV_LOG(ERR, "Unable to config RX MQ\n");
263 ret = axgbe_phy_reset(pdata);
265 PMD_DRV_LOG(ERR, "phy reset failed\n");
268 ret = pdata->hw_if.init(pdata);
270 PMD_DRV_LOG(ERR, "dev_init failed\n");
274 /* enable uio/vfio intr/eventfd mapping */
275 rte_intr_enable(&pdata->pci_dev->intr_handle);
278 pdata->phy_if.phy_start(pdata);
279 axgbe_dev_enable_tx(dev);
280 axgbe_dev_enable_rx(dev);
282 axgbe_clear_bit(AXGBE_STOPPED, &pdata->dev_state);
283 axgbe_clear_bit(AXGBE_DOWN, &pdata->dev_state);
287 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
289 axgbe_dev_stop(struct rte_eth_dev *dev)
291 struct axgbe_port *pdata = dev->data->dev_private;
293 PMD_INIT_FUNC_TRACE();
295 rte_intr_disable(&pdata->pci_dev->intr_handle);
297 if (axgbe_test_bit(AXGBE_STOPPED, &pdata->dev_state))
300 axgbe_set_bit(AXGBE_STOPPED, &pdata->dev_state);
301 axgbe_dev_disable_tx(dev);
302 axgbe_dev_disable_rx(dev);
304 pdata->phy_if.phy_stop(pdata);
305 pdata->hw_if.exit(pdata);
306 memset(&dev->data->dev_link, 0, sizeof(struct rte_eth_link));
307 axgbe_set_bit(AXGBE_DOWN, &pdata->dev_state);
310 /* Clear all resources like TX/RX queues. */
312 axgbe_dev_close(struct rte_eth_dev *dev)
314 axgbe_dev_clear_queues(dev);
318 axgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
320 struct axgbe_port *pdata = dev->data->dev_private;
322 PMD_INIT_FUNC_TRACE();
324 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, 1);
330 axgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
332 struct axgbe_port *pdata = dev->data->dev_private;
334 PMD_INIT_FUNC_TRACE();
336 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, 0);
342 axgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
344 struct axgbe_port *pdata = dev->data->dev_private;
346 PMD_INIT_FUNC_TRACE();
348 if (AXGMAC_IOREAD_BITS(pdata, MAC_PFR, PM))
350 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, 1);
356 axgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
358 struct axgbe_port *pdata = dev->data->dev_private;
360 PMD_INIT_FUNC_TRACE();
362 if (!AXGMAC_IOREAD_BITS(pdata, MAC_PFR, PM))
364 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, 0);
369 /* return 0 means link status changed, -1 means not changed */
371 axgbe_dev_link_update(struct rte_eth_dev *dev,
372 int wait_to_complete __rte_unused)
374 struct axgbe_port *pdata = dev->data->dev_private;
375 struct rte_eth_link link;
378 PMD_INIT_FUNC_TRACE();
381 pdata->phy_if.phy_status(pdata);
383 memset(&link, 0, sizeof(struct rte_eth_link));
384 link.link_duplex = pdata->phy.duplex;
385 link.link_status = pdata->phy_link;
386 link.link_speed = pdata->phy_speed;
387 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
388 ETH_LINK_SPEED_FIXED);
389 ret = rte_eth_linkstatus_set(dev, &link);
391 PMD_DRV_LOG(ERR, "No change in link status\n");
396 static void axgbe_read_mmc_stats(struct axgbe_port *pdata)
398 struct axgbe_mmc_stats *stats = &pdata->mmc_stats;
400 /* Freeze counters */
401 AXGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 1);
404 stats->txoctetcount_gb +=
405 AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_GB_LO);
406 stats->txoctetcount_gb +=
407 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_GB_HI) << 32);
409 stats->txframecount_gb +=
410 AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_GB_LO);
411 stats->txframecount_gb +=
412 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_GB_HI) << 32);
414 stats->txbroadcastframes_g +=
415 AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_G_LO);
416 stats->txbroadcastframes_g +=
417 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_G_HI) << 32);
419 stats->txmulticastframes_g +=
420 AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_G_LO);
421 stats->txmulticastframes_g +=
422 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_G_HI) << 32);
424 stats->tx64octets_gb +=
425 AXGMAC_IOREAD(pdata, MMC_TX64OCTETS_GB_LO);
426 stats->tx64octets_gb +=
427 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX64OCTETS_GB_HI) << 32);
429 stats->tx65to127octets_gb +=
430 AXGMAC_IOREAD(pdata, MMC_TX65TO127OCTETS_GB_LO);
431 stats->tx65to127octets_gb +=
432 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX65TO127OCTETS_GB_HI) << 32);
434 stats->tx128to255octets_gb +=
435 AXGMAC_IOREAD(pdata, MMC_TX128TO255OCTETS_GB_LO);
436 stats->tx128to255octets_gb +=
437 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX128TO255OCTETS_GB_HI) << 32);
439 stats->tx256to511octets_gb +=
440 AXGMAC_IOREAD(pdata, MMC_TX256TO511OCTETS_GB_LO);
441 stats->tx256to511octets_gb +=
442 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX256TO511OCTETS_GB_HI) << 32);
444 stats->tx512to1023octets_gb +=
445 AXGMAC_IOREAD(pdata, MMC_TX512TO1023OCTETS_GB_LO);
446 stats->tx512to1023octets_gb +=
447 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX512TO1023OCTETS_GB_HI) << 32);
449 stats->tx1024tomaxoctets_gb +=
450 AXGMAC_IOREAD(pdata, MMC_TX1024TOMAXOCTETS_GB_LO);
451 stats->tx1024tomaxoctets_gb +=
452 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX1024TOMAXOCTETS_GB_HI) << 32);
454 stats->txunicastframes_gb +=
455 AXGMAC_IOREAD(pdata, MMC_TXUNICASTFRAMES_GB_LO);
456 stats->txunicastframes_gb +=
457 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXUNICASTFRAMES_GB_HI) << 32);
459 stats->txmulticastframes_gb +=
460 AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_GB_LO);
461 stats->txmulticastframes_gb +=
462 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_GB_HI) << 32);
464 stats->txbroadcastframes_g +=
465 AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_GB_LO);
466 stats->txbroadcastframes_g +=
467 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_GB_HI) << 32);
469 stats->txunderflowerror +=
470 AXGMAC_IOREAD(pdata, MMC_TXUNDERFLOWERROR_LO);
471 stats->txunderflowerror +=
472 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXUNDERFLOWERROR_HI) << 32);
474 stats->txoctetcount_g +=
475 AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_G_LO);
476 stats->txoctetcount_g +=
477 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_G_HI) << 32);
479 stats->txframecount_g +=
480 AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_G_LO);
481 stats->txframecount_g +=
482 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_G_HI) << 32);
484 stats->txpauseframes +=
485 AXGMAC_IOREAD(pdata, MMC_TXPAUSEFRAMES_LO);
486 stats->txpauseframes +=
487 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXPAUSEFRAMES_HI) << 32);
489 stats->txvlanframes_g +=
490 AXGMAC_IOREAD(pdata, MMC_TXVLANFRAMES_G_LO);
491 stats->txvlanframes_g +=
492 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXVLANFRAMES_G_HI) << 32);
495 stats->rxframecount_gb +=
496 AXGMAC_IOREAD(pdata, MMC_RXFRAMECOUNT_GB_LO);
497 stats->rxframecount_gb +=
498 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXFRAMECOUNT_GB_HI) << 32);
500 stats->rxoctetcount_gb +=
501 AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_GB_LO);
502 stats->rxoctetcount_gb +=
503 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_GB_HI) << 32);
505 stats->rxoctetcount_g +=
506 AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_G_LO);
507 stats->rxoctetcount_g +=
508 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_G_HI) << 32);
510 stats->rxbroadcastframes_g +=
511 AXGMAC_IOREAD(pdata, MMC_RXBROADCASTFRAMES_G_LO);
512 stats->rxbroadcastframes_g +=
513 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXBROADCASTFRAMES_G_HI) << 32);
515 stats->rxmulticastframes_g +=
516 AXGMAC_IOREAD(pdata, MMC_RXMULTICASTFRAMES_G_LO);
517 stats->rxmulticastframes_g +=
518 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXMULTICASTFRAMES_G_HI) << 32);
521 AXGMAC_IOREAD(pdata, MMC_RXCRCERROR_LO);
523 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXCRCERROR_HI) << 32);
525 stats->rxrunterror +=
526 AXGMAC_IOREAD(pdata, MMC_RXRUNTERROR);
528 stats->rxjabbererror +=
529 AXGMAC_IOREAD(pdata, MMC_RXJABBERERROR);
531 stats->rxundersize_g +=
532 AXGMAC_IOREAD(pdata, MMC_RXUNDERSIZE_G);
534 stats->rxoversize_g +=
535 AXGMAC_IOREAD(pdata, MMC_RXOVERSIZE_G);
537 stats->rx64octets_gb +=
538 AXGMAC_IOREAD(pdata, MMC_RX64OCTETS_GB_LO);
539 stats->rx64octets_gb +=
540 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX64OCTETS_GB_HI) << 32);
542 stats->rx65to127octets_gb +=
543 AXGMAC_IOREAD(pdata, MMC_RX65TO127OCTETS_GB_LO);
544 stats->rx65to127octets_gb +=
545 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX65TO127OCTETS_GB_HI) << 32);
547 stats->rx128to255octets_gb +=
548 AXGMAC_IOREAD(pdata, MMC_RX128TO255OCTETS_GB_LO);
549 stats->rx128to255octets_gb +=
550 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX128TO255OCTETS_GB_HI) << 32);
552 stats->rx256to511octets_gb +=
553 AXGMAC_IOREAD(pdata, MMC_RX256TO511OCTETS_GB_LO);
554 stats->rx256to511octets_gb +=
555 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX256TO511OCTETS_GB_HI) << 32);
557 stats->rx512to1023octets_gb +=
558 AXGMAC_IOREAD(pdata, MMC_RX512TO1023OCTETS_GB_LO);
559 stats->rx512to1023octets_gb +=
560 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX512TO1023OCTETS_GB_HI) << 32);
562 stats->rx1024tomaxoctets_gb +=
563 AXGMAC_IOREAD(pdata, MMC_RX1024TOMAXOCTETS_GB_LO);
564 stats->rx1024tomaxoctets_gb +=
565 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX1024TOMAXOCTETS_GB_HI) << 32);
567 stats->rxunicastframes_g +=
568 AXGMAC_IOREAD(pdata, MMC_RXUNICASTFRAMES_G_LO);
569 stats->rxunicastframes_g +=
570 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXUNICASTFRAMES_G_HI) << 32);
572 stats->rxlengtherror +=
573 AXGMAC_IOREAD(pdata, MMC_RXLENGTHERROR_LO);
574 stats->rxlengtherror +=
575 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXLENGTHERROR_HI) << 32);
577 stats->rxoutofrangetype +=
578 AXGMAC_IOREAD(pdata, MMC_RXOUTOFRANGETYPE_LO);
579 stats->rxoutofrangetype +=
580 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXOUTOFRANGETYPE_HI) << 32);
582 stats->rxpauseframes +=
583 AXGMAC_IOREAD(pdata, MMC_RXPAUSEFRAMES_LO);
584 stats->rxpauseframes +=
585 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXPAUSEFRAMES_HI) << 32);
587 stats->rxfifooverflow +=
588 AXGMAC_IOREAD(pdata, MMC_RXFIFOOVERFLOW_LO);
589 stats->rxfifooverflow +=
590 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXFIFOOVERFLOW_HI) << 32);
592 stats->rxvlanframes_gb +=
593 AXGMAC_IOREAD(pdata, MMC_RXVLANFRAMES_GB_LO);
594 stats->rxvlanframes_gb +=
595 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXVLANFRAMES_GB_HI) << 32);
597 stats->rxwatchdogerror +=
598 AXGMAC_IOREAD(pdata, MMC_RXWATCHDOGERROR);
600 /* Un-freeze counters */
601 AXGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 0);
605 axgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats,
608 struct axgbe_port *pdata = dev->data->dev_private;
614 axgbe_read_mmc_stats(pdata);
616 for (i = 0; i < n && i < AXGBE_XSTATS_COUNT; i++) {
618 stats[i].value = *(u64 *)((uint8_t *)&pdata->mmc_stats +
619 axgbe_xstats_strings[i].offset);
626 axgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
627 struct rte_eth_xstat_name *xstats_names,
632 if (n >= AXGBE_XSTATS_COUNT && xstats_names) {
633 for (i = 0; i < AXGBE_XSTATS_COUNT; ++i) {
634 snprintf(xstats_names[i].name,
635 RTE_ETH_XSTATS_NAME_SIZE, "%s",
636 axgbe_xstats_strings[i].name);
640 return AXGBE_XSTATS_COUNT;
644 axgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
645 uint64_t *values, unsigned int n)
648 uint64_t values_copy[AXGBE_XSTATS_COUNT];
651 struct axgbe_port *pdata = dev->data->dev_private;
653 if (n < AXGBE_XSTATS_COUNT)
654 return AXGBE_XSTATS_COUNT;
656 axgbe_read_mmc_stats(pdata);
658 for (i = 0; i < AXGBE_XSTATS_COUNT; i++) {
659 values[i] = *(u64 *)((uint8_t *)&pdata->mmc_stats +
660 axgbe_xstats_strings[i].offset);
666 axgbe_dev_xstats_get_by_id(dev, NULL, values_copy, AXGBE_XSTATS_COUNT);
668 for (i = 0; i < n; i++) {
669 if (ids[i] >= AXGBE_XSTATS_COUNT) {
670 PMD_DRV_LOG(ERR, "id value isn't valid\n");
673 values[i] = values_copy[ids[i]];
679 axgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev,
680 struct rte_eth_xstat_name *xstats_names,
684 struct rte_eth_xstat_name xstats_names_copy[AXGBE_XSTATS_COUNT];
688 return axgbe_dev_xstats_get_names(dev, xstats_names, size);
690 axgbe_dev_xstats_get_names(dev, xstats_names_copy, size);
692 for (i = 0; i < size; i++) {
693 if (ids[i] >= AXGBE_XSTATS_COUNT) {
694 PMD_DRV_LOG(ERR, "id value isn't valid\n");
697 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
703 axgbe_dev_xstats_reset(struct rte_eth_dev *dev)
705 struct axgbe_port *pdata = dev->data->dev_private;
706 struct axgbe_mmc_stats *stats = &pdata->mmc_stats;
708 /* MMC registers are configured for reset on read */
709 axgbe_read_mmc_stats(pdata);
712 memset(stats, 0, sizeof(*stats));
718 axgbe_dev_stats_get(struct rte_eth_dev *dev,
719 struct rte_eth_stats *stats)
721 struct axgbe_rx_queue *rxq;
722 struct axgbe_tx_queue *txq;
723 struct axgbe_port *pdata = dev->data->dev_private;
724 struct axgbe_mmc_stats *mmc_stats = &pdata->mmc_stats;
727 axgbe_read_mmc_stats(pdata);
729 stats->imissed = mmc_stats->rxfifooverflow;
731 for (i = 0; i < dev->data->nb_rx_queues; i++) {
732 rxq = dev->data->rx_queues[i];
733 stats->q_ipackets[i] = rxq->pkts;
734 stats->ipackets += rxq->pkts;
735 stats->q_ibytes[i] = rxq->bytes;
736 stats->ibytes += rxq->bytes;
737 stats->rx_nombuf += rxq->rx_mbuf_alloc_failed;
738 stats->q_errors[i] = rxq->errors + rxq->rx_mbuf_alloc_failed;
739 stats->ierrors += rxq->errors;
742 for (i = 0; i < dev->data->nb_tx_queues; i++) {
743 txq = dev->data->tx_queues[i];
744 stats->q_opackets[i] = txq->pkts;
745 stats->opackets += txq->pkts;
746 stats->q_obytes[i] = txq->bytes;
747 stats->obytes += txq->bytes;
748 stats->oerrors += txq->errors;
755 axgbe_dev_stats_reset(struct rte_eth_dev *dev)
757 struct axgbe_rx_queue *rxq;
758 struct axgbe_tx_queue *txq;
761 for (i = 0; i < dev->data->nb_rx_queues; i++) {
762 rxq = dev->data->rx_queues[i];
766 rxq->rx_mbuf_alloc_failed = 0;
768 for (i = 0; i < dev->data->nb_tx_queues; i++) {
769 txq = dev->data->tx_queues[i];
779 axgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
781 struct axgbe_port *pdata = dev->data->dev_private;
783 dev_info->max_rx_queues = pdata->rx_ring_count;
784 dev_info->max_tx_queues = pdata->tx_ring_count;
785 dev_info->min_rx_bufsize = AXGBE_RX_MIN_BUF_SIZE;
786 dev_info->max_rx_pktlen = AXGBE_RX_MAX_BUF_SIZE;
787 dev_info->max_mac_addrs = AXGBE_MAX_MAC_ADDRS;
788 dev_info->speed_capa = ETH_LINK_SPEED_10G;
790 dev_info->rx_offload_capa =
791 DEV_RX_OFFLOAD_IPV4_CKSUM |
792 DEV_RX_OFFLOAD_UDP_CKSUM |
793 DEV_RX_OFFLOAD_TCP_CKSUM |
794 DEV_RX_OFFLOAD_KEEP_CRC;
796 dev_info->tx_offload_capa =
797 DEV_TX_OFFLOAD_IPV4_CKSUM |
798 DEV_TX_OFFLOAD_UDP_CKSUM |
799 DEV_TX_OFFLOAD_TCP_CKSUM;
801 if (pdata->hw_feat.rss) {
802 dev_info->flow_type_rss_offloads = AXGBE_RSS_OFFLOAD;
803 dev_info->reta_size = pdata->hw_feat.hash_table_size;
804 dev_info->hash_key_size = AXGBE_RSS_HASH_KEY_SIZE;
807 dev_info->rx_desc_lim = rx_desc_lim;
808 dev_info->tx_desc_lim = tx_desc_lim;
810 dev_info->default_rxconf = (struct rte_eth_rxconf) {
811 .rx_free_thresh = AXGBE_RX_FREE_THRESH,
814 dev_info->default_txconf = (struct rte_eth_txconf) {
815 .tx_free_thresh = AXGBE_TX_FREE_THRESH,
821 static void axgbe_get_all_hw_features(struct axgbe_port *pdata)
823 unsigned int mac_hfr0, mac_hfr1, mac_hfr2;
824 struct axgbe_hw_features *hw_feat = &pdata->hw_feat;
826 mac_hfr0 = AXGMAC_IOREAD(pdata, MAC_HWF0R);
827 mac_hfr1 = AXGMAC_IOREAD(pdata, MAC_HWF1R);
828 mac_hfr2 = AXGMAC_IOREAD(pdata, MAC_HWF2R);
830 memset(hw_feat, 0, sizeof(*hw_feat));
832 hw_feat->version = AXGMAC_IOREAD(pdata, MAC_VR);
834 /* Hardware feature register 0 */
835 hw_feat->gmii = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL);
836 hw_feat->vlhash = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH);
837 hw_feat->sma = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SMASEL);
838 hw_feat->rwk = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RWKSEL);
839 hw_feat->mgk = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MGKSEL);
840 hw_feat->mmc = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MMCSEL);
841 hw_feat->aoe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ARPOFFSEL);
842 hw_feat->ts = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSEL);
843 hw_feat->eee = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, EEESEL);
844 hw_feat->tx_coe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TXCOESEL);
845 hw_feat->rx_coe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RXCOESEL);
846 hw_feat->addn_mac = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R,
848 hw_feat->ts_src = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSTSSEL);
849 hw_feat->sa_vlan_ins = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SAVLANINS);
851 /* Hardware feature register 1 */
852 hw_feat->rx_fifo_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
854 hw_feat->tx_fifo_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
856 hw_feat->adv_ts_hi = AXGMAC_GET_BITS(mac_hfr1,
857 MAC_HWF1R, ADVTHWORD);
858 hw_feat->dma_width = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADDR64);
859 hw_feat->dcb = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN);
860 hw_feat->sph = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN);
861 hw_feat->tso = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN);
862 hw_feat->dma_debug = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA);
863 hw_feat->rss = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, RSSEN);
864 hw_feat->tc_cnt = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC);
865 hw_feat->hash_table_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
867 hw_feat->l3l4_filter_num = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
870 /* Hardware feature register 2 */
871 hw_feat->rx_q_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXQCNT);
872 hw_feat->tx_q_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXQCNT);
873 hw_feat->rx_ch_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXCHCNT);
874 hw_feat->tx_ch_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXCHCNT);
875 hw_feat->pps_out_num = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM);
876 hw_feat->aux_snap_num = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R,
879 /* Translate the Hash Table size into actual number */
880 switch (hw_feat->hash_table_size) {
884 hw_feat->hash_table_size = 64;
887 hw_feat->hash_table_size = 128;
890 hw_feat->hash_table_size = 256;
894 /* Translate the address width setting into actual number */
895 switch (hw_feat->dma_width) {
897 hw_feat->dma_width = 32;
900 hw_feat->dma_width = 40;
903 hw_feat->dma_width = 48;
906 hw_feat->dma_width = 32;
909 /* The Queue, Channel and TC counts are zero based so increment them
910 * to get the actual number
914 hw_feat->rx_ch_cnt++;
915 hw_feat->tx_ch_cnt++;
918 /* Translate the fifo sizes into actual numbers */
919 hw_feat->rx_fifo_size = 1 << (hw_feat->rx_fifo_size + 7);
920 hw_feat->tx_fifo_size = 1 << (hw_feat->tx_fifo_size + 7);
923 static void axgbe_init_all_fptrs(struct axgbe_port *pdata)
925 axgbe_init_function_ptrs_dev(&pdata->hw_if);
926 axgbe_init_function_ptrs_phy(&pdata->phy_if);
927 axgbe_init_function_ptrs_i2c(&pdata->i2c_if);
928 pdata->vdata->init_function_ptrs_phy_impl(&pdata->phy_if);
931 static void axgbe_set_counts(struct axgbe_port *pdata)
933 /* Set all the function pointers */
934 axgbe_init_all_fptrs(pdata);
936 /* Populate the hardware features */
937 axgbe_get_all_hw_features(pdata);
939 /* Set default max values if not provided */
940 if (!pdata->tx_max_channel_count)
941 pdata->tx_max_channel_count = pdata->hw_feat.tx_ch_cnt;
942 if (!pdata->rx_max_channel_count)
943 pdata->rx_max_channel_count = pdata->hw_feat.rx_ch_cnt;
945 if (!pdata->tx_max_q_count)
946 pdata->tx_max_q_count = pdata->hw_feat.tx_q_cnt;
947 if (!pdata->rx_max_q_count)
948 pdata->rx_max_q_count = pdata->hw_feat.rx_q_cnt;
950 /* Calculate the number of Tx and Rx rings to be created
951 * -Tx (DMA) Channels map 1-to-1 to Tx Queues so set
952 * the number of Tx queues to the number of Tx channels
954 * -Rx (DMA) Channels do not map 1-to-1 so use the actual
955 * number of Rx queues or maximum allowed
957 pdata->tx_ring_count = RTE_MIN(pdata->hw_feat.tx_ch_cnt,
958 pdata->tx_max_channel_count);
959 pdata->tx_ring_count = RTE_MIN(pdata->tx_ring_count,
960 pdata->tx_max_q_count);
962 pdata->tx_q_count = pdata->tx_ring_count;
964 pdata->rx_ring_count = RTE_MIN(pdata->hw_feat.rx_ch_cnt,
965 pdata->rx_max_channel_count);
967 pdata->rx_q_count = RTE_MIN(pdata->hw_feat.rx_q_cnt,
968 pdata->rx_max_q_count);
971 static void axgbe_default_config(struct axgbe_port *pdata)
973 pdata->pblx8 = DMA_PBL_X8_ENABLE;
974 pdata->tx_sf_mode = MTL_TSF_ENABLE;
975 pdata->tx_threshold = MTL_TX_THRESHOLD_64;
976 pdata->tx_pbl = DMA_PBL_32;
977 pdata->tx_osp_mode = DMA_OSP_ENABLE;
978 pdata->rx_sf_mode = MTL_RSF_ENABLE;
979 pdata->rx_threshold = MTL_RX_THRESHOLD_64;
980 pdata->rx_pbl = DMA_PBL_32;
981 pdata->pause_autoneg = 1;
984 pdata->phy_speed = SPEED_UNKNOWN;
985 pdata->power_down = 0;
989 pci_device_cmp(const struct rte_device *dev, const void *_pci_id)
991 const struct rte_pci_device *pdev = RTE_DEV_TO_PCI_CONST(dev);
992 const struct rte_pci_id *pcid = _pci_id;
994 if (pdev->id.vendor_id == AMD_PCI_VENDOR_ID &&
995 pdev->id.device_id == pcid->device_id)
1001 pci_search_device(int device_id)
1003 struct rte_bus *pci_bus;
1004 struct rte_pci_id dev_id;
1006 dev_id.device_id = device_id;
1007 pci_bus = rte_bus_find_by_name("pci");
1008 return (pci_bus != NULL) &&
1009 (pci_bus->find_device(NULL, pci_device_cmp, &dev_id) != NULL);
1013 * It returns 0 on success.
1016 eth_axgbe_dev_init(struct rte_eth_dev *eth_dev)
1018 PMD_INIT_FUNC_TRACE();
1019 struct axgbe_port *pdata;
1020 struct rte_pci_device *pci_dev;
1021 uint32_t reg, mac_lo, mac_hi;
1024 eth_dev->dev_ops = &axgbe_eth_dev_ops;
1025 eth_dev->rx_pkt_burst = &axgbe_recv_pkts;
1028 * For secondary processes, we don't initialise any further as primary
1029 * has already done this work.
1031 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1034 pdata = eth_dev->data->dev_private;
1036 axgbe_set_bit(AXGBE_DOWN, &pdata->dev_state);
1037 axgbe_set_bit(AXGBE_STOPPED, &pdata->dev_state);
1038 pdata->eth_dev = eth_dev;
1040 pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1041 pdata->pci_dev = pci_dev;
1044 * Use root complex device ID to differentiate RV AXGBE vs SNOWY AXGBE
1046 if (pci_search_device(AMD_PCI_RV_ROOT_COMPLEX_ID)) {
1047 pdata->xpcs_window_def_reg = PCS_V2_RV_WINDOW_DEF;
1048 pdata->xpcs_window_sel_reg = PCS_V2_RV_WINDOW_SELECT;
1050 pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF;
1051 pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT;
1055 (void *)pci_dev->mem_resource[AXGBE_AXGMAC_BAR].addr;
1056 pdata->xprop_regs = (void *)((uint8_t *)pdata->xgmac_regs
1057 + AXGBE_MAC_PROP_OFFSET);
1058 pdata->xi2c_regs = (void *)((uint8_t *)pdata->xgmac_regs
1059 + AXGBE_I2C_CTRL_OFFSET);
1060 pdata->xpcs_regs = (void *)pci_dev->mem_resource[AXGBE_XPCS_BAR].addr;
1062 /* version specific driver data*/
1063 if (pci_dev->id.device_id == AMD_PCI_AXGBE_DEVICE_V2A)
1064 pdata->vdata = &axgbe_v2a;
1066 pdata->vdata = &axgbe_v2b;
1068 /* Configure the PCS indirect addressing support */
1069 reg = XPCS32_IOREAD(pdata, pdata->xpcs_window_def_reg);
1070 pdata->xpcs_window = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, OFFSET);
1071 pdata->xpcs_window <<= 6;
1072 pdata->xpcs_window_size = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, SIZE);
1073 pdata->xpcs_window_size = 1 << (pdata->xpcs_window_size + 7);
1074 pdata->xpcs_window_mask = pdata->xpcs_window_size - 1;
1077 "xpcs window :%x, size :%x, mask :%x ", pdata->xpcs_window,
1078 pdata->xpcs_window_size, pdata->xpcs_window_mask);
1079 XP_IOWRITE(pdata, XP_INT_EN, 0x1fffff);
1081 /* Retrieve the MAC address */
1082 mac_lo = XP_IOREAD(pdata, XP_MAC_ADDR_LO);
1083 mac_hi = XP_IOREAD(pdata, XP_MAC_ADDR_HI);
1084 pdata->mac_addr.addr_bytes[0] = mac_lo & 0xff;
1085 pdata->mac_addr.addr_bytes[1] = (mac_lo >> 8) & 0xff;
1086 pdata->mac_addr.addr_bytes[2] = (mac_lo >> 16) & 0xff;
1087 pdata->mac_addr.addr_bytes[3] = (mac_lo >> 24) & 0xff;
1088 pdata->mac_addr.addr_bytes[4] = mac_hi & 0xff;
1089 pdata->mac_addr.addr_bytes[5] = (mac_hi >> 8) & 0xff;
1091 eth_dev->data->mac_addrs = rte_zmalloc("axgbe_mac_addr",
1092 RTE_ETHER_ADDR_LEN, 0);
1093 if (!eth_dev->data->mac_addrs) {
1095 "Failed to alloc %u bytes needed to store MAC addr tbl",
1096 RTE_ETHER_ADDR_LEN);
1100 if (!rte_is_valid_assigned_ether_addr(&pdata->mac_addr))
1101 rte_eth_random_addr(pdata->mac_addr.addr_bytes);
1103 /* Copy the permanent MAC address */
1104 rte_ether_addr_copy(&pdata->mac_addr, ð_dev->data->mac_addrs[0]);
1106 /* Clock settings */
1107 pdata->sysclk_rate = AXGBE_V2_DMA_CLOCK_FREQ;
1108 pdata->ptpclk_rate = AXGBE_V2_PTP_CLOCK_FREQ;
1110 /* Set the DMA coherency values */
1111 pdata->coherent = 1;
1112 pdata->axdomain = AXGBE_DMA_OS_AXDOMAIN;
1113 pdata->arcache = AXGBE_DMA_OS_ARCACHE;
1114 pdata->awcache = AXGBE_DMA_OS_AWCACHE;
1116 /* Set the maximum channels and queues */
1117 reg = XP_IOREAD(pdata, XP_PROP_1);
1118 pdata->tx_max_channel_count = XP_GET_BITS(reg, XP_PROP_1, MAX_TX_DMA);
1119 pdata->rx_max_channel_count = XP_GET_BITS(reg, XP_PROP_1, MAX_RX_DMA);
1120 pdata->tx_max_q_count = XP_GET_BITS(reg, XP_PROP_1, MAX_TX_QUEUES);
1121 pdata->rx_max_q_count = XP_GET_BITS(reg, XP_PROP_1, MAX_RX_QUEUES);
1123 /* Set the hardware channel and queue counts */
1124 axgbe_set_counts(pdata);
1126 /* Set the maximum fifo amounts */
1127 reg = XP_IOREAD(pdata, XP_PROP_2);
1128 pdata->tx_max_fifo_size = XP_GET_BITS(reg, XP_PROP_2, TX_FIFO_SIZE);
1129 pdata->tx_max_fifo_size *= 16384;
1130 pdata->tx_max_fifo_size = RTE_MIN(pdata->tx_max_fifo_size,
1131 pdata->vdata->tx_max_fifo_size);
1132 pdata->rx_max_fifo_size = XP_GET_BITS(reg, XP_PROP_2, RX_FIFO_SIZE);
1133 pdata->rx_max_fifo_size *= 16384;
1134 pdata->rx_max_fifo_size = RTE_MIN(pdata->rx_max_fifo_size,
1135 pdata->vdata->rx_max_fifo_size);
1136 /* Issue software reset to DMA */
1137 ret = pdata->hw_if.exit(pdata);
1139 PMD_DRV_LOG(ERR, "hw_if->exit EBUSY error\n");
1141 /* Set default configuration data */
1142 axgbe_default_config(pdata);
1144 /* Set default max values if not provided */
1145 if (!pdata->tx_max_fifo_size)
1146 pdata->tx_max_fifo_size = pdata->hw_feat.tx_fifo_size;
1147 if (!pdata->rx_max_fifo_size)
1148 pdata->rx_max_fifo_size = pdata->hw_feat.rx_fifo_size;
1150 pdata->tx_desc_count = AXGBE_MAX_RING_DESC;
1151 pdata->rx_desc_count = AXGBE_MAX_RING_DESC;
1152 pthread_mutex_init(&pdata->xpcs_mutex, NULL);
1153 pthread_mutex_init(&pdata->i2c_mutex, NULL);
1154 pthread_mutex_init(&pdata->an_mutex, NULL);
1155 pthread_mutex_init(&pdata->phy_mutex, NULL);
1157 ret = pdata->phy_if.phy_init(pdata);
1159 rte_free(eth_dev->data->mac_addrs);
1160 eth_dev->data->mac_addrs = NULL;
1164 rte_intr_callback_register(&pci_dev->intr_handle,
1165 axgbe_dev_interrupt_handler,
1167 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1168 eth_dev->data->port_id, pci_dev->id.vendor_id,
1169 pci_dev->id.device_id);
1175 eth_axgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1177 struct rte_pci_device *pci_dev;
1179 PMD_INIT_FUNC_TRACE();
1181 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1184 pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1185 eth_dev->dev_ops = NULL;
1186 eth_dev->rx_pkt_burst = NULL;
1187 eth_dev->tx_pkt_burst = NULL;
1188 axgbe_dev_clear_queues(eth_dev);
1190 /* disable uio intr before callback unregister */
1191 rte_intr_disable(&pci_dev->intr_handle);
1192 rte_intr_callback_unregister(&pci_dev->intr_handle,
1193 axgbe_dev_interrupt_handler,
1199 static int eth_axgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1200 struct rte_pci_device *pci_dev)
1202 return rte_eth_dev_pci_generic_probe(pci_dev,
1203 sizeof(struct axgbe_port), eth_axgbe_dev_init);
1206 static int eth_axgbe_pci_remove(struct rte_pci_device *pci_dev)
1208 return rte_eth_dev_pci_generic_remove(pci_dev, eth_axgbe_dev_uninit);
1211 static struct rte_pci_driver rte_axgbe_pmd = {
1212 .id_table = pci_id_axgbe_map,
1213 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1214 .probe = eth_axgbe_pci_probe,
1215 .remove = eth_axgbe_pci_remove,
1218 RTE_PMD_REGISTER_PCI(net_axgbe, rte_axgbe_pmd);
1219 RTE_PMD_REGISTER_PCI_TABLE(net_axgbe, pci_id_axgbe_map);
1220 RTE_PMD_REGISTER_KMOD_DEP(net_axgbe, "* igb_uio | uio_pci_generic | vfio-pci");
1222 RTE_INIT(axgbe_init_log)
1224 axgbe_logtype_init = rte_log_register("pmd.net.axgbe.init");
1225 if (axgbe_logtype_init >= 0)
1226 rte_log_set_level(axgbe_logtype_init, RTE_LOG_NOTICE);
1227 axgbe_logtype_driver = rte_log_register("pmd.net.axgbe.driver");
1228 if (axgbe_logtype_driver >= 0)
1229 rte_log_set_level(axgbe_logtype_driver, RTE_LOG_NOTICE);