1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved.
3 * Copyright(c) 2018 Synopsys, Inc. All rights reserved.
6 #include "axgbe_rxtx.h"
7 #include "axgbe_ethdev.h"
8 #include "axgbe_common.h"
10 #include "axgbe_regs.h"
12 static int eth_axgbe_dev_init(struct rte_eth_dev *eth_dev);
13 static int eth_axgbe_dev_uninit(struct rte_eth_dev *eth_dev);
14 static int axgbe_dev_configure(struct rte_eth_dev *dev);
15 static int axgbe_dev_start(struct rte_eth_dev *dev);
16 static void axgbe_dev_stop(struct rte_eth_dev *dev);
17 static void axgbe_dev_interrupt_handler(void *param);
18 static void axgbe_dev_close(struct rte_eth_dev *dev);
19 static int axgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
20 static int axgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
21 static int axgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
22 static int axgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
23 static int axgbe_dev_mac_addr_set(struct rte_eth_dev *dev,
24 struct rte_ether_addr *mac_addr);
25 static int axgbe_dev_mac_addr_add(struct rte_eth_dev *dev,
26 struct rte_ether_addr *mac_addr,
29 static void axgbe_dev_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
30 static int axgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
31 struct rte_ether_addr *mc_addr_set,
33 static int axgbe_dev_uc_hash_table_set(struct rte_eth_dev *dev,
34 struct rte_ether_addr *mac_addr,
36 static int axgbe_dev_uc_all_hash_table_set(struct rte_eth_dev *dev,
38 static int axgbe_dev_link_update(struct rte_eth_dev *dev,
39 int wait_to_complete);
40 static int axgbe_dev_get_regs(struct rte_eth_dev *dev,
41 struct rte_dev_reg_info *regs);
42 static int axgbe_dev_stats_get(struct rte_eth_dev *dev,
43 struct rte_eth_stats *stats);
44 static int axgbe_dev_stats_reset(struct rte_eth_dev *dev);
45 static int axgbe_dev_xstats_get(struct rte_eth_dev *dev,
46 struct rte_eth_xstat *stats,
49 axgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
50 struct rte_eth_xstat_name *xstats_names,
53 axgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev,
58 axgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev,
59 struct rte_eth_xstat_name *xstats_names,
62 static int axgbe_dev_xstats_reset(struct rte_eth_dev *dev);
63 static int axgbe_dev_info_get(struct rte_eth_dev *dev,
64 struct rte_eth_dev_info *dev_info);
65 static int axgbe_flow_ctrl_get(struct rte_eth_dev *dev,
66 struct rte_eth_fc_conf *fc_conf);
67 static int axgbe_flow_ctrl_set(struct rte_eth_dev *dev,
68 struct rte_eth_fc_conf *fc_conf);
69 static int axgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
70 struct rte_eth_pfc_conf *pfc_conf);
73 char name[RTE_ETH_XSTATS_NAME_SIZE];
77 #define AXGMAC_MMC_STAT(_string, _var) \
79 offsetof(struct axgbe_mmc_stats, _var), \
82 static const struct axgbe_xstats axgbe_xstats_strings[] = {
83 AXGMAC_MMC_STAT("tx_bytes", txoctetcount_gb),
84 AXGMAC_MMC_STAT("tx_packets", txframecount_gb),
85 AXGMAC_MMC_STAT("tx_unicast_packets", txunicastframes_gb),
86 AXGMAC_MMC_STAT("tx_broadcast_packets", txbroadcastframes_gb),
87 AXGMAC_MMC_STAT("tx_multicast_packets", txmulticastframes_gb),
88 AXGMAC_MMC_STAT("tx_vlan_packets", txvlanframes_g),
89 AXGMAC_MMC_STAT("tx_64_byte_packets", tx64octets_gb),
90 AXGMAC_MMC_STAT("tx_65_to_127_byte_packets", tx65to127octets_gb),
91 AXGMAC_MMC_STAT("tx_128_to_255_byte_packets", tx128to255octets_gb),
92 AXGMAC_MMC_STAT("tx_256_to_511_byte_packets", tx256to511octets_gb),
93 AXGMAC_MMC_STAT("tx_512_to_1023_byte_packets", tx512to1023octets_gb),
94 AXGMAC_MMC_STAT("tx_1024_to_max_byte_packets", tx1024tomaxoctets_gb),
95 AXGMAC_MMC_STAT("tx_underflow_errors", txunderflowerror),
96 AXGMAC_MMC_STAT("tx_pause_frames", txpauseframes),
98 AXGMAC_MMC_STAT("rx_bytes", rxoctetcount_gb),
99 AXGMAC_MMC_STAT("rx_packets", rxframecount_gb),
100 AXGMAC_MMC_STAT("rx_unicast_packets", rxunicastframes_g),
101 AXGMAC_MMC_STAT("rx_broadcast_packets", rxbroadcastframes_g),
102 AXGMAC_MMC_STAT("rx_multicast_packets", rxmulticastframes_g),
103 AXGMAC_MMC_STAT("rx_vlan_packets", rxvlanframes_gb),
104 AXGMAC_MMC_STAT("rx_64_byte_packets", rx64octets_gb),
105 AXGMAC_MMC_STAT("rx_65_to_127_byte_packets", rx65to127octets_gb),
106 AXGMAC_MMC_STAT("rx_128_to_255_byte_packets", rx128to255octets_gb),
107 AXGMAC_MMC_STAT("rx_256_to_511_byte_packets", rx256to511octets_gb),
108 AXGMAC_MMC_STAT("rx_512_to_1023_byte_packets", rx512to1023octets_gb),
109 AXGMAC_MMC_STAT("rx_1024_to_max_byte_packets", rx1024tomaxoctets_gb),
110 AXGMAC_MMC_STAT("rx_undersize_packets", rxundersize_g),
111 AXGMAC_MMC_STAT("rx_oversize_packets", rxoversize_g),
112 AXGMAC_MMC_STAT("rx_crc_errors", rxcrcerror),
113 AXGMAC_MMC_STAT("rx_crc_errors_small_packets", rxrunterror),
114 AXGMAC_MMC_STAT("rx_crc_errors_giant_packets", rxjabbererror),
115 AXGMAC_MMC_STAT("rx_length_errors", rxlengtherror),
116 AXGMAC_MMC_STAT("rx_out_of_range_errors", rxoutofrangetype),
117 AXGMAC_MMC_STAT("rx_fifo_overflow_errors", rxfifooverflow),
118 AXGMAC_MMC_STAT("rx_watchdog_errors", rxwatchdogerror),
119 AXGMAC_MMC_STAT("rx_pause_frames", rxpauseframes),
122 #define AXGBE_XSTATS_COUNT ARRAY_SIZE(axgbe_xstats_strings)
124 /* The set of PCI devices this driver supports */
125 #define AMD_PCI_VENDOR_ID 0x1022
126 #define AMD_PCI_RV_ROOT_COMPLEX_ID 0x15d0
127 #define AMD_PCI_AXGBE_DEVICE_V2A 0x1458
128 #define AMD_PCI_AXGBE_DEVICE_V2B 0x1459
130 int axgbe_logtype_init;
131 int axgbe_logtype_driver;
133 static const struct rte_pci_id pci_id_axgbe_map[] = {
134 {RTE_PCI_DEVICE(AMD_PCI_VENDOR_ID, AMD_PCI_AXGBE_DEVICE_V2A)},
135 {RTE_PCI_DEVICE(AMD_PCI_VENDOR_ID, AMD_PCI_AXGBE_DEVICE_V2B)},
139 static struct axgbe_version_data axgbe_v2a = {
140 .init_function_ptrs_phy_impl = axgbe_init_function_ptrs_phy_v2,
141 .xpcs_access = AXGBE_XPCS_ACCESS_V2,
143 .tx_max_fifo_size = 229376,
144 .rx_max_fifo_size = 229376,
145 .tx_tstamp_workaround = 1,
148 .an_cdr_workaround = 1,
151 static struct axgbe_version_data axgbe_v2b = {
152 .init_function_ptrs_phy_impl = axgbe_init_function_ptrs_phy_v2,
153 .xpcs_access = AXGBE_XPCS_ACCESS_V2,
155 .tx_max_fifo_size = 65536,
156 .rx_max_fifo_size = 65536,
157 .tx_tstamp_workaround = 1,
160 .an_cdr_workaround = 1,
163 static const struct rte_eth_desc_lim rx_desc_lim = {
164 .nb_max = AXGBE_MAX_RING_DESC,
165 .nb_min = AXGBE_MIN_RING_DESC,
169 static const struct rte_eth_desc_lim tx_desc_lim = {
170 .nb_max = AXGBE_MAX_RING_DESC,
171 .nb_min = AXGBE_MIN_RING_DESC,
175 static const struct eth_dev_ops axgbe_eth_dev_ops = {
176 .dev_configure = axgbe_dev_configure,
177 .dev_start = axgbe_dev_start,
178 .dev_stop = axgbe_dev_stop,
179 .dev_close = axgbe_dev_close,
180 .promiscuous_enable = axgbe_dev_promiscuous_enable,
181 .promiscuous_disable = axgbe_dev_promiscuous_disable,
182 .allmulticast_enable = axgbe_dev_allmulticast_enable,
183 .allmulticast_disable = axgbe_dev_allmulticast_disable,
184 .mac_addr_set = axgbe_dev_mac_addr_set,
185 .mac_addr_add = axgbe_dev_mac_addr_add,
186 .mac_addr_remove = axgbe_dev_mac_addr_remove,
187 .set_mc_addr_list = axgbe_dev_set_mc_addr_list,
188 .uc_hash_table_set = axgbe_dev_uc_hash_table_set,
189 .uc_all_hash_table_set = axgbe_dev_uc_all_hash_table_set,
190 .link_update = axgbe_dev_link_update,
191 .get_reg = axgbe_dev_get_regs,
192 .stats_get = axgbe_dev_stats_get,
193 .stats_reset = axgbe_dev_stats_reset,
194 .xstats_get = axgbe_dev_xstats_get,
195 .xstats_reset = axgbe_dev_xstats_reset,
196 .xstats_get_names = axgbe_dev_xstats_get_names,
197 .xstats_get_names_by_id = axgbe_dev_xstats_get_names_by_id,
198 .xstats_get_by_id = axgbe_dev_xstats_get_by_id,
199 .dev_infos_get = axgbe_dev_info_get,
200 .rx_queue_setup = axgbe_dev_rx_queue_setup,
201 .rx_queue_release = axgbe_dev_rx_queue_release,
202 .tx_queue_setup = axgbe_dev_tx_queue_setup,
203 .tx_queue_release = axgbe_dev_tx_queue_release,
204 .flow_ctrl_get = axgbe_flow_ctrl_get,
205 .flow_ctrl_set = axgbe_flow_ctrl_set,
206 .priority_flow_ctrl_set = axgbe_priority_flow_ctrl_set,
209 static int axgbe_phy_reset(struct axgbe_port *pdata)
211 pdata->phy_link = -1;
212 pdata->phy_speed = SPEED_UNKNOWN;
213 return pdata->phy_if.phy_reset(pdata);
217 * Interrupt handler triggered by NIC for handling
218 * specific interrupt.
221 * Pointer to interrupt handle.
223 * The address of parameter (struct rte_eth_dev *) regsitered before.
229 axgbe_dev_interrupt_handler(void *param)
231 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
232 struct axgbe_port *pdata = dev->data->dev_private;
233 unsigned int dma_isr, dma_ch_isr;
235 pdata->phy_if.an_isr(pdata);
236 /*DMA related interrupts*/
237 dma_isr = AXGMAC_IOREAD(pdata, DMA_ISR);
238 PMD_DRV_LOG(DEBUG, "DMA_ISR=%#010x\n", dma_isr);
242 AXGMAC_DMA_IOREAD((struct axgbe_rx_queue *)
245 PMD_DRV_LOG(DEBUG, "DMA_CH0_ISR=%#010x\n", dma_ch_isr);
246 AXGMAC_DMA_IOWRITE((struct axgbe_rx_queue *)
248 DMA_CH_SR, dma_ch_isr);
251 /* Unmask interrupts since disabled after generation */
252 rte_intr_ack(&pdata->pci_dev->intr_handle);
256 * Configure device link speed and setup link.
257 * It returns 0 on success.
260 axgbe_dev_configure(struct rte_eth_dev *dev)
262 struct axgbe_port *pdata = dev->data->dev_private;
263 /* Checksum offload to hardware */
264 pdata->rx_csum_enable = dev->data->dev_conf.rxmode.offloads &
265 DEV_RX_OFFLOAD_CHECKSUM;
270 axgbe_dev_rx_mq_config(struct rte_eth_dev *dev)
272 struct axgbe_port *pdata = dev->data->dev_private;
274 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS)
275 pdata->rss_enable = 1;
276 else if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_NONE)
277 pdata->rss_enable = 0;
284 axgbe_dev_start(struct rte_eth_dev *dev)
286 struct axgbe_port *pdata = dev->data->dev_private;
288 struct rte_eth_dev_data *dev_data = dev->data;
289 uint16_t max_pkt_len = dev_data->dev_conf.rxmode.max_rx_pkt_len;
291 dev->dev_ops = &axgbe_eth_dev_ops;
293 PMD_INIT_FUNC_TRACE();
296 ret = axgbe_dev_rx_mq_config(dev);
298 PMD_DRV_LOG(ERR, "Unable to config RX MQ\n");
301 ret = axgbe_phy_reset(pdata);
303 PMD_DRV_LOG(ERR, "phy reset failed\n");
306 ret = pdata->hw_if.init(pdata);
308 PMD_DRV_LOG(ERR, "dev_init failed\n");
312 /* enable uio/vfio intr/eventfd mapping */
313 rte_intr_enable(&pdata->pci_dev->intr_handle);
316 pdata->phy_if.phy_start(pdata);
317 axgbe_dev_enable_tx(dev);
318 axgbe_dev_enable_rx(dev);
320 axgbe_clear_bit(AXGBE_STOPPED, &pdata->dev_state);
321 axgbe_clear_bit(AXGBE_DOWN, &pdata->dev_state);
322 if ((dev_data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER) ||
323 max_pkt_len > pdata->rx_buf_size)
324 dev_data->scattered_rx = 1;
326 /* Scatter Rx handling */
327 if (dev_data->scattered_rx)
328 dev->rx_pkt_burst = ð_axgbe_recv_scattered_pkts;
330 dev->rx_pkt_burst = &axgbe_recv_pkts;
335 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
337 axgbe_dev_stop(struct rte_eth_dev *dev)
339 struct axgbe_port *pdata = dev->data->dev_private;
341 PMD_INIT_FUNC_TRACE();
343 rte_intr_disable(&pdata->pci_dev->intr_handle);
345 if (axgbe_test_bit(AXGBE_STOPPED, &pdata->dev_state))
348 axgbe_set_bit(AXGBE_STOPPED, &pdata->dev_state);
349 axgbe_dev_disable_tx(dev);
350 axgbe_dev_disable_rx(dev);
352 pdata->phy_if.phy_stop(pdata);
353 pdata->hw_if.exit(pdata);
354 memset(&dev->data->dev_link, 0, sizeof(struct rte_eth_link));
355 axgbe_set_bit(AXGBE_DOWN, &pdata->dev_state);
358 /* Clear all resources like TX/RX queues. */
360 axgbe_dev_close(struct rte_eth_dev *dev)
362 axgbe_dev_clear_queues(dev);
366 axgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
368 struct axgbe_port *pdata = dev->data->dev_private;
370 PMD_INIT_FUNC_TRACE();
372 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, 1);
378 axgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
380 struct axgbe_port *pdata = dev->data->dev_private;
382 PMD_INIT_FUNC_TRACE();
384 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, 0);
390 axgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
392 struct axgbe_port *pdata = dev->data->dev_private;
394 PMD_INIT_FUNC_TRACE();
396 if (AXGMAC_IOREAD_BITS(pdata, MAC_PFR, PM))
398 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, 1);
404 axgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
406 struct axgbe_port *pdata = dev->data->dev_private;
408 PMD_INIT_FUNC_TRACE();
410 if (!AXGMAC_IOREAD_BITS(pdata, MAC_PFR, PM))
412 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, 0);
418 axgbe_dev_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr)
420 struct axgbe_port *pdata = dev->data->dev_private;
422 /* Set Default MAC Addr */
423 axgbe_set_mac_addn_addr(pdata, (u8 *)mac_addr, 0);
429 axgbe_dev_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
430 uint32_t index, uint32_t pool __rte_unused)
432 struct axgbe_port *pdata = dev->data->dev_private;
433 struct axgbe_hw_features *hw_feat = &pdata->hw_feat;
435 if (index > hw_feat->addn_mac) {
436 PMD_DRV_LOG(ERR, "Invalid Index %d\n", index);
439 axgbe_set_mac_addn_addr(pdata, (u8 *)mac_addr, index);
444 axgbe_dev_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)
446 struct axgbe_port *pdata = dev->data->dev_private;
447 struct axgbe_hw_features *hw_feat = &pdata->hw_feat;
449 if (index > hw_feat->addn_mac) {
450 PMD_DRV_LOG(ERR, "Invalid Index %d\n", index);
453 axgbe_set_mac_addn_addr(pdata, NULL, index);
457 axgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
458 struct rte_ether_addr *mc_addr_set,
461 struct axgbe_port *pdata = dev->data->dev_private;
462 struct axgbe_hw_features *hw_feat = &pdata->hw_feat;
463 uint32_t index = 1; /* 0 is always default mac */
466 if (nb_mc_addr > hw_feat->addn_mac) {
467 PMD_DRV_LOG(ERR, "Invalid Index %d\n", nb_mc_addr);
471 /* clear unicast addresses */
472 for (i = 1; i < hw_feat->addn_mac; i++) {
473 if (rte_is_zero_ether_addr(&dev->data->mac_addrs[i]))
475 memset(&dev->data->mac_addrs[i], 0,
476 sizeof(struct rte_ether_addr));
480 axgbe_set_mac_addn_addr(pdata, (u8 *)mc_addr_set++, index++);
486 axgbe_dev_uc_hash_table_set(struct rte_eth_dev *dev,
487 struct rte_ether_addr *mac_addr, uint8_t add)
489 struct axgbe_port *pdata = dev->data->dev_private;
490 struct axgbe_hw_features *hw_feat = &pdata->hw_feat;
492 if (!hw_feat->hash_table_size) {
493 PMD_DRV_LOG(ERR, "MAC Hash Table not supported\n");
497 axgbe_set_mac_hash_table(pdata, (u8 *)mac_addr, add);
499 if (pdata->uc_hash_mac_addr > 0) {
500 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1);
501 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1);
503 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 0);
504 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 0);
510 axgbe_dev_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t add)
512 struct axgbe_port *pdata = dev->data->dev_private;
513 struct axgbe_hw_features *hw_feat = &pdata->hw_feat;
516 if (!hw_feat->hash_table_size) {
517 PMD_DRV_LOG(ERR, "MAC Hash Table not supported\n");
521 for (index = 0; index < pdata->hash_table_count; index++) {
523 pdata->uc_hash_table[index] = ~0;
525 pdata->uc_hash_table[index] = 0;
527 PMD_DRV_LOG(DEBUG, "%s MAC hash table at Index %#x\n",
528 add ? "set" : "clear", index);
530 AXGMAC_IOWRITE(pdata, MAC_HTR(index),
531 pdata->uc_hash_table[index]);
535 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1);
536 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1);
538 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 0);
539 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 0);
544 /* return 0 means link status changed, -1 means not changed */
546 axgbe_dev_link_update(struct rte_eth_dev *dev,
547 int wait_to_complete __rte_unused)
549 struct axgbe_port *pdata = dev->data->dev_private;
550 struct rte_eth_link link;
553 PMD_INIT_FUNC_TRACE();
556 pdata->phy_if.phy_status(pdata);
558 memset(&link, 0, sizeof(struct rte_eth_link));
559 link.link_duplex = pdata->phy.duplex;
560 link.link_status = pdata->phy_link;
561 link.link_speed = pdata->phy_speed;
562 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
563 ETH_LINK_SPEED_FIXED);
564 ret = rte_eth_linkstatus_set(dev, &link);
566 PMD_DRV_LOG(ERR, "No change in link status\n");
572 axgbe_dev_get_regs(struct rte_eth_dev *dev, struct rte_dev_reg_info *regs)
574 struct axgbe_port *pdata = dev->data->dev_private;
576 if (regs->data == NULL) {
577 regs->length = axgbe_regs_get_count(pdata);
578 regs->width = sizeof(uint32_t);
582 /* Only full register dump is supported */
584 regs->length != (uint32_t)axgbe_regs_get_count(pdata))
587 regs->version = pdata->pci_dev->id.vendor_id << 16 |
588 pdata->pci_dev->id.device_id;
589 axgbe_regs_dump(pdata, regs->data);
592 static void axgbe_read_mmc_stats(struct axgbe_port *pdata)
594 struct axgbe_mmc_stats *stats = &pdata->mmc_stats;
596 /* Freeze counters */
597 AXGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 1);
600 stats->txoctetcount_gb +=
601 AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_GB_LO);
602 stats->txoctetcount_gb +=
603 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_GB_HI) << 32);
605 stats->txframecount_gb +=
606 AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_GB_LO);
607 stats->txframecount_gb +=
608 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_GB_HI) << 32);
610 stats->txbroadcastframes_g +=
611 AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_G_LO);
612 stats->txbroadcastframes_g +=
613 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_G_HI) << 32);
615 stats->txmulticastframes_g +=
616 AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_G_LO);
617 stats->txmulticastframes_g +=
618 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_G_HI) << 32);
620 stats->tx64octets_gb +=
621 AXGMAC_IOREAD(pdata, MMC_TX64OCTETS_GB_LO);
622 stats->tx64octets_gb +=
623 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX64OCTETS_GB_HI) << 32);
625 stats->tx65to127octets_gb +=
626 AXGMAC_IOREAD(pdata, MMC_TX65TO127OCTETS_GB_LO);
627 stats->tx65to127octets_gb +=
628 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX65TO127OCTETS_GB_HI) << 32);
630 stats->tx128to255octets_gb +=
631 AXGMAC_IOREAD(pdata, MMC_TX128TO255OCTETS_GB_LO);
632 stats->tx128to255octets_gb +=
633 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX128TO255OCTETS_GB_HI) << 32);
635 stats->tx256to511octets_gb +=
636 AXGMAC_IOREAD(pdata, MMC_TX256TO511OCTETS_GB_LO);
637 stats->tx256to511octets_gb +=
638 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX256TO511OCTETS_GB_HI) << 32);
640 stats->tx512to1023octets_gb +=
641 AXGMAC_IOREAD(pdata, MMC_TX512TO1023OCTETS_GB_LO);
642 stats->tx512to1023octets_gb +=
643 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX512TO1023OCTETS_GB_HI) << 32);
645 stats->tx1024tomaxoctets_gb +=
646 AXGMAC_IOREAD(pdata, MMC_TX1024TOMAXOCTETS_GB_LO);
647 stats->tx1024tomaxoctets_gb +=
648 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX1024TOMAXOCTETS_GB_HI) << 32);
650 stats->txunicastframes_gb +=
651 AXGMAC_IOREAD(pdata, MMC_TXUNICASTFRAMES_GB_LO);
652 stats->txunicastframes_gb +=
653 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXUNICASTFRAMES_GB_HI) << 32);
655 stats->txmulticastframes_gb +=
656 AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_GB_LO);
657 stats->txmulticastframes_gb +=
658 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_GB_HI) << 32);
660 stats->txbroadcastframes_g +=
661 AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_GB_LO);
662 stats->txbroadcastframes_g +=
663 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_GB_HI) << 32);
665 stats->txunderflowerror +=
666 AXGMAC_IOREAD(pdata, MMC_TXUNDERFLOWERROR_LO);
667 stats->txunderflowerror +=
668 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXUNDERFLOWERROR_HI) << 32);
670 stats->txoctetcount_g +=
671 AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_G_LO);
672 stats->txoctetcount_g +=
673 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_G_HI) << 32);
675 stats->txframecount_g +=
676 AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_G_LO);
677 stats->txframecount_g +=
678 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_G_HI) << 32);
680 stats->txpauseframes +=
681 AXGMAC_IOREAD(pdata, MMC_TXPAUSEFRAMES_LO);
682 stats->txpauseframes +=
683 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXPAUSEFRAMES_HI) << 32);
685 stats->txvlanframes_g +=
686 AXGMAC_IOREAD(pdata, MMC_TXVLANFRAMES_G_LO);
687 stats->txvlanframes_g +=
688 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXVLANFRAMES_G_HI) << 32);
691 stats->rxframecount_gb +=
692 AXGMAC_IOREAD(pdata, MMC_RXFRAMECOUNT_GB_LO);
693 stats->rxframecount_gb +=
694 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXFRAMECOUNT_GB_HI) << 32);
696 stats->rxoctetcount_gb +=
697 AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_GB_LO);
698 stats->rxoctetcount_gb +=
699 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_GB_HI) << 32);
701 stats->rxoctetcount_g +=
702 AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_G_LO);
703 stats->rxoctetcount_g +=
704 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_G_HI) << 32);
706 stats->rxbroadcastframes_g +=
707 AXGMAC_IOREAD(pdata, MMC_RXBROADCASTFRAMES_G_LO);
708 stats->rxbroadcastframes_g +=
709 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXBROADCASTFRAMES_G_HI) << 32);
711 stats->rxmulticastframes_g +=
712 AXGMAC_IOREAD(pdata, MMC_RXMULTICASTFRAMES_G_LO);
713 stats->rxmulticastframes_g +=
714 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXMULTICASTFRAMES_G_HI) << 32);
717 AXGMAC_IOREAD(pdata, MMC_RXCRCERROR_LO);
719 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXCRCERROR_HI) << 32);
721 stats->rxrunterror +=
722 AXGMAC_IOREAD(pdata, MMC_RXRUNTERROR);
724 stats->rxjabbererror +=
725 AXGMAC_IOREAD(pdata, MMC_RXJABBERERROR);
727 stats->rxundersize_g +=
728 AXGMAC_IOREAD(pdata, MMC_RXUNDERSIZE_G);
730 stats->rxoversize_g +=
731 AXGMAC_IOREAD(pdata, MMC_RXOVERSIZE_G);
733 stats->rx64octets_gb +=
734 AXGMAC_IOREAD(pdata, MMC_RX64OCTETS_GB_LO);
735 stats->rx64octets_gb +=
736 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX64OCTETS_GB_HI) << 32);
738 stats->rx65to127octets_gb +=
739 AXGMAC_IOREAD(pdata, MMC_RX65TO127OCTETS_GB_LO);
740 stats->rx65to127octets_gb +=
741 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX65TO127OCTETS_GB_HI) << 32);
743 stats->rx128to255octets_gb +=
744 AXGMAC_IOREAD(pdata, MMC_RX128TO255OCTETS_GB_LO);
745 stats->rx128to255octets_gb +=
746 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX128TO255OCTETS_GB_HI) << 32);
748 stats->rx256to511octets_gb +=
749 AXGMAC_IOREAD(pdata, MMC_RX256TO511OCTETS_GB_LO);
750 stats->rx256to511octets_gb +=
751 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX256TO511OCTETS_GB_HI) << 32);
753 stats->rx512to1023octets_gb +=
754 AXGMAC_IOREAD(pdata, MMC_RX512TO1023OCTETS_GB_LO);
755 stats->rx512to1023octets_gb +=
756 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX512TO1023OCTETS_GB_HI) << 32);
758 stats->rx1024tomaxoctets_gb +=
759 AXGMAC_IOREAD(pdata, MMC_RX1024TOMAXOCTETS_GB_LO);
760 stats->rx1024tomaxoctets_gb +=
761 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX1024TOMAXOCTETS_GB_HI) << 32);
763 stats->rxunicastframes_g +=
764 AXGMAC_IOREAD(pdata, MMC_RXUNICASTFRAMES_G_LO);
765 stats->rxunicastframes_g +=
766 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXUNICASTFRAMES_G_HI) << 32);
768 stats->rxlengtherror +=
769 AXGMAC_IOREAD(pdata, MMC_RXLENGTHERROR_LO);
770 stats->rxlengtherror +=
771 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXLENGTHERROR_HI) << 32);
773 stats->rxoutofrangetype +=
774 AXGMAC_IOREAD(pdata, MMC_RXOUTOFRANGETYPE_LO);
775 stats->rxoutofrangetype +=
776 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXOUTOFRANGETYPE_HI) << 32);
778 stats->rxpauseframes +=
779 AXGMAC_IOREAD(pdata, MMC_RXPAUSEFRAMES_LO);
780 stats->rxpauseframes +=
781 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXPAUSEFRAMES_HI) << 32);
783 stats->rxfifooverflow +=
784 AXGMAC_IOREAD(pdata, MMC_RXFIFOOVERFLOW_LO);
785 stats->rxfifooverflow +=
786 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXFIFOOVERFLOW_HI) << 32);
788 stats->rxvlanframes_gb +=
789 AXGMAC_IOREAD(pdata, MMC_RXVLANFRAMES_GB_LO);
790 stats->rxvlanframes_gb +=
791 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXVLANFRAMES_GB_HI) << 32);
793 stats->rxwatchdogerror +=
794 AXGMAC_IOREAD(pdata, MMC_RXWATCHDOGERROR);
796 /* Un-freeze counters */
797 AXGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 0);
801 axgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats,
804 struct axgbe_port *pdata = dev->data->dev_private;
810 axgbe_read_mmc_stats(pdata);
812 for (i = 0; i < n && i < AXGBE_XSTATS_COUNT; i++) {
814 stats[i].value = *(u64 *)((uint8_t *)&pdata->mmc_stats +
815 axgbe_xstats_strings[i].offset);
822 axgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
823 struct rte_eth_xstat_name *xstats_names,
828 if (n >= AXGBE_XSTATS_COUNT && xstats_names) {
829 for (i = 0; i < AXGBE_XSTATS_COUNT; ++i) {
830 snprintf(xstats_names[i].name,
831 RTE_ETH_XSTATS_NAME_SIZE, "%s",
832 axgbe_xstats_strings[i].name);
836 return AXGBE_XSTATS_COUNT;
840 axgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
841 uint64_t *values, unsigned int n)
844 uint64_t values_copy[AXGBE_XSTATS_COUNT];
847 struct axgbe_port *pdata = dev->data->dev_private;
849 if (n < AXGBE_XSTATS_COUNT)
850 return AXGBE_XSTATS_COUNT;
852 axgbe_read_mmc_stats(pdata);
854 for (i = 0; i < AXGBE_XSTATS_COUNT; i++) {
855 values[i] = *(u64 *)((uint8_t *)&pdata->mmc_stats +
856 axgbe_xstats_strings[i].offset);
862 axgbe_dev_xstats_get_by_id(dev, NULL, values_copy, AXGBE_XSTATS_COUNT);
864 for (i = 0; i < n; i++) {
865 if (ids[i] >= AXGBE_XSTATS_COUNT) {
866 PMD_DRV_LOG(ERR, "id value isn't valid\n");
869 values[i] = values_copy[ids[i]];
875 axgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev,
876 struct rte_eth_xstat_name *xstats_names,
880 struct rte_eth_xstat_name xstats_names_copy[AXGBE_XSTATS_COUNT];
884 return axgbe_dev_xstats_get_names(dev, xstats_names, size);
886 axgbe_dev_xstats_get_names(dev, xstats_names_copy, size);
888 for (i = 0; i < size; i++) {
889 if (ids[i] >= AXGBE_XSTATS_COUNT) {
890 PMD_DRV_LOG(ERR, "id value isn't valid\n");
893 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
899 axgbe_dev_xstats_reset(struct rte_eth_dev *dev)
901 struct axgbe_port *pdata = dev->data->dev_private;
902 struct axgbe_mmc_stats *stats = &pdata->mmc_stats;
904 /* MMC registers are configured for reset on read */
905 axgbe_read_mmc_stats(pdata);
908 memset(stats, 0, sizeof(*stats));
914 axgbe_dev_stats_get(struct rte_eth_dev *dev,
915 struct rte_eth_stats *stats)
917 struct axgbe_rx_queue *rxq;
918 struct axgbe_tx_queue *txq;
919 struct axgbe_port *pdata = dev->data->dev_private;
920 struct axgbe_mmc_stats *mmc_stats = &pdata->mmc_stats;
923 axgbe_read_mmc_stats(pdata);
925 stats->imissed = mmc_stats->rxfifooverflow;
927 for (i = 0; i < dev->data->nb_rx_queues; i++) {
928 rxq = dev->data->rx_queues[i];
929 stats->q_ipackets[i] = rxq->pkts;
930 stats->ipackets += rxq->pkts;
931 stats->q_ibytes[i] = rxq->bytes;
932 stats->ibytes += rxq->bytes;
933 stats->rx_nombuf += rxq->rx_mbuf_alloc_failed;
934 stats->q_errors[i] = rxq->errors + rxq->rx_mbuf_alloc_failed;
935 stats->ierrors += rxq->errors;
938 for (i = 0; i < dev->data->nb_tx_queues; i++) {
939 txq = dev->data->tx_queues[i];
940 stats->q_opackets[i] = txq->pkts;
941 stats->opackets += txq->pkts;
942 stats->q_obytes[i] = txq->bytes;
943 stats->obytes += txq->bytes;
944 stats->oerrors += txq->errors;
951 axgbe_dev_stats_reset(struct rte_eth_dev *dev)
953 struct axgbe_rx_queue *rxq;
954 struct axgbe_tx_queue *txq;
957 for (i = 0; i < dev->data->nb_rx_queues; i++) {
958 rxq = dev->data->rx_queues[i];
962 rxq->rx_mbuf_alloc_failed = 0;
964 for (i = 0; i < dev->data->nb_tx_queues; i++) {
965 txq = dev->data->tx_queues[i];
975 axgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
977 struct axgbe_port *pdata = dev->data->dev_private;
979 dev_info->max_rx_queues = pdata->rx_ring_count;
980 dev_info->max_tx_queues = pdata->tx_ring_count;
981 dev_info->min_rx_bufsize = AXGBE_RX_MIN_BUF_SIZE;
982 dev_info->max_rx_pktlen = AXGBE_RX_MAX_BUF_SIZE;
983 dev_info->max_mac_addrs = pdata->hw_feat.addn_mac + 1;
984 dev_info->max_hash_mac_addrs = pdata->hw_feat.hash_table_size;
985 dev_info->speed_capa = ETH_LINK_SPEED_10G;
987 dev_info->rx_offload_capa =
988 DEV_RX_OFFLOAD_IPV4_CKSUM |
989 DEV_RX_OFFLOAD_UDP_CKSUM |
990 DEV_RX_OFFLOAD_TCP_CKSUM |
991 DEV_RX_OFFLOAD_JUMBO_FRAME |
992 DEV_RX_OFFLOAD_SCATTER |
993 DEV_RX_OFFLOAD_KEEP_CRC;
995 dev_info->tx_offload_capa =
996 DEV_TX_OFFLOAD_IPV4_CKSUM |
997 DEV_TX_OFFLOAD_UDP_CKSUM |
998 DEV_TX_OFFLOAD_TCP_CKSUM;
1000 if (pdata->hw_feat.rss) {
1001 dev_info->flow_type_rss_offloads = AXGBE_RSS_OFFLOAD;
1002 dev_info->reta_size = pdata->hw_feat.hash_table_size;
1003 dev_info->hash_key_size = AXGBE_RSS_HASH_KEY_SIZE;
1006 dev_info->rx_desc_lim = rx_desc_lim;
1007 dev_info->tx_desc_lim = tx_desc_lim;
1009 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1010 .rx_free_thresh = AXGBE_RX_FREE_THRESH,
1013 dev_info->default_txconf = (struct rte_eth_txconf) {
1014 .tx_free_thresh = AXGBE_TX_FREE_THRESH,
1021 axgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1023 struct axgbe_port *pdata = dev->data->dev_private;
1024 struct xgbe_fc_info fc = pdata->fc;
1025 unsigned int reg, reg_val = 0;
1028 reg_val = AXGMAC_IOREAD(pdata, reg);
1029 fc.low_water[0] = AXGMAC_MTL_IOREAD_BITS(pdata, 0, MTL_Q_RQFCR, RFA);
1030 fc.high_water[0] = AXGMAC_MTL_IOREAD_BITS(pdata, 0, MTL_Q_RQFCR, RFD);
1031 fc.pause_time[0] = AXGMAC_GET_BITS(reg_val, MAC_Q0TFCR, PT);
1032 fc.autoneg = pdata->pause_autoneg;
1034 if (pdata->rx_pause && pdata->tx_pause)
1035 fc.mode = RTE_FC_FULL;
1036 else if (pdata->rx_pause)
1037 fc.mode = RTE_FC_RX_PAUSE;
1038 else if (pdata->tx_pause)
1039 fc.mode = RTE_FC_TX_PAUSE;
1041 fc.mode = RTE_FC_NONE;
1043 fc_conf->high_water = (1024 + (fc.low_water[0] << 9)) / 1024;
1044 fc_conf->low_water = (1024 + (fc.high_water[0] << 9)) / 1024;
1045 fc_conf->pause_time = fc.pause_time[0];
1046 fc_conf->send_xon = fc.send_xon;
1047 fc_conf->mode = fc.mode;
1053 axgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1055 struct axgbe_port *pdata = dev->data->dev_private;
1056 struct xgbe_fc_info fc = pdata->fc;
1057 unsigned int reg, reg_val = 0;
1060 pdata->pause_autoneg = fc_conf->autoneg;
1061 pdata->phy.pause_autoneg = pdata->pause_autoneg;
1062 fc.send_xon = fc_conf->send_xon;
1063 AXGMAC_MTL_IOWRITE_BITS(pdata, 0, MTL_Q_RQFCR, RFA,
1064 AXGMAC_FLOW_CONTROL_VALUE(1024 * fc_conf->high_water));
1065 AXGMAC_MTL_IOWRITE_BITS(pdata, 0, MTL_Q_RQFCR, RFD,
1066 AXGMAC_FLOW_CONTROL_VALUE(1024 * fc_conf->low_water));
1067 AXGMAC_SET_BITS(reg_val, MAC_Q0TFCR, PT, fc_conf->pause_time);
1068 AXGMAC_IOWRITE(pdata, reg, reg_val);
1069 fc.mode = fc_conf->mode;
1071 if (fc.mode == RTE_FC_FULL) {
1072 pdata->tx_pause = 1;
1073 pdata->rx_pause = 1;
1074 } else if (fc.mode == RTE_FC_RX_PAUSE) {
1075 pdata->tx_pause = 0;
1076 pdata->rx_pause = 1;
1077 } else if (fc.mode == RTE_FC_TX_PAUSE) {
1078 pdata->tx_pause = 1;
1079 pdata->rx_pause = 0;
1081 pdata->tx_pause = 0;
1082 pdata->rx_pause = 0;
1085 if (pdata->tx_pause != (unsigned int)pdata->phy.tx_pause)
1086 pdata->hw_if.config_tx_flow_control(pdata);
1088 if (pdata->rx_pause != (unsigned int)pdata->phy.rx_pause)
1089 pdata->hw_if.config_rx_flow_control(pdata);
1091 pdata->hw_if.config_flow_control(pdata);
1092 pdata->phy.tx_pause = pdata->tx_pause;
1093 pdata->phy.rx_pause = pdata->rx_pause;
1099 axgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
1100 struct rte_eth_pfc_conf *pfc_conf)
1102 struct axgbe_port *pdata = dev->data->dev_private;
1103 struct xgbe_fc_info fc = pdata->fc;
1106 tc_num = pdata->pfc_map[pfc_conf->priority];
1108 if (pfc_conf->priority >= pdata->hw_feat.tc_cnt) {
1109 PMD_INIT_LOG(ERR, "Max supported traffic class: %d\n",
1110 pdata->hw_feat.tc_cnt);
1114 pdata->pause_autoneg = pfc_conf->fc.autoneg;
1115 pdata->phy.pause_autoneg = pdata->pause_autoneg;
1116 fc.send_xon = pfc_conf->fc.send_xon;
1117 AXGMAC_MTL_IOWRITE_BITS(pdata, tc_num, MTL_Q_RQFCR, RFA,
1118 AXGMAC_FLOW_CONTROL_VALUE(1024 * pfc_conf->fc.high_water));
1119 AXGMAC_MTL_IOWRITE_BITS(pdata, tc_num, MTL_Q_RQFCR, RFD,
1120 AXGMAC_FLOW_CONTROL_VALUE(1024 * pfc_conf->fc.low_water));
1124 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R,
1125 PSTC0, pfc_conf->fc.pause_time);
1128 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R,
1129 PSTC1, pfc_conf->fc.pause_time);
1132 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R,
1133 PSTC2, pfc_conf->fc.pause_time);
1136 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R,
1137 PSTC3, pfc_conf->fc.pause_time);
1140 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R,
1141 PSTC4, pfc_conf->fc.pause_time);
1144 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R,
1145 PSTC5, pfc_conf->fc.pause_time);
1148 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R,
1149 PSTC6, pfc_conf->fc.pause_time);
1152 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R,
1153 PSTC7, pfc_conf->fc.pause_time);
1157 fc.mode = pfc_conf->fc.mode;
1159 if (fc.mode == RTE_FC_FULL) {
1160 pdata->tx_pause = 1;
1161 pdata->rx_pause = 1;
1162 AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 1);
1163 } else if (fc.mode == RTE_FC_RX_PAUSE) {
1164 pdata->tx_pause = 0;
1165 pdata->rx_pause = 1;
1166 AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 1);
1167 } else if (fc.mode == RTE_FC_TX_PAUSE) {
1168 pdata->tx_pause = 1;
1169 pdata->rx_pause = 0;
1170 AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 0);
1172 pdata->tx_pause = 0;
1173 pdata->rx_pause = 0;
1174 AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 0);
1177 if (pdata->tx_pause != (unsigned int)pdata->phy.tx_pause)
1178 pdata->hw_if.config_tx_flow_control(pdata);
1180 if (pdata->rx_pause != (unsigned int)pdata->phy.rx_pause)
1181 pdata->hw_if.config_rx_flow_control(pdata);
1182 pdata->hw_if.config_flow_control(pdata);
1183 pdata->phy.tx_pause = pdata->tx_pause;
1184 pdata->phy.rx_pause = pdata->rx_pause;
1189 static void axgbe_get_all_hw_features(struct axgbe_port *pdata)
1191 unsigned int mac_hfr0, mac_hfr1, mac_hfr2;
1192 struct axgbe_hw_features *hw_feat = &pdata->hw_feat;
1194 mac_hfr0 = AXGMAC_IOREAD(pdata, MAC_HWF0R);
1195 mac_hfr1 = AXGMAC_IOREAD(pdata, MAC_HWF1R);
1196 mac_hfr2 = AXGMAC_IOREAD(pdata, MAC_HWF2R);
1198 memset(hw_feat, 0, sizeof(*hw_feat));
1200 hw_feat->version = AXGMAC_IOREAD(pdata, MAC_VR);
1202 /* Hardware feature register 0 */
1203 hw_feat->gmii = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL);
1204 hw_feat->vlhash = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH);
1205 hw_feat->sma = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SMASEL);
1206 hw_feat->rwk = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RWKSEL);
1207 hw_feat->mgk = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MGKSEL);
1208 hw_feat->mmc = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MMCSEL);
1209 hw_feat->aoe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ARPOFFSEL);
1210 hw_feat->ts = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSEL);
1211 hw_feat->eee = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, EEESEL);
1212 hw_feat->tx_coe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TXCOESEL);
1213 hw_feat->rx_coe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RXCOESEL);
1214 hw_feat->addn_mac = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R,
1216 hw_feat->ts_src = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSTSSEL);
1217 hw_feat->sa_vlan_ins = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SAVLANINS);
1219 /* Hardware feature register 1 */
1220 hw_feat->rx_fifo_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
1222 hw_feat->tx_fifo_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
1224 hw_feat->adv_ts_hi = AXGMAC_GET_BITS(mac_hfr1,
1225 MAC_HWF1R, ADVTHWORD);
1226 hw_feat->dma_width = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADDR64);
1227 hw_feat->dcb = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN);
1228 hw_feat->sph = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN);
1229 hw_feat->tso = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN);
1230 hw_feat->dma_debug = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA);
1231 hw_feat->rss = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, RSSEN);
1232 hw_feat->tc_cnt = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC);
1233 hw_feat->hash_table_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
1235 hw_feat->l3l4_filter_num = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
1238 /* Hardware feature register 2 */
1239 hw_feat->rx_q_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXQCNT);
1240 hw_feat->tx_q_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXQCNT);
1241 hw_feat->rx_ch_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXCHCNT);
1242 hw_feat->tx_ch_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXCHCNT);
1243 hw_feat->pps_out_num = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM);
1244 hw_feat->aux_snap_num = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R,
1247 /* Translate the Hash Table size into actual number */
1248 switch (hw_feat->hash_table_size) {
1252 hw_feat->hash_table_size = 64;
1255 hw_feat->hash_table_size = 128;
1258 hw_feat->hash_table_size = 256;
1262 /* Translate the address width setting into actual number */
1263 switch (hw_feat->dma_width) {
1265 hw_feat->dma_width = 32;
1268 hw_feat->dma_width = 40;
1271 hw_feat->dma_width = 48;
1274 hw_feat->dma_width = 32;
1277 /* The Queue, Channel and TC counts are zero based so increment them
1278 * to get the actual number
1280 hw_feat->rx_q_cnt++;
1281 hw_feat->tx_q_cnt++;
1282 hw_feat->rx_ch_cnt++;
1283 hw_feat->tx_ch_cnt++;
1286 /* Translate the fifo sizes into actual numbers */
1287 hw_feat->rx_fifo_size = 1 << (hw_feat->rx_fifo_size + 7);
1288 hw_feat->tx_fifo_size = 1 << (hw_feat->tx_fifo_size + 7);
1291 static void axgbe_init_all_fptrs(struct axgbe_port *pdata)
1293 axgbe_init_function_ptrs_dev(&pdata->hw_if);
1294 axgbe_init_function_ptrs_phy(&pdata->phy_if);
1295 axgbe_init_function_ptrs_i2c(&pdata->i2c_if);
1296 pdata->vdata->init_function_ptrs_phy_impl(&pdata->phy_if);
1299 static void axgbe_set_counts(struct axgbe_port *pdata)
1301 /* Set all the function pointers */
1302 axgbe_init_all_fptrs(pdata);
1304 /* Populate the hardware features */
1305 axgbe_get_all_hw_features(pdata);
1307 /* Set default max values if not provided */
1308 if (!pdata->tx_max_channel_count)
1309 pdata->tx_max_channel_count = pdata->hw_feat.tx_ch_cnt;
1310 if (!pdata->rx_max_channel_count)
1311 pdata->rx_max_channel_count = pdata->hw_feat.rx_ch_cnt;
1313 if (!pdata->tx_max_q_count)
1314 pdata->tx_max_q_count = pdata->hw_feat.tx_q_cnt;
1315 if (!pdata->rx_max_q_count)
1316 pdata->rx_max_q_count = pdata->hw_feat.rx_q_cnt;
1318 /* Calculate the number of Tx and Rx rings to be created
1319 * -Tx (DMA) Channels map 1-to-1 to Tx Queues so set
1320 * the number of Tx queues to the number of Tx channels
1322 * -Rx (DMA) Channels do not map 1-to-1 so use the actual
1323 * number of Rx queues or maximum allowed
1325 pdata->tx_ring_count = RTE_MIN(pdata->hw_feat.tx_ch_cnt,
1326 pdata->tx_max_channel_count);
1327 pdata->tx_ring_count = RTE_MIN(pdata->tx_ring_count,
1328 pdata->tx_max_q_count);
1330 pdata->tx_q_count = pdata->tx_ring_count;
1332 pdata->rx_ring_count = RTE_MIN(pdata->hw_feat.rx_ch_cnt,
1333 pdata->rx_max_channel_count);
1335 pdata->rx_q_count = RTE_MIN(pdata->hw_feat.rx_q_cnt,
1336 pdata->rx_max_q_count);
1339 static void axgbe_default_config(struct axgbe_port *pdata)
1341 pdata->pblx8 = DMA_PBL_X8_ENABLE;
1342 pdata->tx_sf_mode = MTL_TSF_ENABLE;
1343 pdata->tx_threshold = MTL_TX_THRESHOLD_64;
1344 pdata->tx_pbl = DMA_PBL_32;
1345 pdata->tx_osp_mode = DMA_OSP_ENABLE;
1346 pdata->rx_sf_mode = MTL_RSF_ENABLE;
1347 pdata->rx_threshold = MTL_RX_THRESHOLD_64;
1348 pdata->rx_pbl = DMA_PBL_32;
1349 pdata->pause_autoneg = 1;
1350 pdata->tx_pause = 0;
1351 pdata->rx_pause = 0;
1352 pdata->phy_speed = SPEED_UNKNOWN;
1353 pdata->power_down = 0;
1357 pci_device_cmp(const struct rte_device *dev, const void *_pci_id)
1359 const struct rte_pci_device *pdev = RTE_DEV_TO_PCI_CONST(dev);
1360 const struct rte_pci_id *pcid = _pci_id;
1362 if (pdev->id.vendor_id == AMD_PCI_VENDOR_ID &&
1363 pdev->id.device_id == pcid->device_id)
1369 pci_search_device(int device_id)
1371 struct rte_bus *pci_bus;
1372 struct rte_pci_id dev_id;
1374 dev_id.device_id = device_id;
1375 pci_bus = rte_bus_find_by_name("pci");
1376 return (pci_bus != NULL) &&
1377 (pci_bus->find_device(NULL, pci_device_cmp, &dev_id) != NULL);
1381 * It returns 0 on success.
1384 eth_axgbe_dev_init(struct rte_eth_dev *eth_dev)
1386 PMD_INIT_FUNC_TRACE();
1387 struct axgbe_port *pdata;
1388 struct rte_pci_device *pci_dev;
1389 uint32_t reg, mac_lo, mac_hi;
1393 eth_dev->dev_ops = &axgbe_eth_dev_ops;
1396 * For secondary processes, we don't initialise any further as primary
1397 * has already done this work.
1399 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1402 pdata = eth_dev->data->dev_private;
1404 axgbe_set_bit(AXGBE_DOWN, &pdata->dev_state);
1405 axgbe_set_bit(AXGBE_STOPPED, &pdata->dev_state);
1406 pdata->eth_dev = eth_dev;
1408 pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1409 pdata->pci_dev = pci_dev;
1412 * Use root complex device ID to differentiate RV AXGBE vs SNOWY AXGBE
1414 if (pci_search_device(AMD_PCI_RV_ROOT_COMPLEX_ID)) {
1415 pdata->xpcs_window_def_reg = PCS_V2_RV_WINDOW_DEF;
1416 pdata->xpcs_window_sel_reg = PCS_V2_RV_WINDOW_SELECT;
1418 pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF;
1419 pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT;
1423 (void *)pci_dev->mem_resource[AXGBE_AXGMAC_BAR].addr;
1424 pdata->xprop_regs = (void *)((uint8_t *)pdata->xgmac_regs
1425 + AXGBE_MAC_PROP_OFFSET);
1426 pdata->xi2c_regs = (void *)((uint8_t *)pdata->xgmac_regs
1427 + AXGBE_I2C_CTRL_OFFSET);
1428 pdata->xpcs_regs = (void *)pci_dev->mem_resource[AXGBE_XPCS_BAR].addr;
1430 /* version specific driver data*/
1431 if (pci_dev->id.device_id == AMD_PCI_AXGBE_DEVICE_V2A)
1432 pdata->vdata = &axgbe_v2a;
1434 pdata->vdata = &axgbe_v2b;
1436 /* Configure the PCS indirect addressing support */
1437 reg = XPCS32_IOREAD(pdata, pdata->xpcs_window_def_reg);
1438 pdata->xpcs_window = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, OFFSET);
1439 pdata->xpcs_window <<= 6;
1440 pdata->xpcs_window_size = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, SIZE);
1441 pdata->xpcs_window_size = 1 << (pdata->xpcs_window_size + 7);
1442 pdata->xpcs_window_mask = pdata->xpcs_window_size - 1;
1445 "xpcs window :%x, size :%x, mask :%x ", pdata->xpcs_window,
1446 pdata->xpcs_window_size, pdata->xpcs_window_mask);
1447 XP_IOWRITE(pdata, XP_INT_EN, 0x1fffff);
1449 /* Retrieve the MAC address */
1450 mac_lo = XP_IOREAD(pdata, XP_MAC_ADDR_LO);
1451 mac_hi = XP_IOREAD(pdata, XP_MAC_ADDR_HI);
1452 pdata->mac_addr.addr_bytes[0] = mac_lo & 0xff;
1453 pdata->mac_addr.addr_bytes[1] = (mac_lo >> 8) & 0xff;
1454 pdata->mac_addr.addr_bytes[2] = (mac_lo >> 16) & 0xff;
1455 pdata->mac_addr.addr_bytes[3] = (mac_lo >> 24) & 0xff;
1456 pdata->mac_addr.addr_bytes[4] = mac_hi & 0xff;
1457 pdata->mac_addr.addr_bytes[5] = (mac_hi >> 8) & 0xff;
1459 len = RTE_ETHER_ADDR_LEN * AXGBE_MAX_MAC_ADDRS;
1460 eth_dev->data->mac_addrs = rte_zmalloc("axgbe_mac_addr", len, 0);
1462 if (!eth_dev->data->mac_addrs) {
1464 "Failed to alloc %u bytes needed to "
1465 "store MAC addresses", len);
1469 /* Allocate memory for storing hash filter MAC addresses */
1470 len = RTE_ETHER_ADDR_LEN * AXGBE_MAX_HASH_MAC_ADDRS;
1471 eth_dev->data->hash_mac_addrs = rte_zmalloc("axgbe_hash_mac_addr",
1474 if (eth_dev->data->hash_mac_addrs == NULL) {
1476 "Failed to allocate %d bytes needed to "
1477 "store MAC addresses", len);
1481 if (!rte_is_valid_assigned_ether_addr(&pdata->mac_addr))
1482 rte_eth_random_addr(pdata->mac_addr.addr_bytes);
1484 /* Copy the permanent MAC address */
1485 rte_ether_addr_copy(&pdata->mac_addr, ð_dev->data->mac_addrs[0]);
1487 /* Clock settings */
1488 pdata->sysclk_rate = AXGBE_V2_DMA_CLOCK_FREQ;
1489 pdata->ptpclk_rate = AXGBE_V2_PTP_CLOCK_FREQ;
1491 /* Set the DMA coherency values */
1492 pdata->coherent = 1;
1493 pdata->axdomain = AXGBE_DMA_OS_AXDOMAIN;
1494 pdata->arcache = AXGBE_DMA_OS_ARCACHE;
1495 pdata->awcache = AXGBE_DMA_OS_AWCACHE;
1497 /* Set the maximum channels and queues */
1498 reg = XP_IOREAD(pdata, XP_PROP_1);
1499 pdata->tx_max_channel_count = XP_GET_BITS(reg, XP_PROP_1, MAX_TX_DMA);
1500 pdata->rx_max_channel_count = XP_GET_BITS(reg, XP_PROP_1, MAX_RX_DMA);
1501 pdata->tx_max_q_count = XP_GET_BITS(reg, XP_PROP_1, MAX_TX_QUEUES);
1502 pdata->rx_max_q_count = XP_GET_BITS(reg, XP_PROP_1, MAX_RX_QUEUES);
1504 /* Set the hardware channel and queue counts */
1505 axgbe_set_counts(pdata);
1507 /* Set the maximum fifo amounts */
1508 reg = XP_IOREAD(pdata, XP_PROP_2);
1509 pdata->tx_max_fifo_size = XP_GET_BITS(reg, XP_PROP_2, TX_FIFO_SIZE);
1510 pdata->tx_max_fifo_size *= 16384;
1511 pdata->tx_max_fifo_size = RTE_MIN(pdata->tx_max_fifo_size,
1512 pdata->vdata->tx_max_fifo_size);
1513 pdata->rx_max_fifo_size = XP_GET_BITS(reg, XP_PROP_2, RX_FIFO_SIZE);
1514 pdata->rx_max_fifo_size *= 16384;
1515 pdata->rx_max_fifo_size = RTE_MIN(pdata->rx_max_fifo_size,
1516 pdata->vdata->rx_max_fifo_size);
1517 /* Issue software reset to DMA */
1518 ret = pdata->hw_if.exit(pdata);
1520 PMD_DRV_LOG(ERR, "hw_if->exit EBUSY error\n");
1522 /* Set default configuration data */
1523 axgbe_default_config(pdata);
1525 /* Set default max values if not provided */
1526 if (!pdata->tx_max_fifo_size)
1527 pdata->tx_max_fifo_size = pdata->hw_feat.tx_fifo_size;
1528 if (!pdata->rx_max_fifo_size)
1529 pdata->rx_max_fifo_size = pdata->hw_feat.rx_fifo_size;
1531 pdata->tx_desc_count = AXGBE_MAX_RING_DESC;
1532 pdata->rx_desc_count = AXGBE_MAX_RING_DESC;
1533 pthread_mutex_init(&pdata->xpcs_mutex, NULL);
1534 pthread_mutex_init(&pdata->i2c_mutex, NULL);
1535 pthread_mutex_init(&pdata->an_mutex, NULL);
1536 pthread_mutex_init(&pdata->phy_mutex, NULL);
1538 ret = pdata->phy_if.phy_init(pdata);
1540 rte_free(eth_dev->data->mac_addrs);
1541 eth_dev->data->mac_addrs = NULL;
1545 rte_intr_callback_register(&pci_dev->intr_handle,
1546 axgbe_dev_interrupt_handler,
1548 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1549 eth_dev->data->port_id, pci_dev->id.vendor_id,
1550 pci_dev->id.device_id);
1556 eth_axgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1558 struct rte_pci_device *pci_dev;
1560 PMD_INIT_FUNC_TRACE();
1562 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1565 pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1566 eth_dev->dev_ops = NULL;
1567 eth_dev->rx_pkt_burst = NULL;
1568 eth_dev->tx_pkt_burst = NULL;
1569 axgbe_dev_clear_queues(eth_dev);
1571 /* disable uio intr before callback unregister */
1572 rte_intr_disable(&pci_dev->intr_handle);
1573 rte_intr_callback_unregister(&pci_dev->intr_handle,
1574 axgbe_dev_interrupt_handler,
1580 static int eth_axgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1581 struct rte_pci_device *pci_dev)
1583 return rte_eth_dev_pci_generic_probe(pci_dev,
1584 sizeof(struct axgbe_port), eth_axgbe_dev_init);
1587 static int eth_axgbe_pci_remove(struct rte_pci_device *pci_dev)
1589 return rte_eth_dev_pci_generic_remove(pci_dev, eth_axgbe_dev_uninit);
1592 static struct rte_pci_driver rte_axgbe_pmd = {
1593 .id_table = pci_id_axgbe_map,
1594 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1595 .probe = eth_axgbe_pci_probe,
1596 .remove = eth_axgbe_pci_remove,
1599 RTE_PMD_REGISTER_PCI(net_axgbe, rte_axgbe_pmd);
1600 RTE_PMD_REGISTER_PCI_TABLE(net_axgbe, pci_id_axgbe_map);
1601 RTE_PMD_REGISTER_KMOD_DEP(net_axgbe, "* igb_uio | uio_pci_generic | vfio-pci");
1603 RTE_INIT(axgbe_init_log)
1605 axgbe_logtype_init = rte_log_register("pmd.net.axgbe.init");
1606 if (axgbe_logtype_init >= 0)
1607 rte_log_set_level(axgbe_logtype_init, RTE_LOG_NOTICE);
1608 axgbe_logtype_driver = rte_log_register("pmd.net.axgbe.driver");
1609 if (axgbe_logtype_driver >= 0)
1610 rte_log_set_level(axgbe_logtype_driver, RTE_LOG_NOTICE);