1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved.
3 * Copyright(c) 2018 Synopsys, Inc. All rights reserved.
6 #ifndef RTE_ETH_AXGBE_H_
7 #define RTE_ETH_AXGBE_H_
9 #include <rte_mempool.h>
10 #include <rte_lcore.h>
11 #include "axgbe_common.h"
17 #define AXGBE_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1))
18 #define AXGBE_RX_MAX_BUF_SIZE (0x3fff & ~(64 - 1))
19 #define AXGBE_RX_MIN_BUF_SIZE (RTE_ETHER_MAX_LEN + VLAN_HLEN)
20 #define AXGBE_MAX_MAC_ADDRS 32
21 #define AXGBE_MAX_HASH_MAC_ADDRS 256
23 #define AXGBE_RX_BUF_ALIGN 64
25 #define AXGBE_MAX_DMA_CHANNELS 16
26 #define AXGBE_MAX_QUEUES 16
27 #define AXGBE_PRIORITY_QUEUES 8
28 #define AXGBE_DMA_STOP_TIMEOUT 1
30 /* DMA cache settings - Outer sharable, write-back, write-allocate */
31 #define AXGBE_DMA_OS_AXDOMAIN 0x2
32 #define AXGBE_DMA_OS_ARCACHE 0xb
33 #define AXGBE_DMA_OS_AWCACHE 0xf
35 /* DMA cache settings - System, no caches used */
36 #define AXGBE_DMA_SYS_AXDOMAIN 0x3
37 #define AXGBE_DMA_SYS_ARCACHE 0x0
38 #define AXGBE_DMA_SYS_AWCACHE 0x0
40 /* DMA channel interrupt modes */
41 #define AXGBE_IRQ_MODE_EDGE 0
42 #define AXGBE_IRQ_MODE_LEVEL 1
44 #define AXGBE_DMA_INTERRUPT_MASK 0x31c7
46 #define AXGMAC_MIN_PACKET 60
47 #define AXGMAC_STD_PACKET_MTU 1500
48 #define AXGMAC_MAX_STD_PACKET 1518
49 #define AXGMAC_JUMBO_PACKET_MTU 9000
50 #define AXGMAC_MAX_JUMBO_PACKET 9018
51 /* Inter-frame gap + preamble */
52 #define AXGMAC_ETH_PREAMBLE (12 + 8)
54 #define AXGMAC_PFC_DATA_LEN 46
55 #define AXGMAC_PFC_DELAYS 14000
58 #define AXGBE_AXGMAC_BAR 0
59 #define AXGBE_XPCS_BAR 1
60 #define AXGBE_MAC_PROP_OFFSET 0x1d000
61 #define AXGBE_I2C_CTRL_OFFSET 0x1e000
63 /* PCI clock frequencies */
64 #define AXGBE_V2_DMA_CLOCK_FREQ 500000000
65 #define AXGBE_V2_PTP_CLOCK_FREQ 125000000
67 /* Timestamp support - values based on 50MHz PTP clock
70 #define AXGBE_TSTAMP_SSINC 20
71 #define AXGBE_TSTAMP_SNSINC 0
72 #define AXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
74 #define AXGMAC_FIFO_MIN_ALLOC 2048
75 #define AXGMAC_FIFO_UNIT 256
76 #define AXGMAC_FIFO_ALIGN(_x) \
77 (((_x) + AXGMAC_FIFO_UNIT - 1) & ~(XGMAC_FIFO_UNIT - 1))
78 #define AXGMAC_FIFO_FC_OFF 2048
79 #define AXGMAC_FIFO_FC_MIN 4096
81 #define AXGBE_TC_MIN_QUANTUM 10
83 /* Flow control queue count */
84 #define AXGMAC_MAX_FLOW_CONTROL_QUEUES 8
86 /* Flow control threshold units */
87 #define AXGMAC_FLOW_CONTROL_UNIT 512
88 #define AXGMAC_FLOW_CONTROL_ALIGN(_x) \
89 (((_x) + AXGMAC_FLOW_CONTROL_UNIT - 1) & \
90 ~(AXGMAC_FLOW_CONTROL_UNIT - 1))
91 #define AXGMAC_FLOW_CONTROL_VALUE(_x) \
92 (((_x) < 1024) ? 0 : ((_x) / AXGMAC_FLOW_CONTROL_UNIT) - 2)
93 #define AXGMAC_FLOW_CONTROL_MAX 33280
95 /* Maximum MAC address hash table size (256 bits = 8 dword) */
96 #define AXGBE_MAC_HASH_TABLE_SIZE 8
98 /* Receive Side Scaling */
99 #define AXGBE_RSS_OFFLOAD ( \
101 ETH_RSS_NONFRAG_IPV4_TCP | \
102 ETH_RSS_NONFRAG_IPV4_UDP | \
104 ETH_RSS_NONFRAG_IPV6_TCP | \
105 ETH_RSS_NONFRAG_IPV6_UDP)
107 #define AXGBE_RSS_HASH_KEY_SIZE 40
108 #define AXGBE_RSS_MAX_TABLE_SIZE 256
109 #define AXGBE_RSS_LOOKUP_TABLE_TYPE 0
110 #define AXGBE_RSS_HASH_KEY_TYPE 1
112 /* Auto-negotiation */
113 #define AXGBE_AN_MS_TIMEOUT 500
114 #define AXGBE_LINK_TIMEOUT 5
116 #define AXGBE_SGMII_AN_LINK_STATUS BIT(1)
117 #define AXGBE_SGMII_AN_LINK_SPEED (BIT(2) | BIT(3))
118 #define AXGBE_SGMII_AN_LINK_SPEED_100 0x04
119 #define AXGBE_SGMII_AN_LINK_SPEED_1000 0x08
120 #define AXGBE_SGMII_AN_LINK_DUPLEX BIT(4)
122 /* ECC correctable error notification window (seconds) */
123 #define AXGBE_ECC_LIMIT 60
125 /* MDIO port types */
126 #define AXGMAC_MAX_C22_PORT 3
128 /* Helper macro for descriptor handling
129 * Always use AXGBE_GET_DESC_DATA to access the descriptor data
130 * since the index is free-running and needs to be and-ed
131 * with the descriptor count value of the ring to index to
132 * the proper descriptor data.
134 #define AXGBE_GET_DESC_DATA(_ring, _idx) \
136 ((_idx) & ((_ring)->rdesc_count - 1)))
148 AXGMAC_INT_DMA_CH_SR_TI,
149 AXGMAC_INT_DMA_CH_SR_TPS,
150 AXGMAC_INT_DMA_CH_SR_TBU,
151 AXGMAC_INT_DMA_CH_SR_RI,
152 AXGMAC_INT_DMA_CH_SR_RBU,
153 AXGMAC_INT_DMA_CH_SR_RPS,
154 AXGMAC_INT_DMA_CH_SR_TI_RI,
155 AXGMAC_INT_DMA_CH_SR_FBE,
159 enum axgbe_int_state {
160 AXGMAC_INT_STATE_SAVE,
161 AXGMAC_INT_STATE_RESTORE,
171 AXGBE_SPEED_1000 = 0,
177 enum axgbe_xpcs_access {
178 AXGBE_XPCS_ACCESS_V1 = 0,
179 AXGBE_XPCS_ACCESS_V2,
183 AXGBE_AN_MODE_CL73 = 0,
184 AXGBE_AN_MODE_CL73_REDRV,
186 AXGBE_AN_MODE_CL37_SGMII,
192 AXGBE_AN_PAGE_RECEIVED,
193 AXGBE_AN_INCOMPAT_LINK,
207 AXGBE_MODE_KX_1000 = 0,
211 AXGBE_MODE_SGMII_100,
212 AXGBE_MODE_SGMII_1000,
217 enum axgbe_speedset {
218 AXGBE_SPEEDSET_1000_10000 = 0,
219 AXGBE_SPEEDSET_2500_10000,
222 enum axgbe_mdio_mode {
223 AXGBE_MDIO_MODE_NONE = 0,
224 AXGBE_MDIO_MODE_CL22,
225 AXGBE_MDIO_MODE_CL45,
230 uint32_t advertising;
231 uint32_t lp_advertising;
247 AXGBE_I2C_CMD_READ = 0,
251 struct axgbe_i2c_op {
252 enum axgbe_i2c_cmd cmd;
260 struct axgbe_i2c_op_state {
261 struct axgbe_i2c_op *op;
264 unsigned char *tx_buf;
267 unsigned char *rx_buf;
269 unsigned int tx_abort_source;
275 unsigned int started;
276 unsigned int max_speed_mode;
277 unsigned int rx_fifo_size;
278 unsigned int tx_fifo_size;
280 struct axgbe_i2c_op_state op_state;
284 void (*config_flow_control)(struct axgbe_port *);
285 int (*config_rx_mode)(struct axgbe_port *);
287 int (*init)(struct axgbe_port *);
289 int (*read_mmd_regs)(struct axgbe_port *, int, int);
290 void (*write_mmd_regs)(struct axgbe_port *, int, int, int);
291 int (*set_speed)(struct axgbe_port *, int);
293 int (*set_ext_mii_mode)(struct axgbe_port *, unsigned int,
294 enum axgbe_mdio_mode);
295 int (*read_ext_mii_regs)(struct axgbe_port *, int, int);
296 int (*write_ext_mii_regs)(struct axgbe_port *, int, int, uint16_t);
299 int (*config_tx_flow_control)(struct axgbe_port *);
300 int (*config_rx_flow_control)(struct axgbe_port *);
303 int (*enable_rx_vlan_stripping)(struct axgbe_port *);
304 int (*disable_rx_vlan_stripping)(struct axgbe_port *);
305 int (*enable_rx_vlan_filtering)(struct axgbe_port *);
306 int (*disable_rx_vlan_filtering)(struct axgbe_port *);
307 int (*update_vlan_hash_table)(struct axgbe_port *);
309 int (*exit)(struct axgbe_port *);
312 /* This structure represents implementation specific routines for an
313 * implementation of a PHY. All routines are required unless noted below.
315 * kr_training_pre, kr_training_post
317 struct axgbe_phy_impl_if {
318 /* Perform Setup/teardown actions */
319 int (*init)(struct axgbe_port *);
320 void (*exit)(struct axgbe_port *);
322 /* Perform start/stop specific actions */
323 int (*reset)(struct axgbe_port *);
324 int (*start)(struct axgbe_port *);
325 void (*stop)(struct axgbe_port *);
327 /* Return the link status */
328 int (*link_status)(struct axgbe_port *, int *);
330 /* Indicate if a particular speed is valid */
331 int (*valid_speed)(struct axgbe_port *, int);
333 /* Check if the specified mode can/should be used */
334 bool (*use_mode)(struct axgbe_port *, enum axgbe_mode);
335 /* Switch the PHY into various modes */
336 void (*set_mode)(struct axgbe_port *, enum axgbe_mode);
337 /* Retrieve mode needed for a specific speed */
338 enum axgbe_mode (*get_mode)(struct axgbe_port *, int);
339 /* Retrieve new/next mode when trying to auto-negotiate */
340 enum axgbe_mode (*switch_mode)(struct axgbe_port *);
341 /* Retrieve current mode */
342 enum axgbe_mode (*cur_mode)(struct axgbe_port *);
344 /* Retrieve current auto-negotiation mode */
345 enum axgbe_an_mode (*an_mode)(struct axgbe_port *);
347 /* Configure auto-negotiation settings */
348 int (*an_config)(struct axgbe_port *);
350 /* Set/override auto-negotiation advertisement settings */
351 unsigned int (*an_advertising)(struct axgbe_port *port);
353 /* Process results of auto-negotiation */
354 enum axgbe_mode (*an_outcome)(struct axgbe_port *);
356 /* Pre/Post auto-negotiation support */
357 void (*an_pre)(struct axgbe_port *port);
358 void (*an_post)(struct axgbe_port *port);
360 /* Pre/Post KR training enablement support */
361 void (*kr_training_pre)(struct axgbe_port *);
362 void (*kr_training_post)(struct axgbe_port *);
365 struct axgbe_phy_if {
366 /* For PHY setup/teardown */
367 int (*phy_init)(struct axgbe_port *);
368 void (*phy_exit)(struct axgbe_port *);
370 /* For PHY support when setting device up/down */
371 int (*phy_reset)(struct axgbe_port *);
372 int (*phy_start)(struct axgbe_port *);
373 void (*phy_stop)(struct axgbe_port *);
375 /* For PHY support while device is up */
376 void (*phy_status)(struct axgbe_port *);
377 int (*phy_config_aneg)(struct axgbe_port *);
379 /* For PHY settings validation */
380 int (*phy_valid_speed)(struct axgbe_port *, int);
381 /* For single interrupt support */
382 void (*an_isr)(struct axgbe_port *);
383 /* PHY implementation specific services */
384 struct axgbe_phy_impl_if phy_impl;
387 struct axgbe_i2c_if {
388 /* For initial I2C setup */
389 int (*i2c_init)(struct axgbe_port *);
391 /* For I2C support when setting device up/down */
392 int (*i2c_start)(struct axgbe_port *);
393 void (*i2c_stop)(struct axgbe_port *);
395 /* For performing I2C operations */
396 int (*i2c_xfer)(struct axgbe_port *, struct axgbe_i2c_op *);
399 /* This structure contains flags that indicate what hardware features
400 * or configurations are present in the device.
402 struct axgbe_hw_features {
404 unsigned int version;
406 /* HW Feature Register0 */
407 unsigned int gmii; /* 1000 Mbps support */
408 unsigned int vlhash; /* VLAN Hash Filter */
409 unsigned int sma; /* SMA(MDIO) Interface */
410 unsigned int rwk; /* PMT remote wake-up packet */
411 unsigned int mgk; /* PMT magic packet */
412 unsigned int mmc; /* RMON module */
413 unsigned int aoe; /* ARP Offload */
414 unsigned int ts; /* IEEE 1588-2008 Advanced Timestamp */
415 unsigned int eee; /* Energy Efficient Ethernet */
416 unsigned int tx_coe; /* Tx Checksum Offload */
417 unsigned int rx_coe; /* Rx Checksum Offload */
418 unsigned int addn_mac; /* Additional MAC Addresses */
419 unsigned int ts_src; /* Timestamp Source */
420 unsigned int sa_vlan_ins; /* Source Address or VLAN Insertion */
422 /* HW Feature Register1 */
423 unsigned int rx_fifo_size; /* MTL Receive FIFO Size */
424 unsigned int tx_fifo_size; /* MTL Transmit FIFO Size */
425 unsigned int adv_ts_hi; /* Advance Timestamping High Word */
426 unsigned int dma_width; /* DMA width */
427 unsigned int dcb; /* DCB Feature */
428 unsigned int sph; /* Split Header Feature */
429 unsigned int tso; /* TCP Segmentation Offload */
430 unsigned int dma_debug; /* DMA Debug Registers */
431 unsigned int rss; /* Receive Side Scaling */
432 unsigned int tc_cnt; /* Number of Traffic Classes */
433 unsigned int hash_table_size; /* Hash Table Size */
434 unsigned int l3l4_filter_num; /* Number of L3-L4 Filters */
436 /* HW Feature Register2 */
437 unsigned int rx_q_cnt; /* Number of MTL Receive Queues */
438 unsigned int tx_q_cnt; /* Number of MTL Transmit Queues */
439 unsigned int rx_ch_cnt; /* Number of DMA Receive Channels */
440 unsigned int tx_ch_cnt; /* Number of DMA Transmit Channels */
441 unsigned int pps_out_num; /* Number of PPS outputs */
442 unsigned int aux_snap_num; /* Number of Aux snapshot inputs */
444 /* HW Feature Register3 */
445 unsigned int tx_q_vlan_tag_ins; /* Queue/Channel based VLAN tag */
446 /* insertion on Tx Enable */
447 unsigned int no_of_vlan_extn; /* Number of Extended VLAN Tag */
448 /* Filters Enabled */
451 struct axgbe_version_data {
452 void (*init_function_ptrs_phy_impl)(struct axgbe_phy_if *);
453 enum axgbe_xpcs_access xpcs_access;
454 unsigned int mmc_64bit;
455 unsigned int tx_max_fifo_size;
456 unsigned int rx_max_fifo_size;
457 unsigned int tx_tstamp_workaround;
458 unsigned int ecc_support;
459 unsigned int i2c_support;
460 unsigned int an_cdr_workaround;
463 struct axgbe_mmc_stats {
465 uint64_t txoctetcount_gb;
466 uint64_t txframecount_gb;
467 uint64_t txbroadcastframes_g;
468 uint64_t txmulticastframes_g;
469 uint64_t tx64octets_gb;
470 uint64_t tx65to127octets_gb;
471 uint64_t tx128to255octets_gb;
472 uint64_t tx256to511octets_gb;
473 uint64_t tx512to1023octets_gb;
474 uint64_t tx1024tomaxoctets_gb;
475 uint64_t txunicastframes_gb;
476 uint64_t txmulticastframes_gb;
477 uint64_t txbroadcastframes_gb;
478 uint64_t txunderflowerror;
479 uint64_t txoctetcount_g;
480 uint64_t txframecount_g;
481 uint64_t txpauseframes;
482 uint64_t txvlanframes_g;
485 uint64_t rxframecount_gb;
486 uint64_t rxoctetcount_gb;
487 uint64_t rxoctetcount_g;
488 uint64_t rxbroadcastframes_g;
489 uint64_t rxmulticastframes_g;
491 uint64_t rxrunterror;
492 uint64_t rxjabbererror;
493 uint64_t rxundersize_g;
494 uint64_t rxoversize_g;
495 uint64_t rx64octets_gb;
496 uint64_t rx65to127octets_gb;
497 uint64_t rx128to255octets_gb;
498 uint64_t rx256to511octets_gb;
499 uint64_t rx512to1023octets_gb;
500 uint64_t rx1024tomaxoctets_gb;
501 uint64_t rxunicastframes_g;
502 uint64_t rxlengtherror;
503 uint64_t rxoutofrangetype;
504 uint64_t rxpauseframes;
505 uint64_t rxfifooverflow;
506 uint64_t rxvlanframes_gb;
507 uint64_t rxwatchdogerror;
510 /* Flow control parameters */
511 struct xgbe_fc_info {
512 uint32_t high_water[AXGBE_PRIORITY_QUEUES];
513 uint32_t low_water[AXGBE_PRIORITY_QUEUES];
514 uint16_t pause_time[AXGBE_PRIORITY_QUEUES];
516 enum rte_eth_fc_mode mode;
521 * Structure to store private data for each port.
524 /* Ethdev where port belongs*/
525 struct rte_eth_dev *eth_dev;
527 const struct rte_pci_device *pci_dev;
528 /* Version related data */
529 struct axgbe_version_data *vdata;
531 /* AXGMAC/XPCS related mmio registers */
532 void *xgmac_regs; /* AXGMAC CSRs */
533 void *xpcs_regs; /* XPCS MMD registers */
534 void *xprop_regs; /* AXGBE property registers */
535 void *xi2c_regs; /* AXGBE I2C CSRs */
537 bool cdr_track_early;
538 /* XPCS indirect addressing lock */
539 unsigned int xpcs_window_def_reg;
540 unsigned int xpcs_window_sel_reg;
541 unsigned int xpcs_window;
542 unsigned int xpcs_window_size;
543 unsigned int xpcs_window_mask;
545 /* Flags representing axgbe_state */
548 struct axgbe_hw_if hw_if;
549 struct axgbe_phy_if phy_if;
550 struct axgbe_i2c_if i2c_if;
552 /* AXI DMA settings */
553 unsigned int coherent;
554 unsigned int axdomain;
555 unsigned int arcache;
556 unsigned int awcache;
558 unsigned int tx_max_channel_count;
559 unsigned int rx_max_channel_count;
560 unsigned int channel_count;
561 unsigned int tx_ring_count;
562 unsigned int tx_desc_count;
563 unsigned int rx_ring_count;
564 unsigned int rx_desc_count;
566 unsigned int tx_max_q_count;
567 unsigned int rx_max_q_count;
568 unsigned int tx_q_count;
569 unsigned int rx_q_count;
571 /* Tx/Rx common settings */
575 unsigned int tx_sf_mode;
576 unsigned int tx_threshold;
578 unsigned int tx_osp_mode;
579 unsigned int tx_max_fifo_size;
582 unsigned int rx_sf_mode;
583 unsigned int rx_threshold;
585 unsigned int rx_max_fifo_size;
586 unsigned int rx_buf_size;
589 unsigned long sysclk_rate;
590 unsigned long ptpclk_rate;
592 /* Keeps track of power mode */
593 unsigned int power_down;
595 /* Current PHY settings */
599 pthread_mutex_t xpcs_mutex;
600 pthread_mutex_t i2c_mutex;
601 pthread_mutex_t an_mutex;
602 pthread_mutex_t phy_mutex;
604 /* Flow control settings */
605 unsigned int pause_autoneg;
606 unsigned int tx_pause;
607 unsigned int rx_pause;
608 unsigned int rx_rfa[AXGBE_MAX_QUEUES];
609 unsigned int rx_rfd[AXGBE_MAX_QUEUES];
611 unsigned int pfc_map[AXGBE_MAX_QUEUES];
613 /* Receive Side Scaling settings */
614 u8 rss_key[AXGBE_RSS_HASH_KEY_SIZE];
615 uint32_t rss_table[AXGBE_RSS_MAX_TABLE_SIZE];
616 uint32_t rss_options;
620 /* Hardware features of the device */
621 struct axgbe_hw_features hw_feat;
623 struct rte_ether_addr mac_addr;
625 /* Software Tx/Rx structure pointers*/
629 /* MDIO/PHY related settings */
630 unsigned int phy_started;
632 struct axgbe_phy phy;
634 unsigned long link_check;
635 volatile int mdio_completion;
637 unsigned int kr_redrv;
639 /* Auto-negotiation atate machine support */
641 unsigned int an_status;
642 enum axgbe_an an_result;
643 enum axgbe_an an_state;
644 enum axgbe_rx kr_state;
645 enum axgbe_rx kx_state;
646 unsigned int an_supported;
647 unsigned int parallel_detect;
648 unsigned int fec_ability;
649 unsigned long an_start;
650 enum axgbe_an_mode an_mode;
653 struct axgbe_i2c i2c;
654 volatile int i2c_complete;
656 /* CRC stripping by H/w for Rx packet*/
657 int crc_strip_enable;
658 /* csum enable to hardware */
659 uint32_t rx_csum_enable;
661 struct axgbe_mmc_stats mmc_stats;
662 struct xgbe_fc_info fc;
665 unsigned int hash_table_shift;
666 unsigned int hash_table_count;
667 unsigned int uc_hash_mac_addr;
668 unsigned int uc_hash_table[AXGBE_MAC_HASH_TABLE_SIZE];
670 /* Filtering support */
671 unsigned long active_vlans[VLAN_TABLE_SIZE];
673 /* For IEEE1588 PTP */
674 struct rte_timecounter systime_tc;
675 struct rte_timecounter tx_tstamp;
676 unsigned int tstamp_addend;
680 void axgbe_init_function_ptrs_dev(struct axgbe_hw_if *hw_if);
681 void axgbe_init_function_ptrs_phy(struct axgbe_phy_if *phy_if);
682 void axgbe_init_function_ptrs_phy_v2(struct axgbe_phy_if *phy_if);
683 void axgbe_init_function_ptrs_i2c(struct axgbe_i2c_if *i2c_if);
684 void axgbe_set_mac_addn_addr(struct axgbe_port *pdata, u8 *addr,
686 void axgbe_set_mac_hash_table(struct axgbe_port *pdata, u8 *addr, bool add);
687 int axgbe_write_rss_lookup_table(struct axgbe_port *pdata);
688 int axgbe_write_rss_hash_key(struct axgbe_port *pdata);
690 #endif /* RTE_ETH_AXGBE_H_ */