1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved.
3 * Copyright(c) 2018 Synopsys, Inc. All rights reserved.
6 #ifndef RTE_ETH_AXGBE_H_
7 #define RTE_ETH_AXGBE_H_
9 #include <rte_mempool.h>
10 #include <rte_lcore.h>
11 #include "axgbe_common.h"
16 #define AXGBE_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1))
17 #define AXGBE_RX_MAX_BUF_SIZE (0x3fff & ~(64 - 1))
18 #define AXGBE_RX_MIN_BUF_SIZE (RTE_ETHER_MAX_LEN + VLAN_HLEN)
19 #define AXGBE_MAX_MAC_ADDRS 1
21 #define AXGBE_RX_BUF_ALIGN 64
23 #define AXGBE_MAX_DMA_CHANNELS 16
24 #define AXGBE_MAX_QUEUES 16
25 #define AXGBE_PRIORITY_QUEUES 8
26 #define AXGBE_DMA_STOP_TIMEOUT 1
28 /* DMA cache settings - Outer sharable, write-back, write-allocate */
29 #define AXGBE_DMA_OS_AXDOMAIN 0x2
30 #define AXGBE_DMA_OS_ARCACHE 0xb
31 #define AXGBE_DMA_OS_AWCACHE 0xf
33 /* DMA cache settings - System, no caches used */
34 #define AXGBE_DMA_SYS_AXDOMAIN 0x3
35 #define AXGBE_DMA_SYS_ARCACHE 0x0
36 #define AXGBE_DMA_SYS_AWCACHE 0x0
38 /* DMA channel interrupt modes */
39 #define AXGBE_IRQ_MODE_EDGE 0
40 #define AXGBE_IRQ_MODE_LEVEL 1
42 #define AXGBE_DMA_INTERRUPT_MASK 0x31c7
44 #define AXGMAC_MIN_PACKET 60
45 #define AXGMAC_STD_PACKET_MTU 1500
46 #define AXGMAC_MAX_STD_PACKET 1518
47 #define AXGMAC_JUMBO_PACKET_MTU 9000
48 #define AXGMAC_MAX_JUMBO_PACKET 9018
49 /* Inter-frame gap + preamble */
50 #define AXGMAC_ETH_PREAMBLE (12 + 8)
52 #define AXGMAC_PFC_DATA_LEN 46
53 #define AXGMAC_PFC_DELAYS 14000
56 #define AXGBE_AXGMAC_BAR 0
57 #define AXGBE_XPCS_BAR 1
58 #define AXGBE_MAC_PROP_OFFSET 0x1d000
59 #define AXGBE_I2C_CTRL_OFFSET 0x1e000
61 /* PCI clock frequencies */
62 #define AXGBE_V2_DMA_CLOCK_FREQ 500000000
63 #define AXGBE_V2_PTP_CLOCK_FREQ 125000000
65 #define AXGMAC_FIFO_MIN_ALLOC 2048
66 #define AXGMAC_FIFO_UNIT 256
67 #define AXGMAC_FIFO_ALIGN(_x) \
68 (((_x) + AXGMAC_FIFO_UNIT - 1) & ~(XGMAC_FIFO_UNIT - 1))
69 #define AXGMAC_FIFO_FC_OFF 2048
70 #define AXGMAC_FIFO_FC_MIN 4096
72 #define AXGBE_TC_MIN_QUANTUM 10
74 /* Flow control queue count */
75 #define AXGMAC_MAX_FLOW_CONTROL_QUEUES 8
77 /* Flow control threshold units */
78 #define AXGMAC_FLOW_CONTROL_UNIT 512
79 #define AXGMAC_FLOW_CONTROL_ALIGN(_x) \
80 (((_x) + AXGMAC_FLOW_CONTROL_UNIT - 1) & \
81 ~(AXGMAC_FLOW_CONTROL_UNIT - 1))
82 #define AXGMAC_FLOW_CONTROL_VALUE(_x) \
83 (((_x) < 1024) ? 0 : ((_x) / AXGMAC_FLOW_CONTROL_UNIT) - 2)
84 #define AXGMAC_FLOW_CONTROL_MAX 33280
86 /* Maximum MAC address hash table size (256 bits = 8 bytes) */
87 #define AXGBE_MAC_HASH_TABLE_SIZE 8
89 /* Receive Side Scaling */
90 #define AXGBE_RSS_OFFLOAD ( \
92 ETH_RSS_NONFRAG_IPV4_TCP | \
93 ETH_RSS_NONFRAG_IPV4_UDP | \
95 ETH_RSS_NONFRAG_IPV6_TCP | \
96 ETH_RSS_NONFRAG_IPV6_UDP)
98 #define AXGBE_RSS_HASH_KEY_SIZE 40
99 #define AXGBE_RSS_MAX_TABLE_SIZE 256
100 #define AXGBE_RSS_LOOKUP_TABLE_TYPE 0
101 #define AXGBE_RSS_HASH_KEY_TYPE 1
103 /* Auto-negotiation */
104 #define AXGBE_AN_MS_TIMEOUT 500
105 #define AXGBE_LINK_TIMEOUT 5
107 #define AXGBE_SGMII_AN_LINK_STATUS BIT(1)
108 #define AXGBE_SGMII_AN_LINK_SPEED (BIT(2) | BIT(3))
109 #define AXGBE_SGMII_AN_LINK_SPEED_100 0x04
110 #define AXGBE_SGMII_AN_LINK_SPEED_1000 0x08
111 #define AXGBE_SGMII_AN_LINK_DUPLEX BIT(4)
113 /* ECC correctable error notification window (seconds) */
114 #define AXGBE_ECC_LIMIT 60
116 /* MDIO port types */
117 #define AXGMAC_MAX_C22_PORT 3
119 /* Helper macro for descriptor handling
120 * Always use AXGBE_GET_DESC_DATA to access the descriptor data
121 * since the index is free-running and needs to be and-ed
122 * with the descriptor count value of the ring to index to
123 * the proper descriptor data.
125 #define AXGBE_GET_DESC_DATA(_ring, _idx) \
127 ((_idx) & ((_ring)->rdesc_count - 1)))
139 AXGMAC_INT_DMA_CH_SR_TI,
140 AXGMAC_INT_DMA_CH_SR_TPS,
141 AXGMAC_INT_DMA_CH_SR_TBU,
142 AXGMAC_INT_DMA_CH_SR_RI,
143 AXGMAC_INT_DMA_CH_SR_RBU,
144 AXGMAC_INT_DMA_CH_SR_RPS,
145 AXGMAC_INT_DMA_CH_SR_TI_RI,
146 AXGMAC_INT_DMA_CH_SR_FBE,
150 enum axgbe_int_state {
151 AXGMAC_INT_STATE_SAVE,
152 AXGMAC_INT_STATE_RESTORE,
162 AXGBE_SPEED_1000 = 0,
168 enum axgbe_xpcs_access {
169 AXGBE_XPCS_ACCESS_V1 = 0,
170 AXGBE_XPCS_ACCESS_V2,
174 AXGBE_AN_MODE_CL73 = 0,
175 AXGBE_AN_MODE_CL73_REDRV,
177 AXGBE_AN_MODE_CL37_SGMII,
183 AXGBE_AN_PAGE_RECEIVED,
184 AXGBE_AN_INCOMPAT_LINK,
198 AXGBE_MODE_KX_1000 = 0,
202 AXGBE_MODE_SGMII_100,
203 AXGBE_MODE_SGMII_1000,
208 enum axgbe_speedset {
209 AXGBE_SPEEDSET_1000_10000 = 0,
210 AXGBE_SPEEDSET_2500_10000,
213 enum axgbe_mdio_mode {
214 AXGBE_MDIO_MODE_NONE = 0,
215 AXGBE_MDIO_MODE_CL22,
216 AXGBE_MDIO_MODE_CL45,
221 uint32_t advertising;
222 uint32_t lp_advertising;
238 AXGBE_I2C_CMD_READ = 0,
242 struct axgbe_i2c_op {
243 enum axgbe_i2c_cmd cmd;
251 struct axgbe_i2c_op_state {
252 struct axgbe_i2c_op *op;
255 unsigned char *tx_buf;
258 unsigned char *rx_buf;
260 unsigned int tx_abort_source;
266 unsigned int started;
267 unsigned int max_speed_mode;
268 unsigned int rx_fifo_size;
269 unsigned int tx_fifo_size;
271 struct axgbe_i2c_op_state op_state;
275 void (*config_flow_control)(struct axgbe_port *);
276 int (*config_rx_mode)(struct axgbe_port *);
278 int (*init)(struct axgbe_port *);
280 int (*read_mmd_regs)(struct axgbe_port *, int, int);
281 void (*write_mmd_regs)(struct axgbe_port *, int, int, int);
282 int (*set_speed)(struct axgbe_port *, int);
284 int (*set_ext_mii_mode)(struct axgbe_port *, unsigned int,
285 enum axgbe_mdio_mode);
286 int (*read_ext_mii_regs)(struct axgbe_port *, int, int);
287 int (*write_ext_mii_regs)(struct axgbe_port *, int, int, uint16_t);
290 int (*config_tx_flow_control)(struct axgbe_port *);
291 int (*config_rx_flow_control)(struct axgbe_port *);
293 int (*exit)(struct axgbe_port *);
296 /* This structure represents implementation specific routines for an
297 * implementation of a PHY. All routines are required unless noted below.
299 * kr_training_pre, kr_training_post
301 struct axgbe_phy_impl_if {
302 /* Perform Setup/teardown actions */
303 int (*init)(struct axgbe_port *);
304 void (*exit)(struct axgbe_port *);
306 /* Perform start/stop specific actions */
307 int (*reset)(struct axgbe_port *);
308 int (*start)(struct axgbe_port *);
309 void (*stop)(struct axgbe_port *);
311 /* Return the link status */
312 int (*link_status)(struct axgbe_port *, int *);
314 /* Indicate if a particular speed is valid */
315 int (*valid_speed)(struct axgbe_port *, int);
317 /* Check if the specified mode can/should be used */
318 bool (*use_mode)(struct axgbe_port *, enum axgbe_mode);
319 /* Switch the PHY into various modes */
320 void (*set_mode)(struct axgbe_port *, enum axgbe_mode);
321 /* Retrieve mode needed for a specific speed */
322 enum axgbe_mode (*get_mode)(struct axgbe_port *, int);
323 /* Retrieve new/next mode when trying to auto-negotiate */
324 enum axgbe_mode (*switch_mode)(struct axgbe_port *);
325 /* Retrieve current mode */
326 enum axgbe_mode (*cur_mode)(struct axgbe_port *);
328 /* Retrieve current auto-negotiation mode */
329 enum axgbe_an_mode (*an_mode)(struct axgbe_port *);
331 /* Configure auto-negotiation settings */
332 int (*an_config)(struct axgbe_port *);
334 /* Set/override auto-negotiation advertisement settings */
335 unsigned int (*an_advertising)(struct axgbe_port *port);
337 /* Process results of auto-negotiation */
338 enum axgbe_mode (*an_outcome)(struct axgbe_port *);
340 /* Pre/Post auto-negotiation support */
341 void (*an_pre)(struct axgbe_port *port);
342 void (*an_post)(struct axgbe_port *port);
344 /* Pre/Post KR training enablement support */
345 void (*kr_training_pre)(struct axgbe_port *);
346 void (*kr_training_post)(struct axgbe_port *);
349 struct axgbe_phy_if {
350 /* For PHY setup/teardown */
351 int (*phy_init)(struct axgbe_port *);
352 void (*phy_exit)(struct axgbe_port *);
354 /* For PHY support when setting device up/down */
355 int (*phy_reset)(struct axgbe_port *);
356 int (*phy_start)(struct axgbe_port *);
357 void (*phy_stop)(struct axgbe_port *);
359 /* For PHY support while device is up */
360 void (*phy_status)(struct axgbe_port *);
361 int (*phy_config_aneg)(struct axgbe_port *);
363 /* For PHY settings validation */
364 int (*phy_valid_speed)(struct axgbe_port *, int);
365 /* For single interrupt support */
366 void (*an_isr)(struct axgbe_port *);
367 /* PHY implementation specific services */
368 struct axgbe_phy_impl_if phy_impl;
371 struct axgbe_i2c_if {
372 /* For initial I2C setup */
373 int (*i2c_init)(struct axgbe_port *);
375 /* For I2C support when setting device up/down */
376 int (*i2c_start)(struct axgbe_port *);
377 void (*i2c_stop)(struct axgbe_port *);
379 /* For performing I2C operations */
380 int (*i2c_xfer)(struct axgbe_port *, struct axgbe_i2c_op *);
383 /* This structure contains flags that indicate what hardware features
384 * or configurations are present in the device.
386 struct axgbe_hw_features {
388 unsigned int version;
390 /* HW Feature Register0 */
391 unsigned int gmii; /* 1000 Mbps support */
392 unsigned int vlhash; /* VLAN Hash Filter */
393 unsigned int sma; /* SMA(MDIO) Interface */
394 unsigned int rwk; /* PMT remote wake-up packet */
395 unsigned int mgk; /* PMT magic packet */
396 unsigned int mmc; /* RMON module */
397 unsigned int aoe; /* ARP Offload */
398 unsigned int ts; /* IEEE 1588-2008 Advanced Timestamp */
399 unsigned int eee; /* Energy Efficient Ethernet */
400 unsigned int tx_coe; /* Tx Checksum Offload */
401 unsigned int rx_coe; /* Rx Checksum Offload */
402 unsigned int addn_mac; /* Additional MAC Addresses */
403 unsigned int ts_src; /* Timestamp Source */
404 unsigned int sa_vlan_ins; /* Source Address or VLAN Insertion */
406 /* HW Feature Register1 */
407 unsigned int rx_fifo_size; /* MTL Receive FIFO Size */
408 unsigned int tx_fifo_size; /* MTL Transmit FIFO Size */
409 unsigned int adv_ts_hi; /* Advance Timestamping High Word */
410 unsigned int dma_width; /* DMA width */
411 unsigned int dcb; /* DCB Feature */
412 unsigned int sph; /* Split Header Feature */
413 unsigned int tso; /* TCP Segmentation Offload */
414 unsigned int dma_debug; /* DMA Debug Registers */
415 unsigned int rss; /* Receive Side Scaling */
416 unsigned int tc_cnt; /* Number of Traffic Classes */
417 unsigned int hash_table_size; /* Hash Table Size */
418 unsigned int l3l4_filter_num; /* Number of L3-L4 Filters */
420 /* HW Feature Register2 */
421 unsigned int rx_q_cnt; /* Number of MTL Receive Queues */
422 unsigned int tx_q_cnt; /* Number of MTL Transmit Queues */
423 unsigned int rx_ch_cnt; /* Number of DMA Receive Channels */
424 unsigned int tx_ch_cnt; /* Number of DMA Transmit Channels */
425 unsigned int pps_out_num; /* Number of PPS outputs */
426 unsigned int aux_snap_num; /* Number of Aux snapshot inputs */
429 struct axgbe_version_data {
430 void (*init_function_ptrs_phy_impl)(struct axgbe_phy_if *);
431 enum axgbe_xpcs_access xpcs_access;
432 unsigned int mmc_64bit;
433 unsigned int tx_max_fifo_size;
434 unsigned int rx_max_fifo_size;
435 unsigned int tx_tstamp_workaround;
436 unsigned int ecc_support;
437 unsigned int i2c_support;
438 unsigned int an_cdr_workaround;
441 struct axgbe_mmc_stats {
443 uint64_t txoctetcount_gb;
444 uint64_t txframecount_gb;
445 uint64_t txbroadcastframes_g;
446 uint64_t txmulticastframes_g;
447 uint64_t tx64octets_gb;
448 uint64_t tx65to127octets_gb;
449 uint64_t tx128to255octets_gb;
450 uint64_t tx256to511octets_gb;
451 uint64_t tx512to1023octets_gb;
452 uint64_t tx1024tomaxoctets_gb;
453 uint64_t txunicastframes_gb;
454 uint64_t txmulticastframes_gb;
455 uint64_t txbroadcastframes_gb;
456 uint64_t txunderflowerror;
457 uint64_t txoctetcount_g;
458 uint64_t txframecount_g;
459 uint64_t txpauseframes;
460 uint64_t txvlanframes_g;
463 uint64_t rxframecount_gb;
464 uint64_t rxoctetcount_gb;
465 uint64_t rxoctetcount_g;
466 uint64_t rxbroadcastframes_g;
467 uint64_t rxmulticastframes_g;
469 uint64_t rxrunterror;
470 uint64_t rxjabbererror;
471 uint64_t rxundersize_g;
472 uint64_t rxoversize_g;
473 uint64_t rx64octets_gb;
474 uint64_t rx65to127octets_gb;
475 uint64_t rx128to255octets_gb;
476 uint64_t rx256to511octets_gb;
477 uint64_t rx512to1023octets_gb;
478 uint64_t rx1024tomaxoctets_gb;
479 uint64_t rxunicastframes_g;
480 uint64_t rxlengtherror;
481 uint64_t rxoutofrangetype;
482 uint64_t rxpauseframes;
483 uint64_t rxfifooverflow;
484 uint64_t rxvlanframes_gb;
485 uint64_t rxwatchdogerror;
489 * Structure to store private data for each port.
492 /* Ethdev where port belongs*/
493 struct rte_eth_dev *eth_dev;
495 const struct rte_pci_device *pci_dev;
496 /* Version related data */
497 struct axgbe_version_data *vdata;
499 /* AXGMAC/XPCS related mmio registers */
500 void *xgmac_regs; /* AXGMAC CSRs */
501 void *xpcs_regs; /* XPCS MMD registers */
502 void *xprop_regs; /* AXGBE property registers */
503 void *xi2c_regs; /* AXGBE I2C CSRs */
505 bool cdr_track_early;
506 /* XPCS indirect addressing lock */
507 unsigned int xpcs_window_def_reg;
508 unsigned int xpcs_window_sel_reg;
509 unsigned int xpcs_window;
510 unsigned int xpcs_window_size;
511 unsigned int xpcs_window_mask;
513 /* Flags representing axgbe_state */
514 unsigned long dev_state;
516 struct axgbe_hw_if hw_if;
517 struct axgbe_phy_if phy_if;
518 struct axgbe_i2c_if i2c_if;
520 /* AXI DMA settings */
521 unsigned int coherent;
522 unsigned int axdomain;
523 unsigned int arcache;
524 unsigned int awcache;
526 unsigned int tx_max_channel_count;
527 unsigned int rx_max_channel_count;
528 unsigned int channel_count;
529 unsigned int tx_ring_count;
530 unsigned int tx_desc_count;
531 unsigned int rx_ring_count;
532 unsigned int rx_desc_count;
534 unsigned int tx_max_q_count;
535 unsigned int rx_max_q_count;
536 unsigned int tx_q_count;
537 unsigned int rx_q_count;
539 /* Tx/Rx common settings */
543 unsigned int tx_sf_mode;
544 unsigned int tx_threshold;
546 unsigned int tx_osp_mode;
547 unsigned int tx_max_fifo_size;
550 unsigned int rx_sf_mode;
551 unsigned int rx_threshold;
553 unsigned int rx_max_fifo_size;
554 unsigned int rx_buf_size;
557 unsigned long sysclk_rate;
558 unsigned long ptpclk_rate;
560 /* Keeps track of power mode */
561 unsigned int power_down;
563 /* Current PHY settings */
567 pthread_mutex_t xpcs_mutex;
568 pthread_mutex_t i2c_mutex;
569 pthread_mutex_t an_mutex;
570 pthread_mutex_t phy_mutex;
572 /* Flow control settings */
573 unsigned int pause_autoneg;
574 unsigned int tx_pause;
575 unsigned int rx_pause;
576 unsigned int rx_rfa[AXGBE_MAX_QUEUES];
577 unsigned int rx_rfd[AXGBE_MAX_QUEUES];
580 /* Receive Side Scaling settings */
581 u8 rss_key[AXGBE_RSS_HASH_KEY_SIZE];
582 uint32_t rss_table[AXGBE_RSS_MAX_TABLE_SIZE];
583 uint32_t rss_options;
586 /* Hardware features of the device */
587 struct axgbe_hw_features hw_feat;
589 struct rte_ether_addr mac_addr;
591 /* Software Tx/Rx structure pointers*/
595 /* MDIO/PHY related settings */
596 unsigned int phy_started;
598 struct axgbe_phy phy;
600 unsigned long link_check;
601 volatile int mdio_completion;
603 unsigned int kr_redrv;
605 /* Auto-negotiation atate machine support */
607 unsigned int an_status;
608 enum axgbe_an an_result;
609 enum axgbe_an an_state;
610 enum axgbe_rx kr_state;
611 enum axgbe_rx kx_state;
612 unsigned int an_supported;
613 unsigned int parallel_detect;
614 unsigned int fec_ability;
615 unsigned long an_start;
616 enum axgbe_an_mode an_mode;
619 struct axgbe_i2c i2c;
620 volatile int i2c_complete;
622 /* CRC stripping by H/w for Rx packet*/
623 int crc_strip_enable;
624 /* csum enable to hardware */
625 uint32_t rx_csum_enable;
627 struct axgbe_mmc_stats mmc_stats;
630 void axgbe_init_function_ptrs_dev(struct axgbe_hw_if *hw_if);
631 void axgbe_init_function_ptrs_phy(struct axgbe_phy_if *phy_if);
632 void axgbe_init_function_ptrs_phy_v2(struct axgbe_phy_if *phy_if);
633 void axgbe_init_function_ptrs_i2c(struct axgbe_i2c_if *i2c_if);
635 #endif /* RTE_ETH_AXGBE_H_ */