1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved.
3 * Copyright(c) 2018 Synopsys, Inc. All rights reserved.
6 #ifndef RTE_ETH_AXGBE_H_
7 #define RTE_ETH_AXGBE_H_
9 #include <rte_mempool.h>
10 #include <rte_lcore.h>
11 #include "axgbe_common.h"
16 #define AXGBE_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1))
17 #define AXGBE_RX_MAX_BUF_SIZE (0x3fff & ~(64 - 1))
18 #define AXGBE_RX_MIN_BUF_SIZE (RTE_ETHER_MAX_LEN + VLAN_HLEN)
19 #define AXGBE_MAX_MAC_ADDRS 32
20 #define AXGBE_MAX_HASH_MAC_ADDRS 256
22 #define AXGBE_RX_BUF_ALIGN 64
24 #define AXGBE_MAX_DMA_CHANNELS 16
25 #define AXGBE_MAX_QUEUES 16
26 #define AXGBE_PRIORITY_QUEUES 8
27 #define AXGBE_DMA_STOP_TIMEOUT 1
29 /* DMA cache settings - Outer sharable, write-back, write-allocate */
30 #define AXGBE_DMA_OS_AXDOMAIN 0x2
31 #define AXGBE_DMA_OS_ARCACHE 0xb
32 #define AXGBE_DMA_OS_AWCACHE 0xf
34 /* DMA cache settings - System, no caches used */
35 #define AXGBE_DMA_SYS_AXDOMAIN 0x3
36 #define AXGBE_DMA_SYS_ARCACHE 0x0
37 #define AXGBE_DMA_SYS_AWCACHE 0x0
39 /* DMA channel interrupt modes */
40 #define AXGBE_IRQ_MODE_EDGE 0
41 #define AXGBE_IRQ_MODE_LEVEL 1
43 #define AXGBE_DMA_INTERRUPT_MASK 0x31c7
45 #define AXGMAC_MIN_PACKET 60
46 #define AXGMAC_STD_PACKET_MTU 1500
47 #define AXGMAC_MAX_STD_PACKET 1518
48 #define AXGMAC_JUMBO_PACKET_MTU 9000
49 #define AXGMAC_MAX_JUMBO_PACKET 9018
50 /* Inter-frame gap + preamble */
51 #define AXGMAC_ETH_PREAMBLE (12 + 8)
53 #define AXGMAC_PFC_DATA_LEN 46
54 #define AXGMAC_PFC_DELAYS 14000
57 #define AXGBE_AXGMAC_BAR 0
58 #define AXGBE_XPCS_BAR 1
59 #define AXGBE_MAC_PROP_OFFSET 0x1d000
60 #define AXGBE_I2C_CTRL_OFFSET 0x1e000
62 /* PCI clock frequencies */
63 #define AXGBE_V2_DMA_CLOCK_FREQ 500000000
64 #define AXGBE_V2_PTP_CLOCK_FREQ 125000000
66 #define AXGMAC_FIFO_MIN_ALLOC 2048
67 #define AXGMAC_FIFO_UNIT 256
68 #define AXGMAC_FIFO_ALIGN(_x) \
69 (((_x) + AXGMAC_FIFO_UNIT - 1) & ~(XGMAC_FIFO_UNIT - 1))
70 #define AXGMAC_FIFO_FC_OFF 2048
71 #define AXGMAC_FIFO_FC_MIN 4096
73 #define AXGBE_TC_MIN_QUANTUM 10
75 /* Flow control queue count */
76 #define AXGMAC_MAX_FLOW_CONTROL_QUEUES 8
78 /* Flow control threshold units */
79 #define AXGMAC_FLOW_CONTROL_UNIT 512
80 #define AXGMAC_FLOW_CONTROL_ALIGN(_x) \
81 (((_x) + AXGMAC_FLOW_CONTROL_UNIT - 1) & \
82 ~(AXGMAC_FLOW_CONTROL_UNIT - 1))
83 #define AXGMAC_FLOW_CONTROL_VALUE(_x) \
84 (((_x) < 1024) ? 0 : ((_x) / AXGMAC_FLOW_CONTROL_UNIT) - 2)
85 #define AXGMAC_FLOW_CONTROL_MAX 33280
87 /* Maximum MAC address hash table size (256 bits = 8 dword) */
88 #define AXGBE_MAC_HASH_TABLE_SIZE 8
90 /* Receive Side Scaling */
91 #define AXGBE_RSS_OFFLOAD ( \
93 ETH_RSS_NONFRAG_IPV4_TCP | \
94 ETH_RSS_NONFRAG_IPV4_UDP | \
96 ETH_RSS_NONFRAG_IPV6_TCP | \
97 ETH_RSS_NONFRAG_IPV6_UDP)
99 #define AXGBE_RSS_HASH_KEY_SIZE 40
100 #define AXGBE_RSS_MAX_TABLE_SIZE 256
101 #define AXGBE_RSS_LOOKUP_TABLE_TYPE 0
102 #define AXGBE_RSS_HASH_KEY_TYPE 1
104 /* Auto-negotiation */
105 #define AXGBE_AN_MS_TIMEOUT 500
106 #define AXGBE_LINK_TIMEOUT 5
108 #define AXGBE_SGMII_AN_LINK_STATUS BIT(1)
109 #define AXGBE_SGMII_AN_LINK_SPEED (BIT(2) | BIT(3))
110 #define AXGBE_SGMII_AN_LINK_SPEED_100 0x04
111 #define AXGBE_SGMII_AN_LINK_SPEED_1000 0x08
112 #define AXGBE_SGMII_AN_LINK_DUPLEX BIT(4)
114 /* ECC correctable error notification window (seconds) */
115 #define AXGBE_ECC_LIMIT 60
117 /* MDIO port types */
118 #define AXGMAC_MAX_C22_PORT 3
120 /* Helper macro for descriptor handling
121 * Always use AXGBE_GET_DESC_DATA to access the descriptor data
122 * since the index is free-running and needs to be and-ed
123 * with the descriptor count value of the ring to index to
124 * the proper descriptor data.
126 #define AXGBE_GET_DESC_DATA(_ring, _idx) \
128 ((_idx) & ((_ring)->rdesc_count - 1)))
140 AXGMAC_INT_DMA_CH_SR_TI,
141 AXGMAC_INT_DMA_CH_SR_TPS,
142 AXGMAC_INT_DMA_CH_SR_TBU,
143 AXGMAC_INT_DMA_CH_SR_RI,
144 AXGMAC_INT_DMA_CH_SR_RBU,
145 AXGMAC_INT_DMA_CH_SR_RPS,
146 AXGMAC_INT_DMA_CH_SR_TI_RI,
147 AXGMAC_INT_DMA_CH_SR_FBE,
151 enum axgbe_int_state {
152 AXGMAC_INT_STATE_SAVE,
153 AXGMAC_INT_STATE_RESTORE,
163 AXGBE_SPEED_1000 = 0,
169 enum axgbe_xpcs_access {
170 AXGBE_XPCS_ACCESS_V1 = 0,
171 AXGBE_XPCS_ACCESS_V2,
175 AXGBE_AN_MODE_CL73 = 0,
176 AXGBE_AN_MODE_CL73_REDRV,
178 AXGBE_AN_MODE_CL37_SGMII,
184 AXGBE_AN_PAGE_RECEIVED,
185 AXGBE_AN_INCOMPAT_LINK,
199 AXGBE_MODE_KX_1000 = 0,
203 AXGBE_MODE_SGMII_100,
204 AXGBE_MODE_SGMII_1000,
209 enum axgbe_speedset {
210 AXGBE_SPEEDSET_1000_10000 = 0,
211 AXGBE_SPEEDSET_2500_10000,
214 enum axgbe_mdio_mode {
215 AXGBE_MDIO_MODE_NONE = 0,
216 AXGBE_MDIO_MODE_CL22,
217 AXGBE_MDIO_MODE_CL45,
222 uint32_t advertising;
223 uint32_t lp_advertising;
239 AXGBE_I2C_CMD_READ = 0,
243 struct axgbe_i2c_op {
244 enum axgbe_i2c_cmd cmd;
252 struct axgbe_i2c_op_state {
253 struct axgbe_i2c_op *op;
256 unsigned char *tx_buf;
259 unsigned char *rx_buf;
261 unsigned int tx_abort_source;
267 unsigned int started;
268 unsigned int max_speed_mode;
269 unsigned int rx_fifo_size;
270 unsigned int tx_fifo_size;
272 struct axgbe_i2c_op_state op_state;
276 void (*config_flow_control)(struct axgbe_port *);
277 int (*config_rx_mode)(struct axgbe_port *);
279 int (*init)(struct axgbe_port *);
281 int (*read_mmd_regs)(struct axgbe_port *, int, int);
282 void (*write_mmd_regs)(struct axgbe_port *, int, int, int);
283 int (*set_speed)(struct axgbe_port *, int);
285 int (*set_ext_mii_mode)(struct axgbe_port *, unsigned int,
286 enum axgbe_mdio_mode);
287 int (*read_ext_mii_regs)(struct axgbe_port *, int, int);
288 int (*write_ext_mii_regs)(struct axgbe_port *, int, int, uint16_t);
291 int (*config_tx_flow_control)(struct axgbe_port *);
292 int (*config_rx_flow_control)(struct axgbe_port *);
294 int (*exit)(struct axgbe_port *);
297 /* This structure represents implementation specific routines for an
298 * implementation of a PHY. All routines are required unless noted below.
300 * kr_training_pre, kr_training_post
302 struct axgbe_phy_impl_if {
303 /* Perform Setup/teardown actions */
304 int (*init)(struct axgbe_port *);
305 void (*exit)(struct axgbe_port *);
307 /* Perform start/stop specific actions */
308 int (*reset)(struct axgbe_port *);
309 int (*start)(struct axgbe_port *);
310 void (*stop)(struct axgbe_port *);
312 /* Return the link status */
313 int (*link_status)(struct axgbe_port *, int *);
315 /* Indicate if a particular speed is valid */
316 int (*valid_speed)(struct axgbe_port *, int);
318 /* Check if the specified mode can/should be used */
319 bool (*use_mode)(struct axgbe_port *, enum axgbe_mode);
320 /* Switch the PHY into various modes */
321 void (*set_mode)(struct axgbe_port *, enum axgbe_mode);
322 /* Retrieve mode needed for a specific speed */
323 enum axgbe_mode (*get_mode)(struct axgbe_port *, int);
324 /* Retrieve new/next mode when trying to auto-negotiate */
325 enum axgbe_mode (*switch_mode)(struct axgbe_port *);
326 /* Retrieve current mode */
327 enum axgbe_mode (*cur_mode)(struct axgbe_port *);
329 /* Retrieve current auto-negotiation mode */
330 enum axgbe_an_mode (*an_mode)(struct axgbe_port *);
332 /* Configure auto-negotiation settings */
333 int (*an_config)(struct axgbe_port *);
335 /* Set/override auto-negotiation advertisement settings */
336 unsigned int (*an_advertising)(struct axgbe_port *port);
338 /* Process results of auto-negotiation */
339 enum axgbe_mode (*an_outcome)(struct axgbe_port *);
341 /* Pre/Post auto-negotiation support */
342 void (*an_pre)(struct axgbe_port *port);
343 void (*an_post)(struct axgbe_port *port);
345 /* Pre/Post KR training enablement support */
346 void (*kr_training_pre)(struct axgbe_port *);
347 void (*kr_training_post)(struct axgbe_port *);
350 struct axgbe_phy_if {
351 /* For PHY setup/teardown */
352 int (*phy_init)(struct axgbe_port *);
353 void (*phy_exit)(struct axgbe_port *);
355 /* For PHY support when setting device up/down */
356 int (*phy_reset)(struct axgbe_port *);
357 int (*phy_start)(struct axgbe_port *);
358 void (*phy_stop)(struct axgbe_port *);
360 /* For PHY support while device is up */
361 void (*phy_status)(struct axgbe_port *);
362 int (*phy_config_aneg)(struct axgbe_port *);
364 /* For PHY settings validation */
365 int (*phy_valid_speed)(struct axgbe_port *, int);
366 /* For single interrupt support */
367 void (*an_isr)(struct axgbe_port *);
368 /* PHY implementation specific services */
369 struct axgbe_phy_impl_if phy_impl;
372 struct axgbe_i2c_if {
373 /* For initial I2C setup */
374 int (*i2c_init)(struct axgbe_port *);
376 /* For I2C support when setting device up/down */
377 int (*i2c_start)(struct axgbe_port *);
378 void (*i2c_stop)(struct axgbe_port *);
380 /* For performing I2C operations */
381 int (*i2c_xfer)(struct axgbe_port *, struct axgbe_i2c_op *);
384 /* This structure contains flags that indicate what hardware features
385 * or configurations are present in the device.
387 struct axgbe_hw_features {
389 unsigned int version;
391 /* HW Feature Register0 */
392 unsigned int gmii; /* 1000 Mbps support */
393 unsigned int vlhash; /* VLAN Hash Filter */
394 unsigned int sma; /* SMA(MDIO) Interface */
395 unsigned int rwk; /* PMT remote wake-up packet */
396 unsigned int mgk; /* PMT magic packet */
397 unsigned int mmc; /* RMON module */
398 unsigned int aoe; /* ARP Offload */
399 unsigned int ts; /* IEEE 1588-2008 Advanced Timestamp */
400 unsigned int eee; /* Energy Efficient Ethernet */
401 unsigned int tx_coe; /* Tx Checksum Offload */
402 unsigned int rx_coe; /* Rx Checksum Offload */
403 unsigned int addn_mac; /* Additional MAC Addresses */
404 unsigned int ts_src; /* Timestamp Source */
405 unsigned int sa_vlan_ins; /* Source Address or VLAN Insertion */
407 /* HW Feature Register1 */
408 unsigned int rx_fifo_size; /* MTL Receive FIFO Size */
409 unsigned int tx_fifo_size; /* MTL Transmit FIFO Size */
410 unsigned int adv_ts_hi; /* Advance Timestamping High Word */
411 unsigned int dma_width; /* DMA width */
412 unsigned int dcb; /* DCB Feature */
413 unsigned int sph; /* Split Header Feature */
414 unsigned int tso; /* TCP Segmentation Offload */
415 unsigned int dma_debug; /* DMA Debug Registers */
416 unsigned int rss; /* Receive Side Scaling */
417 unsigned int tc_cnt; /* Number of Traffic Classes */
418 unsigned int hash_table_size; /* Hash Table Size */
419 unsigned int l3l4_filter_num; /* Number of L3-L4 Filters */
421 /* HW Feature Register2 */
422 unsigned int rx_q_cnt; /* Number of MTL Receive Queues */
423 unsigned int tx_q_cnt; /* Number of MTL Transmit Queues */
424 unsigned int rx_ch_cnt; /* Number of DMA Receive Channels */
425 unsigned int tx_ch_cnt; /* Number of DMA Transmit Channels */
426 unsigned int pps_out_num; /* Number of PPS outputs */
427 unsigned int aux_snap_num; /* Number of Aux snapshot inputs */
430 struct axgbe_version_data {
431 void (*init_function_ptrs_phy_impl)(struct axgbe_phy_if *);
432 enum axgbe_xpcs_access xpcs_access;
433 unsigned int mmc_64bit;
434 unsigned int tx_max_fifo_size;
435 unsigned int rx_max_fifo_size;
436 unsigned int tx_tstamp_workaround;
437 unsigned int ecc_support;
438 unsigned int i2c_support;
439 unsigned int an_cdr_workaround;
442 struct axgbe_mmc_stats {
444 uint64_t txoctetcount_gb;
445 uint64_t txframecount_gb;
446 uint64_t txbroadcastframes_g;
447 uint64_t txmulticastframes_g;
448 uint64_t tx64octets_gb;
449 uint64_t tx65to127octets_gb;
450 uint64_t tx128to255octets_gb;
451 uint64_t tx256to511octets_gb;
452 uint64_t tx512to1023octets_gb;
453 uint64_t tx1024tomaxoctets_gb;
454 uint64_t txunicastframes_gb;
455 uint64_t txmulticastframes_gb;
456 uint64_t txbroadcastframes_gb;
457 uint64_t txunderflowerror;
458 uint64_t txoctetcount_g;
459 uint64_t txframecount_g;
460 uint64_t txpauseframes;
461 uint64_t txvlanframes_g;
464 uint64_t rxframecount_gb;
465 uint64_t rxoctetcount_gb;
466 uint64_t rxoctetcount_g;
467 uint64_t rxbroadcastframes_g;
468 uint64_t rxmulticastframes_g;
470 uint64_t rxrunterror;
471 uint64_t rxjabbererror;
472 uint64_t rxundersize_g;
473 uint64_t rxoversize_g;
474 uint64_t rx64octets_gb;
475 uint64_t rx65to127octets_gb;
476 uint64_t rx128to255octets_gb;
477 uint64_t rx256to511octets_gb;
478 uint64_t rx512to1023octets_gb;
479 uint64_t rx1024tomaxoctets_gb;
480 uint64_t rxunicastframes_g;
481 uint64_t rxlengtherror;
482 uint64_t rxoutofrangetype;
483 uint64_t rxpauseframes;
484 uint64_t rxfifooverflow;
485 uint64_t rxvlanframes_gb;
486 uint64_t rxwatchdogerror;
489 /* Flow control parameters */
490 struct xgbe_fc_info {
491 uint32_t high_water[AXGBE_PRIORITY_QUEUES];
492 uint32_t low_water[AXGBE_PRIORITY_QUEUES];
493 uint16_t pause_time[AXGBE_PRIORITY_QUEUES];
495 enum rte_eth_fc_mode mode;
500 * Structure to store private data for each port.
503 /* Ethdev where port belongs*/
504 struct rte_eth_dev *eth_dev;
506 const struct rte_pci_device *pci_dev;
507 /* Version related data */
508 struct axgbe_version_data *vdata;
510 /* AXGMAC/XPCS related mmio registers */
511 void *xgmac_regs; /* AXGMAC CSRs */
512 void *xpcs_regs; /* XPCS MMD registers */
513 void *xprop_regs; /* AXGBE property registers */
514 void *xi2c_regs; /* AXGBE I2C CSRs */
516 bool cdr_track_early;
517 /* XPCS indirect addressing lock */
518 unsigned int xpcs_window_def_reg;
519 unsigned int xpcs_window_sel_reg;
520 unsigned int xpcs_window;
521 unsigned int xpcs_window_size;
522 unsigned int xpcs_window_mask;
524 /* Flags representing axgbe_state */
527 struct axgbe_hw_if hw_if;
528 struct axgbe_phy_if phy_if;
529 struct axgbe_i2c_if i2c_if;
531 /* AXI DMA settings */
532 unsigned int coherent;
533 unsigned int axdomain;
534 unsigned int arcache;
535 unsigned int awcache;
537 unsigned int tx_max_channel_count;
538 unsigned int rx_max_channel_count;
539 unsigned int channel_count;
540 unsigned int tx_ring_count;
541 unsigned int tx_desc_count;
542 unsigned int rx_ring_count;
543 unsigned int rx_desc_count;
545 unsigned int tx_max_q_count;
546 unsigned int rx_max_q_count;
547 unsigned int tx_q_count;
548 unsigned int rx_q_count;
550 /* Tx/Rx common settings */
554 unsigned int tx_sf_mode;
555 unsigned int tx_threshold;
557 unsigned int tx_osp_mode;
558 unsigned int tx_max_fifo_size;
561 unsigned int rx_sf_mode;
562 unsigned int rx_threshold;
564 unsigned int rx_max_fifo_size;
565 unsigned int rx_buf_size;
568 unsigned long sysclk_rate;
569 unsigned long ptpclk_rate;
571 /* Keeps track of power mode */
572 unsigned int power_down;
574 /* Current PHY settings */
578 pthread_mutex_t xpcs_mutex;
579 pthread_mutex_t i2c_mutex;
580 pthread_mutex_t an_mutex;
581 pthread_mutex_t phy_mutex;
583 /* Flow control settings */
584 unsigned int pause_autoneg;
585 unsigned int tx_pause;
586 unsigned int rx_pause;
587 unsigned int rx_rfa[AXGBE_MAX_QUEUES];
588 unsigned int rx_rfd[AXGBE_MAX_QUEUES];
590 unsigned int pfc_map[AXGBE_MAX_QUEUES];
592 /* Receive Side Scaling settings */
593 u8 rss_key[AXGBE_RSS_HASH_KEY_SIZE];
594 uint32_t rss_table[AXGBE_RSS_MAX_TABLE_SIZE];
595 uint32_t rss_options;
599 /* Hardware features of the device */
600 struct axgbe_hw_features hw_feat;
602 struct rte_ether_addr mac_addr;
604 /* Software Tx/Rx structure pointers*/
608 /* MDIO/PHY related settings */
609 unsigned int phy_started;
611 struct axgbe_phy phy;
613 unsigned long link_check;
614 volatile int mdio_completion;
616 unsigned int kr_redrv;
618 /* Auto-negotiation atate machine support */
620 unsigned int an_status;
621 enum axgbe_an an_result;
622 enum axgbe_an an_state;
623 enum axgbe_rx kr_state;
624 enum axgbe_rx kx_state;
625 unsigned int an_supported;
626 unsigned int parallel_detect;
627 unsigned int fec_ability;
628 unsigned long an_start;
629 enum axgbe_an_mode an_mode;
632 struct axgbe_i2c i2c;
633 volatile int i2c_complete;
635 /* CRC stripping by H/w for Rx packet*/
636 int crc_strip_enable;
637 /* csum enable to hardware */
638 uint32_t rx_csum_enable;
640 struct axgbe_mmc_stats mmc_stats;
641 struct xgbe_fc_info fc;
644 unsigned int hash_table_shift;
645 unsigned int hash_table_count;
646 unsigned int uc_hash_mac_addr;
647 unsigned int uc_hash_table[AXGBE_MAC_HASH_TABLE_SIZE];
650 void axgbe_init_function_ptrs_dev(struct axgbe_hw_if *hw_if);
651 void axgbe_init_function_ptrs_phy(struct axgbe_phy_if *phy_if);
652 void axgbe_init_function_ptrs_phy_v2(struct axgbe_phy_if *phy_if);
653 void axgbe_init_function_ptrs_i2c(struct axgbe_i2c_if *i2c_if);
654 void axgbe_set_mac_addn_addr(struct axgbe_port *pdata, u8 *addr,
656 void axgbe_set_mac_hash_table(struct axgbe_port *pdata, u8 *addr, bool add);
657 int axgbe_write_rss_lookup_table(struct axgbe_port *pdata);
658 int axgbe_write_rss_hash_key(struct axgbe_port *pdata);
660 #endif /* RTE_ETH_AXGBE_H_ */