1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved.
3 * Copyright(c) 2018 Synopsys, Inc. All rights reserved.
6 #ifndef RTE_ETH_AXGBE_H_
7 #define RTE_ETH_AXGBE_H_
9 #include <rte_mempool.h>
10 #include <rte_lcore.h>
11 #include "axgbe_common.h"
13 #define AXGBE_MAX_DMA_CHANNELS 16
14 #define AXGBE_MAX_QUEUES 16
15 #define AXGBE_PRIORITY_QUEUES 8
16 #define AXGBE_DMA_STOP_TIMEOUT 1
18 /* DMA cache settings - Outer sharable, write-back, write-allocate */
19 #define AXGBE_DMA_OS_AXDOMAIN 0x2
20 #define AXGBE_DMA_OS_ARCACHE 0xb
21 #define AXGBE_DMA_OS_AWCACHE 0xf
23 /* DMA cache settings - System, no caches used */
24 #define AXGBE_DMA_SYS_AXDOMAIN 0x3
25 #define AXGBE_DMA_SYS_ARCACHE 0x0
26 #define AXGBE_DMA_SYS_AWCACHE 0x0
29 #define AXGBE_AXGMAC_BAR 0
30 #define AXGBE_XPCS_BAR 1
31 #define AXGBE_MAC_PROP_OFFSET 0x1d000
32 #define AXGBE_I2C_CTRL_OFFSET 0x1e000
34 /* PCI clock frequencies */
35 #define AXGBE_V2_DMA_CLOCK_FREQ 500000000
36 #define AXGBE_V2_PTP_CLOCK_FREQ 125000000
38 #define AXGMAC_FIFO_MIN_ALLOC 2048
39 #define AXGMAC_FIFO_UNIT 256
40 #define AXGMAC_FIFO_ALIGN(_x) \
41 (((_x) + AXGMAC_FIFO_UNIT - 1) & ~(XGMAC_FIFO_UNIT - 1))
42 #define AXGMAC_FIFO_FC_OFF 2048
43 #define AXGMAC_FIFO_FC_MIN 4096
45 #define AXGBE_TC_MIN_QUANTUM 10
47 /* Flow control queue count */
48 #define AXGMAC_MAX_FLOW_CONTROL_QUEUES 8
50 /* Flow control threshold units */
51 #define AXGMAC_FLOW_CONTROL_UNIT 512
52 #define AXGMAC_FLOW_CONTROL_ALIGN(_x) \
53 (((_x) + AXGMAC_FLOW_CONTROL_UNIT - 1) & \
54 ~(AXGMAC_FLOW_CONTROL_UNIT - 1))
55 #define AXGMAC_FLOW_CONTROL_VALUE(_x) \
56 (((_x) < 1024) ? 0 : ((_x) / AXGMAC_FLOW_CONTROL_UNIT) - 2)
57 #define AXGMAC_FLOW_CONTROL_MAX 33280
59 /* Maximum MAC address hash table size (256 bits = 8 bytes) */
60 #define AXGBE_MAC_HASH_TABLE_SIZE 8
62 /* Receive Side Scaling */
63 #define AXGBE_RSS_OFFLOAD ( \
65 ETH_RSS_NONFRAG_IPV4_TCP | \
66 ETH_RSS_NONFRAG_IPV4_UDP | \
68 ETH_RSS_NONFRAG_IPV6_TCP | \
69 ETH_RSS_NONFRAG_IPV6_UDP)
71 #define AXGBE_RSS_HASH_KEY_SIZE 40
72 #define AXGBE_RSS_MAX_TABLE_SIZE 256
73 #define AXGBE_RSS_LOOKUP_TABLE_TYPE 0
74 #define AXGBE_RSS_HASH_KEY_TYPE 1
76 /* Auto-negotiation */
77 #define AXGBE_AN_MS_TIMEOUT 500
78 #define AXGBE_LINK_TIMEOUT 5
80 #define AXGBE_SGMII_AN_LINK_STATUS BIT(1)
81 #define AXGBE_SGMII_AN_LINK_SPEED (BIT(2) | BIT(3))
82 #define AXGBE_SGMII_AN_LINK_SPEED_100 0x04
83 #define AXGBE_SGMII_AN_LINK_SPEED_1000 0x08
84 #define AXGBE_SGMII_AN_LINK_DUPLEX BIT(4)
86 /* ECC correctable error notification window (seconds) */
87 #define AXGBE_ECC_LIMIT 60
90 #define AXGMAC_MAX_C22_PORT 3
92 /* Helper macro for descriptor handling
93 * Always use AXGBE_GET_DESC_DATA to access the descriptor data
94 * since the index is free-running and needs to be and-ed
95 * with the descriptor count value of the ring to index to
96 * the proper descriptor data.
98 #define AXGBE_GET_DESC_DATA(_ring, _idx) \
100 ((_idx) & ((_ring)->rdesc_count - 1)))
112 AXGMAC_INT_DMA_CH_SR_TI,
113 AXGMAC_INT_DMA_CH_SR_TPS,
114 AXGMAC_INT_DMA_CH_SR_TBU,
115 AXGMAC_INT_DMA_CH_SR_RI,
116 AXGMAC_INT_DMA_CH_SR_RBU,
117 AXGMAC_INT_DMA_CH_SR_RPS,
118 AXGMAC_INT_DMA_CH_SR_TI_RI,
119 AXGMAC_INT_DMA_CH_SR_FBE,
123 enum axgbe_int_state {
124 AXGMAC_INT_STATE_SAVE,
125 AXGMAC_INT_STATE_RESTORE,
135 AXGBE_SPEED_1000 = 0,
141 enum axgbe_xpcs_access {
142 AXGBE_XPCS_ACCESS_V1 = 0,
143 AXGBE_XPCS_ACCESS_V2,
147 AXGBE_AN_MODE_CL73 = 0,
148 AXGBE_AN_MODE_CL73_REDRV,
150 AXGBE_AN_MODE_CL37_SGMII,
156 AXGBE_AN_PAGE_RECEIVED,
157 AXGBE_AN_INCOMPAT_LINK,
171 AXGBE_MODE_KX_1000 = 0,
175 AXGBE_MODE_SGMII_100,
176 AXGBE_MODE_SGMII_1000,
181 enum axgbe_speedset {
182 AXGBE_SPEEDSET_1000_10000 = 0,
183 AXGBE_SPEEDSET_2500_10000,
186 enum axgbe_mdio_mode {
187 AXGBE_MDIO_MODE_NONE = 0,
188 AXGBE_MDIO_MODE_CL22,
189 AXGBE_MDIO_MODE_CL45,
194 uint32_t advertising;
195 uint32_t lp_advertising;
211 AXGBE_I2C_CMD_READ = 0,
215 struct axgbe_i2c_op {
216 enum axgbe_i2c_cmd cmd;
224 struct axgbe_i2c_op_state {
225 struct axgbe_i2c_op *op;
228 unsigned char *tx_buf;
231 unsigned char *rx_buf;
233 unsigned int tx_abort_source;
239 unsigned int started;
240 unsigned int max_speed_mode;
241 unsigned int rx_fifo_size;
242 unsigned int tx_fifo_size;
244 struct axgbe_i2c_op_state op_state;
248 void (*config_flow_control)(struct axgbe_port *);
249 int (*config_rx_mode)(struct axgbe_port *);
251 int (*init)(struct axgbe_port *);
253 int (*read_mmd_regs)(struct axgbe_port *, int, int);
254 void (*write_mmd_regs)(struct axgbe_port *, int, int, int);
255 int (*set_speed)(struct axgbe_port *, int);
257 int (*set_ext_mii_mode)(struct axgbe_port *, unsigned int,
258 enum axgbe_mdio_mode);
259 int (*read_ext_mii_regs)(struct axgbe_port *, int, int);
260 int (*write_ext_mii_regs)(struct axgbe_port *, int, int, uint16_t);
263 int (*config_tx_flow_control)(struct axgbe_port *);
264 int (*config_rx_flow_control)(struct axgbe_port *);
266 int (*exit)(struct axgbe_port *);
269 /* This structure represents implementation specific routines for an
270 * implementation of a PHY. All routines are required unless noted below.
272 * kr_training_pre, kr_training_post
274 struct axgbe_phy_impl_if {
275 /* Perform Setup/teardown actions */
276 int (*init)(struct axgbe_port *);
277 void (*exit)(struct axgbe_port *);
279 /* Perform start/stop specific actions */
280 int (*reset)(struct axgbe_port *);
281 int (*start)(struct axgbe_port *);
282 void (*stop)(struct axgbe_port *);
284 /* Return the link status */
285 int (*link_status)(struct axgbe_port *, int *);
287 /* Indicate if a particular speed is valid */
288 int (*valid_speed)(struct axgbe_port *, int);
290 /* Check if the specified mode can/should be used */
291 bool (*use_mode)(struct axgbe_port *, enum axgbe_mode);
292 /* Switch the PHY into various modes */
293 void (*set_mode)(struct axgbe_port *, enum axgbe_mode);
294 /* Retrieve mode needed for a specific speed */
295 enum axgbe_mode (*get_mode)(struct axgbe_port *, int);
296 /* Retrieve new/next mode when trying to auto-negotiate */
297 enum axgbe_mode (*switch_mode)(struct axgbe_port *);
298 /* Retrieve current mode */
299 enum axgbe_mode (*cur_mode)(struct axgbe_port *);
301 /* Retrieve current auto-negotiation mode */
302 enum axgbe_an_mode (*an_mode)(struct axgbe_port *);
304 /* Configure auto-negotiation settings */
305 int (*an_config)(struct axgbe_port *);
307 /* Set/override auto-negotiation advertisement settings */
308 unsigned int (*an_advertising)(struct axgbe_port *port);
310 /* Process results of auto-negotiation */
311 enum axgbe_mode (*an_outcome)(struct axgbe_port *);
313 /* Pre/Post KR training enablement support */
314 void (*kr_training_pre)(struct axgbe_port *);
315 void (*kr_training_post)(struct axgbe_port *);
318 struct axgbe_phy_if {
319 /* For PHY setup/teardown */
320 int (*phy_init)(struct axgbe_port *);
321 void (*phy_exit)(struct axgbe_port *);
323 /* For PHY support when setting device up/down */
324 int (*phy_reset)(struct axgbe_port *);
325 int (*phy_start)(struct axgbe_port *);
326 void (*phy_stop)(struct axgbe_port *);
328 /* For PHY support while device is up */
329 void (*phy_status)(struct axgbe_port *);
330 int (*phy_config_aneg)(struct axgbe_port *);
332 /* For PHY settings validation */
333 int (*phy_valid_speed)(struct axgbe_port *, int);
334 /* For single interrupt support */
335 void (*an_isr)(struct axgbe_port *);
336 /* PHY implementation specific services */
337 struct axgbe_phy_impl_if phy_impl;
340 struct axgbe_i2c_if {
341 /* For initial I2C setup */
342 int (*i2c_init)(struct axgbe_port *);
344 /* For I2C support when setting device up/down */
345 int (*i2c_start)(struct axgbe_port *);
346 void (*i2c_stop)(struct axgbe_port *);
348 /* For performing I2C operations */
349 int (*i2c_xfer)(struct axgbe_port *, struct axgbe_i2c_op *);
352 /* This structure contains flags that indicate what hardware features
353 * or configurations are present in the device.
355 struct axgbe_hw_features {
357 unsigned int version;
359 /* HW Feature Register0 */
360 unsigned int gmii; /* 1000 Mbps support */
361 unsigned int vlhash; /* VLAN Hash Filter */
362 unsigned int sma; /* SMA(MDIO) Interface */
363 unsigned int rwk; /* PMT remote wake-up packet */
364 unsigned int mgk; /* PMT magic packet */
365 unsigned int mmc; /* RMON module */
366 unsigned int aoe; /* ARP Offload */
367 unsigned int ts; /* IEEE 1588-2008 Advanced Timestamp */
368 unsigned int eee; /* Energy Efficient Ethernet */
369 unsigned int tx_coe; /* Tx Checksum Offload */
370 unsigned int rx_coe; /* Rx Checksum Offload */
371 unsigned int addn_mac; /* Additional MAC Addresses */
372 unsigned int ts_src; /* Timestamp Source */
373 unsigned int sa_vlan_ins; /* Source Address or VLAN Insertion */
375 /* HW Feature Register1 */
376 unsigned int rx_fifo_size; /* MTL Receive FIFO Size */
377 unsigned int tx_fifo_size; /* MTL Transmit FIFO Size */
378 unsigned int adv_ts_hi; /* Advance Timestamping High Word */
379 unsigned int dma_width; /* DMA width */
380 unsigned int dcb; /* DCB Feature */
381 unsigned int sph; /* Split Header Feature */
382 unsigned int tso; /* TCP Segmentation Offload */
383 unsigned int dma_debug; /* DMA Debug Registers */
384 unsigned int rss; /* Receive Side Scaling */
385 unsigned int tc_cnt; /* Number of Traffic Classes */
386 unsigned int hash_table_size; /* Hash Table Size */
387 unsigned int l3l4_filter_num; /* Number of L3-L4 Filters */
389 /* HW Feature Register2 */
390 unsigned int rx_q_cnt; /* Number of MTL Receive Queues */
391 unsigned int tx_q_cnt; /* Number of MTL Transmit Queues */
392 unsigned int rx_ch_cnt; /* Number of DMA Receive Channels */
393 unsigned int tx_ch_cnt; /* Number of DMA Transmit Channels */
394 unsigned int pps_out_num; /* Number of PPS outputs */
395 unsigned int aux_snap_num; /* Number of Aux snapshot inputs */
398 struct axgbe_version_data {
399 void (*init_function_ptrs_phy_impl)(struct axgbe_phy_if *);
400 enum axgbe_xpcs_access xpcs_access;
401 unsigned int mmc_64bit;
402 unsigned int tx_max_fifo_size;
403 unsigned int rx_max_fifo_size;
404 unsigned int tx_tstamp_workaround;
405 unsigned int ecc_support;
406 unsigned int i2c_support;
410 * Structure to store private data for each port.
413 /* Ethdev where port belongs*/
414 struct rte_eth_dev *eth_dev;
416 const struct rte_pci_device *pci_dev;
417 /* Version related data */
418 struct axgbe_version_data *vdata;
420 /* AXGMAC/XPCS related mmio registers */
421 uint64_t xgmac_regs; /* AXGMAC CSRs */
422 uint64_t xpcs_regs; /* XPCS MMD registers */
423 uint64_t xprop_regs; /* AXGBE property registers */
424 uint64_t xi2c_regs; /* AXGBE I2C CSRs */
426 /* XPCS indirect addressing lock */
427 unsigned int xpcs_window_def_reg;
428 unsigned int xpcs_window_sel_reg;
429 unsigned int xpcs_window;
430 unsigned int xpcs_window_size;
431 unsigned int xpcs_window_mask;
433 /* Flags representing axgbe_state */
434 unsigned long dev_state;
436 struct axgbe_hw_if hw_if;
437 struct axgbe_phy_if phy_if;
438 struct axgbe_i2c_if i2c_if;
440 /* AXI DMA settings */
441 unsigned int coherent;
442 unsigned int axdomain;
443 unsigned int arcache;
444 unsigned int awcache;
446 unsigned int tx_max_channel_count;
447 unsigned int rx_max_channel_count;
448 unsigned int channel_count;
449 unsigned int tx_ring_count;
450 unsigned int tx_desc_count;
451 unsigned int rx_ring_count;
452 unsigned int rx_desc_count;
454 unsigned int tx_max_q_count;
455 unsigned int rx_max_q_count;
456 unsigned int tx_q_count;
457 unsigned int rx_q_count;
459 /* Tx/Rx common settings */
463 unsigned int tx_sf_mode;
464 unsigned int tx_threshold;
466 unsigned int tx_osp_mode;
467 unsigned int tx_max_fifo_size;
470 unsigned int rx_sf_mode;
471 unsigned int rx_threshold;
473 unsigned int rx_max_fifo_size;
474 unsigned int rx_buf_size;
477 unsigned long sysclk_rate;
478 unsigned long ptpclk_rate;
480 /* Keeps track of power mode */
481 unsigned int power_down;
483 /* Current PHY settings */
487 pthread_mutex_t xpcs_mutex;
488 pthread_mutex_t i2c_mutex;
489 pthread_mutex_t an_mutex;
490 pthread_mutex_t phy_mutex;
492 /* Flow control settings */
493 unsigned int pause_autoneg;
494 unsigned int tx_pause;
495 unsigned int rx_pause;
496 unsigned int rx_rfa[AXGBE_MAX_QUEUES];
497 unsigned int rx_rfd[AXGBE_MAX_QUEUES];
500 /* Receive Side Scaling settings */
501 u8 rss_key[AXGBE_RSS_HASH_KEY_SIZE];
502 uint32_t rss_table[AXGBE_RSS_MAX_TABLE_SIZE];
503 uint32_t rss_options;
506 /* Hardware features of the device */
507 struct axgbe_hw_features hw_feat;
509 struct ether_addr mac_addr;
511 /* MDIO/PHY related settings */
512 unsigned int phy_started;
514 struct axgbe_phy phy;
516 unsigned long link_check;
517 volatile int mdio_completion;
519 unsigned int kr_redrv;
521 /* Auto-negotiation atate machine support */
523 unsigned int an_status;
524 enum axgbe_an an_result;
525 enum axgbe_an an_state;
526 enum axgbe_rx kr_state;
527 enum axgbe_rx kx_state;
528 unsigned int an_supported;
529 unsigned int parallel_detect;
530 unsigned int fec_ability;
531 unsigned long an_start;
532 enum axgbe_an_mode an_mode;
535 struct axgbe_i2c i2c;
536 volatile int i2c_complete;
539 void axgbe_init_function_ptrs_dev(struct axgbe_hw_if *hw_if);
540 void axgbe_init_function_ptrs_phy(struct axgbe_phy_if *phy_if);
541 void axgbe_init_function_ptrs_phy_v2(struct axgbe_phy_if *phy_if);
542 void axgbe_init_function_ptrs_i2c(struct axgbe_i2c_if *i2c_if);
544 #endif /* RTE_ETH_AXGBE_H_ */