1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved.
3 * Copyright(c) 2018 Synopsys, Inc. All rights reserved.
6 #include "axgbe_ethdev.h"
7 #include "axgbe_common.h"
10 #define AXGBE_PHY_PORT_SPEED_100 BIT(0)
11 #define AXGBE_PHY_PORT_SPEED_1000 BIT(1)
12 #define AXGBE_PHY_PORT_SPEED_2500 BIT(2)
13 #define AXGBE_PHY_PORT_SPEED_10000 BIT(3)
15 #define AXGBE_MUTEX_RELEASE 0x80000000
17 #define AXGBE_SFP_DIRECT 7
19 /* I2C target addresses */
20 #define AXGBE_SFP_SERIAL_ID_ADDRESS 0x50
21 #define AXGBE_SFP_DIAG_INFO_ADDRESS 0x51
22 #define AXGBE_SFP_PHY_ADDRESS 0x56
23 #define AXGBE_GPIO_ADDRESS_PCA9555 0x20
25 /* SFP sideband signal indicators */
26 #define AXGBE_GPIO_NO_TX_FAULT BIT(0)
27 #define AXGBE_GPIO_NO_RATE_SELECT BIT(1)
28 #define AXGBE_GPIO_NO_MOD_ABSENT BIT(2)
29 #define AXGBE_GPIO_NO_RX_LOS BIT(3)
31 /* Rate-change complete wait/retry count */
32 #define AXGBE_RATECHANGE_COUNT 500
34 /* CDR delay values for KR support (in usec) */
35 #define AXGBE_CDR_DELAY_INIT 10000
36 #define AXGBE_CDR_DELAY_INC 10000
37 #define AXGBE_CDR_DELAY_MAX 100000
39 enum axgbe_port_mode {
40 AXGBE_PORT_MODE_RSVD = 0,
41 AXGBE_PORT_MODE_BACKPLANE,
42 AXGBE_PORT_MODE_BACKPLANE_2500,
43 AXGBE_PORT_MODE_1000BASE_T,
44 AXGBE_PORT_MODE_1000BASE_X,
45 AXGBE_PORT_MODE_NBASE_T,
46 AXGBE_PORT_MODE_10GBASE_T,
47 AXGBE_PORT_MODE_10GBASE_R,
52 enum axgbe_conn_type {
53 AXGBE_CONN_TYPE_NONE = 0,
56 AXGBE_CONN_TYPE_RSVD1,
57 AXGBE_CONN_TYPE_BACKPLANE,
61 /* SFP/SFP+ related definitions */
63 AXGBE_SFP_COMM_DIRECT = 0,
64 AXGBE_SFP_COMM_PCA9545,
67 enum axgbe_sfp_cable {
68 AXGBE_SFP_CABLE_UNKNOWN = 0,
69 AXGBE_SFP_CABLE_ACTIVE,
70 AXGBE_SFP_CABLE_PASSIVE,
74 AXGBE_SFP_BASE_UNKNOWN = 0,
75 AXGBE_SFP_BASE_1000_T,
76 AXGBE_SFP_BASE_1000_SX,
77 AXGBE_SFP_BASE_1000_LX,
78 AXGBE_SFP_BASE_1000_CX,
79 AXGBE_SFP_BASE_10000_SR,
80 AXGBE_SFP_BASE_10000_LR,
81 AXGBE_SFP_BASE_10000_LRM,
82 AXGBE_SFP_BASE_10000_ER,
83 AXGBE_SFP_BASE_10000_CR,
86 enum axgbe_sfp_speed {
87 AXGBE_SFP_SPEED_UNKNOWN = 0,
88 AXGBE_SFP_SPEED_100_1000,
90 AXGBE_SFP_SPEED_10000,
93 /* SFP Serial ID Base ID values relative to an offset of 0 */
94 #define AXGBE_SFP_BASE_ID 0
95 #define AXGBE_SFP_ID_SFP 0x03
97 #define AXGBE_SFP_BASE_EXT_ID 1
98 #define AXGBE_SFP_EXT_ID_SFP 0x04
100 #define AXGBE_SFP_BASE_10GBE_CC 3
101 #define AXGBE_SFP_BASE_10GBE_CC_SR BIT(4)
102 #define AXGBE_SFP_BASE_10GBE_CC_LR BIT(5)
103 #define AXGBE_SFP_BASE_10GBE_CC_LRM BIT(6)
104 #define AXGBE_SFP_BASE_10GBE_CC_ER BIT(7)
106 #define AXGBE_SFP_BASE_1GBE_CC 6
107 #define AXGBE_SFP_BASE_1GBE_CC_SX BIT(0)
108 #define AXGBE_SFP_BASE_1GBE_CC_LX BIT(1)
109 #define AXGBE_SFP_BASE_1GBE_CC_CX BIT(2)
110 #define AXGBE_SFP_BASE_1GBE_CC_T BIT(3)
112 #define AXGBE_SFP_BASE_CABLE 8
113 #define AXGBE_SFP_BASE_CABLE_PASSIVE BIT(2)
114 #define AXGBE_SFP_BASE_CABLE_ACTIVE BIT(3)
116 #define AXGBE_SFP_BASE_BR 12
117 #define AXGBE_SFP_BASE_BR_1GBE_MIN 0x0a
118 #define AXGBE_SFP_BASE_BR_1GBE_MAX 0x0d
119 #define AXGBE_SFP_BASE_BR_10GBE_MIN 0x64
120 #define AXGBE_SFP_BASE_BR_10GBE_MAX 0x68
122 #define AXGBE_SFP_BASE_CU_CABLE_LEN 18
124 #define AXGBE_SFP_BASE_VENDOR_NAME 20
125 #define AXGBE_SFP_BASE_VENDOR_NAME_LEN 16
126 #define AXGBE_SFP_BASE_VENDOR_PN 40
127 #define AXGBE_SFP_BASE_VENDOR_PN_LEN 16
128 #define AXGBE_SFP_BASE_VENDOR_REV 56
129 #define AXGBE_SFP_BASE_VENDOR_REV_LEN 4
131 #define AXGBE_SFP_BASE_CC 63
133 /* SFP Serial ID Extended ID values relative to an offset of 64 */
134 #define AXGBE_SFP_BASE_VENDOR_SN 4
135 #define AXGBE_SFP_BASE_VENDOR_SN_LEN 16
137 #define AXGBE_SFP_EXTD_DIAG 28
138 #define AXGBE_SFP_EXTD_DIAG_ADDR_CHANGE BIT(2)
140 #define AXGBE_SFP_EXTD_SFF_8472 30
142 #define AXGBE_SFP_EXTD_CC 31
144 struct axgbe_sfp_eeprom {
150 #define AXGBE_BEL_FUSE_VENDOR "BEL-FUSE"
151 #define AXGBE_BEL_FUSE_PARTNO "1GBT-SFP06"
153 struct axgbe_sfp_ascii {
155 char vendor[AXGBE_SFP_BASE_VENDOR_NAME_LEN + 1];
156 char partno[AXGBE_SFP_BASE_VENDOR_PN_LEN + 1];
157 char rev[AXGBE_SFP_BASE_VENDOR_REV_LEN + 1];
158 char serno[AXGBE_SFP_BASE_VENDOR_SN_LEN + 1];
162 /* MDIO PHY reset types */
163 enum axgbe_mdio_reset {
164 AXGBE_MDIO_RESET_NONE = 0,
165 AXGBE_MDIO_RESET_I2C_GPIO,
166 AXGBE_MDIO_RESET_INT_GPIO,
167 AXGBE_MDIO_RESET_MAX,
170 /* Re-driver related definitions */
171 enum axgbe_phy_redrv_if {
172 AXGBE_PHY_REDRV_IF_MDIO = 0,
173 AXGBE_PHY_REDRV_IF_I2C,
174 AXGBE_PHY_REDRV_IF_MAX,
177 enum axgbe_phy_redrv_model {
178 AXGBE_PHY_REDRV_MODEL_4223 = 0,
179 AXGBE_PHY_REDRV_MODEL_4227,
180 AXGBE_PHY_REDRV_MODEL_MAX,
183 enum axgbe_phy_redrv_mode {
184 AXGBE_PHY_REDRV_MODE_CX = 5,
185 AXGBE_PHY_REDRV_MODE_SR = 9,
188 #define AXGBE_PHY_REDRV_MODE_REG 0x12b0
190 /* PHY related configuration information */
191 struct axgbe_phy_data {
192 enum axgbe_port_mode port_mode;
194 unsigned int port_id;
196 unsigned int port_speeds;
198 enum axgbe_conn_type conn_type;
200 enum axgbe_mode cur_mode;
201 enum axgbe_mode start_mode;
203 unsigned int rrc_count;
205 unsigned int mdio_addr;
207 unsigned int comm_owned;
210 enum axgbe_sfp_comm sfp_comm;
211 unsigned int sfp_mux_address;
212 unsigned int sfp_mux_channel;
214 unsigned int sfp_gpio_address;
215 unsigned int sfp_gpio_mask;
216 unsigned int sfp_gpio_rx_los;
217 unsigned int sfp_gpio_tx_fault;
218 unsigned int sfp_gpio_mod_absent;
219 unsigned int sfp_gpio_rate_select;
221 unsigned int sfp_rx_los;
222 unsigned int sfp_tx_fault;
223 unsigned int sfp_mod_absent;
224 unsigned int sfp_diags;
225 unsigned int sfp_changed;
226 unsigned int sfp_phy_avail;
227 unsigned int sfp_cable_len;
228 enum axgbe_sfp_base sfp_base;
229 enum axgbe_sfp_cable sfp_cable;
230 enum axgbe_sfp_speed sfp_speed;
231 struct axgbe_sfp_eeprom sfp_eeprom;
233 /* External PHY support */
234 enum axgbe_mdio_mode phydev_mode;
235 enum axgbe_mdio_reset mdio_reset;
236 unsigned int mdio_reset_addr;
237 unsigned int mdio_reset_gpio;
239 /* Re-driver support */
241 unsigned int redrv_if;
242 unsigned int redrv_addr;
243 unsigned int redrv_lane;
244 unsigned int redrv_model;
247 unsigned int phy_cdr_notrack;
248 unsigned int phy_cdr_delay;
251 static enum axgbe_an_mode axgbe_phy_an_mode(struct axgbe_port *pdata);
253 static int axgbe_phy_i2c_xfer(struct axgbe_port *pdata,
254 struct axgbe_i2c_op *i2c_op)
256 struct axgbe_phy_data *phy_data = pdata->phy_data;
258 /* Be sure we own the bus */
259 if (!phy_data->comm_owned)
262 return pdata->i2c_if.i2c_xfer(pdata, i2c_op);
265 static int axgbe_phy_redrv_write(struct axgbe_port *pdata, unsigned int reg,
268 struct axgbe_phy_data *phy_data = pdata->phy_data;
269 struct axgbe_i2c_op i2c_op;
271 u8 redrv_data[5], csum;
272 unsigned int i, retry;
275 /* High byte of register contains read/write indicator */
276 redrv_data[0] = ((reg >> 8) & 0xff) << 1;
277 redrv_data[1] = reg & 0xff;
278 redrv_val = (uint16_t *)&redrv_data[2];
279 *redrv_val = rte_cpu_to_be_16(val);
281 /* Calculate 1 byte checksum */
283 for (i = 0; i < 4; i++) {
284 csum += redrv_data[i];
285 if (redrv_data[i] > csum)
288 redrv_data[4] = ~csum;
292 i2c_op.cmd = AXGBE_I2C_CMD_WRITE;
293 i2c_op.target = phy_data->redrv_addr;
294 i2c_op.len = sizeof(redrv_data);
295 i2c_op.buf = redrv_data;
296 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op);
298 if ((ret == -EAGAIN) && retry--)
306 i2c_op.cmd = AXGBE_I2C_CMD_READ;
307 i2c_op.target = phy_data->redrv_addr;
309 i2c_op.buf = redrv_data;
310 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op);
312 if ((ret == -EAGAIN) && retry--)
318 if (redrv_data[0] != 0xff) {
319 PMD_DRV_LOG(ERR, "Redriver write checksum error\n");
326 static int axgbe_phy_i2c_read(struct axgbe_port *pdata, unsigned int target,
327 void *reg, unsigned int reg_len,
328 void *val, unsigned int val_len)
330 struct axgbe_i2c_op i2c_op;
335 /* Set the specified register to read */
336 i2c_op.cmd = AXGBE_I2C_CMD_WRITE;
337 i2c_op.target = target;
338 i2c_op.len = reg_len;
340 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op);
342 if ((ret == -EAGAIN) && retry--)
350 /* Read the specfied register */
351 i2c_op.cmd = AXGBE_I2C_CMD_READ;
352 i2c_op.target = target;
353 i2c_op.len = val_len;
355 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op);
356 if ((ret == -EAGAIN) && retry--)
362 static int axgbe_phy_sfp_put_mux(struct axgbe_port *pdata)
364 struct axgbe_phy_data *phy_data = pdata->phy_data;
365 struct axgbe_i2c_op i2c_op;
368 if (phy_data->sfp_comm == AXGBE_SFP_COMM_DIRECT)
371 /* Select no mux channels */
373 i2c_op.cmd = AXGBE_I2C_CMD_WRITE;
374 i2c_op.target = phy_data->sfp_mux_address;
375 i2c_op.len = sizeof(mux_channel);
376 i2c_op.buf = &mux_channel;
378 return axgbe_phy_i2c_xfer(pdata, &i2c_op);
381 static int axgbe_phy_sfp_get_mux(struct axgbe_port *pdata)
383 struct axgbe_phy_data *phy_data = pdata->phy_data;
384 struct axgbe_i2c_op i2c_op;
387 if (phy_data->sfp_comm == AXGBE_SFP_COMM_DIRECT)
390 /* Select desired mux channel */
391 mux_channel = 1 << phy_data->sfp_mux_channel;
392 i2c_op.cmd = AXGBE_I2C_CMD_WRITE;
393 i2c_op.target = phy_data->sfp_mux_address;
394 i2c_op.len = sizeof(mux_channel);
395 i2c_op.buf = &mux_channel;
397 return axgbe_phy_i2c_xfer(pdata, &i2c_op);
400 static void axgbe_phy_put_comm_ownership(struct axgbe_port *pdata)
402 struct axgbe_phy_data *phy_data = pdata->phy_data;
404 phy_data->comm_owned = 0;
406 pthread_mutex_unlock(&pdata->phy_mutex);
409 static int axgbe_phy_get_comm_ownership(struct axgbe_port *pdata)
411 struct axgbe_phy_data *phy_data = pdata->phy_data;
413 unsigned int mutex_id;
415 /* The I2C and MDIO/GPIO bus is multiplexed between multiple devices,
416 * the driver needs to take the software mutex and then the hardware
417 * mutexes before being able to use the busses.
419 pthread_mutex_lock(&pdata->phy_mutex);
421 if (phy_data->comm_owned)
424 /* Clear the mutexes */
425 XP_IOWRITE(pdata, XP_I2C_MUTEX, AXGBE_MUTEX_RELEASE);
426 XP_IOWRITE(pdata, XP_MDIO_MUTEX, AXGBE_MUTEX_RELEASE);
428 /* Mutex formats are the same for I2C and MDIO/GPIO */
430 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ID, phy_data->port_id);
431 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ACTIVE, 1);
433 timeout = rte_get_timer_cycles() + (rte_get_timer_hz() * 5);
434 while (time_before(rte_get_timer_cycles(), timeout)) {
435 /* Must be all zeroes in order to obtain the mutex */
436 if (XP_IOREAD(pdata, XP_I2C_MUTEX) ||
437 XP_IOREAD(pdata, XP_MDIO_MUTEX)) {
442 /* Obtain the mutex */
443 XP_IOWRITE(pdata, XP_I2C_MUTEX, mutex_id);
444 XP_IOWRITE(pdata, XP_MDIO_MUTEX, mutex_id);
446 phy_data->comm_owned = 1;
450 pthread_mutex_unlock(&pdata->phy_mutex);
452 PMD_DRV_LOG(ERR, "unable to obtain hardware mutexes\n");
457 static void axgbe_phy_sfp_phy_settings(struct axgbe_port *pdata)
459 struct axgbe_phy_data *phy_data = pdata->phy_data;
461 if (phy_data->sfp_mod_absent) {
462 pdata->phy.speed = SPEED_UNKNOWN;
463 pdata->phy.duplex = DUPLEX_UNKNOWN;
464 pdata->phy.autoneg = AUTONEG_ENABLE;
465 pdata->phy.advertising = pdata->phy.supported;
468 pdata->phy.advertising &= ~ADVERTISED_Autoneg;
469 pdata->phy.advertising &= ~ADVERTISED_TP;
470 pdata->phy.advertising &= ~ADVERTISED_FIBRE;
471 pdata->phy.advertising &= ~ADVERTISED_100baseT_Full;
472 pdata->phy.advertising &= ~ADVERTISED_1000baseT_Full;
473 pdata->phy.advertising &= ~ADVERTISED_10000baseT_Full;
474 pdata->phy.advertising &= ~ADVERTISED_10000baseR_FEC;
476 switch (phy_data->sfp_base) {
477 case AXGBE_SFP_BASE_1000_T:
478 case AXGBE_SFP_BASE_1000_SX:
479 case AXGBE_SFP_BASE_1000_LX:
480 case AXGBE_SFP_BASE_1000_CX:
481 pdata->phy.speed = SPEED_UNKNOWN;
482 pdata->phy.duplex = DUPLEX_UNKNOWN;
483 pdata->phy.autoneg = AUTONEG_ENABLE;
484 pdata->phy.advertising |= ADVERTISED_Autoneg;
486 case AXGBE_SFP_BASE_10000_SR:
487 case AXGBE_SFP_BASE_10000_LR:
488 case AXGBE_SFP_BASE_10000_LRM:
489 case AXGBE_SFP_BASE_10000_ER:
490 case AXGBE_SFP_BASE_10000_CR:
492 pdata->phy.speed = SPEED_10000;
493 pdata->phy.duplex = DUPLEX_FULL;
494 pdata->phy.autoneg = AUTONEG_DISABLE;
498 switch (phy_data->sfp_base) {
499 case AXGBE_SFP_BASE_1000_T:
500 case AXGBE_SFP_BASE_1000_CX:
501 case AXGBE_SFP_BASE_10000_CR:
502 pdata->phy.advertising |= ADVERTISED_TP;
505 pdata->phy.advertising |= ADVERTISED_FIBRE;
508 switch (phy_data->sfp_speed) {
509 case AXGBE_SFP_SPEED_100_1000:
510 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100)
511 pdata->phy.advertising |= ADVERTISED_100baseT_Full;
512 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000)
513 pdata->phy.advertising |= ADVERTISED_1000baseT_Full;
515 case AXGBE_SFP_SPEED_1000:
516 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000)
517 pdata->phy.advertising |= ADVERTISED_1000baseT_Full;
519 case AXGBE_SFP_SPEED_10000:
520 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000)
521 pdata->phy.advertising |= ADVERTISED_10000baseT_Full;
524 /* Choose the fastest supported speed */
525 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000)
526 pdata->phy.advertising |= ADVERTISED_10000baseT_Full;
527 else if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000)
528 pdata->phy.advertising |= ADVERTISED_1000baseT_Full;
529 else if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100)
530 pdata->phy.advertising |= ADVERTISED_100baseT_Full;
534 static bool axgbe_phy_sfp_bit_rate(struct axgbe_sfp_eeprom *sfp_eeprom,
535 enum axgbe_sfp_speed sfp_speed)
537 u8 *sfp_base, min, max;
539 sfp_base = sfp_eeprom->base;
542 case AXGBE_SFP_SPEED_1000:
543 min = AXGBE_SFP_BASE_BR_1GBE_MIN;
544 max = AXGBE_SFP_BASE_BR_1GBE_MAX;
546 case AXGBE_SFP_SPEED_10000:
547 min = AXGBE_SFP_BASE_BR_10GBE_MIN;
548 max = AXGBE_SFP_BASE_BR_10GBE_MAX;
554 return ((sfp_base[AXGBE_SFP_BASE_BR] >= min) &&
555 (sfp_base[AXGBE_SFP_BASE_BR] <= max));
558 static void axgbe_phy_sfp_external_phy(struct axgbe_port *pdata)
560 struct axgbe_phy_data *phy_data = pdata->phy_data;
562 if (!phy_data->sfp_changed)
565 phy_data->sfp_phy_avail = 0;
567 if (phy_data->sfp_base != AXGBE_SFP_BASE_1000_T)
571 static bool axgbe_phy_belfuse_parse_quirks(struct axgbe_port *pdata)
573 struct axgbe_phy_data *phy_data = pdata->phy_data;
574 struct axgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
576 if (memcmp(&sfp_eeprom->base[AXGBE_SFP_BASE_VENDOR_NAME],
577 AXGBE_BEL_FUSE_VENDOR, strlen(AXGBE_BEL_FUSE_VENDOR)))
580 if (!memcmp(&sfp_eeprom->base[AXGBE_SFP_BASE_VENDOR_PN],
581 AXGBE_BEL_FUSE_PARTNO, strlen(AXGBE_BEL_FUSE_PARTNO))) {
582 phy_data->sfp_base = AXGBE_SFP_BASE_1000_SX;
583 phy_data->sfp_cable = AXGBE_SFP_CABLE_ACTIVE;
584 phy_data->sfp_speed = AXGBE_SFP_SPEED_1000;
591 static bool axgbe_phy_sfp_parse_quirks(struct axgbe_port *pdata)
593 if (axgbe_phy_belfuse_parse_quirks(pdata))
599 static void axgbe_phy_sfp_parse_eeprom(struct axgbe_port *pdata)
601 struct axgbe_phy_data *phy_data = pdata->phy_data;
602 struct axgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
605 sfp_base = sfp_eeprom->base;
607 if (sfp_base[AXGBE_SFP_BASE_ID] != AXGBE_SFP_ID_SFP)
610 if (sfp_base[AXGBE_SFP_BASE_EXT_ID] != AXGBE_SFP_EXT_ID_SFP)
613 axgbe_phy_sfp_parse_quirks(pdata);
615 /* Assume ACTIVE cable unless told it is PASSIVE */
616 if (sfp_base[AXGBE_SFP_BASE_CABLE] & AXGBE_SFP_BASE_CABLE_PASSIVE) {
617 phy_data->sfp_cable = AXGBE_SFP_CABLE_PASSIVE;
618 phy_data->sfp_cable_len = sfp_base[AXGBE_SFP_BASE_CU_CABLE_LEN];
620 phy_data->sfp_cable = AXGBE_SFP_CABLE_ACTIVE;
623 /* Determine the type of SFP */
624 if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] & AXGBE_SFP_BASE_10GBE_CC_SR)
625 phy_data->sfp_base = AXGBE_SFP_BASE_10000_SR;
626 else if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] & AXGBE_SFP_BASE_10GBE_CC_LR)
627 phy_data->sfp_base = AXGBE_SFP_BASE_10000_LR;
628 else if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] &
629 AXGBE_SFP_BASE_10GBE_CC_LRM)
630 phy_data->sfp_base = AXGBE_SFP_BASE_10000_LRM;
631 else if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] & AXGBE_SFP_BASE_10GBE_CC_ER)
632 phy_data->sfp_base = AXGBE_SFP_BASE_10000_ER;
633 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_SX)
634 phy_data->sfp_base = AXGBE_SFP_BASE_1000_SX;
635 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_LX)
636 phy_data->sfp_base = AXGBE_SFP_BASE_1000_LX;
637 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_CX)
638 phy_data->sfp_base = AXGBE_SFP_BASE_1000_CX;
639 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_T)
640 phy_data->sfp_base = AXGBE_SFP_BASE_1000_T;
641 else if ((phy_data->sfp_cable == AXGBE_SFP_CABLE_PASSIVE) &&
642 axgbe_phy_sfp_bit_rate(sfp_eeprom, AXGBE_SFP_SPEED_10000))
643 phy_data->sfp_base = AXGBE_SFP_BASE_10000_CR;
645 switch (phy_data->sfp_base) {
646 case AXGBE_SFP_BASE_1000_T:
647 phy_data->sfp_speed = AXGBE_SFP_SPEED_100_1000;
649 case AXGBE_SFP_BASE_1000_SX:
650 case AXGBE_SFP_BASE_1000_LX:
651 case AXGBE_SFP_BASE_1000_CX:
652 phy_data->sfp_speed = AXGBE_SFP_SPEED_1000;
654 case AXGBE_SFP_BASE_10000_SR:
655 case AXGBE_SFP_BASE_10000_LR:
656 case AXGBE_SFP_BASE_10000_LRM:
657 case AXGBE_SFP_BASE_10000_ER:
658 case AXGBE_SFP_BASE_10000_CR:
659 phy_data->sfp_speed = AXGBE_SFP_SPEED_10000;
666 static bool axgbe_phy_sfp_verify_eeprom(uint8_t cc_in, uint8_t *buf,
671 for (cc = 0; len; buf++, len--)
674 return (cc == cc_in) ? true : false;
677 static int axgbe_phy_sfp_read_eeprom(struct axgbe_port *pdata)
679 struct axgbe_phy_data *phy_data = pdata->phy_data;
680 struct axgbe_sfp_eeprom sfp_eeprom;
684 ret = axgbe_phy_sfp_get_mux(pdata);
686 PMD_DRV_LOG(ERR, "I2C error setting SFP MUX\n");
690 /* Read the SFP serial ID eeprom */
692 ret = axgbe_phy_i2c_read(pdata, AXGBE_SFP_SERIAL_ID_ADDRESS,
693 &eeprom_addr, sizeof(eeprom_addr),
694 &sfp_eeprom, sizeof(sfp_eeprom));
696 PMD_DRV_LOG(ERR, "I2C error reading SFP EEPROM\n");
700 /* Validate the contents read */
701 if (!axgbe_phy_sfp_verify_eeprom(sfp_eeprom.base[AXGBE_SFP_BASE_CC],
703 sizeof(sfp_eeprom.base) - 1)) {
708 if (!axgbe_phy_sfp_verify_eeprom(sfp_eeprom.extd[AXGBE_SFP_EXTD_CC],
710 sizeof(sfp_eeprom.extd) - 1)) {
715 /* Check for an added or changed SFP */
716 if (memcmp(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom))) {
717 phy_data->sfp_changed = 1;
718 memcpy(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom));
720 if (sfp_eeprom.extd[AXGBE_SFP_EXTD_SFF_8472]) {
722 diag_type = sfp_eeprom.extd[AXGBE_SFP_EXTD_DIAG];
724 if (!(diag_type & AXGBE_SFP_EXTD_DIAG_ADDR_CHANGE))
725 phy_data->sfp_diags = 1;
728 phy_data->sfp_changed = 0;
732 axgbe_phy_sfp_put_mux(pdata);
737 static void axgbe_phy_sfp_signals(struct axgbe_port *pdata)
739 struct axgbe_phy_data *phy_data = pdata->phy_data;
740 unsigned int gpio_input;
741 u8 gpio_reg, gpio_ports[2];
744 /* Read the input port registers */
746 ret = axgbe_phy_i2c_read(pdata, phy_data->sfp_gpio_address,
747 &gpio_reg, sizeof(gpio_reg),
748 gpio_ports, sizeof(gpio_ports));
750 PMD_DRV_LOG(ERR, "I2C error reading SFP GPIOs\n");
754 gpio_input = (gpio_ports[1] << 8) | gpio_ports[0];
756 if (phy_data->sfp_gpio_mask & AXGBE_GPIO_NO_MOD_ABSENT) {
757 /* No GPIO, just assume the module is present for now */
758 phy_data->sfp_mod_absent = 0;
760 if (!(gpio_input & (1 << phy_data->sfp_gpio_mod_absent)))
761 phy_data->sfp_mod_absent = 0;
764 if (!(phy_data->sfp_gpio_mask & AXGBE_GPIO_NO_RX_LOS) &&
765 (gpio_input & (1 << phy_data->sfp_gpio_rx_los)))
766 phy_data->sfp_rx_los = 1;
768 if (!(phy_data->sfp_gpio_mask & AXGBE_GPIO_NO_TX_FAULT) &&
769 (gpio_input & (1 << phy_data->sfp_gpio_tx_fault)))
770 phy_data->sfp_tx_fault = 1;
773 static void axgbe_phy_sfp_mod_absent(struct axgbe_port *pdata)
775 struct axgbe_phy_data *phy_data = pdata->phy_data;
777 phy_data->sfp_mod_absent = 1;
778 phy_data->sfp_phy_avail = 0;
779 memset(&phy_data->sfp_eeprom, 0, sizeof(phy_data->sfp_eeprom));
782 static void axgbe_phy_sfp_reset(struct axgbe_phy_data *phy_data)
784 phy_data->sfp_rx_los = 0;
785 phy_data->sfp_tx_fault = 0;
786 phy_data->sfp_mod_absent = 1;
787 phy_data->sfp_diags = 0;
788 phy_data->sfp_base = AXGBE_SFP_BASE_UNKNOWN;
789 phy_data->sfp_cable = AXGBE_SFP_CABLE_UNKNOWN;
790 phy_data->sfp_speed = AXGBE_SFP_SPEED_UNKNOWN;
793 static void axgbe_phy_sfp_detect(struct axgbe_port *pdata)
795 struct axgbe_phy_data *phy_data = pdata->phy_data;
798 /* Reset the SFP signals and info */
799 axgbe_phy_sfp_reset(phy_data);
801 ret = axgbe_phy_get_comm_ownership(pdata);
805 /* Read the SFP signals and check for module presence */
806 axgbe_phy_sfp_signals(pdata);
807 if (phy_data->sfp_mod_absent) {
808 axgbe_phy_sfp_mod_absent(pdata);
812 ret = axgbe_phy_sfp_read_eeprom(pdata);
814 /* Treat any error as if there isn't an SFP plugged in */
815 axgbe_phy_sfp_reset(phy_data);
816 axgbe_phy_sfp_mod_absent(pdata);
820 axgbe_phy_sfp_parse_eeprom(pdata);
821 axgbe_phy_sfp_external_phy(pdata);
824 axgbe_phy_sfp_phy_settings(pdata);
825 axgbe_phy_put_comm_ownership(pdata);
828 static void axgbe_phy_phydev_flowctrl(struct axgbe_port *pdata)
830 pdata->phy.tx_pause = 0;
831 pdata->phy.rx_pause = 0;
834 static enum axgbe_mode axgbe_phy_an73_redrv_outcome(struct axgbe_port *pdata)
836 struct axgbe_phy_data *phy_data = pdata->phy_data;
837 enum axgbe_mode mode;
838 unsigned int ad_reg, lp_reg;
840 pdata->phy.lp_advertising |= ADVERTISED_Autoneg;
841 pdata->phy.lp_advertising |= ADVERTISED_Backplane;
843 /* Use external PHY to determine flow control */
844 if (pdata->phy.pause_autoneg)
845 axgbe_phy_phydev_flowctrl(pdata);
847 /* Compare Advertisement and Link Partner register 2 */
848 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
849 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
851 pdata->phy.lp_advertising |= ADVERTISED_10000baseKR_Full;
853 pdata->phy.lp_advertising |= ADVERTISED_1000baseKX_Full;
857 switch (phy_data->port_mode) {
858 case AXGBE_PORT_MODE_BACKPLANE:
859 mode = AXGBE_MODE_KR;
862 mode = AXGBE_MODE_SFI;
865 } else if (ad_reg & 0x20) {
866 switch (phy_data->port_mode) {
867 case AXGBE_PORT_MODE_BACKPLANE:
868 mode = AXGBE_MODE_KX_1000;
870 case AXGBE_PORT_MODE_1000BASE_X:
873 case AXGBE_PORT_MODE_SFP:
874 switch (phy_data->sfp_base) {
875 case AXGBE_SFP_BASE_1000_T:
876 mode = AXGBE_MODE_SGMII_1000;
878 case AXGBE_SFP_BASE_1000_SX:
879 case AXGBE_SFP_BASE_1000_LX:
880 case AXGBE_SFP_BASE_1000_CX:
887 mode = AXGBE_MODE_SGMII_1000;
891 mode = AXGBE_MODE_UNKNOWN;
894 /* Compare Advertisement and Link Partner register 3 */
895 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
896 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
898 pdata->phy.lp_advertising |= ADVERTISED_10000baseR_FEC;
903 static enum axgbe_mode axgbe_phy_an73_outcome(struct axgbe_port *pdata)
905 enum axgbe_mode mode;
906 unsigned int ad_reg, lp_reg;
908 pdata->phy.lp_advertising |= ADVERTISED_Autoneg;
909 pdata->phy.lp_advertising |= ADVERTISED_Backplane;
911 /* Compare Advertisement and Link Partner register 1 */
912 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
913 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA);
915 pdata->phy.lp_advertising |= ADVERTISED_Pause;
917 pdata->phy.lp_advertising |= ADVERTISED_Asym_Pause;
919 if (pdata->phy.pause_autoneg) {
920 /* Set flow control based on auto-negotiation result */
921 pdata->phy.tx_pause = 0;
922 pdata->phy.rx_pause = 0;
924 if (ad_reg & lp_reg & 0x400) {
925 pdata->phy.tx_pause = 1;
926 pdata->phy.rx_pause = 1;
927 } else if (ad_reg & lp_reg & 0x800) {
929 pdata->phy.rx_pause = 1;
930 else if (lp_reg & 0x400)
931 pdata->phy.tx_pause = 1;
935 /* Compare Advertisement and Link Partner register 2 */
936 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
937 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
939 pdata->phy.lp_advertising |= ADVERTISED_10000baseKR_Full;
941 pdata->phy.lp_advertising |= ADVERTISED_1000baseKX_Full;
945 mode = AXGBE_MODE_KR;
946 else if (ad_reg & 0x20)
947 mode = AXGBE_MODE_KX_1000;
949 mode = AXGBE_MODE_UNKNOWN;
951 /* Compare Advertisement and Link Partner register 3 */
952 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
953 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
955 pdata->phy.lp_advertising |= ADVERTISED_10000baseR_FEC;
960 static enum axgbe_mode axgbe_phy_an37_sgmii_outcome(struct axgbe_port *pdata)
962 enum axgbe_mode mode;
964 pdata->phy.lp_advertising |= ADVERTISED_Autoneg;
965 pdata->phy.lp_advertising |= ADVERTISED_1000baseT_Full;
967 if (pdata->phy.pause_autoneg)
968 axgbe_phy_phydev_flowctrl(pdata);
970 switch (pdata->an_status & AXGBE_SGMII_AN_LINK_SPEED) {
971 case AXGBE_SGMII_AN_LINK_SPEED_100:
972 if (pdata->an_status & AXGBE_SGMII_AN_LINK_DUPLEX) {
973 pdata->phy.lp_advertising |= ADVERTISED_100baseT_Full;
974 mode = AXGBE_MODE_SGMII_100;
976 mode = AXGBE_MODE_UNKNOWN;
979 case AXGBE_SGMII_AN_LINK_SPEED_1000:
980 if (pdata->an_status & AXGBE_SGMII_AN_LINK_DUPLEX) {
981 pdata->phy.lp_advertising |= ADVERTISED_1000baseT_Full;
982 mode = AXGBE_MODE_SGMII_1000;
984 /* Half-duplex not supported */
985 mode = AXGBE_MODE_UNKNOWN;
989 mode = AXGBE_MODE_UNKNOWN;
995 static enum axgbe_mode axgbe_phy_an_outcome(struct axgbe_port *pdata)
997 switch (pdata->an_mode) {
998 case AXGBE_AN_MODE_CL73:
999 return axgbe_phy_an73_outcome(pdata);
1000 case AXGBE_AN_MODE_CL73_REDRV:
1001 return axgbe_phy_an73_redrv_outcome(pdata);
1002 case AXGBE_AN_MODE_CL37:
1003 case AXGBE_AN_MODE_CL37_SGMII:
1004 return axgbe_phy_an37_sgmii_outcome(pdata);
1006 return AXGBE_MODE_UNKNOWN;
1010 static unsigned int axgbe_phy_an_advertising(struct axgbe_port *pdata)
1012 struct axgbe_phy_data *phy_data = pdata->phy_data;
1013 unsigned int advertising;
1015 /* Without a re-driver, just return current advertising */
1016 if (!phy_data->redrv)
1017 return pdata->phy.advertising;
1019 /* With the KR re-driver we need to advertise a single speed */
1020 advertising = pdata->phy.advertising;
1021 advertising &= ~ADVERTISED_1000baseKX_Full;
1022 advertising &= ~ADVERTISED_10000baseKR_Full;
1024 switch (phy_data->port_mode) {
1025 case AXGBE_PORT_MODE_BACKPLANE:
1026 advertising |= ADVERTISED_10000baseKR_Full;
1028 case AXGBE_PORT_MODE_BACKPLANE_2500:
1029 advertising |= ADVERTISED_1000baseKX_Full;
1031 case AXGBE_PORT_MODE_1000BASE_T:
1032 case AXGBE_PORT_MODE_1000BASE_X:
1033 case AXGBE_PORT_MODE_NBASE_T:
1034 advertising |= ADVERTISED_1000baseKX_Full;
1036 case AXGBE_PORT_MODE_10GBASE_T:
1037 PMD_DRV_LOG(ERR, "10GBASE_T mode is not supported\n");
1039 case AXGBE_PORT_MODE_10GBASE_R:
1040 advertising |= ADVERTISED_10000baseKR_Full;
1042 case AXGBE_PORT_MODE_SFP:
1043 switch (phy_data->sfp_base) {
1044 case AXGBE_SFP_BASE_1000_T:
1045 case AXGBE_SFP_BASE_1000_SX:
1046 case AXGBE_SFP_BASE_1000_LX:
1047 case AXGBE_SFP_BASE_1000_CX:
1048 advertising |= ADVERTISED_1000baseKX_Full;
1051 advertising |= ADVERTISED_10000baseKR_Full;
1056 advertising |= ADVERTISED_10000baseKR_Full;
1063 static int axgbe_phy_an_config(struct axgbe_port *pdata __rte_unused)
1066 /* Dummy API since there is no case to support
1067 * external phy devices registred through kerenl apis
1071 static enum axgbe_an_mode axgbe_phy_an_sfp_mode(struct axgbe_phy_data *phy_data)
1073 switch (phy_data->sfp_base) {
1074 case AXGBE_SFP_BASE_1000_T:
1075 return AXGBE_AN_MODE_CL37_SGMII;
1076 case AXGBE_SFP_BASE_1000_SX:
1077 case AXGBE_SFP_BASE_1000_LX:
1078 case AXGBE_SFP_BASE_1000_CX:
1079 return AXGBE_AN_MODE_CL37;
1081 return AXGBE_AN_MODE_NONE;
1085 static enum axgbe_an_mode axgbe_phy_an_mode(struct axgbe_port *pdata)
1087 struct axgbe_phy_data *phy_data = pdata->phy_data;
1089 /* A KR re-driver will always require CL73 AN */
1090 if (phy_data->redrv)
1091 return AXGBE_AN_MODE_CL73_REDRV;
1093 switch (phy_data->port_mode) {
1094 case AXGBE_PORT_MODE_BACKPLANE:
1095 return AXGBE_AN_MODE_CL73;
1096 case AXGBE_PORT_MODE_BACKPLANE_2500:
1097 return AXGBE_AN_MODE_NONE;
1098 case AXGBE_PORT_MODE_1000BASE_T:
1099 return AXGBE_AN_MODE_CL37_SGMII;
1100 case AXGBE_PORT_MODE_1000BASE_X:
1101 return AXGBE_AN_MODE_CL37;
1102 case AXGBE_PORT_MODE_NBASE_T:
1103 return AXGBE_AN_MODE_CL37_SGMII;
1104 case AXGBE_PORT_MODE_10GBASE_T:
1105 return AXGBE_AN_MODE_CL73;
1106 case AXGBE_PORT_MODE_10GBASE_R:
1107 return AXGBE_AN_MODE_NONE;
1108 case AXGBE_PORT_MODE_SFP:
1109 return axgbe_phy_an_sfp_mode(phy_data);
1111 return AXGBE_AN_MODE_NONE;
1115 static int axgbe_phy_set_redrv_mode_mdio(struct axgbe_port *pdata,
1116 enum axgbe_phy_redrv_mode mode)
1118 struct axgbe_phy_data *phy_data = pdata->phy_data;
1119 u16 redrv_reg, redrv_val;
1121 redrv_reg = AXGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
1122 redrv_val = (u16)mode;
1124 return pdata->hw_if.write_ext_mii_regs(pdata, phy_data->redrv_addr,
1125 redrv_reg, redrv_val);
1128 static int axgbe_phy_set_redrv_mode_i2c(struct axgbe_port *pdata,
1129 enum axgbe_phy_redrv_mode mode)
1131 struct axgbe_phy_data *phy_data = pdata->phy_data;
1132 unsigned int redrv_reg;
1135 /* Calculate the register to write */
1136 redrv_reg = AXGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
1138 ret = axgbe_phy_redrv_write(pdata, redrv_reg, mode);
1143 static void axgbe_phy_set_redrv_mode(struct axgbe_port *pdata)
1145 struct axgbe_phy_data *phy_data = pdata->phy_data;
1146 enum axgbe_phy_redrv_mode mode;
1149 if (!phy_data->redrv)
1152 mode = AXGBE_PHY_REDRV_MODE_CX;
1153 if ((phy_data->port_mode == AXGBE_PORT_MODE_SFP) &&
1154 (phy_data->sfp_base != AXGBE_SFP_BASE_1000_CX) &&
1155 (phy_data->sfp_base != AXGBE_SFP_BASE_10000_CR))
1156 mode = AXGBE_PHY_REDRV_MODE_SR;
1158 ret = axgbe_phy_get_comm_ownership(pdata);
1162 if (phy_data->redrv_if)
1163 axgbe_phy_set_redrv_mode_i2c(pdata, mode);
1165 axgbe_phy_set_redrv_mode_mdio(pdata, mode);
1167 axgbe_phy_put_comm_ownership(pdata);
1170 static void axgbe_phy_start_ratechange(struct axgbe_port *pdata)
1172 if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
1176 static void axgbe_phy_complete_ratechange(struct axgbe_port *pdata)
1180 /* Wait for command to complete */
1181 wait = AXGBE_RATECHANGE_COUNT;
1183 if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
1190 static void axgbe_phy_rrc(struct axgbe_port *pdata)
1194 axgbe_phy_start_ratechange(pdata);
1196 /* Receiver Reset Cycle */
1198 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 5);
1199 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0);
1201 /* Call FW to make the change */
1202 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
1203 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
1204 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
1206 axgbe_phy_complete_ratechange(pdata);
1209 static void axgbe_phy_power_off(struct axgbe_port *pdata)
1211 struct axgbe_phy_data *phy_data = pdata->phy_data;
1213 axgbe_phy_start_ratechange(pdata);
1215 /* Call FW to make the change */
1216 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, 0);
1217 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
1218 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
1219 axgbe_phy_complete_ratechange(pdata);
1220 phy_data->cur_mode = AXGBE_MODE_UNKNOWN;
1223 static void axgbe_phy_sfi_mode(struct axgbe_port *pdata)
1225 struct axgbe_phy_data *phy_data = pdata->phy_data;
1228 axgbe_phy_set_redrv_mode(pdata);
1230 axgbe_phy_start_ratechange(pdata);
1234 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 3);
1235 if (phy_data->sfp_cable != AXGBE_SFP_CABLE_PASSIVE) {
1236 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0);
1238 if (phy_data->sfp_cable_len <= 1)
1239 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 1);
1240 else if (phy_data->sfp_cable_len <= 3)
1241 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 2);
1243 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 3);
1246 /* Call FW to make the change */
1247 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
1248 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
1249 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
1250 axgbe_phy_complete_ratechange(pdata);
1251 phy_data->cur_mode = AXGBE_MODE_SFI;
1254 static void axgbe_phy_kr_mode(struct axgbe_port *pdata)
1256 struct axgbe_phy_data *phy_data = pdata->phy_data;
1259 axgbe_phy_set_redrv_mode(pdata);
1261 axgbe_phy_start_ratechange(pdata);
1265 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 4);
1266 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0);
1268 /* Call FW to make the change */
1269 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
1270 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
1271 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
1272 axgbe_phy_complete_ratechange(pdata);
1273 phy_data->cur_mode = AXGBE_MODE_KR;
1276 static void axgbe_phy_kx_2500_mode(struct axgbe_port *pdata)
1278 struct axgbe_phy_data *phy_data = pdata->phy_data;
1281 axgbe_phy_set_redrv_mode(pdata);
1283 axgbe_phy_start_ratechange(pdata);
1285 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 2);
1286 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0);
1288 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
1289 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
1291 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
1293 phy_data->cur_mode = AXGBE_MODE_KX_2500;
1296 static void axgbe_phy_sgmii_1000_mode(struct axgbe_port *pdata)
1298 struct axgbe_phy_data *phy_data = pdata->phy_data;
1301 axgbe_phy_set_redrv_mode(pdata);
1304 axgbe_phy_start_ratechange(pdata);
1306 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 1);
1307 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 2);
1309 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
1310 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
1312 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
1314 phy_data->cur_mode = AXGBE_MODE_SGMII_1000;
1317 static enum axgbe_mode axgbe_phy_cur_mode(struct axgbe_port *pdata)
1319 struct axgbe_phy_data *phy_data = pdata->phy_data;
1321 return phy_data->cur_mode;
1324 static enum axgbe_mode axgbe_phy_switch_baset_mode(struct axgbe_port *pdata)
1326 struct axgbe_phy_data *phy_data = pdata->phy_data;
1328 /* No switching if not 10GBase-T */
1329 if (phy_data->port_mode != AXGBE_PORT_MODE_10GBASE_T)
1330 return axgbe_phy_cur_mode(pdata);
1332 switch (axgbe_phy_cur_mode(pdata)) {
1333 case AXGBE_MODE_SGMII_100:
1334 case AXGBE_MODE_SGMII_1000:
1335 return AXGBE_MODE_KR;
1338 return AXGBE_MODE_SGMII_1000;
1342 static enum axgbe_mode axgbe_phy_switch_bp_2500_mode(struct axgbe_port *pdata
1345 return AXGBE_MODE_KX_2500;
1348 static enum axgbe_mode axgbe_phy_switch_bp_mode(struct axgbe_port *pdata)
1350 /* If we are in KR switch to KX, and vice-versa */
1351 switch (axgbe_phy_cur_mode(pdata)) {
1352 case AXGBE_MODE_KX_1000:
1353 return AXGBE_MODE_KR;
1356 return AXGBE_MODE_KX_1000;
1360 static enum axgbe_mode axgbe_phy_switch_mode(struct axgbe_port *pdata)
1362 struct axgbe_phy_data *phy_data = pdata->phy_data;
1364 switch (phy_data->port_mode) {
1365 case AXGBE_PORT_MODE_BACKPLANE:
1366 return axgbe_phy_switch_bp_mode(pdata);
1367 case AXGBE_PORT_MODE_BACKPLANE_2500:
1368 return axgbe_phy_switch_bp_2500_mode(pdata);
1369 case AXGBE_PORT_MODE_1000BASE_T:
1370 case AXGBE_PORT_MODE_NBASE_T:
1371 case AXGBE_PORT_MODE_10GBASE_T:
1372 return axgbe_phy_switch_baset_mode(pdata);
1373 case AXGBE_PORT_MODE_1000BASE_X:
1374 case AXGBE_PORT_MODE_10GBASE_R:
1375 case AXGBE_PORT_MODE_SFP:
1376 /* No switching, so just return current mode */
1377 return axgbe_phy_cur_mode(pdata);
1379 return AXGBE_MODE_UNKNOWN;
1383 static enum axgbe_mode axgbe_phy_get_basex_mode(struct axgbe_phy_data *phy_data
1389 return AXGBE_MODE_X;
1391 return AXGBE_MODE_KR;
1393 return AXGBE_MODE_UNKNOWN;
1397 static enum axgbe_mode axgbe_phy_get_baset_mode(struct axgbe_phy_data *phy_data
1403 return AXGBE_MODE_SGMII_100;
1405 return AXGBE_MODE_SGMII_1000;
1407 return AXGBE_MODE_KR;
1409 return AXGBE_MODE_UNKNOWN;
1413 static enum axgbe_mode axgbe_phy_get_sfp_mode(struct axgbe_phy_data *phy_data,
1418 return AXGBE_MODE_SGMII_100;
1420 if (phy_data->sfp_base == AXGBE_SFP_BASE_1000_T)
1421 return AXGBE_MODE_SGMII_1000;
1423 return AXGBE_MODE_X;
1426 return AXGBE_MODE_SFI;
1428 return AXGBE_MODE_UNKNOWN;
1432 static enum axgbe_mode axgbe_phy_get_bp_2500_mode(int speed)
1436 return AXGBE_MODE_KX_2500;
1438 return AXGBE_MODE_UNKNOWN;
1442 static enum axgbe_mode axgbe_phy_get_bp_mode(int speed)
1446 return AXGBE_MODE_KX_1000;
1448 return AXGBE_MODE_KR;
1450 return AXGBE_MODE_UNKNOWN;
1454 static enum axgbe_mode axgbe_phy_get_mode(struct axgbe_port *pdata,
1457 struct axgbe_phy_data *phy_data = pdata->phy_data;
1459 switch (phy_data->port_mode) {
1460 case AXGBE_PORT_MODE_BACKPLANE:
1461 return axgbe_phy_get_bp_mode(speed);
1462 case AXGBE_PORT_MODE_BACKPLANE_2500:
1463 return axgbe_phy_get_bp_2500_mode(speed);
1464 case AXGBE_PORT_MODE_1000BASE_T:
1465 case AXGBE_PORT_MODE_NBASE_T:
1466 case AXGBE_PORT_MODE_10GBASE_T:
1467 return axgbe_phy_get_baset_mode(phy_data, speed);
1468 case AXGBE_PORT_MODE_1000BASE_X:
1469 case AXGBE_PORT_MODE_10GBASE_R:
1470 return axgbe_phy_get_basex_mode(phy_data, speed);
1471 case AXGBE_PORT_MODE_SFP:
1472 return axgbe_phy_get_sfp_mode(phy_data, speed);
1474 return AXGBE_MODE_UNKNOWN;
1478 static void axgbe_phy_set_mode(struct axgbe_port *pdata, enum axgbe_mode mode)
1482 axgbe_phy_kr_mode(pdata);
1484 case AXGBE_MODE_SFI:
1485 axgbe_phy_sfi_mode(pdata);
1487 case AXGBE_MODE_KX_2500:
1488 axgbe_phy_kx_2500_mode(pdata);
1490 case AXGBE_MODE_SGMII_1000:
1491 axgbe_phy_sgmii_1000_mode(pdata);
1498 static bool axgbe_phy_check_mode(struct axgbe_port *pdata,
1499 enum axgbe_mode mode, u32 advert)
1501 if (pdata->phy.autoneg == AUTONEG_ENABLE) {
1502 if (pdata->phy.advertising & advert)
1505 enum axgbe_mode cur_mode;
1507 cur_mode = axgbe_phy_get_mode(pdata, pdata->phy.speed);
1508 if (cur_mode == mode)
1515 static bool axgbe_phy_use_basex_mode(struct axgbe_port *pdata,
1516 enum axgbe_mode mode)
1520 return axgbe_phy_check_mode(pdata, mode,
1521 ADVERTISED_1000baseT_Full);
1523 return axgbe_phy_check_mode(pdata, mode,
1524 ADVERTISED_10000baseT_Full);
1530 static bool axgbe_phy_use_baset_mode(struct axgbe_port *pdata,
1531 enum axgbe_mode mode)
1534 case AXGBE_MODE_SGMII_100:
1535 return axgbe_phy_check_mode(pdata, mode,
1536 ADVERTISED_100baseT_Full);
1537 case AXGBE_MODE_SGMII_1000:
1538 return axgbe_phy_check_mode(pdata, mode,
1539 ADVERTISED_1000baseT_Full);
1541 return axgbe_phy_check_mode(pdata, mode,
1542 ADVERTISED_10000baseT_Full);
1548 static bool axgbe_phy_use_sfp_mode(struct axgbe_port *pdata,
1549 enum axgbe_mode mode)
1551 struct axgbe_phy_data *phy_data = pdata->phy_data;
1555 if (phy_data->sfp_base == AXGBE_SFP_BASE_1000_T)
1557 return axgbe_phy_check_mode(pdata, mode,
1558 ADVERTISED_1000baseT_Full);
1559 case AXGBE_MODE_SGMII_100:
1560 if (phy_data->sfp_base != AXGBE_SFP_BASE_1000_T)
1562 return axgbe_phy_check_mode(pdata, mode,
1563 ADVERTISED_100baseT_Full);
1564 case AXGBE_MODE_SGMII_1000:
1565 if (phy_data->sfp_base != AXGBE_SFP_BASE_1000_T)
1567 return axgbe_phy_check_mode(pdata, mode,
1568 ADVERTISED_1000baseT_Full);
1569 case AXGBE_MODE_SFI:
1570 return axgbe_phy_check_mode(pdata, mode,
1571 ADVERTISED_10000baseT_Full);
1577 static bool axgbe_phy_use_bp_2500_mode(struct axgbe_port *pdata,
1578 enum axgbe_mode mode)
1581 case AXGBE_MODE_KX_2500:
1582 return axgbe_phy_check_mode(pdata, mode,
1583 ADVERTISED_2500baseX_Full);
1589 static bool axgbe_phy_use_bp_mode(struct axgbe_port *pdata,
1590 enum axgbe_mode mode)
1593 case AXGBE_MODE_KX_1000:
1594 return axgbe_phy_check_mode(pdata, mode,
1595 ADVERTISED_1000baseKX_Full);
1597 return axgbe_phy_check_mode(pdata, mode,
1598 ADVERTISED_10000baseKR_Full);
1604 static bool axgbe_phy_use_mode(struct axgbe_port *pdata, enum axgbe_mode mode)
1606 struct axgbe_phy_data *phy_data = pdata->phy_data;
1608 switch (phy_data->port_mode) {
1609 case AXGBE_PORT_MODE_BACKPLANE:
1610 return axgbe_phy_use_bp_mode(pdata, mode);
1611 case AXGBE_PORT_MODE_BACKPLANE_2500:
1612 return axgbe_phy_use_bp_2500_mode(pdata, mode);
1613 case AXGBE_PORT_MODE_1000BASE_T:
1614 case AXGBE_PORT_MODE_NBASE_T:
1615 case AXGBE_PORT_MODE_10GBASE_T:
1616 return axgbe_phy_use_baset_mode(pdata, mode);
1617 case AXGBE_PORT_MODE_1000BASE_X:
1618 case AXGBE_PORT_MODE_10GBASE_R:
1619 return axgbe_phy_use_basex_mode(pdata, mode);
1620 case AXGBE_PORT_MODE_SFP:
1621 return axgbe_phy_use_sfp_mode(pdata, mode);
1627 static int axgbe_phy_link_status(struct axgbe_port *pdata, int *an_restart)
1629 struct axgbe_phy_data *phy_data = pdata->phy_data;
1634 if (phy_data->port_mode == AXGBE_PORT_MODE_SFP) {
1635 /* Check SFP signals */
1636 axgbe_phy_sfp_detect(pdata);
1638 if (phy_data->sfp_changed) {
1643 if (phy_data->sfp_mod_absent || phy_data->sfp_rx_los)
1647 /* Link status is latched low, so read once to clear
1648 * and then read again to get current state
1650 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
1651 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
1652 if (reg & MDIO_STAT1_LSTATUS)
1655 /* No link, attempt a receiver reset cycle */
1656 if (phy_data->rrc_count++) {
1657 phy_data->rrc_count = 0;
1658 axgbe_phy_rrc(pdata);
1664 static void axgbe_phy_sfp_gpio_setup(struct axgbe_port *pdata)
1666 struct axgbe_phy_data *phy_data = pdata->phy_data;
1669 reg = XP_IOREAD(pdata, XP_PROP_3);
1671 phy_data->sfp_gpio_address = AXGBE_GPIO_ADDRESS_PCA9555 +
1672 XP_GET_BITS(reg, XP_PROP_3, GPIO_ADDR);
1674 phy_data->sfp_gpio_mask = XP_GET_BITS(reg, XP_PROP_3, GPIO_MASK);
1676 phy_data->sfp_gpio_rx_los = XP_GET_BITS(reg, XP_PROP_3,
1678 phy_data->sfp_gpio_tx_fault = XP_GET_BITS(reg, XP_PROP_3,
1680 phy_data->sfp_gpio_mod_absent = XP_GET_BITS(reg, XP_PROP_3,
1682 phy_data->sfp_gpio_rate_select = XP_GET_BITS(reg, XP_PROP_3,
1686 static void axgbe_phy_sfp_comm_setup(struct axgbe_port *pdata)
1688 struct axgbe_phy_data *phy_data = pdata->phy_data;
1689 unsigned int reg, mux_addr_hi, mux_addr_lo;
1691 reg = XP_IOREAD(pdata, XP_PROP_4);
1693 mux_addr_hi = XP_GET_BITS(reg, XP_PROP_4, MUX_ADDR_HI);
1694 mux_addr_lo = XP_GET_BITS(reg, XP_PROP_4, MUX_ADDR_LO);
1695 if (mux_addr_lo == AXGBE_SFP_DIRECT)
1698 phy_data->sfp_comm = AXGBE_SFP_COMM_PCA9545;
1699 phy_data->sfp_mux_address = (mux_addr_hi << 2) + mux_addr_lo;
1700 phy_data->sfp_mux_channel = XP_GET_BITS(reg, XP_PROP_4, MUX_CHAN);
1703 static void axgbe_phy_sfp_setup(struct axgbe_port *pdata)
1705 axgbe_phy_sfp_comm_setup(pdata);
1706 axgbe_phy_sfp_gpio_setup(pdata);
1709 static bool axgbe_phy_redrv_error(struct axgbe_phy_data *phy_data)
1711 if (!phy_data->redrv)
1714 if (phy_data->redrv_if >= AXGBE_PHY_REDRV_IF_MAX)
1717 switch (phy_data->redrv_model) {
1718 case AXGBE_PHY_REDRV_MODEL_4223:
1719 if (phy_data->redrv_lane > 3)
1722 case AXGBE_PHY_REDRV_MODEL_4227:
1723 if (phy_data->redrv_lane > 1)
1733 static int axgbe_phy_mdio_reset_setup(struct axgbe_port *pdata)
1735 struct axgbe_phy_data *phy_data = pdata->phy_data;
1738 if (phy_data->conn_type != AXGBE_CONN_TYPE_MDIO)
1740 reg = XP_IOREAD(pdata, XP_PROP_3);
1741 phy_data->mdio_reset = XP_GET_BITS(reg, XP_PROP_3, MDIO_RESET);
1742 switch (phy_data->mdio_reset) {
1743 case AXGBE_MDIO_RESET_NONE:
1744 case AXGBE_MDIO_RESET_I2C_GPIO:
1745 case AXGBE_MDIO_RESET_INT_GPIO:
1748 PMD_DRV_LOG(ERR, "unsupported MDIO reset (%#x)\n",
1749 phy_data->mdio_reset);
1752 if (phy_data->mdio_reset == AXGBE_MDIO_RESET_I2C_GPIO) {
1753 phy_data->mdio_reset_addr = AXGBE_GPIO_ADDRESS_PCA9555 +
1754 XP_GET_BITS(reg, XP_PROP_3,
1755 MDIO_RESET_I2C_ADDR);
1756 phy_data->mdio_reset_gpio = XP_GET_BITS(reg, XP_PROP_3,
1757 MDIO_RESET_I2C_GPIO);
1758 } else if (phy_data->mdio_reset == AXGBE_MDIO_RESET_INT_GPIO) {
1759 phy_data->mdio_reset_gpio = XP_GET_BITS(reg, XP_PROP_3,
1760 MDIO_RESET_INT_GPIO);
1766 static bool axgbe_phy_port_mode_mismatch(struct axgbe_port *pdata)
1768 struct axgbe_phy_data *phy_data = pdata->phy_data;
1770 switch (phy_data->port_mode) {
1771 case AXGBE_PORT_MODE_BACKPLANE:
1772 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) ||
1773 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000))
1776 case AXGBE_PORT_MODE_BACKPLANE_2500:
1777 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_2500)
1780 case AXGBE_PORT_MODE_1000BASE_T:
1781 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) ||
1782 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000))
1785 case AXGBE_PORT_MODE_1000BASE_X:
1786 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000)
1789 case AXGBE_PORT_MODE_NBASE_T:
1790 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) ||
1791 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) ||
1792 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_2500))
1795 case AXGBE_PORT_MODE_10GBASE_T:
1796 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) ||
1797 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) ||
1798 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000))
1801 case AXGBE_PORT_MODE_10GBASE_R:
1802 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000)
1805 case AXGBE_PORT_MODE_SFP:
1806 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) ||
1807 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) ||
1808 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000))
1818 static bool axgbe_phy_conn_type_mismatch(struct axgbe_port *pdata)
1820 struct axgbe_phy_data *phy_data = pdata->phy_data;
1822 switch (phy_data->port_mode) {
1823 case AXGBE_PORT_MODE_BACKPLANE:
1824 case AXGBE_PORT_MODE_BACKPLANE_2500:
1825 if (phy_data->conn_type == AXGBE_CONN_TYPE_BACKPLANE)
1828 case AXGBE_PORT_MODE_1000BASE_T:
1829 case AXGBE_PORT_MODE_1000BASE_X:
1830 case AXGBE_PORT_MODE_NBASE_T:
1831 case AXGBE_PORT_MODE_10GBASE_T:
1832 case AXGBE_PORT_MODE_10GBASE_R:
1833 if (phy_data->conn_type == AXGBE_CONN_TYPE_MDIO)
1836 case AXGBE_PORT_MODE_SFP:
1837 if (phy_data->conn_type == AXGBE_CONN_TYPE_SFP)
1847 static bool axgbe_phy_port_enabled(struct axgbe_port *pdata)
1851 reg = XP_IOREAD(pdata, XP_PROP_0);
1852 if (!XP_GET_BITS(reg, XP_PROP_0, PORT_SPEEDS))
1854 if (!XP_GET_BITS(reg, XP_PROP_0, CONN_TYPE))
1860 static void axgbe_phy_cdr_track(struct axgbe_port *pdata)
1862 struct axgbe_phy_data *phy_data = pdata->phy_data;
1864 if (!pdata->vdata->an_cdr_workaround)
1867 if (!phy_data->phy_cdr_notrack)
1870 rte_delay_us(phy_data->phy_cdr_delay + 400);
1872 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL,
1873 AXGBE_PMA_CDR_TRACK_EN_MASK,
1874 AXGBE_PMA_CDR_TRACK_EN_ON);
1876 phy_data->phy_cdr_notrack = 0;
1879 static void axgbe_phy_cdr_notrack(struct axgbe_port *pdata)
1881 struct axgbe_phy_data *phy_data = pdata->phy_data;
1883 if (!pdata->vdata->an_cdr_workaround)
1886 if (phy_data->phy_cdr_notrack)
1889 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL,
1890 AXGBE_PMA_CDR_TRACK_EN_MASK,
1891 AXGBE_PMA_CDR_TRACK_EN_OFF);
1893 axgbe_phy_rrc(pdata);
1895 phy_data->phy_cdr_notrack = 1;
1898 static void axgbe_phy_kr_training_post(struct axgbe_port *pdata)
1900 if (!pdata->cdr_track_early)
1901 axgbe_phy_cdr_track(pdata);
1904 static void axgbe_phy_kr_training_pre(struct axgbe_port *pdata)
1906 if (pdata->cdr_track_early)
1907 axgbe_phy_cdr_track(pdata);
1910 static void axgbe_phy_an_post(struct axgbe_port *pdata)
1912 struct axgbe_phy_data *phy_data = pdata->phy_data;
1914 switch (pdata->an_mode) {
1915 case AXGBE_AN_MODE_CL73:
1916 case AXGBE_AN_MODE_CL73_REDRV:
1917 if (phy_data->cur_mode != AXGBE_MODE_KR)
1920 axgbe_phy_cdr_track(pdata);
1922 switch (pdata->an_result) {
1923 case AXGBE_AN_READY:
1924 case AXGBE_AN_COMPLETE:
1927 if (phy_data->phy_cdr_delay < AXGBE_CDR_DELAY_MAX)
1928 phy_data->phy_cdr_delay += AXGBE_CDR_DELAY_INC;
1937 static void axgbe_phy_an_pre(struct axgbe_port *pdata)
1939 struct axgbe_phy_data *phy_data = pdata->phy_data;
1941 switch (pdata->an_mode) {
1942 case AXGBE_AN_MODE_CL73:
1943 case AXGBE_AN_MODE_CL73_REDRV:
1944 if (phy_data->cur_mode != AXGBE_MODE_KR)
1947 axgbe_phy_cdr_notrack(pdata);
1954 static void axgbe_phy_stop(struct axgbe_port *pdata)
1956 struct axgbe_phy_data *phy_data = pdata->phy_data;
1958 /* Reset SFP data */
1959 axgbe_phy_sfp_reset(phy_data);
1960 axgbe_phy_sfp_mod_absent(pdata);
1962 /* Reset CDR support */
1963 axgbe_phy_cdr_track(pdata);
1965 /* Power off the PHY */
1966 axgbe_phy_power_off(pdata);
1968 /* Stop the I2C controller */
1969 pdata->i2c_if.i2c_stop(pdata);
1972 static int axgbe_phy_start(struct axgbe_port *pdata)
1974 struct axgbe_phy_data *phy_data = pdata->phy_data;
1977 /* Start the I2C controller */
1978 ret = pdata->i2c_if.i2c_start(pdata);
1982 /* Start in highest supported mode */
1983 axgbe_phy_set_mode(pdata, phy_data->start_mode);
1985 /* Reset CDR support */
1986 axgbe_phy_cdr_track(pdata);
1988 /* After starting the I2C controller, we can check for an SFP */
1989 switch (phy_data->port_mode) {
1990 case AXGBE_PORT_MODE_SFP:
1991 axgbe_phy_sfp_detect(pdata);
1996 pdata->phy.advertising &= axgbe_phy_an_advertising(pdata);
2001 static int axgbe_phy_reset(struct axgbe_port *pdata)
2003 struct axgbe_phy_data *phy_data = pdata->phy_data;
2004 enum axgbe_mode cur_mode;
2006 /* Reset by power cycling the PHY */
2007 cur_mode = phy_data->cur_mode;
2008 axgbe_phy_power_off(pdata);
2009 /* First time reset is done with passed unknown mode*/
2010 axgbe_phy_set_mode(pdata, cur_mode);
2014 static int axgbe_phy_init(struct axgbe_port *pdata)
2016 struct axgbe_phy_data *phy_data;
2020 /* Check if enabled */
2021 if (!axgbe_phy_port_enabled(pdata)) {
2022 PMD_DRV_LOG(ERR, "device is not enabled\n");
2026 /* Initialize the I2C controller */
2027 ret = pdata->i2c_if.i2c_init(pdata);
2031 phy_data = rte_zmalloc("phy_data memory", sizeof(*phy_data), 0);
2033 PMD_DRV_LOG(ERR, "phy_data allocation failed\n");
2036 pdata->phy_data = phy_data;
2038 reg = XP_IOREAD(pdata, XP_PROP_0);
2039 phy_data->port_mode = XP_GET_BITS(reg, XP_PROP_0, PORT_MODE);
2040 phy_data->port_id = XP_GET_BITS(reg, XP_PROP_0, PORT_ID);
2041 phy_data->port_speeds = XP_GET_BITS(reg, XP_PROP_0, PORT_SPEEDS);
2042 phy_data->conn_type = XP_GET_BITS(reg, XP_PROP_0, CONN_TYPE);
2043 phy_data->mdio_addr = XP_GET_BITS(reg, XP_PROP_0, MDIO_ADDR);
2045 reg = XP_IOREAD(pdata, XP_PROP_4);
2046 phy_data->redrv = XP_GET_BITS(reg, XP_PROP_4, REDRV_PRESENT);
2047 phy_data->redrv_if = XP_GET_BITS(reg, XP_PROP_4, REDRV_IF);
2048 phy_data->redrv_addr = XP_GET_BITS(reg, XP_PROP_4, REDRV_ADDR);
2049 phy_data->redrv_lane = XP_GET_BITS(reg, XP_PROP_4, REDRV_LANE);
2050 phy_data->redrv_model = XP_GET_BITS(reg, XP_PROP_4, REDRV_MODEL);
2052 /* Validate the connection requested */
2053 if (axgbe_phy_conn_type_mismatch(pdata)) {
2054 PMD_DRV_LOG(ERR, "phy mode/connection mismatch (%#x/%#x)\n",
2055 phy_data->port_mode, phy_data->conn_type);
2059 /* Validate the mode requested */
2060 if (axgbe_phy_port_mode_mismatch(pdata)) {
2061 PMD_DRV_LOG(ERR, "phy mode/speed mismatch (%#x/%#x)\n",
2062 phy_data->port_mode, phy_data->port_speeds);
2066 /* Check for and validate MDIO reset support */
2067 ret = axgbe_phy_mdio_reset_setup(pdata);
2071 /* Validate the re-driver information */
2072 if (axgbe_phy_redrv_error(phy_data)) {
2073 PMD_DRV_LOG(ERR, "phy re-driver settings error\n");
2076 pdata->kr_redrv = phy_data->redrv;
2078 /* Indicate current mode is unknown */
2079 phy_data->cur_mode = AXGBE_MODE_UNKNOWN;
2081 /* Initialize supported features */
2082 pdata->phy.supported = 0;
2084 switch (phy_data->port_mode) {
2085 /* Backplane support */
2086 case AXGBE_PORT_MODE_BACKPLANE:
2087 pdata->phy.supported |= SUPPORTED_Autoneg;
2088 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2089 pdata->phy.supported |= SUPPORTED_Backplane;
2090 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) {
2091 pdata->phy.supported |= SUPPORTED_1000baseKX_Full;
2092 phy_data->start_mode = AXGBE_MODE_KX_1000;
2094 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) {
2095 pdata->phy.supported |= SUPPORTED_10000baseKR_Full;
2096 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
2097 pdata->phy.supported |=
2098 SUPPORTED_10000baseR_FEC;
2099 phy_data->start_mode = AXGBE_MODE_KR;
2102 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE;
2104 case AXGBE_PORT_MODE_BACKPLANE_2500:
2105 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2106 pdata->phy.supported |= SUPPORTED_Backplane;
2107 pdata->phy.supported |= SUPPORTED_2500baseX_Full;
2108 phy_data->start_mode = AXGBE_MODE_KX_2500;
2110 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE;
2113 /* MDIO 1GBase-T support */
2114 case AXGBE_PORT_MODE_1000BASE_T:
2115 pdata->phy.supported |= SUPPORTED_Autoneg;
2116 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2117 pdata->phy.supported |= SUPPORTED_TP;
2118 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) {
2119 pdata->phy.supported |= SUPPORTED_100baseT_Full;
2120 phy_data->start_mode = AXGBE_MODE_SGMII_100;
2122 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) {
2123 pdata->phy.supported |= SUPPORTED_1000baseT_Full;
2124 phy_data->start_mode = AXGBE_MODE_SGMII_1000;
2127 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL22;
2130 /* MDIO Base-X support */
2131 case AXGBE_PORT_MODE_1000BASE_X:
2132 pdata->phy.supported |= SUPPORTED_Autoneg;
2133 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2134 pdata->phy.supported |= SUPPORTED_FIBRE;
2135 pdata->phy.supported |= SUPPORTED_1000baseT_Full;
2136 phy_data->start_mode = AXGBE_MODE_X;
2138 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL22;
2141 /* MDIO NBase-T support */
2142 case AXGBE_PORT_MODE_NBASE_T:
2143 pdata->phy.supported |= SUPPORTED_Autoneg;
2144 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2145 pdata->phy.supported |= SUPPORTED_TP;
2146 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) {
2147 pdata->phy.supported |= SUPPORTED_100baseT_Full;
2148 phy_data->start_mode = AXGBE_MODE_SGMII_100;
2150 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) {
2151 pdata->phy.supported |= SUPPORTED_1000baseT_Full;
2152 phy_data->start_mode = AXGBE_MODE_SGMII_1000;
2154 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_2500) {
2155 pdata->phy.supported |= SUPPORTED_2500baseX_Full;
2156 phy_data->start_mode = AXGBE_MODE_KX_2500;
2159 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL45;
2162 /* 10GBase-T support */
2163 case AXGBE_PORT_MODE_10GBASE_T:
2164 pdata->phy.supported |= SUPPORTED_Autoneg;
2165 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2166 pdata->phy.supported |= SUPPORTED_TP;
2167 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) {
2168 pdata->phy.supported |= SUPPORTED_100baseT_Full;
2169 phy_data->start_mode = AXGBE_MODE_SGMII_100;
2171 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) {
2172 pdata->phy.supported |= SUPPORTED_1000baseT_Full;
2173 phy_data->start_mode = AXGBE_MODE_SGMII_1000;
2175 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) {
2176 pdata->phy.supported |= SUPPORTED_10000baseT_Full;
2177 phy_data->start_mode = AXGBE_MODE_KR;
2180 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE;
2183 /* 10GBase-R support */
2184 case AXGBE_PORT_MODE_10GBASE_R:
2185 pdata->phy.supported |= SUPPORTED_Autoneg;
2186 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2187 pdata->phy.supported |= SUPPORTED_TP;
2188 pdata->phy.supported |= SUPPORTED_10000baseT_Full;
2189 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
2190 pdata->phy.supported |= SUPPORTED_10000baseR_FEC;
2191 phy_data->start_mode = AXGBE_MODE_SFI;
2193 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE;
2197 case AXGBE_PORT_MODE_SFP:
2198 pdata->phy.supported |= SUPPORTED_Autoneg;
2199 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2200 pdata->phy.supported |= SUPPORTED_TP;
2201 pdata->phy.supported |= SUPPORTED_FIBRE;
2202 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) {
2203 pdata->phy.supported |= SUPPORTED_100baseT_Full;
2204 phy_data->start_mode = AXGBE_MODE_SGMII_100;
2206 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) {
2207 pdata->phy.supported |= SUPPORTED_1000baseT_Full;
2208 phy_data->start_mode = AXGBE_MODE_SGMII_1000;
2210 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) {
2211 pdata->phy.supported |= SUPPORTED_10000baseT_Full;
2212 phy_data->start_mode = AXGBE_MODE_SFI;
2213 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
2214 pdata->phy.supported |=
2215 SUPPORTED_10000baseR_FEC;
2218 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL22;
2220 axgbe_phy_sfp_setup(pdata);
2226 if ((phy_data->conn_type & AXGBE_CONN_TYPE_MDIO) &&
2227 (phy_data->phydev_mode != AXGBE_MDIO_MODE_NONE)) {
2228 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr,
2229 phy_data->phydev_mode);
2231 PMD_DRV_LOG(ERR, "mdio port/clause not compatible (%d/%u)\n",
2232 phy_data->mdio_addr, phy_data->phydev_mode);
2237 if (phy_data->redrv && !phy_data->redrv_if) {
2238 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr,
2239 AXGBE_MDIO_MODE_CL22);
2241 PMD_DRV_LOG(ERR, "redriver mdio port not compatible (%u)\n",
2242 phy_data->redrv_addr);
2247 phy_data->phy_cdr_delay = AXGBE_CDR_DELAY_INIT;
2250 void axgbe_init_function_ptrs_phy_v2(struct axgbe_phy_if *phy_if)
2252 struct axgbe_phy_impl_if *phy_impl = &phy_if->phy_impl;
2254 phy_impl->init = axgbe_phy_init;
2255 phy_impl->reset = axgbe_phy_reset;
2256 phy_impl->start = axgbe_phy_start;
2257 phy_impl->stop = axgbe_phy_stop;
2258 phy_impl->link_status = axgbe_phy_link_status;
2259 phy_impl->use_mode = axgbe_phy_use_mode;
2260 phy_impl->set_mode = axgbe_phy_set_mode;
2261 phy_impl->get_mode = axgbe_phy_get_mode;
2262 phy_impl->switch_mode = axgbe_phy_switch_mode;
2263 phy_impl->cur_mode = axgbe_phy_cur_mode;
2264 phy_impl->an_mode = axgbe_phy_an_mode;
2265 phy_impl->an_config = axgbe_phy_an_config;
2266 phy_impl->an_advertising = axgbe_phy_an_advertising;
2267 phy_impl->an_outcome = axgbe_phy_an_outcome;
2269 phy_impl->an_pre = axgbe_phy_an_pre;
2270 phy_impl->an_post = axgbe_phy_an_post;
2272 phy_impl->kr_training_pre = axgbe_phy_kr_training_pre;
2273 phy_impl->kr_training_post = axgbe_phy_kr_training_post;