1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved.
3 * Copyright(c) 2018 Synopsys, Inc. All rights reserved.
6 #include "axgbe_ethdev.h"
7 #include "axgbe_common.h"
10 #define AXGBE_PHY_PORT_SPEED_100 BIT(1)
11 #define AXGBE_PHY_PORT_SPEED_1000 BIT(2)
12 #define AXGBE_PHY_PORT_SPEED_2500 BIT(3)
13 #define AXGBE_PHY_PORT_SPEED_10000 BIT(4)
15 #define AXGBE_MUTEX_RELEASE 0x80000000
17 #define AXGBE_SFP_DIRECT 7
19 /* I2C target addresses */
20 #define AXGBE_SFP_SERIAL_ID_ADDRESS 0x50
21 #define AXGBE_SFP_DIAG_INFO_ADDRESS 0x51
22 #define AXGBE_SFP_PHY_ADDRESS 0x56
23 #define AXGBE_GPIO_ADDRESS_PCA9555 0x20
25 /* SFP sideband signal indicators */
26 #define AXGBE_GPIO_NO_TX_FAULT BIT(0)
27 #define AXGBE_GPIO_NO_RATE_SELECT BIT(1)
28 #define AXGBE_GPIO_NO_MOD_ABSENT BIT(2)
29 #define AXGBE_GPIO_NO_RX_LOS BIT(3)
31 /* Rate-change complete wait/retry count */
32 #define AXGBE_RATECHANGE_COUNT 500
34 /* CDR delay values for KR support (in usec) */
35 #define AXGBE_CDR_DELAY_INIT 10000
36 #define AXGBE_CDR_DELAY_INC 10000
37 #define AXGBE_CDR_DELAY_MAX 100000
39 enum axgbe_port_mode {
40 AXGBE_PORT_MODE_RSVD = 0,
41 AXGBE_PORT_MODE_BACKPLANE,
42 AXGBE_PORT_MODE_BACKPLANE_2500,
43 AXGBE_PORT_MODE_1000BASE_T,
44 AXGBE_PORT_MODE_1000BASE_X,
45 AXGBE_PORT_MODE_NBASE_T,
46 AXGBE_PORT_MODE_10GBASE_T,
47 AXGBE_PORT_MODE_10GBASE_R,
49 AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG,
53 enum axgbe_conn_type {
54 AXGBE_CONN_TYPE_NONE = 0,
57 AXGBE_CONN_TYPE_RSVD1,
58 AXGBE_CONN_TYPE_BACKPLANE,
62 /* SFP/SFP+ related definitions */
64 AXGBE_SFP_COMM_DIRECT = 0,
65 AXGBE_SFP_COMM_PCA9545,
68 enum axgbe_sfp_cable {
69 AXGBE_SFP_CABLE_UNKNOWN = 0,
70 AXGBE_SFP_CABLE_ACTIVE,
71 AXGBE_SFP_CABLE_PASSIVE,
75 AXGBE_SFP_BASE_UNKNOWN = 0,
76 AXGBE_SFP_BASE_1000_T,
77 AXGBE_SFP_BASE_1000_SX,
78 AXGBE_SFP_BASE_1000_LX,
79 AXGBE_SFP_BASE_1000_CX,
80 AXGBE_SFP_BASE_10000_SR,
81 AXGBE_SFP_BASE_10000_LR,
82 AXGBE_SFP_BASE_10000_LRM,
83 AXGBE_SFP_BASE_10000_ER,
84 AXGBE_SFP_BASE_10000_CR,
87 enum axgbe_sfp_speed {
88 AXGBE_SFP_SPEED_UNKNOWN = 0,
89 AXGBE_SFP_SPEED_100_1000,
91 AXGBE_SFP_SPEED_10000,
94 /* SFP Serial ID Base ID values relative to an offset of 0 */
95 #define AXGBE_SFP_BASE_ID 0
96 #define AXGBE_SFP_ID_SFP 0x03
98 #define AXGBE_SFP_BASE_EXT_ID 1
99 #define AXGBE_SFP_EXT_ID_SFP 0x04
101 #define AXGBE_SFP_BASE_10GBE_CC 3
102 #define AXGBE_SFP_BASE_10GBE_CC_SR BIT(4)
103 #define AXGBE_SFP_BASE_10GBE_CC_LR BIT(5)
104 #define AXGBE_SFP_BASE_10GBE_CC_LRM BIT(6)
105 #define AXGBE_SFP_BASE_10GBE_CC_ER BIT(7)
107 #define AXGBE_SFP_BASE_1GBE_CC 6
108 #define AXGBE_SFP_BASE_1GBE_CC_SX BIT(0)
109 #define AXGBE_SFP_BASE_1GBE_CC_LX BIT(1)
110 #define AXGBE_SFP_BASE_1GBE_CC_CX BIT(2)
111 #define AXGBE_SFP_BASE_1GBE_CC_T BIT(3)
113 #define AXGBE_SFP_BASE_CABLE 8
114 #define AXGBE_SFP_BASE_CABLE_PASSIVE BIT(2)
115 #define AXGBE_SFP_BASE_CABLE_ACTIVE BIT(3)
117 #define AXGBE_SFP_BASE_BR 12
118 #define AXGBE_SFP_BASE_BR_1GBE_MIN 0x0a
119 #define AXGBE_SFP_BASE_BR_1GBE_MAX 0x0d
120 #define AXGBE_SFP_BASE_BR_10GBE_MIN 0x64
121 #define AXGBE_SFP_BASE_BR_10GBE_MAX 0x68
123 #define AXGBE_SFP_BASE_CU_CABLE_LEN 18
125 #define AXGBE_SFP_BASE_VENDOR_NAME 20
126 #define AXGBE_SFP_BASE_VENDOR_NAME_LEN 16
127 #define AXGBE_SFP_BASE_VENDOR_PN 40
128 #define AXGBE_SFP_BASE_VENDOR_PN_LEN 16
129 #define AXGBE_SFP_BASE_VENDOR_REV 56
130 #define AXGBE_SFP_BASE_VENDOR_REV_LEN 4
132 #define AXGBE_SFP_BASE_CC 63
134 /* SFP Serial ID Extended ID values relative to an offset of 64 */
135 #define AXGBE_SFP_BASE_VENDOR_SN 4
136 #define AXGBE_SFP_BASE_VENDOR_SN_LEN 16
138 #define AXGBE_SFP_EXTD_DIAG 28
139 #define AXGBE_SFP_EXTD_DIAG_ADDR_CHANGE BIT(2)
141 #define AXGBE_SFP_EXTD_SFF_8472 30
143 #define AXGBE_SFP_EXTD_CC 31
145 struct axgbe_sfp_eeprom {
151 #define AXGBE_BEL_FUSE_VENDOR "BEL-FUSE"
152 #define AXGBE_BEL_FUSE_PARTNO "1GBT-SFP06"
154 struct axgbe_sfp_ascii {
156 char vendor[AXGBE_SFP_BASE_VENDOR_NAME_LEN + 1];
157 char partno[AXGBE_SFP_BASE_VENDOR_PN_LEN + 1];
158 char rev[AXGBE_SFP_BASE_VENDOR_REV_LEN + 1];
159 char serno[AXGBE_SFP_BASE_VENDOR_SN_LEN + 1];
163 /* MDIO PHY reset types */
164 enum axgbe_mdio_reset {
165 AXGBE_MDIO_RESET_NONE = 0,
166 AXGBE_MDIO_RESET_I2C_GPIO,
167 AXGBE_MDIO_RESET_INT_GPIO,
168 AXGBE_MDIO_RESET_MAX,
171 /* Re-driver related definitions */
172 enum axgbe_phy_redrv_if {
173 AXGBE_PHY_REDRV_IF_MDIO = 0,
174 AXGBE_PHY_REDRV_IF_I2C,
175 AXGBE_PHY_REDRV_IF_MAX,
178 enum axgbe_phy_redrv_model {
179 AXGBE_PHY_REDRV_MODEL_4223 = 0,
180 AXGBE_PHY_REDRV_MODEL_4227,
181 AXGBE_PHY_REDRV_MODEL_MAX,
184 enum axgbe_phy_redrv_mode {
185 AXGBE_PHY_REDRV_MODE_CX = 5,
186 AXGBE_PHY_REDRV_MODE_SR = 9,
189 #define AXGBE_PHY_REDRV_MODE_REG 0x12b0
191 /* PHY related configuration information */
192 struct axgbe_phy_data {
193 enum axgbe_port_mode port_mode;
195 unsigned int port_id;
197 unsigned int port_speeds;
199 enum axgbe_conn_type conn_type;
201 enum axgbe_mode cur_mode;
202 enum axgbe_mode start_mode;
204 unsigned int rrc_count;
206 unsigned int mdio_addr;
208 unsigned int comm_owned;
211 enum axgbe_sfp_comm sfp_comm;
212 unsigned int sfp_mux_address;
213 unsigned int sfp_mux_channel;
215 unsigned int sfp_gpio_address;
216 unsigned int sfp_gpio_mask;
217 unsigned int sfp_gpio_rx_los;
218 unsigned int sfp_gpio_tx_fault;
219 unsigned int sfp_gpio_mod_absent;
220 unsigned int sfp_gpio_rate_select;
222 unsigned int sfp_rx_los;
223 unsigned int sfp_tx_fault;
224 unsigned int sfp_mod_absent;
225 unsigned int sfp_diags;
226 unsigned int sfp_changed;
227 unsigned int sfp_phy_avail;
228 unsigned int sfp_cable_len;
229 enum axgbe_sfp_base sfp_base;
230 enum axgbe_sfp_cable sfp_cable;
231 enum axgbe_sfp_speed sfp_speed;
232 struct axgbe_sfp_eeprom sfp_eeprom;
234 /* External PHY support */
235 enum axgbe_mdio_mode phydev_mode;
236 enum axgbe_mdio_reset mdio_reset;
237 unsigned int mdio_reset_addr;
238 unsigned int mdio_reset_gpio;
240 /* Re-driver support */
242 unsigned int redrv_if;
243 unsigned int redrv_addr;
244 unsigned int redrv_lane;
245 unsigned int redrv_model;
248 unsigned int phy_cdr_notrack;
249 unsigned int phy_cdr_delay;
252 static enum axgbe_an_mode axgbe_phy_an_mode(struct axgbe_port *pdata);
254 static int axgbe_phy_i2c_xfer(struct axgbe_port *pdata,
255 struct axgbe_i2c_op *i2c_op)
257 struct axgbe_phy_data *phy_data = pdata->phy_data;
259 /* Be sure we own the bus */
260 if (!phy_data->comm_owned)
263 return pdata->i2c_if.i2c_xfer(pdata, i2c_op);
266 static int axgbe_phy_redrv_write(struct axgbe_port *pdata, unsigned int reg,
269 struct axgbe_phy_data *phy_data = pdata->phy_data;
270 struct axgbe_i2c_op i2c_op;
272 u8 redrv_data[5], csum;
273 unsigned int i, retry;
276 /* High byte of register contains read/write indicator */
277 redrv_data[0] = ((reg >> 8) & 0xff) << 1;
278 redrv_data[1] = reg & 0xff;
279 redrv_val = (uint16_t *)&redrv_data[2];
280 *redrv_val = rte_cpu_to_be_16(val);
282 /* Calculate 1 byte checksum */
284 for (i = 0; i < 4; i++) {
285 csum += redrv_data[i];
286 if (redrv_data[i] > csum)
289 redrv_data[4] = ~csum;
293 i2c_op.cmd = AXGBE_I2C_CMD_WRITE;
294 i2c_op.target = phy_data->redrv_addr;
295 i2c_op.len = sizeof(redrv_data);
296 i2c_op.buf = redrv_data;
297 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op);
299 if ((ret == -EAGAIN) && retry--)
307 i2c_op.cmd = AXGBE_I2C_CMD_READ;
308 i2c_op.target = phy_data->redrv_addr;
310 i2c_op.buf = redrv_data;
311 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op);
313 if ((ret == -EAGAIN) && retry--)
319 if (redrv_data[0] != 0xff) {
320 PMD_DRV_LOG(ERR, "Redriver write checksum error\n");
327 static int axgbe_phy_i2c_read(struct axgbe_port *pdata, unsigned int target,
328 void *reg, unsigned int reg_len,
329 void *val, unsigned int val_len)
331 struct axgbe_i2c_op i2c_op;
336 /* Set the specified register to read */
337 i2c_op.cmd = AXGBE_I2C_CMD_WRITE;
338 i2c_op.target = target;
339 i2c_op.len = reg_len;
341 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op);
343 if ((ret == -EAGAIN) && retry--)
351 /* Read the specified register */
352 i2c_op.cmd = AXGBE_I2C_CMD_READ;
353 i2c_op.target = target;
354 i2c_op.len = val_len;
356 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op);
357 if ((ret == -EAGAIN) && retry--)
363 static int axgbe_phy_sfp_put_mux(struct axgbe_port *pdata)
365 struct axgbe_phy_data *phy_data = pdata->phy_data;
366 struct axgbe_i2c_op i2c_op;
369 if (phy_data->sfp_comm == AXGBE_SFP_COMM_DIRECT)
372 /* Select no mux channels */
374 i2c_op.cmd = AXGBE_I2C_CMD_WRITE;
375 i2c_op.target = phy_data->sfp_mux_address;
376 i2c_op.len = sizeof(mux_channel);
377 i2c_op.buf = &mux_channel;
379 return axgbe_phy_i2c_xfer(pdata, &i2c_op);
382 static int axgbe_phy_sfp_get_mux(struct axgbe_port *pdata)
384 struct axgbe_phy_data *phy_data = pdata->phy_data;
385 struct axgbe_i2c_op i2c_op;
388 if (phy_data->sfp_comm == AXGBE_SFP_COMM_DIRECT)
391 /* Select desired mux channel */
392 mux_channel = 1 << phy_data->sfp_mux_channel;
393 i2c_op.cmd = AXGBE_I2C_CMD_WRITE;
394 i2c_op.target = phy_data->sfp_mux_address;
395 i2c_op.len = sizeof(mux_channel);
396 i2c_op.buf = &mux_channel;
398 return axgbe_phy_i2c_xfer(pdata, &i2c_op);
401 static void axgbe_phy_put_comm_ownership(struct axgbe_port *pdata)
403 struct axgbe_phy_data *phy_data = pdata->phy_data;
405 phy_data->comm_owned = 0;
407 pthread_mutex_unlock(&pdata->phy_mutex);
410 static int axgbe_phy_get_comm_ownership(struct axgbe_port *pdata)
412 struct axgbe_phy_data *phy_data = pdata->phy_data;
414 unsigned int mutex_id;
416 /* The I2C and MDIO/GPIO bus is multiplexed between multiple devices,
417 * the driver needs to take the software mutex and then the hardware
418 * mutexes before being able to use the busses.
420 pthread_mutex_lock(&pdata->phy_mutex);
422 if (phy_data->comm_owned)
425 /* Clear the mutexes */
426 XP_IOWRITE(pdata, XP_I2C_MUTEX, AXGBE_MUTEX_RELEASE);
427 XP_IOWRITE(pdata, XP_MDIO_MUTEX, AXGBE_MUTEX_RELEASE);
429 /* Mutex formats are the same for I2C and MDIO/GPIO */
431 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ID, phy_data->port_id);
432 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ACTIVE, 1);
434 timeout = rte_get_timer_cycles() + (rte_get_timer_hz() * 5);
435 while (time_before(rte_get_timer_cycles(), timeout)) {
436 /* Must be all zeroes in order to obtain the mutex */
437 if (XP_IOREAD(pdata, XP_I2C_MUTEX) ||
438 XP_IOREAD(pdata, XP_MDIO_MUTEX)) {
443 /* Obtain the mutex */
444 XP_IOWRITE(pdata, XP_I2C_MUTEX, mutex_id);
445 XP_IOWRITE(pdata, XP_MDIO_MUTEX, mutex_id);
447 phy_data->comm_owned = 1;
451 pthread_mutex_unlock(&pdata->phy_mutex);
453 PMD_DRV_LOG(ERR, "unable to obtain hardware mutexes\n");
458 static void axgbe_phy_sfp_phy_settings(struct axgbe_port *pdata)
460 struct axgbe_phy_data *phy_data = pdata->phy_data;
462 if (phy_data->sfp_mod_absent) {
463 pdata->phy.speed = SPEED_UNKNOWN;
464 pdata->phy.duplex = DUPLEX_UNKNOWN;
465 pdata->phy.autoneg = AUTONEG_ENABLE;
466 pdata->phy.advertising = pdata->phy.supported;
469 pdata->phy.advertising &= ~ADVERTISED_Autoneg;
470 pdata->phy.advertising &= ~ADVERTISED_TP;
471 pdata->phy.advertising &= ~ADVERTISED_FIBRE;
472 pdata->phy.advertising &= ~ADVERTISED_100baseT_Full;
473 pdata->phy.advertising &= ~ADVERTISED_1000baseT_Full;
474 pdata->phy.advertising &= ~ADVERTISED_10000baseT_Full;
475 pdata->phy.advertising &= ~ADVERTISED_10000baseR_FEC;
477 switch (phy_data->sfp_base) {
478 case AXGBE_SFP_BASE_1000_T:
479 case AXGBE_SFP_BASE_1000_SX:
480 case AXGBE_SFP_BASE_1000_LX:
481 case AXGBE_SFP_BASE_1000_CX:
482 pdata->phy.speed = SPEED_UNKNOWN;
483 pdata->phy.duplex = DUPLEX_UNKNOWN;
484 pdata->phy.autoneg = AUTONEG_ENABLE;
485 pdata->phy.advertising |= ADVERTISED_Autoneg;
487 case AXGBE_SFP_BASE_10000_SR:
488 case AXGBE_SFP_BASE_10000_LR:
489 case AXGBE_SFP_BASE_10000_LRM:
490 case AXGBE_SFP_BASE_10000_ER:
491 case AXGBE_SFP_BASE_10000_CR:
493 pdata->phy.speed = SPEED_10000;
494 pdata->phy.duplex = DUPLEX_FULL;
495 pdata->phy.autoneg = AUTONEG_DISABLE;
499 switch (phy_data->sfp_base) {
500 case AXGBE_SFP_BASE_1000_T:
501 case AXGBE_SFP_BASE_1000_CX:
502 case AXGBE_SFP_BASE_10000_CR:
503 pdata->phy.advertising |= ADVERTISED_TP;
506 pdata->phy.advertising |= ADVERTISED_FIBRE;
509 switch (phy_data->sfp_speed) {
510 case AXGBE_SFP_SPEED_100_1000:
511 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100)
512 pdata->phy.advertising |= ADVERTISED_100baseT_Full;
513 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000)
514 pdata->phy.advertising |= ADVERTISED_1000baseT_Full;
516 case AXGBE_SFP_SPEED_1000:
517 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000)
518 pdata->phy.advertising |= ADVERTISED_1000baseT_Full;
520 case AXGBE_SFP_SPEED_10000:
521 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000)
522 pdata->phy.advertising |= ADVERTISED_10000baseT_Full;
525 /* Choose the fastest supported speed */
526 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000)
527 pdata->phy.advertising |= ADVERTISED_10000baseT_Full;
528 else if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000)
529 pdata->phy.advertising |= ADVERTISED_1000baseT_Full;
530 else if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100)
531 pdata->phy.advertising |= ADVERTISED_100baseT_Full;
535 static bool axgbe_phy_sfp_bit_rate(struct axgbe_sfp_eeprom *sfp_eeprom,
536 enum axgbe_sfp_speed sfp_speed)
538 u8 *sfp_base, min, max;
540 sfp_base = sfp_eeprom->base;
543 case AXGBE_SFP_SPEED_1000:
544 min = AXGBE_SFP_BASE_BR_1GBE_MIN;
545 max = AXGBE_SFP_BASE_BR_1GBE_MAX;
547 case AXGBE_SFP_SPEED_10000:
548 min = AXGBE_SFP_BASE_BR_10GBE_MIN;
549 max = AXGBE_SFP_BASE_BR_10GBE_MAX;
555 return ((sfp_base[AXGBE_SFP_BASE_BR] >= min) &&
556 (sfp_base[AXGBE_SFP_BASE_BR] <= max));
559 static void axgbe_phy_sfp_external_phy(struct axgbe_port *pdata)
561 struct axgbe_phy_data *phy_data = pdata->phy_data;
563 if (!phy_data->sfp_changed)
566 phy_data->sfp_phy_avail = 0;
568 if (phy_data->sfp_base != AXGBE_SFP_BASE_1000_T)
572 static bool axgbe_phy_belfuse_parse_quirks(struct axgbe_port *pdata)
574 struct axgbe_phy_data *phy_data = pdata->phy_data;
575 struct axgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
577 if (memcmp(&sfp_eeprom->base[AXGBE_SFP_BASE_VENDOR_NAME],
578 AXGBE_BEL_FUSE_VENDOR, strlen(AXGBE_BEL_FUSE_VENDOR)))
581 if (!memcmp(&sfp_eeprom->base[AXGBE_SFP_BASE_VENDOR_PN],
582 AXGBE_BEL_FUSE_PARTNO, strlen(AXGBE_BEL_FUSE_PARTNO))) {
583 phy_data->sfp_base = AXGBE_SFP_BASE_1000_SX;
584 phy_data->sfp_cable = AXGBE_SFP_CABLE_ACTIVE;
585 phy_data->sfp_speed = AXGBE_SFP_SPEED_1000;
592 static bool axgbe_phy_sfp_parse_quirks(struct axgbe_port *pdata)
594 if (axgbe_phy_belfuse_parse_quirks(pdata))
600 static void axgbe_phy_sfp_parse_eeprom(struct axgbe_port *pdata)
602 struct axgbe_phy_data *phy_data = pdata->phy_data;
603 struct axgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
606 sfp_base = sfp_eeprom->base;
608 if (sfp_base[AXGBE_SFP_BASE_ID] != AXGBE_SFP_ID_SFP)
611 if (sfp_base[AXGBE_SFP_BASE_EXT_ID] != AXGBE_SFP_EXT_ID_SFP)
614 axgbe_phy_sfp_parse_quirks(pdata);
616 /* Assume ACTIVE cable unless told it is PASSIVE */
617 if (sfp_base[AXGBE_SFP_BASE_CABLE] & AXGBE_SFP_BASE_CABLE_PASSIVE) {
618 phy_data->sfp_cable = AXGBE_SFP_CABLE_PASSIVE;
619 phy_data->sfp_cable_len = sfp_base[AXGBE_SFP_BASE_CU_CABLE_LEN];
621 phy_data->sfp_cable = AXGBE_SFP_CABLE_ACTIVE;
624 /* Determine the type of SFP */
625 if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] & AXGBE_SFP_BASE_10GBE_CC_SR)
626 phy_data->sfp_base = AXGBE_SFP_BASE_10000_SR;
627 else if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] & AXGBE_SFP_BASE_10GBE_CC_LR)
628 phy_data->sfp_base = AXGBE_SFP_BASE_10000_LR;
629 else if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] &
630 AXGBE_SFP_BASE_10GBE_CC_LRM)
631 phy_data->sfp_base = AXGBE_SFP_BASE_10000_LRM;
632 else if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] & AXGBE_SFP_BASE_10GBE_CC_ER)
633 phy_data->sfp_base = AXGBE_SFP_BASE_10000_ER;
634 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_SX)
635 phy_data->sfp_base = AXGBE_SFP_BASE_1000_SX;
636 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_LX)
637 phy_data->sfp_base = AXGBE_SFP_BASE_1000_LX;
638 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_CX)
639 phy_data->sfp_base = AXGBE_SFP_BASE_1000_CX;
640 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_T)
641 phy_data->sfp_base = AXGBE_SFP_BASE_1000_T;
642 else if ((phy_data->sfp_cable == AXGBE_SFP_CABLE_PASSIVE) &&
643 axgbe_phy_sfp_bit_rate(sfp_eeprom, AXGBE_SFP_SPEED_10000))
644 phy_data->sfp_base = AXGBE_SFP_BASE_10000_CR;
646 switch (phy_data->sfp_base) {
647 case AXGBE_SFP_BASE_1000_T:
648 phy_data->sfp_speed = AXGBE_SFP_SPEED_100_1000;
650 case AXGBE_SFP_BASE_1000_SX:
651 case AXGBE_SFP_BASE_1000_LX:
652 case AXGBE_SFP_BASE_1000_CX:
653 phy_data->sfp_speed = AXGBE_SFP_SPEED_1000;
655 case AXGBE_SFP_BASE_10000_SR:
656 case AXGBE_SFP_BASE_10000_LR:
657 case AXGBE_SFP_BASE_10000_LRM:
658 case AXGBE_SFP_BASE_10000_ER:
659 case AXGBE_SFP_BASE_10000_CR:
660 phy_data->sfp_speed = AXGBE_SFP_SPEED_10000;
667 static bool axgbe_phy_sfp_verify_eeprom(uint8_t cc_in, uint8_t *buf,
672 for (cc = 0; len; buf++, len--)
675 return (cc == cc_in) ? true : false;
678 static int axgbe_phy_sfp_read_eeprom(struct axgbe_port *pdata)
680 struct axgbe_phy_data *phy_data = pdata->phy_data;
681 struct axgbe_sfp_eeprom sfp_eeprom;
685 ret = axgbe_phy_sfp_get_mux(pdata);
687 PMD_DRV_LOG(ERR, "I2C error setting SFP MUX\n");
691 /* Read the SFP serial ID eeprom */
693 ret = axgbe_phy_i2c_read(pdata, AXGBE_SFP_SERIAL_ID_ADDRESS,
694 &eeprom_addr, sizeof(eeprom_addr),
695 &sfp_eeprom, sizeof(sfp_eeprom));
697 PMD_DRV_LOG(ERR, "I2C error reading SFP EEPROM\n");
701 /* Validate the contents read */
702 if (!axgbe_phy_sfp_verify_eeprom(sfp_eeprom.base[AXGBE_SFP_BASE_CC],
704 sizeof(sfp_eeprom.base) - 1)) {
709 if (!axgbe_phy_sfp_verify_eeprom(sfp_eeprom.extd[AXGBE_SFP_EXTD_CC],
711 sizeof(sfp_eeprom.extd) - 1)) {
716 /* Check for an added or changed SFP */
717 if (memcmp(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom))) {
718 phy_data->sfp_changed = 1;
719 memcpy(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom));
721 if (sfp_eeprom.extd[AXGBE_SFP_EXTD_SFF_8472]) {
723 diag_type = sfp_eeprom.extd[AXGBE_SFP_EXTD_DIAG];
725 if (!(diag_type & AXGBE_SFP_EXTD_DIAG_ADDR_CHANGE))
726 phy_data->sfp_diags = 1;
729 phy_data->sfp_changed = 0;
733 axgbe_phy_sfp_put_mux(pdata);
738 static void axgbe_phy_sfp_signals(struct axgbe_port *pdata)
740 struct axgbe_phy_data *phy_data = pdata->phy_data;
741 unsigned int gpio_input;
742 u8 gpio_reg, gpio_ports[2];
745 /* Read the input port registers */
747 ret = axgbe_phy_i2c_read(pdata, phy_data->sfp_gpio_address,
748 &gpio_reg, sizeof(gpio_reg),
749 gpio_ports, sizeof(gpio_ports));
751 PMD_DRV_LOG(ERR, "I2C error reading SFP GPIOs\n");
755 gpio_input = (gpio_ports[1] << 8) | gpio_ports[0];
757 if (phy_data->sfp_gpio_mask & AXGBE_GPIO_NO_MOD_ABSENT) {
758 /* No GPIO, just assume the module is present for now */
759 phy_data->sfp_mod_absent = 0;
761 if (!(gpio_input & (1 << phy_data->sfp_gpio_mod_absent)))
762 phy_data->sfp_mod_absent = 0;
765 if (!(phy_data->sfp_gpio_mask & AXGBE_GPIO_NO_RX_LOS) &&
766 (gpio_input & (1 << phy_data->sfp_gpio_rx_los)))
767 phy_data->sfp_rx_los = 1;
769 if (!(phy_data->sfp_gpio_mask & AXGBE_GPIO_NO_TX_FAULT) &&
770 (gpio_input & (1 << phy_data->sfp_gpio_tx_fault)))
771 phy_data->sfp_tx_fault = 1;
774 static void axgbe_phy_sfp_mod_absent(struct axgbe_port *pdata)
776 struct axgbe_phy_data *phy_data = pdata->phy_data;
778 phy_data->sfp_mod_absent = 1;
779 phy_data->sfp_phy_avail = 0;
780 memset(&phy_data->sfp_eeprom, 0, sizeof(phy_data->sfp_eeprom));
783 static void axgbe_phy_sfp_reset(struct axgbe_phy_data *phy_data)
785 phy_data->sfp_rx_los = 0;
786 phy_data->sfp_tx_fault = 0;
787 phy_data->sfp_mod_absent = 1;
788 phy_data->sfp_diags = 0;
789 phy_data->sfp_base = AXGBE_SFP_BASE_UNKNOWN;
790 phy_data->sfp_cable = AXGBE_SFP_CABLE_UNKNOWN;
791 phy_data->sfp_speed = AXGBE_SFP_SPEED_UNKNOWN;
794 static const char *axgbe_base_as_string(enum axgbe_sfp_base sfp_base)
797 case AXGBE_SFP_BASE_1000_T:
799 case AXGBE_SFP_BASE_1000_SX:
801 case AXGBE_SFP_BASE_1000_LX:
803 case AXGBE_SFP_BASE_1000_CX:
805 case AXGBE_SFP_BASE_10000_SR:
807 case AXGBE_SFP_BASE_10000_LR:
809 case AXGBE_SFP_BASE_10000_LRM:
811 case AXGBE_SFP_BASE_10000_ER:
813 case AXGBE_SFP_BASE_10000_CR:
820 static void axgbe_phy_sfp_detect(struct axgbe_port *pdata)
822 struct axgbe_phy_data *phy_data = pdata->phy_data;
825 /* Reset the SFP signals and info */
826 axgbe_phy_sfp_reset(phy_data);
828 ret = axgbe_phy_get_comm_ownership(pdata);
832 /* Read the SFP signals and check for module presence */
833 axgbe_phy_sfp_signals(pdata);
834 if (phy_data->sfp_mod_absent) {
835 axgbe_phy_sfp_mod_absent(pdata);
839 ret = axgbe_phy_sfp_read_eeprom(pdata);
841 /* Treat any error as if there isn't an SFP plugged in */
842 axgbe_phy_sfp_reset(phy_data);
843 axgbe_phy_sfp_mod_absent(pdata);
847 axgbe_phy_sfp_parse_eeprom(pdata);
848 axgbe_phy_sfp_external_phy(pdata);
850 PMD_DRV_LOG(DEBUG, "SFP Base: %s\n",
851 axgbe_base_as_string(phy_data->sfp_base));
854 axgbe_phy_sfp_phy_settings(pdata);
855 axgbe_phy_put_comm_ownership(pdata);
858 static void axgbe_phy_phydev_flowctrl(struct axgbe_port *pdata)
860 pdata->phy.tx_pause = 0;
861 pdata->phy.rx_pause = 0;
864 static enum axgbe_mode axgbe_phy_an73_redrv_outcome(struct axgbe_port *pdata)
866 struct axgbe_phy_data *phy_data = pdata->phy_data;
867 enum axgbe_mode mode;
868 unsigned int ad_reg, lp_reg;
870 pdata->phy.lp_advertising |= ADVERTISED_Autoneg;
871 pdata->phy.lp_advertising |= ADVERTISED_Backplane;
873 /* Use external PHY to determine flow control */
874 if (pdata->phy.pause_autoneg)
875 axgbe_phy_phydev_flowctrl(pdata);
877 /* Compare Advertisement and Link Partner register 2 */
878 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
879 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
881 pdata->phy.lp_advertising |= ADVERTISED_10000baseKR_Full;
883 pdata->phy.lp_advertising |= ADVERTISED_1000baseKX_Full;
887 switch (phy_data->port_mode) {
888 case AXGBE_PORT_MODE_BACKPLANE:
889 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
890 mode = AXGBE_MODE_KR;
893 mode = AXGBE_MODE_SFI;
896 } else if (ad_reg & 0x20) {
897 switch (phy_data->port_mode) {
898 case AXGBE_PORT_MODE_BACKPLANE:
899 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
900 mode = AXGBE_MODE_KX_1000;
902 case AXGBE_PORT_MODE_1000BASE_X:
905 case AXGBE_PORT_MODE_SFP:
906 switch (phy_data->sfp_base) {
907 case AXGBE_SFP_BASE_1000_T:
908 mode = AXGBE_MODE_SGMII_1000;
910 case AXGBE_SFP_BASE_1000_SX:
911 case AXGBE_SFP_BASE_1000_LX:
912 case AXGBE_SFP_BASE_1000_CX:
919 mode = AXGBE_MODE_SGMII_1000;
923 mode = AXGBE_MODE_UNKNOWN;
926 /* Compare Advertisement and Link Partner register 3 */
927 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
928 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
930 pdata->phy.lp_advertising |= ADVERTISED_10000baseR_FEC;
935 static enum axgbe_mode axgbe_phy_an73_outcome(struct axgbe_port *pdata)
937 enum axgbe_mode mode;
938 unsigned int ad_reg, lp_reg;
940 pdata->phy.lp_advertising |= ADVERTISED_Autoneg;
941 pdata->phy.lp_advertising |= ADVERTISED_Backplane;
943 /* Compare Advertisement and Link Partner register 1 */
944 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
945 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA);
947 pdata->phy.lp_advertising |= ADVERTISED_Pause;
949 pdata->phy.lp_advertising |= ADVERTISED_Asym_Pause;
951 if (pdata->phy.pause_autoneg) {
952 /* Set flow control based on auto-negotiation result */
953 pdata->phy.tx_pause = 0;
954 pdata->phy.rx_pause = 0;
956 if (ad_reg & lp_reg & 0x400) {
957 pdata->phy.tx_pause = 1;
958 pdata->phy.rx_pause = 1;
959 } else if (ad_reg & lp_reg & 0x800) {
961 pdata->phy.rx_pause = 1;
962 else if (lp_reg & 0x400)
963 pdata->phy.tx_pause = 1;
967 /* Compare Advertisement and Link Partner register 2 */
968 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
969 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
971 pdata->phy.lp_advertising |= ADVERTISED_10000baseKR_Full;
973 pdata->phy.lp_advertising |= ADVERTISED_1000baseKX_Full;
977 mode = AXGBE_MODE_KR;
978 else if (ad_reg & 0x20)
979 mode = AXGBE_MODE_KX_1000;
981 mode = AXGBE_MODE_UNKNOWN;
983 /* Compare Advertisement and Link Partner register 3 */
984 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
985 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
987 pdata->phy.lp_advertising |= ADVERTISED_10000baseR_FEC;
992 static enum axgbe_mode axgbe_phy_an37_sgmii_outcome(struct axgbe_port *pdata)
994 enum axgbe_mode mode;
996 pdata->phy.lp_advertising |= ADVERTISED_Autoneg;
997 pdata->phy.lp_advertising |= ADVERTISED_1000baseT_Full;
999 if (pdata->phy.pause_autoneg)
1000 axgbe_phy_phydev_flowctrl(pdata);
1002 switch (pdata->an_status & AXGBE_SGMII_AN_LINK_SPEED) {
1003 case AXGBE_SGMII_AN_LINK_SPEED_100:
1004 if (pdata->an_status & AXGBE_SGMII_AN_LINK_DUPLEX) {
1005 pdata->phy.lp_advertising |= ADVERTISED_100baseT_Full;
1006 mode = AXGBE_MODE_SGMII_100;
1008 mode = AXGBE_MODE_UNKNOWN;
1011 case AXGBE_SGMII_AN_LINK_SPEED_1000:
1012 if (pdata->an_status & AXGBE_SGMII_AN_LINK_DUPLEX) {
1013 pdata->phy.lp_advertising |= ADVERTISED_1000baseT_Full;
1014 mode = AXGBE_MODE_SGMII_1000;
1016 /* Half-duplex not supported */
1017 mode = AXGBE_MODE_UNKNOWN;
1021 mode = AXGBE_MODE_UNKNOWN;
1027 static enum axgbe_mode axgbe_phy_an_outcome(struct axgbe_port *pdata)
1029 switch (pdata->an_mode) {
1030 case AXGBE_AN_MODE_CL73:
1031 return axgbe_phy_an73_outcome(pdata);
1032 case AXGBE_AN_MODE_CL73_REDRV:
1033 return axgbe_phy_an73_redrv_outcome(pdata);
1034 case AXGBE_AN_MODE_CL37:
1035 case AXGBE_AN_MODE_CL37_SGMII:
1036 return axgbe_phy_an37_sgmii_outcome(pdata);
1038 return AXGBE_MODE_UNKNOWN;
1042 static unsigned int axgbe_phy_an_advertising(struct axgbe_port *pdata)
1044 struct axgbe_phy_data *phy_data = pdata->phy_data;
1045 unsigned int advertising;
1047 /* Without a re-driver, just return current advertising */
1048 if (!phy_data->redrv)
1049 return pdata->phy.advertising;
1051 /* With the KR re-driver we need to advertise a single speed */
1052 advertising = pdata->phy.advertising;
1053 advertising &= ~ADVERTISED_1000baseKX_Full;
1054 advertising &= ~ADVERTISED_10000baseKR_Full;
1056 switch (phy_data->port_mode) {
1057 case AXGBE_PORT_MODE_BACKPLANE:
1058 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
1059 advertising |= ADVERTISED_10000baseKR_Full;
1061 case AXGBE_PORT_MODE_BACKPLANE_2500:
1062 advertising |= ADVERTISED_1000baseKX_Full;
1064 case AXGBE_PORT_MODE_1000BASE_T:
1065 case AXGBE_PORT_MODE_1000BASE_X:
1066 case AXGBE_PORT_MODE_NBASE_T:
1067 advertising |= ADVERTISED_1000baseKX_Full;
1069 case AXGBE_PORT_MODE_10GBASE_T:
1070 PMD_DRV_LOG(ERR, "10GBASE_T mode is not supported\n");
1072 case AXGBE_PORT_MODE_10GBASE_R:
1073 advertising |= ADVERTISED_10000baseKR_Full;
1075 case AXGBE_PORT_MODE_SFP:
1076 switch (phy_data->sfp_base) {
1077 case AXGBE_SFP_BASE_1000_T:
1078 case AXGBE_SFP_BASE_1000_SX:
1079 case AXGBE_SFP_BASE_1000_LX:
1080 case AXGBE_SFP_BASE_1000_CX:
1081 advertising |= ADVERTISED_1000baseKX_Full;
1084 advertising |= ADVERTISED_10000baseKR_Full;
1089 advertising |= ADVERTISED_10000baseKR_Full;
1096 static int axgbe_phy_an_config(struct axgbe_port *pdata __rte_unused)
1099 /* Dummy API since there is no case to support
1100 * external phy devices registered through kernel APIs
1104 static enum axgbe_an_mode axgbe_phy_an_sfp_mode(struct axgbe_phy_data *phy_data)
1106 switch (phy_data->sfp_base) {
1107 case AXGBE_SFP_BASE_1000_T:
1108 return AXGBE_AN_MODE_CL37_SGMII;
1109 case AXGBE_SFP_BASE_1000_SX:
1110 case AXGBE_SFP_BASE_1000_LX:
1111 case AXGBE_SFP_BASE_1000_CX:
1112 return AXGBE_AN_MODE_CL37;
1114 return AXGBE_AN_MODE_NONE;
1118 static enum axgbe_an_mode axgbe_phy_an_mode(struct axgbe_port *pdata)
1120 struct axgbe_phy_data *phy_data = pdata->phy_data;
1122 /* A KR re-driver will always require CL73 AN */
1123 if (phy_data->redrv)
1124 return AXGBE_AN_MODE_CL73_REDRV;
1126 switch (phy_data->port_mode) {
1127 case AXGBE_PORT_MODE_BACKPLANE:
1128 return AXGBE_AN_MODE_CL73;
1129 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
1130 case AXGBE_PORT_MODE_BACKPLANE_2500:
1131 return AXGBE_AN_MODE_NONE;
1132 case AXGBE_PORT_MODE_1000BASE_T:
1133 return AXGBE_AN_MODE_CL37_SGMII;
1134 case AXGBE_PORT_MODE_1000BASE_X:
1135 return AXGBE_AN_MODE_CL37;
1136 case AXGBE_PORT_MODE_NBASE_T:
1137 return AXGBE_AN_MODE_CL37_SGMII;
1138 case AXGBE_PORT_MODE_10GBASE_T:
1139 return AXGBE_AN_MODE_CL73;
1140 case AXGBE_PORT_MODE_10GBASE_R:
1141 return AXGBE_AN_MODE_NONE;
1142 case AXGBE_PORT_MODE_SFP:
1143 return axgbe_phy_an_sfp_mode(phy_data);
1145 return AXGBE_AN_MODE_NONE;
1149 static int axgbe_phy_set_redrv_mode_mdio(struct axgbe_port *pdata,
1150 enum axgbe_phy_redrv_mode mode)
1152 struct axgbe_phy_data *phy_data = pdata->phy_data;
1153 u16 redrv_reg, redrv_val;
1155 redrv_reg = AXGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
1156 redrv_val = (u16)mode;
1158 return pdata->hw_if.write_ext_mii_regs(pdata, phy_data->redrv_addr,
1159 redrv_reg, redrv_val);
1162 static int axgbe_phy_set_redrv_mode_i2c(struct axgbe_port *pdata,
1163 enum axgbe_phy_redrv_mode mode)
1165 struct axgbe_phy_data *phy_data = pdata->phy_data;
1166 unsigned int redrv_reg;
1169 /* Calculate the register to write */
1170 redrv_reg = AXGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
1172 ret = axgbe_phy_redrv_write(pdata, redrv_reg, mode);
1177 static void axgbe_phy_set_redrv_mode(struct axgbe_port *pdata)
1179 struct axgbe_phy_data *phy_data = pdata->phy_data;
1180 enum axgbe_phy_redrv_mode mode;
1183 if (!phy_data->redrv)
1186 mode = AXGBE_PHY_REDRV_MODE_CX;
1187 if ((phy_data->port_mode == AXGBE_PORT_MODE_SFP) &&
1188 (phy_data->sfp_base != AXGBE_SFP_BASE_1000_CX) &&
1189 (phy_data->sfp_base != AXGBE_SFP_BASE_10000_CR))
1190 mode = AXGBE_PHY_REDRV_MODE_SR;
1192 ret = axgbe_phy_get_comm_ownership(pdata);
1196 if (phy_data->redrv_if)
1197 axgbe_phy_set_redrv_mode_i2c(pdata, mode);
1199 axgbe_phy_set_redrv_mode_mdio(pdata, mode);
1201 axgbe_phy_put_comm_ownership(pdata);
1204 static void axgbe_phy_rx_reset(struct axgbe_port *pdata)
1208 reg = XMDIO_READ_BITS(pdata, MDIO_MMD_PCS, MDIO_PCS_DIGITAL_STAT,
1209 XGBE_PCS_PSEQ_STATE_MASK);
1210 if (reg == XGBE_PCS_PSEQ_STATE_POWER_GOOD) {
1211 /* Mailbox command timed out, reset of RX block is required.
1212 * This can be done by asseting the reset bit and wait for
1215 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1,
1216 XGBE_PMA_RX_RST_0_MASK, XGBE_PMA_RX_RST_0_RESET_ON);
1218 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1,
1219 XGBE_PMA_RX_RST_0_MASK, XGBE_PMA_RX_RST_0_RESET_OFF);
1221 PMD_DRV_LOG(ERR, "firmware mailbox reset performed\n");
1226 static void axgbe_phy_pll_ctrl(struct axgbe_port *pdata, bool enable)
1228 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_MISC_CTRL0,
1229 XGBE_PMA_PLL_CTRL_MASK,
1230 enable ? XGBE_PMA_PLL_CTRL_SET
1231 : XGBE_PMA_PLL_CTRL_CLEAR);
1233 /* Wait for command to complete */
1237 static void axgbe_phy_perform_ratechange(struct axgbe_port *pdata,
1238 unsigned int cmd, unsigned int sub_cmd)
1240 unsigned int s0 = 0;
1242 /* Clear the PLL so that it helps in power down sequence */
1243 axgbe_phy_pll_ctrl(pdata, false);
1245 /* Log if a previous command did not complete */
1246 if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) {
1247 PMD_DRV_LOG(NOTICE, "firmware mailbox not ready for command\n");
1248 axgbe_phy_rx_reset(pdata);
1251 /* Construct the command */
1252 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, cmd);
1253 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, sub_cmd);
1255 /* Issue the command */
1256 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
1257 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
1258 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
1260 /* Wait for command to complete */
1261 wait = AXGBE_RATECHANGE_COUNT;
1263 if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
1267 PMD_DRV_LOG(NOTICE, "firmware mailbox command did not complete\n");
1268 /* Reset on error */
1269 axgbe_phy_rx_reset(pdata);
1272 /* Re-enable the PLL control */
1273 axgbe_phy_pll_ctrl(pdata, true);
1275 PMD_DRV_LOG(NOTICE, "firmware mailbox command did not complete\n");
1278 static void axgbe_phy_rrc(struct axgbe_port *pdata)
1282 /* Receiver Reset Cycle */
1283 axgbe_phy_perform_ratechange(pdata, 5, 0);
1285 PMD_DRV_LOG(DEBUG, "receiver reset complete\n");
1288 static void axgbe_phy_power_off(struct axgbe_port *pdata)
1290 struct axgbe_phy_data *phy_data = pdata->phy_data;
1293 axgbe_phy_perform_ratechange(pdata, 0, 0);
1295 phy_data->cur_mode = AXGBE_MODE_UNKNOWN;
1297 PMD_DRV_LOG(DEBUG, "phy powered off\n");
1300 static void axgbe_phy_sfi_mode(struct axgbe_port *pdata)
1302 struct axgbe_phy_data *phy_data = pdata->phy_data;
1304 axgbe_phy_set_redrv_mode(pdata);
1307 if (phy_data->sfp_cable != AXGBE_SFP_CABLE_PASSIVE) {
1308 axgbe_phy_perform_ratechange(pdata, 3, 0);
1310 if (phy_data->sfp_cable_len <= 1)
1311 axgbe_phy_perform_ratechange(pdata, 3, 1);
1312 else if (phy_data->sfp_cable_len <= 3)
1313 axgbe_phy_perform_ratechange(pdata, 3, 2);
1315 axgbe_phy_perform_ratechange(pdata, 3, 3);
1318 phy_data->cur_mode = AXGBE_MODE_SFI;
1320 PMD_DRV_LOG(DEBUG, "10GbE SFI mode set\n");
1323 static void axgbe_phy_kr_mode(struct axgbe_port *pdata)
1325 struct axgbe_phy_data *phy_data = pdata->phy_data;
1327 axgbe_phy_set_redrv_mode(pdata);
1330 axgbe_phy_perform_ratechange(pdata, 4, 0);
1331 phy_data->cur_mode = AXGBE_MODE_KR;
1333 PMD_DRV_LOG(DEBUG, "10GbE KR mode set\n");
1336 static void axgbe_phy_kx_2500_mode(struct axgbe_port *pdata)
1338 struct axgbe_phy_data *phy_data = pdata->phy_data;
1340 axgbe_phy_set_redrv_mode(pdata);
1343 axgbe_phy_perform_ratechange(pdata, 2, 0);
1344 phy_data->cur_mode = AXGBE_MODE_KX_2500;
1347 static void axgbe_phy_sgmii_1000_mode(struct axgbe_port *pdata)
1349 struct axgbe_phy_data *phy_data = pdata->phy_data;
1351 axgbe_phy_set_redrv_mode(pdata);
1354 axgbe_phy_perform_ratechange(pdata, 1, 2);
1356 phy_data->cur_mode = AXGBE_MODE_SGMII_1000;
1359 static enum axgbe_mode axgbe_phy_cur_mode(struct axgbe_port *pdata)
1361 struct axgbe_phy_data *phy_data = pdata->phy_data;
1363 return phy_data->cur_mode;
1366 static enum axgbe_mode axgbe_phy_switch_baset_mode(struct axgbe_port *pdata)
1368 struct axgbe_phy_data *phy_data = pdata->phy_data;
1370 /* No switching if not 10GBase-T */
1371 if (phy_data->port_mode != AXGBE_PORT_MODE_10GBASE_T)
1372 return axgbe_phy_cur_mode(pdata);
1374 switch (axgbe_phy_cur_mode(pdata)) {
1375 case AXGBE_MODE_SGMII_100:
1376 case AXGBE_MODE_SGMII_1000:
1377 return AXGBE_MODE_KR;
1380 return AXGBE_MODE_SGMII_1000;
1384 static enum axgbe_mode axgbe_phy_switch_bp_2500_mode(struct axgbe_port *pdata
1387 return AXGBE_MODE_KX_2500;
1390 static enum axgbe_mode axgbe_phy_switch_bp_mode(struct axgbe_port *pdata)
1392 /* If we are in KR switch to KX, and vice-versa */
1393 switch (axgbe_phy_cur_mode(pdata)) {
1394 case AXGBE_MODE_KX_1000:
1395 return AXGBE_MODE_KR;
1398 return AXGBE_MODE_KX_1000;
1402 static enum axgbe_mode axgbe_phy_switch_mode(struct axgbe_port *pdata)
1404 struct axgbe_phy_data *phy_data = pdata->phy_data;
1406 switch (phy_data->port_mode) {
1407 case AXGBE_PORT_MODE_BACKPLANE:
1408 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
1409 return axgbe_phy_switch_bp_mode(pdata);
1410 case AXGBE_PORT_MODE_BACKPLANE_2500:
1411 return axgbe_phy_switch_bp_2500_mode(pdata);
1412 case AXGBE_PORT_MODE_1000BASE_T:
1413 case AXGBE_PORT_MODE_NBASE_T:
1414 case AXGBE_PORT_MODE_10GBASE_T:
1415 return axgbe_phy_switch_baset_mode(pdata);
1416 case AXGBE_PORT_MODE_1000BASE_X:
1417 case AXGBE_PORT_MODE_10GBASE_R:
1418 case AXGBE_PORT_MODE_SFP:
1419 /* No switching, so just return current mode */
1420 return axgbe_phy_cur_mode(pdata);
1422 return AXGBE_MODE_UNKNOWN;
1426 static enum axgbe_mode axgbe_phy_get_basex_mode(struct axgbe_phy_data *phy_data
1432 return AXGBE_MODE_X;
1434 return AXGBE_MODE_KR;
1436 return AXGBE_MODE_UNKNOWN;
1440 static enum axgbe_mode axgbe_phy_get_baset_mode(struct axgbe_phy_data *phy_data
1446 return AXGBE_MODE_SGMII_100;
1448 return AXGBE_MODE_SGMII_1000;
1450 return AXGBE_MODE_KR;
1452 return AXGBE_MODE_UNKNOWN;
1456 static enum axgbe_mode axgbe_phy_get_sfp_mode(struct axgbe_phy_data *phy_data,
1461 return AXGBE_MODE_SGMII_100;
1463 if (phy_data->sfp_base == AXGBE_SFP_BASE_1000_T)
1464 return AXGBE_MODE_SGMII_1000;
1466 return AXGBE_MODE_X;
1469 return AXGBE_MODE_SFI;
1471 return AXGBE_MODE_UNKNOWN;
1475 static enum axgbe_mode axgbe_phy_get_bp_2500_mode(int speed)
1479 return AXGBE_MODE_KX_2500;
1481 return AXGBE_MODE_UNKNOWN;
1485 static enum axgbe_mode axgbe_phy_get_bp_mode(int speed)
1489 return AXGBE_MODE_KX_1000;
1491 return AXGBE_MODE_KR;
1493 return AXGBE_MODE_UNKNOWN;
1497 static enum axgbe_mode axgbe_phy_get_mode(struct axgbe_port *pdata,
1500 struct axgbe_phy_data *phy_data = pdata->phy_data;
1502 switch (phy_data->port_mode) {
1503 case AXGBE_PORT_MODE_BACKPLANE:
1504 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
1505 return axgbe_phy_get_bp_mode(speed);
1506 case AXGBE_PORT_MODE_BACKPLANE_2500:
1507 return axgbe_phy_get_bp_2500_mode(speed);
1508 case AXGBE_PORT_MODE_1000BASE_T:
1509 case AXGBE_PORT_MODE_NBASE_T:
1510 case AXGBE_PORT_MODE_10GBASE_T:
1511 return axgbe_phy_get_baset_mode(phy_data, speed);
1512 case AXGBE_PORT_MODE_1000BASE_X:
1513 case AXGBE_PORT_MODE_10GBASE_R:
1514 return axgbe_phy_get_basex_mode(phy_data, speed);
1515 case AXGBE_PORT_MODE_SFP:
1516 return axgbe_phy_get_sfp_mode(phy_data, speed);
1518 return AXGBE_MODE_UNKNOWN;
1522 static void axgbe_phy_set_mode(struct axgbe_port *pdata, enum axgbe_mode mode)
1526 axgbe_phy_kr_mode(pdata);
1528 case AXGBE_MODE_SFI:
1529 axgbe_phy_sfi_mode(pdata);
1531 case AXGBE_MODE_KX_2500:
1532 axgbe_phy_kx_2500_mode(pdata);
1534 case AXGBE_MODE_SGMII_1000:
1535 axgbe_phy_sgmii_1000_mode(pdata);
1542 static bool axgbe_phy_check_mode(struct axgbe_port *pdata,
1543 enum axgbe_mode mode, u32 advert)
1545 if (pdata->phy.autoneg == AUTONEG_ENABLE) {
1546 if (pdata->phy.advertising & advert)
1549 enum axgbe_mode cur_mode;
1551 cur_mode = axgbe_phy_get_mode(pdata, pdata->phy.speed);
1552 if (cur_mode == mode)
1559 static bool axgbe_phy_use_basex_mode(struct axgbe_port *pdata,
1560 enum axgbe_mode mode)
1564 return axgbe_phy_check_mode(pdata, mode,
1565 ADVERTISED_1000baseT_Full);
1567 return axgbe_phy_check_mode(pdata, mode,
1568 ADVERTISED_10000baseT_Full);
1574 static bool axgbe_phy_use_baset_mode(struct axgbe_port *pdata,
1575 enum axgbe_mode mode)
1578 case AXGBE_MODE_SGMII_100:
1579 return axgbe_phy_check_mode(pdata, mode,
1580 ADVERTISED_100baseT_Full);
1581 case AXGBE_MODE_SGMII_1000:
1582 return axgbe_phy_check_mode(pdata, mode,
1583 ADVERTISED_1000baseT_Full);
1585 return axgbe_phy_check_mode(pdata, mode,
1586 ADVERTISED_10000baseT_Full);
1592 static bool axgbe_phy_use_sfp_mode(struct axgbe_port *pdata,
1593 enum axgbe_mode mode)
1595 struct axgbe_phy_data *phy_data = pdata->phy_data;
1599 if (phy_data->sfp_base == AXGBE_SFP_BASE_1000_T)
1601 return axgbe_phy_check_mode(pdata, mode,
1602 ADVERTISED_1000baseT_Full);
1603 case AXGBE_MODE_SGMII_100:
1604 if (phy_data->sfp_base != AXGBE_SFP_BASE_1000_T)
1606 return axgbe_phy_check_mode(pdata, mode,
1607 ADVERTISED_100baseT_Full);
1608 case AXGBE_MODE_SGMII_1000:
1609 if (phy_data->sfp_base != AXGBE_SFP_BASE_1000_T)
1611 return axgbe_phy_check_mode(pdata, mode,
1612 ADVERTISED_1000baseT_Full);
1613 case AXGBE_MODE_SFI:
1614 return axgbe_phy_check_mode(pdata, mode,
1615 ADVERTISED_10000baseT_Full);
1621 static bool axgbe_phy_use_bp_2500_mode(struct axgbe_port *pdata,
1622 enum axgbe_mode mode)
1625 case AXGBE_MODE_KX_2500:
1626 return axgbe_phy_check_mode(pdata, mode,
1627 ADVERTISED_2500baseX_Full);
1633 static bool axgbe_phy_use_bp_mode(struct axgbe_port *pdata,
1634 enum axgbe_mode mode)
1637 case AXGBE_MODE_KX_1000:
1638 return axgbe_phy_check_mode(pdata, mode,
1639 ADVERTISED_1000baseKX_Full);
1641 return axgbe_phy_check_mode(pdata, mode,
1642 ADVERTISED_10000baseKR_Full);
1648 static bool axgbe_phy_use_mode(struct axgbe_port *pdata, enum axgbe_mode mode)
1650 struct axgbe_phy_data *phy_data = pdata->phy_data;
1652 switch (phy_data->port_mode) {
1653 case AXGBE_PORT_MODE_BACKPLANE:
1654 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
1655 return axgbe_phy_use_bp_mode(pdata, mode);
1656 case AXGBE_PORT_MODE_BACKPLANE_2500:
1657 return axgbe_phy_use_bp_2500_mode(pdata, mode);
1658 case AXGBE_PORT_MODE_1000BASE_T:
1659 case AXGBE_PORT_MODE_NBASE_T:
1660 case AXGBE_PORT_MODE_10GBASE_T:
1661 return axgbe_phy_use_baset_mode(pdata, mode);
1662 case AXGBE_PORT_MODE_1000BASE_X:
1663 case AXGBE_PORT_MODE_10GBASE_R:
1664 return axgbe_phy_use_basex_mode(pdata, mode);
1665 case AXGBE_PORT_MODE_SFP:
1666 return axgbe_phy_use_sfp_mode(pdata, mode);
1672 static int axgbe_phy_link_status(struct axgbe_port *pdata, int *an_restart)
1674 struct axgbe_phy_data *phy_data = pdata->phy_data;
1679 if (phy_data->port_mode == AXGBE_PORT_MODE_SFP) {
1680 /* Check SFP signals */
1681 axgbe_phy_sfp_detect(pdata);
1683 if (phy_data->sfp_changed) {
1688 if (phy_data->sfp_mod_absent || phy_data->sfp_rx_los)
1692 /* Link status is latched low, so read once to clear
1693 * and then read again to get current state
1695 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
1696 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
1697 if (reg & MDIO_STAT1_LSTATUS)
1700 /* No link, attempt a receiver reset cycle */
1701 if (phy_data->rrc_count++) {
1702 phy_data->rrc_count = 0;
1703 axgbe_phy_rrc(pdata);
1709 static void axgbe_phy_sfp_gpio_setup(struct axgbe_port *pdata)
1711 struct axgbe_phy_data *phy_data = pdata->phy_data;
1714 reg = XP_IOREAD(pdata, XP_PROP_3);
1716 phy_data->sfp_gpio_address = AXGBE_GPIO_ADDRESS_PCA9555 +
1717 XP_GET_BITS(reg, XP_PROP_3, GPIO_ADDR);
1719 phy_data->sfp_gpio_mask = XP_GET_BITS(reg, XP_PROP_3, GPIO_MASK);
1721 phy_data->sfp_gpio_rx_los = XP_GET_BITS(reg, XP_PROP_3,
1723 phy_data->sfp_gpio_tx_fault = XP_GET_BITS(reg, XP_PROP_3,
1725 phy_data->sfp_gpio_mod_absent = XP_GET_BITS(reg, XP_PROP_3,
1727 phy_data->sfp_gpio_rate_select = XP_GET_BITS(reg, XP_PROP_3,
1731 static void axgbe_phy_sfp_comm_setup(struct axgbe_port *pdata)
1733 struct axgbe_phy_data *phy_data = pdata->phy_data;
1734 unsigned int reg, mux_addr_hi, mux_addr_lo;
1736 reg = XP_IOREAD(pdata, XP_PROP_4);
1738 mux_addr_hi = XP_GET_BITS(reg, XP_PROP_4, MUX_ADDR_HI);
1739 mux_addr_lo = XP_GET_BITS(reg, XP_PROP_4, MUX_ADDR_LO);
1740 if (mux_addr_lo == AXGBE_SFP_DIRECT)
1743 phy_data->sfp_comm = AXGBE_SFP_COMM_PCA9545;
1744 phy_data->sfp_mux_address = (mux_addr_hi << 2) + mux_addr_lo;
1745 phy_data->sfp_mux_channel = XP_GET_BITS(reg, XP_PROP_4, MUX_CHAN);
1748 static void axgbe_phy_sfp_setup(struct axgbe_port *pdata)
1750 axgbe_phy_sfp_comm_setup(pdata);
1751 axgbe_phy_sfp_gpio_setup(pdata);
1754 static bool axgbe_phy_redrv_error(struct axgbe_phy_data *phy_data)
1756 if (!phy_data->redrv)
1759 if (phy_data->redrv_if >= AXGBE_PHY_REDRV_IF_MAX)
1762 switch (phy_data->redrv_model) {
1763 case AXGBE_PHY_REDRV_MODEL_4223:
1764 if (phy_data->redrv_lane > 3)
1767 case AXGBE_PHY_REDRV_MODEL_4227:
1768 if (phy_data->redrv_lane > 1)
1778 static int axgbe_phy_mdio_reset_setup(struct axgbe_port *pdata)
1780 struct axgbe_phy_data *phy_data = pdata->phy_data;
1783 if (phy_data->conn_type != AXGBE_CONN_TYPE_MDIO)
1785 reg = XP_IOREAD(pdata, XP_PROP_3);
1786 phy_data->mdio_reset = XP_GET_BITS(reg, XP_PROP_3, MDIO_RESET);
1787 switch (phy_data->mdio_reset) {
1788 case AXGBE_MDIO_RESET_NONE:
1789 case AXGBE_MDIO_RESET_I2C_GPIO:
1790 case AXGBE_MDIO_RESET_INT_GPIO:
1793 PMD_DRV_LOG(ERR, "unsupported MDIO reset (%#x)\n",
1794 phy_data->mdio_reset);
1797 if (phy_data->mdio_reset == AXGBE_MDIO_RESET_I2C_GPIO) {
1798 phy_data->mdio_reset_addr = AXGBE_GPIO_ADDRESS_PCA9555 +
1799 XP_GET_BITS(reg, XP_PROP_3,
1800 MDIO_RESET_I2C_ADDR);
1801 phy_data->mdio_reset_gpio = XP_GET_BITS(reg, XP_PROP_3,
1802 MDIO_RESET_I2C_GPIO);
1803 } else if (phy_data->mdio_reset == AXGBE_MDIO_RESET_INT_GPIO) {
1804 phy_data->mdio_reset_gpio = XP_GET_BITS(reg, XP_PROP_3,
1805 MDIO_RESET_INT_GPIO);
1811 static bool axgbe_phy_port_mode_mismatch(struct axgbe_port *pdata)
1813 struct axgbe_phy_data *phy_data = pdata->phy_data;
1815 switch (phy_data->port_mode) {
1816 case AXGBE_PORT_MODE_BACKPLANE:
1817 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
1818 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) ||
1819 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000))
1822 case AXGBE_PORT_MODE_BACKPLANE_2500:
1823 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_2500)
1826 case AXGBE_PORT_MODE_1000BASE_T:
1827 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) ||
1828 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000))
1831 case AXGBE_PORT_MODE_1000BASE_X:
1832 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000)
1835 case AXGBE_PORT_MODE_NBASE_T:
1836 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) ||
1837 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) ||
1838 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_2500))
1841 case AXGBE_PORT_MODE_10GBASE_T:
1842 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) ||
1843 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) ||
1844 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000))
1847 case AXGBE_PORT_MODE_10GBASE_R:
1848 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000)
1851 case AXGBE_PORT_MODE_SFP:
1852 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) ||
1853 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) ||
1854 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000))
1864 static bool axgbe_phy_conn_type_mismatch(struct axgbe_port *pdata)
1866 struct axgbe_phy_data *phy_data = pdata->phy_data;
1868 switch (phy_data->port_mode) {
1869 case AXGBE_PORT_MODE_BACKPLANE:
1870 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
1871 case AXGBE_PORT_MODE_BACKPLANE_2500:
1872 if (phy_data->conn_type == AXGBE_CONN_TYPE_BACKPLANE)
1875 case AXGBE_PORT_MODE_1000BASE_T:
1876 case AXGBE_PORT_MODE_1000BASE_X:
1877 case AXGBE_PORT_MODE_NBASE_T:
1878 case AXGBE_PORT_MODE_10GBASE_T:
1879 case AXGBE_PORT_MODE_10GBASE_R:
1880 if (phy_data->conn_type == AXGBE_CONN_TYPE_MDIO)
1883 case AXGBE_PORT_MODE_SFP:
1884 if (phy_data->conn_type == AXGBE_CONN_TYPE_SFP)
1894 static bool axgbe_phy_port_enabled(struct axgbe_port *pdata)
1898 reg = XP_IOREAD(pdata, XP_PROP_0);
1899 if (!XP_GET_BITS(reg, XP_PROP_0, PORT_SPEEDS))
1901 if (!XP_GET_BITS(reg, XP_PROP_0, CONN_TYPE))
1907 static void axgbe_phy_cdr_track(struct axgbe_port *pdata)
1909 struct axgbe_phy_data *phy_data = pdata->phy_data;
1911 if (!pdata->vdata->an_cdr_workaround)
1914 if (!phy_data->phy_cdr_notrack)
1917 rte_delay_us(phy_data->phy_cdr_delay + 400);
1919 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL,
1920 AXGBE_PMA_CDR_TRACK_EN_MASK,
1921 AXGBE_PMA_CDR_TRACK_EN_ON);
1923 phy_data->phy_cdr_notrack = 0;
1926 static void axgbe_phy_cdr_notrack(struct axgbe_port *pdata)
1928 struct axgbe_phy_data *phy_data = pdata->phy_data;
1930 if (!pdata->vdata->an_cdr_workaround)
1933 if (phy_data->phy_cdr_notrack)
1936 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL,
1937 AXGBE_PMA_CDR_TRACK_EN_MASK,
1938 AXGBE_PMA_CDR_TRACK_EN_OFF);
1940 axgbe_phy_rrc(pdata);
1942 phy_data->phy_cdr_notrack = 1;
1945 static void axgbe_phy_kr_training_post(struct axgbe_port *pdata)
1947 if (!pdata->cdr_track_early)
1948 axgbe_phy_cdr_track(pdata);
1951 static void axgbe_phy_kr_training_pre(struct axgbe_port *pdata)
1953 if (pdata->cdr_track_early)
1954 axgbe_phy_cdr_track(pdata);
1957 static void axgbe_phy_an_post(struct axgbe_port *pdata)
1959 struct axgbe_phy_data *phy_data = pdata->phy_data;
1961 switch (pdata->an_mode) {
1962 case AXGBE_AN_MODE_CL73:
1963 case AXGBE_AN_MODE_CL73_REDRV:
1964 if (phy_data->cur_mode != AXGBE_MODE_KR)
1967 axgbe_phy_cdr_track(pdata);
1969 switch (pdata->an_result) {
1970 case AXGBE_AN_READY:
1971 case AXGBE_AN_COMPLETE:
1974 if (phy_data->phy_cdr_delay < AXGBE_CDR_DELAY_MAX)
1975 phy_data->phy_cdr_delay += AXGBE_CDR_DELAY_INC;
1984 static void axgbe_phy_an_pre(struct axgbe_port *pdata)
1986 struct axgbe_phy_data *phy_data = pdata->phy_data;
1988 switch (pdata->an_mode) {
1989 case AXGBE_AN_MODE_CL73:
1990 case AXGBE_AN_MODE_CL73_REDRV:
1991 if (phy_data->cur_mode != AXGBE_MODE_KR)
1994 axgbe_phy_cdr_notrack(pdata);
2001 static void axgbe_phy_stop(struct axgbe_port *pdata)
2003 struct axgbe_phy_data *phy_data = pdata->phy_data;
2005 /* Reset SFP data */
2006 axgbe_phy_sfp_reset(phy_data);
2007 axgbe_phy_sfp_mod_absent(pdata);
2009 /* Reset CDR support */
2010 axgbe_phy_cdr_track(pdata);
2012 /* Power off the PHY */
2013 axgbe_phy_power_off(pdata);
2015 /* Stop the I2C controller */
2016 pdata->i2c_if.i2c_stop(pdata);
2019 static int axgbe_phy_start(struct axgbe_port *pdata)
2021 struct axgbe_phy_data *phy_data = pdata->phy_data;
2024 /* Start the I2C controller */
2025 ret = pdata->i2c_if.i2c_start(pdata);
2029 /* Start in highest supported mode */
2030 axgbe_phy_set_mode(pdata, phy_data->start_mode);
2032 /* Reset CDR support */
2033 axgbe_phy_cdr_track(pdata);
2035 /* After starting the I2C controller, we can check for an SFP */
2036 switch (phy_data->port_mode) {
2037 case AXGBE_PORT_MODE_SFP:
2038 axgbe_phy_sfp_detect(pdata);
2043 pdata->phy.advertising &= axgbe_phy_an_advertising(pdata);
2048 static int axgbe_phy_reset(struct axgbe_port *pdata)
2050 struct axgbe_phy_data *phy_data = pdata->phy_data;
2051 enum axgbe_mode cur_mode;
2053 /* Reset by power cycling the PHY */
2054 cur_mode = phy_data->cur_mode;
2055 axgbe_phy_power_off(pdata);
2056 /* First time reset is done with passed unknown mode*/
2057 axgbe_phy_set_mode(pdata, cur_mode);
2061 static int axgbe_phy_init(struct axgbe_port *pdata)
2063 struct axgbe_phy_data *phy_data;
2067 /* Check if enabled */
2068 if (!axgbe_phy_port_enabled(pdata)) {
2069 PMD_DRV_LOG(ERR, "device is not enabled\n");
2073 /* Initialize the I2C controller */
2074 ret = pdata->i2c_if.i2c_init(pdata);
2078 phy_data = rte_zmalloc("phy_data memory", sizeof(*phy_data), 0);
2080 PMD_DRV_LOG(ERR, "phy_data allocation failed\n");
2083 pdata->phy_data = phy_data;
2085 reg = XP_IOREAD(pdata, XP_PROP_0);
2086 phy_data->port_mode = XP_GET_BITS(reg, XP_PROP_0, PORT_MODE);
2087 phy_data->port_id = XP_GET_BITS(reg, XP_PROP_0, PORT_ID);
2088 phy_data->port_speeds = XP_GET_BITS(reg, XP_PROP_0, PORT_SPEEDS);
2089 phy_data->conn_type = XP_GET_BITS(reg, XP_PROP_0, CONN_TYPE);
2090 phy_data->mdio_addr = XP_GET_BITS(reg, XP_PROP_0, MDIO_ADDR);
2092 reg = XP_IOREAD(pdata, XP_PROP_4);
2093 phy_data->redrv = XP_GET_BITS(reg, XP_PROP_4, REDRV_PRESENT);
2094 phy_data->redrv_if = XP_GET_BITS(reg, XP_PROP_4, REDRV_IF);
2095 phy_data->redrv_addr = XP_GET_BITS(reg, XP_PROP_4, REDRV_ADDR);
2096 phy_data->redrv_lane = XP_GET_BITS(reg, XP_PROP_4, REDRV_LANE);
2097 phy_data->redrv_model = XP_GET_BITS(reg, XP_PROP_4, REDRV_MODEL);
2099 /* Validate the connection requested */
2100 if (axgbe_phy_conn_type_mismatch(pdata)) {
2101 PMD_DRV_LOG(ERR, "phy mode/connection mismatch (%#x/%#x)\n",
2102 phy_data->port_mode, phy_data->conn_type);
2106 /* Validate the mode requested */
2107 if (axgbe_phy_port_mode_mismatch(pdata)) {
2108 PMD_DRV_LOG(ERR, "phy mode/speed mismatch (%#x/%#x)\n",
2109 phy_data->port_mode, phy_data->port_speeds);
2113 /* Check for and validate MDIO reset support */
2114 ret = axgbe_phy_mdio_reset_setup(pdata);
2118 /* Validate the re-driver information */
2119 if (axgbe_phy_redrv_error(phy_data)) {
2120 PMD_DRV_LOG(ERR, "phy re-driver settings error\n");
2123 pdata->kr_redrv = phy_data->redrv;
2125 /* Indicate current mode is unknown */
2126 phy_data->cur_mode = AXGBE_MODE_UNKNOWN;
2128 /* Initialize supported features */
2129 pdata->phy.supported = 0;
2131 switch (phy_data->port_mode) {
2132 /* Backplane support */
2133 case AXGBE_PORT_MODE_BACKPLANE:
2134 pdata->phy.supported |= SUPPORTED_Autoneg;
2136 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
2137 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2138 pdata->phy.supported |= SUPPORTED_Backplane;
2139 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) {
2140 pdata->phy.supported |= SUPPORTED_1000baseKX_Full;
2141 phy_data->start_mode = AXGBE_MODE_KX_1000;
2143 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) {
2144 pdata->phy.supported |= SUPPORTED_10000baseKR_Full;
2145 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
2146 pdata->phy.supported |=
2147 SUPPORTED_10000baseR_FEC;
2148 phy_data->start_mode = AXGBE_MODE_KR;
2151 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE;
2153 case AXGBE_PORT_MODE_BACKPLANE_2500:
2154 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2155 pdata->phy.supported |= SUPPORTED_Backplane;
2156 pdata->phy.supported |= SUPPORTED_2500baseX_Full;
2157 phy_data->start_mode = AXGBE_MODE_KX_2500;
2159 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE;
2162 /* MDIO 1GBase-T support */
2163 case AXGBE_PORT_MODE_1000BASE_T:
2164 pdata->phy.supported |= SUPPORTED_Autoneg;
2165 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2166 pdata->phy.supported |= SUPPORTED_TP;
2167 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) {
2168 pdata->phy.supported |= SUPPORTED_100baseT_Full;
2169 phy_data->start_mode = AXGBE_MODE_SGMII_100;
2171 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) {
2172 pdata->phy.supported |= SUPPORTED_1000baseT_Full;
2173 phy_data->start_mode = AXGBE_MODE_SGMII_1000;
2176 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL22;
2179 /* MDIO Base-X support */
2180 case AXGBE_PORT_MODE_1000BASE_X:
2181 pdata->phy.supported |= SUPPORTED_Autoneg;
2182 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2183 pdata->phy.supported |= SUPPORTED_FIBRE;
2184 pdata->phy.supported |= SUPPORTED_1000baseT_Full;
2185 phy_data->start_mode = AXGBE_MODE_X;
2187 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL22;
2190 /* MDIO NBase-T support */
2191 case AXGBE_PORT_MODE_NBASE_T:
2192 pdata->phy.supported |= SUPPORTED_Autoneg;
2193 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2194 pdata->phy.supported |= SUPPORTED_TP;
2195 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) {
2196 pdata->phy.supported |= SUPPORTED_100baseT_Full;
2197 phy_data->start_mode = AXGBE_MODE_SGMII_100;
2199 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) {
2200 pdata->phy.supported |= SUPPORTED_1000baseT_Full;
2201 phy_data->start_mode = AXGBE_MODE_SGMII_1000;
2203 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_2500) {
2204 pdata->phy.supported |= SUPPORTED_2500baseX_Full;
2205 phy_data->start_mode = AXGBE_MODE_KX_2500;
2208 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL45;
2211 /* 10GBase-T support */
2212 case AXGBE_PORT_MODE_10GBASE_T:
2213 pdata->phy.supported |= SUPPORTED_Autoneg;
2214 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2215 pdata->phy.supported |= SUPPORTED_TP;
2216 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) {
2217 pdata->phy.supported |= SUPPORTED_100baseT_Full;
2218 phy_data->start_mode = AXGBE_MODE_SGMII_100;
2220 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) {
2221 pdata->phy.supported |= SUPPORTED_1000baseT_Full;
2222 phy_data->start_mode = AXGBE_MODE_SGMII_1000;
2224 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) {
2225 pdata->phy.supported |= SUPPORTED_10000baseT_Full;
2226 phy_data->start_mode = AXGBE_MODE_KR;
2229 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE;
2232 /* 10GBase-R support */
2233 case AXGBE_PORT_MODE_10GBASE_R:
2234 pdata->phy.supported |= SUPPORTED_Autoneg;
2235 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2236 pdata->phy.supported |= SUPPORTED_TP;
2237 pdata->phy.supported |= SUPPORTED_10000baseT_Full;
2238 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
2239 pdata->phy.supported |= SUPPORTED_10000baseR_FEC;
2240 phy_data->start_mode = AXGBE_MODE_SFI;
2242 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE;
2246 case AXGBE_PORT_MODE_SFP:
2247 pdata->phy.supported |= SUPPORTED_Autoneg;
2248 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2249 pdata->phy.supported |= SUPPORTED_TP;
2250 pdata->phy.supported |= SUPPORTED_FIBRE;
2251 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) {
2252 pdata->phy.supported |= SUPPORTED_100baseT_Full;
2253 phy_data->start_mode = AXGBE_MODE_SGMII_100;
2255 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) {
2256 pdata->phy.supported |= SUPPORTED_1000baseT_Full;
2257 phy_data->start_mode = AXGBE_MODE_SGMII_1000;
2259 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) {
2260 pdata->phy.supported |= SUPPORTED_10000baseT_Full;
2261 phy_data->start_mode = AXGBE_MODE_SFI;
2262 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
2263 pdata->phy.supported |=
2264 SUPPORTED_10000baseR_FEC;
2267 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL22;
2269 axgbe_phy_sfp_setup(pdata);
2275 if ((phy_data->conn_type & AXGBE_CONN_TYPE_MDIO) &&
2276 (phy_data->phydev_mode != AXGBE_MDIO_MODE_NONE)) {
2277 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr,
2278 phy_data->phydev_mode);
2280 PMD_DRV_LOG(ERR, "mdio port/clause not compatible (%d/%u)\n",
2281 phy_data->mdio_addr, phy_data->phydev_mode);
2286 if (phy_data->redrv && !phy_data->redrv_if) {
2287 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr,
2288 AXGBE_MDIO_MODE_CL22);
2290 PMD_DRV_LOG(ERR, "redriver mdio port not compatible (%u)\n",
2291 phy_data->redrv_addr);
2296 phy_data->phy_cdr_delay = AXGBE_CDR_DELAY_INIT;
2299 void axgbe_init_function_ptrs_phy_v2(struct axgbe_phy_if *phy_if)
2301 struct axgbe_phy_impl_if *phy_impl = &phy_if->phy_impl;
2303 phy_impl->init = axgbe_phy_init;
2304 phy_impl->reset = axgbe_phy_reset;
2305 phy_impl->start = axgbe_phy_start;
2306 phy_impl->stop = axgbe_phy_stop;
2307 phy_impl->link_status = axgbe_phy_link_status;
2308 phy_impl->use_mode = axgbe_phy_use_mode;
2309 phy_impl->set_mode = axgbe_phy_set_mode;
2310 phy_impl->get_mode = axgbe_phy_get_mode;
2311 phy_impl->switch_mode = axgbe_phy_switch_mode;
2312 phy_impl->cur_mode = axgbe_phy_cur_mode;
2313 phy_impl->an_mode = axgbe_phy_an_mode;
2314 phy_impl->an_config = axgbe_phy_an_config;
2315 phy_impl->an_advertising = axgbe_phy_an_advertising;
2316 phy_impl->an_outcome = axgbe_phy_an_outcome;
2318 phy_impl->an_pre = axgbe_phy_an_pre;
2319 phy_impl->an_post = axgbe_phy_an_post;
2321 phy_impl->kr_training_pre = axgbe_phy_kr_training_pre;
2322 phy_impl->kr_training_post = axgbe_phy_kr_training_post;