1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved.
3 * Copyright(c) 2018 Synopsys, Inc. All rights reserved.
6 #include "axgbe_ethdev.h"
7 #include "axgbe_common.h"
10 #define AXGBE_PHY_PORT_SPEED_100 BIT(0)
11 #define AXGBE_PHY_PORT_SPEED_1000 BIT(1)
12 #define AXGBE_PHY_PORT_SPEED_2500 BIT(2)
13 #define AXGBE_PHY_PORT_SPEED_10000 BIT(3)
15 #define AXGBE_MUTEX_RELEASE 0x80000000
17 #define AXGBE_SFP_DIRECT 7
19 /* I2C target addresses */
20 #define AXGBE_SFP_SERIAL_ID_ADDRESS 0x50
21 #define AXGBE_SFP_DIAG_INFO_ADDRESS 0x51
22 #define AXGBE_SFP_PHY_ADDRESS 0x56
23 #define AXGBE_GPIO_ADDRESS_PCA9555 0x20
25 /* SFP sideband signal indicators */
26 #define AXGBE_GPIO_NO_TX_FAULT BIT(0)
27 #define AXGBE_GPIO_NO_RATE_SELECT BIT(1)
28 #define AXGBE_GPIO_NO_MOD_ABSENT BIT(2)
29 #define AXGBE_GPIO_NO_RX_LOS BIT(3)
31 /* Rate-change complete wait/retry count */
32 #define AXGBE_RATECHANGE_COUNT 500
34 /* CDR delay values for KR support (in usec) */
35 #define AXGBE_CDR_DELAY_INIT 10000
36 #define AXGBE_CDR_DELAY_INC 10000
37 #define AXGBE_CDR_DELAY_MAX 100000
39 enum axgbe_port_mode {
40 AXGBE_PORT_MODE_RSVD = 0,
41 AXGBE_PORT_MODE_BACKPLANE,
42 AXGBE_PORT_MODE_BACKPLANE_2500,
43 AXGBE_PORT_MODE_1000BASE_T,
44 AXGBE_PORT_MODE_1000BASE_X,
45 AXGBE_PORT_MODE_NBASE_T,
46 AXGBE_PORT_MODE_10GBASE_T,
47 AXGBE_PORT_MODE_10GBASE_R,
52 enum axgbe_conn_type {
53 AXGBE_CONN_TYPE_NONE = 0,
56 AXGBE_CONN_TYPE_RSVD1,
57 AXGBE_CONN_TYPE_BACKPLANE,
61 /* SFP/SFP+ related definitions */
63 AXGBE_SFP_COMM_DIRECT = 0,
64 AXGBE_SFP_COMM_PCA9545,
67 enum axgbe_sfp_cable {
68 AXGBE_SFP_CABLE_UNKNOWN = 0,
69 AXGBE_SFP_CABLE_ACTIVE,
70 AXGBE_SFP_CABLE_PASSIVE,
74 AXGBE_SFP_BASE_UNKNOWN = 0,
75 AXGBE_SFP_BASE_1000_T,
76 AXGBE_SFP_BASE_1000_SX,
77 AXGBE_SFP_BASE_1000_LX,
78 AXGBE_SFP_BASE_1000_CX,
79 AXGBE_SFP_BASE_10000_SR,
80 AXGBE_SFP_BASE_10000_LR,
81 AXGBE_SFP_BASE_10000_LRM,
82 AXGBE_SFP_BASE_10000_ER,
83 AXGBE_SFP_BASE_10000_CR,
86 enum axgbe_sfp_speed {
87 AXGBE_SFP_SPEED_UNKNOWN = 0,
88 AXGBE_SFP_SPEED_100_1000,
90 AXGBE_SFP_SPEED_10000,
93 /* SFP Serial ID Base ID values relative to an offset of 0 */
94 #define AXGBE_SFP_BASE_ID 0
95 #define AXGBE_SFP_ID_SFP 0x03
97 #define AXGBE_SFP_BASE_EXT_ID 1
98 #define AXGBE_SFP_EXT_ID_SFP 0x04
100 #define AXGBE_SFP_BASE_10GBE_CC 3
101 #define AXGBE_SFP_BASE_10GBE_CC_SR BIT(4)
102 #define AXGBE_SFP_BASE_10GBE_CC_LR BIT(5)
103 #define AXGBE_SFP_BASE_10GBE_CC_LRM BIT(6)
104 #define AXGBE_SFP_BASE_10GBE_CC_ER BIT(7)
106 #define AXGBE_SFP_BASE_1GBE_CC 6
107 #define AXGBE_SFP_BASE_1GBE_CC_SX BIT(0)
108 #define AXGBE_SFP_BASE_1GBE_CC_LX BIT(1)
109 #define AXGBE_SFP_BASE_1GBE_CC_CX BIT(2)
110 #define AXGBE_SFP_BASE_1GBE_CC_T BIT(3)
112 #define AXGBE_SFP_BASE_CABLE 8
113 #define AXGBE_SFP_BASE_CABLE_PASSIVE BIT(2)
114 #define AXGBE_SFP_BASE_CABLE_ACTIVE BIT(3)
116 #define AXGBE_SFP_BASE_BR 12
117 #define AXGBE_SFP_BASE_BR_1GBE_MIN 0x0a
118 #define AXGBE_SFP_BASE_BR_1GBE_MAX 0x0d
119 #define AXGBE_SFP_BASE_BR_10GBE_MIN 0x64
120 #define AXGBE_SFP_BASE_BR_10GBE_MAX 0x68
122 #define AXGBE_SFP_BASE_CU_CABLE_LEN 18
124 #define AXGBE_SFP_BASE_VENDOR_NAME 20
125 #define AXGBE_SFP_BASE_VENDOR_NAME_LEN 16
126 #define AXGBE_SFP_BASE_VENDOR_PN 40
127 #define AXGBE_SFP_BASE_VENDOR_PN_LEN 16
128 #define AXGBE_SFP_BASE_VENDOR_REV 56
129 #define AXGBE_SFP_BASE_VENDOR_REV_LEN 4
131 #define AXGBE_SFP_BASE_CC 63
133 /* SFP Serial ID Extended ID values relative to an offset of 64 */
134 #define AXGBE_SFP_BASE_VENDOR_SN 4
135 #define AXGBE_SFP_BASE_VENDOR_SN_LEN 16
137 #define AXGBE_SFP_EXTD_DIAG 28
138 #define AXGBE_SFP_EXTD_DIAG_ADDR_CHANGE BIT(2)
140 #define AXGBE_SFP_EXTD_SFF_8472 30
142 #define AXGBE_SFP_EXTD_CC 31
144 struct axgbe_sfp_eeprom {
150 #define AXGBE_BEL_FUSE_VENDOR "BEL-FUSE"
151 #define AXGBE_BEL_FUSE_PARTNO "1GBT-SFP06"
153 struct axgbe_sfp_ascii {
155 char vendor[AXGBE_SFP_BASE_VENDOR_NAME_LEN + 1];
156 char partno[AXGBE_SFP_BASE_VENDOR_PN_LEN + 1];
157 char rev[AXGBE_SFP_BASE_VENDOR_REV_LEN + 1];
158 char serno[AXGBE_SFP_BASE_VENDOR_SN_LEN + 1];
162 /* MDIO PHY reset types */
163 enum axgbe_mdio_reset {
164 AXGBE_MDIO_RESET_NONE = 0,
165 AXGBE_MDIO_RESET_I2C_GPIO,
166 AXGBE_MDIO_RESET_INT_GPIO,
167 AXGBE_MDIO_RESET_MAX,
170 /* Re-driver related definitions */
171 enum axgbe_phy_redrv_if {
172 AXGBE_PHY_REDRV_IF_MDIO = 0,
173 AXGBE_PHY_REDRV_IF_I2C,
174 AXGBE_PHY_REDRV_IF_MAX,
177 enum axgbe_phy_redrv_model {
178 AXGBE_PHY_REDRV_MODEL_4223 = 0,
179 AXGBE_PHY_REDRV_MODEL_4227,
180 AXGBE_PHY_REDRV_MODEL_MAX,
183 enum axgbe_phy_redrv_mode {
184 AXGBE_PHY_REDRV_MODE_CX = 5,
185 AXGBE_PHY_REDRV_MODE_SR = 9,
188 #define AXGBE_PHY_REDRV_MODE_REG 0x12b0
190 /* PHY related configuration information */
191 struct axgbe_phy_data {
192 enum axgbe_port_mode port_mode;
194 unsigned int port_id;
196 unsigned int port_speeds;
198 enum axgbe_conn_type conn_type;
200 enum axgbe_mode cur_mode;
201 enum axgbe_mode start_mode;
203 unsigned int rrc_count;
205 unsigned int mdio_addr;
207 unsigned int comm_owned;
210 enum axgbe_sfp_comm sfp_comm;
211 unsigned int sfp_mux_address;
212 unsigned int sfp_mux_channel;
214 unsigned int sfp_gpio_address;
215 unsigned int sfp_gpio_mask;
216 unsigned int sfp_gpio_rx_los;
217 unsigned int sfp_gpio_tx_fault;
218 unsigned int sfp_gpio_mod_absent;
219 unsigned int sfp_gpio_rate_select;
221 unsigned int sfp_rx_los;
222 unsigned int sfp_tx_fault;
223 unsigned int sfp_mod_absent;
224 unsigned int sfp_diags;
225 unsigned int sfp_changed;
226 unsigned int sfp_phy_avail;
227 unsigned int sfp_cable_len;
228 enum axgbe_sfp_base sfp_base;
229 enum axgbe_sfp_cable sfp_cable;
230 enum axgbe_sfp_speed sfp_speed;
231 struct axgbe_sfp_eeprom sfp_eeprom;
233 /* External PHY support */
234 enum axgbe_mdio_mode phydev_mode;
235 enum axgbe_mdio_reset mdio_reset;
236 unsigned int mdio_reset_addr;
237 unsigned int mdio_reset_gpio;
239 /* Re-driver support */
241 unsigned int redrv_if;
242 unsigned int redrv_addr;
243 unsigned int redrv_lane;
244 unsigned int redrv_model;
247 unsigned int phy_cdr_notrack;
248 unsigned int phy_cdr_delay;
251 static enum axgbe_an_mode axgbe_phy_an_mode(struct axgbe_port *pdata);
253 static int axgbe_phy_i2c_xfer(struct axgbe_port *pdata,
254 struct axgbe_i2c_op *i2c_op)
256 struct axgbe_phy_data *phy_data = pdata->phy_data;
258 /* Be sure we own the bus */
259 if (!phy_data->comm_owned)
262 return pdata->i2c_if.i2c_xfer(pdata, i2c_op);
265 static int axgbe_phy_redrv_write(struct axgbe_port *pdata, unsigned int reg,
268 struct axgbe_phy_data *phy_data = pdata->phy_data;
269 struct axgbe_i2c_op i2c_op;
271 u8 redrv_data[5], csum;
272 unsigned int i, retry;
275 /* High byte of register contains read/write indicator */
276 redrv_data[0] = ((reg >> 8) & 0xff) << 1;
277 redrv_data[1] = reg & 0xff;
278 redrv_val = (uint16_t *)&redrv_data[2];
279 *redrv_val = rte_cpu_to_be_16(val);
281 /* Calculate 1 byte checksum */
283 for (i = 0; i < 4; i++) {
284 csum += redrv_data[i];
285 if (redrv_data[i] > csum)
288 redrv_data[4] = ~csum;
292 i2c_op.cmd = AXGBE_I2C_CMD_WRITE;
293 i2c_op.target = phy_data->redrv_addr;
294 i2c_op.len = sizeof(redrv_data);
295 i2c_op.buf = redrv_data;
296 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op);
298 if ((ret == -EAGAIN) && retry--)
306 i2c_op.cmd = AXGBE_I2C_CMD_READ;
307 i2c_op.target = phy_data->redrv_addr;
309 i2c_op.buf = redrv_data;
310 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op);
312 if ((ret == -EAGAIN) && retry--)
318 if (redrv_data[0] != 0xff) {
319 PMD_DRV_LOG(ERR, "Redriver write checksum error\n");
326 static int axgbe_phy_i2c_read(struct axgbe_port *pdata, unsigned int target,
327 void *reg, unsigned int reg_len,
328 void *val, unsigned int val_len)
330 struct axgbe_i2c_op i2c_op;
335 /* Set the specified register to read */
336 i2c_op.cmd = AXGBE_I2C_CMD_WRITE;
337 i2c_op.target = target;
338 i2c_op.len = reg_len;
340 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op);
342 if ((ret == -EAGAIN) && retry--)
350 /* Read the specfied register */
351 i2c_op.cmd = AXGBE_I2C_CMD_READ;
352 i2c_op.target = target;
353 i2c_op.len = val_len;
355 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op);
356 if ((ret == -EAGAIN) && retry--)
362 static int axgbe_phy_sfp_put_mux(struct axgbe_port *pdata)
364 struct axgbe_phy_data *phy_data = pdata->phy_data;
365 struct axgbe_i2c_op i2c_op;
368 if (phy_data->sfp_comm == AXGBE_SFP_COMM_DIRECT)
371 /* Select no mux channels */
373 i2c_op.cmd = AXGBE_I2C_CMD_WRITE;
374 i2c_op.target = phy_data->sfp_mux_address;
375 i2c_op.len = sizeof(mux_channel);
376 i2c_op.buf = &mux_channel;
378 return axgbe_phy_i2c_xfer(pdata, &i2c_op);
381 static int axgbe_phy_sfp_get_mux(struct axgbe_port *pdata)
383 struct axgbe_phy_data *phy_data = pdata->phy_data;
384 struct axgbe_i2c_op i2c_op;
387 if (phy_data->sfp_comm == AXGBE_SFP_COMM_DIRECT)
390 /* Select desired mux channel */
391 mux_channel = 1 << phy_data->sfp_mux_channel;
392 i2c_op.cmd = AXGBE_I2C_CMD_WRITE;
393 i2c_op.target = phy_data->sfp_mux_address;
394 i2c_op.len = sizeof(mux_channel);
395 i2c_op.buf = &mux_channel;
397 return axgbe_phy_i2c_xfer(pdata, &i2c_op);
400 static void axgbe_phy_put_comm_ownership(struct axgbe_port *pdata)
402 struct axgbe_phy_data *phy_data = pdata->phy_data;
404 phy_data->comm_owned = 0;
406 pthread_mutex_unlock(&pdata->phy_mutex);
409 static int axgbe_phy_get_comm_ownership(struct axgbe_port *pdata)
411 struct axgbe_phy_data *phy_data = pdata->phy_data;
413 unsigned int mutex_id;
415 /* The I2C and MDIO/GPIO bus is multiplexed between multiple devices,
416 * the driver needs to take the software mutex and then the hardware
417 * mutexes before being able to use the busses.
419 pthread_mutex_lock(&pdata->phy_mutex);
421 if (phy_data->comm_owned)
424 /* Clear the mutexes */
425 XP_IOWRITE(pdata, XP_I2C_MUTEX, AXGBE_MUTEX_RELEASE);
426 XP_IOWRITE(pdata, XP_MDIO_MUTEX, AXGBE_MUTEX_RELEASE);
428 /* Mutex formats are the same for I2C and MDIO/GPIO */
430 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ID, phy_data->port_id);
431 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ACTIVE, 1);
433 timeout = rte_get_timer_cycles() + (rte_get_timer_hz() * 5);
434 while (time_before(rte_get_timer_cycles(), timeout)) {
435 /* Must be all zeroes in order to obtain the mutex */
436 if (XP_IOREAD(pdata, XP_I2C_MUTEX) ||
437 XP_IOREAD(pdata, XP_MDIO_MUTEX)) {
442 /* Obtain the mutex */
443 XP_IOWRITE(pdata, XP_I2C_MUTEX, mutex_id);
444 XP_IOWRITE(pdata, XP_MDIO_MUTEX, mutex_id);
446 phy_data->comm_owned = 1;
450 pthread_mutex_unlock(&pdata->phy_mutex);
452 PMD_DRV_LOG(ERR, "unable to obtain hardware mutexes\n");
457 static void axgbe_phy_sfp_phy_settings(struct axgbe_port *pdata)
459 struct axgbe_phy_data *phy_data = pdata->phy_data;
461 if (phy_data->sfp_mod_absent) {
462 pdata->phy.speed = SPEED_UNKNOWN;
463 pdata->phy.duplex = DUPLEX_UNKNOWN;
464 pdata->phy.autoneg = AUTONEG_ENABLE;
465 pdata->phy.advertising = pdata->phy.supported;
468 pdata->phy.advertising &= ~ADVERTISED_Autoneg;
469 pdata->phy.advertising &= ~ADVERTISED_TP;
470 pdata->phy.advertising &= ~ADVERTISED_FIBRE;
471 pdata->phy.advertising &= ~ADVERTISED_100baseT_Full;
472 pdata->phy.advertising &= ~ADVERTISED_1000baseT_Full;
473 pdata->phy.advertising &= ~ADVERTISED_10000baseT_Full;
474 pdata->phy.advertising &= ~ADVERTISED_10000baseR_FEC;
476 switch (phy_data->sfp_base) {
477 case AXGBE_SFP_BASE_1000_T:
478 case AXGBE_SFP_BASE_1000_SX:
479 case AXGBE_SFP_BASE_1000_LX:
480 case AXGBE_SFP_BASE_1000_CX:
481 pdata->phy.speed = SPEED_UNKNOWN;
482 pdata->phy.duplex = DUPLEX_UNKNOWN;
483 pdata->phy.autoneg = AUTONEG_ENABLE;
484 pdata->phy.advertising |= ADVERTISED_Autoneg;
486 case AXGBE_SFP_BASE_10000_SR:
487 case AXGBE_SFP_BASE_10000_LR:
488 case AXGBE_SFP_BASE_10000_LRM:
489 case AXGBE_SFP_BASE_10000_ER:
490 case AXGBE_SFP_BASE_10000_CR:
492 pdata->phy.speed = SPEED_10000;
493 pdata->phy.duplex = DUPLEX_FULL;
494 pdata->phy.autoneg = AUTONEG_DISABLE;
498 switch (phy_data->sfp_base) {
499 case AXGBE_SFP_BASE_1000_T:
500 case AXGBE_SFP_BASE_1000_CX:
501 case AXGBE_SFP_BASE_10000_CR:
502 pdata->phy.advertising |= ADVERTISED_TP;
505 pdata->phy.advertising |= ADVERTISED_FIBRE;
508 switch (phy_data->sfp_speed) {
509 case AXGBE_SFP_SPEED_100_1000:
510 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100)
511 pdata->phy.advertising |= ADVERTISED_100baseT_Full;
512 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000)
513 pdata->phy.advertising |= ADVERTISED_1000baseT_Full;
515 case AXGBE_SFP_SPEED_1000:
516 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000)
517 pdata->phy.advertising |= ADVERTISED_1000baseT_Full;
519 case AXGBE_SFP_SPEED_10000:
520 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000)
521 pdata->phy.advertising |= ADVERTISED_10000baseT_Full;
524 /* Choose the fastest supported speed */
525 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000)
526 pdata->phy.advertising |= ADVERTISED_10000baseT_Full;
527 else if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000)
528 pdata->phy.advertising |= ADVERTISED_1000baseT_Full;
529 else if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100)
530 pdata->phy.advertising |= ADVERTISED_100baseT_Full;
534 static bool axgbe_phy_sfp_bit_rate(struct axgbe_sfp_eeprom *sfp_eeprom,
535 enum axgbe_sfp_speed sfp_speed)
537 u8 *sfp_base, min, max;
539 sfp_base = sfp_eeprom->base;
542 case AXGBE_SFP_SPEED_1000:
543 min = AXGBE_SFP_BASE_BR_1GBE_MIN;
544 max = AXGBE_SFP_BASE_BR_1GBE_MAX;
546 case AXGBE_SFP_SPEED_10000:
547 min = AXGBE_SFP_BASE_BR_10GBE_MIN;
548 max = AXGBE_SFP_BASE_BR_10GBE_MAX;
554 return ((sfp_base[AXGBE_SFP_BASE_BR] >= min) &&
555 (sfp_base[AXGBE_SFP_BASE_BR] <= max));
558 static void axgbe_phy_sfp_external_phy(struct axgbe_port *pdata)
560 struct axgbe_phy_data *phy_data = pdata->phy_data;
562 if (!phy_data->sfp_changed)
565 phy_data->sfp_phy_avail = 0;
567 if (phy_data->sfp_base != AXGBE_SFP_BASE_1000_T)
571 static bool axgbe_phy_belfuse_parse_quirks(struct axgbe_port *pdata)
573 struct axgbe_phy_data *phy_data = pdata->phy_data;
574 struct axgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
576 if (memcmp(&sfp_eeprom->base[AXGBE_SFP_BASE_VENDOR_NAME],
577 AXGBE_BEL_FUSE_VENDOR, strlen(AXGBE_BEL_FUSE_VENDOR)))
580 if (!memcmp(&sfp_eeprom->base[AXGBE_SFP_BASE_VENDOR_PN],
581 AXGBE_BEL_FUSE_PARTNO, strlen(AXGBE_BEL_FUSE_PARTNO))) {
582 phy_data->sfp_base = AXGBE_SFP_BASE_1000_SX;
583 phy_data->sfp_cable = AXGBE_SFP_CABLE_ACTIVE;
584 phy_data->sfp_speed = AXGBE_SFP_SPEED_1000;
591 static bool axgbe_phy_sfp_parse_quirks(struct axgbe_port *pdata)
593 if (axgbe_phy_belfuse_parse_quirks(pdata))
599 static void axgbe_phy_sfp_parse_eeprom(struct axgbe_port *pdata)
601 struct axgbe_phy_data *phy_data = pdata->phy_data;
602 struct axgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
605 sfp_base = sfp_eeprom->base;
607 if (sfp_base[AXGBE_SFP_BASE_ID] != AXGBE_SFP_ID_SFP)
610 if (sfp_base[AXGBE_SFP_BASE_EXT_ID] != AXGBE_SFP_EXT_ID_SFP)
613 axgbe_phy_sfp_parse_quirks(pdata);
615 /* Assume ACTIVE cable unless told it is PASSIVE */
616 if (sfp_base[AXGBE_SFP_BASE_CABLE] & AXGBE_SFP_BASE_CABLE_PASSIVE) {
617 phy_data->sfp_cable = AXGBE_SFP_CABLE_PASSIVE;
618 phy_data->sfp_cable_len = sfp_base[AXGBE_SFP_BASE_CU_CABLE_LEN];
620 phy_data->sfp_cable = AXGBE_SFP_CABLE_ACTIVE;
623 /* Determine the type of SFP */
624 if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] & AXGBE_SFP_BASE_10GBE_CC_SR)
625 phy_data->sfp_base = AXGBE_SFP_BASE_10000_SR;
626 else if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] & AXGBE_SFP_BASE_10GBE_CC_LR)
627 phy_data->sfp_base = AXGBE_SFP_BASE_10000_LR;
628 else if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] &
629 AXGBE_SFP_BASE_10GBE_CC_LRM)
630 phy_data->sfp_base = AXGBE_SFP_BASE_10000_LRM;
631 else if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] & AXGBE_SFP_BASE_10GBE_CC_ER)
632 phy_data->sfp_base = AXGBE_SFP_BASE_10000_ER;
633 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_SX)
634 phy_data->sfp_base = AXGBE_SFP_BASE_1000_SX;
635 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_LX)
636 phy_data->sfp_base = AXGBE_SFP_BASE_1000_LX;
637 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_CX)
638 phy_data->sfp_base = AXGBE_SFP_BASE_1000_CX;
639 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_T)
640 phy_data->sfp_base = AXGBE_SFP_BASE_1000_T;
641 else if ((phy_data->sfp_cable == AXGBE_SFP_CABLE_PASSIVE) &&
642 axgbe_phy_sfp_bit_rate(sfp_eeprom, AXGBE_SFP_SPEED_10000))
643 phy_data->sfp_base = AXGBE_SFP_BASE_10000_CR;
645 switch (phy_data->sfp_base) {
646 case AXGBE_SFP_BASE_1000_T:
647 phy_data->sfp_speed = AXGBE_SFP_SPEED_100_1000;
649 case AXGBE_SFP_BASE_1000_SX:
650 case AXGBE_SFP_BASE_1000_LX:
651 case AXGBE_SFP_BASE_1000_CX:
652 phy_data->sfp_speed = AXGBE_SFP_SPEED_1000;
654 case AXGBE_SFP_BASE_10000_SR:
655 case AXGBE_SFP_BASE_10000_LR:
656 case AXGBE_SFP_BASE_10000_LRM:
657 case AXGBE_SFP_BASE_10000_ER:
658 case AXGBE_SFP_BASE_10000_CR:
659 phy_data->sfp_speed = AXGBE_SFP_SPEED_10000;
666 static bool axgbe_phy_sfp_verify_eeprom(uint8_t cc_in, uint8_t *buf,
671 for (cc = 0; len; buf++, len--)
674 return (cc == cc_in) ? true : false;
677 static int axgbe_phy_sfp_read_eeprom(struct axgbe_port *pdata)
679 struct axgbe_phy_data *phy_data = pdata->phy_data;
680 struct axgbe_sfp_eeprom sfp_eeprom;
684 ret = axgbe_phy_sfp_get_mux(pdata);
686 PMD_DRV_LOG(ERR, "I2C error setting SFP MUX\n");
690 /* Read the SFP serial ID eeprom */
692 ret = axgbe_phy_i2c_read(pdata, AXGBE_SFP_SERIAL_ID_ADDRESS,
693 &eeprom_addr, sizeof(eeprom_addr),
694 &sfp_eeprom, sizeof(sfp_eeprom));
696 PMD_DRV_LOG(ERR, "I2C error reading SFP EEPROM\n");
700 /* Validate the contents read */
701 if (!axgbe_phy_sfp_verify_eeprom(sfp_eeprom.base[AXGBE_SFP_BASE_CC],
703 sizeof(sfp_eeprom.base) - 1)) {
708 if (!axgbe_phy_sfp_verify_eeprom(sfp_eeprom.extd[AXGBE_SFP_EXTD_CC],
710 sizeof(sfp_eeprom.extd) - 1)) {
715 /* Check for an added or changed SFP */
716 if (memcmp(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom))) {
717 phy_data->sfp_changed = 1;
718 memcpy(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom));
720 if (sfp_eeprom.extd[AXGBE_SFP_EXTD_SFF_8472]) {
722 diag_type = sfp_eeprom.extd[AXGBE_SFP_EXTD_DIAG];
724 if (!(diag_type & AXGBE_SFP_EXTD_DIAG_ADDR_CHANGE))
725 phy_data->sfp_diags = 1;
728 phy_data->sfp_changed = 0;
732 axgbe_phy_sfp_put_mux(pdata);
737 static void axgbe_phy_sfp_signals(struct axgbe_port *pdata)
739 struct axgbe_phy_data *phy_data = pdata->phy_data;
740 unsigned int gpio_input;
741 u8 gpio_reg, gpio_ports[2];
744 /* Read the input port registers */
746 ret = axgbe_phy_i2c_read(pdata, phy_data->sfp_gpio_address,
747 &gpio_reg, sizeof(gpio_reg),
748 gpio_ports, sizeof(gpio_ports));
750 PMD_DRV_LOG(ERR, "I2C error reading SFP GPIOs\n");
754 gpio_input = (gpio_ports[1] << 8) | gpio_ports[0];
756 if (phy_data->sfp_gpio_mask & AXGBE_GPIO_NO_MOD_ABSENT) {
757 /* No GPIO, just assume the module is present for now */
758 phy_data->sfp_mod_absent = 0;
760 if (!(gpio_input & (1 << phy_data->sfp_gpio_mod_absent)))
761 phy_data->sfp_mod_absent = 0;
764 if (!(phy_data->sfp_gpio_mask & AXGBE_GPIO_NO_RX_LOS) &&
765 (gpio_input & (1 << phy_data->sfp_gpio_rx_los)))
766 phy_data->sfp_rx_los = 1;
768 if (!(phy_data->sfp_gpio_mask & AXGBE_GPIO_NO_TX_FAULT) &&
769 (gpio_input & (1 << phy_data->sfp_gpio_tx_fault)))
770 phy_data->sfp_tx_fault = 1;
773 static void axgbe_phy_sfp_mod_absent(struct axgbe_port *pdata)
775 struct axgbe_phy_data *phy_data = pdata->phy_data;
777 phy_data->sfp_mod_absent = 1;
778 phy_data->sfp_phy_avail = 0;
779 memset(&phy_data->sfp_eeprom, 0, sizeof(phy_data->sfp_eeprom));
782 static void axgbe_phy_sfp_reset(struct axgbe_phy_data *phy_data)
784 phy_data->sfp_rx_los = 0;
785 phy_data->sfp_tx_fault = 0;
786 phy_data->sfp_mod_absent = 1;
787 phy_data->sfp_diags = 0;
788 phy_data->sfp_base = AXGBE_SFP_BASE_UNKNOWN;
789 phy_data->sfp_cable = AXGBE_SFP_CABLE_UNKNOWN;
790 phy_data->sfp_speed = AXGBE_SFP_SPEED_UNKNOWN;
793 static void axgbe_phy_sfp_detect(struct axgbe_port *pdata)
795 struct axgbe_phy_data *phy_data = pdata->phy_data;
798 /* Reset the SFP signals and info */
799 axgbe_phy_sfp_reset(phy_data);
801 ret = axgbe_phy_get_comm_ownership(pdata);
805 /* Read the SFP signals and check for module presence */
806 axgbe_phy_sfp_signals(pdata);
807 if (phy_data->sfp_mod_absent) {
808 axgbe_phy_sfp_mod_absent(pdata);
812 ret = axgbe_phy_sfp_read_eeprom(pdata);
814 /* Treat any error as if there isn't an SFP plugged in */
815 axgbe_phy_sfp_reset(phy_data);
816 axgbe_phy_sfp_mod_absent(pdata);
820 axgbe_phy_sfp_parse_eeprom(pdata);
821 axgbe_phy_sfp_external_phy(pdata);
824 axgbe_phy_sfp_phy_settings(pdata);
825 axgbe_phy_put_comm_ownership(pdata);
828 static void axgbe_phy_phydev_flowctrl(struct axgbe_port *pdata)
830 pdata->phy.tx_pause = 0;
831 pdata->phy.rx_pause = 0;
834 static enum axgbe_mode axgbe_phy_an73_redrv_outcome(struct axgbe_port *pdata)
836 struct axgbe_phy_data *phy_data = pdata->phy_data;
837 enum axgbe_mode mode;
838 unsigned int ad_reg, lp_reg;
840 pdata->phy.lp_advertising |= ADVERTISED_Autoneg;
841 pdata->phy.lp_advertising |= ADVERTISED_Backplane;
843 /* Use external PHY to determine flow control */
844 if (pdata->phy.pause_autoneg)
845 axgbe_phy_phydev_flowctrl(pdata);
847 /* Compare Advertisement and Link Partner register 2 */
848 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
849 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
851 pdata->phy.lp_advertising |= ADVERTISED_10000baseKR_Full;
853 pdata->phy.lp_advertising |= ADVERTISED_1000baseKX_Full;
857 switch (phy_data->port_mode) {
858 case AXGBE_PORT_MODE_BACKPLANE:
859 mode = AXGBE_MODE_KR;
862 mode = AXGBE_MODE_SFI;
865 } else if (ad_reg & 0x20) {
866 switch (phy_data->port_mode) {
867 case AXGBE_PORT_MODE_BACKPLANE:
868 mode = AXGBE_MODE_KX_1000;
870 case AXGBE_PORT_MODE_1000BASE_X:
873 case AXGBE_PORT_MODE_SFP:
874 switch (phy_data->sfp_base) {
875 case AXGBE_SFP_BASE_1000_T:
876 mode = AXGBE_MODE_SGMII_1000;
878 case AXGBE_SFP_BASE_1000_SX:
879 case AXGBE_SFP_BASE_1000_LX:
880 case AXGBE_SFP_BASE_1000_CX:
887 mode = AXGBE_MODE_SGMII_1000;
891 mode = AXGBE_MODE_UNKNOWN;
894 /* Compare Advertisement and Link Partner register 3 */
895 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
896 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
898 pdata->phy.lp_advertising |= ADVERTISED_10000baseR_FEC;
903 static enum axgbe_mode axgbe_phy_an73_outcome(struct axgbe_port *pdata)
905 enum axgbe_mode mode;
906 unsigned int ad_reg, lp_reg;
908 pdata->phy.lp_advertising |= ADVERTISED_Autoneg;
909 pdata->phy.lp_advertising |= ADVERTISED_Backplane;
911 /* Compare Advertisement and Link Partner register 1 */
912 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
913 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA);
915 pdata->phy.lp_advertising |= ADVERTISED_Pause;
917 pdata->phy.lp_advertising |= ADVERTISED_Asym_Pause;
919 if (pdata->phy.pause_autoneg) {
920 /* Set flow control based on auto-negotiation result */
921 pdata->phy.tx_pause = 0;
922 pdata->phy.rx_pause = 0;
924 if (ad_reg & lp_reg & 0x400) {
925 pdata->phy.tx_pause = 1;
926 pdata->phy.rx_pause = 1;
927 } else if (ad_reg & lp_reg & 0x800) {
929 pdata->phy.rx_pause = 1;
930 else if (lp_reg & 0x400)
931 pdata->phy.tx_pause = 1;
935 /* Compare Advertisement and Link Partner register 2 */
936 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
937 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
939 pdata->phy.lp_advertising |= ADVERTISED_10000baseKR_Full;
941 pdata->phy.lp_advertising |= ADVERTISED_1000baseKX_Full;
945 mode = AXGBE_MODE_KR;
946 else if (ad_reg & 0x20)
947 mode = AXGBE_MODE_KX_1000;
949 mode = AXGBE_MODE_UNKNOWN;
951 /* Compare Advertisement and Link Partner register 3 */
952 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
953 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
955 pdata->phy.lp_advertising |= ADVERTISED_10000baseR_FEC;
960 static enum axgbe_mode axgbe_phy_an_outcome(struct axgbe_port *pdata)
962 switch (pdata->an_mode) {
963 case AXGBE_AN_MODE_CL73:
964 return axgbe_phy_an73_outcome(pdata);
965 case AXGBE_AN_MODE_CL73_REDRV:
966 return axgbe_phy_an73_redrv_outcome(pdata);
967 case AXGBE_AN_MODE_CL37:
968 case AXGBE_AN_MODE_CL37_SGMII:
970 return AXGBE_MODE_UNKNOWN;
974 static unsigned int axgbe_phy_an_advertising(struct axgbe_port *pdata)
976 struct axgbe_phy_data *phy_data = pdata->phy_data;
977 unsigned int advertising;
979 /* Without a re-driver, just return current advertising */
980 if (!phy_data->redrv)
981 return pdata->phy.advertising;
983 /* With the KR re-driver we need to advertise a single speed */
984 advertising = pdata->phy.advertising;
985 advertising &= ~ADVERTISED_1000baseKX_Full;
986 advertising &= ~ADVERTISED_10000baseKR_Full;
988 switch (phy_data->port_mode) {
989 case AXGBE_PORT_MODE_BACKPLANE:
990 advertising |= ADVERTISED_10000baseKR_Full;
992 case AXGBE_PORT_MODE_BACKPLANE_2500:
993 advertising |= ADVERTISED_1000baseKX_Full;
995 case AXGBE_PORT_MODE_1000BASE_T:
996 case AXGBE_PORT_MODE_1000BASE_X:
997 case AXGBE_PORT_MODE_NBASE_T:
998 advertising |= ADVERTISED_1000baseKX_Full;
1000 case AXGBE_PORT_MODE_10GBASE_T:
1001 PMD_DRV_LOG(ERR, "10GBASE_T mode is not supported\n");
1003 case AXGBE_PORT_MODE_10GBASE_R:
1004 advertising |= ADVERTISED_10000baseKR_Full;
1006 case AXGBE_PORT_MODE_SFP:
1007 switch (phy_data->sfp_base) {
1008 case AXGBE_SFP_BASE_1000_T:
1009 case AXGBE_SFP_BASE_1000_SX:
1010 case AXGBE_SFP_BASE_1000_LX:
1011 case AXGBE_SFP_BASE_1000_CX:
1012 advertising |= ADVERTISED_1000baseKX_Full;
1015 advertising |= ADVERTISED_10000baseKR_Full;
1020 advertising |= ADVERTISED_10000baseKR_Full;
1027 static int axgbe_phy_an_config(struct axgbe_port *pdata __rte_unused)
1030 /* Dummy API since there is no case to support
1031 * external phy devices registred through kerenl apis
1035 static enum axgbe_an_mode axgbe_phy_an_sfp_mode(struct axgbe_phy_data *phy_data)
1037 switch (phy_data->sfp_base) {
1038 case AXGBE_SFP_BASE_1000_T:
1039 return AXGBE_AN_MODE_CL37_SGMII;
1040 case AXGBE_SFP_BASE_1000_SX:
1041 case AXGBE_SFP_BASE_1000_LX:
1042 case AXGBE_SFP_BASE_1000_CX:
1043 return AXGBE_AN_MODE_CL37;
1045 return AXGBE_AN_MODE_NONE;
1049 static enum axgbe_an_mode axgbe_phy_an_mode(struct axgbe_port *pdata)
1051 struct axgbe_phy_data *phy_data = pdata->phy_data;
1053 /* A KR re-driver will always require CL73 AN */
1054 if (phy_data->redrv)
1055 return AXGBE_AN_MODE_CL73_REDRV;
1057 switch (phy_data->port_mode) {
1058 case AXGBE_PORT_MODE_BACKPLANE:
1059 return AXGBE_AN_MODE_CL73;
1060 case AXGBE_PORT_MODE_BACKPLANE_2500:
1061 return AXGBE_AN_MODE_NONE;
1062 case AXGBE_PORT_MODE_1000BASE_T:
1063 return AXGBE_AN_MODE_CL37_SGMII;
1064 case AXGBE_PORT_MODE_1000BASE_X:
1065 return AXGBE_AN_MODE_CL37;
1066 case AXGBE_PORT_MODE_NBASE_T:
1067 return AXGBE_AN_MODE_CL37_SGMII;
1068 case AXGBE_PORT_MODE_10GBASE_T:
1069 return AXGBE_AN_MODE_CL73;
1070 case AXGBE_PORT_MODE_10GBASE_R:
1071 return AXGBE_AN_MODE_NONE;
1072 case AXGBE_PORT_MODE_SFP:
1073 return axgbe_phy_an_sfp_mode(phy_data);
1075 return AXGBE_AN_MODE_NONE;
1079 static int axgbe_phy_set_redrv_mode_mdio(struct axgbe_port *pdata,
1080 enum axgbe_phy_redrv_mode mode)
1082 struct axgbe_phy_data *phy_data = pdata->phy_data;
1083 u16 redrv_reg, redrv_val;
1085 redrv_reg = AXGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
1086 redrv_val = (u16)mode;
1088 return pdata->hw_if.write_ext_mii_regs(pdata, phy_data->redrv_addr,
1089 redrv_reg, redrv_val);
1092 static int axgbe_phy_set_redrv_mode_i2c(struct axgbe_port *pdata,
1093 enum axgbe_phy_redrv_mode mode)
1095 struct axgbe_phy_data *phy_data = pdata->phy_data;
1096 unsigned int redrv_reg;
1099 /* Calculate the register to write */
1100 redrv_reg = AXGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
1102 ret = axgbe_phy_redrv_write(pdata, redrv_reg, mode);
1107 static void axgbe_phy_set_redrv_mode(struct axgbe_port *pdata)
1109 struct axgbe_phy_data *phy_data = pdata->phy_data;
1110 enum axgbe_phy_redrv_mode mode;
1113 if (!phy_data->redrv)
1116 mode = AXGBE_PHY_REDRV_MODE_CX;
1117 if ((phy_data->port_mode == AXGBE_PORT_MODE_SFP) &&
1118 (phy_data->sfp_base != AXGBE_SFP_BASE_1000_CX) &&
1119 (phy_data->sfp_base != AXGBE_SFP_BASE_10000_CR))
1120 mode = AXGBE_PHY_REDRV_MODE_SR;
1122 ret = axgbe_phy_get_comm_ownership(pdata);
1126 if (phy_data->redrv_if)
1127 axgbe_phy_set_redrv_mode_i2c(pdata, mode);
1129 axgbe_phy_set_redrv_mode_mdio(pdata, mode);
1131 axgbe_phy_put_comm_ownership(pdata);
1134 static void axgbe_phy_start_ratechange(struct axgbe_port *pdata)
1136 if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
1140 static void axgbe_phy_complete_ratechange(struct axgbe_port *pdata)
1144 /* Wait for command to complete */
1145 wait = AXGBE_RATECHANGE_COUNT;
1147 if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
1154 static void axgbe_phy_rrc(struct axgbe_port *pdata)
1158 axgbe_phy_start_ratechange(pdata);
1160 /* Receiver Reset Cycle */
1162 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 5);
1163 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0);
1165 /* Call FW to make the change */
1166 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
1167 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
1168 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
1170 axgbe_phy_complete_ratechange(pdata);
1173 static void axgbe_phy_power_off(struct axgbe_port *pdata)
1175 struct axgbe_phy_data *phy_data = pdata->phy_data;
1177 axgbe_phy_start_ratechange(pdata);
1179 /* Call FW to make the change */
1180 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, 0);
1181 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
1182 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
1183 axgbe_phy_complete_ratechange(pdata);
1184 phy_data->cur_mode = AXGBE_MODE_UNKNOWN;
1187 static void axgbe_phy_sfi_mode(struct axgbe_port *pdata)
1189 struct axgbe_phy_data *phy_data = pdata->phy_data;
1192 axgbe_phy_set_redrv_mode(pdata);
1194 axgbe_phy_start_ratechange(pdata);
1198 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 3);
1199 if (phy_data->sfp_cable != AXGBE_SFP_CABLE_PASSIVE) {
1200 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0);
1202 if (phy_data->sfp_cable_len <= 1)
1203 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 1);
1204 else if (phy_data->sfp_cable_len <= 3)
1205 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 2);
1207 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 3);
1210 /* Call FW to make the change */
1211 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
1212 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
1213 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
1214 axgbe_phy_complete_ratechange(pdata);
1215 phy_data->cur_mode = AXGBE_MODE_SFI;
1218 static void axgbe_phy_kr_mode(struct axgbe_port *pdata)
1220 struct axgbe_phy_data *phy_data = pdata->phy_data;
1223 axgbe_phy_set_redrv_mode(pdata);
1225 axgbe_phy_start_ratechange(pdata);
1229 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 4);
1230 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0);
1232 /* Call FW to make the change */
1233 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
1234 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
1235 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
1236 axgbe_phy_complete_ratechange(pdata);
1237 phy_data->cur_mode = AXGBE_MODE_KR;
1240 static void axgbe_phy_kx_2500_mode(struct axgbe_port *pdata)
1242 struct axgbe_phy_data *phy_data = pdata->phy_data;
1245 axgbe_phy_set_redrv_mode(pdata);
1247 axgbe_phy_start_ratechange(pdata);
1249 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 2);
1250 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0);
1252 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
1253 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
1255 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
1257 phy_data->cur_mode = AXGBE_MODE_KX_2500;
1260 static void axgbe_phy_sgmii_1000_mode(struct axgbe_port *pdata)
1262 struct axgbe_phy_data *phy_data = pdata->phy_data;
1265 axgbe_phy_set_redrv_mode(pdata);
1268 axgbe_phy_start_ratechange(pdata);
1270 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 1);
1271 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 2);
1273 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
1274 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
1276 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
1278 phy_data->cur_mode = AXGBE_MODE_SGMII_1000;
1281 static enum axgbe_mode axgbe_phy_cur_mode(struct axgbe_port *pdata)
1283 struct axgbe_phy_data *phy_data = pdata->phy_data;
1285 return phy_data->cur_mode;
1288 static enum axgbe_mode axgbe_phy_switch_baset_mode(struct axgbe_port *pdata)
1290 struct axgbe_phy_data *phy_data = pdata->phy_data;
1292 /* No switching if not 10GBase-T */
1293 if (phy_data->port_mode != AXGBE_PORT_MODE_10GBASE_T)
1294 return axgbe_phy_cur_mode(pdata);
1296 switch (axgbe_phy_cur_mode(pdata)) {
1297 case AXGBE_MODE_SGMII_100:
1298 case AXGBE_MODE_SGMII_1000:
1299 return AXGBE_MODE_KR;
1302 return AXGBE_MODE_SGMII_1000;
1306 static enum axgbe_mode axgbe_phy_switch_bp_2500_mode(struct axgbe_port *pdata
1309 return AXGBE_MODE_KX_2500;
1312 static enum axgbe_mode axgbe_phy_switch_bp_mode(struct axgbe_port *pdata)
1314 /* If we are in KR switch to KX, and vice-versa */
1315 switch (axgbe_phy_cur_mode(pdata)) {
1316 case AXGBE_MODE_KX_1000:
1317 return AXGBE_MODE_KR;
1320 return AXGBE_MODE_KX_1000;
1324 static enum axgbe_mode axgbe_phy_switch_mode(struct axgbe_port *pdata)
1326 struct axgbe_phy_data *phy_data = pdata->phy_data;
1328 switch (phy_data->port_mode) {
1329 case AXGBE_PORT_MODE_BACKPLANE:
1330 return axgbe_phy_switch_bp_mode(pdata);
1331 case AXGBE_PORT_MODE_BACKPLANE_2500:
1332 return axgbe_phy_switch_bp_2500_mode(pdata);
1333 case AXGBE_PORT_MODE_1000BASE_T:
1334 case AXGBE_PORT_MODE_NBASE_T:
1335 case AXGBE_PORT_MODE_10GBASE_T:
1336 return axgbe_phy_switch_baset_mode(pdata);
1337 case AXGBE_PORT_MODE_1000BASE_X:
1338 case AXGBE_PORT_MODE_10GBASE_R:
1339 case AXGBE_PORT_MODE_SFP:
1340 /* No switching, so just return current mode */
1341 return axgbe_phy_cur_mode(pdata);
1343 return AXGBE_MODE_UNKNOWN;
1347 static enum axgbe_mode axgbe_phy_get_basex_mode(struct axgbe_phy_data *phy_data
1353 return AXGBE_MODE_X;
1355 return AXGBE_MODE_KR;
1357 return AXGBE_MODE_UNKNOWN;
1361 static enum axgbe_mode axgbe_phy_get_baset_mode(struct axgbe_phy_data *phy_data
1367 return AXGBE_MODE_SGMII_100;
1369 return AXGBE_MODE_SGMII_1000;
1371 return AXGBE_MODE_KR;
1373 return AXGBE_MODE_UNKNOWN;
1377 static enum axgbe_mode axgbe_phy_get_sfp_mode(struct axgbe_phy_data *phy_data,
1382 return AXGBE_MODE_SGMII_100;
1384 if (phy_data->sfp_base == AXGBE_SFP_BASE_1000_T)
1385 return AXGBE_MODE_SGMII_1000;
1387 return AXGBE_MODE_X;
1390 return AXGBE_MODE_SFI;
1392 return AXGBE_MODE_UNKNOWN;
1396 static enum axgbe_mode axgbe_phy_get_bp_2500_mode(int speed)
1400 return AXGBE_MODE_KX_2500;
1402 return AXGBE_MODE_UNKNOWN;
1406 static enum axgbe_mode axgbe_phy_get_bp_mode(int speed)
1410 return AXGBE_MODE_KX_1000;
1412 return AXGBE_MODE_KR;
1414 return AXGBE_MODE_UNKNOWN;
1418 static enum axgbe_mode axgbe_phy_get_mode(struct axgbe_port *pdata,
1421 struct axgbe_phy_data *phy_data = pdata->phy_data;
1423 switch (phy_data->port_mode) {
1424 case AXGBE_PORT_MODE_BACKPLANE:
1425 return axgbe_phy_get_bp_mode(speed);
1426 case AXGBE_PORT_MODE_BACKPLANE_2500:
1427 return axgbe_phy_get_bp_2500_mode(speed);
1428 case AXGBE_PORT_MODE_1000BASE_T:
1429 case AXGBE_PORT_MODE_NBASE_T:
1430 case AXGBE_PORT_MODE_10GBASE_T:
1431 return axgbe_phy_get_baset_mode(phy_data, speed);
1432 case AXGBE_PORT_MODE_1000BASE_X:
1433 case AXGBE_PORT_MODE_10GBASE_R:
1434 return axgbe_phy_get_basex_mode(phy_data, speed);
1435 case AXGBE_PORT_MODE_SFP:
1436 return axgbe_phy_get_sfp_mode(phy_data, speed);
1438 return AXGBE_MODE_UNKNOWN;
1442 static void axgbe_phy_set_mode(struct axgbe_port *pdata, enum axgbe_mode mode)
1446 axgbe_phy_kr_mode(pdata);
1448 case AXGBE_MODE_SFI:
1449 axgbe_phy_sfi_mode(pdata);
1451 case AXGBE_MODE_KX_2500:
1452 axgbe_phy_kx_2500_mode(pdata);
1454 case AXGBE_MODE_SGMII_1000:
1455 axgbe_phy_sgmii_1000_mode(pdata);
1462 static bool axgbe_phy_check_mode(struct axgbe_port *pdata,
1463 enum axgbe_mode mode, u32 advert)
1465 if (pdata->phy.autoneg == AUTONEG_ENABLE) {
1466 if (pdata->phy.advertising & advert)
1469 enum axgbe_mode cur_mode;
1471 cur_mode = axgbe_phy_get_mode(pdata, pdata->phy.speed);
1472 if (cur_mode == mode)
1479 static bool axgbe_phy_use_basex_mode(struct axgbe_port *pdata,
1480 enum axgbe_mode mode)
1484 return axgbe_phy_check_mode(pdata, mode,
1485 ADVERTISED_1000baseT_Full);
1487 return axgbe_phy_check_mode(pdata, mode,
1488 ADVERTISED_10000baseT_Full);
1494 static bool axgbe_phy_use_baset_mode(struct axgbe_port *pdata,
1495 enum axgbe_mode mode)
1498 case AXGBE_MODE_SGMII_100:
1499 return axgbe_phy_check_mode(pdata, mode,
1500 ADVERTISED_100baseT_Full);
1501 case AXGBE_MODE_SGMII_1000:
1502 return axgbe_phy_check_mode(pdata, mode,
1503 ADVERTISED_1000baseT_Full);
1505 return axgbe_phy_check_mode(pdata, mode,
1506 ADVERTISED_10000baseT_Full);
1512 static bool axgbe_phy_use_sfp_mode(struct axgbe_port *pdata,
1513 enum axgbe_mode mode)
1515 struct axgbe_phy_data *phy_data = pdata->phy_data;
1519 if (phy_data->sfp_base == AXGBE_SFP_BASE_1000_T)
1521 return axgbe_phy_check_mode(pdata, mode,
1522 ADVERTISED_1000baseT_Full);
1523 case AXGBE_MODE_SGMII_100:
1524 if (phy_data->sfp_base != AXGBE_SFP_BASE_1000_T)
1526 return axgbe_phy_check_mode(pdata, mode,
1527 ADVERTISED_100baseT_Full);
1528 case AXGBE_MODE_SGMII_1000:
1529 if (phy_data->sfp_base != AXGBE_SFP_BASE_1000_T)
1531 return axgbe_phy_check_mode(pdata, mode,
1532 ADVERTISED_1000baseT_Full);
1533 case AXGBE_MODE_SFI:
1534 return axgbe_phy_check_mode(pdata, mode,
1535 ADVERTISED_10000baseT_Full);
1541 static bool axgbe_phy_use_bp_2500_mode(struct axgbe_port *pdata,
1542 enum axgbe_mode mode)
1545 case AXGBE_MODE_KX_2500:
1546 return axgbe_phy_check_mode(pdata, mode,
1547 ADVERTISED_2500baseX_Full);
1553 static bool axgbe_phy_use_bp_mode(struct axgbe_port *pdata,
1554 enum axgbe_mode mode)
1557 case AXGBE_MODE_KX_1000:
1558 return axgbe_phy_check_mode(pdata, mode,
1559 ADVERTISED_1000baseKX_Full);
1561 return axgbe_phy_check_mode(pdata, mode,
1562 ADVERTISED_10000baseKR_Full);
1568 static bool axgbe_phy_use_mode(struct axgbe_port *pdata, enum axgbe_mode mode)
1570 struct axgbe_phy_data *phy_data = pdata->phy_data;
1572 switch (phy_data->port_mode) {
1573 case AXGBE_PORT_MODE_BACKPLANE:
1574 return axgbe_phy_use_bp_mode(pdata, mode);
1575 case AXGBE_PORT_MODE_BACKPLANE_2500:
1576 return axgbe_phy_use_bp_2500_mode(pdata, mode);
1577 case AXGBE_PORT_MODE_1000BASE_T:
1578 case AXGBE_PORT_MODE_NBASE_T:
1579 case AXGBE_PORT_MODE_10GBASE_T:
1580 return axgbe_phy_use_baset_mode(pdata, mode);
1581 case AXGBE_PORT_MODE_1000BASE_X:
1582 case AXGBE_PORT_MODE_10GBASE_R:
1583 return axgbe_phy_use_basex_mode(pdata, mode);
1584 case AXGBE_PORT_MODE_SFP:
1585 return axgbe_phy_use_sfp_mode(pdata, mode);
1591 static int axgbe_phy_link_status(struct axgbe_port *pdata, int *an_restart)
1593 struct axgbe_phy_data *phy_data = pdata->phy_data;
1598 if (phy_data->port_mode == AXGBE_PORT_MODE_SFP) {
1599 /* Check SFP signals */
1600 axgbe_phy_sfp_detect(pdata);
1602 if (phy_data->sfp_changed) {
1607 if (phy_data->sfp_mod_absent || phy_data->sfp_rx_los)
1611 /* Link status is latched low, so read once to clear
1612 * and then read again to get current state
1614 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
1615 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
1616 if (reg & MDIO_STAT1_LSTATUS)
1619 /* No link, attempt a receiver reset cycle */
1620 if (phy_data->rrc_count++) {
1621 phy_data->rrc_count = 0;
1622 axgbe_phy_rrc(pdata);
1628 static void axgbe_phy_sfp_gpio_setup(struct axgbe_port *pdata)
1630 struct axgbe_phy_data *phy_data = pdata->phy_data;
1633 reg = XP_IOREAD(pdata, XP_PROP_3);
1635 phy_data->sfp_gpio_address = AXGBE_GPIO_ADDRESS_PCA9555 +
1636 XP_GET_BITS(reg, XP_PROP_3, GPIO_ADDR);
1638 phy_data->sfp_gpio_mask = XP_GET_BITS(reg, XP_PROP_3, GPIO_MASK);
1640 phy_data->sfp_gpio_rx_los = XP_GET_BITS(reg, XP_PROP_3,
1642 phy_data->sfp_gpio_tx_fault = XP_GET_BITS(reg, XP_PROP_3,
1644 phy_data->sfp_gpio_mod_absent = XP_GET_BITS(reg, XP_PROP_3,
1646 phy_data->sfp_gpio_rate_select = XP_GET_BITS(reg, XP_PROP_3,
1650 static void axgbe_phy_sfp_comm_setup(struct axgbe_port *pdata)
1652 struct axgbe_phy_data *phy_data = pdata->phy_data;
1653 unsigned int reg, mux_addr_hi, mux_addr_lo;
1655 reg = XP_IOREAD(pdata, XP_PROP_4);
1657 mux_addr_hi = XP_GET_BITS(reg, XP_PROP_4, MUX_ADDR_HI);
1658 mux_addr_lo = XP_GET_BITS(reg, XP_PROP_4, MUX_ADDR_LO);
1659 if (mux_addr_lo == AXGBE_SFP_DIRECT)
1662 phy_data->sfp_comm = AXGBE_SFP_COMM_PCA9545;
1663 phy_data->sfp_mux_address = (mux_addr_hi << 2) + mux_addr_lo;
1664 phy_data->sfp_mux_channel = XP_GET_BITS(reg, XP_PROP_4, MUX_CHAN);
1667 static void axgbe_phy_sfp_setup(struct axgbe_port *pdata)
1669 axgbe_phy_sfp_comm_setup(pdata);
1670 axgbe_phy_sfp_gpio_setup(pdata);
1673 static bool axgbe_phy_redrv_error(struct axgbe_phy_data *phy_data)
1675 if (!phy_data->redrv)
1678 if (phy_data->redrv_if >= AXGBE_PHY_REDRV_IF_MAX)
1681 switch (phy_data->redrv_model) {
1682 case AXGBE_PHY_REDRV_MODEL_4223:
1683 if (phy_data->redrv_lane > 3)
1686 case AXGBE_PHY_REDRV_MODEL_4227:
1687 if (phy_data->redrv_lane > 1)
1697 static int axgbe_phy_mdio_reset_setup(struct axgbe_port *pdata)
1699 struct axgbe_phy_data *phy_data = pdata->phy_data;
1702 if (phy_data->conn_type != AXGBE_CONN_TYPE_MDIO)
1704 reg = XP_IOREAD(pdata, XP_PROP_3);
1705 phy_data->mdio_reset = XP_GET_BITS(reg, XP_PROP_3, MDIO_RESET);
1706 switch (phy_data->mdio_reset) {
1707 case AXGBE_MDIO_RESET_NONE:
1708 case AXGBE_MDIO_RESET_I2C_GPIO:
1709 case AXGBE_MDIO_RESET_INT_GPIO:
1712 PMD_DRV_LOG(ERR, "unsupported MDIO reset (%#x)\n",
1713 phy_data->mdio_reset);
1716 if (phy_data->mdio_reset == AXGBE_MDIO_RESET_I2C_GPIO) {
1717 phy_data->mdio_reset_addr = AXGBE_GPIO_ADDRESS_PCA9555 +
1718 XP_GET_BITS(reg, XP_PROP_3,
1719 MDIO_RESET_I2C_ADDR);
1720 phy_data->mdio_reset_gpio = XP_GET_BITS(reg, XP_PROP_3,
1721 MDIO_RESET_I2C_GPIO);
1722 } else if (phy_data->mdio_reset == AXGBE_MDIO_RESET_INT_GPIO) {
1723 phy_data->mdio_reset_gpio = XP_GET_BITS(reg, XP_PROP_3,
1724 MDIO_RESET_INT_GPIO);
1730 static bool axgbe_phy_port_mode_mismatch(struct axgbe_port *pdata)
1732 struct axgbe_phy_data *phy_data = pdata->phy_data;
1734 switch (phy_data->port_mode) {
1735 case AXGBE_PORT_MODE_BACKPLANE:
1736 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) ||
1737 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000))
1740 case AXGBE_PORT_MODE_BACKPLANE_2500:
1741 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_2500)
1744 case AXGBE_PORT_MODE_1000BASE_T:
1745 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) ||
1746 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000))
1749 case AXGBE_PORT_MODE_1000BASE_X:
1750 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000)
1753 case AXGBE_PORT_MODE_NBASE_T:
1754 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) ||
1755 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) ||
1756 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_2500))
1759 case AXGBE_PORT_MODE_10GBASE_T:
1760 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) ||
1761 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) ||
1762 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000))
1765 case AXGBE_PORT_MODE_10GBASE_R:
1766 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000)
1769 case AXGBE_PORT_MODE_SFP:
1770 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) ||
1771 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) ||
1772 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000))
1782 static bool axgbe_phy_conn_type_mismatch(struct axgbe_port *pdata)
1784 struct axgbe_phy_data *phy_data = pdata->phy_data;
1786 switch (phy_data->port_mode) {
1787 case AXGBE_PORT_MODE_BACKPLANE:
1788 case AXGBE_PORT_MODE_BACKPLANE_2500:
1789 if (phy_data->conn_type == AXGBE_CONN_TYPE_BACKPLANE)
1792 case AXGBE_PORT_MODE_1000BASE_T:
1793 case AXGBE_PORT_MODE_1000BASE_X:
1794 case AXGBE_PORT_MODE_NBASE_T:
1795 case AXGBE_PORT_MODE_10GBASE_T:
1796 case AXGBE_PORT_MODE_10GBASE_R:
1797 if (phy_data->conn_type == AXGBE_CONN_TYPE_MDIO)
1800 case AXGBE_PORT_MODE_SFP:
1801 if (phy_data->conn_type == AXGBE_CONN_TYPE_SFP)
1811 static bool axgbe_phy_port_enabled(struct axgbe_port *pdata)
1815 reg = XP_IOREAD(pdata, XP_PROP_0);
1816 if (!XP_GET_BITS(reg, XP_PROP_0, PORT_SPEEDS))
1818 if (!XP_GET_BITS(reg, XP_PROP_0, CONN_TYPE))
1824 static void axgbe_phy_cdr_track(struct axgbe_port *pdata)
1826 struct axgbe_phy_data *phy_data = pdata->phy_data;
1828 if (!pdata->vdata->an_cdr_workaround)
1831 if (!phy_data->phy_cdr_notrack)
1834 rte_delay_us(phy_data->phy_cdr_delay + 400);
1836 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL,
1837 AXGBE_PMA_CDR_TRACK_EN_MASK,
1838 AXGBE_PMA_CDR_TRACK_EN_ON);
1840 phy_data->phy_cdr_notrack = 0;
1843 static void axgbe_phy_cdr_notrack(struct axgbe_port *pdata)
1845 struct axgbe_phy_data *phy_data = pdata->phy_data;
1847 if (!pdata->vdata->an_cdr_workaround)
1850 if (phy_data->phy_cdr_notrack)
1853 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL,
1854 AXGBE_PMA_CDR_TRACK_EN_MASK,
1855 AXGBE_PMA_CDR_TRACK_EN_OFF);
1857 axgbe_phy_rrc(pdata);
1859 phy_data->phy_cdr_notrack = 1;
1862 static void axgbe_phy_kr_training_post(struct axgbe_port *pdata)
1864 if (!pdata->cdr_track_early)
1865 axgbe_phy_cdr_track(pdata);
1868 static void axgbe_phy_kr_training_pre(struct axgbe_port *pdata)
1870 if (pdata->cdr_track_early)
1871 axgbe_phy_cdr_track(pdata);
1874 static void axgbe_phy_an_post(struct axgbe_port *pdata)
1876 struct axgbe_phy_data *phy_data = pdata->phy_data;
1878 switch (pdata->an_mode) {
1879 case AXGBE_AN_MODE_CL73:
1880 case AXGBE_AN_MODE_CL73_REDRV:
1881 if (phy_data->cur_mode != AXGBE_MODE_KR)
1884 axgbe_phy_cdr_track(pdata);
1886 switch (pdata->an_result) {
1887 case AXGBE_AN_READY:
1888 case AXGBE_AN_COMPLETE:
1891 if (phy_data->phy_cdr_delay < AXGBE_CDR_DELAY_MAX)
1892 phy_data->phy_cdr_delay += AXGBE_CDR_DELAY_INC;
1901 static void axgbe_phy_an_pre(struct axgbe_port *pdata)
1903 struct axgbe_phy_data *phy_data = pdata->phy_data;
1905 switch (pdata->an_mode) {
1906 case AXGBE_AN_MODE_CL73:
1907 case AXGBE_AN_MODE_CL73_REDRV:
1908 if (phy_data->cur_mode != AXGBE_MODE_KR)
1911 axgbe_phy_cdr_notrack(pdata);
1918 static void axgbe_phy_stop(struct axgbe_port *pdata)
1920 struct axgbe_phy_data *phy_data = pdata->phy_data;
1922 /* Reset SFP data */
1923 axgbe_phy_sfp_reset(phy_data);
1924 axgbe_phy_sfp_mod_absent(pdata);
1926 /* Reset CDR support */
1927 axgbe_phy_cdr_track(pdata);
1929 /* Power off the PHY */
1930 axgbe_phy_power_off(pdata);
1932 /* Stop the I2C controller */
1933 pdata->i2c_if.i2c_stop(pdata);
1936 static int axgbe_phy_start(struct axgbe_port *pdata)
1938 struct axgbe_phy_data *phy_data = pdata->phy_data;
1941 /* Start the I2C controller */
1942 ret = pdata->i2c_if.i2c_start(pdata);
1946 /* Start in highest supported mode */
1947 axgbe_phy_set_mode(pdata, phy_data->start_mode);
1949 /* Reset CDR support */
1950 axgbe_phy_cdr_track(pdata);
1952 /* After starting the I2C controller, we can check for an SFP */
1953 switch (phy_data->port_mode) {
1954 case AXGBE_PORT_MODE_SFP:
1955 axgbe_phy_sfp_detect(pdata);
1964 static int axgbe_phy_reset(struct axgbe_port *pdata)
1966 struct axgbe_phy_data *phy_data = pdata->phy_data;
1967 enum axgbe_mode cur_mode;
1969 /* Reset by power cycling the PHY */
1970 cur_mode = phy_data->cur_mode;
1971 axgbe_phy_power_off(pdata);
1972 /* First time reset is done with passed unknown mode*/
1973 axgbe_phy_set_mode(pdata, cur_mode);
1977 static int axgbe_phy_init(struct axgbe_port *pdata)
1979 struct axgbe_phy_data *phy_data;
1983 /* Check if enabled */
1984 if (!axgbe_phy_port_enabled(pdata)) {
1985 PMD_DRV_LOG(ERR, "device is not enabled\n");
1989 /* Initialize the I2C controller */
1990 ret = pdata->i2c_if.i2c_init(pdata);
1994 phy_data = rte_zmalloc("phy_data memory", sizeof(*phy_data), 0);
1996 PMD_DRV_LOG(ERR, "phy_data allocation failed\n");
1999 pdata->phy_data = phy_data;
2001 reg = XP_IOREAD(pdata, XP_PROP_0);
2002 phy_data->port_mode = XP_GET_BITS(reg, XP_PROP_0, PORT_MODE);
2003 phy_data->port_id = XP_GET_BITS(reg, XP_PROP_0, PORT_ID);
2004 phy_data->port_speeds = XP_GET_BITS(reg, XP_PROP_0, PORT_SPEEDS);
2005 phy_data->conn_type = XP_GET_BITS(reg, XP_PROP_0, CONN_TYPE);
2006 phy_data->mdio_addr = XP_GET_BITS(reg, XP_PROP_0, MDIO_ADDR);
2008 reg = XP_IOREAD(pdata, XP_PROP_4);
2009 phy_data->redrv = XP_GET_BITS(reg, XP_PROP_4, REDRV_PRESENT);
2010 phy_data->redrv_if = XP_GET_BITS(reg, XP_PROP_4, REDRV_IF);
2011 phy_data->redrv_addr = XP_GET_BITS(reg, XP_PROP_4, REDRV_ADDR);
2012 phy_data->redrv_lane = XP_GET_BITS(reg, XP_PROP_4, REDRV_LANE);
2013 phy_data->redrv_model = XP_GET_BITS(reg, XP_PROP_4, REDRV_MODEL);
2015 /* Validate the connection requested */
2016 if (axgbe_phy_conn_type_mismatch(pdata)) {
2017 PMD_DRV_LOG(ERR, "phy mode/connection mismatch (%#x/%#x)\n",
2018 phy_data->port_mode, phy_data->conn_type);
2022 /* Validate the mode requested */
2023 if (axgbe_phy_port_mode_mismatch(pdata)) {
2024 PMD_DRV_LOG(ERR, "phy mode/speed mismatch (%#x/%#x)\n",
2025 phy_data->port_mode, phy_data->port_speeds);
2029 /* Check for and validate MDIO reset support */
2030 ret = axgbe_phy_mdio_reset_setup(pdata);
2034 /* Validate the re-driver information */
2035 if (axgbe_phy_redrv_error(phy_data)) {
2036 PMD_DRV_LOG(ERR, "phy re-driver settings error\n");
2039 pdata->kr_redrv = phy_data->redrv;
2041 /* Indicate current mode is unknown */
2042 phy_data->cur_mode = AXGBE_MODE_UNKNOWN;
2044 /* Initialize supported features */
2045 pdata->phy.supported = 0;
2047 switch (phy_data->port_mode) {
2048 /* Backplane support */
2049 case AXGBE_PORT_MODE_BACKPLANE:
2050 pdata->phy.supported |= SUPPORTED_Autoneg;
2051 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2052 pdata->phy.supported |= SUPPORTED_Backplane;
2053 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) {
2054 pdata->phy.supported |= SUPPORTED_1000baseKX_Full;
2055 phy_data->start_mode = AXGBE_MODE_KX_1000;
2057 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) {
2058 pdata->phy.supported |= SUPPORTED_10000baseKR_Full;
2059 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
2060 pdata->phy.supported |=
2061 SUPPORTED_10000baseR_FEC;
2062 phy_data->start_mode = AXGBE_MODE_KR;
2065 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE;
2067 case AXGBE_PORT_MODE_BACKPLANE_2500:
2068 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2069 pdata->phy.supported |= SUPPORTED_Backplane;
2070 pdata->phy.supported |= SUPPORTED_2500baseX_Full;
2071 phy_data->start_mode = AXGBE_MODE_KX_2500;
2073 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE;
2076 /* MDIO 1GBase-T support */
2077 case AXGBE_PORT_MODE_1000BASE_T:
2078 pdata->phy.supported |= SUPPORTED_Autoneg;
2079 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2080 pdata->phy.supported |= SUPPORTED_TP;
2081 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) {
2082 pdata->phy.supported |= SUPPORTED_100baseT_Full;
2083 phy_data->start_mode = AXGBE_MODE_SGMII_100;
2085 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) {
2086 pdata->phy.supported |= SUPPORTED_1000baseT_Full;
2087 phy_data->start_mode = AXGBE_MODE_SGMII_1000;
2090 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL22;
2093 /* MDIO Base-X support */
2094 case AXGBE_PORT_MODE_1000BASE_X:
2095 pdata->phy.supported |= SUPPORTED_Autoneg;
2096 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2097 pdata->phy.supported |= SUPPORTED_FIBRE;
2098 pdata->phy.supported |= SUPPORTED_1000baseT_Full;
2099 phy_data->start_mode = AXGBE_MODE_X;
2101 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL22;
2104 /* MDIO NBase-T support */
2105 case AXGBE_PORT_MODE_NBASE_T:
2106 pdata->phy.supported |= SUPPORTED_Autoneg;
2107 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2108 pdata->phy.supported |= SUPPORTED_TP;
2109 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) {
2110 pdata->phy.supported |= SUPPORTED_100baseT_Full;
2111 phy_data->start_mode = AXGBE_MODE_SGMII_100;
2113 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) {
2114 pdata->phy.supported |= SUPPORTED_1000baseT_Full;
2115 phy_data->start_mode = AXGBE_MODE_SGMII_1000;
2117 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_2500) {
2118 pdata->phy.supported |= SUPPORTED_2500baseX_Full;
2119 phy_data->start_mode = AXGBE_MODE_KX_2500;
2122 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL45;
2125 /* 10GBase-T support */
2126 case AXGBE_PORT_MODE_10GBASE_T:
2127 pdata->phy.supported |= SUPPORTED_Autoneg;
2128 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2129 pdata->phy.supported |= SUPPORTED_TP;
2130 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) {
2131 pdata->phy.supported |= SUPPORTED_100baseT_Full;
2132 phy_data->start_mode = AXGBE_MODE_SGMII_100;
2134 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) {
2135 pdata->phy.supported |= SUPPORTED_1000baseT_Full;
2136 phy_data->start_mode = AXGBE_MODE_SGMII_1000;
2138 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) {
2139 pdata->phy.supported |= SUPPORTED_10000baseT_Full;
2140 phy_data->start_mode = AXGBE_MODE_KR;
2143 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE;
2146 /* 10GBase-R support */
2147 case AXGBE_PORT_MODE_10GBASE_R:
2148 pdata->phy.supported |= SUPPORTED_Autoneg;
2149 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2150 pdata->phy.supported |= SUPPORTED_TP;
2151 pdata->phy.supported |= SUPPORTED_10000baseT_Full;
2152 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
2153 pdata->phy.supported |= SUPPORTED_10000baseR_FEC;
2154 phy_data->start_mode = AXGBE_MODE_SFI;
2156 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE;
2160 case AXGBE_PORT_MODE_SFP:
2161 pdata->phy.supported |= SUPPORTED_Autoneg;
2162 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2163 pdata->phy.supported |= SUPPORTED_TP;
2164 pdata->phy.supported |= SUPPORTED_FIBRE;
2165 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) {
2166 pdata->phy.supported |= SUPPORTED_100baseT_Full;
2167 phy_data->start_mode = AXGBE_MODE_SGMII_100;
2169 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) {
2170 pdata->phy.supported |= SUPPORTED_1000baseT_Full;
2171 phy_data->start_mode = AXGBE_MODE_SGMII_1000;
2173 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) {
2174 pdata->phy.supported |= SUPPORTED_10000baseT_Full;
2175 phy_data->start_mode = AXGBE_MODE_SFI;
2176 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
2177 pdata->phy.supported |=
2178 SUPPORTED_10000baseR_FEC;
2181 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL22;
2183 axgbe_phy_sfp_setup(pdata);
2189 if ((phy_data->conn_type & AXGBE_CONN_TYPE_MDIO) &&
2190 (phy_data->phydev_mode != AXGBE_MDIO_MODE_NONE)) {
2191 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr,
2192 phy_data->phydev_mode);
2194 PMD_DRV_LOG(ERR, "mdio port/clause not compatible (%d/%u)\n",
2195 phy_data->mdio_addr, phy_data->phydev_mode);
2200 if (phy_data->redrv && !phy_data->redrv_if) {
2201 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr,
2202 AXGBE_MDIO_MODE_CL22);
2204 PMD_DRV_LOG(ERR, "redriver mdio port not compatible (%u)\n",
2205 phy_data->redrv_addr);
2210 phy_data->phy_cdr_delay = AXGBE_CDR_DELAY_INIT;
2213 void axgbe_init_function_ptrs_phy_v2(struct axgbe_phy_if *phy_if)
2215 struct axgbe_phy_impl_if *phy_impl = &phy_if->phy_impl;
2217 phy_impl->init = axgbe_phy_init;
2218 phy_impl->reset = axgbe_phy_reset;
2219 phy_impl->start = axgbe_phy_start;
2220 phy_impl->stop = axgbe_phy_stop;
2221 phy_impl->link_status = axgbe_phy_link_status;
2222 phy_impl->use_mode = axgbe_phy_use_mode;
2223 phy_impl->set_mode = axgbe_phy_set_mode;
2224 phy_impl->get_mode = axgbe_phy_get_mode;
2225 phy_impl->switch_mode = axgbe_phy_switch_mode;
2226 phy_impl->cur_mode = axgbe_phy_cur_mode;
2227 phy_impl->an_mode = axgbe_phy_an_mode;
2228 phy_impl->an_config = axgbe_phy_an_config;
2229 phy_impl->an_advertising = axgbe_phy_an_advertising;
2230 phy_impl->an_outcome = axgbe_phy_an_outcome;
2232 phy_impl->an_pre = axgbe_phy_an_pre;
2233 phy_impl->an_post = axgbe_phy_an_post;
2235 phy_impl->kr_training_pre = axgbe_phy_kr_training_pre;
2236 phy_impl->kr_training_post = axgbe_phy_kr_training_post;