1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved.
3 * Copyright(c) 2018 Synopsys, Inc. All rights reserved.
6 #include "axgbe_ethdev.h"
7 #include "axgbe_common.h"
10 #define AXGBE_PHY_PORT_SPEED_100 BIT(0)
11 #define AXGBE_PHY_PORT_SPEED_1000 BIT(1)
12 #define AXGBE_PHY_PORT_SPEED_2500 BIT(2)
13 #define AXGBE_PHY_PORT_SPEED_10000 BIT(3)
15 #define AXGBE_MUTEX_RELEASE 0x80000000
17 #define AXGBE_SFP_DIRECT 7
19 /* I2C target addresses */
20 #define AXGBE_SFP_SERIAL_ID_ADDRESS 0x50
21 #define AXGBE_SFP_DIAG_INFO_ADDRESS 0x51
22 #define AXGBE_SFP_PHY_ADDRESS 0x56
23 #define AXGBE_GPIO_ADDRESS_PCA9555 0x20
25 /* SFP sideband signal indicators */
26 #define AXGBE_GPIO_NO_TX_FAULT BIT(0)
27 #define AXGBE_GPIO_NO_RATE_SELECT BIT(1)
28 #define AXGBE_GPIO_NO_MOD_ABSENT BIT(2)
29 #define AXGBE_GPIO_NO_RX_LOS BIT(3)
31 /* Rate-change complete wait/retry count */
32 #define AXGBE_RATECHANGE_COUNT 500
34 enum axgbe_port_mode {
35 AXGBE_PORT_MODE_RSVD = 0,
36 AXGBE_PORT_MODE_BACKPLANE,
37 AXGBE_PORT_MODE_BACKPLANE_2500,
38 AXGBE_PORT_MODE_1000BASE_T,
39 AXGBE_PORT_MODE_1000BASE_X,
40 AXGBE_PORT_MODE_NBASE_T,
41 AXGBE_PORT_MODE_10GBASE_T,
42 AXGBE_PORT_MODE_10GBASE_R,
47 enum axgbe_conn_type {
48 AXGBE_CONN_TYPE_NONE = 0,
51 AXGBE_CONN_TYPE_RSVD1,
52 AXGBE_CONN_TYPE_BACKPLANE,
56 /* SFP/SFP+ related definitions */
58 AXGBE_SFP_COMM_DIRECT = 0,
59 AXGBE_SFP_COMM_PCA9545,
62 enum axgbe_sfp_cable {
63 AXGBE_SFP_CABLE_UNKNOWN = 0,
64 AXGBE_SFP_CABLE_ACTIVE,
65 AXGBE_SFP_CABLE_PASSIVE,
69 AXGBE_SFP_BASE_UNKNOWN = 0,
70 AXGBE_SFP_BASE_1000_T,
71 AXGBE_SFP_BASE_1000_SX,
72 AXGBE_SFP_BASE_1000_LX,
73 AXGBE_SFP_BASE_1000_CX,
74 AXGBE_SFP_BASE_10000_SR,
75 AXGBE_SFP_BASE_10000_LR,
76 AXGBE_SFP_BASE_10000_LRM,
77 AXGBE_SFP_BASE_10000_ER,
78 AXGBE_SFP_BASE_10000_CR,
81 enum axgbe_sfp_speed {
82 AXGBE_SFP_SPEED_UNKNOWN = 0,
83 AXGBE_SFP_SPEED_100_1000,
85 AXGBE_SFP_SPEED_10000,
88 /* SFP Serial ID Base ID values relative to an offset of 0 */
89 #define AXGBE_SFP_BASE_ID 0
90 #define AXGBE_SFP_ID_SFP 0x03
92 #define AXGBE_SFP_BASE_EXT_ID 1
93 #define AXGBE_SFP_EXT_ID_SFP 0x04
95 #define AXGBE_SFP_BASE_10GBE_CC 3
96 #define AXGBE_SFP_BASE_10GBE_CC_SR BIT(4)
97 #define AXGBE_SFP_BASE_10GBE_CC_LR BIT(5)
98 #define AXGBE_SFP_BASE_10GBE_CC_LRM BIT(6)
99 #define AXGBE_SFP_BASE_10GBE_CC_ER BIT(7)
101 #define AXGBE_SFP_BASE_1GBE_CC 6
102 #define AXGBE_SFP_BASE_1GBE_CC_SX BIT(0)
103 #define AXGBE_SFP_BASE_1GBE_CC_LX BIT(1)
104 #define AXGBE_SFP_BASE_1GBE_CC_CX BIT(2)
105 #define AXGBE_SFP_BASE_1GBE_CC_T BIT(3)
107 #define AXGBE_SFP_BASE_CABLE 8
108 #define AXGBE_SFP_BASE_CABLE_PASSIVE BIT(2)
109 #define AXGBE_SFP_BASE_CABLE_ACTIVE BIT(3)
111 #define AXGBE_SFP_BASE_BR 12
112 #define AXGBE_SFP_BASE_BR_1GBE_MIN 0x0a
113 #define AXGBE_SFP_BASE_BR_1GBE_MAX 0x0d
114 #define AXGBE_SFP_BASE_BR_10GBE_MIN 0x64
115 #define AXGBE_SFP_BASE_BR_10GBE_MAX 0x68
117 #define AXGBE_SFP_BASE_CU_CABLE_LEN 18
119 #define AXGBE_SFP_BASE_VENDOR_NAME 20
120 #define AXGBE_SFP_BASE_VENDOR_NAME_LEN 16
121 #define AXGBE_SFP_BASE_VENDOR_PN 40
122 #define AXGBE_SFP_BASE_VENDOR_PN_LEN 16
123 #define AXGBE_SFP_BASE_VENDOR_REV 56
124 #define AXGBE_SFP_BASE_VENDOR_REV_LEN 4
126 #define AXGBE_SFP_BASE_CC 63
128 /* SFP Serial ID Extended ID values relative to an offset of 64 */
129 #define AXGBE_SFP_BASE_VENDOR_SN 4
130 #define AXGBE_SFP_BASE_VENDOR_SN_LEN 16
132 #define AXGBE_SFP_EXTD_DIAG 28
133 #define AXGBE_SFP_EXTD_DIAG_ADDR_CHANGE BIT(2)
135 #define AXGBE_SFP_EXTD_SFF_8472 30
137 #define AXGBE_SFP_EXTD_CC 31
139 struct axgbe_sfp_eeprom {
145 #define AXGBE_BEL_FUSE_VENDOR "BEL-FUSE"
146 #define AXGBE_BEL_FUSE_PARTNO "1GBT-SFP06"
148 struct axgbe_sfp_ascii {
150 char vendor[AXGBE_SFP_BASE_VENDOR_NAME_LEN + 1];
151 char partno[AXGBE_SFP_BASE_VENDOR_PN_LEN + 1];
152 char rev[AXGBE_SFP_BASE_VENDOR_REV_LEN + 1];
153 char serno[AXGBE_SFP_BASE_VENDOR_SN_LEN + 1];
157 /* MDIO PHY reset types */
158 enum axgbe_mdio_reset {
159 AXGBE_MDIO_RESET_NONE = 0,
160 AXGBE_MDIO_RESET_I2C_GPIO,
161 AXGBE_MDIO_RESET_INT_GPIO,
162 AXGBE_MDIO_RESET_MAX,
165 /* Re-driver related definitions */
166 enum axgbe_phy_redrv_if {
167 AXGBE_PHY_REDRV_IF_MDIO = 0,
168 AXGBE_PHY_REDRV_IF_I2C,
169 AXGBE_PHY_REDRV_IF_MAX,
172 enum axgbe_phy_redrv_model {
173 AXGBE_PHY_REDRV_MODEL_4223 = 0,
174 AXGBE_PHY_REDRV_MODEL_4227,
175 AXGBE_PHY_REDRV_MODEL_MAX,
178 enum axgbe_phy_redrv_mode {
179 AXGBE_PHY_REDRV_MODE_CX = 5,
180 AXGBE_PHY_REDRV_MODE_SR = 9,
183 #define AXGBE_PHY_REDRV_MODE_REG 0x12b0
185 /* PHY related configuration information */
186 struct axgbe_phy_data {
187 enum axgbe_port_mode port_mode;
189 unsigned int port_id;
191 unsigned int port_speeds;
193 enum axgbe_conn_type conn_type;
195 enum axgbe_mode cur_mode;
196 enum axgbe_mode start_mode;
198 unsigned int rrc_count;
200 unsigned int mdio_addr;
202 unsigned int comm_owned;
205 enum axgbe_sfp_comm sfp_comm;
206 unsigned int sfp_mux_address;
207 unsigned int sfp_mux_channel;
209 unsigned int sfp_gpio_address;
210 unsigned int sfp_gpio_mask;
211 unsigned int sfp_gpio_rx_los;
212 unsigned int sfp_gpio_tx_fault;
213 unsigned int sfp_gpio_mod_absent;
214 unsigned int sfp_gpio_rate_select;
216 unsigned int sfp_rx_los;
217 unsigned int sfp_tx_fault;
218 unsigned int sfp_mod_absent;
219 unsigned int sfp_diags;
220 unsigned int sfp_changed;
221 unsigned int sfp_phy_avail;
222 unsigned int sfp_cable_len;
223 enum axgbe_sfp_base sfp_base;
224 enum axgbe_sfp_cable sfp_cable;
225 enum axgbe_sfp_speed sfp_speed;
226 struct axgbe_sfp_eeprom sfp_eeprom;
228 /* External PHY support */
229 enum axgbe_mdio_mode phydev_mode;
230 enum axgbe_mdio_reset mdio_reset;
231 unsigned int mdio_reset_addr;
232 unsigned int mdio_reset_gpio;
234 /* Re-driver support */
236 unsigned int redrv_if;
237 unsigned int redrv_addr;
238 unsigned int redrv_lane;
239 unsigned int redrv_model;
242 static enum axgbe_an_mode axgbe_phy_an_mode(struct axgbe_port *pdata);
244 static int axgbe_phy_i2c_xfer(struct axgbe_port *pdata,
245 struct axgbe_i2c_op *i2c_op)
247 struct axgbe_phy_data *phy_data = pdata->phy_data;
249 /* Be sure we own the bus */
250 if (!phy_data->comm_owned)
253 return pdata->i2c_if.i2c_xfer(pdata, i2c_op);
256 static int axgbe_phy_redrv_write(struct axgbe_port *pdata, unsigned int reg,
259 struct axgbe_phy_data *phy_data = pdata->phy_data;
260 struct axgbe_i2c_op i2c_op;
262 u8 redrv_data[5], csum;
263 unsigned int i, retry;
266 /* High byte of register contains read/write indicator */
267 redrv_data[0] = ((reg >> 8) & 0xff) << 1;
268 redrv_data[1] = reg & 0xff;
269 redrv_val = (uint16_t *)&redrv_data[2];
270 *redrv_val = rte_cpu_to_be_16(val);
272 /* Calculate 1 byte checksum */
274 for (i = 0; i < 4; i++) {
275 csum += redrv_data[i];
276 if (redrv_data[i] > csum)
279 redrv_data[4] = ~csum;
283 i2c_op.cmd = AXGBE_I2C_CMD_WRITE;
284 i2c_op.target = phy_data->redrv_addr;
285 i2c_op.len = sizeof(redrv_data);
286 i2c_op.buf = redrv_data;
287 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op);
289 if ((ret == -EAGAIN) && retry--)
297 i2c_op.cmd = AXGBE_I2C_CMD_READ;
298 i2c_op.target = phy_data->redrv_addr;
300 i2c_op.buf = redrv_data;
301 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op);
303 if ((ret == -EAGAIN) && retry--)
309 if (redrv_data[0] != 0xff) {
310 PMD_DRV_LOG(ERR, "Redriver write checksum error\n");
317 static int axgbe_phy_i2c_read(struct axgbe_port *pdata, unsigned int target,
318 void *reg, unsigned int reg_len,
319 void *val, unsigned int val_len)
321 struct axgbe_i2c_op i2c_op;
326 /* Set the specified register to read */
327 i2c_op.cmd = AXGBE_I2C_CMD_WRITE;
328 i2c_op.target = target;
329 i2c_op.len = reg_len;
331 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op);
333 if ((ret == -EAGAIN) && retry--)
341 /* Read the specfied register */
342 i2c_op.cmd = AXGBE_I2C_CMD_READ;
343 i2c_op.target = target;
344 i2c_op.len = val_len;
346 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op);
347 if ((ret == -EAGAIN) && retry--)
353 static int axgbe_phy_sfp_put_mux(struct axgbe_port *pdata)
355 struct axgbe_phy_data *phy_data = pdata->phy_data;
356 struct axgbe_i2c_op i2c_op;
359 if (phy_data->sfp_comm == AXGBE_SFP_COMM_DIRECT)
362 /* Select no mux channels */
364 i2c_op.cmd = AXGBE_I2C_CMD_WRITE;
365 i2c_op.target = phy_data->sfp_mux_address;
366 i2c_op.len = sizeof(mux_channel);
367 i2c_op.buf = &mux_channel;
369 return axgbe_phy_i2c_xfer(pdata, &i2c_op);
372 static int axgbe_phy_sfp_get_mux(struct axgbe_port *pdata)
374 struct axgbe_phy_data *phy_data = pdata->phy_data;
375 struct axgbe_i2c_op i2c_op;
378 if (phy_data->sfp_comm == AXGBE_SFP_COMM_DIRECT)
381 /* Select desired mux channel */
382 mux_channel = 1 << phy_data->sfp_mux_channel;
383 i2c_op.cmd = AXGBE_I2C_CMD_WRITE;
384 i2c_op.target = phy_data->sfp_mux_address;
385 i2c_op.len = sizeof(mux_channel);
386 i2c_op.buf = &mux_channel;
388 return axgbe_phy_i2c_xfer(pdata, &i2c_op);
391 static void axgbe_phy_put_comm_ownership(struct axgbe_port *pdata)
393 struct axgbe_phy_data *phy_data = pdata->phy_data;
395 phy_data->comm_owned = 0;
397 pthread_mutex_unlock(&pdata->phy_mutex);
400 static int axgbe_phy_get_comm_ownership(struct axgbe_port *pdata)
402 struct axgbe_phy_data *phy_data = pdata->phy_data;
404 unsigned int mutex_id;
406 if (phy_data->comm_owned)
409 /* The I2C and MDIO/GPIO bus is multiplexed between multiple devices,
410 * the driver needs to take the software mutex and then the hardware
411 * mutexes before being able to use the busses.
413 pthread_mutex_lock(&pdata->phy_mutex);
415 /* Clear the mutexes */
416 XP_IOWRITE(pdata, XP_I2C_MUTEX, AXGBE_MUTEX_RELEASE);
417 XP_IOWRITE(pdata, XP_MDIO_MUTEX, AXGBE_MUTEX_RELEASE);
419 /* Mutex formats are the same for I2C and MDIO/GPIO */
421 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ID, phy_data->port_id);
422 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ACTIVE, 1);
424 timeout = rte_get_timer_cycles() + (rte_get_timer_hz() * 5);
425 while (time_before(rte_get_timer_cycles(), timeout)) {
426 /* Must be all zeroes in order to obtain the mutex */
427 if (XP_IOREAD(pdata, XP_I2C_MUTEX) ||
428 XP_IOREAD(pdata, XP_MDIO_MUTEX)) {
433 /* Obtain the mutex */
434 XP_IOWRITE(pdata, XP_I2C_MUTEX, mutex_id);
435 XP_IOWRITE(pdata, XP_MDIO_MUTEX, mutex_id);
437 phy_data->comm_owned = 1;
441 pthread_mutex_unlock(&pdata->phy_mutex);
443 PMD_DRV_LOG(ERR, "unable to obtain hardware mutexes\n");
448 static void axgbe_phy_sfp_phy_settings(struct axgbe_port *pdata)
450 struct axgbe_phy_data *phy_data = pdata->phy_data;
452 if (phy_data->sfp_mod_absent) {
453 pdata->phy.speed = SPEED_UNKNOWN;
454 pdata->phy.duplex = DUPLEX_UNKNOWN;
455 pdata->phy.autoneg = AUTONEG_ENABLE;
456 pdata->phy.advertising = pdata->phy.supported;
459 pdata->phy.advertising &= ~ADVERTISED_Autoneg;
460 pdata->phy.advertising &= ~ADVERTISED_TP;
461 pdata->phy.advertising &= ~ADVERTISED_FIBRE;
462 pdata->phy.advertising &= ~ADVERTISED_100baseT_Full;
463 pdata->phy.advertising &= ~ADVERTISED_1000baseT_Full;
464 pdata->phy.advertising &= ~ADVERTISED_10000baseT_Full;
465 pdata->phy.advertising &= ~ADVERTISED_10000baseR_FEC;
467 switch (phy_data->sfp_base) {
468 case AXGBE_SFP_BASE_1000_T:
469 case AXGBE_SFP_BASE_1000_SX:
470 case AXGBE_SFP_BASE_1000_LX:
471 case AXGBE_SFP_BASE_1000_CX:
472 pdata->phy.speed = SPEED_UNKNOWN;
473 pdata->phy.duplex = DUPLEX_UNKNOWN;
474 pdata->phy.autoneg = AUTONEG_ENABLE;
475 pdata->phy.advertising |= ADVERTISED_Autoneg;
477 case AXGBE_SFP_BASE_10000_SR:
478 case AXGBE_SFP_BASE_10000_LR:
479 case AXGBE_SFP_BASE_10000_LRM:
480 case AXGBE_SFP_BASE_10000_ER:
481 case AXGBE_SFP_BASE_10000_CR:
483 pdata->phy.speed = SPEED_10000;
484 pdata->phy.duplex = DUPLEX_FULL;
485 pdata->phy.autoneg = AUTONEG_DISABLE;
489 switch (phy_data->sfp_base) {
490 case AXGBE_SFP_BASE_1000_T:
491 case AXGBE_SFP_BASE_1000_CX:
492 case AXGBE_SFP_BASE_10000_CR:
493 pdata->phy.advertising |= ADVERTISED_TP;
496 pdata->phy.advertising |= ADVERTISED_FIBRE;
499 switch (phy_data->sfp_speed) {
500 case AXGBE_SFP_SPEED_100_1000:
501 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100)
502 pdata->phy.advertising |= ADVERTISED_100baseT_Full;
503 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000)
504 pdata->phy.advertising |= ADVERTISED_1000baseT_Full;
506 case AXGBE_SFP_SPEED_1000:
507 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000)
508 pdata->phy.advertising |= ADVERTISED_1000baseT_Full;
510 case AXGBE_SFP_SPEED_10000:
511 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000)
512 pdata->phy.advertising |= ADVERTISED_10000baseT_Full;
515 /* Choose the fastest supported speed */
516 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000)
517 pdata->phy.advertising |= ADVERTISED_10000baseT_Full;
518 else if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000)
519 pdata->phy.advertising |= ADVERTISED_1000baseT_Full;
520 else if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100)
521 pdata->phy.advertising |= ADVERTISED_100baseT_Full;
525 static bool axgbe_phy_sfp_bit_rate(struct axgbe_sfp_eeprom *sfp_eeprom,
526 enum axgbe_sfp_speed sfp_speed)
528 u8 *sfp_base, min, max;
530 sfp_base = sfp_eeprom->base;
533 case AXGBE_SFP_SPEED_1000:
534 min = AXGBE_SFP_BASE_BR_1GBE_MIN;
535 max = AXGBE_SFP_BASE_BR_1GBE_MAX;
537 case AXGBE_SFP_SPEED_10000:
538 min = AXGBE_SFP_BASE_BR_10GBE_MIN;
539 max = AXGBE_SFP_BASE_BR_10GBE_MAX;
545 return ((sfp_base[AXGBE_SFP_BASE_BR] >= min) &&
546 (sfp_base[AXGBE_SFP_BASE_BR] <= max));
549 static void axgbe_phy_sfp_external_phy(struct axgbe_port *pdata)
551 struct axgbe_phy_data *phy_data = pdata->phy_data;
553 if (!phy_data->sfp_changed)
556 phy_data->sfp_phy_avail = 0;
558 if (phy_data->sfp_base != AXGBE_SFP_BASE_1000_T)
562 static bool axgbe_phy_belfuse_parse_quirks(struct axgbe_port *pdata)
564 struct axgbe_phy_data *phy_data = pdata->phy_data;
565 struct axgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
567 if (memcmp(&sfp_eeprom->base[AXGBE_SFP_BASE_VENDOR_NAME],
568 AXGBE_BEL_FUSE_VENDOR, AXGBE_SFP_BASE_VENDOR_NAME_LEN))
571 if (!memcmp(&sfp_eeprom->base[AXGBE_SFP_BASE_VENDOR_PN],
572 AXGBE_BEL_FUSE_PARTNO, AXGBE_SFP_BASE_VENDOR_PN_LEN)) {
573 phy_data->sfp_base = AXGBE_SFP_BASE_1000_SX;
574 phy_data->sfp_cable = AXGBE_SFP_CABLE_ACTIVE;
575 phy_data->sfp_speed = AXGBE_SFP_SPEED_1000;
582 static bool axgbe_phy_sfp_parse_quirks(struct axgbe_port *pdata)
584 if (axgbe_phy_belfuse_parse_quirks(pdata))
590 static void axgbe_phy_sfp_parse_eeprom(struct axgbe_port *pdata)
592 struct axgbe_phy_data *phy_data = pdata->phy_data;
593 struct axgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
596 sfp_base = sfp_eeprom->base;
598 if (sfp_base[AXGBE_SFP_BASE_ID] != AXGBE_SFP_ID_SFP)
601 if (sfp_base[AXGBE_SFP_BASE_EXT_ID] != AXGBE_SFP_EXT_ID_SFP)
604 if (axgbe_phy_sfp_parse_quirks(pdata))
607 /* Assume ACTIVE cable unless told it is PASSIVE */
608 if (sfp_base[AXGBE_SFP_BASE_CABLE] & AXGBE_SFP_BASE_CABLE_PASSIVE) {
609 phy_data->sfp_cable = AXGBE_SFP_CABLE_PASSIVE;
610 phy_data->sfp_cable_len = sfp_base[AXGBE_SFP_BASE_CU_CABLE_LEN];
612 phy_data->sfp_cable = AXGBE_SFP_CABLE_ACTIVE;
615 /* Determine the type of SFP */
616 if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] & AXGBE_SFP_BASE_10GBE_CC_SR)
617 phy_data->sfp_base = AXGBE_SFP_BASE_10000_SR;
618 else if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] & AXGBE_SFP_BASE_10GBE_CC_LR)
619 phy_data->sfp_base = AXGBE_SFP_BASE_10000_LR;
620 else if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] &
621 AXGBE_SFP_BASE_10GBE_CC_LRM)
622 phy_data->sfp_base = AXGBE_SFP_BASE_10000_LRM;
623 else if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] & AXGBE_SFP_BASE_10GBE_CC_ER)
624 phy_data->sfp_base = AXGBE_SFP_BASE_10000_ER;
625 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_SX)
626 phy_data->sfp_base = AXGBE_SFP_BASE_1000_SX;
627 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_LX)
628 phy_data->sfp_base = AXGBE_SFP_BASE_1000_LX;
629 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_CX)
630 phy_data->sfp_base = AXGBE_SFP_BASE_1000_CX;
631 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_T)
632 phy_data->sfp_base = AXGBE_SFP_BASE_1000_T;
633 else if ((phy_data->sfp_cable == AXGBE_SFP_CABLE_PASSIVE) &&
634 axgbe_phy_sfp_bit_rate(sfp_eeprom, AXGBE_SFP_SPEED_10000))
635 phy_data->sfp_base = AXGBE_SFP_BASE_10000_CR;
637 switch (phy_data->sfp_base) {
638 case AXGBE_SFP_BASE_1000_T:
639 phy_data->sfp_speed = AXGBE_SFP_SPEED_100_1000;
641 case AXGBE_SFP_BASE_1000_SX:
642 case AXGBE_SFP_BASE_1000_LX:
643 case AXGBE_SFP_BASE_1000_CX:
644 phy_data->sfp_speed = AXGBE_SFP_SPEED_1000;
646 case AXGBE_SFP_BASE_10000_SR:
647 case AXGBE_SFP_BASE_10000_LR:
648 case AXGBE_SFP_BASE_10000_LRM:
649 case AXGBE_SFP_BASE_10000_ER:
650 case AXGBE_SFP_BASE_10000_CR:
651 phy_data->sfp_speed = AXGBE_SFP_SPEED_10000;
658 static bool axgbe_phy_sfp_verify_eeprom(uint8_t cc_in, uint8_t *buf,
663 for (cc = 0; len; buf++, len--)
666 return (cc == cc_in) ? true : false;
669 static int axgbe_phy_sfp_read_eeprom(struct axgbe_port *pdata)
671 struct axgbe_phy_data *phy_data = pdata->phy_data;
672 struct axgbe_sfp_eeprom sfp_eeprom;
676 ret = axgbe_phy_sfp_get_mux(pdata);
678 PMD_DRV_LOG(ERR, "I2C error setting SFP MUX\n");
682 /* Read the SFP serial ID eeprom */
684 ret = axgbe_phy_i2c_read(pdata, AXGBE_SFP_SERIAL_ID_ADDRESS,
685 &eeprom_addr, sizeof(eeprom_addr),
686 &sfp_eeprom, sizeof(sfp_eeprom));
688 PMD_DRV_LOG(ERR, "I2C error reading SFP EEPROM\n");
692 /* Validate the contents read */
693 if (!axgbe_phy_sfp_verify_eeprom(sfp_eeprom.base[AXGBE_SFP_BASE_CC],
695 sizeof(sfp_eeprom.base) - 1)) {
700 if (!axgbe_phy_sfp_verify_eeprom(sfp_eeprom.extd[AXGBE_SFP_EXTD_CC],
702 sizeof(sfp_eeprom.extd) - 1)) {
707 /* Check for an added or changed SFP */
708 if (memcmp(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom))) {
709 phy_data->sfp_changed = 1;
710 memcpy(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom));
712 if (sfp_eeprom.extd[AXGBE_SFP_EXTD_SFF_8472]) {
714 diag_type = sfp_eeprom.extd[AXGBE_SFP_EXTD_DIAG];
716 if (!(diag_type & AXGBE_SFP_EXTD_DIAG_ADDR_CHANGE))
717 phy_data->sfp_diags = 1;
720 phy_data->sfp_changed = 0;
724 axgbe_phy_sfp_put_mux(pdata);
729 static void axgbe_phy_sfp_signals(struct axgbe_port *pdata)
731 struct axgbe_phy_data *phy_data = pdata->phy_data;
732 unsigned int gpio_input;
733 u8 gpio_reg, gpio_ports[2];
736 /* Read the input port registers */
738 ret = axgbe_phy_i2c_read(pdata, phy_data->sfp_gpio_address,
739 &gpio_reg, sizeof(gpio_reg),
740 gpio_ports, sizeof(gpio_ports));
742 PMD_DRV_LOG(ERR, "I2C error reading SFP GPIOs\n");
746 gpio_input = (gpio_ports[1] << 8) | gpio_ports[0];
748 if (phy_data->sfp_gpio_mask & AXGBE_GPIO_NO_MOD_ABSENT) {
749 /* No GPIO, just assume the module is present for now */
750 phy_data->sfp_mod_absent = 0;
752 if (!(gpio_input & (1 << phy_data->sfp_gpio_mod_absent)))
753 phy_data->sfp_mod_absent = 0;
756 if (!(phy_data->sfp_gpio_mask & AXGBE_GPIO_NO_RX_LOS) &&
757 (gpio_input & (1 << phy_data->sfp_gpio_rx_los)))
758 phy_data->sfp_rx_los = 1;
760 if (!(phy_data->sfp_gpio_mask & AXGBE_GPIO_NO_TX_FAULT) &&
761 (gpio_input & (1 << phy_data->sfp_gpio_tx_fault)))
762 phy_data->sfp_tx_fault = 1;
765 static void axgbe_phy_sfp_mod_absent(struct axgbe_port *pdata)
767 struct axgbe_phy_data *phy_data = pdata->phy_data;
769 phy_data->sfp_mod_absent = 1;
770 phy_data->sfp_phy_avail = 0;
771 memset(&phy_data->sfp_eeprom, 0, sizeof(phy_data->sfp_eeprom));
774 static void axgbe_phy_sfp_reset(struct axgbe_phy_data *phy_data)
776 phy_data->sfp_rx_los = 0;
777 phy_data->sfp_tx_fault = 0;
778 phy_data->sfp_mod_absent = 1;
779 phy_data->sfp_diags = 0;
780 phy_data->sfp_base = AXGBE_SFP_BASE_UNKNOWN;
781 phy_data->sfp_cable = AXGBE_SFP_CABLE_UNKNOWN;
782 phy_data->sfp_speed = AXGBE_SFP_SPEED_UNKNOWN;
785 static void axgbe_phy_sfp_detect(struct axgbe_port *pdata)
787 struct axgbe_phy_data *phy_data = pdata->phy_data;
790 /* Reset the SFP signals and info */
791 axgbe_phy_sfp_reset(phy_data);
793 ret = axgbe_phy_get_comm_ownership(pdata);
797 /* Read the SFP signals and check for module presence */
798 axgbe_phy_sfp_signals(pdata);
799 if (phy_data->sfp_mod_absent) {
800 axgbe_phy_sfp_mod_absent(pdata);
804 ret = axgbe_phy_sfp_read_eeprom(pdata);
806 /* Treat any error as if there isn't an SFP plugged in */
807 axgbe_phy_sfp_reset(phy_data);
808 axgbe_phy_sfp_mod_absent(pdata);
812 axgbe_phy_sfp_parse_eeprom(pdata);
813 axgbe_phy_sfp_external_phy(pdata);
816 axgbe_phy_sfp_phy_settings(pdata);
817 axgbe_phy_put_comm_ownership(pdata);
820 static void axgbe_phy_phydev_flowctrl(struct axgbe_port *pdata)
822 pdata->phy.tx_pause = 0;
823 pdata->phy.rx_pause = 0;
826 static enum axgbe_mode axgbe_phy_an73_redrv_outcome(struct axgbe_port *pdata)
828 struct axgbe_phy_data *phy_data = pdata->phy_data;
829 enum axgbe_mode mode;
830 unsigned int ad_reg, lp_reg;
832 pdata->phy.lp_advertising |= ADVERTISED_Autoneg;
833 pdata->phy.lp_advertising |= ADVERTISED_Backplane;
835 /* Use external PHY to determine flow control */
836 if (pdata->phy.pause_autoneg)
837 axgbe_phy_phydev_flowctrl(pdata);
839 /* Compare Advertisement and Link Partner register 2 */
840 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
841 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
843 pdata->phy.lp_advertising |= ADVERTISED_10000baseKR_Full;
845 pdata->phy.lp_advertising |= ADVERTISED_1000baseKX_Full;
849 switch (phy_data->port_mode) {
850 case AXGBE_PORT_MODE_BACKPLANE:
851 mode = AXGBE_MODE_KR;
854 mode = AXGBE_MODE_SFI;
857 } else if (ad_reg & 0x20) {
858 switch (phy_data->port_mode) {
859 case AXGBE_PORT_MODE_BACKPLANE:
860 mode = AXGBE_MODE_KX_1000;
862 case AXGBE_PORT_MODE_1000BASE_X:
865 case AXGBE_PORT_MODE_SFP:
866 switch (phy_data->sfp_base) {
867 case AXGBE_SFP_BASE_1000_T:
868 mode = AXGBE_MODE_SGMII_1000;
870 case AXGBE_SFP_BASE_1000_SX:
871 case AXGBE_SFP_BASE_1000_LX:
872 case AXGBE_SFP_BASE_1000_CX:
879 mode = AXGBE_MODE_SGMII_1000;
883 mode = AXGBE_MODE_UNKNOWN;
886 /* Compare Advertisement and Link Partner register 3 */
887 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
888 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
890 pdata->phy.lp_advertising |= ADVERTISED_10000baseR_FEC;
895 static enum axgbe_mode axgbe_phy_an73_outcome(struct axgbe_port *pdata)
897 enum axgbe_mode mode;
898 unsigned int ad_reg, lp_reg;
900 pdata->phy.lp_advertising |= ADVERTISED_Autoneg;
901 pdata->phy.lp_advertising |= ADVERTISED_Backplane;
903 /* Compare Advertisement and Link Partner register 1 */
904 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
905 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA);
907 pdata->phy.lp_advertising |= ADVERTISED_Pause;
909 pdata->phy.lp_advertising |= ADVERTISED_Asym_Pause;
911 if (pdata->phy.pause_autoneg) {
912 /* Set flow control based on auto-negotiation result */
913 pdata->phy.tx_pause = 0;
914 pdata->phy.rx_pause = 0;
916 if (ad_reg & lp_reg & 0x400) {
917 pdata->phy.tx_pause = 1;
918 pdata->phy.rx_pause = 1;
919 } else if (ad_reg & lp_reg & 0x800) {
921 pdata->phy.rx_pause = 1;
922 else if (lp_reg & 0x400)
923 pdata->phy.tx_pause = 1;
927 /* Compare Advertisement and Link Partner register 2 */
928 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
929 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
931 pdata->phy.lp_advertising |= ADVERTISED_10000baseKR_Full;
933 pdata->phy.lp_advertising |= ADVERTISED_1000baseKX_Full;
937 mode = AXGBE_MODE_KR;
938 else if (ad_reg & 0x20)
939 mode = AXGBE_MODE_KX_1000;
941 mode = AXGBE_MODE_UNKNOWN;
943 /* Compare Advertisement and Link Partner register 3 */
944 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
945 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
947 pdata->phy.lp_advertising |= ADVERTISED_10000baseR_FEC;
952 static enum axgbe_mode axgbe_phy_an_outcome(struct axgbe_port *pdata)
954 switch (pdata->an_mode) {
955 case AXGBE_AN_MODE_CL73:
956 return axgbe_phy_an73_outcome(pdata);
957 case AXGBE_AN_MODE_CL73_REDRV:
958 return axgbe_phy_an73_redrv_outcome(pdata);
959 case AXGBE_AN_MODE_CL37:
960 case AXGBE_AN_MODE_CL37_SGMII:
962 return AXGBE_MODE_UNKNOWN;
966 static unsigned int axgbe_phy_an_advertising(struct axgbe_port *pdata)
968 struct axgbe_phy_data *phy_data = pdata->phy_data;
969 unsigned int advertising;
971 /* Without a re-driver, just return current advertising */
972 if (!phy_data->redrv)
973 return pdata->phy.advertising;
975 /* With the KR re-driver we need to advertise a single speed */
976 advertising = pdata->phy.advertising;
977 advertising &= ~ADVERTISED_1000baseKX_Full;
978 advertising &= ~ADVERTISED_10000baseKR_Full;
980 switch (phy_data->port_mode) {
981 case AXGBE_PORT_MODE_BACKPLANE:
982 advertising |= ADVERTISED_10000baseKR_Full;
984 case AXGBE_PORT_MODE_BACKPLANE_2500:
985 advertising |= ADVERTISED_1000baseKX_Full;
987 case AXGBE_PORT_MODE_1000BASE_T:
988 case AXGBE_PORT_MODE_1000BASE_X:
989 case AXGBE_PORT_MODE_NBASE_T:
990 advertising |= ADVERTISED_1000baseKX_Full;
992 case AXGBE_PORT_MODE_10GBASE_T:
993 PMD_DRV_LOG(ERR, "10GBASE_T mode is not supported\n");
995 case AXGBE_PORT_MODE_10GBASE_R:
996 advertising |= ADVERTISED_10000baseKR_Full;
998 case AXGBE_PORT_MODE_SFP:
999 switch (phy_data->sfp_base) {
1000 case AXGBE_SFP_BASE_1000_T:
1001 case AXGBE_SFP_BASE_1000_SX:
1002 case AXGBE_SFP_BASE_1000_LX:
1003 case AXGBE_SFP_BASE_1000_CX:
1004 advertising |= ADVERTISED_1000baseKX_Full;
1007 advertising |= ADVERTISED_10000baseKR_Full;
1012 advertising |= ADVERTISED_10000baseKR_Full;
1019 static int axgbe_phy_an_config(struct axgbe_port *pdata __rte_unused)
1022 /* Dummy API since there is no case to support
1023 * external phy devices registred through kerenl apis
1027 static enum axgbe_an_mode axgbe_phy_an_sfp_mode(struct axgbe_phy_data *phy_data)
1029 switch (phy_data->sfp_base) {
1030 case AXGBE_SFP_BASE_1000_T:
1031 return AXGBE_AN_MODE_CL37_SGMII;
1032 case AXGBE_SFP_BASE_1000_SX:
1033 case AXGBE_SFP_BASE_1000_LX:
1034 case AXGBE_SFP_BASE_1000_CX:
1035 return AXGBE_AN_MODE_CL37;
1037 return AXGBE_AN_MODE_NONE;
1041 static enum axgbe_an_mode axgbe_phy_an_mode(struct axgbe_port *pdata)
1043 struct axgbe_phy_data *phy_data = pdata->phy_data;
1045 /* A KR re-driver will always require CL73 AN */
1046 if (phy_data->redrv)
1047 return AXGBE_AN_MODE_CL73_REDRV;
1049 switch (phy_data->port_mode) {
1050 case AXGBE_PORT_MODE_BACKPLANE:
1051 return AXGBE_AN_MODE_CL73;
1052 case AXGBE_PORT_MODE_BACKPLANE_2500:
1053 return AXGBE_AN_MODE_NONE;
1054 case AXGBE_PORT_MODE_1000BASE_T:
1055 return AXGBE_AN_MODE_CL37_SGMII;
1056 case AXGBE_PORT_MODE_1000BASE_X:
1057 return AXGBE_AN_MODE_CL37;
1058 case AXGBE_PORT_MODE_NBASE_T:
1059 return AXGBE_AN_MODE_CL37_SGMII;
1060 case AXGBE_PORT_MODE_10GBASE_T:
1061 return AXGBE_AN_MODE_CL73;
1062 case AXGBE_PORT_MODE_10GBASE_R:
1063 return AXGBE_AN_MODE_NONE;
1064 case AXGBE_PORT_MODE_SFP:
1065 return axgbe_phy_an_sfp_mode(phy_data);
1067 return AXGBE_AN_MODE_NONE;
1071 static int axgbe_phy_set_redrv_mode_mdio(struct axgbe_port *pdata,
1072 enum axgbe_phy_redrv_mode mode)
1074 struct axgbe_phy_data *phy_data = pdata->phy_data;
1075 u16 redrv_reg, redrv_val;
1077 redrv_reg = AXGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
1078 redrv_val = (u16)mode;
1080 return pdata->hw_if.write_ext_mii_regs(pdata, phy_data->redrv_addr,
1081 redrv_reg, redrv_val);
1084 static int axgbe_phy_set_redrv_mode_i2c(struct axgbe_port *pdata,
1085 enum axgbe_phy_redrv_mode mode)
1087 struct axgbe_phy_data *phy_data = pdata->phy_data;
1088 unsigned int redrv_reg;
1091 /* Calculate the register to write */
1092 redrv_reg = AXGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
1094 ret = axgbe_phy_redrv_write(pdata, redrv_reg, mode);
1099 static void axgbe_phy_set_redrv_mode(struct axgbe_port *pdata)
1101 struct axgbe_phy_data *phy_data = pdata->phy_data;
1102 enum axgbe_phy_redrv_mode mode;
1105 if (!phy_data->redrv)
1108 mode = AXGBE_PHY_REDRV_MODE_CX;
1109 if ((phy_data->port_mode == AXGBE_PORT_MODE_SFP) &&
1110 (phy_data->sfp_base != AXGBE_SFP_BASE_1000_CX) &&
1111 (phy_data->sfp_base != AXGBE_SFP_BASE_10000_CR))
1112 mode = AXGBE_PHY_REDRV_MODE_SR;
1114 ret = axgbe_phy_get_comm_ownership(pdata);
1118 if (phy_data->redrv_if)
1119 axgbe_phy_set_redrv_mode_i2c(pdata, mode);
1121 axgbe_phy_set_redrv_mode_mdio(pdata, mode);
1123 axgbe_phy_put_comm_ownership(pdata);
1126 static void axgbe_phy_start_ratechange(struct axgbe_port *pdata)
1128 if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
1132 static void axgbe_phy_complete_ratechange(struct axgbe_port *pdata)
1136 /* Wait for command to complete */
1137 wait = AXGBE_RATECHANGE_COUNT;
1139 if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
1146 static void axgbe_phy_rrc(struct axgbe_port *pdata)
1150 axgbe_phy_start_ratechange(pdata);
1152 /* Receiver Reset Cycle */
1154 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 5);
1155 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0);
1157 /* Call FW to make the change */
1158 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
1159 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
1160 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
1162 axgbe_phy_complete_ratechange(pdata);
1165 static void axgbe_phy_power_off(struct axgbe_port *pdata)
1167 struct axgbe_phy_data *phy_data = pdata->phy_data;
1169 axgbe_phy_start_ratechange(pdata);
1171 /* Call FW to make the change */
1172 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, 0);
1173 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
1174 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
1175 axgbe_phy_complete_ratechange(pdata);
1176 phy_data->cur_mode = AXGBE_MODE_UNKNOWN;
1179 static void axgbe_phy_sfi_mode(struct axgbe_port *pdata)
1181 struct axgbe_phy_data *phy_data = pdata->phy_data;
1184 axgbe_phy_set_redrv_mode(pdata);
1186 axgbe_phy_start_ratechange(pdata);
1190 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 3);
1191 if (phy_data->sfp_cable != AXGBE_SFP_CABLE_PASSIVE) {
1192 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0);
1194 if (phy_data->sfp_cable_len <= 1)
1195 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 1);
1196 else if (phy_data->sfp_cable_len <= 3)
1197 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 2);
1199 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 3);
1202 /* Call FW to make the change */
1203 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
1204 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
1205 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
1206 axgbe_phy_complete_ratechange(pdata);
1207 phy_data->cur_mode = AXGBE_MODE_SFI;
1210 static void axgbe_phy_kr_mode(struct axgbe_port *pdata)
1212 struct axgbe_phy_data *phy_data = pdata->phy_data;
1215 axgbe_phy_set_redrv_mode(pdata);
1217 axgbe_phy_start_ratechange(pdata);
1221 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 4);
1222 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0);
1224 /* Call FW to make the change */
1225 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
1226 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
1227 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
1228 axgbe_phy_complete_ratechange(pdata);
1229 phy_data->cur_mode = AXGBE_MODE_KR;
1232 static enum axgbe_mode axgbe_phy_cur_mode(struct axgbe_port *pdata)
1234 struct axgbe_phy_data *phy_data = pdata->phy_data;
1236 return phy_data->cur_mode;
1239 static enum axgbe_mode axgbe_phy_switch_baset_mode(struct axgbe_port *pdata)
1241 struct axgbe_phy_data *phy_data = pdata->phy_data;
1243 /* No switching if not 10GBase-T */
1244 if (phy_data->port_mode != AXGBE_PORT_MODE_10GBASE_T)
1245 return axgbe_phy_cur_mode(pdata);
1247 switch (axgbe_phy_cur_mode(pdata)) {
1248 case AXGBE_MODE_SGMII_100:
1249 case AXGBE_MODE_SGMII_1000:
1250 return AXGBE_MODE_KR;
1253 return AXGBE_MODE_SGMII_1000;
1257 static enum axgbe_mode axgbe_phy_switch_bp_2500_mode(struct axgbe_port *pdata
1260 return AXGBE_MODE_KX_2500;
1263 static enum axgbe_mode axgbe_phy_switch_bp_mode(struct axgbe_port *pdata)
1265 /* If we are in KR switch to KX, and vice-versa */
1266 switch (axgbe_phy_cur_mode(pdata)) {
1267 case AXGBE_MODE_KX_1000:
1268 return AXGBE_MODE_KR;
1271 return AXGBE_MODE_KX_1000;
1275 static enum axgbe_mode axgbe_phy_switch_mode(struct axgbe_port *pdata)
1277 struct axgbe_phy_data *phy_data = pdata->phy_data;
1279 switch (phy_data->port_mode) {
1280 case AXGBE_PORT_MODE_BACKPLANE:
1281 return axgbe_phy_switch_bp_mode(pdata);
1282 case AXGBE_PORT_MODE_BACKPLANE_2500:
1283 return axgbe_phy_switch_bp_2500_mode(pdata);
1284 case AXGBE_PORT_MODE_1000BASE_T:
1285 case AXGBE_PORT_MODE_NBASE_T:
1286 case AXGBE_PORT_MODE_10GBASE_T:
1287 return axgbe_phy_switch_baset_mode(pdata);
1288 case AXGBE_PORT_MODE_1000BASE_X:
1289 case AXGBE_PORT_MODE_10GBASE_R:
1290 case AXGBE_PORT_MODE_SFP:
1291 /* No switching, so just return current mode */
1292 return axgbe_phy_cur_mode(pdata);
1294 return AXGBE_MODE_UNKNOWN;
1298 static enum axgbe_mode axgbe_phy_get_basex_mode(struct axgbe_phy_data *phy_data
1304 return AXGBE_MODE_X;
1306 return AXGBE_MODE_KR;
1308 return AXGBE_MODE_UNKNOWN;
1312 static enum axgbe_mode axgbe_phy_get_baset_mode(struct axgbe_phy_data *phy_data
1318 return AXGBE_MODE_SGMII_100;
1320 return AXGBE_MODE_SGMII_1000;
1322 return AXGBE_MODE_KR;
1324 return AXGBE_MODE_UNKNOWN;
1328 static enum axgbe_mode axgbe_phy_get_sfp_mode(struct axgbe_phy_data *phy_data,
1333 return AXGBE_MODE_SGMII_100;
1335 if (phy_data->sfp_base == AXGBE_SFP_BASE_1000_T)
1336 return AXGBE_MODE_SGMII_1000;
1338 return AXGBE_MODE_X;
1341 return AXGBE_MODE_SFI;
1343 return AXGBE_MODE_UNKNOWN;
1347 static enum axgbe_mode axgbe_phy_get_bp_2500_mode(int speed)
1351 return AXGBE_MODE_KX_2500;
1353 return AXGBE_MODE_UNKNOWN;
1357 static enum axgbe_mode axgbe_phy_get_bp_mode(int speed)
1361 return AXGBE_MODE_KX_1000;
1363 return AXGBE_MODE_KR;
1365 return AXGBE_MODE_UNKNOWN;
1369 static enum axgbe_mode axgbe_phy_get_mode(struct axgbe_port *pdata,
1372 struct axgbe_phy_data *phy_data = pdata->phy_data;
1374 switch (phy_data->port_mode) {
1375 case AXGBE_PORT_MODE_BACKPLANE:
1376 return axgbe_phy_get_bp_mode(speed);
1377 case AXGBE_PORT_MODE_BACKPLANE_2500:
1378 return axgbe_phy_get_bp_2500_mode(speed);
1379 case AXGBE_PORT_MODE_1000BASE_T:
1380 case AXGBE_PORT_MODE_NBASE_T:
1381 case AXGBE_PORT_MODE_10GBASE_T:
1382 return axgbe_phy_get_baset_mode(phy_data, speed);
1383 case AXGBE_PORT_MODE_1000BASE_X:
1384 case AXGBE_PORT_MODE_10GBASE_R:
1385 return axgbe_phy_get_basex_mode(phy_data, speed);
1386 case AXGBE_PORT_MODE_SFP:
1387 return axgbe_phy_get_sfp_mode(phy_data, speed);
1389 return AXGBE_MODE_UNKNOWN;
1393 static void axgbe_phy_set_mode(struct axgbe_port *pdata, enum axgbe_mode mode)
1397 axgbe_phy_kr_mode(pdata);
1399 case AXGBE_MODE_SFI:
1400 axgbe_phy_sfi_mode(pdata);
1407 static bool axgbe_phy_check_mode(struct axgbe_port *pdata,
1408 enum axgbe_mode mode, u32 advert)
1410 if (pdata->phy.autoneg == AUTONEG_ENABLE) {
1411 if (pdata->phy.advertising & advert)
1414 enum axgbe_mode cur_mode;
1416 cur_mode = axgbe_phy_get_mode(pdata, pdata->phy.speed);
1417 if (cur_mode == mode)
1424 static bool axgbe_phy_use_basex_mode(struct axgbe_port *pdata,
1425 enum axgbe_mode mode)
1429 return axgbe_phy_check_mode(pdata, mode,
1430 ADVERTISED_1000baseT_Full);
1432 return axgbe_phy_check_mode(pdata, mode,
1433 ADVERTISED_10000baseT_Full);
1439 static bool axgbe_phy_use_baset_mode(struct axgbe_port *pdata,
1440 enum axgbe_mode mode)
1443 case AXGBE_MODE_SGMII_100:
1444 return axgbe_phy_check_mode(pdata, mode,
1445 ADVERTISED_100baseT_Full);
1446 case AXGBE_MODE_SGMII_1000:
1447 return axgbe_phy_check_mode(pdata, mode,
1448 ADVERTISED_1000baseT_Full);
1450 return axgbe_phy_check_mode(pdata, mode,
1451 ADVERTISED_10000baseT_Full);
1457 static bool axgbe_phy_use_sfp_mode(struct axgbe_port *pdata,
1458 enum axgbe_mode mode)
1460 struct axgbe_phy_data *phy_data = pdata->phy_data;
1464 if (phy_data->sfp_base == AXGBE_SFP_BASE_1000_T)
1466 return axgbe_phy_check_mode(pdata, mode,
1467 ADVERTISED_1000baseT_Full);
1468 case AXGBE_MODE_SGMII_100:
1469 if (phy_data->sfp_base != AXGBE_SFP_BASE_1000_T)
1471 return axgbe_phy_check_mode(pdata, mode,
1472 ADVERTISED_100baseT_Full);
1473 case AXGBE_MODE_SGMII_1000:
1474 if (phy_data->sfp_base != AXGBE_SFP_BASE_1000_T)
1476 return axgbe_phy_check_mode(pdata, mode,
1477 ADVERTISED_1000baseT_Full);
1478 case AXGBE_MODE_SFI:
1479 return axgbe_phy_check_mode(pdata, mode,
1480 ADVERTISED_10000baseT_Full);
1486 static bool axgbe_phy_use_bp_2500_mode(struct axgbe_port *pdata,
1487 enum axgbe_mode mode)
1490 case AXGBE_MODE_KX_2500:
1491 return axgbe_phy_check_mode(pdata, mode,
1492 ADVERTISED_2500baseX_Full);
1498 static bool axgbe_phy_use_bp_mode(struct axgbe_port *pdata,
1499 enum axgbe_mode mode)
1502 case AXGBE_MODE_KX_1000:
1503 return axgbe_phy_check_mode(pdata, mode,
1504 ADVERTISED_1000baseKX_Full);
1506 return axgbe_phy_check_mode(pdata, mode,
1507 ADVERTISED_10000baseKR_Full);
1513 static bool axgbe_phy_use_mode(struct axgbe_port *pdata, enum axgbe_mode mode)
1515 struct axgbe_phy_data *phy_data = pdata->phy_data;
1517 switch (phy_data->port_mode) {
1518 case AXGBE_PORT_MODE_BACKPLANE:
1519 return axgbe_phy_use_bp_mode(pdata, mode);
1520 case AXGBE_PORT_MODE_BACKPLANE_2500:
1521 return axgbe_phy_use_bp_2500_mode(pdata, mode);
1522 case AXGBE_PORT_MODE_1000BASE_T:
1523 case AXGBE_PORT_MODE_NBASE_T:
1524 case AXGBE_PORT_MODE_10GBASE_T:
1525 return axgbe_phy_use_baset_mode(pdata, mode);
1526 case AXGBE_PORT_MODE_1000BASE_X:
1527 case AXGBE_PORT_MODE_10GBASE_R:
1528 return axgbe_phy_use_basex_mode(pdata, mode);
1529 case AXGBE_PORT_MODE_SFP:
1530 return axgbe_phy_use_sfp_mode(pdata, mode);
1536 static int axgbe_phy_link_status(struct axgbe_port *pdata, int *an_restart)
1538 struct axgbe_phy_data *phy_data = pdata->phy_data;
1543 if (phy_data->port_mode == AXGBE_PORT_MODE_SFP) {
1544 /* Check SFP signals */
1545 axgbe_phy_sfp_detect(pdata);
1547 if (phy_data->sfp_changed) {
1552 if (phy_data->sfp_mod_absent || phy_data->sfp_rx_los)
1556 /* Link status is latched low, so read once to clear
1557 * and then read again to get current state
1559 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
1560 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
1561 if (reg & MDIO_STAT1_LSTATUS)
1564 /* No link, attempt a receiver reset cycle */
1565 if (phy_data->rrc_count++) {
1566 phy_data->rrc_count = 0;
1567 axgbe_phy_rrc(pdata);
1573 static void axgbe_phy_sfp_gpio_setup(struct axgbe_port *pdata)
1575 struct axgbe_phy_data *phy_data = pdata->phy_data;
1578 reg = XP_IOREAD(pdata, XP_PROP_3);
1580 phy_data->sfp_gpio_address = AXGBE_GPIO_ADDRESS_PCA9555 +
1581 XP_GET_BITS(reg, XP_PROP_3, GPIO_ADDR);
1583 phy_data->sfp_gpio_mask = XP_GET_BITS(reg, XP_PROP_3, GPIO_MASK);
1585 phy_data->sfp_gpio_rx_los = XP_GET_BITS(reg, XP_PROP_3,
1587 phy_data->sfp_gpio_tx_fault = XP_GET_BITS(reg, XP_PROP_3,
1589 phy_data->sfp_gpio_mod_absent = XP_GET_BITS(reg, XP_PROP_3,
1591 phy_data->sfp_gpio_rate_select = XP_GET_BITS(reg, XP_PROP_3,
1595 static void axgbe_phy_sfp_comm_setup(struct axgbe_port *pdata)
1597 struct axgbe_phy_data *phy_data = pdata->phy_data;
1598 unsigned int reg, mux_addr_hi, mux_addr_lo;
1600 reg = XP_IOREAD(pdata, XP_PROP_4);
1602 mux_addr_hi = XP_GET_BITS(reg, XP_PROP_4, MUX_ADDR_HI);
1603 mux_addr_lo = XP_GET_BITS(reg, XP_PROP_4, MUX_ADDR_LO);
1604 if (mux_addr_lo == AXGBE_SFP_DIRECT)
1607 phy_data->sfp_comm = AXGBE_SFP_COMM_PCA9545;
1608 phy_data->sfp_mux_address = (mux_addr_hi << 2) + mux_addr_lo;
1609 phy_data->sfp_mux_channel = XP_GET_BITS(reg, XP_PROP_4, MUX_CHAN);
1612 static void axgbe_phy_sfp_setup(struct axgbe_port *pdata)
1614 axgbe_phy_sfp_comm_setup(pdata);
1615 axgbe_phy_sfp_gpio_setup(pdata);
1618 static bool axgbe_phy_redrv_error(struct axgbe_phy_data *phy_data)
1620 if (!phy_data->redrv)
1623 if (phy_data->redrv_if >= AXGBE_PHY_REDRV_IF_MAX)
1626 switch (phy_data->redrv_model) {
1627 case AXGBE_PHY_REDRV_MODEL_4223:
1628 if (phy_data->redrv_lane > 3)
1631 case AXGBE_PHY_REDRV_MODEL_4227:
1632 if (phy_data->redrv_lane > 1)
1642 static int axgbe_phy_mdio_reset_setup(struct axgbe_port *pdata)
1644 struct axgbe_phy_data *phy_data = pdata->phy_data;
1647 if (phy_data->conn_type != AXGBE_CONN_TYPE_MDIO)
1649 reg = XP_IOREAD(pdata, XP_PROP_3);
1650 phy_data->mdio_reset = XP_GET_BITS(reg, XP_PROP_3, MDIO_RESET);
1651 switch (phy_data->mdio_reset) {
1652 case AXGBE_MDIO_RESET_NONE:
1653 case AXGBE_MDIO_RESET_I2C_GPIO:
1654 case AXGBE_MDIO_RESET_INT_GPIO:
1657 PMD_DRV_LOG(ERR, "unsupported MDIO reset (%#x)\n",
1658 phy_data->mdio_reset);
1661 if (phy_data->mdio_reset == AXGBE_MDIO_RESET_I2C_GPIO) {
1662 phy_data->mdio_reset_addr = AXGBE_GPIO_ADDRESS_PCA9555 +
1663 XP_GET_BITS(reg, XP_PROP_3,
1664 MDIO_RESET_I2C_ADDR);
1665 phy_data->mdio_reset_gpio = XP_GET_BITS(reg, XP_PROP_3,
1666 MDIO_RESET_I2C_GPIO);
1667 } else if (phy_data->mdio_reset == AXGBE_MDIO_RESET_INT_GPIO) {
1668 phy_data->mdio_reset_gpio = XP_GET_BITS(reg, XP_PROP_3,
1669 MDIO_RESET_INT_GPIO);
1675 static bool axgbe_phy_port_mode_mismatch(struct axgbe_port *pdata)
1677 struct axgbe_phy_data *phy_data = pdata->phy_data;
1679 switch (phy_data->port_mode) {
1680 case AXGBE_PORT_MODE_BACKPLANE:
1681 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) ||
1682 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000))
1685 case AXGBE_PORT_MODE_BACKPLANE_2500:
1686 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_2500)
1689 case AXGBE_PORT_MODE_1000BASE_T:
1690 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) ||
1691 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000))
1694 case AXGBE_PORT_MODE_1000BASE_X:
1695 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000)
1698 case AXGBE_PORT_MODE_NBASE_T:
1699 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) ||
1700 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) ||
1701 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_2500))
1704 case AXGBE_PORT_MODE_10GBASE_T:
1705 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) ||
1706 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) ||
1707 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000))
1710 case AXGBE_PORT_MODE_10GBASE_R:
1711 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000)
1714 case AXGBE_PORT_MODE_SFP:
1715 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) ||
1716 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) ||
1717 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000))
1727 static bool axgbe_phy_conn_type_mismatch(struct axgbe_port *pdata)
1729 struct axgbe_phy_data *phy_data = pdata->phy_data;
1731 switch (phy_data->port_mode) {
1732 case AXGBE_PORT_MODE_BACKPLANE:
1733 case AXGBE_PORT_MODE_BACKPLANE_2500:
1734 if (phy_data->conn_type == AXGBE_CONN_TYPE_BACKPLANE)
1737 case AXGBE_PORT_MODE_1000BASE_T:
1738 case AXGBE_PORT_MODE_1000BASE_X:
1739 case AXGBE_PORT_MODE_NBASE_T:
1740 case AXGBE_PORT_MODE_10GBASE_T:
1741 case AXGBE_PORT_MODE_10GBASE_R:
1742 if (phy_data->conn_type == AXGBE_CONN_TYPE_MDIO)
1745 case AXGBE_PORT_MODE_SFP:
1746 if (phy_data->conn_type == AXGBE_CONN_TYPE_SFP)
1756 static bool axgbe_phy_port_enabled(struct axgbe_port *pdata)
1760 reg = XP_IOREAD(pdata, XP_PROP_0);
1761 if (!XP_GET_BITS(reg, XP_PROP_0, PORT_SPEEDS))
1763 if (!XP_GET_BITS(reg, XP_PROP_0, CONN_TYPE))
1769 static void axgbe_phy_stop(struct axgbe_port *pdata)
1771 struct axgbe_phy_data *phy_data = pdata->phy_data;
1773 /* Reset SFP data */
1774 axgbe_phy_sfp_reset(phy_data);
1775 axgbe_phy_sfp_mod_absent(pdata);
1777 /* Power off the PHY */
1778 axgbe_phy_power_off(pdata);
1780 /* Stop the I2C controller */
1781 pdata->i2c_if.i2c_stop(pdata);
1784 static int axgbe_phy_start(struct axgbe_port *pdata)
1786 struct axgbe_phy_data *phy_data = pdata->phy_data;
1789 /* Start the I2C controller */
1790 ret = pdata->i2c_if.i2c_start(pdata);
1794 /* Start in highest supported mode */
1795 axgbe_phy_set_mode(pdata, phy_data->start_mode);
1797 /* After starting the I2C controller, we can check for an SFP */
1798 switch (phy_data->port_mode) {
1799 case AXGBE_PORT_MODE_SFP:
1800 axgbe_phy_sfp_detect(pdata);
1809 static int axgbe_phy_reset(struct axgbe_port *pdata)
1811 struct axgbe_phy_data *phy_data = pdata->phy_data;
1812 enum axgbe_mode cur_mode;
1814 /* Reset by power cycling the PHY */
1815 cur_mode = phy_data->cur_mode;
1816 axgbe_phy_power_off(pdata);
1817 /* First time reset is done with passed unknown mode*/
1818 axgbe_phy_set_mode(pdata, cur_mode);
1822 static int axgbe_phy_init(struct axgbe_port *pdata)
1824 struct axgbe_phy_data *phy_data;
1828 /* Check if enabled */
1829 if (!axgbe_phy_port_enabled(pdata)) {
1830 PMD_DRV_LOG(ERR, "device is not enabled\n");
1834 /* Initialize the I2C controller */
1835 ret = pdata->i2c_if.i2c_init(pdata);
1839 phy_data = rte_zmalloc("phy_data memory", sizeof(*phy_data), 0);
1841 PMD_DRV_LOG(ERR, "phy_data allocation failed\n");
1844 pdata->phy_data = phy_data;
1846 reg = XP_IOREAD(pdata, XP_PROP_0);
1847 phy_data->port_mode = XP_GET_BITS(reg, XP_PROP_0, PORT_MODE);
1848 phy_data->port_id = XP_GET_BITS(reg, XP_PROP_0, PORT_ID);
1849 phy_data->port_speeds = XP_GET_BITS(reg, XP_PROP_0, PORT_SPEEDS);
1850 phy_data->conn_type = XP_GET_BITS(reg, XP_PROP_0, CONN_TYPE);
1851 phy_data->mdio_addr = XP_GET_BITS(reg, XP_PROP_0, MDIO_ADDR);
1853 reg = XP_IOREAD(pdata, XP_PROP_4);
1854 phy_data->redrv = XP_GET_BITS(reg, XP_PROP_4, REDRV_PRESENT);
1855 phy_data->redrv_if = XP_GET_BITS(reg, XP_PROP_4, REDRV_IF);
1856 phy_data->redrv_addr = XP_GET_BITS(reg, XP_PROP_4, REDRV_ADDR);
1857 phy_data->redrv_lane = XP_GET_BITS(reg, XP_PROP_4, REDRV_LANE);
1858 phy_data->redrv_model = XP_GET_BITS(reg, XP_PROP_4, REDRV_MODEL);
1860 /* Validate the connection requested */
1861 if (axgbe_phy_conn_type_mismatch(pdata)) {
1862 PMD_DRV_LOG(ERR, "phy mode/connection mismatch (%#x/%#x)\n",
1863 phy_data->port_mode, phy_data->conn_type);
1867 /* Validate the mode requested */
1868 if (axgbe_phy_port_mode_mismatch(pdata)) {
1869 PMD_DRV_LOG(ERR, "phy mode/speed mismatch (%#x/%#x)\n",
1870 phy_data->port_mode, phy_data->port_speeds);
1874 /* Check for and validate MDIO reset support */
1875 ret = axgbe_phy_mdio_reset_setup(pdata);
1879 /* Validate the re-driver information */
1880 if (axgbe_phy_redrv_error(phy_data)) {
1881 PMD_DRV_LOG(ERR, "phy re-driver settings error\n");
1884 pdata->kr_redrv = phy_data->redrv;
1886 /* Indicate current mode is unknown */
1887 phy_data->cur_mode = AXGBE_MODE_UNKNOWN;
1889 /* Initialize supported features */
1890 pdata->phy.supported = 0;
1892 switch (phy_data->port_mode) {
1893 /* Backplane support */
1894 case AXGBE_PORT_MODE_BACKPLANE:
1895 pdata->phy.supported |= SUPPORTED_Autoneg;
1896 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
1897 pdata->phy.supported |= SUPPORTED_Backplane;
1898 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) {
1899 pdata->phy.supported |= SUPPORTED_1000baseKX_Full;
1900 phy_data->start_mode = AXGBE_MODE_KX_1000;
1902 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) {
1903 pdata->phy.supported |= SUPPORTED_10000baseKR_Full;
1904 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
1905 pdata->phy.supported |=
1906 SUPPORTED_10000baseR_FEC;
1907 phy_data->start_mode = AXGBE_MODE_KR;
1910 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE;
1912 case AXGBE_PORT_MODE_BACKPLANE_2500:
1913 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
1914 pdata->phy.supported |= SUPPORTED_Backplane;
1915 pdata->phy.supported |= SUPPORTED_2500baseX_Full;
1916 phy_data->start_mode = AXGBE_MODE_KX_2500;
1918 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE;
1921 /* MDIO 1GBase-T support */
1922 case AXGBE_PORT_MODE_1000BASE_T:
1923 pdata->phy.supported |= SUPPORTED_Autoneg;
1924 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
1925 pdata->phy.supported |= SUPPORTED_TP;
1926 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) {
1927 pdata->phy.supported |= SUPPORTED_100baseT_Full;
1928 phy_data->start_mode = AXGBE_MODE_SGMII_100;
1930 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) {
1931 pdata->phy.supported |= SUPPORTED_1000baseT_Full;
1932 phy_data->start_mode = AXGBE_MODE_SGMII_1000;
1935 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL22;
1938 /* MDIO Base-X support */
1939 case AXGBE_PORT_MODE_1000BASE_X:
1940 pdata->phy.supported |= SUPPORTED_Autoneg;
1941 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
1942 pdata->phy.supported |= SUPPORTED_FIBRE;
1943 pdata->phy.supported |= SUPPORTED_1000baseT_Full;
1944 phy_data->start_mode = AXGBE_MODE_X;
1946 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL22;
1949 /* MDIO NBase-T support */
1950 case AXGBE_PORT_MODE_NBASE_T:
1951 pdata->phy.supported |= SUPPORTED_Autoneg;
1952 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
1953 pdata->phy.supported |= SUPPORTED_TP;
1954 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) {
1955 pdata->phy.supported |= SUPPORTED_100baseT_Full;
1956 phy_data->start_mode = AXGBE_MODE_SGMII_100;
1958 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) {
1959 pdata->phy.supported |= SUPPORTED_1000baseT_Full;
1960 phy_data->start_mode = AXGBE_MODE_SGMII_1000;
1962 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_2500) {
1963 pdata->phy.supported |= SUPPORTED_2500baseX_Full;
1964 phy_data->start_mode = AXGBE_MODE_KX_2500;
1967 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL45;
1970 /* 10GBase-T support */
1971 case AXGBE_PORT_MODE_10GBASE_T:
1972 pdata->phy.supported |= SUPPORTED_Autoneg;
1973 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
1974 pdata->phy.supported |= SUPPORTED_TP;
1975 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) {
1976 pdata->phy.supported |= SUPPORTED_100baseT_Full;
1977 phy_data->start_mode = AXGBE_MODE_SGMII_100;
1979 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) {
1980 pdata->phy.supported |= SUPPORTED_1000baseT_Full;
1981 phy_data->start_mode = AXGBE_MODE_SGMII_1000;
1983 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) {
1984 pdata->phy.supported |= SUPPORTED_10000baseT_Full;
1985 phy_data->start_mode = AXGBE_MODE_KR;
1988 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE;
1991 /* 10GBase-R support */
1992 case AXGBE_PORT_MODE_10GBASE_R:
1993 pdata->phy.supported |= SUPPORTED_Autoneg;
1994 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
1995 pdata->phy.supported |= SUPPORTED_TP;
1996 pdata->phy.supported |= SUPPORTED_10000baseT_Full;
1997 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
1998 pdata->phy.supported |= SUPPORTED_10000baseR_FEC;
1999 phy_data->start_mode = AXGBE_MODE_SFI;
2001 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE;
2005 case AXGBE_PORT_MODE_SFP:
2006 pdata->phy.supported |= SUPPORTED_Autoneg;
2007 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2008 pdata->phy.supported |= SUPPORTED_TP;
2009 pdata->phy.supported |= SUPPORTED_FIBRE;
2010 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) {
2011 pdata->phy.supported |= SUPPORTED_100baseT_Full;
2012 phy_data->start_mode = AXGBE_MODE_SGMII_100;
2014 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) {
2015 pdata->phy.supported |= SUPPORTED_1000baseT_Full;
2016 phy_data->start_mode = AXGBE_MODE_SGMII_1000;
2018 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) {
2019 pdata->phy.supported |= SUPPORTED_10000baseT_Full;
2020 phy_data->start_mode = AXGBE_MODE_SFI;
2021 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
2022 pdata->phy.supported |=
2023 SUPPORTED_10000baseR_FEC;
2026 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL22;
2028 axgbe_phy_sfp_setup(pdata);
2034 if ((phy_data->conn_type & AXGBE_CONN_TYPE_MDIO) &&
2035 (phy_data->phydev_mode != AXGBE_MDIO_MODE_NONE)) {
2036 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr,
2037 phy_data->phydev_mode);
2039 PMD_DRV_LOG(ERR, "mdio port/clause not compatible (%d/%u)\n",
2040 phy_data->mdio_addr, phy_data->phydev_mode);
2045 if (phy_data->redrv && !phy_data->redrv_if) {
2046 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr,
2047 AXGBE_MDIO_MODE_CL22);
2049 PMD_DRV_LOG(ERR, "redriver mdio port not compatible (%u)\n",
2050 phy_data->redrv_addr);
2056 void axgbe_init_function_ptrs_phy_v2(struct axgbe_phy_if *phy_if)
2058 struct axgbe_phy_impl_if *phy_impl = &phy_if->phy_impl;
2060 phy_impl->init = axgbe_phy_init;
2061 phy_impl->reset = axgbe_phy_reset;
2062 phy_impl->start = axgbe_phy_start;
2063 phy_impl->stop = axgbe_phy_stop;
2064 phy_impl->link_status = axgbe_phy_link_status;
2065 phy_impl->use_mode = axgbe_phy_use_mode;
2066 phy_impl->set_mode = axgbe_phy_set_mode;
2067 phy_impl->get_mode = axgbe_phy_get_mode;
2068 phy_impl->switch_mode = axgbe_phy_switch_mode;
2069 phy_impl->cur_mode = axgbe_phy_cur_mode;
2070 phy_impl->an_mode = axgbe_phy_an_mode;
2071 phy_impl->an_config = axgbe_phy_an_config;
2072 phy_impl->an_advertising = axgbe_phy_an_advertising;
2073 phy_impl->an_outcome = axgbe_phy_an_outcome;