1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved.
3 * Copyright(c) 2018 Synopsys, Inc. All rights reserved.
6 #include "axgbe_ethdev.h"
7 #include "axgbe_common.h"
10 #define AXGBE_PHY_PORT_SPEED_100 BIT(0)
11 #define AXGBE_PHY_PORT_SPEED_1000 BIT(1)
12 #define AXGBE_PHY_PORT_SPEED_2500 BIT(2)
13 #define AXGBE_PHY_PORT_SPEED_10000 BIT(3)
15 #define AXGBE_MUTEX_RELEASE 0x80000000
17 #define AXGBE_SFP_DIRECT 7
19 /* I2C target addresses */
20 #define AXGBE_SFP_SERIAL_ID_ADDRESS 0x50
21 #define AXGBE_SFP_DIAG_INFO_ADDRESS 0x51
22 #define AXGBE_SFP_PHY_ADDRESS 0x56
23 #define AXGBE_GPIO_ADDRESS_PCA9555 0x20
25 /* SFP sideband signal indicators */
26 #define AXGBE_GPIO_NO_TX_FAULT BIT(0)
27 #define AXGBE_GPIO_NO_RATE_SELECT BIT(1)
28 #define AXGBE_GPIO_NO_MOD_ABSENT BIT(2)
29 #define AXGBE_GPIO_NO_RX_LOS BIT(3)
31 /* Rate-change complete wait/retry count */
32 #define AXGBE_RATECHANGE_COUNT 500
34 /* CDR delay values for KR support (in usec) */
35 #define AXGBE_CDR_DELAY_INIT 10000
36 #define AXGBE_CDR_DELAY_INC 10000
37 #define AXGBE_CDR_DELAY_MAX 100000
39 enum axgbe_port_mode {
40 AXGBE_PORT_MODE_RSVD = 0,
41 AXGBE_PORT_MODE_BACKPLANE,
42 AXGBE_PORT_MODE_BACKPLANE_2500,
43 AXGBE_PORT_MODE_1000BASE_T,
44 AXGBE_PORT_MODE_1000BASE_X,
45 AXGBE_PORT_MODE_NBASE_T,
46 AXGBE_PORT_MODE_10GBASE_T,
47 AXGBE_PORT_MODE_10GBASE_R,
52 enum axgbe_conn_type {
53 AXGBE_CONN_TYPE_NONE = 0,
56 AXGBE_CONN_TYPE_RSVD1,
57 AXGBE_CONN_TYPE_BACKPLANE,
61 /* SFP/SFP+ related definitions */
63 AXGBE_SFP_COMM_DIRECT = 0,
64 AXGBE_SFP_COMM_PCA9545,
67 enum axgbe_sfp_cable {
68 AXGBE_SFP_CABLE_UNKNOWN = 0,
69 AXGBE_SFP_CABLE_ACTIVE,
70 AXGBE_SFP_CABLE_PASSIVE,
74 AXGBE_SFP_BASE_UNKNOWN = 0,
75 AXGBE_SFP_BASE_1000_T,
76 AXGBE_SFP_BASE_1000_SX,
77 AXGBE_SFP_BASE_1000_LX,
78 AXGBE_SFP_BASE_1000_CX,
79 AXGBE_SFP_BASE_10000_SR,
80 AXGBE_SFP_BASE_10000_LR,
81 AXGBE_SFP_BASE_10000_LRM,
82 AXGBE_SFP_BASE_10000_ER,
83 AXGBE_SFP_BASE_10000_CR,
86 enum axgbe_sfp_speed {
87 AXGBE_SFP_SPEED_UNKNOWN = 0,
88 AXGBE_SFP_SPEED_100_1000,
90 AXGBE_SFP_SPEED_10000,
93 /* SFP Serial ID Base ID values relative to an offset of 0 */
94 #define AXGBE_SFP_BASE_ID 0
95 #define AXGBE_SFP_ID_SFP 0x03
97 #define AXGBE_SFP_BASE_EXT_ID 1
98 #define AXGBE_SFP_EXT_ID_SFP 0x04
100 #define AXGBE_SFP_BASE_10GBE_CC 3
101 #define AXGBE_SFP_BASE_10GBE_CC_SR BIT(4)
102 #define AXGBE_SFP_BASE_10GBE_CC_LR BIT(5)
103 #define AXGBE_SFP_BASE_10GBE_CC_LRM BIT(6)
104 #define AXGBE_SFP_BASE_10GBE_CC_ER BIT(7)
106 #define AXGBE_SFP_BASE_1GBE_CC 6
107 #define AXGBE_SFP_BASE_1GBE_CC_SX BIT(0)
108 #define AXGBE_SFP_BASE_1GBE_CC_LX BIT(1)
109 #define AXGBE_SFP_BASE_1GBE_CC_CX BIT(2)
110 #define AXGBE_SFP_BASE_1GBE_CC_T BIT(3)
112 #define AXGBE_SFP_BASE_CABLE 8
113 #define AXGBE_SFP_BASE_CABLE_PASSIVE BIT(2)
114 #define AXGBE_SFP_BASE_CABLE_ACTIVE BIT(3)
116 #define AXGBE_SFP_BASE_BR 12
117 #define AXGBE_SFP_BASE_BR_1GBE_MIN 0x0a
118 #define AXGBE_SFP_BASE_BR_1GBE_MAX 0x0d
119 #define AXGBE_SFP_BASE_BR_10GBE_MIN 0x64
120 #define AXGBE_SFP_BASE_BR_10GBE_MAX 0x68
122 #define AXGBE_SFP_BASE_CU_CABLE_LEN 18
124 #define AXGBE_SFP_BASE_VENDOR_NAME 20
125 #define AXGBE_SFP_BASE_VENDOR_NAME_LEN 16
126 #define AXGBE_SFP_BASE_VENDOR_PN 40
127 #define AXGBE_SFP_BASE_VENDOR_PN_LEN 16
128 #define AXGBE_SFP_BASE_VENDOR_REV 56
129 #define AXGBE_SFP_BASE_VENDOR_REV_LEN 4
131 #define AXGBE_SFP_BASE_CC 63
133 /* SFP Serial ID Extended ID values relative to an offset of 64 */
134 #define AXGBE_SFP_BASE_VENDOR_SN 4
135 #define AXGBE_SFP_BASE_VENDOR_SN_LEN 16
137 #define AXGBE_SFP_EXTD_DIAG 28
138 #define AXGBE_SFP_EXTD_DIAG_ADDR_CHANGE BIT(2)
140 #define AXGBE_SFP_EXTD_SFF_8472 30
142 #define AXGBE_SFP_EXTD_CC 31
144 struct axgbe_sfp_eeprom {
150 #define AXGBE_BEL_FUSE_VENDOR "BEL-FUSE"
151 #define AXGBE_BEL_FUSE_PARTNO "1GBT-SFP06"
153 struct axgbe_sfp_ascii {
155 char vendor[AXGBE_SFP_BASE_VENDOR_NAME_LEN + 1];
156 char partno[AXGBE_SFP_BASE_VENDOR_PN_LEN + 1];
157 char rev[AXGBE_SFP_BASE_VENDOR_REV_LEN + 1];
158 char serno[AXGBE_SFP_BASE_VENDOR_SN_LEN + 1];
162 /* MDIO PHY reset types */
163 enum axgbe_mdio_reset {
164 AXGBE_MDIO_RESET_NONE = 0,
165 AXGBE_MDIO_RESET_I2C_GPIO,
166 AXGBE_MDIO_RESET_INT_GPIO,
167 AXGBE_MDIO_RESET_MAX,
170 /* Re-driver related definitions */
171 enum axgbe_phy_redrv_if {
172 AXGBE_PHY_REDRV_IF_MDIO = 0,
173 AXGBE_PHY_REDRV_IF_I2C,
174 AXGBE_PHY_REDRV_IF_MAX,
177 enum axgbe_phy_redrv_model {
178 AXGBE_PHY_REDRV_MODEL_4223 = 0,
179 AXGBE_PHY_REDRV_MODEL_4227,
180 AXGBE_PHY_REDRV_MODEL_MAX,
183 enum axgbe_phy_redrv_mode {
184 AXGBE_PHY_REDRV_MODE_CX = 5,
185 AXGBE_PHY_REDRV_MODE_SR = 9,
188 #define AXGBE_PHY_REDRV_MODE_REG 0x12b0
190 /* PHY related configuration information */
191 struct axgbe_phy_data {
192 enum axgbe_port_mode port_mode;
194 unsigned int port_id;
196 unsigned int port_speeds;
198 enum axgbe_conn_type conn_type;
200 enum axgbe_mode cur_mode;
201 enum axgbe_mode start_mode;
203 unsigned int rrc_count;
205 unsigned int mdio_addr;
207 unsigned int comm_owned;
210 enum axgbe_sfp_comm sfp_comm;
211 unsigned int sfp_mux_address;
212 unsigned int sfp_mux_channel;
214 unsigned int sfp_gpio_address;
215 unsigned int sfp_gpio_mask;
216 unsigned int sfp_gpio_rx_los;
217 unsigned int sfp_gpio_tx_fault;
218 unsigned int sfp_gpio_mod_absent;
219 unsigned int sfp_gpio_rate_select;
221 unsigned int sfp_rx_los;
222 unsigned int sfp_tx_fault;
223 unsigned int sfp_mod_absent;
224 unsigned int sfp_diags;
225 unsigned int sfp_changed;
226 unsigned int sfp_phy_avail;
227 unsigned int sfp_cable_len;
228 enum axgbe_sfp_base sfp_base;
229 enum axgbe_sfp_cable sfp_cable;
230 enum axgbe_sfp_speed sfp_speed;
231 struct axgbe_sfp_eeprom sfp_eeprom;
233 /* External PHY support */
234 enum axgbe_mdio_mode phydev_mode;
235 enum axgbe_mdio_reset mdio_reset;
236 unsigned int mdio_reset_addr;
237 unsigned int mdio_reset_gpio;
239 /* Re-driver support */
241 unsigned int redrv_if;
242 unsigned int redrv_addr;
243 unsigned int redrv_lane;
244 unsigned int redrv_model;
247 unsigned int phy_cdr_notrack;
248 unsigned int phy_cdr_delay;
251 static enum axgbe_an_mode axgbe_phy_an_mode(struct axgbe_port *pdata);
253 static int axgbe_phy_i2c_xfer(struct axgbe_port *pdata,
254 struct axgbe_i2c_op *i2c_op)
256 struct axgbe_phy_data *phy_data = pdata->phy_data;
258 /* Be sure we own the bus */
259 if (!phy_data->comm_owned)
262 return pdata->i2c_if.i2c_xfer(pdata, i2c_op);
265 static int axgbe_phy_redrv_write(struct axgbe_port *pdata, unsigned int reg,
268 struct axgbe_phy_data *phy_data = pdata->phy_data;
269 struct axgbe_i2c_op i2c_op;
271 u8 redrv_data[5], csum;
272 unsigned int i, retry;
275 /* High byte of register contains read/write indicator */
276 redrv_data[0] = ((reg >> 8) & 0xff) << 1;
277 redrv_data[1] = reg & 0xff;
278 redrv_val = (uint16_t *)&redrv_data[2];
279 *redrv_val = rte_cpu_to_be_16(val);
281 /* Calculate 1 byte checksum */
283 for (i = 0; i < 4; i++) {
284 csum += redrv_data[i];
285 if (redrv_data[i] > csum)
288 redrv_data[4] = ~csum;
292 i2c_op.cmd = AXGBE_I2C_CMD_WRITE;
293 i2c_op.target = phy_data->redrv_addr;
294 i2c_op.len = sizeof(redrv_data);
295 i2c_op.buf = redrv_data;
296 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op);
298 if ((ret == -EAGAIN) && retry--)
306 i2c_op.cmd = AXGBE_I2C_CMD_READ;
307 i2c_op.target = phy_data->redrv_addr;
309 i2c_op.buf = redrv_data;
310 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op);
312 if ((ret == -EAGAIN) && retry--)
318 if (redrv_data[0] != 0xff) {
319 PMD_DRV_LOG(ERR, "Redriver write checksum error\n");
326 static int axgbe_phy_i2c_read(struct axgbe_port *pdata, unsigned int target,
327 void *reg, unsigned int reg_len,
328 void *val, unsigned int val_len)
330 struct axgbe_i2c_op i2c_op;
335 /* Set the specified register to read */
336 i2c_op.cmd = AXGBE_I2C_CMD_WRITE;
337 i2c_op.target = target;
338 i2c_op.len = reg_len;
340 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op);
342 if ((ret == -EAGAIN) && retry--)
350 /* Read the specified register */
351 i2c_op.cmd = AXGBE_I2C_CMD_READ;
352 i2c_op.target = target;
353 i2c_op.len = val_len;
355 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op);
356 if ((ret == -EAGAIN) && retry--)
362 static int axgbe_phy_sfp_put_mux(struct axgbe_port *pdata)
364 struct axgbe_phy_data *phy_data = pdata->phy_data;
365 struct axgbe_i2c_op i2c_op;
368 if (phy_data->sfp_comm == AXGBE_SFP_COMM_DIRECT)
371 /* Select no mux channels */
373 i2c_op.cmd = AXGBE_I2C_CMD_WRITE;
374 i2c_op.target = phy_data->sfp_mux_address;
375 i2c_op.len = sizeof(mux_channel);
376 i2c_op.buf = &mux_channel;
378 return axgbe_phy_i2c_xfer(pdata, &i2c_op);
381 static int axgbe_phy_sfp_get_mux(struct axgbe_port *pdata)
383 struct axgbe_phy_data *phy_data = pdata->phy_data;
384 struct axgbe_i2c_op i2c_op;
387 if (phy_data->sfp_comm == AXGBE_SFP_COMM_DIRECT)
390 /* Select desired mux channel */
391 mux_channel = 1 << phy_data->sfp_mux_channel;
392 i2c_op.cmd = AXGBE_I2C_CMD_WRITE;
393 i2c_op.target = phy_data->sfp_mux_address;
394 i2c_op.len = sizeof(mux_channel);
395 i2c_op.buf = &mux_channel;
397 return axgbe_phy_i2c_xfer(pdata, &i2c_op);
400 static void axgbe_phy_put_comm_ownership(struct axgbe_port *pdata)
402 struct axgbe_phy_data *phy_data = pdata->phy_data;
404 phy_data->comm_owned = 0;
406 pthread_mutex_unlock(&pdata->phy_mutex);
409 static int axgbe_phy_get_comm_ownership(struct axgbe_port *pdata)
411 struct axgbe_phy_data *phy_data = pdata->phy_data;
413 unsigned int mutex_id;
415 /* The I2C and MDIO/GPIO bus is multiplexed between multiple devices,
416 * the driver needs to take the software mutex and then the hardware
417 * mutexes before being able to use the busses.
419 pthread_mutex_lock(&pdata->phy_mutex);
421 if (phy_data->comm_owned)
424 /* Clear the mutexes */
425 XP_IOWRITE(pdata, XP_I2C_MUTEX, AXGBE_MUTEX_RELEASE);
426 XP_IOWRITE(pdata, XP_MDIO_MUTEX, AXGBE_MUTEX_RELEASE);
428 /* Mutex formats are the same for I2C and MDIO/GPIO */
430 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ID, phy_data->port_id);
431 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ACTIVE, 1);
433 timeout = rte_get_timer_cycles() + (rte_get_timer_hz() * 5);
434 while (time_before(rte_get_timer_cycles(), timeout)) {
435 /* Must be all zeroes in order to obtain the mutex */
436 if (XP_IOREAD(pdata, XP_I2C_MUTEX) ||
437 XP_IOREAD(pdata, XP_MDIO_MUTEX)) {
442 /* Obtain the mutex */
443 XP_IOWRITE(pdata, XP_I2C_MUTEX, mutex_id);
444 XP_IOWRITE(pdata, XP_MDIO_MUTEX, mutex_id);
446 phy_data->comm_owned = 1;
450 pthread_mutex_unlock(&pdata->phy_mutex);
452 PMD_DRV_LOG(ERR, "unable to obtain hardware mutexes\n");
457 static void axgbe_phy_sfp_phy_settings(struct axgbe_port *pdata)
459 struct axgbe_phy_data *phy_data = pdata->phy_data;
461 if (phy_data->sfp_mod_absent) {
462 pdata->phy.speed = SPEED_UNKNOWN;
463 pdata->phy.duplex = DUPLEX_UNKNOWN;
464 pdata->phy.autoneg = AUTONEG_ENABLE;
465 pdata->phy.advertising = pdata->phy.supported;
468 pdata->phy.advertising &= ~ADVERTISED_Autoneg;
469 pdata->phy.advertising &= ~ADVERTISED_TP;
470 pdata->phy.advertising &= ~ADVERTISED_FIBRE;
471 pdata->phy.advertising &= ~ADVERTISED_100baseT_Full;
472 pdata->phy.advertising &= ~ADVERTISED_1000baseT_Full;
473 pdata->phy.advertising &= ~ADVERTISED_10000baseT_Full;
474 pdata->phy.advertising &= ~ADVERTISED_10000baseR_FEC;
476 switch (phy_data->sfp_base) {
477 case AXGBE_SFP_BASE_1000_T:
478 case AXGBE_SFP_BASE_1000_SX:
479 case AXGBE_SFP_BASE_1000_LX:
480 case AXGBE_SFP_BASE_1000_CX:
481 pdata->phy.speed = SPEED_UNKNOWN;
482 pdata->phy.duplex = DUPLEX_UNKNOWN;
483 pdata->phy.autoneg = AUTONEG_ENABLE;
484 pdata->phy.advertising |= ADVERTISED_Autoneg;
486 case AXGBE_SFP_BASE_10000_SR:
487 case AXGBE_SFP_BASE_10000_LR:
488 case AXGBE_SFP_BASE_10000_LRM:
489 case AXGBE_SFP_BASE_10000_ER:
490 case AXGBE_SFP_BASE_10000_CR:
492 pdata->phy.speed = SPEED_10000;
493 pdata->phy.duplex = DUPLEX_FULL;
494 pdata->phy.autoneg = AUTONEG_DISABLE;
498 switch (phy_data->sfp_base) {
499 case AXGBE_SFP_BASE_1000_T:
500 case AXGBE_SFP_BASE_1000_CX:
501 case AXGBE_SFP_BASE_10000_CR:
502 pdata->phy.advertising |= ADVERTISED_TP;
505 pdata->phy.advertising |= ADVERTISED_FIBRE;
508 switch (phy_data->sfp_speed) {
509 case AXGBE_SFP_SPEED_100_1000:
510 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100)
511 pdata->phy.advertising |= ADVERTISED_100baseT_Full;
512 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000)
513 pdata->phy.advertising |= ADVERTISED_1000baseT_Full;
515 case AXGBE_SFP_SPEED_1000:
516 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000)
517 pdata->phy.advertising |= ADVERTISED_1000baseT_Full;
519 case AXGBE_SFP_SPEED_10000:
520 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000)
521 pdata->phy.advertising |= ADVERTISED_10000baseT_Full;
524 /* Choose the fastest supported speed */
525 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000)
526 pdata->phy.advertising |= ADVERTISED_10000baseT_Full;
527 else if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000)
528 pdata->phy.advertising |= ADVERTISED_1000baseT_Full;
529 else if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100)
530 pdata->phy.advertising |= ADVERTISED_100baseT_Full;
534 static bool axgbe_phy_sfp_bit_rate(struct axgbe_sfp_eeprom *sfp_eeprom,
535 enum axgbe_sfp_speed sfp_speed)
537 u8 *sfp_base, min, max;
539 sfp_base = sfp_eeprom->base;
542 case AXGBE_SFP_SPEED_1000:
543 min = AXGBE_SFP_BASE_BR_1GBE_MIN;
544 max = AXGBE_SFP_BASE_BR_1GBE_MAX;
546 case AXGBE_SFP_SPEED_10000:
547 min = AXGBE_SFP_BASE_BR_10GBE_MIN;
548 max = AXGBE_SFP_BASE_BR_10GBE_MAX;
554 return ((sfp_base[AXGBE_SFP_BASE_BR] >= min) &&
555 (sfp_base[AXGBE_SFP_BASE_BR] <= max));
558 static void axgbe_phy_sfp_external_phy(struct axgbe_port *pdata)
560 struct axgbe_phy_data *phy_data = pdata->phy_data;
562 if (!phy_data->sfp_changed)
565 phy_data->sfp_phy_avail = 0;
567 if (phy_data->sfp_base != AXGBE_SFP_BASE_1000_T)
571 static bool axgbe_phy_belfuse_parse_quirks(struct axgbe_port *pdata)
573 struct axgbe_phy_data *phy_data = pdata->phy_data;
574 struct axgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
576 if (memcmp(&sfp_eeprom->base[AXGBE_SFP_BASE_VENDOR_NAME],
577 AXGBE_BEL_FUSE_VENDOR, strlen(AXGBE_BEL_FUSE_VENDOR)))
580 if (!memcmp(&sfp_eeprom->base[AXGBE_SFP_BASE_VENDOR_PN],
581 AXGBE_BEL_FUSE_PARTNO, strlen(AXGBE_BEL_FUSE_PARTNO))) {
582 phy_data->sfp_base = AXGBE_SFP_BASE_1000_SX;
583 phy_data->sfp_cable = AXGBE_SFP_CABLE_ACTIVE;
584 phy_data->sfp_speed = AXGBE_SFP_SPEED_1000;
591 static bool axgbe_phy_sfp_parse_quirks(struct axgbe_port *pdata)
593 if (axgbe_phy_belfuse_parse_quirks(pdata))
599 static void axgbe_phy_sfp_parse_eeprom(struct axgbe_port *pdata)
601 struct axgbe_phy_data *phy_data = pdata->phy_data;
602 struct axgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
605 sfp_base = sfp_eeprom->base;
607 if (sfp_base[AXGBE_SFP_BASE_ID] != AXGBE_SFP_ID_SFP)
610 if (sfp_base[AXGBE_SFP_BASE_EXT_ID] != AXGBE_SFP_EXT_ID_SFP)
613 axgbe_phy_sfp_parse_quirks(pdata);
615 /* Assume ACTIVE cable unless told it is PASSIVE */
616 if (sfp_base[AXGBE_SFP_BASE_CABLE] & AXGBE_SFP_BASE_CABLE_PASSIVE) {
617 phy_data->sfp_cable = AXGBE_SFP_CABLE_PASSIVE;
618 phy_data->sfp_cable_len = sfp_base[AXGBE_SFP_BASE_CU_CABLE_LEN];
620 phy_data->sfp_cable = AXGBE_SFP_CABLE_ACTIVE;
623 /* Determine the type of SFP */
624 if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] & AXGBE_SFP_BASE_10GBE_CC_SR)
625 phy_data->sfp_base = AXGBE_SFP_BASE_10000_SR;
626 else if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] & AXGBE_SFP_BASE_10GBE_CC_LR)
627 phy_data->sfp_base = AXGBE_SFP_BASE_10000_LR;
628 else if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] &
629 AXGBE_SFP_BASE_10GBE_CC_LRM)
630 phy_data->sfp_base = AXGBE_SFP_BASE_10000_LRM;
631 else if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] & AXGBE_SFP_BASE_10GBE_CC_ER)
632 phy_data->sfp_base = AXGBE_SFP_BASE_10000_ER;
633 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_SX)
634 phy_data->sfp_base = AXGBE_SFP_BASE_1000_SX;
635 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_LX)
636 phy_data->sfp_base = AXGBE_SFP_BASE_1000_LX;
637 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_CX)
638 phy_data->sfp_base = AXGBE_SFP_BASE_1000_CX;
639 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_T)
640 phy_data->sfp_base = AXGBE_SFP_BASE_1000_T;
641 else if ((phy_data->sfp_cable == AXGBE_SFP_CABLE_PASSIVE) &&
642 axgbe_phy_sfp_bit_rate(sfp_eeprom, AXGBE_SFP_SPEED_10000))
643 phy_data->sfp_base = AXGBE_SFP_BASE_10000_CR;
645 switch (phy_data->sfp_base) {
646 case AXGBE_SFP_BASE_1000_T:
647 phy_data->sfp_speed = AXGBE_SFP_SPEED_100_1000;
649 case AXGBE_SFP_BASE_1000_SX:
650 case AXGBE_SFP_BASE_1000_LX:
651 case AXGBE_SFP_BASE_1000_CX:
652 phy_data->sfp_speed = AXGBE_SFP_SPEED_1000;
654 case AXGBE_SFP_BASE_10000_SR:
655 case AXGBE_SFP_BASE_10000_LR:
656 case AXGBE_SFP_BASE_10000_LRM:
657 case AXGBE_SFP_BASE_10000_ER:
658 case AXGBE_SFP_BASE_10000_CR:
659 phy_data->sfp_speed = AXGBE_SFP_SPEED_10000;
666 static bool axgbe_phy_sfp_verify_eeprom(uint8_t cc_in, uint8_t *buf,
671 for (cc = 0; len; buf++, len--)
674 return (cc == cc_in) ? true : false;
677 static int axgbe_phy_sfp_read_eeprom(struct axgbe_port *pdata)
679 struct axgbe_phy_data *phy_data = pdata->phy_data;
680 struct axgbe_sfp_eeprom sfp_eeprom;
684 ret = axgbe_phy_sfp_get_mux(pdata);
686 PMD_DRV_LOG(ERR, "I2C error setting SFP MUX\n");
690 /* Read the SFP serial ID eeprom */
692 ret = axgbe_phy_i2c_read(pdata, AXGBE_SFP_SERIAL_ID_ADDRESS,
693 &eeprom_addr, sizeof(eeprom_addr),
694 &sfp_eeprom, sizeof(sfp_eeprom));
696 PMD_DRV_LOG(ERR, "I2C error reading SFP EEPROM\n");
700 /* Validate the contents read */
701 if (!axgbe_phy_sfp_verify_eeprom(sfp_eeprom.base[AXGBE_SFP_BASE_CC],
703 sizeof(sfp_eeprom.base) - 1)) {
708 if (!axgbe_phy_sfp_verify_eeprom(sfp_eeprom.extd[AXGBE_SFP_EXTD_CC],
710 sizeof(sfp_eeprom.extd) - 1)) {
715 /* Check for an added or changed SFP */
716 if (memcmp(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom))) {
717 phy_data->sfp_changed = 1;
718 memcpy(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom));
720 if (sfp_eeprom.extd[AXGBE_SFP_EXTD_SFF_8472]) {
722 diag_type = sfp_eeprom.extd[AXGBE_SFP_EXTD_DIAG];
724 if (!(diag_type & AXGBE_SFP_EXTD_DIAG_ADDR_CHANGE))
725 phy_data->sfp_diags = 1;
728 phy_data->sfp_changed = 0;
732 axgbe_phy_sfp_put_mux(pdata);
737 static void axgbe_phy_sfp_signals(struct axgbe_port *pdata)
739 struct axgbe_phy_data *phy_data = pdata->phy_data;
740 unsigned int gpio_input;
741 u8 gpio_reg, gpio_ports[2];
744 /* Read the input port registers */
746 ret = axgbe_phy_i2c_read(pdata, phy_data->sfp_gpio_address,
747 &gpio_reg, sizeof(gpio_reg),
748 gpio_ports, sizeof(gpio_ports));
750 PMD_DRV_LOG(ERR, "I2C error reading SFP GPIOs\n");
754 gpio_input = (gpio_ports[1] << 8) | gpio_ports[0];
756 if (phy_data->sfp_gpio_mask & AXGBE_GPIO_NO_MOD_ABSENT) {
757 /* No GPIO, just assume the module is present for now */
758 phy_data->sfp_mod_absent = 0;
760 if (!(gpio_input & (1 << phy_data->sfp_gpio_mod_absent)))
761 phy_data->sfp_mod_absent = 0;
764 if (!(phy_data->sfp_gpio_mask & AXGBE_GPIO_NO_RX_LOS) &&
765 (gpio_input & (1 << phy_data->sfp_gpio_rx_los)))
766 phy_data->sfp_rx_los = 1;
768 if (!(phy_data->sfp_gpio_mask & AXGBE_GPIO_NO_TX_FAULT) &&
769 (gpio_input & (1 << phy_data->sfp_gpio_tx_fault)))
770 phy_data->sfp_tx_fault = 1;
773 static void axgbe_phy_sfp_mod_absent(struct axgbe_port *pdata)
775 struct axgbe_phy_data *phy_data = pdata->phy_data;
777 phy_data->sfp_mod_absent = 1;
778 phy_data->sfp_phy_avail = 0;
779 memset(&phy_data->sfp_eeprom, 0, sizeof(phy_data->sfp_eeprom));
782 static void axgbe_phy_sfp_reset(struct axgbe_phy_data *phy_data)
784 phy_data->sfp_rx_los = 0;
785 phy_data->sfp_tx_fault = 0;
786 phy_data->sfp_mod_absent = 1;
787 phy_data->sfp_diags = 0;
788 phy_data->sfp_base = AXGBE_SFP_BASE_UNKNOWN;
789 phy_data->sfp_cable = AXGBE_SFP_CABLE_UNKNOWN;
790 phy_data->sfp_speed = AXGBE_SFP_SPEED_UNKNOWN;
793 static const char *axgbe_base_as_string(enum axgbe_sfp_base sfp_base)
796 case AXGBE_SFP_BASE_1000_T:
798 case AXGBE_SFP_BASE_1000_SX:
800 case AXGBE_SFP_BASE_1000_LX:
802 case AXGBE_SFP_BASE_1000_CX:
804 case AXGBE_SFP_BASE_10000_SR:
806 case AXGBE_SFP_BASE_10000_LR:
808 case AXGBE_SFP_BASE_10000_LRM:
810 case AXGBE_SFP_BASE_10000_ER:
812 case AXGBE_SFP_BASE_10000_CR:
819 static void axgbe_phy_sfp_detect(struct axgbe_port *pdata)
821 struct axgbe_phy_data *phy_data = pdata->phy_data;
824 /* Reset the SFP signals and info */
825 axgbe_phy_sfp_reset(phy_data);
827 ret = axgbe_phy_get_comm_ownership(pdata);
831 /* Read the SFP signals and check for module presence */
832 axgbe_phy_sfp_signals(pdata);
833 if (phy_data->sfp_mod_absent) {
834 axgbe_phy_sfp_mod_absent(pdata);
838 ret = axgbe_phy_sfp_read_eeprom(pdata);
840 /* Treat any error as if there isn't an SFP plugged in */
841 axgbe_phy_sfp_reset(phy_data);
842 axgbe_phy_sfp_mod_absent(pdata);
846 axgbe_phy_sfp_parse_eeprom(pdata);
847 axgbe_phy_sfp_external_phy(pdata);
849 PMD_DRV_LOG(DEBUG, "SFP Base: %s\n",
850 axgbe_base_as_string(phy_data->sfp_base));
853 axgbe_phy_sfp_phy_settings(pdata);
854 axgbe_phy_put_comm_ownership(pdata);
857 static void axgbe_phy_phydev_flowctrl(struct axgbe_port *pdata)
859 pdata->phy.tx_pause = 0;
860 pdata->phy.rx_pause = 0;
863 static enum axgbe_mode axgbe_phy_an73_redrv_outcome(struct axgbe_port *pdata)
865 struct axgbe_phy_data *phy_data = pdata->phy_data;
866 enum axgbe_mode mode;
867 unsigned int ad_reg, lp_reg;
869 pdata->phy.lp_advertising |= ADVERTISED_Autoneg;
870 pdata->phy.lp_advertising |= ADVERTISED_Backplane;
872 /* Use external PHY to determine flow control */
873 if (pdata->phy.pause_autoneg)
874 axgbe_phy_phydev_flowctrl(pdata);
876 /* Compare Advertisement and Link Partner register 2 */
877 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
878 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
880 pdata->phy.lp_advertising |= ADVERTISED_10000baseKR_Full;
882 pdata->phy.lp_advertising |= ADVERTISED_1000baseKX_Full;
886 switch (phy_data->port_mode) {
887 case AXGBE_PORT_MODE_BACKPLANE:
888 mode = AXGBE_MODE_KR;
891 mode = AXGBE_MODE_SFI;
894 } else if (ad_reg & 0x20) {
895 switch (phy_data->port_mode) {
896 case AXGBE_PORT_MODE_BACKPLANE:
897 mode = AXGBE_MODE_KX_1000;
899 case AXGBE_PORT_MODE_1000BASE_X:
902 case AXGBE_PORT_MODE_SFP:
903 switch (phy_data->sfp_base) {
904 case AXGBE_SFP_BASE_1000_T:
905 mode = AXGBE_MODE_SGMII_1000;
907 case AXGBE_SFP_BASE_1000_SX:
908 case AXGBE_SFP_BASE_1000_LX:
909 case AXGBE_SFP_BASE_1000_CX:
916 mode = AXGBE_MODE_SGMII_1000;
920 mode = AXGBE_MODE_UNKNOWN;
923 /* Compare Advertisement and Link Partner register 3 */
924 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
925 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
927 pdata->phy.lp_advertising |= ADVERTISED_10000baseR_FEC;
932 static enum axgbe_mode axgbe_phy_an73_outcome(struct axgbe_port *pdata)
934 enum axgbe_mode mode;
935 unsigned int ad_reg, lp_reg;
937 pdata->phy.lp_advertising |= ADVERTISED_Autoneg;
938 pdata->phy.lp_advertising |= ADVERTISED_Backplane;
940 /* Compare Advertisement and Link Partner register 1 */
941 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
942 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA);
944 pdata->phy.lp_advertising |= ADVERTISED_Pause;
946 pdata->phy.lp_advertising |= ADVERTISED_Asym_Pause;
948 if (pdata->phy.pause_autoneg) {
949 /* Set flow control based on auto-negotiation result */
950 pdata->phy.tx_pause = 0;
951 pdata->phy.rx_pause = 0;
953 if (ad_reg & lp_reg & 0x400) {
954 pdata->phy.tx_pause = 1;
955 pdata->phy.rx_pause = 1;
956 } else if (ad_reg & lp_reg & 0x800) {
958 pdata->phy.rx_pause = 1;
959 else if (lp_reg & 0x400)
960 pdata->phy.tx_pause = 1;
964 /* Compare Advertisement and Link Partner register 2 */
965 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
966 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
968 pdata->phy.lp_advertising |= ADVERTISED_10000baseKR_Full;
970 pdata->phy.lp_advertising |= ADVERTISED_1000baseKX_Full;
974 mode = AXGBE_MODE_KR;
975 else if (ad_reg & 0x20)
976 mode = AXGBE_MODE_KX_1000;
978 mode = AXGBE_MODE_UNKNOWN;
980 /* Compare Advertisement and Link Partner register 3 */
981 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
982 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
984 pdata->phy.lp_advertising |= ADVERTISED_10000baseR_FEC;
989 static enum axgbe_mode axgbe_phy_an37_sgmii_outcome(struct axgbe_port *pdata)
991 enum axgbe_mode mode;
993 pdata->phy.lp_advertising |= ADVERTISED_Autoneg;
994 pdata->phy.lp_advertising |= ADVERTISED_1000baseT_Full;
996 if (pdata->phy.pause_autoneg)
997 axgbe_phy_phydev_flowctrl(pdata);
999 switch (pdata->an_status & AXGBE_SGMII_AN_LINK_SPEED) {
1000 case AXGBE_SGMII_AN_LINK_SPEED_100:
1001 if (pdata->an_status & AXGBE_SGMII_AN_LINK_DUPLEX) {
1002 pdata->phy.lp_advertising |= ADVERTISED_100baseT_Full;
1003 mode = AXGBE_MODE_SGMII_100;
1005 mode = AXGBE_MODE_UNKNOWN;
1008 case AXGBE_SGMII_AN_LINK_SPEED_1000:
1009 if (pdata->an_status & AXGBE_SGMII_AN_LINK_DUPLEX) {
1010 pdata->phy.lp_advertising |= ADVERTISED_1000baseT_Full;
1011 mode = AXGBE_MODE_SGMII_1000;
1013 /* Half-duplex not supported */
1014 mode = AXGBE_MODE_UNKNOWN;
1018 mode = AXGBE_MODE_UNKNOWN;
1024 static enum axgbe_mode axgbe_phy_an_outcome(struct axgbe_port *pdata)
1026 switch (pdata->an_mode) {
1027 case AXGBE_AN_MODE_CL73:
1028 return axgbe_phy_an73_outcome(pdata);
1029 case AXGBE_AN_MODE_CL73_REDRV:
1030 return axgbe_phy_an73_redrv_outcome(pdata);
1031 case AXGBE_AN_MODE_CL37:
1032 case AXGBE_AN_MODE_CL37_SGMII:
1033 return axgbe_phy_an37_sgmii_outcome(pdata);
1035 return AXGBE_MODE_UNKNOWN;
1039 static unsigned int axgbe_phy_an_advertising(struct axgbe_port *pdata)
1041 struct axgbe_phy_data *phy_data = pdata->phy_data;
1042 unsigned int advertising;
1044 /* Without a re-driver, just return current advertising */
1045 if (!phy_data->redrv)
1046 return pdata->phy.advertising;
1048 /* With the KR re-driver we need to advertise a single speed */
1049 advertising = pdata->phy.advertising;
1050 advertising &= ~ADVERTISED_1000baseKX_Full;
1051 advertising &= ~ADVERTISED_10000baseKR_Full;
1053 switch (phy_data->port_mode) {
1054 case AXGBE_PORT_MODE_BACKPLANE:
1055 advertising |= ADVERTISED_10000baseKR_Full;
1057 case AXGBE_PORT_MODE_BACKPLANE_2500:
1058 advertising |= ADVERTISED_1000baseKX_Full;
1060 case AXGBE_PORT_MODE_1000BASE_T:
1061 case AXGBE_PORT_MODE_1000BASE_X:
1062 case AXGBE_PORT_MODE_NBASE_T:
1063 advertising |= ADVERTISED_1000baseKX_Full;
1065 case AXGBE_PORT_MODE_10GBASE_T:
1066 PMD_DRV_LOG(ERR, "10GBASE_T mode is not supported\n");
1068 case AXGBE_PORT_MODE_10GBASE_R:
1069 advertising |= ADVERTISED_10000baseKR_Full;
1071 case AXGBE_PORT_MODE_SFP:
1072 switch (phy_data->sfp_base) {
1073 case AXGBE_SFP_BASE_1000_T:
1074 case AXGBE_SFP_BASE_1000_SX:
1075 case AXGBE_SFP_BASE_1000_LX:
1076 case AXGBE_SFP_BASE_1000_CX:
1077 advertising |= ADVERTISED_1000baseKX_Full;
1080 advertising |= ADVERTISED_10000baseKR_Full;
1085 advertising |= ADVERTISED_10000baseKR_Full;
1092 static int axgbe_phy_an_config(struct axgbe_port *pdata __rte_unused)
1095 /* Dummy API since there is no case to support
1096 * external phy devices registered through kernel APIs
1100 static enum axgbe_an_mode axgbe_phy_an_sfp_mode(struct axgbe_phy_data *phy_data)
1102 switch (phy_data->sfp_base) {
1103 case AXGBE_SFP_BASE_1000_T:
1104 return AXGBE_AN_MODE_CL37_SGMII;
1105 case AXGBE_SFP_BASE_1000_SX:
1106 case AXGBE_SFP_BASE_1000_LX:
1107 case AXGBE_SFP_BASE_1000_CX:
1108 return AXGBE_AN_MODE_CL37;
1110 return AXGBE_AN_MODE_NONE;
1114 static enum axgbe_an_mode axgbe_phy_an_mode(struct axgbe_port *pdata)
1116 struct axgbe_phy_data *phy_data = pdata->phy_data;
1118 /* A KR re-driver will always require CL73 AN */
1119 if (phy_data->redrv)
1120 return AXGBE_AN_MODE_CL73_REDRV;
1122 switch (phy_data->port_mode) {
1123 case AXGBE_PORT_MODE_BACKPLANE:
1124 return AXGBE_AN_MODE_CL73;
1125 case AXGBE_PORT_MODE_BACKPLANE_2500:
1126 return AXGBE_AN_MODE_NONE;
1127 case AXGBE_PORT_MODE_1000BASE_T:
1128 return AXGBE_AN_MODE_CL37_SGMII;
1129 case AXGBE_PORT_MODE_1000BASE_X:
1130 return AXGBE_AN_MODE_CL37;
1131 case AXGBE_PORT_MODE_NBASE_T:
1132 return AXGBE_AN_MODE_CL37_SGMII;
1133 case AXGBE_PORT_MODE_10GBASE_T:
1134 return AXGBE_AN_MODE_CL73;
1135 case AXGBE_PORT_MODE_10GBASE_R:
1136 return AXGBE_AN_MODE_NONE;
1137 case AXGBE_PORT_MODE_SFP:
1138 return axgbe_phy_an_sfp_mode(phy_data);
1140 return AXGBE_AN_MODE_NONE;
1144 static int axgbe_phy_set_redrv_mode_mdio(struct axgbe_port *pdata,
1145 enum axgbe_phy_redrv_mode mode)
1147 struct axgbe_phy_data *phy_data = pdata->phy_data;
1148 u16 redrv_reg, redrv_val;
1150 redrv_reg = AXGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
1151 redrv_val = (u16)mode;
1153 return pdata->hw_if.write_ext_mii_regs(pdata, phy_data->redrv_addr,
1154 redrv_reg, redrv_val);
1157 static int axgbe_phy_set_redrv_mode_i2c(struct axgbe_port *pdata,
1158 enum axgbe_phy_redrv_mode mode)
1160 struct axgbe_phy_data *phy_data = pdata->phy_data;
1161 unsigned int redrv_reg;
1164 /* Calculate the register to write */
1165 redrv_reg = AXGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
1167 ret = axgbe_phy_redrv_write(pdata, redrv_reg, mode);
1172 static void axgbe_phy_set_redrv_mode(struct axgbe_port *pdata)
1174 struct axgbe_phy_data *phy_data = pdata->phy_data;
1175 enum axgbe_phy_redrv_mode mode;
1178 if (!phy_data->redrv)
1181 mode = AXGBE_PHY_REDRV_MODE_CX;
1182 if ((phy_data->port_mode == AXGBE_PORT_MODE_SFP) &&
1183 (phy_data->sfp_base != AXGBE_SFP_BASE_1000_CX) &&
1184 (phy_data->sfp_base != AXGBE_SFP_BASE_10000_CR))
1185 mode = AXGBE_PHY_REDRV_MODE_SR;
1187 ret = axgbe_phy_get_comm_ownership(pdata);
1191 if (phy_data->redrv_if)
1192 axgbe_phy_set_redrv_mode_i2c(pdata, mode);
1194 axgbe_phy_set_redrv_mode_mdio(pdata, mode);
1196 axgbe_phy_put_comm_ownership(pdata);
1199 static void axgbe_phy_rx_reset(struct axgbe_port *pdata)
1203 reg = XMDIO_READ_BITS(pdata, MDIO_MMD_PCS, MDIO_PCS_DIGITAL_STAT,
1204 XGBE_PCS_PSEQ_STATE_MASK);
1205 if (reg == XGBE_PCS_PSEQ_STATE_POWER_GOOD) {
1206 /* Mailbox command timed out, reset of RX block is required.
1207 * This can be done by asseting the reset bit and wait for
1210 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1,
1211 XGBE_PMA_RX_RST_0_MASK, XGBE_PMA_RX_RST_0_RESET_ON);
1213 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1,
1214 XGBE_PMA_RX_RST_0_MASK, XGBE_PMA_RX_RST_0_RESET_OFF);
1216 PMD_DRV_LOG(ERR, "firmware mailbox reset performed\n");
1221 static void axgbe_phy_pll_ctrl(struct axgbe_port *pdata, bool enable)
1223 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_MISC_CTRL0,
1224 XGBE_PMA_PLL_CTRL_MASK,
1225 enable ? XGBE_PMA_PLL_CTRL_SET
1226 : XGBE_PMA_PLL_CTRL_CLEAR);
1228 /* Wait for command to complete */
1232 static void axgbe_phy_perform_ratechange(struct axgbe_port *pdata,
1233 unsigned int cmd, unsigned int sub_cmd)
1235 unsigned int s0 = 0;
1237 /* Clear the PLL so that it helps in power down sequence */
1238 axgbe_phy_pll_ctrl(pdata, false);
1240 /* Log if a previous command did not complete */
1241 if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) {
1242 PMD_DRV_LOG(NOTICE, "firmware mailbox not ready for command\n");
1243 axgbe_phy_rx_reset(pdata);
1246 /* Construct the command */
1247 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, cmd);
1248 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, sub_cmd);
1250 /* Issue the command */
1251 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
1252 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
1253 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
1255 /* Wait for command to complete */
1256 wait = AXGBE_RATECHANGE_COUNT;
1258 if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
1262 PMD_DRV_LOG(NOTICE, "firmware mailbox command did not complete\n");
1263 /* Reset on error */
1264 axgbe_phy_rx_reset(pdata);
1267 /* Re-enable the PLL control */
1268 axgbe_phy_pll_ctrl(pdata, true);
1270 PMD_DRV_LOG(NOTICE, "firmware mailbox command did not complete\n");
1273 static void axgbe_phy_rrc(struct axgbe_port *pdata)
1277 /* Receiver Reset Cycle */
1278 axgbe_phy_perform_ratechange(pdata, 5, 0);
1280 PMD_DRV_LOG(DEBUG, "receiver reset complete\n");
1283 static void axgbe_phy_power_off(struct axgbe_port *pdata)
1285 struct axgbe_phy_data *phy_data = pdata->phy_data;
1288 axgbe_phy_perform_ratechange(pdata, 0, 0);
1290 phy_data->cur_mode = AXGBE_MODE_UNKNOWN;
1292 PMD_DRV_LOG(DEBUG, "phy powered off\n");
1295 static void axgbe_phy_sfi_mode(struct axgbe_port *pdata)
1297 struct axgbe_phy_data *phy_data = pdata->phy_data;
1299 axgbe_phy_set_redrv_mode(pdata);
1302 if (phy_data->sfp_cable != AXGBE_SFP_CABLE_PASSIVE) {
1303 axgbe_phy_perform_ratechange(pdata, 3, 0);
1305 if (phy_data->sfp_cable_len <= 1)
1306 axgbe_phy_perform_ratechange(pdata, 3, 1);
1307 else if (phy_data->sfp_cable_len <= 3)
1308 axgbe_phy_perform_ratechange(pdata, 3, 2);
1310 axgbe_phy_perform_ratechange(pdata, 3, 3);
1313 phy_data->cur_mode = AXGBE_MODE_SFI;
1315 PMD_DRV_LOG(DEBUG, "10GbE SFI mode set\n");
1318 static void axgbe_phy_kr_mode(struct axgbe_port *pdata)
1320 struct axgbe_phy_data *phy_data = pdata->phy_data;
1322 axgbe_phy_set_redrv_mode(pdata);
1325 axgbe_phy_perform_ratechange(pdata, 4, 0);
1326 phy_data->cur_mode = AXGBE_MODE_KR;
1328 PMD_DRV_LOG(DEBUG, "10GbE KR mode set\n");
1331 static void axgbe_phy_kx_2500_mode(struct axgbe_port *pdata)
1333 struct axgbe_phy_data *phy_data = pdata->phy_data;
1335 axgbe_phy_set_redrv_mode(pdata);
1338 axgbe_phy_perform_ratechange(pdata, 2, 0);
1339 phy_data->cur_mode = AXGBE_MODE_KX_2500;
1342 static void axgbe_phy_sgmii_1000_mode(struct axgbe_port *pdata)
1344 struct axgbe_phy_data *phy_data = pdata->phy_data;
1346 axgbe_phy_set_redrv_mode(pdata);
1349 axgbe_phy_perform_ratechange(pdata, 1, 2);
1351 phy_data->cur_mode = AXGBE_MODE_SGMII_1000;
1354 static enum axgbe_mode axgbe_phy_cur_mode(struct axgbe_port *pdata)
1356 struct axgbe_phy_data *phy_data = pdata->phy_data;
1358 return phy_data->cur_mode;
1361 static enum axgbe_mode axgbe_phy_switch_baset_mode(struct axgbe_port *pdata)
1363 struct axgbe_phy_data *phy_data = pdata->phy_data;
1365 /* No switching if not 10GBase-T */
1366 if (phy_data->port_mode != AXGBE_PORT_MODE_10GBASE_T)
1367 return axgbe_phy_cur_mode(pdata);
1369 switch (axgbe_phy_cur_mode(pdata)) {
1370 case AXGBE_MODE_SGMII_100:
1371 case AXGBE_MODE_SGMII_1000:
1372 return AXGBE_MODE_KR;
1375 return AXGBE_MODE_SGMII_1000;
1379 static enum axgbe_mode axgbe_phy_switch_bp_2500_mode(struct axgbe_port *pdata
1382 return AXGBE_MODE_KX_2500;
1385 static enum axgbe_mode axgbe_phy_switch_bp_mode(struct axgbe_port *pdata)
1387 /* If we are in KR switch to KX, and vice-versa */
1388 switch (axgbe_phy_cur_mode(pdata)) {
1389 case AXGBE_MODE_KX_1000:
1390 return AXGBE_MODE_KR;
1393 return AXGBE_MODE_KX_1000;
1397 static enum axgbe_mode axgbe_phy_switch_mode(struct axgbe_port *pdata)
1399 struct axgbe_phy_data *phy_data = pdata->phy_data;
1401 switch (phy_data->port_mode) {
1402 case AXGBE_PORT_MODE_BACKPLANE:
1403 return axgbe_phy_switch_bp_mode(pdata);
1404 case AXGBE_PORT_MODE_BACKPLANE_2500:
1405 return axgbe_phy_switch_bp_2500_mode(pdata);
1406 case AXGBE_PORT_MODE_1000BASE_T:
1407 case AXGBE_PORT_MODE_NBASE_T:
1408 case AXGBE_PORT_MODE_10GBASE_T:
1409 return axgbe_phy_switch_baset_mode(pdata);
1410 case AXGBE_PORT_MODE_1000BASE_X:
1411 case AXGBE_PORT_MODE_10GBASE_R:
1412 case AXGBE_PORT_MODE_SFP:
1413 /* No switching, so just return current mode */
1414 return axgbe_phy_cur_mode(pdata);
1416 return AXGBE_MODE_UNKNOWN;
1420 static enum axgbe_mode axgbe_phy_get_basex_mode(struct axgbe_phy_data *phy_data
1426 return AXGBE_MODE_X;
1428 return AXGBE_MODE_KR;
1430 return AXGBE_MODE_UNKNOWN;
1434 static enum axgbe_mode axgbe_phy_get_baset_mode(struct axgbe_phy_data *phy_data
1440 return AXGBE_MODE_SGMII_100;
1442 return AXGBE_MODE_SGMII_1000;
1444 return AXGBE_MODE_KR;
1446 return AXGBE_MODE_UNKNOWN;
1450 static enum axgbe_mode axgbe_phy_get_sfp_mode(struct axgbe_phy_data *phy_data,
1455 return AXGBE_MODE_SGMII_100;
1457 if (phy_data->sfp_base == AXGBE_SFP_BASE_1000_T)
1458 return AXGBE_MODE_SGMII_1000;
1460 return AXGBE_MODE_X;
1463 return AXGBE_MODE_SFI;
1465 return AXGBE_MODE_UNKNOWN;
1469 static enum axgbe_mode axgbe_phy_get_bp_2500_mode(int speed)
1473 return AXGBE_MODE_KX_2500;
1475 return AXGBE_MODE_UNKNOWN;
1479 static enum axgbe_mode axgbe_phy_get_bp_mode(int speed)
1483 return AXGBE_MODE_KX_1000;
1485 return AXGBE_MODE_KR;
1487 return AXGBE_MODE_UNKNOWN;
1491 static enum axgbe_mode axgbe_phy_get_mode(struct axgbe_port *pdata,
1494 struct axgbe_phy_data *phy_data = pdata->phy_data;
1496 switch (phy_data->port_mode) {
1497 case AXGBE_PORT_MODE_BACKPLANE:
1498 return axgbe_phy_get_bp_mode(speed);
1499 case AXGBE_PORT_MODE_BACKPLANE_2500:
1500 return axgbe_phy_get_bp_2500_mode(speed);
1501 case AXGBE_PORT_MODE_1000BASE_T:
1502 case AXGBE_PORT_MODE_NBASE_T:
1503 case AXGBE_PORT_MODE_10GBASE_T:
1504 return axgbe_phy_get_baset_mode(phy_data, speed);
1505 case AXGBE_PORT_MODE_1000BASE_X:
1506 case AXGBE_PORT_MODE_10GBASE_R:
1507 return axgbe_phy_get_basex_mode(phy_data, speed);
1508 case AXGBE_PORT_MODE_SFP:
1509 return axgbe_phy_get_sfp_mode(phy_data, speed);
1511 return AXGBE_MODE_UNKNOWN;
1515 static void axgbe_phy_set_mode(struct axgbe_port *pdata, enum axgbe_mode mode)
1519 axgbe_phy_kr_mode(pdata);
1521 case AXGBE_MODE_SFI:
1522 axgbe_phy_sfi_mode(pdata);
1524 case AXGBE_MODE_KX_2500:
1525 axgbe_phy_kx_2500_mode(pdata);
1527 case AXGBE_MODE_SGMII_1000:
1528 axgbe_phy_sgmii_1000_mode(pdata);
1535 static bool axgbe_phy_check_mode(struct axgbe_port *pdata,
1536 enum axgbe_mode mode, u32 advert)
1538 if (pdata->phy.autoneg == AUTONEG_ENABLE) {
1539 if (pdata->phy.advertising & advert)
1542 enum axgbe_mode cur_mode;
1544 cur_mode = axgbe_phy_get_mode(pdata, pdata->phy.speed);
1545 if (cur_mode == mode)
1552 static bool axgbe_phy_use_basex_mode(struct axgbe_port *pdata,
1553 enum axgbe_mode mode)
1557 return axgbe_phy_check_mode(pdata, mode,
1558 ADVERTISED_1000baseT_Full);
1560 return axgbe_phy_check_mode(pdata, mode,
1561 ADVERTISED_10000baseT_Full);
1567 static bool axgbe_phy_use_baset_mode(struct axgbe_port *pdata,
1568 enum axgbe_mode mode)
1571 case AXGBE_MODE_SGMII_100:
1572 return axgbe_phy_check_mode(pdata, mode,
1573 ADVERTISED_100baseT_Full);
1574 case AXGBE_MODE_SGMII_1000:
1575 return axgbe_phy_check_mode(pdata, mode,
1576 ADVERTISED_1000baseT_Full);
1578 return axgbe_phy_check_mode(pdata, mode,
1579 ADVERTISED_10000baseT_Full);
1585 static bool axgbe_phy_use_sfp_mode(struct axgbe_port *pdata,
1586 enum axgbe_mode mode)
1588 struct axgbe_phy_data *phy_data = pdata->phy_data;
1592 if (phy_data->sfp_base == AXGBE_SFP_BASE_1000_T)
1594 return axgbe_phy_check_mode(pdata, mode,
1595 ADVERTISED_1000baseT_Full);
1596 case AXGBE_MODE_SGMII_100:
1597 if (phy_data->sfp_base != AXGBE_SFP_BASE_1000_T)
1599 return axgbe_phy_check_mode(pdata, mode,
1600 ADVERTISED_100baseT_Full);
1601 case AXGBE_MODE_SGMII_1000:
1602 if (phy_data->sfp_base != AXGBE_SFP_BASE_1000_T)
1604 return axgbe_phy_check_mode(pdata, mode,
1605 ADVERTISED_1000baseT_Full);
1606 case AXGBE_MODE_SFI:
1607 return axgbe_phy_check_mode(pdata, mode,
1608 ADVERTISED_10000baseT_Full);
1614 static bool axgbe_phy_use_bp_2500_mode(struct axgbe_port *pdata,
1615 enum axgbe_mode mode)
1618 case AXGBE_MODE_KX_2500:
1619 return axgbe_phy_check_mode(pdata, mode,
1620 ADVERTISED_2500baseX_Full);
1626 static bool axgbe_phy_use_bp_mode(struct axgbe_port *pdata,
1627 enum axgbe_mode mode)
1630 case AXGBE_MODE_KX_1000:
1631 return axgbe_phy_check_mode(pdata, mode,
1632 ADVERTISED_1000baseKX_Full);
1634 return axgbe_phy_check_mode(pdata, mode,
1635 ADVERTISED_10000baseKR_Full);
1641 static bool axgbe_phy_use_mode(struct axgbe_port *pdata, enum axgbe_mode mode)
1643 struct axgbe_phy_data *phy_data = pdata->phy_data;
1645 switch (phy_data->port_mode) {
1646 case AXGBE_PORT_MODE_BACKPLANE:
1647 return axgbe_phy_use_bp_mode(pdata, mode);
1648 case AXGBE_PORT_MODE_BACKPLANE_2500:
1649 return axgbe_phy_use_bp_2500_mode(pdata, mode);
1650 case AXGBE_PORT_MODE_1000BASE_T:
1651 case AXGBE_PORT_MODE_NBASE_T:
1652 case AXGBE_PORT_MODE_10GBASE_T:
1653 return axgbe_phy_use_baset_mode(pdata, mode);
1654 case AXGBE_PORT_MODE_1000BASE_X:
1655 case AXGBE_PORT_MODE_10GBASE_R:
1656 return axgbe_phy_use_basex_mode(pdata, mode);
1657 case AXGBE_PORT_MODE_SFP:
1658 return axgbe_phy_use_sfp_mode(pdata, mode);
1664 static int axgbe_phy_link_status(struct axgbe_port *pdata, int *an_restart)
1666 struct axgbe_phy_data *phy_data = pdata->phy_data;
1671 if (phy_data->port_mode == AXGBE_PORT_MODE_SFP) {
1672 /* Check SFP signals */
1673 axgbe_phy_sfp_detect(pdata);
1675 if (phy_data->sfp_changed) {
1680 if (phy_data->sfp_mod_absent || phy_data->sfp_rx_los)
1684 /* Link status is latched low, so read once to clear
1685 * and then read again to get current state
1687 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
1688 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
1689 if (reg & MDIO_STAT1_LSTATUS)
1692 /* No link, attempt a receiver reset cycle */
1693 if (phy_data->rrc_count++) {
1694 phy_data->rrc_count = 0;
1695 axgbe_phy_rrc(pdata);
1701 static void axgbe_phy_sfp_gpio_setup(struct axgbe_port *pdata)
1703 struct axgbe_phy_data *phy_data = pdata->phy_data;
1706 reg = XP_IOREAD(pdata, XP_PROP_3);
1708 phy_data->sfp_gpio_address = AXGBE_GPIO_ADDRESS_PCA9555 +
1709 XP_GET_BITS(reg, XP_PROP_3, GPIO_ADDR);
1711 phy_data->sfp_gpio_mask = XP_GET_BITS(reg, XP_PROP_3, GPIO_MASK);
1713 phy_data->sfp_gpio_rx_los = XP_GET_BITS(reg, XP_PROP_3,
1715 phy_data->sfp_gpio_tx_fault = XP_GET_BITS(reg, XP_PROP_3,
1717 phy_data->sfp_gpio_mod_absent = XP_GET_BITS(reg, XP_PROP_3,
1719 phy_data->sfp_gpio_rate_select = XP_GET_BITS(reg, XP_PROP_3,
1723 static void axgbe_phy_sfp_comm_setup(struct axgbe_port *pdata)
1725 struct axgbe_phy_data *phy_data = pdata->phy_data;
1726 unsigned int reg, mux_addr_hi, mux_addr_lo;
1728 reg = XP_IOREAD(pdata, XP_PROP_4);
1730 mux_addr_hi = XP_GET_BITS(reg, XP_PROP_4, MUX_ADDR_HI);
1731 mux_addr_lo = XP_GET_BITS(reg, XP_PROP_4, MUX_ADDR_LO);
1732 if (mux_addr_lo == AXGBE_SFP_DIRECT)
1735 phy_data->sfp_comm = AXGBE_SFP_COMM_PCA9545;
1736 phy_data->sfp_mux_address = (mux_addr_hi << 2) + mux_addr_lo;
1737 phy_data->sfp_mux_channel = XP_GET_BITS(reg, XP_PROP_4, MUX_CHAN);
1740 static void axgbe_phy_sfp_setup(struct axgbe_port *pdata)
1742 axgbe_phy_sfp_comm_setup(pdata);
1743 axgbe_phy_sfp_gpio_setup(pdata);
1746 static bool axgbe_phy_redrv_error(struct axgbe_phy_data *phy_data)
1748 if (!phy_data->redrv)
1751 if (phy_data->redrv_if >= AXGBE_PHY_REDRV_IF_MAX)
1754 switch (phy_data->redrv_model) {
1755 case AXGBE_PHY_REDRV_MODEL_4223:
1756 if (phy_data->redrv_lane > 3)
1759 case AXGBE_PHY_REDRV_MODEL_4227:
1760 if (phy_data->redrv_lane > 1)
1770 static int axgbe_phy_mdio_reset_setup(struct axgbe_port *pdata)
1772 struct axgbe_phy_data *phy_data = pdata->phy_data;
1775 if (phy_data->conn_type != AXGBE_CONN_TYPE_MDIO)
1777 reg = XP_IOREAD(pdata, XP_PROP_3);
1778 phy_data->mdio_reset = XP_GET_BITS(reg, XP_PROP_3, MDIO_RESET);
1779 switch (phy_data->mdio_reset) {
1780 case AXGBE_MDIO_RESET_NONE:
1781 case AXGBE_MDIO_RESET_I2C_GPIO:
1782 case AXGBE_MDIO_RESET_INT_GPIO:
1785 PMD_DRV_LOG(ERR, "unsupported MDIO reset (%#x)\n",
1786 phy_data->mdio_reset);
1789 if (phy_data->mdio_reset == AXGBE_MDIO_RESET_I2C_GPIO) {
1790 phy_data->mdio_reset_addr = AXGBE_GPIO_ADDRESS_PCA9555 +
1791 XP_GET_BITS(reg, XP_PROP_3,
1792 MDIO_RESET_I2C_ADDR);
1793 phy_data->mdio_reset_gpio = XP_GET_BITS(reg, XP_PROP_3,
1794 MDIO_RESET_I2C_GPIO);
1795 } else if (phy_data->mdio_reset == AXGBE_MDIO_RESET_INT_GPIO) {
1796 phy_data->mdio_reset_gpio = XP_GET_BITS(reg, XP_PROP_3,
1797 MDIO_RESET_INT_GPIO);
1803 static bool axgbe_phy_port_mode_mismatch(struct axgbe_port *pdata)
1805 struct axgbe_phy_data *phy_data = pdata->phy_data;
1807 switch (phy_data->port_mode) {
1808 case AXGBE_PORT_MODE_BACKPLANE:
1809 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) ||
1810 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000))
1813 case AXGBE_PORT_MODE_BACKPLANE_2500:
1814 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_2500)
1817 case AXGBE_PORT_MODE_1000BASE_T:
1818 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) ||
1819 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000))
1822 case AXGBE_PORT_MODE_1000BASE_X:
1823 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000)
1826 case AXGBE_PORT_MODE_NBASE_T:
1827 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) ||
1828 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) ||
1829 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_2500))
1832 case AXGBE_PORT_MODE_10GBASE_T:
1833 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) ||
1834 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) ||
1835 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000))
1838 case AXGBE_PORT_MODE_10GBASE_R:
1839 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000)
1842 case AXGBE_PORT_MODE_SFP:
1843 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) ||
1844 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) ||
1845 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000))
1855 static bool axgbe_phy_conn_type_mismatch(struct axgbe_port *pdata)
1857 struct axgbe_phy_data *phy_data = pdata->phy_data;
1859 switch (phy_data->port_mode) {
1860 case AXGBE_PORT_MODE_BACKPLANE:
1861 case AXGBE_PORT_MODE_BACKPLANE_2500:
1862 if (phy_data->conn_type == AXGBE_CONN_TYPE_BACKPLANE)
1865 case AXGBE_PORT_MODE_1000BASE_T:
1866 case AXGBE_PORT_MODE_1000BASE_X:
1867 case AXGBE_PORT_MODE_NBASE_T:
1868 case AXGBE_PORT_MODE_10GBASE_T:
1869 case AXGBE_PORT_MODE_10GBASE_R:
1870 if (phy_data->conn_type == AXGBE_CONN_TYPE_MDIO)
1873 case AXGBE_PORT_MODE_SFP:
1874 if (phy_data->conn_type == AXGBE_CONN_TYPE_SFP)
1884 static bool axgbe_phy_port_enabled(struct axgbe_port *pdata)
1888 reg = XP_IOREAD(pdata, XP_PROP_0);
1889 if (!XP_GET_BITS(reg, XP_PROP_0, PORT_SPEEDS))
1891 if (!XP_GET_BITS(reg, XP_PROP_0, CONN_TYPE))
1897 static void axgbe_phy_cdr_track(struct axgbe_port *pdata)
1899 struct axgbe_phy_data *phy_data = pdata->phy_data;
1901 if (!pdata->vdata->an_cdr_workaround)
1904 if (!phy_data->phy_cdr_notrack)
1907 rte_delay_us(phy_data->phy_cdr_delay + 400);
1909 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL,
1910 AXGBE_PMA_CDR_TRACK_EN_MASK,
1911 AXGBE_PMA_CDR_TRACK_EN_ON);
1913 phy_data->phy_cdr_notrack = 0;
1916 static void axgbe_phy_cdr_notrack(struct axgbe_port *pdata)
1918 struct axgbe_phy_data *phy_data = pdata->phy_data;
1920 if (!pdata->vdata->an_cdr_workaround)
1923 if (phy_data->phy_cdr_notrack)
1926 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL,
1927 AXGBE_PMA_CDR_TRACK_EN_MASK,
1928 AXGBE_PMA_CDR_TRACK_EN_OFF);
1930 axgbe_phy_rrc(pdata);
1932 phy_data->phy_cdr_notrack = 1;
1935 static void axgbe_phy_kr_training_post(struct axgbe_port *pdata)
1937 if (!pdata->cdr_track_early)
1938 axgbe_phy_cdr_track(pdata);
1941 static void axgbe_phy_kr_training_pre(struct axgbe_port *pdata)
1943 if (pdata->cdr_track_early)
1944 axgbe_phy_cdr_track(pdata);
1947 static void axgbe_phy_an_post(struct axgbe_port *pdata)
1949 struct axgbe_phy_data *phy_data = pdata->phy_data;
1951 switch (pdata->an_mode) {
1952 case AXGBE_AN_MODE_CL73:
1953 case AXGBE_AN_MODE_CL73_REDRV:
1954 if (phy_data->cur_mode != AXGBE_MODE_KR)
1957 axgbe_phy_cdr_track(pdata);
1959 switch (pdata->an_result) {
1960 case AXGBE_AN_READY:
1961 case AXGBE_AN_COMPLETE:
1964 if (phy_data->phy_cdr_delay < AXGBE_CDR_DELAY_MAX)
1965 phy_data->phy_cdr_delay += AXGBE_CDR_DELAY_INC;
1974 static void axgbe_phy_an_pre(struct axgbe_port *pdata)
1976 struct axgbe_phy_data *phy_data = pdata->phy_data;
1978 switch (pdata->an_mode) {
1979 case AXGBE_AN_MODE_CL73:
1980 case AXGBE_AN_MODE_CL73_REDRV:
1981 if (phy_data->cur_mode != AXGBE_MODE_KR)
1984 axgbe_phy_cdr_notrack(pdata);
1991 static void axgbe_phy_stop(struct axgbe_port *pdata)
1993 struct axgbe_phy_data *phy_data = pdata->phy_data;
1995 /* Reset SFP data */
1996 axgbe_phy_sfp_reset(phy_data);
1997 axgbe_phy_sfp_mod_absent(pdata);
1999 /* Reset CDR support */
2000 axgbe_phy_cdr_track(pdata);
2002 /* Power off the PHY */
2003 axgbe_phy_power_off(pdata);
2005 /* Stop the I2C controller */
2006 pdata->i2c_if.i2c_stop(pdata);
2009 static int axgbe_phy_start(struct axgbe_port *pdata)
2011 struct axgbe_phy_data *phy_data = pdata->phy_data;
2014 /* Start the I2C controller */
2015 ret = pdata->i2c_if.i2c_start(pdata);
2019 /* Start in highest supported mode */
2020 axgbe_phy_set_mode(pdata, phy_data->start_mode);
2022 /* Reset CDR support */
2023 axgbe_phy_cdr_track(pdata);
2025 /* After starting the I2C controller, we can check for an SFP */
2026 switch (phy_data->port_mode) {
2027 case AXGBE_PORT_MODE_SFP:
2028 axgbe_phy_sfp_detect(pdata);
2033 pdata->phy.advertising &= axgbe_phy_an_advertising(pdata);
2038 static int axgbe_phy_reset(struct axgbe_port *pdata)
2040 struct axgbe_phy_data *phy_data = pdata->phy_data;
2041 enum axgbe_mode cur_mode;
2043 /* Reset by power cycling the PHY */
2044 cur_mode = phy_data->cur_mode;
2045 axgbe_phy_power_off(pdata);
2046 /* First time reset is done with passed unknown mode*/
2047 axgbe_phy_set_mode(pdata, cur_mode);
2051 static int axgbe_phy_init(struct axgbe_port *pdata)
2053 struct axgbe_phy_data *phy_data;
2057 /* Check if enabled */
2058 if (!axgbe_phy_port_enabled(pdata)) {
2059 PMD_DRV_LOG(ERR, "device is not enabled\n");
2063 /* Initialize the I2C controller */
2064 ret = pdata->i2c_if.i2c_init(pdata);
2068 phy_data = rte_zmalloc("phy_data memory", sizeof(*phy_data), 0);
2070 PMD_DRV_LOG(ERR, "phy_data allocation failed\n");
2073 pdata->phy_data = phy_data;
2075 reg = XP_IOREAD(pdata, XP_PROP_0);
2076 phy_data->port_mode = XP_GET_BITS(reg, XP_PROP_0, PORT_MODE);
2077 phy_data->port_id = XP_GET_BITS(reg, XP_PROP_0, PORT_ID);
2078 phy_data->port_speeds = XP_GET_BITS(reg, XP_PROP_0, PORT_SPEEDS);
2079 phy_data->conn_type = XP_GET_BITS(reg, XP_PROP_0, CONN_TYPE);
2080 phy_data->mdio_addr = XP_GET_BITS(reg, XP_PROP_0, MDIO_ADDR);
2082 reg = XP_IOREAD(pdata, XP_PROP_4);
2083 phy_data->redrv = XP_GET_BITS(reg, XP_PROP_4, REDRV_PRESENT);
2084 phy_data->redrv_if = XP_GET_BITS(reg, XP_PROP_4, REDRV_IF);
2085 phy_data->redrv_addr = XP_GET_BITS(reg, XP_PROP_4, REDRV_ADDR);
2086 phy_data->redrv_lane = XP_GET_BITS(reg, XP_PROP_4, REDRV_LANE);
2087 phy_data->redrv_model = XP_GET_BITS(reg, XP_PROP_4, REDRV_MODEL);
2089 /* Validate the connection requested */
2090 if (axgbe_phy_conn_type_mismatch(pdata)) {
2091 PMD_DRV_LOG(ERR, "phy mode/connection mismatch (%#x/%#x)\n",
2092 phy_data->port_mode, phy_data->conn_type);
2096 /* Validate the mode requested */
2097 if (axgbe_phy_port_mode_mismatch(pdata)) {
2098 PMD_DRV_LOG(ERR, "phy mode/speed mismatch (%#x/%#x)\n",
2099 phy_data->port_mode, phy_data->port_speeds);
2103 /* Check for and validate MDIO reset support */
2104 ret = axgbe_phy_mdio_reset_setup(pdata);
2108 /* Validate the re-driver information */
2109 if (axgbe_phy_redrv_error(phy_data)) {
2110 PMD_DRV_LOG(ERR, "phy re-driver settings error\n");
2113 pdata->kr_redrv = phy_data->redrv;
2115 /* Indicate current mode is unknown */
2116 phy_data->cur_mode = AXGBE_MODE_UNKNOWN;
2118 /* Initialize supported features */
2119 pdata->phy.supported = 0;
2121 switch (phy_data->port_mode) {
2122 /* Backplane support */
2123 case AXGBE_PORT_MODE_BACKPLANE:
2124 pdata->phy.supported |= SUPPORTED_Autoneg;
2125 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2126 pdata->phy.supported |= SUPPORTED_Backplane;
2127 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) {
2128 pdata->phy.supported |= SUPPORTED_1000baseKX_Full;
2129 phy_data->start_mode = AXGBE_MODE_KX_1000;
2131 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) {
2132 pdata->phy.supported |= SUPPORTED_10000baseKR_Full;
2133 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
2134 pdata->phy.supported |=
2135 SUPPORTED_10000baseR_FEC;
2136 phy_data->start_mode = AXGBE_MODE_KR;
2139 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE;
2141 case AXGBE_PORT_MODE_BACKPLANE_2500:
2142 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2143 pdata->phy.supported |= SUPPORTED_Backplane;
2144 pdata->phy.supported |= SUPPORTED_2500baseX_Full;
2145 phy_data->start_mode = AXGBE_MODE_KX_2500;
2147 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE;
2150 /* MDIO 1GBase-T support */
2151 case AXGBE_PORT_MODE_1000BASE_T:
2152 pdata->phy.supported |= SUPPORTED_Autoneg;
2153 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2154 pdata->phy.supported |= SUPPORTED_TP;
2155 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) {
2156 pdata->phy.supported |= SUPPORTED_100baseT_Full;
2157 phy_data->start_mode = AXGBE_MODE_SGMII_100;
2159 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) {
2160 pdata->phy.supported |= SUPPORTED_1000baseT_Full;
2161 phy_data->start_mode = AXGBE_MODE_SGMII_1000;
2164 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL22;
2167 /* MDIO Base-X support */
2168 case AXGBE_PORT_MODE_1000BASE_X:
2169 pdata->phy.supported |= SUPPORTED_Autoneg;
2170 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2171 pdata->phy.supported |= SUPPORTED_FIBRE;
2172 pdata->phy.supported |= SUPPORTED_1000baseT_Full;
2173 phy_data->start_mode = AXGBE_MODE_X;
2175 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL22;
2178 /* MDIO NBase-T support */
2179 case AXGBE_PORT_MODE_NBASE_T:
2180 pdata->phy.supported |= SUPPORTED_Autoneg;
2181 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2182 pdata->phy.supported |= SUPPORTED_TP;
2183 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) {
2184 pdata->phy.supported |= SUPPORTED_100baseT_Full;
2185 phy_data->start_mode = AXGBE_MODE_SGMII_100;
2187 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) {
2188 pdata->phy.supported |= SUPPORTED_1000baseT_Full;
2189 phy_data->start_mode = AXGBE_MODE_SGMII_1000;
2191 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_2500) {
2192 pdata->phy.supported |= SUPPORTED_2500baseX_Full;
2193 phy_data->start_mode = AXGBE_MODE_KX_2500;
2196 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL45;
2199 /* 10GBase-T support */
2200 case AXGBE_PORT_MODE_10GBASE_T:
2201 pdata->phy.supported |= SUPPORTED_Autoneg;
2202 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2203 pdata->phy.supported |= SUPPORTED_TP;
2204 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) {
2205 pdata->phy.supported |= SUPPORTED_100baseT_Full;
2206 phy_data->start_mode = AXGBE_MODE_SGMII_100;
2208 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) {
2209 pdata->phy.supported |= SUPPORTED_1000baseT_Full;
2210 phy_data->start_mode = AXGBE_MODE_SGMII_1000;
2212 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) {
2213 pdata->phy.supported |= SUPPORTED_10000baseT_Full;
2214 phy_data->start_mode = AXGBE_MODE_KR;
2217 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE;
2220 /* 10GBase-R support */
2221 case AXGBE_PORT_MODE_10GBASE_R:
2222 pdata->phy.supported |= SUPPORTED_Autoneg;
2223 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2224 pdata->phy.supported |= SUPPORTED_TP;
2225 pdata->phy.supported |= SUPPORTED_10000baseT_Full;
2226 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
2227 pdata->phy.supported |= SUPPORTED_10000baseR_FEC;
2228 phy_data->start_mode = AXGBE_MODE_SFI;
2230 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE;
2234 case AXGBE_PORT_MODE_SFP:
2235 pdata->phy.supported |= SUPPORTED_Autoneg;
2236 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2237 pdata->phy.supported |= SUPPORTED_TP;
2238 pdata->phy.supported |= SUPPORTED_FIBRE;
2239 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) {
2240 pdata->phy.supported |= SUPPORTED_100baseT_Full;
2241 phy_data->start_mode = AXGBE_MODE_SGMII_100;
2243 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) {
2244 pdata->phy.supported |= SUPPORTED_1000baseT_Full;
2245 phy_data->start_mode = AXGBE_MODE_SGMII_1000;
2247 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) {
2248 pdata->phy.supported |= SUPPORTED_10000baseT_Full;
2249 phy_data->start_mode = AXGBE_MODE_SFI;
2250 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
2251 pdata->phy.supported |=
2252 SUPPORTED_10000baseR_FEC;
2255 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL22;
2257 axgbe_phy_sfp_setup(pdata);
2263 if ((phy_data->conn_type & AXGBE_CONN_TYPE_MDIO) &&
2264 (phy_data->phydev_mode != AXGBE_MDIO_MODE_NONE)) {
2265 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr,
2266 phy_data->phydev_mode);
2268 PMD_DRV_LOG(ERR, "mdio port/clause not compatible (%d/%u)\n",
2269 phy_data->mdio_addr, phy_data->phydev_mode);
2274 if (phy_data->redrv && !phy_data->redrv_if) {
2275 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr,
2276 AXGBE_MDIO_MODE_CL22);
2278 PMD_DRV_LOG(ERR, "redriver mdio port not compatible (%u)\n",
2279 phy_data->redrv_addr);
2284 phy_data->phy_cdr_delay = AXGBE_CDR_DELAY_INIT;
2287 void axgbe_init_function_ptrs_phy_v2(struct axgbe_phy_if *phy_if)
2289 struct axgbe_phy_impl_if *phy_impl = &phy_if->phy_impl;
2291 phy_impl->init = axgbe_phy_init;
2292 phy_impl->reset = axgbe_phy_reset;
2293 phy_impl->start = axgbe_phy_start;
2294 phy_impl->stop = axgbe_phy_stop;
2295 phy_impl->link_status = axgbe_phy_link_status;
2296 phy_impl->use_mode = axgbe_phy_use_mode;
2297 phy_impl->set_mode = axgbe_phy_set_mode;
2298 phy_impl->get_mode = axgbe_phy_get_mode;
2299 phy_impl->switch_mode = axgbe_phy_switch_mode;
2300 phy_impl->cur_mode = axgbe_phy_cur_mode;
2301 phy_impl->an_mode = axgbe_phy_an_mode;
2302 phy_impl->an_config = axgbe_phy_an_config;
2303 phy_impl->an_advertising = axgbe_phy_an_advertising;
2304 phy_impl->an_outcome = axgbe_phy_an_outcome;
2306 phy_impl->an_pre = axgbe_phy_an_pre;
2307 phy_impl->an_post = axgbe_phy_an_post;
2309 phy_impl->kr_training_pre = axgbe_phy_kr_training_pre;
2310 phy_impl->kr_training_post = axgbe_phy_kr_training_post;