1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved.
3 * Copyright(c) 2018 Synopsys, Inc. All rights reserved.
6 #include "axgbe_ethdev.h"
7 #include "axgbe_rxtx.h"
11 #include <rte_mempool.h>
16 axgbe_rx_queue_release(struct axgbe_rx_queue *rx_queue)
19 struct rte_mbuf **sw_ring;
22 sw_ring = rx_queue->sw_ring;
24 for (i = 0; i < rx_queue->nb_desc; i++) {
26 rte_pktmbuf_free(sw_ring[i]);
34 void axgbe_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t queue_idx)
36 axgbe_rx_queue_release(dev->data->rx_queues[queue_idx]);
39 int axgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
40 uint16_t nb_desc, unsigned int socket_id,
41 const struct rte_eth_rxconf *rx_conf,
42 struct rte_mempool *mp)
44 PMD_INIT_FUNC_TRACE();
46 const struct rte_memzone *dma;
47 struct axgbe_rx_queue *rxq;
48 uint32_t rx_desc = nb_desc;
49 struct axgbe_port *pdata = dev->data->dev_private;
52 * validate Rx descriptors count
53 * should be power of 2 and less than h/w supported
55 if ((!rte_is_power_of_2(rx_desc)) ||
56 rx_desc > pdata->rx_desc_count)
58 /* First allocate the rx queue data structure */
59 rxq = rte_zmalloc_socket("ethdev RX queue",
60 sizeof(struct axgbe_rx_queue),
61 RTE_CACHE_LINE_SIZE, socket_id);
63 PMD_INIT_LOG(ERR, "rte_zmalloc for rxq failed!");
71 rxq->queue_id = queue_idx;
72 rxq->port_id = dev->data->port_id;
73 rxq->nb_desc = rx_desc;
74 rxq->dma_regs = (void *)((uint8_t *)pdata->xgmac_regs + DMA_CH_BASE +
75 (DMA_CH_INC * rxq->queue_id));
76 rxq->dma_tail_reg = (volatile uint32_t *)((uint8_t *)rxq->dma_regs +
78 if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC)
79 rxq->crc_len = RTE_ETHER_CRC_LEN;
83 /* CRC strip in AXGBE supports per port not per queue */
84 pdata->crc_strip_enable = (rxq->crc_len == 0) ? 1 : 0;
85 rxq->free_thresh = rx_conf->rx_free_thresh ?
86 rx_conf->rx_free_thresh : AXGBE_RX_FREE_THRESH;
87 if (rxq->free_thresh > rxq->nb_desc)
88 rxq->free_thresh = rxq->nb_desc >> 3;
90 /* Allocate RX ring hardware descriptors */
91 size = rxq->nb_desc * sizeof(union axgbe_rx_desc);
92 dma = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx, size, 128,
95 PMD_DRV_LOG(ERR, "ring_dma_zone_reserve for rx_ring failed\n");
96 axgbe_rx_queue_release(rxq);
99 rxq->ring_phys_addr = (uint64_t)dma->iova;
100 rxq->desc = (volatile union axgbe_rx_desc *)dma->addr;
101 memset((void *)rxq->desc, 0, size);
102 /* Allocate software ring */
103 size = rxq->nb_desc * sizeof(struct rte_mbuf *);
104 rxq->sw_ring = rte_zmalloc_socket("sw_ring", size,
108 PMD_DRV_LOG(ERR, "rte_zmalloc for sw_ring failed\n");
109 axgbe_rx_queue_release(rxq);
112 dev->data->rx_queues[queue_idx] = rxq;
113 if (!pdata->rx_queues)
114 pdata->rx_queues = dev->data->rx_queues;
119 static void axgbe_prepare_rx_stop(struct axgbe_port *pdata,
122 unsigned int rx_status;
123 unsigned long rx_timeout;
125 /* The Rx engine cannot be stopped if it is actively processing
126 * packets. Wait for the Rx queue to empty the Rx fifo. Don't
127 * wait forever though...
129 rx_timeout = rte_get_timer_cycles() + (AXGBE_DMA_STOP_TIMEOUT *
132 while (time_before(rte_get_timer_cycles(), rx_timeout)) {
133 rx_status = AXGMAC_MTL_IOREAD(pdata, queue, MTL_Q_RQDR);
134 if ((AXGMAC_GET_BITS(rx_status, MTL_Q_RQDR, PRXQ) == 0) &&
135 (AXGMAC_GET_BITS(rx_status, MTL_Q_RQDR, RXQSTS) == 0))
141 if (!time_before(rte_get_timer_cycles(), rx_timeout))
143 "timed out waiting for Rx queue %u to empty\n",
147 void axgbe_dev_disable_rx(struct rte_eth_dev *dev)
149 struct axgbe_rx_queue *rxq;
150 struct axgbe_port *pdata = dev->data->dev_private;
154 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 0);
155 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 0);
156 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 0);
157 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 0);
159 /* Prepare for Rx DMA channel stop */
160 for (i = 0; i < dev->data->nb_rx_queues; i++) {
161 rxq = dev->data->rx_queues[i];
162 axgbe_prepare_rx_stop(pdata, i);
164 /* Disable each Rx queue */
165 AXGMAC_IOWRITE(pdata, MAC_RQC0R, 0);
166 for (i = 0; i < dev->data->nb_rx_queues; i++) {
167 rxq = dev->data->rx_queues[i];
168 /* Disable Rx DMA channel */
169 AXGMAC_DMA_IOWRITE_BITS(rxq, DMA_CH_RCR, SR, 0);
173 void axgbe_dev_enable_rx(struct rte_eth_dev *dev)
175 struct axgbe_rx_queue *rxq;
176 struct axgbe_port *pdata = dev->data->dev_private;
178 unsigned int reg_val = 0;
180 for (i = 0; i < dev->data->nb_rx_queues; i++) {
181 rxq = dev->data->rx_queues[i];
182 /* Enable Rx DMA channel */
183 AXGMAC_DMA_IOWRITE_BITS(rxq, DMA_CH_RCR, SR, 1);
187 for (i = 0; i < pdata->rx_q_count; i++)
188 reg_val |= (0x02 << (i << 1));
189 AXGMAC_IOWRITE(pdata, MAC_RQC0R, reg_val);
192 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 1);
193 /* Frame is forwarded after stripping CRC to application*/
194 if (pdata->crc_strip_enable) {
195 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 1);
196 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 1);
198 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 1);
201 /* Rx function one to one refresh */
203 axgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
206 PMD_INIT_FUNC_TRACE();
208 struct axgbe_rx_queue *rxq = rx_queue;
209 volatile union axgbe_rx_desc *desc;
210 uint64_t old_dirty = rxq->dirty;
211 struct rte_mbuf *mbuf, *tmbuf;
212 unsigned int err, etlt;
213 uint32_t error_status;
214 uint16_t idx, pidx, pkt_len;
217 idx = AXGBE_GET_DESC_IDX(rxq, rxq->cur);
218 while (nb_rx < nb_pkts) {
219 if (unlikely(idx == rxq->nb_desc))
222 desc = &rxq->desc[idx];
224 if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, OWN))
226 tmbuf = rte_mbuf_raw_alloc(rxq->mb_pool);
227 if (unlikely(!tmbuf)) {
228 PMD_DRV_LOG(ERR, "RX mbuf alloc failed port_id = %u"
230 (unsigned int)rxq->port_id,
231 (unsigned int)rxq->queue_id);
233 rxq->port_id].data->rx_mbuf_alloc_failed++;
234 rxq->rx_mbuf_alloc_failed++;
238 if (unlikely(pidx == rxq->nb_desc))
241 rte_prefetch0(rxq->sw_ring[pidx]);
242 if ((pidx & 0x3) == 0) {
243 rte_prefetch0(&rxq->desc[pidx]);
244 rte_prefetch0(&rxq->sw_ring[pidx]);
247 mbuf = rxq->sw_ring[idx];
248 /* Check for any errors and free mbuf*/
249 err = AXGMAC_GET_BITS_LE(desc->write.desc3,
250 RX_NORMAL_DESC3, ES);
253 error_status = desc->write.desc3 & AXGBE_ERR_STATUS;
254 if ((error_status != AXGBE_L3_CSUM_ERR) &&
255 (error_status != AXGBE_L4_CSUM_ERR)) {
257 rte_pktmbuf_free(mbuf);
261 if (rxq->pdata->rx_csum_enable) {
263 mbuf->ol_flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;
264 mbuf->ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;
265 if (unlikely(error_status == AXGBE_L3_CSUM_ERR)) {
266 mbuf->ol_flags &= ~RTE_MBUF_F_RX_IP_CKSUM_GOOD;
267 mbuf->ol_flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD;
268 mbuf->ol_flags &= ~RTE_MBUF_F_RX_L4_CKSUM_GOOD;
269 mbuf->ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_UNKNOWN;
271 unlikely(error_status == AXGBE_L4_CSUM_ERR)) {
272 mbuf->ol_flags &= ~RTE_MBUF_F_RX_L4_CKSUM_GOOD;
273 mbuf->ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD;
276 rte_prefetch1(rte_pktmbuf_mtod(mbuf, void *));
277 /* Get the RSS hash */
278 if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, RSV))
279 mbuf->hash.rss = rte_le_to_cpu_32(desc->write.desc1);
280 etlt = AXGMAC_GET_BITS_LE(desc->write.desc3,
281 RX_NORMAL_DESC3, ETLT);
282 offloads = rxq->pdata->eth_dev->data->dev_conf.rxmode.offloads;
284 if (etlt == RX_CVLAN_TAG_PRESENT) {
285 mbuf->ol_flags |= RTE_MBUF_F_RX_VLAN;
287 AXGMAC_GET_BITS_LE(desc->write.desc0,
288 RX_NORMAL_DESC0, OVT);
289 if (offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP)
290 mbuf->ol_flags |= RTE_MBUF_F_RX_VLAN_STRIPPED;
292 mbuf->ol_flags &= ~RTE_MBUF_F_RX_VLAN_STRIPPED;
295 ~(RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED);
299 /* Indicate if a Context Descriptor is next */
300 if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, CDA))
301 mbuf->ol_flags |= RTE_MBUF_F_RX_IEEE1588_PTP
302 | RTE_MBUF_F_RX_IEEE1588_TMST;
303 pkt_len = AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3,
307 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
309 mbuf->port = rxq->port_id;
310 mbuf->pkt_len = pkt_len;
311 mbuf->data_len = pkt_len;
312 rxq->bytes += pkt_len;
313 rx_pkts[nb_rx++] = mbuf;
316 rxq->sw_ring[idx++] = tmbuf;
318 rte_cpu_to_le_64(rte_mbuf_data_iova_default(tmbuf));
319 memset((void *)(&desc->read.desc2), 0, 8);
320 AXGMAC_SET_BITS_LE(desc->read.desc3, RX_NORMAL_DESC3, OWN, 1);
324 if (rxq->dirty != old_dirty) {
326 idx = AXGBE_GET_DESC_IDX(rxq, rxq->dirty - 1);
327 AXGMAC_DMA_IOWRITE(rxq, DMA_CH_RDTR_LO,
328 low32_value(rxq->ring_phys_addr +
329 (idx * sizeof(union axgbe_rx_desc))));
336 uint16_t eth_axgbe_recv_scattered_pkts(void *rx_queue,
337 struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
339 PMD_INIT_FUNC_TRACE();
341 struct axgbe_rx_queue *rxq = rx_queue;
342 volatile union axgbe_rx_desc *desc;
344 uint64_t old_dirty = rxq->dirty;
345 struct rte_mbuf *first_seg = NULL;
346 struct rte_mbuf *mbuf, *tmbuf;
347 unsigned int err, etlt;
348 uint32_t error_status;
349 uint16_t idx, pidx, data_len = 0, pkt_len = 0;
352 idx = AXGBE_GET_DESC_IDX(rxq, rxq->cur);
353 while (nb_rx < nb_pkts) {
356 if (unlikely(idx == rxq->nb_desc))
359 desc = &rxq->desc[idx];
361 if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, OWN))
364 tmbuf = rte_mbuf_raw_alloc(rxq->mb_pool);
365 if (unlikely(!tmbuf)) {
366 PMD_DRV_LOG(ERR, "RX mbuf alloc failed port_id = %u"
368 (unsigned int)rxq->port_id,
369 (unsigned int)rxq->queue_id);
370 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
375 if (unlikely(pidx == rxq->nb_desc))
378 rte_prefetch0(rxq->sw_ring[pidx]);
379 if ((pidx & 0x3) == 0) {
380 rte_prefetch0(&rxq->desc[pidx]);
381 rte_prefetch0(&rxq->sw_ring[pidx]);
384 mbuf = rxq->sw_ring[idx];
385 /* Check for any errors and free mbuf*/
386 err = AXGMAC_GET_BITS_LE(desc->write.desc3,
387 RX_NORMAL_DESC3, ES);
390 error_status = desc->write.desc3 & AXGBE_ERR_STATUS;
391 if ((error_status != AXGBE_L3_CSUM_ERR)
392 && (error_status != AXGBE_L4_CSUM_ERR)) {
394 rte_pktmbuf_free(mbuf);
398 rte_prefetch1(rte_pktmbuf_mtod(mbuf, void *));
400 if (!AXGMAC_GET_BITS_LE(desc->write.desc3,
401 RX_NORMAL_DESC3, LD)) {
403 pkt_len = rxq->buf_size;
407 pkt_len = AXGMAC_GET_BITS_LE(desc->write.desc3,
408 RX_NORMAL_DESC3, PL);
409 data_len = pkt_len - rxq->crc_len;
412 if (first_seg != NULL) {
413 if (rte_pktmbuf_chain(first_seg, mbuf) != 0)
414 rte_mempool_put(rxq->mb_pool,
420 /* Get the RSS hash */
421 if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, RSV))
422 mbuf->hash.rss = rte_le_to_cpu_32(desc->write.desc1);
423 etlt = AXGMAC_GET_BITS_LE(desc->write.desc3,
424 RX_NORMAL_DESC3, ETLT);
425 offloads = rxq->pdata->eth_dev->data->dev_conf.rxmode.offloads;
427 if (etlt == RX_CVLAN_TAG_PRESENT) {
428 mbuf->ol_flags |= RTE_MBUF_F_RX_VLAN;
430 AXGMAC_GET_BITS_LE(desc->write.desc0,
431 RX_NORMAL_DESC0, OVT);
432 if (offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP)
433 mbuf->ol_flags |= RTE_MBUF_F_RX_VLAN_STRIPPED;
435 mbuf->ol_flags &= ~RTE_MBUF_F_RX_VLAN_STRIPPED;
438 ~(RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED);
443 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
444 mbuf->data_len = data_len;
448 rxq->sw_ring[idx++] = tmbuf;
450 rte_cpu_to_le_64(rte_mbuf_data_iova_default(tmbuf));
451 memset((void *)(&desc->read.desc2), 0, 8);
452 AXGMAC_SET_BITS_LE(desc->read.desc3, RX_NORMAL_DESC3, OWN, 1);
456 rte_pktmbuf_free(mbuf);
460 first_seg->pkt_len = pkt_len;
461 rxq->bytes += pkt_len;
464 first_seg->port = rxq->port_id;
465 if (rxq->pdata->rx_csum_enable) {
467 mbuf->ol_flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;
468 mbuf->ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;
469 if (unlikely(error_status == AXGBE_L3_CSUM_ERR)) {
470 mbuf->ol_flags &= ~RTE_MBUF_F_RX_IP_CKSUM_GOOD;
471 mbuf->ol_flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD;
472 mbuf->ol_flags &= ~RTE_MBUF_F_RX_L4_CKSUM_GOOD;
473 mbuf->ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_UNKNOWN;
474 } else if (unlikely(error_status
475 == AXGBE_L4_CSUM_ERR)) {
476 mbuf->ol_flags &= ~RTE_MBUF_F_RX_L4_CKSUM_GOOD;
477 mbuf->ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD;
481 rx_pkts[nb_rx++] = first_seg;
483 /* Setup receipt context for a new packet.*/
487 /* Save receive context.*/
490 if (rxq->dirty != old_dirty) {
492 idx = AXGBE_GET_DESC_IDX(rxq, rxq->dirty - 1);
493 AXGMAC_DMA_IOWRITE(rxq, DMA_CH_RDTR_LO,
494 low32_value(rxq->ring_phys_addr +
495 (idx * sizeof(union axgbe_rx_desc))));
501 static void axgbe_tx_queue_release(struct axgbe_tx_queue *tx_queue)
504 struct rte_mbuf **sw_ring;
507 sw_ring = tx_queue->sw_ring;
509 for (i = 0; i < tx_queue->nb_desc; i++) {
511 rte_pktmbuf_free(sw_ring[i]);
519 void axgbe_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t queue_idx)
521 axgbe_tx_queue_release(dev->data->tx_queues[queue_idx]);
524 int axgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
525 uint16_t nb_desc, unsigned int socket_id,
526 const struct rte_eth_txconf *tx_conf)
528 PMD_INIT_FUNC_TRACE();
530 struct axgbe_port *pdata;
531 struct axgbe_tx_queue *txq;
533 const struct rte_memzone *tz;
537 pdata = dev->data->dev_private;
540 * validate tx descriptors count
541 * should be power of 2 and less than h/w supported
543 if ((!rte_is_power_of_2(tx_desc)) ||
544 tx_desc > pdata->tx_desc_count ||
545 tx_desc < AXGBE_MIN_RING_DESC)
548 /* First allocate the tx queue data structure */
549 txq = rte_zmalloc("ethdev TX queue", sizeof(struct axgbe_tx_queue),
550 RTE_CACHE_LINE_SIZE);
554 offloads = tx_conf->offloads |
555 txq->pdata->eth_dev->data->dev_conf.txmode.offloads;
556 txq->nb_desc = tx_desc;
557 txq->free_thresh = tx_conf->tx_free_thresh ?
558 tx_conf->tx_free_thresh : AXGBE_TX_FREE_THRESH;
559 if (txq->free_thresh > txq->nb_desc)
560 txq->free_thresh = (txq->nb_desc >> 1);
561 txq->free_batch_cnt = txq->free_thresh;
563 /* In vector_tx path threshold should be multiple of queue_size*/
564 if (txq->nb_desc % txq->free_thresh != 0)
565 txq->vector_disable = 1;
568 txq->vector_disable = 1;
570 /* Allocate TX ring hardware descriptors */
571 tsize = txq->nb_desc * sizeof(struct axgbe_tx_desc);
572 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
573 tsize, AXGBE_DESC_ALIGN, socket_id);
575 axgbe_tx_queue_release(txq);
578 memset(tz->addr, 0, tsize);
579 txq->ring_phys_addr = (uint64_t)tz->iova;
580 txq->desc = tz->addr;
581 txq->queue_id = queue_idx;
582 txq->port_id = dev->data->port_id;
583 txq->dma_regs = (void *)((uint8_t *)pdata->xgmac_regs + DMA_CH_BASE +
584 (DMA_CH_INC * txq->queue_id));
585 txq->dma_tail_reg = (volatile uint32_t *)((uint8_t *)txq->dma_regs +
589 txq->nb_desc_free = txq->nb_desc;
590 /* Allocate software ring */
591 tsize = txq->nb_desc * sizeof(struct rte_mbuf *);
592 txq->sw_ring = rte_zmalloc("tx_sw_ring", tsize,
593 RTE_CACHE_LINE_SIZE);
595 axgbe_tx_queue_release(txq);
598 dev->data->tx_queues[queue_idx] = txq;
599 if (!pdata->tx_queues)
600 pdata->tx_queues = dev->data->tx_queues;
602 if (txq->vector_disable ||
603 rte_vect_get_max_simd_bitwidth() < RTE_VECT_SIMD_128)
604 dev->tx_pkt_burst = &axgbe_xmit_pkts;
607 dev->tx_pkt_burst = &axgbe_xmit_pkts_vec;
609 dev->tx_pkt_burst = &axgbe_xmit_pkts;
615 int axgbe_dev_fw_version_get(struct rte_eth_dev *eth_dev,
616 char *fw_version, size_t fw_size)
618 struct axgbe_port *pdata;
619 struct axgbe_hw_features *hw_feat;
622 pdata = (struct axgbe_port *)eth_dev->data->dev_private;
623 hw_feat = &pdata->hw_feat;
625 ret = snprintf(fw_version, fw_size, "%d.%d.%d",
626 AXGMAC_GET_BITS(hw_feat->version, MAC_VR, USERVER),
627 AXGMAC_GET_BITS(hw_feat->version, MAC_VR, DEVID),
628 AXGMAC_GET_BITS(hw_feat->version, MAC_VR, SNPSVER));
632 ret += 1; /* add the size of '\0' */
633 if (fw_size < (size_t)ret)
639 static void axgbe_txq_prepare_tx_stop(struct axgbe_port *pdata,
642 unsigned int tx_status;
643 unsigned long tx_timeout;
645 /* The Tx engine cannot be stopped if it is actively processing
646 * packets. Wait for the Tx queue to empty the Tx fifo. Don't
647 * wait forever though...
649 tx_timeout = rte_get_timer_cycles() + (AXGBE_DMA_STOP_TIMEOUT *
651 while (time_before(rte_get_timer_cycles(), tx_timeout)) {
652 tx_status = AXGMAC_MTL_IOREAD(pdata, queue, MTL_Q_TQDR);
653 if ((AXGMAC_GET_BITS(tx_status, MTL_Q_TQDR, TRCSTS) != 1) &&
654 (AXGMAC_GET_BITS(tx_status, MTL_Q_TQDR, TXQSTS) == 0))
660 if (!time_before(rte_get_timer_cycles(), tx_timeout))
662 "timed out waiting for Tx queue %u to empty\n",
666 static void axgbe_prepare_tx_stop(struct axgbe_port *pdata,
669 unsigned int tx_dsr, tx_pos, tx_qidx;
670 unsigned int tx_status;
671 unsigned long tx_timeout;
673 if (AXGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) > 0x20)
674 return axgbe_txq_prepare_tx_stop(pdata, queue);
676 /* Calculate the status register to read and the position within */
677 if (queue < DMA_DSRX_FIRST_QUEUE) {
679 tx_pos = (queue * DMA_DSR_Q_WIDTH) + DMA_DSR0_TPS_START;
681 tx_qidx = queue - DMA_DSRX_FIRST_QUEUE;
683 tx_dsr = DMA_DSR1 + ((tx_qidx / DMA_DSRX_QPR) * DMA_DSRX_INC);
684 tx_pos = ((tx_qidx % DMA_DSRX_QPR) * DMA_DSR_Q_WIDTH) +
688 /* The Tx engine cannot be stopped if it is actively processing
689 * descriptors. Wait for the Tx engine to enter the stopped or
690 * suspended state. Don't wait forever though...
692 tx_timeout = rte_get_timer_cycles() + (AXGBE_DMA_STOP_TIMEOUT *
694 while (time_before(rte_get_timer_cycles(), tx_timeout)) {
695 tx_status = AXGMAC_IOREAD(pdata, tx_dsr);
696 tx_status = GET_BITS(tx_status, tx_pos, DMA_DSR_TPS_WIDTH);
697 if ((tx_status == DMA_TPS_STOPPED) ||
698 (tx_status == DMA_TPS_SUSPENDED))
704 if (!time_before(rte_get_timer_cycles(), tx_timeout))
706 "timed out waiting for Tx DMA channel %u to stop\n",
710 void axgbe_dev_disable_tx(struct rte_eth_dev *dev)
712 struct axgbe_tx_queue *txq;
713 struct axgbe_port *pdata = dev->data->dev_private;
716 /* Prepare for stopping DMA channel */
717 for (i = 0; i < pdata->tx_q_count; i++) {
718 txq = dev->data->tx_queues[i];
719 axgbe_prepare_tx_stop(pdata, i);
722 AXGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0);
723 /* Disable each Tx queue*/
724 for (i = 0; i < pdata->tx_q_count; i++)
725 AXGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN,
727 /* Disable each Tx DMA channel */
728 for (i = 0; i < dev->data->nb_tx_queues; i++) {
729 txq = dev->data->tx_queues[i];
730 AXGMAC_DMA_IOWRITE_BITS(txq, DMA_CH_TCR, ST, 0);
734 void axgbe_dev_enable_tx(struct rte_eth_dev *dev)
736 struct axgbe_tx_queue *txq;
737 struct axgbe_port *pdata = dev->data->dev_private;
740 for (i = 0; i < dev->data->nb_tx_queues; i++) {
741 txq = dev->data->tx_queues[i];
742 /* Enable Tx DMA channel */
743 AXGMAC_DMA_IOWRITE_BITS(txq, DMA_CH_TCR, ST, 1);
746 for (i = 0; i < pdata->tx_q_count; i++)
747 AXGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN,
750 AXGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1);
753 /* Free Tx conformed mbufs */
754 static void axgbe_xmit_cleanup(struct axgbe_tx_queue *txq)
756 volatile struct axgbe_tx_desc *desc;
759 idx = AXGBE_GET_DESC_IDX(txq, txq->dirty);
760 while (txq->cur != txq->dirty) {
761 if (unlikely(idx == txq->nb_desc))
763 desc = &txq->desc[idx];
764 /* Check for ownership */
765 if (AXGMAC_GET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, OWN))
767 memset((void *)&desc->desc2, 0, 8);
769 rte_pktmbuf_free(txq->sw_ring[idx]);
770 txq->sw_ring[idx++] = NULL;
775 /* Tx Descriptor formation
776 * Considering each mbuf requires one desc
779 static int axgbe_xmit_hw(struct axgbe_tx_queue *txq,
780 struct rte_mbuf *mbuf)
782 volatile struct axgbe_tx_desc *desc;
786 idx = AXGBE_GET_DESC_IDX(txq, txq->cur);
787 desc = &txq->desc[idx];
789 /* Update buffer address and length */
790 desc->baddr = rte_mbuf_data_iova(mbuf);
791 AXGMAC_SET_BITS_LE(desc->desc2, TX_NORMAL_DESC2, HL_B1L,
793 /* Total msg length to transmit */
794 AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, FL,
796 /* Timestamp enablement check */
797 if (mbuf->ol_flags & RTE_MBUF_F_TX_IEEE1588_TMST)
798 AXGMAC_SET_BITS_LE(desc->desc2, TX_NORMAL_DESC2, TTSE, 1);
800 /* Mark it as First and Last Descriptor */
801 AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, FD, 1);
802 AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, LD, 1);
803 /* Mark it as a NORMAL descriptor */
804 AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, CTXT, 0);
805 /* configure h/w Offload */
806 mask = mbuf->ol_flags & RTE_MBUF_F_TX_L4_MASK;
807 if (mask == RTE_MBUF_F_TX_TCP_CKSUM || mask == RTE_MBUF_F_TX_UDP_CKSUM)
808 AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, CIC, 0x3);
809 else if (mbuf->ol_flags & RTE_MBUF_F_TX_IP_CKSUM)
810 AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, CIC, 0x1);
813 if (mbuf->ol_flags & (RTE_MBUF_F_TX_VLAN | RTE_MBUF_F_TX_QINQ)) {
814 /* Mark it as a CONTEXT descriptor */
815 AXGMAC_SET_BITS_LE(desc->desc3, TX_CONTEXT_DESC3,
817 /* Set the VLAN tag */
818 AXGMAC_SET_BITS_LE(desc->desc3, TX_CONTEXT_DESC3,
820 /* Indicate this descriptor contains the VLAN tag */
821 AXGMAC_SET_BITS_LE(desc->desc3, TX_CONTEXT_DESC3,
823 AXGMAC_SET_BITS_LE(desc->desc2, TX_NORMAL_DESC2, VTIR,
824 TX_NORMAL_DESC2_VLAN_INSERT);
826 AXGMAC_SET_BITS_LE(desc->desc2, TX_NORMAL_DESC2, VTIR, 0x0);
831 AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, OWN, 1);
836 txq->sw_ring[idx] = mbuf;
837 /* Update current index*/
840 txq->bytes += mbuf->pkt_len;
845 /* Eal supported tx wrapper*/
847 axgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
850 PMD_INIT_FUNC_TRACE();
852 if (unlikely(nb_pkts == 0))
855 struct axgbe_tx_queue *txq;
856 uint16_t nb_desc_free;
857 uint16_t nb_pkt_sent = 0;
860 struct rte_mbuf *mbuf;
862 txq = (struct axgbe_tx_queue *)tx_queue;
863 nb_desc_free = txq->nb_desc - (txq->cur - txq->dirty);
865 if (unlikely(nb_desc_free <= txq->free_thresh)) {
866 axgbe_xmit_cleanup(txq);
867 nb_desc_free = txq->nb_desc - (txq->cur - txq->dirty);
868 if (unlikely(nb_desc_free == 0))
871 nb_pkts = RTE_MIN(nb_desc_free, nb_pkts);
874 if (axgbe_xmit_hw(txq, mbuf))
879 /* Sync read and write */
881 idx = AXGBE_GET_DESC_IDX(txq, txq->cur);
882 tail_addr = low32_value(txq->ring_phys_addr +
883 idx * sizeof(struct axgbe_tx_desc));
884 /* Update tail reg with next immediate address to kick Tx DMA channel*/
885 AXGMAC_DMA_IOWRITE(txq, DMA_CH_TDTR_LO, tail_addr);
886 txq->pkts += nb_pkt_sent;
890 void axgbe_dev_clear_queues(struct rte_eth_dev *dev)
892 PMD_INIT_FUNC_TRACE();
894 struct axgbe_rx_queue *rxq;
895 struct axgbe_tx_queue *txq;
897 for (i = 0; i < dev->data->nb_rx_queues; i++) {
898 rxq = dev->data->rx_queues[i];
901 axgbe_rx_queue_release(rxq);
902 dev->data->rx_queues[i] = NULL;
906 for (i = 0; i < dev->data->nb_tx_queues; i++) {
907 txq = dev->data->tx_queues[i];
910 axgbe_tx_queue_release(txq);
911 dev->data->tx_queues[i] = NULL;
917 axgbe_dev_rx_descriptor_status(void *rx_queue, uint16_t offset)
919 struct axgbe_rx_queue *rxq = rx_queue;
920 volatile union axgbe_rx_desc *desc;
924 if (unlikely(offset >= rxq->nb_desc))
927 if (offset >= rxq->nb_desc - rxq->dirty)
928 return RTE_ETH_RX_DESC_UNAVAIL;
930 idx = AXGBE_GET_DESC_IDX(rxq, rxq->cur);
931 desc = &rxq->desc[idx + offset];
933 if (!AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, OWN))
934 return RTE_ETH_RX_DESC_DONE;
936 return RTE_ETH_RX_DESC_AVAIL;
940 axgbe_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)
942 struct axgbe_tx_queue *txq = tx_queue;
943 volatile struct axgbe_tx_desc *desc;
947 if (unlikely(offset >= txq->nb_desc))
950 if (offset >= txq->nb_desc - txq->dirty)
951 return RTE_ETH_TX_DESC_UNAVAIL;
953 idx = AXGBE_GET_DESC_IDX(txq, txq->dirty + txq->free_batch_cnt - 1);
954 desc = &txq->desc[idx + offset];
956 if (!AXGMAC_GET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, OWN))
957 return RTE_ETH_TX_DESC_DONE;
959 return RTE_ETH_TX_DESC_FULL;