1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved.
3 * Copyright(c) 2018 Synopsys, Inc. All rights reserved.
6 #include "axgbe_ethdev.h"
7 #include "axgbe_rxtx.h"
11 #include <rte_mempool.h>
15 axgbe_rx_queue_release(struct axgbe_rx_queue *rx_queue)
18 struct rte_mbuf **sw_ring;
21 sw_ring = rx_queue->sw_ring;
23 for (i = 0; i < rx_queue->nb_desc; i++) {
25 rte_pktmbuf_free(sw_ring[i]);
33 void axgbe_dev_rx_queue_release(void *rxq)
35 axgbe_rx_queue_release(rxq);
38 int axgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
39 uint16_t nb_desc, unsigned int socket_id,
40 const struct rte_eth_rxconf *rx_conf,
41 struct rte_mempool *mp)
43 PMD_INIT_FUNC_TRACE();
45 const struct rte_memzone *dma;
46 struct axgbe_rx_queue *rxq;
47 uint32_t rx_desc = nb_desc;
48 struct axgbe_port *pdata = dev->data->dev_private;
51 * validate Rx descriptors count
52 * should be power of 2 and less than h/w supported
54 if ((!rte_is_power_of_2(rx_desc)) ||
55 rx_desc > pdata->rx_desc_count)
57 /* First allocate the rx queue data structure */
58 rxq = rte_zmalloc_socket("ethdev RX queue",
59 sizeof(struct axgbe_rx_queue),
60 RTE_CACHE_LINE_SIZE, socket_id);
62 PMD_INIT_LOG(ERR, "rte_zmalloc for rxq failed!");
70 rxq->queue_id = queue_idx;
71 rxq->port_id = dev->data->port_id;
72 rxq->nb_desc = rx_desc;
73 rxq->dma_regs = (void *)((uint8_t *)pdata->xgmac_regs + DMA_CH_BASE +
74 (DMA_CH_INC * rxq->queue_id));
75 rxq->dma_tail_reg = (volatile uint32_t *)((uint8_t *)rxq->dma_regs +
77 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
78 rxq->crc_len = RTE_ETHER_CRC_LEN;
82 /* CRC strip in AXGBE supports per port not per queue */
83 pdata->crc_strip_enable = (rxq->crc_len == 0) ? 1 : 0;
84 rxq->free_thresh = rx_conf->rx_free_thresh ?
85 rx_conf->rx_free_thresh : AXGBE_RX_FREE_THRESH;
86 if (rxq->free_thresh > rxq->nb_desc)
87 rxq->free_thresh = rxq->nb_desc >> 3;
89 /* Allocate RX ring hardware descriptors */
90 size = rxq->nb_desc * sizeof(union axgbe_rx_desc);
91 dma = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx, size, 128,
94 PMD_DRV_LOG(ERR, "ring_dma_zone_reserve for rx_ring failed\n");
95 axgbe_rx_queue_release(rxq);
98 rxq->ring_phys_addr = (uint64_t)dma->iova;
99 rxq->desc = (volatile union axgbe_rx_desc *)dma->addr;
100 memset((void *)rxq->desc, 0, size);
101 /* Allocate software ring */
102 size = rxq->nb_desc * sizeof(struct rte_mbuf *);
103 rxq->sw_ring = rte_zmalloc_socket("sw_ring", size,
107 PMD_DRV_LOG(ERR, "rte_zmalloc for sw_ring failed\n");
108 axgbe_rx_queue_release(rxq);
111 dev->data->rx_queues[queue_idx] = rxq;
112 if (!pdata->rx_queues)
113 pdata->rx_queues = dev->data->rx_queues;
118 static void axgbe_prepare_rx_stop(struct axgbe_port *pdata,
121 unsigned int rx_status;
122 unsigned long rx_timeout;
124 /* The Rx engine cannot be stopped if it is actively processing
125 * packets. Wait for the Rx queue to empty the Rx fifo. Don't
126 * wait forever though...
128 rx_timeout = rte_get_timer_cycles() + (AXGBE_DMA_STOP_TIMEOUT *
131 while (time_before(rte_get_timer_cycles(), rx_timeout)) {
132 rx_status = AXGMAC_MTL_IOREAD(pdata, queue, MTL_Q_RQDR);
133 if ((AXGMAC_GET_BITS(rx_status, MTL_Q_RQDR, PRXQ) == 0) &&
134 (AXGMAC_GET_BITS(rx_status, MTL_Q_RQDR, RXQSTS) == 0))
140 if (!time_before(rte_get_timer_cycles(), rx_timeout))
142 "timed out waiting for Rx queue %u to empty\n",
146 void axgbe_dev_disable_rx(struct rte_eth_dev *dev)
148 struct axgbe_rx_queue *rxq;
149 struct axgbe_port *pdata = dev->data->dev_private;
153 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 0);
154 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 0);
155 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 0);
156 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 0);
158 /* Prepare for Rx DMA channel stop */
159 for (i = 0; i < dev->data->nb_rx_queues; i++) {
160 rxq = dev->data->rx_queues[i];
161 axgbe_prepare_rx_stop(pdata, i);
163 /* Disable each Rx queue */
164 AXGMAC_IOWRITE(pdata, MAC_RQC0R, 0);
165 for (i = 0; i < dev->data->nb_rx_queues; i++) {
166 rxq = dev->data->rx_queues[i];
167 /* Disable Rx DMA channel */
168 AXGMAC_DMA_IOWRITE_BITS(rxq, DMA_CH_RCR, SR, 0);
172 void axgbe_dev_enable_rx(struct rte_eth_dev *dev)
174 struct axgbe_rx_queue *rxq;
175 struct axgbe_port *pdata = dev->data->dev_private;
177 unsigned int reg_val = 0;
179 for (i = 0; i < dev->data->nb_rx_queues; i++) {
180 rxq = dev->data->rx_queues[i];
181 /* Enable Rx DMA channel */
182 AXGMAC_DMA_IOWRITE_BITS(rxq, DMA_CH_RCR, SR, 1);
186 for (i = 0; i < pdata->rx_q_count; i++)
187 reg_val |= (0x02 << (i << 1));
188 AXGMAC_IOWRITE(pdata, MAC_RQC0R, reg_val);
191 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 1);
192 /* Frame is forwarded after stripping CRC to application*/
193 if (pdata->crc_strip_enable) {
194 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 1);
195 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 1);
197 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 1);
200 /* Rx function one to one refresh */
202 axgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
205 PMD_INIT_FUNC_TRACE();
207 struct axgbe_rx_queue *rxq = rx_queue;
208 volatile union axgbe_rx_desc *desc;
209 uint64_t old_dirty = rxq->dirty;
210 struct rte_mbuf *mbuf, *tmbuf;
212 uint32_t error_status;
213 uint16_t idx, pidx, pkt_len;
215 idx = AXGBE_GET_DESC_IDX(rxq, rxq->cur);
216 while (nb_rx < nb_pkts) {
217 if (unlikely(idx == rxq->nb_desc))
220 desc = &rxq->desc[idx];
222 if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, OWN))
224 tmbuf = rte_mbuf_raw_alloc(rxq->mb_pool);
225 if (unlikely(!tmbuf)) {
226 PMD_DRV_LOG(ERR, "RX mbuf alloc failed port_id = %u"
228 (unsigned int)rxq->port_id,
229 (unsigned int)rxq->queue_id);
231 rxq->port_id].data->rx_mbuf_alloc_failed++;
232 rxq->rx_mbuf_alloc_failed++;
236 if (unlikely(pidx == rxq->nb_desc))
239 rte_prefetch0(rxq->sw_ring[pidx]);
240 if ((pidx & 0x3) == 0) {
241 rte_prefetch0(&rxq->desc[pidx]);
242 rte_prefetch0(&rxq->sw_ring[pidx]);
245 mbuf = rxq->sw_ring[idx];
246 /* Check for any errors and free mbuf*/
247 err = AXGMAC_GET_BITS_LE(desc->write.desc3,
248 RX_NORMAL_DESC3, ES);
251 error_status = desc->write.desc3 & AXGBE_ERR_STATUS;
252 if ((error_status != AXGBE_L3_CSUM_ERR) &&
253 (error_status != AXGBE_L4_CSUM_ERR)) {
255 rte_pktmbuf_free(mbuf);
259 if (rxq->pdata->rx_csum_enable) {
261 mbuf->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
262 mbuf->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
263 if (unlikely(error_status == AXGBE_L3_CSUM_ERR)) {
264 mbuf->ol_flags &= ~PKT_RX_IP_CKSUM_GOOD;
265 mbuf->ol_flags |= PKT_RX_IP_CKSUM_BAD;
266 mbuf->ol_flags &= ~PKT_RX_L4_CKSUM_GOOD;
267 mbuf->ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;
269 unlikely(error_status == AXGBE_L4_CSUM_ERR)) {
270 mbuf->ol_flags &= ~PKT_RX_L4_CKSUM_GOOD;
271 mbuf->ol_flags |= PKT_RX_L4_CKSUM_BAD;
274 rte_prefetch1(rte_pktmbuf_mtod(mbuf, void *));
275 /* Get the RSS hash */
276 if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, RSV))
277 mbuf->hash.rss = rte_le_to_cpu_32(desc->write.desc1);
278 /* Indicate if a Context Descriptor is next */
279 if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, CDA))
280 mbuf->ol_flags |= PKT_RX_IEEE1588_PTP
281 | PKT_RX_IEEE1588_TMST;
282 pkt_len = AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3,
286 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
288 mbuf->port = rxq->port_id;
289 mbuf->pkt_len = pkt_len;
290 mbuf->data_len = pkt_len;
291 rxq->bytes += pkt_len;
292 rx_pkts[nb_rx++] = mbuf;
295 rxq->sw_ring[idx++] = tmbuf;
297 rte_cpu_to_le_64(rte_mbuf_data_iova_default(tmbuf));
298 memset((void *)(&desc->read.desc2), 0, 8);
299 AXGMAC_SET_BITS_LE(desc->read.desc3, RX_NORMAL_DESC3, OWN, 1);
303 if (rxq->dirty != old_dirty) {
305 idx = AXGBE_GET_DESC_IDX(rxq, rxq->dirty - 1);
306 AXGMAC_DMA_IOWRITE(rxq, DMA_CH_RDTR_LO,
307 low32_value(rxq->ring_phys_addr +
308 (idx * sizeof(union axgbe_rx_desc))));
315 uint16_t eth_axgbe_recv_scattered_pkts(void *rx_queue,
316 struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
318 PMD_INIT_FUNC_TRACE();
320 struct axgbe_rx_queue *rxq = rx_queue;
321 volatile union axgbe_rx_desc *desc;
323 uint64_t old_dirty = rxq->dirty;
324 struct rte_mbuf *first_seg = NULL;
325 struct rte_mbuf *mbuf, *tmbuf;
327 uint32_t error_status;
328 uint16_t idx, pidx, data_len = 0, pkt_len = 0;
330 idx = AXGBE_GET_DESC_IDX(rxq, rxq->cur);
331 while (nb_rx < nb_pkts) {
334 if (unlikely(idx == rxq->nb_desc))
337 desc = &rxq->desc[idx];
339 if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, OWN))
342 tmbuf = rte_mbuf_raw_alloc(rxq->mb_pool);
343 if (unlikely(!tmbuf)) {
344 PMD_DRV_LOG(ERR, "RX mbuf alloc failed port_id = %u"
346 (unsigned int)rxq->port_id,
347 (unsigned int)rxq->queue_id);
348 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
353 if (unlikely(pidx == rxq->nb_desc))
356 rte_prefetch0(rxq->sw_ring[pidx]);
357 if ((pidx & 0x3) == 0) {
358 rte_prefetch0(&rxq->desc[pidx]);
359 rte_prefetch0(&rxq->sw_ring[pidx]);
362 mbuf = rxq->sw_ring[idx];
363 /* Check for any errors and free mbuf*/
364 err = AXGMAC_GET_BITS_LE(desc->write.desc3,
365 RX_NORMAL_DESC3, ES);
368 error_status = desc->write.desc3 & AXGBE_ERR_STATUS;
369 if ((error_status != AXGBE_L3_CSUM_ERR)
370 && (error_status != AXGBE_L4_CSUM_ERR)) {
372 rte_pktmbuf_free(mbuf);
376 rte_prefetch1(rte_pktmbuf_mtod(mbuf, void *));
378 if (!AXGMAC_GET_BITS_LE(desc->write.desc3,
379 RX_NORMAL_DESC3, LD)) {
381 pkt_len = rxq->buf_size;
385 pkt_len = AXGMAC_GET_BITS_LE(desc->write.desc3,
386 RX_NORMAL_DESC3, PL);
387 data_len = pkt_len - rxq->crc_len;
390 if (first_seg != NULL) {
391 if (rte_pktmbuf_chain(first_seg, mbuf) != 0)
392 rte_mempool_put(rxq->mb_pool,
398 /* Get the RSS hash */
399 if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, RSV))
400 mbuf->hash.rss = rte_le_to_cpu_32(desc->write.desc1);
403 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
404 mbuf->data_len = data_len;
408 rxq->sw_ring[idx++] = tmbuf;
410 rte_cpu_to_le_64(rte_mbuf_data_iova_default(tmbuf));
411 memset((void *)(&desc->read.desc2), 0, 8);
412 AXGMAC_SET_BITS_LE(desc->read.desc3, RX_NORMAL_DESC3, OWN, 1);
416 rte_pktmbuf_free(mbuf);
420 first_seg->pkt_len = pkt_len;
421 rxq->bytes += pkt_len;
424 first_seg->port = rxq->port_id;
425 if (rxq->pdata->rx_csum_enable) {
427 mbuf->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
428 mbuf->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
429 if (unlikely(error_status == AXGBE_L3_CSUM_ERR)) {
430 mbuf->ol_flags &= ~PKT_RX_IP_CKSUM_GOOD;
431 mbuf->ol_flags |= PKT_RX_IP_CKSUM_BAD;
432 mbuf->ol_flags &= ~PKT_RX_L4_CKSUM_GOOD;
433 mbuf->ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;
434 } else if (unlikely(error_status
435 == AXGBE_L4_CSUM_ERR)) {
436 mbuf->ol_flags &= ~PKT_RX_L4_CKSUM_GOOD;
437 mbuf->ol_flags |= PKT_RX_L4_CKSUM_BAD;
441 rx_pkts[nb_rx++] = first_seg;
443 /* Setup receipt context for a new packet.*/
447 /* Save receive context.*/
450 if (rxq->dirty != old_dirty) {
452 idx = AXGBE_GET_DESC_IDX(rxq, rxq->dirty - 1);
453 AXGMAC_DMA_IOWRITE(rxq, DMA_CH_RDTR_LO,
454 low32_value(rxq->ring_phys_addr +
455 (idx * sizeof(union axgbe_rx_desc))));
461 static void axgbe_tx_queue_release(struct axgbe_tx_queue *tx_queue)
464 struct rte_mbuf **sw_ring;
467 sw_ring = tx_queue->sw_ring;
469 for (i = 0; i < tx_queue->nb_desc; i++) {
471 rte_pktmbuf_free(sw_ring[i]);
479 void axgbe_dev_tx_queue_release(void *txq)
481 axgbe_tx_queue_release(txq);
484 int axgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
485 uint16_t nb_desc, unsigned int socket_id,
486 const struct rte_eth_txconf *tx_conf)
488 PMD_INIT_FUNC_TRACE();
490 struct axgbe_port *pdata;
491 struct axgbe_tx_queue *txq;
493 const struct rte_memzone *tz;
496 pdata = dev->data->dev_private;
499 * validate tx descriptors count
500 * should be power of 2 and less than h/w supported
502 if ((!rte_is_power_of_2(tx_desc)) ||
503 tx_desc > pdata->tx_desc_count ||
504 tx_desc < AXGBE_MIN_RING_DESC)
507 /* First allocate the tx queue data structure */
508 txq = rte_zmalloc("ethdev TX queue", sizeof(struct axgbe_tx_queue),
509 RTE_CACHE_LINE_SIZE);
514 txq->nb_desc = tx_desc;
515 txq->free_thresh = tx_conf->tx_free_thresh ?
516 tx_conf->tx_free_thresh : AXGBE_TX_FREE_THRESH;
517 if (txq->free_thresh > txq->nb_desc)
518 txq->free_thresh = (txq->nb_desc >> 1);
519 txq->free_batch_cnt = txq->free_thresh;
521 /* In vector_tx path threshold should be multiple of queue_size*/
522 if (txq->nb_desc % txq->free_thresh != 0)
523 txq->vector_disable = 1;
525 if (tx_conf->offloads != 0)
526 txq->vector_disable = 1;
528 /* Allocate TX ring hardware descriptors */
529 tsize = txq->nb_desc * sizeof(struct axgbe_tx_desc);
530 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
531 tsize, AXGBE_DESC_ALIGN, socket_id);
533 axgbe_tx_queue_release(txq);
536 memset(tz->addr, 0, tsize);
537 txq->ring_phys_addr = (uint64_t)tz->iova;
538 txq->desc = tz->addr;
539 txq->queue_id = queue_idx;
540 txq->port_id = dev->data->port_id;
541 txq->dma_regs = (void *)((uint8_t *)pdata->xgmac_regs + DMA_CH_BASE +
542 (DMA_CH_INC * txq->queue_id));
543 txq->dma_tail_reg = (volatile uint32_t *)((uint8_t *)txq->dma_regs +
547 txq->nb_desc_free = txq->nb_desc;
548 /* Allocate software ring */
549 tsize = txq->nb_desc * sizeof(struct rte_mbuf *);
550 txq->sw_ring = rte_zmalloc("tx_sw_ring", tsize,
551 RTE_CACHE_LINE_SIZE);
553 axgbe_tx_queue_release(txq);
556 dev->data->tx_queues[queue_idx] = txq;
557 if (!pdata->tx_queues)
558 pdata->tx_queues = dev->data->tx_queues;
560 if (txq->vector_disable)
561 dev->tx_pkt_burst = &axgbe_xmit_pkts;
564 dev->tx_pkt_burst = &axgbe_xmit_pkts_vec;
566 dev->tx_pkt_burst = &axgbe_xmit_pkts;
572 static void axgbe_txq_prepare_tx_stop(struct axgbe_port *pdata,
575 unsigned int tx_status;
576 unsigned long tx_timeout;
578 /* The Tx engine cannot be stopped if it is actively processing
579 * packets. Wait for the Tx queue to empty the Tx fifo. Don't
580 * wait forever though...
582 tx_timeout = rte_get_timer_cycles() + (AXGBE_DMA_STOP_TIMEOUT *
584 while (time_before(rte_get_timer_cycles(), tx_timeout)) {
585 tx_status = AXGMAC_MTL_IOREAD(pdata, queue, MTL_Q_TQDR);
586 if ((AXGMAC_GET_BITS(tx_status, MTL_Q_TQDR, TRCSTS) != 1) &&
587 (AXGMAC_GET_BITS(tx_status, MTL_Q_TQDR, TXQSTS) == 0))
593 if (!time_before(rte_get_timer_cycles(), tx_timeout))
595 "timed out waiting for Tx queue %u to empty\n",
599 static void axgbe_prepare_tx_stop(struct axgbe_port *pdata,
602 unsigned int tx_dsr, tx_pos, tx_qidx;
603 unsigned int tx_status;
604 unsigned long tx_timeout;
606 if (AXGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) > 0x20)
607 return axgbe_txq_prepare_tx_stop(pdata, queue);
609 /* Calculate the status register to read and the position within */
610 if (queue < DMA_DSRX_FIRST_QUEUE) {
612 tx_pos = (queue * DMA_DSR_Q_WIDTH) + DMA_DSR0_TPS_START;
614 tx_qidx = queue - DMA_DSRX_FIRST_QUEUE;
616 tx_dsr = DMA_DSR1 + ((tx_qidx / DMA_DSRX_QPR) * DMA_DSRX_INC);
617 tx_pos = ((tx_qidx % DMA_DSRX_QPR) * DMA_DSR_Q_WIDTH) +
621 /* The Tx engine cannot be stopped if it is actively processing
622 * descriptors. Wait for the Tx engine to enter the stopped or
623 * suspended state. Don't wait forever though...
625 tx_timeout = rte_get_timer_cycles() + (AXGBE_DMA_STOP_TIMEOUT *
627 while (time_before(rte_get_timer_cycles(), tx_timeout)) {
628 tx_status = AXGMAC_IOREAD(pdata, tx_dsr);
629 tx_status = GET_BITS(tx_status, tx_pos, DMA_DSR_TPS_WIDTH);
630 if ((tx_status == DMA_TPS_STOPPED) ||
631 (tx_status == DMA_TPS_SUSPENDED))
637 if (!time_before(rte_get_timer_cycles(), tx_timeout))
639 "timed out waiting for Tx DMA channel %u to stop\n",
643 void axgbe_dev_disable_tx(struct rte_eth_dev *dev)
645 struct axgbe_tx_queue *txq;
646 struct axgbe_port *pdata = dev->data->dev_private;
649 /* Prepare for stopping DMA channel */
650 for (i = 0; i < pdata->tx_q_count; i++) {
651 txq = dev->data->tx_queues[i];
652 axgbe_prepare_tx_stop(pdata, i);
655 AXGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0);
656 /* Disable each Tx queue*/
657 for (i = 0; i < pdata->tx_q_count; i++)
658 AXGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN,
660 /* Disable each Tx DMA channel */
661 for (i = 0; i < dev->data->nb_tx_queues; i++) {
662 txq = dev->data->tx_queues[i];
663 AXGMAC_DMA_IOWRITE_BITS(txq, DMA_CH_TCR, ST, 0);
667 void axgbe_dev_enable_tx(struct rte_eth_dev *dev)
669 struct axgbe_tx_queue *txq;
670 struct axgbe_port *pdata = dev->data->dev_private;
673 for (i = 0; i < dev->data->nb_tx_queues; i++) {
674 txq = dev->data->tx_queues[i];
675 /* Enable Tx DMA channel */
676 AXGMAC_DMA_IOWRITE_BITS(txq, DMA_CH_TCR, ST, 1);
679 for (i = 0; i < pdata->tx_q_count; i++)
680 AXGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN,
683 AXGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1);
686 /* Free Tx conformed mbufs */
687 static void axgbe_xmit_cleanup(struct axgbe_tx_queue *txq)
689 volatile struct axgbe_tx_desc *desc;
692 idx = AXGBE_GET_DESC_IDX(txq, txq->dirty);
693 while (txq->cur != txq->dirty) {
694 if (unlikely(idx == txq->nb_desc))
696 desc = &txq->desc[idx];
697 /* Check for ownership */
698 if (AXGMAC_GET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, OWN))
700 memset((void *)&desc->desc2, 0, 8);
702 rte_pktmbuf_free(txq->sw_ring[idx]);
703 txq->sw_ring[idx++] = NULL;
708 /* Tx Descriptor formation
709 * Considering each mbuf requires one desc
712 static int axgbe_xmit_hw(struct axgbe_tx_queue *txq,
713 struct rte_mbuf *mbuf)
715 volatile struct axgbe_tx_desc *desc;
719 idx = AXGBE_GET_DESC_IDX(txq, txq->cur);
720 desc = &txq->desc[idx];
722 /* Update buffer address and length */
723 desc->baddr = rte_mbuf_data_iova(mbuf);
724 AXGMAC_SET_BITS_LE(desc->desc2, TX_NORMAL_DESC2, HL_B1L,
726 /* Total msg length to transmit */
727 AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, FL,
729 /* Timestamp enablement check */
730 if (mbuf->ol_flags & PKT_TX_IEEE1588_TMST)
731 AXGMAC_SET_BITS_LE(desc->desc2, TX_NORMAL_DESC2, TTSE, 1);
733 /* Mark it as First and Last Descriptor */
734 AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, FD, 1);
735 AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, LD, 1);
736 /* Mark it as a NORMAL descriptor */
737 AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, CTXT, 0);
738 /* configure h/w Offload */
739 mask = mbuf->ol_flags & PKT_TX_L4_MASK;
740 if ((mask == PKT_TX_TCP_CKSUM) || (mask == PKT_TX_UDP_CKSUM))
741 AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, CIC, 0x3);
742 else if (mbuf->ol_flags & PKT_TX_IP_CKSUM)
743 AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, CIC, 0x1);
747 AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, OWN, 1);
751 txq->sw_ring[idx] = mbuf;
752 /* Update current index*/
755 txq->bytes += mbuf->pkt_len;
760 /* Eal supported tx wrapper*/
762 axgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
765 PMD_INIT_FUNC_TRACE();
767 if (unlikely(nb_pkts == 0))
770 struct axgbe_tx_queue *txq;
771 uint16_t nb_desc_free;
772 uint16_t nb_pkt_sent = 0;
775 struct rte_mbuf *mbuf;
777 txq = (struct axgbe_tx_queue *)tx_queue;
778 nb_desc_free = txq->nb_desc - (txq->cur - txq->dirty);
780 if (unlikely(nb_desc_free <= txq->free_thresh)) {
781 axgbe_xmit_cleanup(txq);
782 nb_desc_free = txq->nb_desc - (txq->cur - txq->dirty);
783 if (unlikely(nb_desc_free == 0))
786 nb_pkts = RTE_MIN(nb_desc_free, nb_pkts);
789 if (axgbe_xmit_hw(txq, mbuf))
794 /* Sync read and write */
796 idx = AXGBE_GET_DESC_IDX(txq, txq->cur);
797 tail_addr = low32_value(txq->ring_phys_addr +
798 idx * sizeof(struct axgbe_tx_desc));
799 /* Update tail reg with next immediate address to kick Tx DMA channel*/
800 AXGMAC_DMA_IOWRITE(txq, DMA_CH_TDTR_LO, tail_addr);
801 txq->pkts += nb_pkt_sent;
805 void axgbe_dev_clear_queues(struct rte_eth_dev *dev)
807 PMD_INIT_FUNC_TRACE();
809 struct axgbe_rx_queue *rxq;
810 struct axgbe_tx_queue *txq;
812 for (i = 0; i < dev->data->nb_rx_queues; i++) {
813 rxq = dev->data->rx_queues[i];
816 axgbe_rx_queue_release(rxq);
817 dev->data->rx_queues[i] = NULL;
821 for (i = 0; i < dev->data->nb_tx_queues; i++) {
822 txq = dev->data->tx_queues[i];
825 axgbe_tx_queue_release(txq);
826 dev->data->tx_queues[i] = NULL;
832 axgbe_dev_rx_descriptor_status(void *rx_queue, uint16_t offset)
834 struct axgbe_rx_queue *rxq = rx_queue;
835 volatile union axgbe_rx_desc *desc;
839 if (unlikely(offset >= rxq->nb_desc))
842 if (offset >= rxq->nb_desc - rxq->dirty)
843 return RTE_ETH_RX_DESC_UNAVAIL;
845 idx = AXGBE_GET_DESC_IDX(rxq, rxq->cur);
846 desc = &rxq->desc[idx + offset];
848 if (!AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, OWN))
849 return RTE_ETH_RX_DESC_DONE;
851 return RTE_ETH_RX_DESC_AVAIL;
855 axgbe_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)
857 struct axgbe_tx_queue *txq = tx_queue;
858 volatile struct axgbe_tx_desc *desc;
862 if (unlikely(offset >= txq->nb_desc))
865 if (offset >= txq->nb_desc - txq->dirty)
866 return RTE_ETH_TX_DESC_UNAVAIL;
868 idx = AXGBE_GET_DESC_IDX(txq, txq->dirty + txq->free_batch_cnt - 1);
869 desc = &txq->desc[idx + offset];
871 if (!AXGMAC_GET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, OWN))
872 return RTE_ETH_TX_DESC_DONE;
874 return RTE_ETH_TX_DESC_FULL;