1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2007-2013 Broadcom Corporation.
4 * Eric Davis <edavis@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
6 * Gary Zambrano <zambrano@broadcom.com>
8 * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
9 * Copyright (c) 2015-2018 Cavium Inc.
10 * All rights reserved.
14 #define BNX2X_DRIVER_VERSION "1.78.18"
17 #include "bnx2x_vfpf.h"
19 #include "ecore_init.h"
20 #include "ecore_init_ops.h"
22 #include "rte_version.h"
24 #include <sys/types.h>
29 #define BNX2X_PMD_VER_PREFIX "BNX2X PMD"
30 #define BNX2X_PMD_VERSION_MAJOR 1
31 #define BNX2X_PMD_VERSION_MINOR 0
32 #define BNX2X_PMD_VERSION_REVISION 6
33 #define BNX2X_PMD_VERSION_PATCH 1
35 static inline const char *
36 bnx2x_pmd_version(void)
38 static char version[32];
40 snprintf(version, sizeof(version), "%s %s_%d.%d.%d.%d",
43 BNX2X_PMD_VERSION_MAJOR,
44 BNX2X_PMD_VERSION_MINOR,
45 BNX2X_PMD_VERSION_REVISION,
46 BNX2X_PMD_VERSION_PATCH);
51 static z_stream zlib_stream;
53 #define EVL_VLID_MASK 0x0FFF
55 #define BNX2X_DEF_SB_ATT_IDX 0x0001
56 #define BNX2X_DEF_SB_IDX 0x0002
59 * FLR Support - bnx2x_pf_flr_clnup() is called during nic_load in the per
60 * function HW initialization.
62 #define FLR_WAIT_USEC 10000 /* 10 msecs */
63 #define FLR_WAIT_INTERVAL 50 /* usecs */
64 #define FLR_POLL_CNT (FLR_WAIT_USEC / FLR_WAIT_INTERVAL) /* 200 */
66 struct pbf_pN_buf_regs {
73 struct pbf_pN_cmd_regs {
79 /* resources needed for unloading a previously loaded device */
81 #define BNX2X_PREV_WAIT_NEEDED 1
82 rte_spinlock_t bnx2x_prev_mtx;
83 struct bnx2x_prev_list_node {
84 LIST_ENTRY(bnx2x_prev_list_node) node;
92 static LIST_HEAD(, bnx2x_prev_list_node) bnx2x_prev_list
93 = LIST_HEAD_INITIALIZER(bnx2x_prev_list);
95 static int load_count[2][3] = { { 0 } };
96 /* per-path: 0-common, 1-port0, 2-port1 */
98 static void bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg,
100 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc);
101 static void storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng,
103 static void bnx2x_set_reset_global(struct bnx2x_softc *sc);
104 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc);
105 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine);
106 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc);
107 static uint8_t bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global,
109 static void bnx2x_int_disable(struct bnx2x_softc *sc);
110 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc);
111 static void bnx2x_pf_disable(struct bnx2x_softc *sc);
112 static void bnx2x_update_rx_prod(struct bnx2x_softc *sc,
113 struct bnx2x_fastpath *fp,
114 uint16_t rx_bd_prod, uint16_t rx_cq_prod);
115 static void bnx2x_link_report(struct bnx2x_softc *sc);
116 void bnx2x_link_status_update(struct bnx2x_softc *sc);
117 static int bnx2x_alloc_mem(struct bnx2x_softc *sc);
118 static void bnx2x_free_mem(struct bnx2x_softc *sc);
119 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc);
120 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc);
121 static __rte_noinline
122 int bnx2x_nic_load(struct bnx2x_softc *sc);
124 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc);
125 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp, int scan_fp);
126 static void bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id,
127 uint8_t storm, uint16_t index, uint8_t op,
130 int bnx2x_test_bit(int nr, volatile unsigned long *addr)
135 res = ((*addr) & (1UL << nr)) != 0;
140 void bnx2x_set_bit(unsigned int nr, volatile unsigned long *addr)
142 __sync_fetch_and_or(addr, (1UL << nr));
145 void bnx2x_clear_bit(int nr, volatile unsigned long *addr)
147 __sync_fetch_and_and(addr, ~(1UL << nr));
150 int bnx2x_test_and_clear_bit(int nr, volatile unsigned long *addr)
152 unsigned long mask = (1UL << nr);
153 return __sync_fetch_and_and(addr, ~mask) & mask;
156 int bnx2x_cmpxchg(volatile int *addr, int old, int new)
158 return __sync_val_compare_and_swap(addr, old, new);
162 bnx2x_dma_alloc(struct bnx2x_softc *sc, size_t size, struct bnx2x_dma *dma,
163 const char *msg, uint32_t align)
165 char mz_name[RTE_MEMZONE_NAMESIZE];
166 const struct rte_memzone *z;
170 snprintf(mz_name, sizeof(mz_name), "bnx2x%d_%s_%" PRIx64, SC_ABS_FUNC(sc), msg,
171 rte_get_timer_cycles());
173 snprintf(mz_name, sizeof(mz_name), "bnx2x%d_%s_%" PRIx64, sc->pcie_device, msg,
174 rte_get_timer_cycles());
176 /* Caller must take care that strlen(mz_name) < RTE_MEMZONE_NAMESIZE */
177 z = rte_memzone_reserve_aligned(mz_name, (uint64_t)size,
179 RTE_MEMZONE_IOVA_CONTIG, align);
181 PMD_DRV_LOG(ERR, sc, "DMA alloc failed for %s", msg);
184 dma->paddr = (uint64_t) z->iova;
185 dma->vaddr = z->addr;
187 PMD_DRV_LOG(DEBUG, sc,
188 "%s: virt=%p phys=%" PRIx64, msg, dma->vaddr, dma->paddr);
193 static int bnx2x_acquire_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
195 uint32_t lock_status;
196 uint32_t resource_bit = (1 << resource);
197 int func = SC_FUNC(sc);
198 uint32_t hw_lock_control_reg;
201 PMD_INIT_FUNC_TRACE(sc);
203 /* validate the resource is within range */
204 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
205 PMD_DRV_LOG(NOTICE, sc,
206 "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
212 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
214 hw_lock_control_reg =
215 (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
218 /* validate the resource is not already taken */
219 lock_status = REG_RD(sc, hw_lock_control_reg);
220 if (lock_status & resource_bit) {
221 PMD_DRV_LOG(NOTICE, sc,
222 "resource in use (status 0x%x bit 0x%x)",
223 lock_status, resource_bit);
227 /* try every 5ms for 5 seconds */
228 for (cnt = 0; cnt < 1000; cnt++) {
229 REG_WR(sc, (hw_lock_control_reg + 4), resource_bit);
230 lock_status = REG_RD(sc, hw_lock_control_reg);
231 if (lock_status & resource_bit) {
237 PMD_DRV_LOG(NOTICE, sc, "Resource lock timeout!");
241 static int bnx2x_release_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
243 uint32_t lock_status;
244 uint32_t resource_bit = (1 << resource);
245 int func = SC_FUNC(sc);
246 uint32_t hw_lock_control_reg;
248 PMD_INIT_FUNC_TRACE(sc);
250 /* validate the resource is within range */
251 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
252 PMD_DRV_LOG(NOTICE, sc,
253 "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
259 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
261 hw_lock_control_reg =
262 (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
265 /* validate the resource is currently taken */
266 lock_status = REG_RD(sc, hw_lock_control_reg);
267 if (!(lock_status & resource_bit)) {
268 PMD_DRV_LOG(NOTICE, sc,
269 "resource not in use (status 0x%x bit 0x%x)",
270 lock_status, resource_bit);
274 REG_WR(sc, hw_lock_control_reg, resource_bit);
278 /* copy command into DMAE command memory and set DMAE command Go */
279 void bnx2x_post_dmae(struct bnx2x_softc *sc, struct dmae_command *dmae, int idx)
284 cmd_offset = (DMAE_REG_CMD_MEM + (sizeof(struct dmae_command) * idx));
285 for (i = 0; i < ((sizeof(struct dmae_command) / 4)); i++) {
286 REG_WR(sc, (cmd_offset + (i * 4)), *(((uint32_t *) dmae) + i));
289 REG_WR(sc, dmae_reg_go_c[idx], 1);
292 uint32_t bnx2x_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type)
294 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
295 DMAE_COMMAND_C_TYPE_ENABLE);
298 uint32_t bnx2x_dmae_opcode_clr_src_reset(uint32_t opcode)
300 return opcode & ~DMAE_COMMAND_SRC_RESET;
304 bnx2x_dmae_opcode(struct bnx2x_softc * sc, uint8_t src_type, uint8_t dst_type,
305 uint8_t with_comp, uint8_t comp_type)
309 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
310 (dst_type << DMAE_COMMAND_DST_SHIFT));
312 opcode |= (DMAE_COMMAND_SRC_RESET | DMAE_COMMAND_DST_RESET);
314 opcode |= (SC_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
316 opcode |= ((SC_VN(sc) << DMAE_COMMAND_E1HVN_SHIFT) |
317 (SC_VN(sc) << DMAE_COMMAND_DST_VN_SHIFT));
319 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
322 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
324 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
328 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
335 bnx2x_prep_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae,
336 uint8_t src_type, uint8_t dst_type)
338 memset(dmae, 0, sizeof(struct dmae_command));
341 dmae->opcode = bnx2x_dmae_opcode(sc, src_type, dst_type,
342 TRUE, DMAE_COMP_PCI);
344 /* fill in the completion parameters */
345 dmae->comp_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_comp));
346 dmae->comp_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_comp));
347 dmae->comp_val = DMAE_COMP_VAL;
350 /* issue a DMAE command over the init channel and wait for completion */
352 bnx2x_issue_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae)
354 uint32_t *wb_comp = BNX2X_SP(sc, wb_comp);
355 int timeout = CHIP_REV_IS_SLOW(sc) ? 400000 : 4000;
357 /* reset completion */
360 /* post the command on the channel used for initializations */
361 bnx2x_post_dmae(sc, dmae, INIT_DMAE_C(sc));
363 /* wait for completion */
366 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
368 (sc->recovery_state != BNX2X_RECOVERY_DONE &&
369 sc->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
370 PMD_DRV_LOG(INFO, sc, "DMAE timeout!");
378 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
379 PMD_DRV_LOG(INFO, sc, "DMAE PCI error!");
380 return DMAE_PCI_ERROR;
386 void bnx2x_read_dmae(struct bnx2x_softc *sc, uint32_t src_addr, uint32_t len32)
388 struct dmae_command dmae;
393 if (!sc->dmae_ready) {
394 data = BNX2X_SP(sc, wb_data[0]);
396 for (i = 0; i < len32; i++) {
397 data[i] = REG_RD(sc, (src_addr + (i * 4)));
403 /* set opcode and fixed command fields */
404 bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
406 /* fill in addresses and len */
407 dmae.src_addr_lo = (src_addr >> 2); /* GRC addr has dword resolution */
408 dmae.src_addr_hi = 0;
409 dmae.dst_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_data));
410 dmae.dst_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_data));
413 /* issue the command and wait for completion */
414 if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
415 rte_panic("DMAE failed (%d)", rc);
420 bnx2x_write_dmae(struct bnx2x_softc *sc, rte_iova_t dma_addr, uint32_t dst_addr,
423 struct dmae_command dmae;
426 if (!sc->dmae_ready) {
427 ecore_init_str_wr(sc, dst_addr, BNX2X_SP(sc, wb_data[0]), len32);
431 /* set opcode and fixed command fields */
432 bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
434 /* fill in addresses and len */
435 dmae.src_addr_lo = U64_LO(dma_addr);
436 dmae.src_addr_hi = U64_HI(dma_addr);
437 dmae.dst_addr_lo = (dst_addr >> 2); /* GRC addr has dword resolution */
438 dmae.dst_addr_hi = 0;
441 /* issue the command and wait for completion */
442 if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
443 rte_panic("DMAE failed (%d)", rc);
448 bnx2x_write_dmae_phys_len(struct bnx2x_softc *sc, rte_iova_t phys_addr,
449 uint32_t addr, uint32_t len)
451 uint32_t dmae_wr_max = DMAE_LEN32_WR_MAX(sc);
454 while (len > dmae_wr_max) {
455 bnx2x_write_dmae(sc, (phys_addr + offset), /* src DMA address */
456 (addr + offset), /* dst GRC address */
458 offset += (dmae_wr_max * 4);
462 bnx2x_write_dmae(sc, (phys_addr + offset), /* src DMA address */
463 (addr + offset), /* dst GRC address */
468 bnx2x_set_ctx_validation(struct bnx2x_softc *sc, struct eth_context *cxt,
471 /* ustorm cxt validation */
472 cxt->ustorm_ag_context.cdu_usage =
473 CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
474 CDU_REGION_NUMBER_UCM_AG,
475 ETH_CONNECTION_TYPE);
476 /* xcontext validation */
477 cxt->xstorm_ag_context.cdu_reserved =
478 CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
479 CDU_REGION_NUMBER_XCM_AG,
480 ETH_CONNECTION_TYPE);
484 bnx2x_storm_memset_hc_timeout(struct bnx2x_softc *sc, uint8_t fw_sb_id,
485 uint8_t sb_index, uint8_t ticks)
488 (BAR_CSTRORM_INTMEM +
489 CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(fw_sb_id, sb_index));
491 REG_WR8(sc, addr, ticks);
495 bnx2x_storm_memset_hc_disable(struct bnx2x_softc *sc, uint16_t fw_sb_id,
496 uint8_t sb_index, uint8_t disable)
498 uint32_t enable_flag =
499 (disable) ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
501 (BAR_CSTRORM_INTMEM +
502 CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(fw_sb_id, sb_index));
506 flags = REG_RD8(sc, addr);
507 flags &= ~HC_INDEX_DATA_HC_ENABLED;
508 flags |= enable_flag;
509 REG_WR8(sc, addr, flags);
513 bnx2x_update_coalesce_sb_index(struct bnx2x_softc *sc, uint8_t fw_sb_id,
514 uint8_t sb_index, uint8_t disable, uint16_t usec)
516 uint8_t ticks = (usec / 4);
518 bnx2x_storm_memset_hc_timeout(sc, fw_sb_id, sb_index, ticks);
520 disable = (disable) ? 1 : ((usec) ? 0 : 1);
521 bnx2x_storm_memset_hc_disable(sc, fw_sb_id, sb_index, disable);
524 uint32_t elink_cb_reg_read(struct bnx2x_softc *sc, uint32_t reg_addr)
526 return REG_RD(sc, reg_addr);
529 void elink_cb_reg_write(struct bnx2x_softc *sc, uint32_t reg_addr, uint32_t val)
531 REG_WR(sc, reg_addr, val);
535 elink_cb_event_log(__rte_unused struct bnx2x_softc *sc,
536 __rte_unused const elink_log_id_t elink_log_id, ...)
538 PMD_DRV_LOG(DEBUG, sc, "ELINK EVENT LOG (%d)", elink_log_id);
541 static int bnx2x_set_spio(struct bnx2x_softc *sc, int spio, uint32_t mode)
545 /* Only 2 SPIOs are configurable */
546 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
547 PMD_DRV_LOG(NOTICE, sc, "Invalid SPIO 0x%x", spio);
551 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
553 /* read SPIO and mask except the float bits */
554 spio_reg = (REG_RD(sc, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
557 case MISC_SPIO_OUTPUT_LOW:
558 /* clear FLOAT and set CLR */
559 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
560 spio_reg |= (spio << MISC_SPIO_CLR_POS);
563 case MISC_SPIO_OUTPUT_HIGH:
564 /* clear FLOAT and set SET */
565 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
566 spio_reg |= (spio << MISC_SPIO_SET_POS);
569 case MISC_SPIO_INPUT_HI_Z:
571 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
578 REG_WR(sc, MISC_REG_SPIO, spio_reg);
579 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
584 static int bnx2x_gpio_read(struct bnx2x_softc *sc, int gpio_num, uint8_t port)
586 /* The GPIO should be swapped if swap register is set and active */
587 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
588 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
589 int gpio_shift = gpio_num;
591 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
593 uint32_t gpio_mask = (1 << gpio_shift);
596 if (gpio_num > MISC_REGISTERS_GPIO_3) {
597 PMD_DRV_LOG(NOTICE, sc, "Invalid GPIO %d", gpio_num);
601 /* read GPIO value */
602 gpio_reg = REG_RD(sc, MISC_REG_GPIO);
604 /* get the requested pin value */
605 return ((gpio_reg & gpio_mask) == gpio_mask) ? 1 : 0;
609 bnx2x_gpio_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode, uint8_t port)
611 /* The GPIO should be swapped if swap register is set and active */
612 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
613 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
614 int gpio_shift = gpio_num;
616 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
618 uint32_t gpio_mask = (1 << gpio_shift);
621 if (gpio_num > MISC_REGISTERS_GPIO_3) {
622 PMD_DRV_LOG(NOTICE, sc, "Invalid GPIO %d", gpio_num);
626 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
628 /* read GPIO and mask except the float bits */
629 gpio_reg = (REG_RD(sc, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
632 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
633 /* clear FLOAT and set CLR */
634 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
635 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
638 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
639 /* clear FLOAT and set SET */
640 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
641 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
644 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
646 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
653 REG_WR(sc, MISC_REG_GPIO, gpio_reg);
654 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
660 bnx2x_gpio_mult_write(struct bnx2x_softc *sc, uint8_t pins, uint32_t mode)
664 /* any port swapping should be handled by caller */
666 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
668 /* read GPIO and mask except the float bits */
669 gpio_reg = REG_RD(sc, MISC_REG_GPIO);
670 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
671 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
672 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
675 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
677 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
680 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
682 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
685 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
687 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
691 PMD_DRV_LOG(NOTICE, sc,
692 "Invalid GPIO mode assignment %d", mode);
693 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
697 REG_WR(sc, MISC_REG_GPIO, gpio_reg);
698 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
704 bnx2x_gpio_int_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode,
707 /* The GPIO should be swapped if swap register is set and active */
708 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
709 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
710 int gpio_shift = gpio_num;
712 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
714 uint32_t gpio_mask = (1 << gpio_shift);
717 if (gpio_num > MISC_REGISTERS_GPIO_3) {
718 PMD_DRV_LOG(NOTICE, sc, "Invalid GPIO %d", gpio_num);
722 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
725 gpio_reg = REG_RD(sc, MISC_REG_GPIO_INT);
728 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
729 /* clear SET and set CLR */
730 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
731 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
734 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
735 /* clear CLR and set SET */
736 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
737 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
744 REG_WR(sc, MISC_REG_GPIO_INT, gpio_reg);
745 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
751 elink_cb_gpio_read(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t port)
753 return bnx2x_gpio_read(sc, gpio_num, port);
756 uint8_t elink_cb_gpio_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode, /* 0=low 1=high */
759 return bnx2x_gpio_write(sc, gpio_num, mode, port);
763 elink_cb_gpio_mult_write(struct bnx2x_softc * sc, uint8_t pins,
764 uint8_t mode /* 0=low 1=high */ )
766 return bnx2x_gpio_mult_write(sc, pins, mode);
769 uint8_t elink_cb_gpio_int_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode, /* 0=low 1=high */
772 return bnx2x_gpio_int_write(sc, gpio_num, mode, port);
775 void elink_cb_notify_link_changed(struct bnx2x_softc *sc)
777 REG_WR(sc, (MISC_REG_AEU_GENERAL_ATTN_12 +
778 (SC_FUNC(sc) * sizeof(uint32_t))), 1);
781 /* send the MCP a request, block until there is a reply */
783 elink_cb_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
785 int mb_idx = SC_FW_MB_IDX(sc);
789 uint8_t delay = CHIP_REV_IS_SLOW(sc) ? 100 : 10;
792 SHMEM_WR(sc, func_mb[mb_idx].drv_mb_param, param);
793 SHMEM_WR(sc, func_mb[mb_idx].drv_mb_header, (command | seq));
795 PMD_DRV_LOG(DEBUG, sc,
796 "wrote command 0x%08x to FW MB param 0x%08x",
797 (command | seq), param);
799 /* Let the FW do it's magic. GIve it up to 5 seconds... */
802 rc = SHMEM_RD(sc, func_mb[mb_idx].fw_mb_header);
803 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
805 /* is this a reply to our command? */
806 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) {
807 rc &= FW_MSG_CODE_MASK;
810 PMD_DRV_LOG(NOTICE, sc, "FW failed to respond!");
818 bnx2x_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
820 return elink_cb_fw_command(sc, command, param);
824 __storm_memset_dma_mapping(struct bnx2x_softc *sc, uint32_t addr,
827 REG_WR(sc, addr, U64_LO(mapping));
828 REG_WR(sc, (addr + 4), U64_HI(mapping));
832 storm_memset_spq_addr(struct bnx2x_softc *sc, rte_iova_t mapping,
835 uint32_t addr = (XSEM_REG_FAST_MEMORY +
836 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid));
837 __storm_memset_dma_mapping(sc, addr, mapping);
841 storm_memset_vf_to_pf(struct bnx2x_softc *sc, uint16_t abs_fid, uint16_t pf_id)
843 REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid)),
845 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid)),
847 REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid)),
849 REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid)),
854 storm_memset_func_en(struct bnx2x_softc *sc, uint16_t abs_fid, uint8_t enable)
856 REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid)),
858 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid)),
860 REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid)),
862 REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid)),
867 storm_memset_eq_data(struct bnx2x_softc *sc, struct event_ring_data *eq_data,
873 addr = (BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid));
874 size = sizeof(struct event_ring_data);
875 ecore_storm_memset_struct(sc, addr, size, (uint32_t *) eq_data);
879 storm_memset_eq_prod(struct bnx2x_softc *sc, uint16_t eq_prod, uint16_t pfid)
881 uint32_t addr = (BAR_CSTRORM_INTMEM +
882 CSTORM_EVENT_RING_PROD_OFFSET(pfid));
883 REG_WR16(sc, addr, eq_prod);
887 * Post a slowpath command.
889 * A slowpath command is used to propagate a configuration change through
890 * the controller in a controlled manner, allowing each STORM processor and
891 * other H/W blocks to phase in the change. The commands sent on the
892 * slowpath are referred to as ramrods. Depending on the ramrod used the
893 * completion of the ramrod will occur in different ways. Here's a
894 * breakdown of ramrods and how they complete:
896 * RAMROD_CMD_ID_ETH_PORT_SETUP
897 * Used to setup the leading connection on a port. Completes on the
898 * Receive Completion Queue (RCQ) of that port (typically fp[0]).
900 * RAMROD_CMD_ID_ETH_CLIENT_SETUP
901 * Used to setup an additional connection on a port. Completes on the
902 * RCQ of the multi-queue/RSS connection being initialized.
904 * RAMROD_CMD_ID_ETH_STAT_QUERY
905 * Used to force the storm processors to update the statistics database
906 * in host memory. This ramrod is send on the leading connection CID and
907 * completes as an index increment of the CSTORM on the default status
910 * RAMROD_CMD_ID_ETH_UPDATE
911 * Used to update the state of the leading connection, usually to udpate
912 * the RSS indirection table. Completes on the RCQ of the leading
913 * connection. (Not currently used under FreeBSD until OS support becomes
916 * RAMROD_CMD_ID_ETH_HALT
917 * Used when tearing down a connection prior to driver unload. Completes
918 * on the RCQ of the multi-queue/RSS connection being torn down. Don't
919 * use this on the leading connection.
921 * RAMROD_CMD_ID_ETH_SET_MAC
922 * Sets the Unicast/Broadcast/Multicast used by the port. Completes on
923 * the RCQ of the leading connection.
925 * RAMROD_CMD_ID_ETH_CFC_DEL
926 * Used when tearing down a conneciton prior to driver unload. Completes
927 * on the RCQ of the leading connection (since the current connection
928 * has been completely removed from controller memory).
930 * RAMROD_CMD_ID_ETH_PORT_DEL
931 * Used to tear down the leading connection prior to driver unload,
932 * typically fp[0]. Completes as an index increment of the CSTORM on the
933 * default status block.
935 * RAMROD_CMD_ID_ETH_FORWARD_SETUP
936 * Used for connection offload. Completes on the RCQ of the multi-queue
937 * RSS connection that is being offloaded. (Not currently used under
940 * There can only be one command pending per function.
943 * 0 = Success, !0 = Failure.
946 /* must be called under the spq lock */
947 static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x_softc *sc)
949 struct eth_spe *next_spe = sc->spq_prod_bd;
951 if (sc->spq_prod_bd == sc->spq_last_bd) {
952 /* wrap back to the first eth_spq */
953 sc->spq_prod_bd = sc->spq;
954 sc->spq_prod_idx = 0;
963 /* must be called under the spq lock */
964 static void bnx2x_sp_prod_update(struct bnx2x_softc *sc)
966 int func = SC_FUNC(sc);
969 * Make sure that BD data is updated before writing the producer.
970 * BD data is written to the memory, the producer is read from the
971 * memory, thus we need a full memory barrier to ensure the ordering.
975 REG_WR16(sc, (BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func)),
982 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
984 * @cmd: command to check
985 * @cmd_type: command type
987 static int bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
989 if ((cmd_type == NONE_CONNECTION_TYPE) ||
990 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
991 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
992 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
993 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
994 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
995 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) {
1003 * bnx2x_sp_post - place a single command on an SP ring
1005 * @sc: driver handle
1006 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
1007 * @cid: SW CID the command is related to
1008 * @data_hi: command private data address (high 32 bits)
1009 * @data_lo: command private data address (low 32 bits)
1010 * @cmd_type: command type (e.g. NONE, ETH)
1012 * SP data is handled as if it's always an address pair, thus data fields are
1013 * not swapped to little endian in upper functions. Instead this function swaps
1014 * data as if it's two uint32 fields.
1017 bnx2x_sp_post(struct bnx2x_softc *sc, int command, int cid, uint32_t data_hi,
1018 uint32_t data_lo, int cmd_type)
1020 struct eth_spe *spe;
1024 common = bnx2x_is_contextless_ramrod(command, cmd_type);
1027 if (!atomic_load_acq_long(&sc->eq_spq_left)) {
1028 PMD_DRV_LOG(INFO, sc, "EQ ring is full!");
1032 if (!atomic_load_acq_long(&sc->cq_spq_left)) {
1033 PMD_DRV_LOG(INFO, sc, "SPQ ring is full!");
1038 spe = bnx2x_sp_get_next(sc);
1040 /* CID needs port number to be encoded int it */
1041 spe->hdr.conn_and_cmd_data =
1042 htole32((command << SPE_HDR_CMD_ID_SHIFT) | HW_CID(sc, cid));
1044 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
1046 /* TBD: Check if it works for VFs */
1047 type |= ((SC_FUNC(sc) << SPE_HDR_FUNCTION_ID_SHIFT) &
1048 SPE_HDR_FUNCTION_ID);
1050 spe->hdr.type = htole16(type);
1052 spe->data.update_data_addr.hi = htole32(data_hi);
1053 spe->data.update_data_addr.lo = htole32(data_lo);
1056 * It's ok if the actual decrement is issued towards the memory
1057 * somewhere between the lock and unlock. Thus no more explict
1058 * memory barrier is needed.
1061 atomic_subtract_acq_long(&sc->eq_spq_left, 1);
1063 atomic_subtract_acq_long(&sc->cq_spq_left, 1);
1066 PMD_DRV_LOG(DEBUG, sc,
1067 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x"
1068 "data (%x:%x) type(0x%x) left (CQ, EQ) (%lx,%lx)",
1070 (uint32_t) U64_HI(sc->spq_dma.paddr),
1071 (uint32_t) (U64_LO(sc->spq_dma.paddr) +
1072 (uint8_t *) sc->spq_prod_bd -
1073 (uint8_t *) sc->spq), command, common,
1074 HW_CID(sc, cid), data_hi, data_lo, type,
1075 atomic_load_acq_long(&sc->cq_spq_left),
1076 atomic_load_acq_long(&sc->eq_spq_left));
1078 bnx2x_sp_prod_update(sc);
1083 static void bnx2x_drv_pulse(struct bnx2x_softc *sc)
1085 SHMEM_WR(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb,
1086 sc->fw_drv_pulse_wr_seq);
1089 static int bnx2x_tx_queue_has_work(const struct bnx2x_fastpath *fp)
1092 struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1094 if (unlikely(!txq)) {
1095 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1099 mb(); /* status block fields can change */
1100 hw_cons = le16toh(*fp->tx_cons_sb);
1101 return hw_cons != txq->tx_pkt_head;
1104 static uint8_t bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
1106 /* expand this for multi-cos if ever supported */
1107 return bnx2x_tx_queue_has_work(fp);
1110 static int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
1112 uint16_t rx_cq_cons_sb;
1113 struct bnx2x_rx_queue *rxq;
1114 rxq = fp->sc->rx_queues[fp->index];
1115 if (unlikely(!rxq)) {
1116 PMD_RX_LOG(ERR, "ERROR: RX queue is NULL");
1120 mb(); /* status block fields can change */
1121 rx_cq_cons_sb = le16toh(*fp->rx_cq_cons_sb);
1122 if (unlikely((rx_cq_cons_sb & MAX_RCQ_ENTRIES(rxq)) ==
1123 MAX_RCQ_ENTRIES(rxq)))
1125 return rxq->rx_cq_head != rx_cq_cons_sb;
1129 bnx2x_sp_event(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
1130 union eth_rx_cqe *rr_cqe)
1132 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1133 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1134 enum ecore_queue_cmd drv_cmd = ECORE_Q_CMD_MAX;
1135 struct ecore_queue_sp_obj *q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
1137 PMD_DRV_LOG(DEBUG, sc,
1138 "fp=%d cid=%d got ramrod #%d state is %x type is %d",
1139 fp->index, cid, command, sc->state,
1140 rr_cqe->ramrod_cqe.ramrod_type);
1143 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1144 PMD_DRV_LOG(DEBUG, sc, "got UPDATE ramrod. CID %d", cid);
1145 drv_cmd = ECORE_Q_CMD_UPDATE;
1148 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1149 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] setup ramrod", cid);
1150 drv_cmd = ECORE_Q_CMD_SETUP;
1153 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1154 PMD_DRV_LOG(DEBUG, sc,
1155 "got MULTI[%d] tx-only setup ramrod", cid);
1156 drv_cmd = ECORE_Q_CMD_SETUP_TX_ONLY;
1159 case (RAMROD_CMD_ID_ETH_HALT):
1160 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] halt ramrod", cid);
1161 drv_cmd = ECORE_Q_CMD_HALT;
1164 case (RAMROD_CMD_ID_ETH_TERMINATE):
1165 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] teminate ramrod", cid);
1166 drv_cmd = ECORE_Q_CMD_TERMINATE;
1169 case (RAMROD_CMD_ID_ETH_EMPTY):
1170 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] empty ramrod", cid);
1171 drv_cmd = ECORE_Q_CMD_EMPTY;
1175 PMD_DRV_LOG(DEBUG, sc,
1176 "ERROR: unexpected MC reply (%d)"
1177 "on fp[%d]", command, fp->index);
1181 if ((drv_cmd != ECORE_Q_CMD_MAX) &&
1182 q_obj->complete_cmd(sc, q_obj, drv_cmd)) {
1184 * q_obj->complete_cmd() failure means that this was
1185 * an unexpected completion.
1187 * In this case we don't want to increase the sc->spq_left
1188 * because apparently we haven't sent this command the first
1191 // rte_panic("Unexpected SP completion");
1195 atomic_add_acq_long(&sc->cq_spq_left, 1);
1197 PMD_DRV_LOG(DEBUG, sc, "sc->cq_spq_left 0x%lx",
1198 atomic_load_acq_long(&sc->cq_spq_left));
1201 static uint8_t bnx2x_rxeof(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
1203 struct bnx2x_rx_queue *rxq;
1204 uint16_t bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
1205 uint16_t hw_cq_cons, sw_cq_cons, sw_cq_prod;
1207 rxq = sc->rx_queues[fp->index];
1209 PMD_RX_LOG(ERR, "RX queue %d is NULL", fp->index);
1213 /* CQ "next element" is of the size of the regular element */
1214 hw_cq_cons = le16toh(*fp->rx_cq_cons_sb);
1215 if (unlikely((hw_cq_cons & USABLE_RCQ_ENTRIES_PER_PAGE) ==
1216 USABLE_RCQ_ENTRIES_PER_PAGE)) {
1220 bd_cons = rxq->rx_bd_head;
1221 bd_prod = rxq->rx_bd_tail;
1222 bd_prod_fw = bd_prod;
1223 sw_cq_cons = rxq->rx_cq_head;
1224 sw_cq_prod = rxq->rx_cq_tail;
1227 * Memory barrier necessary as speculative reads of the rx
1228 * buffer can be ahead of the index in the status block
1232 while (sw_cq_cons != hw_cq_cons) {
1233 union eth_rx_cqe *cqe;
1234 struct eth_fast_path_rx_cqe *cqe_fp;
1235 uint8_t cqe_fp_flags;
1236 enum eth_rx_cqe_type cqe_fp_type;
1238 comp_ring_cons = RCQ_ENTRY(sw_cq_cons, rxq);
1239 bd_prod = RX_BD(bd_prod, rxq);
1240 bd_cons = RX_BD(bd_cons, rxq);
1242 cqe = &rxq->cq_ring[comp_ring_cons];
1243 cqe_fp = &cqe->fast_path_cqe;
1244 cqe_fp_flags = cqe_fp->type_error_flags;
1245 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
1247 /* is this a slowpath msg? */
1248 if (CQE_TYPE_SLOW(cqe_fp_type)) {
1249 bnx2x_sp_event(sc, fp, cqe);
1253 /* is this an error packet? */
1254 if (unlikely(cqe_fp_flags &
1255 ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG)) {
1256 PMD_RX_LOG(DEBUG, "flags 0x%x rx packet %u",
1257 cqe_fp_flags, sw_cq_cons);
1261 PMD_RX_LOG(DEBUG, "Dropping fastpath called from attn poller!");
1264 bd_cons = NEXT_RX_BD(bd_cons);
1265 bd_prod = NEXT_RX_BD(bd_prod);
1266 bd_prod_fw = NEXT_RX_BD(bd_prod_fw);
1269 sw_cq_prod = NEXT_RCQ_IDX(sw_cq_prod);
1270 sw_cq_cons = NEXT_RCQ_IDX(sw_cq_cons);
1272 } /* while work to do */
1274 rxq->rx_bd_head = bd_cons;
1275 rxq->rx_bd_tail = bd_prod_fw;
1276 rxq->rx_cq_head = sw_cq_cons;
1277 rxq->rx_cq_tail = sw_cq_prod;
1279 /* Update producers */
1280 bnx2x_update_rx_prod(sc, fp, bd_prod_fw, sw_cq_prod);
1282 return sw_cq_cons != hw_cq_cons;
1286 bnx2x_free_tx_pkt(__rte_unused struct bnx2x_fastpath *fp, struct bnx2x_tx_queue *txq,
1287 uint16_t pkt_idx, uint16_t bd_idx)
1289 struct eth_tx_start_bd *tx_start_bd =
1290 &txq->tx_ring[TX_BD(bd_idx, txq)].start_bd;
1291 uint16_t nbd = rte_le_to_cpu_16(tx_start_bd->nbd);
1292 struct rte_mbuf *tx_mbuf = txq->sw_ring[TX_BD(pkt_idx, txq)];
1294 if (likely(tx_mbuf != NULL)) {
1295 rte_pktmbuf_free_seg(tx_mbuf);
1297 PMD_RX_LOG(ERR, "fp[%02d] lost mbuf %lu",
1298 fp->index, (unsigned long)TX_BD(pkt_idx, txq));
1301 txq->sw_ring[TX_BD(pkt_idx, txq)] = NULL;
1302 txq->nb_tx_avail += nbd;
1305 bd_idx = NEXT_TX_BD(bd_idx);
1310 /* processes transmit completions */
1311 uint8_t bnx2x_txeof(__rte_unused struct bnx2x_softc * sc, struct bnx2x_fastpath * fp)
1313 uint16_t bd_cons, hw_cons, sw_cons;
1314 __rte_unused uint16_t tx_bd_avail;
1316 struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1318 if (unlikely(!txq)) {
1319 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1323 bd_cons = txq->tx_bd_head;
1324 hw_cons = rte_le_to_cpu_16(*fp->tx_cons_sb);
1325 sw_cons = txq->tx_pkt_head;
1327 while (sw_cons != hw_cons) {
1328 bd_cons = bnx2x_free_tx_pkt(fp, txq, sw_cons, bd_cons);
1332 txq->tx_pkt_head = sw_cons;
1333 txq->tx_bd_head = bd_cons;
1335 tx_bd_avail = txq->nb_tx_avail;
1337 PMD_TX_LOG(DEBUG, "fp[%02d] avail=%u cons_sb=%u, "
1338 "pkt_head=%u pkt_tail=%u bd_head=%u bd_tail=%u",
1339 fp->index, tx_bd_avail, hw_cons,
1340 txq->tx_pkt_head, txq->tx_pkt_tail,
1341 txq->tx_bd_head, txq->tx_bd_tail);
1345 static void bnx2x_drain_tx_queues(struct bnx2x_softc *sc)
1347 struct bnx2x_fastpath *fp;
1350 /* wait until all TX fastpath tasks have completed */
1351 for (i = 0; i < sc->num_queues; i++) {
1356 while (bnx2x_has_tx_work(fp)) {
1357 bnx2x_txeof(sc, fp);
1361 "Timeout waiting for fp[%d] "
1362 "transmits to complete!", i);
1363 rte_panic("tx drain failure");
1377 bnx2x_del_all_macs(struct bnx2x_softc *sc, struct ecore_vlan_mac_obj *mac_obj,
1378 int mac_type, uint8_t wait_for_comp)
1380 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1383 /* wait for completion of requested */
1384 if (wait_for_comp) {
1385 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1388 /* Set the mac type of addresses we want to clear */
1389 bnx2x_set_bit(mac_type, &vlan_mac_flags);
1391 rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1393 PMD_DRV_LOG(ERR, sc, "Failed to delete MACs (%d)", rc);
1399 bnx2x_fill_accept_flags(struct bnx2x_softc *sc, uint32_t rx_mode,
1400 unsigned long *rx_accept_flags,
1401 unsigned long *tx_accept_flags)
1403 /* Clear the flags first */
1404 *rx_accept_flags = 0;
1405 *tx_accept_flags = 0;
1408 case BNX2X_RX_MODE_NONE:
1410 * 'drop all' supersedes any accept flags that may have been
1411 * passed to the function.
1415 case BNX2X_RX_MODE_NORMAL:
1416 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1417 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, rx_accept_flags);
1418 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1420 /* internal switching mode */
1421 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1422 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, tx_accept_flags);
1423 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1427 case BNX2X_RX_MODE_ALLMULTI:
1428 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1429 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1430 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1432 /* internal switching mode */
1433 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1434 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1435 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1439 case BNX2X_RX_MODE_ALLMULTI_PROMISC:
1440 case BNX2X_RX_MODE_PROMISC:
1442 * According to deffinition of SI mode, iface in promisc mode
1443 * should receive matched and unmatched (in resolution of port)
1446 bnx2x_set_bit(ECORE_ACCEPT_UNMATCHED, rx_accept_flags);
1447 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1448 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1449 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1451 /* internal switching mode */
1452 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1453 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1456 bnx2x_set_bit(ECORE_ACCEPT_ALL_UNICAST, tx_accept_flags);
1458 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1464 PMD_RX_LOG(ERR, "Unknown rx_mode (%d)", rx_mode);
1468 /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
1469 if (rx_mode != BNX2X_RX_MODE_NONE) {
1470 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, rx_accept_flags);
1471 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, tx_accept_flags);
1478 bnx2x_set_q_rx_mode(struct bnx2x_softc *sc, uint8_t cl_id,
1479 unsigned long rx_mode_flags,
1480 unsigned long rx_accept_flags,
1481 unsigned long tx_accept_flags, unsigned long ramrod_flags)
1483 struct ecore_rx_mode_ramrod_params ramrod_param;
1486 memset(&ramrod_param, 0, sizeof(ramrod_param));
1488 /* Prepare ramrod parameters */
1489 ramrod_param.cid = 0;
1490 ramrod_param.cl_id = cl_id;
1491 ramrod_param.rx_mode_obj = &sc->rx_mode_obj;
1492 ramrod_param.func_id = SC_FUNC(sc);
1494 ramrod_param.pstate = &sc->sp_state;
1495 ramrod_param.state = ECORE_FILTER_RX_MODE_PENDING;
1497 ramrod_param.rdata = BNX2X_SP(sc, rx_mode_rdata);
1498 ramrod_param.rdata_mapping =
1499 (rte_iova_t)BNX2X_SP_MAPPING(sc, rx_mode_rdata),
1500 bnx2x_set_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
1502 ramrod_param.ramrod_flags = ramrod_flags;
1503 ramrod_param.rx_mode_flags = rx_mode_flags;
1505 ramrod_param.rx_accept_flags = rx_accept_flags;
1506 ramrod_param.tx_accept_flags = tx_accept_flags;
1508 rc = ecore_config_rx_mode(sc, &ramrod_param);
1510 PMD_RX_LOG(ERR, "Set rx_mode %d failed", sc->rx_mode);
1517 int bnx2x_set_storm_rx_mode(struct bnx2x_softc *sc)
1519 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
1520 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
1523 rc = bnx2x_fill_accept_flags(sc, sc->rx_mode, &rx_accept_flags,
1529 bnx2x_set_bit(RAMROD_RX, &ramrod_flags);
1530 bnx2x_set_bit(RAMROD_TX, &ramrod_flags);
1531 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1533 return bnx2x_set_q_rx_mode(sc, sc->fp[0].cl_id, rx_mode_flags,
1534 rx_accept_flags, tx_accept_flags,
1538 /* returns the "mcp load_code" according to global load_count array */
1539 static int bnx2x_nic_load_no_mcp(struct bnx2x_softc *sc)
1541 int path = SC_PATH(sc);
1542 int port = SC_PORT(sc);
1544 PMD_DRV_LOG(INFO, sc, "NO MCP - load counts[%d] %d, %d, %d",
1545 path, load_count[path][0], load_count[path][1],
1546 load_count[path][2]);
1548 load_count[path][0]++;
1549 load_count[path][1 + port]++;
1550 PMD_DRV_LOG(INFO, sc, "NO MCP - new load counts[%d] %d, %d, %d",
1551 path, load_count[path][0], load_count[path][1],
1552 load_count[path][2]);
1553 if (load_count[path][0] == 1)
1554 return FW_MSG_CODE_DRV_LOAD_COMMON;
1555 else if (load_count[path][1 + port] == 1)
1556 return FW_MSG_CODE_DRV_LOAD_PORT;
1558 return FW_MSG_CODE_DRV_LOAD_FUNCTION;
1561 /* returns the "mcp load_code" according to global load_count array */
1562 static int bnx2x_nic_unload_no_mcp(struct bnx2x_softc *sc)
1564 int port = SC_PORT(sc);
1565 int path = SC_PATH(sc);
1567 PMD_DRV_LOG(INFO, sc, "NO MCP - load counts[%d] %d, %d, %d",
1568 path, load_count[path][0], load_count[path][1],
1569 load_count[path][2]);
1570 load_count[path][0]--;
1571 load_count[path][1 + port]--;
1572 PMD_DRV_LOG(INFO, sc, "NO MCP - new load counts[%d] %d, %d, %d",
1573 path, load_count[path][0], load_count[path][1],
1574 load_count[path][2]);
1575 if (load_count[path][0] == 0) {
1576 return FW_MSG_CODE_DRV_UNLOAD_COMMON;
1577 } else if (load_count[path][1 + port] == 0) {
1578 return FW_MSG_CODE_DRV_UNLOAD_PORT;
1580 return FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
1584 /* request unload mode from the MCP: COMMON, PORT or FUNCTION */
1585 static uint32_t bnx2x_send_unload_req(struct bnx2x_softc *sc, int unload_mode)
1587 uint32_t reset_code = 0;
1589 /* Select the UNLOAD request mode */
1590 if (unload_mode == UNLOAD_NORMAL) {
1591 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1593 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1596 /* Send the request to the MCP */
1597 if (!BNX2X_NOMCP(sc)) {
1598 reset_code = bnx2x_fw_command(sc, reset_code, 0);
1600 reset_code = bnx2x_nic_unload_no_mcp(sc);
1606 /* send UNLOAD_DONE command to the MCP */
1607 static void bnx2x_send_unload_done(struct bnx2x_softc *sc, uint8_t keep_link)
1609 uint32_t reset_param =
1610 keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
1612 /* Report UNLOAD_DONE to MCP */
1613 if (!BNX2X_NOMCP(sc)) {
1614 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
1618 static int bnx2x_func_wait_started(struct bnx2x_softc *sc)
1622 if (!sc->port.pmf) {
1627 * (assumption: No Attention from MCP at this stage)
1628 * PMF probably in the middle of TX disable/enable transaction
1629 * 1. Sync IRS for default SB
1630 * 2. Sync SP queue - this guarantees us that attention handling started
1631 * 3. Wait, that TX disable/enable transaction completes
1633 * 1+2 guarantee that if DCBX attention was scheduled it already changed
1634 * pending bit of transaction from STARTED-->TX_STOPPED, if we already
1635 * received completion for the transaction the state is TX_STOPPED.
1636 * State will return to STARTED after completion of TX_STOPPED-->STARTED
1640 while (ecore_func_get_state(sc, &sc->func_obj) !=
1641 ECORE_F_STATE_STARTED && tout--) {
1645 if (ecore_func_get_state(sc, &sc->func_obj) != ECORE_F_STATE_STARTED) {
1647 * Failed to complete the transaction in a "good way"
1648 * Force both transactions with CLR bit.
1650 struct ecore_func_state_params func_params = { NULL };
1652 PMD_DRV_LOG(NOTICE, sc, "Unexpected function state! "
1653 "Forcing STARTED-->TX_STOPPED-->STARTED");
1655 func_params.f_obj = &sc->func_obj;
1656 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1658 /* STARTED-->TX_STOPPED */
1659 func_params.cmd = ECORE_F_CMD_TX_STOP;
1660 ecore_func_state_change(sc, &func_params);
1662 /* TX_STOPPED-->STARTED */
1663 func_params.cmd = ECORE_F_CMD_TX_START;
1664 return ecore_func_state_change(sc, &func_params);
1670 static int bnx2x_stop_queue(struct bnx2x_softc *sc, int index)
1672 struct bnx2x_fastpath *fp = &sc->fp[index];
1673 struct ecore_queue_state_params q_params = { NULL };
1676 PMD_DRV_LOG(DEBUG, sc, "stopping queue %d cid %d", index, fp->index);
1678 q_params.q_obj = &sc->sp_objs[fp->index].q_obj;
1679 /* We want to wait for completion in this context */
1680 bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
1682 /* Stop the primary connection: */
1684 /* ...halt the connection */
1685 q_params.cmd = ECORE_Q_CMD_HALT;
1686 rc = ecore_queue_state_change(sc, &q_params);
1691 /* ...terminate the connection */
1692 q_params.cmd = ECORE_Q_CMD_TERMINATE;
1693 memset(&q_params.params.terminate, 0,
1694 sizeof(q_params.params.terminate));
1695 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
1696 rc = ecore_queue_state_change(sc, &q_params);
1701 /* ...delete cfc entry */
1702 q_params.cmd = ECORE_Q_CMD_CFC_DEL;
1703 memset(&q_params.params.cfc_del, 0, sizeof(q_params.params.cfc_del));
1704 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
1705 return ecore_queue_state_change(sc, &q_params);
1708 /* wait for the outstanding SP commands */
1709 static uint8_t bnx2x_wait_sp_comp(struct bnx2x_softc *sc, unsigned long mask)
1712 int tout = 5000; /* wait for 5 secs tops */
1716 if (!(atomic_load_acq_long(&sc->sp_state) & mask)) {
1725 tmp = atomic_load_acq_long(&sc->sp_state);
1727 PMD_DRV_LOG(INFO, sc, "Filtering completion timed out: "
1728 "sp_state 0x%lx, mask 0x%lx", tmp, mask);
1735 static int bnx2x_func_stop(struct bnx2x_softc *sc)
1737 struct ecore_func_state_params func_params = { NULL };
1740 /* prepare parameters for function state transitions */
1741 bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1742 func_params.f_obj = &sc->func_obj;
1743 func_params.cmd = ECORE_F_CMD_STOP;
1746 * Try to stop the function the 'good way'. If it fails (in case
1747 * of a parity error during bnx2x_chip_cleanup()) and we are
1748 * not in a debug mode, perform a state transaction in order to
1749 * enable further HW_RESET transaction.
1751 rc = ecore_func_state_change(sc, &func_params);
1753 PMD_DRV_LOG(NOTICE, sc, "FUNC_STOP ramrod failed. "
1754 "Running a dry transaction");
1755 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1756 return ecore_func_state_change(sc, &func_params);
1762 static int bnx2x_reset_hw(struct bnx2x_softc *sc, uint32_t load_code)
1764 struct ecore_func_state_params func_params = { NULL };
1766 /* Prepare parameters for function state transitions */
1767 bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1769 func_params.f_obj = &sc->func_obj;
1770 func_params.cmd = ECORE_F_CMD_HW_RESET;
1772 func_params.params.hw_init.load_phase = load_code;
1774 return ecore_func_state_change(sc, &func_params);
1777 static void bnx2x_int_disable_sync(struct bnx2x_softc *sc, int disable_hw)
1780 /* prevent the HW from sending interrupts */
1781 bnx2x_int_disable(sc);
1786 bnx2x_chip_cleanup(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1788 int port = SC_PORT(sc);
1789 struct ecore_mcast_ramrod_params rparam = { NULL };
1790 uint32_t reset_code;
1793 bnx2x_drain_tx_queues(sc);
1795 /* give HW time to discard old tx messages */
1798 /* Clean all ETH MACs */
1799 rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_ETH_MAC,
1802 PMD_DRV_LOG(NOTICE, sc,
1803 "Failed to delete all ETH MACs (%d)", rc);
1806 /* Clean up UC list */
1807 rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_UC_LIST_MAC,
1810 PMD_DRV_LOG(NOTICE, sc,
1811 "Failed to delete UC MACs list (%d)", rc);
1815 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
1817 /* Set "drop all" to stop Rx */
1820 * We need to take the if_maddr_lock() here in order to prevent
1821 * a race between the completion code and this code.
1824 if (bnx2x_test_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) {
1825 bnx2x_set_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state);
1827 bnx2x_set_storm_rx_mode(sc);
1830 /* Clean up multicast configuration */
1831 rparam.mcast_obj = &sc->mcast_obj;
1832 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1834 PMD_DRV_LOG(NOTICE, sc,
1835 "Failed to send DEL MCAST command (%d)", rc);
1839 * Send the UNLOAD_REQUEST to the MCP. This will return if
1840 * this function should perform FUNCTION, PORT, or COMMON HW
1843 reset_code = bnx2x_send_unload_req(sc, unload_mode);
1846 * (assumption: No Attention from MCP at this stage)
1847 * PMF probably in the middle of TX disable/enable transaction
1849 rc = bnx2x_func_wait_started(sc);
1851 PMD_DRV_LOG(NOTICE, sc, "bnx2x_func_wait_started failed");
1855 * Close multi and leading connections
1856 * Completions for ramrods are collected in a synchronous way
1858 for (i = 0; i < sc->num_queues; i++) {
1859 if (bnx2x_stop_queue(sc, i)) {
1865 * If SP settings didn't get completed so far - something
1866 * very wrong has happen.
1868 if (!bnx2x_wait_sp_comp(sc, ~0x0UL)) {
1869 PMD_DRV_LOG(NOTICE, sc, "Common slow path ramrods got stuck!");
1874 rc = bnx2x_func_stop(sc);
1876 PMD_DRV_LOG(NOTICE, sc, "Function stop failed!");
1879 /* disable HW interrupts */
1880 bnx2x_int_disable_sync(sc, TRUE);
1882 /* Reset the chip */
1883 rc = bnx2x_reset_hw(sc, reset_code);
1885 PMD_DRV_LOG(NOTICE, sc, "Hardware reset failed");
1888 /* Report UNLOAD_DONE to MCP */
1889 bnx2x_send_unload_done(sc, keep_link);
1892 static void bnx2x_disable_close_the_gate(struct bnx2x_softc *sc)
1896 PMD_DRV_LOG(DEBUG, sc, "Disabling 'close the gates'");
1898 val = REG_RD(sc, MISC_REG_AEU_GENERAL_MASK);
1899 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
1900 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
1901 REG_WR(sc, MISC_REG_AEU_GENERAL_MASK, val);
1905 * Cleans the object that have internal lists without sending
1906 * ramrods. Should be run when interrutps are disabled.
1908 static void bnx2x_squeeze_objects(struct bnx2x_softc *sc)
1910 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1911 struct ecore_mcast_ramrod_params rparam = { NULL };
1912 struct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj;
1915 /* Cleanup MACs' object first... */
1917 /* Wait for completion of requested */
1918 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1919 /* Perform a dry cleanup */
1920 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &ramrod_flags);
1922 /* Clean ETH primary MAC */
1923 bnx2x_set_bit(ECORE_ETH_MAC, &vlan_mac_flags);
1924 rc = mac_obj->delete_all(sc, &sc->sp_objs->mac_obj, &vlan_mac_flags,
1927 PMD_DRV_LOG(NOTICE, sc, "Failed to clean ETH MACs (%d)", rc);
1930 /* Cleanup UC list */
1932 bnx2x_set_bit(ECORE_UC_LIST_MAC, &vlan_mac_flags);
1933 rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1935 PMD_DRV_LOG(NOTICE, sc,
1936 "Failed to clean UC list MACs (%d)", rc);
1939 /* Now clean mcast object... */
1941 rparam.mcast_obj = &sc->mcast_obj;
1942 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags);
1944 /* Add a DEL command... */
1945 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1947 PMD_DRV_LOG(NOTICE, sc,
1948 "Failed to send DEL MCAST command (%d)", rc);
1951 /* now wait until all pending commands are cleared */
1953 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
1956 PMD_DRV_LOG(NOTICE, sc,
1957 "Failed to clean MCAST object (%d)", rc);
1961 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
1965 /* stop the controller */
1968 bnx2x_nic_unload(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1970 uint8_t global = FALSE;
1973 PMD_DRV_LOG(DEBUG, sc, "Starting NIC unload...");
1975 /* mark driver as unloaded in shmem2 */
1976 if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
1977 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
1978 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
1979 val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
1982 if (IS_PF(sc) && sc->recovery_state != BNX2X_RECOVERY_DONE &&
1983 (sc->state == BNX2X_STATE_CLOSED || sc->state == BNX2X_STATE_ERROR)) {
1985 * We can get here if the driver has been unloaded
1986 * during parity error recovery and is either waiting for a
1987 * leader to complete or for other functions to unload and
1988 * then ifconfig down has been issued. In this case we want to
1989 * unload and let other functions to complete a recovery
1992 sc->recovery_state = BNX2X_RECOVERY_DONE;
1994 bnx2x_release_leader_lock(sc);
1997 PMD_DRV_LOG(NOTICE, sc, "Can't unload in closed or error state");
2002 * Nothing to do during unload if previous bnx2x_nic_load()
2003 * did not completed successfully - all resourses are released.
2005 if ((sc->state == BNX2X_STATE_CLOSED) || (sc->state == BNX2X_STATE_ERROR)) {
2009 sc->state = BNX2X_STATE_CLOSING_WAITING_HALT;
2012 sc->rx_mode = BNX2X_RX_MODE_NONE;
2013 bnx2x_set_rx_mode(sc);
2017 /* set ALWAYS_ALIVE bit in shmem */
2018 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2020 bnx2x_drv_pulse(sc);
2022 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2023 bnx2x_save_statistics(sc);
2026 /* wait till consumers catch up with producers in all queues */
2027 bnx2x_drain_tx_queues(sc);
2029 /* if VF indicate to PF this function is going down (PF will delete sp
2030 * elements and clear initializations
2033 bnx2x_vf_unload(sc);
2034 } else if (unload_mode != UNLOAD_RECOVERY) {
2035 /* if this is a normal/close unload need to clean up chip */
2036 bnx2x_chip_cleanup(sc, unload_mode, keep_link);
2038 /* Send the UNLOAD_REQUEST to the MCP */
2039 bnx2x_send_unload_req(sc, unload_mode);
2042 * Prevent transactions to host from the functions on the
2043 * engine that doesn't reset global blocks in case of global
2044 * attention once gloabl blocks are reset and gates are opened
2045 * (the engine which leader will perform the recovery
2048 if (!CHIP_IS_E1x(sc)) {
2049 bnx2x_pf_disable(sc);
2052 /* disable HW interrupts */
2053 bnx2x_int_disable_sync(sc, TRUE);
2055 /* Report UNLOAD_DONE to MCP */
2056 bnx2x_send_unload_done(sc, FALSE);
2060 * At this stage no more interrupts will arrive so we may safely clean
2061 * the queue'able objects here in case they failed to get cleaned so far.
2064 bnx2x_squeeze_objects(sc);
2067 /* There should be no more pending SP commands at this stage */
2076 bnx2x_free_fw_stats_mem(sc);
2078 sc->state = BNX2X_STATE_CLOSED;
2081 * Check if there are pending parity attentions. If there are - set
2082 * RECOVERY_IN_PROGRESS.
2084 if (IS_PF(sc) && bnx2x_chk_parity_attn(sc, &global, FALSE)) {
2085 bnx2x_set_reset_in_progress(sc);
2087 /* Set RESET_IS_GLOBAL if needed */
2089 bnx2x_set_reset_global(sc);
2094 * The last driver must disable a "close the gate" if there is no
2095 * parity attention or "process kill" pending.
2097 if (IS_PF(sc) && !bnx2x_clear_pf_load(sc) &&
2098 bnx2x_reset_is_done(sc, SC_PATH(sc))) {
2099 bnx2x_disable_close_the_gate(sc);
2102 PMD_DRV_LOG(DEBUG, sc, "Ended NIC unload");
2108 * Encapsulte an mbuf cluster into the tx bd chain and makes the memory
2109 * visible to the controller.
2111 * If an mbuf is submitted to this routine and cannot be given to the
2112 * controller (e.g. it has too many fragments) then the function may free
2113 * the mbuf and return to the caller.
2116 * int: Number of TX BDs used for the mbuf
2118 * Note the side effect that an mbuf may be freed if it causes a problem.
2120 int bnx2x_tx_encap(struct bnx2x_tx_queue *txq, struct rte_mbuf *m0)
2122 struct eth_tx_start_bd *tx_start_bd;
2123 uint16_t bd_prod, pkt_prod;
2124 struct bnx2x_softc *sc;
2128 bd_prod = txq->tx_bd_tail;
2129 pkt_prod = txq->tx_pkt_tail;
2131 txq->sw_ring[TX_BD(pkt_prod, txq)] = m0;
2133 tx_start_bd = &txq->tx_ring[TX_BD(bd_prod, txq)].start_bd;
2136 rte_cpu_to_le_64(rte_mbuf_data_iova(m0));
2137 tx_start_bd->nbytes = rte_cpu_to_le_16(m0->data_len);
2138 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2139 tx_start_bd->general_data =
2140 (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
2142 tx_start_bd->nbd = rte_cpu_to_le_16(2);
2144 if (m0->ol_flags & PKT_TX_VLAN_PKT) {
2145 tx_start_bd->vlan_or_ethertype =
2146 rte_cpu_to_le_16(m0->vlan_tci);
2147 tx_start_bd->bd_flags.as_bitfield |=
2148 (X_ETH_OUTBAND_VLAN <<
2149 ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT);
2152 tx_start_bd->vlan_or_ethertype =
2153 rte_cpu_to_le_16(pkt_prod);
2155 struct ether_hdr *eh =
2156 rte_pktmbuf_mtod(m0, struct ether_hdr *);
2158 tx_start_bd->vlan_or_ethertype =
2159 rte_cpu_to_le_16(rte_be_to_cpu_16(eh->ether_type));
2163 bd_prod = NEXT_TX_BD(bd_prod);
2165 struct eth_tx_parse_bd_e2 *tx_parse_bd;
2166 const struct ether_hdr *eh =
2167 rte_pktmbuf_mtod(m0, struct ether_hdr *);
2168 uint8_t mac_type = UNICAST_ADDRESS;
2171 &txq->tx_ring[TX_BD(bd_prod, txq)].parse_bd_e2;
2172 if (is_multicast_ether_addr(&eh->d_addr)) {
2173 if (is_broadcast_ether_addr(&eh->d_addr))
2174 mac_type = BROADCAST_ADDRESS;
2176 mac_type = MULTICAST_ADDRESS;
2178 tx_parse_bd->parsing_data =
2179 (mac_type << ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT);
2181 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_hi,
2182 &eh->d_addr.addr_bytes[0], 2);
2183 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_mid,
2184 &eh->d_addr.addr_bytes[2], 2);
2185 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_lo,
2186 &eh->d_addr.addr_bytes[4], 2);
2187 rte_memcpy(&tx_parse_bd->data.mac_addr.src_hi,
2188 &eh->s_addr.addr_bytes[0], 2);
2189 rte_memcpy(&tx_parse_bd->data.mac_addr.src_mid,
2190 &eh->s_addr.addr_bytes[2], 2);
2191 rte_memcpy(&tx_parse_bd->data.mac_addr.src_lo,
2192 &eh->s_addr.addr_bytes[4], 2);
2194 tx_parse_bd->data.mac_addr.dst_hi =
2195 rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_hi);
2196 tx_parse_bd->data.mac_addr.dst_mid =
2197 rte_cpu_to_be_16(tx_parse_bd->data.
2199 tx_parse_bd->data.mac_addr.dst_lo =
2200 rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_lo);
2201 tx_parse_bd->data.mac_addr.src_hi =
2202 rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_hi);
2203 tx_parse_bd->data.mac_addr.src_mid =
2204 rte_cpu_to_be_16(tx_parse_bd->data.
2206 tx_parse_bd->data.mac_addr.src_lo =
2207 rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_lo);
2210 "PBD dst %x %x %x src %x %x %x p_data %x",
2211 tx_parse_bd->data.mac_addr.dst_hi,
2212 tx_parse_bd->data.mac_addr.dst_mid,
2213 tx_parse_bd->data.mac_addr.dst_lo,
2214 tx_parse_bd->data.mac_addr.src_hi,
2215 tx_parse_bd->data.mac_addr.src_mid,
2216 tx_parse_bd->data.mac_addr.src_lo,
2217 tx_parse_bd->parsing_data);
2221 "start bd: nbytes %d flags %x vlan %x",
2222 tx_start_bd->nbytes,
2223 tx_start_bd->bd_flags.as_bitfield,
2224 tx_start_bd->vlan_or_ethertype);
2226 bd_prod = NEXT_TX_BD(bd_prod);
2229 if (TX_IDX(bd_prod) < 2)
2232 txq->nb_tx_avail -= 2;
2233 txq->tx_bd_tail = bd_prod;
2234 txq->tx_pkt_tail = pkt_prod;
2239 static uint16_t bnx2x_cid_ilt_lines(struct bnx2x_softc *sc)
2241 return L2_ILT_LINES(sc);
2244 static void bnx2x_ilt_set_info(struct bnx2x_softc *sc)
2246 struct ilt_client_info *ilt_client;
2247 struct ecore_ilt *ilt = sc->ilt;
2250 PMD_INIT_FUNC_TRACE(sc);
2252 ilt->start_line = FUNC_ILT_BASE(SC_FUNC(sc));
2255 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
2256 ilt_client->client_num = ILT_CLIENT_CDU;
2257 ilt_client->page_size = CDU_ILT_PAGE_SZ;
2258 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
2259 ilt_client->start = line;
2260 line += bnx2x_cid_ilt_lines(sc);
2262 if (CNIC_SUPPORT(sc)) {
2263 line += CNIC_ILT_LINES;
2266 ilt_client->end = (line - 1);
2269 if (QM_INIT(sc->qm_cid_count)) {
2270 ilt_client = &ilt->clients[ILT_CLIENT_QM];
2271 ilt_client->client_num = ILT_CLIENT_QM;
2272 ilt_client->page_size = QM_ILT_PAGE_SZ;
2273 ilt_client->flags = 0;
2274 ilt_client->start = line;
2276 /* 4 bytes for each cid */
2277 line += DIV_ROUND_UP(sc->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
2280 ilt_client->end = (line - 1);
2283 if (CNIC_SUPPORT(sc)) {
2285 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
2286 ilt_client->client_num = ILT_CLIENT_SRC;
2287 ilt_client->page_size = SRC_ILT_PAGE_SZ;
2288 ilt_client->flags = 0;
2289 ilt_client->start = line;
2290 line += SRC_ILT_LINES;
2291 ilt_client->end = (line - 1);
2294 ilt_client = &ilt->clients[ILT_CLIENT_TM];
2295 ilt_client->client_num = ILT_CLIENT_TM;
2296 ilt_client->page_size = TM_ILT_PAGE_SZ;
2297 ilt_client->flags = 0;
2298 ilt_client->start = line;
2299 line += TM_ILT_LINES;
2300 ilt_client->end = (line - 1);
2303 assert((line <= ILT_MAX_LINES));
2306 static void bnx2x_set_fp_rx_buf_size(struct bnx2x_softc *sc)
2310 for (i = 0; i < sc->num_queues; i++) {
2311 /* get the Rx buffer size for RX frames */
2312 sc->fp[i].rx_buf_size =
2313 (IP_HEADER_ALIGNMENT_PADDING + ETH_OVERHEAD + sc->mtu);
2317 int bnx2x_alloc_ilt_mem(struct bnx2x_softc *sc)
2320 sc->ilt = rte_malloc("", sizeof(struct ecore_ilt), RTE_CACHE_LINE_SIZE);
2322 return sc->ilt == NULL;
2325 static int bnx2x_alloc_ilt_lines_mem(struct bnx2x_softc *sc)
2327 sc->ilt->lines = rte_calloc("",
2328 sizeof(struct ilt_line), ILT_MAX_LINES,
2329 RTE_CACHE_LINE_SIZE);
2330 return sc->ilt->lines == NULL;
2333 void bnx2x_free_ilt_mem(struct bnx2x_softc *sc)
2339 static void bnx2x_free_ilt_lines_mem(struct bnx2x_softc *sc)
2341 if (sc->ilt->lines != NULL) {
2342 rte_free(sc->ilt->lines);
2343 sc->ilt->lines = NULL;
2347 static void bnx2x_free_mem(struct bnx2x_softc *sc)
2351 for (i = 0; i < L2_ILT_LINES(sc); i++) {
2352 sc->context[i].vcxt = NULL;
2353 sc->context[i].size = 0;
2356 ecore_ilt_mem_op(sc, ILT_MEMOP_FREE);
2358 bnx2x_free_ilt_lines_mem(sc);
2361 static int bnx2x_alloc_mem(struct bnx2x_softc *sc)
2366 char cdu_name[RTE_MEMZONE_NAMESIZE];
2369 * Allocate memory for CDU context:
2370 * This memory is allocated separately and not in the generic ILT
2371 * functions because CDU differs in few aspects:
2372 * 1. There can be multiple entities allocating memory for context -
2373 * regular L2, CNIC, and SRIOV drivers. Each separately controls
2374 * its own ILT lines.
2375 * 2. Since CDU page-size is not a single 4KB page (which is the case
2376 * for the other ILT clients), to be efficient we want to support
2377 * allocation of sub-page-size in the last entry.
2378 * 3. Context pointers are used by the driver to pass to FW / update
2379 * the context (for the other ILT clients the pointers are used just to
2380 * free the memory during unload).
2382 context_size = (sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(sc));
2383 for (i = 0, allocated = 0; allocated < context_size; i++) {
2384 sc->context[i].size = min(CDU_ILT_PAGE_SZ,
2385 (context_size - allocated));
2387 snprintf(cdu_name, sizeof(cdu_name), "cdu_%d", i);
2388 if (bnx2x_dma_alloc(sc, sc->context[i].size,
2389 &sc->context[i].vcxt_dma,
2390 cdu_name, BNX2X_PAGE_SIZE) != 0) {
2395 sc->context[i].vcxt =
2396 (union cdu_context *)sc->context[i].vcxt_dma.vaddr;
2398 allocated += sc->context[i].size;
2401 bnx2x_alloc_ilt_lines_mem(sc);
2403 if (ecore_ilt_mem_op(sc, ILT_MEMOP_ALLOC)) {
2404 PMD_DRV_LOG(NOTICE, sc, "ecore_ilt_mem_op ILT_MEMOP_ALLOC failed");
2412 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc)
2414 sc->fw_stats_num = 0;
2416 sc->fw_stats_req_size = 0;
2417 sc->fw_stats_req = NULL;
2418 sc->fw_stats_req_mapping = 0;
2420 sc->fw_stats_data_size = 0;
2421 sc->fw_stats_data = NULL;
2422 sc->fw_stats_data_mapping = 0;
2425 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc)
2427 uint8_t num_queue_stats;
2428 int num_groups, vf_headroom = 0;
2430 /* number of queues for statistics is number of eth queues */
2431 num_queue_stats = BNX2X_NUM_ETH_QUEUES(sc);
2434 * Total number of FW statistics requests =
2435 * 1 for port stats + 1 for PF stats + num of queues
2437 sc->fw_stats_num = (2 + num_queue_stats);
2440 * Request is built from stats_query_header and an array of
2441 * stats_query_cmd_group each of which contains STATS_QUERY_CMD_COUNT
2442 * rules. The real number or requests is configured in the
2443 * stats_query_header.
2445 num_groups = (sc->fw_stats_num + vf_headroom) / STATS_QUERY_CMD_COUNT;
2446 if ((sc->fw_stats_num + vf_headroom) % STATS_QUERY_CMD_COUNT)
2449 sc->fw_stats_req_size =
2450 (sizeof(struct stats_query_header) +
2451 (num_groups * sizeof(struct stats_query_cmd_group)));
2454 * Data for statistics requests + stats_counter.
2455 * stats_counter holds per-STORM counters that are incremented when
2456 * STORM has finished with the current request. Memory for FCoE
2457 * offloaded statistics are counted anyway, even if they will not be sent.
2458 * VF stats are not accounted for here as the data of VF stats is stored
2459 * in memory allocated by the VF, not here.
2461 sc->fw_stats_data_size =
2462 (sizeof(struct stats_counter) +
2463 sizeof(struct per_port_stats) + sizeof(struct per_pf_stats) +
2464 /* sizeof(struct fcoe_statistics_params) + */
2465 (sizeof(struct per_queue_stats) * num_queue_stats));
2467 if (bnx2x_dma_alloc(sc, (sc->fw_stats_req_size + sc->fw_stats_data_size),
2468 &sc->fw_stats_dma, "fw_stats",
2469 RTE_CACHE_LINE_SIZE) != 0) {
2470 bnx2x_free_fw_stats_mem(sc);
2474 /* set up the shortcuts */
2476 sc->fw_stats_req = (struct bnx2x_fw_stats_req *)sc->fw_stats_dma.vaddr;
2477 sc->fw_stats_req_mapping = sc->fw_stats_dma.paddr;
2480 (struct bnx2x_fw_stats_data *)((uint8_t *) sc->fw_stats_dma.vaddr +
2481 sc->fw_stats_req_size);
2482 sc->fw_stats_data_mapping = (sc->fw_stats_dma.paddr +
2483 sc->fw_stats_req_size);
2490 * 0-7 - Engine0 load counter.
2491 * 8-15 - Engine1 load counter.
2492 * 16 - Engine0 RESET_IN_PROGRESS bit.
2493 * 17 - Engine1 RESET_IN_PROGRESS bit.
2494 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active
2495 * function on the engine
2496 * 19 - Engine1 ONE_IS_LOADED.
2497 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
2498 * leader to complete (check for both RESET_IN_PROGRESS bits and not
2499 * for just the one belonging to its engine).
2501 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
2502 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
2503 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
2504 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
2505 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
2506 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
2507 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
2508 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
2510 /* set the GLOBAL_RESET bit, should be run under rtnl lock */
2511 static void bnx2x_set_reset_global(struct bnx2x_softc *sc)
2514 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2515 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2516 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
2517 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2520 /* clear the GLOBAL_RESET bit, should be run under rtnl lock */
2521 static void bnx2x_clear_reset_global(struct bnx2x_softc *sc)
2524 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2525 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2526 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
2527 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2530 /* checks the GLOBAL_RESET bit, should be run under rtnl lock */
2531 static uint8_t bnx2x_reset_is_global(struct bnx2x_softc *sc)
2533 return REG_RD(sc, BNX2X_RECOVERY_GLOB_REG) & BNX2X_GLOBAL_RESET_BIT;
2536 /* clear RESET_IN_PROGRESS bit for the engine, should be run under rtnl lock */
2537 static void bnx2x_set_reset_done(struct bnx2x_softc *sc)
2540 uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2541 BNX2X_PATH0_RST_IN_PROG_BIT;
2543 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2545 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2548 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2550 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2553 /* set RESET_IN_PROGRESS for the engine, should be run under rtnl lock */
2554 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc)
2557 uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2558 BNX2X_PATH0_RST_IN_PROG_BIT;
2560 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2562 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2565 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2567 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2570 /* check RESET_IN_PROGRESS bit for an engine, should be run under rtnl lock */
2571 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine)
2573 uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2574 uint32_t bit = engine ? BNX2X_PATH1_RST_IN_PROG_BIT :
2575 BNX2X_PATH0_RST_IN_PROG_BIT;
2577 /* return false if bit is set */
2578 return (val & bit) ? FALSE : TRUE;
2581 /* get the load status for an engine, should be run under rtnl lock */
2582 static uint8_t bnx2x_get_load_status(struct bnx2x_softc *sc, int engine)
2584 uint32_t mask = engine ? BNX2X_PATH1_LOAD_CNT_MASK :
2585 BNX2X_PATH0_LOAD_CNT_MASK;
2586 uint32_t shift = engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2587 BNX2X_PATH0_LOAD_CNT_SHIFT;
2588 uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2590 val = ((val & mask) >> shift);
2595 /* set pf load mark */
2596 static void bnx2x_set_pf_load(struct bnx2x_softc *sc)
2600 uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2601 BNX2X_PATH0_LOAD_CNT_MASK;
2602 uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2603 BNX2X_PATH0_LOAD_CNT_SHIFT;
2605 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2607 PMD_INIT_FUNC_TRACE(sc);
2609 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2611 /* get the current counter value */
2612 val1 = ((val & mask) >> shift);
2614 /* set bit of this PF */
2615 val1 |= (1 << SC_ABS_FUNC(sc));
2617 /* clear the old value */
2620 /* set the new one */
2621 val |= ((val1 << shift) & mask);
2623 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2625 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2628 /* clear pf load mark */
2629 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc)
2632 uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2633 BNX2X_PATH0_LOAD_CNT_MASK;
2634 uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2635 BNX2X_PATH0_LOAD_CNT_SHIFT;
2637 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2638 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2640 /* get the current counter value */
2641 val1 = (val & mask) >> shift;
2643 /* clear bit of that PF */
2644 val1 &= ~(1 << SC_ABS_FUNC(sc));
2646 /* clear the old value */
2649 /* set the new one */
2650 val |= ((val1 << shift) & mask);
2652 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2653 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2657 /* send load requrest to mcp and analyze response */
2658 static int bnx2x_nic_load_request(struct bnx2x_softc *sc, uint32_t * load_code)
2660 PMD_INIT_FUNC_TRACE(sc);
2664 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
2665 DRV_MSG_SEQ_NUMBER_MASK);
2667 PMD_DRV_LOG(DEBUG, sc, "initial fw_seq 0x%04x", sc->fw_seq);
2670 /* get the current FW pulse sequence */
2671 sc->fw_drv_pulse_wr_seq =
2672 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb) &
2673 DRV_PULSE_SEQ_MASK);
2675 /* set ALWAYS_ALIVE bit in shmem */
2676 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2677 bnx2x_drv_pulse(sc);
2681 (*load_code) = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
2682 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
2684 /* if the MCP fails to respond we must abort */
2685 if (!(*load_code)) {
2686 PMD_DRV_LOG(NOTICE, sc, "MCP response failure!");
2690 /* if MCP refused then must abort */
2691 if ((*load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED) {
2692 PMD_DRV_LOG(NOTICE, sc, "MCP refused load request");
2700 * Check whether another PF has already loaded FW to chip. In virtualized
2701 * environments a pf from anoth VM may have already initialized the device
2702 * including loading FW.
2704 static int bnx2x_nic_load_analyze_req(struct bnx2x_softc *sc, uint32_t load_code)
2706 uint32_t my_fw, loaded_fw;
2708 /* is another pf loaded on this engine? */
2709 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
2710 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
2711 /* build my FW version dword */
2712 my_fw = (BNX2X_5710_FW_MAJOR_VERSION +
2713 (BNX2X_5710_FW_MINOR_VERSION << 8) +
2714 (BNX2X_5710_FW_REVISION_VERSION << 16) +
2715 (BNX2X_5710_FW_ENGINEERING_VERSION << 24));
2717 /* read loaded FW from chip */
2718 loaded_fw = REG_RD(sc, XSEM_REG_PRAM);
2719 PMD_DRV_LOG(DEBUG, sc, "loaded FW 0x%08x / my FW 0x%08x",
2722 /* abort nic load if version mismatch */
2723 if (my_fw != loaded_fw) {
2724 PMD_DRV_LOG(NOTICE, sc,
2725 "FW 0x%08x already loaded (mine is 0x%08x)",
2734 /* mark PMF if applicable */
2735 static void bnx2x_nic_load_pmf(struct bnx2x_softc *sc, uint32_t load_code)
2737 uint32_t ncsi_oem_data_addr;
2739 PMD_INIT_FUNC_TRACE(sc);
2741 if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
2742 (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
2743 (load_code == FW_MSG_CODE_DRV_LOAD_PORT)) {
2745 * Barrier here for ordering between the writing to sc->port.pmf here
2746 * and reading it from the periodic task.
2754 PMD_DRV_LOG(DEBUG, sc, "pmf %d", sc->port.pmf);
2756 if (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) {
2757 if (SHMEM2_HAS(sc, ncsi_oem_data_addr)) {
2758 ncsi_oem_data_addr = SHMEM2_RD(sc, ncsi_oem_data_addr);
2759 if (ncsi_oem_data_addr) {
2761 (ncsi_oem_data_addr +
2762 offsetof(struct glob_ncsi_oem_data,
2763 driver_version)), 0);
2769 static void bnx2x_read_mf_cfg(struct bnx2x_softc *sc)
2771 int n = (CHIP_IS_MODE_4_PORT(sc) ? 2 : 1);
2775 if (BNX2X_NOMCP(sc)) {
2776 return; /* what should be the default bvalue in this case */
2780 * The formula for computing the absolute function number is...
2781 * For 2 port configuration (4 functions per port):
2782 * abs_func = 2 * vn + SC_PORT + SC_PATH
2783 * For 4 port configuration (2 functions per port):
2784 * abs_func = 4 * vn + 2 * SC_PORT + SC_PATH
2786 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
2787 abs_func = (n * (2 * vn + SC_PORT(sc)) + SC_PATH(sc));
2788 if (abs_func >= E1H_FUNC_MAX) {
2791 sc->devinfo.mf_info.mf_config[vn] =
2792 MFCFG_RD(sc, func_mf_config[abs_func].config);
2795 if (sc->devinfo.mf_info.mf_config[SC_VN(sc)] &
2796 FUNC_MF_CFG_FUNC_DISABLED) {
2797 PMD_DRV_LOG(DEBUG, sc, "mf_cfg function disabled");
2798 sc->flags |= BNX2X_MF_FUNC_DIS;
2800 PMD_DRV_LOG(DEBUG, sc, "mf_cfg function enabled");
2801 sc->flags &= ~BNX2X_MF_FUNC_DIS;
2805 /* acquire split MCP access lock register */
2806 static int bnx2x_acquire_alr(struct bnx2x_softc *sc)
2810 for (j = 0; j < 1000; j++) {
2812 REG_WR(sc, GRCBASE_MCP + 0x9c, val);
2813 val = REG_RD(sc, GRCBASE_MCP + 0x9c);
2814 if (val & (1L << 31))
2820 if (!(val & (1L << 31))) {
2821 PMD_DRV_LOG(NOTICE, sc, "Cannot acquire MCP access lock register");
2828 /* release split MCP access lock register */
2829 static void bnx2x_release_alr(struct bnx2x_softc *sc)
2831 REG_WR(sc, GRCBASE_MCP + 0x9c, 0);
2834 static void bnx2x_fan_failure(struct bnx2x_softc *sc)
2836 int port = SC_PORT(sc);
2837 uint32_t ext_phy_config;
2839 /* mark the failure */
2841 SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
2843 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2844 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
2845 SHMEM_WR(sc, dev_info.port_hw_config[port].external_phy_config,
2848 /* log the failure */
2849 PMD_DRV_LOG(INFO, sc,
2850 "Fan Failure has caused the driver to shutdown "
2851 "the card to prevent permanent damage. "
2852 "Please contact OEM Support for assistance");
2854 rte_panic("Schedule task to handle fan failure");
2857 /* this function is called upon a link interrupt */
2858 static void bnx2x_link_attn(struct bnx2x_softc *sc)
2860 uint32_t pause_enabled = 0;
2861 struct host_port_stats *pstats;
2864 /* Make sure that we are synced with the current statistics */
2865 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2867 elink_link_update(&sc->link_params, &sc->link_vars);
2869 if (sc->link_vars.link_up) {
2871 /* dropless flow control */
2872 if (sc->dropless_fc) {
2875 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
2880 (BAR_USTRORM_INTMEM +
2881 USTORM_ETH_PAUSE_ENABLED_OFFSET(SC_PORT(sc))),
2885 if (sc->link_vars.mac_type != ELINK_MAC_TYPE_EMAC) {
2886 pstats = BNX2X_SP(sc, port_stats);
2887 /* reset old mac stats */
2888 memset(&(pstats->mac_stx[0]), 0,
2889 sizeof(struct mac_stx));
2892 if (sc->state == BNX2X_STATE_OPEN) {
2893 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
2897 if (sc->link_vars.link_up && sc->link_vars.line_speed) {
2898 cmng_fns = bnx2x_get_cmng_fns_mode(sc);
2900 if (cmng_fns != CMNG_FNS_NONE) {
2901 bnx2x_cmng_fns_init(sc, FALSE, cmng_fns);
2902 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
2906 bnx2x_link_report(sc);
2909 bnx2x_link_sync_notify(sc);
2913 static void bnx2x_attn_int_asserted(struct bnx2x_softc *sc, uint32_t asserted)
2915 int port = SC_PORT(sc);
2916 uint32_t aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2917 MISC_REG_AEU_MASK_ATTN_FUNC_0;
2918 uint32_t nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2919 NIG_REG_MASK_INTERRUPT_PORT0;
2921 uint32_t nig_mask = 0;
2926 if (sc->attn_state & asserted) {
2927 PMD_DRV_LOG(ERR, sc, "IGU ERROR attn=0x%08x", asserted);
2930 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2932 aeu_mask = REG_RD(sc, aeu_addr);
2934 aeu_mask &= ~(asserted & 0x3ff);
2936 REG_WR(sc, aeu_addr, aeu_mask);
2938 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2940 sc->attn_state |= asserted;
2942 if (asserted & ATTN_HARD_WIRED_MASK) {
2943 if (asserted & ATTN_NIG_FOR_FUNC) {
2945 /* save nig interrupt mask */
2946 nig_mask = REG_RD(sc, nig_int_mask_addr);
2948 /* If nig_mask is not set, no need to call the update function */
2950 REG_WR(sc, nig_int_mask_addr, 0);
2952 bnx2x_link_attn(sc);
2955 /* handle unicore attn? */
2958 if (asserted & ATTN_SW_TIMER_4_FUNC) {
2959 PMD_DRV_LOG(DEBUG, sc, "ATTN_SW_TIMER_4_FUNC!");
2962 if (asserted & GPIO_2_FUNC) {
2963 PMD_DRV_LOG(DEBUG, sc, "GPIO_2_FUNC!");
2966 if (asserted & GPIO_3_FUNC) {
2967 PMD_DRV_LOG(DEBUG, sc, "GPIO_3_FUNC!");
2970 if (asserted & GPIO_4_FUNC) {
2971 PMD_DRV_LOG(DEBUG, sc, "GPIO_4_FUNC!");
2975 if (asserted & ATTN_GENERAL_ATTN_1) {
2976 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_1!");
2977 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
2979 if (asserted & ATTN_GENERAL_ATTN_2) {
2980 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_2!");
2981 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
2983 if (asserted & ATTN_GENERAL_ATTN_3) {
2984 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_3!");
2985 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
2988 if (asserted & ATTN_GENERAL_ATTN_4) {
2989 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_4!");
2990 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
2992 if (asserted & ATTN_GENERAL_ATTN_5) {
2993 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_5!");
2994 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
2996 if (asserted & ATTN_GENERAL_ATTN_6) {
2997 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_6!");
2998 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3003 if (sc->devinfo.int_block == INT_BLOCK_HC) {
3005 (HC_REG_COMMAND_REG + port * 32 +
3006 COMMAND_REG_ATTN_BITS_SET);
3008 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER * 8);
3011 PMD_DRV_LOG(DEBUG, sc, "about to mask 0x%08x at %s addr 0x%08x",
3013 (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
3015 REG_WR(sc, reg_addr, asserted);
3017 /* now set back the mask */
3018 if (asserted & ATTN_NIG_FOR_FUNC) {
3020 * Verify that IGU ack through BAR was written before restoring
3021 * NIG mask. This loop should exit after 2-3 iterations max.
3023 if (sc->devinfo.int_block != INT_BLOCK_HC) {
3028 REG_RD(sc, IGU_REG_ATTENTION_ACK_BITS);
3029 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0)
3030 && (++cnt < MAX_IGU_ATTN_ACK_TO));
3033 PMD_DRV_LOG(ERR, sc,
3034 "Failed to verify IGU ack on time");
3040 REG_WR(sc, nig_int_mask_addr, nig_mask);
3046 bnx2x_print_next_block(__rte_unused struct bnx2x_softc *sc, __rte_unused int idx,
3047 __rte_unused const char *blk)
3049 PMD_DRV_LOG(INFO, sc, "%s%s", idx ? ", " : "", blk);
3053 bnx2x_check_blocks_with_parity0(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3056 uint32_t cur_bit = 0;
3059 for (i = 0; sig; i++) {
3060 cur_bit = ((uint32_t) 0x1 << i);
3061 if (sig & cur_bit) {
3063 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3065 bnx2x_print_next_block(sc, par_num++,
3068 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3070 bnx2x_print_next_block(sc, par_num++,
3073 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3075 bnx2x_print_next_block(sc, par_num++,
3078 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3080 bnx2x_print_next_block(sc, par_num++,
3083 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3085 bnx2x_print_next_block(sc, par_num++,
3088 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3090 bnx2x_print_next_block(sc, par_num++,
3093 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3095 bnx2x_print_next_block(sc, par_num++,
3109 bnx2x_check_blocks_with_parity1(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3110 uint8_t * global, uint8_t print)
3113 uint32_t cur_bit = 0;
3114 for (i = 0; sig; i++) {
3115 cur_bit = ((uint32_t) 0x1 << i);
3116 if (sig & cur_bit) {
3118 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3120 bnx2x_print_next_block(sc, par_num++,
3123 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3125 bnx2x_print_next_block(sc, par_num++,
3128 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3130 bnx2x_print_next_block(sc, par_num++,
3133 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3135 bnx2x_print_next_block(sc, par_num++,
3138 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
3140 bnx2x_print_next_block(sc, par_num++,
3143 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3145 bnx2x_print_next_block(sc, par_num++,
3148 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3150 bnx2x_print_next_block(sc, par_num++,
3153 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
3155 bnx2x_print_next_block(sc, par_num++,
3158 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3160 bnx2x_print_next_block(sc, par_num++,
3164 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3166 bnx2x_print_next_block(sc, par_num++,
3169 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3171 bnx2x_print_next_block(sc, par_num++,
3174 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
3176 bnx2x_print_next_block(sc, par_num++,
3179 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3181 bnx2x_print_next_block(sc, par_num++,
3184 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3186 bnx2x_print_next_block(sc, par_num++,
3189 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3191 bnx2x_print_next_block(sc, par_num++,
3194 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
3196 bnx2x_print_next_block(sc, par_num++,
3210 bnx2x_check_blocks_with_parity2(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3213 uint32_t cur_bit = 0;
3216 for (i = 0; sig; i++) {
3217 cur_bit = ((uint32_t) 0x1 << i);
3218 if (sig & cur_bit) {
3220 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3222 bnx2x_print_next_block(sc, par_num++,
3225 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3227 bnx2x_print_next_block(sc, par_num++,
3230 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3232 bnx2x_print_next_block(sc, par_num++,
3233 "PXPPCICLOCKCLIENT");
3235 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3237 bnx2x_print_next_block(sc, par_num++,
3240 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3242 bnx2x_print_next_block(sc, par_num++,
3245 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
3247 bnx2x_print_next_block(sc, par_num++,
3250 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3252 bnx2x_print_next_block(sc, par_num++,
3255 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3257 bnx2x_print_next_block(sc, par_num++,
3271 bnx2x_check_blocks_with_parity3(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3272 uint8_t * global, uint8_t print)
3274 uint32_t cur_bit = 0;
3277 for (i = 0; sig; i++) {
3278 cur_bit = ((uint32_t) 0x1 << i);
3279 if (sig & cur_bit) {
3281 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3283 bnx2x_print_next_block(sc, par_num++,
3287 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3289 bnx2x_print_next_block(sc, par_num++,
3293 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3295 bnx2x_print_next_block(sc, par_num++,
3299 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3301 bnx2x_print_next_block(sc, par_num++,
3316 bnx2x_check_blocks_with_parity4(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3319 uint32_t cur_bit = 0;
3322 for (i = 0; sig; i++) {
3323 cur_bit = ((uint32_t) 0x1 << i);
3324 if (sig & cur_bit) {
3326 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
3328 bnx2x_print_next_block(sc, par_num++,
3331 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
3333 bnx2x_print_next_block(sc, par_num++,
3347 bnx2x_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print,
3352 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
3353 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
3354 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
3355 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
3356 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
3357 PMD_DRV_LOG(ERR, sc,
3358 "Parity error: HW block parity attention:"
3359 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x",
3360 (uint32_t) (sig[0] & HW_PRTY_ASSERT_SET_0),
3361 (uint32_t) (sig[1] & HW_PRTY_ASSERT_SET_1),
3362 (uint32_t) (sig[2] & HW_PRTY_ASSERT_SET_2),
3363 (uint32_t) (sig[3] & HW_PRTY_ASSERT_SET_3),
3364 (uint32_t) (sig[4] & HW_PRTY_ASSERT_SET_4));
3367 PMD_DRV_LOG(INFO, sc, "Parity errors detected in blocks: ");
3370 bnx2x_check_blocks_with_parity0(sc, sig[0] &
3371 HW_PRTY_ASSERT_SET_0,
3374 bnx2x_check_blocks_with_parity1(sc, sig[1] &
3375 HW_PRTY_ASSERT_SET_1,
3376 par_num, global, print);
3378 bnx2x_check_blocks_with_parity2(sc, sig[2] &
3379 HW_PRTY_ASSERT_SET_2,
3382 bnx2x_check_blocks_with_parity3(sc, sig[3] &
3383 HW_PRTY_ASSERT_SET_3,
3384 par_num, global, print);
3386 bnx2x_check_blocks_with_parity4(sc, sig[4] &
3387 HW_PRTY_ASSERT_SET_4,
3391 PMD_DRV_LOG(INFO, sc, "");
3400 bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print)
3402 struct attn_route attn = { {0} };
3403 int port = SC_PORT(sc);
3405 attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
3406 attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
3407 attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
3408 attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
3410 if (!CHIP_IS_E1x(sc))
3412 REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
3414 return bnx2x_parity_attn(sc, global, print, attn.sig);
3417 static void bnx2x_attn_int_deasserted4(struct bnx2x_softc *sc, uint32_t attn)
3421 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
3422 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
3423 PMD_DRV_LOG(INFO, sc, "ERROR: PGLUE hw attention 0x%08x", val);
3424 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
3425 PMD_DRV_LOG(INFO, sc,
3426 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR");
3427 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
3428 PMD_DRV_LOG(INFO, sc,
3429 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR");
3430 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
3431 PMD_DRV_LOG(INFO, sc,
3432 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN");
3433 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
3434 PMD_DRV_LOG(INFO, sc,
3435 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN");
3437 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
3438 PMD_DRV_LOG(INFO, sc,
3439 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN");
3441 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
3442 PMD_DRV_LOG(INFO, sc,
3443 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN");
3444 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
3445 PMD_DRV_LOG(INFO, sc,
3446 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN");
3447 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
3448 PMD_DRV_LOG(INFO, sc,
3449 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN");
3450 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
3451 PMD_DRV_LOG(INFO, sc,
3452 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW");
3455 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
3456 val = REG_RD(sc, ATC_REG_ATC_INT_STS_CLR);
3457 PMD_DRV_LOG(INFO, sc, "ERROR: ATC hw attention 0x%08x", val);
3458 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
3459 PMD_DRV_LOG(INFO, sc,
3460 "ERROR: ATC_ATC_INT_STS_REG_ADDRESS_ERROR");
3461 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
3462 PMD_DRV_LOG(INFO, sc,
3463 "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND");
3464 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
3465 PMD_DRV_LOG(INFO, sc,
3466 "ERROR: ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS");
3467 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
3468 PMD_DRV_LOG(INFO, sc,
3469 "ERROR: ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT");
3470 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
3471 PMD_DRV_LOG(INFO, sc,
3472 "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR");
3473 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
3474 PMD_DRV_LOG(INFO, sc,
3475 "ERROR: ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU");
3478 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3479 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
3480 PMD_DRV_LOG(INFO, sc,
3481 "ERROR: FATAL parity attention set4 0x%08x",
3483 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
3485 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
3489 static void bnx2x_e1h_disable(struct bnx2x_softc *sc)
3491 int port = SC_PORT(sc);
3493 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
3496 static void bnx2x_e1h_enable(struct bnx2x_softc *sc)
3498 int port = SC_PORT(sc);
3500 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3504 * called due to MCP event (on pmf):
3505 * reread new bandwidth configuration
3507 * notify others function about the change
3509 static void bnx2x_config_mf_bw(struct bnx2x_softc *sc)
3511 if (sc->link_vars.link_up) {
3512 bnx2x_cmng_fns_init(sc, TRUE, CMNG_FNS_MINMAX);
3513 bnx2x_link_sync_notify(sc);
3516 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
3519 static void bnx2x_set_mf_bw(struct bnx2x_softc *sc)
3521 bnx2x_config_mf_bw(sc);
3522 bnx2x_fw_command(sc, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3525 static void bnx2x_handle_eee_event(struct bnx2x_softc *sc)
3527 bnx2x_fw_command(sc, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3530 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3532 static void bnx2x_drv_info_ether_stat(struct bnx2x_softc *sc)
3534 struct eth_stats_info *ether_stat = &sc->sp->drv_info_to_mcp.ether_stat;
3536 strncpy(ether_stat->version, BNX2X_DRIVER_VERSION,
3537 ETH_STAT_INFO_VERSION_LEN);
3539 sc->sp_objs[0].mac_obj.get_n_elements(sc, &sc->sp_objs[0].mac_obj,
3540 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3541 ether_stat->mac_local + MAC_PAD,
3544 ether_stat->mtu_size = sc->mtu;
3546 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3547 ether_stat->promiscuous_mode = 0; // (flags & PROMISC) ? 1 : 0;
3549 ether_stat->txq_size = sc->tx_ring_size;
3550 ether_stat->rxq_size = sc->rx_ring_size;
3553 static void bnx2x_handle_drv_info_req(struct bnx2x_softc *sc)
3555 enum drv_info_opcode op_code;
3556 uint32_t drv_info_ctl = SHMEM2_RD(sc, drv_info_control);
3558 /* if drv_info version supported by MFW doesn't match - send NACK */
3559 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3560 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3564 op_code = ((drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3565 DRV_INFO_CONTROL_OP_CODE_SHIFT);
3567 memset(&sc->sp->drv_info_to_mcp, 0, sizeof(union drv_info_to_mcp));
3570 case ETH_STATS_OPCODE:
3571 bnx2x_drv_info_ether_stat(sc);
3573 case FCOE_STATS_OPCODE:
3574 case ISCSI_STATS_OPCODE:
3576 /* if op code isn't supported - send NACK */
3577 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3582 * If we got drv_info attn from MFW then these fields are defined in
3585 SHMEM2_WR(sc, drv_info_host_addr_lo,
3586 U64_LO(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3587 SHMEM2_WR(sc, drv_info_host_addr_hi,
3588 U64_HI(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3590 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3593 static void bnx2x_dcc_event(struct bnx2x_softc *sc, uint32_t dcc_event)
3595 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3597 * This is the only place besides the function initialization
3598 * where the sc->flags can change so it is done without any
3602 mf_info.mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_DISABLED) {
3603 PMD_DRV_LOG(DEBUG, sc, "mf_cfg function disabled");
3604 sc->flags |= BNX2X_MF_FUNC_DIS;
3605 bnx2x_e1h_disable(sc);
3607 PMD_DRV_LOG(DEBUG, sc, "mf_cfg function enabled");
3608 sc->flags &= ~BNX2X_MF_FUNC_DIS;
3609 bnx2x_e1h_enable(sc);
3611 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3614 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3615 bnx2x_config_mf_bw(sc);
3616 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3619 /* Report results to MCP */
3621 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_FAILURE, 0);
3623 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_OK, 0);
3626 static void bnx2x_pmf_update(struct bnx2x_softc *sc)
3628 int port = SC_PORT(sc);
3634 * We need the mb() to ensure the ordering between the writing to
3635 * sc->port.pmf here and reading it from the bnx2x_periodic_task().
3639 /* enable nig attention */
3640 val = (0xff0f | (1 << (SC_VN(sc) + 4)));
3641 if (sc->devinfo.int_block == INT_BLOCK_HC) {
3642 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, val);
3643 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, val);
3644 } else if (!CHIP_IS_E1x(sc)) {
3645 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
3646 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
3649 bnx2x_stats_handle(sc, STATS_EVENT_PMF);
3652 static int bnx2x_mc_assert(struct bnx2x_softc *sc)
3656 __rte_unused uint32_t row0, row1, row2, row3;
3660 REG_RD8(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_INDEX_OFFSET);
3662 PMD_DRV_LOG(ERR, sc, "XSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3664 /* print the asserts */
3665 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3669 BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i));
3672 BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3676 BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3680 BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3683 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3684 PMD_DRV_LOG(ERR, sc,
3685 "XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3686 i, row3, row2, row1, row0);
3695 REG_RD8(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_INDEX_OFFSET);
3697 PMD_DRV_LOG(ERR, sc, "TSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3700 /* print the asserts */
3701 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3705 BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i));
3708 BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3712 BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3716 BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3719 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3720 PMD_DRV_LOG(ERR, sc,
3721 "TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3722 i, row3, row2, row1, row0);
3731 REG_RD8(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_INDEX_OFFSET);
3733 PMD_DRV_LOG(ERR, sc, "CSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3736 /* print the asserts */
3737 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3741 BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i));
3744 BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3748 BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3752 BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3755 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3756 PMD_DRV_LOG(ERR, sc,
3757 "CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3758 i, row3, row2, row1, row0);
3767 REG_RD8(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_INDEX_OFFSET);
3769 PMD_DRV_LOG(ERR, sc, "USTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3772 /* print the asserts */
3773 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3777 BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i));
3780 BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3784 BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3788 BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3791 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3792 PMD_DRV_LOG(ERR, sc,
3793 "USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3794 i, row3, row2, row1, row0);
3804 static void bnx2x_attn_int_deasserted3(struct bnx2x_softc *sc, uint32_t attn)
3806 int func = SC_FUNC(sc);
3809 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3811 if (attn & BNX2X_PMF_LINK_ASSERT(sc)) {
3813 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
3814 bnx2x_read_mf_cfg(sc);
3815 sc->devinfo.mf_info.mf_config[SC_VN(sc)] =
3817 func_mf_config[SC_ABS_FUNC(sc)].config);
3819 SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_status);
3821 if (val & DRV_STATUS_DCC_EVENT_MASK)
3824 DRV_STATUS_DCC_EVENT_MASK));
3826 if (val & DRV_STATUS_SET_MF_BW)
3827 bnx2x_set_mf_bw(sc);
3829 if (val & DRV_STATUS_DRV_INFO_REQ)
3830 bnx2x_handle_drv_info_req(sc);
3832 if ((sc->port.pmf == 0) && (val & DRV_STATUS_PMF))
3833 bnx2x_pmf_update(sc);
3835 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
3836 bnx2x_handle_eee_event(sc);
3838 if (sc->link_vars.periodic_flags &
3839 ELINK_PERIODIC_FLAGS_LINK_EVENT) {
3840 /* sync with link */
3841 sc->link_vars.periodic_flags &=
3842 ~ELINK_PERIODIC_FLAGS_LINK_EVENT;
3844 bnx2x_link_sync_notify(sc);
3846 bnx2x_link_report(sc);
3850 * Always call it here: bnx2x_link_report() will
3851 * prevent the link indication duplication.
3853 bnx2x_link_status_update(sc);
3855 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3857 PMD_DRV_LOG(ERR, sc, "MC assert!");
3858 bnx2x_mc_assert(sc);
3859 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3860 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3861 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3862 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3863 rte_panic("MC assert!");
3865 } else if (attn & BNX2X_MCP_ASSERT) {
3867 PMD_DRV_LOG(ERR, sc, "MCP assert!");
3868 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3871 PMD_DRV_LOG(ERR, sc,
3872 "Unknown HW assert! (attn 0x%08x)", attn);
3876 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3877 PMD_DRV_LOG(ERR, sc, "LATCHED attention 0x%08x (masked)", attn);
3878 if (attn & BNX2X_GRC_TIMEOUT) {
3879 val = REG_RD(sc, MISC_REG_GRC_TIMEOUT_ATTN);
3880 PMD_DRV_LOG(ERR, sc, "GRC time-out 0x%08x", val);
3882 if (attn & BNX2X_GRC_RSV) {
3883 val = REG_RD(sc, MISC_REG_GRC_RSV_ATTN);
3884 PMD_DRV_LOG(ERR, sc, "GRC reserved 0x%08x", val);
3886 REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3890 static void bnx2x_attn_int_deasserted2(struct bnx2x_softc *sc, uint32_t attn)
3892 int port = SC_PORT(sc);
3894 uint32_t val0, mask0, val1, mask1;
3897 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3898 val = REG_RD(sc, CFC_REG_CFC_INT_STS_CLR);
3899 PMD_DRV_LOG(ERR, sc, "CFC hw attention 0x%08x", val);
3900 /* CFC error attention */
3902 PMD_DRV_LOG(ERR, sc, "FATAL error from CFC");
3906 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3907 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_0);
3908 PMD_DRV_LOG(ERR, sc, "PXP hw attention-0 0x%08x", val);
3909 /* RQ_USDMDP_FIFO_OVERFLOW */
3910 if (val & 0x18000) {
3911 PMD_DRV_LOG(ERR, sc, "FATAL error from PXP");
3914 if (!CHIP_IS_E1x(sc)) {
3915 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_1);
3916 PMD_DRV_LOG(ERR, sc, "PXP hw attention-1 0x%08x", val);
3919 #define PXP2_EOP_ERROR_BIT PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR
3920 #define AEU_PXP2_HW_INT_BIT AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT
3922 if (attn & AEU_PXP2_HW_INT_BIT) {
3923 /* CQ47854 workaround do not panic on
3924 * PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3926 if (!CHIP_IS_E1x(sc)) {
3927 mask0 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_0);
3928 val1 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_1);
3929 mask1 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_1);
3930 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_0);
3932 * If the only PXP2_EOP_ERROR_BIT is set in
3933 * STS0 and STS1 - clear it
3935 * probably we lose additional attentions between
3936 * STS0 and STS_CLR0, in this case user will not
3937 * be notified about them
3939 if (val0 & mask0 & PXP2_EOP_ERROR_BIT &&
3941 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
3943 /* print the register, since no one can restore it */
3944 PMD_DRV_LOG(ERR, sc,
3945 "PXP2_REG_PXP2_INT_STS_CLR_0 0x%08x", val0);
3948 * if PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3951 if (val0 & PXP2_EOP_ERROR_BIT) {
3952 PMD_DRV_LOG(ERR, sc, "PXP2_WR_PGLUE_EOP_ERROR");
3955 * if only PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR is
3956 * set then clear attention from PXP2 block without panic
3958 if (((val0 & mask0) == PXP2_EOP_ERROR_BIT) &&
3959 ((val1 & mask1) == 0))
3960 attn &= ~AEU_PXP2_HW_INT_BIT;
3965 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3966 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3967 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3969 val = REG_RD(sc, reg_offset);
3970 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3971 REG_WR(sc, reg_offset, val);
3973 PMD_DRV_LOG(ERR, sc,
3974 "FATAL HW block attention set2 0x%x",
3975 (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_2));
3976 rte_panic("HW block attention set2");
3980 static void bnx2x_attn_int_deasserted1(struct bnx2x_softc *sc, uint32_t attn)
3982 int port = SC_PORT(sc);
3986 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3987 val = REG_RD(sc, DORQ_REG_DORQ_INT_STS_CLR);
3988 PMD_DRV_LOG(ERR, sc, "DB hw attention 0x%08x", val);
3989 /* DORQ discard attention */
3991 PMD_DRV_LOG(ERR, sc, "FATAL error from DORQ");
3995 if (attn & HW_INTERRUT_ASSERT_SET_1) {
3996 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3997 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3999 val = REG_RD(sc, reg_offset);
4000 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4001 REG_WR(sc, reg_offset, val);
4003 PMD_DRV_LOG(ERR, sc,
4004 "FATAL HW block attention set1 0x%08x",
4005 (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_1));
4006 rte_panic("HW block attention set1");
4010 static void bnx2x_attn_int_deasserted0(struct bnx2x_softc *sc, uint32_t attn)
4012 int port = SC_PORT(sc);
4016 reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4017 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
4019 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4020 val = REG_RD(sc, reg_offset);
4021 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4022 REG_WR(sc, reg_offset, val);
4024 PMD_DRV_LOG(WARNING, sc, "SPIO5 hw attention");
4026 /* Fan failure attention */
4027 elink_hw_reset_phy(&sc->link_params);
4028 bnx2x_fan_failure(sc);
4031 if ((attn & sc->link_vars.aeu_int_mask) && sc->port.pmf) {
4032 elink_handle_module_detect_int(&sc->link_params);
4035 if (attn & HW_INTERRUT_ASSERT_SET_0) {
4036 val = REG_RD(sc, reg_offset);
4037 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4038 REG_WR(sc, reg_offset, val);
4040 rte_panic("FATAL HW block attention set0 0x%lx",
4041 (attn & HW_INTERRUT_ASSERT_SET_0));
4045 static void bnx2x_attn_int_deasserted(struct bnx2x_softc *sc, uint32_t deasserted)
4047 struct attn_route attn;
4048 struct attn_route *group_mask;
4049 int port = SC_PORT(sc);
4054 uint8_t global = FALSE;
4057 * Need to take HW lock because MCP or other port might also
4058 * try to handle this event.
4060 bnx2x_acquire_alr(sc);
4062 if (bnx2x_chk_parity_attn(sc, &global, TRUE)) {
4063 sc->recovery_state = BNX2X_RECOVERY_INIT;
4065 /* disable HW interrupts */
4066 bnx2x_int_disable(sc);
4067 bnx2x_release_alr(sc);
4071 attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
4072 attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
4073 attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
4074 attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
4075 if (!CHIP_IS_E1x(sc)) {
4077 REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
4082 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4083 if (deasserted & (1 << index)) {
4084 group_mask = &sc->attn_group[index];
4086 bnx2x_attn_int_deasserted4(sc,
4088 sig[4] & group_mask->sig[4]);
4089 bnx2x_attn_int_deasserted3(sc,
4091 sig[3] & group_mask->sig[3]);
4092 bnx2x_attn_int_deasserted1(sc,
4094 sig[1] & group_mask->sig[1]);
4095 bnx2x_attn_int_deasserted2(sc,
4097 sig[2] & group_mask->sig[2]);
4098 bnx2x_attn_int_deasserted0(sc,
4100 sig[0] & group_mask->sig[0]);
4104 bnx2x_release_alr(sc);
4106 if (sc->devinfo.int_block == INT_BLOCK_HC) {
4107 reg_addr = (HC_REG_COMMAND_REG + port * 32 +
4108 COMMAND_REG_ATTN_BITS_CLR);
4110 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER * 8);
4114 PMD_DRV_LOG(DEBUG, sc,
4115 "about to mask 0x%08x at %s addr 0x%08x", val,
4116 (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
4118 REG_WR(sc, reg_addr, val);
4120 if (~sc->attn_state & deasserted) {
4121 PMD_DRV_LOG(ERR, sc, "IGU error");
4124 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4125 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4127 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4129 aeu_mask = REG_RD(sc, reg_addr);
4131 aeu_mask |= (deasserted & 0x3ff);
4133 REG_WR(sc, reg_addr, aeu_mask);
4134 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4136 sc->attn_state &= ~deasserted;
4139 static void bnx2x_attn_int(struct bnx2x_softc *sc)
4141 /* read local copy of bits */
4142 uint32_t attn_bits = le32toh(sc->def_sb->atten_status_block.attn_bits);
4144 le32toh(sc->def_sb->atten_status_block.attn_bits_ack);
4145 uint32_t attn_state = sc->attn_state;
4147 /* look for changed bits */
4148 uint32_t asserted = attn_bits & ~attn_ack & ~attn_state;
4149 uint32_t deasserted = ~attn_bits & attn_ack & attn_state;
4151 PMD_DRV_LOG(DEBUG, sc,
4152 "attn_bits 0x%08x attn_ack 0x%08x asserted 0x%08x deasserted 0x%08x",
4153 attn_bits, attn_ack, asserted, deasserted);
4155 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) {
4156 PMD_DRV_LOG(ERR, sc, "BAD attention state");
4159 /* handle bits that were raised */
4161 bnx2x_attn_int_asserted(sc, asserted);
4165 bnx2x_attn_int_deasserted(sc, deasserted);
4169 static uint16_t bnx2x_update_dsb_idx(struct bnx2x_softc *sc)
4171 struct host_sp_status_block *def_sb = sc->def_sb;
4174 mb(); /* status block is written to by the chip */
4176 if (sc->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
4177 sc->def_att_idx = def_sb->atten_status_block.attn_bits_index;
4178 rc |= BNX2X_DEF_SB_ATT_IDX;
4181 if (sc->def_idx != def_sb->sp_sb.running_index) {
4182 sc->def_idx = def_sb->sp_sb.running_index;
4183 rc |= BNX2X_DEF_SB_IDX;
4191 static struct ecore_queue_sp_obj *bnx2x_cid_to_q_obj(struct bnx2x_softc *sc,
4194 return &sc->sp_objs[CID_TO_FP(cid, sc)].q_obj;
4197 static void bnx2x_handle_mcast_eqe(struct bnx2x_softc *sc)
4199 struct ecore_mcast_ramrod_params rparam;
4202 memset(&rparam, 0, sizeof(rparam));
4204 rparam.mcast_obj = &sc->mcast_obj;
4206 /* clear pending state for the last command */
4207 sc->mcast_obj.raw.clear_pending(&sc->mcast_obj.raw);
4209 /* if there are pending mcast commands - send them */
4210 if (sc->mcast_obj.check_pending(&sc->mcast_obj)) {
4211 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
4213 PMD_DRV_LOG(INFO, sc,
4214 "Failed to send pending mcast commands (%d)",
4221 bnx2x_handle_classification_eqe(struct bnx2x_softc *sc, union event_ring_elem *elem)
4223 unsigned long ramrod_flags = 0;
4225 uint32_t cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4226 struct ecore_vlan_mac_obj *vlan_mac_obj;
4228 /* always push next commands out, don't wait here */
4229 bnx2x_set_bit(RAMROD_CONT, &ramrod_flags);
4231 switch (le32toh(elem->message.data.eth_event.echo) >> BNX2X_SWCID_SHIFT) {
4232 case ECORE_FILTER_MAC_PENDING:
4233 PMD_DRV_LOG(DEBUG, sc, "Got SETUP_MAC completions");
4234 vlan_mac_obj = &sc->sp_objs[cid].mac_obj;
4237 case ECORE_FILTER_MCAST_PENDING:
4238 PMD_DRV_LOG(DEBUG, sc, "Got SETUP_MCAST completions");
4239 bnx2x_handle_mcast_eqe(sc);
4243 PMD_DRV_LOG(NOTICE, sc, "Unsupported classification command: %d",
4244 elem->message.data.eth_event.echo);
4248 rc = vlan_mac_obj->complete(sc, vlan_mac_obj, elem, &ramrod_flags);
4251 PMD_DRV_LOG(NOTICE, sc,
4252 "Failed to schedule new commands (%d)", rc);
4253 } else if (rc > 0) {
4254 PMD_DRV_LOG(DEBUG, sc, "Scheduled next pending commands...");
4258 static void bnx2x_handle_rx_mode_eqe(struct bnx2x_softc *sc)
4260 bnx2x_clear_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
4262 /* send rx_mode command again if was requested */
4263 if (bnx2x_test_and_clear_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state)) {
4264 bnx2x_set_storm_rx_mode(sc);
4268 static void bnx2x_update_eq_prod(struct bnx2x_softc *sc, uint16_t prod)
4270 storm_memset_eq_prod(sc, prod, SC_FUNC(sc));
4271 wmb(); /* keep prod updates ordered */
4274 static void bnx2x_eq_int(struct bnx2x_softc *sc)
4276 uint16_t hw_cons, sw_cons, sw_prod;
4277 union event_ring_elem *elem;
4282 struct ecore_queue_sp_obj *q_obj;
4283 struct ecore_func_sp_obj *f_obj = &sc->func_obj;
4284 struct ecore_raw_obj *rss_raw = &sc->rss_conf_obj.raw;
4286 hw_cons = le16toh(*sc->eq_cons_sb);
4289 * The hw_cons range is 1-255, 257 - the sw_cons range is 0-254, 256.
4290 * when we get to the next-page we need to adjust so the loop
4291 * condition below will be met. The next element is the size of a
4292 * regular element and hence incrementing by 1
4294 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) {
4299 * This function may never run in parallel with itself for a
4300 * specific sc and no need for a read memory barrier here.
4302 sw_cons = sc->eq_cons;
4303 sw_prod = sc->eq_prod;
4307 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4309 elem = &sc->eq[EQ_DESC(sw_cons)];
4311 /* elem CID originates from FW, actually LE */
4312 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4313 opcode = elem->message.opcode;
4315 /* handle eq element */
4317 case EVENT_RING_OPCODE_STAT_QUERY:
4318 PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "got statistics completion event %d",
4320 /* nothing to do with stats comp */
4323 case EVENT_RING_OPCODE_CFC_DEL:
4324 /* handle according to cid range */
4325 /* we may want to verify here that the sc state is HALTING */
4326 PMD_DRV_LOG(DEBUG, sc, "got delete ramrod for MULTI[%d]",
4328 q_obj = bnx2x_cid_to_q_obj(sc, cid);
4329 if (q_obj->complete_cmd(sc, q_obj, ECORE_Q_CMD_CFC_DEL)) {
4334 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4335 PMD_DRV_LOG(DEBUG, sc, "got STOP TRAFFIC");
4336 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_STOP)) {
4341 case EVENT_RING_OPCODE_START_TRAFFIC:
4342 PMD_DRV_LOG(DEBUG, sc, "got START TRAFFIC");
4343 if (f_obj->complete_cmd
4344 (sc, f_obj, ECORE_F_CMD_TX_START)) {
4349 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
4350 echo = elem->message.data.function_update_event.echo;
4351 if (echo == SWITCH_UPDATE) {
4352 PMD_DRV_LOG(DEBUG, sc,
4353 "got FUNC_SWITCH_UPDATE ramrod");
4354 if (f_obj->complete_cmd(sc, f_obj,
4355 ECORE_F_CMD_SWITCH_UPDATE))
4360 PMD_DRV_LOG(DEBUG, sc,
4361 "AFEX: ramrod completed FUNCTION_UPDATE");
4362 f_obj->complete_cmd(sc, f_obj,
4363 ECORE_F_CMD_AFEX_UPDATE);
4367 case EVENT_RING_OPCODE_FORWARD_SETUP:
4368 q_obj = &bnx2x_fwd_sp_obj(sc, q_obj);
4369 if (q_obj->complete_cmd(sc, q_obj,
4370 ECORE_Q_CMD_SETUP_TX_ONLY)) {
4375 case EVENT_RING_OPCODE_FUNCTION_START:
4376 PMD_DRV_LOG(DEBUG, sc, "got FUNC_START ramrod");
4377 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_START)) {
4382 case EVENT_RING_OPCODE_FUNCTION_STOP:
4383 PMD_DRV_LOG(DEBUG, sc, "got FUNC_STOP ramrod");
4384 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_STOP)) {
4390 switch (opcode | sc->state) {
4391 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPEN):
4392 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPENING_WAITING_PORT):
4394 elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4395 PMD_DRV_LOG(DEBUG, sc, "got RSS_UPDATE ramrod. CID %d",
4397 rss_raw->clear_pending(rss_raw);
4400 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4401 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4402 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_CLOSING_WAITING_HALT):
4403 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_OPEN):
4404 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_DIAG):
4405 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4406 PMD_DRV_LOG(DEBUG, sc,
4407 "got (un)set mac ramrod");
4408 bnx2x_handle_classification_eqe(sc, elem);
4411 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_OPEN):
4412 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_DIAG):
4413 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4414 PMD_DRV_LOG(DEBUG, sc,
4415 "got mcast ramrod");
4416 bnx2x_handle_mcast_eqe(sc);
4419 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_OPEN):
4420 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_DIAG):
4421 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4422 PMD_DRV_LOG(DEBUG, sc,
4423 "got rx_mode ramrod");
4424 bnx2x_handle_rx_mode_eqe(sc);
4428 /* unknown event log error and continue */
4429 PMD_DRV_LOG(INFO, sc, "Unknown EQ event %d, sc->state 0x%x",
4430 elem->message.opcode, sc->state);
4438 atomic_add_acq_long(&sc->eq_spq_left, spqe_cnt);
4440 sc->eq_cons = sw_cons;
4441 sc->eq_prod = sw_prod;
4443 /* make sure that above mem writes were issued towards the memory */
4446 /* update producer */
4447 bnx2x_update_eq_prod(sc, sc->eq_prod);
4450 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc)
4455 PMD_DRV_LOG(DEBUG, sc, "---> SP TASK <---");
4457 /* what work needs to be performed? */
4458 status = bnx2x_update_dsb_idx(sc);
4460 PMD_DRV_LOG(DEBUG, sc, "dsb status 0x%04x", status);
4463 if (status & BNX2X_DEF_SB_ATT_IDX) {
4464 PMD_DRV_LOG(DEBUG, sc, "---> ATTN INTR <---");
4466 status &= ~BNX2X_DEF_SB_ATT_IDX;
4470 /* SP events: STAT_QUERY and others */
4471 if (status & BNX2X_DEF_SB_IDX) {
4472 /* handle EQ completions */
4473 PMD_DRV_LOG(DEBUG, sc, "---> EQ INTR <---");
4475 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
4476 le16toh(sc->def_idx), IGU_INT_NOP, 1);
4477 status &= ~BNX2X_DEF_SB_IDX;
4480 /* if status is non zero then something went wrong */
4481 if (unlikely(status)) {
4482 PMD_DRV_LOG(INFO, sc,
4483 "Got an unknown SP interrupt! (0x%04x)", status);
4486 /* ack status block only if something was actually handled */
4487 bnx2x_ack_sb(sc, sc->igu_dsb_id, ATTENTION_ID,
4488 le16toh(sc->def_att_idx), IGU_INT_ENABLE, 1);
4493 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp, int scan_fp)
4495 struct bnx2x_softc *sc = fp->sc;
4496 uint8_t more_rx = FALSE;
4498 PMD_DEBUG_PERIODIC_LOG(DEBUG, sc,
4499 "---> FP TASK QUEUE (%d) <--", fp->index);
4501 /* update the fastpath index */
4502 bnx2x_update_fp_sb_idx(fp);
4505 if (bnx2x_has_rx_work(fp)) {
4506 more_rx = bnx2x_rxeof(sc, fp);
4510 /* still more work to do */
4511 bnx2x_handle_fp_tq(fp, scan_fp);
4516 bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
4517 le16toh(fp->fp_hc_idx), IGU_INT_ENABLE, 1);
4521 * Legacy interrupt entry point.
4523 * Verifies that the controller generated the interrupt and
4524 * then calls a separate routine to handle the various
4525 * interrupt causes: link, RX, and TX.
4527 int bnx2x_intr_legacy(struct bnx2x_softc *sc, int scan_fp)
4529 struct bnx2x_fastpath *fp;
4530 uint32_t status, mask;
4534 * 0 for ustorm, 1 for cstorm
4535 * the bits returned from ack_int() are 0-15
4536 * bit 0 = attention status block
4537 * bit 1 = fast path status block
4538 * a mask of 0x2 or more = tx/rx event
4539 * a mask of 1 = slow path event
4542 status = bnx2x_ack_int(sc);
4544 /* the interrupt is not for us */
4545 if (unlikely(status == 0)) {
4549 PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "Interrupt status 0x%04x", status);
4550 //bnx2x_dump_status_block(sc);
4552 FOR_EACH_ETH_QUEUE(sc, i) {
4554 mask = (0x2 << (fp->index + CNIC_SUPPORT(sc)));
4555 if (status & mask) {
4556 /* acknowledge and disable further fastpath interrupts */
4557 bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
4558 0, IGU_INT_DISABLE, 0);
4559 bnx2x_handle_fp_tq(fp, scan_fp);
4564 if (unlikely(status & 0x1)) {
4565 /* acknowledge and disable further slowpath interrupts */
4566 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
4567 0, IGU_INT_DISABLE, 0);
4568 rc = bnx2x_handle_sp_tq(sc);
4572 if (unlikely(status)) {
4573 PMD_DRV_LOG(WARNING, sc,
4574 "Unexpected fastpath status (0x%08x)!", status);
4580 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc);
4581 static int bnx2x_init_hw_common(struct bnx2x_softc *sc);
4582 static int bnx2x_init_hw_port(struct bnx2x_softc *sc);
4583 static int bnx2x_init_hw_func(struct bnx2x_softc *sc);
4584 static void bnx2x_reset_common(struct bnx2x_softc *sc);
4585 static void bnx2x_reset_port(struct bnx2x_softc *sc);
4586 static void bnx2x_reset_func(struct bnx2x_softc *sc);
4587 static int bnx2x_init_firmware(struct bnx2x_softc *sc);
4588 static void bnx2x_release_firmware(struct bnx2x_softc *sc);
4591 ecore_func_sp_drv_ops bnx2x_func_sp_drv = {
4592 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
4593 .init_hw_cmn = bnx2x_init_hw_common,
4594 .init_hw_port = bnx2x_init_hw_port,
4595 .init_hw_func = bnx2x_init_hw_func,
4597 .reset_hw_cmn = bnx2x_reset_common,
4598 .reset_hw_port = bnx2x_reset_port,
4599 .reset_hw_func = bnx2x_reset_func,
4601 .init_fw = bnx2x_init_firmware,
4602 .release_fw = bnx2x_release_firmware,
4605 static void bnx2x_init_func_obj(struct bnx2x_softc *sc)
4609 PMD_INIT_FUNC_TRACE(sc);
4611 ecore_init_func_obj(sc,
4613 BNX2X_SP(sc, func_rdata),
4614 (rte_iova_t)BNX2X_SP_MAPPING(sc, func_rdata),
4615 BNX2X_SP(sc, func_afex_rdata),
4616 (rte_iova_t)BNX2X_SP_MAPPING(sc, func_afex_rdata),
4617 &bnx2x_func_sp_drv);
4620 static int bnx2x_init_hw(struct bnx2x_softc *sc, uint32_t load_code)
4622 struct ecore_func_state_params func_params = { NULL };
4625 PMD_INIT_FUNC_TRACE(sc);
4627 /* prepare the parameters for function state transitions */
4628 bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
4630 func_params.f_obj = &sc->func_obj;
4631 func_params.cmd = ECORE_F_CMD_HW_INIT;
4633 func_params.params.hw_init.load_phase = load_code;
4636 * Via a plethora of function pointers, we will eventually reach
4637 * bnx2x_init_hw_common(), bnx2x_init_hw_port(), or bnx2x_init_hw_func().
4639 rc = ecore_func_state_change(sc, &func_params);
4645 bnx2x_fill(struct bnx2x_softc *sc, uint32_t addr, int fill, uint32_t len)
4649 if (!(len % 4) && !(addr % 4)) {
4650 for (i = 0; i < len; i += 4) {
4651 REG_WR(sc, (addr + i), fill);
4654 for (i = 0; i < len; i++) {
4655 REG_WR8(sc, (addr + i), fill);
4660 /* writes FP SP data to FW - data_size in dwords */
4662 bnx2x_wr_fp_sb_data(struct bnx2x_softc *sc, int fw_sb_id, uint32_t * sb_data_p,
4667 for (index = 0; index < data_size; index++) {
4669 (BAR_CSTRORM_INTMEM +
4670 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
4671 (sizeof(uint32_t) * index)), *(sb_data_p + index));
4675 static void bnx2x_zero_fp_sb(struct bnx2x_softc *sc, int fw_sb_id)
4677 struct hc_status_block_data_e2 sb_data_e2;
4678 struct hc_status_block_data_e1x sb_data_e1x;
4679 uint32_t *sb_data_p;
4680 uint32_t data_size = 0;
4682 if (!CHIP_IS_E1x(sc)) {
4683 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4684 sb_data_e2.common.state = SB_DISABLED;
4685 sb_data_e2.common.p_func.vf_valid = FALSE;
4686 sb_data_p = (uint32_t *) & sb_data_e2;
4687 data_size = (sizeof(struct hc_status_block_data_e2) /
4690 memset(&sb_data_e1x, 0,
4691 sizeof(struct hc_status_block_data_e1x));
4692 sb_data_e1x.common.state = SB_DISABLED;
4693 sb_data_e1x.common.p_func.vf_valid = FALSE;
4694 sb_data_p = (uint32_t *) & sb_data_e1x;
4695 data_size = (sizeof(struct hc_status_block_data_e1x) /
4699 bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4702 (BAR_CSTRORM_INTMEM + CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id)), 0,
4703 CSTORM_STATUS_BLOCK_SIZE);
4704 bnx2x_fill(sc, (BAR_CSTRORM_INTMEM + CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id)),
4705 0, CSTORM_SYNC_BLOCK_SIZE);
4709 bnx2x_wr_sp_sb_data(struct bnx2x_softc *sc,
4710 struct hc_sp_status_block_data *sp_sb_data)
4715 i < (sizeof(struct hc_sp_status_block_data) / sizeof(uint32_t));
4718 (BAR_CSTRORM_INTMEM +
4719 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(SC_FUNC(sc)) +
4720 (i * sizeof(uint32_t))),
4721 *((uint32_t *) sp_sb_data + i));
4725 static void bnx2x_zero_sp_sb(struct bnx2x_softc *sc)
4727 struct hc_sp_status_block_data sp_sb_data;
4729 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4731 sp_sb_data.state = SB_DISABLED;
4732 sp_sb_data.p_func.vf_valid = FALSE;
4734 bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
4737 (BAR_CSTRORM_INTMEM +
4738 CSTORM_SP_STATUS_BLOCK_OFFSET(SC_FUNC(sc))),
4739 0, CSTORM_SP_STATUS_BLOCK_SIZE);
4741 (BAR_CSTRORM_INTMEM +
4742 CSTORM_SP_SYNC_BLOCK_OFFSET(SC_FUNC(sc))),
4743 0, CSTORM_SP_SYNC_BLOCK_SIZE);
4747 bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, int igu_sb_id,
4750 hc_sm->igu_sb_id = igu_sb_id;
4751 hc_sm->igu_seg_id = igu_seg_id;
4752 hc_sm->timer_value = 0xFF;
4753 hc_sm->time_to_expire = 0xFFFFFFFF;
4756 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
4758 /* zero out state machine indices */
4761 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4764 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4765 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
4766 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
4767 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
4772 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
4773 (SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4776 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
4777 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4778 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
4779 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4780 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
4781 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4782 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
4783 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4787 bnx2x_init_sb(struct bnx2x_softc *sc, rte_iova_t busaddr, int vfid,
4788 uint8_t vf_valid, int fw_sb_id, int igu_sb_id)
4790 struct hc_status_block_data_e2 sb_data_e2;
4791 struct hc_status_block_data_e1x sb_data_e1x;
4792 struct hc_status_block_sm *hc_sm_p;
4793 uint32_t *sb_data_p;
4797 if (CHIP_INT_MODE_IS_BC(sc)) {
4798 igu_seg_id = HC_SEG_ACCESS_NORM;
4800 igu_seg_id = IGU_SEG_ACCESS_NORM;
4803 bnx2x_zero_fp_sb(sc, fw_sb_id);
4805 if (!CHIP_IS_E1x(sc)) {
4806 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4807 sb_data_e2.common.state = SB_ENABLED;
4808 sb_data_e2.common.p_func.pf_id = SC_FUNC(sc);
4809 sb_data_e2.common.p_func.vf_id = vfid;
4810 sb_data_e2.common.p_func.vf_valid = vf_valid;
4811 sb_data_e2.common.p_func.vnic_id = SC_VN(sc);
4812 sb_data_e2.common.same_igu_sb_1b = TRUE;
4813 sb_data_e2.common.host_sb_addr.hi = U64_HI(busaddr);
4814 sb_data_e2.common.host_sb_addr.lo = U64_LO(busaddr);
4815 hc_sm_p = sb_data_e2.common.state_machine;
4816 sb_data_p = (uint32_t *) & sb_data_e2;
4817 data_size = (sizeof(struct hc_status_block_data_e2) /
4819 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
4821 memset(&sb_data_e1x, 0,
4822 sizeof(struct hc_status_block_data_e1x));
4823 sb_data_e1x.common.state = SB_ENABLED;
4824 sb_data_e1x.common.p_func.pf_id = SC_FUNC(sc);
4825 sb_data_e1x.common.p_func.vf_id = 0xff;
4826 sb_data_e1x.common.p_func.vf_valid = FALSE;
4827 sb_data_e1x.common.p_func.vnic_id = SC_VN(sc);
4828 sb_data_e1x.common.same_igu_sb_1b = TRUE;
4829 sb_data_e1x.common.host_sb_addr.hi = U64_HI(busaddr);
4830 sb_data_e1x.common.host_sb_addr.lo = U64_LO(busaddr);
4831 hc_sm_p = sb_data_e1x.common.state_machine;
4832 sb_data_p = (uint32_t *) & sb_data_e1x;
4833 data_size = (sizeof(struct hc_status_block_data_e1x) /
4835 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
4838 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], igu_sb_id, igu_seg_id);
4839 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], igu_sb_id, igu_seg_id);
4841 /* write indices to HW - PCI guarantees endianity of regpairs */
4842 bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4845 static uint8_t bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp)
4847 if (CHIP_IS_E1x(fp->sc)) {
4848 return fp->cl_id + SC_PORT(fp->sc) * ETH_MAX_RX_CLIENTS_E1H;
4855 bnx2x_rx_ustorm_prods_offset(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
4857 uint32_t offset = BAR_USTRORM_INTMEM;
4860 return PXP_VF_ADDR_USDM_QUEUES_START +
4861 (sc->acquire_resp.resc.hw_qid[fp->index] *
4862 sizeof(struct ustorm_queue_zone_data));
4863 } else if (!CHIP_IS_E1x(sc)) {
4864 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
4866 offset += USTORM_RX_PRODS_E1X_OFFSET(SC_PORT(sc), fp->cl_id);
4872 static void bnx2x_init_eth_fp(struct bnx2x_softc *sc, int idx)
4874 struct bnx2x_fastpath *fp = &sc->fp[idx];
4875 uint32_t cids[ECORE_MULTI_TX_COS] = { 0 };
4876 unsigned long q_type = 0;
4882 fp->igu_sb_id = (sc->igu_base_sb + idx + CNIC_SUPPORT(sc));
4883 fp->fw_sb_id = (sc->base_fw_ndsb + idx + CNIC_SUPPORT(sc));
4885 if (CHIP_IS_E1x(sc))
4886 fp->cl_id = SC_L_ID(sc) + idx;
4888 /* want client ID same as IGU SB ID for non-E1 */
4889 fp->cl_id = fp->igu_sb_id;
4890 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
4892 /* setup sb indices */
4893 if (!CHIP_IS_E1x(sc)) {
4894 fp->sb_index_values = fp->status_block.e2_sb->sb.index_values;
4895 fp->sb_running_index = fp->status_block.e2_sb->sb.running_index;
4897 fp->sb_index_values = fp->status_block.e1x_sb->sb.index_values;
4898 fp->sb_running_index =
4899 fp->status_block.e1x_sb->sb.running_index;
4903 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(sc, fp);
4905 fp->rx_cq_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS];
4907 for (cos = 0; cos < sc->max_cos; cos++) {
4910 fp->tx_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0];
4912 /* nothing more for a VF to do */
4917 bnx2x_init_sb(sc, fp->sb_dma.paddr, BNX2X_VF_ID_INVALID, FALSE,
4918 fp->fw_sb_id, fp->igu_sb_id);
4920 bnx2x_update_fp_sb_idx(fp);
4922 /* Configure Queue State object */
4923 bnx2x_set_bit(ECORE_Q_TYPE_HAS_RX, &q_type);
4924 bnx2x_set_bit(ECORE_Q_TYPE_HAS_TX, &q_type);
4926 ecore_init_queue_obj(sc,
4927 &sc->sp_objs[idx].q_obj,
4932 BNX2X_SP(sc, q_rdata),
4933 (rte_iova_t)BNX2X_SP_MAPPING(sc, q_rdata),
4936 /* configure classification DBs */
4937 ecore_init_mac_obj(sc,
4938 &sc->sp_objs[idx].mac_obj,
4942 BNX2X_SP(sc, mac_rdata),
4943 (rte_iova_t)BNX2X_SP_MAPPING(sc, mac_rdata),
4944 ECORE_FILTER_MAC_PENDING, &sc->sp_state,
4945 ECORE_OBJ_TYPE_RX_TX, &sc->macs_pool);
4949 bnx2x_update_rx_prod(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
4950 uint16_t rx_bd_prod, uint16_t rx_cq_prod)
4952 union ustorm_eth_rx_producers rx_prods;
4955 /* update producers */
4956 rx_prods.prod.bd_prod = rx_bd_prod;
4957 rx_prods.prod.cqe_prod = rx_cq_prod;
4958 rx_prods.prod.reserved = 0;
4961 * Make sure that the BD and SGE data is updated before updating the
4962 * producers since FW might read the BD/SGE right after the producer
4964 * This is only applicable for weak-ordered memory model archs such
4965 * as IA-64. The following barrier is also mandatory since FW will
4966 * assumes BDs must have buffers.
4970 for (i = 0; i < (sizeof(rx_prods) / 4); i++) {
4972 (fp->ustorm_rx_prods_offset + (i * 4)),
4973 rx_prods.raw_data[i]);
4976 wmb(); /* keep prod updates ordered */
4979 static void bnx2x_init_rx_rings(struct bnx2x_softc *sc)
4981 struct bnx2x_fastpath *fp;
4983 struct bnx2x_rx_queue *rxq;
4985 for (i = 0; i < sc->num_queues; i++) {
4987 rxq = sc->rx_queues[fp->index];
4989 PMD_RX_LOG(ERR, "RX queue is NULL");
4993 rxq->rx_bd_head = 0;
4994 rxq->rx_bd_tail = rxq->nb_rx_desc;
4995 rxq->rx_cq_head = 0;
4996 rxq->rx_cq_tail = TOTAL_RCQ_ENTRIES(rxq);
4997 *fp->rx_cq_cons_sb = 0;
5000 * Activate the BD ring...
5001 * Warning, this will generate an interrupt (to the TSTORM)
5002 * so this can only be done after the chip is initialized
5004 bnx2x_update_rx_prod(sc, fp, rxq->rx_bd_tail, rxq->rx_cq_tail);
5012 static void bnx2x_init_tx_ring_one(struct bnx2x_fastpath *fp)
5014 struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
5016 fp->tx_db.data.header.header = 1 << DOORBELL_HDR_DB_TYPE_SHIFT;
5017 fp->tx_db.data.zero_fill1 = 0;
5018 fp->tx_db.data.prod = 0;
5021 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
5025 txq->tx_pkt_tail = 0;
5026 txq->tx_pkt_head = 0;
5027 txq->tx_bd_tail = 0;
5028 txq->tx_bd_head = 0;
5031 static void bnx2x_init_tx_rings(struct bnx2x_softc *sc)
5035 for (i = 0; i < sc->num_queues; i++) {
5036 bnx2x_init_tx_ring_one(&sc->fp[i]);
5040 static void bnx2x_init_def_sb(struct bnx2x_softc *sc)
5042 struct host_sp_status_block *def_sb = sc->def_sb;
5043 rte_iova_t mapping = sc->def_sb_dma.paddr;
5044 int igu_sp_sb_index;
5046 int port = SC_PORT(sc);
5047 int func = SC_FUNC(sc);
5048 int reg_offset, reg_offset_en5;
5051 struct hc_sp_status_block_data sp_sb_data;
5053 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5055 if (CHIP_INT_MODE_IS_BC(sc)) {
5056 igu_sp_sb_index = DEF_SB_IGU_ID;
5057 igu_seg_id = HC_SEG_ACCESS_DEF;
5059 igu_sp_sb_index = sc->igu_dsb_id;
5060 igu_seg_id = IGU_SEG_ACCESS_DEF;
5064 section = ((uint64_t) mapping +
5065 offsetof(struct host_sp_status_block, atten_status_block));
5066 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5069 reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5070 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
5072 reg_offset_en5 = (port) ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5073 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0;
5075 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5076 /* take care of sig[0]..sig[4] */
5077 for (sindex = 0; sindex < 4; sindex++) {
5078 sc->attn_group[index].sig[sindex] =
5080 (reg_offset + (sindex * 0x4) +
5084 if (!CHIP_IS_E1x(sc)) {
5086 * enable5 is separate from the rest of the registers,
5087 * and the address skip is 4 and not 16 between the
5090 sc->attn_group[index].sig[4] =
5091 REG_RD(sc, (reg_offset_en5 + (0x4 * index)));
5093 sc->attn_group[index].sig[4] = 0;
5097 if (sc->devinfo.int_block == INT_BLOCK_HC) {
5099 port ? HC_REG_ATTN_MSG1_ADDR_L : HC_REG_ATTN_MSG0_ADDR_L;
5100 REG_WR(sc, reg_offset, U64_LO(section));
5101 REG_WR(sc, (reg_offset + 4), U64_HI(section));
5102 } else if (!CHIP_IS_E1x(sc)) {
5103 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5104 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5107 section = ((uint64_t) mapping +
5108 offsetof(struct host_sp_status_block, sp_sb));
5110 bnx2x_zero_sp_sb(sc);
5112 /* PCI guarantees endianity of regpair */
5113 sp_sb_data.state = SB_ENABLED;
5114 sp_sb_data.host_sb_addr.lo = U64_LO(section);
5115 sp_sb_data.host_sb_addr.hi = U64_HI(section);
5116 sp_sb_data.igu_sb_id = igu_sp_sb_index;
5117 sp_sb_data.igu_seg_id = igu_seg_id;
5118 sp_sb_data.p_func.pf_id = func;
5119 sp_sb_data.p_func.vnic_id = SC_VN(sc);
5120 sp_sb_data.p_func.vf_id = 0xff;
5122 bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
5124 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5127 static void bnx2x_init_sp_ring(struct bnx2x_softc *sc)
5129 atomic_store_rel_long(&sc->cq_spq_left, MAX_SPQ_PENDING);
5130 sc->spq_prod_idx = 0;
5132 &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_ETH_DEF_CONS];
5133 sc->spq_prod_bd = sc->spq;
5134 sc->spq_last_bd = (sc->spq_prod_bd + MAX_SP_DESC_CNT);
5137 static void bnx2x_init_eq_ring(struct bnx2x_softc *sc)
5139 union event_ring_elem *elem;
5142 for (i = 1; i <= NUM_EQ_PAGES; i++) {
5143 elem = &sc->eq[EQ_DESC_CNT_PAGE * i - 1];
5145 elem->next_page.addr.hi = htole32(U64_HI(sc->eq_dma.paddr +
5147 (i % NUM_EQ_PAGES)));
5148 elem->next_page.addr.lo = htole32(U64_LO(sc->eq_dma.paddr +
5150 (i % NUM_EQ_PAGES)));
5154 sc->eq_prod = NUM_EQ_DESC;
5155 sc->eq_cons_sb = &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_EQ_CONS];
5157 atomic_store_rel_long(&sc->eq_spq_left,
5158 (min((MAX_SP_DESC_CNT - MAX_SPQ_PENDING),
5162 static void bnx2x_init_internal_common(struct bnx2x_softc *sc)
5168 * In switch independent mode, the TSTORM needs to accept
5169 * packets that failed classification, since approximate match
5170 * mac addresses aren't written to NIG LLH.
5173 (BAR_TSTRORM_INTMEM +
5174 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 2);
5177 (BAR_TSTRORM_INTMEM +
5178 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 0);
5181 * Zero this manually as its initialization is currently missing
5184 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) {
5186 (BAR_USTRORM_INTMEM + USTORM_AGG_DATA_OFFSET + (i * 4)),
5190 if (!CHIP_IS_E1x(sc)) {
5191 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET),
5192 CHIP_INT_MODE_IS_BC(sc) ? HC_IGU_BC_MODE :
5197 static void bnx2x_init_internal(struct bnx2x_softc *sc, uint32_t load_code)
5199 switch (load_code) {
5200 case FW_MSG_CODE_DRV_LOAD_COMMON:
5201 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5202 bnx2x_init_internal_common(sc);
5205 case FW_MSG_CODE_DRV_LOAD_PORT:
5209 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5210 /* internal memory per function is initialized inside bnx2x_pf_init */
5214 PMD_DRV_LOG(NOTICE, sc, "Unknown load_code (0x%x) from MCP",
5221 storm_memset_func_cfg(struct bnx2x_softc *sc,
5222 struct tstorm_eth_function_common_config *tcfg,
5228 addr = (BAR_TSTRORM_INTMEM +
5229 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid));
5230 size = sizeof(struct tstorm_eth_function_common_config);
5231 ecore_storm_memset_struct(sc, addr, size, (uint32_t *) tcfg);
5234 static void bnx2x_func_init(struct bnx2x_softc *sc, struct bnx2x_func_init_params *p)
5236 struct tstorm_eth_function_common_config tcfg = { 0 };
5238 if (CHIP_IS_E1x(sc)) {
5239 storm_memset_func_cfg(sc, &tcfg, p->func_id);
5242 /* Enable the function in the FW */
5243 storm_memset_vf_to_pf(sc, p->func_id, p->pf_id);
5244 storm_memset_func_en(sc, p->func_id, 1);
5247 if (p->func_flgs & FUNC_FLG_SPQ) {
5248 storm_memset_spq_addr(sc, p->spq_map, p->func_id);
5250 (XSEM_REG_FAST_MEMORY +
5251 XSTORM_SPQ_PROD_OFFSET(p->func_id)), p->spq_prod);
5256 * Calculates the sum of vn_min_rates.
5257 * It's needed for further normalizing of the min_rates.
5259 * sum of vn_min_rates.
5261 * 0 - if all the min_rates are 0.
5262 * In the later case fainess algorithm should be deactivated.
5263 * If all min rates are not zero then those that are zeroes will be set to 1.
5265 static void bnx2x_calc_vn_min(struct bnx2x_softc *sc, struct cmng_init_input *input)
5268 uint32_t vn_min_rate;
5272 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5273 vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5274 vn_min_rate = (((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
5275 FUNC_MF_CFG_MIN_BW_SHIFT) * 100);
5277 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5278 /* skip hidden VNs */
5280 } else if (!vn_min_rate) {
5281 /* If min rate is zero - set it to 100 */
5282 vn_min_rate = DEF_MIN_RATE;
5287 input->vnic_min_rate[vn] = vn_min_rate;
5290 /* if ETS or all min rates are zeros - disable fairness */
5292 input->flags.cmng_enables &= ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5294 input->flags.cmng_enables |= CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5299 bnx2x_extract_max_cfg(__rte_unused struct bnx2x_softc *sc, uint32_t mf_cfg)
5301 uint16_t max_cfg = ((mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
5302 FUNC_MF_CFG_MAX_BW_SHIFT);
5305 PMD_DRV_LOG(DEBUG, sc,
5306 "Max BW configured to 0 - using 100 instead");
5314 bnx2x_calc_vn_max(struct bnx2x_softc *sc, int vn, struct cmng_init_input *input)
5316 uint16_t vn_max_rate;
5317 uint32_t vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5320 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5323 max_cfg = bnx2x_extract_max_cfg(sc, vn_cfg);
5326 /* max_cfg in percents of linkspeed */
5328 ((sc->link_vars.line_speed * max_cfg) / 100);
5329 } else { /* SD modes */
5330 /* max_cfg is absolute in 100Mb units */
5331 vn_max_rate = (max_cfg * 100);
5335 input->vnic_max_rate[vn] = vn_max_rate;
5339 bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg, uint8_t cmng_type)
5341 struct cmng_init_input input;
5344 memset(&input, 0, sizeof(struct cmng_init_input));
5346 input.port_rate = sc->link_vars.line_speed;
5348 if (cmng_type == CMNG_FNS_MINMAX) {
5349 /* read mf conf from shmem */
5351 bnx2x_read_mf_cfg(sc);
5354 /* get VN min rate and enable fairness if not 0 */
5355 bnx2x_calc_vn_min(sc, &input);
5357 /* get VN max rate */
5359 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5360 bnx2x_calc_vn_max(sc, vn, &input);
5364 /* always enable rate shaping and fairness */
5365 input.flags.cmng_enables |= CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
5367 ecore_init_cmng(&input, &sc->cmng);
5372 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc)
5374 if (CHIP_REV_IS_SLOW(sc)) {
5375 return CMNG_FNS_NONE;
5379 return CMNG_FNS_MINMAX;
5382 return CMNG_FNS_NONE;
5386 storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng, uint8_t port)
5393 addr = (BAR_XSTRORM_INTMEM + XSTORM_CMNG_PER_PORT_VARS_OFFSET(port));
5394 size = sizeof(struct cmng_struct_per_port);
5395 ecore_storm_memset_struct(sc, addr, size, (uint32_t *) & cmng->port);
5397 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5398 func = func_by_vn(sc, vn);
5400 addr = (BAR_XSTRORM_INTMEM +
5401 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func));
5402 size = sizeof(struct rate_shaping_vars_per_vn);
5403 ecore_storm_memset_struct(sc, addr, size,
5404 (uint32_t *) & cmng->
5405 vnic.vnic_max_rate[vn]);
5407 addr = (BAR_XSTRORM_INTMEM +
5408 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func));
5409 size = sizeof(struct fairness_vars_per_vn);
5410 ecore_storm_memset_struct(sc, addr, size,
5411 (uint32_t *) & cmng->
5412 vnic.vnic_min_rate[vn]);
5416 static void bnx2x_pf_init(struct bnx2x_softc *sc)
5418 struct bnx2x_func_init_params func_init;
5419 struct event_ring_data eq_data;
5422 memset(&eq_data, 0, sizeof(struct event_ring_data));
5423 memset(&func_init, 0, sizeof(struct bnx2x_func_init_params));
5425 if (!CHIP_IS_E1x(sc)) {
5426 /* reset IGU PF statistics: MSIX + ATTN */
5429 (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5430 (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5431 ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5435 (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5436 (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5437 (BNX2X_IGU_STAS_MSG_PF_CNT * 4) +
5438 ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5442 /* function setup flags */
5443 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
5445 func_init.func_flgs = flags;
5446 func_init.pf_id = SC_FUNC(sc);
5447 func_init.func_id = SC_FUNC(sc);
5448 func_init.spq_map = sc->spq_dma.paddr;
5449 func_init.spq_prod = sc->spq_prod_idx;
5451 bnx2x_func_init(sc, &func_init);
5453 memset(&sc->cmng, 0, sizeof(struct cmng_struct_per_port));
5456 * Congestion management values depend on the link rate.
5457 * There is no active link so initial link rate is set to 10Gbps.
5458 * When the link comes up the congestion management values are
5459 * re-calculated according to the actual link rate.
5461 sc->link_vars.line_speed = SPEED_10000;
5462 bnx2x_cmng_fns_init(sc, TRUE, bnx2x_get_cmng_fns_mode(sc));
5464 /* Only the PMF sets the HW */
5466 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
5469 /* init Event Queue - PCI bus guarantees correct endainity */
5470 eq_data.base_addr.hi = U64_HI(sc->eq_dma.paddr);
5471 eq_data.base_addr.lo = U64_LO(sc->eq_dma.paddr);
5472 eq_data.producer = sc->eq_prod;
5473 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
5474 eq_data.sb_id = DEF_SB_ID;
5475 storm_memset_eq_data(sc, &eq_data, SC_FUNC(sc));
5478 static void bnx2x_hc_int_enable(struct bnx2x_softc *sc)
5480 int port = SC_PORT(sc);
5481 uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5482 uint32_t val = REG_RD(sc, addr);
5483 uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5484 || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5485 uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5486 uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5489 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5490 HC_CONFIG_0_REG_INT_LINE_EN_0);
5491 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5492 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5494 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
5497 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
5498 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5499 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5500 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5502 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5503 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5504 HC_CONFIG_0_REG_INT_LINE_EN_0 |
5505 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5507 REG_WR(sc, addr, val);
5509 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
5512 REG_WR(sc, addr, val);
5514 /* ensure that HC_CONFIG is written before leading/trailing edge config */
5517 /* init leading/trailing edge */
5519 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5521 /* enable nig and gpio3 attention */
5528 REG_WR(sc, (HC_REG_TRAILING_EDGE_0 + port * 8), val);
5529 REG_WR(sc, (HC_REG_LEADING_EDGE_0 + port * 8), val);
5531 /* make sure that interrupts are indeed enabled from here on */
5535 static void bnx2x_igu_int_enable(struct bnx2x_softc *sc)
5538 uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5539 || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5540 uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5541 uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5543 val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5546 val &= ~(IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5547 val |= (IGU_PF_CONF_MSI_MSIX_EN | IGU_PF_CONF_ATTN_BIT_EN);
5549 val |= IGU_PF_CONF_SINGLE_ISR_EN;
5552 val &= ~IGU_PF_CONF_INT_LINE_EN;
5553 val |= (IGU_PF_CONF_MSI_MSIX_EN |
5554 IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5556 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
5557 val |= (IGU_PF_CONF_INT_LINE_EN |
5558 IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5561 /* clean previous status - need to configure igu prior to ack */
5562 if ((!msix) || single_msix) {
5563 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5567 val |= IGU_PF_CONF_FUNC_EN;
5569 PMD_DRV_LOG(DEBUG, sc, "write 0x%x to IGU mode %s",
5570 val, ((msix) ? "MSI-X" : ((msi) ? "MSI" : "INTx")));
5572 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5576 /* init leading/trailing edge */
5578 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5580 /* enable nig and gpio3 attention */
5587 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
5588 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
5590 /* make sure that interrupts are indeed enabled from here on */
5594 static void bnx2x_int_enable(struct bnx2x_softc *sc)
5596 if (sc->devinfo.int_block == INT_BLOCK_HC) {
5597 bnx2x_hc_int_enable(sc);
5599 bnx2x_igu_int_enable(sc);
5603 static void bnx2x_hc_int_disable(struct bnx2x_softc *sc)
5605 int port = SC_PORT(sc);
5606 uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5607 uint32_t val = REG_RD(sc, addr);
5609 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5610 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5611 HC_CONFIG_0_REG_INT_LINE_EN_0 | HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5612 /* flush all outstanding writes */
5615 REG_WR(sc, addr, val);
5616 if (REG_RD(sc, addr) != val) {
5617 PMD_DRV_LOG(ERR, sc, "proper val not read from HC IGU!");
5621 static void bnx2x_igu_int_disable(struct bnx2x_softc *sc)
5623 uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5625 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
5626 IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_ATTN_BIT_EN);
5628 PMD_DRV_LOG(DEBUG, sc, "write %x to IGU", val);
5630 /* flush all outstanding writes */
5633 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5634 if (REG_RD(sc, IGU_REG_PF_CONFIGURATION) != val) {
5635 PMD_DRV_LOG(ERR, sc, "proper val not read from IGU!");
5639 static void bnx2x_int_disable(struct bnx2x_softc *sc)
5641 if (sc->devinfo.int_block == INT_BLOCK_HC) {
5642 bnx2x_hc_int_disable(sc);
5644 bnx2x_igu_int_disable(sc);
5648 static void bnx2x_nic_init(struct bnx2x_softc *sc, int load_code)
5652 PMD_INIT_FUNC_TRACE(sc);
5654 for (i = 0; i < sc->num_queues; i++) {
5655 bnx2x_init_eth_fp(sc, i);
5658 rmb(); /* ensure status block indices were read */
5660 bnx2x_init_rx_rings(sc);
5661 bnx2x_init_tx_rings(sc);
5664 bnx2x_memset_stats(sc);
5668 /* initialize MOD_ABS interrupts */
5669 elink_init_mod_abs_int(sc, &sc->link_vars,
5670 sc->devinfo.chip_id,
5671 sc->devinfo.shmem_base,
5672 sc->devinfo.shmem2_base, SC_PORT(sc));
5674 bnx2x_init_def_sb(sc);
5675 bnx2x_update_dsb_idx(sc);
5676 bnx2x_init_sp_ring(sc);
5677 bnx2x_init_eq_ring(sc);
5678 bnx2x_init_internal(sc, load_code);
5680 bnx2x_stats_init(sc);
5682 /* flush all before enabling interrupts */
5685 bnx2x_int_enable(sc);
5687 /* check for SPIO5 */
5688 bnx2x_attn_int_deasserted0(sc,
5690 (MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
5692 AEU_INPUTS_ATTN_BITS_SPIO5);
5695 static void bnx2x_init_objs(struct bnx2x_softc *sc)
5697 /* mcast rules must be added to tx if tx switching is enabled */
5698 ecore_obj_type o_type;
5699 if (sc->flags & BNX2X_TX_SWITCHING)
5700 o_type = ECORE_OBJ_TYPE_RX_TX;
5702 o_type = ECORE_OBJ_TYPE_RX;
5704 /* RX_MODE controlling object */
5705 ecore_init_rx_mode_obj(sc, &sc->rx_mode_obj);
5707 /* multicast configuration controlling object */
5708 ecore_init_mcast_obj(sc,
5714 BNX2X_SP(sc, mcast_rdata),
5715 (rte_iova_t)BNX2X_SP_MAPPING(sc, mcast_rdata),
5716 ECORE_FILTER_MCAST_PENDING,
5717 &sc->sp_state, o_type);
5719 /* Setup CAM credit pools */
5720 ecore_init_mac_credit_pool(sc,
5723 CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5724 VNICS_PER_PATH(sc));
5726 ecore_init_vlan_credit_pool(sc,
5728 SC_ABS_FUNC(sc) >> 1,
5729 CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5730 VNICS_PER_PATH(sc));
5732 /* RSS configuration object */
5733 ecore_init_rss_config_obj(&sc->rss_conf_obj,
5738 BNX2X_SP(sc, rss_rdata),
5739 (rte_iova_t)BNX2X_SP_MAPPING(sc, rss_rdata),
5740 ECORE_FILTER_RSS_CONF_PENDING,
5741 &sc->sp_state, ECORE_OBJ_TYPE_RX);
5745 * Initialize the function. This must be called before sending CLIENT_SETUP
5746 * for the first client.
5748 static int bnx2x_func_start(struct bnx2x_softc *sc)
5750 struct ecore_func_state_params func_params = { NULL };
5751 struct ecore_func_start_params *start_params =
5752 &func_params.params.start;
5754 /* Prepare parameters for function state transitions */
5755 bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
5757 func_params.f_obj = &sc->func_obj;
5758 func_params.cmd = ECORE_F_CMD_START;
5760 /* Function parameters */
5761 start_params->mf_mode = sc->devinfo.mf_info.mf_mode;
5762 start_params->sd_vlan_tag = OVLAN(sc);
5764 if (CHIP_IS_E2(sc) || CHIP_IS_E3(sc)) {
5765 start_params->network_cos_mode = STATIC_COS;
5766 } else { /* CHIP_IS_E1X */
5767 start_params->network_cos_mode = FW_WRR;
5770 start_params->gre_tunnel_mode = 0;
5771 start_params->gre_tunnel_rss = 0;
5773 return ecore_func_state_change(sc, &func_params);
5776 static int bnx2x_set_power_state(struct bnx2x_softc *sc, uint8_t state)
5780 /* If there is no power capability, silently succeed */
5781 if (!(sc->devinfo.pcie_cap_flags & BNX2X_PM_CAPABLE_FLAG)) {
5782 PMD_DRV_LOG(WARNING, sc, "No power capability");
5786 pci_read(sc, (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS), &pmcsr,
5792 (sc->devinfo.pcie_pm_cap_reg +
5794 ((pmcsr & ~PCIM_PSTAT_DMASK) | PCIM_PSTAT_PME));
5796 if (pmcsr & PCIM_PSTAT_DMASK) {
5797 /* delay required during transition out of D3hot */
5804 /* don't shut down the power for emulation and FPGA */
5805 if (CHIP_REV_IS_SLOW(sc)) {
5809 pmcsr &= ~PCIM_PSTAT_DMASK;
5810 pmcsr |= PCIM_PSTAT_D3;
5813 pmcsr |= PCIM_PSTAT_PMEENABLE;
5817 (sc->devinfo.pcie_pm_cap_reg +
5818 PCIR_POWER_STATUS), pmcsr);
5821 * No more memory access after this point until device is brought back
5827 PMD_DRV_LOG(NOTICE, sc, "Can't support PCI power state = %d",
5835 /* return true if succeeded to acquire the lock */
5836 static uint8_t bnx2x_trylock_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
5838 uint32_t lock_status;
5839 uint32_t resource_bit = (1 << resource);
5840 int func = SC_FUNC(sc);
5841 uint32_t hw_lock_control_reg;
5843 /* Validating that the resource is within range */
5844 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
5845 PMD_DRV_LOG(INFO, sc,
5846 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)",
5847 resource, HW_LOCK_MAX_RESOURCE_VALUE);
5852 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func * 8);
5854 hw_lock_control_reg =
5855 (MISC_REG_DRIVER_CONTROL_7 + (func - 6) * 8);
5858 /* try to acquire the lock */
5859 REG_WR(sc, hw_lock_control_reg + 4, resource_bit);
5860 lock_status = REG_RD(sc, hw_lock_control_reg);
5861 if (lock_status & resource_bit) {
5865 PMD_DRV_LOG(NOTICE, sc, "Failed to get a resource lock 0x%x", resource);
5871 * Get the recovery leader resource id according to the engine this function
5872 * belongs to. Currently only only 2 engines is supported.
5874 static int bnx2x_get_leader_lock_resource(struct bnx2x_softc *sc)
5877 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
5879 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
5883 /* try to acquire a leader lock for current engine */
5884 static uint8_t bnx2x_trylock_leader_lock(struct bnx2x_softc *sc)
5886 return bnx2x_trylock_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5889 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc)
5891 return bnx2x_release_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5894 /* close gates #2, #3 and #4 */
5895 static void bnx2x_set_234_gates(struct bnx2x_softc *sc, uint8_t close)
5899 /* gates #2 and #4a are closed/opened */
5901 REG_WR(sc, PXP_REG_HST_DISCARD_DOORBELLS, ! !close);
5903 REG_WR(sc, PXP_REG_HST_DISCARD_INTERNAL_WRITES, ! !close);
5906 if (CHIP_IS_E1x(sc)) {
5907 /* prevent interrupts from HC on both ports */
5908 val = REG_RD(sc, HC_REG_CONFIG_1);
5910 REG_WR(sc, HC_REG_CONFIG_1, (val & ~(uint32_t)
5911 HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5913 REG_WR(sc, HC_REG_CONFIG_1,
5914 (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5916 val = REG_RD(sc, HC_REG_CONFIG_0);
5918 REG_WR(sc, HC_REG_CONFIG_0, (val & ~(uint32_t)
5919 HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5921 REG_WR(sc, HC_REG_CONFIG_0,
5922 (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5925 /* Prevent incoming interrupts in IGU */
5926 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
5929 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5931 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5933 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5935 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5941 /* poll for pending writes bit, it should get cleared in no more than 1s */
5942 static int bnx2x_er_poll_igu_vq(struct bnx2x_softc *sc)
5944 uint32_t cnt = 1000;
5945 uint32_t pend_bits = 0;
5948 pend_bits = REG_RD(sc, IGU_REG_PENDING_BITS_STATUS);
5950 if (pend_bits == 0) {
5955 } while (cnt-- > 0);
5958 PMD_DRV_LOG(NOTICE, sc, "Still pending IGU requests bits=0x%08x!",
5966 #define SHARED_MF_CLP_MAGIC 0x80000000 /* 'magic' bit */
5968 static void bnx2x_clp_reset_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
5970 /* Do some magic... */
5971 uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
5972 *magic_val = val & SHARED_MF_CLP_MAGIC;
5973 MFCFG_WR(sc, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
5976 /* restore the value of the 'magic' bit */
5977 static void bnx2x_clp_reset_done(struct bnx2x_softc *sc, uint32_t magic_val)
5979 /* Restore the 'magic' bit value... */
5980 uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
5981 MFCFG_WR(sc, shared_mf_config.clp_mb,
5982 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
5985 /* prepare for MCP reset, takes care of CLP configurations */
5986 static void bnx2x_reset_mcp_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
5989 uint32_t validity_offset;
5991 /* set `magic' bit in order to save MF config */
5992 bnx2x_clp_reset_prep(sc, magic_val);
5994 /* get shmem offset */
5995 shmem = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
5997 offsetof(struct shmem_region, validity_map[SC_PORT(sc)]);
5999 /* Clear validity map flags */
6001 REG_WR(sc, shmem + validity_offset, 0);
6005 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
6006 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
6008 static void bnx2x_mcp_wait_one(struct bnx2x_softc *sc)
6010 /* special handling for emulation and FPGA (10 times longer) */
6011 if (CHIP_REV_IS_SLOW(sc)) {
6012 DELAY((MCP_ONE_TIMEOUT * 10) * 1000);
6014 DELAY((MCP_ONE_TIMEOUT) * 1000);
6018 /* initialize shmem_base and waits for validity signature to appear */
6019 static int bnx2x_init_shmem(struct bnx2x_softc *sc)
6025 sc->devinfo.shmem_base =
6026 sc->link_params.shmem_base =
6027 REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
6029 if (sc->devinfo.shmem_base) {
6030 val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
6031 if (val & SHR_MEM_VALIDITY_MB)
6035 bnx2x_mcp_wait_one(sc);
6037 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
6039 PMD_DRV_LOG(NOTICE, sc, "BAD MCP validity signature");
6044 static int bnx2x_reset_mcp_comp(struct bnx2x_softc *sc, uint32_t magic_val)
6046 int rc = bnx2x_init_shmem(sc);
6048 /* Restore the `magic' bit value */
6049 bnx2x_clp_reset_done(sc, magic_val);
6054 static void bnx2x_pxp_prep(struct bnx2x_softc *sc)
6056 REG_WR(sc, PXP2_REG_RD_START_INIT, 0);
6057 REG_WR(sc, PXP2_REG_RQ_RBC_DONE, 0);
6062 * Reset the whole chip except for:
6064 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by one reset bit)
6066 * - MISC (including AEU)
6070 static void bnx2x_process_kill_chip_reset(struct bnx2x_softc *sc, uint8_t global)
6072 uint32_t not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
6073 uint32_t global_bits2, stay_reset2;
6076 * Bits that have to be set in reset_mask2 if we want to reset 'global'
6077 * (per chip) blocks.
6080 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
6081 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
6084 * Don't reset the following blocks.
6085 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
6086 * reset, as in 4 port device they might still be owned
6087 * by the MCP (there is only one leader per path).
6090 MISC_REGISTERS_RESET_REG_1_RST_HC |
6091 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
6092 MISC_REGISTERS_RESET_REG_1_RST_PXP;
6095 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
6096 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
6097 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
6098 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
6099 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
6100 MISC_REGISTERS_RESET_REG_2_RST_GRC |
6101 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
6102 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
6103 MISC_REGISTERS_RESET_REG_2_RST_ATC |
6104 MISC_REGISTERS_RESET_REG_2_PGLC |
6105 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
6106 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
6107 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
6108 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
6109 MISC_REGISTERS_RESET_REG_2_UMAC0 | MISC_REGISTERS_RESET_REG_2_UMAC1;
6112 * Keep the following blocks in reset:
6113 * - all xxMACs are handled by the elink code.
6116 MISC_REGISTERS_RESET_REG_2_XMAC |
6117 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
6119 /* Full reset masks according to the chip */
6120 reset_mask1 = 0xffffffff;
6122 if (CHIP_IS_E1H(sc))
6123 reset_mask2 = 0x1ffff;
6124 else if (CHIP_IS_E2(sc))
6125 reset_mask2 = 0xfffff;
6126 else /* CHIP_IS_E3 */
6127 reset_mask2 = 0x3ffffff;
6129 /* Don't reset global blocks unless we need to */
6131 reset_mask2 &= ~global_bits2;
6134 * In case of attention in the QM, we need to reset PXP
6135 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
6136 * because otherwise QM reset would release 'close the gates' shortly
6137 * before resetting the PXP, then the PSWRQ would send a write
6138 * request to PGLUE. Then when PXP is reset, PGLUE would try to
6139 * read the payload data from PSWWR, but PSWWR would not
6140 * respond. The write queue in PGLUE would stuck, dmae commands
6141 * would not return. Therefore it's important to reset the second
6142 * reset register (containing the
6143 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
6144 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
6147 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
6148 reset_mask2 & (~not_reset_mask2));
6150 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6151 reset_mask1 & (~not_reset_mask1));
6156 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
6157 reset_mask2 & (~stay_reset2));
6162 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
6166 static int bnx2x_process_kill(struct bnx2x_softc *sc, uint8_t global)
6170 uint32_t sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
6171 uint32_t tags_63_32 = 0;
6173 /* Empty the Tetris buffer, wait for 1s */
6175 sr_cnt = REG_RD(sc, PXP2_REG_RD_SR_CNT);
6176 blk_cnt = REG_RD(sc, PXP2_REG_RD_BLK_CNT);
6177 port_is_idle_0 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_0);
6178 port_is_idle_1 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_1);
6179 pgl_exp_rom2 = REG_RD(sc, PXP2_REG_PGL_EXP_ROM2);
6180 if (CHIP_IS_E3(sc)) {
6181 tags_63_32 = REG_RD(sc, PGLUE_B_REG_TAGS_63_32);
6184 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
6185 ((port_is_idle_0 & 0x1) == 0x1) &&
6186 ((port_is_idle_1 & 0x1) == 0x1) &&
6187 (pgl_exp_rom2 == 0xffffffff) &&
6188 (!CHIP_IS_E3(sc) || (tags_63_32 == 0xffffffff)))
6191 } while (cnt-- > 0);
6194 PMD_DRV_LOG(NOTICE, sc,
6195 "ERROR: Tetris buffer didn't get empty or there "
6196 "are still outstanding read requests after 1s! "
6197 "sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, "
6198 "port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x",
6199 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
6206 /* Close gates #2, #3 and #4 */
6207 bnx2x_set_234_gates(sc, TRUE);
6209 /* Poll for IGU VQs for 57712 and newer chips */
6210 if (!CHIP_IS_E1x(sc) && bnx2x_er_poll_igu_vq(sc)) {
6214 /* clear "unprepared" bit */
6215 REG_WR(sc, MISC_REG_UNPREPARED, 0);
6218 /* Make sure all is written to the chip before the reset */
6222 * Wait for 1ms to empty GLUE and PCI-E core queues,
6223 * PSWHST, GRC and PSWRD Tetris buffer.
6227 /* Prepare to chip reset: */
6230 bnx2x_reset_mcp_prep(sc, &val);
6237 /* reset the chip */
6238 bnx2x_process_kill_chip_reset(sc, global);
6241 /* Recover after reset: */
6243 if (global && bnx2x_reset_mcp_comp(sc, val)) {
6247 /* Open the gates #2, #3 and #4 */
6248 bnx2x_set_234_gates(sc, FALSE);
6253 static int bnx2x_leader_reset(struct bnx2x_softc *sc)
6256 uint8_t global = bnx2x_reset_is_global(sc);
6260 * If not going to reset MCP, load "fake" driver to reset HW while
6261 * driver is owner of the HW.
6263 if (!global && !BNX2X_NOMCP(sc)) {
6264 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
6265 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
6267 PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
6269 goto exit_leader_reset;
6272 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
6273 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
6274 PMD_DRV_LOG(NOTICE, sc,
6275 "MCP unexpected response, aborting");
6277 goto exit_leader_reset2;
6280 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
6282 PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
6284 goto exit_leader_reset2;
6288 /* try to recover after the failure */
6289 if (bnx2x_process_kill(sc, global)) {
6290 PMD_DRV_LOG(NOTICE, sc, "Something bad occurred on engine %d!",
6293 goto exit_leader_reset2;
6297 * Clear the RESET_IN_PROGRESS and RESET_GLOBAL bits and update the driver
6300 bnx2x_set_reset_done(sc);
6302 bnx2x_clear_reset_global(sc);
6307 /* unload "fake driver" if it was loaded */
6308 if (!global &&!BNX2X_NOMCP(sc)) {
6309 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
6310 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
6316 bnx2x_release_leader_lock(sc);
6323 * prepare INIT transition, parameters configured:
6324 * - HC configuration
6325 * - Queue's CDU context
6328 bnx2x_pf_q_prep_init(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6329 struct ecore_queue_init_params *init_params)
6332 int cxt_index, cxt_offset;
6334 bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->rx.flags);
6335 bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->tx.flags);
6337 bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->rx.flags);
6338 bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->tx.flags);
6341 init_params->rx.hc_rate =
6342 sc->hc_rx_ticks ? (1000000 / sc->hc_rx_ticks) : 0;
6343 init_params->tx.hc_rate =
6344 sc->hc_tx_ticks ? (1000000 / sc->hc_tx_ticks) : 0;
6347 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = fp->fw_sb_id;
6349 /* CQ index among the SB indices */
6350 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6351 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
6353 /* set maximum number of COSs supported by this queue */
6354 init_params->max_cos = sc->max_cos;
6356 /* set the context pointers queue object */
6357 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
6358 cxt_index = fp->index / ILT_PAGE_CIDS;
6359 cxt_offset = fp->index - (cxt_index * ILT_PAGE_CIDS);
6360 init_params->cxts[cos] =
6361 &sc->context[cxt_index].vcxt[cxt_offset].eth;
6365 /* set flags that are common for the Tx-only and not normal connections */
6366 static unsigned long
6367 bnx2x_get_common_flags(struct bnx2x_softc *sc, uint8_t zero_stats)
6369 unsigned long flags = 0;
6371 /* PF driver will always initialize the Queue to an ACTIVE state */
6372 bnx2x_set_bit(ECORE_Q_FLG_ACTIVE, &flags);
6375 * tx only connections collect statistics (on the same index as the
6376 * parent connection). The statistics are zeroed when the parent
6377 * connection is initialized.
6380 bnx2x_set_bit(ECORE_Q_FLG_STATS, &flags);
6382 bnx2x_set_bit(ECORE_Q_FLG_ZERO_STATS, &flags);
6386 * tx only connections can support tx-switching, though their
6387 * CoS-ness doesn't survive the loopback
6389 if (sc->flags & BNX2X_TX_SWITCHING) {
6390 bnx2x_set_bit(ECORE_Q_FLG_TX_SWITCH, &flags);
6393 bnx2x_set_bit(ECORE_Q_FLG_PCSUM_ON_PKT, &flags);
6398 static unsigned long bnx2x_get_q_flags(struct bnx2x_softc *sc, uint8_t leading)
6400 unsigned long flags = 0;
6403 bnx2x_set_bit(ECORE_Q_FLG_OV, &flags);
6407 bnx2x_set_bit(ECORE_Q_FLG_LEADING_RSS, &flags);
6408 bnx2x_set_bit(ECORE_Q_FLG_MCAST, &flags);
6411 bnx2x_set_bit(ECORE_Q_FLG_VLAN, &flags);
6413 /* merge with common flags */
6414 return flags | bnx2x_get_common_flags(sc, TRUE);
6418 bnx2x_pf_q_prep_general(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6419 struct ecore_general_setup_params *gen_init, uint8_t cos)
6421 gen_init->stat_id = bnx2x_stats_id(fp);
6422 gen_init->spcl_id = fp->cl_id;
6423 gen_init->mtu = sc->mtu;
6424 gen_init->cos = cos;
6428 bnx2x_pf_rx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6429 struct rxq_pause_params *pause,
6430 struct ecore_rxq_setup_params *rxq_init)
6432 struct bnx2x_rx_queue *rxq;
6434 rxq = sc->rx_queues[fp->index];
6436 PMD_RX_LOG(ERR, "RX queue is NULL");
6440 pause->bd_th_lo = BD_TH_LO(sc);
6441 pause->bd_th_hi = BD_TH_HI(sc);
6443 pause->rcq_th_lo = RCQ_TH_LO(sc);
6444 pause->rcq_th_hi = RCQ_TH_HI(sc);
6446 /* validate rings have enough entries to cross high thresholds */
6447 if (sc->dropless_fc &&
6448 pause->bd_th_hi + FW_PREFETCH_CNT > sc->rx_ring_size) {
6449 PMD_DRV_LOG(WARNING, sc, "rx bd ring threshold limit");
6452 if (sc->dropless_fc &&
6453 pause->rcq_th_hi + FW_PREFETCH_CNT > USABLE_RCQ_ENTRIES(rxq)) {
6454 PMD_DRV_LOG(WARNING, sc, "rcq ring threshold limit");
6460 rxq_init->dscr_map = (rte_iova_t)rxq->rx_ring_phys_addr;
6461 rxq_init->rcq_map = (rte_iova_t)rxq->cq_ring_phys_addr;
6462 rxq_init->rcq_np_map = (rte_iova_t)(rxq->cq_ring_phys_addr +
6466 * This should be a maximum number of data bytes that may be
6467 * placed on the BD (not including paddings).
6469 rxq_init->buf_sz = (fp->rx_buf_size - IP_HEADER_ALIGNMENT_PADDING);
6471 rxq_init->cl_qzone_id = fp->cl_qzone_id;
6472 rxq_init->rss_engine_id = SC_FUNC(sc);
6473 rxq_init->mcast_engine_id = SC_FUNC(sc);
6475 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
6476 rxq_init->fw_sb_id = fp->fw_sb_id;
6478 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6481 * configure silent vlan removal
6482 * if multi function mode is afex, then mask default vlan
6484 if (IS_MF_AFEX(sc)) {
6485 rxq_init->silent_removal_value =
6486 sc->devinfo.mf_info.afex_def_vlan_tag;
6487 rxq_init->silent_removal_mask = EVL_VLID_MASK;
6492 bnx2x_pf_tx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6493 struct ecore_txq_setup_params *txq_init, uint8_t cos)
6495 struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
6498 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
6501 txq_init->dscr_map = (rte_iova_t)txq->tx_ring_phys_addr;
6502 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
6503 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
6504 txq_init->fw_sb_id = fp->fw_sb_id;
6507 * set the TSS leading client id for TX classfication to the
6508 * leading RSS client id
6510 txq_init->tss_leading_cl_id = BNX2X_FP(sc, 0, cl_id);
6514 * This function performs 2 steps in a queue state machine:
6519 bnx2x_setup_queue(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp, uint8_t leading)
6521 struct ecore_queue_state_params q_params = { NULL };
6522 struct ecore_queue_setup_params *setup_params = &q_params.params.setup;
6525 PMD_DRV_LOG(DEBUG, sc, "setting up queue %d", fp->index);
6527 bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6529 q_params.q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
6531 /* we want to wait for completion in this context */
6532 bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
6534 /* prepare the INIT parameters */
6535 bnx2x_pf_q_prep_init(sc, fp, &q_params.params.init);
6537 /* Set the command */
6538 q_params.cmd = ECORE_Q_CMD_INIT;
6540 /* Change the state to INIT */
6541 rc = ecore_queue_state_change(sc, &q_params);
6543 PMD_DRV_LOG(NOTICE, sc, "Queue(%d) INIT failed", fp->index);
6547 PMD_DRV_LOG(DEBUG, sc, "init complete");
6549 /* now move the Queue to the SETUP state */
6550 memset(setup_params, 0, sizeof(*setup_params));
6552 /* set Queue flags */
6553 setup_params->flags = bnx2x_get_q_flags(sc, leading);
6555 /* set general SETUP parameters */
6556 bnx2x_pf_q_prep_general(sc, fp, &setup_params->gen_params,
6557 FIRST_TX_COS_INDEX);
6559 bnx2x_pf_rx_q_prep(sc, fp,
6560 &setup_params->pause_params,
6561 &setup_params->rxq_params);
6563 bnx2x_pf_tx_q_prep(sc, fp, &setup_params->txq_params, FIRST_TX_COS_INDEX);
6565 /* Set the command */
6566 q_params.cmd = ECORE_Q_CMD_SETUP;
6568 /* change the state to SETUP */
6569 rc = ecore_queue_state_change(sc, &q_params);
6571 PMD_DRV_LOG(NOTICE, sc, "Queue(%d) SETUP failed", fp->index);
6578 static int bnx2x_setup_leading(struct bnx2x_softc *sc)
6581 return bnx2x_setup_queue(sc, &sc->fp[0], TRUE);
6583 return bnx2x_vf_setup_queue(sc, &sc->fp[0], TRUE);
6587 bnx2x_config_rss_pf(struct bnx2x_softc *sc, struct ecore_rss_config_obj *rss_obj,
6588 uint8_t config_hash)
6590 struct ecore_config_rss_params params = { NULL };
6594 * Although RSS is meaningless when there is a single HW queue we
6595 * still need it enabled in order to have HW Rx hash generated.
6598 params.rss_obj = rss_obj;
6600 bnx2x_set_bit(RAMROD_COMP_WAIT, ¶ms.ramrod_flags);
6602 bnx2x_set_bit(ECORE_RSS_MODE_REGULAR, ¶ms.rss_flags);
6604 /* RSS configuration */
6605 bnx2x_set_bit(ECORE_RSS_IPV4, ¶ms.rss_flags);
6606 bnx2x_set_bit(ECORE_RSS_IPV4_TCP, ¶ms.rss_flags);
6607 bnx2x_set_bit(ECORE_RSS_IPV6, ¶ms.rss_flags);
6608 bnx2x_set_bit(ECORE_RSS_IPV6_TCP, ¶ms.rss_flags);
6609 if (rss_obj->udp_rss_v4) {
6610 bnx2x_set_bit(ECORE_RSS_IPV4_UDP, ¶ms.rss_flags);
6612 if (rss_obj->udp_rss_v6) {
6613 bnx2x_set_bit(ECORE_RSS_IPV6_UDP, ¶ms.rss_flags);
6617 params.rss_result_mask = MULTI_MASK;
6619 rte_memcpy(params.ind_table, rss_obj->ind_table,
6620 sizeof(params.ind_table));
6624 for (i = 0; i < sizeof(params.rss_key) / 4; i++) {
6625 params.rss_key[i] = (uint32_t) rte_rand();
6628 bnx2x_set_bit(ECORE_RSS_SET_SRCH, ¶ms.rss_flags);
6632 return ecore_config_rss(sc, ¶ms);
6634 return bnx2x_vf_config_rss(sc, ¶ms);
6637 static int bnx2x_config_rss_eth(struct bnx2x_softc *sc, uint8_t config_hash)
6639 return bnx2x_config_rss_pf(sc, &sc->rss_conf_obj, config_hash);
6642 static int bnx2x_init_rss_pf(struct bnx2x_softc *sc)
6644 uint8_t num_eth_queues = BNX2X_NUM_ETH_QUEUES(sc);
6648 * Prepare the initial contents of the indirection table if
6651 for (i = 0; i < sizeof(sc->rss_conf_obj.ind_table); i++) {
6652 sc->rss_conf_obj.ind_table[i] =
6653 (sc->fp->cl_id + (i % num_eth_queues));
6657 sc->rss_conf_obj.udp_rss_v4 = sc->rss_conf_obj.udp_rss_v6 = 1;
6661 * For 57711 SEARCHER configuration (rss_keys) is
6662 * per-port, so if explicit configuration is needed, do it only
6665 * For 57712 and newer it's a per-function configuration.
6667 return bnx2x_config_rss_eth(sc, sc->port.pmf || !CHIP_IS_E1x(sc));
6671 bnx2x_set_mac_one(struct bnx2x_softc *sc, uint8_t * mac,
6672 struct ecore_vlan_mac_obj *obj, uint8_t set, int mac_type,
6673 unsigned long *ramrod_flags)
6675 struct ecore_vlan_mac_ramrod_params ramrod_param;
6678 memset(&ramrod_param, 0, sizeof(ramrod_param));
6680 /* fill in general parameters */
6681 ramrod_param.vlan_mac_obj = obj;
6682 ramrod_param.ramrod_flags = *ramrod_flags;
6684 /* fill a user request section if needed */
6685 if (!bnx2x_test_bit(RAMROD_CONT, ramrod_flags)) {
6686 rte_memcpy(ramrod_param.user_req.u.mac.mac, mac,
6689 bnx2x_set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
6691 /* Set the command: ADD or DEL */
6692 ramrod_param.user_req.cmd = (set) ? ECORE_VLAN_MAC_ADD :
6696 rc = ecore_config_vlan_mac(sc, &ramrod_param);
6698 if (rc == ECORE_EXISTS) {
6699 PMD_DRV_LOG(INFO, sc, "Failed to schedule ADD operations (EEXIST)");
6700 /* do not treat adding same MAC as error */
6702 } else if (rc < 0) {
6703 PMD_DRV_LOG(ERR, sc,
6704 "%s MAC failed (%d)", (set ? "Set" : "Delete"), rc);
6710 static int bnx2x_set_eth_mac(struct bnx2x_softc *sc, uint8_t set)
6712 unsigned long ramrod_flags = 0;
6714 PMD_DRV_LOG(DEBUG, sc, "Adding Ethernet MAC");
6716 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
6718 /* Eth MAC is set on RSS leading client (fp[0]) */
6719 return bnx2x_set_mac_one(sc, sc->link_params.mac_addr,
6720 &sc->sp_objs->mac_obj,
6721 set, ECORE_ETH_MAC, &ramrod_flags);
6724 static int bnx2x_get_cur_phy_idx(struct bnx2x_softc *sc)
6726 uint32_t sel_phy_idx = 0;
6728 if (sc->link_params.num_phys <= 1) {
6729 return ELINK_INT_PHY;
6732 if (sc->link_vars.link_up) {
6733 sel_phy_idx = ELINK_EXT_PHY1;
6734 /* In case link is SERDES, check if the ELINK_EXT_PHY2 is the one */
6735 if ((sc->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
6736 (sc->link_params.phy[ELINK_EXT_PHY2].supported &
6737 ELINK_SUPPORTED_FIBRE))
6738 sel_phy_idx = ELINK_EXT_PHY2;
6740 switch (elink_phy_selection(&sc->link_params)) {
6741 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6742 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
6743 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6744 sel_phy_idx = ELINK_EXT_PHY1;
6746 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
6747 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6748 sel_phy_idx = ELINK_EXT_PHY2;
6756 static int bnx2x_get_link_cfg_idx(struct bnx2x_softc *sc)
6758 uint32_t sel_phy_idx = bnx2x_get_cur_phy_idx(sc);
6761 * The selected activated PHY is always after swapping (in case PHY
6762 * swapping is enabled). So when swapping is enabled, we need to reverse
6766 if (sc->link_params.multi_phy_config & PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
6767 if (sel_phy_idx == ELINK_EXT_PHY1)
6768 sel_phy_idx = ELINK_EXT_PHY2;
6769 else if (sel_phy_idx == ELINK_EXT_PHY2)
6770 sel_phy_idx = ELINK_EXT_PHY1;
6773 return ELINK_LINK_CONFIG_IDX(sel_phy_idx);
6776 static void bnx2x_set_requested_fc(struct bnx2x_softc *sc)
6779 * Initialize link parameters structure variables
6780 * It is recommended to turn off RX FC for jumbo frames
6781 * for better performance
6783 if (CHIP_IS_E1x(sc) && (sc->mtu > 5000)) {
6784 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_TX;
6786 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_BOTH;
6790 static void bnx2x_calc_fc_adv(struct bnx2x_softc *sc)
6792 uint8_t cfg_idx = bnx2x_get_link_cfg_idx(sc);
6793 switch (sc->link_vars.ieee_fc &
6794 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
6795 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
6797 sc->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
6801 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
6802 sc->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
6806 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
6807 sc->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
6812 static uint16_t bnx2x_get_mf_speed(struct bnx2x_softc *sc)
6814 uint16_t line_speed = sc->link_vars.line_speed;
6816 uint16_t maxCfg = bnx2x_extract_max_cfg(sc,
6818 mf_info.mf_config[SC_VN
6821 /* calculate the current MAX line speed limit for the MF devices */
6823 line_speed = (line_speed * maxCfg) / 100;
6824 } else { /* SD mode */
6825 uint16_t vn_max_rate = maxCfg * 100;
6827 if (vn_max_rate < line_speed) {
6828 line_speed = vn_max_rate;
6837 bnx2x_fill_report_data(struct bnx2x_softc *sc, struct bnx2x_link_report_data *data)
6839 uint16_t line_speed = bnx2x_get_mf_speed(sc);
6841 memset(data, 0, sizeof(*data));
6843 /* fill the report data with the effective line speed */
6844 data->line_speed = line_speed;
6847 if (!sc->link_vars.link_up || (sc->flags & BNX2X_MF_FUNC_DIS)) {
6848 bnx2x_set_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6849 &data->link_report_flags);
6853 if (sc->link_vars.duplex == DUPLEX_FULL) {
6854 bnx2x_set_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6855 &data->link_report_flags);
6858 /* Rx Flow Control is ON */
6859 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_RX) {
6860 bnx2x_set_bit(BNX2X_LINK_REPORT_RX_FC_ON, &data->link_report_flags);
6863 /* Tx Flow Control is ON */
6864 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
6865 bnx2x_set_bit(BNX2X_LINK_REPORT_TX_FC_ON, &data->link_report_flags);
6869 /* report link status to OS, should be called under phy_lock */
6870 static void bnx2x_link_report(struct bnx2x_softc *sc)
6872 struct bnx2x_link_report_data cur_data;
6876 bnx2x_read_mf_cfg(sc);
6879 /* Read the current link report info */
6880 bnx2x_fill_report_data(sc, &cur_data);
6882 /* Don't report link down or exactly the same link status twice */
6883 if (!memcmp(&cur_data, &sc->last_reported_link, sizeof(cur_data)) ||
6884 (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6885 &sc->last_reported_link.link_report_flags) &&
6886 bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6887 &cur_data.link_report_flags))) {
6893 /* report new link params and remember the state for the next time */
6894 rte_memcpy(&sc->last_reported_link, &cur_data, sizeof(cur_data));
6896 if (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6897 &cur_data.link_report_flags)) {
6898 PMD_DRV_LOG(INFO, sc, "NIC Link is Down");
6900 __rte_unused const char *duplex;
6901 __rte_unused const char *flow;
6903 if (bnx2x_test_and_clear_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6904 &cur_data.link_report_flags)) {
6911 * Handle the FC at the end so that only these flags would be
6912 * possibly set. This way we may easily check if there is no FC
6915 if (cur_data.link_report_flags) {
6916 if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6917 &cur_data.link_report_flags) &&
6918 bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6919 &cur_data.link_report_flags)) {
6920 flow = "ON - receive & transmit";
6921 } else if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6922 &cur_data.link_report_flags) &&
6923 !bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6924 &cur_data.link_report_flags)) {
6925 flow = "ON - receive";
6926 } else if (!bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6927 &cur_data.link_report_flags) &&
6928 bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6929 &cur_data.link_report_flags)) {
6930 flow = "ON - transmit";
6932 flow = "none"; /* possible? */
6938 PMD_DRV_LOG(INFO, sc,
6939 "NIC Link is Up, %d Mbps %s duplex, Flow control: %s",
6940 cur_data.line_speed, duplex, flow);
6944 void bnx2x_link_status_update(struct bnx2x_softc *sc)
6946 if (sc->state != BNX2X_STATE_OPEN) {
6950 if (IS_PF(sc) && !CHIP_REV_IS_SLOW(sc)) {
6951 elink_link_status_update(&sc->link_params, &sc->link_vars);
6953 sc->port.supported[0] |= (ELINK_SUPPORTED_10baseT_Half |
6954 ELINK_SUPPORTED_10baseT_Full |
6955 ELINK_SUPPORTED_100baseT_Half |
6956 ELINK_SUPPORTED_100baseT_Full |
6957 ELINK_SUPPORTED_1000baseT_Full |
6958 ELINK_SUPPORTED_2500baseX_Full |
6959 ELINK_SUPPORTED_10000baseT_Full |
6960 ELINK_SUPPORTED_TP |
6961 ELINK_SUPPORTED_FIBRE |
6962 ELINK_SUPPORTED_Autoneg |
6963 ELINK_SUPPORTED_Pause |
6964 ELINK_SUPPORTED_Asym_Pause);
6965 sc->port.advertising[0] = sc->port.supported[0];
6967 sc->link_params.sc = sc;
6968 sc->link_params.port = SC_PORT(sc);
6969 sc->link_params.req_duplex[0] = DUPLEX_FULL;
6970 sc->link_params.req_flow_ctrl[0] = ELINK_FLOW_CTRL_NONE;
6971 sc->link_params.req_line_speed[0] = SPEED_10000;
6972 sc->link_params.speed_cap_mask[0] = 0x7f0000;
6973 sc->link_params.switch_cfg = ELINK_SWITCH_CFG_10G;
6975 if (CHIP_REV_IS_FPGA(sc)) {
6976 sc->link_vars.mac_type = ELINK_MAC_TYPE_EMAC;
6977 sc->link_vars.line_speed = ELINK_SPEED_1000;
6978 sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
6979 LINK_STATUS_SPEED_AND_DUPLEX_1000TFD);
6981 sc->link_vars.mac_type = ELINK_MAC_TYPE_BMAC;
6982 sc->link_vars.line_speed = ELINK_SPEED_10000;
6983 sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
6984 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
6987 sc->link_vars.link_up = 1;
6989 sc->link_vars.duplex = DUPLEX_FULL;
6990 sc->link_vars.flow_ctrl = ELINK_FLOW_CTRL_NONE;
6994 NIG_REG_EGRESS_DRAIN0_MODE +
6995 sc->link_params.port * 4, 0);
6996 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
6997 bnx2x_link_report(sc);
7002 if (sc->link_vars.link_up) {
7003 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7005 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
7007 bnx2x_link_report(sc);
7009 bnx2x_link_report(sc);
7010 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7014 static int bnx2x_initial_phy_init(struct bnx2x_softc *sc, int load_mode)
7016 int rc, cfg_idx = bnx2x_get_link_cfg_idx(sc);
7017 uint16_t req_line_speed = sc->link_params.req_line_speed[cfg_idx];
7018 struct elink_params *lp = &sc->link_params;
7020 bnx2x_set_requested_fc(sc);
7022 if (load_mode == LOAD_DIAG) {
7023 lp->loopback_mode = ELINK_LOOPBACK_XGXS;
7024 /* Prefer doing PHY loopback at 10G speed, if possible */
7025 if (lp->req_line_speed[cfg_idx] < ELINK_SPEED_10000) {
7026 if (lp->speed_cap_mask[cfg_idx] &
7027 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
7028 lp->req_line_speed[cfg_idx] = ELINK_SPEED_10000;
7030 lp->req_line_speed[cfg_idx] = ELINK_SPEED_1000;
7035 if (load_mode == LOAD_LOOPBACK_EXT) {
7036 lp->loopback_mode = ELINK_LOOPBACK_EXT;
7039 rc = elink_phy_init(&sc->link_params, &sc->link_vars);
7041 bnx2x_calc_fc_adv(sc);
7043 if (sc->link_vars.link_up) {
7044 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7045 bnx2x_link_report(sc);
7048 sc->link_params.req_line_speed[cfg_idx] = req_line_speed;
7052 /* update flags in shmem */
7054 bnx2x_update_drv_flags(struct bnx2x_softc *sc, uint32_t flags, uint32_t set)
7058 if (SHMEM2_HAS(sc, drv_flags)) {
7059 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7060 drv_flags = SHMEM2_RD(sc, drv_flags);
7065 drv_flags &= ~flags;
7068 SHMEM2_WR(sc, drv_flags, drv_flags);
7070 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7074 /* periodic timer callout routine, only runs when the interface is up */
7075 void bnx2x_periodic_callout(struct bnx2x_softc *sc)
7077 if ((sc->state != BNX2X_STATE_OPEN) ||
7078 (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_STOP)) {
7079 PMD_DRV_LOG(INFO, sc, "periodic callout exit (state=0x%x)",
7083 if (!CHIP_REV_IS_SLOW(sc)) {
7085 * This barrier is needed to ensure the ordering between the writing
7086 * to the sc->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
7091 elink_period_func(&sc->link_params, &sc->link_vars);
7095 if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7096 int mb_idx = SC_FW_MB_IDX(sc);
7100 ++sc->fw_drv_pulse_wr_seq;
7101 sc->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
7103 drv_pulse = sc->fw_drv_pulse_wr_seq;
7104 bnx2x_drv_pulse(sc);
7106 mcp_pulse = (SHMEM_RD(sc, func_mb[mb_idx].mcp_pulse_mb) &
7107 MCP_PULSE_SEQ_MASK);
7110 * The delta between driver pulse and mcp response should
7111 * be 1 (before mcp response) or 0 (after mcp response).
7113 if ((drv_pulse != mcp_pulse) &&
7114 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
7115 /* someone lost a heartbeat... */
7116 PMD_DRV_LOG(ERR, sc,
7117 "drv_pulse (0x%x) != mcp_pulse (0x%x)",
7118 drv_pulse, mcp_pulse);
7124 /* start the controller */
7125 static __rte_noinline
7126 int bnx2x_nic_load(struct bnx2x_softc *sc)
7129 uint32_t load_code = 0;
7132 PMD_INIT_FUNC_TRACE(sc);
7134 sc->state = BNX2X_STATE_OPENING_WAITING_LOAD;
7137 /* must be called before memory allocation and HW init */
7138 bnx2x_ilt_set_info(sc);
7141 bnx2x_set_fp_rx_buf_size(sc);
7144 if (bnx2x_alloc_mem(sc) != 0) {
7145 sc->state = BNX2X_STATE_CLOSED;
7147 goto bnx2x_nic_load_error0;
7151 if (bnx2x_alloc_fw_stats_mem(sc) != 0) {
7152 sc->state = BNX2X_STATE_CLOSED;
7154 goto bnx2x_nic_load_error0;
7158 rc = bnx2x_vf_init(sc);
7160 sc->state = BNX2X_STATE_ERROR;
7161 goto bnx2x_nic_load_error0;
7166 /* set pf load just before approaching the MCP */
7167 bnx2x_set_pf_load(sc);
7169 /* if MCP exists send load request and analyze response */
7170 if (!BNX2X_NOMCP(sc)) {
7171 /* attempt to load pf */
7172 if (bnx2x_nic_load_request(sc, &load_code) != 0) {
7173 sc->state = BNX2X_STATE_CLOSED;
7175 goto bnx2x_nic_load_error1;
7178 /* what did the MCP say? */
7179 if (bnx2x_nic_load_analyze_req(sc, load_code) != 0) {
7180 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7181 sc->state = BNX2X_STATE_CLOSED;
7183 goto bnx2x_nic_load_error2;
7186 PMD_DRV_LOG(INFO, sc, "Device has no MCP!");
7187 load_code = bnx2x_nic_load_no_mcp(sc);
7190 /* mark PMF if applicable */
7191 bnx2x_nic_load_pmf(sc, load_code);
7193 /* Init Function state controlling object */
7194 bnx2x_init_func_obj(sc);
7197 if (bnx2x_init_hw(sc, load_code) != 0) {
7198 PMD_DRV_LOG(NOTICE, sc, "HW init failed");
7199 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7200 sc->state = BNX2X_STATE_CLOSED;
7202 goto bnx2x_nic_load_error2;
7206 bnx2x_nic_init(sc, load_code);
7208 /* Init per-function objects */
7210 bnx2x_init_objs(sc);
7212 /* set AFEX default VLAN tag to an invalid value */
7213 sc->devinfo.mf_info.afex_def_vlan_tag = -1;
7215 sc->state = BNX2X_STATE_OPENING_WAITING_PORT;
7216 rc = bnx2x_func_start(sc);
7218 PMD_DRV_LOG(NOTICE, sc, "Function start failed!");
7219 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7220 sc->state = BNX2X_STATE_ERROR;
7221 goto bnx2x_nic_load_error3;
7224 /* send LOAD_DONE command to MCP */
7225 if (!BNX2X_NOMCP(sc)) {
7227 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7229 PMD_DRV_LOG(NOTICE, sc,
7230 "MCP response failure, aborting");
7231 sc->state = BNX2X_STATE_ERROR;
7233 goto bnx2x_nic_load_error3;
7238 rc = bnx2x_setup_leading(sc);
7240 PMD_DRV_LOG(NOTICE, sc, "Setup leading failed!");
7241 sc->state = BNX2X_STATE_ERROR;
7242 goto bnx2x_nic_load_error3;
7245 FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, i) {
7247 rc = bnx2x_setup_queue(sc, &sc->fp[i], FALSE);
7248 else /* IS_VF(sc) */
7249 rc = bnx2x_vf_setup_queue(sc, &sc->fp[i], FALSE);
7252 PMD_DRV_LOG(NOTICE, sc, "Queue(%d) setup failed", i);
7253 sc->state = BNX2X_STATE_ERROR;
7254 goto bnx2x_nic_load_error3;
7258 rc = bnx2x_init_rss_pf(sc);
7260 PMD_DRV_LOG(NOTICE, sc, "PF RSS init failed");
7261 sc->state = BNX2X_STATE_ERROR;
7262 goto bnx2x_nic_load_error3;
7265 /* now when Clients are configured we are ready to work */
7266 sc->state = BNX2X_STATE_OPEN;
7268 /* Configure a ucast MAC */
7270 rc = bnx2x_set_eth_mac(sc, TRUE);
7271 } else { /* IS_VF(sc) */
7272 rc = bnx2x_vf_set_mac(sc, TRUE);
7276 PMD_DRV_LOG(NOTICE, sc, "Setting Ethernet MAC failed");
7277 sc->state = BNX2X_STATE_ERROR;
7278 goto bnx2x_nic_load_error3;
7282 rc = bnx2x_initial_phy_init(sc, LOAD_OPEN);
7284 sc->state = BNX2X_STATE_ERROR;
7285 goto bnx2x_nic_load_error3;
7289 sc->link_params.feature_config_flags &=
7290 ~ELINK_FEATURE_CONFIG_BOOT_FROM_SAN;
7293 switch (LOAD_OPEN) {
7299 case LOAD_LOOPBACK_EXT:
7300 sc->state = BNX2X_STATE_DIAG;
7308 bnx2x_update_drv_flags(sc, 1 << DRV_FLAGS_PORT_MASK, 0);
7310 bnx2x_link_status_update(sc);
7313 if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
7314 /* mark driver is loaded in shmem2 */
7315 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
7316 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
7318 DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED |
7319 DRV_FLAGS_CAPABILITIES_LOADED_L2));
7322 /* start fast path */
7323 /* Initialize Rx filter */
7324 bnx2x_set_rx_mode(sc);
7326 /* wait for all pending SP commands to complete */
7327 if (IS_PF(sc) && !bnx2x_wait_sp_comp(sc, ~0x0UL)) {
7328 PMD_DRV_LOG(NOTICE, sc, "Timeout waiting for all SPs to complete!");
7329 bnx2x_periodic_stop(sc);
7330 bnx2x_nic_unload(sc, UNLOAD_CLOSE, FALSE);
7334 PMD_DRV_LOG(DEBUG, sc, "NIC successfully loaded");
7338 bnx2x_nic_load_error3:
7341 bnx2x_int_disable_sync(sc, 1);
7343 /* clean out queued objects */
7344 bnx2x_squeeze_objects(sc);
7347 bnx2x_nic_load_error2:
7349 if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7350 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
7351 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
7356 bnx2x_nic_load_error1:
7358 /* clear pf_load status, as it was already set */
7360 bnx2x_clear_pf_load(sc);
7363 bnx2x_nic_load_error0:
7365 bnx2x_free_fw_stats_mem(sc);
7372 * Handles controller initialization.
7374 int bnx2x_init(struct bnx2x_softc *sc)
7376 int other_engine = SC_PATH(sc) ? 0 : 1;
7377 uint8_t other_load_status, load_status;
7378 uint8_t global = FALSE;
7381 /* Check if the driver is still running and bail out if it is. */
7382 if (sc->state != BNX2X_STATE_CLOSED) {
7383 PMD_DRV_LOG(DEBUG, sc, "Init called while driver is running!");
7385 goto bnx2x_init_done;
7388 bnx2x_set_power_state(sc, PCI_PM_D0);
7391 * If parity occurred during the unload, then attentions and/or
7392 * RECOVERY_IN_PROGRESS may still be set. If so we want the first function
7393 * loaded on the current engine to complete the recovery. Parity recovery
7394 * is only relevant for PF driver.
7397 other_load_status = bnx2x_get_load_status(sc, other_engine);
7398 load_status = bnx2x_get_load_status(sc, SC_PATH(sc));
7400 if (!bnx2x_reset_is_done(sc, SC_PATH(sc)) ||
7401 bnx2x_chk_parity_attn(sc, &global, TRUE)) {
7404 * If there are attentions and they are in global blocks, set
7405 * the GLOBAL_RESET bit regardless whether it will be this
7406 * function that will complete the recovery or not.
7409 bnx2x_set_reset_global(sc);
7413 * Only the first function on the current engine should try
7414 * to recover in open. In case of attentions in global blocks
7415 * only the first in the chip should try to recover.
7418 && (!global ||!other_load_status))
7419 && bnx2x_trylock_leader_lock(sc)
7420 && !bnx2x_leader_reset(sc)) {
7421 PMD_DRV_LOG(INFO, sc,
7422 "Recovered during init");
7426 /* recovery has failed... */
7427 bnx2x_set_power_state(sc, PCI_PM_D3hot);
7429 sc->recovery_state = BNX2X_RECOVERY_FAILED;
7431 PMD_DRV_LOG(NOTICE, sc,
7432 "Recovery flow hasn't properly "
7433 "completed yet, try again later. "
7434 "If you still see this message after a "
7435 "few retries then power cycle is required.");
7438 goto bnx2x_init_done;
7443 sc->recovery_state = BNX2X_RECOVERY_DONE;
7445 rc = bnx2x_nic_load(sc);
7450 PMD_DRV_LOG(NOTICE, sc, "Initialization failed, "
7451 "stack notified driver is NOT running!");
7457 static void bnx2x_get_function_num(struct bnx2x_softc *sc)
7462 * Read the ME register to get the function number. The ME register
7463 * holds the relative-function number and absolute-function number. The
7464 * absolute-function number appears only in E2 and above. Before that
7465 * these bits always contained zero, therefore we cannot blindly use them.
7468 val = REG_RD(sc, BAR_ME_REGISTER);
7471 (uint8_t) ((val & ME_REG_PF_NUM) >> ME_REG_PF_NUM_SHIFT);
7473 (uint8_t) ((val & ME_REG_ABS_PF_NUM) >> ME_REG_ABS_PF_NUM_SHIFT) &
7476 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7477 sc->pfunc_abs = ((sc->pfunc_rel << 1) | sc->path_id);
7479 sc->pfunc_abs = (sc->pfunc_rel | sc->path_id);
7482 PMD_DRV_LOG(DEBUG, sc,
7483 "Relative function %d, Absolute function %d, Path %d",
7484 sc->pfunc_rel, sc->pfunc_abs, sc->path_id);
7487 static uint32_t bnx2x_get_shmem_mf_cfg_base(struct bnx2x_softc *sc)
7489 uint32_t shmem2_size;
7491 uint32_t mf_cfg_offset_value;
7494 offset = (SHMEM_ADDR(sc, func_mb) +
7495 (MAX_FUNC_NUM * sizeof(struct drv_func_mb)));
7498 if (sc->devinfo.shmem2_base != 0) {
7499 shmem2_size = SHMEM2_RD(sc, size);
7500 if (shmem2_size > offsetof(struct shmem2_region, mf_cfg_addr)) {
7501 mf_cfg_offset_value = SHMEM2_RD(sc, mf_cfg_addr);
7502 if (SHMEM_MF_CFG_ADDR_NONE != mf_cfg_offset_value) {
7503 offset = mf_cfg_offset_value;
7511 static uint32_t bnx2x_pcie_capability_read(struct bnx2x_softc *sc, int reg)
7514 struct bnx2x_pci_cap *caps;
7516 /* ensure PCIe capability is enabled */
7517 caps = pci_find_cap(sc, PCIY_EXPRESS, BNX2X_PCI_CAP);
7519 PMD_DRV_LOG(DEBUG, sc, "Found PCIe capability: "
7520 "id=0x%04X type=0x%04X addr=0x%08X",
7521 caps->id, caps->type, caps->addr);
7522 pci_read(sc, (caps->addr + reg), &ret, 2);
7526 PMD_DRV_LOG(WARNING, sc, "PCIe capability NOT FOUND!!!");
7531 static uint8_t bnx2x_is_pcie_pending(struct bnx2x_softc *sc)
7533 return bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_STA) &
7534 PCIM_EXP_STA_TRANSACTION_PND;
7538 * Walk the PCI capabiites list for the device to find what features are
7539 * supported. These capabilites may be enabled/disabled by firmware so it's
7540 * best to walk the list rather than make assumptions.
7542 static void bnx2x_probe_pci_caps(struct bnx2x_softc *sc)
7544 PMD_INIT_FUNC_TRACE(sc);
7546 struct bnx2x_pci_cap *caps;
7547 uint16_t link_status;
7550 /* check if PCI Power Management is enabled */
7551 caps = pci_find_cap(sc, PCIY_PMG, BNX2X_PCI_CAP);
7553 PMD_DRV_LOG(DEBUG, sc, "Found PM capability: "
7554 "id=0x%04X type=0x%04X addr=0x%08X",
7555 caps->id, caps->type, caps->addr);
7557 sc->devinfo.pcie_cap_flags |= BNX2X_PM_CAPABLE_FLAG;
7558 sc->devinfo.pcie_pm_cap_reg = caps->addr;
7561 link_status = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_LINK_STA);
7563 sc->devinfo.pcie_link_speed = (link_status & PCIM_LINK_STA_SPEED);
7564 sc->devinfo.pcie_link_width =
7565 ((link_status & PCIM_LINK_STA_WIDTH) >> 4);
7567 PMD_DRV_LOG(DEBUG, sc, "PCIe link speed=%d width=%d",
7568 sc->devinfo.pcie_link_speed, sc->devinfo.pcie_link_width);
7570 sc->devinfo.pcie_cap_flags |= BNX2X_PCIE_CAPABLE_FLAG;
7572 /* check if MSI capability is enabled */
7573 caps = pci_find_cap(sc, PCIY_MSI, BNX2X_PCI_CAP);
7575 PMD_DRV_LOG(DEBUG, sc, "Found MSI capability at 0x%04x", reg);
7577 sc->devinfo.pcie_cap_flags |= BNX2X_MSI_CAPABLE_FLAG;
7578 sc->devinfo.pcie_msi_cap_reg = caps->addr;
7581 /* check if MSI-X capability is enabled */
7582 caps = pci_find_cap(sc, PCIY_MSIX, BNX2X_PCI_CAP);
7584 PMD_DRV_LOG(DEBUG, sc, "Found MSI-X capability at 0x%04x", reg);
7586 sc->devinfo.pcie_cap_flags |= BNX2X_MSIX_CAPABLE_FLAG;
7587 sc->devinfo.pcie_msix_cap_reg = caps->addr;
7591 static int bnx2x_get_shmem_mf_cfg_info_sd(struct bnx2x_softc *sc)
7593 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7596 /* get the outer vlan if we're in switch-dependent mode */
7598 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7599 mf_info->ext_id = (uint16_t) val;
7601 mf_info->multi_vnics_mode = 1;
7603 if (!VALID_OVLAN(mf_info->ext_id)) {
7604 PMD_DRV_LOG(NOTICE, sc, "Invalid VLAN (%d)", mf_info->ext_id);
7608 /* get the capabilities */
7609 if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK) ==
7610 FUNC_MF_CFG_PROTOCOL_ISCSI) {
7611 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ISCSI;
7612 } else if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK)
7613 == FUNC_MF_CFG_PROTOCOL_FCOE) {
7614 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_FCOE;
7616 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ETHERNET;
7619 mf_info->vnics_per_port =
7620 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7625 static uint32_t bnx2x_get_shmem_ext_proto_support_flags(struct bnx2x_softc *sc)
7627 uint32_t retval = 0;
7630 val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7632 if (val & MACP_FUNC_CFG_FLAGS_ENABLED) {
7633 if (val & MACP_FUNC_CFG_FLAGS_ETHERNET) {
7634 retval |= MF_PROTO_SUPPORT_ETHERNET;
7636 if (val & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
7637 retval |= MF_PROTO_SUPPORT_ISCSI;
7639 if (val & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
7640 retval |= MF_PROTO_SUPPORT_FCOE;
7647 static int bnx2x_get_shmem_mf_cfg_info_si(struct bnx2x_softc *sc)
7649 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7653 * There is no outer vlan if we're in switch-independent mode.
7654 * If the mac is valid then assume multi-function.
7657 val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7659 mf_info->multi_vnics_mode = ((val & MACP_FUNC_CFG_FLAGS_MASK) != 0);
7661 mf_info->mf_protos_supported =
7662 bnx2x_get_shmem_ext_proto_support_flags(sc);
7664 mf_info->vnics_per_port =
7665 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7670 static int bnx2x_get_shmem_mf_cfg_info_niv(struct bnx2x_softc *sc)
7672 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7674 uint32_t func_config;
7675 uint32_t niv_config;
7677 mf_info->multi_vnics_mode = 1;
7679 e1hov_tag = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7680 func_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7681 niv_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].afex_config);
7684 (uint16_t) ((e1hov_tag & FUNC_MF_CFG_E1HOV_TAG_MASK) >>
7685 FUNC_MF_CFG_E1HOV_TAG_SHIFT);
7687 mf_info->default_vlan =
7688 (uint16_t) ((e1hov_tag & FUNC_MF_CFG_AFEX_VLAN_MASK) >>
7689 FUNC_MF_CFG_AFEX_VLAN_SHIFT);
7691 mf_info->niv_allowed_priorities =
7692 (uint8_t) ((niv_config & FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
7693 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT);
7695 mf_info->niv_default_cos =
7696 (uint8_t) ((func_config & FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
7697 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT);
7699 mf_info->afex_vlan_mode =
7700 ((niv_config & FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
7701 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT);
7703 mf_info->niv_mba_enabled =
7704 ((niv_config & FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK) >>
7705 FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT);
7707 mf_info->mf_protos_supported =
7708 bnx2x_get_shmem_ext_proto_support_flags(sc);
7710 mf_info->vnics_per_port =
7711 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7716 static int bnx2x_check_valid_mf_cfg(struct bnx2x_softc *sc)
7718 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7725 /* various MF mode sanity checks... */
7727 if (mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_HIDE) {
7728 PMD_DRV_LOG(NOTICE, sc,
7729 "Enumerated function %d is marked as hidden",
7734 if ((mf_info->vnics_per_port > 1) && !mf_info->multi_vnics_mode) {
7735 PMD_DRV_LOG(NOTICE, sc, "vnics_per_port=%d multi_vnics_mode=%d",
7736 mf_info->vnics_per_port, mf_info->multi_vnics_mode);
7740 if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7741 /* vnic id > 0 must have valid ovlan in switch-dependent mode */
7742 if ((SC_VN(sc) > 0) && !VALID_OVLAN(OVLAN(sc))) {
7743 PMD_DRV_LOG(NOTICE, sc, "mf_mode=SD vnic_id=%d ovlan=%d",
7744 SC_VN(sc), OVLAN(sc));
7748 if (!VALID_OVLAN(OVLAN(sc)) && mf_info->multi_vnics_mode) {
7749 PMD_DRV_LOG(NOTICE, sc,
7750 "mf_mode=SD multi_vnics_mode=%d ovlan=%d",
7751 mf_info->multi_vnics_mode, OVLAN(sc));
7756 * Verify all functions are either MF or SF mode. If MF, make sure
7757 * sure that all non-hidden functions have a valid ovlan. If SF,
7758 * make sure that all non-hidden functions have an invalid ovlan.
7760 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7761 mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7762 ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7763 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE) &&
7764 (((mf_info->multi_vnics_mode)
7765 && !VALID_OVLAN(ovlan1))
7766 || ((!mf_info->multi_vnics_mode)
7767 && VALID_OVLAN(ovlan1)))) {
7768 PMD_DRV_LOG(NOTICE, sc,
7769 "mf_mode=SD function %d MF config "
7770 "mismatch, multi_vnics_mode=%d ovlan=%d",
7771 i, mf_info->multi_vnics_mode,
7777 /* Verify all funcs on the same port each have a different ovlan. */
7778 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7779 mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7780 ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7781 /* iterate from the next function on the port to the max func */
7782 for (j = i + 2; j < MAX_FUNC_NUM; j += 2) {
7784 MFCFG_RD(sc, func_mf_config[j].config);
7786 MFCFG_RD(sc, func_mf_config[j].e1hov_tag);
7787 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE)
7788 && VALID_OVLAN(ovlan1)
7789 && !(mf_cfg2 & FUNC_MF_CFG_FUNC_HIDE)
7790 && VALID_OVLAN(ovlan2)
7791 && (ovlan1 == ovlan2)) {
7792 PMD_DRV_LOG(NOTICE, sc,
7793 "mf_mode=SD functions %d and %d "
7794 "have the same ovlan (%d)",
7801 /* MULTI_FUNCTION_SD */
7805 static int bnx2x_get_mf_cfg_info(struct bnx2x_softc *sc)
7807 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7808 uint32_t val, mac_upper;
7811 /* initialize mf_info defaults */
7812 mf_info->vnics_per_port = 1;
7813 mf_info->multi_vnics_mode = FALSE;
7814 mf_info->path_has_ovlan = FALSE;
7815 mf_info->mf_mode = SINGLE_FUNCTION;
7817 if (!CHIP_IS_MF_CAP(sc)) {
7821 if (sc->devinfo.mf_cfg_base == SHMEM_MF_CFG_ADDR_NONE) {
7822 PMD_DRV_LOG(NOTICE, sc, "Invalid mf_cfg_base!");
7826 /* get the MF mode (switch dependent / independent / single-function) */
7828 val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
7830 switch (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK) {
7831 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
7834 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7836 /* check for legal upper mac bytes */
7837 if (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT) {
7838 mf_info->mf_mode = MULTI_FUNCTION_SI;
7840 PMD_DRV_LOG(NOTICE, sc,
7841 "Invalid config for Switch Independent mode");
7846 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
7847 case SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4:
7849 /* get outer vlan configuration */
7850 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7852 if ((val & FUNC_MF_CFG_E1HOV_TAG_MASK) !=
7853 FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
7854 mf_info->mf_mode = MULTI_FUNCTION_SD;
7856 PMD_DRV_LOG(NOTICE, sc,
7857 "Invalid config for Switch Dependent mode");
7862 case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
7864 /* not in MF mode, vnics_per_port=1 and multi_vnics_mode=FALSE */
7867 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
7870 * Mark MF mode as NIV if MCP version includes NPAR-SD support
7871 * and the MAC address is valid.
7874 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7876 if ((SHMEM2_HAS(sc, afex_driver_support)) &&
7877 (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT)) {
7878 mf_info->mf_mode = MULTI_FUNCTION_AFEX;
7880 PMD_DRV_LOG(NOTICE, sc, "Invalid config for AFEX mode");
7887 PMD_DRV_LOG(NOTICE, sc, "Unknown MF mode (0x%08x)",
7888 (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK));
7893 /* set path mf_mode (which could be different than function mf_mode) */
7894 if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7895 mf_info->path_has_ovlan = TRUE;
7896 } else if (mf_info->mf_mode == SINGLE_FUNCTION) {
7898 * Decide on path multi vnics mode. If we're not in MF mode and in
7899 * 4-port mode, this is good enough to check vnic-0 of the other port
7902 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7903 uint8_t other_port = !(PORT_ID(sc) & 1);
7904 uint8_t abs_func_other_port =
7905 (SC_PATH(sc) + (2 * other_port));
7910 [abs_func_other_port].e1hov_tag);
7912 mf_info->path_has_ovlan = VALID_OVLAN((uint16_t) val);
7916 if (mf_info->mf_mode == SINGLE_FUNCTION) {
7917 /* invalid MF config */
7918 if (SC_VN(sc) >= 1) {
7919 PMD_DRV_LOG(NOTICE, sc, "VNIC ID >= 1 in SF mode");
7926 /* get the MF configuration */
7927 mf_info->mf_config[SC_VN(sc)] =
7928 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7930 switch (mf_info->mf_mode) {
7931 case MULTI_FUNCTION_SD:
7933 bnx2x_get_shmem_mf_cfg_info_sd(sc);
7936 case MULTI_FUNCTION_SI:
7938 bnx2x_get_shmem_mf_cfg_info_si(sc);
7941 case MULTI_FUNCTION_AFEX:
7943 bnx2x_get_shmem_mf_cfg_info_niv(sc);
7948 PMD_DRV_LOG(NOTICE, sc, "Get MF config failed (mf_mode=0x%08x)",
7953 /* get the congestion management parameters */
7956 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7957 /* get min/max bw */
7958 val = MFCFG_RD(sc, func_mf_config[i].config);
7959 mf_info->min_bw[vnic] =
7960 ((val & FUNC_MF_CFG_MIN_BW_MASK) >>
7961 FUNC_MF_CFG_MIN_BW_SHIFT);
7962 mf_info->max_bw[vnic] =
7963 ((val & FUNC_MF_CFG_MAX_BW_MASK) >>
7964 FUNC_MF_CFG_MAX_BW_SHIFT);
7968 return bnx2x_check_valid_mf_cfg(sc);
7971 static int bnx2x_get_shmem_info(struct bnx2x_softc *sc)
7974 uint32_t mac_hi, mac_lo, val;
7976 PMD_INIT_FUNC_TRACE(sc);
7979 mac_hi = mac_lo = 0;
7981 sc->link_params.sc = sc;
7982 sc->link_params.port = port;
7984 /* get the hardware config info */
7985 sc->devinfo.hw_config = SHMEM_RD(sc, dev_info.shared_hw_config.config);
7986 sc->devinfo.hw_config2 =
7987 SHMEM_RD(sc, dev_info.shared_hw_config.config2);
7989 sc->link_params.hw_led_mode =
7990 ((sc->devinfo.hw_config & SHARED_HW_CFG_LED_MODE_MASK) >>
7991 SHARED_HW_CFG_LED_MODE_SHIFT);
7993 /* get the port feature config */
7995 SHMEM_RD(sc, dev_info.port_feature_config[port].config);
7997 /* get the link params */
7998 sc->link_params.speed_cap_mask[ELINK_INT_PHY] =
7999 SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask)
8000 & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
8001 sc->link_params.speed_cap_mask[ELINK_EXT_PHY1] =
8002 SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask2)
8003 & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
8005 /* get the lane config */
8006 sc->link_params.lane_config =
8007 SHMEM_RD(sc, dev_info.port_hw_config[port].lane_config);
8009 /* get the link config */
8010 val = SHMEM_RD(sc, dev_info.port_feature_config[port].link_config);
8011 sc->port.link_config[ELINK_INT_PHY] = val;
8012 sc->link_params.switch_cfg = (val & PORT_FEATURE_CONNECTED_SWITCH_MASK);
8013 sc->port.link_config[ELINK_EXT_PHY1] =
8014 SHMEM_RD(sc, dev_info.port_feature_config[port].link_config2);
8016 /* get the override preemphasis flag and enable it or turn it off */
8017 val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
8018 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) {
8019 sc->link_params.feature_config_flags |=
8020 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8022 sc->link_params.feature_config_flags &=
8023 ~ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8026 /* get the initial value of the link params */
8027 sc->link_params.multi_phy_config =
8028 SHMEM_RD(sc, dev_info.port_hw_config[port].multi_phy_config);
8030 /* get external phy info */
8031 sc->port.ext_phy_config =
8032 SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
8034 /* get the multifunction configuration */
8035 bnx2x_get_mf_cfg_info(sc);
8037 /* get the mac address */
8040 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
8042 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_lower);
8044 mac_hi = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_upper);
8045 mac_lo = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_lower);
8048 if ((mac_lo == 0) && (mac_hi == 0)) {
8049 *sc->mac_addr_str = 0;
8050 PMD_DRV_LOG(NOTICE, sc, "No Ethernet address programmed!");
8052 sc->link_params.mac_addr[0] = (uint8_t) (mac_hi >> 8);
8053 sc->link_params.mac_addr[1] = (uint8_t) (mac_hi);
8054 sc->link_params.mac_addr[2] = (uint8_t) (mac_lo >> 24);
8055 sc->link_params.mac_addr[3] = (uint8_t) (mac_lo >> 16);
8056 sc->link_params.mac_addr[4] = (uint8_t) (mac_lo >> 8);
8057 sc->link_params.mac_addr[5] = (uint8_t) (mac_lo);
8058 snprintf(sc->mac_addr_str, sizeof(sc->mac_addr_str),
8059 "%02x:%02x:%02x:%02x:%02x:%02x",
8060 sc->link_params.mac_addr[0],
8061 sc->link_params.mac_addr[1],
8062 sc->link_params.mac_addr[2],
8063 sc->link_params.mac_addr[3],
8064 sc->link_params.mac_addr[4],
8065 sc->link_params.mac_addr[5]);
8066 PMD_DRV_LOG(DEBUG, sc,
8067 "Ethernet address: %s", sc->mac_addr_str);
8073 static void bnx2x_media_detect(struct bnx2x_softc *sc)
8075 uint32_t phy_idx = bnx2x_get_cur_phy_idx(sc);
8076 switch (sc->link_params.phy[phy_idx].media_type) {
8077 case ELINK_ETH_PHY_SFPP_10G_FIBER:
8078 case ELINK_ETH_PHY_SFP_1G_FIBER:
8079 case ELINK_ETH_PHY_XFP_FIBER:
8080 case ELINK_ETH_PHY_KR:
8081 case ELINK_ETH_PHY_CX4:
8082 PMD_DRV_LOG(INFO, sc, "Found 10GBase-CX4 media.");
8083 sc->media = IFM_10G_CX4;
8085 case ELINK_ETH_PHY_DA_TWINAX:
8086 PMD_DRV_LOG(INFO, sc, "Found 10Gb Twinax media.");
8087 sc->media = IFM_10G_TWINAX;
8089 case ELINK_ETH_PHY_BASE_T:
8090 PMD_DRV_LOG(INFO, sc, "Found 10GBase-T media.");
8091 sc->media = IFM_10G_T;
8093 case ELINK_ETH_PHY_NOT_PRESENT:
8094 PMD_DRV_LOG(INFO, sc, "Media not present.");
8097 case ELINK_ETH_PHY_UNSPECIFIED:
8099 PMD_DRV_LOG(INFO, sc, "Unknown media!");
8105 #define GET_FIELD(value, fname) \
8106 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
8107 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
8108 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
8110 static int bnx2x_get_igu_cam_info(struct bnx2x_softc *sc)
8112 int pfid = SC_FUNC(sc);
8115 uint8_t fid, igu_sb_cnt = 0;
8117 sc->igu_base_sb = 0xff;
8119 if (CHIP_INT_MODE_IS_BC(sc)) {
8121 igu_sb_cnt = sc->igu_sb_cnt;
8122 sc->igu_base_sb = ((CHIP_IS_MODE_4_PORT(sc) ? pfid : vn) *
8124 sc->igu_dsb_id = (E1HVN_MAX * FP_SB_MAX_E1x +
8125 (CHIP_IS_MODE_4_PORT(sc) ? pfid : vn));
8129 /* IGU in normal mode - read CAM */
8131 igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; igu_sb_id++) {
8132 val = REG_RD(sc, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
8133 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) {
8137 if (fid & IGU_FID_ENCODE_IS_PF) {
8138 if ((fid & IGU_FID_PF_NUM_MASK) != pfid) {
8141 if (IGU_VEC(val) == 0) {
8142 /* default status block */
8143 sc->igu_dsb_id = igu_sb_id;
8145 if (sc->igu_base_sb == 0xff) {
8146 sc->igu_base_sb = igu_sb_id;
8154 * Due to new PF resource allocation by MFW T7.4 and above, it's optional
8155 * that number of CAM entries will not be equal to the value advertised in
8156 * PCI. Driver should use the minimal value of both as the actual status
8159 sc->igu_sb_cnt = min(sc->igu_sb_cnt, igu_sb_cnt);
8161 if (igu_sb_cnt == 0) {
8162 PMD_DRV_LOG(ERR, sc, "CAM configuration error");
8170 * Gather various information from the device config space, the device itself,
8171 * shmem, and the user input.
8173 static int bnx2x_get_device_info(struct bnx2x_softc *sc)
8178 /* get the chip revision (chip metal comes from pci config space) */
8179 sc->devinfo.chip_id = sc->link_params.chip_id =
8180 (((REG_RD(sc, MISC_REG_CHIP_NUM) & 0xffff) << 16) |
8181 ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12) |
8182 (((REG_RD(sc, PCICFG_OFFSET + PCI_ID_VAL3) >> 24) & 0xf) << 4) |
8183 ((REG_RD(sc, MISC_REG_BOND_ID) & 0xf) << 0));
8185 /* force 57811 according to MISC register */
8186 if (REG_RD(sc, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
8187 if (CHIP_IS_57810(sc)) {
8188 sc->devinfo.chip_id = ((CHIP_NUM_57811 << 16) |
8190 devinfo.chip_id & 0x0000ffff));
8191 } else if (CHIP_IS_57810_MF(sc)) {
8192 sc->devinfo.chip_id = ((CHIP_NUM_57811_MF << 16) |
8194 devinfo.chip_id & 0x0000ffff));
8196 sc->devinfo.chip_id |= 0x1;
8199 PMD_DRV_LOG(DEBUG, sc,
8200 "chip_id=0x%08x (num=0x%04x rev=0x%01x metal=0x%02x bond=0x%01x)",
8201 sc->devinfo.chip_id,
8202 ((sc->devinfo.chip_id >> 16) & 0xffff),
8203 ((sc->devinfo.chip_id >> 12) & 0xf),
8204 ((sc->devinfo.chip_id >> 4) & 0xff),
8205 ((sc->devinfo.chip_id >> 0) & 0xf));
8207 val = (REG_RD(sc, 0x2874) & 0x55);
8208 if ((sc->devinfo.chip_id & 0x1) || (CHIP_IS_E1H(sc) && (val == 0x55))) {
8209 sc->flags |= BNX2X_ONE_PORT_FLAG;
8210 PMD_DRV_LOG(DEBUG, sc, "single port device");
8213 /* set the doorbell size */
8214 sc->doorbell_size = (1 << BNX2X_DB_SHIFT);
8216 /* determine whether the device is in 2 port or 4 port mode */
8217 sc->devinfo.chip_port_mode = CHIP_PORT_MODE_NONE; /* E1h */
8218 if (CHIP_IS_E2E3(sc)) {
8220 * Read port4mode_en_ovwr[0]:
8221 * If 1, four port mode is in port4mode_en_ovwr[1].
8222 * If 0, four port mode is in port4mode_en[0].
8224 val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);
8226 val = ((val >> 1) & 1);
8228 val = REG_RD(sc, MISC_REG_PORT4MODE_EN);
8231 sc->devinfo.chip_port_mode =
8232 (val) ? CHIP_4_PORT_MODE : CHIP_2_PORT_MODE;
8234 PMD_DRV_LOG(DEBUG, sc, "Port mode = %s", (val) ? "4" : "2");
8237 /* get the function and path info for the device */
8238 bnx2x_get_function_num(sc);
8240 /* get the shared memory base address */
8241 sc->devinfo.shmem_base =
8242 sc->link_params.shmem_base = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
8243 sc->devinfo.shmem2_base =
8244 REG_RD(sc, (SC_PATH(sc) ? MISC_REG_GENERIC_CR_1 :
8245 MISC_REG_GENERIC_CR_0));
8247 if (!sc->devinfo.shmem_base) {
8248 /* this should ONLY prevent upcoming shmem reads */
8249 PMD_DRV_LOG(INFO, sc, "MCP not active");
8250 sc->flags |= BNX2X_NO_MCP_FLAG;
8254 /* make sure the shared memory contents are valid */
8255 val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
8256 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) !=
8257 (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) {
8258 PMD_DRV_LOG(NOTICE, sc, "Invalid SHMEM validity signature: 0x%08x",
8263 /* get the bootcode version */
8264 sc->devinfo.bc_ver = SHMEM_RD(sc, dev_info.bc_rev);
8265 snprintf(sc->devinfo.bc_ver_str,
8266 sizeof(sc->devinfo.bc_ver_str),
8268 ((sc->devinfo.bc_ver >> 24) & 0xff),
8269 ((sc->devinfo.bc_ver >> 16) & 0xff),
8270 ((sc->devinfo.bc_ver >> 8) & 0xff));
8271 PMD_DRV_LOG(INFO, sc, "Bootcode version: %s", sc->devinfo.bc_ver_str);
8273 /* get the bootcode shmem address */
8274 sc->devinfo.mf_cfg_base = bnx2x_get_shmem_mf_cfg_base(sc);
8276 /* clean indirect addresses as they're not used */
8277 pci_write_long(sc, PCICFG_GRC_ADDRESS, 0);
8279 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F0, 0);
8280 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F0, 0);
8281 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F0, 0);
8282 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F0, 0);
8283 if (CHIP_IS_E1x(sc)) {
8284 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F1, 0);
8285 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F1, 0);
8286 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F1, 0);
8287 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F1, 0);
8291 /* get the nvram size */
8292 val = REG_RD(sc, MCP_REG_MCPR_NVM_CFG4);
8293 sc->devinfo.flash_size =
8294 (NVRAM_1MB_SIZE << (val & MCPR_NVM_CFG4_FLASH_SIZE));
8296 bnx2x_set_power_state(sc, PCI_PM_D0);
8297 /* get various configuration parameters from shmem */
8298 bnx2x_get_shmem_info(sc);
8300 /* initialize IGU parameters */
8301 if (CHIP_IS_E1x(sc)) {
8302 sc->devinfo.int_block = INT_BLOCK_HC;
8303 sc->igu_dsb_id = DEF_SB_IGU_ID;
8304 sc->igu_base_sb = 0;
8306 sc->devinfo.int_block = INT_BLOCK_IGU;
8308 /* do not allow device reset during IGU info preocessing */
8309 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8311 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
8313 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8316 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
8317 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION, val);
8318 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x7f);
8320 while (tout && REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8325 if (REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8326 PMD_DRV_LOG(NOTICE, sc,
8327 "FORCING IGU Normal Mode failed!!!");
8328 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8333 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8334 PMD_DRV_LOG(DEBUG, sc, "IGU Backward Compatible Mode");
8335 sc->devinfo.int_block |= INT_BLOCK_MODE_BW_COMP;
8337 PMD_DRV_LOG(DEBUG, sc, "IGU Normal Mode");
8340 rc = bnx2x_get_igu_cam_info(sc);
8342 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8350 * Get base FW non-default (fast path) status block ID. This value is
8351 * used to initialize the fw_sb_id saved on the fp/queue structure to
8352 * determine the id used by the FW.
8354 if (CHIP_IS_E1x(sc)) {
8356 ((SC_PORT(sc) * FP_SB_MAX_E1x) + SC_L_ID(sc));
8359 * 57712+ - We currently use one FW SB per IGU SB (Rx and Tx of
8360 * the same queue are indicated on the same IGU SB). So we prefer
8361 * FW and IGU SBs to be the same value.
8363 sc->base_fw_ndsb = sc->igu_base_sb;
8366 elink_phy_probe(&sc->link_params);
8372 bnx2x_link_settings_supported(struct bnx2x_softc *sc, uint32_t switch_cfg)
8374 uint32_t cfg_size = 0;
8376 uint8_t port = SC_PORT(sc);
8378 /* aggregation of supported attributes of all external phys */
8379 sc->port.supported[0] = 0;
8380 sc->port.supported[1] = 0;
8382 switch (sc->link_params.num_phys) {
8384 sc->port.supported[0] =
8385 sc->link_params.phy[ELINK_INT_PHY].supported;
8389 sc->port.supported[0] =
8390 sc->link_params.phy[ELINK_EXT_PHY1].supported;
8394 if (sc->link_params.multi_phy_config &
8395 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
8396 sc->port.supported[1] =
8397 sc->link_params.phy[ELINK_EXT_PHY1].supported;
8398 sc->port.supported[0] =
8399 sc->link_params.phy[ELINK_EXT_PHY2].supported;
8401 sc->port.supported[0] =
8402 sc->link_params.phy[ELINK_EXT_PHY1].supported;
8403 sc->port.supported[1] =
8404 sc->link_params.phy[ELINK_EXT_PHY2].supported;
8410 if (!(sc->port.supported[0] || sc->port.supported[1])) {
8411 PMD_DRV_LOG(ERR, sc,
8412 "Invalid phy config in NVRAM (PHY1=0x%08x PHY2=0x%08x)",
8414 dev_info.port_hw_config
8415 [port].external_phy_config),
8417 dev_info.port_hw_config
8418 [port].external_phy_config2));
8423 sc->port.phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR);
8425 switch (switch_cfg) {
8426 case ELINK_SWITCH_CFG_1G:
8429 NIG_REG_SERDES0_CTRL_PHY_ADDR + port * 0x10);
8431 case ELINK_SWITCH_CFG_10G:
8434 NIG_REG_XGXS0_CTRL_PHY_ADDR + port * 0x18);
8437 PMD_DRV_LOG(ERR, sc,
8438 "Invalid switch config in"
8439 "link_config=0x%08x",
8440 sc->port.link_config[0]);
8445 PMD_DRV_LOG(INFO, sc, "PHY addr 0x%08x", sc->port.phy_addr);
8447 /* mask what we support according to speed_cap_mask per configuration */
8448 for (idx = 0; idx < cfg_size; idx++) {
8449 if (!(sc->link_params.speed_cap_mask[idx] &
8450 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) {
8451 sc->port.supported[idx] &=
8452 ~ELINK_SUPPORTED_10baseT_Half;
8455 if (!(sc->link_params.speed_cap_mask[idx] &
8456 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) {
8457 sc->port.supported[idx] &=
8458 ~ELINK_SUPPORTED_10baseT_Full;
8461 if (!(sc->link_params.speed_cap_mask[idx] &
8462 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) {
8463 sc->port.supported[idx] &=
8464 ~ELINK_SUPPORTED_100baseT_Half;
8467 if (!(sc->link_params.speed_cap_mask[idx] &
8468 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) {
8469 sc->port.supported[idx] &=
8470 ~ELINK_SUPPORTED_100baseT_Full;
8473 if (!(sc->link_params.speed_cap_mask[idx] &
8474 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) {
8475 sc->port.supported[idx] &=
8476 ~ELINK_SUPPORTED_1000baseT_Full;
8479 if (!(sc->link_params.speed_cap_mask[idx] &
8480 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) {
8481 sc->port.supported[idx] &=
8482 ~ELINK_SUPPORTED_2500baseX_Full;
8485 if (!(sc->link_params.speed_cap_mask[idx] &
8486 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8487 sc->port.supported[idx] &=
8488 ~ELINK_SUPPORTED_10000baseT_Full;
8491 if (!(sc->link_params.speed_cap_mask[idx] &
8492 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) {
8493 sc->port.supported[idx] &=
8494 ~ELINK_SUPPORTED_20000baseKR2_Full;
8498 PMD_DRV_LOG(INFO, sc, "PHY supported 0=0x%08x 1=0x%08x",
8499 sc->port.supported[0], sc->port.supported[1]);
8502 static void bnx2x_link_settings_requested(struct bnx2x_softc *sc)
8504 uint32_t link_config;
8506 uint32_t cfg_size = 0;
8508 sc->port.advertising[0] = 0;
8509 sc->port.advertising[1] = 0;
8511 switch (sc->link_params.num_phys) {
8521 for (idx = 0; idx < cfg_size; idx++) {
8522 sc->link_params.req_duplex[idx] = DUPLEX_FULL;
8523 link_config = sc->port.link_config[idx];
8525 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
8526 case PORT_FEATURE_LINK_SPEED_AUTO:
8527 if (sc->port.supported[idx] & ELINK_SUPPORTED_Autoneg) {
8528 sc->link_params.req_line_speed[idx] =
8529 ELINK_SPEED_AUTO_NEG;
8530 sc->port.advertising[idx] |=
8531 sc->port.supported[idx];
8532 if (sc->link_params.phy[ELINK_EXT_PHY1].type ==
8533 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833)
8534 sc->port.advertising[idx] |=
8535 (ELINK_SUPPORTED_100baseT_Half |
8536 ELINK_SUPPORTED_100baseT_Full);
8538 /* force 10G, no AN */
8539 sc->link_params.req_line_speed[idx] =
8541 sc->port.advertising[idx] |=
8542 (ADVERTISED_10000baseT_Full |
8548 case PORT_FEATURE_LINK_SPEED_10M_FULL:
8550 port.supported[idx] & ELINK_SUPPORTED_10baseT_Full)
8552 sc->link_params.req_line_speed[idx] =
8554 sc->port.advertising[idx] |=
8555 (ADVERTISED_10baseT_Full | ADVERTISED_TP);
8557 PMD_DRV_LOG(ERR, sc,
8558 "Invalid NVRAM config link_config=0x%08x "
8559 "speed_cap_mask=0x%08x",
8562 link_params.speed_cap_mask[idx]);
8567 case PORT_FEATURE_LINK_SPEED_10M_HALF:
8569 port.supported[idx] & ELINK_SUPPORTED_10baseT_Half)
8571 sc->link_params.req_line_speed[idx] =
8573 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8574 sc->port.advertising[idx] |=
8575 (ADVERTISED_10baseT_Half | ADVERTISED_TP);
8577 PMD_DRV_LOG(ERR, sc,
8578 "Invalid NVRAM config link_config=0x%08x "
8579 "speed_cap_mask=0x%08x",
8582 link_params.speed_cap_mask[idx]);
8587 case PORT_FEATURE_LINK_SPEED_100M_FULL:
8589 port.supported[idx] & ELINK_SUPPORTED_100baseT_Full)
8591 sc->link_params.req_line_speed[idx] =
8593 sc->port.advertising[idx] |=
8594 (ADVERTISED_100baseT_Full | ADVERTISED_TP);
8596 PMD_DRV_LOG(ERR, sc,
8597 "Invalid NVRAM config link_config=0x%08x "
8598 "speed_cap_mask=0x%08x",
8601 link_params.speed_cap_mask[idx]);
8606 case PORT_FEATURE_LINK_SPEED_100M_HALF:
8608 port.supported[idx] & ELINK_SUPPORTED_100baseT_Half)
8610 sc->link_params.req_line_speed[idx] =
8612 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8613 sc->port.advertising[idx] |=
8614 (ADVERTISED_100baseT_Half | ADVERTISED_TP);
8616 PMD_DRV_LOG(ERR, sc,
8617 "Invalid NVRAM config link_config=0x%08x "
8618 "speed_cap_mask=0x%08x",
8621 link_params.speed_cap_mask[idx]);
8626 case PORT_FEATURE_LINK_SPEED_1G:
8627 if (sc->port.supported[idx] &
8628 ELINK_SUPPORTED_1000baseT_Full) {
8629 sc->link_params.req_line_speed[idx] =
8631 sc->port.advertising[idx] |=
8632 (ADVERTISED_1000baseT_Full | ADVERTISED_TP);
8634 PMD_DRV_LOG(ERR, sc,
8635 "Invalid NVRAM config link_config=0x%08x "
8636 "speed_cap_mask=0x%08x",
8639 link_params.speed_cap_mask[idx]);
8644 case PORT_FEATURE_LINK_SPEED_2_5G:
8645 if (sc->port.supported[idx] &
8646 ELINK_SUPPORTED_2500baseX_Full) {
8647 sc->link_params.req_line_speed[idx] =
8649 sc->port.advertising[idx] |=
8650 (ADVERTISED_2500baseX_Full | ADVERTISED_TP);
8652 PMD_DRV_LOG(ERR, sc,
8653 "Invalid NVRAM config link_config=0x%08x "
8654 "speed_cap_mask=0x%08x",
8657 link_params.speed_cap_mask[idx]);
8662 case PORT_FEATURE_LINK_SPEED_10G_CX4:
8663 if (sc->port.supported[idx] &
8664 ELINK_SUPPORTED_10000baseT_Full) {
8665 sc->link_params.req_line_speed[idx] =
8667 sc->port.advertising[idx] |=
8668 (ADVERTISED_10000baseT_Full |
8671 PMD_DRV_LOG(ERR, sc,
8672 "Invalid NVRAM config link_config=0x%08x "
8673 "speed_cap_mask=0x%08x",
8676 link_params.speed_cap_mask[idx]);
8681 case PORT_FEATURE_LINK_SPEED_20G:
8682 sc->link_params.req_line_speed[idx] = ELINK_SPEED_20000;
8686 PMD_DRV_LOG(ERR, sc,
8687 "Invalid NVRAM config link_config=0x%08x "
8688 "speed_cap_mask=0x%08x", link_config,
8689 sc->link_params.speed_cap_mask[idx]);
8690 sc->link_params.req_line_speed[idx] =
8691 ELINK_SPEED_AUTO_NEG;
8692 sc->port.advertising[idx] = sc->port.supported[idx];
8696 sc->link_params.req_flow_ctrl[idx] =
8697 (link_config & PORT_FEATURE_FLOW_CONTROL_MASK);
8699 if (sc->link_params.req_flow_ctrl[idx] == ELINK_FLOW_CTRL_AUTO) {
8702 port.supported[idx] & ELINK_SUPPORTED_Autoneg)) {
8703 sc->link_params.req_flow_ctrl[idx] =
8704 ELINK_FLOW_CTRL_NONE;
8706 bnx2x_set_requested_fc(sc);
8712 static void bnx2x_get_phy_info(struct bnx2x_softc *sc)
8714 uint8_t port = SC_PORT(sc);
8717 PMD_INIT_FUNC_TRACE(sc);
8719 /* shmem data already read in bnx2x_get_shmem_info() */
8721 bnx2x_link_settings_supported(sc, sc->link_params.switch_cfg);
8722 bnx2x_link_settings_requested(sc);
8724 /* configure link feature according to nvram value */
8726 (((SHMEM_RD(sc, dev_info.port_feature_config[port].eee_power_mode))
8727 & PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
8728 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
8729 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
8730 sc->link_params.eee_mode = (ELINK_EEE_MODE_ADV_LPI |
8731 ELINK_EEE_MODE_ENABLE_LPI |
8732 ELINK_EEE_MODE_OUTPUT_TIME);
8734 sc->link_params.eee_mode = 0;
8737 /* get the media type */
8738 bnx2x_media_detect(sc);
8741 static void bnx2x_set_modes_bitmap(struct bnx2x_softc *sc)
8743 uint32_t flags = MODE_ASIC | MODE_PORT2;
8745 if (CHIP_IS_E2(sc)) {
8747 } else if (CHIP_IS_E3(sc)) {
8749 if (CHIP_REV(sc) == CHIP_REV_Ax) {
8750 flags |= MODE_E3_A0;
8751 } else { /*if (CHIP_REV(sc) == CHIP_REV_Bx) */
8753 flags |= MODE_E3_B0 | MODE_COS3;
8759 switch (sc->devinfo.mf_info.mf_mode) {
8760 case MULTI_FUNCTION_SD:
8761 flags |= MODE_MF_SD;
8763 case MULTI_FUNCTION_SI:
8764 flags |= MODE_MF_SI;
8766 case MULTI_FUNCTION_AFEX:
8767 flags |= MODE_MF_AFEX;
8774 #if defined(__LITTLE_ENDIAN)
8775 flags |= MODE_LITTLE_ENDIAN;
8776 #else /* __BIG_ENDIAN */
8777 flags |= MODE_BIG_ENDIAN;
8780 INIT_MODE_FLAGS(sc) = flags;
8783 int bnx2x_alloc_hsi_mem(struct bnx2x_softc *sc)
8785 struct bnx2x_fastpath *fp;
8790 /************************/
8791 /* DEFAULT STATUS BLOCK */
8792 /************************/
8794 if (bnx2x_dma_alloc(sc, sizeof(struct host_sp_status_block),
8795 &sc->def_sb_dma, "def_sb",
8796 RTE_CACHE_LINE_SIZE) != 0) {
8801 (struct host_sp_status_block *)sc->def_sb_dma.vaddr;
8806 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8807 &sc->eq_dma, "ev_queue",
8808 RTE_CACHE_LINE_SIZE) != 0) {
8813 sc->eq = (union event_ring_elem *)sc->eq_dma.vaddr;
8819 if (bnx2x_dma_alloc(sc, sizeof(struct bnx2x_slowpath),
8821 RTE_CACHE_LINE_SIZE) != 0) {
8827 sc->sp = (struct bnx2x_slowpath *)sc->sp_dma.vaddr;
8829 /*******************/
8830 /* SLOW PATH QUEUE */
8831 /*******************/
8833 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8834 &sc->spq_dma, "sp_queue",
8835 RTE_CACHE_LINE_SIZE) != 0) {
8842 sc->spq = (struct eth_spe *)sc->spq_dma.vaddr;
8844 /***************************/
8845 /* FW DECOMPRESSION BUFFER */
8846 /***************************/
8848 if (bnx2x_dma_alloc(sc, FW_BUF_SIZE, &sc->gz_buf_dma,
8849 "fw_buf", RTE_CACHE_LINE_SIZE) != 0) {
8857 sc->gz_buf = (void *)sc->gz_buf_dma.vaddr;
8864 /* allocate DMA memory for each fastpath structure */
8865 for (i = 0; i < sc->num_queues; i++) {
8870 /*******************/
8871 /* FP STATUS BLOCK */
8872 /*******************/
8874 snprintf(buf, sizeof(buf), "fp_%d_sb", i);
8875 if (bnx2x_dma_alloc(sc, sizeof(union bnx2x_host_hc_status_block),
8876 &fp->sb_dma, buf, RTE_CACHE_LINE_SIZE) != 0) {
8877 PMD_DRV_LOG(NOTICE, sc, "Failed to alloc %s", buf);
8880 if (CHIP_IS_E2E3(sc)) {
8881 fp->status_block.e2_sb =
8882 (struct host_hc_status_block_e2 *)
8885 fp->status_block.e1x_sb =
8886 (struct host_hc_status_block_e1x *)
8895 void bnx2x_free_hsi_mem(struct bnx2x_softc *sc)
8897 struct bnx2x_fastpath *fp;
8900 for (i = 0; i < sc->num_queues; i++) {
8903 /*******************/
8904 /* FP STATUS BLOCK */
8905 /*******************/
8907 memset(&fp->status_block, 0, sizeof(fp->status_block));
8910 /***************************/
8911 /* FW DECOMPRESSION BUFFER */
8912 /***************************/
8916 /*******************/
8917 /* SLOW PATH QUEUE */
8918 /*******************/
8934 /************************/
8935 /* DEFAULT STATUS BLOCK */
8936 /************************/
8943 * Previous driver DMAE transaction may have occurred when pre-boot stage
8944 * ended and boot began. This would invalidate the addresses of the
8945 * transaction, resulting in was-error bit set in the PCI causing all
8946 * hw-to-host PCIe transactions to timeout. If this happened we want to clear
8947 * the interrupt which detected this from the pglueb and the was-done bit
8949 static void bnx2x_prev_interrupted_dmae(struct bnx2x_softc *sc)
8953 if (!CHIP_IS_E1x(sc)) {
8954 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS);
8955 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
8956 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
8962 static int bnx2x_prev_mcp_done(struct bnx2x_softc *sc)
8964 uint32_t rc = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE,
8965 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
8967 PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
8974 static struct bnx2x_prev_list_node *bnx2x_prev_path_get_entry(struct bnx2x_softc *sc)
8976 struct bnx2x_prev_list_node *tmp;
8978 LIST_FOREACH(tmp, &bnx2x_prev_list, node) {
8979 if ((sc->pcie_bus == tmp->bus) &&
8980 (sc->pcie_device == tmp->slot) &&
8981 (SC_PATH(sc) == tmp->path)) {
8989 static uint8_t bnx2x_prev_is_path_marked(struct bnx2x_softc *sc)
8991 struct bnx2x_prev_list_node *tmp;
8994 rte_spinlock_lock(&bnx2x_prev_mtx);
8996 tmp = bnx2x_prev_path_get_entry(sc);
8999 PMD_DRV_LOG(DEBUG, sc,
9000 "Path %d/%d/%d was marked by AER",
9001 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9004 PMD_DRV_LOG(DEBUG, sc,
9005 "Path %d/%d/%d was already cleaned from previous drivers",
9006 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9010 rte_spinlock_unlock(&bnx2x_prev_mtx);
9015 static int bnx2x_prev_mark_path(struct bnx2x_softc *sc, uint8_t after_undi)
9017 struct bnx2x_prev_list_node *tmp;
9019 rte_spinlock_lock(&bnx2x_prev_mtx);
9021 /* Check whether the entry for this path already exists */
9022 tmp = bnx2x_prev_path_get_entry(sc);
9025 PMD_DRV_LOG(DEBUG, sc,
9026 "Re-marking AER in path %d/%d/%d",
9027 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9029 PMD_DRV_LOG(DEBUG, sc,
9030 "Removing AER indication from path %d/%d/%d",
9031 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9035 rte_spinlock_unlock(&bnx2x_prev_mtx);
9039 rte_spinlock_unlock(&bnx2x_prev_mtx);
9041 /* Create an entry for this path and add it */
9042 tmp = rte_malloc("", sizeof(struct bnx2x_prev_list_node),
9043 RTE_CACHE_LINE_SIZE);
9045 PMD_DRV_LOG(NOTICE, sc, "Failed to allocate 'bnx2x_prev_list_node'");
9049 tmp->bus = sc->pcie_bus;
9050 tmp->slot = sc->pcie_device;
9051 tmp->path = SC_PATH(sc);
9053 tmp->undi = after_undi ? (1 << SC_PORT(sc)) : 0;
9055 rte_spinlock_lock(&bnx2x_prev_mtx);
9057 LIST_INSERT_HEAD(&bnx2x_prev_list, tmp, node);
9059 rte_spinlock_unlock(&bnx2x_prev_mtx);
9064 static int bnx2x_do_flr(struct bnx2x_softc *sc)
9068 /* only E2 and onwards support FLR */
9069 if (CHIP_IS_E1x(sc)) {
9070 PMD_DRV_LOG(WARNING, sc, "FLR not supported in E1H");
9074 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9075 if (sc->devinfo.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9076 PMD_DRV_LOG(WARNING, sc,
9077 "FLR not supported by BC_VER: 0x%08x",
9078 sc->devinfo.bc_ver);
9082 /* Wait for Transaction Pending bit clean */
9083 for (i = 0; i < 4; i++) {
9085 DELAY(((1 << (i - 1)) * 100) * 1000);
9088 if (!bnx2x_is_pcie_pending(sc)) {
9093 PMD_DRV_LOG(NOTICE, sc, "PCIE transaction is not cleared, "
9094 "proceeding with reset anyway");
9097 bnx2x_fw_command(sc, DRV_MSG_CODE_INITIATE_FLR, 0);
9102 struct bnx2x_mac_vals {
9110 uint32_t bmac_val[2];
9114 bnx2x_prev_unload_close_mac(struct bnx2x_softc *sc, struct bnx2x_mac_vals *vals)
9116 uint32_t val, base_addr, offset, mask, reset_reg;
9117 uint8_t mac_stopped = FALSE;
9118 uint8_t port = SC_PORT(sc);
9119 uint32_t wb_data[2];
9121 /* reset addresses as they also mark which values were changed */
9122 vals->bmac_addr = 0;
9123 vals->umac_addr = 0;
9124 vals->xmac_addr = 0;
9125 vals->emac_addr = 0;
9127 reset_reg = REG_RD(sc, MISC_REG_RESET_REG_2);
9129 if (!CHIP_IS_E3(sc)) {
9130 val = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9131 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9132 if ((mask & reset_reg) && val) {
9133 base_addr = SC_PORT(sc) ? NIG_REG_INGRESS_BMAC1_MEM
9134 : NIG_REG_INGRESS_BMAC0_MEM;
9135 offset = CHIP_IS_E2(sc) ? BIGMAC2_REGISTER_BMAC_CONTROL
9136 : BIGMAC_REGISTER_BMAC_CONTROL;
9139 * use rd/wr since we cannot use dmae. This is safe
9140 * since MCP won't access the bus due to the request
9141 * to unload, and no function on the path can be
9142 * loaded at this time.
9144 wb_data[0] = REG_RD(sc, base_addr + offset);
9145 wb_data[1] = REG_RD(sc, base_addr + offset + 0x4);
9146 vals->bmac_addr = base_addr + offset;
9147 vals->bmac_val[0] = wb_data[0];
9148 vals->bmac_val[1] = wb_data[1];
9149 wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE;
9150 REG_WR(sc, vals->bmac_addr, wb_data[0]);
9151 REG_WR(sc, vals->bmac_addr + 0x4, wb_data[1]);
9154 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + SC_PORT(sc) * 4;
9155 vals->emac_val = REG_RD(sc, vals->emac_addr);
9156 REG_WR(sc, vals->emac_addr, 0);
9159 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9160 base_addr = SC_PORT(sc) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9161 val = REG_RD(sc, base_addr + XMAC_REG_PFC_CTRL_HI);
9162 REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9164 REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9166 vals->xmac_addr = base_addr + XMAC_REG_CTRL;
9167 vals->xmac_val = REG_RD(sc, vals->xmac_addr);
9168 REG_WR(sc, vals->xmac_addr, 0);
9172 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9173 if (mask & reset_reg) {
9174 base_addr = SC_PORT(sc) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9175 vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
9176 vals->umac_val = REG_RD(sc, vals->umac_addr);
9177 REG_WR(sc, vals->umac_addr, 0);
9187 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9188 #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
9189 #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
9190 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
9193 bnx2x_prev_unload_undi_inc(struct bnx2x_softc *sc, uint8_t port, uint8_t inc)
9196 uint32_t tmp_reg = REG_RD(sc, BNX2X_PREV_UNDI_PROD_ADDR(port));
9198 rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9199 bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9201 tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9202 REG_WR(sc, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9205 static int bnx2x_prev_unload_common(struct bnx2x_softc *sc)
9207 uint32_t reset_reg, tmp_reg = 0, rc;
9208 uint8_t prev_undi = FALSE;
9209 struct bnx2x_mac_vals mac_vals;
9210 uint32_t timer_count = 1000;
9214 * It is possible a previous function received 'common' answer,
9215 * but hasn't loaded yet, therefore creating a scenario of
9216 * multiple functions receiving 'common' on the same path.
9218 memset(&mac_vals, 0, sizeof(mac_vals));
9220 if (bnx2x_prev_is_path_marked(sc)) {
9221 return bnx2x_prev_mcp_done(sc);
9224 reset_reg = REG_RD(sc, MISC_REG_RESET_REG_1);
9226 /* Reset should be performed after BRB is emptied */
9227 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
9228 /* Close the MAC Rx to prevent BRB from filling up */
9229 bnx2x_prev_unload_close_mac(sc, &mac_vals);
9231 /* close LLH filters towards the BRB */
9232 elink_set_rx_filter(&sc->link_params, 0);
9235 * Check if the UNDI driver was previously loaded.
9236 * UNDI driver initializes CID offset for normal bell to 0x7
9238 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
9239 tmp_reg = REG_RD(sc, DORQ_REG_NORM_CID_OFST);
9240 if (tmp_reg == 0x7) {
9241 PMD_DRV_LOG(DEBUG, sc, "UNDI previously loaded");
9243 /* clear the UNDI indication */
9244 REG_WR(sc, DORQ_REG_NORM_CID_OFST, 0);
9245 /* clear possible idle check errors */
9246 REG_RD(sc, NIG_REG_NIG_INT_STS_CLR_0);
9250 /* wait until BRB is empty */
9251 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9252 while (timer_count) {
9255 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9260 PMD_DRV_LOG(DEBUG, sc, "BRB still has 0x%08x", tmp_reg);
9262 /* reset timer as long as BRB actually gets emptied */
9263 if (prev_brb > tmp_reg) {
9269 /* If UNDI resides in memory, manually increment it */
9271 bnx2x_prev_unload_undi_inc(sc, SC_PORT(sc), 1);
9278 PMD_DRV_LOG(NOTICE, sc, "Failed to empty BRB");
9282 /* No packets are in the pipeline, path is ready for reset */
9283 bnx2x_reset_common(sc);
9285 if (mac_vals.xmac_addr) {
9286 REG_WR(sc, mac_vals.xmac_addr, mac_vals.xmac_val);
9288 if (mac_vals.umac_addr) {
9289 REG_WR(sc, mac_vals.umac_addr, mac_vals.umac_val);
9291 if (mac_vals.emac_addr) {
9292 REG_WR(sc, mac_vals.emac_addr, mac_vals.emac_val);
9294 if (mac_vals.bmac_addr) {
9295 REG_WR(sc, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
9296 REG_WR(sc, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
9299 rc = bnx2x_prev_mark_path(sc, prev_undi);
9301 bnx2x_prev_mcp_done(sc);
9305 return bnx2x_prev_mcp_done(sc);
9308 static int bnx2x_prev_unload_uncommon(struct bnx2x_softc *sc)
9312 /* Test if previous unload process was already finished for this path */
9313 if (bnx2x_prev_is_path_marked(sc)) {
9314 return bnx2x_prev_mcp_done(sc);
9318 * If function has FLR capabilities, and existing FW version matches
9319 * the one required, then FLR will be sufficient to clean any residue
9320 * left by previous driver
9322 rc = bnx2x_nic_load_analyze_req(sc, FW_MSG_CODE_DRV_LOAD_FUNCTION);
9324 /* fw version is good */
9325 rc = bnx2x_do_flr(sc);
9329 /* FLR was performed */
9333 PMD_DRV_LOG(INFO, sc, "Could not FLR");
9335 /* Close the MCP request, return failure */
9336 rc = bnx2x_prev_mcp_done(sc);
9338 rc = BNX2X_PREV_WAIT_NEEDED;
9344 static int bnx2x_prev_unload(struct bnx2x_softc *sc)
9346 int time_counter = 10;
9347 uint32_t fw, hw_lock_reg, hw_lock_val;
9351 * Clear HW from errors which may have resulted from an interrupted
9354 bnx2x_prev_interrupted_dmae(sc);
9356 /* Release previously held locks */
9357 if (SC_FUNC(sc) <= 5)
9358 hw_lock_reg = (MISC_REG_DRIVER_CONTROL_1 + SC_FUNC(sc) * 8);
9361 (MISC_REG_DRIVER_CONTROL_7 + (SC_FUNC(sc) - 6) * 8);
9363 hw_lock_val = (REG_RD(sc, hw_lock_reg));
9365 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
9366 REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
9367 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << SC_PORT(sc)));
9369 REG_WR(sc, hw_lock_reg, 0xffffffff);
9372 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(sc, MCP_REG_MCPR_ACCESS_LOCK)) {
9373 REG_WR(sc, MCP_REG_MCPR_ACCESS_LOCK, 0);
9377 /* Lock MCP using an unload request */
9378 fw = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
9380 PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
9385 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
9386 rc = bnx2x_prev_unload_common(sc);
9390 /* non-common reply from MCP might require looping */
9391 rc = bnx2x_prev_unload_uncommon(sc);
9392 if (rc != BNX2X_PREV_WAIT_NEEDED) {
9397 } while (--time_counter);
9399 if (!time_counter || rc) {
9400 PMD_DRV_LOG(NOTICE, sc, "Failed to unload previous driver!");
9408 bnx2x_dcbx_set_state(struct bnx2x_softc *sc, uint8_t dcb_on, uint32_t dcbx_enabled)
9410 if (!CHIP_IS_E1x(sc)) {
9411 sc->dcb_state = dcb_on;
9412 sc->dcbx_enabled = dcbx_enabled;
9414 sc->dcb_state = FALSE;
9415 sc->dcbx_enabled = BNX2X_DCBX_ENABLED_INVALID;
9417 PMD_DRV_LOG(DEBUG, sc,
9418 "DCB state [%s:%s]",
9419 dcb_on ? "ON" : "OFF",
9420 (dcbx_enabled == BNX2X_DCBX_ENABLED_OFF) ? "user-mode" :
9422 BNX2X_DCBX_ENABLED_ON_NEG_OFF) ? "on-chip static"
9424 BNX2X_DCBX_ENABLED_ON_NEG_ON) ?
9425 "on-chip with negotiation" : "invalid");
9428 static int bnx2x_set_qm_cid_count(struct bnx2x_softc *sc)
9430 int cid_count = BNX2X_L2_MAX_CID(sc);
9432 if (CNIC_SUPPORT(sc)) {
9433 cid_count += CNIC_CID_MAX;
9436 return roundup(cid_count, QM_CID_ROUND);
9439 static void bnx2x_init_multi_cos(struct bnx2x_softc *sc)
9443 uint32_t pri_map = 0;
9445 for (pri = 0; pri < BNX2X_MAX_PRIORITY; pri++) {
9446 cos = ((pri_map & (0xf << (pri * 4))) >> (pri * 4));
9447 if (cos < sc->max_cos) {
9448 sc->prio_to_cos[pri] = cos;
9450 PMD_DRV_LOG(WARNING, sc,
9451 "Invalid COS %d for priority %d "
9452 "(max COS is %d), setting to 0", cos, pri,
9454 sc->prio_to_cos[pri] = 0;
9459 static int bnx2x_pci_get_caps(struct bnx2x_softc *sc)
9466 struct bnx2x_pci_cap *cap;
9468 cap = sc->pci_caps = rte_zmalloc("caps", sizeof(struct bnx2x_pci_cap),
9469 RTE_CACHE_LINE_SIZE);
9471 PMD_DRV_LOG(NOTICE, sc, "Failed to allocate memory");
9476 pci_read(sc, PCI_STATUS, &status, 2);
9477 if (!(status & PCI_STATUS_CAP_LIST)) {
9479 pci_read(sc, PCIR_STATUS, &status, 2);
9480 if (!(status & PCIM_STATUS_CAPPRESENT)) {
9482 PMD_DRV_LOG(NOTICE, sc, "PCIe capability reading failed");
9487 pci_read(sc, PCI_CAPABILITY_LIST, &pci_cap.next, 1);
9489 pci_read(sc, PCIR_CAP_PTR, &pci_cap.next, 1);
9491 while (pci_cap.next) {
9492 cap->addr = pci_cap.next & ~3;
9493 pci_read(sc, pci_cap.next & ~3, &pci_cap, 2);
9494 if (pci_cap.id == 0xff)
9496 cap->id = pci_cap.id;
9497 cap->type = BNX2X_PCI_CAP;
9498 cap->next = rte_zmalloc("pci_cap",
9499 sizeof(struct bnx2x_pci_cap),
9500 RTE_CACHE_LINE_SIZE);
9502 PMD_DRV_LOG(NOTICE, sc, "Failed to allocate memory");
9511 static void bnx2x_init_rte(struct bnx2x_softc *sc)
9514 sc->max_tx_queues = min(BNX2X_VF_MAX_QUEUES_PER_VF,
9516 sc->max_rx_queues = min(BNX2X_VF_MAX_QUEUES_PER_VF,
9519 sc->max_rx_queues = BNX2X_MAX_RSS_COUNT(sc);
9520 sc->max_tx_queues = sc->max_rx_queues;
9524 #define FW_HEADER_LEN 104
9525 #define FW_NAME_57711 "/lib/firmware/bnx2x/bnx2x-e1h-7.2.51.0.fw"
9526 #define FW_NAME_57810 "/lib/firmware/bnx2x/bnx2x-e2-7.2.51.0.fw"
9528 void bnx2x_load_firmware(struct bnx2x_softc *sc)
9534 fwname = sc->devinfo.device_id == CHIP_NUM_57711
9535 ? FW_NAME_57711 : FW_NAME_57810;
9536 f = open(fwname, O_RDONLY);
9538 PMD_DRV_LOG(NOTICE, sc, "Can't open firmware file");
9542 if (fstat(f, &st) < 0) {
9543 PMD_DRV_LOG(NOTICE, sc, "Can't stat firmware file");
9548 sc->firmware = rte_zmalloc("bnx2x_fw", st.st_size, RTE_CACHE_LINE_SIZE);
9549 if (!sc->firmware) {
9550 PMD_DRV_LOG(NOTICE, sc, "Can't allocate memory for firmware");
9555 if (read(f, sc->firmware, st.st_size) != st.st_size) {
9556 PMD_DRV_LOG(NOTICE, sc, "Can't read firmware data");
9562 sc->fw_len = st.st_size;
9563 if (sc->fw_len < FW_HEADER_LEN) {
9564 PMD_DRV_LOG(NOTICE, sc,
9565 "Invalid fw size: %" PRIu64, sc->fw_len);
9568 PMD_DRV_LOG(DEBUG, sc, "fw_len = %" PRIu64, sc->fw_len);
9572 bnx2x_data_to_init_ops(uint8_t * data, struct raw_op *dst, uint32_t len)
9574 uint32_t *src = (uint32_t *) data;
9577 for (i = 0, j = 0; i < len / 8; ++i, j += 2) {
9578 tmp = rte_be_to_cpu_32(src[j]);
9579 dst[i].op = (tmp >> 24) & 0xFF;
9580 dst[i].offset = tmp & 0xFFFFFF;
9581 dst[i].raw_data = rte_be_to_cpu_32(src[j + 1]);
9586 bnx2x_data_to_init_offsets(uint8_t * data, uint16_t * dst, uint32_t len)
9588 uint16_t *src = (uint16_t *) data;
9591 for (i = 0; i < len / 2; ++i)
9592 dst[i] = rte_be_to_cpu_16(src[i]);
9595 static void bnx2x_data_to_init_data(uint8_t * data, uint32_t * dst, uint32_t len)
9597 uint32_t *src = (uint32_t *) data;
9600 for (i = 0; i < len / 4; ++i)
9601 dst[i] = rte_be_to_cpu_32(src[i]);
9604 static void bnx2x_data_to_iro_array(uint8_t * data, struct iro *dst, uint32_t len)
9606 uint32_t *src = (uint32_t *) data;
9609 for (i = 0, j = 0; i < len / sizeof(struct iro); ++i, ++j) {
9610 dst[i].base = rte_be_to_cpu_32(src[j++]);
9611 tmp = rte_be_to_cpu_32(src[j]);
9612 dst[i].m1 = (tmp >> 16) & 0xFFFF;
9613 dst[i].m2 = tmp & 0xFFFF;
9615 tmp = rte_be_to_cpu_32(src[j]);
9616 dst[i].m3 = (tmp >> 16) & 0xFFFF;
9617 dst[i].size = tmp & 0xFFFF;
9622 * Device attach function.
9624 * Allocates device resources, performs secondary chip identification, and
9625 * initializes driver instance variables. This function is called from driver
9626 * load after a successful probe.
9629 * 0 = Success, >0 = Failure
9631 int bnx2x_attach(struct bnx2x_softc *sc)
9635 PMD_DRV_LOG(DEBUG, sc, "Starting attach...");
9637 rc = bnx2x_pci_get_caps(sc);
9639 PMD_DRV_LOG(NOTICE, sc, "PCIe caps reading was failed");
9643 sc->state = BNX2X_STATE_CLOSED;
9645 pci_write_long(sc, PCICFG_GRC_ADDRESS, PCICFG_VENDOR_ID_OFFSET);
9647 sc->igu_base_addr = IS_VF(sc) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
9649 /* get PCI capabilites */
9650 bnx2x_probe_pci_caps(sc);
9652 if (sc->devinfo.pcie_msix_cap_reg != 0) {
9655 (sc->devinfo.pcie_msix_cap_reg + PCIR_MSIX_CTRL), &val,
9657 sc->igu_sb_cnt = (val & PCIM_MSIXCTRL_TABLE_SIZE) + 1;
9662 /* Init RTE stuff */
9666 /* Enable internal target-read (in case we are probed after PF
9667 * FLR). Must be done prior to any BAR read access. Only for
9670 if (!CHIP_IS_E1x(sc)) {
9671 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ,
9676 /* get device info and set params */
9677 if (bnx2x_get_device_info(sc) != 0) {
9678 PMD_DRV_LOG(NOTICE, sc, "getting device info");
9682 /* get phy settings from shmem and 'and' against admin settings */
9683 bnx2x_get_phy_info(sc);
9685 /* Left mac of VF unfilled, PF should set it for VF */
9686 memset(sc->link_params.mac_addr, 0, ETHER_ADDR_LEN);
9691 /* set the default MTU (changed via ifconfig) */
9692 sc->mtu = ETHER_MTU;
9694 bnx2x_set_modes_bitmap(sc);
9696 /* need to reset chip if UNDI was active */
9697 if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
9700 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
9701 DRV_MSG_SEQ_NUMBER_MASK);
9702 bnx2x_prev_unload(sc);
9705 bnx2x_dcbx_set_state(sc, FALSE, BNX2X_DCBX_ENABLED_OFF);
9707 /* calculate qm_cid_count */
9708 sc->qm_cid_count = bnx2x_set_qm_cid_count(sc);
9711 bnx2x_init_multi_cos(sc);
9717 bnx2x_igu_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t segment,
9718 uint16_t index, uint8_t op, uint8_t update)
9720 uint32_t igu_addr = sc->igu_base_addr;
9721 igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
9722 bnx2x_igu_ack_sb_gen(sc, segment, index, op, update, igu_addr);
9726 bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t storm,
9727 uint16_t index, uint8_t op, uint8_t update)
9729 if (unlikely(sc->devinfo.int_block == INT_BLOCK_HC))
9730 bnx2x_hc_ack_sb(sc, igu_sb_id, storm, index, op, update);
9733 if (CHIP_INT_MODE_IS_BC(sc)) {
9735 } else if (igu_sb_id != sc->igu_dsb_id) {
9736 segment = IGU_SEG_ACCESS_DEF;
9737 } else if (storm == ATTENTION_ID) {
9738 segment = IGU_SEG_ACCESS_ATTN;
9740 segment = IGU_SEG_ACCESS_DEF;
9742 bnx2x_igu_ack_sb(sc, igu_sb_id, segment, index, op, update);
9747 bnx2x_igu_clear_sb_gen(struct bnx2x_softc *sc, uint8_t func, uint8_t idu_sb_id,
9750 uint32_t data, ctl, cnt = 100;
9751 uint32_t igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
9752 uint32_t igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
9753 uint32_t igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP +
9754 (idu_sb_id / 32) * 4;
9755 uint32_t sb_bit = 1 << (idu_sb_id % 32);
9756 uint32_t func_encode = func |
9757 (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
9758 uint32_t addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
9760 /* Not supported in BC mode */
9761 if (CHIP_INT_MODE_IS_BC(sc)) {
9765 data = ((IGU_USE_REGISTER_cstorm_type_0_sb_cleanup <<
9766 IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
9767 IGU_REGULAR_CLEANUP_SET | IGU_REGULAR_BCLEANUP);
9769 ctl = ((addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT) |
9770 (func_encode << IGU_CTRL_REG_FID_SHIFT) |
9771 (IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT));
9773 REG_WR(sc, igu_addr_data, data);
9777 PMD_DRV_LOG(DEBUG, sc, "write 0x%08x to IGU(via GRC) addr 0x%x",
9779 REG_WR(sc, igu_addr_ctl, ctl);
9783 /* wait for clean up to finish */
9784 while (!(REG_RD(sc, igu_addr_ack) & sb_bit) && --cnt) {
9788 if (!(REG_RD(sc, igu_addr_ack) & sb_bit)) {
9789 PMD_DRV_LOG(DEBUG, sc,
9790 "Unable to finish IGU cleanup: "
9791 "idu_sb_id %d offset %d bit %d (cnt %d)",
9792 idu_sb_id, idu_sb_id / 32, idu_sb_id % 32, cnt);
9796 static void bnx2x_igu_clear_sb(struct bnx2x_softc *sc, uint8_t idu_sb_id)
9798 bnx2x_igu_clear_sb_gen(sc, SC_FUNC(sc), idu_sb_id, TRUE /*PF*/);
9801 /*******************/
9802 /* ECORE CALLBACKS */
9803 /*******************/
9805 static void bnx2x_reset_common(struct bnx2x_softc *sc)
9807 uint32_t val = 0x1400;
9809 PMD_INIT_FUNC_TRACE(sc);
9812 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR),
9815 if (CHIP_IS_E3(sc)) {
9816 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
9817 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
9820 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR), val);
9823 static void bnx2x_common_init_phy(struct bnx2x_softc *sc)
9825 uint32_t shmem_base[2];
9826 uint32_t shmem2_base[2];
9828 /* Avoid common init in case MFW supports LFA */
9829 if (SHMEM2_RD(sc, size) >
9830 (uint32_t) offsetof(struct shmem2_region,
9831 lfa_host_addr[SC_PORT(sc)])) {
9835 shmem_base[0] = sc->devinfo.shmem_base;
9836 shmem2_base[0] = sc->devinfo.shmem2_base;
9838 if (!CHIP_IS_E1x(sc)) {
9839 shmem_base[1] = SHMEM2_RD(sc, other_shmem_base_addr);
9840 shmem2_base[1] = SHMEM2_RD(sc, other_shmem2_base_addr);
9843 elink_common_init_phy(sc, shmem_base, shmem2_base,
9844 sc->devinfo.chip_id, 0);
9847 static void bnx2x_pf_disable(struct bnx2x_softc *sc)
9849 uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
9851 val &= ~IGU_PF_CONF_FUNC_EN;
9853 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
9854 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
9855 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 0);
9858 static void bnx2x_init_pxp(struct bnx2x_softc *sc)
9861 int r_order, w_order;
9863 devctl = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_CTL);
9865 w_order = ((devctl & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5);
9866 r_order = ((devctl & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12);
9868 ecore_init_pxp_arb(sc, r_order, w_order);
9871 static uint32_t bnx2x_get_pretend_reg(struct bnx2x_softc *sc)
9873 uint32_t base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9874 uint32_t stride = (PXP2_REG_PGL_PRETEND_FUNC_F1 - base);
9875 return base + (SC_ABS_FUNC(sc)) * stride;
9879 * Called only on E1H or E2.
9880 * When pretending to be PF, the pretend value is the function number 0..7.
9881 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
9884 static int bnx2x_pretend_func(struct bnx2x_softc *sc, uint16_t pretend_func_val)
9886 uint32_t pretend_reg;
9888 if (CHIP_IS_E1H(sc) && (pretend_func_val > E1H_FUNC_MAX))
9891 /* get my own pretend register */
9892 pretend_reg = bnx2x_get_pretend_reg(sc);
9893 REG_WR(sc, pretend_reg, pretend_func_val);
9894 REG_RD(sc, pretend_reg);
9898 static void bnx2x_setup_fan_failure_detection(struct bnx2x_softc *sc)
9905 val = (SHMEM_RD(sc, dev_info.shared_hw_config.config2) &
9906 SHARED_HW_CFG_FAN_FAILURE_MASK);
9908 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) {
9912 * The fan failure mechanism is usually related to the PHY type since
9913 * the power consumption of the board is affected by the PHY. Currently,
9914 * fan is required for most designs with SFX7101, BNX2X8727 and BNX2X8481.
9916 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) {
9917 for (port = PORT_0; port < PORT_MAX; port++) {
9918 is_required |= elink_fan_failure_det_req(sc,
9922 devinfo.shmem2_base,
9927 if (is_required == 0) {
9931 /* Fan failure is indicated by SPIO 5 */
9932 bnx2x_set_spio(sc, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
9934 /* set to active low mode */
9935 val = REG_RD(sc, MISC_REG_SPIO_INT);
9936 val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
9937 REG_WR(sc, MISC_REG_SPIO_INT, val);
9939 /* enable interrupt to signal the IGU */
9940 val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
9941 val |= MISC_SPIO_SPIO5;
9942 REG_WR(sc, MISC_REG_SPIO_EVENT_EN, val);
9945 static void bnx2x_enable_blocks_attention(struct bnx2x_softc *sc)
9949 REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0);
9950 if (!CHIP_IS_E1x(sc)) {
9951 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0x40);
9953 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0);
9955 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
9956 REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
9958 * mask read length error interrupts in brb for parser
9959 * (parsing unit and 'checksum and crc' unit)
9960 * these errors are legal (PU reads fixed length and CAC can cause
9961 * read length error on truncated packets)
9963 REG_WR(sc, BRB1_REG_BRB1_INT_MASK, 0xFC00);
9964 REG_WR(sc, QM_REG_QM_INT_MASK, 0);
9965 REG_WR(sc, TM_REG_TM_INT_MASK, 0);
9966 REG_WR(sc, XSDM_REG_XSDM_INT_MASK_0, 0);
9967 REG_WR(sc, XSDM_REG_XSDM_INT_MASK_1, 0);
9968 REG_WR(sc, XCM_REG_XCM_INT_MASK, 0);
9969 /* REG_WR(sc, XSEM_REG_XSEM_INT_MASK_0, 0); */
9970 /* REG_WR(sc, XSEM_REG_XSEM_INT_MASK_1, 0); */
9971 REG_WR(sc, USDM_REG_USDM_INT_MASK_0, 0);
9972 REG_WR(sc, USDM_REG_USDM_INT_MASK_1, 0);
9973 REG_WR(sc, UCM_REG_UCM_INT_MASK, 0);
9974 /* REG_WR(sc, USEM_REG_USEM_INT_MASK_0, 0); */
9975 /* REG_WR(sc, USEM_REG_USEM_INT_MASK_1, 0); */
9976 REG_WR(sc, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
9977 REG_WR(sc, CSDM_REG_CSDM_INT_MASK_0, 0);
9978 REG_WR(sc, CSDM_REG_CSDM_INT_MASK_1, 0);
9979 REG_WR(sc, CCM_REG_CCM_INT_MASK, 0);
9980 /* REG_WR(sc, CSEM_REG_CSEM_INT_MASK_0, 0); */
9981 /* REG_WR(sc, CSEM_REG_CSEM_INT_MASK_1, 0); */
9983 val = (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
9984 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
9985 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN);
9986 if (!CHIP_IS_E1x(sc)) {
9987 val |= (PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
9988 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED);
9990 REG_WR(sc, PXP2_REG_PXP2_INT_MASK_0, val);
9992 REG_WR(sc, TSDM_REG_TSDM_INT_MASK_0, 0);
9993 REG_WR(sc, TSDM_REG_TSDM_INT_MASK_1, 0);
9994 REG_WR(sc, TCM_REG_TCM_INT_MASK, 0);
9995 /* REG_WR(sc, TSEM_REG_TSEM_INT_MASK_0, 0); */
9997 if (!CHIP_IS_E1x(sc)) {
9998 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
9999 REG_WR(sc, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
10002 REG_WR(sc, CDU_REG_CDU_INT_MASK, 0);
10003 REG_WR(sc, DMAE_REG_DMAE_INT_MASK, 0);
10004 /* REG_WR(sc, MISC_REG_MISC_INT_MASK, 0); */
10005 REG_WR(sc, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
10009 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
10011 * @sc: driver handle
10013 static int bnx2x_init_hw_common(struct bnx2x_softc *sc)
10015 uint8_t abs_func_id;
10018 PMD_DRV_LOG(DEBUG, sc,
10019 "starting common init for func %d", SC_ABS_FUNC(sc));
10022 * take the RESET lock to protect undi_unload flow from accessing
10023 * registers while we are resetting the chip
10025 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10027 bnx2x_reset_common(sc);
10029 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET), 0xffffffff);
10032 if (CHIP_IS_E3(sc)) {
10033 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
10034 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
10037 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET), val);
10039 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10041 ecore_init_block(sc, BLOCK_MISC, PHASE_COMMON);
10043 if (!CHIP_IS_E1x(sc)) {
10045 * 4-port mode or 2-port mode we need to turn off master-enable for
10046 * everyone. After that we turn it back on for self. So, we disregard
10047 * multi-function, and always disable all functions on the given path,
10048 * this means 0,2,4,6 for path 0 and 1,3,5,7 for path 1
10050 for (abs_func_id = SC_PATH(sc);
10051 abs_func_id < (E2_FUNC_MAX * 2); abs_func_id += 2) {
10052 if (abs_func_id == SC_ABS_FUNC(sc)) {
10054 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
10059 bnx2x_pretend_func(sc, abs_func_id);
10061 /* clear pf enable */
10062 bnx2x_pf_disable(sc);
10064 bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10068 ecore_init_block(sc, BLOCK_PXP, PHASE_COMMON);
10070 ecore_init_block(sc, BLOCK_PXP2, PHASE_COMMON);
10071 bnx2x_init_pxp(sc);
10073 #ifdef __BIG_ENDIAN
10074 REG_WR(sc, PXP2_REG_RQ_QM_ENDIAN_M, 1);
10075 REG_WR(sc, PXP2_REG_RQ_TM_ENDIAN_M, 1);
10076 REG_WR(sc, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
10077 REG_WR(sc, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
10078 REG_WR(sc, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
10079 /* make sure this value is 0 */
10080 REG_WR(sc, PXP2_REG_RQ_HC_ENDIAN_M, 0);
10082 //REG_WR(sc, PXP2_REG_RD_PBF_SWAP_MODE, 1);
10083 REG_WR(sc, PXP2_REG_RD_QM_SWAP_MODE, 1);
10084 REG_WR(sc, PXP2_REG_RD_TM_SWAP_MODE, 1);
10085 REG_WR(sc, PXP2_REG_RD_SRC_SWAP_MODE, 1);
10086 REG_WR(sc, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
10089 ecore_ilt_init_page_size(sc, INITOP_SET);
10091 if (CHIP_REV_IS_FPGA(sc) && CHIP_IS_E1H(sc)) {
10092 REG_WR(sc, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
10095 /* let the HW do it's magic... */
10098 /* finish PXP init */
10100 val = REG_RD(sc, PXP2_REG_RQ_CFG_DONE);
10102 PMD_DRV_LOG(NOTICE, sc, "PXP2 CFG failed");
10105 val = REG_RD(sc, PXP2_REG_RD_INIT_DONE);
10107 PMD_DRV_LOG(NOTICE, sc, "PXP2 RD_INIT failed");
10112 * Timer bug workaround for E2 only. We need to set the entire ILT to have
10113 * entries with value "0" and valid bit on. This needs to be done by the
10114 * first PF that is loaded in a path (i.e. common phase)
10116 if (!CHIP_IS_E1x(sc)) {
10118 * In E2 there is a bug in the timers block that can cause function 6 / 7
10119 * (i.e. vnic3) to start even if it is marked as "scan-off".
10120 * This occurs when a different function (func2,3) is being marked
10121 * as "scan-off". Real-life scenario for example: if a driver is being
10122 * load-unloaded while func6,7 are down. This will cause the timer to access
10123 * the ilt, translate to a logical address and send a request to read/write.
10124 * Since the ilt for the function that is down is not valid, this will cause
10125 * a translation error which is unrecoverable.
10126 * The Workaround is intended to make sure that when this happens nothing
10127 * fatal will occur. The workaround:
10128 * 1. First PF driver which loads on a path will:
10129 * a. After taking the chip out of reset, by using pretend,
10130 * it will write "0" to the following registers of
10132 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10133 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
10134 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
10135 * And for itself it will write '1' to
10136 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
10137 * dmae-operations (writing to pram for example.)
10138 * note: can be done for only function 6,7 but cleaner this
10140 * b. Write zero+valid to the entire ILT.
10141 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
10142 * VNIC3 (of that port). The range allocated will be the
10143 * entire ILT. This is needed to prevent ILT range error.
10144 * 2. Any PF driver load flow:
10145 * a. ILT update with the physical addresses of the allocated
10147 * b. Wait 20msec. - note that this timeout is needed to make
10148 * sure there are no requests in one of the PXP internal
10149 * queues with "old" ILT addresses.
10150 * c. PF enable in the PGLC.
10151 * d. Clear the was_error of the PF in the PGLC. (could have
10152 * occurred while driver was down)
10153 * e. PF enable in the CFC (WEAK + STRONG)
10154 * f. Timers scan enable
10155 * 3. PF driver unload flow:
10156 * a. Clear the Timers scan_en.
10157 * b. Polling for scan_on=0 for that PF.
10158 * c. Clear the PF enable bit in the PXP.
10159 * d. Clear the PF enable in the CFC (WEAK + STRONG)
10160 * e. Write zero+valid to all ILT entries (The valid bit must
10162 * f. If this is VNIC 3 of a port then also init
10163 * first_timers_ilt_entry to zero and last_timers_ilt_entry
10164 * to the last enrty in the ILT.
10167 * Currently the PF error in the PGLC is non recoverable.
10168 * In the future the there will be a recovery routine for this error.
10169 * Currently attention is masked.
10170 * Having an MCP lock on the load/unload process does not guarantee that
10171 * there is no Timer disable during Func6/7 enable. This is because the
10172 * Timers scan is currently being cleared by the MCP on FLR.
10173 * Step 2.d can be done only for PF6/7 and the driver can also check if
10174 * there is error before clearing it. But the flow above is simpler and
10176 * All ILT entries are written by zero+valid and not just PF6/7
10177 * ILT entries since in the future the ILT entries allocation for
10178 * PF-s might be dynamic.
10180 struct ilt_client_info ilt_cli;
10181 struct ecore_ilt ilt;
10183 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
10184 memset(&ilt, 0, sizeof(struct ecore_ilt));
10186 /* initialize dummy TM client */
10188 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
10189 ilt_cli.client_num = ILT_CLIENT_TM;
10192 * Step 1: set zeroes to all ilt page entries with valid bit on
10193 * Step 2: set the timers first/last ilt entry to point
10194 * to the entire range to prevent ILT range error for 3rd/4th
10195 * vnic (this code assumes existence of the vnic)
10197 * both steps performed by call to ecore_ilt_client_init_op()
10198 * with dummy TM client
10200 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
10201 * and his brother are split registers
10204 bnx2x_pretend_func(sc, (SC_PATH(sc) + 6));
10205 ecore_ilt_client_init_op_ilt(sc, &ilt, &ilt_cli, INITOP_CLEAR);
10206 bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10208 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
10209 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
10210 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
10213 REG_WR(sc, PXP2_REG_RQ_DISABLE_INPUTS, 0);
10214 REG_WR(sc, PXP2_REG_RD_DISABLE_INPUTS, 0);
10216 if (!CHIP_IS_E1x(sc)) {
10219 ecore_init_block(sc, BLOCK_PGLUE_B, PHASE_COMMON);
10220 ecore_init_block(sc, BLOCK_ATC, PHASE_COMMON);
10222 /* let the HW do it's magic... */
10225 val = REG_RD(sc, ATC_REG_ATC_INIT_DONE);
10226 } while (factor-- && (val != 1));
10229 PMD_DRV_LOG(NOTICE, sc, "ATC_INIT failed");
10234 ecore_init_block(sc, BLOCK_DMAE, PHASE_COMMON);
10236 /* clean the DMAE memory */
10237 sc->dmae_ready = 1;
10238 ecore_init_fill(sc, TSEM_REG_PRAM, 0, 8);
10240 ecore_init_block(sc, BLOCK_TCM, PHASE_COMMON);
10242 ecore_init_block(sc, BLOCK_UCM, PHASE_COMMON);
10244 ecore_init_block(sc, BLOCK_CCM, PHASE_COMMON);
10246 ecore_init_block(sc, BLOCK_XCM, PHASE_COMMON);
10248 bnx2x_read_dmae(sc, XSEM_REG_PASSIVE_BUFFER, 3);
10249 bnx2x_read_dmae(sc, CSEM_REG_PASSIVE_BUFFER, 3);
10250 bnx2x_read_dmae(sc, TSEM_REG_PASSIVE_BUFFER, 3);
10251 bnx2x_read_dmae(sc, USEM_REG_PASSIVE_BUFFER, 3);
10253 ecore_init_block(sc, BLOCK_QM, PHASE_COMMON);
10255 /* QM queues pointers table */
10256 ecore_qm_init_ptr_table(sc, sc->qm_cid_count, INITOP_SET);
10258 /* soft reset pulse */
10259 REG_WR(sc, QM_REG_SOFT_RESET, 1);
10260 REG_WR(sc, QM_REG_SOFT_RESET, 0);
10262 if (CNIC_SUPPORT(sc))
10263 ecore_init_block(sc, BLOCK_TM, PHASE_COMMON);
10265 ecore_init_block(sc, BLOCK_DORQ, PHASE_COMMON);
10266 REG_WR(sc, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
10268 if (!CHIP_REV_IS_SLOW(sc)) {
10269 /* enable hw interrupt from doorbell Q */
10270 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
10273 ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON);
10275 ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON);
10276 REG_WR(sc, PRS_REG_A_PRSU_20, 0xf);
10277 REG_WR(sc, PRS_REG_E1HOV_MODE, sc->devinfo.mf_info.path_has_ovlan);
10279 if (!CHIP_IS_E1x(sc) && !CHIP_IS_E3B0(sc)) {
10280 if (IS_MF_AFEX(sc)) {
10282 * configure that AFEX and VLAN headers must be
10283 * received in AFEX mode
10285 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC, 0xE);
10286 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS, 0xA);
10287 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
10288 REG_WR(sc, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
10289 REG_WR(sc, PRS_REG_TAG_LEN_0, 0x4);
10292 * Bit-map indicating which L2 hdrs may appear
10293 * after the basic Ethernet header
10295 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC,
10296 sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10300 ecore_init_block(sc, BLOCK_TSDM, PHASE_COMMON);
10301 ecore_init_block(sc, BLOCK_CSDM, PHASE_COMMON);
10302 ecore_init_block(sc, BLOCK_USDM, PHASE_COMMON);
10303 ecore_init_block(sc, BLOCK_XSDM, PHASE_COMMON);
10305 if (!CHIP_IS_E1x(sc)) {
10306 /* reset VFC memories */
10307 REG_WR(sc, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10308 VFC_MEMORIES_RST_REG_CAM_RST |
10309 VFC_MEMORIES_RST_REG_RAM_RST);
10310 REG_WR(sc, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10311 VFC_MEMORIES_RST_REG_CAM_RST |
10312 VFC_MEMORIES_RST_REG_RAM_RST);
10317 ecore_init_block(sc, BLOCK_TSEM, PHASE_COMMON);
10318 ecore_init_block(sc, BLOCK_USEM, PHASE_COMMON);
10319 ecore_init_block(sc, BLOCK_CSEM, PHASE_COMMON);
10320 ecore_init_block(sc, BLOCK_XSEM, PHASE_COMMON);
10322 /* sync semi rtc */
10323 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x80000000);
10324 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x80000000);
10326 ecore_init_block(sc, BLOCK_UPB, PHASE_COMMON);
10327 ecore_init_block(sc, BLOCK_XPB, PHASE_COMMON);
10328 ecore_init_block(sc, BLOCK_PBF, PHASE_COMMON);
10330 if (!CHIP_IS_E1x(sc)) {
10331 if (IS_MF_AFEX(sc)) {
10333 * configure that AFEX and VLAN headers must be
10334 * sent in AFEX mode
10336 REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC, 0xE);
10337 REG_WR(sc, PBF_REG_MUST_HAVE_HDRS, 0xA);
10338 REG_WR(sc, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
10339 REG_WR(sc, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
10340 REG_WR(sc, PBF_REG_TAG_LEN_0, 0x4);
10342 REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC,
10343 sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10347 REG_WR(sc, SRC_REG_SOFT_RST, 1);
10349 ecore_init_block(sc, BLOCK_SRC, PHASE_COMMON);
10351 if (CNIC_SUPPORT(sc)) {
10352 REG_WR(sc, SRC_REG_KEYSEARCH_0, 0x63285672);
10353 REG_WR(sc, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
10354 REG_WR(sc, SRC_REG_KEYSEARCH_2, 0x223aef9b);
10355 REG_WR(sc, SRC_REG_KEYSEARCH_3, 0x26001e3a);
10356 REG_WR(sc, SRC_REG_KEYSEARCH_4, 0x7ae91116);
10357 REG_WR(sc, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
10358 REG_WR(sc, SRC_REG_KEYSEARCH_6, 0x298d8adf);
10359 REG_WR(sc, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
10360 REG_WR(sc, SRC_REG_KEYSEARCH_8, 0x1830f82f);
10361 REG_WR(sc, SRC_REG_KEYSEARCH_9, 0x01e46be7);
10363 REG_WR(sc, SRC_REG_SOFT_RST, 0);
10365 if (sizeof(union cdu_context) != 1024) {
10366 /* we currently assume that a context is 1024 bytes */
10367 PMD_DRV_LOG(NOTICE, sc,
10368 "please adjust the size of cdu_context(%ld)",
10369 (long)sizeof(union cdu_context));
10372 ecore_init_block(sc, BLOCK_CDU, PHASE_COMMON);
10373 val = (4 << 24) + (0 << 12) + 1024;
10374 REG_WR(sc, CDU_REG_CDU_GLOBAL_PARAMS, val);
10376 ecore_init_block(sc, BLOCK_CFC, PHASE_COMMON);
10378 REG_WR(sc, CFC_REG_INIT_REG, 0x7FF);
10379 /* enable context validation interrupt from CFC */
10380 REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
10382 /* set the thresholds to prevent CFC/CDU race */
10383 REG_WR(sc, CFC_REG_DEBUG0, 0x20020000);
10384 ecore_init_block(sc, BLOCK_HC, PHASE_COMMON);
10386 if (!CHIP_IS_E1x(sc) && BNX2X_NOMCP(sc)) {
10387 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x36);
10390 ecore_init_block(sc, BLOCK_IGU, PHASE_COMMON);
10391 ecore_init_block(sc, BLOCK_MISC_AEU, PHASE_COMMON);
10393 /* Reset PCIE errors for debug */
10394 REG_WR(sc, 0x2814, 0xffffffff);
10395 REG_WR(sc, 0x3820, 0xffffffff);
10397 if (!CHIP_IS_E1x(sc)) {
10398 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
10399 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
10400 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
10401 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
10402 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
10403 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
10404 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
10405 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
10406 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
10407 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
10408 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
10411 ecore_init_block(sc, BLOCK_NIG, PHASE_COMMON);
10413 /* in E3 this done in per-port section */
10414 if (!CHIP_IS_E3(sc))
10415 REG_WR(sc, NIG_REG_LLH_MF_MODE, IS_MF(sc));
10417 if (CHIP_IS_E1H(sc)) {
10418 /* not applicable for E2 (and above ...) */
10419 REG_WR(sc, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(sc));
10422 if (CHIP_REV_IS_SLOW(sc)) {
10426 /* finish CFC init */
10427 val = reg_poll(sc, CFC_REG_LL_INIT_DONE, 1, 100, 10);
10429 PMD_DRV_LOG(NOTICE, sc, "CFC LL_INIT failed");
10432 val = reg_poll(sc, CFC_REG_AC_INIT_DONE, 1, 100, 10);
10434 PMD_DRV_LOG(NOTICE, sc, "CFC AC_INIT failed");
10437 val = reg_poll(sc, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
10439 PMD_DRV_LOG(NOTICE, sc, "CFC CAM_INIT failed");
10442 REG_WR(sc, CFC_REG_DEBUG0, 0);
10444 bnx2x_setup_fan_failure_detection(sc);
10446 /* clear PXP2 attentions */
10447 REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
10449 bnx2x_enable_blocks_attention(sc);
10451 if (!CHIP_REV_IS_SLOW(sc)) {
10452 ecore_enable_blocks_parity(sc);
10455 if (!BNX2X_NOMCP(sc)) {
10456 if (CHIP_IS_E1x(sc)) {
10457 bnx2x_common_init_phy(sc);
10465 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
10467 * @sc: driver handle
10469 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc)
10471 int rc = bnx2x_init_hw_common(sc);
10477 /* In E2 2-PORT mode, same ext phy is used for the two paths */
10478 if (!BNX2X_NOMCP(sc)) {
10479 bnx2x_common_init_phy(sc);
10485 static int bnx2x_init_hw_port(struct bnx2x_softc *sc)
10487 int port = SC_PORT(sc);
10488 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
10489 uint32_t low, high;
10492 PMD_DRV_LOG(DEBUG, sc, "starting port init for port %d", port);
10494 REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
10496 ecore_init_block(sc, BLOCK_MISC, init_phase);
10497 ecore_init_block(sc, BLOCK_PXP, init_phase);
10498 ecore_init_block(sc, BLOCK_PXP2, init_phase);
10501 * Timers bug workaround: disables the pf_master bit in pglue at
10502 * common phase, we need to enable it here before any dmae access are
10503 * attempted. Therefore we manually added the enable-master to the
10504 * port phase (it also happens in the function phase)
10506 if (!CHIP_IS_E1x(sc)) {
10507 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
10510 ecore_init_block(sc, BLOCK_ATC, init_phase);
10511 ecore_init_block(sc, BLOCK_DMAE, init_phase);
10512 ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
10513 ecore_init_block(sc, BLOCK_QM, init_phase);
10515 ecore_init_block(sc, BLOCK_TCM, init_phase);
10516 ecore_init_block(sc, BLOCK_UCM, init_phase);
10517 ecore_init_block(sc, BLOCK_CCM, init_phase);
10518 ecore_init_block(sc, BLOCK_XCM, init_phase);
10520 /* QM cid (connection) count */
10521 ecore_qm_init_cid_count(sc, sc->qm_cid_count, INITOP_SET);
10523 if (CNIC_SUPPORT(sc)) {
10524 ecore_init_block(sc, BLOCK_TM, init_phase);
10525 REG_WR(sc, TM_REG_LIN0_SCAN_TIME + port * 4, 20);
10526 REG_WR(sc, TM_REG_LIN0_MAX_ACTIVE_CID + port * 4, 31);
10529 ecore_init_block(sc, BLOCK_DORQ, init_phase);
10531 ecore_init_block(sc, BLOCK_BRB1, init_phase);
10533 if (CHIP_IS_E1H(sc)) {
10535 low = (BNX2X_ONE_PORT(sc) ? 160 : 246);
10536 } else if (sc->mtu > 4096) {
10537 if (BNX2X_ONE_PORT(sc)) {
10541 /* (24*1024 + val*4)/256 */
10542 low = (96 + (val / 64) + ((val % 64) ? 1 : 0));
10545 low = (BNX2X_ONE_PORT(sc) ? 80 : 160);
10547 high = (low + 56); /* 14*1024/256 */
10548 REG_WR(sc, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port * 4, low);
10549 REG_WR(sc, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port * 4, high);
10552 if (CHIP_IS_MODE_4_PORT(sc)) {
10553 REG_WR(sc, SC_PORT(sc) ?
10554 BRB1_REG_MAC_GUARANTIED_1 :
10555 BRB1_REG_MAC_GUARANTIED_0, 40);
10558 ecore_init_block(sc, BLOCK_PRS, init_phase);
10559 if (CHIP_IS_E3B0(sc)) {
10560 if (IS_MF_AFEX(sc)) {
10561 /* configure headers for AFEX mode */
10563 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_1,
10565 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_1,
10567 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_1, 0xA);
10569 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10571 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_0,
10573 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
10576 /* Ovlan exists only if we are in multi-function +
10577 * switch-dependent mode, in switch-independent there
10578 * is no ovlan headers
10580 REG_WR(sc, SC_PORT(sc) ?
10581 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
10582 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10583 (sc->devinfo.mf_info.path_has_ovlan ? 7 : 6));
10587 ecore_init_block(sc, BLOCK_TSDM, init_phase);
10588 ecore_init_block(sc, BLOCK_CSDM, init_phase);
10589 ecore_init_block(sc, BLOCK_USDM, init_phase);
10590 ecore_init_block(sc, BLOCK_XSDM, init_phase);
10592 ecore_init_block(sc, BLOCK_TSEM, init_phase);
10593 ecore_init_block(sc, BLOCK_USEM, init_phase);
10594 ecore_init_block(sc, BLOCK_CSEM, init_phase);
10595 ecore_init_block(sc, BLOCK_XSEM, init_phase);
10597 ecore_init_block(sc, BLOCK_UPB, init_phase);
10598 ecore_init_block(sc, BLOCK_XPB, init_phase);
10600 ecore_init_block(sc, BLOCK_PBF, init_phase);
10602 if (CHIP_IS_E1x(sc)) {
10603 /* configure PBF to work without PAUSE mtu 9000 */
10604 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 0);
10606 /* update threshold */
10607 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, (9040 / 16));
10608 /* update init credit */
10609 REG_WR(sc, PBF_REG_P0_INIT_CRD + port * 4,
10610 (9040 / 16) + 553 - 22);
10612 /* probe changes */
10613 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 1);
10615 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0);
10618 if (CNIC_SUPPORT(sc)) {
10619 ecore_init_block(sc, BLOCK_SRC, init_phase);
10622 ecore_init_block(sc, BLOCK_CDU, init_phase);
10623 ecore_init_block(sc, BLOCK_CFC, init_phase);
10624 ecore_init_block(sc, BLOCK_HC, init_phase);
10625 ecore_init_block(sc, BLOCK_IGU, init_phase);
10626 ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
10627 /* init aeu_mask_attn_func_0/1:
10628 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
10629 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
10630 * bits 4-7 are used for "per vn group attention" */
10631 val = IS_MF(sc) ? 0xF7 : 0x7;
10633 REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, val);
10635 ecore_init_block(sc, BLOCK_NIG, init_phase);
10637 if (!CHIP_IS_E1x(sc)) {
10638 /* Bit-map indicating which L2 hdrs may appear after the
10639 * basic Ethernet header
10641 if (IS_MF_AFEX(sc)) {
10642 REG_WR(sc, SC_PORT(sc) ?
10643 NIG_REG_P1_HDRS_AFTER_BASIC :
10644 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
10646 REG_WR(sc, SC_PORT(sc) ?
10647 NIG_REG_P1_HDRS_AFTER_BASIC :
10648 NIG_REG_P0_HDRS_AFTER_BASIC,
10649 IS_MF_SD(sc) ? 7 : 6);
10652 if (CHIP_IS_E3(sc)) {
10653 REG_WR(sc, SC_PORT(sc) ?
10654 NIG_REG_LLH1_MF_MODE :
10655 NIG_REG_LLH_MF_MODE, IS_MF(sc));
10658 if (!CHIP_IS_E3(sc)) {
10659 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1);
10662 /* 0x2 disable mf_ov, 0x1 enable */
10663 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port * 4,
10664 (IS_MF_SD(sc) ? 0x1 : 0x2));
10666 if (!CHIP_IS_E1x(sc)) {
10668 switch (sc->devinfo.mf_info.mf_mode) {
10669 case MULTI_FUNCTION_SD:
10672 case MULTI_FUNCTION_SI:
10673 case MULTI_FUNCTION_AFEX:
10678 REG_WR(sc, (SC_PORT(sc) ? NIG_REG_LLH1_CLS_TYPE :
10679 NIG_REG_LLH0_CLS_TYPE), val);
10681 REG_WR(sc, NIG_REG_LLFC_ENABLE_0 + port * 4, 0);
10682 REG_WR(sc, NIG_REG_LLFC_OUT_EN_0 + port * 4, 0);
10683 REG_WR(sc, NIG_REG_PAUSE_ENABLE_0 + port * 4, 1);
10685 /* If SPIO5 is set to generate interrupts, enable it for this port */
10686 val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
10687 if (val & MISC_SPIO_SPIO5) {
10688 uint32_t reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
10689 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
10690 val = REG_RD(sc, reg_addr);
10691 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
10692 REG_WR(sc, reg_addr, val);
10699 bnx2x_flr_clnup_reg_poll(struct bnx2x_softc *sc, uint32_t reg,
10700 uint32_t expected, uint32_t poll_count)
10702 uint32_t cur_cnt = poll_count;
10705 while ((val = REG_RD(sc, reg)) != expected && cur_cnt--) {
10706 DELAY(FLR_WAIT_INTERVAL);
10713 bnx2x_flr_clnup_poll_hw_counter(struct bnx2x_softc *sc, uint32_t reg,
10714 __rte_unused const char *msg, uint32_t poll_cnt)
10716 uint32_t val = bnx2x_flr_clnup_reg_poll(sc, reg, 0, poll_cnt);
10719 PMD_DRV_LOG(NOTICE, sc, "%s usage count=%d", msg, val);
10726 /* Common routines with VF FLR cleanup */
10727 static uint32_t bnx2x_flr_clnup_poll_count(struct bnx2x_softc *sc)
10729 /* adjust polling timeout */
10730 if (CHIP_REV_IS_EMUL(sc)) {
10731 return FLR_POLL_CNT * 2000;
10734 if (CHIP_REV_IS_FPGA(sc)) {
10735 return FLR_POLL_CNT * 120;
10738 return FLR_POLL_CNT;
10741 static int bnx2x_poll_hw_usage_counters(struct bnx2x_softc *sc, uint32_t poll_cnt)
10743 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
10744 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10745 CFC_REG_NUM_LCIDS_INSIDE_PF,
10746 "CFC PF usage counter timed out",
10751 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
10752 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10753 DORQ_REG_PF_USAGE_CNT,
10754 "DQ PF usage counter timed out",
10759 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
10760 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10761 QM_REG_PF_USG_CNT_0 + 4 * SC_FUNC(sc),
10762 "QM PF usage counter timed out",
10767 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
10768 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10769 TM_REG_LIN0_VNIC_UC + 4 * SC_PORT(sc),
10770 "Timers VNIC usage counter timed out",
10775 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10776 TM_REG_LIN0_NUM_SCANS +
10778 "Timers NUM_SCANS usage counter timed out",
10783 /* Wait DMAE PF usage counter to zero */
10784 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10785 dmae_reg_go_c[INIT_DMAE_C(sc)],
10786 "DMAE dommand register timed out",
10794 #define OP_GEN_PARAM(param) \
10795 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
10796 #define OP_GEN_TYPE(type) \
10797 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
10798 #define OP_GEN_AGG_VECT(index) \
10799 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
10802 bnx2x_send_final_clnup(struct bnx2x_softc *sc, uint8_t clnup_func,
10805 uint32_t op_gen_command = 0;
10806 uint32_t comp_addr = (BAR_CSTRORM_INTMEM +
10807 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func));
10810 if (REG_RD(sc, comp_addr)) {
10811 PMD_DRV_LOG(NOTICE, sc,
10812 "Cleanup complete was not 0 before sending");
10816 op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
10817 op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
10818 op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
10819 op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
10821 REG_WR(sc, XSDM_REG_OPERATION_GEN, op_gen_command);
10823 if (bnx2x_flr_clnup_reg_poll(sc, comp_addr, 1, poll_cnt) != 1) {
10824 PMD_DRV_LOG(NOTICE, sc, "FW final cleanup did not succeed");
10825 PMD_DRV_LOG(DEBUG, sc, "At timeout completion address contained %x",
10826 (REG_RD(sc, comp_addr)));
10827 rte_panic("FLR cleanup failed");
10831 /* Zero completion for nxt FLR */
10832 REG_WR(sc, comp_addr, 0);
10838 bnx2x_pbf_pN_buf_flushed(struct bnx2x_softc *sc, struct pbf_pN_buf_regs *regs,
10839 uint32_t poll_count)
10841 uint32_t init_crd, crd, crd_start, crd_freed, crd_freed_start;
10842 uint32_t cur_cnt = poll_count;
10844 crd_freed = crd_freed_start = REG_RD(sc, regs->crd_freed);
10845 crd = crd_start = REG_RD(sc, regs->crd);
10846 init_crd = REG_RD(sc, regs->init_crd);
10848 while ((crd != init_crd) &&
10849 ((uint32_t) ((int32_t) crd_freed - (int32_t) crd_freed_start) <
10850 (init_crd - crd_start))) {
10852 DELAY(FLR_WAIT_INTERVAL);
10853 crd = REG_RD(sc, regs->crd);
10854 crd_freed = REG_RD(sc, regs->crd_freed);
10862 bnx2x_pbf_pN_cmd_flushed(struct bnx2x_softc *sc, struct pbf_pN_cmd_regs *regs,
10863 uint32_t poll_count)
10865 uint32_t occup, to_free, freed, freed_start;
10866 uint32_t cur_cnt = poll_count;
10868 occup = to_free = REG_RD(sc, regs->lines_occup);
10869 freed = freed_start = REG_RD(sc, regs->lines_freed);
10872 ((uint32_t) ((int32_t) freed - (int32_t) freed_start) <
10875 DELAY(FLR_WAIT_INTERVAL);
10876 occup = REG_RD(sc, regs->lines_occup);
10877 freed = REG_RD(sc, regs->lines_freed);
10884 static void bnx2x_tx_hw_flushed(struct bnx2x_softc *sc, uint32_t poll_count)
10886 struct pbf_pN_cmd_regs cmd_regs[] = {
10887 {0, (CHIP_IS_E3B0(sc)) ?
10888 PBF_REG_TQ_OCCUPANCY_Q0 : PBF_REG_P0_TQ_OCCUPANCY,
10889 (CHIP_IS_E3B0(sc)) ?
10890 PBF_REG_TQ_LINES_FREED_CNT_Q0 : PBF_REG_P0_TQ_LINES_FREED_CNT},
10891 {1, (CHIP_IS_E3B0(sc)) ?
10892 PBF_REG_TQ_OCCUPANCY_Q1 : PBF_REG_P1_TQ_OCCUPANCY,
10893 (CHIP_IS_E3B0(sc)) ?
10894 PBF_REG_TQ_LINES_FREED_CNT_Q1 : PBF_REG_P1_TQ_LINES_FREED_CNT},
10895 {4, (CHIP_IS_E3B0(sc)) ?
10896 PBF_REG_TQ_OCCUPANCY_LB_Q : PBF_REG_P4_TQ_OCCUPANCY,
10897 (CHIP_IS_E3B0(sc)) ?
10898 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
10899 PBF_REG_P4_TQ_LINES_FREED_CNT}
10902 struct pbf_pN_buf_regs buf_regs[] = {
10903 {0, (CHIP_IS_E3B0(sc)) ?
10904 PBF_REG_INIT_CRD_Q0 : PBF_REG_P0_INIT_CRD,
10905 (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q0 : PBF_REG_P0_CREDIT,
10906 (CHIP_IS_E3B0(sc)) ?
10907 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
10908 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
10909 {1, (CHIP_IS_E3B0(sc)) ?
10910 PBF_REG_INIT_CRD_Q1 : PBF_REG_P1_INIT_CRD,
10911 (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q1 : PBF_REG_P1_CREDIT,
10912 (CHIP_IS_E3B0(sc)) ?
10913 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
10914 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
10915 {4, (CHIP_IS_E3B0(sc)) ?
10916 PBF_REG_INIT_CRD_LB_Q : PBF_REG_P4_INIT_CRD,
10917 (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_LB_Q : PBF_REG_P4_CREDIT,
10918 (CHIP_IS_E3B0(sc)) ?
10919 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
10920 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
10925 /* Verify the command queues are flushed P0, P1, P4 */
10926 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) {
10927 bnx2x_pbf_pN_cmd_flushed(sc, &cmd_regs[i], poll_count);
10930 /* Verify the transmission buffers are flushed P0, P1, P4 */
10931 for (i = 0; i < ARRAY_SIZE(buf_regs); i++) {
10932 bnx2x_pbf_pN_buf_flushed(sc, &buf_regs[i], poll_count);
10936 static void bnx2x_hw_enable_status(struct bnx2x_softc *sc)
10938 __rte_unused uint32_t val;
10940 val = REG_RD(sc, CFC_REG_WEAK_ENABLE_PF);
10941 PMD_DRV_LOG(DEBUG, sc, "CFC_REG_WEAK_ENABLE_PF is 0x%x", val);
10943 val = REG_RD(sc, PBF_REG_DISABLE_PF);
10944 PMD_DRV_LOG(DEBUG, sc, "PBF_REG_DISABLE_PF is 0x%x", val);
10946 val = REG_RD(sc, IGU_REG_PCI_PF_MSI_EN);
10947 PMD_DRV_LOG(DEBUG, sc, "IGU_REG_PCI_PF_MSI_EN is 0x%x", val);
10949 val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_EN);
10950 PMD_DRV_LOG(DEBUG, sc, "IGU_REG_PCI_PF_MSIX_EN is 0x%x", val);
10952 val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
10953 PMD_DRV_LOG(DEBUG, sc, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x", val);
10955 val = REG_RD(sc, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
10956 PMD_DRV_LOG(DEBUG, sc,
10957 "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x", val);
10959 val = REG_RD(sc, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
10960 PMD_DRV_LOG(DEBUG, sc,
10961 "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x", val);
10963 val = REG_RD(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
10964 PMD_DRV_LOG(DEBUG, sc, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x",
10969 * bnx2x_pf_flr_clnup
10970 * a. re-enable target read on the PF
10971 * b. poll cfc per function usgae counter
10972 * c. poll the qm perfunction usage counter
10973 * d. poll the tm per function usage counter
10974 * e. poll the tm per function scan-done indication
10975 * f. clear the dmae channel associated wit hthe PF
10976 * g. zero the igu 'trailing edge' and 'leading edge' regs (attentions)
10977 * h. call the common flr cleanup code with -1 (pf indication)
10979 static int bnx2x_pf_flr_clnup(struct bnx2x_softc *sc)
10981 uint32_t poll_cnt = bnx2x_flr_clnup_poll_count(sc);
10983 /* Re-enable PF target read access */
10984 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
10986 /* Poll HW usage counters */
10987 if (bnx2x_poll_hw_usage_counters(sc, poll_cnt)) {
10991 /* Zero the igu 'trailing edge' and 'leading edge' */
10993 /* Send the FW cleanup command */
10994 if (bnx2x_send_final_clnup(sc, (uint8_t) SC_FUNC(sc), poll_cnt)) {
11000 /* Verify TX hw is flushed */
11001 bnx2x_tx_hw_flushed(sc, poll_cnt);
11003 /* Wait 100ms (not adjusted according to platform) */
11006 /* Verify no pending pci transactions */
11007 if (bnx2x_is_pcie_pending(sc)) {
11008 PMD_DRV_LOG(NOTICE, sc, "PCIE Transactions still pending");
11012 bnx2x_hw_enable_status(sc);
11015 * Master enable - Due to WB DMAE writes performed before this
11016 * register is re-initialized as part of the regular function init
11018 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11023 static int bnx2x_init_hw_func(struct bnx2x_softc *sc)
11025 int port = SC_PORT(sc);
11026 int func = SC_FUNC(sc);
11027 int init_phase = PHASE_PF0 + func;
11028 struct ecore_ilt *ilt = sc->ilt;
11029 uint16_t cdu_ilt_start;
11030 uint32_t addr, val;
11031 uint32_t main_mem_base, main_mem_size, main_mem_prty_clr;
11032 int main_mem_width, rc;
11035 PMD_DRV_LOG(DEBUG, sc, "starting func init for func %d", func);
11038 if (!CHIP_IS_E1x(sc)) {
11039 rc = bnx2x_pf_flr_clnup(sc);
11041 PMD_DRV_LOG(NOTICE, sc, "FLR cleanup failed!");
11046 /* set MSI reconfigure capability */
11047 if (sc->devinfo.int_block == INT_BLOCK_HC) {
11048 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
11049 val = REG_RD(sc, addr);
11050 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
11051 REG_WR(sc, addr, val);
11054 ecore_init_block(sc, BLOCK_PXP, init_phase);
11055 ecore_init_block(sc, BLOCK_PXP2, init_phase);
11058 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
11060 for (i = 0; i < L2_ILT_LINES(sc); i++) {
11061 ilt->lines[cdu_ilt_start + i].page = sc->context[i].vcxt;
11062 ilt->lines[cdu_ilt_start + i].page_mapping =
11063 (rte_iova_t)sc->context[i].vcxt_dma.paddr;
11064 ilt->lines[cdu_ilt_start + i].size = sc->context[i].size;
11066 ecore_ilt_init_op(sc, INITOP_SET);
11068 REG_WR(sc, PRS_REG_NIC_MODE, 1);
11070 if (!CHIP_IS_E1x(sc)) {
11071 uint32_t pf_conf = IGU_PF_CONF_FUNC_EN;
11073 /* Turn on a single ISR mode in IGU if driver is going to use
11076 if ((sc->interrupt_mode != INTR_MODE_MSIX)
11077 || (sc->interrupt_mode != INTR_MODE_SINGLE_MSIX)) {
11078 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
11082 * Timers workaround bug: function init part.
11083 * Need to wait 20msec after initializing ILT,
11084 * needed to make sure there are no requests in
11085 * one of the PXP internal queues with "old" ILT addresses
11090 * Master enable - Due to WB DMAE writes performed before this
11091 * register is re-initialized as part of the regular function
11094 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11095 /* Enable the function in IGU */
11096 REG_WR(sc, IGU_REG_PF_CONFIGURATION, pf_conf);
11099 sc->dmae_ready = 1;
11101 ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
11103 if (!CHIP_IS_E1x(sc))
11104 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
11106 ecore_init_block(sc, BLOCK_ATC, init_phase);
11107 ecore_init_block(sc, BLOCK_DMAE, init_phase);
11108 ecore_init_block(sc, BLOCK_NIG, init_phase);
11109 ecore_init_block(sc, BLOCK_SRC, init_phase);
11110 ecore_init_block(sc, BLOCK_MISC, init_phase);
11111 ecore_init_block(sc, BLOCK_TCM, init_phase);
11112 ecore_init_block(sc, BLOCK_UCM, init_phase);
11113 ecore_init_block(sc, BLOCK_CCM, init_phase);
11114 ecore_init_block(sc, BLOCK_XCM, init_phase);
11115 ecore_init_block(sc, BLOCK_TSEM, init_phase);
11116 ecore_init_block(sc, BLOCK_USEM, init_phase);
11117 ecore_init_block(sc, BLOCK_CSEM, init_phase);
11118 ecore_init_block(sc, BLOCK_XSEM, init_phase);
11120 if (!CHIP_IS_E1x(sc))
11121 REG_WR(sc, QM_REG_PF_EN, 1);
11123 if (!CHIP_IS_E1x(sc)) {
11124 REG_WR(sc, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11125 REG_WR(sc, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11126 REG_WR(sc, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11127 REG_WR(sc, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11129 ecore_init_block(sc, BLOCK_QM, init_phase);
11131 ecore_init_block(sc, BLOCK_TM, init_phase);
11132 ecore_init_block(sc, BLOCK_DORQ, init_phase);
11134 ecore_init_block(sc, BLOCK_BRB1, init_phase);
11135 ecore_init_block(sc, BLOCK_PRS, init_phase);
11136 ecore_init_block(sc, BLOCK_TSDM, init_phase);
11137 ecore_init_block(sc, BLOCK_CSDM, init_phase);
11138 ecore_init_block(sc, BLOCK_USDM, init_phase);
11139 ecore_init_block(sc, BLOCK_XSDM, init_phase);
11140 ecore_init_block(sc, BLOCK_UPB, init_phase);
11141 ecore_init_block(sc, BLOCK_XPB, init_phase);
11142 ecore_init_block(sc, BLOCK_PBF, init_phase);
11143 if (!CHIP_IS_E1x(sc))
11144 REG_WR(sc, PBF_REG_DISABLE_PF, 0);
11146 ecore_init_block(sc, BLOCK_CDU, init_phase);
11148 ecore_init_block(sc, BLOCK_CFC, init_phase);
11150 if (!CHIP_IS_E1x(sc))
11151 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 1);
11154 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
11155 REG_WR(sc, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8, OVLAN(sc));
11158 ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
11160 /* HC init per function */
11161 if (sc->devinfo.int_block == INT_BLOCK_HC) {
11162 if (CHIP_IS_E1H(sc)) {
11163 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11165 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11166 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11168 ecore_init_block(sc, BLOCK_HC, init_phase);
11171 uint32_t num_segs, sb_idx, prod_offset;
11173 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11175 if (!CHIP_IS_E1x(sc)) {
11176 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11177 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11180 ecore_init_block(sc, BLOCK_IGU, init_phase);
11182 if (!CHIP_IS_E1x(sc)) {
11186 * E2 mode: address 0-135 match to the mapping memory;
11187 * 136 - PF0 default prod; 137 - PF1 default prod;
11188 * 138 - PF2 default prod; 139 - PF3 default prod;
11189 * 140 - PF0 attn prod; 141 - PF1 attn prod;
11190 * 142 - PF2 attn prod; 143 - PF3 attn prod;
11191 * 144-147 reserved.
11193 * E1.5 mode - In backward compatible mode;
11194 * for non default SB; each even line in the memory
11195 * holds the U producer and each odd line hold
11196 * the C producer. The first 128 producers are for
11197 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
11198 * producers are for the DSB for each PF.
11199 * Each PF has five segments: (the order inside each
11200 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
11201 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
11202 * 144-147 attn prods;
11204 /* non-default-status-blocks */
11205 num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11206 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
11207 for (sb_idx = 0; sb_idx < sc->igu_sb_cnt; sb_idx++) {
11208 prod_offset = (sc->igu_base_sb + sb_idx) *
11211 for (i = 0; i < num_segs; i++) {
11212 addr = IGU_REG_PROD_CONS_MEMORY +
11213 (prod_offset + i) * 4;
11214 REG_WR(sc, addr, 0);
11216 /* send consumer update with value 0 */
11217 bnx2x_ack_sb(sc, sc->igu_base_sb + sb_idx,
11218 USTORM_ID, 0, IGU_INT_NOP, 1);
11219 bnx2x_igu_clear_sb(sc, sc->igu_base_sb + sb_idx);
11222 /* default-status-blocks */
11223 num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11224 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
11226 if (CHIP_IS_MODE_4_PORT(sc))
11227 dsb_idx = SC_FUNC(sc);
11229 dsb_idx = SC_VN(sc);
11231 prod_offset = (CHIP_INT_MODE_IS_BC(sc) ?
11232 IGU_BC_BASE_DSB_PROD + dsb_idx :
11233 IGU_NORM_BASE_DSB_PROD + dsb_idx);
11236 * igu prods come in chunks of E1HVN_MAX (4) -
11237 * does not matters what is the current chip mode
11239 for (i = 0; i < (num_segs * E1HVN_MAX); i += E1HVN_MAX) {
11240 addr = IGU_REG_PROD_CONS_MEMORY +
11241 (prod_offset + i) * 4;
11242 REG_WR(sc, addr, 0);
11244 /* send consumer update with 0 */
11245 if (CHIP_INT_MODE_IS_BC(sc)) {
11246 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11247 USTORM_ID, 0, IGU_INT_NOP, 1);
11248 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11249 CSTORM_ID, 0, IGU_INT_NOP, 1);
11250 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11251 XSTORM_ID, 0, IGU_INT_NOP, 1);
11252 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11253 TSTORM_ID, 0, IGU_INT_NOP, 1);
11254 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11255 ATTENTION_ID, 0, IGU_INT_NOP, 1);
11257 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11258 USTORM_ID, 0, IGU_INT_NOP, 1);
11259 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11260 ATTENTION_ID, 0, IGU_INT_NOP, 1);
11262 bnx2x_igu_clear_sb(sc, sc->igu_dsb_id);
11264 /* !!! these should become driver const once
11265 rf-tool supports split-68 const */
11266 REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
11267 REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
11268 REG_WR(sc, IGU_REG_SB_MASK_LSB, 0);
11269 REG_WR(sc, IGU_REG_SB_MASK_MSB, 0);
11270 REG_WR(sc, IGU_REG_PBA_STATUS_LSB, 0);
11271 REG_WR(sc, IGU_REG_PBA_STATUS_MSB, 0);
11275 /* Reset PCIE errors for debug */
11276 REG_WR(sc, 0x2114, 0xffffffff);
11277 REG_WR(sc, 0x2120, 0xffffffff);
11279 if (CHIP_IS_E1x(sc)) {
11280 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords */
11281 main_mem_base = HC_REG_MAIN_MEMORY +
11282 SC_PORT(sc) * (main_mem_size * 4);
11283 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
11284 main_mem_width = 8;
11286 val = REG_RD(sc, main_mem_prty_clr);
11288 PMD_DRV_LOG(DEBUG, sc,
11289 "Parity errors in HC block during function init (0x%x)!",
11293 /* Clear "false" parity errors in MSI-X table */
11294 for (i = main_mem_base;
11295 i < main_mem_base + main_mem_size * 4;
11296 i += main_mem_width) {
11297 bnx2x_read_dmae(sc, i, main_mem_width / 4);
11298 bnx2x_write_dmae(sc, BNX2X_SP_MAPPING(sc, wb_data),
11299 i, main_mem_width / 4);
11301 /* Clear HC parity attention */
11302 REG_RD(sc, main_mem_prty_clr);
11305 /* Enable STORMs SP logging */
11306 REG_WR8(sc, BAR_USTRORM_INTMEM +
11307 USTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11308 REG_WR8(sc, BAR_TSTRORM_INTMEM +
11309 TSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11310 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11311 CSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11312 REG_WR8(sc, BAR_XSTRORM_INTMEM +
11313 XSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11315 elink_phy_probe(&sc->link_params);
11320 static void bnx2x_link_reset(struct bnx2x_softc *sc)
11322 if (!BNX2X_NOMCP(sc)) {
11323 elink_lfa_reset(&sc->link_params, &sc->link_vars);
11325 if (!CHIP_REV_IS_SLOW(sc)) {
11326 PMD_DRV_LOG(WARNING, sc,
11327 "Bootcode is missing - cannot reset link");
11332 static void bnx2x_reset_port(struct bnx2x_softc *sc)
11334 int port = SC_PORT(sc);
11337 /* reset physical Link */
11338 bnx2x_link_reset(sc);
11340 REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
11342 /* Do not rcv packets to BRB */
11343 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + port * 4, 0x0);
11344 /* Do not direct rcv packets that are not for MCP to the BRB */
11345 REG_WR(sc, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
11346 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
11348 /* Configure AEU */
11349 REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, 0);
11353 /* Check for BRB port occupancy */
11354 val = REG_RD(sc, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port * 4);
11356 PMD_DRV_LOG(DEBUG, sc,
11357 "BRB1 is not empty, %d blocks are occupied", val);
11361 static void bnx2x_ilt_wr(struct bnx2x_softc *sc, uint32_t index, rte_iova_t addr)
11364 uint32_t wb_write[2];
11366 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index * 8;
11368 wb_write[0] = ONCHIP_ADDR1(addr);
11369 wb_write[1] = ONCHIP_ADDR2(addr);
11370 REG_WR_DMAE(sc, reg, wb_write, 2);
11373 static void bnx2x_clear_func_ilt(struct bnx2x_softc *sc, uint32_t func)
11375 uint32_t i, base = FUNC_ILT_BASE(func);
11376 for (i = base; i < base + ILT_PER_FUNC; i++) {
11377 bnx2x_ilt_wr(sc, i, 0);
11381 static void bnx2x_reset_func(struct bnx2x_softc *sc)
11383 struct bnx2x_fastpath *fp;
11384 int port = SC_PORT(sc);
11385 int func = SC_FUNC(sc);
11388 /* Disable the function in the FW */
11389 REG_WR8(sc, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
11390 REG_WR8(sc, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
11391 REG_WR8(sc, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
11392 REG_WR8(sc, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
11395 FOR_EACH_ETH_QUEUE(sc, i) {
11397 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11398 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
11403 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11404 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), SB_DISABLED);
11406 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) {
11407 REG_WR(sc, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
11411 /* Configure IGU */
11412 if (sc->devinfo.int_block == INT_BLOCK_HC) {
11413 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11414 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11416 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11417 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11420 if (CNIC_LOADED(sc)) {
11421 /* Disable Timer scan */
11422 REG_WR(sc, TM_REG_EN_LINEAR0_TIMER + port * 4, 0);
11424 * Wait for at least 10ms and up to 2 second for the timers
11427 for (i = 0; i < 200; i++) {
11429 if (!REG_RD(sc, TM_REG_LIN0_SCAN_ON + port * 4))
11435 bnx2x_clear_func_ilt(sc, func);
11438 * Timers workaround bug for E2: if this is vnic-3,
11439 * we need to set the entire ilt range for this timers.
11441 if (!CHIP_IS_E1x(sc) && SC_VN(sc) == 3) {
11442 struct ilt_client_info ilt_cli;
11443 /* use dummy TM client */
11444 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
11446 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
11447 ilt_cli.client_num = ILT_CLIENT_TM;
11449 ecore_ilt_boundry_init_op(sc, &ilt_cli, 0);
11452 /* this assumes that reset_port() called before reset_func() */
11453 if (!CHIP_IS_E1x(sc)) {
11454 bnx2x_pf_disable(sc);
11457 sc->dmae_ready = 0;
11460 static void bnx2x_release_firmware(struct bnx2x_softc *sc)
11462 rte_free(sc->init_ops);
11463 rte_free(sc->init_ops_offsets);
11464 rte_free(sc->init_data);
11465 rte_free(sc->iro_array);
11468 static int bnx2x_init_firmware(struct bnx2x_softc *sc)
11471 uint8_t *p = sc->firmware;
11474 for (i = 0; i < 24; ++i)
11475 off[i] = rte_be_to_cpu_32(*((uint32_t *) sc->firmware + i));
11478 sc->init_ops = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11481 bnx2x_data_to_init_ops(p + off[1], sc->init_ops, len);
11484 sc->init_ops_offsets = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11485 if (!sc->init_ops_offsets)
11487 bnx2x_data_to_init_offsets(p + off[3], sc->init_ops_offsets, len);
11490 sc->init_data = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11491 if (!sc->init_data)
11493 bnx2x_data_to_init_data(p + off[5], sc->init_data, len);
11495 sc->tsem_int_table_data = p + off[7];
11496 sc->tsem_pram_data = p + off[9];
11497 sc->usem_int_table_data = p + off[11];
11498 sc->usem_pram_data = p + off[13];
11499 sc->csem_int_table_data = p + off[15];
11500 sc->csem_pram_data = p + off[17];
11501 sc->xsem_int_table_data = p + off[19];
11502 sc->xsem_pram_data = p + off[21];
11505 sc->iro_array = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11506 if (!sc->iro_array)
11508 bnx2x_data_to_iro_array(p + off[23], sc->iro_array, len);
11513 bnx2x_release_firmware(sc);
11517 static int cut_gzip_prefix(const uint8_t * zbuf, int len)
11519 #define MIN_PREFIX_SIZE (10)
11521 int n = MIN_PREFIX_SIZE;
11524 if (!(zbuf[0] == 0x1f && zbuf[1] == 0x8b && zbuf[2] == Z_DEFLATED) ||
11525 len <= MIN_PREFIX_SIZE) {
11529 /* optional extra fields are present */
11530 if (zbuf[3] & 0x4) {
11537 /* file name is present */
11538 if (zbuf[3] & 0x8) {
11539 while ((zbuf[n++] != 0) && (n < len)) ;
11545 static int ecore_gunzip(struct bnx2x_softc *sc, const uint8_t * zbuf, int len)
11548 int data_begin = cut_gzip_prefix(zbuf, len);
11550 PMD_DRV_LOG(DEBUG, sc, "ecore_gunzip %d", len);
11552 if (data_begin <= 0) {
11553 PMD_DRV_LOG(NOTICE, sc, "bad gzip prefix");
11557 memset(&zlib_stream, 0, sizeof(zlib_stream));
11558 zlib_stream.next_in = zbuf + data_begin;
11559 zlib_stream.avail_in = len - data_begin;
11560 zlib_stream.next_out = sc->gz_buf;
11561 zlib_stream.avail_out = FW_BUF_SIZE;
11563 ret = inflateInit2(&zlib_stream, -MAX_WBITS);
11565 PMD_DRV_LOG(NOTICE, sc, "zlib inflateInit2 error");
11569 ret = inflate(&zlib_stream, Z_FINISH);
11570 if ((ret != Z_STREAM_END) && (ret != Z_OK)) {
11571 PMD_DRV_LOG(NOTICE, sc, "zlib inflate error: %d %s", ret,
11575 sc->gz_outlen = zlib_stream.total_out;
11576 if (sc->gz_outlen & 0x3) {
11577 PMD_DRV_LOG(NOTICE, sc, "firmware is not aligned. gz_outlen == %d",
11580 sc->gz_outlen >>= 2;
11582 inflateEnd(&zlib_stream);
11584 if (ret == Z_STREAM_END)
11591 ecore_write_dmae_phys_len(struct bnx2x_softc *sc, rte_iova_t phys_addr,
11592 uint32_t addr, uint32_t len)
11594 bnx2x_write_dmae_phys_len(sc, phys_addr, addr, len);
11598 ecore_storm_memset_struct(struct bnx2x_softc *sc, uint32_t addr, size_t size,
11602 for (i = 0; i < size / 4; i++) {
11603 REG_WR(sc, addr + (i * 4), data[i]);
11607 static const char *get_ext_phy_type(uint32_t ext_phy_type)
11609 uint32_t phy_type_idx = ext_phy_type >> 8;
11610 static const char *types[] =
11611 { "DIRECT", "BNX2X-8071", "BNX2X-8072", "BNX2X-8073",
11612 "BNX2X-8705", "BNX2X-8706", "BNX2X-8726", "BNX2X-8481", "SFX-7101",
11614 "BNX2X-8727-NOC", "BNX2X-84823", "NOT_CONN", "FAILURE"
11617 if (phy_type_idx < 12)
11618 return types[phy_type_idx];
11619 else if (PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN == ext_phy_type)
11625 static const char *get_state(uint32_t state)
11627 uint32_t state_idx = state >> 12;
11628 static const char *states[] = { "CLOSED", "OPENING_WAIT4_LOAD",
11629 "OPENING_WAIT4_PORT", "OPEN", "CLOSING_WAIT4_HALT",
11630 "CLOSING_WAIT4_DELETE", "CLOSING_WAIT4_UNLOAD",
11631 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
11632 "UNKNOWN", "DISABLED", "DIAG", "ERROR", "UNDEFINED"
11635 if (state_idx <= 0xF)
11636 return states[state_idx];
11638 return states[0x10];
11641 static const char *get_recovery_state(uint32_t state)
11643 static const char *states[] = { "NONE", "DONE", "INIT",
11644 "WAIT", "FAILED", "NIC_LOADING"
11646 return states[state];
11649 static const char *get_rx_mode(uint32_t mode)
11651 static const char *modes[] = { "NONE", "NORMAL", "ALLMULTI",
11652 "PROMISC", "MAX_MULTICAST", "ERROR"
11656 return modes[mode];
11657 else if (BNX2X_MAX_MULTICAST == mode)
11663 #define BNX2X_INFO_STR_MAX 256
11664 static const char *get_bnx2x_flags(uint32_t flags)
11667 static const char *flag[] = { "ONE_PORT ", "NO_ISCSI ",
11668 "NO_FCOE ", "NO_WOL ", "USING_DAC ", "USING_MSIX ",
11669 "USING_MSI ", "DISABLE_MSI ", "UNKNOWN ", "NO_MCP ",
11670 "SAFC_TX_FLAG ", "MF_FUNC_DIS ", "TX_SWITCHING "
11672 static char flag_str[BNX2X_INFO_STR_MAX];
11673 memset(flag_str, 0, BNX2X_INFO_STR_MAX);
11675 for (i = 0; i < 5; i++)
11676 if (flags & (1 << i)) {
11677 strcat(flag_str, flag[i]);
11681 static char unknown[BNX2X_INFO_STR_MAX];
11682 snprintf(unknown, 32, "Unknown flag mask %x", flags);
11683 strcat(flag_str, unknown);
11689 * Prints useful adapter info.
11691 void bnx2x_print_adapter_info(struct bnx2x_softc *sc)
11694 __rte_unused uint32_t ext_phy_type;
11696 PMD_INIT_FUNC_TRACE(sc);
11697 if (sc->link_vars.phy_flags & PHY_XGXS_FLAG)
11698 ext_phy_type = ELINK_XGXS_EXT_PHY_TYPE(REG_RD(sc,
11703 dev_info.port_hw_config
11704 [0].external_phy_config)));
11706 ext_phy_type = ELINK_SERDES_EXT_PHY_TYPE(REG_RD(sc,
11712 dev_info.port_hw_config
11713 [0].external_phy_config)));
11715 PMD_DRV_LOG(INFO, sc, "\n\n===================================\n");
11716 /* Hardware chip info. */
11717 PMD_DRV_LOG(INFO, sc, "%12s : %#08x", "ASIC", sc->devinfo.chip_id);
11718 PMD_DRV_LOG(INFO, sc, "%12s : %c%d", "Rev", (CHIP_REV(sc) >> 12) + 'A',
11719 (CHIP_METAL(sc) >> 4));
11722 PMD_DRV_LOG(INFO, sc,
11723 "%12s : %d, ", "Bus PCIe", sc->devinfo.pcie_link_width);
11724 switch (sc->devinfo.pcie_link_speed) {
11726 PMD_DRV_LOG(INFO, sc, "%23s", "2.5 Gbps");
11729 PMD_DRV_LOG(INFO, sc, "%21s", "5 Gbps");
11732 PMD_DRV_LOG(INFO, sc, "%21s", "8 Gbps");
11735 PMD_DRV_LOG(INFO, sc, "%33s", "Unknown link speed");
11738 /* Device features. */
11739 PMD_DRV_LOG(INFO, sc, "%12s : ", "Flags");
11741 /* Miscellaneous flags. */
11742 if (sc->devinfo.pcie_cap_flags & BNX2X_MSI_CAPABLE_FLAG) {
11743 PMD_DRV_LOG(INFO, sc, "%18s", "MSI");
11747 if (sc->devinfo.pcie_cap_flags & BNX2X_MSIX_CAPABLE_FLAG) {
11749 PMD_DRV_LOG(INFO, sc, "|");
11750 PMD_DRV_LOG(INFO, sc, "%20s", "MSI-X");
11755 PMD_DRV_LOG(INFO, sc, "%12s : ", "Queues");
11756 switch (sc->sp->rss_rdata.rss_mode) {
11757 case ETH_RSS_MODE_DISABLED:
11758 PMD_DRV_LOG(INFO, sc, "%19s", "None");
11760 case ETH_RSS_MODE_REGULAR:
11761 PMD_DRV_LOG(INFO, sc,
11762 "%18s : %d", "RSS", sc->num_queues);
11765 PMD_DRV_LOG(INFO, sc, "%22s", "Unknown");
11770 /* RTE and Driver versions */
11771 PMD_DRV_LOG(INFO, sc, "%12s : %s", "DPDK",
11773 PMD_DRV_LOG(INFO, sc, "%12s : %s", "Driver",
11774 bnx2x_pmd_version());
11776 /* Firmware versions and device features. */
11777 PMD_DRV_LOG(INFO, sc, "%12s : %d.%d.%d",
11779 BNX2X_5710_FW_MAJOR_VERSION,
11780 BNX2X_5710_FW_MINOR_VERSION,
11781 BNX2X_5710_FW_REVISION_VERSION);
11782 PMD_DRV_LOG(INFO, sc, "%12s : %s",
11783 "Bootcode", sc->devinfo.bc_ver_str);
11785 PMD_DRV_LOG(INFO, sc, "\n\n===================================\n");
11786 PMD_DRV_LOG(INFO, sc, "%12s : %u", "Bnx2x Func", sc->pcie_func);
11787 PMD_DRV_LOG(INFO, sc,
11788 "%12s : %s", "Bnx2x Flags", get_bnx2x_flags(sc->flags));
11789 PMD_DRV_LOG(INFO, sc, "%12s : %s", "DMAE Is",
11790 (sc->dmae_ready ? "Ready" : "Not Ready"));
11791 PMD_DRV_LOG(INFO, sc, "%12s : %s", "OVLAN", (OVLAN(sc) ? "YES" : "NO"));
11792 PMD_DRV_LOG(INFO, sc, "%12s : %s", "MF", (IS_MF(sc) ? "YES" : "NO"));
11793 PMD_DRV_LOG(INFO, sc, "%12s : %u", "MTU", sc->mtu);
11794 PMD_DRV_LOG(INFO, sc,
11795 "%12s : %s", "PHY Type", get_ext_phy_type(ext_phy_type));
11796 PMD_DRV_LOG(INFO, sc, "%12s : %x:%x:%x:%x:%x:%x", "MAC Addr",
11797 sc->link_params.mac_addr[0],
11798 sc->link_params.mac_addr[1],
11799 sc->link_params.mac_addr[2],
11800 sc->link_params.mac_addr[3],
11801 sc->link_params.mac_addr[4],
11802 sc->link_params.mac_addr[5]);
11803 PMD_DRV_LOG(INFO, sc, "%12s : %s", "RX Mode", get_rx_mode(sc->rx_mode));
11804 PMD_DRV_LOG(INFO, sc, "%12s : %s", "State", get_state(sc->state));
11805 if (sc->recovery_state)
11806 PMD_DRV_LOG(INFO, sc, "%12s : %s", "Recovery",
11807 get_recovery_state(sc->recovery_state));
11808 PMD_DRV_LOG(INFO, sc, "%12s : CQ = %lx, EQ = %lx", "SPQ Left",
11809 sc->cq_spq_left, sc->eq_spq_left);
11810 PMD_DRV_LOG(INFO, sc,
11811 "%12s : %x", "Switch", sc->link_params.switch_cfg);
11812 PMD_DRV_LOG(INFO, sc, "\n\n===================================\n");