1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2007-2013 Broadcom Corporation.
4 * Eric Davis <edavis@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
6 * Gary Zambrano <zambrano@broadcom.com>
8 * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
9 * Copyright (c) 2015-2018 Cavium Inc.
10 * All rights reserved.
14 #define BNX2X_DRIVER_VERSION "1.78.18"
17 #include "bnx2x_vfpf.h"
19 #include "ecore_init.h"
20 #include "ecore_init_ops.h"
22 #include "rte_version.h"
24 #include <sys/types.h>
29 #define BNX2X_PMD_VER_PREFIX "BNX2X PMD"
30 #define BNX2X_PMD_VERSION_MAJOR 1
31 #define BNX2X_PMD_VERSION_MINOR 0
32 #define BNX2X_PMD_VERSION_REVISION 7
33 #define BNX2X_PMD_VERSION_PATCH 1
35 static inline const char *
36 bnx2x_pmd_version(void)
38 static char version[32];
40 snprintf(version, sizeof(version), "%s %s_%d.%d.%d.%d",
43 BNX2X_PMD_VERSION_MAJOR,
44 BNX2X_PMD_VERSION_MINOR,
45 BNX2X_PMD_VERSION_REVISION,
46 BNX2X_PMD_VERSION_PATCH);
51 static z_stream zlib_stream;
53 #define EVL_VLID_MASK 0x0FFF
55 #define BNX2X_DEF_SB_ATT_IDX 0x0001
56 #define BNX2X_DEF_SB_IDX 0x0002
59 * FLR Support - bnx2x_pf_flr_clnup() is called during nic_load in the per
60 * function HW initialization.
62 #define FLR_WAIT_USEC 10000 /* 10 msecs */
63 #define FLR_WAIT_INTERVAL 50 /* usecs */
64 #define FLR_POLL_CNT (FLR_WAIT_USEC / FLR_WAIT_INTERVAL) /* 200 */
66 struct pbf_pN_buf_regs {
73 struct pbf_pN_cmd_regs {
79 /* resources needed for unloading a previously loaded device */
81 #define BNX2X_PREV_WAIT_NEEDED 1
82 rte_spinlock_t bnx2x_prev_mtx;
83 struct bnx2x_prev_list_node {
84 LIST_ENTRY(bnx2x_prev_list_node) node;
92 static LIST_HEAD(, bnx2x_prev_list_node) bnx2x_prev_list
93 = LIST_HEAD_INITIALIZER(bnx2x_prev_list);
95 static int load_count[2][3] = { { 0 } };
96 /* per-path: 0-common, 1-port0, 2-port1 */
98 static void bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg,
100 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc);
101 static void storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng,
103 static void bnx2x_set_reset_global(struct bnx2x_softc *sc);
104 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc);
105 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine);
106 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc);
107 static uint8_t bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global,
109 static void bnx2x_int_disable(struct bnx2x_softc *sc);
110 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc);
111 static void bnx2x_pf_disable(struct bnx2x_softc *sc);
112 static void bnx2x_update_rx_prod(struct bnx2x_softc *sc,
113 struct bnx2x_fastpath *fp,
114 uint16_t rx_bd_prod, uint16_t rx_cq_prod);
115 static void bnx2x_link_report_locked(struct bnx2x_softc *sc);
116 static void bnx2x_link_report(struct bnx2x_softc *sc);
117 void bnx2x_link_status_update(struct bnx2x_softc *sc);
118 static int bnx2x_alloc_mem(struct bnx2x_softc *sc);
119 static void bnx2x_free_mem(struct bnx2x_softc *sc);
120 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc);
121 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc);
122 static __rte_noinline
123 int bnx2x_nic_load(struct bnx2x_softc *sc);
125 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc);
126 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp, int scan_fp);
127 static void bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id,
128 uint8_t storm, uint16_t index, uint8_t op,
131 int bnx2x_test_bit(int nr, volatile unsigned long *addr)
136 res = ((*addr) & (1UL << nr)) != 0;
141 void bnx2x_set_bit(unsigned int nr, volatile unsigned long *addr)
143 __sync_fetch_and_or(addr, (1UL << nr));
146 void bnx2x_clear_bit(int nr, volatile unsigned long *addr)
148 __sync_fetch_and_and(addr, ~(1UL << nr));
151 int bnx2x_test_and_clear_bit(int nr, volatile unsigned long *addr)
153 unsigned long mask = (1UL << nr);
154 return __sync_fetch_and_and(addr, ~mask) & mask;
157 int bnx2x_cmpxchg(volatile int *addr, int old, int new)
159 return __sync_val_compare_and_swap(addr, old, new);
163 bnx2x_dma_alloc(struct bnx2x_softc *sc, size_t size, struct bnx2x_dma *dma,
164 const char *msg, uint32_t align)
166 char mz_name[RTE_MEMZONE_NAMESIZE];
167 const struct rte_memzone *z;
171 snprintf(mz_name, sizeof(mz_name), "bnx2x%d_%s_%" PRIx64, SC_ABS_FUNC(sc), msg,
172 rte_get_timer_cycles());
174 snprintf(mz_name, sizeof(mz_name), "bnx2x%d_%s_%" PRIx64, sc->pcie_device, msg,
175 rte_get_timer_cycles());
177 /* Caller must take care that strlen(mz_name) < RTE_MEMZONE_NAMESIZE */
178 z = rte_memzone_reserve_aligned(mz_name, (uint64_t)size,
180 RTE_MEMZONE_IOVA_CONTIG, align);
182 PMD_DRV_LOG(ERR, sc, "DMA alloc failed for %s", msg);
185 dma->paddr = (uint64_t) z->iova;
186 dma->vaddr = z->addr;
188 PMD_DRV_LOG(DEBUG, sc,
189 "%s: virt=%p phys=%" PRIx64, msg, dma->vaddr, dma->paddr);
194 static int bnx2x_acquire_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
196 uint32_t lock_status;
197 uint32_t resource_bit = (1 << resource);
198 int func = SC_FUNC(sc);
199 uint32_t hw_lock_control_reg;
202 #ifndef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
204 PMD_INIT_FUNC_TRACE(sc);
206 PMD_INIT_FUNC_TRACE(sc);
209 /* validate the resource is within range */
210 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
211 PMD_DRV_LOG(NOTICE, sc,
212 "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
218 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
220 hw_lock_control_reg =
221 (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
224 /* validate the resource is not already taken */
225 lock_status = REG_RD(sc, hw_lock_control_reg);
226 if (lock_status & resource_bit) {
227 PMD_DRV_LOG(NOTICE, sc,
228 "resource in use (status 0x%x bit 0x%x)",
229 lock_status, resource_bit);
233 /* try every 5ms for 5 seconds */
234 for (cnt = 0; cnt < 1000; cnt++) {
235 REG_WR(sc, (hw_lock_control_reg + 4), resource_bit);
236 lock_status = REG_RD(sc, hw_lock_control_reg);
237 if (lock_status & resource_bit) {
243 PMD_DRV_LOG(NOTICE, sc, "Resource 0x%x resource_bit 0x%x lock timeout!",
244 resource, resource_bit);
248 static int bnx2x_release_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
250 uint32_t lock_status;
251 uint32_t resource_bit = (1 << resource);
252 int func = SC_FUNC(sc);
253 uint32_t hw_lock_control_reg;
255 #ifndef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
257 PMD_INIT_FUNC_TRACE(sc);
259 PMD_INIT_FUNC_TRACE(sc);
262 /* validate the resource is within range */
263 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
264 PMD_DRV_LOG(NOTICE, sc,
265 "(resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE)"
266 " resource_bit 0x%x", resource, resource_bit);
271 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
273 hw_lock_control_reg =
274 (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
277 /* validate the resource is currently taken */
278 lock_status = REG_RD(sc, hw_lock_control_reg);
279 if (!(lock_status & resource_bit)) {
280 PMD_DRV_LOG(NOTICE, sc,
281 "resource not in use (status 0x%x bit 0x%x)",
282 lock_status, resource_bit);
286 REG_WR(sc, hw_lock_control_reg, resource_bit);
290 static void bnx2x_acquire_phy_lock(struct bnx2x_softc *sc)
293 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_MDIO);
296 static void bnx2x_release_phy_lock(struct bnx2x_softc *sc)
298 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_MDIO);
299 BNX2X_PHY_UNLOCK(sc);
302 /* copy command into DMAE command memory and set DMAE command Go */
303 void bnx2x_post_dmae(struct bnx2x_softc *sc, struct dmae_command *dmae, int idx)
308 cmd_offset = (DMAE_REG_CMD_MEM + (sizeof(struct dmae_command) * idx));
309 for (i = 0; i < ((sizeof(struct dmae_command) / 4)); i++) {
310 REG_WR(sc, (cmd_offset + (i * 4)), *(((uint32_t *) dmae) + i));
313 REG_WR(sc, dmae_reg_go_c[idx], 1);
316 uint32_t bnx2x_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type)
318 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
319 DMAE_COMMAND_C_TYPE_ENABLE);
322 uint32_t bnx2x_dmae_opcode_clr_src_reset(uint32_t opcode)
324 return opcode & ~DMAE_COMMAND_SRC_RESET;
328 bnx2x_dmae_opcode(struct bnx2x_softc * sc, uint8_t src_type, uint8_t dst_type,
329 uint8_t with_comp, uint8_t comp_type)
333 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
334 (dst_type << DMAE_COMMAND_DST_SHIFT));
336 opcode |= (DMAE_COMMAND_SRC_RESET | DMAE_COMMAND_DST_RESET);
338 opcode |= (SC_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
340 opcode |= ((SC_VN(sc) << DMAE_COMMAND_E1HVN_SHIFT) |
341 (SC_VN(sc) << DMAE_COMMAND_DST_VN_SHIFT));
343 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
346 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
348 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
352 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
359 bnx2x_prep_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae,
360 uint8_t src_type, uint8_t dst_type)
362 memset(dmae, 0, sizeof(struct dmae_command));
365 dmae->opcode = bnx2x_dmae_opcode(sc, src_type, dst_type,
366 TRUE, DMAE_COMP_PCI);
368 /* fill in the completion parameters */
369 dmae->comp_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_comp));
370 dmae->comp_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_comp));
371 dmae->comp_val = DMAE_COMP_VAL;
374 /* issue a DMAE command over the init channel and wait for completion */
376 bnx2x_issue_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae)
378 uint32_t *wb_comp = BNX2X_SP(sc, wb_comp);
379 int timeout = CHIP_REV_IS_SLOW(sc) ? 400000 : 4000;
381 /* reset completion */
384 /* post the command on the channel used for initializations */
385 bnx2x_post_dmae(sc, dmae, INIT_DMAE_C(sc));
387 /* wait for completion */
390 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
392 (sc->recovery_state != BNX2X_RECOVERY_DONE &&
393 sc->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
394 PMD_DRV_LOG(INFO, sc, "DMAE timeout!");
402 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
403 PMD_DRV_LOG(INFO, sc, "DMAE PCI error!");
404 return DMAE_PCI_ERROR;
410 void bnx2x_read_dmae(struct bnx2x_softc *sc, uint32_t src_addr, uint32_t len32)
412 struct dmae_command dmae;
417 if (!sc->dmae_ready) {
418 data = BNX2X_SP(sc, wb_data[0]);
420 for (i = 0; i < len32; i++) {
421 data[i] = REG_RD(sc, (src_addr + (i * 4)));
427 /* set opcode and fixed command fields */
428 bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
430 /* fill in addresses and len */
431 dmae.src_addr_lo = (src_addr >> 2); /* GRC addr has dword resolution */
432 dmae.src_addr_hi = 0;
433 dmae.dst_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_data));
434 dmae.dst_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_data));
437 /* issue the command and wait for completion */
438 if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
439 rte_panic("DMAE failed (%d)", rc);
444 bnx2x_write_dmae(struct bnx2x_softc *sc, rte_iova_t dma_addr, uint32_t dst_addr,
447 struct dmae_command dmae;
450 if (!sc->dmae_ready) {
451 ecore_init_str_wr(sc, dst_addr, BNX2X_SP(sc, wb_data[0]), len32);
455 /* set opcode and fixed command fields */
456 bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
458 /* fill in addresses and len */
459 dmae.src_addr_lo = U64_LO(dma_addr);
460 dmae.src_addr_hi = U64_HI(dma_addr);
461 dmae.dst_addr_lo = (dst_addr >> 2); /* GRC addr has dword resolution */
462 dmae.dst_addr_hi = 0;
465 /* issue the command and wait for completion */
466 if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
467 rte_panic("DMAE failed (%d)", rc);
472 bnx2x_write_dmae_phys_len(struct bnx2x_softc *sc, rte_iova_t phys_addr,
473 uint32_t addr, uint32_t len)
475 uint32_t dmae_wr_max = DMAE_LEN32_WR_MAX(sc);
478 while (len > dmae_wr_max) {
479 bnx2x_write_dmae(sc, (phys_addr + offset), /* src DMA address */
480 (addr + offset), /* dst GRC address */
482 offset += (dmae_wr_max * 4);
486 bnx2x_write_dmae(sc, (phys_addr + offset), /* src DMA address */
487 (addr + offset), /* dst GRC address */
492 bnx2x_set_ctx_validation(struct bnx2x_softc *sc, struct eth_context *cxt,
495 /* ustorm cxt validation */
496 cxt->ustorm_ag_context.cdu_usage =
497 CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
498 CDU_REGION_NUMBER_UCM_AG,
499 ETH_CONNECTION_TYPE);
500 /* xcontext validation */
501 cxt->xstorm_ag_context.cdu_reserved =
502 CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
503 CDU_REGION_NUMBER_XCM_AG,
504 ETH_CONNECTION_TYPE);
508 bnx2x_storm_memset_hc_timeout(struct bnx2x_softc *sc, uint8_t fw_sb_id,
509 uint8_t sb_index, uint8_t ticks)
512 (BAR_CSTRORM_INTMEM +
513 CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(fw_sb_id, sb_index));
515 REG_WR8(sc, addr, ticks);
519 bnx2x_storm_memset_hc_disable(struct bnx2x_softc *sc, uint16_t fw_sb_id,
520 uint8_t sb_index, uint8_t disable)
522 uint32_t enable_flag =
523 (disable) ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
525 (BAR_CSTRORM_INTMEM +
526 CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(fw_sb_id, sb_index));
530 flags = REG_RD8(sc, addr);
531 flags &= ~HC_INDEX_DATA_HC_ENABLED;
532 flags |= enable_flag;
533 REG_WR8(sc, addr, flags);
537 bnx2x_update_coalesce_sb_index(struct bnx2x_softc *sc, uint8_t fw_sb_id,
538 uint8_t sb_index, uint8_t disable, uint16_t usec)
540 uint8_t ticks = (usec / 4);
542 bnx2x_storm_memset_hc_timeout(sc, fw_sb_id, sb_index, ticks);
544 disable = (disable) ? 1 : ((usec) ? 0 : 1);
545 bnx2x_storm_memset_hc_disable(sc, fw_sb_id, sb_index, disable);
548 uint32_t elink_cb_reg_read(struct bnx2x_softc *sc, uint32_t reg_addr)
550 return REG_RD(sc, reg_addr);
553 void elink_cb_reg_write(struct bnx2x_softc *sc, uint32_t reg_addr, uint32_t val)
555 REG_WR(sc, reg_addr, val);
559 elink_cb_event_log(__rte_unused struct bnx2x_softc *sc,
560 __rte_unused const elink_log_id_t elink_log_id, ...)
562 PMD_DRV_LOG(DEBUG, sc, "ELINK EVENT LOG (%d)", elink_log_id);
565 static int bnx2x_set_spio(struct bnx2x_softc *sc, int spio, uint32_t mode)
569 /* Only 2 SPIOs are configurable */
570 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
571 PMD_DRV_LOG(NOTICE, sc, "Invalid SPIO 0x%x", spio);
575 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
577 /* read SPIO and mask except the float bits */
578 spio_reg = (REG_RD(sc, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
581 case MISC_SPIO_OUTPUT_LOW:
582 /* clear FLOAT and set CLR */
583 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
584 spio_reg |= (spio << MISC_SPIO_CLR_POS);
587 case MISC_SPIO_OUTPUT_HIGH:
588 /* clear FLOAT and set SET */
589 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
590 spio_reg |= (spio << MISC_SPIO_SET_POS);
593 case MISC_SPIO_INPUT_HI_Z:
595 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
602 REG_WR(sc, MISC_REG_SPIO, spio_reg);
603 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
608 static int bnx2x_gpio_read(struct bnx2x_softc *sc, int gpio_num, uint8_t port)
610 /* The GPIO should be swapped if swap register is set and active */
611 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
612 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
613 int gpio_shift = gpio_num;
615 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
617 uint32_t gpio_mask = (1 << gpio_shift);
620 if (gpio_num > MISC_REGISTERS_GPIO_3) {
621 PMD_DRV_LOG(NOTICE, sc, "Invalid GPIO %d", gpio_num);
625 /* read GPIO value */
626 gpio_reg = REG_RD(sc, MISC_REG_GPIO);
628 /* get the requested pin value */
629 return ((gpio_reg & gpio_mask) == gpio_mask) ? 1 : 0;
633 bnx2x_gpio_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode, uint8_t port)
635 /* The GPIO should be swapped if swap register is set and active */
636 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
637 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
638 int gpio_shift = gpio_num;
640 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
642 uint32_t gpio_mask = (1 << gpio_shift);
645 if (gpio_num > MISC_REGISTERS_GPIO_3) {
646 PMD_DRV_LOG(NOTICE, sc, "Invalid GPIO %d", gpio_num);
650 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
652 /* read GPIO and mask except the float bits */
653 gpio_reg = (REG_RD(sc, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
656 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
657 /* clear FLOAT and set CLR */
658 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
659 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
662 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
663 /* clear FLOAT and set SET */
664 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
665 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
668 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
670 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
677 REG_WR(sc, MISC_REG_GPIO, gpio_reg);
678 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
684 bnx2x_gpio_mult_write(struct bnx2x_softc *sc, uint8_t pins, uint32_t mode)
688 /* any port swapping should be handled by caller */
690 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
692 /* read GPIO and mask except the float bits */
693 gpio_reg = REG_RD(sc, MISC_REG_GPIO);
694 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
695 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
696 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
699 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
701 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
704 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
706 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
709 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
711 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
715 PMD_DRV_LOG(NOTICE, sc,
716 "Invalid GPIO mode assignment %d", mode);
717 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
721 REG_WR(sc, MISC_REG_GPIO, gpio_reg);
722 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
728 bnx2x_gpio_int_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode,
731 /* The GPIO should be swapped if swap register is set and active */
732 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
733 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
734 int gpio_shift = gpio_num;
736 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
738 uint32_t gpio_mask = (1 << gpio_shift);
741 if (gpio_num > MISC_REGISTERS_GPIO_3) {
742 PMD_DRV_LOG(NOTICE, sc, "Invalid GPIO %d", gpio_num);
746 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
749 gpio_reg = REG_RD(sc, MISC_REG_GPIO_INT);
752 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
753 /* clear SET and set CLR */
754 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
755 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
758 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
759 /* clear CLR and set SET */
760 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
761 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
768 REG_WR(sc, MISC_REG_GPIO_INT, gpio_reg);
769 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
775 elink_cb_gpio_read(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t port)
777 return bnx2x_gpio_read(sc, gpio_num, port);
780 uint8_t elink_cb_gpio_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode, /* 0=low 1=high */
783 return bnx2x_gpio_write(sc, gpio_num, mode, port);
787 elink_cb_gpio_mult_write(struct bnx2x_softc * sc, uint8_t pins,
788 uint8_t mode /* 0=low 1=high */ )
790 return bnx2x_gpio_mult_write(sc, pins, mode);
793 uint8_t elink_cb_gpio_int_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode, /* 0=low 1=high */
796 return bnx2x_gpio_int_write(sc, gpio_num, mode, port);
799 void elink_cb_notify_link_changed(struct bnx2x_softc *sc)
801 REG_WR(sc, (MISC_REG_AEU_GENERAL_ATTN_12 +
802 (SC_FUNC(sc) * sizeof(uint32_t))), 1);
805 /* send the MCP a request, block until there is a reply */
807 elink_cb_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
809 int mb_idx = SC_FW_MB_IDX(sc);
813 uint8_t delay = CHIP_REV_IS_SLOW(sc) ? 100 : 10;
816 SHMEM_WR(sc, func_mb[mb_idx].drv_mb_param, param);
817 SHMEM_WR(sc, func_mb[mb_idx].drv_mb_header, (command | seq));
819 PMD_DRV_LOG(DEBUG, sc,
820 "wrote command 0x%08x to FW MB param 0x%08x",
821 (command | seq), param);
823 /* Let the FW do it's magic. GIve it up to 5 seconds... */
826 rc = SHMEM_RD(sc, func_mb[mb_idx].fw_mb_header);
827 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
829 /* is this a reply to our command? */
830 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) {
831 rc &= FW_MSG_CODE_MASK;
834 PMD_DRV_LOG(NOTICE, sc, "FW failed to respond!");
842 bnx2x_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
844 return elink_cb_fw_command(sc, command, param);
848 __storm_memset_dma_mapping(struct bnx2x_softc *sc, uint32_t addr,
851 REG_WR(sc, addr, U64_LO(mapping));
852 REG_WR(sc, (addr + 4), U64_HI(mapping));
856 storm_memset_spq_addr(struct bnx2x_softc *sc, rte_iova_t mapping,
859 uint32_t addr = (XSEM_REG_FAST_MEMORY +
860 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid));
861 __storm_memset_dma_mapping(sc, addr, mapping);
865 storm_memset_vf_to_pf(struct bnx2x_softc *sc, uint16_t abs_fid, uint16_t pf_id)
867 REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid)),
869 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid)),
871 REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid)),
873 REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid)),
878 storm_memset_func_en(struct bnx2x_softc *sc, uint16_t abs_fid, uint8_t enable)
880 REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid)),
882 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid)),
884 REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid)),
886 REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid)),
891 storm_memset_eq_data(struct bnx2x_softc *sc, struct event_ring_data *eq_data,
897 addr = (BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid));
898 size = sizeof(struct event_ring_data);
899 ecore_storm_memset_struct(sc, addr, size, (uint32_t *) eq_data);
903 storm_memset_eq_prod(struct bnx2x_softc *sc, uint16_t eq_prod, uint16_t pfid)
905 uint32_t addr = (BAR_CSTRORM_INTMEM +
906 CSTORM_EVENT_RING_PROD_OFFSET(pfid));
907 REG_WR16(sc, addr, eq_prod);
911 * Post a slowpath command.
913 * A slowpath command is used to propagate a configuration change through
914 * the controller in a controlled manner, allowing each STORM processor and
915 * other H/W blocks to phase in the change. The commands sent on the
916 * slowpath are referred to as ramrods. Depending on the ramrod used the
917 * completion of the ramrod will occur in different ways. Here's a
918 * breakdown of ramrods and how they complete:
920 * RAMROD_CMD_ID_ETH_PORT_SETUP
921 * Used to setup the leading connection on a port. Completes on the
922 * Receive Completion Queue (RCQ) of that port (typically fp[0]).
924 * RAMROD_CMD_ID_ETH_CLIENT_SETUP
925 * Used to setup an additional connection on a port. Completes on the
926 * RCQ of the multi-queue/RSS connection being initialized.
928 * RAMROD_CMD_ID_ETH_STAT_QUERY
929 * Used to force the storm processors to update the statistics database
930 * in host memory. This ramrod is send on the leading connection CID and
931 * completes as an index increment of the CSTORM on the default status
934 * RAMROD_CMD_ID_ETH_UPDATE
935 * Used to update the state of the leading connection, usually to udpate
936 * the RSS indirection table. Completes on the RCQ of the leading
937 * connection. (Not currently used under FreeBSD until OS support becomes
940 * RAMROD_CMD_ID_ETH_HALT
941 * Used when tearing down a connection prior to driver unload. Completes
942 * on the RCQ of the multi-queue/RSS connection being torn down. Don't
943 * use this on the leading connection.
945 * RAMROD_CMD_ID_ETH_SET_MAC
946 * Sets the Unicast/Broadcast/Multicast used by the port. Completes on
947 * the RCQ of the leading connection.
949 * RAMROD_CMD_ID_ETH_CFC_DEL
950 * Used when tearing down a conneciton prior to driver unload. Completes
951 * on the RCQ of the leading connection (since the current connection
952 * has been completely removed from controller memory).
954 * RAMROD_CMD_ID_ETH_PORT_DEL
955 * Used to tear down the leading connection prior to driver unload,
956 * typically fp[0]. Completes as an index increment of the CSTORM on the
957 * default status block.
959 * RAMROD_CMD_ID_ETH_FORWARD_SETUP
960 * Used for connection offload. Completes on the RCQ of the multi-queue
961 * RSS connection that is being offloaded. (Not currently used under
964 * There can only be one command pending per function.
967 * 0 = Success, !0 = Failure.
970 /* must be called under the spq lock */
971 static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x_softc *sc)
973 struct eth_spe *next_spe = sc->spq_prod_bd;
975 if (sc->spq_prod_bd == sc->spq_last_bd) {
976 /* wrap back to the first eth_spq */
977 sc->spq_prod_bd = sc->spq;
978 sc->spq_prod_idx = 0;
987 /* must be called under the spq lock */
988 static void bnx2x_sp_prod_update(struct bnx2x_softc *sc)
990 int func = SC_FUNC(sc);
993 * Make sure that BD data is updated before writing the producer.
994 * BD data is written to the memory, the producer is read from the
995 * memory, thus we need a full memory barrier to ensure the ordering.
999 REG_WR16(sc, (BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func)),
1006 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
1008 * @cmd: command to check
1009 * @cmd_type: command type
1011 static int bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
1013 if ((cmd_type == NONE_CONNECTION_TYPE) ||
1014 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
1015 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
1016 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
1017 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
1018 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
1019 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) {
1027 * bnx2x_sp_post - place a single command on an SP ring
1029 * @sc: driver handle
1030 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
1031 * @cid: SW CID the command is related to
1032 * @data_hi: command private data address (high 32 bits)
1033 * @data_lo: command private data address (low 32 bits)
1034 * @cmd_type: command type (e.g. NONE, ETH)
1036 * SP data is handled as if it's always an address pair, thus data fields are
1037 * not swapped to little endian in upper functions. Instead this function swaps
1038 * data as if it's two uint32 fields.
1041 bnx2x_sp_post(struct bnx2x_softc *sc, int command, int cid, uint32_t data_hi,
1042 uint32_t data_lo, int cmd_type)
1044 struct eth_spe *spe;
1048 common = bnx2x_is_contextless_ramrod(command, cmd_type);
1051 if (!atomic_load_acq_long(&sc->eq_spq_left)) {
1052 PMD_DRV_LOG(INFO, sc, "EQ ring is full!");
1056 if (!atomic_load_acq_long(&sc->cq_spq_left)) {
1057 PMD_DRV_LOG(INFO, sc, "SPQ ring is full!");
1062 spe = bnx2x_sp_get_next(sc);
1064 /* CID needs port number to be encoded int it */
1065 spe->hdr.conn_and_cmd_data =
1066 htole32((command << SPE_HDR_CMD_ID_SHIFT) | HW_CID(sc, cid));
1068 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
1070 /* TBD: Check if it works for VFs */
1071 type |= ((SC_FUNC(sc) << SPE_HDR_FUNCTION_ID_SHIFT) &
1072 SPE_HDR_FUNCTION_ID);
1074 spe->hdr.type = htole16(type);
1076 spe->data.update_data_addr.hi = htole32(data_hi);
1077 spe->data.update_data_addr.lo = htole32(data_lo);
1080 * It's ok if the actual decrement is issued towards the memory
1081 * somewhere between the lock and unlock. Thus no more explict
1082 * memory barrier is needed.
1085 atomic_subtract_acq_long(&sc->eq_spq_left, 1);
1087 atomic_subtract_acq_long(&sc->cq_spq_left, 1);
1090 PMD_DRV_LOG(DEBUG, sc,
1091 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x"
1092 "data (%x:%x) type(0x%x) left (CQ, EQ) (%lx,%lx)",
1094 (uint32_t) U64_HI(sc->spq_dma.paddr),
1095 (uint32_t) (U64_LO(sc->spq_dma.paddr) +
1096 (uint8_t *) sc->spq_prod_bd -
1097 (uint8_t *) sc->spq), command, common,
1098 HW_CID(sc, cid), data_hi, data_lo, type,
1099 atomic_load_acq_long(&sc->cq_spq_left),
1100 atomic_load_acq_long(&sc->eq_spq_left));
1102 bnx2x_sp_prod_update(sc);
1107 static void bnx2x_drv_pulse(struct bnx2x_softc *sc)
1109 SHMEM_WR(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb,
1110 sc->fw_drv_pulse_wr_seq);
1113 static int bnx2x_tx_queue_has_work(const struct bnx2x_fastpath *fp)
1116 struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1118 if (unlikely(!txq)) {
1119 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1123 mb(); /* status block fields can change */
1124 hw_cons = le16toh(*fp->tx_cons_sb);
1125 return hw_cons != txq->tx_pkt_head;
1128 static uint8_t bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
1130 /* expand this for multi-cos if ever supported */
1131 return bnx2x_tx_queue_has_work(fp);
1134 static int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
1136 uint16_t rx_cq_cons_sb;
1137 struct bnx2x_rx_queue *rxq;
1138 rxq = fp->sc->rx_queues[fp->index];
1139 if (unlikely(!rxq)) {
1140 PMD_RX_LOG(ERR, "ERROR: RX queue is NULL");
1144 mb(); /* status block fields can change */
1145 rx_cq_cons_sb = le16toh(*fp->rx_cq_cons_sb);
1146 if (unlikely((rx_cq_cons_sb & MAX_RCQ_ENTRIES(rxq)) ==
1147 MAX_RCQ_ENTRIES(rxq)))
1149 return rxq->rx_cq_head != rx_cq_cons_sb;
1153 bnx2x_sp_event(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
1154 union eth_rx_cqe *rr_cqe)
1156 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1157 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1158 enum ecore_queue_cmd drv_cmd = ECORE_Q_CMD_MAX;
1159 struct ecore_queue_sp_obj *q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
1161 PMD_DRV_LOG(DEBUG, sc,
1162 "fp=%d cid=%d got ramrod #%d state is %x type is %d",
1163 fp->index, cid, command, sc->state,
1164 rr_cqe->ramrod_cqe.ramrod_type);
1167 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1168 PMD_DRV_LOG(DEBUG, sc, "got UPDATE ramrod. CID %d", cid);
1169 drv_cmd = ECORE_Q_CMD_UPDATE;
1172 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1173 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] setup ramrod", cid);
1174 drv_cmd = ECORE_Q_CMD_SETUP;
1177 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1178 PMD_DRV_LOG(DEBUG, sc,
1179 "got MULTI[%d] tx-only setup ramrod", cid);
1180 drv_cmd = ECORE_Q_CMD_SETUP_TX_ONLY;
1183 case (RAMROD_CMD_ID_ETH_HALT):
1184 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] halt ramrod", cid);
1185 drv_cmd = ECORE_Q_CMD_HALT;
1188 case (RAMROD_CMD_ID_ETH_TERMINATE):
1189 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] teminate ramrod", cid);
1190 drv_cmd = ECORE_Q_CMD_TERMINATE;
1193 case (RAMROD_CMD_ID_ETH_EMPTY):
1194 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] empty ramrod", cid);
1195 drv_cmd = ECORE_Q_CMD_EMPTY;
1199 PMD_DRV_LOG(DEBUG, sc,
1200 "ERROR: unexpected MC reply (%d)"
1201 "on fp[%d]", command, fp->index);
1205 if ((drv_cmd != ECORE_Q_CMD_MAX) &&
1206 q_obj->complete_cmd(sc, q_obj, drv_cmd)) {
1208 * q_obj->complete_cmd() failure means that this was
1209 * an unexpected completion.
1211 * In this case we don't want to increase the sc->spq_left
1212 * because apparently we haven't sent this command the first
1215 // rte_panic("Unexpected SP completion");
1219 atomic_add_acq_long(&sc->cq_spq_left, 1);
1221 PMD_DRV_LOG(DEBUG, sc, "sc->cq_spq_left 0x%lx",
1222 atomic_load_acq_long(&sc->cq_spq_left));
1225 static uint8_t bnx2x_rxeof(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
1227 struct bnx2x_rx_queue *rxq;
1228 uint16_t bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
1229 uint16_t hw_cq_cons, sw_cq_cons, sw_cq_prod;
1231 rxq = sc->rx_queues[fp->index];
1233 PMD_RX_LOG(ERR, "RX queue %d is NULL", fp->index);
1237 /* CQ "next element" is of the size of the regular element */
1238 hw_cq_cons = le16toh(*fp->rx_cq_cons_sb);
1239 if (unlikely((hw_cq_cons & USABLE_RCQ_ENTRIES_PER_PAGE) ==
1240 USABLE_RCQ_ENTRIES_PER_PAGE)) {
1244 bd_cons = rxq->rx_bd_head;
1245 bd_prod = rxq->rx_bd_tail;
1246 bd_prod_fw = bd_prod;
1247 sw_cq_cons = rxq->rx_cq_head;
1248 sw_cq_prod = rxq->rx_cq_tail;
1251 * Memory barrier necessary as speculative reads of the rx
1252 * buffer can be ahead of the index in the status block
1256 while (sw_cq_cons != hw_cq_cons) {
1257 union eth_rx_cqe *cqe;
1258 struct eth_fast_path_rx_cqe *cqe_fp;
1259 uint8_t cqe_fp_flags;
1260 enum eth_rx_cqe_type cqe_fp_type;
1262 comp_ring_cons = RCQ_ENTRY(sw_cq_cons, rxq);
1263 bd_prod = RX_BD(bd_prod, rxq);
1264 bd_cons = RX_BD(bd_cons, rxq);
1266 cqe = &rxq->cq_ring[comp_ring_cons];
1267 cqe_fp = &cqe->fast_path_cqe;
1268 cqe_fp_flags = cqe_fp->type_error_flags;
1269 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
1271 /* is this a slowpath msg? */
1272 if (CQE_TYPE_SLOW(cqe_fp_type)) {
1273 bnx2x_sp_event(sc, fp, cqe);
1277 /* is this an error packet? */
1278 if (unlikely(cqe_fp_flags &
1279 ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG)) {
1280 PMD_RX_LOG(DEBUG, "flags 0x%x rx packet %u",
1281 cqe_fp_flags, sw_cq_cons);
1285 PMD_RX_LOG(DEBUG, "Dropping fastpath called from attn poller!");
1288 bd_cons = NEXT_RX_BD(bd_cons);
1289 bd_prod = NEXT_RX_BD(bd_prod);
1290 bd_prod_fw = NEXT_RX_BD(bd_prod_fw);
1293 sw_cq_prod = NEXT_RCQ_IDX(sw_cq_prod);
1294 sw_cq_cons = NEXT_RCQ_IDX(sw_cq_cons);
1296 } /* while work to do */
1298 rxq->rx_bd_head = bd_cons;
1299 rxq->rx_bd_tail = bd_prod_fw;
1300 rxq->rx_cq_head = sw_cq_cons;
1301 rxq->rx_cq_tail = sw_cq_prod;
1303 /* Update producers */
1304 bnx2x_update_rx_prod(sc, fp, bd_prod_fw, sw_cq_prod);
1306 return sw_cq_cons != hw_cq_cons;
1310 bnx2x_free_tx_pkt(__rte_unused struct bnx2x_fastpath *fp, struct bnx2x_tx_queue *txq,
1311 uint16_t pkt_idx, uint16_t bd_idx)
1313 struct eth_tx_start_bd *tx_start_bd =
1314 &txq->tx_ring[TX_BD(bd_idx, txq)].start_bd;
1315 uint16_t nbd = rte_le_to_cpu_16(tx_start_bd->nbd);
1316 struct rte_mbuf *tx_mbuf = txq->sw_ring[TX_BD(pkt_idx, txq)];
1318 if (likely(tx_mbuf != NULL)) {
1319 rte_pktmbuf_free_seg(tx_mbuf);
1321 PMD_RX_LOG(ERR, "fp[%02d] lost mbuf %lu",
1322 fp->index, (unsigned long)TX_BD(pkt_idx, txq));
1325 txq->sw_ring[TX_BD(pkt_idx, txq)] = NULL;
1326 txq->nb_tx_avail += nbd;
1329 bd_idx = NEXT_TX_BD(bd_idx);
1334 /* processes transmit completions */
1335 uint8_t bnx2x_txeof(__rte_unused struct bnx2x_softc * sc, struct bnx2x_fastpath * fp)
1337 uint16_t bd_cons, hw_cons, sw_cons;
1338 __rte_unused uint16_t tx_bd_avail;
1340 struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1342 if (unlikely(!txq)) {
1343 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1347 bd_cons = txq->tx_bd_head;
1348 hw_cons = rte_le_to_cpu_16(*fp->tx_cons_sb);
1349 sw_cons = txq->tx_pkt_head;
1351 while (sw_cons != hw_cons) {
1352 bd_cons = bnx2x_free_tx_pkt(fp, txq, sw_cons, bd_cons);
1356 txq->tx_pkt_head = sw_cons;
1357 txq->tx_bd_head = bd_cons;
1359 tx_bd_avail = txq->nb_tx_avail;
1361 PMD_TX_LOG(DEBUG, "fp[%02d] avail=%u cons_sb=%u, "
1362 "pkt_head=%u pkt_tail=%u bd_head=%u bd_tail=%u",
1363 fp->index, tx_bd_avail, hw_cons,
1364 txq->tx_pkt_head, txq->tx_pkt_tail,
1365 txq->tx_bd_head, txq->tx_bd_tail);
1369 static void bnx2x_drain_tx_queues(struct bnx2x_softc *sc)
1371 struct bnx2x_fastpath *fp;
1374 /* wait until all TX fastpath tasks have completed */
1375 for (i = 0; i < sc->num_queues; i++) {
1380 while (bnx2x_has_tx_work(fp)) {
1381 bnx2x_txeof(sc, fp);
1385 "Timeout waiting for fp[%d] "
1386 "transmits to complete!", i);
1387 rte_panic("tx drain failure");
1401 bnx2x_del_all_macs(struct bnx2x_softc *sc, struct ecore_vlan_mac_obj *mac_obj,
1402 int mac_type, uint8_t wait_for_comp)
1404 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1407 /* wait for completion of requested */
1408 if (wait_for_comp) {
1409 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1412 /* Set the mac type of addresses we want to clear */
1413 bnx2x_set_bit(mac_type, &vlan_mac_flags);
1415 rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1417 PMD_DRV_LOG(ERR, sc, "Failed to delete MACs (%d)", rc);
1423 bnx2x_fill_accept_flags(struct bnx2x_softc *sc, uint32_t rx_mode,
1424 unsigned long *rx_accept_flags,
1425 unsigned long *tx_accept_flags)
1427 /* Clear the flags first */
1428 *rx_accept_flags = 0;
1429 *tx_accept_flags = 0;
1432 case BNX2X_RX_MODE_NONE:
1434 * 'drop all' supersedes any accept flags that may have been
1435 * passed to the function.
1439 case BNX2X_RX_MODE_NORMAL:
1440 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1441 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, rx_accept_flags);
1442 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1444 /* internal switching mode */
1445 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1446 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, tx_accept_flags);
1447 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1451 case BNX2X_RX_MODE_ALLMULTI:
1452 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1453 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1454 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1456 /* internal switching mode */
1457 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1458 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1459 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1463 case BNX2X_RX_MODE_ALLMULTI_PROMISC:
1464 case BNX2X_RX_MODE_PROMISC:
1466 * According to deffinition of SI mode, iface in promisc mode
1467 * should receive matched and unmatched (in resolution of port)
1470 bnx2x_set_bit(ECORE_ACCEPT_UNMATCHED, rx_accept_flags);
1471 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1472 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1473 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1475 /* internal switching mode */
1476 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1477 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1480 bnx2x_set_bit(ECORE_ACCEPT_ALL_UNICAST, tx_accept_flags);
1482 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1488 PMD_RX_LOG(ERR, "Unknown rx_mode (%d)", rx_mode);
1492 /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
1493 if (rx_mode != BNX2X_RX_MODE_NONE) {
1494 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, rx_accept_flags);
1495 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, tx_accept_flags);
1502 bnx2x_set_q_rx_mode(struct bnx2x_softc *sc, uint8_t cl_id,
1503 unsigned long rx_mode_flags,
1504 unsigned long rx_accept_flags,
1505 unsigned long tx_accept_flags, unsigned long ramrod_flags)
1507 struct ecore_rx_mode_ramrod_params ramrod_param;
1510 memset(&ramrod_param, 0, sizeof(ramrod_param));
1512 /* Prepare ramrod parameters */
1513 ramrod_param.cid = 0;
1514 ramrod_param.cl_id = cl_id;
1515 ramrod_param.rx_mode_obj = &sc->rx_mode_obj;
1516 ramrod_param.func_id = SC_FUNC(sc);
1518 ramrod_param.pstate = &sc->sp_state;
1519 ramrod_param.state = ECORE_FILTER_RX_MODE_PENDING;
1521 ramrod_param.rdata = BNX2X_SP(sc, rx_mode_rdata);
1522 ramrod_param.rdata_mapping =
1523 (rte_iova_t)BNX2X_SP_MAPPING(sc, rx_mode_rdata),
1524 bnx2x_set_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
1526 ramrod_param.ramrod_flags = ramrod_flags;
1527 ramrod_param.rx_mode_flags = rx_mode_flags;
1529 ramrod_param.rx_accept_flags = rx_accept_flags;
1530 ramrod_param.tx_accept_flags = tx_accept_flags;
1532 rc = ecore_config_rx_mode(sc, &ramrod_param);
1534 PMD_RX_LOG(ERR, "Set rx_mode %d failed", sc->rx_mode);
1541 int bnx2x_set_storm_rx_mode(struct bnx2x_softc *sc)
1543 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
1544 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
1547 rc = bnx2x_fill_accept_flags(sc, sc->rx_mode, &rx_accept_flags,
1553 bnx2x_set_bit(RAMROD_RX, &ramrod_flags);
1554 bnx2x_set_bit(RAMROD_TX, &ramrod_flags);
1555 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1557 return bnx2x_set_q_rx_mode(sc, sc->fp[0].cl_id, rx_mode_flags,
1558 rx_accept_flags, tx_accept_flags,
1562 /* returns the "mcp load_code" according to global load_count array */
1563 static int bnx2x_nic_load_no_mcp(struct bnx2x_softc *sc)
1565 int path = SC_PATH(sc);
1566 int port = SC_PORT(sc);
1568 PMD_DRV_LOG(INFO, sc, "NO MCP - load counts[%d] %d, %d, %d",
1569 path, load_count[path][0], load_count[path][1],
1570 load_count[path][2]);
1572 load_count[path][0]++;
1573 load_count[path][1 + port]++;
1574 PMD_DRV_LOG(INFO, sc, "NO MCP - new load counts[%d] %d, %d, %d",
1575 path, load_count[path][0], load_count[path][1],
1576 load_count[path][2]);
1577 if (load_count[path][0] == 1)
1578 return FW_MSG_CODE_DRV_LOAD_COMMON;
1579 else if (load_count[path][1 + port] == 1)
1580 return FW_MSG_CODE_DRV_LOAD_PORT;
1582 return FW_MSG_CODE_DRV_LOAD_FUNCTION;
1585 /* returns the "mcp load_code" according to global load_count array */
1586 static int bnx2x_nic_unload_no_mcp(struct bnx2x_softc *sc)
1588 int port = SC_PORT(sc);
1589 int path = SC_PATH(sc);
1591 PMD_DRV_LOG(INFO, sc, "NO MCP - load counts[%d] %d, %d, %d",
1592 path, load_count[path][0], load_count[path][1],
1593 load_count[path][2]);
1594 load_count[path][0]--;
1595 load_count[path][1 + port]--;
1596 PMD_DRV_LOG(INFO, sc, "NO MCP - new load counts[%d] %d, %d, %d",
1597 path, load_count[path][0], load_count[path][1],
1598 load_count[path][2]);
1599 if (load_count[path][0] == 0) {
1600 return FW_MSG_CODE_DRV_UNLOAD_COMMON;
1601 } else if (load_count[path][1 + port] == 0) {
1602 return FW_MSG_CODE_DRV_UNLOAD_PORT;
1604 return FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
1608 /* request unload mode from the MCP: COMMON, PORT or FUNCTION */
1609 static uint32_t bnx2x_send_unload_req(struct bnx2x_softc *sc, int unload_mode)
1611 uint32_t reset_code = 0;
1613 /* Select the UNLOAD request mode */
1614 if (unload_mode == UNLOAD_NORMAL) {
1615 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1617 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1620 /* Send the request to the MCP */
1621 if (!BNX2X_NOMCP(sc)) {
1622 reset_code = bnx2x_fw_command(sc, reset_code, 0);
1624 reset_code = bnx2x_nic_unload_no_mcp(sc);
1630 /* send UNLOAD_DONE command to the MCP */
1631 static void bnx2x_send_unload_done(struct bnx2x_softc *sc, uint8_t keep_link)
1633 uint32_t reset_param =
1634 keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
1636 /* Report UNLOAD_DONE to MCP */
1637 if (!BNX2X_NOMCP(sc)) {
1638 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
1642 static int bnx2x_func_wait_started(struct bnx2x_softc *sc)
1646 if (!sc->port.pmf) {
1651 * (assumption: No Attention from MCP at this stage)
1652 * PMF probably in the middle of TX disable/enable transaction
1653 * 1. Sync IRS for default SB
1654 * 2. Sync SP queue - this guarantees us that attention handling started
1655 * 3. Wait, that TX disable/enable transaction completes
1657 * 1+2 guarantee that if DCBX attention was scheduled it already changed
1658 * pending bit of transaction from STARTED-->TX_STOPPED, if we already
1659 * received completion for the transaction the state is TX_STOPPED.
1660 * State will return to STARTED after completion of TX_STOPPED-->STARTED
1664 while (ecore_func_get_state(sc, &sc->func_obj) !=
1665 ECORE_F_STATE_STARTED && tout--) {
1669 if (ecore_func_get_state(sc, &sc->func_obj) != ECORE_F_STATE_STARTED) {
1671 * Failed to complete the transaction in a "good way"
1672 * Force both transactions with CLR bit.
1674 struct ecore_func_state_params func_params = { NULL };
1676 PMD_DRV_LOG(NOTICE, sc, "Unexpected function state! "
1677 "Forcing STARTED-->TX_STOPPED-->STARTED");
1679 func_params.f_obj = &sc->func_obj;
1680 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1682 /* STARTED-->TX_STOPPED */
1683 func_params.cmd = ECORE_F_CMD_TX_STOP;
1684 ecore_func_state_change(sc, &func_params);
1686 /* TX_STOPPED-->STARTED */
1687 func_params.cmd = ECORE_F_CMD_TX_START;
1688 return ecore_func_state_change(sc, &func_params);
1694 static int bnx2x_stop_queue(struct bnx2x_softc *sc, int index)
1696 struct bnx2x_fastpath *fp = &sc->fp[index];
1697 struct ecore_queue_state_params q_params = { NULL };
1700 PMD_DRV_LOG(DEBUG, sc, "stopping queue %d cid %d", index, fp->index);
1702 q_params.q_obj = &sc->sp_objs[fp->index].q_obj;
1703 /* We want to wait for completion in this context */
1704 bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
1706 /* Stop the primary connection: */
1708 /* ...halt the connection */
1709 q_params.cmd = ECORE_Q_CMD_HALT;
1710 rc = ecore_queue_state_change(sc, &q_params);
1715 /* ...terminate the connection */
1716 q_params.cmd = ECORE_Q_CMD_TERMINATE;
1717 memset(&q_params.params.terminate, 0,
1718 sizeof(q_params.params.terminate));
1719 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
1720 rc = ecore_queue_state_change(sc, &q_params);
1725 /* ...delete cfc entry */
1726 q_params.cmd = ECORE_Q_CMD_CFC_DEL;
1727 memset(&q_params.params.cfc_del, 0, sizeof(q_params.params.cfc_del));
1728 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
1729 return ecore_queue_state_change(sc, &q_params);
1732 /* wait for the outstanding SP commands */
1733 static uint8_t bnx2x_wait_sp_comp(struct bnx2x_softc *sc, unsigned long mask)
1736 int tout = 5000; /* wait for 5 secs tops */
1740 if (!(atomic_load_acq_long(&sc->sp_state) & mask)) {
1749 tmp = atomic_load_acq_long(&sc->sp_state);
1751 PMD_DRV_LOG(INFO, sc, "Filtering completion timed out: "
1752 "sp_state 0x%lx, mask 0x%lx", tmp, mask);
1759 static int bnx2x_func_stop(struct bnx2x_softc *sc)
1761 struct ecore_func_state_params func_params = { NULL };
1764 /* prepare parameters for function state transitions */
1765 bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1766 func_params.f_obj = &sc->func_obj;
1767 func_params.cmd = ECORE_F_CMD_STOP;
1770 * Try to stop the function the 'good way'. If it fails (in case
1771 * of a parity error during bnx2x_chip_cleanup()) and we are
1772 * not in a debug mode, perform a state transaction in order to
1773 * enable further HW_RESET transaction.
1775 rc = ecore_func_state_change(sc, &func_params);
1777 PMD_DRV_LOG(NOTICE, sc, "FUNC_STOP ramrod failed. "
1778 "Running a dry transaction");
1779 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1780 return ecore_func_state_change(sc, &func_params);
1786 static int bnx2x_reset_hw(struct bnx2x_softc *sc, uint32_t load_code)
1788 struct ecore_func_state_params func_params = { NULL };
1790 /* Prepare parameters for function state transitions */
1791 bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1793 func_params.f_obj = &sc->func_obj;
1794 func_params.cmd = ECORE_F_CMD_HW_RESET;
1796 func_params.params.hw_init.load_phase = load_code;
1798 return ecore_func_state_change(sc, &func_params);
1801 static void bnx2x_int_disable_sync(struct bnx2x_softc *sc, int disable_hw)
1804 /* prevent the HW from sending interrupts */
1805 bnx2x_int_disable(sc);
1810 bnx2x_chip_cleanup(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1812 int port = SC_PORT(sc);
1813 struct ecore_mcast_ramrod_params rparam = { NULL };
1814 uint32_t reset_code;
1817 bnx2x_drain_tx_queues(sc);
1819 /* give HW time to discard old tx messages */
1822 /* Clean all ETH MACs */
1823 rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_ETH_MAC,
1826 PMD_DRV_LOG(NOTICE, sc,
1827 "Failed to delete all ETH MACs (%d)", rc);
1830 /* Clean up UC list */
1831 rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_UC_LIST_MAC,
1834 PMD_DRV_LOG(NOTICE, sc,
1835 "Failed to delete UC MACs list (%d)", rc);
1839 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
1841 /* Set "drop all" to stop Rx */
1844 * We need to take the if_maddr_lock() here in order to prevent
1845 * a race between the completion code and this code.
1848 if (bnx2x_test_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) {
1849 bnx2x_set_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state);
1851 bnx2x_set_storm_rx_mode(sc);
1854 /* Clean up multicast configuration */
1855 rparam.mcast_obj = &sc->mcast_obj;
1856 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1858 PMD_DRV_LOG(NOTICE, sc,
1859 "Failed to send DEL MCAST command (%d)", rc);
1863 * Send the UNLOAD_REQUEST to the MCP. This will return if
1864 * this function should perform FUNCTION, PORT, or COMMON HW
1867 reset_code = bnx2x_send_unload_req(sc, unload_mode);
1870 * (assumption: No Attention from MCP at this stage)
1871 * PMF probably in the middle of TX disable/enable transaction
1873 rc = bnx2x_func_wait_started(sc);
1875 PMD_DRV_LOG(NOTICE, sc, "bnx2x_func_wait_started failed");
1879 * Close multi and leading connections
1880 * Completions for ramrods are collected in a synchronous way
1882 for (i = 0; i < sc->num_queues; i++) {
1883 if (bnx2x_stop_queue(sc, i)) {
1889 * If SP settings didn't get completed so far - something
1890 * very wrong has happen.
1892 if (!bnx2x_wait_sp_comp(sc, ~0x0UL)) {
1893 PMD_DRV_LOG(NOTICE, sc, "Common slow path ramrods got stuck!");
1898 rc = bnx2x_func_stop(sc);
1900 PMD_DRV_LOG(NOTICE, sc, "Function stop failed!");
1903 /* disable HW interrupts */
1904 bnx2x_int_disable_sync(sc, TRUE);
1906 /* Reset the chip */
1907 rc = bnx2x_reset_hw(sc, reset_code);
1909 PMD_DRV_LOG(NOTICE, sc, "Hardware reset failed");
1912 /* Report UNLOAD_DONE to MCP */
1913 bnx2x_send_unload_done(sc, keep_link);
1916 static void bnx2x_disable_close_the_gate(struct bnx2x_softc *sc)
1920 PMD_DRV_LOG(DEBUG, sc, "Disabling 'close the gates'");
1922 val = REG_RD(sc, MISC_REG_AEU_GENERAL_MASK);
1923 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
1924 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
1925 REG_WR(sc, MISC_REG_AEU_GENERAL_MASK, val);
1929 * Cleans the object that have internal lists without sending
1930 * ramrods. Should be run when interrutps are disabled.
1932 static void bnx2x_squeeze_objects(struct bnx2x_softc *sc)
1934 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1935 struct ecore_mcast_ramrod_params rparam = { NULL };
1936 struct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj;
1939 /* Cleanup MACs' object first... */
1941 /* Wait for completion of requested */
1942 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1943 /* Perform a dry cleanup */
1944 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &ramrod_flags);
1946 /* Clean ETH primary MAC */
1947 bnx2x_set_bit(ECORE_ETH_MAC, &vlan_mac_flags);
1948 rc = mac_obj->delete_all(sc, &sc->sp_objs->mac_obj, &vlan_mac_flags,
1951 PMD_DRV_LOG(NOTICE, sc, "Failed to clean ETH MACs (%d)", rc);
1954 /* Cleanup UC list */
1956 bnx2x_set_bit(ECORE_UC_LIST_MAC, &vlan_mac_flags);
1957 rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1959 PMD_DRV_LOG(NOTICE, sc,
1960 "Failed to clean UC list MACs (%d)", rc);
1963 /* Now clean mcast object... */
1965 rparam.mcast_obj = &sc->mcast_obj;
1966 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags);
1968 /* Add a DEL command... */
1969 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1971 PMD_DRV_LOG(NOTICE, sc,
1972 "Failed to send DEL MCAST command (%d)", rc);
1975 /* now wait until all pending commands are cleared */
1977 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
1980 PMD_DRV_LOG(NOTICE, sc,
1981 "Failed to clean MCAST object (%d)", rc);
1985 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
1989 /* stop the controller */
1992 bnx2x_nic_unload(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1994 uint8_t global = FALSE;
1997 PMD_DRV_LOG(DEBUG, sc, "Starting NIC unload...");
1999 /* mark driver as unloaded in shmem2 */
2000 if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
2001 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
2002 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
2003 val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
2006 if (IS_PF(sc) && sc->recovery_state != BNX2X_RECOVERY_DONE &&
2007 (sc->state == BNX2X_STATE_CLOSED || sc->state == BNX2X_STATE_ERROR)) {
2009 * We can get here if the driver has been unloaded
2010 * during parity error recovery and is either waiting for a
2011 * leader to complete or for other functions to unload and
2012 * then ifconfig down has been issued. In this case we want to
2013 * unload and let other functions to complete a recovery
2016 sc->recovery_state = BNX2X_RECOVERY_DONE;
2018 bnx2x_release_leader_lock(sc);
2021 PMD_DRV_LOG(NOTICE, sc, "Can't unload in closed or error state");
2026 * Nothing to do during unload if previous bnx2x_nic_load()
2027 * did not completed successfully - all resourses are released.
2029 if ((sc->state == BNX2X_STATE_CLOSED) || (sc->state == BNX2X_STATE_ERROR)) {
2033 sc->state = BNX2X_STATE_CLOSING_WAITING_HALT;
2036 sc->rx_mode = BNX2X_RX_MODE_NONE;
2037 bnx2x_set_rx_mode(sc);
2041 /* set ALWAYS_ALIVE bit in shmem */
2042 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2044 bnx2x_drv_pulse(sc);
2046 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2047 bnx2x_save_statistics(sc);
2050 /* wait till consumers catch up with producers in all queues */
2051 bnx2x_drain_tx_queues(sc);
2053 /* if VF indicate to PF this function is going down (PF will delete sp
2054 * elements and clear initializations
2057 bnx2x_vf_unload(sc);
2058 } else if (unload_mode != UNLOAD_RECOVERY) {
2059 /* if this is a normal/close unload need to clean up chip */
2060 bnx2x_chip_cleanup(sc, unload_mode, keep_link);
2062 /* Send the UNLOAD_REQUEST to the MCP */
2063 bnx2x_send_unload_req(sc, unload_mode);
2066 * Prevent transactions to host from the functions on the
2067 * engine that doesn't reset global blocks in case of global
2068 * attention once gloabl blocks are reset and gates are opened
2069 * (the engine which leader will perform the recovery
2072 if (!CHIP_IS_E1x(sc)) {
2073 bnx2x_pf_disable(sc);
2076 /* disable HW interrupts */
2077 bnx2x_int_disable_sync(sc, TRUE);
2079 /* Report UNLOAD_DONE to MCP */
2080 bnx2x_send_unload_done(sc, FALSE);
2084 * At this stage no more interrupts will arrive so we may safely clean
2085 * the queue'able objects here in case they failed to get cleaned so far.
2088 bnx2x_squeeze_objects(sc);
2091 /* There should be no more pending SP commands at this stage */
2100 bnx2x_free_fw_stats_mem(sc);
2102 sc->state = BNX2X_STATE_CLOSED;
2105 * Check if there are pending parity attentions. If there are - set
2106 * RECOVERY_IN_PROGRESS.
2108 if (IS_PF(sc) && bnx2x_chk_parity_attn(sc, &global, FALSE)) {
2109 bnx2x_set_reset_in_progress(sc);
2111 /* Set RESET_IS_GLOBAL if needed */
2113 bnx2x_set_reset_global(sc);
2118 * The last driver must disable a "close the gate" if there is no
2119 * parity attention or "process kill" pending.
2121 if (IS_PF(sc) && !bnx2x_clear_pf_load(sc) &&
2122 bnx2x_reset_is_done(sc, SC_PATH(sc))) {
2123 bnx2x_disable_close_the_gate(sc);
2126 PMD_DRV_LOG(DEBUG, sc, "Ended NIC unload");
2132 * Encapsulte an mbuf cluster into the tx bd chain and makes the memory
2133 * visible to the controller.
2135 * If an mbuf is submitted to this routine and cannot be given to the
2136 * controller (e.g. it has too many fragments) then the function may free
2137 * the mbuf and return to the caller.
2140 * int: Number of TX BDs used for the mbuf
2142 * Note the side effect that an mbuf may be freed if it causes a problem.
2144 int bnx2x_tx_encap(struct bnx2x_tx_queue *txq, struct rte_mbuf *m0)
2146 struct eth_tx_start_bd *tx_start_bd;
2147 uint16_t bd_prod, pkt_prod;
2148 struct bnx2x_softc *sc;
2152 bd_prod = txq->tx_bd_tail;
2153 pkt_prod = txq->tx_pkt_tail;
2155 txq->sw_ring[TX_BD(pkt_prod, txq)] = m0;
2157 tx_start_bd = &txq->tx_ring[TX_BD(bd_prod, txq)].start_bd;
2160 rte_cpu_to_le_64(rte_mbuf_data_iova(m0));
2161 tx_start_bd->nbytes = rte_cpu_to_le_16(m0->data_len);
2162 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2163 tx_start_bd->general_data =
2164 (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
2166 tx_start_bd->nbd = rte_cpu_to_le_16(2);
2168 if (m0->ol_flags & PKT_TX_VLAN_PKT) {
2169 tx_start_bd->vlan_or_ethertype =
2170 rte_cpu_to_le_16(m0->vlan_tci);
2171 tx_start_bd->bd_flags.as_bitfield |=
2172 (X_ETH_OUTBAND_VLAN <<
2173 ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT);
2176 tx_start_bd->vlan_or_ethertype =
2177 rte_cpu_to_le_16(pkt_prod);
2179 struct ether_hdr *eh =
2180 rte_pktmbuf_mtod(m0, struct ether_hdr *);
2182 tx_start_bd->vlan_or_ethertype =
2183 rte_cpu_to_le_16(rte_be_to_cpu_16(eh->ether_type));
2187 bd_prod = NEXT_TX_BD(bd_prod);
2189 struct eth_tx_parse_bd_e2 *tx_parse_bd;
2190 const struct ether_hdr *eh =
2191 rte_pktmbuf_mtod(m0, struct ether_hdr *);
2192 uint8_t mac_type = UNICAST_ADDRESS;
2195 &txq->tx_ring[TX_BD(bd_prod, txq)].parse_bd_e2;
2196 if (is_multicast_ether_addr(&eh->d_addr)) {
2197 if (is_broadcast_ether_addr(&eh->d_addr))
2198 mac_type = BROADCAST_ADDRESS;
2200 mac_type = MULTICAST_ADDRESS;
2202 tx_parse_bd->parsing_data =
2203 (mac_type << ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT);
2205 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_hi,
2206 &eh->d_addr.addr_bytes[0], 2);
2207 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_mid,
2208 &eh->d_addr.addr_bytes[2], 2);
2209 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_lo,
2210 &eh->d_addr.addr_bytes[4], 2);
2211 rte_memcpy(&tx_parse_bd->data.mac_addr.src_hi,
2212 &eh->s_addr.addr_bytes[0], 2);
2213 rte_memcpy(&tx_parse_bd->data.mac_addr.src_mid,
2214 &eh->s_addr.addr_bytes[2], 2);
2215 rte_memcpy(&tx_parse_bd->data.mac_addr.src_lo,
2216 &eh->s_addr.addr_bytes[4], 2);
2218 tx_parse_bd->data.mac_addr.dst_hi =
2219 rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_hi);
2220 tx_parse_bd->data.mac_addr.dst_mid =
2221 rte_cpu_to_be_16(tx_parse_bd->data.
2223 tx_parse_bd->data.mac_addr.dst_lo =
2224 rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_lo);
2225 tx_parse_bd->data.mac_addr.src_hi =
2226 rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_hi);
2227 tx_parse_bd->data.mac_addr.src_mid =
2228 rte_cpu_to_be_16(tx_parse_bd->data.
2230 tx_parse_bd->data.mac_addr.src_lo =
2231 rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_lo);
2234 "PBD dst %x %x %x src %x %x %x p_data %x",
2235 tx_parse_bd->data.mac_addr.dst_hi,
2236 tx_parse_bd->data.mac_addr.dst_mid,
2237 tx_parse_bd->data.mac_addr.dst_lo,
2238 tx_parse_bd->data.mac_addr.src_hi,
2239 tx_parse_bd->data.mac_addr.src_mid,
2240 tx_parse_bd->data.mac_addr.src_lo,
2241 tx_parse_bd->parsing_data);
2245 "start bd: nbytes %d flags %x vlan %x",
2246 tx_start_bd->nbytes,
2247 tx_start_bd->bd_flags.as_bitfield,
2248 tx_start_bd->vlan_or_ethertype);
2250 bd_prod = NEXT_TX_BD(bd_prod);
2253 if (TX_IDX(bd_prod) < 2)
2256 txq->nb_tx_avail -= 2;
2257 txq->tx_bd_tail = bd_prod;
2258 txq->tx_pkt_tail = pkt_prod;
2263 static uint16_t bnx2x_cid_ilt_lines(struct bnx2x_softc *sc)
2265 return L2_ILT_LINES(sc);
2268 static void bnx2x_ilt_set_info(struct bnx2x_softc *sc)
2270 struct ilt_client_info *ilt_client;
2271 struct ecore_ilt *ilt = sc->ilt;
2274 PMD_INIT_FUNC_TRACE(sc);
2276 ilt->start_line = FUNC_ILT_BASE(SC_FUNC(sc));
2279 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
2280 ilt_client->client_num = ILT_CLIENT_CDU;
2281 ilt_client->page_size = CDU_ILT_PAGE_SZ;
2282 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
2283 ilt_client->start = line;
2284 line += bnx2x_cid_ilt_lines(sc);
2286 if (CNIC_SUPPORT(sc)) {
2287 line += CNIC_ILT_LINES;
2290 ilt_client->end = (line - 1);
2293 if (QM_INIT(sc->qm_cid_count)) {
2294 ilt_client = &ilt->clients[ILT_CLIENT_QM];
2295 ilt_client->client_num = ILT_CLIENT_QM;
2296 ilt_client->page_size = QM_ILT_PAGE_SZ;
2297 ilt_client->flags = 0;
2298 ilt_client->start = line;
2300 /* 4 bytes for each cid */
2301 line += DIV_ROUND_UP(sc->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
2304 ilt_client->end = (line - 1);
2307 if (CNIC_SUPPORT(sc)) {
2309 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
2310 ilt_client->client_num = ILT_CLIENT_SRC;
2311 ilt_client->page_size = SRC_ILT_PAGE_SZ;
2312 ilt_client->flags = 0;
2313 ilt_client->start = line;
2314 line += SRC_ILT_LINES;
2315 ilt_client->end = (line - 1);
2318 ilt_client = &ilt->clients[ILT_CLIENT_TM];
2319 ilt_client->client_num = ILT_CLIENT_TM;
2320 ilt_client->page_size = TM_ILT_PAGE_SZ;
2321 ilt_client->flags = 0;
2322 ilt_client->start = line;
2323 line += TM_ILT_LINES;
2324 ilt_client->end = (line - 1);
2327 assert((line <= ILT_MAX_LINES));
2330 static void bnx2x_set_fp_rx_buf_size(struct bnx2x_softc *sc)
2334 for (i = 0; i < sc->num_queues; i++) {
2335 /* get the Rx buffer size for RX frames */
2336 sc->fp[i].rx_buf_size =
2337 (IP_HEADER_ALIGNMENT_PADDING + ETH_OVERHEAD + sc->mtu);
2341 int bnx2x_alloc_ilt_mem(struct bnx2x_softc *sc)
2344 sc->ilt = rte_malloc("", sizeof(struct ecore_ilt), RTE_CACHE_LINE_SIZE);
2346 return sc->ilt == NULL;
2349 static int bnx2x_alloc_ilt_lines_mem(struct bnx2x_softc *sc)
2351 sc->ilt->lines = rte_calloc("",
2352 sizeof(struct ilt_line), ILT_MAX_LINES,
2353 RTE_CACHE_LINE_SIZE);
2354 return sc->ilt->lines == NULL;
2357 void bnx2x_free_ilt_mem(struct bnx2x_softc *sc)
2363 static void bnx2x_free_ilt_lines_mem(struct bnx2x_softc *sc)
2365 if (sc->ilt->lines != NULL) {
2366 rte_free(sc->ilt->lines);
2367 sc->ilt->lines = NULL;
2371 static void bnx2x_free_mem(struct bnx2x_softc *sc)
2375 for (i = 0; i < L2_ILT_LINES(sc); i++) {
2376 sc->context[i].vcxt = NULL;
2377 sc->context[i].size = 0;
2380 ecore_ilt_mem_op(sc, ILT_MEMOP_FREE);
2382 bnx2x_free_ilt_lines_mem(sc);
2385 static int bnx2x_alloc_mem(struct bnx2x_softc *sc)
2390 char cdu_name[RTE_MEMZONE_NAMESIZE];
2393 * Allocate memory for CDU context:
2394 * This memory is allocated separately and not in the generic ILT
2395 * functions because CDU differs in few aspects:
2396 * 1. There can be multiple entities allocating memory for context -
2397 * regular L2, CNIC, and SRIOV drivers. Each separately controls
2398 * its own ILT lines.
2399 * 2. Since CDU page-size is not a single 4KB page (which is the case
2400 * for the other ILT clients), to be efficient we want to support
2401 * allocation of sub-page-size in the last entry.
2402 * 3. Context pointers are used by the driver to pass to FW / update
2403 * the context (for the other ILT clients the pointers are used just to
2404 * free the memory during unload).
2406 context_size = (sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(sc));
2407 for (i = 0, allocated = 0; allocated < context_size; i++) {
2408 sc->context[i].size = min(CDU_ILT_PAGE_SZ,
2409 (context_size - allocated));
2411 snprintf(cdu_name, sizeof(cdu_name), "cdu_%d", i);
2412 if (bnx2x_dma_alloc(sc, sc->context[i].size,
2413 &sc->context[i].vcxt_dma,
2414 cdu_name, BNX2X_PAGE_SIZE) != 0) {
2419 sc->context[i].vcxt =
2420 (union cdu_context *)sc->context[i].vcxt_dma.vaddr;
2422 allocated += sc->context[i].size;
2425 bnx2x_alloc_ilt_lines_mem(sc);
2427 if (ecore_ilt_mem_op(sc, ILT_MEMOP_ALLOC)) {
2428 PMD_DRV_LOG(NOTICE, sc, "ecore_ilt_mem_op ILT_MEMOP_ALLOC failed");
2436 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc)
2438 sc->fw_stats_num = 0;
2440 sc->fw_stats_req_size = 0;
2441 sc->fw_stats_req = NULL;
2442 sc->fw_stats_req_mapping = 0;
2444 sc->fw_stats_data_size = 0;
2445 sc->fw_stats_data = NULL;
2446 sc->fw_stats_data_mapping = 0;
2449 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc)
2451 uint8_t num_queue_stats;
2452 int num_groups, vf_headroom = 0;
2454 /* number of queues for statistics is number of eth queues */
2455 num_queue_stats = BNX2X_NUM_ETH_QUEUES(sc);
2458 * Total number of FW statistics requests =
2459 * 1 for port stats + 1 for PF stats + num of queues
2461 sc->fw_stats_num = (2 + num_queue_stats);
2464 * Request is built from stats_query_header and an array of
2465 * stats_query_cmd_group each of which contains STATS_QUERY_CMD_COUNT
2466 * rules. The real number or requests is configured in the
2467 * stats_query_header.
2469 num_groups = (sc->fw_stats_num + vf_headroom) / STATS_QUERY_CMD_COUNT;
2470 if ((sc->fw_stats_num + vf_headroom) % STATS_QUERY_CMD_COUNT)
2473 sc->fw_stats_req_size =
2474 (sizeof(struct stats_query_header) +
2475 (num_groups * sizeof(struct stats_query_cmd_group)));
2478 * Data for statistics requests + stats_counter.
2479 * stats_counter holds per-STORM counters that are incremented when
2480 * STORM has finished with the current request. Memory for FCoE
2481 * offloaded statistics are counted anyway, even if they will not be sent.
2482 * VF stats are not accounted for here as the data of VF stats is stored
2483 * in memory allocated by the VF, not here.
2485 sc->fw_stats_data_size =
2486 (sizeof(struct stats_counter) +
2487 sizeof(struct per_port_stats) + sizeof(struct per_pf_stats) +
2488 /* sizeof(struct fcoe_statistics_params) + */
2489 (sizeof(struct per_queue_stats) * num_queue_stats));
2491 if (bnx2x_dma_alloc(sc, (sc->fw_stats_req_size + sc->fw_stats_data_size),
2492 &sc->fw_stats_dma, "fw_stats",
2493 RTE_CACHE_LINE_SIZE) != 0) {
2494 bnx2x_free_fw_stats_mem(sc);
2498 /* set up the shortcuts */
2500 sc->fw_stats_req = (struct bnx2x_fw_stats_req *)sc->fw_stats_dma.vaddr;
2501 sc->fw_stats_req_mapping = sc->fw_stats_dma.paddr;
2504 (struct bnx2x_fw_stats_data *)((uint8_t *) sc->fw_stats_dma.vaddr +
2505 sc->fw_stats_req_size);
2506 sc->fw_stats_data_mapping = (sc->fw_stats_dma.paddr +
2507 sc->fw_stats_req_size);
2514 * 0-7 - Engine0 load counter.
2515 * 8-15 - Engine1 load counter.
2516 * 16 - Engine0 RESET_IN_PROGRESS bit.
2517 * 17 - Engine1 RESET_IN_PROGRESS bit.
2518 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active
2519 * function on the engine
2520 * 19 - Engine1 ONE_IS_LOADED.
2521 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
2522 * leader to complete (check for both RESET_IN_PROGRESS bits and not
2523 * for just the one belonging to its engine).
2525 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
2526 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
2527 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
2528 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
2529 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
2530 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
2531 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
2532 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
2534 /* set the GLOBAL_RESET bit, should be run under rtnl lock */
2535 static void bnx2x_set_reset_global(struct bnx2x_softc *sc)
2538 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2539 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2540 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
2541 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2544 /* clear the GLOBAL_RESET bit, should be run under rtnl lock */
2545 static void bnx2x_clear_reset_global(struct bnx2x_softc *sc)
2548 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2549 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2550 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
2551 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2554 /* checks the GLOBAL_RESET bit, should be run under rtnl lock */
2555 static uint8_t bnx2x_reset_is_global(struct bnx2x_softc *sc)
2557 return REG_RD(sc, BNX2X_RECOVERY_GLOB_REG) & BNX2X_GLOBAL_RESET_BIT;
2560 /* clear RESET_IN_PROGRESS bit for the engine, should be run under rtnl lock */
2561 static void bnx2x_set_reset_done(struct bnx2x_softc *sc)
2564 uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2565 BNX2X_PATH0_RST_IN_PROG_BIT;
2567 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2569 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2572 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2574 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2577 /* set RESET_IN_PROGRESS for the engine, should be run under rtnl lock */
2578 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc)
2581 uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2582 BNX2X_PATH0_RST_IN_PROG_BIT;
2584 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2586 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2589 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2591 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2594 /* check RESET_IN_PROGRESS bit for an engine, should be run under rtnl lock */
2595 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine)
2597 uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2598 uint32_t bit = engine ? BNX2X_PATH1_RST_IN_PROG_BIT :
2599 BNX2X_PATH0_RST_IN_PROG_BIT;
2601 /* return false if bit is set */
2602 return (val & bit) ? FALSE : TRUE;
2605 /* get the load status for an engine, should be run under rtnl lock */
2606 static uint8_t bnx2x_get_load_status(struct bnx2x_softc *sc, int engine)
2608 uint32_t mask = engine ? BNX2X_PATH1_LOAD_CNT_MASK :
2609 BNX2X_PATH0_LOAD_CNT_MASK;
2610 uint32_t shift = engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2611 BNX2X_PATH0_LOAD_CNT_SHIFT;
2612 uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2614 val = ((val & mask) >> shift);
2619 /* set pf load mark */
2620 static void bnx2x_set_pf_load(struct bnx2x_softc *sc)
2624 uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2625 BNX2X_PATH0_LOAD_CNT_MASK;
2626 uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2627 BNX2X_PATH0_LOAD_CNT_SHIFT;
2629 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2631 PMD_INIT_FUNC_TRACE(sc);
2633 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2635 /* get the current counter value */
2636 val1 = ((val & mask) >> shift);
2638 /* set bit of this PF */
2639 val1 |= (1 << SC_ABS_FUNC(sc));
2641 /* clear the old value */
2644 /* set the new one */
2645 val |= ((val1 << shift) & mask);
2647 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2649 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2652 /* clear pf load mark */
2653 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc)
2656 uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2657 BNX2X_PATH0_LOAD_CNT_MASK;
2658 uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2659 BNX2X_PATH0_LOAD_CNT_SHIFT;
2661 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2662 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2664 /* get the current counter value */
2665 val1 = (val & mask) >> shift;
2667 /* clear bit of that PF */
2668 val1 &= ~(1 << SC_ABS_FUNC(sc));
2670 /* clear the old value */
2673 /* set the new one */
2674 val |= ((val1 << shift) & mask);
2676 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2677 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2681 /* send load requrest to mcp and analyze response */
2682 static int bnx2x_nic_load_request(struct bnx2x_softc *sc, uint32_t * load_code)
2684 PMD_INIT_FUNC_TRACE(sc);
2688 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
2689 DRV_MSG_SEQ_NUMBER_MASK);
2691 PMD_DRV_LOG(DEBUG, sc, "initial fw_seq 0x%04x", sc->fw_seq);
2694 /* get the current FW pulse sequence */
2695 sc->fw_drv_pulse_wr_seq =
2696 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb) &
2697 DRV_PULSE_SEQ_MASK);
2699 /* set ALWAYS_ALIVE bit in shmem */
2700 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2701 bnx2x_drv_pulse(sc);
2705 (*load_code) = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
2706 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
2708 /* if the MCP fails to respond we must abort */
2709 if (!(*load_code)) {
2710 PMD_DRV_LOG(NOTICE, sc, "MCP response failure!");
2714 /* if MCP refused then must abort */
2715 if ((*load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED) {
2716 PMD_DRV_LOG(NOTICE, sc, "MCP refused load request");
2724 * Check whether another PF has already loaded FW to chip. In virtualized
2725 * environments a pf from anoth VM may have already initialized the device
2726 * including loading FW.
2728 static int bnx2x_nic_load_analyze_req(struct bnx2x_softc *sc, uint32_t load_code)
2730 uint32_t my_fw, loaded_fw;
2732 /* is another pf loaded on this engine? */
2733 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
2734 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
2735 /* build my FW version dword */
2736 my_fw = (BNX2X_5710_FW_MAJOR_VERSION +
2737 (BNX2X_5710_FW_MINOR_VERSION << 8) +
2738 (BNX2X_5710_FW_REVISION_VERSION << 16) +
2739 (BNX2X_5710_FW_ENGINEERING_VERSION << 24));
2741 /* read loaded FW from chip */
2742 loaded_fw = REG_RD(sc, XSEM_REG_PRAM);
2743 PMD_DRV_LOG(DEBUG, sc, "loaded FW 0x%08x / my FW 0x%08x",
2746 /* abort nic load if version mismatch */
2747 if (my_fw != loaded_fw) {
2748 PMD_DRV_LOG(NOTICE, sc,
2749 "FW 0x%08x already loaded (mine is 0x%08x)",
2758 /* mark PMF if applicable */
2759 static void bnx2x_nic_load_pmf(struct bnx2x_softc *sc, uint32_t load_code)
2761 uint32_t ncsi_oem_data_addr;
2763 PMD_INIT_FUNC_TRACE(sc);
2765 if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
2766 (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
2767 (load_code == FW_MSG_CODE_DRV_LOAD_PORT)) {
2769 * Barrier here for ordering between the writing to sc->port.pmf here
2770 * and reading it from the periodic task.
2778 PMD_DRV_LOG(DEBUG, sc, "pmf %d", sc->port.pmf);
2780 if (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) {
2781 if (SHMEM2_HAS(sc, ncsi_oem_data_addr)) {
2782 ncsi_oem_data_addr = SHMEM2_RD(sc, ncsi_oem_data_addr);
2783 if (ncsi_oem_data_addr) {
2785 (ncsi_oem_data_addr +
2786 offsetof(struct glob_ncsi_oem_data,
2787 driver_version)), 0);
2793 static void bnx2x_read_mf_cfg(struct bnx2x_softc *sc)
2795 int n = (CHIP_IS_MODE_4_PORT(sc) ? 2 : 1);
2799 if (BNX2X_NOMCP(sc)) {
2800 return; /* what should be the default bvalue in this case */
2804 * The formula for computing the absolute function number is...
2805 * For 2 port configuration (4 functions per port):
2806 * abs_func = 2 * vn + SC_PORT + SC_PATH
2807 * For 4 port configuration (2 functions per port):
2808 * abs_func = 4 * vn + 2 * SC_PORT + SC_PATH
2810 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
2811 abs_func = (n * (2 * vn + SC_PORT(sc)) + SC_PATH(sc));
2812 if (abs_func >= E1H_FUNC_MAX) {
2815 sc->devinfo.mf_info.mf_config[vn] =
2816 MFCFG_RD(sc, func_mf_config[abs_func].config);
2819 if (sc->devinfo.mf_info.mf_config[SC_VN(sc)] &
2820 FUNC_MF_CFG_FUNC_DISABLED) {
2821 PMD_DRV_LOG(DEBUG, sc, "mf_cfg function disabled");
2822 sc->flags |= BNX2X_MF_FUNC_DIS;
2824 PMD_DRV_LOG(DEBUG, sc, "mf_cfg function enabled");
2825 sc->flags &= ~BNX2X_MF_FUNC_DIS;
2829 /* acquire split MCP access lock register */
2830 static int bnx2x_acquire_alr(struct bnx2x_softc *sc)
2834 for (j = 0; j < 1000; j++) {
2836 REG_WR(sc, GRCBASE_MCP + 0x9c, val);
2837 val = REG_RD(sc, GRCBASE_MCP + 0x9c);
2838 if (val & (1L << 31))
2844 if (!(val & (1L << 31))) {
2845 PMD_DRV_LOG(NOTICE, sc, "Cannot acquire MCP access lock register");
2852 /* release split MCP access lock register */
2853 static void bnx2x_release_alr(struct bnx2x_softc *sc)
2855 REG_WR(sc, GRCBASE_MCP + 0x9c, 0);
2858 static void bnx2x_fan_failure(struct bnx2x_softc *sc)
2860 int port = SC_PORT(sc);
2861 uint32_t ext_phy_config;
2863 /* mark the failure */
2865 SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
2867 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2868 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
2869 SHMEM_WR(sc, dev_info.port_hw_config[port].external_phy_config,
2872 /* log the failure */
2873 PMD_DRV_LOG(INFO, sc,
2874 "Fan Failure has caused the driver to shutdown "
2875 "the card to prevent permanent damage. "
2876 "Please contact OEM Support for assistance");
2878 rte_panic("Schedule task to handle fan failure");
2881 /* this function is called upon a link interrupt */
2882 static void bnx2x_link_attn(struct bnx2x_softc *sc)
2884 uint32_t pause_enabled = 0;
2885 struct host_port_stats *pstats;
2888 /* Make sure that we are synced with the current statistics */
2889 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2891 elink_link_update(&sc->link_params, &sc->link_vars);
2893 if (sc->link_vars.link_up) {
2895 /* dropless flow control */
2896 if (sc->dropless_fc) {
2899 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
2904 (BAR_USTRORM_INTMEM +
2905 USTORM_ETH_PAUSE_ENABLED_OFFSET(SC_PORT(sc))),
2909 if (sc->link_vars.mac_type != ELINK_MAC_TYPE_EMAC) {
2910 pstats = BNX2X_SP(sc, port_stats);
2911 /* reset old mac stats */
2912 memset(&(pstats->mac_stx[0]), 0,
2913 sizeof(struct mac_stx));
2916 if (sc->state == BNX2X_STATE_OPEN) {
2917 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
2921 if (sc->link_vars.link_up && sc->link_vars.line_speed) {
2922 cmng_fns = bnx2x_get_cmng_fns_mode(sc);
2924 if (cmng_fns != CMNG_FNS_NONE) {
2925 bnx2x_cmng_fns_init(sc, FALSE, cmng_fns);
2926 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
2930 bnx2x_link_report_locked(sc);
2933 bnx2x_link_sync_notify(sc);
2937 static void bnx2x_attn_int_asserted(struct bnx2x_softc *sc, uint32_t asserted)
2939 int port = SC_PORT(sc);
2940 uint32_t aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2941 MISC_REG_AEU_MASK_ATTN_FUNC_0;
2942 uint32_t nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2943 NIG_REG_MASK_INTERRUPT_PORT0;
2945 uint32_t nig_mask = 0;
2950 if (sc->attn_state & asserted) {
2951 PMD_DRV_LOG(ERR, sc, "IGU ERROR attn=0x%08x", asserted);
2954 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2956 aeu_mask = REG_RD(sc, aeu_addr);
2958 aeu_mask &= ~(asserted & 0x3ff);
2960 REG_WR(sc, aeu_addr, aeu_mask);
2962 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2964 sc->attn_state |= asserted;
2966 if (asserted & ATTN_HARD_WIRED_MASK) {
2967 if (asserted & ATTN_NIG_FOR_FUNC) {
2969 bnx2x_acquire_phy_lock(sc);
2970 /* save nig interrupt mask */
2971 nig_mask = REG_RD(sc, nig_int_mask_addr);
2973 /* If nig_mask is not set, no need to call the update function */
2975 REG_WR(sc, nig_int_mask_addr, 0);
2977 bnx2x_link_attn(sc);
2980 /* handle unicore attn? */
2983 if (asserted & ATTN_SW_TIMER_4_FUNC) {
2984 PMD_DRV_LOG(DEBUG, sc, "ATTN_SW_TIMER_4_FUNC!");
2987 if (asserted & GPIO_2_FUNC) {
2988 PMD_DRV_LOG(DEBUG, sc, "GPIO_2_FUNC!");
2991 if (asserted & GPIO_3_FUNC) {
2992 PMD_DRV_LOG(DEBUG, sc, "GPIO_3_FUNC!");
2995 if (asserted & GPIO_4_FUNC) {
2996 PMD_DRV_LOG(DEBUG, sc, "GPIO_4_FUNC!");
3000 if (asserted & ATTN_GENERAL_ATTN_1) {
3001 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_1!");
3002 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3004 if (asserted & ATTN_GENERAL_ATTN_2) {
3005 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_2!");
3006 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3008 if (asserted & ATTN_GENERAL_ATTN_3) {
3009 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_3!");
3010 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3013 if (asserted & ATTN_GENERAL_ATTN_4) {
3014 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_4!");
3015 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3017 if (asserted & ATTN_GENERAL_ATTN_5) {
3018 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_5!");
3019 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3021 if (asserted & ATTN_GENERAL_ATTN_6) {
3022 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_6!");
3023 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3028 if (sc->devinfo.int_block == INT_BLOCK_HC) {
3030 (HC_REG_COMMAND_REG + port * 32 +
3031 COMMAND_REG_ATTN_BITS_SET);
3033 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER * 8);
3036 PMD_DRV_LOG(DEBUG, sc, "about to mask 0x%08x at %s addr 0x%08x",
3038 (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
3040 REG_WR(sc, reg_addr, asserted);
3042 /* now set back the mask */
3043 if (asserted & ATTN_NIG_FOR_FUNC) {
3045 * Verify that IGU ack through BAR was written before restoring
3046 * NIG mask. This loop should exit after 2-3 iterations max.
3048 if (sc->devinfo.int_block != INT_BLOCK_HC) {
3053 REG_RD(sc, IGU_REG_ATTENTION_ACK_BITS);
3054 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0)
3055 && (++cnt < MAX_IGU_ATTN_ACK_TO));
3058 PMD_DRV_LOG(ERR, sc,
3059 "Failed to verify IGU ack on time");
3065 REG_WR(sc, nig_int_mask_addr, nig_mask);
3067 bnx2x_release_phy_lock(sc);
3072 bnx2x_print_next_block(__rte_unused struct bnx2x_softc *sc, __rte_unused int idx,
3073 __rte_unused const char *blk)
3075 PMD_DRV_LOG(INFO, sc, "%s%s", idx ? ", " : "", blk);
3079 bnx2x_check_blocks_with_parity0(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3082 uint32_t cur_bit = 0;
3085 for (i = 0; sig; i++) {
3086 cur_bit = ((uint32_t) 0x1 << i);
3087 if (sig & cur_bit) {
3089 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3091 bnx2x_print_next_block(sc, par_num++,
3094 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3096 bnx2x_print_next_block(sc, par_num++,
3099 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3101 bnx2x_print_next_block(sc, par_num++,
3104 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3106 bnx2x_print_next_block(sc, par_num++,
3109 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3111 bnx2x_print_next_block(sc, par_num++,
3114 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3116 bnx2x_print_next_block(sc, par_num++,
3119 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3121 bnx2x_print_next_block(sc, par_num++,
3135 bnx2x_check_blocks_with_parity1(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3136 uint8_t * global, uint8_t print)
3139 uint32_t cur_bit = 0;
3140 for (i = 0; sig; i++) {
3141 cur_bit = ((uint32_t) 0x1 << i);
3142 if (sig & cur_bit) {
3144 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3146 bnx2x_print_next_block(sc, par_num++,
3149 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3151 bnx2x_print_next_block(sc, par_num++,
3154 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3156 bnx2x_print_next_block(sc, par_num++,
3159 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3161 bnx2x_print_next_block(sc, par_num++,
3164 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
3166 bnx2x_print_next_block(sc, par_num++,
3169 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3171 bnx2x_print_next_block(sc, par_num++,
3174 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3176 bnx2x_print_next_block(sc, par_num++,
3179 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
3181 bnx2x_print_next_block(sc, par_num++,
3184 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3186 bnx2x_print_next_block(sc, par_num++,
3190 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3192 bnx2x_print_next_block(sc, par_num++,
3195 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3197 bnx2x_print_next_block(sc, par_num++,
3200 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
3202 bnx2x_print_next_block(sc, par_num++,
3205 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3207 bnx2x_print_next_block(sc, par_num++,
3210 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3212 bnx2x_print_next_block(sc, par_num++,
3215 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3217 bnx2x_print_next_block(sc, par_num++,
3220 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
3222 bnx2x_print_next_block(sc, par_num++,
3236 bnx2x_check_blocks_with_parity2(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3239 uint32_t cur_bit = 0;
3242 for (i = 0; sig; i++) {
3243 cur_bit = ((uint32_t) 0x1 << i);
3244 if (sig & cur_bit) {
3246 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3248 bnx2x_print_next_block(sc, par_num++,
3251 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3253 bnx2x_print_next_block(sc, par_num++,
3256 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3258 bnx2x_print_next_block(sc, par_num++,
3259 "PXPPCICLOCKCLIENT");
3261 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3263 bnx2x_print_next_block(sc, par_num++,
3266 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3268 bnx2x_print_next_block(sc, par_num++,
3271 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
3273 bnx2x_print_next_block(sc, par_num++,
3276 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3278 bnx2x_print_next_block(sc, par_num++,
3281 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3283 bnx2x_print_next_block(sc, par_num++,
3297 bnx2x_check_blocks_with_parity3(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3298 uint8_t * global, uint8_t print)
3300 uint32_t cur_bit = 0;
3303 for (i = 0; sig; i++) {
3304 cur_bit = ((uint32_t) 0x1 << i);
3305 if (sig & cur_bit) {
3307 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3309 bnx2x_print_next_block(sc, par_num++,
3313 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3315 bnx2x_print_next_block(sc, par_num++,
3319 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3321 bnx2x_print_next_block(sc, par_num++,
3325 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3327 bnx2x_print_next_block(sc, par_num++,
3342 bnx2x_check_blocks_with_parity4(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3345 uint32_t cur_bit = 0;
3348 for (i = 0; sig; i++) {
3349 cur_bit = ((uint32_t) 0x1 << i);
3350 if (sig & cur_bit) {
3352 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
3354 bnx2x_print_next_block(sc, par_num++,
3357 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
3359 bnx2x_print_next_block(sc, par_num++,
3373 bnx2x_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print,
3378 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
3379 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
3380 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
3381 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
3382 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
3383 PMD_DRV_LOG(ERR, sc,
3384 "Parity error: HW block parity attention:"
3385 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x",
3386 (uint32_t) (sig[0] & HW_PRTY_ASSERT_SET_0),
3387 (uint32_t) (sig[1] & HW_PRTY_ASSERT_SET_1),
3388 (uint32_t) (sig[2] & HW_PRTY_ASSERT_SET_2),
3389 (uint32_t) (sig[3] & HW_PRTY_ASSERT_SET_3),
3390 (uint32_t) (sig[4] & HW_PRTY_ASSERT_SET_4));
3393 PMD_DRV_LOG(INFO, sc, "Parity errors detected in blocks: ");
3396 bnx2x_check_blocks_with_parity0(sc, sig[0] &
3397 HW_PRTY_ASSERT_SET_0,
3400 bnx2x_check_blocks_with_parity1(sc, sig[1] &
3401 HW_PRTY_ASSERT_SET_1,
3402 par_num, global, print);
3404 bnx2x_check_blocks_with_parity2(sc, sig[2] &
3405 HW_PRTY_ASSERT_SET_2,
3408 bnx2x_check_blocks_with_parity3(sc, sig[3] &
3409 HW_PRTY_ASSERT_SET_3,
3410 par_num, global, print);
3412 bnx2x_check_blocks_with_parity4(sc, sig[4] &
3413 HW_PRTY_ASSERT_SET_4,
3417 PMD_DRV_LOG(INFO, sc, "");
3426 bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print)
3428 struct attn_route attn = { {0} };
3429 int port = SC_PORT(sc);
3431 attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
3432 attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
3433 attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
3434 attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
3436 if (!CHIP_IS_E1x(sc))
3438 REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
3440 return bnx2x_parity_attn(sc, global, print, attn.sig);
3443 static void bnx2x_attn_int_deasserted4(struct bnx2x_softc *sc, uint32_t attn)
3447 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
3448 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
3449 PMD_DRV_LOG(INFO, sc, "ERROR: PGLUE hw attention 0x%08x", val);
3450 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
3451 PMD_DRV_LOG(INFO, sc,
3452 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR");
3453 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
3454 PMD_DRV_LOG(INFO, sc,
3455 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR");
3456 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
3457 PMD_DRV_LOG(INFO, sc,
3458 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN");
3459 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
3460 PMD_DRV_LOG(INFO, sc,
3461 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN");
3463 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
3464 PMD_DRV_LOG(INFO, sc,
3465 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN");
3467 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
3468 PMD_DRV_LOG(INFO, sc,
3469 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN");
3470 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
3471 PMD_DRV_LOG(INFO, sc,
3472 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN");
3473 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
3474 PMD_DRV_LOG(INFO, sc,
3475 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN");
3476 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
3477 PMD_DRV_LOG(INFO, sc,
3478 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW");
3481 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
3482 val = REG_RD(sc, ATC_REG_ATC_INT_STS_CLR);
3483 PMD_DRV_LOG(INFO, sc, "ERROR: ATC hw attention 0x%08x", val);
3484 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
3485 PMD_DRV_LOG(INFO, sc,
3486 "ERROR: ATC_ATC_INT_STS_REG_ADDRESS_ERROR");
3487 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
3488 PMD_DRV_LOG(INFO, sc,
3489 "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND");
3490 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
3491 PMD_DRV_LOG(INFO, sc,
3492 "ERROR: ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS");
3493 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
3494 PMD_DRV_LOG(INFO, sc,
3495 "ERROR: ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT");
3496 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
3497 PMD_DRV_LOG(INFO, sc,
3498 "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR");
3499 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
3500 PMD_DRV_LOG(INFO, sc,
3501 "ERROR: ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU");
3504 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3505 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
3506 PMD_DRV_LOG(INFO, sc,
3507 "ERROR: FATAL parity attention set4 0x%08x",
3509 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
3511 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
3515 static void bnx2x_e1h_disable(struct bnx2x_softc *sc)
3517 int port = SC_PORT(sc);
3519 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
3522 static void bnx2x_e1h_enable(struct bnx2x_softc *sc)
3524 int port = SC_PORT(sc);
3526 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3530 * called due to MCP event (on pmf):
3531 * reread new bandwidth configuration
3533 * notify others function about the change
3535 static void bnx2x_config_mf_bw(struct bnx2x_softc *sc)
3537 if (sc->link_vars.link_up) {
3538 bnx2x_cmng_fns_init(sc, TRUE, CMNG_FNS_MINMAX);
3539 bnx2x_link_sync_notify(sc);
3542 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
3545 static void bnx2x_set_mf_bw(struct bnx2x_softc *sc)
3547 bnx2x_config_mf_bw(sc);
3548 bnx2x_fw_command(sc, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3551 static void bnx2x_handle_eee_event(struct bnx2x_softc *sc)
3553 bnx2x_fw_command(sc, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3556 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3558 static void bnx2x_drv_info_ether_stat(struct bnx2x_softc *sc)
3560 struct eth_stats_info *ether_stat = &sc->sp->drv_info_to_mcp.ether_stat;
3562 strncpy(ether_stat->version, BNX2X_DRIVER_VERSION,
3563 ETH_STAT_INFO_VERSION_LEN);
3565 sc->sp_objs[0].mac_obj.get_n_elements(sc, &sc->sp_objs[0].mac_obj,
3566 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3567 ether_stat->mac_local + MAC_PAD,
3570 ether_stat->mtu_size = sc->mtu;
3572 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3573 ether_stat->promiscuous_mode = 0; // (flags & PROMISC) ? 1 : 0;
3575 ether_stat->txq_size = sc->tx_ring_size;
3576 ether_stat->rxq_size = sc->rx_ring_size;
3579 static void bnx2x_handle_drv_info_req(struct bnx2x_softc *sc)
3581 enum drv_info_opcode op_code;
3582 uint32_t drv_info_ctl = SHMEM2_RD(sc, drv_info_control);
3584 /* if drv_info version supported by MFW doesn't match - send NACK */
3585 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3586 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3590 op_code = ((drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3591 DRV_INFO_CONTROL_OP_CODE_SHIFT);
3593 memset(&sc->sp->drv_info_to_mcp, 0, sizeof(union drv_info_to_mcp));
3596 case ETH_STATS_OPCODE:
3597 bnx2x_drv_info_ether_stat(sc);
3599 case FCOE_STATS_OPCODE:
3600 case ISCSI_STATS_OPCODE:
3602 /* if op code isn't supported - send NACK */
3603 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3608 * If we got drv_info attn from MFW then these fields are defined in
3611 SHMEM2_WR(sc, drv_info_host_addr_lo,
3612 U64_LO(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3613 SHMEM2_WR(sc, drv_info_host_addr_hi,
3614 U64_HI(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3616 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3619 static void bnx2x_dcc_event(struct bnx2x_softc *sc, uint32_t dcc_event)
3621 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3623 * This is the only place besides the function initialization
3624 * where the sc->flags can change so it is done without any
3628 mf_info.mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_DISABLED) {
3629 PMD_DRV_LOG(DEBUG, sc, "mf_cfg function disabled");
3630 sc->flags |= BNX2X_MF_FUNC_DIS;
3631 bnx2x_e1h_disable(sc);
3633 PMD_DRV_LOG(DEBUG, sc, "mf_cfg function enabled");
3634 sc->flags &= ~BNX2X_MF_FUNC_DIS;
3635 bnx2x_e1h_enable(sc);
3637 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3640 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3641 bnx2x_config_mf_bw(sc);
3642 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3645 /* Report results to MCP */
3647 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_FAILURE, 0);
3649 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_OK, 0);
3652 static void bnx2x_pmf_update(struct bnx2x_softc *sc)
3654 int port = SC_PORT(sc);
3660 * We need the mb() to ensure the ordering between the writing to
3661 * sc->port.pmf here and reading it from the bnx2x_periodic_task().
3665 /* enable nig attention */
3666 val = (0xff0f | (1 << (SC_VN(sc) + 4)));
3667 if (sc->devinfo.int_block == INT_BLOCK_HC) {
3668 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, val);
3669 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, val);
3670 } else if (!CHIP_IS_E1x(sc)) {
3671 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
3672 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
3675 bnx2x_stats_handle(sc, STATS_EVENT_PMF);
3678 static int bnx2x_mc_assert(struct bnx2x_softc *sc)
3682 __rte_unused uint32_t row0, row1, row2, row3;
3686 REG_RD8(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_INDEX_OFFSET);
3688 PMD_DRV_LOG(ERR, sc, "XSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3690 /* print the asserts */
3691 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3695 BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i));
3698 BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3702 BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3706 BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3709 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3710 PMD_DRV_LOG(ERR, sc,
3711 "XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3712 i, row3, row2, row1, row0);
3721 REG_RD8(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_INDEX_OFFSET);
3723 PMD_DRV_LOG(ERR, sc, "TSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3726 /* print the asserts */
3727 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3731 BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i));
3734 BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3738 BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3742 BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3745 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3746 PMD_DRV_LOG(ERR, sc,
3747 "TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3748 i, row3, row2, row1, row0);
3757 REG_RD8(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_INDEX_OFFSET);
3759 PMD_DRV_LOG(ERR, sc, "CSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3762 /* print the asserts */
3763 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3767 BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i));
3770 BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3774 BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3778 BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3781 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3782 PMD_DRV_LOG(ERR, sc,
3783 "CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3784 i, row3, row2, row1, row0);
3793 REG_RD8(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_INDEX_OFFSET);
3795 PMD_DRV_LOG(ERR, sc, "USTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3798 /* print the asserts */
3799 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3803 BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i));
3806 BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3810 BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3814 BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3817 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3818 PMD_DRV_LOG(ERR, sc,
3819 "USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3820 i, row3, row2, row1, row0);
3830 static void bnx2x_attn_int_deasserted3(struct bnx2x_softc *sc, uint32_t attn)
3832 int func = SC_FUNC(sc);
3835 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3837 if (attn & BNX2X_PMF_LINK_ASSERT(sc)) {
3839 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
3840 bnx2x_read_mf_cfg(sc);
3841 sc->devinfo.mf_info.mf_config[SC_VN(sc)] =
3843 func_mf_config[SC_ABS_FUNC(sc)].config);
3845 SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_status);
3847 if (val & DRV_STATUS_DCC_EVENT_MASK)
3850 DRV_STATUS_DCC_EVENT_MASK));
3852 if (val & DRV_STATUS_SET_MF_BW)
3853 bnx2x_set_mf_bw(sc);
3855 if (val & DRV_STATUS_DRV_INFO_REQ)
3856 bnx2x_handle_drv_info_req(sc);
3858 if ((sc->port.pmf == 0) && (val & DRV_STATUS_PMF))
3859 bnx2x_pmf_update(sc);
3861 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
3862 bnx2x_handle_eee_event(sc);
3864 if (sc->link_vars.periodic_flags &
3865 ELINK_PERIODIC_FLAGS_LINK_EVENT) {
3866 /* sync with link */
3867 bnx2x_acquire_phy_lock(sc);
3868 sc->link_vars.periodic_flags &=
3869 ~ELINK_PERIODIC_FLAGS_LINK_EVENT;
3870 bnx2x_release_phy_lock(sc);
3872 bnx2x_link_sync_notify(sc);
3874 bnx2x_link_report(sc);
3878 * Always call it here: bnx2x_link_report() will
3879 * prevent the link indication duplication.
3881 bnx2x_link_status_update(sc);
3883 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3885 PMD_DRV_LOG(ERR, sc, "MC assert!");
3886 bnx2x_mc_assert(sc);
3887 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3888 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3889 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3890 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3891 rte_panic("MC assert!");
3893 } else if (attn & BNX2X_MCP_ASSERT) {
3895 PMD_DRV_LOG(ERR, sc, "MCP assert!");
3896 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3899 PMD_DRV_LOG(ERR, sc,
3900 "Unknown HW assert! (attn 0x%08x)", attn);
3904 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3905 PMD_DRV_LOG(ERR, sc, "LATCHED attention 0x%08x (masked)", attn);
3906 if (attn & BNX2X_GRC_TIMEOUT) {
3907 val = REG_RD(sc, MISC_REG_GRC_TIMEOUT_ATTN);
3908 PMD_DRV_LOG(ERR, sc, "GRC time-out 0x%08x", val);
3910 if (attn & BNX2X_GRC_RSV) {
3911 val = REG_RD(sc, MISC_REG_GRC_RSV_ATTN);
3912 PMD_DRV_LOG(ERR, sc, "GRC reserved 0x%08x", val);
3914 REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3918 static void bnx2x_attn_int_deasserted2(struct bnx2x_softc *sc, uint32_t attn)
3920 int port = SC_PORT(sc);
3922 uint32_t val0, mask0, val1, mask1;
3925 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3926 val = REG_RD(sc, CFC_REG_CFC_INT_STS_CLR);
3927 PMD_DRV_LOG(ERR, sc, "CFC hw attention 0x%08x", val);
3928 /* CFC error attention */
3930 PMD_DRV_LOG(ERR, sc, "FATAL error from CFC");
3934 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3935 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_0);
3936 PMD_DRV_LOG(ERR, sc, "PXP hw attention-0 0x%08x", val);
3937 /* RQ_USDMDP_FIFO_OVERFLOW */
3938 if (val & 0x18000) {
3939 PMD_DRV_LOG(ERR, sc, "FATAL error from PXP");
3942 if (!CHIP_IS_E1x(sc)) {
3943 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_1);
3944 PMD_DRV_LOG(ERR, sc, "PXP hw attention-1 0x%08x", val);
3947 #define PXP2_EOP_ERROR_BIT PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR
3948 #define AEU_PXP2_HW_INT_BIT AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT
3950 if (attn & AEU_PXP2_HW_INT_BIT) {
3951 /* CQ47854 workaround do not panic on
3952 * PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3954 if (!CHIP_IS_E1x(sc)) {
3955 mask0 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_0);
3956 val1 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_1);
3957 mask1 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_1);
3958 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_0);
3960 * If the only PXP2_EOP_ERROR_BIT is set in
3961 * STS0 and STS1 - clear it
3963 * probably we lose additional attentions between
3964 * STS0 and STS_CLR0, in this case user will not
3965 * be notified about them
3967 if (val0 & mask0 & PXP2_EOP_ERROR_BIT &&
3969 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
3971 /* print the register, since no one can restore it */
3972 PMD_DRV_LOG(ERR, sc,
3973 "PXP2_REG_PXP2_INT_STS_CLR_0 0x%08x", val0);
3976 * if PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3979 if (val0 & PXP2_EOP_ERROR_BIT) {
3980 PMD_DRV_LOG(ERR, sc, "PXP2_WR_PGLUE_EOP_ERROR");
3983 * if only PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR is
3984 * set then clear attention from PXP2 block without panic
3986 if (((val0 & mask0) == PXP2_EOP_ERROR_BIT) &&
3987 ((val1 & mask1) == 0))
3988 attn &= ~AEU_PXP2_HW_INT_BIT;
3993 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3994 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3995 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3997 val = REG_RD(sc, reg_offset);
3998 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3999 REG_WR(sc, reg_offset, val);
4001 PMD_DRV_LOG(ERR, sc,
4002 "FATAL HW block attention set2 0x%x",
4003 (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_2));
4004 rte_panic("HW block attention set2");
4008 static void bnx2x_attn_int_deasserted1(struct bnx2x_softc *sc, uint32_t attn)
4010 int port = SC_PORT(sc);
4014 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
4015 val = REG_RD(sc, DORQ_REG_DORQ_INT_STS_CLR);
4016 PMD_DRV_LOG(ERR, sc, "DB hw attention 0x%08x", val);
4017 /* DORQ discard attention */
4019 PMD_DRV_LOG(ERR, sc, "FATAL error from DORQ");
4023 if (attn & HW_INTERRUT_ASSERT_SET_1) {
4024 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4025 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4027 val = REG_RD(sc, reg_offset);
4028 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4029 REG_WR(sc, reg_offset, val);
4031 PMD_DRV_LOG(ERR, sc,
4032 "FATAL HW block attention set1 0x%08x",
4033 (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_1));
4034 rte_panic("HW block attention set1");
4038 static void bnx2x_attn_int_deasserted0(struct bnx2x_softc *sc, uint32_t attn)
4040 int port = SC_PORT(sc);
4044 reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4045 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
4047 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4048 val = REG_RD(sc, reg_offset);
4049 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4050 REG_WR(sc, reg_offset, val);
4052 PMD_DRV_LOG(WARNING, sc, "SPIO5 hw attention");
4054 /* Fan failure attention */
4055 elink_hw_reset_phy(&sc->link_params);
4056 bnx2x_fan_failure(sc);
4059 if ((attn & sc->link_vars.aeu_int_mask) && sc->port.pmf) {
4060 bnx2x_acquire_phy_lock(sc);
4061 elink_handle_module_detect_int(&sc->link_params);
4062 bnx2x_release_phy_lock(sc);
4065 if (attn & HW_INTERRUT_ASSERT_SET_0) {
4066 val = REG_RD(sc, reg_offset);
4067 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4068 REG_WR(sc, reg_offset, val);
4070 rte_panic("FATAL HW block attention set0 0x%lx",
4071 (attn & HW_INTERRUT_ASSERT_SET_0));
4075 static void bnx2x_attn_int_deasserted(struct bnx2x_softc *sc, uint32_t deasserted)
4077 struct attn_route attn;
4078 struct attn_route *group_mask;
4079 int port = SC_PORT(sc);
4084 uint8_t global = FALSE;
4087 * Need to take HW lock because MCP or other port might also
4088 * try to handle this event.
4090 bnx2x_acquire_alr(sc);
4092 if (bnx2x_chk_parity_attn(sc, &global, TRUE)) {
4093 sc->recovery_state = BNX2X_RECOVERY_INIT;
4095 /* disable HW interrupts */
4096 bnx2x_int_disable(sc);
4097 bnx2x_release_alr(sc);
4101 attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
4102 attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
4103 attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
4104 attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
4105 if (!CHIP_IS_E1x(sc)) {
4107 REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
4112 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4113 if (deasserted & (1 << index)) {
4114 group_mask = &sc->attn_group[index];
4116 bnx2x_attn_int_deasserted4(sc,
4118 sig[4] & group_mask->sig[4]);
4119 bnx2x_attn_int_deasserted3(sc,
4121 sig[3] & group_mask->sig[3]);
4122 bnx2x_attn_int_deasserted1(sc,
4124 sig[1] & group_mask->sig[1]);
4125 bnx2x_attn_int_deasserted2(sc,
4127 sig[2] & group_mask->sig[2]);
4128 bnx2x_attn_int_deasserted0(sc,
4130 sig[0] & group_mask->sig[0]);
4134 bnx2x_release_alr(sc);
4136 if (sc->devinfo.int_block == INT_BLOCK_HC) {
4137 reg_addr = (HC_REG_COMMAND_REG + port * 32 +
4138 COMMAND_REG_ATTN_BITS_CLR);
4140 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER * 8);
4144 PMD_DRV_LOG(DEBUG, sc,
4145 "about to mask 0x%08x at %s addr 0x%08x", val,
4146 (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
4148 REG_WR(sc, reg_addr, val);
4150 if (~sc->attn_state & deasserted) {
4151 PMD_DRV_LOG(ERR, sc, "IGU error");
4154 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4155 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4157 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4159 aeu_mask = REG_RD(sc, reg_addr);
4161 aeu_mask |= (deasserted & 0x3ff);
4163 REG_WR(sc, reg_addr, aeu_mask);
4164 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4166 sc->attn_state &= ~deasserted;
4169 static void bnx2x_attn_int(struct bnx2x_softc *sc)
4171 /* read local copy of bits */
4172 uint32_t attn_bits = le32toh(sc->def_sb->atten_status_block.attn_bits);
4174 le32toh(sc->def_sb->atten_status_block.attn_bits_ack);
4175 uint32_t attn_state = sc->attn_state;
4177 /* look for changed bits */
4178 uint32_t asserted = attn_bits & ~attn_ack & ~attn_state;
4179 uint32_t deasserted = ~attn_bits & attn_ack & attn_state;
4181 PMD_DRV_LOG(DEBUG, sc,
4182 "attn_bits 0x%08x attn_ack 0x%08x asserted 0x%08x deasserted 0x%08x",
4183 attn_bits, attn_ack, asserted, deasserted);
4185 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) {
4186 PMD_DRV_LOG(ERR, sc, "BAD attention state");
4189 /* handle bits that were raised */
4191 bnx2x_attn_int_asserted(sc, asserted);
4195 bnx2x_attn_int_deasserted(sc, deasserted);
4199 static uint16_t bnx2x_update_dsb_idx(struct bnx2x_softc *sc)
4201 struct host_sp_status_block *def_sb = sc->def_sb;
4207 mb(); /* status block is written to by the chip */
4209 if (sc->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
4210 sc->def_att_idx = def_sb->atten_status_block.attn_bits_index;
4211 rc |= BNX2X_DEF_SB_ATT_IDX;
4214 if (sc->def_idx != def_sb->sp_sb.running_index) {
4215 sc->def_idx = def_sb->sp_sb.running_index;
4216 rc |= BNX2X_DEF_SB_IDX;
4224 static struct ecore_queue_sp_obj *bnx2x_cid_to_q_obj(struct bnx2x_softc *sc,
4227 return &sc->sp_objs[CID_TO_FP(cid, sc)].q_obj;
4230 static void bnx2x_handle_mcast_eqe(struct bnx2x_softc *sc)
4232 struct ecore_mcast_ramrod_params rparam;
4235 memset(&rparam, 0, sizeof(rparam));
4237 rparam.mcast_obj = &sc->mcast_obj;
4239 /* clear pending state for the last command */
4240 sc->mcast_obj.raw.clear_pending(&sc->mcast_obj.raw);
4242 /* if there are pending mcast commands - send them */
4243 if (sc->mcast_obj.check_pending(&sc->mcast_obj)) {
4244 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
4246 PMD_DRV_LOG(INFO, sc,
4247 "Failed to send pending mcast commands (%d)",
4254 bnx2x_handle_classification_eqe(struct bnx2x_softc *sc, union event_ring_elem *elem)
4256 unsigned long ramrod_flags = 0;
4258 uint32_t cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4259 struct ecore_vlan_mac_obj *vlan_mac_obj;
4261 /* always push next commands out, don't wait here */
4262 bnx2x_set_bit(RAMROD_CONT, &ramrod_flags);
4264 switch (le32toh(elem->message.data.eth_event.echo) >> BNX2X_SWCID_SHIFT) {
4265 case ECORE_FILTER_MAC_PENDING:
4266 PMD_DRV_LOG(DEBUG, sc, "Got SETUP_MAC completions");
4267 vlan_mac_obj = &sc->sp_objs[cid].mac_obj;
4270 case ECORE_FILTER_MCAST_PENDING:
4271 PMD_DRV_LOG(DEBUG, sc, "Got SETUP_MCAST completions");
4272 bnx2x_handle_mcast_eqe(sc);
4276 PMD_DRV_LOG(NOTICE, sc, "Unsupported classification command: %d",
4277 elem->message.data.eth_event.echo);
4281 rc = vlan_mac_obj->complete(sc, vlan_mac_obj, elem, &ramrod_flags);
4284 PMD_DRV_LOG(NOTICE, sc,
4285 "Failed to schedule new commands (%d)", rc);
4286 } else if (rc > 0) {
4287 PMD_DRV_LOG(DEBUG, sc, "Scheduled next pending commands...");
4291 static void bnx2x_handle_rx_mode_eqe(struct bnx2x_softc *sc)
4293 bnx2x_clear_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
4295 /* send rx_mode command again if was requested */
4296 if (bnx2x_test_and_clear_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state)) {
4297 bnx2x_set_storm_rx_mode(sc);
4301 static void bnx2x_update_eq_prod(struct bnx2x_softc *sc, uint16_t prod)
4303 storm_memset_eq_prod(sc, prod, SC_FUNC(sc));
4304 wmb(); /* keep prod updates ordered */
4307 static void bnx2x_eq_int(struct bnx2x_softc *sc)
4309 uint16_t hw_cons, sw_cons, sw_prod;
4310 union event_ring_elem *elem;
4315 struct ecore_queue_sp_obj *q_obj;
4316 struct ecore_func_sp_obj *f_obj = &sc->func_obj;
4317 struct ecore_raw_obj *rss_raw = &sc->rss_conf_obj.raw;
4319 hw_cons = le16toh(*sc->eq_cons_sb);
4322 * The hw_cons range is 1-255, 257 - the sw_cons range is 0-254, 256.
4323 * when we get to the next-page we need to adjust so the loop
4324 * condition below will be met. The next element is the size of a
4325 * regular element and hence incrementing by 1
4327 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) {
4332 * This function may never run in parallel with itself for a
4333 * specific sc and no need for a read memory barrier here.
4335 sw_cons = sc->eq_cons;
4336 sw_prod = sc->eq_prod;
4340 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4342 elem = &sc->eq[EQ_DESC(sw_cons)];
4344 /* elem CID originates from FW, actually LE */
4345 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4346 opcode = elem->message.opcode;
4348 /* handle eq element */
4350 case EVENT_RING_OPCODE_STAT_QUERY:
4351 PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "got statistics completion event %d",
4353 /* nothing to do with stats comp */
4356 case EVENT_RING_OPCODE_CFC_DEL:
4357 /* handle according to cid range */
4358 /* we may want to verify here that the sc state is HALTING */
4359 PMD_DRV_LOG(DEBUG, sc, "got delete ramrod for MULTI[%d]",
4361 q_obj = bnx2x_cid_to_q_obj(sc, cid);
4362 if (q_obj->complete_cmd(sc, q_obj, ECORE_Q_CMD_CFC_DEL)) {
4367 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4368 PMD_DRV_LOG(DEBUG, sc, "got STOP TRAFFIC");
4369 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_STOP)) {
4374 case EVENT_RING_OPCODE_START_TRAFFIC:
4375 PMD_DRV_LOG(DEBUG, sc, "got START TRAFFIC");
4376 if (f_obj->complete_cmd
4377 (sc, f_obj, ECORE_F_CMD_TX_START)) {
4382 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
4383 echo = elem->message.data.function_update_event.echo;
4384 if (echo == SWITCH_UPDATE) {
4385 PMD_DRV_LOG(DEBUG, sc,
4386 "got FUNC_SWITCH_UPDATE ramrod");
4387 if (f_obj->complete_cmd(sc, f_obj,
4388 ECORE_F_CMD_SWITCH_UPDATE))
4393 PMD_DRV_LOG(DEBUG, sc,
4394 "AFEX: ramrod completed FUNCTION_UPDATE");
4395 f_obj->complete_cmd(sc, f_obj,
4396 ECORE_F_CMD_AFEX_UPDATE);
4400 case EVENT_RING_OPCODE_FORWARD_SETUP:
4401 q_obj = &bnx2x_fwd_sp_obj(sc, q_obj);
4402 if (q_obj->complete_cmd(sc, q_obj,
4403 ECORE_Q_CMD_SETUP_TX_ONLY)) {
4408 case EVENT_RING_OPCODE_FUNCTION_START:
4409 PMD_DRV_LOG(DEBUG, sc, "got FUNC_START ramrod");
4410 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_START)) {
4415 case EVENT_RING_OPCODE_FUNCTION_STOP:
4416 PMD_DRV_LOG(DEBUG, sc, "got FUNC_STOP ramrod");
4417 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_STOP)) {
4423 switch (opcode | sc->state) {
4424 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPEN):
4425 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPENING_WAITING_PORT):
4427 elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4428 PMD_DRV_LOG(DEBUG, sc, "got RSS_UPDATE ramrod. CID %d",
4430 rss_raw->clear_pending(rss_raw);
4433 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4434 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4435 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_CLOSING_WAITING_HALT):
4436 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_OPEN):
4437 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_DIAG):
4438 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4439 PMD_DRV_LOG(DEBUG, sc,
4440 "got (un)set mac ramrod");
4441 bnx2x_handle_classification_eqe(sc, elem);
4444 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_OPEN):
4445 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_DIAG):
4446 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4447 PMD_DRV_LOG(DEBUG, sc,
4448 "got mcast ramrod");
4449 bnx2x_handle_mcast_eqe(sc);
4452 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_OPEN):
4453 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_DIAG):
4454 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4455 PMD_DRV_LOG(DEBUG, sc,
4456 "got rx_mode ramrod");
4457 bnx2x_handle_rx_mode_eqe(sc);
4461 /* unknown event log error and continue */
4462 PMD_DRV_LOG(INFO, sc, "Unknown EQ event %d, sc->state 0x%x",
4463 elem->message.opcode, sc->state);
4471 atomic_add_acq_long(&sc->eq_spq_left, spqe_cnt);
4473 sc->eq_cons = sw_cons;
4474 sc->eq_prod = sw_prod;
4476 /* make sure that above mem writes were issued towards the memory */
4479 /* update producer */
4480 bnx2x_update_eq_prod(sc, sc->eq_prod);
4483 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc)
4488 PMD_DRV_LOG(DEBUG, sc, "---> SP TASK <---");
4490 /* what work needs to be performed? */
4491 status = bnx2x_update_dsb_idx(sc);
4493 PMD_DRV_LOG(DEBUG, sc, "dsb status 0x%04x", status);
4496 if (status & BNX2X_DEF_SB_ATT_IDX) {
4497 PMD_DRV_LOG(DEBUG, sc, "---> ATTN INTR <---");
4499 status &= ~BNX2X_DEF_SB_ATT_IDX;
4503 /* SP events: STAT_QUERY and others */
4504 if (status & BNX2X_DEF_SB_IDX) {
4505 /* handle EQ completions */
4506 PMD_DRV_LOG(DEBUG, sc, "---> EQ INTR <---");
4508 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
4509 le16toh(sc->def_idx), IGU_INT_NOP, 1);
4510 status &= ~BNX2X_DEF_SB_IDX;
4513 /* if status is non zero then something went wrong */
4514 if (unlikely(status)) {
4515 PMD_DRV_LOG(INFO, sc,
4516 "Got an unknown SP interrupt! (0x%04x)", status);
4519 /* ack status block only if something was actually handled */
4520 bnx2x_ack_sb(sc, sc->igu_dsb_id, ATTENTION_ID,
4521 le16toh(sc->def_att_idx), IGU_INT_ENABLE, 1);
4526 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp, int scan_fp)
4528 struct bnx2x_softc *sc = fp->sc;
4529 uint8_t more_rx = FALSE;
4531 /* Make sure FP is initialized */
4532 if (!fp->sb_running_index)
4535 PMD_DEBUG_PERIODIC_LOG(DEBUG, sc,
4536 "---> FP TASK QUEUE (%d) <--", fp->index);
4538 /* update the fastpath index */
4539 bnx2x_update_fp_sb_idx(fp);
4542 if (bnx2x_has_rx_work(fp)) {
4543 more_rx = bnx2x_rxeof(sc, fp);
4547 /* still more work to do */
4548 bnx2x_handle_fp_tq(fp, scan_fp);
4553 bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
4554 le16toh(fp->fp_hc_idx), IGU_INT_ENABLE, 1);
4558 * Legacy interrupt entry point.
4560 * Verifies that the controller generated the interrupt and
4561 * then calls a separate routine to handle the various
4562 * interrupt causes: link, RX, and TX.
4564 int bnx2x_intr_legacy(struct bnx2x_softc *sc, int scan_fp)
4566 struct bnx2x_fastpath *fp;
4567 uint32_t status, mask;
4571 * 0 for ustorm, 1 for cstorm
4572 * the bits returned from ack_int() are 0-15
4573 * bit 0 = attention status block
4574 * bit 1 = fast path status block
4575 * a mask of 0x2 or more = tx/rx event
4576 * a mask of 1 = slow path event
4579 status = bnx2x_ack_int(sc);
4581 /* the interrupt is not for us */
4582 if (unlikely(status == 0)) {
4586 PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "Interrupt status 0x%04x", status);
4587 //bnx2x_dump_status_block(sc);
4589 FOR_EACH_ETH_QUEUE(sc, i) {
4591 mask = (0x2 << (fp->index + CNIC_SUPPORT(sc)));
4592 if (status & mask) {
4593 /* acknowledge and disable further fastpath interrupts */
4594 bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
4595 0, IGU_INT_DISABLE, 0);
4596 bnx2x_handle_fp_tq(fp, scan_fp);
4601 if (unlikely(status & 0x1)) {
4602 /* acknowledge and disable further slowpath interrupts */
4603 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
4604 0, IGU_INT_DISABLE, 0);
4605 rc = bnx2x_handle_sp_tq(sc);
4609 if (unlikely(status)) {
4610 PMD_DRV_LOG(WARNING, sc,
4611 "Unexpected fastpath status (0x%08x)!", status);
4617 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc);
4618 static int bnx2x_init_hw_common(struct bnx2x_softc *sc);
4619 static int bnx2x_init_hw_port(struct bnx2x_softc *sc);
4620 static int bnx2x_init_hw_func(struct bnx2x_softc *sc);
4621 static void bnx2x_reset_common(struct bnx2x_softc *sc);
4622 static void bnx2x_reset_port(struct bnx2x_softc *sc);
4623 static void bnx2x_reset_func(struct bnx2x_softc *sc);
4624 static int bnx2x_init_firmware(struct bnx2x_softc *sc);
4625 static void bnx2x_release_firmware(struct bnx2x_softc *sc);
4628 ecore_func_sp_drv_ops bnx2x_func_sp_drv = {
4629 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
4630 .init_hw_cmn = bnx2x_init_hw_common,
4631 .init_hw_port = bnx2x_init_hw_port,
4632 .init_hw_func = bnx2x_init_hw_func,
4634 .reset_hw_cmn = bnx2x_reset_common,
4635 .reset_hw_port = bnx2x_reset_port,
4636 .reset_hw_func = bnx2x_reset_func,
4638 .init_fw = bnx2x_init_firmware,
4639 .release_fw = bnx2x_release_firmware,
4642 static void bnx2x_init_func_obj(struct bnx2x_softc *sc)
4646 PMD_INIT_FUNC_TRACE(sc);
4648 ecore_init_func_obj(sc,
4650 BNX2X_SP(sc, func_rdata),
4651 (rte_iova_t)BNX2X_SP_MAPPING(sc, func_rdata),
4652 BNX2X_SP(sc, func_afex_rdata),
4653 (rte_iova_t)BNX2X_SP_MAPPING(sc, func_afex_rdata),
4654 &bnx2x_func_sp_drv);
4657 static int bnx2x_init_hw(struct bnx2x_softc *sc, uint32_t load_code)
4659 struct ecore_func_state_params func_params = { NULL };
4662 PMD_INIT_FUNC_TRACE(sc);
4664 /* prepare the parameters for function state transitions */
4665 bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
4667 func_params.f_obj = &sc->func_obj;
4668 func_params.cmd = ECORE_F_CMD_HW_INIT;
4670 func_params.params.hw_init.load_phase = load_code;
4673 * Via a plethora of function pointers, we will eventually reach
4674 * bnx2x_init_hw_common(), bnx2x_init_hw_port(), or bnx2x_init_hw_func().
4676 rc = ecore_func_state_change(sc, &func_params);
4682 bnx2x_fill(struct bnx2x_softc *sc, uint32_t addr, int fill, uint32_t len)
4686 if (!(len % 4) && !(addr % 4)) {
4687 for (i = 0; i < len; i += 4) {
4688 REG_WR(sc, (addr + i), fill);
4691 for (i = 0; i < len; i++) {
4692 REG_WR8(sc, (addr + i), fill);
4697 /* writes FP SP data to FW - data_size in dwords */
4699 bnx2x_wr_fp_sb_data(struct bnx2x_softc *sc, int fw_sb_id, uint32_t * sb_data_p,
4704 for (index = 0; index < data_size; index++) {
4706 (BAR_CSTRORM_INTMEM +
4707 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
4708 (sizeof(uint32_t) * index)), *(sb_data_p + index));
4712 static void bnx2x_zero_fp_sb(struct bnx2x_softc *sc, int fw_sb_id)
4714 struct hc_status_block_data_e2 sb_data_e2;
4715 struct hc_status_block_data_e1x sb_data_e1x;
4716 uint32_t *sb_data_p;
4717 uint32_t data_size = 0;
4719 if (!CHIP_IS_E1x(sc)) {
4720 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4721 sb_data_e2.common.state = SB_DISABLED;
4722 sb_data_e2.common.p_func.vf_valid = FALSE;
4723 sb_data_p = (uint32_t *) & sb_data_e2;
4724 data_size = (sizeof(struct hc_status_block_data_e2) /
4727 memset(&sb_data_e1x, 0,
4728 sizeof(struct hc_status_block_data_e1x));
4729 sb_data_e1x.common.state = SB_DISABLED;
4730 sb_data_e1x.common.p_func.vf_valid = FALSE;
4731 sb_data_p = (uint32_t *) & sb_data_e1x;
4732 data_size = (sizeof(struct hc_status_block_data_e1x) /
4736 bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4739 (BAR_CSTRORM_INTMEM + CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id)), 0,
4740 CSTORM_STATUS_BLOCK_SIZE);
4741 bnx2x_fill(sc, (BAR_CSTRORM_INTMEM + CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id)),
4742 0, CSTORM_SYNC_BLOCK_SIZE);
4746 bnx2x_wr_sp_sb_data(struct bnx2x_softc *sc,
4747 struct hc_sp_status_block_data *sp_sb_data)
4752 i < (sizeof(struct hc_sp_status_block_data) / sizeof(uint32_t));
4755 (BAR_CSTRORM_INTMEM +
4756 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(SC_FUNC(sc)) +
4757 (i * sizeof(uint32_t))),
4758 *((uint32_t *) sp_sb_data + i));
4762 static void bnx2x_zero_sp_sb(struct bnx2x_softc *sc)
4764 struct hc_sp_status_block_data sp_sb_data;
4766 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4768 sp_sb_data.state = SB_DISABLED;
4769 sp_sb_data.p_func.vf_valid = FALSE;
4771 bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
4774 (BAR_CSTRORM_INTMEM +
4775 CSTORM_SP_STATUS_BLOCK_OFFSET(SC_FUNC(sc))),
4776 0, CSTORM_SP_STATUS_BLOCK_SIZE);
4778 (BAR_CSTRORM_INTMEM +
4779 CSTORM_SP_SYNC_BLOCK_OFFSET(SC_FUNC(sc))),
4780 0, CSTORM_SP_SYNC_BLOCK_SIZE);
4784 bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, int igu_sb_id,
4787 hc_sm->igu_sb_id = igu_sb_id;
4788 hc_sm->igu_seg_id = igu_seg_id;
4789 hc_sm->timer_value = 0xFF;
4790 hc_sm->time_to_expire = 0xFFFFFFFF;
4793 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
4795 /* zero out state machine indices */
4798 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4801 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4802 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
4803 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
4804 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
4809 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
4810 (SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4813 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
4814 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4815 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
4816 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4817 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
4818 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4819 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
4820 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4824 bnx2x_init_sb(struct bnx2x_softc *sc, rte_iova_t busaddr, int vfid,
4825 uint8_t vf_valid, int fw_sb_id, int igu_sb_id)
4827 struct hc_status_block_data_e2 sb_data_e2;
4828 struct hc_status_block_data_e1x sb_data_e1x;
4829 struct hc_status_block_sm *hc_sm_p;
4830 uint32_t *sb_data_p;
4834 if (CHIP_INT_MODE_IS_BC(sc)) {
4835 igu_seg_id = HC_SEG_ACCESS_NORM;
4837 igu_seg_id = IGU_SEG_ACCESS_NORM;
4840 bnx2x_zero_fp_sb(sc, fw_sb_id);
4842 if (!CHIP_IS_E1x(sc)) {
4843 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4844 sb_data_e2.common.state = SB_ENABLED;
4845 sb_data_e2.common.p_func.pf_id = SC_FUNC(sc);
4846 sb_data_e2.common.p_func.vf_id = vfid;
4847 sb_data_e2.common.p_func.vf_valid = vf_valid;
4848 sb_data_e2.common.p_func.vnic_id = SC_VN(sc);
4849 sb_data_e2.common.same_igu_sb_1b = TRUE;
4850 sb_data_e2.common.host_sb_addr.hi = U64_HI(busaddr);
4851 sb_data_e2.common.host_sb_addr.lo = U64_LO(busaddr);
4852 hc_sm_p = sb_data_e2.common.state_machine;
4853 sb_data_p = (uint32_t *) & sb_data_e2;
4854 data_size = (sizeof(struct hc_status_block_data_e2) /
4856 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
4858 memset(&sb_data_e1x, 0,
4859 sizeof(struct hc_status_block_data_e1x));
4860 sb_data_e1x.common.state = SB_ENABLED;
4861 sb_data_e1x.common.p_func.pf_id = SC_FUNC(sc);
4862 sb_data_e1x.common.p_func.vf_id = 0xff;
4863 sb_data_e1x.common.p_func.vf_valid = FALSE;
4864 sb_data_e1x.common.p_func.vnic_id = SC_VN(sc);
4865 sb_data_e1x.common.same_igu_sb_1b = TRUE;
4866 sb_data_e1x.common.host_sb_addr.hi = U64_HI(busaddr);
4867 sb_data_e1x.common.host_sb_addr.lo = U64_LO(busaddr);
4868 hc_sm_p = sb_data_e1x.common.state_machine;
4869 sb_data_p = (uint32_t *) & sb_data_e1x;
4870 data_size = (sizeof(struct hc_status_block_data_e1x) /
4872 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
4875 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], igu_sb_id, igu_seg_id);
4876 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], igu_sb_id, igu_seg_id);
4878 /* write indices to HW - PCI guarantees endianity of regpairs */
4879 bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4882 static uint8_t bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp)
4884 if (CHIP_IS_E1x(fp->sc)) {
4885 return fp->cl_id + SC_PORT(fp->sc) * ETH_MAX_RX_CLIENTS_E1H;
4892 bnx2x_rx_ustorm_prods_offset(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
4894 uint32_t offset = BAR_USTRORM_INTMEM;
4897 return PXP_VF_ADDR_USDM_QUEUES_START +
4898 (sc->acquire_resp.resc.hw_qid[fp->index] *
4899 sizeof(struct ustorm_queue_zone_data));
4900 } else if (!CHIP_IS_E1x(sc)) {
4901 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
4903 offset += USTORM_RX_PRODS_E1X_OFFSET(SC_PORT(sc), fp->cl_id);
4909 static void bnx2x_init_eth_fp(struct bnx2x_softc *sc, int idx)
4911 struct bnx2x_fastpath *fp = &sc->fp[idx];
4912 uint32_t cids[ECORE_MULTI_TX_COS] = { 0 };
4913 unsigned long q_type = 0;
4919 fp->igu_sb_id = (sc->igu_base_sb + idx + CNIC_SUPPORT(sc));
4920 fp->fw_sb_id = (sc->base_fw_ndsb + idx + CNIC_SUPPORT(sc));
4922 if (CHIP_IS_E1x(sc))
4923 fp->cl_id = SC_L_ID(sc) + idx;
4925 /* want client ID same as IGU SB ID for non-E1 */
4926 fp->cl_id = fp->igu_sb_id;
4927 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
4929 /* setup sb indices */
4930 if (!CHIP_IS_E1x(sc)) {
4931 fp->sb_index_values = fp->status_block.e2_sb->sb.index_values;
4932 fp->sb_running_index = fp->status_block.e2_sb->sb.running_index;
4934 fp->sb_index_values = fp->status_block.e1x_sb->sb.index_values;
4935 fp->sb_running_index =
4936 fp->status_block.e1x_sb->sb.running_index;
4940 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(sc, fp);
4942 fp->rx_cq_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS];
4944 for (cos = 0; cos < sc->max_cos; cos++) {
4947 fp->tx_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0];
4949 /* nothing more for a VF to do */
4954 bnx2x_init_sb(sc, fp->sb_dma.paddr, BNX2X_VF_ID_INVALID, FALSE,
4955 fp->fw_sb_id, fp->igu_sb_id);
4957 bnx2x_update_fp_sb_idx(fp);
4959 /* Configure Queue State object */
4960 bnx2x_set_bit(ECORE_Q_TYPE_HAS_RX, &q_type);
4961 bnx2x_set_bit(ECORE_Q_TYPE_HAS_TX, &q_type);
4963 ecore_init_queue_obj(sc,
4964 &sc->sp_objs[idx].q_obj,
4969 BNX2X_SP(sc, q_rdata),
4970 (rte_iova_t)BNX2X_SP_MAPPING(sc, q_rdata),
4973 /* configure classification DBs */
4974 ecore_init_mac_obj(sc,
4975 &sc->sp_objs[idx].mac_obj,
4979 BNX2X_SP(sc, mac_rdata),
4980 (rte_iova_t)BNX2X_SP_MAPPING(sc, mac_rdata),
4981 ECORE_FILTER_MAC_PENDING, &sc->sp_state,
4982 ECORE_OBJ_TYPE_RX_TX, &sc->macs_pool);
4986 bnx2x_update_rx_prod(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
4987 uint16_t rx_bd_prod, uint16_t rx_cq_prod)
4989 union ustorm_eth_rx_producers rx_prods;
4992 /* update producers */
4993 rx_prods.prod.bd_prod = rx_bd_prod;
4994 rx_prods.prod.cqe_prod = rx_cq_prod;
4995 rx_prods.prod.reserved = 0;
4998 * Make sure that the BD and SGE data is updated before updating the
4999 * producers since FW might read the BD/SGE right after the producer
5001 * This is only applicable for weak-ordered memory model archs such
5002 * as IA-64. The following barrier is also mandatory since FW will
5003 * assumes BDs must have buffers.
5007 for (i = 0; i < (sizeof(rx_prods) / 4); i++) {
5009 (fp->ustorm_rx_prods_offset + (i * 4)),
5010 rx_prods.raw_data[i]);
5013 wmb(); /* keep prod updates ordered */
5016 static void bnx2x_init_rx_rings(struct bnx2x_softc *sc)
5018 struct bnx2x_fastpath *fp;
5020 struct bnx2x_rx_queue *rxq;
5022 for (i = 0; i < sc->num_queues; i++) {
5024 rxq = sc->rx_queues[fp->index];
5026 PMD_RX_LOG(ERR, "RX queue is NULL");
5030 rxq->rx_bd_head = 0;
5031 rxq->rx_bd_tail = rxq->nb_rx_desc;
5032 rxq->rx_cq_head = 0;
5033 rxq->rx_cq_tail = TOTAL_RCQ_ENTRIES(rxq);
5034 *fp->rx_cq_cons_sb = 0;
5037 * Activate the BD ring...
5038 * Warning, this will generate an interrupt (to the TSTORM)
5039 * so this can only be done after the chip is initialized
5041 bnx2x_update_rx_prod(sc, fp, rxq->rx_bd_tail, rxq->rx_cq_tail);
5049 static void bnx2x_init_tx_ring_one(struct bnx2x_fastpath *fp)
5051 struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
5053 fp->tx_db.data.header.header = 1 << DOORBELL_HDR_DB_TYPE_SHIFT;
5054 fp->tx_db.data.zero_fill1 = 0;
5055 fp->tx_db.data.prod = 0;
5058 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
5062 txq->tx_pkt_tail = 0;
5063 txq->tx_pkt_head = 0;
5064 txq->tx_bd_tail = 0;
5065 txq->tx_bd_head = 0;
5068 static void bnx2x_init_tx_rings(struct bnx2x_softc *sc)
5072 for (i = 0; i < sc->num_queues; i++) {
5073 bnx2x_init_tx_ring_one(&sc->fp[i]);
5077 static void bnx2x_init_def_sb(struct bnx2x_softc *sc)
5079 struct host_sp_status_block *def_sb = sc->def_sb;
5080 rte_iova_t mapping = sc->def_sb_dma.paddr;
5081 int igu_sp_sb_index;
5083 int port = SC_PORT(sc);
5084 int func = SC_FUNC(sc);
5085 int reg_offset, reg_offset_en5;
5088 struct hc_sp_status_block_data sp_sb_data;
5090 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5092 if (CHIP_INT_MODE_IS_BC(sc)) {
5093 igu_sp_sb_index = DEF_SB_IGU_ID;
5094 igu_seg_id = HC_SEG_ACCESS_DEF;
5096 igu_sp_sb_index = sc->igu_dsb_id;
5097 igu_seg_id = IGU_SEG_ACCESS_DEF;
5101 section = ((uint64_t) mapping +
5102 offsetof(struct host_sp_status_block, atten_status_block));
5103 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5106 reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5107 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
5109 reg_offset_en5 = (port) ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5110 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0;
5112 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5113 /* take care of sig[0]..sig[4] */
5114 for (sindex = 0; sindex < 4; sindex++) {
5115 sc->attn_group[index].sig[sindex] =
5117 (reg_offset + (sindex * 0x4) +
5121 if (!CHIP_IS_E1x(sc)) {
5123 * enable5 is separate from the rest of the registers,
5124 * and the address skip is 4 and not 16 between the
5127 sc->attn_group[index].sig[4] =
5128 REG_RD(sc, (reg_offset_en5 + (0x4 * index)));
5130 sc->attn_group[index].sig[4] = 0;
5134 if (sc->devinfo.int_block == INT_BLOCK_HC) {
5136 port ? HC_REG_ATTN_MSG1_ADDR_L : HC_REG_ATTN_MSG0_ADDR_L;
5137 REG_WR(sc, reg_offset, U64_LO(section));
5138 REG_WR(sc, (reg_offset + 4), U64_HI(section));
5139 } else if (!CHIP_IS_E1x(sc)) {
5140 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5141 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5144 section = ((uint64_t) mapping +
5145 offsetof(struct host_sp_status_block, sp_sb));
5147 bnx2x_zero_sp_sb(sc);
5149 /* PCI guarantees endianity of regpair */
5150 sp_sb_data.state = SB_ENABLED;
5151 sp_sb_data.host_sb_addr.lo = U64_LO(section);
5152 sp_sb_data.host_sb_addr.hi = U64_HI(section);
5153 sp_sb_data.igu_sb_id = igu_sp_sb_index;
5154 sp_sb_data.igu_seg_id = igu_seg_id;
5155 sp_sb_data.p_func.pf_id = func;
5156 sp_sb_data.p_func.vnic_id = SC_VN(sc);
5157 sp_sb_data.p_func.vf_id = 0xff;
5159 bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
5161 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5164 static void bnx2x_init_sp_ring(struct bnx2x_softc *sc)
5166 atomic_store_rel_long(&sc->cq_spq_left, MAX_SPQ_PENDING);
5167 sc->spq_prod_idx = 0;
5169 &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_ETH_DEF_CONS];
5170 sc->spq_prod_bd = sc->spq;
5171 sc->spq_last_bd = (sc->spq_prod_bd + MAX_SP_DESC_CNT);
5174 static void bnx2x_init_eq_ring(struct bnx2x_softc *sc)
5176 union event_ring_elem *elem;
5179 for (i = 1; i <= NUM_EQ_PAGES; i++) {
5180 elem = &sc->eq[EQ_DESC_CNT_PAGE * i - 1];
5182 elem->next_page.addr.hi = htole32(U64_HI(sc->eq_dma.paddr +
5184 (i % NUM_EQ_PAGES)));
5185 elem->next_page.addr.lo = htole32(U64_LO(sc->eq_dma.paddr +
5187 (i % NUM_EQ_PAGES)));
5191 sc->eq_prod = NUM_EQ_DESC;
5192 sc->eq_cons_sb = &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_EQ_CONS];
5194 atomic_store_rel_long(&sc->eq_spq_left,
5195 (min((MAX_SP_DESC_CNT - MAX_SPQ_PENDING),
5199 static void bnx2x_init_internal_common(struct bnx2x_softc *sc)
5205 * In switch independent mode, the TSTORM needs to accept
5206 * packets that failed classification, since approximate match
5207 * mac addresses aren't written to NIG LLH.
5210 (BAR_TSTRORM_INTMEM +
5211 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 2);
5214 (BAR_TSTRORM_INTMEM +
5215 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 0);
5218 * Zero this manually as its initialization is currently missing
5221 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) {
5223 (BAR_USTRORM_INTMEM + USTORM_AGG_DATA_OFFSET + (i * 4)),
5227 if (!CHIP_IS_E1x(sc)) {
5228 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET),
5229 CHIP_INT_MODE_IS_BC(sc) ? HC_IGU_BC_MODE :
5234 static void bnx2x_init_internal(struct bnx2x_softc *sc, uint32_t load_code)
5236 switch (load_code) {
5237 case FW_MSG_CODE_DRV_LOAD_COMMON:
5238 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5239 bnx2x_init_internal_common(sc);
5242 case FW_MSG_CODE_DRV_LOAD_PORT:
5246 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5247 /* internal memory per function is initialized inside bnx2x_pf_init */
5251 PMD_DRV_LOG(NOTICE, sc, "Unknown load_code (0x%x) from MCP",
5258 storm_memset_func_cfg(struct bnx2x_softc *sc,
5259 struct tstorm_eth_function_common_config *tcfg,
5265 addr = (BAR_TSTRORM_INTMEM +
5266 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid));
5267 size = sizeof(struct tstorm_eth_function_common_config);
5268 ecore_storm_memset_struct(sc, addr, size, (uint32_t *) tcfg);
5271 static void bnx2x_func_init(struct bnx2x_softc *sc, struct bnx2x_func_init_params *p)
5273 struct tstorm_eth_function_common_config tcfg = { 0 };
5275 if (CHIP_IS_E1x(sc)) {
5276 storm_memset_func_cfg(sc, &tcfg, p->func_id);
5279 /* Enable the function in the FW */
5280 storm_memset_vf_to_pf(sc, p->func_id, p->pf_id);
5281 storm_memset_func_en(sc, p->func_id, 1);
5284 if (p->func_flgs & FUNC_FLG_SPQ) {
5285 storm_memset_spq_addr(sc, p->spq_map, p->func_id);
5287 (XSEM_REG_FAST_MEMORY +
5288 XSTORM_SPQ_PROD_OFFSET(p->func_id)), p->spq_prod);
5293 * Calculates the sum of vn_min_rates.
5294 * It's needed for further normalizing of the min_rates.
5296 * sum of vn_min_rates.
5298 * 0 - if all the min_rates are 0.
5299 * In the later case fainess algorithm should be deactivated.
5300 * If all min rates are not zero then those that are zeroes will be set to 1.
5302 static void bnx2x_calc_vn_min(struct bnx2x_softc *sc, struct cmng_init_input *input)
5305 uint32_t vn_min_rate;
5309 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5310 vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5311 vn_min_rate = (((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
5312 FUNC_MF_CFG_MIN_BW_SHIFT) * 100);
5314 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5315 /* skip hidden VNs */
5317 } else if (!vn_min_rate) {
5318 /* If min rate is zero - set it to 100 */
5319 vn_min_rate = DEF_MIN_RATE;
5324 input->vnic_min_rate[vn] = vn_min_rate;
5327 /* if ETS or all min rates are zeros - disable fairness */
5329 input->flags.cmng_enables &= ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5331 input->flags.cmng_enables |= CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5336 bnx2x_extract_max_cfg(__rte_unused struct bnx2x_softc *sc, uint32_t mf_cfg)
5338 uint16_t max_cfg = ((mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
5339 FUNC_MF_CFG_MAX_BW_SHIFT);
5342 PMD_DRV_LOG(DEBUG, sc,
5343 "Max BW configured to 0 - using 100 instead");
5351 bnx2x_calc_vn_max(struct bnx2x_softc *sc, int vn, struct cmng_init_input *input)
5353 uint16_t vn_max_rate;
5354 uint32_t vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5357 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5360 max_cfg = bnx2x_extract_max_cfg(sc, vn_cfg);
5363 /* max_cfg in percents of linkspeed */
5365 ((sc->link_vars.line_speed * max_cfg) / 100);
5366 } else { /* SD modes */
5367 /* max_cfg is absolute in 100Mb units */
5368 vn_max_rate = (max_cfg * 100);
5372 input->vnic_max_rate[vn] = vn_max_rate;
5376 bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg, uint8_t cmng_type)
5378 struct cmng_init_input input;
5381 memset(&input, 0, sizeof(struct cmng_init_input));
5383 input.port_rate = sc->link_vars.line_speed;
5385 if (cmng_type == CMNG_FNS_MINMAX) {
5386 /* read mf conf from shmem */
5388 bnx2x_read_mf_cfg(sc);
5391 /* get VN min rate and enable fairness if not 0 */
5392 bnx2x_calc_vn_min(sc, &input);
5394 /* get VN max rate */
5396 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5397 bnx2x_calc_vn_max(sc, vn, &input);
5401 /* always enable rate shaping and fairness */
5402 input.flags.cmng_enables |= CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
5404 ecore_init_cmng(&input, &sc->cmng);
5409 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc)
5411 if (CHIP_REV_IS_SLOW(sc)) {
5412 return CMNG_FNS_NONE;
5416 return CMNG_FNS_MINMAX;
5419 return CMNG_FNS_NONE;
5423 storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng, uint8_t port)
5430 addr = (BAR_XSTRORM_INTMEM + XSTORM_CMNG_PER_PORT_VARS_OFFSET(port));
5431 size = sizeof(struct cmng_struct_per_port);
5432 ecore_storm_memset_struct(sc, addr, size, (uint32_t *) & cmng->port);
5434 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5435 func = func_by_vn(sc, vn);
5437 addr = (BAR_XSTRORM_INTMEM +
5438 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func));
5439 size = sizeof(struct rate_shaping_vars_per_vn);
5440 ecore_storm_memset_struct(sc, addr, size,
5441 (uint32_t *) & cmng->
5442 vnic.vnic_max_rate[vn]);
5444 addr = (BAR_XSTRORM_INTMEM +
5445 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func));
5446 size = sizeof(struct fairness_vars_per_vn);
5447 ecore_storm_memset_struct(sc, addr, size,
5448 (uint32_t *) & cmng->
5449 vnic.vnic_min_rate[vn]);
5453 static void bnx2x_pf_init(struct bnx2x_softc *sc)
5455 struct bnx2x_func_init_params func_init;
5456 struct event_ring_data eq_data;
5459 memset(&eq_data, 0, sizeof(struct event_ring_data));
5460 memset(&func_init, 0, sizeof(struct bnx2x_func_init_params));
5462 if (!CHIP_IS_E1x(sc)) {
5463 /* reset IGU PF statistics: MSIX + ATTN */
5466 (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5467 (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5468 ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5472 (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5473 (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5474 (BNX2X_IGU_STAS_MSG_PF_CNT * 4) +
5475 ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5479 /* function setup flags */
5480 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
5482 func_init.func_flgs = flags;
5483 func_init.pf_id = SC_FUNC(sc);
5484 func_init.func_id = SC_FUNC(sc);
5485 func_init.spq_map = sc->spq_dma.paddr;
5486 func_init.spq_prod = sc->spq_prod_idx;
5488 bnx2x_func_init(sc, &func_init);
5490 memset(&sc->cmng, 0, sizeof(struct cmng_struct_per_port));
5493 * Congestion management values depend on the link rate.
5494 * There is no active link so initial link rate is set to 10Gbps.
5495 * When the link comes up the congestion management values are
5496 * re-calculated according to the actual link rate.
5498 sc->link_vars.line_speed = SPEED_10000;
5499 bnx2x_cmng_fns_init(sc, TRUE, bnx2x_get_cmng_fns_mode(sc));
5501 /* Only the PMF sets the HW */
5503 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
5506 /* init Event Queue - PCI bus guarantees correct endainity */
5507 eq_data.base_addr.hi = U64_HI(sc->eq_dma.paddr);
5508 eq_data.base_addr.lo = U64_LO(sc->eq_dma.paddr);
5509 eq_data.producer = sc->eq_prod;
5510 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
5511 eq_data.sb_id = DEF_SB_ID;
5512 storm_memset_eq_data(sc, &eq_data, SC_FUNC(sc));
5515 static void bnx2x_hc_int_enable(struct bnx2x_softc *sc)
5517 int port = SC_PORT(sc);
5518 uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5519 uint32_t val = REG_RD(sc, addr);
5520 uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5521 || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5522 uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5523 uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5526 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5527 HC_CONFIG_0_REG_INT_LINE_EN_0);
5528 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5529 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5531 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
5534 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
5535 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5536 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5537 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5539 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5540 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5541 HC_CONFIG_0_REG_INT_LINE_EN_0 |
5542 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5544 REG_WR(sc, addr, val);
5546 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
5549 REG_WR(sc, addr, val);
5551 /* ensure that HC_CONFIG is written before leading/trailing edge config */
5554 /* init leading/trailing edge */
5556 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5558 /* enable nig and gpio3 attention */
5565 REG_WR(sc, (HC_REG_TRAILING_EDGE_0 + port * 8), val);
5566 REG_WR(sc, (HC_REG_LEADING_EDGE_0 + port * 8), val);
5568 /* make sure that interrupts are indeed enabled from here on */
5572 static void bnx2x_igu_int_enable(struct bnx2x_softc *sc)
5575 uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5576 || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5577 uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5578 uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5580 val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5583 val &= ~(IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5584 val |= (IGU_PF_CONF_MSI_MSIX_EN | IGU_PF_CONF_ATTN_BIT_EN);
5586 val |= IGU_PF_CONF_SINGLE_ISR_EN;
5589 val &= ~IGU_PF_CONF_INT_LINE_EN;
5590 val |= (IGU_PF_CONF_MSI_MSIX_EN |
5591 IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5593 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
5594 val |= (IGU_PF_CONF_INT_LINE_EN |
5595 IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5598 /* clean previous status - need to configure igu prior to ack */
5599 if ((!msix) || single_msix) {
5600 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5604 val |= IGU_PF_CONF_FUNC_EN;
5606 PMD_DRV_LOG(DEBUG, sc, "write 0x%x to IGU mode %s",
5607 val, ((msix) ? "MSI-X" : ((msi) ? "MSI" : "INTx")));
5609 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5613 /* init leading/trailing edge */
5615 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5617 /* enable nig and gpio3 attention */
5624 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
5625 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
5627 /* make sure that interrupts are indeed enabled from here on */
5631 static void bnx2x_int_enable(struct bnx2x_softc *sc)
5633 if (sc->devinfo.int_block == INT_BLOCK_HC) {
5634 bnx2x_hc_int_enable(sc);
5636 bnx2x_igu_int_enable(sc);
5640 static void bnx2x_hc_int_disable(struct bnx2x_softc *sc)
5642 int port = SC_PORT(sc);
5643 uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5644 uint32_t val = REG_RD(sc, addr);
5646 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5647 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5648 HC_CONFIG_0_REG_INT_LINE_EN_0 | HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5649 /* flush all outstanding writes */
5652 REG_WR(sc, addr, val);
5653 if (REG_RD(sc, addr) != val) {
5654 PMD_DRV_LOG(ERR, sc, "proper val not read from HC IGU!");
5658 static void bnx2x_igu_int_disable(struct bnx2x_softc *sc)
5660 uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5662 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
5663 IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_ATTN_BIT_EN);
5665 PMD_DRV_LOG(DEBUG, sc, "write %x to IGU", val);
5667 /* flush all outstanding writes */
5670 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5671 if (REG_RD(sc, IGU_REG_PF_CONFIGURATION) != val) {
5672 PMD_DRV_LOG(ERR, sc, "proper val not read from IGU!");
5676 static void bnx2x_int_disable(struct bnx2x_softc *sc)
5678 if (sc->devinfo.int_block == INT_BLOCK_HC) {
5679 bnx2x_hc_int_disable(sc);
5681 bnx2x_igu_int_disable(sc);
5685 static void bnx2x_nic_init(struct bnx2x_softc *sc, int load_code)
5689 PMD_INIT_FUNC_TRACE(sc);
5691 for (i = 0; i < sc->num_queues; i++) {
5692 bnx2x_init_eth_fp(sc, i);
5695 rmb(); /* ensure status block indices were read */
5697 bnx2x_init_rx_rings(sc);
5698 bnx2x_init_tx_rings(sc);
5701 bnx2x_memset_stats(sc);
5705 /* initialize MOD_ABS interrupts */
5706 elink_init_mod_abs_int(sc, &sc->link_vars,
5707 sc->devinfo.chip_id,
5708 sc->devinfo.shmem_base,
5709 sc->devinfo.shmem2_base, SC_PORT(sc));
5711 bnx2x_init_def_sb(sc);
5712 bnx2x_update_dsb_idx(sc);
5713 bnx2x_init_sp_ring(sc);
5714 bnx2x_init_eq_ring(sc);
5715 bnx2x_init_internal(sc, load_code);
5717 bnx2x_stats_init(sc);
5719 /* flush all before enabling interrupts */
5722 bnx2x_int_enable(sc);
5724 /* check for SPIO5 */
5725 bnx2x_attn_int_deasserted0(sc,
5727 (MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
5729 AEU_INPUTS_ATTN_BITS_SPIO5);
5732 static void bnx2x_init_objs(struct bnx2x_softc *sc)
5734 /* mcast rules must be added to tx if tx switching is enabled */
5735 ecore_obj_type o_type;
5736 if (sc->flags & BNX2X_TX_SWITCHING)
5737 o_type = ECORE_OBJ_TYPE_RX_TX;
5739 o_type = ECORE_OBJ_TYPE_RX;
5741 /* RX_MODE controlling object */
5742 ecore_init_rx_mode_obj(sc, &sc->rx_mode_obj);
5744 /* multicast configuration controlling object */
5745 ecore_init_mcast_obj(sc,
5751 BNX2X_SP(sc, mcast_rdata),
5752 (rte_iova_t)BNX2X_SP_MAPPING(sc, mcast_rdata),
5753 ECORE_FILTER_MCAST_PENDING,
5754 &sc->sp_state, o_type);
5756 /* Setup CAM credit pools */
5757 ecore_init_mac_credit_pool(sc,
5760 CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5761 VNICS_PER_PATH(sc));
5763 ecore_init_vlan_credit_pool(sc,
5765 SC_ABS_FUNC(sc) >> 1,
5766 CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5767 VNICS_PER_PATH(sc));
5769 /* RSS configuration object */
5770 ecore_init_rss_config_obj(&sc->rss_conf_obj,
5775 BNX2X_SP(sc, rss_rdata),
5776 (rte_iova_t)BNX2X_SP_MAPPING(sc, rss_rdata),
5777 ECORE_FILTER_RSS_CONF_PENDING,
5778 &sc->sp_state, ECORE_OBJ_TYPE_RX);
5782 * Initialize the function. This must be called before sending CLIENT_SETUP
5783 * for the first client.
5785 static int bnx2x_func_start(struct bnx2x_softc *sc)
5787 struct ecore_func_state_params func_params = { NULL };
5788 struct ecore_func_start_params *start_params =
5789 &func_params.params.start;
5791 /* Prepare parameters for function state transitions */
5792 bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
5794 func_params.f_obj = &sc->func_obj;
5795 func_params.cmd = ECORE_F_CMD_START;
5797 /* Function parameters */
5798 start_params->mf_mode = sc->devinfo.mf_info.mf_mode;
5799 start_params->sd_vlan_tag = OVLAN(sc);
5801 if (CHIP_IS_E2(sc) || CHIP_IS_E3(sc)) {
5802 start_params->network_cos_mode = STATIC_COS;
5803 } else { /* CHIP_IS_E1X */
5804 start_params->network_cos_mode = FW_WRR;
5807 start_params->gre_tunnel_mode = 0;
5808 start_params->gre_tunnel_rss = 0;
5810 return ecore_func_state_change(sc, &func_params);
5813 static int bnx2x_set_power_state(struct bnx2x_softc *sc, uint8_t state)
5817 /* If there is no power capability, silently succeed */
5818 if (!(sc->devinfo.pcie_cap_flags & BNX2X_PM_CAPABLE_FLAG)) {
5819 PMD_DRV_LOG(INFO, sc, "No power capability");
5823 pci_read(sc, (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS), &pmcsr,
5829 (sc->devinfo.pcie_pm_cap_reg +
5831 ((pmcsr & ~PCIM_PSTAT_DMASK) | PCIM_PSTAT_PME));
5833 if (pmcsr & PCIM_PSTAT_DMASK) {
5834 /* delay required during transition out of D3hot */
5841 /* don't shut down the power for emulation and FPGA */
5842 if (CHIP_REV_IS_SLOW(sc)) {
5846 pmcsr &= ~PCIM_PSTAT_DMASK;
5847 pmcsr |= PCIM_PSTAT_D3;
5850 pmcsr |= PCIM_PSTAT_PMEENABLE;
5854 (sc->devinfo.pcie_pm_cap_reg +
5855 PCIR_POWER_STATUS), pmcsr);
5858 * No more memory access after this point until device is brought back
5864 PMD_DRV_LOG(NOTICE, sc, "Can't support PCI power state = %d",
5872 /* return true if succeeded to acquire the lock */
5873 static uint8_t bnx2x_trylock_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
5875 uint32_t lock_status;
5876 uint32_t resource_bit = (1 << resource);
5877 int func = SC_FUNC(sc);
5878 uint32_t hw_lock_control_reg;
5880 /* Validating that the resource is within range */
5881 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
5882 PMD_DRV_LOG(INFO, sc,
5883 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)",
5884 resource, HW_LOCK_MAX_RESOURCE_VALUE);
5889 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func * 8);
5891 hw_lock_control_reg =
5892 (MISC_REG_DRIVER_CONTROL_7 + (func - 6) * 8);
5895 /* try to acquire the lock */
5896 REG_WR(sc, hw_lock_control_reg + 4, resource_bit);
5897 lock_status = REG_RD(sc, hw_lock_control_reg);
5898 if (lock_status & resource_bit) {
5902 PMD_DRV_LOG(NOTICE, sc, "Failed to get a resource lock 0x%x", resource);
5908 * Get the recovery leader resource id according to the engine this function
5909 * belongs to. Currently only only 2 engines is supported.
5911 static int bnx2x_get_leader_lock_resource(struct bnx2x_softc *sc)
5914 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
5916 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
5920 /* try to acquire a leader lock for current engine */
5921 static uint8_t bnx2x_trylock_leader_lock(struct bnx2x_softc *sc)
5923 return bnx2x_trylock_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5926 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc)
5928 return bnx2x_release_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5931 /* close gates #2, #3 and #4 */
5932 static void bnx2x_set_234_gates(struct bnx2x_softc *sc, uint8_t close)
5936 /* gates #2 and #4a are closed/opened */
5938 REG_WR(sc, PXP_REG_HST_DISCARD_DOORBELLS, ! !close);
5940 REG_WR(sc, PXP_REG_HST_DISCARD_INTERNAL_WRITES, ! !close);
5943 if (CHIP_IS_E1x(sc)) {
5944 /* prevent interrupts from HC on both ports */
5945 val = REG_RD(sc, HC_REG_CONFIG_1);
5947 REG_WR(sc, HC_REG_CONFIG_1, (val & ~(uint32_t)
5948 HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5950 REG_WR(sc, HC_REG_CONFIG_1,
5951 (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5953 val = REG_RD(sc, HC_REG_CONFIG_0);
5955 REG_WR(sc, HC_REG_CONFIG_0, (val & ~(uint32_t)
5956 HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5958 REG_WR(sc, HC_REG_CONFIG_0,
5959 (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5962 /* Prevent incoming interrupts in IGU */
5963 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
5966 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5968 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5970 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5972 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5978 /* poll for pending writes bit, it should get cleared in no more than 1s */
5979 static int bnx2x_er_poll_igu_vq(struct bnx2x_softc *sc)
5981 uint32_t cnt = 1000;
5982 uint32_t pend_bits = 0;
5985 pend_bits = REG_RD(sc, IGU_REG_PENDING_BITS_STATUS);
5987 if (pend_bits == 0) {
5992 } while (cnt-- > 0);
5995 PMD_DRV_LOG(NOTICE, sc, "Still pending IGU requests bits=0x%08x!",
6003 #define SHARED_MF_CLP_MAGIC 0x80000000 /* 'magic' bit */
6005 static void bnx2x_clp_reset_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
6007 /* Do some magic... */
6008 uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
6009 *magic_val = val & SHARED_MF_CLP_MAGIC;
6010 MFCFG_WR(sc, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
6013 /* restore the value of the 'magic' bit */
6014 static void bnx2x_clp_reset_done(struct bnx2x_softc *sc, uint32_t magic_val)
6016 /* Restore the 'magic' bit value... */
6017 uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
6018 MFCFG_WR(sc, shared_mf_config.clp_mb,
6019 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
6022 /* prepare for MCP reset, takes care of CLP configurations */
6023 static void bnx2x_reset_mcp_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
6026 uint32_t validity_offset;
6028 /* set `magic' bit in order to save MF config */
6029 bnx2x_clp_reset_prep(sc, magic_val);
6031 /* get shmem offset */
6032 shmem = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
6034 offsetof(struct shmem_region, validity_map[SC_PORT(sc)]);
6036 /* Clear validity map flags */
6038 REG_WR(sc, shmem + validity_offset, 0);
6042 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
6043 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
6045 static void bnx2x_mcp_wait_one(struct bnx2x_softc *sc)
6047 /* special handling for emulation and FPGA (10 times longer) */
6048 if (CHIP_REV_IS_SLOW(sc)) {
6049 DELAY((MCP_ONE_TIMEOUT * 10) * 1000);
6051 DELAY((MCP_ONE_TIMEOUT) * 1000);
6055 /* initialize shmem_base and waits for validity signature to appear */
6056 static int bnx2x_init_shmem(struct bnx2x_softc *sc)
6062 sc->devinfo.shmem_base =
6063 sc->link_params.shmem_base =
6064 REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
6066 if (sc->devinfo.shmem_base) {
6067 val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
6068 if (val & SHR_MEM_VALIDITY_MB)
6072 bnx2x_mcp_wait_one(sc);
6074 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
6076 PMD_DRV_LOG(NOTICE, sc, "BAD MCP validity signature");
6081 static int bnx2x_reset_mcp_comp(struct bnx2x_softc *sc, uint32_t magic_val)
6083 int rc = bnx2x_init_shmem(sc);
6085 /* Restore the `magic' bit value */
6086 bnx2x_clp_reset_done(sc, magic_val);
6091 static void bnx2x_pxp_prep(struct bnx2x_softc *sc)
6093 REG_WR(sc, PXP2_REG_RD_START_INIT, 0);
6094 REG_WR(sc, PXP2_REG_RQ_RBC_DONE, 0);
6099 * Reset the whole chip except for:
6101 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by one reset bit)
6103 * - MISC (including AEU)
6107 static void bnx2x_process_kill_chip_reset(struct bnx2x_softc *sc, uint8_t global)
6109 uint32_t not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
6110 uint32_t global_bits2, stay_reset2;
6113 * Bits that have to be set in reset_mask2 if we want to reset 'global'
6114 * (per chip) blocks.
6117 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
6118 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
6121 * Don't reset the following blocks.
6122 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
6123 * reset, as in 4 port device they might still be owned
6124 * by the MCP (there is only one leader per path).
6127 MISC_REGISTERS_RESET_REG_1_RST_HC |
6128 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
6129 MISC_REGISTERS_RESET_REG_1_RST_PXP;
6132 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
6133 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
6134 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
6135 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
6136 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
6137 MISC_REGISTERS_RESET_REG_2_RST_GRC |
6138 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
6139 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
6140 MISC_REGISTERS_RESET_REG_2_RST_ATC |
6141 MISC_REGISTERS_RESET_REG_2_PGLC |
6142 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
6143 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
6144 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
6145 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
6146 MISC_REGISTERS_RESET_REG_2_UMAC0 | MISC_REGISTERS_RESET_REG_2_UMAC1;
6149 * Keep the following blocks in reset:
6150 * - all xxMACs are handled by the elink code.
6153 MISC_REGISTERS_RESET_REG_2_XMAC |
6154 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
6156 /* Full reset masks according to the chip */
6157 reset_mask1 = 0xffffffff;
6159 if (CHIP_IS_E1H(sc))
6160 reset_mask2 = 0x1ffff;
6161 else if (CHIP_IS_E2(sc))
6162 reset_mask2 = 0xfffff;
6163 else /* CHIP_IS_E3 */
6164 reset_mask2 = 0x3ffffff;
6166 /* Don't reset global blocks unless we need to */
6168 reset_mask2 &= ~global_bits2;
6171 * In case of attention in the QM, we need to reset PXP
6172 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
6173 * because otherwise QM reset would release 'close the gates' shortly
6174 * before resetting the PXP, then the PSWRQ would send a write
6175 * request to PGLUE. Then when PXP is reset, PGLUE would try to
6176 * read the payload data from PSWWR, but PSWWR would not
6177 * respond. The write queue in PGLUE would stuck, dmae commands
6178 * would not return. Therefore it's important to reset the second
6179 * reset register (containing the
6180 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
6181 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
6184 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
6185 reset_mask2 & (~not_reset_mask2));
6187 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6188 reset_mask1 & (~not_reset_mask1));
6193 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
6194 reset_mask2 & (~stay_reset2));
6199 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
6203 static int bnx2x_process_kill(struct bnx2x_softc *sc, uint8_t global)
6207 uint32_t sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
6208 uint32_t tags_63_32 = 0;
6210 /* Empty the Tetris buffer, wait for 1s */
6212 sr_cnt = REG_RD(sc, PXP2_REG_RD_SR_CNT);
6213 blk_cnt = REG_RD(sc, PXP2_REG_RD_BLK_CNT);
6214 port_is_idle_0 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_0);
6215 port_is_idle_1 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_1);
6216 pgl_exp_rom2 = REG_RD(sc, PXP2_REG_PGL_EXP_ROM2);
6217 if (CHIP_IS_E3(sc)) {
6218 tags_63_32 = REG_RD(sc, PGLUE_B_REG_TAGS_63_32);
6221 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
6222 ((port_is_idle_0 & 0x1) == 0x1) &&
6223 ((port_is_idle_1 & 0x1) == 0x1) &&
6224 (pgl_exp_rom2 == 0xffffffff) &&
6225 (!CHIP_IS_E3(sc) || (tags_63_32 == 0xffffffff)))
6228 } while (cnt-- > 0);
6231 PMD_DRV_LOG(NOTICE, sc,
6232 "ERROR: Tetris buffer didn't get empty or there "
6233 "are still outstanding read requests after 1s! "
6234 "sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, "
6235 "port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x",
6236 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
6243 /* Close gates #2, #3 and #4 */
6244 bnx2x_set_234_gates(sc, TRUE);
6246 /* Poll for IGU VQs for 57712 and newer chips */
6247 if (!CHIP_IS_E1x(sc) && bnx2x_er_poll_igu_vq(sc)) {
6251 /* clear "unprepared" bit */
6252 REG_WR(sc, MISC_REG_UNPREPARED, 0);
6255 /* Make sure all is written to the chip before the reset */
6259 * Wait for 1ms to empty GLUE and PCI-E core queues,
6260 * PSWHST, GRC and PSWRD Tetris buffer.
6264 /* Prepare to chip reset: */
6267 bnx2x_reset_mcp_prep(sc, &val);
6274 /* reset the chip */
6275 bnx2x_process_kill_chip_reset(sc, global);
6278 /* Recover after reset: */
6280 if (global && bnx2x_reset_mcp_comp(sc, val)) {
6284 /* Open the gates #2, #3 and #4 */
6285 bnx2x_set_234_gates(sc, FALSE);
6290 static int bnx2x_leader_reset(struct bnx2x_softc *sc)
6293 uint8_t global = bnx2x_reset_is_global(sc);
6297 * If not going to reset MCP, load "fake" driver to reset HW while
6298 * driver is owner of the HW.
6300 if (!global && !BNX2X_NOMCP(sc)) {
6301 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
6302 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
6304 PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
6306 goto exit_leader_reset;
6309 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
6310 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
6311 PMD_DRV_LOG(NOTICE, sc,
6312 "MCP unexpected response, aborting");
6314 goto exit_leader_reset2;
6317 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
6319 PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
6321 goto exit_leader_reset2;
6325 /* try to recover after the failure */
6326 if (bnx2x_process_kill(sc, global)) {
6327 PMD_DRV_LOG(NOTICE, sc, "Something bad occurred on engine %d!",
6330 goto exit_leader_reset2;
6334 * Clear the RESET_IN_PROGRESS and RESET_GLOBAL bits and update the driver
6337 bnx2x_set_reset_done(sc);
6339 bnx2x_clear_reset_global(sc);
6344 /* unload "fake driver" if it was loaded */
6345 if (!global &&!BNX2X_NOMCP(sc)) {
6346 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
6347 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
6353 bnx2x_release_leader_lock(sc);
6360 * prepare INIT transition, parameters configured:
6361 * - HC configuration
6362 * - Queue's CDU context
6365 bnx2x_pf_q_prep_init(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6366 struct ecore_queue_init_params *init_params)
6369 int cxt_index, cxt_offset;
6371 bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->rx.flags);
6372 bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->tx.flags);
6374 bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->rx.flags);
6375 bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->tx.flags);
6378 init_params->rx.hc_rate =
6379 sc->hc_rx_ticks ? (1000000 / sc->hc_rx_ticks) : 0;
6380 init_params->tx.hc_rate =
6381 sc->hc_tx_ticks ? (1000000 / sc->hc_tx_ticks) : 0;
6384 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = fp->fw_sb_id;
6386 /* CQ index among the SB indices */
6387 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6388 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
6390 /* set maximum number of COSs supported by this queue */
6391 init_params->max_cos = sc->max_cos;
6393 /* set the context pointers queue object */
6394 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
6395 cxt_index = fp->index / ILT_PAGE_CIDS;
6396 cxt_offset = fp->index - (cxt_index * ILT_PAGE_CIDS);
6397 init_params->cxts[cos] =
6398 &sc->context[cxt_index].vcxt[cxt_offset].eth;
6402 /* set flags that are common for the Tx-only and not normal connections */
6403 static unsigned long
6404 bnx2x_get_common_flags(struct bnx2x_softc *sc, uint8_t zero_stats)
6406 unsigned long flags = 0;
6408 /* PF driver will always initialize the Queue to an ACTIVE state */
6409 bnx2x_set_bit(ECORE_Q_FLG_ACTIVE, &flags);
6412 * tx only connections collect statistics (on the same index as the
6413 * parent connection). The statistics are zeroed when the parent
6414 * connection is initialized.
6417 bnx2x_set_bit(ECORE_Q_FLG_STATS, &flags);
6419 bnx2x_set_bit(ECORE_Q_FLG_ZERO_STATS, &flags);
6423 * tx only connections can support tx-switching, though their
6424 * CoS-ness doesn't survive the loopback
6426 if (sc->flags & BNX2X_TX_SWITCHING) {
6427 bnx2x_set_bit(ECORE_Q_FLG_TX_SWITCH, &flags);
6430 bnx2x_set_bit(ECORE_Q_FLG_PCSUM_ON_PKT, &flags);
6435 static unsigned long bnx2x_get_q_flags(struct bnx2x_softc *sc, uint8_t leading)
6437 unsigned long flags = 0;
6440 bnx2x_set_bit(ECORE_Q_FLG_OV, &flags);
6444 bnx2x_set_bit(ECORE_Q_FLG_LEADING_RSS, &flags);
6445 bnx2x_set_bit(ECORE_Q_FLG_MCAST, &flags);
6448 bnx2x_set_bit(ECORE_Q_FLG_VLAN, &flags);
6450 /* merge with common flags */
6451 return flags | bnx2x_get_common_flags(sc, TRUE);
6455 bnx2x_pf_q_prep_general(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6456 struct ecore_general_setup_params *gen_init, uint8_t cos)
6458 gen_init->stat_id = bnx2x_stats_id(fp);
6459 gen_init->spcl_id = fp->cl_id;
6460 gen_init->mtu = sc->mtu;
6461 gen_init->cos = cos;
6465 bnx2x_pf_rx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6466 struct rxq_pause_params *pause,
6467 struct ecore_rxq_setup_params *rxq_init)
6469 struct bnx2x_rx_queue *rxq;
6471 rxq = sc->rx_queues[fp->index];
6473 PMD_RX_LOG(ERR, "RX queue is NULL");
6477 pause->bd_th_lo = BD_TH_LO(sc);
6478 pause->bd_th_hi = BD_TH_HI(sc);
6480 pause->rcq_th_lo = RCQ_TH_LO(sc);
6481 pause->rcq_th_hi = RCQ_TH_HI(sc);
6483 /* validate rings have enough entries to cross high thresholds */
6484 if (sc->dropless_fc &&
6485 pause->bd_th_hi + FW_PREFETCH_CNT > sc->rx_ring_size) {
6486 PMD_DRV_LOG(WARNING, sc, "rx bd ring threshold limit");
6489 if (sc->dropless_fc &&
6490 pause->rcq_th_hi + FW_PREFETCH_CNT > USABLE_RCQ_ENTRIES(rxq)) {
6491 PMD_DRV_LOG(WARNING, sc, "rcq ring threshold limit");
6497 rxq_init->dscr_map = (rte_iova_t)rxq->rx_ring_phys_addr;
6498 rxq_init->rcq_map = (rte_iova_t)rxq->cq_ring_phys_addr;
6499 rxq_init->rcq_np_map = (rte_iova_t)(rxq->cq_ring_phys_addr +
6503 * This should be a maximum number of data bytes that may be
6504 * placed on the BD (not including paddings).
6506 rxq_init->buf_sz = (fp->rx_buf_size - IP_HEADER_ALIGNMENT_PADDING);
6508 rxq_init->cl_qzone_id = fp->cl_qzone_id;
6509 rxq_init->rss_engine_id = SC_FUNC(sc);
6510 rxq_init->mcast_engine_id = SC_FUNC(sc);
6512 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
6513 rxq_init->fw_sb_id = fp->fw_sb_id;
6515 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6518 * configure silent vlan removal
6519 * if multi function mode is afex, then mask default vlan
6521 if (IS_MF_AFEX(sc)) {
6522 rxq_init->silent_removal_value =
6523 sc->devinfo.mf_info.afex_def_vlan_tag;
6524 rxq_init->silent_removal_mask = EVL_VLID_MASK;
6529 bnx2x_pf_tx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6530 struct ecore_txq_setup_params *txq_init, uint8_t cos)
6532 struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
6535 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
6538 txq_init->dscr_map = (rte_iova_t)txq->tx_ring_phys_addr;
6539 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
6540 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
6541 txq_init->fw_sb_id = fp->fw_sb_id;
6544 * set the TSS leading client id for TX classfication to the
6545 * leading RSS client id
6547 txq_init->tss_leading_cl_id = BNX2X_FP(sc, 0, cl_id);
6551 * This function performs 2 steps in a queue state machine:
6556 bnx2x_setup_queue(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp, uint8_t leading)
6558 struct ecore_queue_state_params q_params = { NULL };
6559 struct ecore_queue_setup_params *setup_params = &q_params.params.setup;
6562 PMD_DRV_LOG(DEBUG, sc, "setting up queue %d", fp->index);
6564 bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6566 q_params.q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
6568 /* we want to wait for completion in this context */
6569 bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
6571 /* prepare the INIT parameters */
6572 bnx2x_pf_q_prep_init(sc, fp, &q_params.params.init);
6574 /* Set the command */
6575 q_params.cmd = ECORE_Q_CMD_INIT;
6577 /* Change the state to INIT */
6578 rc = ecore_queue_state_change(sc, &q_params);
6580 PMD_DRV_LOG(NOTICE, sc, "Queue(%d) INIT failed", fp->index);
6584 PMD_DRV_LOG(DEBUG, sc, "init complete");
6586 /* now move the Queue to the SETUP state */
6587 memset(setup_params, 0, sizeof(*setup_params));
6589 /* set Queue flags */
6590 setup_params->flags = bnx2x_get_q_flags(sc, leading);
6592 /* set general SETUP parameters */
6593 bnx2x_pf_q_prep_general(sc, fp, &setup_params->gen_params,
6594 FIRST_TX_COS_INDEX);
6596 bnx2x_pf_rx_q_prep(sc, fp,
6597 &setup_params->pause_params,
6598 &setup_params->rxq_params);
6600 bnx2x_pf_tx_q_prep(sc, fp, &setup_params->txq_params, FIRST_TX_COS_INDEX);
6602 /* Set the command */
6603 q_params.cmd = ECORE_Q_CMD_SETUP;
6605 /* change the state to SETUP */
6606 rc = ecore_queue_state_change(sc, &q_params);
6608 PMD_DRV_LOG(NOTICE, sc, "Queue(%d) SETUP failed", fp->index);
6615 static int bnx2x_setup_leading(struct bnx2x_softc *sc)
6618 return bnx2x_setup_queue(sc, &sc->fp[0], TRUE);
6620 return bnx2x_vf_setup_queue(sc, &sc->fp[0], TRUE);
6624 bnx2x_config_rss_pf(struct bnx2x_softc *sc, struct ecore_rss_config_obj *rss_obj,
6625 uint8_t config_hash)
6627 struct ecore_config_rss_params params = { NULL };
6631 * Although RSS is meaningless when there is a single HW queue we
6632 * still need it enabled in order to have HW Rx hash generated.
6635 params.rss_obj = rss_obj;
6637 bnx2x_set_bit(RAMROD_COMP_WAIT, ¶ms.ramrod_flags);
6639 bnx2x_set_bit(ECORE_RSS_MODE_REGULAR, ¶ms.rss_flags);
6641 /* RSS configuration */
6642 bnx2x_set_bit(ECORE_RSS_IPV4, ¶ms.rss_flags);
6643 bnx2x_set_bit(ECORE_RSS_IPV4_TCP, ¶ms.rss_flags);
6644 bnx2x_set_bit(ECORE_RSS_IPV6, ¶ms.rss_flags);
6645 bnx2x_set_bit(ECORE_RSS_IPV6_TCP, ¶ms.rss_flags);
6646 if (rss_obj->udp_rss_v4) {
6647 bnx2x_set_bit(ECORE_RSS_IPV4_UDP, ¶ms.rss_flags);
6649 if (rss_obj->udp_rss_v6) {
6650 bnx2x_set_bit(ECORE_RSS_IPV6_UDP, ¶ms.rss_flags);
6654 params.rss_result_mask = MULTI_MASK;
6656 rte_memcpy(params.ind_table, rss_obj->ind_table,
6657 sizeof(params.ind_table));
6661 for (i = 0; i < sizeof(params.rss_key) / 4; i++) {
6662 params.rss_key[i] = (uint32_t) rte_rand();
6665 bnx2x_set_bit(ECORE_RSS_SET_SRCH, ¶ms.rss_flags);
6669 return ecore_config_rss(sc, ¶ms);
6671 return bnx2x_vf_config_rss(sc, ¶ms);
6674 static int bnx2x_config_rss_eth(struct bnx2x_softc *sc, uint8_t config_hash)
6676 return bnx2x_config_rss_pf(sc, &sc->rss_conf_obj, config_hash);
6679 static int bnx2x_init_rss_pf(struct bnx2x_softc *sc)
6681 uint8_t num_eth_queues = BNX2X_NUM_ETH_QUEUES(sc);
6685 * Prepare the initial contents of the indirection table if
6688 for (i = 0; i < sizeof(sc->rss_conf_obj.ind_table); i++) {
6689 sc->rss_conf_obj.ind_table[i] =
6690 (sc->fp->cl_id + (i % num_eth_queues));
6694 sc->rss_conf_obj.udp_rss_v4 = sc->rss_conf_obj.udp_rss_v6 = 1;
6698 * For 57711 SEARCHER configuration (rss_keys) is
6699 * per-port, so if explicit configuration is needed, do it only
6702 * For 57712 and newer it's a per-function configuration.
6704 return bnx2x_config_rss_eth(sc, sc->port.pmf || !CHIP_IS_E1x(sc));
6708 bnx2x_set_mac_one(struct bnx2x_softc *sc, uint8_t * mac,
6709 struct ecore_vlan_mac_obj *obj, uint8_t set, int mac_type,
6710 unsigned long *ramrod_flags)
6712 struct ecore_vlan_mac_ramrod_params ramrod_param;
6715 memset(&ramrod_param, 0, sizeof(ramrod_param));
6717 /* fill in general parameters */
6718 ramrod_param.vlan_mac_obj = obj;
6719 ramrod_param.ramrod_flags = *ramrod_flags;
6721 /* fill a user request section if needed */
6722 if (!bnx2x_test_bit(RAMROD_CONT, ramrod_flags)) {
6723 rte_memcpy(ramrod_param.user_req.u.mac.mac, mac,
6726 bnx2x_set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
6728 /* Set the command: ADD or DEL */
6729 ramrod_param.user_req.cmd = (set) ? ECORE_VLAN_MAC_ADD :
6733 rc = ecore_config_vlan_mac(sc, &ramrod_param);
6735 if (rc == ECORE_EXISTS) {
6736 PMD_DRV_LOG(INFO, sc, "Failed to schedule ADD operations (EEXIST)");
6737 /* do not treat adding same MAC as error */
6739 } else if (rc < 0) {
6740 PMD_DRV_LOG(ERR, sc,
6741 "%s MAC failed (%d)", (set ? "Set" : "Delete"), rc);
6747 static int bnx2x_set_eth_mac(struct bnx2x_softc *sc, uint8_t set)
6749 unsigned long ramrod_flags = 0;
6751 PMD_DRV_LOG(DEBUG, sc, "Adding Ethernet MAC");
6753 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
6755 /* Eth MAC is set on RSS leading client (fp[0]) */
6756 return bnx2x_set_mac_one(sc, sc->link_params.mac_addr,
6757 &sc->sp_objs->mac_obj,
6758 set, ECORE_ETH_MAC, &ramrod_flags);
6761 static int bnx2x_get_cur_phy_idx(struct bnx2x_softc *sc)
6763 uint32_t sel_phy_idx = 0;
6765 if (sc->link_params.num_phys <= 1) {
6766 return ELINK_INT_PHY;
6769 if (sc->link_vars.link_up) {
6770 sel_phy_idx = ELINK_EXT_PHY1;
6771 /* In case link is SERDES, check if the ELINK_EXT_PHY2 is the one */
6772 if ((sc->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
6773 (sc->link_params.phy[ELINK_EXT_PHY2].supported &
6774 ELINK_SUPPORTED_FIBRE))
6775 sel_phy_idx = ELINK_EXT_PHY2;
6777 switch (elink_phy_selection(&sc->link_params)) {
6778 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6779 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
6780 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6781 sel_phy_idx = ELINK_EXT_PHY1;
6783 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
6784 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6785 sel_phy_idx = ELINK_EXT_PHY2;
6793 static int bnx2x_get_link_cfg_idx(struct bnx2x_softc *sc)
6795 uint32_t sel_phy_idx = bnx2x_get_cur_phy_idx(sc);
6798 * The selected activated PHY is always after swapping (in case PHY
6799 * swapping is enabled). So when swapping is enabled, we need to reverse
6803 if (sc->link_params.multi_phy_config & PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
6804 if (sel_phy_idx == ELINK_EXT_PHY1)
6805 sel_phy_idx = ELINK_EXT_PHY2;
6806 else if (sel_phy_idx == ELINK_EXT_PHY2)
6807 sel_phy_idx = ELINK_EXT_PHY1;
6810 return ELINK_LINK_CONFIG_IDX(sel_phy_idx);
6813 static void bnx2x_set_requested_fc(struct bnx2x_softc *sc)
6816 * Initialize link parameters structure variables
6817 * It is recommended to turn off RX FC for jumbo frames
6818 * for better performance
6820 if (CHIP_IS_E1x(sc) && (sc->mtu > 5000)) {
6821 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_TX;
6823 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_BOTH;
6827 static void bnx2x_calc_fc_adv(struct bnx2x_softc *sc)
6829 uint8_t cfg_idx = bnx2x_get_link_cfg_idx(sc);
6830 switch (sc->link_vars.ieee_fc &
6831 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
6832 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
6834 sc->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
6838 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
6839 sc->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
6843 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
6844 sc->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
6849 static uint16_t bnx2x_get_mf_speed(struct bnx2x_softc *sc)
6851 uint16_t line_speed = sc->link_vars.line_speed;
6853 uint16_t maxCfg = bnx2x_extract_max_cfg(sc,
6855 mf_info.mf_config[SC_VN
6858 /* calculate the current MAX line speed limit for the MF devices */
6860 line_speed = (line_speed * maxCfg) / 100;
6861 } else { /* SD mode */
6862 uint16_t vn_max_rate = maxCfg * 100;
6864 if (vn_max_rate < line_speed) {
6865 line_speed = vn_max_rate;
6874 bnx2x_fill_report_data(struct bnx2x_softc *sc, struct bnx2x_link_report_data *data)
6876 uint16_t line_speed = bnx2x_get_mf_speed(sc);
6878 memset(data, 0, sizeof(*data));
6880 /* fill the report data with the effective line speed */
6881 data->line_speed = line_speed;
6884 if (!sc->link_vars.link_up || (sc->flags & BNX2X_MF_FUNC_DIS)) {
6885 bnx2x_set_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6886 &data->link_report_flags);
6890 if (sc->link_vars.duplex == DUPLEX_FULL) {
6891 bnx2x_set_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6892 &data->link_report_flags);
6895 /* Rx Flow Control is ON */
6896 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_RX) {
6897 bnx2x_set_bit(BNX2X_LINK_REPORT_RX_FC_ON, &data->link_report_flags);
6900 /* Tx Flow Control is ON */
6901 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
6902 bnx2x_set_bit(BNX2X_LINK_REPORT_TX_FC_ON, &data->link_report_flags);
6906 /* report link status to OS, should be called under phy_lock */
6907 static void bnx2x_link_report_locked(struct bnx2x_softc *sc)
6909 struct bnx2x_link_report_data cur_data;
6913 bnx2x_read_mf_cfg(sc);
6916 /* Read the current link report info */
6917 bnx2x_fill_report_data(sc, &cur_data);
6919 /* Don't report link down or exactly the same link status twice */
6920 if (!memcmp(&cur_data, &sc->last_reported_link, sizeof(cur_data)) ||
6921 (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6922 &sc->last_reported_link.link_report_flags) &&
6923 bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6924 &cur_data.link_report_flags))) {
6928 ELINK_DEBUG_P2(sc, "Change in link status : cur_data = %lx, last_reported_link = %lx",
6929 cur_data.link_report_flags,
6930 sc->last_reported_link.link_report_flags);
6934 ELINK_DEBUG_P1(sc, "link status change count = %x", sc->link_cnt);
6935 /* report new link params and remember the state for the next time */
6936 rte_memcpy(&sc->last_reported_link, &cur_data, sizeof(cur_data));
6938 if (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6939 &cur_data.link_report_flags)) {
6940 ELINK_DEBUG_P0(sc, "NIC Link is Down");
6942 __rte_unused const char *duplex;
6943 __rte_unused const char *flow;
6945 if (bnx2x_test_and_clear_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6946 &cur_data.link_report_flags)) {
6948 ELINK_DEBUG_P0(sc, "link set to full duplex");
6951 ELINK_DEBUG_P0(sc, "link set to half duplex");
6955 * Handle the FC at the end so that only these flags would be
6956 * possibly set. This way we may easily check if there is no FC
6959 if (cur_data.link_report_flags) {
6960 if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6961 &cur_data.link_report_flags) &&
6962 bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6963 &cur_data.link_report_flags)) {
6964 flow = "ON - receive & transmit";
6965 } else if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6966 &cur_data.link_report_flags) &&
6967 !bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6968 &cur_data.link_report_flags)) {
6969 flow = "ON - receive";
6970 } else if (!bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6971 &cur_data.link_report_flags) &&
6972 bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6973 &cur_data.link_report_flags)) {
6974 flow = "ON - transmit";
6976 flow = "none"; /* possible? */
6982 PMD_DRV_LOG(INFO, sc,
6983 "NIC Link is Up, %d Mbps %s duplex, Flow control: %s",
6984 cur_data.line_speed, duplex, flow);
6989 bnx2x_link_report(struct bnx2x_softc *sc)
6991 bnx2x_acquire_phy_lock(sc);
6992 bnx2x_link_report_locked(sc);
6993 bnx2x_release_phy_lock(sc);
6996 void bnx2x_link_status_update(struct bnx2x_softc *sc)
6998 if (sc->state != BNX2X_STATE_OPEN) {
7002 if (IS_PF(sc) && !CHIP_REV_IS_SLOW(sc)) {
7003 elink_link_status_update(&sc->link_params, &sc->link_vars);
7005 sc->port.supported[0] |= (ELINK_SUPPORTED_10baseT_Half |
7006 ELINK_SUPPORTED_10baseT_Full |
7007 ELINK_SUPPORTED_100baseT_Half |
7008 ELINK_SUPPORTED_100baseT_Full |
7009 ELINK_SUPPORTED_1000baseT_Full |
7010 ELINK_SUPPORTED_2500baseX_Full |
7011 ELINK_SUPPORTED_10000baseT_Full |
7012 ELINK_SUPPORTED_TP |
7013 ELINK_SUPPORTED_FIBRE |
7014 ELINK_SUPPORTED_Autoneg |
7015 ELINK_SUPPORTED_Pause |
7016 ELINK_SUPPORTED_Asym_Pause);
7017 sc->port.advertising[0] = sc->port.supported[0];
7019 sc->link_params.sc = sc;
7020 sc->link_params.port = SC_PORT(sc);
7021 sc->link_params.req_duplex[0] = DUPLEX_FULL;
7022 sc->link_params.req_flow_ctrl[0] = ELINK_FLOW_CTRL_NONE;
7023 sc->link_params.req_line_speed[0] = SPEED_10000;
7024 sc->link_params.speed_cap_mask[0] = 0x7f0000;
7025 sc->link_params.switch_cfg = ELINK_SWITCH_CFG_10G;
7027 if (CHIP_REV_IS_FPGA(sc)) {
7028 sc->link_vars.mac_type = ELINK_MAC_TYPE_EMAC;
7029 sc->link_vars.line_speed = ELINK_SPEED_1000;
7030 sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
7031 LINK_STATUS_SPEED_AND_DUPLEX_1000TFD);
7033 sc->link_vars.mac_type = ELINK_MAC_TYPE_BMAC;
7034 sc->link_vars.line_speed = ELINK_SPEED_10000;
7035 sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
7036 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
7039 sc->link_vars.link_up = 1;
7041 sc->link_vars.duplex = DUPLEX_FULL;
7042 sc->link_vars.flow_ctrl = ELINK_FLOW_CTRL_NONE;
7046 NIG_REG_EGRESS_DRAIN0_MODE +
7047 sc->link_params.port * 4, 0);
7048 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7049 bnx2x_link_report(sc);
7054 if (sc->link_vars.link_up) {
7055 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7057 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
7059 bnx2x_link_report(sc);
7061 bnx2x_link_report_locked(sc);
7062 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7066 static int bnx2x_initial_phy_init(struct bnx2x_softc *sc, int load_mode)
7068 int rc, cfg_idx = bnx2x_get_link_cfg_idx(sc);
7069 uint16_t req_line_speed = sc->link_params.req_line_speed[cfg_idx];
7070 struct elink_params *lp = &sc->link_params;
7072 bnx2x_set_requested_fc(sc);
7074 bnx2x_acquire_phy_lock(sc);
7076 if (load_mode == LOAD_DIAG) {
7077 lp->loopback_mode = ELINK_LOOPBACK_XGXS;
7078 /* Prefer doing PHY loopback at 10G speed, if possible */
7079 if (lp->req_line_speed[cfg_idx] < ELINK_SPEED_10000) {
7080 if (lp->speed_cap_mask[cfg_idx] &
7081 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
7082 lp->req_line_speed[cfg_idx] = ELINK_SPEED_10000;
7084 lp->req_line_speed[cfg_idx] = ELINK_SPEED_1000;
7089 if (load_mode == LOAD_LOOPBACK_EXT) {
7090 lp->loopback_mode = ELINK_LOOPBACK_EXT;
7093 rc = elink_phy_init(&sc->link_params, &sc->link_vars);
7095 bnx2x_release_phy_lock(sc);
7097 bnx2x_calc_fc_adv(sc);
7099 if (sc->link_vars.link_up) {
7100 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7101 bnx2x_link_report(sc);
7104 sc->link_params.req_line_speed[cfg_idx] = req_line_speed;
7108 /* update flags in shmem */
7110 bnx2x_update_drv_flags(struct bnx2x_softc *sc, uint32_t flags, uint32_t set)
7114 if (SHMEM2_HAS(sc, drv_flags)) {
7115 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7116 drv_flags = SHMEM2_RD(sc, drv_flags);
7121 drv_flags &= ~flags;
7124 SHMEM2_WR(sc, drv_flags, drv_flags);
7126 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7130 /* periodic timer callout routine, only runs when the interface is up */
7131 void bnx2x_periodic_callout(struct bnx2x_softc *sc)
7133 if ((sc->state != BNX2X_STATE_OPEN) ||
7134 (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_STOP)) {
7135 PMD_DRV_LOG(DEBUG, sc, "periodic callout exit (state=0x%x)",
7139 if (!CHIP_REV_IS_SLOW(sc)) {
7141 * This barrier is needed to ensure the ordering between the writing
7142 * to the sc->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
7147 bnx2x_acquire_phy_lock(sc);
7148 elink_period_func(&sc->link_params, &sc->link_vars);
7149 bnx2x_release_phy_lock(sc);
7153 if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7154 int mb_idx = SC_FW_MB_IDX(sc);
7158 ++sc->fw_drv_pulse_wr_seq;
7159 sc->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
7161 drv_pulse = sc->fw_drv_pulse_wr_seq;
7162 bnx2x_drv_pulse(sc);
7164 mcp_pulse = (SHMEM_RD(sc, func_mb[mb_idx].mcp_pulse_mb) &
7165 MCP_PULSE_SEQ_MASK);
7168 * The delta between driver pulse and mcp response should
7169 * be 1 (before mcp response) or 0 (after mcp response).
7171 if ((drv_pulse != mcp_pulse) &&
7172 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
7173 /* someone lost a heartbeat... */
7174 PMD_DRV_LOG(ERR, sc,
7175 "drv_pulse (0x%x) != mcp_pulse (0x%x)",
7176 drv_pulse, mcp_pulse);
7182 /* start the controller */
7183 static __rte_noinline
7184 int bnx2x_nic_load(struct bnx2x_softc *sc)
7187 uint32_t load_code = 0;
7190 PMD_INIT_FUNC_TRACE(sc);
7192 sc->state = BNX2X_STATE_OPENING_WAITING_LOAD;
7195 /* must be called before memory allocation and HW init */
7196 bnx2x_ilt_set_info(sc);
7199 bnx2x_set_fp_rx_buf_size(sc);
7202 if (bnx2x_alloc_mem(sc) != 0) {
7203 sc->state = BNX2X_STATE_CLOSED;
7205 goto bnx2x_nic_load_error0;
7209 if (bnx2x_alloc_fw_stats_mem(sc) != 0) {
7210 sc->state = BNX2X_STATE_CLOSED;
7212 goto bnx2x_nic_load_error0;
7216 rc = bnx2x_vf_init(sc);
7218 sc->state = BNX2X_STATE_ERROR;
7219 goto bnx2x_nic_load_error0;
7224 /* set pf load just before approaching the MCP */
7225 bnx2x_set_pf_load(sc);
7227 /* if MCP exists send load request and analyze response */
7228 if (!BNX2X_NOMCP(sc)) {
7229 /* attempt to load pf */
7230 if (bnx2x_nic_load_request(sc, &load_code) != 0) {
7231 sc->state = BNX2X_STATE_CLOSED;
7233 goto bnx2x_nic_load_error1;
7236 /* what did the MCP say? */
7237 if (bnx2x_nic_load_analyze_req(sc, load_code) != 0) {
7238 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7239 sc->state = BNX2X_STATE_CLOSED;
7241 goto bnx2x_nic_load_error2;
7244 PMD_DRV_LOG(INFO, sc, "Device has no MCP!");
7245 load_code = bnx2x_nic_load_no_mcp(sc);
7248 /* mark PMF if applicable */
7249 bnx2x_nic_load_pmf(sc, load_code);
7251 /* Init Function state controlling object */
7252 bnx2x_init_func_obj(sc);
7255 if (bnx2x_init_hw(sc, load_code) != 0) {
7256 PMD_DRV_LOG(NOTICE, sc, "HW init failed");
7257 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7258 sc->state = BNX2X_STATE_CLOSED;
7260 goto bnx2x_nic_load_error2;
7264 bnx2x_nic_init(sc, load_code);
7266 /* Init per-function objects */
7268 bnx2x_init_objs(sc);
7270 /* set AFEX default VLAN tag to an invalid value */
7271 sc->devinfo.mf_info.afex_def_vlan_tag = -1;
7273 sc->state = BNX2X_STATE_OPENING_WAITING_PORT;
7274 rc = bnx2x_func_start(sc);
7276 PMD_DRV_LOG(NOTICE, sc, "Function start failed!");
7277 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7278 sc->state = BNX2X_STATE_ERROR;
7279 goto bnx2x_nic_load_error3;
7282 /* send LOAD_DONE command to MCP */
7283 if (!BNX2X_NOMCP(sc)) {
7285 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7287 PMD_DRV_LOG(NOTICE, sc,
7288 "MCP response failure, aborting");
7289 sc->state = BNX2X_STATE_ERROR;
7291 goto bnx2x_nic_load_error3;
7296 rc = bnx2x_setup_leading(sc);
7298 PMD_DRV_LOG(NOTICE, sc, "Setup leading failed!");
7299 sc->state = BNX2X_STATE_ERROR;
7300 goto bnx2x_nic_load_error3;
7303 FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, i) {
7305 rc = bnx2x_setup_queue(sc, &sc->fp[i], FALSE);
7306 else /* IS_VF(sc) */
7307 rc = bnx2x_vf_setup_queue(sc, &sc->fp[i], FALSE);
7310 PMD_DRV_LOG(NOTICE, sc, "Queue(%d) setup failed", i);
7311 sc->state = BNX2X_STATE_ERROR;
7312 goto bnx2x_nic_load_error3;
7316 rc = bnx2x_init_rss_pf(sc);
7318 PMD_DRV_LOG(NOTICE, sc, "PF RSS init failed");
7319 sc->state = BNX2X_STATE_ERROR;
7320 goto bnx2x_nic_load_error3;
7323 /* now when Clients are configured we are ready to work */
7324 sc->state = BNX2X_STATE_OPEN;
7326 /* Configure a ucast MAC */
7328 rc = bnx2x_set_eth_mac(sc, TRUE);
7329 } else { /* IS_VF(sc) */
7330 rc = bnx2x_vf_set_mac(sc, TRUE);
7334 PMD_DRV_LOG(NOTICE, sc, "Setting Ethernet MAC failed");
7335 sc->state = BNX2X_STATE_ERROR;
7336 goto bnx2x_nic_load_error3;
7340 rc = bnx2x_initial_phy_init(sc, LOAD_OPEN);
7342 sc->state = BNX2X_STATE_ERROR;
7343 goto bnx2x_nic_load_error3;
7347 sc->link_params.feature_config_flags &=
7348 ~ELINK_FEATURE_CONFIG_BOOT_FROM_SAN;
7351 switch (LOAD_OPEN) {
7357 case LOAD_LOOPBACK_EXT:
7358 sc->state = BNX2X_STATE_DIAG;
7366 bnx2x_update_drv_flags(sc, 1 << DRV_FLAGS_PORT_MASK, 0);
7368 bnx2x_link_status_update(sc);
7371 if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
7372 /* mark driver is loaded in shmem2 */
7373 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
7374 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
7376 DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED |
7377 DRV_FLAGS_CAPABILITIES_LOADED_L2));
7380 /* start fast path */
7381 /* Initialize Rx filter */
7382 bnx2x_set_rx_mode(sc);
7384 /* wait for all pending SP commands to complete */
7385 if (IS_PF(sc) && !bnx2x_wait_sp_comp(sc, ~0x0UL)) {
7386 PMD_DRV_LOG(NOTICE, sc, "Timeout waiting for all SPs to complete!");
7387 bnx2x_periodic_stop(sc);
7388 bnx2x_nic_unload(sc, UNLOAD_CLOSE, FALSE);
7392 PMD_DRV_LOG(DEBUG, sc, "NIC successfully loaded");
7396 bnx2x_nic_load_error3:
7399 bnx2x_int_disable_sync(sc, 1);
7401 /* clean out queued objects */
7402 bnx2x_squeeze_objects(sc);
7405 bnx2x_nic_load_error2:
7407 if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7408 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
7409 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
7414 bnx2x_nic_load_error1:
7416 /* clear pf_load status, as it was already set */
7418 bnx2x_clear_pf_load(sc);
7421 bnx2x_nic_load_error0:
7423 bnx2x_free_fw_stats_mem(sc);
7430 * Handles controller initialization.
7432 int bnx2x_init(struct bnx2x_softc *sc)
7434 int other_engine = SC_PATH(sc) ? 0 : 1;
7435 uint8_t other_load_status, load_status;
7436 uint8_t global = FALSE;
7439 /* Check if the driver is still running and bail out if it is. */
7440 if (sc->state != BNX2X_STATE_CLOSED) {
7441 PMD_DRV_LOG(DEBUG, sc, "Init called while driver is running!");
7443 goto bnx2x_init_done;
7446 bnx2x_set_power_state(sc, PCI_PM_D0);
7449 * If parity occurred during the unload, then attentions and/or
7450 * RECOVERY_IN_PROGRESS may still be set. If so we want the first function
7451 * loaded on the current engine to complete the recovery. Parity recovery
7452 * is only relevant for PF driver.
7455 other_load_status = bnx2x_get_load_status(sc, other_engine);
7456 load_status = bnx2x_get_load_status(sc, SC_PATH(sc));
7458 if (!bnx2x_reset_is_done(sc, SC_PATH(sc)) ||
7459 bnx2x_chk_parity_attn(sc, &global, TRUE)) {
7462 * If there are attentions and they are in global blocks, set
7463 * the GLOBAL_RESET bit regardless whether it will be this
7464 * function that will complete the recovery or not.
7467 bnx2x_set_reset_global(sc);
7471 * Only the first function on the current engine should try
7472 * to recover in open. In case of attentions in global blocks
7473 * only the first in the chip should try to recover.
7476 && (!global ||!other_load_status))
7477 && bnx2x_trylock_leader_lock(sc)
7478 && !bnx2x_leader_reset(sc)) {
7479 PMD_DRV_LOG(INFO, sc,
7480 "Recovered during init");
7484 /* recovery has failed... */
7485 bnx2x_set_power_state(sc, PCI_PM_D3hot);
7487 sc->recovery_state = BNX2X_RECOVERY_FAILED;
7489 PMD_DRV_LOG(NOTICE, sc,
7490 "Recovery flow hasn't properly "
7491 "completed yet, try again later. "
7492 "If you still see this message after a "
7493 "few retries then power cycle is required.");
7496 goto bnx2x_init_done;
7501 sc->recovery_state = BNX2X_RECOVERY_DONE;
7503 rc = bnx2x_nic_load(sc);
7508 PMD_DRV_LOG(NOTICE, sc, "Initialization failed, "
7509 "stack notified driver is NOT running!");
7515 static void bnx2x_get_function_num(struct bnx2x_softc *sc)
7520 * Read the ME register to get the function number. The ME register
7521 * holds the relative-function number and absolute-function number. The
7522 * absolute-function number appears only in E2 and above. Before that
7523 * these bits always contained zero, therefore we cannot blindly use them.
7526 val = REG_RD(sc, BAR_ME_REGISTER);
7529 (uint8_t) ((val & ME_REG_PF_NUM) >> ME_REG_PF_NUM_SHIFT);
7531 (uint8_t) ((val & ME_REG_ABS_PF_NUM) >> ME_REG_ABS_PF_NUM_SHIFT) &
7534 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7535 sc->pfunc_abs = ((sc->pfunc_rel << 1) | sc->path_id);
7537 sc->pfunc_abs = (sc->pfunc_rel | sc->path_id);
7540 PMD_DRV_LOG(DEBUG, sc,
7541 "Relative function %d, Absolute function %d, Path %d",
7542 sc->pfunc_rel, sc->pfunc_abs, sc->path_id);
7545 static uint32_t bnx2x_get_shmem_mf_cfg_base(struct bnx2x_softc *sc)
7547 uint32_t shmem2_size;
7549 uint32_t mf_cfg_offset_value;
7552 offset = (SHMEM_ADDR(sc, func_mb) +
7553 (MAX_FUNC_NUM * sizeof(struct drv_func_mb)));
7556 if (sc->devinfo.shmem2_base != 0) {
7557 shmem2_size = SHMEM2_RD(sc, size);
7558 if (shmem2_size > offsetof(struct shmem2_region, mf_cfg_addr)) {
7559 mf_cfg_offset_value = SHMEM2_RD(sc, mf_cfg_addr);
7560 if (SHMEM_MF_CFG_ADDR_NONE != mf_cfg_offset_value) {
7561 offset = mf_cfg_offset_value;
7569 static uint32_t bnx2x_pcie_capability_read(struct bnx2x_softc *sc, int reg)
7572 struct bnx2x_pci_cap *caps;
7574 /* ensure PCIe capability is enabled */
7575 caps = pci_find_cap(sc, PCIY_EXPRESS, BNX2X_PCI_CAP);
7577 PMD_DRV_LOG(DEBUG, sc, "Found PCIe capability: "
7578 "id=0x%04X type=0x%04X addr=0x%08X",
7579 caps->id, caps->type, caps->addr);
7580 pci_read(sc, (caps->addr + reg), &ret, 2);
7584 PMD_DRV_LOG(WARNING, sc, "PCIe capability NOT FOUND!!!");
7589 static uint8_t bnx2x_is_pcie_pending(struct bnx2x_softc *sc)
7591 return bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_STA) &
7592 PCIM_EXP_STA_TRANSACTION_PND;
7596 * Walk the PCI capabiites list for the device to find what features are
7597 * supported. These capabilites may be enabled/disabled by firmware so it's
7598 * best to walk the list rather than make assumptions.
7600 static void bnx2x_probe_pci_caps(struct bnx2x_softc *sc)
7602 PMD_INIT_FUNC_TRACE(sc);
7604 struct bnx2x_pci_cap *caps;
7605 uint16_t link_status;
7608 /* check if PCI Power Management is enabled */
7609 caps = pci_find_cap(sc, PCIY_PMG, BNX2X_PCI_CAP);
7611 PMD_DRV_LOG(DEBUG, sc, "Found PM capability: "
7612 "id=0x%04X type=0x%04X addr=0x%08X",
7613 caps->id, caps->type, caps->addr);
7615 sc->devinfo.pcie_cap_flags |= BNX2X_PM_CAPABLE_FLAG;
7616 sc->devinfo.pcie_pm_cap_reg = caps->addr;
7619 link_status = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_LINK_STA);
7621 sc->devinfo.pcie_link_speed = (link_status & PCIM_LINK_STA_SPEED);
7622 sc->devinfo.pcie_link_width =
7623 ((link_status & PCIM_LINK_STA_WIDTH) >> 4);
7625 PMD_DRV_LOG(DEBUG, sc, "PCIe link speed=%d width=%d",
7626 sc->devinfo.pcie_link_speed, sc->devinfo.pcie_link_width);
7628 sc->devinfo.pcie_cap_flags |= BNX2X_PCIE_CAPABLE_FLAG;
7630 /* check if MSI capability is enabled */
7631 caps = pci_find_cap(sc, PCIY_MSI, BNX2X_PCI_CAP);
7633 PMD_DRV_LOG(DEBUG, sc, "Found MSI capability at 0x%04x", reg);
7635 sc->devinfo.pcie_cap_flags |= BNX2X_MSI_CAPABLE_FLAG;
7636 sc->devinfo.pcie_msi_cap_reg = caps->addr;
7639 /* check if MSI-X capability is enabled */
7640 caps = pci_find_cap(sc, PCIY_MSIX, BNX2X_PCI_CAP);
7642 PMD_DRV_LOG(DEBUG, sc, "Found MSI-X capability at 0x%04x", reg);
7644 sc->devinfo.pcie_cap_flags |= BNX2X_MSIX_CAPABLE_FLAG;
7645 sc->devinfo.pcie_msix_cap_reg = caps->addr;
7649 static int bnx2x_get_shmem_mf_cfg_info_sd(struct bnx2x_softc *sc)
7651 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7654 /* get the outer vlan if we're in switch-dependent mode */
7656 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7657 mf_info->ext_id = (uint16_t) val;
7659 mf_info->multi_vnics_mode = 1;
7661 if (!VALID_OVLAN(mf_info->ext_id)) {
7662 PMD_DRV_LOG(NOTICE, sc, "Invalid VLAN (%d)", mf_info->ext_id);
7666 /* get the capabilities */
7667 if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK) ==
7668 FUNC_MF_CFG_PROTOCOL_ISCSI) {
7669 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ISCSI;
7670 } else if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK)
7671 == FUNC_MF_CFG_PROTOCOL_FCOE) {
7672 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_FCOE;
7674 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ETHERNET;
7677 mf_info->vnics_per_port =
7678 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7683 static uint32_t bnx2x_get_shmem_ext_proto_support_flags(struct bnx2x_softc *sc)
7685 uint32_t retval = 0;
7688 val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7690 if (val & MACP_FUNC_CFG_FLAGS_ENABLED) {
7691 if (val & MACP_FUNC_CFG_FLAGS_ETHERNET) {
7692 retval |= MF_PROTO_SUPPORT_ETHERNET;
7694 if (val & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
7695 retval |= MF_PROTO_SUPPORT_ISCSI;
7697 if (val & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
7698 retval |= MF_PROTO_SUPPORT_FCOE;
7705 static int bnx2x_get_shmem_mf_cfg_info_si(struct bnx2x_softc *sc)
7707 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7711 * There is no outer vlan if we're in switch-independent mode.
7712 * If the mac is valid then assume multi-function.
7715 val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7717 mf_info->multi_vnics_mode = ((val & MACP_FUNC_CFG_FLAGS_MASK) != 0);
7719 mf_info->mf_protos_supported =
7720 bnx2x_get_shmem_ext_proto_support_flags(sc);
7722 mf_info->vnics_per_port =
7723 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7728 static int bnx2x_get_shmem_mf_cfg_info_niv(struct bnx2x_softc *sc)
7730 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7732 uint32_t func_config;
7733 uint32_t niv_config;
7735 mf_info->multi_vnics_mode = 1;
7737 e1hov_tag = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7738 func_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7739 niv_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].afex_config);
7742 (uint16_t) ((e1hov_tag & FUNC_MF_CFG_E1HOV_TAG_MASK) >>
7743 FUNC_MF_CFG_E1HOV_TAG_SHIFT);
7745 mf_info->default_vlan =
7746 (uint16_t) ((e1hov_tag & FUNC_MF_CFG_AFEX_VLAN_MASK) >>
7747 FUNC_MF_CFG_AFEX_VLAN_SHIFT);
7749 mf_info->niv_allowed_priorities =
7750 (uint8_t) ((niv_config & FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
7751 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT);
7753 mf_info->niv_default_cos =
7754 (uint8_t) ((func_config & FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
7755 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT);
7757 mf_info->afex_vlan_mode =
7758 ((niv_config & FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
7759 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT);
7761 mf_info->niv_mba_enabled =
7762 ((niv_config & FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK) >>
7763 FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT);
7765 mf_info->mf_protos_supported =
7766 bnx2x_get_shmem_ext_proto_support_flags(sc);
7768 mf_info->vnics_per_port =
7769 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7774 static int bnx2x_check_valid_mf_cfg(struct bnx2x_softc *sc)
7776 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7783 /* various MF mode sanity checks... */
7785 if (mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_HIDE) {
7786 PMD_DRV_LOG(NOTICE, sc,
7787 "Enumerated function %d is marked as hidden",
7792 if ((mf_info->vnics_per_port > 1) && !mf_info->multi_vnics_mode) {
7793 PMD_DRV_LOG(NOTICE, sc, "vnics_per_port=%d multi_vnics_mode=%d",
7794 mf_info->vnics_per_port, mf_info->multi_vnics_mode);
7798 if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7799 /* vnic id > 0 must have valid ovlan in switch-dependent mode */
7800 if ((SC_VN(sc) > 0) && !VALID_OVLAN(OVLAN(sc))) {
7801 PMD_DRV_LOG(NOTICE, sc, "mf_mode=SD vnic_id=%d ovlan=%d",
7802 SC_VN(sc), OVLAN(sc));
7806 if (!VALID_OVLAN(OVLAN(sc)) && mf_info->multi_vnics_mode) {
7807 PMD_DRV_LOG(NOTICE, sc,
7808 "mf_mode=SD multi_vnics_mode=%d ovlan=%d",
7809 mf_info->multi_vnics_mode, OVLAN(sc));
7814 * Verify all functions are either MF or SF mode. If MF, make sure
7815 * sure that all non-hidden functions have a valid ovlan. If SF,
7816 * make sure that all non-hidden functions have an invalid ovlan.
7818 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7819 mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7820 ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7821 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE) &&
7822 (((mf_info->multi_vnics_mode)
7823 && !VALID_OVLAN(ovlan1))
7824 || ((!mf_info->multi_vnics_mode)
7825 && VALID_OVLAN(ovlan1)))) {
7826 PMD_DRV_LOG(NOTICE, sc,
7827 "mf_mode=SD function %d MF config "
7828 "mismatch, multi_vnics_mode=%d ovlan=%d",
7829 i, mf_info->multi_vnics_mode,
7835 /* Verify all funcs on the same port each have a different ovlan. */
7836 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7837 mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7838 ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7839 /* iterate from the next function on the port to the max func */
7840 for (j = i + 2; j < MAX_FUNC_NUM; j += 2) {
7842 MFCFG_RD(sc, func_mf_config[j].config);
7844 MFCFG_RD(sc, func_mf_config[j].e1hov_tag);
7845 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE)
7846 && VALID_OVLAN(ovlan1)
7847 && !(mf_cfg2 & FUNC_MF_CFG_FUNC_HIDE)
7848 && VALID_OVLAN(ovlan2)
7849 && (ovlan1 == ovlan2)) {
7850 PMD_DRV_LOG(NOTICE, sc,
7851 "mf_mode=SD functions %d and %d "
7852 "have the same ovlan (%d)",
7859 /* MULTI_FUNCTION_SD */
7863 static int bnx2x_get_mf_cfg_info(struct bnx2x_softc *sc)
7865 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7866 uint32_t val, mac_upper;
7869 /* initialize mf_info defaults */
7870 mf_info->vnics_per_port = 1;
7871 mf_info->multi_vnics_mode = FALSE;
7872 mf_info->path_has_ovlan = FALSE;
7873 mf_info->mf_mode = SINGLE_FUNCTION;
7875 if (!CHIP_IS_MF_CAP(sc)) {
7879 if (sc->devinfo.mf_cfg_base == SHMEM_MF_CFG_ADDR_NONE) {
7880 PMD_DRV_LOG(NOTICE, sc, "Invalid mf_cfg_base!");
7884 /* get the MF mode (switch dependent / independent / single-function) */
7886 val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
7888 switch (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK) {
7889 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
7892 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7894 /* check for legal upper mac bytes */
7895 if (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT) {
7896 mf_info->mf_mode = MULTI_FUNCTION_SI;
7898 PMD_DRV_LOG(NOTICE, sc,
7899 "Invalid config for Switch Independent mode");
7904 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
7905 case SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4:
7907 /* get outer vlan configuration */
7908 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7910 if ((val & FUNC_MF_CFG_E1HOV_TAG_MASK) !=
7911 FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
7912 mf_info->mf_mode = MULTI_FUNCTION_SD;
7914 PMD_DRV_LOG(NOTICE, sc,
7915 "Invalid config for Switch Dependent mode");
7920 case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
7922 /* not in MF mode, vnics_per_port=1 and multi_vnics_mode=FALSE */
7925 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
7928 * Mark MF mode as NIV if MCP version includes NPAR-SD support
7929 * and the MAC address is valid.
7932 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7934 if ((SHMEM2_HAS(sc, afex_driver_support)) &&
7935 (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT)) {
7936 mf_info->mf_mode = MULTI_FUNCTION_AFEX;
7938 PMD_DRV_LOG(NOTICE, sc, "Invalid config for AFEX mode");
7945 PMD_DRV_LOG(NOTICE, sc, "Unknown MF mode (0x%08x)",
7946 (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK));
7951 /* set path mf_mode (which could be different than function mf_mode) */
7952 if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7953 mf_info->path_has_ovlan = TRUE;
7954 } else if (mf_info->mf_mode == SINGLE_FUNCTION) {
7956 * Decide on path multi vnics mode. If we're not in MF mode and in
7957 * 4-port mode, this is good enough to check vnic-0 of the other port
7960 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7961 uint8_t other_port = !(PORT_ID(sc) & 1);
7962 uint8_t abs_func_other_port =
7963 (SC_PATH(sc) + (2 * other_port));
7968 [abs_func_other_port].e1hov_tag);
7970 mf_info->path_has_ovlan = VALID_OVLAN((uint16_t) val);
7974 if (mf_info->mf_mode == SINGLE_FUNCTION) {
7975 /* invalid MF config */
7976 if (SC_VN(sc) >= 1) {
7977 PMD_DRV_LOG(NOTICE, sc, "VNIC ID >= 1 in SF mode");
7984 /* get the MF configuration */
7985 mf_info->mf_config[SC_VN(sc)] =
7986 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7988 switch (mf_info->mf_mode) {
7989 case MULTI_FUNCTION_SD:
7991 bnx2x_get_shmem_mf_cfg_info_sd(sc);
7994 case MULTI_FUNCTION_SI:
7996 bnx2x_get_shmem_mf_cfg_info_si(sc);
7999 case MULTI_FUNCTION_AFEX:
8001 bnx2x_get_shmem_mf_cfg_info_niv(sc);
8006 PMD_DRV_LOG(NOTICE, sc, "Get MF config failed (mf_mode=0x%08x)",
8011 /* get the congestion management parameters */
8014 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
8015 /* get min/max bw */
8016 val = MFCFG_RD(sc, func_mf_config[i].config);
8017 mf_info->min_bw[vnic] =
8018 ((val & FUNC_MF_CFG_MIN_BW_MASK) >>
8019 FUNC_MF_CFG_MIN_BW_SHIFT);
8020 mf_info->max_bw[vnic] =
8021 ((val & FUNC_MF_CFG_MAX_BW_MASK) >>
8022 FUNC_MF_CFG_MAX_BW_SHIFT);
8026 return bnx2x_check_valid_mf_cfg(sc);
8029 static int bnx2x_get_shmem_info(struct bnx2x_softc *sc)
8032 uint32_t mac_hi, mac_lo, val;
8034 PMD_INIT_FUNC_TRACE(sc);
8037 mac_hi = mac_lo = 0;
8039 sc->link_params.sc = sc;
8040 sc->link_params.port = port;
8042 /* get the hardware config info */
8043 sc->devinfo.hw_config = SHMEM_RD(sc, dev_info.shared_hw_config.config);
8044 sc->devinfo.hw_config2 =
8045 SHMEM_RD(sc, dev_info.shared_hw_config.config2);
8047 sc->link_params.hw_led_mode =
8048 ((sc->devinfo.hw_config & SHARED_HW_CFG_LED_MODE_MASK) >>
8049 SHARED_HW_CFG_LED_MODE_SHIFT);
8051 /* get the port feature config */
8053 SHMEM_RD(sc, dev_info.port_feature_config[port].config);
8055 /* get the link params */
8056 sc->link_params.speed_cap_mask[ELINK_INT_PHY] =
8057 SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask)
8058 & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
8059 sc->link_params.speed_cap_mask[ELINK_EXT_PHY1] =
8060 SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask2)
8061 & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
8063 /* get the lane config */
8064 sc->link_params.lane_config =
8065 SHMEM_RD(sc, dev_info.port_hw_config[port].lane_config);
8067 /* get the link config */
8068 val = SHMEM_RD(sc, dev_info.port_feature_config[port].link_config);
8069 sc->port.link_config[ELINK_INT_PHY] = val;
8070 sc->link_params.switch_cfg = (val & PORT_FEATURE_CONNECTED_SWITCH_MASK);
8071 sc->port.link_config[ELINK_EXT_PHY1] =
8072 SHMEM_RD(sc, dev_info.port_feature_config[port].link_config2);
8074 /* get the override preemphasis flag and enable it or turn it off */
8075 val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
8076 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) {
8077 sc->link_params.feature_config_flags |=
8078 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8080 sc->link_params.feature_config_flags &=
8081 ~ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8084 /* get the initial value of the link params */
8085 sc->link_params.multi_phy_config =
8086 SHMEM_RD(sc, dev_info.port_hw_config[port].multi_phy_config);
8088 /* get external phy info */
8089 sc->port.ext_phy_config =
8090 SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
8092 /* get the multifunction configuration */
8093 bnx2x_get_mf_cfg_info(sc);
8095 /* get the mac address */
8098 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
8100 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_lower);
8102 mac_hi = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_upper);
8103 mac_lo = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_lower);
8106 if ((mac_lo == 0) && (mac_hi == 0)) {
8107 *sc->mac_addr_str = 0;
8108 PMD_DRV_LOG(NOTICE, sc, "No Ethernet address programmed!");
8110 sc->link_params.mac_addr[0] = (uint8_t) (mac_hi >> 8);
8111 sc->link_params.mac_addr[1] = (uint8_t) (mac_hi);
8112 sc->link_params.mac_addr[2] = (uint8_t) (mac_lo >> 24);
8113 sc->link_params.mac_addr[3] = (uint8_t) (mac_lo >> 16);
8114 sc->link_params.mac_addr[4] = (uint8_t) (mac_lo >> 8);
8115 sc->link_params.mac_addr[5] = (uint8_t) (mac_lo);
8116 snprintf(sc->mac_addr_str, sizeof(sc->mac_addr_str),
8117 "%02x:%02x:%02x:%02x:%02x:%02x",
8118 sc->link_params.mac_addr[0],
8119 sc->link_params.mac_addr[1],
8120 sc->link_params.mac_addr[2],
8121 sc->link_params.mac_addr[3],
8122 sc->link_params.mac_addr[4],
8123 sc->link_params.mac_addr[5]);
8124 PMD_DRV_LOG(DEBUG, sc,
8125 "Ethernet address: %s", sc->mac_addr_str);
8131 static void bnx2x_media_detect(struct bnx2x_softc *sc)
8133 uint32_t phy_idx = bnx2x_get_cur_phy_idx(sc);
8134 switch (sc->link_params.phy[phy_idx].media_type) {
8135 case ELINK_ETH_PHY_SFPP_10G_FIBER:
8136 case ELINK_ETH_PHY_SFP_1G_FIBER:
8137 case ELINK_ETH_PHY_XFP_FIBER:
8138 case ELINK_ETH_PHY_KR:
8139 case ELINK_ETH_PHY_CX4:
8140 PMD_DRV_LOG(INFO, sc, "Found 10GBase-CX4 media.");
8141 sc->media = IFM_10G_CX4;
8143 case ELINK_ETH_PHY_DA_TWINAX:
8144 PMD_DRV_LOG(INFO, sc, "Found 10Gb Twinax media.");
8145 sc->media = IFM_10G_TWINAX;
8147 case ELINK_ETH_PHY_BASE_T:
8148 PMD_DRV_LOG(INFO, sc, "Found 10GBase-T media.");
8149 sc->media = IFM_10G_T;
8151 case ELINK_ETH_PHY_NOT_PRESENT:
8152 PMD_DRV_LOG(INFO, sc, "Media not present.");
8155 case ELINK_ETH_PHY_UNSPECIFIED:
8157 PMD_DRV_LOG(INFO, sc, "Unknown media!");
8163 #define GET_FIELD(value, fname) \
8164 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
8165 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
8166 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
8168 static int bnx2x_get_igu_cam_info(struct bnx2x_softc *sc)
8170 int pfid = SC_FUNC(sc);
8173 uint8_t fid, igu_sb_cnt = 0;
8175 sc->igu_base_sb = 0xff;
8177 if (CHIP_INT_MODE_IS_BC(sc)) {
8179 igu_sb_cnt = sc->igu_sb_cnt;
8180 sc->igu_base_sb = ((CHIP_IS_MODE_4_PORT(sc) ? pfid : vn) *
8182 sc->igu_dsb_id = (E1HVN_MAX * FP_SB_MAX_E1x +
8183 (CHIP_IS_MODE_4_PORT(sc) ? pfid : vn));
8187 /* IGU in normal mode - read CAM */
8189 igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; igu_sb_id++) {
8190 val = REG_RD(sc, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
8191 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) {
8195 if (fid & IGU_FID_ENCODE_IS_PF) {
8196 if ((fid & IGU_FID_PF_NUM_MASK) != pfid) {
8199 if (IGU_VEC(val) == 0) {
8200 /* default status block */
8201 sc->igu_dsb_id = igu_sb_id;
8203 if (sc->igu_base_sb == 0xff) {
8204 sc->igu_base_sb = igu_sb_id;
8212 * Due to new PF resource allocation by MFW T7.4 and above, it's optional
8213 * that number of CAM entries will not be equal to the value advertised in
8214 * PCI. Driver should use the minimal value of both as the actual status
8217 sc->igu_sb_cnt = min(sc->igu_sb_cnt, igu_sb_cnt);
8219 if (igu_sb_cnt == 0) {
8220 PMD_DRV_LOG(ERR, sc, "CAM configuration error");
8228 * Gather various information from the device config space, the device itself,
8229 * shmem, and the user input.
8231 static int bnx2x_get_device_info(struct bnx2x_softc *sc)
8236 /* get the chip revision (chip metal comes from pci config space) */
8237 sc->devinfo.chip_id = sc->link_params.chip_id =
8238 (((REG_RD(sc, MISC_REG_CHIP_NUM) & 0xffff) << 16) |
8239 ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12) |
8240 (((REG_RD(sc, PCICFG_OFFSET + PCI_ID_VAL3) >> 24) & 0xf) << 4) |
8241 ((REG_RD(sc, MISC_REG_BOND_ID) & 0xf) << 0));
8243 /* force 57811 according to MISC register */
8244 if (REG_RD(sc, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
8245 if (CHIP_IS_57810(sc)) {
8246 sc->devinfo.chip_id = ((CHIP_NUM_57811 << 16) |
8248 devinfo.chip_id & 0x0000ffff));
8249 } else if (CHIP_IS_57810_MF(sc)) {
8250 sc->devinfo.chip_id = ((CHIP_NUM_57811_MF << 16) |
8252 devinfo.chip_id & 0x0000ffff));
8254 sc->devinfo.chip_id |= 0x1;
8257 PMD_DRV_LOG(DEBUG, sc,
8258 "chip_id=0x%08x (num=0x%04x rev=0x%01x metal=0x%02x bond=0x%01x)",
8259 sc->devinfo.chip_id,
8260 ((sc->devinfo.chip_id >> 16) & 0xffff),
8261 ((sc->devinfo.chip_id >> 12) & 0xf),
8262 ((sc->devinfo.chip_id >> 4) & 0xff),
8263 ((sc->devinfo.chip_id >> 0) & 0xf));
8265 val = (REG_RD(sc, 0x2874) & 0x55);
8266 if ((sc->devinfo.chip_id & 0x1) || (CHIP_IS_E1H(sc) && (val == 0x55))) {
8267 sc->flags |= BNX2X_ONE_PORT_FLAG;
8268 PMD_DRV_LOG(DEBUG, sc, "single port device");
8271 /* set the doorbell size */
8272 sc->doorbell_size = (1 << BNX2X_DB_SHIFT);
8274 /* determine whether the device is in 2 port or 4 port mode */
8275 sc->devinfo.chip_port_mode = CHIP_PORT_MODE_NONE; /* E1h */
8276 if (CHIP_IS_E2E3(sc)) {
8278 * Read port4mode_en_ovwr[0]:
8279 * If 1, four port mode is in port4mode_en_ovwr[1].
8280 * If 0, four port mode is in port4mode_en[0].
8282 val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);
8284 val = ((val >> 1) & 1);
8286 val = REG_RD(sc, MISC_REG_PORT4MODE_EN);
8289 sc->devinfo.chip_port_mode =
8290 (val) ? CHIP_4_PORT_MODE : CHIP_2_PORT_MODE;
8292 PMD_DRV_LOG(DEBUG, sc, "Port mode = %s", (val) ? "4" : "2");
8295 /* get the function and path info for the device */
8296 bnx2x_get_function_num(sc);
8298 /* get the shared memory base address */
8299 sc->devinfo.shmem_base =
8300 sc->link_params.shmem_base = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
8301 sc->devinfo.shmem2_base =
8302 REG_RD(sc, (SC_PATH(sc) ? MISC_REG_GENERIC_CR_1 :
8303 MISC_REG_GENERIC_CR_0));
8305 if (!sc->devinfo.shmem_base) {
8306 /* this should ONLY prevent upcoming shmem reads */
8307 PMD_DRV_LOG(INFO, sc, "MCP not active");
8308 sc->flags |= BNX2X_NO_MCP_FLAG;
8312 /* make sure the shared memory contents are valid */
8313 val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
8314 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) !=
8315 (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) {
8316 PMD_DRV_LOG(NOTICE, sc, "Invalid SHMEM validity signature: 0x%08x",
8321 /* get the bootcode version */
8322 sc->devinfo.bc_ver = SHMEM_RD(sc, dev_info.bc_rev);
8323 snprintf(sc->devinfo.bc_ver_str,
8324 sizeof(sc->devinfo.bc_ver_str),
8326 ((sc->devinfo.bc_ver >> 24) & 0xff),
8327 ((sc->devinfo.bc_ver >> 16) & 0xff),
8328 ((sc->devinfo.bc_ver >> 8) & 0xff));
8329 PMD_DRV_LOG(DEBUG, sc, "Bootcode version: %s", sc->devinfo.bc_ver_str);
8331 /* get the bootcode shmem address */
8332 sc->devinfo.mf_cfg_base = bnx2x_get_shmem_mf_cfg_base(sc);
8334 /* clean indirect addresses as they're not used */
8335 pci_write_long(sc, PCICFG_GRC_ADDRESS, 0);
8337 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F0, 0);
8338 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F0, 0);
8339 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F0, 0);
8340 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F0, 0);
8341 if (CHIP_IS_E1x(sc)) {
8342 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F1, 0);
8343 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F1, 0);
8344 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F1, 0);
8345 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F1, 0);
8349 /* get the nvram size */
8350 val = REG_RD(sc, MCP_REG_MCPR_NVM_CFG4);
8351 sc->devinfo.flash_size =
8352 (NVRAM_1MB_SIZE << (val & MCPR_NVM_CFG4_FLASH_SIZE));
8354 bnx2x_set_power_state(sc, PCI_PM_D0);
8355 /* get various configuration parameters from shmem */
8356 bnx2x_get_shmem_info(sc);
8358 /* initialize IGU parameters */
8359 if (CHIP_IS_E1x(sc)) {
8360 sc->devinfo.int_block = INT_BLOCK_HC;
8361 sc->igu_dsb_id = DEF_SB_IGU_ID;
8362 sc->igu_base_sb = 0;
8364 sc->devinfo.int_block = INT_BLOCK_IGU;
8366 /* do not allow device reset during IGU info preocessing */
8367 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8369 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
8371 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8374 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
8375 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION, val);
8376 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x7f);
8378 while (tout && REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8383 if (REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8384 PMD_DRV_LOG(NOTICE, sc,
8385 "FORCING IGU Normal Mode failed!!!");
8386 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8391 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8392 PMD_DRV_LOG(DEBUG, sc, "IGU Backward Compatible Mode");
8393 sc->devinfo.int_block |= INT_BLOCK_MODE_BW_COMP;
8395 PMD_DRV_LOG(DEBUG, sc, "IGU Normal Mode");
8398 rc = bnx2x_get_igu_cam_info(sc);
8400 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8408 * Get base FW non-default (fast path) status block ID. This value is
8409 * used to initialize the fw_sb_id saved on the fp/queue structure to
8410 * determine the id used by the FW.
8412 if (CHIP_IS_E1x(sc)) {
8414 ((SC_PORT(sc) * FP_SB_MAX_E1x) + SC_L_ID(sc));
8417 * 57712+ - We currently use one FW SB per IGU SB (Rx and Tx of
8418 * the same queue are indicated on the same IGU SB). So we prefer
8419 * FW and IGU SBs to be the same value.
8421 sc->base_fw_ndsb = sc->igu_base_sb;
8424 elink_phy_probe(&sc->link_params);
8430 bnx2x_link_settings_supported(struct bnx2x_softc *sc, uint32_t switch_cfg)
8432 uint32_t cfg_size = 0;
8434 uint8_t port = SC_PORT(sc);
8436 /* aggregation of supported attributes of all external phys */
8437 sc->port.supported[0] = 0;
8438 sc->port.supported[1] = 0;
8440 switch (sc->link_params.num_phys) {
8442 sc->port.supported[0] =
8443 sc->link_params.phy[ELINK_INT_PHY].supported;
8447 sc->port.supported[0] =
8448 sc->link_params.phy[ELINK_EXT_PHY1].supported;
8452 if (sc->link_params.multi_phy_config &
8453 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
8454 sc->port.supported[1] =
8455 sc->link_params.phy[ELINK_EXT_PHY1].supported;
8456 sc->port.supported[0] =
8457 sc->link_params.phy[ELINK_EXT_PHY2].supported;
8459 sc->port.supported[0] =
8460 sc->link_params.phy[ELINK_EXT_PHY1].supported;
8461 sc->port.supported[1] =
8462 sc->link_params.phy[ELINK_EXT_PHY2].supported;
8468 if (!(sc->port.supported[0] || sc->port.supported[1])) {
8469 PMD_DRV_LOG(ERR, sc,
8470 "Invalid phy config in NVRAM (PHY1=0x%08x PHY2=0x%08x)",
8472 dev_info.port_hw_config
8473 [port].external_phy_config),
8475 dev_info.port_hw_config
8476 [port].external_phy_config2));
8481 sc->port.phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR);
8483 switch (switch_cfg) {
8484 case ELINK_SWITCH_CFG_1G:
8487 NIG_REG_SERDES0_CTRL_PHY_ADDR + port * 0x10);
8489 case ELINK_SWITCH_CFG_10G:
8492 NIG_REG_XGXS0_CTRL_PHY_ADDR + port * 0x18);
8495 PMD_DRV_LOG(ERR, sc,
8496 "Invalid switch config in"
8497 "link_config=0x%08x",
8498 sc->port.link_config[0]);
8503 PMD_DRV_LOG(INFO, sc, "PHY addr 0x%08x", sc->port.phy_addr);
8505 /* mask what we support according to speed_cap_mask per configuration */
8506 for (idx = 0; idx < cfg_size; idx++) {
8507 if (!(sc->link_params.speed_cap_mask[idx] &
8508 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) {
8509 sc->port.supported[idx] &=
8510 ~ELINK_SUPPORTED_10baseT_Half;
8513 if (!(sc->link_params.speed_cap_mask[idx] &
8514 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) {
8515 sc->port.supported[idx] &=
8516 ~ELINK_SUPPORTED_10baseT_Full;
8519 if (!(sc->link_params.speed_cap_mask[idx] &
8520 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) {
8521 sc->port.supported[idx] &=
8522 ~ELINK_SUPPORTED_100baseT_Half;
8525 if (!(sc->link_params.speed_cap_mask[idx] &
8526 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) {
8527 sc->port.supported[idx] &=
8528 ~ELINK_SUPPORTED_100baseT_Full;
8531 if (!(sc->link_params.speed_cap_mask[idx] &
8532 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) {
8533 sc->port.supported[idx] &=
8534 ~ELINK_SUPPORTED_1000baseT_Full;
8537 if (!(sc->link_params.speed_cap_mask[idx] &
8538 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) {
8539 sc->port.supported[idx] &=
8540 ~ELINK_SUPPORTED_2500baseX_Full;
8543 if (!(sc->link_params.speed_cap_mask[idx] &
8544 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8545 sc->port.supported[idx] &=
8546 ~ELINK_SUPPORTED_10000baseT_Full;
8549 if (!(sc->link_params.speed_cap_mask[idx] &
8550 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) {
8551 sc->port.supported[idx] &=
8552 ~ELINK_SUPPORTED_20000baseKR2_Full;
8556 PMD_DRV_LOG(INFO, sc, "PHY supported 0=0x%08x 1=0x%08x",
8557 sc->port.supported[0], sc->port.supported[1]);
8560 static void bnx2x_link_settings_requested(struct bnx2x_softc *sc)
8562 uint32_t link_config;
8564 uint32_t cfg_size = 0;
8566 sc->port.advertising[0] = 0;
8567 sc->port.advertising[1] = 0;
8569 switch (sc->link_params.num_phys) {
8579 for (idx = 0; idx < cfg_size; idx++) {
8580 sc->link_params.req_duplex[idx] = DUPLEX_FULL;
8581 link_config = sc->port.link_config[idx];
8583 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
8584 case PORT_FEATURE_LINK_SPEED_AUTO:
8585 if (sc->port.supported[idx] & ELINK_SUPPORTED_Autoneg) {
8586 sc->link_params.req_line_speed[idx] =
8587 ELINK_SPEED_AUTO_NEG;
8588 sc->port.advertising[idx] |=
8589 sc->port.supported[idx];
8590 if (sc->link_params.phy[ELINK_EXT_PHY1].type ==
8591 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833)
8592 sc->port.advertising[idx] |=
8593 (ELINK_SUPPORTED_100baseT_Half |
8594 ELINK_SUPPORTED_100baseT_Full);
8596 /* force 10G, no AN */
8597 sc->link_params.req_line_speed[idx] =
8599 sc->port.advertising[idx] |=
8600 (ADVERTISED_10000baseT_Full |
8606 case PORT_FEATURE_LINK_SPEED_10M_FULL:
8608 port.supported[idx] & ELINK_SUPPORTED_10baseT_Full)
8610 sc->link_params.req_line_speed[idx] =
8612 sc->port.advertising[idx] |=
8613 (ADVERTISED_10baseT_Full | ADVERTISED_TP);
8615 PMD_DRV_LOG(ERR, sc,
8616 "Invalid NVRAM config link_config=0x%08x "
8617 "speed_cap_mask=0x%08x",
8620 link_params.speed_cap_mask[idx]);
8625 case PORT_FEATURE_LINK_SPEED_10M_HALF:
8627 port.supported[idx] & ELINK_SUPPORTED_10baseT_Half)
8629 sc->link_params.req_line_speed[idx] =
8631 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8632 sc->port.advertising[idx] |=
8633 (ADVERTISED_10baseT_Half | ADVERTISED_TP);
8635 PMD_DRV_LOG(ERR, sc,
8636 "Invalid NVRAM config link_config=0x%08x "
8637 "speed_cap_mask=0x%08x",
8640 link_params.speed_cap_mask[idx]);
8645 case PORT_FEATURE_LINK_SPEED_100M_FULL:
8647 port.supported[idx] & ELINK_SUPPORTED_100baseT_Full)
8649 sc->link_params.req_line_speed[idx] =
8651 sc->port.advertising[idx] |=
8652 (ADVERTISED_100baseT_Full | ADVERTISED_TP);
8654 PMD_DRV_LOG(ERR, sc,
8655 "Invalid NVRAM config link_config=0x%08x "
8656 "speed_cap_mask=0x%08x",
8659 link_params.speed_cap_mask[idx]);
8664 case PORT_FEATURE_LINK_SPEED_100M_HALF:
8666 port.supported[idx] & ELINK_SUPPORTED_100baseT_Half)
8668 sc->link_params.req_line_speed[idx] =
8670 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8671 sc->port.advertising[idx] |=
8672 (ADVERTISED_100baseT_Half | ADVERTISED_TP);
8674 PMD_DRV_LOG(ERR, sc,
8675 "Invalid NVRAM config link_config=0x%08x "
8676 "speed_cap_mask=0x%08x",
8679 link_params.speed_cap_mask[idx]);
8684 case PORT_FEATURE_LINK_SPEED_1G:
8685 if (sc->port.supported[idx] &
8686 ELINK_SUPPORTED_1000baseT_Full) {
8687 sc->link_params.req_line_speed[idx] =
8689 sc->port.advertising[idx] |=
8690 (ADVERTISED_1000baseT_Full | ADVERTISED_TP);
8692 PMD_DRV_LOG(ERR, sc,
8693 "Invalid NVRAM config link_config=0x%08x "
8694 "speed_cap_mask=0x%08x",
8697 link_params.speed_cap_mask[idx]);
8702 case PORT_FEATURE_LINK_SPEED_2_5G:
8703 if (sc->port.supported[idx] &
8704 ELINK_SUPPORTED_2500baseX_Full) {
8705 sc->link_params.req_line_speed[idx] =
8707 sc->port.advertising[idx] |=
8708 (ADVERTISED_2500baseX_Full | ADVERTISED_TP);
8710 PMD_DRV_LOG(ERR, sc,
8711 "Invalid NVRAM config link_config=0x%08x "
8712 "speed_cap_mask=0x%08x",
8715 link_params.speed_cap_mask[idx]);
8720 case PORT_FEATURE_LINK_SPEED_10G_CX4:
8721 if (sc->port.supported[idx] &
8722 ELINK_SUPPORTED_10000baseT_Full) {
8723 sc->link_params.req_line_speed[idx] =
8725 sc->port.advertising[idx] |=
8726 (ADVERTISED_10000baseT_Full |
8729 PMD_DRV_LOG(ERR, sc,
8730 "Invalid NVRAM config link_config=0x%08x "
8731 "speed_cap_mask=0x%08x",
8734 link_params.speed_cap_mask[idx]);
8739 case PORT_FEATURE_LINK_SPEED_20G:
8740 sc->link_params.req_line_speed[idx] = ELINK_SPEED_20000;
8744 PMD_DRV_LOG(ERR, sc,
8745 "Invalid NVRAM config link_config=0x%08x "
8746 "speed_cap_mask=0x%08x", link_config,
8747 sc->link_params.speed_cap_mask[idx]);
8748 sc->link_params.req_line_speed[idx] =
8749 ELINK_SPEED_AUTO_NEG;
8750 sc->port.advertising[idx] = sc->port.supported[idx];
8754 sc->link_params.req_flow_ctrl[idx] =
8755 (link_config & PORT_FEATURE_FLOW_CONTROL_MASK);
8757 if (sc->link_params.req_flow_ctrl[idx] == ELINK_FLOW_CTRL_AUTO) {
8760 port.supported[idx] & ELINK_SUPPORTED_Autoneg)) {
8761 sc->link_params.req_flow_ctrl[idx] =
8762 ELINK_FLOW_CTRL_NONE;
8764 bnx2x_set_requested_fc(sc);
8770 static void bnx2x_get_phy_info(struct bnx2x_softc *sc)
8772 uint8_t port = SC_PORT(sc);
8775 PMD_INIT_FUNC_TRACE(sc);
8777 /* shmem data already read in bnx2x_get_shmem_info() */
8779 bnx2x_link_settings_supported(sc, sc->link_params.switch_cfg);
8780 bnx2x_link_settings_requested(sc);
8782 /* configure link feature according to nvram value */
8784 (((SHMEM_RD(sc, dev_info.port_feature_config[port].eee_power_mode))
8785 & PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
8786 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
8787 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
8788 sc->link_params.eee_mode = (ELINK_EEE_MODE_ADV_LPI |
8789 ELINK_EEE_MODE_ENABLE_LPI |
8790 ELINK_EEE_MODE_OUTPUT_TIME);
8792 sc->link_params.eee_mode = 0;
8795 /* get the media type */
8796 bnx2x_media_detect(sc);
8799 static void bnx2x_set_modes_bitmap(struct bnx2x_softc *sc)
8801 uint32_t flags = MODE_ASIC | MODE_PORT2;
8803 if (CHIP_IS_E2(sc)) {
8805 } else if (CHIP_IS_E3(sc)) {
8807 if (CHIP_REV(sc) == CHIP_REV_Ax) {
8808 flags |= MODE_E3_A0;
8809 } else { /*if (CHIP_REV(sc) == CHIP_REV_Bx) */
8811 flags |= MODE_E3_B0 | MODE_COS3;
8817 switch (sc->devinfo.mf_info.mf_mode) {
8818 case MULTI_FUNCTION_SD:
8819 flags |= MODE_MF_SD;
8821 case MULTI_FUNCTION_SI:
8822 flags |= MODE_MF_SI;
8824 case MULTI_FUNCTION_AFEX:
8825 flags |= MODE_MF_AFEX;
8832 #if defined(__LITTLE_ENDIAN)
8833 flags |= MODE_LITTLE_ENDIAN;
8834 #else /* __BIG_ENDIAN */
8835 flags |= MODE_BIG_ENDIAN;
8838 INIT_MODE_FLAGS(sc) = flags;
8841 int bnx2x_alloc_hsi_mem(struct bnx2x_softc *sc)
8843 struct bnx2x_fastpath *fp;
8848 /************************/
8849 /* DEFAULT STATUS BLOCK */
8850 /************************/
8852 if (bnx2x_dma_alloc(sc, sizeof(struct host_sp_status_block),
8853 &sc->def_sb_dma, "def_sb",
8854 RTE_CACHE_LINE_SIZE) != 0) {
8859 (struct host_sp_status_block *)sc->def_sb_dma.vaddr;
8864 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8865 &sc->eq_dma, "ev_queue",
8866 RTE_CACHE_LINE_SIZE) != 0) {
8871 sc->eq = (union event_ring_elem *)sc->eq_dma.vaddr;
8877 if (bnx2x_dma_alloc(sc, sizeof(struct bnx2x_slowpath),
8879 RTE_CACHE_LINE_SIZE) != 0) {
8885 sc->sp = (struct bnx2x_slowpath *)sc->sp_dma.vaddr;
8887 /*******************/
8888 /* SLOW PATH QUEUE */
8889 /*******************/
8891 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8892 &sc->spq_dma, "sp_queue",
8893 RTE_CACHE_LINE_SIZE) != 0) {
8900 sc->spq = (struct eth_spe *)sc->spq_dma.vaddr;
8902 /***************************/
8903 /* FW DECOMPRESSION BUFFER */
8904 /***************************/
8906 if (bnx2x_dma_alloc(sc, FW_BUF_SIZE, &sc->gz_buf_dma,
8907 "fw_buf", RTE_CACHE_LINE_SIZE) != 0) {
8915 sc->gz_buf = (void *)sc->gz_buf_dma.vaddr;
8922 /* allocate DMA memory for each fastpath structure */
8923 for (i = 0; i < sc->num_queues; i++) {
8928 /*******************/
8929 /* FP STATUS BLOCK */
8930 /*******************/
8932 snprintf(buf, sizeof(buf), "fp_%d_sb", i);
8933 if (bnx2x_dma_alloc(sc, sizeof(union bnx2x_host_hc_status_block),
8934 &fp->sb_dma, buf, RTE_CACHE_LINE_SIZE) != 0) {
8935 PMD_DRV_LOG(NOTICE, sc, "Failed to alloc %s", buf);
8938 if (CHIP_IS_E2E3(sc)) {
8939 fp->status_block.e2_sb =
8940 (struct host_hc_status_block_e2 *)
8943 fp->status_block.e1x_sb =
8944 (struct host_hc_status_block_e1x *)
8953 void bnx2x_free_hsi_mem(struct bnx2x_softc *sc)
8955 struct bnx2x_fastpath *fp;
8958 for (i = 0; i < sc->num_queues; i++) {
8961 /*******************/
8962 /* FP STATUS BLOCK */
8963 /*******************/
8965 memset(&fp->status_block, 0, sizeof(fp->status_block));
8968 /***************************/
8969 /* FW DECOMPRESSION BUFFER */
8970 /***************************/
8974 /*******************/
8975 /* SLOW PATH QUEUE */
8976 /*******************/
8992 /************************/
8993 /* DEFAULT STATUS BLOCK */
8994 /************************/
9001 * Previous driver DMAE transaction may have occurred when pre-boot stage
9002 * ended and boot began. This would invalidate the addresses of the
9003 * transaction, resulting in was-error bit set in the PCI causing all
9004 * hw-to-host PCIe transactions to timeout. If this happened we want to clear
9005 * the interrupt which detected this from the pglueb and the was-done bit
9007 static void bnx2x_prev_interrupted_dmae(struct bnx2x_softc *sc)
9011 if (!CHIP_IS_E1x(sc)) {
9012 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS);
9013 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
9014 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
9020 static int bnx2x_prev_mcp_done(struct bnx2x_softc *sc)
9022 uint32_t rc = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE,
9023 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
9025 PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
9032 static struct bnx2x_prev_list_node *bnx2x_prev_path_get_entry(struct bnx2x_softc *sc)
9034 struct bnx2x_prev_list_node *tmp;
9036 LIST_FOREACH(tmp, &bnx2x_prev_list, node) {
9037 if ((sc->pcie_bus == tmp->bus) &&
9038 (sc->pcie_device == tmp->slot) &&
9039 (SC_PATH(sc) == tmp->path)) {
9047 static uint8_t bnx2x_prev_is_path_marked(struct bnx2x_softc *sc)
9049 struct bnx2x_prev_list_node *tmp;
9052 rte_spinlock_lock(&bnx2x_prev_mtx);
9054 tmp = bnx2x_prev_path_get_entry(sc);
9057 PMD_DRV_LOG(DEBUG, sc,
9058 "Path %d/%d/%d was marked by AER",
9059 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9062 PMD_DRV_LOG(DEBUG, sc,
9063 "Path %d/%d/%d was already cleaned from previous drivers",
9064 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9068 rte_spinlock_unlock(&bnx2x_prev_mtx);
9073 static int bnx2x_prev_mark_path(struct bnx2x_softc *sc, uint8_t after_undi)
9075 struct bnx2x_prev_list_node *tmp;
9077 rte_spinlock_lock(&bnx2x_prev_mtx);
9079 /* Check whether the entry for this path already exists */
9080 tmp = bnx2x_prev_path_get_entry(sc);
9083 PMD_DRV_LOG(DEBUG, sc,
9084 "Re-marking AER in path %d/%d/%d",
9085 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9087 PMD_DRV_LOG(DEBUG, sc,
9088 "Removing AER indication from path %d/%d/%d",
9089 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9093 rte_spinlock_unlock(&bnx2x_prev_mtx);
9097 rte_spinlock_unlock(&bnx2x_prev_mtx);
9099 /* Create an entry for this path and add it */
9100 tmp = rte_malloc("", sizeof(struct bnx2x_prev_list_node),
9101 RTE_CACHE_LINE_SIZE);
9103 PMD_DRV_LOG(NOTICE, sc, "Failed to allocate 'bnx2x_prev_list_node'");
9107 tmp->bus = sc->pcie_bus;
9108 tmp->slot = sc->pcie_device;
9109 tmp->path = SC_PATH(sc);
9111 tmp->undi = after_undi ? (1 << SC_PORT(sc)) : 0;
9113 rte_spinlock_lock(&bnx2x_prev_mtx);
9115 LIST_INSERT_HEAD(&bnx2x_prev_list, tmp, node);
9117 rte_spinlock_unlock(&bnx2x_prev_mtx);
9122 static int bnx2x_do_flr(struct bnx2x_softc *sc)
9126 /* only E2 and onwards support FLR */
9127 if (CHIP_IS_E1x(sc)) {
9128 PMD_DRV_LOG(WARNING, sc, "FLR not supported in E1H");
9132 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9133 if (sc->devinfo.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9134 PMD_DRV_LOG(WARNING, sc,
9135 "FLR not supported by BC_VER: 0x%08x",
9136 sc->devinfo.bc_ver);
9140 /* Wait for Transaction Pending bit clean */
9141 for (i = 0; i < 4; i++) {
9143 DELAY(((1 << (i - 1)) * 100) * 1000);
9146 if (!bnx2x_is_pcie_pending(sc)) {
9151 PMD_DRV_LOG(NOTICE, sc, "PCIE transaction is not cleared, "
9152 "proceeding with reset anyway");
9155 bnx2x_fw_command(sc, DRV_MSG_CODE_INITIATE_FLR, 0);
9160 struct bnx2x_mac_vals {
9168 uint32_t bmac_val[2];
9172 bnx2x_prev_unload_close_mac(struct bnx2x_softc *sc, struct bnx2x_mac_vals *vals)
9174 uint32_t val, base_addr, offset, mask, reset_reg;
9175 uint8_t mac_stopped = FALSE;
9176 uint8_t port = SC_PORT(sc);
9177 uint32_t wb_data[2];
9179 /* reset addresses as they also mark which values were changed */
9180 vals->bmac_addr = 0;
9181 vals->umac_addr = 0;
9182 vals->xmac_addr = 0;
9183 vals->emac_addr = 0;
9185 reset_reg = REG_RD(sc, MISC_REG_RESET_REG_2);
9187 if (!CHIP_IS_E3(sc)) {
9188 val = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9189 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9190 if ((mask & reset_reg) && val) {
9191 base_addr = SC_PORT(sc) ? NIG_REG_INGRESS_BMAC1_MEM
9192 : NIG_REG_INGRESS_BMAC0_MEM;
9193 offset = CHIP_IS_E2(sc) ? BIGMAC2_REGISTER_BMAC_CONTROL
9194 : BIGMAC_REGISTER_BMAC_CONTROL;
9197 * use rd/wr since we cannot use dmae. This is safe
9198 * since MCP won't access the bus due to the request
9199 * to unload, and no function on the path can be
9200 * loaded at this time.
9202 wb_data[0] = REG_RD(sc, base_addr + offset);
9203 wb_data[1] = REG_RD(sc, base_addr + offset + 0x4);
9204 vals->bmac_addr = base_addr + offset;
9205 vals->bmac_val[0] = wb_data[0];
9206 vals->bmac_val[1] = wb_data[1];
9207 wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE;
9208 REG_WR(sc, vals->bmac_addr, wb_data[0]);
9209 REG_WR(sc, vals->bmac_addr + 0x4, wb_data[1]);
9212 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + SC_PORT(sc) * 4;
9213 vals->emac_val = REG_RD(sc, vals->emac_addr);
9214 REG_WR(sc, vals->emac_addr, 0);
9217 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9218 base_addr = SC_PORT(sc) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9219 val = REG_RD(sc, base_addr + XMAC_REG_PFC_CTRL_HI);
9220 REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9222 REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9224 vals->xmac_addr = base_addr + XMAC_REG_CTRL;
9225 vals->xmac_val = REG_RD(sc, vals->xmac_addr);
9226 REG_WR(sc, vals->xmac_addr, 0);
9230 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9231 if (mask & reset_reg) {
9232 base_addr = SC_PORT(sc) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9233 vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
9234 vals->umac_val = REG_RD(sc, vals->umac_addr);
9235 REG_WR(sc, vals->umac_addr, 0);
9245 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9246 #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
9247 #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
9248 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
9251 bnx2x_prev_unload_undi_inc(struct bnx2x_softc *sc, uint8_t port, uint8_t inc)
9254 uint32_t tmp_reg = REG_RD(sc, BNX2X_PREV_UNDI_PROD_ADDR(port));
9256 rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9257 bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9259 tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9260 REG_WR(sc, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9263 static int bnx2x_prev_unload_common(struct bnx2x_softc *sc)
9265 uint32_t reset_reg, tmp_reg = 0, rc;
9266 uint8_t prev_undi = FALSE;
9267 struct bnx2x_mac_vals mac_vals;
9268 uint32_t timer_count = 1000;
9272 * It is possible a previous function received 'common' answer,
9273 * but hasn't loaded yet, therefore creating a scenario of
9274 * multiple functions receiving 'common' on the same path.
9276 memset(&mac_vals, 0, sizeof(mac_vals));
9278 if (bnx2x_prev_is_path_marked(sc)) {
9279 return bnx2x_prev_mcp_done(sc);
9282 reset_reg = REG_RD(sc, MISC_REG_RESET_REG_1);
9284 /* Reset should be performed after BRB is emptied */
9285 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
9286 /* Close the MAC Rx to prevent BRB from filling up */
9287 bnx2x_prev_unload_close_mac(sc, &mac_vals);
9289 /* close LLH filters towards the BRB */
9290 elink_set_rx_filter(&sc->link_params, 0);
9293 * Check if the UNDI driver was previously loaded.
9294 * UNDI driver initializes CID offset for normal bell to 0x7
9296 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
9297 tmp_reg = REG_RD(sc, DORQ_REG_NORM_CID_OFST);
9298 if (tmp_reg == 0x7) {
9299 PMD_DRV_LOG(DEBUG, sc, "UNDI previously loaded");
9301 /* clear the UNDI indication */
9302 REG_WR(sc, DORQ_REG_NORM_CID_OFST, 0);
9303 /* clear possible idle check errors */
9304 REG_RD(sc, NIG_REG_NIG_INT_STS_CLR_0);
9308 /* wait until BRB is empty */
9309 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9310 while (timer_count) {
9313 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9318 PMD_DRV_LOG(DEBUG, sc, "BRB still has 0x%08x", tmp_reg);
9320 /* reset timer as long as BRB actually gets emptied */
9321 if (prev_brb > tmp_reg) {
9327 /* If UNDI resides in memory, manually increment it */
9329 bnx2x_prev_unload_undi_inc(sc, SC_PORT(sc), 1);
9336 PMD_DRV_LOG(NOTICE, sc, "Failed to empty BRB");
9340 /* No packets are in the pipeline, path is ready for reset */
9341 bnx2x_reset_common(sc);
9343 if (mac_vals.xmac_addr) {
9344 REG_WR(sc, mac_vals.xmac_addr, mac_vals.xmac_val);
9346 if (mac_vals.umac_addr) {
9347 REG_WR(sc, mac_vals.umac_addr, mac_vals.umac_val);
9349 if (mac_vals.emac_addr) {
9350 REG_WR(sc, mac_vals.emac_addr, mac_vals.emac_val);
9352 if (mac_vals.bmac_addr) {
9353 REG_WR(sc, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
9354 REG_WR(sc, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
9357 rc = bnx2x_prev_mark_path(sc, prev_undi);
9359 bnx2x_prev_mcp_done(sc);
9363 return bnx2x_prev_mcp_done(sc);
9366 static int bnx2x_prev_unload_uncommon(struct bnx2x_softc *sc)
9370 /* Test if previous unload process was already finished for this path */
9371 if (bnx2x_prev_is_path_marked(sc)) {
9372 return bnx2x_prev_mcp_done(sc);
9376 * If function has FLR capabilities, and existing FW version matches
9377 * the one required, then FLR will be sufficient to clean any residue
9378 * left by previous driver
9380 rc = bnx2x_nic_load_analyze_req(sc, FW_MSG_CODE_DRV_LOAD_FUNCTION);
9382 /* fw version is good */
9383 rc = bnx2x_do_flr(sc);
9387 /* FLR was performed */
9391 PMD_DRV_LOG(INFO, sc, "Could not FLR");
9393 /* Close the MCP request, return failure */
9394 rc = bnx2x_prev_mcp_done(sc);
9396 rc = BNX2X_PREV_WAIT_NEEDED;
9402 static int bnx2x_prev_unload(struct bnx2x_softc *sc)
9404 int time_counter = 10;
9405 uint32_t fw, hw_lock_reg, hw_lock_val;
9408 PMD_INIT_FUNC_TRACE(sc);
9411 * Clear HW from errors which may have resulted from an interrupted
9414 bnx2x_prev_interrupted_dmae(sc);
9416 /* Release previously held locks */
9417 hw_lock_reg = (SC_FUNC(sc) <= 5) ?
9418 (MISC_REG_DRIVER_CONTROL_1 + SC_FUNC(sc) * 8) :
9419 (MISC_REG_DRIVER_CONTROL_7 + (SC_FUNC(sc) - 6) * 8);
9421 hw_lock_val = (REG_RD(sc, hw_lock_reg));
9423 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
9424 PMD_DRV_LOG(DEBUG, sc, "Releasing previously held NVRAM lock\n");
9425 REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
9426 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << SC_PORT(sc)));
9428 PMD_DRV_LOG(DEBUG, sc, "Releasing previously held HW lock\n");
9429 REG_WR(sc, hw_lock_reg, 0xffffffff);
9432 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(sc, MCP_REG_MCPR_ACCESS_LOCK)) {
9433 PMD_DRV_LOG(DEBUG, sc, "Releasing previously held ALR\n");
9434 REG_WR(sc, MCP_REG_MCPR_ACCESS_LOCK, 0);
9438 /* Lock MCP using an unload request */
9439 fw = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
9441 PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
9446 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
9447 rc = bnx2x_prev_unload_common(sc);
9451 /* non-common reply from MCP might require looping */
9452 rc = bnx2x_prev_unload_uncommon(sc);
9453 if (rc != BNX2X_PREV_WAIT_NEEDED) {
9458 } while (--time_counter);
9460 if (!time_counter || rc) {
9461 PMD_DRV_LOG(NOTICE, sc, "Failed to unload previous driver!");
9469 bnx2x_dcbx_set_state(struct bnx2x_softc *sc, uint8_t dcb_on, uint32_t dcbx_enabled)
9471 if (!CHIP_IS_E1x(sc)) {
9472 sc->dcb_state = dcb_on;
9473 sc->dcbx_enabled = dcbx_enabled;
9475 sc->dcb_state = FALSE;
9476 sc->dcbx_enabled = BNX2X_DCBX_ENABLED_INVALID;
9478 PMD_DRV_LOG(DEBUG, sc,
9479 "DCB state [%s:%s]",
9480 dcb_on ? "ON" : "OFF",
9481 (dcbx_enabled == BNX2X_DCBX_ENABLED_OFF) ? "user-mode" :
9483 BNX2X_DCBX_ENABLED_ON_NEG_OFF) ? "on-chip static"
9485 BNX2X_DCBX_ENABLED_ON_NEG_ON) ?
9486 "on-chip with negotiation" : "invalid");
9489 static int bnx2x_set_qm_cid_count(struct bnx2x_softc *sc)
9491 int cid_count = BNX2X_L2_MAX_CID(sc);
9493 if (CNIC_SUPPORT(sc)) {
9494 cid_count += CNIC_CID_MAX;
9497 return roundup(cid_count, QM_CID_ROUND);
9500 static void bnx2x_init_multi_cos(struct bnx2x_softc *sc)
9504 uint32_t pri_map = 0;
9506 for (pri = 0; pri < BNX2X_MAX_PRIORITY; pri++) {
9507 cos = ((pri_map & (0xf << (pri * 4))) >> (pri * 4));
9508 if (cos < sc->max_cos) {
9509 sc->prio_to_cos[pri] = cos;
9511 PMD_DRV_LOG(WARNING, sc,
9512 "Invalid COS %d for priority %d "
9513 "(max COS is %d), setting to 0", cos, pri,
9515 sc->prio_to_cos[pri] = 0;
9520 static int bnx2x_pci_get_caps(struct bnx2x_softc *sc)
9527 struct bnx2x_pci_cap *cap;
9529 cap = sc->pci_caps = rte_zmalloc("caps", sizeof(struct bnx2x_pci_cap),
9530 RTE_CACHE_LINE_SIZE);
9532 PMD_DRV_LOG(NOTICE, sc, "Failed to allocate memory");
9537 pci_read(sc, PCI_STATUS, &status, 2);
9538 if (!(status & PCI_STATUS_CAP_LIST)) {
9540 pci_read(sc, PCIR_STATUS, &status, 2);
9541 if (!(status & PCIM_STATUS_CAPPRESENT)) {
9543 PMD_DRV_LOG(NOTICE, sc, "PCIe capability reading failed");
9548 pci_read(sc, PCI_CAPABILITY_LIST, &pci_cap.next, 1);
9550 pci_read(sc, PCIR_CAP_PTR, &pci_cap.next, 1);
9552 while (pci_cap.next) {
9553 cap->addr = pci_cap.next & ~3;
9554 pci_read(sc, pci_cap.next & ~3, &pci_cap, 2);
9555 if (pci_cap.id == 0xff)
9557 cap->id = pci_cap.id;
9558 cap->type = BNX2X_PCI_CAP;
9559 cap->next = rte_zmalloc("pci_cap",
9560 sizeof(struct bnx2x_pci_cap),
9561 RTE_CACHE_LINE_SIZE);
9563 PMD_DRV_LOG(NOTICE, sc, "Failed to allocate memory");
9572 static void bnx2x_init_rte(struct bnx2x_softc *sc)
9575 sc->max_tx_queues = min(BNX2X_VF_MAX_QUEUES_PER_VF,
9577 sc->max_rx_queues = min(BNX2X_VF_MAX_QUEUES_PER_VF,
9580 sc->max_rx_queues = BNX2X_MAX_RSS_COUNT(sc);
9581 sc->max_tx_queues = sc->max_rx_queues;
9585 #define FW_HEADER_LEN 104
9586 #define FW_NAME_57711 "/lib/firmware/bnx2x/bnx2x-e1h-7.2.51.0.fw"
9587 #define FW_NAME_57810 "/lib/firmware/bnx2x/bnx2x-e2-7.2.51.0.fw"
9589 void bnx2x_load_firmware(struct bnx2x_softc *sc)
9595 fwname = sc->devinfo.device_id == CHIP_NUM_57711
9596 ? FW_NAME_57711 : FW_NAME_57810;
9597 f = open(fwname, O_RDONLY);
9599 PMD_DRV_LOG(NOTICE, sc, "Can't open firmware file");
9603 if (fstat(f, &st) < 0) {
9604 PMD_DRV_LOG(NOTICE, sc, "Can't stat firmware file");
9609 sc->firmware = rte_zmalloc("bnx2x_fw", st.st_size, RTE_CACHE_LINE_SIZE);
9610 if (!sc->firmware) {
9611 PMD_DRV_LOG(NOTICE, sc, "Can't allocate memory for firmware");
9616 if (read(f, sc->firmware, st.st_size) != st.st_size) {
9617 PMD_DRV_LOG(NOTICE, sc, "Can't read firmware data");
9623 sc->fw_len = st.st_size;
9624 if (sc->fw_len < FW_HEADER_LEN) {
9625 PMD_DRV_LOG(NOTICE, sc,
9626 "Invalid fw size: %" PRIu64, sc->fw_len);
9629 PMD_DRV_LOG(DEBUG, sc, "fw_len = %" PRIu64, sc->fw_len);
9633 bnx2x_data_to_init_ops(uint8_t * data, struct raw_op *dst, uint32_t len)
9635 uint32_t *src = (uint32_t *) data;
9638 for (i = 0, j = 0; i < len / 8; ++i, j += 2) {
9639 tmp = rte_be_to_cpu_32(src[j]);
9640 dst[i].op = (tmp >> 24) & 0xFF;
9641 dst[i].offset = tmp & 0xFFFFFF;
9642 dst[i].raw_data = rte_be_to_cpu_32(src[j + 1]);
9647 bnx2x_data_to_init_offsets(uint8_t * data, uint16_t * dst, uint32_t len)
9649 uint16_t *src = (uint16_t *) data;
9652 for (i = 0; i < len / 2; ++i)
9653 dst[i] = rte_be_to_cpu_16(src[i]);
9656 static void bnx2x_data_to_init_data(uint8_t * data, uint32_t * dst, uint32_t len)
9658 uint32_t *src = (uint32_t *) data;
9661 for (i = 0; i < len / 4; ++i)
9662 dst[i] = rte_be_to_cpu_32(src[i]);
9665 static void bnx2x_data_to_iro_array(uint8_t * data, struct iro *dst, uint32_t len)
9667 uint32_t *src = (uint32_t *) data;
9670 for (i = 0, j = 0; i < len / sizeof(struct iro); ++i, ++j) {
9671 dst[i].base = rte_be_to_cpu_32(src[j++]);
9672 tmp = rte_be_to_cpu_32(src[j]);
9673 dst[i].m1 = (tmp >> 16) & 0xFFFF;
9674 dst[i].m2 = tmp & 0xFFFF;
9676 tmp = rte_be_to_cpu_32(src[j]);
9677 dst[i].m3 = (tmp >> 16) & 0xFFFF;
9678 dst[i].size = tmp & 0xFFFF;
9683 * Device attach function.
9685 * Allocates device resources, performs secondary chip identification, and
9686 * initializes driver instance variables. This function is called from driver
9687 * load after a successful probe.
9690 * 0 = Success, >0 = Failure
9692 int bnx2x_attach(struct bnx2x_softc *sc)
9696 PMD_DRV_LOG(DEBUG, sc, "Starting attach...");
9698 rc = bnx2x_pci_get_caps(sc);
9700 PMD_DRV_LOG(NOTICE, sc, "PCIe caps reading was failed");
9704 sc->state = BNX2X_STATE_CLOSED;
9706 pci_write_long(sc, PCICFG_GRC_ADDRESS, PCICFG_VENDOR_ID_OFFSET);
9708 sc->igu_base_addr = IS_VF(sc) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
9710 /* get PCI capabilites */
9711 bnx2x_probe_pci_caps(sc);
9713 if (sc->devinfo.pcie_msix_cap_reg != 0) {
9716 (sc->devinfo.pcie_msix_cap_reg + PCIR_MSIX_CTRL), &val,
9718 sc->igu_sb_cnt = (val & PCIM_MSIXCTRL_TABLE_SIZE) + 1;
9723 /* Init RTE stuff */
9727 /* Enable internal target-read (in case we are probed after PF
9728 * FLR). Must be done prior to any BAR read access. Only for
9731 if (!CHIP_IS_E1x(sc)) {
9732 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ,
9737 /* get device info and set params */
9738 if (bnx2x_get_device_info(sc) != 0) {
9739 PMD_DRV_LOG(NOTICE, sc, "getting device info");
9743 /* get phy settings from shmem and 'and' against admin settings */
9744 bnx2x_get_phy_info(sc);
9746 /* Left mac of VF unfilled, PF should set it for VF */
9747 memset(sc->link_params.mac_addr, 0, ETHER_ADDR_LEN);
9752 /* set the default MTU (changed via ifconfig) */
9753 sc->mtu = ETHER_MTU;
9755 bnx2x_set_modes_bitmap(sc);
9757 /* need to reset chip if UNDI was active */
9758 if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
9761 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
9762 DRV_MSG_SEQ_NUMBER_MASK);
9763 PMD_DRV_LOG(DEBUG, sc, "prev unload fw_seq 0x%04x",
9765 bnx2x_prev_unload(sc);
9768 bnx2x_dcbx_set_state(sc, FALSE, BNX2X_DCBX_ENABLED_OFF);
9770 /* calculate qm_cid_count */
9771 sc->qm_cid_count = bnx2x_set_qm_cid_count(sc);
9774 bnx2x_init_multi_cos(sc);
9780 bnx2x_igu_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t segment,
9781 uint16_t index, uint8_t op, uint8_t update)
9783 uint32_t igu_addr = sc->igu_base_addr;
9784 igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
9785 bnx2x_igu_ack_sb_gen(sc, segment, index, op, update, igu_addr);
9789 bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t storm,
9790 uint16_t index, uint8_t op, uint8_t update)
9792 if (unlikely(sc->devinfo.int_block == INT_BLOCK_HC))
9793 bnx2x_hc_ack_sb(sc, igu_sb_id, storm, index, op, update);
9796 if (CHIP_INT_MODE_IS_BC(sc)) {
9798 } else if (igu_sb_id != sc->igu_dsb_id) {
9799 segment = IGU_SEG_ACCESS_DEF;
9800 } else if (storm == ATTENTION_ID) {
9801 segment = IGU_SEG_ACCESS_ATTN;
9803 segment = IGU_SEG_ACCESS_DEF;
9805 bnx2x_igu_ack_sb(sc, igu_sb_id, segment, index, op, update);
9810 bnx2x_igu_clear_sb_gen(struct bnx2x_softc *sc, uint8_t func, uint8_t idu_sb_id,
9813 uint32_t data, ctl, cnt = 100;
9814 uint32_t igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
9815 uint32_t igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
9816 uint32_t igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP +
9817 (idu_sb_id / 32) * 4;
9818 uint32_t sb_bit = 1 << (idu_sb_id % 32);
9819 uint32_t func_encode = func |
9820 (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
9821 uint32_t addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
9823 /* Not supported in BC mode */
9824 if (CHIP_INT_MODE_IS_BC(sc)) {
9828 data = ((IGU_USE_REGISTER_cstorm_type_0_sb_cleanup <<
9829 IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
9830 IGU_REGULAR_CLEANUP_SET | IGU_REGULAR_BCLEANUP);
9832 ctl = ((addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT) |
9833 (func_encode << IGU_CTRL_REG_FID_SHIFT) |
9834 (IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT));
9836 REG_WR(sc, igu_addr_data, data);
9840 PMD_DRV_LOG(DEBUG, sc, "write 0x%08x to IGU(via GRC) addr 0x%x",
9842 REG_WR(sc, igu_addr_ctl, ctl);
9846 /* wait for clean up to finish */
9847 while (!(REG_RD(sc, igu_addr_ack) & sb_bit) && --cnt) {
9851 if (!(REG_RD(sc, igu_addr_ack) & sb_bit)) {
9852 PMD_DRV_LOG(DEBUG, sc,
9853 "Unable to finish IGU cleanup: "
9854 "idu_sb_id %d offset %d bit %d (cnt %d)",
9855 idu_sb_id, idu_sb_id / 32, idu_sb_id % 32, cnt);
9859 static void bnx2x_igu_clear_sb(struct bnx2x_softc *sc, uint8_t idu_sb_id)
9861 bnx2x_igu_clear_sb_gen(sc, SC_FUNC(sc), idu_sb_id, TRUE /*PF*/);
9864 /*******************/
9865 /* ECORE CALLBACKS */
9866 /*******************/
9868 static void bnx2x_reset_common(struct bnx2x_softc *sc)
9870 uint32_t val = 0x1400;
9872 PMD_INIT_FUNC_TRACE(sc);
9875 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR),
9878 if (CHIP_IS_E3(sc)) {
9879 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
9880 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
9883 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR), val);
9886 static void bnx2x_common_init_phy(struct bnx2x_softc *sc)
9888 uint32_t shmem_base[2];
9889 uint32_t shmem2_base[2];
9891 /* Avoid common init in case MFW supports LFA */
9892 if (SHMEM2_RD(sc, size) >
9893 (uint32_t) offsetof(struct shmem2_region,
9894 lfa_host_addr[SC_PORT(sc)])) {
9898 shmem_base[0] = sc->devinfo.shmem_base;
9899 shmem2_base[0] = sc->devinfo.shmem2_base;
9901 if (!CHIP_IS_E1x(sc)) {
9902 shmem_base[1] = SHMEM2_RD(sc, other_shmem_base_addr);
9903 shmem2_base[1] = SHMEM2_RD(sc, other_shmem2_base_addr);
9906 bnx2x_acquire_phy_lock(sc);
9907 elink_common_init_phy(sc, shmem_base, shmem2_base,
9908 sc->devinfo.chip_id, 0);
9909 bnx2x_release_phy_lock(sc);
9912 static void bnx2x_pf_disable(struct bnx2x_softc *sc)
9914 uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
9916 val &= ~IGU_PF_CONF_FUNC_EN;
9918 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
9919 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
9920 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 0);
9923 static void bnx2x_init_pxp(struct bnx2x_softc *sc)
9926 int r_order, w_order;
9928 devctl = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_CTL);
9930 w_order = ((devctl & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5);
9931 r_order = ((devctl & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12);
9933 ecore_init_pxp_arb(sc, r_order, w_order);
9936 static uint32_t bnx2x_get_pretend_reg(struct bnx2x_softc *sc)
9938 uint32_t base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9939 uint32_t stride = (PXP2_REG_PGL_PRETEND_FUNC_F1 - base);
9940 return base + (SC_ABS_FUNC(sc)) * stride;
9944 * Called only on E1H or E2.
9945 * When pretending to be PF, the pretend value is the function number 0..7.
9946 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
9949 static int bnx2x_pretend_func(struct bnx2x_softc *sc, uint16_t pretend_func_val)
9951 uint32_t pretend_reg;
9953 if (CHIP_IS_E1H(sc) && (pretend_func_val > E1H_FUNC_MAX))
9956 /* get my own pretend register */
9957 pretend_reg = bnx2x_get_pretend_reg(sc);
9958 REG_WR(sc, pretend_reg, pretend_func_val);
9959 REG_RD(sc, pretend_reg);
9963 static void bnx2x_setup_fan_failure_detection(struct bnx2x_softc *sc)
9970 val = (SHMEM_RD(sc, dev_info.shared_hw_config.config2) &
9971 SHARED_HW_CFG_FAN_FAILURE_MASK);
9973 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) {
9977 * The fan failure mechanism is usually related to the PHY type since
9978 * the power consumption of the board is affected by the PHY. Currently,
9979 * fan is required for most designs with SFX7101, BNX2X8727 and BNX2X8481.
9981 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) {
9982 for (port = PORT_0; port < PORT_MAX; port++) {
9983 is_required |= elink_fan_failure_det_req(sc,
9987 devinfo.shmem2_base,
9992 if (is_required == 0) {
9996 /* Fan failure is indicated by SPIO 5 */
9997 bnx2x_set_spio(sc, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
9999 /* set to active low mode */
10000 val = REG_RD(sc, MISC_REG_SPIO_INT);
10001 val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
10002 REG_WR(sc, MISC_REG_SPIO_INT, val);
10004 /* enable interrupt to signal the IGU */
10005 val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
10006 val |= MISC_SPIO_SPIO5;
10007 REG_WR(sc, MISC_REG_SPIO_EVENT_EN, val);
10010 static void bnx2x_enable_blocks_attention(struct bnx2x_softc *sc)
10014 REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0);
10015 if (!CHIP_IS_E1x(sc)) {
10016 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0x40);
10018 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0);
10020 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
10021 REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
10023 * mask read length error interrupts in brb for parser
10024 * (parsing unit and 'checksum and crc' unit)
10025 * these errors are legal (PU reads fixed length and CAC can cause
10026 * read length error on truncated packets)
10028 REG_WR(sc, BRB1_REG_BRB1_INT_MASK, 0xFC00);
10029 REG_WR(sc, QM_REG_QM_INT_MASK, 0);
10030 REG_WR(sc, TM_REG_TM_INT_MASK, 0);
10031 REG_WR(sc, XSDM_REG_XSDM_INT_MASK_0, 0);
10032 REG_WR(sc, XSDM_REG_XSDM_INT_MASK_1, 0);
10033 REG_WR(sc, XCM_REG_XCM_INT_MASK, 0);
10034 /* REG_WR(sc, XSEM_REG_XSEM_INT_MASK_0, 0); */
10035 /* REG_WR(sc, XSEM_REG_XSEM_INT_MASK_1, 0); */
10036 REG_WR(sc, USDM_REG_USDM_INT_MASK_0, 0);
10037 REG_WR(sc, USDM_REG_USDM_INT_MASK_1, 0);
10038 REG_WR(sc, UCM_REG_UCM_INT_MASK, 0);
10039 /* REG_WR(sc, USEM_REG_USEM_INT_MASK_0, 0); */
10040 /* REG_WR(sc, USEM_REG_USEM_INT_MASK_1, 0); */
10041 REG_WR(sc, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
10042 REG_WR(sc, CSDM_REG_CSDM_INT_MASK_0, 0);
10043 REG_WR(sc, CSDM_REG_CSDM_INT_MASK_1, 0);
10044 REG_WR(sc, CCM_REG_CCM_INT_MASK, 0);
10045 /* REG_WR(sc, CSEM_REG_CSEM_INT_MASK_0, 0); */
10046 /* REG_WR(sc, CSEM_REG_CSEM_INT_MASK_1, 0); */
10048 val = (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
10049 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
10050 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN);
10051 if (!CHIP_IS_E1x(sc)) {
10052 val |= (PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
10053 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED);
10055 REG_WR(sc, PXP2_REG_PXP2_INT_MASK_0, val);
10057 REG_WR(sc, TSDM_REG_TSDM_INT_MASK_0, 0);
10058 REG_WR(sc, TSDM_REG_TSDM_INT_MASK_1, 0);
10059 REG_WR(sc, TCM_REG_TCM_INT_MASK, 0);
10060 /* REG_WR(sc, TSEM_REG_TSEM_INT_MASK_0, 0); */
10062 if (!CHIP_IS_E1x(sc)) {
10063 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
10064 REG_WR(sc, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
10067 REG_WR(sc, CDU_REG_CDU_INT_MASK, 0);
10068 REG_WR(sc, DMAE_REG_DMAE_INT_MASK, 0);
10069 /* REG_WR(sc, MISC_REG_MISC_INT_MASK, 0); */
10070 REG_WR(sc, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
10074 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
10076 * @sc: driver handle
10078 static int bnx2x_init_hw_common(struct bnx2x_softc *sc)
10080 uint8_t abs_func_id;
10083 PMD_DRV_LOG(DEBUG, sc,
10084 "starting common init for func %d", SC_ABS_FUNC(sc));
10087 * take the RESET lock to protect undi_unload flow from accessing
10088 * registers while we are resetting the chip
10090 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10092 bnx2x_reset_common(sc);
10094 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET), 0xffffffff);
10097 if (CHIP_IS_E3(sc)) {
10098 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
10099 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
10102 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET), val);
10104 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10106 ecore_init_block(sc, BLOCK_MISC, PHASE_COMMON);
10108 if (!CHIP_IS_E1x(sc)) {
10110 * 4-port mode or 2-port mode we need to turn off master-enable for
10111 * everyone. After that we turn it back on for self. So, we disregard
10112 * multi-function, and always disable all functions on the given path,
10113 * this means 0,2,4,6 for path 0 and 1,3,5,7 for path 1
10115 for (abs_func_id = SC_PATH(sc);
10116 abs_func_id < (E2_FUNC_MAX * 2); abs_func_id += 2) {
10117 if (abs_func_id == SC_ABS_FUNC(sc)) {
10119 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
10124 bnx2x_pretend_func(sc, abs_func_id);
10126 /* clear pf enable */
10127 bnx2x_pf_disable(sc);
10129 bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10133 ecore_init_block(sc, BLOCK_PXP, PHASE_COMMON);
10135 ecore_init_block(sc, BLOCK_PXP2, PHASE_COMMON);
10136 bnx2x_init_pxp(sc);
10138 #ifdef __BIG_ENDIAN
10139 REG_WR(sc, PXP2_REG_RQ_QM_ENDIAN_M, 1);
10140 REG_WR(sc, PXP2_REG_RQ_TM_ENDIAN_M, 1);
10141 REG_WR(sc, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
10142 REG_WR(sc, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
10143 REG_WR(sc, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
10144 /* make sure this value is 0 */
10145 REG_WR(sc, PXP2_REG_RQ_HC_ENDIAN_M, 0);
10147 //REG_WR(sc, PXP2_REG_RD_PBF_SWAP_MODE, 1);
10148 REG_WR(sc, PXP2_REG_RD_QM_SWAP_MODE, 1);
10149 REG_WR(sc, PXP2_REG_RD_TM_SWAP_MODE, 1);
10150 REG_WR(sc, PXP2_REG_RD_SRC_SWAP_MODE, 1);
10151 REG_WR(sc, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
10154 ecore_ilt_init_page_size(sc, INITOP_SET);
10156 if (CHIP_REV_IS_FPGA(sc) && CHIP_IS_E1H(sc)) {
10157 REG_WR(sc, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
10160 /* let the HW do it's magic... */
10163 /* finish PXP init */
10165 val = REG_RD(sc, PXP2_REG_RQ_CFG_DONE);
10167 PMD_DRV_LOG(NOTICE, sc, "PXP2 CFG failed");
10170 val = REG_RD(sc, PXP2_REG_RD_INIT_DONE);
10172 PMD_DRV_LOG(NOTICE, sc, "PXP2 RD_INIT failed");
10177 * Timer bug workaround for E2 only. We need to set the entire ILT to have
10178 * entries with value "0" and valid bit on. This needs to be done by the
10179 * first PF that is loaded in a path (i.e. common phase)
10181 if (!CHIP_IS_E1x(sc)) {
10183 * In E2 there is a bug in the timers block that can cause function 6 / 7
10184 * (i.e. vnic3) to start even if it is marked as "scan-off".
10185 * This occurs when a different function (func2,3) is being marked
10186 * as "scan-off". Real-life scenario for example: if a driver is being
10187 * load-unloaded while func6,7 are down. This will cause the timer to access
10188 * the ilt, translate to a logical address and send a request to read/write.
10189 * Since the ilt for the function that is down is not valid, this will cause
10190 * a translation error which is unrecoverable.
10191 * The Workaround is intended to make sure that when this happens nothing
10192 * fatal will occur. The workaround:
10193 * 1. First PF driver which loads on a path will:
10194 * a. After taking the chip out of reset, by using pretend,
10195 * it will write "0" to the following registers of
10197 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10198 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
10199 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
10200 * And for itself it will write '1' to
10201 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
10202 * dmae-operations (writing to pram for example.)
10203 * note: can be done for only function 6,7 but cleaner this
10205 * b. Write zero+valid to the entire ILT.
10206 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
10207 * VNIC3 (of that port). The range allocated will be the
10208 * entire ILT. This is needed to prevent ILT range error.
10209 * 2. Any PF driver load flow:
10210 * a. ILT update with the physical addresses of the allocated
10212 * b. Wait 20msec. - note that this timeout is needed to make
10213 * sure there are no requests in one of the PXP internal
10214 * queues with "old" ILT addresses.
10215 * c. PF enable in the PGLC.
10216 * d. Clear the was_error of the PF in the PGLC. (could have
10217 * occurred while driver was down)
10218 * e. PF enable in the CFC (WEAK + STRONG)
10219 * f. Timers scan enable
10220 * 3. PF driver unload flow:
10221 * a. Clear the Timers scan_en.
10222 * b. Polling for scan_on=0 for that PF.
10223 * c. Clear the PF enable bit in the PXP.
10224 * d. Clear the PF enable in the CFC (WEAK + STRONG)
10225 * e. Write zero+valid to all ILT entries (The valid bit must
10227 * f. If this is VNIC 3 of a port then also init
10228 * first_timers_ilt_entry to zero and last_timers_ilt_entry
10229 * to the last enrty in the ILT.
10232 * Currently the PF error in the PGLC is non recoverable.
10233 * In the future the there will be a recovery routine for this error.
10234 * Currently attention is masked.
10235 * Having an MCP lock on the load/unload process does not guarantee that
10236 * there is no Timer disable during Func6/7 enable. This is because the
10237 * Timers scan is currently being cleared by the MCP on FLR.
10238 * Step 2.d can be done only for PF6/7 and the driver can also check if
10239 * there is error before clearing it. But the flow above is simpler and
10241 * All ILT entries are written by zero+valid and not just PF6/7
10242 * ILT entries since in the future the ILT entries allocation for
10243 * PF-s might be dynamic.
10245 struct ilt_client_info ilt_cli;
10246 struct ecore_ilt ilt;
10248 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
10249 memset(&ilt, 0, sizeof(struct ecore_ilt));
10251 /* initialize dummy TM client */
10253 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
10254 ilt_cli.client_num = ILT_CLIENT_TM;
10257 * Step 1: set zeroes to all ilt page entries with valid bit on
10258 * Step 2: set the timers first/last ilt entry to point
10259 * to the entire range to prevent ILT range error for 3rd/4th
10260 * vnic (this code assumes existence of the vnic)
10262 * both steps performed by call to ecore_ilt_client_init_op()
10263 * with dummy TM client
10265 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
10266 * and his brother are split registers
10269 bnx2x_pretend_func(sc, (SC_PATH(sc) + 6));
10270 ecore_ilt_client_init_op_ilt(sc, &ilt, &ilt_cli, INITOP_CLEAR);
10271 bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10273 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
10274 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
10275 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
10278 REG_WR(sc, PXP2_REG_RQ_DISABLE_INPUTS, 0);
10279 REG_WR(sc, PXP2_REG_RD_DISABLE_INPUTS, 0);
10281 if (!CHIP_IS_E1x(sc)) {
10284 ecore_init_block(sc, BLOCK_PGLUE_B, PHASE_COMMON);
10285 ecore_init_block(sc, BLOCK_ATC, PHASE_COMMON);
10287 /* let the HW do it's magic... */
10290 val = REG_RD(sc, ATC_REG_ATC_INIT_DONE);
10291 } while (factor-- && (val != 1));
10294 PMD_DRV_LOG(NOTICE, sc, "ATC_INIT failed");
10299 ecore_init_block(sc, BLOCK_DMAE, PHASE_COMMON);
10301 /* clean the DMAE memory */
10302 sc->dmae_ready = 1;
10303 ecore_init_fill(sc, TSEM_REG_PRAM, 0, 8);
10305 ecore_init_block(sc, BLOCK_TCM, PHASE_COMMON);
10307 ecore_init_block(sc, BLOCK_UCM, PHASE_COMMON);
10309 ecore_init_block(sc, BLOCK_CCM, PHASE_COMMON);
10311 ecore_init_block(sc, BLOCK_XCM, PHASE_COMMON);
10313 bnx2x_read_dmae(sc, XSEM_REG_PASSIVE_BUFFER, 3);
10314 bnx2x_read_dmae(sc, CSEM_REG_PASSIVE_BUFFER, 3);
10315 bnx2x_read_dmae(sc, TSEM_REG_PASSIVE_BUFFER, 3);
10316 bnx2x_read_dmae(sc, USEM_REG_PASSIVE_BUFFER, 3);
10318 ecore_init_block(sc, BLOCK_QM, PHASE_COMMON);
10320 /* QM queues pointers table */
10321 ecore_qm_init_ptr_table(sc, sc->qm_cid_count, INITOP_SET);
10323 /* soft reset pulse */
10324 REG_WR(sc, QM_REG_SOFT_RESET, 1);
10325 REG_WR(sc, QM_REG_SOFT_RESET, 0);
10327 if (CNIC_SUPPORT(sc))
10328 ecore_init_block(sc, BLOCK_TM, PHASE_COMMON);
10330 ecore_init_block(sc, BLOCK_DORQ, PHASE_COMMON);
10331 REG_WR(sc, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
10333 if (!CHIP_REV_IS_SLOW(sc)) {
10334 /* enable hw interrupt from doorbell Q */
10335 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
10338 ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON);
10340 ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON);
10341 REG_WR(sc, PRS_REG_A_PRSU_20, 0xf);
10342 REG_WR(sc, PRS_REG_E1HOV_MODE, sc->devinfo.mf_info.path_has_ovlan);
10344 if (!CHIP_IS_E1x(sc) && !CHIP_IS_E3B0(sc)) {
10345 if (IS_MF_AFEX(sc)) {
10347 * configure that AFEX and VLAN headers must be
10348 * received in AFEX mode
10350 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC, 0xE);
10351 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS, 0xA);
10352 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
10353 REG_WR(sc, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
10354 REG_WR(sc, PRS_REG_TAG_LEN_0, 0x4);
10357 * Bit-map indicating which L2 hdrs may appear
10358 * after the basic Ethernet header
10360 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC,
10361 sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10365 ecore_init_block(sc, BLOCK_TSDM, PHASE_COMMON);
10366 ecore_init_block(sc, BLOCK_CSDM, PHASE_COMMON);
10367 ecore_init_block(sc, BLOCK_USDM, PHASE_COMMON);
10368 ecore_init_block(sc, BLOCK_XSDM, PHASE_COMMON);
10370 if (!CHIP_IS_E1x(sc)) {
10371 /* reset VFC memories */
10372 REG_WR(sc, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10373 VFC_MEMORIES_RST_REG_CAM_RST |
10374 VFC_MEMORIES_RST_REG_RAM_RST);
10375 REG_WR(sc, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10376 VFC_MEMORIES_RST_REG_CAM_RST |
10377 VFC_MEMORIES_RST_REG_RAM_RST);
10382 ecore_init_block(sc, BLOCK_TSEM, PHASE_COMMON);
10383 ecore_init_block(sc, BLOCK_USEM, PHASE_COMMON);
10384 ecore_init_block(sc, BLOCK_CSEM, PHASE_COMMON);
10385 ecore_init_block(sc, BLOCK_XSEM, PHASE_COMMON);
10387 /* sync semi rtc */
10388 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x80000000);
10389 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x80000000);
10391 ecore_init_block(sc, BLOCK_UPB, PHASE_COMMON);
10392 ecore_init_block(sc, BLOCK_XPB, PHASE_COMMON);
10393 ecore_init_block(sc, BLOCK_PBF, PHASE_COMMON);
10395 if (!CHIP_IS_E1x(sc)) {
10396 if (IS_MF_AFEX(sc)) {
10398 * configure that AFEX and VLAN headers must be
10399 * sent in AFEX mode
10401 REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC, 0xE);
10402 REG_WR(sc, PBF_REG_MUST_HAVE_HDRS, 0xA);
10403 REG_WR(sc, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
10404 REG_WR(sc, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
10405 REG_WR(sc, PBF_REG_TAG_LEN_0, 0x4);
10407 REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC,
10408 sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10412 REG_WR(sc, SRC_REG_SOFT_RST, 1);
10414 ecore_init_block(sc, BLOCK_SRC, PHASE_COMMON);
10416 if (CNIC_SUPPORT(sc)) {
10417 REG_WR(sc, SRC_REG_KEYSEARCH_0, 0x63285672);
10418 REG_WR(sc, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
10419 REG_WR(sc, SRC_REG_KEYSEARCH_2, 0x223aef9b);
10420 REG_WR(sc, SRC_REG_KEYSEARCH_3, 0x26001e3a);
10421 REG_WR(sc, SRC_REG_KEYSEARCH_4, 0x7ae91116);
10422 REG_WR(sc, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
10423 REG_WR(sc, SRC_REG_KEYSEARCH_6, 0x298d8adf);
10424 REG_WR(sc, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
10425 REG_WR(sc, SRC_REG_KEYSEARCH_8, 0x1830f82f);
10426 REG_WR(sc, SRC_REG_KEYSEARCH_9, 0x01e46be7);
10428 REG_WR(sc, SRC_REG_SOFT_RST, 0);
10430 if (sizeof(union cdu_context) != 1024) {
10431 /* we currently assume that a context is 1024 bytes */
10432 PMD_DRV_LOG(NOTICE, sc,
10433 "please adjust the size of cdu_context(%ld)",
10434 (long)sizeof(union cdu_context));
10437 ecore_init_block(sc, BLOCK_CDU, PHASE_COMMON);
10438 val = (4 << 24) + (0 << 12) + 1024;
10439 REG_WR(sc, CDU_REG_CDU_GLOBAL_PARAMS, val);
10441 ecore_init_block(sc, BLOCK_CFC, PHASE_COMMON);
10443 REG_WR(sc, CFC_REG_INIT_REG, 0x7FF);
10444 /* enable context validation interrupt from CFC */
10445 REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
10447 /* set the thresholds to prevent CFC/CDU race */
10448 REG_WR(sc, CFC_REG_DEBUG0, 0x20020000);
10449 ecore_init_block(sc, BLOCK_HC, PHASE_COMMON);
10451 if (!CHIP_IS_E1x(sc) && BNX2X_NOMCP(sc)) {
10452 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x36);
10455 ecore_init_block(sc, BLOCK_IGU, PHASE_COMMON);
10456 ecore_init_block(sc, BLOCK_MISC_AEU, PHASE_COMMON);
10458 /* Reset PCIE errors for debug */
10459 REG_WR(sc, 0x2814, 0xffffffff);
10460 REG_WR(sc, 0x3820, 0xffffffff);
10462 if (!CHIP_IS_E1x(sc)) {
10463 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
10464 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
10465 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
10466 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
10467 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
10468 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
10469 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
10470 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
10471 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
10472 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
10473 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
10476 ecore_init_block(sc, BLOCK_NIG, PHASE_COMMON);
10478 /* in E3 this done in per-port section */
10479 if (!CHIP_IS_E3(sc))
10480 REG_WR(sc, NIG_REG_LLH_MF_MODE, IS_MF(sc));
10482 if (CHIP_IS_E1H(sc)) {
10483 /* not applicable for E2 (and above ...) */
10484 REG_WR(sc, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(sc));
10487 if (CHIP_REV_IS_SLOW(sc)) {
10491 /* finish CFC init */
10492 val = reg_poll(sc, CFC_REG_LL_INIT_DONE, 1, 100, 10);
10494 PMD_DRV_LOG(NOTICE, sc, "CFC LL_INIT failed");
10497 val = reg_poll(sc, CFC_REG_AC_INIT_DONE, 1, 100, 10);
10499 PMD_DRV_LOG(NOTICE, sc, "CFC AC_INIT failed");
10502 val = reg_poll(sc, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
10504 PMD_DRV_LOG(NOTICE, sc, "CFC CAM_INIT failed");
10507 REG_WR(sc, CFC_REG_DEBUG0, 0);
10509 bnx2x_setup_fan_failure_detection(sc);
10511 /* clear PXP2 attentions */
10512 REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
10514 bnx2x_enable_blocks_attention(sc);
10516 if (!CHIP_REV_IS_SLOW(sc)) {
10517 ecore_enable_blocks_parity(sc);
10520 if (!BNX2X_NOMCP(sc)) {
10521 if (CHIP_IS_E1x(sc)) {
10522 bnx2x_common_init_phy(sc);
10530 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
10532 * @sc: driver handle
10534 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc)
10536 int rc = bnx2x_init_hw_common(sc);
10542 /* In E2 2-PORT mode, same ext phy is used for the two paths */
10543 if (!BNX2X_NOMCP(sc)) {
10544 bnx2x_common_init_phy(sc);
10550 static int bnx2x_init_hw_port(struct bnx2x_softc *sc)
10552 int port = SC_PORT(sc);
10553 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
10554 uint32_t low, high;
10557 PMD_DRV_LOG(DEBUG, sc, "starting port init for port %d", port);
10559 REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
10561 ecore_init_block(sc, BLOCK_MISC, init_phase);
10562 ecore_init_block(sc, BLOCK_PXP, init_phase);
10563 ecore_init_block(sc, BLOCK_PXP2, init_phase);
10566 * Timers bug workaround: disables the pf_master bit in pglue at
10567 * common phase, we need to enable it here before any dmae access are
10568 * attempted. Therefore we manually added the enable-master to the
10569 * port phase (it also happens in the function phase)
10571 if (!CHIP_IS_E1x(sc)) {
10572 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
10575 ecore_init_block(sc, BLOCK_ATC, init_phase);
10576 ecore_init_block(sc, BLOCK_DMAE, init_phase);
10577 ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
10578 ecore_init_block(sc, BLOCK_QM, init_phase);
10580 ecore_init_block(sc, BLOCK_TCM, init_phase);
10581 ecore_init_block(sc, BLOCK_UCM, init_phase);
10582 ecore_init_block(sc, BLOCK_CCM, init_phase);
10583 ecore_init_block(sc, BLOCK_XCM, init_phase);
10585 /* QM cid (connection) count */
10586 ecore_qm_init_cid_count(sc, sc->qm_cid_count, INITOP_SET);
10588 if (CNIC_SUPPORT(sc)) {
10589 ecore_init_block(sc, BLOCK_TM, init_phase);
10590 REG_WR(sc, TM_REG_LIN0_SCAN_TIME + port * 4, 20);
10591 REG_WR(sc, TM_REG_LIN0_MAX_ACTIVE_CID + port * 4, 31);
10594 ecore_init_block(sc, BLOCK_DORQ, init_phase);
10596 ecore_init_block(sc, BLOCK_BRB1, init_phase);
10598 if (CHIP_IS_E1H(sc)) {
10600 low = (BNX2X_ONE_PORT(sc) ? 160 : 246);
10601 } else if (sc->mtu > 4096) {
10602 if (BNX2X_ONE_PORT(sc)) {
10606 /* (24*1024 + val*4)/256 */
10607 low = (96 + (val / 64) + ((val % 64) ? 1 : 0));
10610 low = (BNX2X_ONE_PORT(sc) ? 80 : 160);
10612 high = (low + 56); /* 14*1024/256 */
10613 REG_WR(sc, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port * 4, low);
10614 REG_WR(sc, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port * 4, high);
10617 if (CHIP_IS_MODE_4_PORT(sc)) {
10618 REG_WR(sc, SC_PORT(sc) ?
10619 BRB1_REG_MAC_GUARANTIED_1 :
10620 BRB1_REG_MAC_GUARANTIED_0, 40);
10623 ecore_init_block(sc, BLOCK_PRS, init_phase);
10624 if (CHIP_IS_E3B0(sc)) {
10625 if (IS_MF_AFEX(sc)) {
10626 /* configure headers for AFEX mode */
10628 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_1,
10630 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_1,
10632 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_1, 0xA);
10634 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10636 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_0,
10638 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
10641 /* Ovlan exists only if we are in multi-function +
10642 * switch-dependent mode, in switch-independent there
10643 * is no ovlan headers
10645 REG_WR(sc, SC_PORT(sc) ?
10646 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
10647 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10648 (sc->devinfo.mf_info.path_has_ovlan ? 7 : 6));
10652 ecore_init_block(sc, BLOCK_TSDM, init_phase);
10653 ecore_init_block(sc, BLOCK_CSDM, init_phase);
10654 ecore_init_block(sc, BLOCK_USDM, init_phase);
10655 ecore_init_block(sc, BLOCK_XSDM, init_phase);
10657 ecore_init_block(sc, BLOCK_TSEM, init_phase);
10658 ecore_init_block(sc, BLOCK_USEM, init_phase);
10659 ecore_init_block(sc, BLOCK_CSEM, init_phase);
10660 ecore_init_block(sc, BLOCK_XSEM, init_phase);
10662 ecore_init_block(sc, BLOCK_UPB, init_phase);
10663 ecore_init_block(sc, BLOCK_XPB, init_phase);
10665 ecore_init_block(sc, BLOCK_PBF, init_phase);
10667 if (CHIP_IS_E1x(sc)) {
10668 /* configure PBF to work without PAUSE mtu 9000 */
10669 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 0);
10671 /* update threshold */
10672 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, (9040 / 16));
10673 /* update init credit */
10674 REG_WR(sc, PBF_REG_P0_INIT_CRD + port * 4,
10675 (9040 / 16) + 553 - 22);
10677 /* probe changes */
10678 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 1);
10680 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0);
10683 if (CNIC_SUPPORT(sc)) {
10684 ecore_init_block(sc, BLOCK_SRC, init_phase);
10687 ecore_init_block(sc, BLOCK_CDU, init_phase);
10688 ecore_init_block(sc, BLOCK_CFC, init_phase);
10689 ecore_init_block(sc, BLOCK_HC, init_phase);
10690 ecore_init_block(sc, BLOCK_IGU, init_phase);
10691 ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
10692 /* init aeu_mask_attn_func_0/1:
10693 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
10694 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
10695 * bits 4-7 are used for "per vn group attention" */
10696 val = IS_MF(sc) ? 0xF7 : 0x7;
10698 REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, val);
10700 ecore_init_block(sc, BLOCK_NIG, init_phase);
10702 if (!CHIP_IS_E1x(sc)) {
10703 /* Bit-map indicating which L2 hdrs may appear after the
10704 * basic Ethernet header
10706 if (IS_MF_AFEX(sc)) {
10707 REG_WR(sc, SC_PORT(sc) ?
10708 NIG_REG_P1_HDRS_AFTER_BASIC :
10709 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
10711 REG_WR(sc, SC_PORT(sc) ?
10712 NIG_REG_P1_HDRS_AFTER_BASIC :
10713 NIG_REG_P0_HDRS_AFTER_BASIC,
10714 IS_MF_SD(sc) ? 7 : 6);
10717 if (CHIP_IS_E3(sc)) {
10718 REG_WR(sc, SC_PORT(sc) ?
10719 NIG_REG_LLH1_MF_MODE :
10720 NIG_REG_LLH_MF_MODE, IS_MF(sc));
10723 if (!CHIP_IS_E3(sc)) {
10724 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1);
10727 /* 0x2 disable mf_ov, 0x1 enable */
10728 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port * 4,
10729 (IS_MF_SD(sc) ? 0x1 : 0x2));
10731 if (!CHIP_IS_E1x(sc)) {
10733 switch (sc->devinfo.mf_info.mf_mode) {
10734 case MULTI_FUNCTION_SD:
10737 case MULTI_FUNCTION_SI:
10738 case MULTI_FUNCTION_AFEX:
10743 REG_WR(sc, (SC_PORT(sc) ? NIG_REG_LLH1_CLS_TYPE :
10744 NIG_REG_LLH0_CLS_TYPE), val);
10746 REG_WR(sc, NIG_REG_LLFC_ENABLE_0 + port * 4, 0);
10747 REG_WR(sc, NIG_REG_LLFC_OUT_EN_0 + port * 4, 0);
10748 REG_WR(sc, NIG_REG_PAUSE_ENABLE_0 + port * 4, 1);
10750 /* If SPIO5 is set to generate interrupts, enable it for this port */
10751 val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
10752 if (val & MISC_SPIO_SPIO5) {
10753 uint32_t reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
10754 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
10755 val = REG_RD(sc, reg_addr);
10756 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
10757 REG_WR(sc, reg_addr, val);
10764 bnx2x_flr_clnup_reg_poll(struct bnx2x_softc *sc, uint32_t reg,
10765 uint32_t expected, uint32_t poll_count)
10767 uint32_t cur_cnt = poll_count;
10770 while ((val = REG_RD(sc, reg)) != expected && cur_cnt--) {
10771 DELAY(FLR_WAIT_INTERVAL);
10778 bnx2x_flr_clnup_poll_hw_counter(struct bnx2x_softc *sc, uint32_t reg,
10779 __rte_unused const char *msg, uint32_t poll_cnt)
10781 uint32_t val = bnx2x_flr_clnup_reg_poll(sc, reg, 0, poll_cnt);
10784 PMD_DRV_LOG(NOTICE, sc, "%s usage count=%d", msg, val);
10791 /* Common routines with VF FLR cleanup */
10792 static uint32_t bnx2x_flr_clnup_poll_count(struct bnx2x_softc *sc)
10794 /* adjust polling timeout */
10795 if (CHIP_REV_IS_EMUL(sc)) {
10796 return FLR_POLL_CNT * 2000;
10799 if (CHIP_REV_IS_FPGA(sc)) {
10800 return FLR_POLL_CNT * 120;
10803 return FLR_POLL_CNT;
10806 static int bnx2x_poll_hw_usage_counters(struct bnx2x_softc *sc, uint32_t poll_cnt)
10808 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
10809 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10810 CFC_REG_NUM_LCIDS_INSIDE_PF,
10811 "CFC PF usage counter timed out",
10816 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
10817 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10818 DORQ_REG_PF_USAGE_CNT,
10819 "DQ PF usage counter timed out",
10824 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
10825 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10826 QM_REG_PF_USG_CNT_0 + 4 * SC_FUNC(sc),
10827 "QM PF usage counter timed out",
10832 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
10833 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10834 TM_REG_LIN0_VNIC_UC + 4 * SC_PORT(sc),
10835 "Timers VNIC usage counter timed out",
10840 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10841 TM_REG_LIN0_NUM_SCANS +
10843 "Timers NUM_SCANS usage counter timed out",
10848 /* Wait DMAE PF usage counter to zero */
10849 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10850 dmae_reg_go_c[INIT_DMAE_C(sc)],
10851 "DMAE dommand register timed out",
10859 #define OP_GEN_PARAM(param) \
10860 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
10861 #define OP_GEN_TYPE(type) \
10862 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
10863 #define OP_GEN_AGG_VECT(index) \
10864 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
10867 bnx2x_send_final_clnup(struct bnx2x_softc *sc, uint8_t clnup_func,
10870 uint32_t op_gen_command = 0;
10871 uint32_t comp_addr = (BAR_CSTRORM_INTMEM +
10872 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func));
10875 if (REG_RD(sc, comp_addr)) {
10876 PMD_DRV_LOG(NOTICE, sc,
10877 "Cleanup complete was not 0 before sending");
10881 op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
10882 op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
10883 op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
10884 op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
10886 REG_WR(sc, XSDM_REG_OPERATION_GEN, op_gen_command);
10888 if (bnx2x_flr_clnup_reg_poll(sc, comp_addr, 1, poll_cnt) != 1) {
10889 PMD_DRV_LOG(NOTICE, sc, "FW final cleanup did not succeed");
10890 PMD_DRV_LOG(DEBUG, sc, "At timeout completion address contained %x",
10891 (REG_RD(sc, comp_addr)));
10892 rte_panic("FLR cleanup failed");
10896 /* Zero completion for nxt FLR */
10897 REG_WR(sc, comp_addr, 0);
10903 bnx2x_pbf_pN_buf_flushed(struct bnx2x_softc *sc, struct pbf_pN_buf_regs *regs,
10904 uint32_t poll_count)
10906 uint32_t init_crd, crd, crd_start, crd_freed, crd_freed_start;
10907 uint32_t cur_cnt = poll_count;
10909 crd_freed = crd_freed_start = REG_RD(sc, regs->crd_freed);
10910 crd = crd_start = REG_RD(sc, regs->crd);
10911 init_crd = REG_RD(sc, regs->init_crd);
10913 while ((crd != init_crd) &&
10914 ((uint32_t) ((int32_t) crd_freed - (int32_t) crd_freed_start) <
10915 (init_crd - crd_start))) {
10917 DELAY(FLR_WAIT_INTERVAL);
10918 crd = REG_RD(sc, regs->crd);
10919 crd_freed = REG_RD(sc, regs->crd_freed);
10927 bnx2x_pbf_pN_cmd_flushed(struct bnx2x_softc *sc, struct pbf_pN_cmd_regs *regs,
10928 uint32_t poll_count)
10930 uint32_t occup, to_free, freed, freed_start;
10931 uint32_t cur_cnt = poll_count;
10933 occup = to_free = REG_RD(sc, regs->lines_occup);
10934 freed = freed_start = REG_RD(sc, regs->lines_freed);
10937 ((uint32_t) ((int32_t) freed - (int32_t) freed_start) <
10940 DELAY(FLR_WAIT_INTERVAL);
10941 occup = REG_RD(sc, regs->lines_occup);
10942 freed = REG_RD(sc, regs->lines_freed);
10949 static void bnx2x_tx_hw_flushed(struct bnx2x_softc *sc, uint32_t poll_count)
10951 struct pbf_pN_cmd_regs cmd_regs[] = {
10952 {0, (CHIP_IS_E3B0(sc)) ?
10953 PBF_REG_TQ_OCCUPANCY_Q0 : PBF_REG_P0_TQ_OCCUPANCY,
10954 (CHIP_IS_E3B0(sc)) ?
10955 PBF_REG_TQ_LINES_FREED_CNT_Q0 : PBF_REG_P0_TQ_LINES_FREED_CNT},
10956 {1, (CHIP_IS_E3B0(sc)) ?
10957 PBF_REG_TQ_OCCUPANCY_Q1 : PBF_REG_P1_TQ_OCCUPANCY,
10958 (CHIP_IS_E3B0(sc)) ?
10959 PBF_REG_TQ_LINES_FREED_CNT_Q1 : PBF_REG_P1_TQ_LINES_FREED_CNT},
10960 {4, (CHIP_IS_E3B0(sc)) ?
10961 PBF_REG_TQ_OCCUPANCY_LB_Q : PBF_REG_P4_TQ_OCCUPANCY,
10962 (CHIP_IS_E3B0(sc)) ?
10963 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
10964 PBF_REG_P4_TQ_LINES_FREED_CNT}
10967 struct pbf_pN_buf_regs buf_regs[] = {
10968 {0, (CHIP_IS_E3B0(sc)) ?
10969 PBF_REG_INIT_CRD_Q0 : PBF_REG_P0_INIT_CRD,
10970 (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q0 : PBF_REG_P0_CREDIT,
10971 (CHIP_IS_E3B0(sc)) ?
10972 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
10973 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
10974 {1, (CHIP_IS_E3B0(sc)) ?
10975 PBF_REG_INIT_CRD_Q1 : PBF_REG_P1_INIT_CRD,
10976 (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q1 : PBF_REG_P1_CREDIT,
10977 (CHIP_IS_E3B0(sc)) ?
10978 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
10979 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
10980 {4, (CHIP_IS_E3B0(sc)) ?
10981 PBF_REG_INIT_CRD_LB_Q : PBF_REG_P4_INIT_CRD,
10982 (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_LB_Q : PBF_REG_P4_CREDIT,
10983 (CHIP_IS_E3B0(sc)) ?
10984 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
10985 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
10990 /* Verify the command queues are flushed P0, P1, P4 */
10991 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) {
10992 bnx2x_pbf_pN_cmd_flushed(sc, &cmd_regs[i], poll_count);
10995 /* Verify the transmission buffers are flushed P0, P1, P4 */
10996 for (i = 0; i < ARRAY_SIZE(buf_regs); i++) {
10997 bnx2x_pbf_pN_buf_flushed(sc, &buf_regs[i], poll_count);
11001 static void bnx2x_hw_enable_status(struct bnx2x_softc *sc)
11003 __rte_unused uint32_t val;
11005 val = REG_RD(sc, CFC_REG_WEAK_ENABLE_PF);
11006 PMD_DRV_LOG(DEBUG, sc, "CFC_REG_WEAK_ENABLE_PF is 0x%x", val);
11008 val = REG_RD(sc, PBF_REG_DISABLE_PF);
11009 PMD_DRV_LOG(DEBUG, sc, "PBF_REG_DISABLE_PF is 0x%x", val);
11011 val = REG_RD(sc, IGU_REG_PCI_PF_MSI_EN);
11012 PMD_DRV_LOG(DEBUG, sc, "IGU_REG_PCI_PF_MSI_EN is 0x%x", val);
11014 val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_EN);
11015 PMD_DRV_LOG(DEBUG, sc, "IGU_REG_PCI_PF_MSIX_EN is 0x%x", val);
11017 val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
11018 PMD_DRV_LOG(DEBUG, sc, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x", val);
11020 val = REG_RD(sc, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
11021 PMD_DRV_LOG(DEBUG, sc,
11022 "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x", val);
11024 val = REG_RD(sc, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
11025 PMD_DRV_LOG(DEBUG, sc,
11026 "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x", val);
11028 val = REG_RD(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
11029 PMD_DRV_LOG(DEBUG, sc, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x",
11034 * bnx2x_pf_flr_clnup
11035 * a. re-enable target read on the PF
11036 * b. poll cfc per function usgae counter
11037 * c. poll the qm perfunction usage counter
11038 * d. poll the tm per function usage counter
11039 * e. poll the tm per function scan-done indication
11040 * f. clear the dmae channel associated wit hthe PF
11041 * g. zero the igu 'trailing edge' and 'leading edge' regs (attentions)
11042 * h. call the common flr cleanup code with -1 (pf indication)
11044 static int bnx2x_pf_flr_clnup(struct bnx2x_softc *sc)
11046 uint32_t poll_cnt = bnx2x_flr_clnup_poll_count(sc);
11048 /* Re-enable PF target read access */
11049 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
11051 /* Poll HW usage counters */
11052 if (bnx2x_poll_hw_usage_counters(sc, poll_cnt)) {
11056 /* Zero the igu 'trailing edge' and 'leading edge' */
11058 /* Send the FW cleanup command */
11059 if (bnx2x_send_final_clnup(sc, (uint8_t) SC_FUNC(sc), poll_cnt)) {
11065 /* Verify TX hw is flushed */
11066 bnx2x_tx_hw_flushed(sc, poll_cnt);
11068 /* Wait 100ms (not adjusted according to platform) */
11071 /* Verify no pending pci transactions */
11072 if (bnx2x_is_pcie_pending(sc)) {
11073 PMD_DRV_LOG(NOTICE, sc, "PCIE Transactions still pending");
11077 bnx2x_hw_enable_status(sc);
11080 * Master enable - Due to WB DMAE writes performed before this
11081 * register is re-initialized as part of the regular function init
11083 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11088 static int bnx2x_init_hw_func(struct bnx2x_softc *sc)
11090 int port = SC_PORT(sc);
11091 int func = SC_FUNC(sc);
11092 int init_phase = PHASE_PF0 + func;
11093 struct ecore_ilt *ilt = sc->ilt;
11094 uint16_t cdu_ilt_start;
11095 uint32_t addr, val;
11096 uint32_t main_mem_base, main_mem_size, main_mem_prty_clr;
11097 int main_mem_width, rc;
11100 PMD_DRV_LOG(DEBUG, sc, "starting func init for func %d", func);
11103 if (!CHIP_IS_E1x(sc)) {
11104 rc = bnx2x_pf_flr_clnup(sc);
11106 PMD_DRV_LOG(NOTICE, sc, "FLR cleanup failed!");
11111 /* set MSI reconfigure capability */
11112 if (sc->devinfo.int_block == INT_BLOCK_HC) {
11113 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
11114 val = REG_RD(sc, addr);
11115 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
11116 REG_WR(sc, addr, val);
11119 ecore_init_block(sc, BLOCK_PXP, init_phase);
11120 ecore_init_block(sc, BLOCK_PXP2, init_phase);
11123 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
11125 for (i = 0; i < L2_ILT_LINES(sc); i++) {
11126 ilt->lines[cdu_ilt_start + i].page = sc->context[i].vcxt;
11127 ilt->lines[cdu_ilt_start + i].page_mapping =
11128 (rte_iova_t)sc->context[i].vcxt_dma.paddr;
11129 ilt->lines[cdu_ilt_start + i].size = sc->context[i].size;
11131 ecore_ilt_init_op(sc, INITOP_SET);
11133 REG_WR(sc, PRS_REG_NIC_MODE, 1);
11135 if (!CHIP_IS_E1x(sc)) {
11136 uint32_t pf_conf = IGU_PF_CONF_FUNC_EN;
11138 /* Turn on a single ISR mode in IGU if driver is going to use
11141 if ((sc->interrupt_mode != INTR_MODE_MSIX)
11142 || (sc->interrupt_mode != INTR_MODE_SINGLE_MSIX)) {
11143 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
11147 * Timers workaround bug: function init part.
11148 * Need to wait 20msec after initializing ILT,
11149 * needed to make sure there are no requests in
11150 * one of the PXP internal queues with "old" ILT addresses
11155 * Master enable - Due to WB DMAE writes performed before this
11156 * register is re-initialized as part of the regular function
11159 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11160 /* Enable the function in IGU */
11161 REG_WR(sc, IGU_REG_PF_CONFIGURATION, pf_conf);
11164 sc->dmae_ready = 1;
11166 ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
11168 if (!CHIP_IS_E1x(sc))
11169 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
11171 ecore_init_block(sc, BLOCK_ATC, init_phase);
11172 ecore_init_block(sc, BLOCK_DMAE, init_phase);
11173 ecore_init_block(sc, BLOCK_NIG, init_phase);
11174 ecore_init_block(sc, BLOCK_SRC, init_phase);
11175 ecore_init_block(sc, BLOCK_MISC, init_phase);
11176 ecore_init_block(sc, BLOCK_TCM, init_phase);
11177 ecore_init_block(sc, BLOCK_UCM, init_phase);
11178 ecore_init_block(sc, BLOCK_CCM, init_phase);
11179 ecore_init_block(sc, BLOCK_XCM, init_phase);
11180 ecore_init_block(sc, BLOCK_TSEM, init_phase);
11181 ecore_init_block(sc, BLOCK_USEM, init_phase);
11182 ecore_init_block(sc, BLOCK_CSEM, init_phase);
11183 ecore_init_block(sc, BLOCK_XSEM, init_phase);
11185 if (!CHIP_IS_E1x(sc))
11186 REG_WR(sc, QM_REG_PF_EN, 1);
11188 if (!CHIP_IS_E1x(sc)) {
11189 REG_WR(sc, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11190 REG_WR(sc, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11191 REG_WR(sc, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11192 REG_WR(sc, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11194 ecore_init_block(sc, BLOCK_QM, init_phase);
11196 ecore_init_block(sc, BLOCK_TM, init_phase);
11197 ecore_init_block(sc, BLOCK_DORQ, init_phase);
11199 ecore_init_block(sc, BLOCK_BRB1, init_phase);
11200 ecore_init_block(sc, BLOCK_PRS, init_phase);
11201 ecore_init_block(sc, BLOCK_TSDM, init_phase);
11202 ecore_init_block(sc, BLOCK_CSDM, init_phase);
11203 ecore_init_block(sc, BLOCK_USDM, init_phase);
11204 ecore_init_block(sc, BLOCK_XSDM, init_phase);
11205 ecore_init_block(sc, BLOCK_UPB, init_phase);
11206 ecore_init_block(sc, BLOCK_XPB, init_phase);
11207 ecore_init_block(sc, BLOCK_PBF, init_phase);
11208 if (!CHIP_IS_E1x(sc))
11209 REG_WR(sc, PBF_REG_DISABLE_PF, 0);
11211 ecore_init_block(sc, BLOCK_CDU, init_phase);
11213 ecore_init_block(sc, BLOCK_CFC, init_phase);
11215 if (!CHIP_IS_E1x(sc))
11216 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 1);
11219 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
11220 REG_WR(sc, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8, OVLAN(sc));
11223 ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
11225 /* HC init per function */
11226 if (sc->devinfo.int_block == INT_BLOCK_HC) {
11227 if (CHIP_IS_E1H(sc)) {
11228 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11230 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11231 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11233 ecore_init_block(sc, BLOCK_HC, init_phase);
11236 uint32_t num_segs, sb_idx, prod_offset;
11238 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11240 if (!CHIP_IS_E1x(sc)) {
11241 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11242 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11245 ecore_init_block(sc, BLOCK_IGU, init_phase);
11247 if (!CHIP_IS_E1x(sc)) {
11251 * E2 mode: address 0-135 match to the mapping memory;
11252 * 136 - PF0 default prod; 137 - PF1 default prod;
11253 * 138 - PF2 default prod; 139 - PF3 default prod;
11254 * 140 - PF0 attn prod; 141 - PF1 attn prod;
11255 * 142 - PF2 attn prod; 143 - PF3 attn prod;
11256 * 144-147 reserved.
11258 * E1.5 mode - In backward compatible mode;
11259 * for non default SB; each even line in the memory
11260 * holds the U producer and each odd line hold
11261 * the C producer. The first 128 producers are for
11262 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
11263 * producers are for the DSB for each PF.
11264 * Each PF has five segments: (the order inside each
11265 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
11266 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
11267 * 144-147 attn prods;
11269 /* non-default-status-blocks */
11270 num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11271 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
11272 for (sb_idx = 0; sb_idx < sc->igu_sb_cnt; sb_idx++) {
11273 prod_offset = (sc->igu_base_sb + sb_idx) *
11276 for (i = 0; i < num_segs; i++) {
11277 addr = IGU_REG_PROD_CONS_MEMORY +
11278 (prod_offset + i) * 4;
11279 REG_WR(sc, addr, 0);
11281 /* send consumer update with value 0 */
11282 bnx2x_ack_sb(sc, sc->igu_base_sb + sb_idx,
11283 USTORM_ID, 0, IGU_INT_NOP, 1);
11284 bnx2x_igu_clear_sb(sc, sc->igu_base_sb + sb_idx);
11287 /* default-status-blocks */
11288 num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11289 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
11291 if (CHIP_IS_MODE_4_PORT(sc))
11292 dsb_idx = SC_FUNC(sc);
11294 dsb_idx = SC_VN(sc);
11296 prod_offset = (CHIP_INT_MODE_IS_BC(sc) ?
11297 IGU_BC_BASE_DSB_PROD + dsb_idx :
11298 IGU_NORM_BASE_DSB_PROD + dsb_idx);
11301 * igu prods come in chunks of E1HVN_MAX (4) -
11302 * does not matters what is the current chip mode
11304 for (i = 0; i < (num_segs * E1HVN_MAX); i += E1HVN_MAX) {
11305 addr = IGU_REG_PROD_CONS_MEMORY +
11306 (prod_offset + i) * 4;
11307 REG_WR(sc, addr, 0);
11309 /* send consumer update with 0 */
11310 if (CHIP_INT_MODE_IS_BC(sc)) {
11311 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11312 USTORM_ID, 0, IGU_INT_NOP, 1);
11313 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11314 CSTORM_ID, 0, IGU_INT_NOP, 1);
11315 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11316 XSTORM_ID, 0, IGU_INT_NOP, 1);
11317 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11318 TSTORM_ID, 0, IGU_INT_NOP, 1);
11319 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11320 ATTENTION_ID, 0, IGU_INT_NOP, 1);
11322 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11323 USTORM_ID, 0, IGU_INT_NOP, 1);
11324 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11325 ATTENTION_ID, 0, IGU_INT_NOP, 1);
11327 bnx2x_igu_clear_sb(sc, sc->igu_dsb_id);
11329 /* !!! these should become driver const once
11330 rf-tool supports split-68 const */
11331 REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
11332 REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
11333 REG_WR(sc, IGU_REG_SB_MASK_LSB, 0);
11334 REG_WR(sc, IGU_REG_SB_MASK_MSB, 0);
11335 REG_WR(sc, IGU_REG_PBA_STATUS_LSB, 0);
11336 REG_WR(sc, IGU_REG_PBA_STATUS_MSB, 0);
11340 /* Reset PCIE errors for debug */
11341 REG_WR(sc, 0x2114, 0xffffffff);
11342 REG_WR(sc, 0x2120, 0xffffffff);
11344 if (CHIP_IS_E1x(sc)) {
11345 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords */
11346 main_mem_base = HC_REG_MAIN_MEMORY +
11347 SC_PORT(sc) * (main_mem_size * 4);
11348 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
11349 main_mem_width = 8;
11351 val = REG_RD(sc, main_mem_prty_clr);
11353 PMD_DRV_LOG(DEBUG, sc,
11354 "Parity errors in HC block during function init (0x%x)!",
11358 /* Clear "false" parity errors in MSI-X table */
11359 for (i = main_mem_base;
11360 i < main_mem_base + main_mem_size * 4;
11361 i += main_mem_width) {
11362 bnx2x_read_dmae(sc, i, main_mem_width / 4);
11363 bnx2x_write_dmae(sc, BNX2X_SP_MAPPING(sc, wb_data),
11364 i, main_mem_width / 4);
11366 /* Clear HC parity attention */
11367 REG_RD(sc, main_mem_prty_clr);
11370 /* Enable STORMs SP logging */
11371 REG_WR8(sc, BAR_USTRORM_INTMEM +
11372 USTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11373 REG_WR8(sc, BAR_TSTRORM_INTMEM +
11374 TSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11375 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11376 CSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11377 REG_WR8(sc, BAR_XSTRORM_INTMEM +
11378 XSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11380 elink_phy_probe(&sc->link_params);
11385 static void bnx2x_link_reset(struct bnx2x_softc *sc)
11387 if (!BNX2X_NOMCP(sc)) {
11388 bnx2x_acquire_phy_lock(sc);
11389 elink_lfa_reset(&sc->link_params, &sc->link_vars);
11390 bnx2x_release_phy_lock(sc);
11392 if (!CHIP_REV_IS_SLOW(sc)) {
11393 PMD_DRV_LOG(WARNING, sc,
11394 "Bootcode is missing - cannot reset link");
11399 static void bnx2x_reset_port(struct bnx2x_softc *sc)
11401 int port = SC_PORT(sc);
11404 /* reset physical Link */
11405 bnx2x_link_reset(sc);
11407 REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
11409 /* Do not rcv packets to BRB */
11410 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + port * 4, 0x0);
11411 /* Do not direct rcv packets that are not for MCP to the BRB */
11412 REG_WR(sc, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
11413 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
11415 /* Configure AEU */
11416 REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, 0);
11420 /* Check for BRB port occupancy */
11421 val = REG_RD(sc, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port * 4);
11423 PMD_DRV_LOG(DEBUG, sc,
11424 "BRB1 is not empty, %d blocks are occupied", val);
11428 static void bnx2x_ilt_wr(struct bnx2x_softc *sc, uint32_t index, rte_iova_t addr)
11431 uint32_t wb_write[2];
11433 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index * 8;
11435 wb_write[0] = ONCHIP_ADDR1(addr);
11436 wb_write[1] = ONCHIP_ADDR2(addr);
11437 REG_WR_DMAE(sc, reg, wb_write, 2);
11440 static void bnx2x_clear_func_ilt(struct bnx2x_softc *sc, uint32_t func)
11442 uint32_t i, base = FUNC_ILT_BASE(func);
11443 for (i = base; i < base + ILT_PER_FUNC; i++) {
11444 bnx2x_ilt_wr(sc, i, 0);
11448 static void bnx2x_reset_func(struct bnx2x_softc *sc)
11450 struct bnx2x_fastpath *fp;
11451 int port = SC_PORT(sc);
11452 int func = SC_FUNC(sc);
11455 /* Disable the function in the FW */
11456 REG_WR8(sc, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
11457 REG_WR8(sc, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
11458 REG_WR8(sc, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
11459 REG_WR8(sc, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
11462 FOR_EACH_ETH_QUEUE(sc, i) {
11464 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11465 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
11470 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11471 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), SB_DISABLED);
11473 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) {
11474 REG_WR(sc, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
11478 /* Configure IGU */
11479 if (sc->devinfo.int_block == INT_BLOCK_HC) {
11480 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11481 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11483 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11484 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11487 if (CNIC_LOADED(sc)) {
11488 /* Disable Timer scan */
11489 REG_WR(sc, TM_REG_EN_LINEAR0_TIMER + port * 4, 0);
11491 * Wait for at least 10ms and up to 2 second for the timers
11494 for (i = 0; i < 200; i++) {
11496 if (!REG_RD(sc, TM_REG_LIN0_SCAN_ON + port * 4))
11502 bnx2x_clear_func_ilt(sc, func);
11505 * Timers workaround bug for E2: if this is vnic-3,
11506 * we need to set the entire ilt range for this timers.
11508 if (!CHIP_IS_E1x(sc) && SC_VN(sc) == 3) {
11509 struct ilt_client_info ilt_cli;
11510 /* use dummy TM client */
11511 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
11513 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
11514 ilt_cli.client_num = ILT_CLIENT_TM;
11516 ecore_ilt_boundry_init_op(sc, &ilt_cli, 0);
11519 /* this assumes that reset_port() called before reset_func() */
11520 if (!CHIP_IS_E1x(sc)) {
11521 bnx2x_pf_disable(sc);
11524 sc->dmae_ready = 0;
11527 static void bnx2x_release_firmware(struct bnx2x_softc *sc)
11529 rte_free(sc->init_ops);
11530 rte_free(sc->init_ops_offsets);
11531 rte_free(sc->init_data);
11532 rte_free(sc->iro_array);
11535 static int bnx2x_init_firmware(struct bnx2x_softc *sc)
11538 uint8_t *p = sc->firmware;
11541 for (i = 0; i < 24; ++i)
11542 off[i] = rte_be_to_cpu_32(*((uint32_t *) sc->firmware + i));
11545 sc->init_ops = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11548 bnx2x_data_to_init_ops(p + off[1], sc->init_ops, len);
11551 sc->init_ops_offsets = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11552 if (!sc->init_ops_offsets)
11554 bnx2x_data_to_init_offsets(p + off[3], sc->init_ops_offsets, len);
11557 sc->init_data = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11558 if (!sc->init_data)
11560 bnx2x_data_to_init_data(p + off[5], sc->init_data, len);
11562 sc->tsem_int_table_data = p + off[7];
11563 sc->tsem_pram_data = p + off[9];
11564 sc->usem_int_table_data = p + off[11];
11565 sc->usem_pram_data = p + off[13];
11566 sc->csem_int_table_data = p + off[15];
11567 sc->csem_pram_data = p + off[17];
11568 sc->xsem_int_table_data = p + off[19];
11569 sc->xsem_pram_data = p + off[21];
11572 sc->iro_array = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11573 if (!sc->iro_array)
11575 bnx2x_data_to_iro_array(p + off[23], sc->iro_array, len);
11580 bnx2x_release_firmware(sc);
11584 static int cut_gzip_prefix(const uint8_t * zbuf, int len)
11586 #define MIN_PREFIX_SIZE (10)
11588 int n = MIN_PREFIX_SIZE;
11591 if (!(zbuf[0] == 0x1f && zbuf[1] == 0x8b && zbuf[2] == Z_DEFLATED) ||
11592 len <= MIN_PREFIX_SIZE) {
11596 /* optional extra fields are present */
11597 if (zbuf[3] & 0x4) {
11604 /* file name is present */
11605 if (zbuf[3] & 0x8) {
11606 while ((zbuf[n++] != 0) && (n < len)) ;
11612 static int ecore_gunzip(struct bnx2x_softc *sc, const uint8_t * zbuf, int len)
11615 int data_begin = cut_gzip_prefix(zbuf, len);
11617 PMD_DRV_LOG(DEBUG, sc, "ecore_gunzip %d", len);
11619 if (data_begin <= 0) {
11620 PMD_DRV_LOG(NOTICE, sc, "bad gzip prefix");
11624 memset(&zlib_stream, 0, sizeof(zlib_stream));
11625 zlib_stream.next_in = zbuf + data_begin;
11626 zlib_stream.avail_in = len - data_begin;
11627 zlib_stream.next_out = sc->gz_buf;
11628 zlib_stream.avail_out = FW_BUF_SIZE;
11630 ret = inflateInit2(&zlib_stream, -MAX_WBITS);
11632 PMD_DRV_LOG(NOTICE, sc, "zlib inflateInit2 error");
11636 ret = inflate(&zlib_stream, Z_FINISH);
11637 if ((ret != Z_STREAM_END) && (ret != Z_OK)) {
11638 PMD_DRV_LOG(NOTICE, sc, "zlib inflate error: %d %s", ret,
11642 sc->gz_outlen = zlib_stream.total_out;
11643 if (sc->gz_outlen & 0x3) {
11644 PMD_DRV_LOG(NOTICE, sc, "firmware is not aligned. gz_outlen == %d",
11647 sc->gz_outlen >>= 2;
11649 inflateEnd(&zlib_stream);
11651 if (ret == Z_STREAM_END)
11658 ecore_write_dmae_phys_len(struct bnx2x_softc *sc, rte_iova_t phys_addr,
11659 uint32_t addr, uint32_t len)
11661 bnx2x_write_dmae_phys_len(sc, phys_addr, addr, len);
11665 ecore_storm_memset_struct(struct bnx2x_softc *sc, uint32_t addr, size_t size,
11669 for (i = 0; i < size / 4; i++) {
11670 REG_WR(sc, addr + (i * 4), data[i]);
11674 static const char *get_ext_phy_type(uint32_t ext_phy_type)
11676 uint32_t phy_type_idx = ext_phy_type >> 8;
11677 static const char *types[] =
11678 { "DIRECT", "BNX2X-8071", "BNX2X-8072", "BNX2X-8073",
11679 "BNX2X-8705", "BNX2X-8706", "BNX2X-8726", "BNX2X-8481", "SFX-7101",
11681 "BNX2X-8727-NOC", "BNX2X-84823", "NOT_CONN", "FAILURE"
11684 if (phy_type_idx < 12)
11685 return types[phy_type_idx];
11686 else if (PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN == ext_phy_type)
11692 static const char *get_state(uint32_t state)
11694 uint32_t state_idx = state >> 12;
11695 static const char *states[] = { "CLOSED", "OPENING_WAIT4_LOAD",
11696 "OPENING_WAIT4_PORT", "OPEN", "CLOSING_WAIT4_HALT",
11697 "CLOSING_WAIT4_DELETE", "CLOSING_WAIT4_UNLOAD",
11698 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
11699 "UNKNOWN", "DISABLED", "DIAG", "ERROR", "UNDEFINED"
11702 if (state_idx <= 0xF)
11703 return states[state_idx];
11705 return states[0x10];
11708 static const char *get_recovery_state(uint32_t state)
11710 static const char *states[] = { "NONE", "DONE", "INIT",
11711 "WAIT", "FAILED", "NIC_LOADING"
11713 return states[state];
11716 static const char *get_rx_mode(uint32_t mode)
11718 static const char *modes[] = { "NONE", "NORMAL", "ALLMULTI",
11719 "PROMISC", "MAX_MULTICAST", "ERROR"
11723 return modes[mode];
11724 else if (BNX2X_MAX_MULTICAST == mode)
11730 #define BNX2X_INFO_STR_MAX 256
11731 static const char *get_bnx2x_flags(uint32_t flags)
11734 static const char *flag[] = { "ONE_PORT ", "NO_ISCSI ",
11735 "NO_FCOE ", "NO_WOL ", "USING_DAC ", "USING_MSIX ",
11736 "USING_MSI ", "DISABLE_MSI ", "UNKNOWN ", "NO_MCP ",
11737 "SAFC_TX_FLAG ", "MF_FUNC_DIS ", "TX_SWITCHING "
11739 static char flag_str[BNX2X_INFO_STR_MAX];
11740 memset(flag_str, 0, BNX2X_INFO_STR_MAX);
11742 for (i = 0; i < 5; i++)
11743 if (flags & (1 << i)) {
11744 strcat(flag_str, flag[i]);
11748 static char unknown[BNX2X_INFO_STR_MAX];
11749 snprintf(unknown, 32, "Unknown flag mask %x", flags);
11750 strcat(flag_str, unknown);
11755 /* Prints useful adapter info. */
11756 void bnx2x_print_adapter_info(struct bnx2x_softc *sc)
11760 PMD_DRV_LOG(INFO, sc, "========================================");
11761 /* DPDK and Driver versions */
11762 PMD_DRV_LOG(INFO, sc, "%12s : %s", "DPDK",
11764 PMD_DRV_LOG(INFO, sc, "%12s : %s", "Driver",
11765 bnx2x_pmd_version());
11766 /* Firmware versions. */
11767 PMD_DRV_LOG(INFO, sc, "%12s : %d.%d.%d",
11769 BNX2X_5710_FW_MAJOR_VERSION,
11770 BNX2X_5710_FW_MINOR_VERSION,
11771 BNX2X_5710_FW_REVISION_VERSION);
11772 PMD_DRV_LOG(INFO, sc, "%12s : %s",
11773 "Bootcode", sc->devinfo.bc_ver_str);
11774 /* Hardware chip info. */
11775 PMD_DRV_LOG(INFO, sc, "%12s : %#08x", "ASIC", sc->devinfo.chip_id);
11776 PMD_DRV_LOG(INFO, sc, "%12s : %c%d", "Rev", (CHIP_REV(sc) >> 12) + 'A',
11777 (CHIP_METAL(sc) >> 4));
11778 /* Bus PCIe info. */
11779 PMD_DRV_LOG(INFO, sc, "%12s : 0x%x", "Vendor Id",
11780 sc->devinfo.vendor_id);
11781 PMD_DRV_LOG(INFO, sc, "%12s : 0x%x", "Device Id",
11782 sc->devinfo.device_id);
11783 PMD_DRV_LOG(INFO, sc, "%12s : width x%d, ", "Bus PCIe",
11784 sc->devinfo.pcie_link_width);
11785 switch (sc->devinfo.pcie_link_speed) {
11787 PMD_DRV_LOG(INFO, sc, "%23s", "2.5 Gbps");
11790 PMD_DRV_LOG(INFO, sc, "%21s", "5 Gbps");
11793 PMD_DRV_LOG(INFO, sc, "%21s", "8 Gbps");
11796 PMD_DRV_LOG(INFO, sc, "%33s", "Unknown link speed");
11798 /* Device features. */
11799 PMD_DRV_LOG(INFO, sc, "%12s : ", "Flags");
11800 /* Miscellaneous flags. */
11801 if (sc->devinfo.pcie_cap_flags & BNX2X_MSI_CAPABLE_FLAG) {
11802 PMD_DRV_LOG(INFO, sc, "%18s", "MSI");
11805 if (sc->devinfo.pcie_cap_flags & BNX2X_MSIX_CAPABLE_FLAG) {
11807 PMD_DRV_LOG(INFO, sc, "|");
11808 PMD_DRV_LOG(INFO, sc, "%20s", "MSI-X");
11811 PMD_DRV_LOG(INFO, sc, "%12s : %s", "OVLAN", (OVLAN(sc) ? "YES" : "NO"));
11812 PMD_DRV_LOG(INFO, sc, "%12s : %s", "MF", (IS_MF(sc) ? "YES" : "NO"));
11813 PMD_DRV_LOG(INFO, sc, "========================================");
11816 /* Prints useful device info. */
11817 void bnx2x_print_device_info(struct bnx2x_softc *sc)
11819 __rte_unused uint32_t ext_phy_type;
11820 uint32_t offset, reg_val;
11822 PMD_INIT_FUNC_TRACE(sc);
11823 offset = offsetof(struct shmem_region,
11824 dev_info.port_hw_config[0].external_phy_config);
11825 reg_val = REG_RD(sc, sc->devinfo.shmem_base + offset);
11826 if (sc->link_vars.phy_flags & PHY_XGXS_FLAG)
11827 ext_phy_type = ELINK_XGXS_EXT_PHY_TYPE(reg_val);
11829 ext_phy_type = ELINK_SERDES_EXT_PHY_TYPE(reg_val);
11831 /* Device features. */
11832 PMD_DRV_LOG(INFO, sc, "%12s : %u", "Bnx2x Func", sc->pcie_func);
11833 PMD_DRV_LOG(INFO, sc,
11834 "%12s : %s", "Bnx2x Flags", get_bnx2x_flags(sc->flags));
11835 PMD_DRV_LOG(INFO, sc, "%12s : %s", "DMAE Is",
11836 (sc->dmae_ready ? "Ready" : "Not Ready"));
11837 PMD_DRV_LOG(INFO, sc, "%12s : %u", "MTU", sc->mtu);
11838 PMD_DRV_LOG(INFO, sc,
11839 "%12s : %s", "PHY Type", get_ext_phy_type(ext_phy_type));
11840 PMD_DRV_LOG(INFO, sc, "%12s : %x:%x:%x:%x:%x:%x", "MAC Addr",
11841 sc->link_params.mac_addr[0],
11842 sc->link_params.mac_addr[1],
11843 sc->link_params.mac_addr[2],
11844 sc->link_params.mac_addr[3],
11845 sc->link_params.mac_addr[4],
11846 sc->link_params.mac_addr[5]);
11847 PMD_DRV_LOG(INFO, sc, "%12s : %s", "RX Mode", get_rx_mode(sc->rx_mode));
11848 PMD_DRV_LOG(INFO, sc, "%12s : %s", "State", get_state(sc->state));
11849 if (sc->recovery_state)
11850 PMD_DRV_LOG(INFO, sc, "%12s : %s", "Recovery",
11851 get_recovery_state(sc->recovery_state));
11854 switch (sc->sp->rss_rdata.rss_mode) {
11855 case ETH_RSS_MODE_DISABLED:
11856 PMD_DRV_LOG(INFO, sc, "%12s : %s", "Queues", "RSS mode - None");
11858 case ETH_RSS_MODE_REGULAR:
11859 PMD_DRV_LOG(INFO, sc, "%12s : %s,", "Queues", "RSS mode - Regular");
11860 PMD_DRV_LOG(INFO, sc, "%16d", sc->num_queues);
11863 PMD_DRV_LOG(INFO, sc, "%12s : %s", "Queues", "RSS mode - Unknown");
11867 PMD_DRV_LOG(INFO, sc, "%12s : CQ = %lx, EQ = %lx", "SPQ Left",
11868 sc->cq_spq_left, sc->eq_spq_left);
11870 PMD_DRV_LOG(INFO, sc,
11871 "%12s : %x", "Switch", sc->link_params.switch_cfg);
11872 PMD_DRV_LOG(INFO, sc, "pcie_bus=%d, pcie_device=%d",
11873 sc->pcie_bus, sc->pcie_device);
11874 PMD_DRV_LOG(INFO, sc, "bar0.addr=%p, bar1.addr=%p",
11875 sc->bar[BAR0].base_addr, sc->bar[BAR1].base_addr);
11876 PMD_DRV_LOG(INFO, sc, "port=%d, path=%d, vnic=%d, func=%d",
11877 PORT_ID(sc), PATH_ID(sc), VNIC_ID(sc), FUNC_ID(sc));