1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2007-2013 Broadcom Corporation.
4 * Eric Davis <edavis@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
6 * Gary Zambrano <zambrano@broadcom.com>
8 * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
9 * Copyright (c) 2015-2018 Cavium Inc.
10 * All rights reserved.
14 #define BNX2X_DRIVER_VERSION "1.78.18"
17 #include "bnx2x_vfpf.h"
19 #include "ecore_init.h"
20 #include "ecore_init_ops.h"
22 #include "rte_version.h"
24 #include <sys/types.h>
29 #define BNX2X_PMD_VER_PREFIX "BNX2X PMD"
30 #define BNX2X_PMD_VERSION_MAJOR 1
31 #define BNX2X_PMD_VERSION_MINOR 0
32 #define BNX2X_PMD_VERSION_REVISION 6
33 #define BNX2X_PMD_VERSION_PATCH 1
35 static inline const char *
36 bnx2x_pmd_version(void)
38 static char version[32];
40 snprintf(version, sizeof(version), "%s %s_%d.%d.%d.%d",
43 BNX2X_PMD_VERSION_MAJOR,
44 BNX2X_PMD_VERSION_MINOR,
45 BNX2X_PMD_VERSION_REVISION,
46 BNX2X_PMD_VERSION_PATCH);
51 static z_stream zlib_stream;
53 #define EVL_VLID_MASK 0x0FFF
55 #define BNX2X_DEF_SB_ATT_IDX 0x0001
56 #define BNX2X_DEF_SB_IDX 0x0002
59 * FLR Support - bnx2x_pf_flr_clnup() is called during nic_load in the per
60 * function HW initialization.
62 #define FLR_WAIT_USEC 10000 /* 10 msecs */
63 #define FLR_WAIT_INTERVAL 50 /* usecs */
64 #define FLR_POLL_CNT (FLR_WAIT_USEC / FLR_WAIT_INTERVAL) /* 200 */
66 struct pbf_pN_buf_regs {
73 struct pbf_pN_cmd_regs {
79 /* resources needed for unloading a previously loaded device */
81 #define BNX2X_PREV_WAIT_NEEDED 1
82 rte_spinlock_t bnx2x_prev_mtx;
83 struct bnx2x_prev_list_node {
84 LIST_ENTRY(bnx2x_prev_list_node) node;
92 static LIST_HEAD(, bnx2x_prev_list_node) bnx2x_prev_list
93 = LIST_HEAD_INITIALIZER(bnx2x_prev_list);
95 static int load_count[2][3] = { { 0 } };
96 /* per-path: 0-common, 1-port0, 2-port1 */
98 static void bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg,
100 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc);
101 static void storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng,
103 static void bnx2x_set_reset_global(struct bnx2x_softc *sc);
104 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc);
105 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine);
106 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc);
107 static uint8_t bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global,
109 static void bnx2x_int_disable(struct bnx2x_softc *sc);
110 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc);
111 static void bnx2x_pf_disable(struct bnx2x_softc *sc);
112 static void bnx2x_update_rx_prod(struct bnx2x_softc *sc,
113 struct bnx2x_fastpath *fp,
114 uint16_t rx_bd_prod, uint16_t rx_cq_prod);
115 static void bnx2x_link_report(struct bnx2x_softc *sc);
116 void bnx2x_link_status_update(struct bnx2x_softc *sc);
117 static int bnx2x_alloc_mem(struct bnx2x_softc *sc);
118 static void bnx2x_free_mem(struct bnx2x_softc *sc);
119 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc);
120 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc);
121 static __rte_noinline
122 int bnx2x_nic_load(struct bnx2x_softc *sc);
124 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc);
125 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp, int scan_fp);
126 static void bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id,
127 uint8_t storm, uint16_t index, uint8_t op,
130 int bnx2x_test_bit(int nr, volatile unsigned long *addr)
135 res = ((*addr) & (1UL << nr)) != 0;
140 void bnx2x_set_bit(unsigned int nr, volatile unsigned long *addr)
142 __sync_fetch_and_or(addr, (1UL << nr));
145 void bnx2x_clear_bit(int nr, volatile unsigned long *addr)
147 __sync_fetch_and_and(addr, ~(1UL << nr));
150 int bnx2x_test_and_clear_bit(int nr, volatile unsigned long *addr)
152 unsigned long mask = (1UL << nr);
153 return __sync_fetch_and_and(addr, ~mask) & mask;
156 int bnx2x_cmpxchg(volatile int *addr, int old, int new)
158 return __sync_val_compare_and_swap(addr, old, new);
162 bnx2x_dma_alloc(struct bnx2x_softc *sc, size_t size, struct bnx2x_dma *dma,
163 const char *msg, uint32_t align)
165 char mz_name[RTE_MEMZONE_NAMESIZE];
166 const struct rte_memzone *z;
170 snprintf(mz_name, sizeof(mz_name), "bnx2x%d_%s_%" PRIx64, SC_ABS_FUNC(sc), msg,
171 rte_get_timer_cycles());
173 snprintf(mz_name, sizeof(mz_name), "bnx2x%d_%s_%" PRIx64, sc->pcie_device, msg,
174 rte_get_timer_cycles());
176 /* Caller must take care that strlen(mz_name) < RTE_MEMZONE_NAMESIZE */
177 z = rte_memzone_reserve_aligned(mz_name, (uint64_t)size,
179 RTE_MEMZONE_IOVA_CONTIG, align);
181 PMD_DRV_LOG(ERR, "DMA alloc failed for %s", msg);
184 dma->paddr = (uint64_t) z->iova;
185 dma->vaddr = z->addr;
187 PMD_DRV_LOG(DEBUG, "%s: virt=%p phys=%" PRIx64, msg, dma->vaddr, dma->paddr);
192 static int bnx2x_acquire_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
194 uint32_t lock_status;
195 uint32_t resource_bit = (1 << resource);
196 int func = SC_FUNC(sc);
197 uint32_t hw_lock_control_reg;
200 PMD_INIT_FUNC_TRACE();
202 /* validate the resource is within range */
203 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
205 "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
211 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
213 hw_lock_control_reg =
214 (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
217 /* validate the resource is not already taken */
218 lock_status = REG_RD(sc, hw_lock_control_reg);
219 if (lock_status & resource_bit) {
221 "resource in use (status 0x%x bit 0x%x)",
222 lock_status, resource_bit);
226 /* try every 5ms for 5 seconds */
227 for (cnt = 0; cnt < 1000; cnt++) {
228 REG_WR(sc, (hw_lock_control_reg + 4), resource_bit);
229 lock_status = REG_RD(sc, hw_lock_control_reg);
230 if (lock_status & resource_bit) {
236 PMD_DRV_LOG(NOTICE, "Resource lock timeout!");
240 static int bnx2x_release_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
242 uint32_t lock_status;
243 uint32_t resource_bit = (1 << resource);
244 int func = SC_FUNC(sc);
245 uint32_t hw_lock_control_reg;
247 PMD_INIT_FUNC_TRACE();
249 /* validate the resource is within range */
250 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
252 "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
258 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
260 hw_lock_control_reg =
261 (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
264 /* validate the resource is currently taken */
265 lock_status = REG_RD(sc, hw_lock_control_reg);
266 if (!(lock_status & resource_bit)) {
268 "resource not in use (status 0x%x bit 0x%x)",
269 lock_status, resource_bit);
273 REG_WR(sc, hw_lock_control_reg, resource_bit);
277 /* copy command into DMAE command memory and set DMAE command Go */
278 void bnx2x_post_dmae(struct bnx2x_softc *sc, struct dmae_command *dmae, int idx)
283 cmd_offset = (DMAE_REG_CMD_MEM + (sizeof(struct dmae_command) * idx));
284 for (i = 0; i < ((sizeof(struct dmae_command) / 4)); i++) {
285 REG_WR(sc, (cmd_offset + (i * 4)), *(((uint32_t *) dmae) + i));
288 REG_WR(sc, dmae_reg_go_c[idx], 1);
291 uint32_t bnx2x_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type)
293 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
294 DMAE_COMMAND_C_TYPE_ENABLE);
297 uint32_t bnx2x_dmae_opcode_clr_src_reset(uint32_t opcode)
299 return opcode & ~DMAE_COMMAND_SRC_RESET;
303 bnx2x_dmae_opcode(struct bnx2x_softc * sc, uint8_t src_type, uint8_t dst_type,
304 uint8_t with_comp, uint8_t comp_type)
308 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
309 (dst_type << DMAE_COMMAND_DST_SHIFT));
311 opcode |= (DMAE_COMMAND_SRC_RESET | DMAE_COMMAND_DST_RESET);
313 opcode |= (SC_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
315 opcode |= ((SC_VN(sc) << DMAE_COMMAND_E1HVN_SHIFT) |
316 (SC_VN(sc) << DMAE_COMMAND_DST_VN_SHIFT));
318 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
321 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
323 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
327 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
334 bnx2x_prep_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae,
335 uint8_t src_type, uint8_t dst_type)
337 memset(dmae, 0, sizeof(struct dmae_command));
340 dmae->opcode = bnx2x_dmae_opcode(sc, src_type, dst_type,
341 TRUE, DMAE_COMP_PCI);
343 /* fill in the completion parameters */
344 dmae->comp_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_comp));
345 dmae->comp_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_comp));
346 dmae->comp_val = DMAE_COMP_VAL;
349 /* issue a DMAE command over the init channel and wait for completion */
351 bnx2x_issue_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae)
353 uint32_t *wb_comp = BNX2X_SP(sc, wb_comp);
354 int timeout = CHIP_REV_IS_SLOW(sc) ? 400000 : 4000;
356 /* reset completion */
359 /* post the command on the channel used for initializations */
360 bnx2x_post_dmae(sc, dmae, INIT_DMAE_C(sc));
362 /* wait for completion */
365 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
367 (sc->recovery_state != BNX2X_RECOVERY_DONE &&
368 sc->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
369 PMD_DRV_LOG(INFO, "DMAE timeout!");
377 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
378 PMD_DRV_LOG(INFO, "DMAE PCI error!");
379 return DMAE_PCI_ERROR;
385 void bnx2x_read_dmae(struct bnx2x_softc *sc, uint32_t src_addr, uint32_t len32)
387 struct dmae_command dmae;
392 if (!sc->dmae_ready) {
393 data = BNX2X_SP(sc, wb_data[0]);
395 for (i = 0; i < len32; i++) {
396 data[i] = REG_RD(sc, (src_addr + (i * 4)));
402 /* set opcode and fixed command fields */
403 bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
405 /* fill in addresses and len */
406 dmae.src_addr_lo = (src_addr >> 2); /* GRC addr has dword resolution */
407 dmae.src_addr_hi = 0;
408 dmae.dst_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_data));
409 dmae.dst_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_data));
412 /* issue the command and wait for completion */
413 if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
414 rte_panic("DMAE failed (%d)", rc);
419 bnx2x_write_dmae(struct bnx2x_softc *sc, rte_iova_t dma_addr, uint32_t dst_addr,
422 struct dmae_command dmae;
425 if (!sc->dmae_ready) {
426 ecore_init_str_wr(sc, dst_addr, BNX2X_SP(sc, wb_data[0]), len32);
430 /* set opcode and fixed command fields */
431 bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
433 /* fill in addresses and len */
434 dmae.src_addr_lo = U64_LO(dma_addr);
435 dmae.src_addr_hi = U64_HI(dma_addr);
436 dmae.dst_addr_lo = (dst_addr >> 2); /* GRC addr has dword resolution */
437 dmae.dst_addr_hi = 0;
440 /* issue the command and wait for completion */
441 if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
442 rte_panic("DMAE failed (%d)", rc);
447 bnx2x_write_dmae_phys_len(struct bnx2x_softc *sc, rte_iova_t phys_addr,
448 uint32_t addr, uint32_t len)
450 uint32_t dmae_wr_max = DMAE_LEN32_WR_MAX(sc);
453 while (len > dmae_wr_max) {
454 bnx2x_write_dmae(sc, (phys_addr + offset), /* src DMA address */
455 (addr + offset), /* dst GRC address */
457 offset += (dmae_wr_max * 4);
461 bnx2x_write_dmae(sc, (phys_addr + offset), /* src DMA address */
462 (addr + offset), /* dst GRC address */
467 bnx2x_set_ctx_validation(struct bnx2x_softc *sc, struct eth_context *cxt,
470 /* ustorm cxt validation */
471 cxt->ustorm_ag_context.cdu_usage =
472 CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
473 CDU_REGION_NUMBER_UCM_AG,
474 ETH_CONNECTION_TYPE);
475 /* xcontext validation */
476 cxt->xstorm_ag_context.cdu_reserved =
477 CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
478 CDU_REGION_NUMBER_XCM_AG,
479 ETH_CONNECTION_TYPE);
483 bnx2x_storm_memset_hc_timeout(struct bnx2x_softc *sc, uint8_t fw_sb_id,
484 uint8_t sb_index, uint8_t ticks)
487 (BAR_CSTRORM_INTMEM +
488 CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(fw_sb_id, sb_index));
490 REG_WR8(sc, addr, ticks);
494 bnx2x_storm_memset_hc_disable(struct bnx2x_softc *sc, uint16_t fw_sb_id,
495 uint8_t sb_index, uint8_t disable)
497 uint32_t enable_flag =
498 (disable) ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
500 (BAR_CSTRORM_INTMEM +
501 CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(fw_sb_id, sb_index));
505 flags = REG_RD8(sc, addr);
506 flags &= ~HC_INDEX_DATA_HC_ENABLED;
507 flags |= enable_flag;
508 REG_WR8(sc, addr, flags);
512 bnx2x_update_coalesce_sb_index(struct bnx2x_softc *sc, uint8_t fw_sb_id,
513 uint8_t sb_index, uint8_t disable, uint16_t usec)
515 uint8_t ticks = (usec / 4);
517 bnx2x_storm_memset_hc_timeout(sc, fw_sb_id, sb_index, ticks);
519 disable = (disable) ? 1 : ((usec) ? 0 : 1);
520 bnx2x_storm_memset_hc_disable(sc, fw_sb_id, sb_index, disable);
523 uint32_t elink_cb_reg_read(struct bnx2x_softc *sc, uint32_t reg_addr)
525 return REG_RD(sc, reg_addr);
528 void elink_cb_reg_write(struct bnx2x_softc *sc, uint32_t reg_addr, uint32_t val)
530 REG_WR(sc, reg_addr, val);
534 elink_cb_event_log(__rte_unused struct bnx2x_softc *sc,
535 __rte_unused const elink_log_id_t elink_log_id, ...)
537 PMD_DRV_LOG(DEBUG, "ELINK EVENT LOG (%d)", elink_log_id);
540 static int bnx2x_set_spio(struct bnx2x_softc *sc, int spio, uint32_t mode)
544 /* Only 2 SPIOs are configurable */
545 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
546 PMD_DRV_LOG(NOTICE, "Invalid SPIO 0x%x", spio);
550 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
552 /* read SPIO and mask except the float bits */
553 spio_reg = (REG_RD(sc, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
556 case MISC_SPIO_OUTPUT_LOW:
557 /* clear FLOAT and set CLR */
558 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
559 spio_reg |= (spio << MISC_SPIO_CLR_POS);
562 case MISC_SPIO_OUTPUT_HIGH:
563 /* clear FLOAT and set SET */
564 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
565 spio_reg |= (spio << MISC_SPIO_SET_POS);
568 case MISC_SPIO_INPUT_HI_Z:
570 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
577 REG_WR(sc, MISC_REG_SPIO, spio_reg);
578 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
583 static int bnx2x_gpio_read(struct bnx2x_softc *sc, int gpio_num, uint8_t port)
585 /* The GPIO should be swapped if swap register is set and active */
586 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
587 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
588 int gpio_shift = gpio_num;
590 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
592 uint32_t gpio_mask = (1 << gpio_shift);
595 if (gpio_num > MISC_REGISTERS_GPIO_3) {
596 PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
600 /* read GPIO value */
601 gpio_reg = REG_RD(sc, MISC_REG_GPIO);
603 /* get the requested pin value */
604 return ((gpio_reg & gpio_mask) == gpio_mask) ? 1 : 0;
608 bnx2x_gpio_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode, uint8_t port)
610 /* The GPIO should be swapped if swap register is set and active */
611 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
612 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
613 int gpio_shift = gpio_num;
615 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
617 uint32_t gpio_mask = (1 << gpio_shift);
620 if (gpio_num > MISC_REGISTERS_GPIO_3) {
621 PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
625 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
627 /* read GPIO and mask except the float bits */
628 gpio_reg = (REG_RD(sc, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
631 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
632 /* clear FLOAT and set CLR */
633 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
634 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
637 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
638 /* clear FLOAT and set SET */
639 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
640 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
643 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
645 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
652 REG_WR(sc, MISC_REG_GPIO, gpio_reg);
653 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
659 bnx2x_gpio_mult_write(struct bnx2x_softc *sc, uint8_t pins, uint32_t mode)
663 /* any port swapping should be handled by caller */
665 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
667 /* read GPIO and mask except the float bits */
668 gpio_reg = REG_RD(sc, MISC_REG_GPIO);
669 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
670 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
671 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
674 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
676 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
679 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
681 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
684 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
686 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
690 PMD_DRV_LOG(NOTICE, "Invalid GPIO mode assignment %d", mode);
691 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
695 REG_WR(sc, MISC_REG_GPIO, gpio_reg);
696 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
702 bnx2x_gpio_int_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode,
705 /* The GPIO should be swapped if swap register is set and active */
706 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
707 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
708 int gpio_shift = gpio_num;
710 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
712 uint32_t gpio_mask = (1 << gpio_shift);
715 if (gpio_num > MISC_REGISTERS_GPIO_3) {
716 PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
720 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
723 gpio_reg = REG_RD(sc, MISC_REG_GPIO_INT);
726 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
727 /* clear SET and set CLR */
728 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
729 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
732 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
733 /* clear CLR and set SET */
734 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
735 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
742 REG_WR(sc, MISC_REG_GPIO_INT, gpio_reg);
743 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
749 elink_cb_gpio_read(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t port)
751 return bnx2x_gpio_read(sc, gpio_num, port);
754 uint8_t elink_cb_gpio_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode, /* 0=low 1=high */
757 return bnx2x_gpio_write(sc, gpio_num, mode, port);
761 elink_cb_gpio_mult_write(struct bnx2x_softc * sc, uint8_t pins,
762 uint8_t mode /* 0=low 1=high */ )
764 return bnx2x_gpio_mult_write(sc, pins, mode);
767 uint8_t elink_cb_gpio_int_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode, /* 0=low 1=high */
770 return bnx2x_gpio_int_write(sc, gpio_num, mode, port);
773 void elink_cb_notify_link_changed(struct bnx2x_softc *sc)
775 REG_WR(sc, (MISC_REG_AEU_GENERAL_ATTN_12 +
776 (SC_FUNC(sc) * sizeof(uint32_t))), 1);
779 /* send the MCP a request, block until there is a reply */
781 elink_cb_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
783 int mb_idx = SC_FW_MB_IDX(sc);
787 uint8_t delay = CHIP_REV_IS_SLOW(sc) ? 100 : 10;
790 SHMEM_WR(sc, func_mb[mb_idx].drv_mb_param, param);
791 SHMEM_WR(sc, func_mb[mb_idx].drv_mb_header, (command | seq));
794 "wrote command 0x%08x to FW MB param 0x%08x",
795 (command | seq), param);
797 /* Let the FW do it's magic. GIve it up to 5 seconds... */
800 rc = SHMEM_RD(sc, func_mb[mb_idx].fw_mb_header);
801 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
803 /* is this a reply to our command? */
804 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) {
805 rc &= FW_MSG_CODE_MASK;
808 PMD_DRV_LOG(NOTICE, "FW failed to respond!");
816 bnx2x_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
818 return elink_cb_fw_command(sc, command, param);
822 __storm_memset_dma_mapping(struct bnx2x_softc *sc, uint32_t addr,
825 REG_WR(sc, addr, U64_LO(mapping));
826 REG_WR(sc, (addr + 4), U64_HI(mapping));
830 storm_memset_spq_addr(struct bnx2x_softc *sc, rte_iova_t mapping,
833 uint32_t addr = (XSEM_REG_FAST_MEMORY +
834 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid));
835 __storm_memset_dma_mapping(sc, addr, mapping);
839 storm_memset_vf_to_pf(struct bnx2x_softc *sc, uint16_t abs_fid, uint16_t pf_id)
841 REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid)),
843 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid)),
845 REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid)),
847 REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid)),
852 storm_memset_func_en(struct bnx2x_softc *sc, uint16_t abs_fid, uint8_t enable)
854 REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid)),
856 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid)),
858 REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid)),
860 REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid)),
865 storm_memset_eq_data(struct bnx2x_softc *sc, struct event_ring_data *eq_data,
871 addr = (BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid));
872 size = sizeof(struct event_ring_data);
873 ecore_storm_memset_struct(sc, addr, size, (uint32_t *) eq_data);
877 storm_memset_eq_prod(struct bnx2x_softc *sc, uint16_t eq_prod, uint16_t pfid)
879 uint32_t addr = (BAR_CSTRORM_INTMEM +
880 CSTORM_EVENT_RING_PROD_OFFSET(pfid));
881 REG_WR16(sc, addr, eq_prod);
885 * Post a slowpath command.
887 * A slowpath command is used to propagate a configuration change through
888 * the controller in a controlled manner, allowing each STORM processor and
889 * other H/W blocks to phase in the change. The commands sent on the
890 * slowpath are referred to as ramrods. Depending on the ramrod used the
891 * completion of the ramrod will occur in different ways. Here's a
892 * breakdown of ramrods and how they complete:
894 * RAMROD_CMD_ID_ETH_PORT_SETUP
895 * Used to setup the leading connection on a port. Completes on the
896 * Receive Completion Queue (RCQ) of that port (typically fp[0]).
898 * RAMROD_CMD_ID_ETH_CLIENT_SETUP
899 * Used to setup an additional connection on a port. Completes on the
900 * RCQ of the multi-queue/RSS connection being initialized.
902 * RAMROD_CMD_ID_ETH_STAT_QUERY
903 * Used to force the storm processors to update the statistics database
904 * in host memory. This ramrod is send on the leading connection CID and
905 * completes as an index increment of the CSTORM on the default status
908 * RAMROD_CMD_ID_ETH_UPDATE
909 * Used to update the state of the leading connection, usually to udpate
910 * the RSS indirection table. Completes on the RCQ of the leading
911 * connection. (Not currently used under FreeBSD until OS support becomes
914 * RAMROD_CMD_ID_ETH_HALT
915 * Used when tearing down a connection prior to driver unload. Completes
916 * on the RCQ of the multi-queue/RSS connection being torn down. Don't
917 * use this on the leading connection.
919 * RAMROD_CMD_ID_ETH_SET_MAC
920 * Sets the Unicast/Broadcast/Multicast used by the port. Completes on
921 * the RCQ of the leading connection.
923 * RAMROD_CMD_ID_ETH_CFC_DEL
924 * Used when tearing down a conneciton prior to driver unload. Completes
925 * on the RCQ of the leading connection (since the current connection
926 * has been completely removed from controller memory).
928 * RAMROD_CMD_ID_ETH_PORT_DEL
929 * Used to tear down the leading connection prior to driver unload,
930 * typically fp[0]. Completes as an index increment of the CSTORM on the
931 * default status block.
933 * RAMROD_CMD_ID_ETH_FORWARD_SETUP
934 * Used for connection offload. Completes on the RCQ of the multi-queue
935 * RSS connection that is being offloaded. (Not currently used under
938 * There can only be one command pending per function.
941 * 0 = Success, !0 = Failure.
944 /* must be called under the spq lock */
945 static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x_softc *sc)
947 struct eth_spe *next_spe = sc->spq_prod_bd;
949 if (sc->spq_prod_bd == sc->spq_last_bd) {
950 /* wrap back to the first eth_spq */
951 sc->spq_prod_bd = sc->spq;
952 sc->spq_prod_idx = 0;
961 /* must be called under the spq lock */
962 static void bnx2x_sp_prod_update(struct bnx2x_softc *sc)
964 int func = SC_FUNC(sc);
967 * Make sure that BD data is updated before writing the producer.
968 * BD data is written to the memory, the producer is read from the
969 * memory, thus we need a full memory barrier to ensure the ordering.
973 REG_WR16(sc, (BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func)),
980 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
982 * @cmd: command to check
983 * @cmd_type: command type
985 static int bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
987 if ((cmd_type == NONE_CONNECTION_TYPE) ||
988 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
989 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
990 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
991 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
992 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
993 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) {
1001 * bnx2x_sp_post - place a single command on an SP ring
1003 * @sc: driver handle
1004 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
1005 * @cid: SW CID the command is related to
1006 * @data_hi: command private data address (high 32 bits)
1007 * @data_lo: command private data address (low 32 bits)
1008 * @cmd_type: command type (e.g. NONE, ETH)
1010 * SP data is handled as if it's always an address pair, thus data fields are
1011 * not swapped to little endian in upper functions. Instead this function swaps
1012 * data as if it's two uint32 fields.
1015 bnx2x_sp_post(struct bnx2x_softc *sc, int command, int cid, uint32_t data_hi,
1016 uint32_t data_lo, int cmd_type)
1018 struct eth_spe *spe;
1022 common = bnx2x_is_contextless_ramrod(command, cmd_type);
1025 if (!atomic_load_acq_long(&sc->eq_spq_left)) {
1026 PMD_DRV_LOG(INFO, "EQ ring is full!");
1030 if (!atomic_load_acq_long(&sc->cq_spq_left)) {
1031 PMD_DRV_LOG(INFO, "SPQ ring is full!");
1036 spe = bnx2x_sp_get_next(sc);
1038 /* CID needs port number to be encoded int it */
1039 spe->hdr.conn_and_cmd_data =
1040 htole32((command << SPE_HDR_CMD_ID_SHIFT) | HW_CID(sc, cid));
1042 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
1044 /* TBD: Check if it works for VFs */
1045 type |= ((SC_FUNC(sc) << SPE_HDR_FUNCTION_ID_SHIFT) &
1046 SPE_HDR_FUNCTION_ID);
1048 spe->hdr.type = htole16(type);
1050 spe->data.update_data_addr.hi = htole32(data_hi);
1051 spe->data.update_data_addr.lo = htole32(data_lo);
1054 * It's ok if the actual decrement is issued towards the memory
1055 * somewhere between the lock and unlock. Thus no more explict
1056 * memory barrier is needed.
1059 atomic_subtract_acq_long(&sc->eq_spq_left, 1);
1061 atomic_subtract_acq_long(&sc->cq_spq_left, 1);
1065 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x"
1066 "data (%x:%x) type(0x%x) left (CQ, EQ) (%lx,%lx)",
1068 (uint32_t) U64_HI(sc->spq_dma.paddr),
1069 (uint32_t) (U64_LO(sc->spq_dma.paddr) +
1070 (uint8_t *) sc->spq_prod_bd -
1071 (uint8_t *) sc->spq), command, common,
1072 HW_CID(sc, cid), data_hi, data_lo, type,
1073 atomic_load_acq_long(&sc->cq_spq_left),
1074 atomic_load_acq_long(&sc->eq_spq_left));
1076 bnx2x_sp_prod_update(sc);
1081 static void bnx2x_drv_pulse(struct bnx2x_softc *sc)
1083 SHMEM_WR(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb,
1084 sc->fw_drv_pulse_wr_seq);
1087 static int bnx2x_tx_queue_has_work(const struct bnx2x_fastpath *fp)
1090 struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1092 if (unlikely(!txq)) {
1093 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1097 mb(); /* status block fields can change */
1098 hw_cons = le16toh(*fp->tx_cons_sb);
1099 return hw_cons != txq->tx_pkt_head;
1102 static uint8_t bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
1104 /* expand this for multi-cos if ever supported */
1105 return bnx2x_tx_queue_has_work(fp);
1108 static int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
1110 uint16_t rx_cq_cons_sb;
1111 struct bnx2x_rx_queue *rxq;
1112 rxq = fp->sc->rx_queues[fp->index];
1113 if (unlikely(!rxq)) {
1114 PMD_RX_LOG(ERR, "ERROR: RX queue is NULL");
1118 mb(); /* status block fields can change */
1119 rx_cq_cons_sb = le16toh(*fp->rx_cq_cons_sb);
1120 if (unlikely((rx_cq_cons_sb & MAX_RCQ_ENTRIES(rxq)) ==
1121 MAX_RCQ_ENTRIES(rxq)))
1123 return rxq->rx_cq_head != rx_cq_cons_sb;
1127 bnx2x_sp_event(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
1128 union eth_rx_cqe *rr_cqe)
1130 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1131 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1132 enum ecore_queue_cmd drv_cmd = ECORE_Q_CMD_MAX;
1133 struct ecore_queue_sp_obj *q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
1136 "fp=%d cid=%d got ramrod #%d state is %x type is %d",
1137 fp->index, cid, command, sc->state,
1138 rr_cqe->ramrod_cqe.ramrod_type);
1141 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1142 PMD_DRV_LOG(DEBUG, "got UPDATE ramrod. CID %d", cid);
1143 drv_cmd = ECORE_Q_CMD_UPDATE;
1146 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1147 PMD_DRV_LOG(DEBUG, "got MULTI[%d] setup ramrod", cid);
1148 drv_cmd = ECORE_Q_CMD_SETUP;
1151 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1152 PMD_DRV_LOG(DEBUG, "got MULTI[%d] tx-only setup ramrod", cid);
1153 drv_cmd = ECORE_Q_CMD_SETUP_TX_ONLY;
1156 case (RAMROD_CMD_ID_ETH_HALT):
1157 PMD_DRV_LOG(DEBUG, "got MULTI[%d] halt ramrod", cid);
1158 drv_cmd = ECORE_Q_CMD_HALT;
1161 case (RAMROD_CMD_ID_ETH_TERMINATE):
1162 PMD_DRV_LOG(DEBUG, "got MULTI[%d] teminate ramrod", cid);
1163 drv_cmd = ECORE_Q_CMD_TERMINATE;
1166 case (RAMROD_CMD_ID_ETH_EMPTY):
1167 PMD_DRV_LOG(DEBUG, "got MULTI[%d] empty ramrod", cid);
1168 drv_cmd = ECORE_Q_CMD_EMPTY;
1173 "ERROR: unexpected MC reply (%d)"
1174 "on fp[%d]", command, fp->index);
1178 if ((drv_cmd != ECORE_Q_CMD_MAX) &&
1179 q_obj->complete_cmd(sc, q_obj, drv_cmd)) {
1181 * q_obj->complete_cmd() failure means that this was
1182 * an unexpected completion.
1184 * In this case we don't want to increase the sc->spq_left
1185 * because apparently we haven't sent this command the first
1188 // rte_panic("Unexpected SP completion");
1192 atomic_add_acq_long(&sc->cq_spq_left, 1);
1194 PMD_DRV_LOG(DEBUG, "sc->cq_spq_left 0x%lx",
1195 atomic_load_acq_long(&sc->cq_spq_left));
1198 static uint8_t bnx2x_rxeof(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
1200 struct bnx2x_rx_queue *rxq;
1201 uint16_t bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
1202 uint16_t hw_cq_cons, sw_cq_cons, sw_cq_prod;
1204 rxq = sc->rx_queues[fp->index];
1206 PMD_RX_LOG(ERR, "RX queue %d is NULL", fp->index);
1210 /* CQ "next element" is of the size of the regular element */
1211 hw_cq_cons = le16toh(*fp->rx_cq_cons_sb);
1212 if (unlikely((hw_cq_cons & USABLE_RCQ_ENTRIES_PER_PAGE) ==
1213 USABLE_RCQ_ENTRIES_PER_PAGE)) {
1217 bd_cons = rxq->rx_bd_head;
1218 bd_prod = rxq->rx_bd_tail;
1219 bd_prod_fw = bd_prod;
1220 sw_cq_cons = rxq->rx_cq_head;
1221 sw_cq_prod = rxq->rx_cq_tail;
1224 * Memory barrier necessary as speculative reads of the rx
1225 * buffer can be ahead of the index in the status block
1229 while (sw_cq_cons != hw_cq_cons) {
1230 union eth_rx_cqe *cqe;
1231 struct eth_fast_path_rx_cqe *cqe_fp;
1232 uint8_t cqe_fp_flags;
1233 enum eth_rx_cqe_type cqe_fp_type;
1235 comp_ring_cons = RCQ_ENTRY(sw_cq_cons, rxq);
1236 bd_prod = RX_BD(bd_prod, rxq);
1237 bd_cons = RX_BD(bd_cons, rxq);
1239 cqe = &rxq->cq_ring[comp_ring_cons];
1240 cqe_fp = &cqe->fast_path_cqe;
1241 cqe_fp_flags = cqe_fp->type_error_flags;
1242 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
1244 /* is this a slowpath msg? */
1245 if (CQE_TYPE_SLOW(cqe_fp_type)) {
1246 bnx2x_sp_event(sc, fp, cqe);
1250 /* is this an error packet? */
1251 if (unlikely(cqe_fp_flags &
1252 ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG)) {
1253 PMD_RX_LOG(DEBUG, "flags 0x%x rx packet %u",
1254 cqe_fp_flags, sw_cq_cons);
1258 PMD_RX_LOG(DEBUG, "Dropping fastpath called from attn poller!");
1261 bd_cons = NEXT_RX_BD(bd_cons);
1262 bd_prod = NEXT_RX_BD(bd_prod);
1263 bd_prod_fw = NEXT_RX_BD(bd_prod_fw);
1266 sw_cq_prod = NEXT_RCQ_IDX(sw_cq_prod);
1267 sw_cq_cons = NEXT_RCQ_IDX(sw_cq_cons);
1269 } /* while work to do */
1271 rxq->rx_bd_head = bd_cons;
1272 rxq->rx_bd_tail = bd_prod_fw;
1273 rxq->rx_cq_head = sw_cq_cons;
1274 rxq->rx_cq_tail = sw_cq_prod;
1276 /* Update producers */
1277 bnx2x_update_rx_prod(sc, fp, bd_prod_fw, sw_cq_prod);
1279 return sw_cq_cons != hw_cq_cons;
1283 bnx2x_free_tx_pkt(__rte_unused struct bnx2x_fastpath *fp, struct bnx2x_tx_queue *txq,
1284 uint16_t pkt_idx, uint16_t bd_idx)
1286 struct eth_tx_start_bd *tx_start_bd =
1287 &txq->tx_ring[TX_BD(bd_idx, txq)].start_bd;
1288 uint16_t nbd = rte_le_to_cpu_16(tx_start_bd->nbd);
1289 struct rte_mbuf *tx_mbuf = txq->sw_ring[TX_BD(pkt_idx, txq)];
1291 if (likely(tx_mbuf != NULL)) {
1292 rte_pktmbuf_free_seg(tx_mbuf);
1294 PMD_RX_LOG(ERR, "fp[%02d] lost mbuf %lu",
1295 fp->index, (unsigned long)TX_BD(pkt_idx, txq));
1298 txq->sw_ring[TX_BD(pkt_idx, txq)] = NULL;
1299 txq->nb_tx_avail += nbd;
1302 bd_idx = NEXT_TX_BD(bd_idx);
1307 /* processes transmit completions */
1308 uint8_t bnx2x_txeof(__rte_unused struct bnx2x_softc * sc, struct bnx2x_fastpath * fp)
1310 uint16_t bd_cons, hw_cons, sw_cons;
1311 __rte_unused uint16_t tx_bd_avail;
1313 struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1315 if (unlikely(!txq)) {
1316 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1320 bd_cons = txq->tx_bd_head;
1321 hw_cons = rte_le_to_cpu_16(*fp->tx_cons_sb);
1322 sw_cons = txq->tx_pkt_head;
1324 while (sw_cons != hw_cons) {
1325 bd_cons = bnx2x_free_tx_pkt(fp, txq, sw_cons, bd_cons);
1329 txq->tx_pkt_head = sw_cons;
1330 txq->tx_bd_head = bd_cons;
1332 tx_bd_avail = txq->nb_tx_avail;
1334 PMD_TX_LOG(DEBUG, "fp[%02d] avail=%u cons_sb=%u, "
1335 "pkt_head=%u pkt_tail=%u bd_head=%u bd_tail=%u",
1336 fp->index, tx_bd_avail, hw_cons,
1337 txq->tx_pkt_head, txq->tx_pkt_tail,
1338 txq->tx_bd_head, txq->tx_bd_tail);
1342 static void bnx2x_drain_tx_queues(struct bnx2x_softc *sc)
1344 struct bnx2x_fastpath *fp;
1347 /* wait until all TX fastpath tasks have completed */
1348 for (i = 0; i < sc->num_queues; i++) {
1353 while (bnx2x_has_tx_work(fp)) {
1354 bnx2x_txeof(sc, fp);
1358 "Timeout waiting for fp[%d] "
1359 "transmits to complete!", i);
1360 rte_panic("tx drain failure");
1374 bnx2x_del_all_macs(struct bnx2x_softc *sc, struct ecore_vlan_mac_obj *mac_obj,
1375 int mac_type, uint8_t wait_for_comp)
1377 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1380 /* wait for completion of requested */
1381 if (wait_for_comp) {
1382 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1385 /* Set the mac type of addresses we want to clear */
1386 bnx2x_set_bit(mac_type, &vlan_mac_flags);
1388 rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1390 PMD_DRV_LOG(ERR, "Failed to delete MACs (%d)", rc);
1396 bnx2x_fill_accept_flags(struct bnx2x_softc *sc, uint32_t rx_mode,
1397 unsigned long *rx_accept_flags,
1398 unsigned long *tx_accept_flags)
1400 /* Clear the flags first */
1401 *rx_accept_flags = 0;
1402 *tx_accept_flags = 0;
1405 case BNX2X_RX_MODE_NONE:
1407 * 'drop all' supersedes any accept flags that may have been
1408 * passed to the function.
1412 case BNX2X_RX_MODE_NORMAL:
1413 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1414 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, rx_accept_flags);
1415 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1417 /* internal switching mode */
1418 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1419 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, tx_accept_flags);
1420 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1424 case BNX2X_RX_MODE_ALLMULTI:
1425 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1426 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1427 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1429 /* internal switching mode */
1430 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1431 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1432 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1436 case BNX2X_RX_MODE_ALLMULTI_PROMISC:
1437 case BNX2X_RX_MODE_PROMISC:
1439 * According to deffinition of SI mode, iface in promisc mode
1440 * should receive matched and unmatched (in resolution of port)
1443 bnx2x_set_bit(ECORE_ACCEPT_UNMATCHED, rx_accept_flags);
1444 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1445 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1446 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1448 /* internal switching mode */
1449 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1450 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1453 bnx2x_set_bit(ECORE_ACCEPT_ALL_UNICAST, tx_accept_flags);
1455 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1461 PMD_RX_LOG(ERR, "Unknown rx_mode (%d)", rx_mode);
1465 /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
1466 if (rx_mode != BNX2X_RX_MODE_NONE) {
1467 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, rx_accept_flags);
1468 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, tx_accept_flags);
1475 bnx2x_set_q_rx_mode(struct bnx2x_softc *sc, uint8_t cl_id,
1476 unsigned long rx_mode_flags,
1477 unsigned long rx_accept_flags,
1478 unsigned long tx_accept_flags, unsigned long ramrod_flags)
1480 struct ecore_rx_mode_ramrod_params ramrod_param;
1483 memset(&ramrod_param, 0, sizeof(ramrod_param));
1485 /* Prepare ramrod parameters */
1486 ramrod_param.cid = 0;
1487 ramrod_param.cl_id = cl_id;
1488 ramrod_param.rx_mode_obj = &sc->rx_mode_obj;
1489 ramrod_param.func_id = SC_FUNC(sc);
1491 ramrod_param.pstate = &sc->sp_state;
1492 ramrod_param.state = ECORE_FILTER_RX_MODE_PENDING;
1494 ramrod_param.rdata = BNX2X_SP(sc, rx_mode_rdata);
1495 ramrod_param.rdata_mapping =
1496 (rte_iova_t)BNX2X_SP_MAPPING(sc, rx_mode_rdata),
1497 bnx2x_set_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
1499 ramrod_param.ramrod_flags = ramrod_flags;
1500 ramrod_param.rx_mode_flags = rx_mode_flags;
1502 ramrod_param.rx_accept_flags = rx_accept_flags;
1503 ramrod_param.tx_accept_flags = tx_accept_flags;
1505 rc = ecore_config_rx_mode(sc, &ramrod_param);
1507 PMD_RX_LOG(ERR, "Set rx_mode %d failed", sc->rx_mode);
1514 int bnx2x_set_storm_rx_mode(struct bnx2x_softc *sc)
1516 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
1517 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
1520 rc = bnx2x_fill_accept_flags(sc, sc->rx_mode, &rx_accept_flags,
1526 bnx2x_set_bit(RAMROD_RX, &ramrod_flags);
1527 bnx2x_set_bit(RAMROD_TX, &ramrod_flags);
1528 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1530 return bnx2x_set_q_rx_mode(sc, sc->fp[0].cl_id, rx_mode_flags,
1531 rx_accept_flags, tx_accept_flags,
1535 /* returns the "mcp load_code" according to global load_count array */
1536 static int bnx2x_nic_load_no_mcp(struct bnx2x_softc *sc)
1538 int path = SC_PATH(sc);
1539 int port = SC_PORT(sc);
1541 PMD_DRV_LOG(INFO, "NO MCP - load counts[%d] %d, %d, %d",
1542 path, load_count[path][0], load_count[path][1],
1543 load_count[path][2]);
1545 load_count[path][0]++;
1546 load_count[path][1 + port]++;
1547 PMD_DRV_LOG(INFO, "NO MCP - new load counts[%d] %d, %d, %d",
1548 path, load_count[path][0], load_count[path][1],
1549 load_count[path][2]);
1550 if (load_count[path][0] == 1)
1551 return FW_MSG_CODE_DRV_LOAD_COMMON;
1552 else if (load_count[path][1 + port] == 1)
1553 return FW_MSG_CODE_DRV_LOAD_PORT;
1555 return FW_MSG_CODE_DRV_LOAD_FUNCTION;
1558 /* returns the "mcp load_code" according to global load_count array */
1559 static int bnx2x_nic_unload_no_mcp(struct bnx2x_softc *sc)
1561 int port = SC_PORT(sc);
1562 int path = SC_PATH(sc);
1564 PMD_DRV_LOG(INFO, "NO MCP - load counts[%d] %d, %d, %d",
1565 path, load_count[path][0], load_count[path][1],
1566 load_count[path][2]);
1567 load_count[path][0]--;
1568 load_count[path][1 + port]--;
1569 PMD_DRV_LOG(INFO, "NO MCP - new load counts[%d] %d, %d, %d",
1570 path, load_count[path][0], load_count[path][1],
1571 load_count[path][2]);
1572 if (load_count[path][0] == 0) {
1573 return FW_MSG_CODE_DRV_UNLOAD_COMMON;
1574 } else if (load_count[path][1 + port] == 0) {
1575 return FW_MSG_CODE_DRV_UNLOAD_PORT;
1577 return FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
1581 /* request unload mode from the MCP: COMMON, PORT or FUNCTION */
1582 static uint32_t bnx2x_send_unload_req(struct bnx2x_softc *sc, int unload_mode)
1584 uint32_t reset_code = 0;
1586 /* Select the UNLOAD request mode */
1587 if (unload_mode == UNLOAD_NORMAL) {
1588 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1590 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1593 /* Send the request to the MCP */
1594 if (!BNX2X_NOMCP(sc)) {
1595 reset_code = bnx2x_fw_command(sc, reset_code, 0);
1597 reset_code = bnx2x_nic_unload_no_mcp(sc);
1603 /* send UNLOAD_DONE command to the MCP */
1604 static void bnx2x_send_unload_done(struct bnx2x_softc *sc, uint8_t keep_link)
1606 uint32_t reset_param =
1607 keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
1609 /* Report UNLOAD_DONE to MCP */
1610 if (!BNX2X_NOMCP(sc)) {
1611 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
1615 static int bnx2x_func_wait_started(struct bnx2x_softc *sc)
1619 if (!sc->port.pmf) {
1624 * (assumption: No Attention from MCP at this stage)
1625 * PMF probably in the middle of TX disable/enable transaction
1626 * 1. Sync IRS for default SB
1627 * 2. Sync SP queue - this guarantees us that attention handling started
1628 * 3. Wait, that TX disable/enable transaction completes
1630 * 1+2 guarantee that if DCBX attention was scheduled it already changed
1631 * pending bit of transaction from STARTED-->TX_STOPPED, if we already
1632 * received completion for the transaction the state is TX_STOPPED.
1633 * State will return to STARTED after completion of TX_STOPPED-->STARTED
1637 while (ecore_func_get_state(sc, &sc->func_obj) !=
1638 ECORE_F_STATE_STARTED && tout--) {
1642 if (ecore_func_get_state(sc, &sc->func_obj) != ECORE_F_STATE_STARTED) {
1644 * Failed to complete the transaction in a "good way"
1645 * Force both transactions with CLR bit.
1647 struct ecore_func_state_params func_params = { NULL };
1649 PMD_DRV_LOG(NOTICE, "Unexpected function state! "
1650 "Forcing STARTED-->TX_STOPPED-->STARTED");
1652 func_params.f_obj = &sc->func_obj;
1653 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1655 /* STARTED-->TX_STOPPED */
1656 func_params.cmd = ECORE_F_CMD_TX_STOP;
1657 ecore_func_state_change(sc, &func_params);
1659 /* TX_STOPPED-->STARTED */
1660 func_params.cmd = ECORE_F_CMD_TX_START;
1661 return ecore_func_state_change(sc, &func_params);
1667 static int bnx2x_stop_queue(struct bnx2x_softc *sc, int index)
1669 struct bnx2x_fastpath *fp = &sc->fp[index];
1670 struct ecore_queue_state_params q_params = { NULL };
1673 PMD_DRV_LOG(DEBUG, "stopping queue %d cid %d", index, fp->index);
1675 q_params.q_obj = &sc->sp_objs[fp->index].q_obj;
1676 /* We want to wait for completion in this context */
1677 bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
1679 /* Stop the primary connection: */
1681 /* ...halt the connection */
1682 q_params.cmd = ECORE_Q_CMD_HALT;
1683 rc = ecore_queue_state_change(sc, &q_params);
1688 /* ...terminate the connection */
1689 q_params.cmd = ECORE_Q_CMD_TERMINATE;
1690 memset(&q_params.params.terminate, 0,
1691 sizeof(q_params.params.terminate));
1692 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
1693 rc = ecore_queue_state_change(sc, &q_params);
1698 /* ...delete cfc entry */
1699 q_params.cmd = ECORE_Q_CMD_CFC_DEL;
1700 memset(&q_params.params.cfc_del, 0, sizeof(q_params.params.cfc_del));
1701 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
1702 return ecore_queue_state_change(sc, &q_params);
1705 /* wait for the outstanding SP commands */
1706 static uint8_t bnx2x_wait_sp_comp(struct bnx2x_softc *sc, unsigned long mask)
1709 int tout = 5000; /* wait for 5 secs tops */
1713 if (!(atomic_load_acq_long(&sc->sp_state) & mask)) {
1722 tmp = atomic_load_acq_long(&sc->sp_state);
1724 PMD_DRV_LOG(INFO, "Filtering completion timed out: "
1725 "sp_state 0x%lx, mask 0x%lx", tmp, mask);
1732 static int bnx2x_func_stop(struct bnx2x_softc *sc)
1734 struct ecore_func_state_params func_params = { NULL };
1737 /* prepare parameters for function state transitions */
1738 bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1739 func_params.f_obj = &sc->func_obj;
1740 func_params.cmd = ECORE_F_CMD_STOP;
1743 * Try to stop the function the 'good way'. If it fails (in case
1744 * of a parity error during bnx2x_chip_cleanup()) and we are
1745 * not in a debug mode, perform a state transaction in order to
1746 * enable further HW_RESET transaction.
1748 rc = ecore_func_state_change(sc, &func_params);
1750 PMD_DRV_LOG(NOTICE, "FUNC_STOP ramrod failed. "
1751 "Running a dry transaction");
1752 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1753 return ecore_func_state_change(sc, &func_params);
1759 static int bnx2x_reset_hw(struct bnx2x_softc *sc, uint32_t load_code)
1761 struct ecore_func_state_params func_params = { NULL };
1763 /* Prepare parameters for function state transitions */
1764 bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1766 func_params.f_obj = &sc->func_obj;
1767 func_params.cmd = ECORE_F_CMD_HW_RESET;
1769 func_params.params.hw_init.load_phase = load_code;
1771 return ecore_func_state_change(sc, &func_params);
1774 static void bnx2x_int_disable_sync(struct bnx2x_softc *sc, int disable_hw)
1777 /* prevent the HW from sending interrupts */
1778 bnx2x_int_disable(sc);
1783 bnx2x_chip_cleanup(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1785 int port = SC_PORT(sc);
1786 struct ecore_mcast_ramrod_params rparam = { NULL };
1787 uint32_t reset_code;
1790 bnx2x_drain_tx_queues(sc);
1792 /* give HW time to discard old tx messages */
1795 /* Clean all ETH MACs */
1796 rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_ETH_MAC,
1799 PMD_DRV_LOG(NOTICE, "Failed to delete all ETH MACs (%d)", rc);
1802 /* Clean up UC list */
1803 rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_UC_LIST_MAC,
1806 PMD_DRV_LOG(NOTICE, "Failed to delete UC MACs list (%d)", rc);
1810 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
1812 /* Set "drop all" to stop Rx */
1815 * We need to take the if_maddr_lock() here in order to prevent
1816 * a race between the completion code and this code.
1819 if (bnx2x_test_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) {
1820 bnx2x_set_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state);
1822 bnx2x_set_storm_rx_mode(sc);
1825 /* Clean up multicast configuration */
1826 rparam.mcast_obj = &sc->mcast_obj;
1827 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1830 "Failed to send DEL MCAST command (%d)", rc);
1834 * Send the UNLOAD_REQUEST to the MCP. This will return if
1835 * this function should perform FUNCTION, PORT, or COMMON HW
1838 reset_code = bnx2x_send_unload_req(sc, unload_mode);
1841 * (assumption: No Attention from MCP at this stage)
1842 * PMF probably in the middle of TX disable/enable transaction
1844 rc = bnx2x_func_wait_started(sc);
1846 PMD_DRV_LOG(NOTICE, "bnx2x_func_wait_started failed");
1850 * Close multi and leading connections
1851 * Completions for ramrods are collected in a synchronous way
1853 for (i = 0; i < sc->num_queues; i++) {
1854 if (bnx2x_stop_queue(sc, i)) {
1860 * If SP settings didn't get completed so far - something
1861 * very wrong has happen.
1863 if (!bnx2x_wait_sp_comp(sc, ~0x0UL)) {
1864 PMD_DRV_LOG(NOTICE, "Common slow path ramrods got stuck!");
1869 rc = bnx2x_func_stop(sc);
1871 PMD_DRV_LOG(NOTICE, "Function stop failed!");
1874 /* disable HW interrupts */
1875 bnx2x_int_disable_sync(sc, TRUE);
1877 /* Reset the chip */
1878 rc = bnx2x_reset_hw(sc, reset_code);
1880 PMD_DRV_LOG(NOTICE, "Hardware reset failed");
1883 /* Report UNLOAD_DONE to MCP */
1884 bnx2x_send_unload_done(sc, keep_link);
1887 static void bnx2x_disable_close_the_gate(struct bnx2x_softc *sc)
1891 PMD_DRV_LOG(DEBUG, "Disabling 'close the gates'");
1893 val = REG_RD(sc, MISC_REG_AEU_GENERAL_MASK);
1894 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
1895 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
1896 REG_WR(sc, MISC_REG_AEU_GENERAL_MASK, val);
1900 * Cleans the object that have internal lists without sending
1901 * ramrods. Should be run when interrutps are disabled.
1903 static void bnx2x_squeeze_objects(struct bnx2x_softc *sc)
1905 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1906 struct ecore_mcast_ramrod_params rparam = { NULL };
1907 struct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj;
1910 /* Cleanup MACs' object first... */
1912 /* Wait for completion of requested */
1913 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1914 /* Perform a dry cleanup */
1915 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &ramrod_flags);
1917 /* Clean ETH primary MAC */
1918 bnx2x_set_bit(ECORE_ETH_MAC, &vlan_mac_flags);
1919 rc = mac_obj->delete_all(sc, &sc->sp_objs->mac_obj, &vlan_mac_flags,
1922 PMD_DRV_LOG(NOTICE, "Failed to clean ETH MACs (%d)", rc);
1925 /* Cleanup UC list */
1927 bnx2x_set_bit(ECORE_UC_LIST_MAC, &vlan_mac_flags);
1928 rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1930 PMD_DRV_LOG(NOTICE, "Failed to clean UC list MACs (%d)", rc);
1933 /* Now clean mcast object... */
1935 rparam.mcast_obj = &sc->mcast_obj;
1936 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags);
1938 /* Add a DEL command... */
1939 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1942 "Failed to send DEL MCAST command (%d)", rc);
1945 /* now wait until all pending commands are cleared */
1947 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
1951 "Failed to clean MCAST object (%d)", rc);
1955 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
1959 /* stop the controller */
1962 bnx2x_nic_unload(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1964 uint8_t global = FALSE;
1967 PMD_DRV_LOG(DEBUG, "Starting NIC unload...");
1969 /* mark driver as unloaded in shmem2 */
1970 if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
1971 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
1972 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
1973 val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
1976 if (IS_PF(sc) && sc->recovery_state != BNX2X_RECOVERY_DONE &&
1977 (sc->state == BNX2X_STATE_CLOSED || sc->state == BNX2X_STATE_ERROR)) {
1979 * We can get here if the driver has been unloaded
1980 * during parity error recovery and is either waiting for a
1981 * leader to complete or for other functions to unload and
1982 * then ifconfig down has been issued. In this case we want to
1983 * unload and let other functions to complete a recovery
1986 sc->recovery_state = BNX2X_RECOVERY_DONE;
1988 bnx2x_release_leader_lock(sc);
1991 PMD_DRV_LOG(NOTICE, "Can't unload in closed or error state");
1996 * Nothing to do during unload if previous bnx2x_nic_load()
1997 * did not completed successfully - all resourses are released.
1999 if ((sc->state == BNX2X_STATE_CLOSED) || (sc->state == BNX2X_STATE_ERROR)) {
2003 sc->state = BNX2X_STATE_CLOSING_WAITING_HALT;
2006 sc->rx_mode = BNX2X_RX_MODE_NONE;
2007 bnx2x_set_rx_mode(sc);
2011 /* set ALWAYS_ALIVE bit in shmem */
2012 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2014 bnx2x_drv_pulse(sc);
2016 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2017 bnx2x_save_statistics(sc);
2020 /* wait till consumers catch up with producers in all queues */
2021 bnx2x_drain_tx_queues(sc);
2023 /* if VF indicate to PF this function is going down (PF will delete sp
2024 * elements and clear initializations
2027 bnx2x_vf_unload(sc);
2028 } else if (unload_mode != UNLOAD_RECOVERY) {
2029 /* if this is a normal/close unload need to clean up chip */
2030 bnx2x_chip_cleanup(sc, unload_mode, keep_link);
2032 /* Send the UNLOAD_REQUEST to the MCP */
2033 bnx2x_send_unload_req(sc, unload_mode);
2036 * Prevent transactions to host from the functions on the
2037 * engine that doesn't reset global blocks in case of global
2038 * attention once gloabl blocks are reset and gates are opened
2039 * (the engine which leader will perform the recovery
2042 if (!CHIP_IS_E1x(sc)) {
2043 bnx2x_pf_disable(sc);
2046 /* disable HW interrupts */
2047 bnx2x_int_disable_sync(sc, TRUE);
2049 /* Report UNLOAD_DONE to MCP */
2050 bnx2x_send_unload_done(sc, FALSE);
2054 * At this stage no more interrupts will arrive so we may safely clean
2055 * the queue'able objects here in case they failed to get cleaned so far.
2058 bnx2x_squeeze_objects(sc);
2061 /* There should be no more pending SP commands at this stage */
2070 bnx2x_free_fw_stats_mem(sc);
2072 sc->state = BNX2X_STATE_CLOSED;
2075 * Check if there are pending parity attentions. If there are - set
2076 * RECOVERY_IN_PROGRESS.
2078 if (IS_PF(sc) && bnx2x_chk_parity_attn(sc, &global, FALSE)) {
2079 bnx2x_set_reset_in_progress(sc);
2081 /* Set RESET_IS_GLOBAL if needed */
2083 bnx2x_set_reset_global(sc);
2088 * The last driver must disable a "close the gate" if there is no
2089 * parity attention or "process kill" pending.
2091 if (IS_PF(sc) && !bnx2x_clear_pf_load(sc) &&
2092 bnx2x_reset_is_done(sc, SC_PATH(sc))) {
2093 bnx2x_disable_close_the_gate(sc);
2096 PMD_DRV_LOG(DEBUG, "Ended NIC unload");
2102 * Encapsulte an mbuf cluster into the tx bd chain and makes the memory
2103 * visible to the controller.
2105 * If an mbuf is submitted to this routine and cannot be given to the
2106 * controller (e.g. it has too many fragments) then the function may free
2107 * the mbuf and return to the caller.
2110 * int: Number of TX BDs used for the mbuf
2112 * Note the side effect that an mbuf may be freed if it causes a problem.
2114 int bnx2x_tx_encap(struct bnx2x_tx_queue *txq, struct rte_mbuf *m0)
2116 struct eth_tx_start_bd *tx_start_bd;
2117 uint16_t bd_prod, pkt_prod;
2118 struct bnx2x_softc *sc;
2122 bd_prod = txq->tx_bd_tail;
2123 pkt_prod = txq->tx_pkt_tail;
2125 txq->sw_ring[TX_BD(pkt_prod, txq)] = m0;
2127 tx_start_bd = &txq->tx_ring[TX_BD(bd_prod, txq)].start_bd;
2130 rte_cpu_to_le_64(rte_mbuf_data_iova(m0));
2131 tx_start_bd->nbytes = rte_cpu_to_le_16(m0->data_len);
2132 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2133 tx_start_bd->general_data =
2134 (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
2136 tx_start_bd->nbd = rte_cpu_to_le_16(2);
2138 if (m0->ol_flags & PKT_TX_VLAN_PKT) {
2139 tx_start_bd->vlan_or_ethertype =
2140 rte_cpu_to_le_16(m0->vlan_tci);
2141 tx_start_bd->bd_flags.as_bitfield |=
2142 (X_ETH_OUTBAND_VLAN <<
2143 ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT);
2146 tx_start_bd->vlan_or_ethertype =
2147 rte_cpu_to_le_16(pkt_prod);
2149 struct ether_hdr *eh =
2150 rte_pktmbuf_mtod(m0, struct ether_hdr *);
2152 tx_start_bd->vlan_or_ethertype =
2153 rte_cpu_to_le_16(rte_be_to_cpu_16(eh->ether_type));
2157 bd_prod = NEXT_TX_BD(bd_prod);
2159 struct eth_tx_parse_bd_e2 *tx_parse_bd;
2160 const struct ether_hdr *eh =
2161 rte_pktmbuf_mtod(m0, struct ether_hdr *);
2162 uint8_t mac_type = UNICAST_ADDRESS;
2165 &txq->tx_ring[TX_BD(bd_prod, txq)].parse_bd_e2;
2166 if (is_multicast_ether_addr(&eh->d_addr)) {
2167 if (is_broadcast_ether_addr(&eh->d_addr))
2168 mac_type = BROADCAST_ADDRESS;
2170 mac_type = MULTICAST_ADDRESS;
2172 tx_parse_bd->parsing_data =
2173 (mac_type << ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT);
2175 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_hi,
2176 &eh->d_addr.addr_bytes[0], 2);
2177 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_mid,
2178 &eh->d_addr.addr_bytes[2], 2);
2179 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_lo,
2180 &eh->d_addr.addr_bytes[4], 2);
2181 rte_memcpy(&tx_parse_bd->data.mac_addr.src_hi,
2182 &eh->s_addr.addr_bytes[0], 2);
2183 rte_memcpy(&tx_parse_bd->data.mac_addr.src_mid,
2184 &eh->s_addr.addr_bytes[2], 2);
2185 rte_memcpy(&tx_parse_bd->data.mac_addr.src_lo,
2186 &eh->s_addr.addr_bytes[4], 2);
2188 tx_parse_bd->data.mac_addr.dst_hi =
2189 rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_hi);
2190 tx_parse_bd->data.mac_addr.dst_mid =
2191 rte_cpu_to_be_16(tx_parse_bd->data.
2193 tx_parse_bd->data.mac_addr.dst_lo =
2194 rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_lo);
2195 tx_parse_bd->data.mac_addr.src_hi =
2196 rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_hi);
2197 tx_parse_bd->data.mac_addr.src_mid =
2198 rte_cpu_to_be_16(tx_parse_bd->data.
2200 tx_parse_bd->data.mac_addr.src_lo =
2201 rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_lo);
2204 "PBD dst %x %x %x src %x %x %x p_data %x",
2205 tx_parse_bd->data.mac_addr.dst_hi,
2206 tx_parse_bd->data.mac_addr.dst_mid,
2207 tx_parse_bd->data.mac_addr.dst_lo,
2208 tx_parse_bd->data.mac_addr.src_hi,
2209 tx_parse_bd->data.mac_addr.src_mid,
2210 tx_parse_bd->data.mac_addr.src_lo,
2211 tx_parse_bd->parsing_data);
2215 "start bd: nbytes %d flags %x vlan %x",
2216 tx_start_bd->nbytes,
2217 tx_start_bd->bd_flags.as_bitfield,
2218 tx_start_bd->vlan_or_ethertype);
2220 bd_prod = NEXT_TX_BD(bd_prod);
2223 if (TX_IDX(bd_prod) < 2)
2226 txq->nb_tx_avail -= 2;
2227 txq->tx_bd_tail = bd_prod;
2228 txq->tx_pkt_tail = pkt_prod;
2233 static uint16_t bnx2x_cid_ilt_lines(struct bnx2x_softc *sc)
2235 return L2_ILT_LINES(sc);
2238 static void bnx2x_ilt_set_info(struct bnx2x_softc *sc)
2240 struct ilt_client_info *ilt_client;
2241 struct ecore_ilt *ilt = sc->ilt;
2244 PMD_INIT_FUNC_TRACE();
2246 ilt->start_line = FUNC_ILT_BASE(SC_FUNC(sc));
2249 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
2250 ilt_client->client_num = ILT_CLIENT_CDU;
2251 ilt_client->page_size = CDU_ILT_PAGE_SZ;
2252 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
2253 ilt_client->start = line;
2254 line += bnx2x_cid_ilt_lines(sc);
2256 if (CNIC_SUPPORT(sc)) {
2257 line += CNIC_ILT_LINES;
2260 ilt_client->end = (line - 1);
2263 if (QM_INIT(sc->qm_cid_count)) {
2264 ilt_client = &ilt->clients[ILT_CLIENT_QM];
2265 ilt_client->client_num = ILT_CLIENT_QM;
2266 ilt_client->page_size = QM_ILT_PAGE_SZ;
2267 ilt_client->flags = 0;
2268 ilt_client->start = line;
2270 /* 4 bytes for each cid */
2271 line += DIV_ROUND_UP(sc->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
2274 ilt_client->end = (line - 1);
2277 if (CNIC_SUPPORT(sc)) {
2279 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
2280 ilt_client->client_num = ILT_CLIENT_SRC;
2281 ilt_client->page_size = SRC_ILT_PAGE_SZ;
2282 ilt_client->flags = 0;
2283 ilt_client->start = line;
2284 line += SRC_ILT_LINES;
2285 ilt_client->end = (line - 1);
2288 ilt_client = &ilt->clients[ILT_CLIENT_TM];
2289 ilt_client->client_num = ILT_CLIENT_TM;
2290 ilt_client->page_size = TM_ILT_PAGE_SZ;
2291 ilt_client->flags = 0;
2292 ilt_client->start = line;
2293 line += TM_ILT_LINES;
2294 ilt_client->end = (line - 1);
2297 assert((line <= ILT_MAX_LINES));
2300 static void bnx2x_set_fp_rx_buf_size(struct bnx2x_softc *sc)
2304 for (i = 0; i < sc->num_queues; i++) {
2305 /* get the Rx buffer size for RX frames */
2306 sc->fp[i].rx_buf_size =
2307 (IP_HEADER_ALIGNMENT_PADDING + ETH_OVERHEAD + sc->mtu);
2311 int bnx2x_alloc_ilt_mem(struct bnx2x_softc *sc)
2314 sc->ilt = rte_malloc("", sizeof(struct ecore_ilt), RTE_CACHE_LINE_SIZE);
2316 return sc->ilt == NULL;
2319 static int bnx2x_alloc_ilt_lines_mem(struct bnx2x_softc *sc)
2321 sc->ilt->lines = rte_calloc("",
2322 sizeof(struct ilt_line), ILT_MAX_LINES,
2323 RTE_CACHE_LINE_SIZE);
2324 return sc->ilt->lines == NULL;
2327 void bnx2x_free_ilt_mem(struct bnx2x_softc *sc)
2333 static void bnx2x_free_ilt_lines_mem(struct bnx2x_softc *sc)
2335 if (sc->ilt->lines != NULL) {
2336 rte_free(sc->ilt->lines);
2337 sc->ilt->lines = NULL;
2341 static void bnx2x_free_mem(struct bnx2x_softc *sc)
2345 for (i = 0; i < L2_ILT_LINES(sc); i++) {
2346 sc->context[i].vcxt = NULL;
2347 sc->context[i].size = 0;
2350 ecore_ilt_mem_op(sc, ILT_MEMOP_FREE);
2352 bnx2x_free_ilt_lines_mem(sc);
2355 static int bnx2x_alloc_mem(struct bnx2x_softc *sc)
2360 char cdu_name[RTE_MEMZONE_NAMESIZE];
2363 * Allocate memory for CDU context:
2364 * This memory is allocated separately and not in the generic ILT
2365 * functions because CDU differs in few aspects:
2366 * 1. There can be multiple entities allocating memory for context -
2367 * regular L2, CNIC, and SRIOV drivers. Each separately controls
2368 * its own ILT lines.
2369 * 2. Since CDU page-size is not a single 4KB page (which is the case
2370 * for the other ILT clients), to be efficient we want to support
2371 * allocation of sub-page-size in the last entry.
2372 * 3. Context pointers are used by the driver to pass to FW / update
2373 * the context (for the other ILT clients the pointers are used just to
2374 * free the memory during unload).
2376 context_size = (sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(sc));
2377 for (i = 0, allocated = 0; allocated < context_size; i++) {
2378 sc->context[i].size = min(CDU_ILT_PAGE_SZ,
2379 (context_size - allocated));
2381 snprintf(cdu_name, sizeof(cdu_name), "cdu_%d", i);
2382 if (bnx2x_dma_alloc(sc, sc->context[i].size,
2383 &sc->context[i].vcxt_dma,
2384 cdu_name, BNX2X_PAGE_SIZE) != 0) {
2389 sc->context[i].vcxt =
2390 (union cdu_context *)sc->context[i].vcxt_dma.vaddr;
2392 allocated += sc->context[i].size;
2395 bnx2x_alloc_ilt_lines_mem(sc);
2397 if (ecore_ilt_mem_op(sc, ILT_MEMOP_ALLOC)) {
2398 PMD_DRV_LOG(NOTICE, "ecore_ilt_mem_op ILT_MEMOP_ALLOC failed");
2406 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc)
2408 sc->fw_stats_num = 0;
2410 sc->fw_stats_req_size = 0;
2411 sc->fw_stats_req = NULL;
2412 sc->fw_stats_req_mapping = 0;
2414 sc->fw_stats_data_size = 0;
2415 sc->fw_stats_data = NULL;
2416 sc->fw_stats_data_mapping = 0;
2419 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc)
2421 uint8_t num_queue_stats;
2422 int num_groups, vf_headroom = 0;
2424 /* number of queues for statistics is number of eth queues */
2425 num_queue_stats = BNX2X_NUM_ETH_QUEUES(sc);
2428 * Total number of FW statistics requests =
2429 * 1 for port stats + 1 for PF stats + num of queues
2431 sc->fw_stats_num = (2 + num_queue_stats);
2434 * Request is built from stats_query_header and an array of
2435 * stats_query_cmd_group each of which contains STATS_QUERY_CMD_COUNT
2436 * rules. The real number or requests is configured in the
2437 * stats_query_header.
2439 num_groups = (sc->fw_stats_num + vf_headroom) / STATS_QUERY_CMD_COUNT;
2440 if ((sc->fw_stats_num + vf_headroom) % STATS_QUERY_CMD_COUNT)
2443 sc->fw_stats_req_size =
2444 (sizeof(struct stats_query_header) +
2445 (num_groups * sizeof(struct stats_query_cmd_group)));
2448 * Data for statistics requests + stats_counter.
2449 * stats_counter holds per-STORM counters that are incremented when
2450 * STORM has finished with the current request. Memory for FCoE
2451 * offloaded statistics are counted anyway, even if they will not be sent.
2452 * VF stats are not accounted for here as the data of VF stats is stored
2453 * in memory allocated by the VF, not here.
2455 sc->fw_stats_data_size =
2456 (sizeof(struct stats_counter) +
2457 sizeof(struct per_port_stats) + sizeof(struct per_pf_stats) +
2458 /* sizeof(struct fcoe_statistics_params) + */
2459 (sizeof(struct per_queue_stats) * num_queue_stats));
2461 if (bnx2x_dma_alloc(sc, (sc->fw_stats_req_size + sc->fw_stats_data_size),
2462 &sc->fw_stats_dma, "fw_stats",
2463 RTE_CACHE_LINE_SIZE) != 0) {
2464 bnx2x_free_fw_stats_mem(sc);
2468 /* set up the shortcuts */
2470 sc->fw_stats_req = (struct bnx2x_fw_stats_req *)sc->fw_stats_dma.vaddr;
2471 sc->fw_stats_req_mapping = sc->fw_stats_dma.paddr;
2474 (struct bnx2x_fw_stats_data *)((uint8_t *) sc->fw_stats_dma.vaddr +
2475 sc->fw_stats_req_size);
2476 sc->fw_stats_data_mapping = (sc->fw_stats_dma.paddr +
2477 sc->fw_stats_req_size);
2484 * 0-7 - Engine0 load counter.
2485 * 8-15 - Engine1 load counter.
2486 * 16 - Engine0 RESET_IN_PROGRESS bit.
2487 * 17 - Engine1 RESET_IN_PROGRESS bit.
2488 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active
2489 * function on the engine
2490 * 19 - Engine1 ONE_IS_LOADED.
2491 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
2492 * leader to complete (check for both RESET_IN_PROGRESS bits and not
2493 * for just the one belonging to its engine).
2495 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
2496 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
2497 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
2498 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
2499 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
2500 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
2501 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
2502 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
2504 /* set the GLOBAL_RESET bit, should be run under rtnl lock */
2505 static void bnx2x_set_reset_global(struct bnx2x_softc *sc)
2508 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2509 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2510 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
2511 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2514 /* clear the GLOBAL_RESET bit, should be run under rtnl lock */
2515 static void bnx2x_clear_reset_global(struct bnx2x_softc *sc)
2518 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2519 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2520 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
2521 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2524 /* checks the GLOBAL_RESET bit, should be run under rtnl lock */
2525 static uint8_t bnx2x_reset_is_global(struct bnx2x_softc *sc)
2527 return REG_RD(sc, BNX2X_RECOVERY_GLOB_REG) & BNX2X_GLOBAL_RESET_BIT;
2530 /* clear RESET_IN_PROGRESS bit for the engine, should be run under rtnl lock */
2531 static void bnx2x_set_reset_done(struct bnx2x_softc *sc)
2534 uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2535 BNX2X_PATH0_RST_IN_PROG_BIT;
2537 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2539 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2542 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2544 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2547 /* set RESET_IN_PROGRESS for the engine, should be run under rtnl lock */
2548 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc)
2551 uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2552 BNX2X_PATH0_RST_IN_PROG_BIT;
2554 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2556 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2559 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2561 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2564 /* check RESET_IN_PROGRESS bit for an engine, should be run under rtnl lock */
2565 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine)
2567 uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2568 uint32_t bit = engine ? BNX2X_PATH1_RST_IN_PROG_BIT :
2569 BNX2X_PATH0_RST_IN_PROG_BIT;
2571 /* return false if bit is set */
2572 return (val & bit) ? FALSE : TRUE;
2575 /* get the load status for an engine, should be run under rtnl lock */
2576 static uint8_t bnx2x_get_load_status(struct bnx2x_softc *sc, int engine)
2578 uint32_t mask = engine ? BNX2X_PATH1_LOAD_CNT_MASK :
2579 BNX2X_PATH0_LOAD_CNT_MASK;
2580 uint32_t shift = engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2581 BNX2X_PATH0_LOAD_CNT_SHIFT;
2582 uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2584 val = ((val & mask) >> shift);
2589 /* set pf load mark */
2590 static void bnx2x_set_pf_load(struct bnx2x_softc *sc)
2594 uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2595 BNX2X_PATH0_LOAD_CNT_MASK;
2596 uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2597 BNX2X_PATH0_LOAD_CNT_SHIFT;
2599 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2601 PMD_INIT_FUNC_TRACE();
2603 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2605 /* get the current counter value */
2606 val1 = ((val & mask) >> shift);
2608 /* set bit of this PF */
2609 val1 |= (1 << SC_ABS_FUNC(sc));
2611 /* clear the old value */
2614 /* set the new one */
2615 val |= ((val1 << shift) & mask);
2617 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2619 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2622 /* clear pf load mark */
2623 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc)
2626 uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2627 BNX2X_PATH0_LOAD_CNT_MASK;
2628 uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2629 BNX2X_PATH0_LOAD_CNT_SHIFT;
2631 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2632 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2634 /* get the current counter value */
2635 val1 = (val & mask) >> shift;
2637 /* clear bit of that PF */
2638 val1 &= ~(1 << SC_ABS_FUNC(sc));
2640 /* clear the old value */
2643 /* set the new one */
2644 val |= ((val1 << shift) & mask);
2646 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2647 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2651 /* send load requrest to mcp and analyze response */
2652 static int bnx2x_nic_load_request(struct bnx2x_softc *sc, uint32_t * load_code)
2654 PMD_INIT_FUNC_TRACE();
2658 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
2659 DRV_MSG_SEQ_NUMBER_MASK);
2661 PMD_DRV_LOG(DEBUG, "initial fw_seq 0x%04x", sc->fw_seq);
2664 /* get the current FW pulse sequence */
2665 sc->fw_drv_pulse_wr_seq =
2666 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb) &
2667 DRV_PULSE_SEQ_MASK);
2669 /* set ALWAYS_ALIVE bit in shmem */
2670 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2671 bnx2x_drv_pulse(sc);
2675 (*load_code) = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
2676 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
2678 /* if the MCP fails to respond we must abort */
2679 if (!(*load_code)) {
2680 PMD_DRV_LOG(NOTICE, "MCP response failure!");
2684 /* if MCP refused then must abort */
2685 if ((*load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED) {
2686 PMD_DRV_LOG(NOTICE, "MCP refused load request");
2694 * Check whether another PF has already loaded FW to chip. In virtualized
2695 * environments a pf from anoth VM may have already initialized the device
2696 * including loading FW.
2698 static int bnx2x_nic_load_analyze_req(struct bnx2x_softc *sc, uint32_t load_code)
2700 uint32_t my_fw, loaded_fw;
2702 /* is another pf loaded on this engine? */
2703 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
2704 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
2705 /* build my FW version dword */
2706 my_fw = (BNX2X_5710_FW_MAJOR_VERSION +
2707 (BNX2X_5710_FW_MINOR_VERSION << 8) +
2708 (BNX2X_5710_FW_REVISION_VERSION << 16) +
2709 (BNX2X_5710_FW_ENGINEERING_VERSION << 24));
2711 /* read loaded FW from chip */
2712 loaded_fw = REG_RD(sc, XSEM_REG_PRAM);
2713 PMD_DRV_LOG(DEBUG, "loaded FW 0x%08x / my FW 0x%08x",
2716 /* abort nic load if version mismatch */
2717 if (my_fw != loaded_fw) {
2719 "FW 0x%08x already loaded (mine is 0x%08x)",
2728 /* mark PMF if applicable */
2729 static void bnx2x_nic_load_pmf(struct bnx2x_softc *sc, uint32_t load_code)
2731 uint32_t ncsi_oem_data_addr;
2733 PMD_INIT_FUNC_TRACE();
2735 if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
2736 (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
2737 (load_code == FW_MSG_CODE_DRV_LOAD_PORT)) {
2739 * Barrier here for ordering between the writing to sc->port.pmf here
2740 * and reading it from the periodic task.
2748 PMD_DRV_LOG(DEBUG, "pmf %d", sc->port.pmf);
2750 if (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) {
2751 if (SHMEM2_HAS(sc, ncsi_oem_data_addr)) {
2752 ncsi_oem_data_addr = SHMEM2_RD(sc, ncsi_oem_data_addr);
2753 if (ncsi_oem_data_addr) {
2755 (ncsi_oem_data_addr +
2756 offsetof(struct glob_ncsi_oem_data,
2757 driver_version)), 0);
2763 static void bnx2x_read_mf_cfg(struct bnx2x_softc *sc)
2765 int n = (CHIP_IS_MODE_4_PORT(sc) ? 2 : 1);
2769 if (BNX2X_NOMCP(sc)) {
2770 return; /* what should be the default bvalue in this case */
2774 * The formula for computing the absolute function number is...
2775 * For 2 port configuration (4 functions per port):
2776 * abs_func = 2 * vn + SC_PORT + SC_PATH
2777 * For 4 port configuration (2 functions per port):
2778 * abs_func = 4 * vn + 2 * SC_PORT + SC_PATH
2780 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
2781 abs_func = (n * (2 * vn + SC_PORT(sc)) + SC_PATH(sc));
2782 if (abs_func >= E1H_FUNC_MAX) {
2785 sc->devinfo.mf_info.mf_config[vn] =
2786 MFCFG_RD(sc, func_mf_config[abs_func].config);
2789 if (sc->devinfo.mf_info.mf_config[SC_VN(sc)] &
2790 FUNC_MF_CFG_FUNC_DISABLED) {
2791 PMD_DRV_LOG(DEBUG, "mf_cfg function disabled");
2792 sc->flags |= BNX2X_MF_FUNC_DIS;
2794 PMD_DRV_LOG(DEBUG, "mf_cfg function enabled");
2795 sc->flags &= ~BNX2X_MF_FUNC_DIS;
2799 /* acquire split MCP access lock register */
2800 static int bnx2x_acquire_alr(struct bnx2x_softc *sc)
2804 for (j = 0; j < 1000; j++) {
2806 REG_WR(sc, GRCBASE_MCP + 0x9c, val);
2807 val = REG_RD(sc, GRCBASE_MCP + 0x9c);
2808 if (val & (1L << 31))
2814 if (!(val & (1L << 31))) {
2815 PMD_DRV_LOG(NOTICE, "Cannot acquire MCP access lock register");
2822 /* release split MCP access lock register */
2823 static void bnx2x_release_alr(struct bnx2x_softc *sc)
2825 REG_WR(sc, GRCBASE_MCP + 0x9c, 0);
2828 static void bnx2x_fan_failure(struct bnx2x_softc *sc)
2830 int port = SC_PORT(sc);
2831 uint32_t ext_phy_config;
2833 /* mark the failure */
2835 SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
2837 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2838 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
2839 SHMEM_WR(sc, dev_info.port_hw_config[port].external_phy_config,
2842 /* log the failure */
2844 "Fan Failure has caused the driver to shutdown "
2845 "the card to prevent permanent damage. "
2846 "Please contact OEM Support for assistance");
2848 rte_panic("Schedule task to handle fan failure");
2851 /* this function is called upon a link interrupt */
2852 static void bnx2x_link_attn(struct bnx2x_softc *sc)
2854 uint32_t pause_enabled = 0;
2855 struct host_port_stats *pstats;
2858 /* Make sure that we are synced with the current statistics */
2859 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2861 elink_link_update(&sc->link_params, &sc->link_vars);
2863 if (sc->link_vars.link_up) {
2865 /* dropless flow control */
2866 if (sc->dropless_fc) {
2869 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
2874 (BAR_USTRORM_INTMEM +
2875 USTORM_ETH_PAUSE_ENABLED_OFFSET(SC_PORT(sc))),
2879 if (sc->link_vars.mac_type != ELINK_MAC_TYPE_EMAC) {
2880 pstats = BNX2X_SP(sc, port_stats);
2881 /* reset old mac stats */
2882 memset(&(pstats->mac_stx[0]), 0,
2883 sizeof(struct mac_stx));
2886 if (sc->state == BNX2X_STATE_OPEN) {
2887 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
2891 if (sc->link_vars.link_up && sc->link_vars.line_speed) {
2892 cmng_fns = bnx2x_get_cmng_fns_mode(sc);
2894 if (cmng_fns != CMNG_FNS_NONE) {
2895 bnx2x_cmng_fns_init(sc, FALSE, cmng_fns);
2896 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
2900 bnx2x_link_report(sc);
2903 bnx2x_link_sync_notify(sc);
2907 static void bnx2x_attn_int_asserted(struct bnx2x_softc *sc, uint32_t asserted)
2909 int port = SC_PORT(sc);
2910 uint32_t aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2911 MISC_REG_AEU_MASK_ATTN_FUNC_0;
2912 uint32_t nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2913 NIG_REG_MASK_INTERRUPT_PORT0;
2915 uint32_t nig_mask = 0;
2920 if (sc->attn_state & asserted) {
2921 PMD_DRV_LOG(ERR, "IGU ERROR attn=0x%08x", asserted);
2924 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2926 aeu_mask = REG_RD(sc, aeu_addr);
2928 aeu_mask &= ~(asserted & 0x3ff);
2930 REG_WR(sc, aeu_addr, aeu_mask);
2932 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2934 sc->attn_state |= asserted;
2936 if (asserted & ATTN_HARD_WIRED_MASK) {
2937 if (asserted & ATTN_NIG_FOR_FUNC) {
2939 /* save nig interrupt mask */
2940 nig_mask = REG_RD(sc, nig_int_mask_addr);
2942 /* If nig_mask is not set, no need to call the update function */
2944 REG_WR(sc, nig_int_mask_addr, 0);
2946 bnx2x_link_attn(sc);
2949 /* handle unicore attn? */
2952 if (asserted & ATTN_SW_TIMER_4_FUNC) {
2953 PMD_DRV_LOG(DEBUG, "ATTN_SW_TIMER_4_FUNC!");
2956 if (asserted & GPIO_2_FUNC) {
2957 PMD_DRV_LOG(DEBUG, "GPIO_2_FUNC!");
2960 if (asserted & GPIO_3_FUNC) {
2961 PMD_DRV_LOG(DEBUG, "GPIO_3_FUNC!");
2964 if (asserted & GPIO_4_FUNC) {
2965 PMD_DRV_LOG(DEBUG, "GPIO_4_FUNC!");
2969 if (asserted & ATTN_GENERAL_ATTN_1) {
2970 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_1!");
2971 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
2973 if (asserted & ATTN_GENERAL_ATTN_2) {
2974 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_2!");
2975 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
2977 if (asserted & ATTN_GENERAL_ATTN_3) {
2978 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_3!");
2979 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
2982 if (asserted & ATTN_GENERAL_ATTN_4) {
2983 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_4!");
2984 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
2986 if (asserted & ATTN_GENERAL_ATTN_5) {
2987 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_5!");
2988 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
2990 if (asserted & ATTN_GENERAL_ATTN_6) {
2991 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_6!");
2992 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
2997 if (sc->devinfo.int_block == INT_BLOCK_HC) {
2999 (HC_REG_COMMAND_REG + port * 32 +
3000 COMMAND_REG_ATTN_BITS_SET);
3002 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER * 8);
3005 PMD_DRV_LOG(DEBUG, "about to mask 0x%08x at %s addr 0x%08x",
3007 (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
3009 REG_WR(sc, reg_addr, asserted);
3011 /* now set back the mask */
3012 if (asserted & ATTN_NIG_FOR_FUNC) {
3014 * Verify that IGU ack through BAR was written before restoring
3015 * NIG mask. This loop should exit after 2-3 iterations max.
3017 if (sc->devinfo.int_block != INT_BLOCK_HC) {
3022 REG_RD(sc, IGU_REG_ATTENTION_ACK_BITS);
3023 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0)
3024 && (++cnt < MAX_IGU_ATTN_ACK_TO));
3028 "Failed to verify IGU ack on time");
3034 REG_WR(sc, nig_int_mask_addr, nig_mask);
3040 bnx2x_print_next_block(__rte_unused struct bnx2x_softc *sc, __rte_unused int idx,
3041 __rte_unused const char *blk)
3043 PMD_DRV_LOG(INFO, "%s%s", idx ? ", " : "", blk);
3047 bnx2x_check_blocks_with_parity0(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3050 uint32_t cur_bit = 0;
3053 for (i = 0; sig; i++) {
3054 cur_bit = ((uint32_t) 0x1 << i);
3055 if (sig & cur_bit) {
3057 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3059 bnx2x_print_next_block(sc, par_num++,
3062 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3064 bnx2x_print_next_block(sc, par_num++,
3067 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3069 bnx2x_print_next_block(sc, par_num++,
3072 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3074 bnx2x_print_next_block(sc, par_num++,
3077 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3079 bnx2x_print_next_block(sc, par_num++,
3082 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3084 bnx2x_print_next_block(sc, par_num++,
3087 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3089 bnx2x_print_next_block(sc, par_num++,
3103 bnx2x_check_blocks_with_parity1(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3104 uint8_t * global, uint8_t print)
3107 uint32_t cur_bit = 0;
3108 for (i = 0; sig; i++) {
3109 cur_bit = ((uint32_t) 0x1 << i);
3110 if (sig & cur_bit) {
3112 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3114 bnx2x_print_next_block(sc, par_num++,
3117 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3119 bnx2x_print_next_block(sc, par_num++,
3122 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3124 bnx2x_print_next_block(sc, par_num++,
3127 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3129 bnx2x_print_next_block(sc, par_num++,
3132 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
3134 bnx2x_print_next_block(sc, par_num++,
3137 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3139 bnx2x_print_next_block(sc, par_num++,
3142 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3144 bnx2x_print_next_block(sc, par_num++,
3147 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
3149 bnx2x_print_next_block(sc, par_num++,
3152 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3154 bnx2x_print_next_block(sc, par_num++,
3158 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3160 bnx2x_print_next_block(sc, par_num++,
3163 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3165 bnx2x_print_next_block(sc, par_num++,
3168 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
3170 bnx2x_print_next_block(sc, par_num++,
3173 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3175 bnx2x_print_next_block(sc, par_num++,
3178 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3180 bnx2x_print_next_block(sc, par_num++,
3183 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3185 bnx2x_print_next_block(sc, par_num++,
3188 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
3190 bnx2x_print_next_block(sc, par_num++,
3204 bnx2x_check_blocks_with_parity2(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3207 uint32_t cur_bit = 0;
3210 for (i = 0; sig; i++) {
3211 cur_bit = ((uint32_t) 0x1 << i);
3212 if (sig & cur_bit) {
3214 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3216 bnx2x_print_next_block(sc, par_num++,
3219 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3221 bnx2x_print_next_block(sc, par_num++,
3224 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3226 bnx2x_print_next_block(sc, par_num++,
3227 "PXPPCICLOCKCLIENT");
3229 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3231 bnx2x_print_next_block(sc, par_num++,
3234 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3236 bnx2x_print_next_block(sc, par_num++,
3239 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
3241 bnx2x_print_next_block(sc, par_num++,
3244 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3246 bnx2x_print_next_block(sc, par_num++,
3249 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3251 bnx2x_print_next_block(sc, par_num++,
3265 bnx2x_check_blocks_with_parity3(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3266 uint8_t * global, uint8_t print)
3268 uint32_t cur_bit = 0;
3271 for (i = 0; sig; i++) {
3272 cur_bit = ((uint32_t) 0x1 << i);
3273 if (sig & cur_bit) {
3275 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3277 bnx2x_print_next_block(sc, par_num++,
3281 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3283 bnx2x_print_next_block(sc, par_num++,
3287 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3289 bnx2x_print_next_block(sc, par_num++,
3293 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3295 bnx2x_print_next_block(sc, par_num++,
3310 bnx2x_check_blocks_with_parity4(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3313 uint32_t cur_bit = 0;
3316 for (i = 0; sig; i++) {
3317 cur_bit = ((uint32_t) 0x1 << i);
3318 if (sig & cur_bit) {
3320 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
3322 bnx2x_print_next_block(sc, par_num++,
3325 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
3327 bnx2x_print_next_block(sc, par_num++,
3341 bnx2x_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print,
3346 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
3347 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
3348 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
3349 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
3350 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
3352 "Parity error: HW block parity attention:"
3353 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x",
3354 (uint32_t) (sig[0] & HW_PRTY_ASSERT_SET_0),
3355 (uint32_t) (sig[1] & HW_PRTY_ASSERT_SET_1),
3356 (uint32_t) (sig[2] & HW_PRTY_ASSERT_SET_2),
3357 (uint32_t) (sig[3] & HW_PRTY_ASSERT_SET_3),
3358 (uint32_t) (sig[4] & HW_PRTY_ASSERT_SET_4));
3361 PMD_DRV_LOG(INFO, "Parity errors detected in blocks: ");
3364 bnx2x_check_blocks_with_parity0(sc, sig[0] &
3365 HW_PRTY_ASSERT_SET_0,
3368 bnx2x_check_blocks_with_parity1(sc, sig[1] &
3369 HW_PRTY_ASSERT_SET_1,
3370 par_num, global, print);
3372 bnx2x_check_blocks_with_parity2(sc, sig[2] &
3373 HW_PRTY_ASSERT_SET_2,
3376 bnx2x_check_blocks_with_parity3(sc, sig[3] &
3377 HW_PRTY_ASSERT_SET_3,
3378 par_num, global, print);
3380 bnx2x_check_blocks_with_parity4(sc, sig[4] &
3381 HW_PRTY_ASSERT_SET_4,
3385 PMD_DRV_LOG(INFO, "");
3394 bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print)
3396 struct attn_route attn = { {0} };
3397 int port = SC_PORT(sc);
3399 attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
3400 attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
3401 attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
3402 attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
3404 if (!CHIP_IS_E1x(sc))
3406 REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
3408 return bnx2x_parity_attn(sc, global, print, attn.sig);
3411 static void bnx2x_attn_int_deasserted4(struct bnx2x_softc *sc, uint32_t attn)
3415 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
3416 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
3417 PMD_DRV_LOG(INFO, "ERROR: PGLUE hw attention 0x%08x", val);
3418 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
3420 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR");
3421 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
3423 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR");
3424 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
3426 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN");
3427 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
3429 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN");
3431 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
3433 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN");
3435 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
3437 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN");
3438 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
3440 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN");
3441 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
3443 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN");
3444 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
3446 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW");
3449 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
3450 val = REG_RD(sc, ATC_REG_ATC_INT_STS_CLR);
3451 PMD_DRV_LOG(INFO, "ERROR: ATC hw attention 0x%08x", val);
3452 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
3454 "ERROR: ATC_ATC_INT_STS_REG_ADDRESS_ERROR");
3455 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
3457 "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND");
3458 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
3460 "ERROR: ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS");
3461 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
3463 "ERROR: ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT");
3464 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
3466 "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR");
3467 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
3469 "ERROR: ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU");
3472 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3473 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
3475 "ERROR: FATAL parity attention set4 0x%08x",
3477 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
3479 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
3483 static void bnx2x_e1h_disable(struct bnx2x_softc *sc)
3485 int port = SC_PORT(sc);
3487 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
3490 static void bnx2x_e1h_enable(struct bnx2x_softc *sc)
3492 int port = SC_PORT(sc);
3494 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3498 * called due to MCP event (on pmf):
3499 * reread new bandwidth configuration
3501 * notify others function about the change
3503 static void bnx2x_config_mf_bw(struct bnx2x_softc *sc)
3505 if (sc->link_vars.link_up) {
3506 bnx2x_cmng_fns_init(sc, TRUE, CMNG_FNS_MINMAX);
3507 bnx2x_link_sync_notify(sc);
3510 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
3513 static void bnx2x_set_mf_bw(struct bnx2x_softc *sc)
3515 bnx2x_config_mf_bw(sc);
3516 bnx2x_fw_command(sc, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3519 static void bnx2x_handle_eee_event(struct bnx2x_softc *sc)
3521 bnx2x_fw_command(sc, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3524 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3526 static void bnx2x_drv_info_ether_stat(struct bnx2x_softc *sc)
3528 struct eth_stats_info *ether_stat = &sc->sp->drv_info_to_mcp.ether_stat;
3530 strncpy(ether_stat->version, BNX2X_DRIVER_VERSION,
3531 ETH_STAT_INFO_VERSION_LEN);
3533 sc->sp_objs[0].mac_obj.get_n_elements(sc, &sc->sp_objs[0].mac_obj,
3534 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3535 ether_stat->mac_local + MAC_PAD,
3538 ether_stat->mtu_size = sc->mtu;
3540 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3541 ether_stat->promiscuous_mode = 0; // (flags & PROMISC) ? 1 : 0;
3543 ether_stat->txq_size = sc->tx_ring_size;
3544 ether_stat->rxq_size = sc->rx_ring_size;
3547 static void bnx2x_handle_drv_info_req(struct bnx2x_softc *sc)
3549 enum drv_info_opcode op_code;
3550 uint32_t drv_info_ctl = SHMEM2_RD(sc, drv_info_control);
3552 /* if drv_info version supported by MFW doesn't match - send NACK */
3553 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3554 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3558 op_code = ((drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3559 DRV_INFO_CONTROL_OP_CODE_SHIFT);
3561 memset(&sc->sp->drv_info_to_mcp, 0, sizeof(union drv_info_to_mcp));
3564 case ETH_STATS_OPCODE:
3565 bnx2x_drv_info_ether_stat(sc);
3567 case FCOE_STATS_OPCODE:
3568 case ISCSI_STATS_OPCODE:
3570 /* if op code isn't supported - send NACK */
3571 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3576 * If we got drv_info attn from MFW then these fields are defined in
3579 SHMEM2_WR(sc, drv_info_host_addr_lo,
3580 U64_LO(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3581 SHMEM2_WR(sc, drv_info_host_addr_hi,
3582 U64_HI(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3584 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3587 static void bnx2x_dcc_event(struct bnx2x_softc *sc, uint32_t dcc_event)
3589 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3591 * This is the only place besides the function initialization
3592 * where the sc->flags can change so it is done without any
3596 mf_info.mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_DISABLED) {
3597 PMD_DRV_LOG(DEBUG, "mf_cfg function disabled");
3598 sc->flags |= BNX2X_MF_FUNC_DIS;
3599 bnx2x_e1h_disable(sc);
3601 PMD_DRV_LOG(DEBUG, "mf_cfg function enabled");
3602 sc->flags &= ~BNX2X_MF_FUNC_DIS;
3603 bnx2x_e1h_enable(sc);
3605 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3608 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3609 bnx2x_config_mf_bw(sc);
3610 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3613 /* Report results to MCP */
3615 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_FAILURE, 0);
3617 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_OK, 0);
3620 static void bnx2x_pmf_update(struct bnx2x_softc *sc)
3622 int port = SC_PORT(sc);
3628 * We need the mb() to ensure the ordering between the writing to
3629 * sc->port.pmf here and reading it from the bnx2x_periodic_task().
3633 /* enable nig attention */
3634 val = (0xff0f | (1 << (SC_VN(sc) + 4)));
3635 if (sc->devinfo.int_block == INT_BLOCK_HC) {
3636 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, val);
3637 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, val);
3638 } else if (!CHIP_IS_E1x(sc)) {
3639 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
3640 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
3643 bnx2x_stats_handle(sc, STATS_EVENT_PMF);
3646 static int bnx2x_mc_assert(struct bnx2x_softc *sc)
3650 __rte_unused uint32_t row0, row1, row2, row3;
3654 REG_RD8(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_INDEX_OFFSET);
3656 PMD_DRV_LOG(ERR, "XSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3658 /* print the asserts */
3659 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3663 BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i));
3666 BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3670 BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3674 BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3677 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3679 "XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3680 i, row3, row2, row1, row0);
3689 REG_RD8(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_INDEX_OFFSET);
3691 PMD_DRV_LOG(ERR, "TSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3694 /* print the asserts */
3695 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3699 BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i));
3702 BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3706 BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3710 BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3713 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3715 "TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3716 i, row3, row2, row1, row0);
3725 REG_RD8(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_INDEX_OFFSET);
3727 PMD_DRV_LOG(ERR, "CSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3730 /* print the asserts */
3731 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3735 BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i));
3738 BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3742 BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3746 BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3749 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3751 "CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3752 i, row3, row2, row1, row0);
3761 REG_RD8(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_INDEX_OFFSET);
3763 PMD_DRV_LOG(ERR, "USTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3766 /* print the asserts */
3767 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3771 BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i));
3774 BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3778 BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3782 BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3785 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3787 "USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3788 i, row3, row2, row1, row0);
3798 static void bnx2x_attn_int_deasserted3(struct bnx2x_softc *sc, uint32_t attn)
3800 int func = SC_FUNC(sc);
3803 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3805 if (attn & BNX2X_PMF_LINK_ASSERT(sc)) {
3807 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
3808 bnx2x_read_mf_cfg(sc);
3809 sc->devinfo.mf_info.mf_config[SC_VN(sc)] =
3811 func_mf_config[SC_ABS_FUNC(sc)].config);
3813 SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_status);
3815 if (val & DRV_STATUS_DCC_EVENT_MASK)
3818 DRV_STATUS_DCC_EVENT_MASK));
3820 if (val & DRV_STATUS_SET_MF_BW)
3821 bnx2x_set_mf_bw(sc);
3823 if (val & DRV_STATUS_DRV_INFO_REQ)
3824 bnx2x_handle_drv_info_req(sc);
3826 if ((sc->port.pmf == 0) && (val & DRV_STATUS_PMF))
3827 bnx2x_pmf_update(sc);
3829 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
3830 bnx2x_handle_eee_event(sc);
3832 if (sc->link_vars.periodic_flags &
3833 ELINK_PERIODIC_FLAGS_LINK_EVENT) {
3834 /* sync with link */
3835 sc->link_vars.periodic_flags &=
3836 ~ELINK_PERIODIC_FLAGS_LINK_EVENT;
3838 bnx2x_link_sync_notify(sc);
3840 bnx2x_link_report(sc);
3844 * Always call it here: bnx2x_link_report() will
3845 * prevent the link indication duplication.
3847 bnx2x_link_status_update(sc);
3849 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3851 PMD_DRV_LOG(ERR, "MC assert!");
3852 bnx2x_mc_assert(sc);
3853 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3854 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3855 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3856 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3857 rte_panic("MC assert!");
3859 } else if (attn & BNX2X_MCP_ASSERT) {
3861 PMD_DRV_LOG(ERR, "MCP assert!");
3862 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3866 "Unknown HW assert! (attn 0x%08x)", attn);
3870 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3871 PMD_DRV_LOG(ERR, "LATCHED attention 0x%08x (masked)", attn);
3872 if (attn & BNX2X_GRC_TIMEOUT) {
3873 val = REG_RD(sc, MISC_REG_GRC_TIMEOUT_ATTN);
3874 PMD_DRV_LOG(ERR, "GRC time-out 0x%08x", val);
3876 if (attn & BNX2X_GRC_RSV) {
3877 val = REG_RD(sc, MISC_REG_GRC_RSV_ATTN);
3878 PMD_DRV_LOG(ERR, "GRC reserved 0x%08x", val);
3880 REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3884 static void bnx2x_attn_int_deasserted2(struct bnx2x_softc *sc, uint32_t attn)
3886 int port = SC_PORT(sc);
3888 uint32_t val0, mask0, val1, mask1;
3891 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3892 val = REG_RD(sc, CFC_REG_CFC_INT_STS_CLR);
3893 PMD_DRV_LOG(ERR, "CFC hw attention 0x%08x", val);
3894 /* CFC error attention */
3896 PMD_DRV_LOG(ERR, "FATAL error from CFC");
3900 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3901 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_0);
3902 PMD_DRV_LOG(ERR, "PXP hw attention-0 0x%08x", val);
3903 /* RQ_USDMDP_FIFO_OVERFLOW */
3904 if (val & 0x18000) {
3905 PMD_DRV_LOG(ERR, "FATAL error from PXP");
3908 if (!CHIP_IS_E1x(sc)) {
3909 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_1);
3910 PMD_DRV_LOG(ERR, "PXP hw attention-1 0x%08x", val);
3913 #define PXP2_EOP_ERROR_BIT PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR
3914 #define AEU_PXP2_HW_INT_BIT AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT
3916 if (attn & AEU_PXP2_HW_INT_BIT) {
3917 /* CQ47854 workaround do not panic on
3918 * PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3920 if (!CHIP_IS_E1x(sc)) {
3921 mask0 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_0);
3922 val1 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_1);
3923 mask1 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_1);
3924 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_0);
3926 * If the only PXP2_EOP_ERROR_BIT is set in
3927 * STS0 and STS1 - clear it
3929 * probably we lose additional attentions between
3930 * STS0 and STS_CLR0, in this case user will not
3931 * be notified about them
3933 if (val0 & mask0 & PXP2_EOP_ERROR_BIT &&
3935 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
3937 /* print the register, since no one can restore it */
3939 "PXP2_REG_PXP2_INT_STS_CLR_0 0x%08x", val0);
3942 * if PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3945 if (val0 & PXP2_EOP_ERROR_BIT) {
3946 PMD_DRV_LOG(ERR, "PXP2_WR_PGLUE_EOP_ERROR");
3949 * if only PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR is
3950 * set then clear attention from PXP2 block without panic
3952 if (((val0 & mask0) == PXP2_EOP_ERROR_BIT) &&
3953 ((val1 & mask1) == 0))
3954 attn &= ~AEU_PXP2_HW_INT_BIT;
3959 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3960 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3961 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3963 val = REG_RD(sc, reg_offset);
3964 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3965 REG_WR(sc, reg_offset, val);
3968 "FATAL HW block attention set2 0x%x",
3969 (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_2));
3970 rte_panic("HW block attention set2");
3974 static void bnx2x_attn_int_deasserted1(struct bnx2x_softc *sc, uint32_t attn)
3976 int port = SC_PORT(sc);
3980 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3981 val = REG_RD(sc, DORQ_REG_DORQ_INT_STS_CLR);
3982 PMD_DRV_LOG(ERR, "DB hw attention 0x%08x", val);
3983 /* DORQ discard attention */
3985 PMD_DRV_LOG(ERR, "FATAL error from DORQ");
3989 if (attn & HW_INTERRUT_ASSERT_SET_1) {
3990 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3991 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3993 val = REG_RD(sc, reg_offset);
3994 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3995 REG_WR(sc, reg_offset, val);
3998 "FATAL HW block attention set1 0x%08x",
3999 (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_1));
4000 rte_panic("HW block attention set1");
4004 static void bnx2x_attn_int_deasserted0(struct bnx2x_softc *sc, uint32_t attn)
4006 int port = SC_PORT(sc);
4010 reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4011 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
4013 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4014 val = REG_RD(sc, reg_offset);
4015 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4016 REG_WR(sc, reg_offset, val);
4018 PMD_DRV_LOG(WARNING, "SPIO5 hw attention");
4020 /* Fan failure attention */
4021 elink_hw_reset_phy(&sc->link_params);
4022 bnx2x_fan_failure(sc);
4025 if ((attn & sc->link_vars.aeu_int_mask) && sc->port.pmf) {
4026 elink_handle_module_detect_int(&sc->link_params);
4029 if (attn & HW_INTERRUT_ASSERT_SET_0) {
4030 val = REG_RD(sc, reg_offset);
4031 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4032 REG_WR(sc, reg_offset, val);
4034 rte_panic("FATAL HW block attention set0 0x%lx",
4035 (attn & HW_INTERRUT_ASSERT_SET_0));
4039 static void bnx2x_attn_int_deasserted(struct bnx2x_softc *sc, uint32_t deasserted)
4041 struct attn_route attn;
4042 struct attn_route *group_mask;
4043 int port = SC_PORT(sc);
4048 uint8_t global = FALSE;
4051 * Need to take HW lock because MCP or other port might also
4052 * try to handle this event.
4054 bnx2x_acquire_alr(sc);
4056 if (bnx2x_chk_parity_attn(sc, &global, TRUE)) {
4057 sc->recovery_state = BNX2X_RECOVERY_INIT;
4059 /* disable HW interrupts */
4060 bnx2x_int_disable(sc);
4061 bnx2x_release_alr(sc);
4065 attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
4066 attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
4067 attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
4068 attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
4069 if (!CHIP_IS_E1x(sc)) {
4071 REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
4076 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4077 if (deasserted & (1 << index)) {
4078 group_mask = &sc->attn_group[index];
4080 bnx2x_attn_int_deasserted4(sc,
4082 sig[4] & group_mask->sig[4]);
4083 bnx2x_attn_int_deasserted3(sc,
4085 sig[3] & group_mask->sig[3]);
4086 bnx2x_attn_int_deasserted1(sc,
4088 sig[1] & group_mask->sig[1]);
4089 bnx2x_attn_int_deasserted2(sc,
4091 sig[2] & group_mask->sig[2]);
4092 bnx2x_attn_int_deasserted0(sc,
4094 sig[0] & group_mask->sig[0]);
4098 bnx2x_release_alr(sc);
4100 if (sc->devinfo.int_block == INT_BLOCK_HC) {
4101 reg_addr = (HC_REG_COMMAND_REG + port * 32 +
4102 COMMAND_REG_ATTN_BITS_CLR);
4104 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER * 8);
4109 "about to mask 0x%08x at %s addr 0x%08x", val,
4110 (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
4112 REG_WR(sc, reg_addr, val);
4114 if (~sc->attn_state & deasserted) {
4115 PMD_DRV_LOG(ERR, "IGU error");
4118 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4119 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4121 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4123 aeu_mask = REG_RD(sc, reg_addr);
4125 aeu_mask |= (deasserted & 0x3ff);
4127 REG_WR(sc, reg_addr, aeu_mask);
4128 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4130 sc->attn_state &= ~deasserted;
4133 static void bnx2x_attn_int(struct bnx2x_softc *sc)
4135 /* read local copy of bits */
4136 uint32_t attn_bits = le32toh(sc->def_sb->atten_status_block.attn_bits);
4138 le32toh(sc->def_sb->atten_status_block.attn_bits_ack);
4139 uint32_t attn_state = sc->attn_state;
4141 /* look for changed bits */
4142 uint32_t asserted = attn_bits & ~attn_ack & ~attn_state;
4143 uint32_t deasserted = ~attn_bits & attn_ack & attn_state;
4146 "attn_bits 0x%08x attn_ack 0x%08x asserted 0x%08x deasserted 0x%08x",
4147 attn_bits, attn_ack, asserted, deasserted);
4149 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) {
4150 PMD_DRV_LOG(ERR, "BAD attention state");
4153 /* handle bits that were raised */
4155 bnx2x_attn_int_asserted(sc, asserted);
4159 bnx2x_attn_int_deasserted(sc, deasserted);
4163 static uint16_t bnx2x_update_dsb_idx(struct bnx2x_softc *sc)
4165 struct host_sp_status_block *def_sb = sc->def_sb;
4168 mb(); /* status block is written to by the chip */
4170 if (sc->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
4171 sc->def_att_idx = def_sb->atten_status_block.attn_bits_index;
4172 rc |= BNX2X_DEF_SB_ATT_IDX;
4175 if (sc->def_idx != def_sb->sp_sb.running_index) {
4176 sc->def_idx = def_sb->sp_sb.running_index;
4177 rc |= BNX2X_DEF_SB_IDX;
4185 static struct ecore_queue_sp_obj *bnx2x_cid_to_q_obj(struct bnx2x_softc *sc,
4188 return &sc->sp_objs[CID_TO_FP(cid, sc)].q_obj;
4191 static void bnx2x_handle_mcast_eqe(struct bnx2x_softc *sc)
4193 struct ecore_mcast_ramrod_params rparam;
4196 memset(&rparam, 0, sizeof(rparam));
4198 rparam.mcast_obj = &sc->mcast_obj;
4200 /* clear pending state for the last command */
4201 sc->mcast_obj.raw.clear_pending(&sc->mcast_obj.raw);
4203 /* if there are pending mcast commands - send them */
4204 if (sc->mcast_obj.check_pending(&sc->mcast_obj)) {
4205 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
4208 "Failed to send pending mcast commands (%d)",
4215 bnx2x_handle_classification_eqe(struct bnx2x_softc *sc, union event_ring_elem *elem)
4217 unsigned long ramrod_flags = 0;
4219 uint32_t cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4220 struct ecore_vlan_mac_obj *vlan_mac_obj;
4222 /* always push next commands out, don't wait here */
4223 bnx2x_set_bit(RAMROD_CONT, &ramrod_flags);
4225 switch (le32toh(elem->message.data.eth_event.echo) >> BNX2X_SWCID_SHIFT) {
4226 case ECORE_FILTER_MAC_PENDING:
4227 PMD_DRV_LOG(DEBUG, "Got SETUP_MAC completions");
4228 vlan_mac_obj = &sc->sp_objs[cid].mac_obj;
4231 case ECORE_FILTER_MCAST_PENDING:
4232 PMD_DRV_LOG(DEBUG, "Got SETUP_MCAST completions");
4233 bnx2x_handle_mcast_eqe(sc);
4237 PMD_DRV_LOG(NOTICE, "Unsupported classification command: %d",
4238 elem->message.data.eth_event.echo);
4242 rc = vlan_mac_obj->complete(sc, vlan_mac_obj, elem, &ramrod_flags);
4245 PMD_DRV_LOG(NOTICE, "Failed to schedule new commands (%d)", rc);
4246 } else if (rc > 0) {
4247 PMD_DRV_LOG(DEBUG, "Scheduled next pending commands...");
4251 static void bnx2x_handle_rx_mode_eqe(struct bnx2x_softc *sc)
4253 bnx2x_clear_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
4255 /* send rx_mode command again if was requested */
4256 if (bnx2x_test_and_clear_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state)) {
4257 bnx2x_set_storm_rx_mode(sc);
4261 static void bnx2x_update_eq_prod(struct bnx2x_softc *sc, uint16_t prod)
4263 storm_memset_eq_prod(sc, prod, SC_FUNC(sc));
4264 wmb(); /* keep prod updates ordered */
4267 static void bnx2x_eq_int(struct bnx2x_softc *sc)
4269 uint16_t hw_cons, sw_cons, sw_prod;
4270 union event_ring_elem *elem;
4275 struct ecore_queue_sp_obj *q_obj;
4276 struct ecore_func_sp_obj *f_obj = &sc->func_obj;
4277 struct ecore_raw_obj *rss_raw = &sc->rss_conf_obj.raw;
4279 hw_cons = le16toh(*sc->eq_cons_sb);
4282 * The hw_cons range is 1-255, 257 - the sw_cons range is 0-254, 256.
4283 * when we get to the next-page we need to adjust so the loop
4284 * condition below will be met. The next element is the size of a
4285 * regular element and hence incrementing by 1
4287 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) {
4292 * This function may never run in parallel with itself for a
4293 * specific sc and no need for a read memory barrier here.
4295 sw_cons = sc->eq_cons;
4296 sw_prod = sc->eq_prod;
4300 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4302 elem = &sc->eq[EQ_DESC(sw_cons)];
4304 /* elem CID originates from FW, actually LE */
4305 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4306 opcode = elem->message.opcode;
4308 /* handle eq element */
4310 case EVENT_RING_OPCODE_STAT_QUERY:
4311 PMD_DEBUG_PERIODIC_LOG(DEBUG, "got statistics completion event %d",
4313 /* nothing to do with stats comp */
4316 case EVENT_RING_OPCODE_CFC_DEL:
4317 /* handle according to cid range */
4318 /* we may want to verify here that the sc state is HALTING */
4319 PMD_DRV_LOG(DEBUG, "got delete ramrod for MULTI[%d]",
4321 q_obj = bnx2x_cid_to_q_obj(sc, cid);
4322 if (q_obj->complete_cmd(sc, q_obj, ECORE_Q_CMD_CFC_DEL)) {
4327 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4328 PMD_DRV_LOG(DEBUG, "got STOP TRAFFIC");
4329 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_STOP)) {
4334 case EVENT_RING_OPCODE_START_TRAFFIC:
4335 PMD_DRV_LOG(DEBUG, "got START TRAFFIC");
4336 if (f_obj->complete_cmd
4337 (sc, f_obj, ECORE_F_CMD_TX_START)) {
4342 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
4343 echo = elem->message.data.function_update_event.echo;
4344 if (echo == SWITCH_UPDATE) {
4346 "got FUNC_SWITCH_UPDATE ramrod");
4347 if (f_obj->complete_cmd(sc, f_obj,
4348 ECORE_F_CMD_SWITCH_UPDATE))
4354 "AFEX: ramrod completed FUNCTION_UPDATE");
4355 f_obj->complete_cmd(sc, f_obj,
4356 ECORE_F_CMD_AFEX_UPDATE);
4360 case EVENT_RING_OPCODE_FORWARD_SETUP:
4361 q_obj = &bnx2x_fwd_sp_obj(sc, q_obj);
4362 if (q_obj->complete_cmd(sc, q_obj,
4363 ECORE_Q_CMD_SETUP_TX_ONLY)) {
4368 case EVENT_RING_OPCODE_FUNCTION_START:
4369 PMD_DRV_LOG(DEBUG, "got FUNC_START ramrod");
4370 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_START)) {
4375 case EVENT_RING_OPCODE_FUNCTION_STOP:
4376 PMD_DRV_LOG(DEBUG, "got FUNC_STOP ramrod");
4377 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_STOP)) {
4383 switch (opcode | sc->state) {
4384 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPEN):
4385 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPENING_WAITING_PORT):
4387 elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4388 PMD_DRV_LOG(DEBUG, "got RSS_UPDATE ramrod. CID %d",
4390 rss_raw->clear_pending(rss_raw);
4393 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4394 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4395 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_CLOSING_WAITING_HALT):
4396 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_OPEN):
4397 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_DIAG):
4398 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4400 "got (un)set mac ramrod");
4401 bnx2x_handle_classification_eqe(sc, elem);
4404 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_OPEN):
4405 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_DIAG):
4406 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4408 "got mcast ramrod");
4409 bnx2x_handle_mcast_eqe(sc);
4412 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_OPEN):
4413 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_DIAG):
4414 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4416 "got rx_mode ramrod");
4417 bnx2x_handle_rx_mode_eqe(sc);
4421 /* unknown event log error and continue */
4422 PMD_DRV_LOG(INFO, "Unknown EQ event %d, sc->state 0x%x",
4423 elem->message.opcode, sc->state);
4431 atomic_add_acq_long(&sc->eq_spq_left, spqe_cnt);
4433 sc->eq_cons = sw_cons;
4434 sc->eq_prod = sw_prod;
4436 /* make sure that above mem writes were issued towards the memory */
4439 /* update producer */
4440 bnx2x_update_eq_prod(sc, sc->eq_prod);
4443 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc)
4448 /* what work needs to be performed? */
4449 status = bnx2x_update_dsb_idx(sc);
4452 if (status & BNX2X_DEF_SB_ATT_IDX) {
4453 PMD_DRV_LOG(DEBUG, "---> ATTN INTR <---");
4455 status &= ~BNX2X_DEF_SB_ATT_IDX;
4459 /* SP events: STAT_QUERY and others */
4460 if (status & BNX2X_DEF_SB_IDX) {
4461 /* handle EQ completions */
4462 PMD_DEBUG_PERIODIC_LOG(DEBUG, "---> EQ INTR <---");
4464 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
4465 le16toh(sc->def_idx), IGU_INT_NOP, 1);
4466 status &= ~BNX2X_DEF_SB_IDX;
4469 /* if status is non zero then something went wrong */
4470 if (unlikely(status)) {
4472 "Got an unknown SP interrupt! (0x%04x)", status);
4475 /* ack status block only if something was actually handled */
4476 bnx2x_ack_sb(sc, sc->igu_dsb_id, ATTENTION_ID,
4477 le16toh(sc->def_att_idx), IGU_INT_ENABLE, 1);
4482 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp, int scan_fp)
4484 struct bnx2x_softc *sc = fp->sc;
4485 uint8_t more_rx = FALSE;
4487 PMD_DRV_LOG(DEBUG, "---> FP TASK QUEUE (%d) <--", fp->index);
4489 /* update the fastpath index */
4490 bnx2x_update_fp_sb_idx(fp);
4493 if (bnx2x_has_rx_work(fp)) {
4494 more_rx = bnx2x_rxeof(sc, fp);
4498 /* still more work to do */
4499 bnx2x_handle_fp_tq(fp, scan_fp);
4504 bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
4505 le16toh(fp->fp_hc_idx), IGU_INT_ENABLE, 1);
4509 * Legacy interrupt entry point.
4511 * Verifies that the controller generated the interrupt and
4512 * then calls a separate routine to handle the various
4513 * interrupt causes: link, RX, and TX.
4515 int bnx2x_intr_legacy(struct bnx2x_softc *sc, int scan_fp)
4517 struct bnx2x_fastpath *fp;
4518 uint32_t status, mask;
4522 * 0 for ustorm, 1 for cstorm
4523 * the bits returned from ack_int() are 0-15
4524 * bit 0 = attention status block
4525 * bit 1 = fast path status block
4526 * a mask of 0x2 or more = tx/rx event
4527 * a mask of 1 = slow path event
4530 status = bnx2x_ack_int(sc);
4532 /* the interrupt is not for us */
4533 if (unlikely(status == 0)) {
4537 PMD_DEBUG_PERIODIC_LOG(DEBUG, "Interrupt status 0x%04x", status);
4538 //bnx2x_dump_status_block(sc);
4540 FOR_EACH_ETH_QUEUE(sc, i) {
4542 mask = (0x2 << (fp->index + CNIC_SUPPORT(sc)));
4543 if (status & mask) {
4544 bnx2x_handle_fp_tq(fp, scan_fp);
4549 if (unlikely(status & 0x1)) {
4550 rc = bnx2x_handle_sp_tq(sc);
4554 if (unlikely(status)) {
4555 PMD_DRV_LOG(WARNING,
4556 "Unexpected fastpath status (0x%08x)!", status);
4562 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc);
4563 static int bnx2x_init_hw_common(struct bnx2x_softc *sc);
4564 static int bnx2x_init_hw_port(struct bnx2x_softc *sc);
4565 static int bnx2x_init_hw_func(struct bnx2x_softc *sc);
4566 static void bnx2x_reset_common(struct bnx2x_softc *sc);
4567 static void bnx2x_reset_port(struct bnx2x_softc *sc);
4568 static void bnx2x_reset_func(struct bnx2x_softc *sc);
4569 static int bnx2x_init_firmware(struct bnx2x_softc *sc);
4570 static void bnx2x_release_firmware(struct bnx2x_softc *sc);
4573 ecore_func_sp_drv_ops bnx2x_func_sp_drv = {
4574 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
4575 .init_hw_cmn = bnx2x_init_hw_common,
4576 .init_hw_port = bnx2x_init_hw_port,
4577 .init_hw_func = bnx2x_init_hw_func,
4579 .reset_hw_cmn = bnx2x_reset_common,
4580 .reset_hw_port = bnx2x_reset_port,
4581 .reset_hw_func = bnx2x_reset_func,
4583 .init_fw = bnx2x_init_firmware,
4584 .release_fw = bnx2x_release_firmware,
4587 static void bnx2x_init_func_obj(struct bnx2x_softc *sc)
4591 PMD_INIT_FUNC_TRACE();
4593 ecore_init_func_obj(sc,
4595 BNX2X_SP(sc, func_rdata),
4596 (rte_iova_t)BNX2X_SP_MAPPING(sc, func_rdata),
4597 BNX2X_SP(sc, func_afex_rdata),
4598 (rte_iova_t)BNX2X_SP_MAPPING(sc, func_afex_rdata),
4599 &bnx2x_func_sp_drv);
4602 static int bnx2x_init_hw(struct bnx2x_softc *sc, uint32_t load_code)
4604 struct ecore_func_state_params func_params = { NULL };
4607 PMD_INIT_FUNC_TRACE();
4609 /* prepare the parameters for function state transitions */
4610 bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
4612 func_params.f_obj = &sc->func_obj;
4613 func_params.cmd = ECORE_F_CMD_HW_INIT;
4615 func_params.params.hw_init.load_phase = load_code;
4618 * Via a plethora of function pointers, we will eventually reach
4619 * bnx2x_init_hw_common(), bnx2x_init_hw_port(), or bnx2x_init_hw_func().
4621 rc = ecore_func_state_change(sc, &func_params);
4627 bnx2x_fill(struct bnx2x_softc *sc, uint32_t addr, int fill, uint32_t len)
4631 if (!(len % 4) && !(addr % 4)) {
4632 for (i = 0; i < len; i += 4) {
4633 REG_WR(sc, (addr + i), fill);
4636 for (i = 0; i < len; i++) {
4637 REG_WR8(sc, (addr + i), fill);
4642 /* writes FP SP data to FW - data_size in dwords */
4644 bnx2x_wr_fp_sb_data(struct bnx2x_softc *sc, int fw_sb_id, uint32_t * sb_data_p,
4649 for (index = 0; index < data_size; index++) {
4651 (BAR_CSTRORM_INTMEM +
4652 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
4653 (sizeof(uint32_t) * index)), *(sb_data_p + index));
4657 static void bnx2x_zero_fp_sb(struct bnx2x_softc *sc, int fw_sb_id)
4659 struct hc_status_block_data_e2 sb_data_e2;
4660 struct hc_status_block_data_e1x sb_data_e1x;
4661 uint32_t *sb_data_p;
4662 uint32_t data_size = 0;
4664 if (!CHIP_IS_E1x(sc)) {
4665 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4666 sb_data_e2.common.state = SB_DISABLED;
4667 sb_data_e2.common.p_func.vf_valid = FALSE;
4668 sb_data_p = (uint32_t *) & sb_data_e2;
4669 data_size = (sizeof(struct hc_status_block_data_e2) /
4672 memset(&sb_data_e1x, 0,
4673 sizeof(struct hc_status_block_data_e1x));
4674 sb_data_e1x.common.state = SB_DISABLED;
4675 sb_data_e1x.common.p_func.vf_valid = FALSE;
4676 sb_data_p = (uint32_t *) & sb_data_e1x;
4677 data_size = (sizeof(struct hc_status_block_data_e1x) /
4681 bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4684 (BAR_CSTRORM_INTMEM + CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id)), 0,
4685 CSTORM_STATUS_BLOCK_SIZE);
4686 bnx2x_fill(sc, (BAR_CSTRORM_INTMEM + CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id)),
4687 0, CSTORM_SYNC_BLOCK_SIZE);
4691 bnx2x_wr_sp_sb_data(struct bnx2x_softc *sc,
4692 struct hc_sp_status_block_data *sp_sb_data)
4697 i < (sizeof(struct hc_sp_status_block_data) / sizeof(uint32_t));
4700 (BAR_CSTRORM_INTMEM +
4701 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(SC_FUNC(sc)) +
4702 (i * sizeof(uint32_t))),
4703 *((uint32_t *) sp_sb_data + i));
4707 static void bnx2x_zero_sp_sb(struct bnx2x_softc *sc)
4709 struct hc_sp_status_block_data sp_sb_data;
4711 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4713 sp_sb_data.state = SB_DISABLED;
4714 sp_sb_data.p_func.vf_valid = FALSE;
4716 bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
4719 (BAR_CSTRORM_INTMEM +
4720 CSTORM_SP_STATUS_BLOCK_OFFSET(SC_FUNC(sc))),
4721 0, CSTORM_SP_STATUS_BLOCK_SIZE);
4723 (BAR_CSTRORM_INTMEM +
4724 CSTORM_SP_SYNC_BLOCK_OFFSET(SC_FUNC(sc))),
4725 0, CSTORM_SP_SYNC_BLOCK_SIZE);
4729 bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, int igu_sb_id,
4732 hc_sm->igu_sb_id = igu_sb_id;
4733 hc_sm->igu_seg_id = igu_seg_id;
4734 hc_sm->timer_value = 0xFF;
4735 hc_sm->time_to_expire = 0xFFFFFFFF;
4738 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
4740 /* zero out state machine indices */
4743 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4746 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4747 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
4748 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
4749 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
4754 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
4755 (SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4758 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
4759 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4760 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
4761 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4762 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
4763 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4764 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
4765 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4769 bnx2x_init_sb(struct bnx2x_softc *sc, rte_iova_t busaddr, int vfid,
4770 uint8_t vf_valid, int fw_sb_id, int igu_sb_id)
4772 struct hc_status_block_data_e2 sb_data_e2;
4773 struct hc_status_block_data_e1x sb_data_e1x;
4774 struct hc_status_block_sm *hc_sm_p;
4775 uint32_t *sb_data_p;
4779 if (CHIP_INT_MODE_IS_BC(sc)) {
4780 igu_seg_id = HC_SEG_ACCESS_NORM;
4782 igu_seg_id = IGU_SEG_ACCESS_NORM;
4785 bnx2x_zero_fp_sb(sc, fw_sb_id);
4787 if (!CHIP_IS_E1x(sc)) {
4788 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4789 sb_data_e2.common.state = SB_ENABLED;
4790 sb_data_e2.common.p_func.pf_id = SC_FUNC(sc);
4791 sb_data_e2.common.p_func.vf_id = vfid;
4792 sb_data_e2.common.p_func.vf_valid = vf_valid;
4793 sb_data_e2.common.p_func.vnic_id = SC_VN(sc);
4794 sb_data_e2.common.same_igu_sb_1b = TRUE;
4795 sb_data_e2.common.host_sb_addr.hi = U64_HI(busaddr);
4796 sb_data_e2.common.host_sb_addr.lo = U64_LO(busaddr);
4797 hc_sm_p = sb_data_e2.common.state_machine;
4798 sb_data_p = (uint32_t *) & sb_data_e2;
4799 data_size = (sizeof(struct hc_status_block_data_e2) /
4801 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
4803 memset(&sb_data_e1x, 0,
4804 sizeof(struct hc_status_block_data_e1x));
4805 sb_data_e1x.common.state = SB_ENABLED;
4806 sb_data_e1x.common.p_func.pf_id = SC_FUNC(sc);
4807 sb_data_e1x.common.p_func.vf_id = 0xff;
4808 sb_data_e1x.common.p_func.vf_valid = FALSE;
4809 sb_data_e1x.common.p_func.vnic_id = SC_VN(sc);
4810 sb_data_e1x.common.same_igu_sb_1b = TRUE;
4811 sb_data_e1x.common.host_sb_addr.hi = U64_HI(busaddr);
4812 sb_data_e1x.common.host_sb_addr.lo = U64_LO(busaddr);
4813 hc_sm_p = sb_data_e1x.common.state_machine;
4814 sb_data_p = (uint32_t *) & sb_data_e1x;
4815 data_size = (sizeof(struct hc_status_block_data_e1x) /
4817 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
4820 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], igu_sb_id, igu_seg_id);
4821 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], igu_sb_id, igu_seg_id);
4823 /* write indices to HW - PCI guarantees endianity of regpairs */
4824 bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4827 static uint8_t bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp)
4829 if (CHIP_IS_E1x(fp->sc)) {
4830 return fp->cl_id + SC_PORT(fp->sc) * ETH_MAX_RX_CLIENTS_E1H;
4837 bnx2x_rx_ustorm_prods_offset(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
4839 uint32_t offset = BAR_USTRORM_INTMEM;
4842 return PXP_VF_ADDR_USDM_QUEUES_START +
4843 (sc->acquire_resp.resc.hw_qid[fp->index] *
4844 sizeof(struct ustorm_queue_zone_data));
4845 } else if (!CHIP_IS_E1x(sc)) {
4846 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
4848 offset += USTORM_RX_PRODS_E1X_OFFSET(SC_PORT(sc), fp->cl_id);
4854 static void bnx2x_init_eth_fp(struct bnx2x_softc *sc, int idx)
4856 struct bnx2x_fastpath *fp = &sc->fp[idx];
4857 uint32_t cids[ECORE_MULTI_TX_COS] = { 0 };
4858 unsigned long q_type = 0;
4864 fp->igu_sb_id = (sc->igu_base_sb + idx + CNIC_SUPPORT(sc));
4865 fp->fw_sb_id = (sc->base_fw_ndsb + idx + CNIC_SUPPORT(sc));
4867 if (CHIP_IS_E1x(sc))
4868 fp->cl_id = SC_L_ID(sc) + idx;
4870 /* want client ID same as IGU SB ID for non-E1 */
4871 fp->cl_id = fp->igu_sb_id;
4872 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
4874 /* setup sb indices */
4875 if (!CHIP_IS_E1x(sc)) {
4876 fp->sb_index_values = fp->status_block.e2_sb->sb.index_values;
4877 fp->sb_running_index = fp->status_block.e2_sb->sb.running_index;
4879 fp->sb_index_values = fp->status_block.e1x_sb->sb.index_values;
4880 fp->sb_running_index =
4881 fp->status_block.e1x_sb->sb.running_index;
4885 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(sc, fp);
4887 fp->rx_cq_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS];
4889 for (cos = 0; cos < sc->max_cos; cos++) {
4892 fp->tx_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0];
4894 /* nothing more for a VF to do */
4899 bnx2x_init_sb(sc, fp->sb_dma.paddr, BNX2X_VF_ID_INVALID, FALSE,
4900 fp->fw_sb_id, fp->igu_sb_id);
4902 bnx2x_update_fp_sb_idx(fp);
4904 /* Configure Queue State object */
4905 bnx2x_set_bit(ECORE_Q_TYPE_HAS_RX, &q_type);
4906 bnx2x_set_bit(ECORE_Q_TYPE_HAS_TX, &q_type);
4908 ecore_init_queue_obj(sc,
4909 &sc->sp_objs[idx].q_obj,
4914 BNX2X_SP(sc, q_rdata),
4915 (rte_iova_t)BNX2X_SP_MAPPING(sc, q_rdata),
4918 /* configure classification DBs */
4919 ecore_init_mac_obj(sc,
4920 &sc->sp_objs[idx].mac_obj,
4924 BNX2X_SP(sc, mac_rdata),
4925 (rte_iova_t)BNX2X_SP_MAPPING(sc, mac_rdata),
4926 ECORE_FILTER_MAC_PENDING, &sc->sp_state,
4927 ECORE_OBJ_TYPE_RX_TX, &sc->macs_pool);
4931 bnx2x_update_rx_prod(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
4932 uint16_t rx_bd_prod, uint16_t rx_cq_prod)
4934 union ustorm_eth_rx_producers rx_prods;
4937 /* update producers */
4938 rx_prods.prod.bd_prod = rx_bd_prod;
4939 rx_prods.prod.cqe_prod = rx_cq_prod;
4940 rx_prods.prod.reserved = 0;
4943 * Make sure that the BD and SGE data is updated before updating the
4944 * producers since FW might read the BD/SGE right after the producer
4946 * This is only applicable for weak-ordered memory model archs such
4947 * as IA-64. The following barrier is also mandatory since FW will
4948 * assumes BDs must have buffers.
4952 for (i = 0; i < (sizeof(rx_prods) / 4); i++) {
4954 (fp->ustorm_rx_prods_offset + (i * 4)),
4955 rx_prods.raw_data[i]);
4958 wmb(); /* keep prod updates ordered */
4961 static void bnx2x_init_rx_rings(struct bnx2x_softc *sc)
4963 struct bnx2x_fastpath *fp;
4965 struct bnx2x_rx_queue *rxq;
4967 for (i = 0; i < sc->num_queues; i++) {
4969 rxq = sc->rx_queues[fp->index];
4971 PMD_RX_LOG(ERR, "RX queue is NULL");
4975 rxq->rx_bd_head = 0;
4976 rxq->rx_bd_tail = rxq->nb_rx_desc;
4977 rxq->rx_cq_head = 0;
4978 rxq->rx_cq_tail = TOTAL_RCQ_ENTRIES(rxq);
4979 *fp->rx_cq_cons_sb = 0;
4982 * Activate the BD ring...
4983 * Warning, this will generate an interrupt (to the TSTORM)
4984 * so this can only be done after the chip is initialized
4986 bnx2x_update_rx_prod(sc, fp, rxq->rx_bd_tail, rxq->rx_cq_tail);
4994 static void bnx2x_init_tx_ring_one(struct bnx2x_fastpath *fp)
4996 struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
4998 fp->tx_db.data.header.header = 1 << DOORBELL_HDR_DB_TYPE_SHIFT;
4999 fp->tx_db.data.zero_fill1 = 0;
5000 fp->tx_db.data.prod = 0;
5003 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
5007 txq->tx_pkt_tail = 0;
5008 txq->tx_pkt_head = 0;
5009 txq->tx_bd_tail = 0;
5010 txq->tx_bd_head = 0;
5013 static void bnx2x_init_tx_rings(struct bnx2x_softc *sc)
5017 for (i = 0; i < sc->num_queues; i++) {
5018 bnx2x_init_tx_ring_one(&sc->fp[i]);
5022 static void bnx2x_init_def_sb(struct bnx2x_softc *sc)
5024 struct host_sp_status_block *def_sb = sc->def_sb;
5025 rte_iova_t mapping = sc->def_sb_dma.paddr;
5026 int igu_sp_sb_index;
5028 int port = SC_PORT(sc);
5029 int func = SC_FUNC(sc);
5030 int reg_offset, reg_offset_en5;
5033 struct hc_sp_status_block_data sp_sb_data;
5035 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5037 if (CHIP_INT_MODE_IS_BC(sc)) {
5038 igu_sp_sb_index = DEF_SB_IGU_ID;
5039 igu_seg_id = HC_SEG_ACCESS_DEF;
5041 igu_sp_sb_index = sc->igu_dsb_id;
5042 igu_seg_id = IGU_SEG_ACCESS_DEF;
5046 section = ((uint64_t) mapping +
5047 offsetof(struct host_sp_status_block, atten_status_block));
5048 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5051 reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5052 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
5054 reg_offset_en5 = (port) ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5055 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0;
5057 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5058 /* take care of sig[0]..sig[4] */
5059 for (sindex = 0; sindex < 4; sindex++) {
5060 sc->attn_group[index].sig[sindex] =
5062 (reg_offset + (sindex * 0x4) +
5066 if (!CHIP_IS_E1x(sc)) {
5068 * enable5 is separate from the rest of the registers,
5069 * and the address skip is 4 and not 16 between the
5072 sc->attn_group[index].sig[4] =
5073 REG_RD(sc, (reg_offset_en5 + (0x4 * index)));
5075 sc->attn_group[index].sig[4] = 0;
5079 if (sc->devinfo.int_block == INT_BLOCK_HC) {
5081 port ? HC_REG_ATTN_MSG1_ADDR_L : HC_REG_ATTN_MSG0_ADDR_L;
5082 REG_WR(sc, reg_offset, U64_LO(section));
5083 REG_WR(sc, (reg_offset + 4), U64_HI(section));
5084 } else if (!CHIP_IS_E1x(sc)) {
5085 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5086 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5089 section = ((uint64_t) mapping +
5090 offsetof(struct host_sp_status_block, sp_sb));
5092 bnx2x_zero_sp_sb(sc);
5094 /* PCI guarantees endianity of regpair */
5095 sp_sb_data.state = SB_ENABLED;
5096 sp_sb_data.host_sb_addr.lo = U64_LO(section);
5097 sp_sb_data.host_sb_addr.hi = U64_HI(section);
5098 sp_sb_data.igu_sb_id = igu_sp_sb_index;
5099 sp_sb_data.igu_seg_id = igu_seg_id;
5100 sp_sb_data.p_func.pf_id = func;
5101 sp_sb_data.p_func.vnic_id = SC_VN(sc);
5102 sp_sb_data.p_func.vf_id = 0xff;
5104 bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
5106 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5109 static void bnx2x_init_sp_ring(struct bnx2x_softc *sc)
5111 atomic_store_rel_long(&sc->cq_spq_left, MAX_SPQ_PENDING);
5112 sc->spq_prod_idx = 0;
5114 &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_ETH_DEF_CONS];
5115 sc->spq_prod_bd = sc->spq;
5116 sc->spq_last_bd = (sc->spq_prod_bd + MAX_SP_DESC_CNT);
5119 static void bnx2x_init_eq_ring(struct bnx2x_softc *sc)
5121 union event_ring_elem *elem;
5124 for (i = 1; i <= NUM_EQ_PAGES; i++) {
5125 elem = &sc->eq[EQ_DESC_CNT_PAGE * i - 1];
5127 elem->next_page.addr.hi = htole32(U64_HI(sc->eq_dma.paddr +
5129 (i % NUM_EQ_PAGES)));
5130 elem->next_page.addr.lo = htole32(U64_LO(sc->eq_dma.paddr +
5132 (i % NUM_EQ_PAGES)));
5136 sc->eq_prod = NUM_EQ_DESC;
5137 sc->eq_cons_sb = &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_EQ_CONS];
5139 atomic_store_rel_long(&sc->eq_spq_left,
5140 (min((MAX_SP_DESC_CNT - MAX_SPQ_PENDING),
5144 static void bnx2x_init_internal_common(struct bnx2x_softc *sc)
5150 * In switch independent mode, the TSTORM needs to accept
5151 * packets that failed classification, since approximate match
5152 * mac addresses aren't written to NIG LLH.
5155 (BAR_TSTRORM_INTMEM +
5156 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 2);
5159 (BAR_TSTRORM_INTMEM +
5160 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 0);
5163 * Zero this manually as its initialization is currently missing
5166 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) {
5168 (BAR_USTRORM_INTMEM + USTORM_AGG_DATA_OFFSET + (i * 4)),
5172 if (!CHIP_IS_E1x(sc)) {
5173 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET),
5174 CHIP_INT_MODE_IS_BC(sc) ? HC_IGU_BC_MODE :
5179 static void bnx2x_init_internal(struct bnx2x_softc *sc, uint32_t load_code)
5181 switch (load_code) {
5182 case FW_MSG_CODE_DRV_LOAD_COMMON:
5183 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5184 bnx2x_init_internal_common(sc);
5187 case FW_MSG_CODE_DRV_LOAD_PORT:
5191 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5192 /* internal memory per function is initialized inside bnx2x_pf_init */
5196 PMD_DRV_LOG(NOTICE, "Unknown load_code (0x%x) from MCP",
5203 storm_memset_func_cfg(struct bnx2x_softc *sc,
5204 struct tstorm_eth_function_common_config *tcfg,
5210 addr = (BAR_TSTRORM_INTMEM +
5211 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid));
5212 size = sizeof(struct tstorm_eth_function_common_config);
5213 ecore_storm_memset_struct(sc, addr, size, (uint32_t *) tcfg);
5216 static void bnx2x_func_init(struct bnx2x_softc *sc, struct bnx2x_func_init_params *p)
5218 struct tstorm_eth_function_common_config tcfg = { 0 };
5220 if (CHIP_IS_E1x(sc)) {
5221 storm_memset_func_cfg(sc, &tcfg, p->func_id);
5224 /* Enable the function in the FW */
5225 storm_memset_vf_to_pf(sc, p->func_id, p->pf_id);
5226 storm_memset_func_en(sc, p->func_id, 1);
5229 if (p->func_flgs & FUNC_FLG_SPQ) {
5230 storm_memset_spq_addr(sc, p->spq_map, p->func_id);
5232 (XSEM_REG_FAST_MEMORY +
5233 XSTORM_SPQ_PROD_OFFSET(p->func_id)), p->spq_prod);
5238 * Calculates the sum of vn_min_rates.
5239 * It's needed for further normalizing of the min_rates.
5241 * sum of vn_min_rates.
5243 * 0 - if all the min_rates are 0.
5244 * In the later case fainess algorithm should be deactivated.
5245 * If all min rates are not zero then those that are zeroes will be set to 1.
5247 static void bnx2x_calc_vn_min(struct bnx2x_softc *sc, struct cmng_init_input *input)
5250 uint32_t vn_min_rate;
5254 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5255 vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5256 vn_min_rate = (((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
5257 FUNC_MF_CFG_MIN_BW_SHIFT) * 100);
5259 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5260 /* skip hidden VNs */
5262 } else if (!vn_min_rate) {
5263 /* If min rate is zero - set it to 100 */
5264 vn_min_rate = DEF_MIN_RATE;
5269 input->vnic_min_rate[vn] = vn_min_rate;
5272 /* if ETS or all min rates are zeros - disable fairness */
5274 input->flags.cmng_enables &= ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5276 input->flags.cmng_enables |= CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5281 bnx2x_extract_max_cfg(__rte_unused struct bnx2x_softc *sc, uint32_t mf_cfg)
5283 uint16_t max_cfg = ((mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
5284 FUNC_MF_CFG_MAX_BW_SHIFT);
5288 "Max BW configured to 0 - using 100 instead");
5296 bnx2x_calc_vn_max(struct bnx2x_softc *sc, int vn, struct cmng_init_input *input)
5298 uint16_t vn_max_rate;
5299 uint32_t vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5302 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5305 max_cfg = bnx2x_extract_max_cfg(sc, vn_cfg);
5308 /* max_cfg in percents of linkspeed */
5310 ((sc->link_vars.line_speed * max_cfg) / 100);
5311 } else { /* SD modes */
5312 /* max_cfg is absolute in 100Mb units */
5313 vn_max_rate = (max_cfg * 100);
5317 input->vnic_max_rate[vn] = vn_max_rate;
5321 bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg, uint8_t cmng_type)
5323 struct cmng_init_input input;
5326 memset(&input, 0, sizeof(struct cmng_init_input));
5328 input.port_rate = sc->link_vars.line_speed;
5330 if (cmng_type == CMNG_FNS_MINMAX) {
5331 /* read mf conf from shmem */
5333 bnx2x_read_mf_cfg(sc);
5336 /* get VN min rate and enable fairness if not 0 */
5337 bnx2x_calc_vn_min(sc, &input);
5339 /* get VN max rate */
5341 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5342 bnx2x_calc_vn_max(sc, vn, &input);
5346 /* always enable rate shaping and fairness */
5347 input.flags.cmng_enables |= CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
5349 ecore_init_cmng(&input, &sc->cmng);
5354 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc)
5356 if (CHIP_REV_IS_SLOW(sc)) {
5357 return CMNG_FNS_NONE;
5361 return CMNG_FNS_MINMAX;
5364 return CMNG_FNS_NONE;
5368 storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng, uint8_t port)
5375 addr = (BAR_XSTRORM_INTMEM + XSTORM_CMNG_PER_PORT_VARS_OFFSET(port));
5376 size = sizeof(struct cmng_struct_per_port);
5377 ecore_storm_memset_struct(sc, addr, size, (uint32_t *) & cmng->port);
5379 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5380 func = func_by_vn(sc, vn);
5382 addr = (BAR_XSTRORM_INTMEM +
5383 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func));
5384 size = sizeof(struct rate_shaping_vars_per_vn);
5385 ecore_storm_memset_struct(sc, addr, size,
5386 (uint32_t *) & cmng->
5387 vnic.vnic_max_rate[vn]);
5389 addr = (BAR_XSTRORM_INTMEM +
5390 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func));
5391 size = sizeof(struct fairness_vars_per_vn);
5392 ecore_storm_memset_struct(sc, addr, size,
5393 (uint32_t *) & cmng->
5394 vnic.vnic_min_rate[vn]);
5398 static void bnx2x_pf_init(struct bnx2x_softc *sc)
5400 struct bnx2x_func_init_params func_init;
5401 struct event_ring_data eq_data;
5404 memset(&eq_data, 0, sizeof(struct event_ring_data));
5405 memset(&func_init, 0, sizeof(struct bnx2x_func_init_params));
5407 if (!CHIP_IS_E1x(sc)) {
5408 /* reset IGU PF statistics: MSIX + ATTN */
5411 (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5412 (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5413 ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5417 (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5418 (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5419 (BNX2X_IGU_STAS_MSG_PF_CNT * 4) +
5420 ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5424 /* function setup flags */
5425 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
5427 func_init.func_flgs = flags;
5428 func_init.pf_id = SC_FUNC(sc);
5429 func_init.func_id = SC_FUNC(sc);
5430 func_init.spq_map = sc->spq_dma.paddr;
5431 func_init.spq_prod = sc->spq_prod_idx;
5433 bnx2x_func_init(sc, &func_init);
5435 memset(&sc->cmng, 0, sizeof(struct cmng_struct_per_port));
5438 * Congestion management values depend on the link rate.
5439 * There is no active link so initial link rate is set to 10Gbps.
5440 * When the link comes up the congestion management values are
5441 * re-calculated according to the actual link rate.
5443 sc->link_vars.line_speed = SPEED_10000;
5444 bnx2x_cmng_fns_init(sc, TRUE, bnx2x_get_cmng_fns_mode(sc));
5446 /* Only the PMF sets the HW */
5448 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
5451 /* init Event Queue - PCI bus guarantees correct endainity */
5452 eq_data.base_addr.hi = U64_HI(sc->eq_dma.paddr);
5453 eq_data.base_addr.lo = U64_LO(sc->eq_dma.paddr);
5454 eq_data.producer = sc->eq_prod;
5455 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
5456 eq_data.sb_id = DEF_SB_ID;
5457 storm_memset_eq_data(sc, &eq_data, SC_FUNC(sc));
5460 static void bnx2x_hc_int_enable(struct bnx2x_softc *sc)
5462 int port = SC_PORT(sc);
5463 uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5464 uint32_t val = REG_RD(sc, addr);
5465 uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5466 || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5467 uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5468 uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5471 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5472 HC_CONFIG_0_REG_INT_LINE_EN_0);
5473 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5474 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5476 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
5479 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
5480 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5481 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5482 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5484 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5485 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5486 HC_CONFIG_0_REG_INT_LINE_EN_0 |
5487 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5489 REG_WR(sc, addr, val);
5491 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
5494 REG_WR(sc, addr, val);
5496 /* ensure that HC_CONFIG is written before leading/trailing edge config */
5499 /* init leading/trailing edge */
5501 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5503 /* enable nig and gpio3 attention */
5510 REG_WR(sc, (HC_REG_TRAILING_EDGE_0 + port * 8), val);
5511 REG_WR(sc, (HC_REG_LEADING_EDGE_0 + port * 8), val);
5513 /* make sure that interrupts are indeed enabled from here on */
5517 static void bnx2x_igu_int_enable(struct bnx2x_softc *sc)
5520 uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5521 || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5522 uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5523 uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5525 val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5528 val &= ~(IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5529 val |= (IGU_PF_CONF_MSI_MSIX_EN | IGU_PF_CONF_ATTN_BIT_EN);
5531 val |= IGU_PF_CONF_SINGLE_ISR_EN;
5534 val &= ~IGU_PF_CONF_INT_LINE_EN;
5535 val |= (IGU_PF_CONF_MSI_MSIX_EN |
5536 IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5538 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
5539 val |= (IGU_PF_CONF_INT_LINE_EN |
5540 IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5543 /* clean previous status - need to configure igu prior to ack */
5544 if ((!msix) || single_msix) {
5545 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5549 val |= IGU_PF_CONF_FUNC_EN;
5551 PMD_DRV_LOG(DEBUG, "write 0x%x to IGU mode %s",
5552 val, ((msix) ? "MSI-X" : ((msi) ? "MSI" : "INTx")));
5554 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5558 /* init leading/trailing edge */
5560 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5562 /* enable nig and gpio3 attention */
5569 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
5570 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
5572 /* make sure that interrupts are indeed enabled from here on */
5576 static void bnx2x_int_enable(struct bnx2x_softc *sc)
5578 if (sc->devinfo.int_block == INT_BLOCK_HC) {
5579 bnx2x_hc_int_enable(sc);
5581 bnx2x_igu_int_enable(sc);
5585 static void bnx2x_hc_int_disable(struct bnx2x_softc *sc)
5587 int port = SC_PORT(sc);
5588 uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5589 uint32_t val = REG_RD(sc, addr);
5591 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5592 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5593 HC_CONFIG_0_REG_INT_LINE_EN_0 | HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5594 /* flush all outstanding writes */
5597 REG_WR(sc, addr, val);
5598 if (REG_RD(sc, addr) != val) {
5599 PMD_DRV_LOG(ERR, "proper val not read from HC IGU!");
5603 static void bnx2x_igu_int_disable(struct bnx2x_softc *sc)
5605 uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5607 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
5608 IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_ATTN_BIT_EN);
5610 PMD_DRV_LOG(DEBUG, "write %x to IGU", val);
5612 /* flush all outstanding writes */
5615 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5616 if (REG_RD(sc, IGU_REG_PF_CONFIGURATION) != val) {
5617 PMD_DRV_LOG(ERR, "proper val not read from IGU!");
5621 static void bnx2x_int_disable(struct bnx2x_softc *sc)
5623 if (sc->devinfo.int_block == INT_BLOCK_HC) {
5624 bnx2x_hc_int_disable(sc);
5626 bnx2x_igu_int_disable(sc);
5630 static void bnx2x_nic_init(struct bnx2x_softc *sc, int load_code)
5634 PMD_INIT_FUNC_TRACE();
5636 for (i = 0; i < sc->num_queues; i++) {
5637 bnx2x_init_eth_fp(sc, i);
5640 rmb(); /* ensure status block indices were read */
5642 bnx2x_init_rx_rings(sc);
5643 bnx2x_init_tx_rings(sc);
5646 bnx2x_memset_stats(sc);
5650 /* initialize MOD_ABS interrupts */
5651 elink_init_mod_abs_int(sc, &sc->link_vars,
5652 sc->devinfo.chip_id,
5653 sc->devinfo.shmem_base,
5654 sc->devinfo.shmem2_base, SC_PORT(sc));
5656 bnx2x_init_def_sb(sc);
5657 bnx2x_update_dsb_idx(sc);
5658 bnx2x_init_sp_ring(sc);
5659 bnx2x_init_eq_ring(sc);
5660 bnx2x_init_internal(sc, load_code);
5662 bnx2x_stats_init(sc);
5664 /* flush all before enabling interrupts */
5667 bnx2x_int_enable(sc);
5669 /* check for SPIO5 */
5670 bnx2x_attn_int_deasserted0(sc,
5672 (MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
5674 AEU_INPUTS_ATTN_BITS_SPIO5);
5677 static void bnx2x_init_objs(struct bnx2x_softc *sc)
5679 /* mcast rules must be added to tx if tx switching is enabled */
5680 ecore_obj_type o_type;
5681 if (sc->flags & BNX2X_TX_SWITCHING)
5682 o_type = ECORE_OBJ_TYPE_RX_TX;
5684 o_type = ECORE_OBJ_TYPE_RX;
5686 /* RX_MODE controlling object */
5687 ecore_init_rx_mode_obj(sc, &sc->rx_mode_obj);
5689 /* multicast configuration controlling object */
5690 ecore_init_mcast_obj(sc,
5696 BNX2X_SP(sc, mcast_rdata),
5697 (rte_iova_t)BNX2X_SP_MAPPING(sc, mcast_rdata),
5698 ECORE_FILTER_MCAST_PENDING,
5699 &sc->sp_state, o_type);
5701 /* Setup CAM credit pools */
5702 ecore_init_mac_credit_pool(sc,
5705 CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5706 VNICS_PER_PATH(sc));
5708 ecore_init_vlan_credit_pool(sc,
5710 SC_ABS_FUNC(sc) >> 1,
5711 CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5712 VNICS_PER_PATH(sc));
5714 /* RSS configuration object */
5715 ecore_init_rss_config_obj(&sc->rss_conf_obj,
5720 BNX2X_SP(sc, rss_rdata),
5721 (rte_iova_t)BNX2X_SP_MAPPING(sc, rss_rdata),
5722 ECORE_FILTER_RSS_CONF_PENDING,
5723 &sc->sp_state, ECORE_OBJ_TYPE_RX);
5727 * Initialize the function. This must be called before sending CLIENT_SETUP
5728 * for the first client.
5730 static int bnx2x_func_start(struct bnx2x_softc *sc)
5732 struct ecore_func_state_params func_params = { NULL };
5733 struct ecore_func_start_params *start_params =
5734 &func_params.params.start;
5736 /* Prepare parameters for function state transitions */
5737 bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
5739 func_params.f_obj = &sc->func_obj;
5740 func_params.cmd = ECORE_F_CMD_START;
5742 /* Function parameters */
5743 start_params->mf_mode = sc->devinfo.mf_info.mf_mode;
5744 start_params->sd_vlan_tag = OVLAN(sc);
5746 if (CHIP_IS_E2(sc) || CHIP_IS_E3(sc)) {
5747 start_params->network_cos_mode = STATIC_COS;
5748 } else { /* CHIP_IS_E1X */
5749 start_params->network_cos_mode = FW_WRR;
5752 start_params->gre_tunnel_mode = 0;
5753 start_params->gre_tunnel_rss = 0;
5755 return ecore_func_state_change(sc, &func_params);
5758 static int bnx2x_set_power_state(struct bnx2x_softc *sc, uint8_t state)
5762 /* If there is no power capability, silently succeed */
5763 if (!(sc->devinfo.pcie_cap_flags & BNX2X_PM_CAPABLE_FLAG)) {
5764 PMD_DRV_LOG(WARNING, "No power capability");
5768 pci_read(sc, (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS), &pmcsr,
5774 (sc->devinfo.pcie_pm_cap_reg +
5776 ((pmcsr & ~PCIM_PSTAT_DMASK) | PCIM_PSTAT_PME));
5778 if (pmcsr & PCIM_PSTAT_DMASK) {
5779 /* delay required during transition out of D3hot */
5786 /* don't shut down the power for emulation and FPGA */
5787 if (CHIP_REV_IS_SLOW(sc)) {
5791 pmcsr &= ~PCIM_PSTAT_DMASK;
5792 pmcsr |= PCIM_PSTAT_D3;
5795 pmcsr |= PCIM_PSTAT_PMEENABLE;
5799 (sc->devinfo.pcie_pm_cap_reg +
5800 PCIR_POWER_STATUS), pmcsr);
5803 * No more memory access after this point until device is brought back
5809 PMD_DRV_LOG(NOTICE, "Can't support PCI power state = %d",
5817 /* return true if succeeded to acquire the lock */
5818 static uint8_t bnx2x_trylock_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
5820 uint32_t lock_status;
5821 uint32_t resource_bit = (1 << resource);
5822 int func = SC_FUNC(sc);
5823 uint32_t hw_lock_control_reg;
5825 /* Validating that the resource is within range */
5826 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
5828 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)",
5829 resource, HW_LOCK_MAX_RESOURCE_VALUE);
5834 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func * 8);
5836 hw_lock_control_reg =
5837 (MISC_REG_DRIVER_CONTROL_7 + (func - 6) * 8);
5840 /* try to acquire the lock */
5841 REG_WR(sc, hw_lock_control_reg + 4, resource_bit);
5842 lock_status = REG_RD(sc, hw_lock_control_reg);
5843 if (lock_status & resource_bit) {
5847 PMD_DRV_LOG(NOTICE, "Failed to get a resource lock 0x%x", resource);
5853 * Get the recovery leader resource id according to the engine this function
5854 * belongs to. Currently only only 2 engines is supported.
5856 static int bnx2x_get_leader_lock_resource(struct bnx2x_softc *sc)
5859 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
5861 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
5865 /* try to acquire a leader lock for current engine */
5866 static uint8_t bnx2x_trylock_leader_lock(struct bnx2x_softc *sc)
5868 return bnx2x_trylock_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5871 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc)
5873 return bnx2x_release_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5876 /* close gates #2, #3 and #4 */
5877 static void bnx2x_set_234_gates(struct bnx2x_softc *sc, uint8_t close)
5881 /* gates #2 and #4a are closed/opened */
5883 REG_WR(sc, PXP_REG_HST_DISCARD_DOORBELLS, ! !close);
5885 REG_WR(sc, PXP_REG_HST_DISCARD_INTERNAL_WRITES, ! !close);
5888 if (CHIP_IS_E1x(sc)) {
5889 /* prevent interrupts from HC on both ports */
5890 val = REG_RD(sc, HC_REG_CONFIG_1);
5892 REG_WR(sc, HC_REG_CONFIG_1, (val & ~(uint32_t)
5893 HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5895 REG_WR(sc, HC_REG_CONFIG_1,
5896 (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5898 val = REG_RD(sc, HC_REG_CONFIG_0);
5900 REG_WR(sc, HC_REG_CONFIG_0, (val & ~(uint32_t)
5901 HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5903 REG_WR(sc, HC_REG_CONFIG_0,
5904 (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5907 /* Prevent incoming interrupts in IGU */
5908 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
5911 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5913 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5915 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5917 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5923 /* poll for pending writes bit, it should get cleared in no more than 1s */
5924 static int bnx2x_er_poll_igu_vq(struct bnx2x_softc *sc)
5926 uint32_t cnt = 1000;
5927 uint32_t pend_bits = 0;
5930 pend_bits = REG_RD(sc, IGU_REG_PENDING_BITS_STATUS);
5932 if (pend_bits == 0) {
5937 } while (cnt-- > 0);
5940 PMD_DRV_LOG(NOTICE, "Still pending IGU requests bits=0x%08x!",
5948 #define SHARED_MF_CLP_MAGIC 0x80000000 /* 'magic' bit */
5950 static void bnx2x_clp_reset_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
5952 /* Do some magic... */
5953 uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
5954 *magic_val = val & SHARED_MF_CLP_MAGIC;
5955 MFCFG_WR(sc, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
5958 /* restore the value of the 'magic' bit */
5959 static void bnx2x_clp_reset_done(struct bnx2x_softc *sc, uint32_t magic_val)
5961 /* Restore the 'magic' bit value... */
5962 uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
5963 MFCFG_WR(sc, shared_mf_config.clp_mb,
5964 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
5967 /* prepare for MCP reset, takes care of CLP configurations */
5968 static void bnx2x_reset_mcp_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
5971 uint32_t validity_offset;
5973 /* set `magic' bit in order to save MF config */
5974 bnx2x_clp_reset_prep(sc, magic_val);
5976 /* get shmem offset */
5977 shmem = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
5979 offsetof(struct shmem_region, validity_map[SC_PORT(sc)]);
5981 /* Clear validity map flags */
5983 REG_WR(sc, shmem + validity_offset, 0);
5987 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
5988 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
5990 static void bnx2x_mcp_wait_one(struct bnx2x_softc *sc)
5992 /* special handling for emulation and FPGA (10 times longer) */
5993 if (CHIP_REV_IS_SLOW(sc)) {
5994 DELAY((MCP_ONE_TIMEOUT * 10) * 1000);
5996 DELAY((MCP_ONE_TIMEOUT) * 1000);
6000 /* initialize shmem_base and waits for validity signature to appear */
6001 static int bnx2x_init_shmem(struct bnx2x_softc *sc)
6007 sc->devinfo.shmem_base =
6008 sc->link_params.shmem_base =
6009 REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
6011 if (sc->devinfo.shmem_base) {
6012 val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
6013 if (val & SHR_MEM_VALIDITY_MB)
6017 bnx2x_mcp_wait_one(sc);
6019 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
6021 PMD_DRV_LOG(NOTICE, "BAD MCP validity signature");
6026 static int bnx2x_reset_mcp_comp(struct bnx2x_softc *sc, uint32_t magic_val)
6028 int rc = bnx2x_init_shmem(sc);
6030 /* Restore the `magic' bit value */
6031 bnx2x_clp_reset_done(sc, magic_val);
6036 static void bnx2x_pxp_prep(struct bnx2x_softc *sc)
6038 REG_WR(sc, PXP2_REG_RD_START_INIT, 0);
6039 REG_WR(sc, PXP2_REG_RQ_RBC_DONE, 0);
6044 * Reset the whole chip except for:
6046 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by one reset bit)
6048 * - MISC (including AEU)
6052 static void bnx2x_process_kill_chip_reset(struct bnx2x_softc *sc, uint8_t global)
6054 uint32_t not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
6055 uint32_t global_bits2, stay_reset2;
6058 * Bits that have to be set in reset_mask2 if we want to reset 'global'
6059 * (per chip) blocks.
6062 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
6063 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
6066 * Don't reset the following blocks.
6067 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
6068 * reset, as in 4 port device they might still be owned
6069 * by the MCP (there is only one leader per path).
6072 MISC_REGISTERS_RESET_REG_1_RST_HC |
6073 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
6074 MISC_REGISTERS_RESET_REG_1_RST_PXP;
6077 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
6078 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
6079 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
6080 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
6081 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
6082 MISC_REGISTERS_RESET_REG_2_RST_GRC |
6083 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
6084 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
6085 MISC_REGISTERS_RESET_REG_2_RST_ATC |
6086 MISC_REGISTERS_RESET_REG_2_PGLC |
6087 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
6088 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
6089 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
6090 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
6091 MISC_REGISTERS_RESET_REG_2_UMAC0 | MISC_REGISTERS_RESET_REG_2_UMAC1;
6094 * Keep the following blocks in reset:
6095 * - all xxMACs are handled by the elink code.
6098 MISC_REGISTERS_RESET_REG_2_XMAC |
6099 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
6101 /* Full reset masks according to the chip */
6102 reset_mask1 = 0xffffffff;
6104 if (CHIP_IS_E1H(sc))
6105 reset_mask2 = 0x1ffff;
6106 else if (CHIP_IS_E2(sc))
6107 reset_mask2 = 0xfffff;
6108 else /* CHIP_IS_E3 */
6109 reset_mask2 = 0x3ffffff;
6111 /* Don't reset global blocks unless we need to */
6113 reset_mask2 &= ~global_bits2;
6116 * In case of attention in the QM, we need to reset PXP
6117 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
6118 * because otherwise QM reset would release 'close the gates' shortly
6119 * before resetting the PXP, then the PSWRQ would send a write
6120 * request to PGLUE. Then when PXP is reset, PGLUE would try to
6121 * read the payload data from PSWWR, but PSWWR would not
6122 * respond. The write queue in PGLUE would stuck, dmae commands
6123 * would not return. Therefore it's important to reset the second
6124 * reset register (containing the
6125 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
6126 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
6129 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
6130 reset_mask2 & (~not_reset_mask2));
6132 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6133 reset_mask1 & (~not_reset_mask1));
6138 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
6139 reset_mask2 & (~stay_reset2));
6144 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
6148 static int bnx2x_process_kill(struct bnx2x_softc *sc, uint8_t global)
6152 uint32_t sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
6153 uint32_t tags_63_32 = 0;
6155 /* Empty the Tetris buffer, wait for 1s */
6157 sr_cnt = REG_RD(sc, PXP2_REG_RD_SR_CNT);
6158 blk_cnt = REG_RD(sc, PXP2_REG_RD_BLK_CNT);
6159 port_is_idle_0 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_0);
6160 port_is_idle_1 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_1);
6161 pgl_exp_rom2 = REG_RD(sc, PXP2_REG_PGL_EXP_ROM2);
6162 if (CHIP_IS_E3(sc)) {
6163 tags_63_32 = REG_RD(sc, PGLUE_B_REG_TAGS_63_32);
6166 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
6167 ((port_is_idle_0 & 0x1) == 0x1) &&
6168 ((port_is_idle_1 & 0x1) == 0x1) &&
6169 (pgl_exp_rom2 == 0xffffffff) &&
6170 (!CHIP_IS_E3(sc) || (tags_63_32 == 0xffffffff)))
6173 } while (cnt-- > 0);
6177 "ERROR: Tetris buffer didn't get empty or there "
6178 "are still outstanding read requests after 1s! "
6179 "sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, "
6180 "port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x",
6181 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
6188 /* Close gates #2, #3 and #4 */
6189 bnx2x_set_234_gates(sc, TRUE);
6191 /* Poll for IGU VQs for 57712 and newer chips */
6192 if (!CHIP_IS_E1x(sc) && bnx2x_er_poll_igu_vq(sc)) {
6196 /* clear "unprepared" bit */
6197 REG_WR(sc, MISC_REG_UNPREPARED, 0);
6200 /* Make sure all is written to the chip before the reset */
6204 * Wait for 1ms to empty GLUE and PCI-E core queues,
6205 * PSWHST, GRC and PSWRD Tetris buffer.
6209 /* Prepare to chip reset: */
6212 bnx2x_reset_mcp_prep(sc, &val);
6219 /* reset the chip */
6220 bnx2x_process_kill_chip_reset(sc, global);
6223 /* Recover after reset: */
6225 if (global && bnx2x_reset_mcp_comp(sc, val)) {
6229 /* Open the gates #2, #3 and #4 */
6230 bnx2x_set_234_gates(sc, FALSE);
6235 static int bnx2x_leader_reset(struct bnx2x_softc *sc)
6238 uint8_t global = bnx2x_reset_is_global(sc);
6242 * If not going to reset MCP, load "fake" driver to reset HW while
6243 * driver is owner of the HW.
6245 if (!global && !BNX2X_NOMCP(sc)) {
6246 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
6247 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
6249 PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
6251 goto exit_leader_reset;
6254 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
6255 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
6257 "MCP unexpected response, aborting");
6259 goto exit_leader_reset2;
6262 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
6264 PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
6266 goto exit_leader_reset2;
6270 /* try to recover after the failure */
6271 if (bnx2x_process_kill(sc, global)) {
6272 PMD_DRV_LOG(NOTICE, "Something bad occurred on engine %d!",
6275 goto exit_leader_reset2;
6279 * Clear the RESET_IN_PROGRESS and RESET_GLOBAL bits and update the driver
6282 bnx2x_set_reset_done(sc);
6284 bnx2x_clear_reset_global(sc);
6289 /* unload "fake driver" if it was loaded */
6290 if (!global &&!BNX2X_NOMCP(sc)) {
6291 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
6292 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
6298 bnx2x_release_leader_lock(sc);
6305 * prepare INIT transition, parameters configured:
6306 * - HC configuration
6307 * - Queue's CDU context
6310 bnx2x_pf_q_prep_init(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6311 struct ecore_queue_init_params *init_params)
6314 int cxt_index, cxt_offset;
6316 bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->rx.flags);
6317 bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->tx.flags);
6319 bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->rx.flags);
6320 bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->tx.flags);
6323 init_params->rx.hc_rate =
6324 sc->hc_rx_ticks ? (1000000 / sc->hc_rx_ticks) : 0;
6325 init_params->tx.hc_rate =
6326 sc->hc_tx_ticks ? (1000000 / sc->hc_tx_ticks) : 0;
6329 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = fp->fw_sb_id;
6331 /* CQ index among the SB indices */
6332 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6333 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
6335 /* set maximum number of COSs supported by this queue */
6336 init_params->max_cos = sc->max_cos;
6338 /* set the context pointers queue object */
6339 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
6340 cxt_index = fp->index / ILT_PAGE_CIDS;
6341 cxt_offset = fp->index - (cxt_index * ILT_PAGE_CIDS);
6342 init_params->cxts[cos] =
6343 &sc->context[cxt_index].vcxt[cxt_offset].eth;
6347 /* set flags that are common for the Tx-only and not normal connections */
6348 static unsigned long
6349 bnx2x_get_common_flags(struct bnx2x_softc *sc, uint8_t zero_stats)
6351 unsigned long flags = 0;
6353 /* PF driver will always initialize the Queue to an ACTIVE state */
6354 bnx2x_set_bit(ECORE_Q_FLG_ACTIVE, &flags);
6357 * tx only connections collect statistics (on the same index as the
6358 * parent connection). The statistics are zeroed when the parent
6359 * connection is initialized.
6362 bnx2x_set_bit(ECORE_Q_FLG_STATS, &flags);
6364 bnx2x_set_bit(ECORE_Q_FLG_ZERO_STATS, &flags);
6368 * tx only connections can support tx-switching, though their
6369 * CoS-ness doesn't survive the loopback
6371 if (sc->flags & BNX2X_TX_SWITCHING) {
6372 bnx2x_set_bit(ECORE_Q_FLG_TX_SWITCH, &flags);
6375 bnx2x_set_bit(ECORE_Q_FLG_PCSUM_ON_PKT, &flags);
6380 static unsigned long bnx2x_get_q_flags(struct bnx2x_softc *sc, uint8_t leading)
6382 unsigned long flags = 0;
6385 bnx2x_set_bit(ECORE_Q_FLG_OV, &flags);
6389 bnx2x_set_bit(ECORE_Q_FLG_LEADING_RSS, &flags);
6390 bnx2x_set_bit(ECORE_Q_FLG_MCAST, &flags);
6393 bnx2x_set_bit(ECORE_Q_FLG_VLAN, &flags);
6395 /* merge with common flags */
6396 return flags | bnx2x_get_common_flags(sc, TRUE);
6400 bnx2x_pf_q_prep_general(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6401 struct ecore_general_setup_params *gen_init, uint8_t cos)
6403 gen_init->stat_id = bnx2x_stats_id(fp);
6404 gen_init->spcl_id = fp->cl_id;
6405 gen_init->mtu = sc->mtu;
6406 gen_init->cos = cos;
6410 bnx2x_pf_rx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6411 struct rxq_pause_params *pause,
6412 struct ecore_rxq_setup_params *rxq_init)
6414 struct bnx2x_rx_queue *rxq;
6416 rxq = sc->rx_queues[fp->index];
6418 PMD_RX_LOG(ERR, "RX queue is NULL");
6422 pause->bd_th_lo = BD_TH_LO(sc);
6423 pause->bd_th_hi = BD_TH_HI(sc);
6425 pause->rcq_th_lo = RCQ_TH_LO(sc);
6426 pause->rcq_th_hi = RCQ_TH_HI(sc);
6428 /* validate rings have enough entries to cross high thresholds */
6429 if (sc->dropless_fc &&
6430 pause->bd_th_hi + FW_PREFETCH_CNT > sc->rx_ring_size) {
6431 PMD_DRV_LOG(WARNING, "rx bd ring threshold limit");
6434 if (sc->dropless_fc &&
6435 pause->rcq_th_hi + FW_PREFETCH_CNT > USABLE_RCQ_ENTRIES(rxq)) {
6436 PMD_DRV_LOG(WARNING, "rcq ring threshold limit");
6442 rxq_init->dscr_map = (rte_iova_t)rxq->rx_ring_phys_addr;
6443 rxq_init->rcq_map = (rte_iova_t)rxq->cq_ring_phys_addr;
6444 rxq_init->rcq_np_map = (rte_iova_t)(rxq->cq_ring_phys_addr +
6448 * This should be a maximum number of data bytes that may be
6449 * placed on the BD (not including paddings).
6451 rxq_init->buf_sz = (fp->rx_buf_size - IP_HEADER_ALIGNMENT_PADDING);
6453 rxq_init->cl_qzone_id = fp->cl_qzone_id;
6454 rxq_init->rss_engine_id = SC_FUNC(sc);
6455 rxq_init->mcast_engine_id = SC_FUNC(sc);
6457 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
6458 rxq_init->fw_sb_id = fp->fw_sb_id;
6460 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6463 * configure silent vlan removal
6464 * if multi function mode is afex, then mask default vlan
6466 if (IS_MF_AFEX(sc)) {
6467 rxq_init->silent_removal_value =
6468 sc->devinfo.mf_info.afex_def_vlan_tag;
6469 rxq_init->silent_removal_mask = EVL_VLID_MASK;
6474 bnx2x_pf_tx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6475 struct ecore_txq_setup_params *txq_init, uint8_t cos)
6477 struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
6480 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
6483 txq_init->dscr_map = (rte_iova_t)txq->tx_ring_phys_addr;
6484 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
6485 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
6486 txq_init->fw_sb_id = fp->fw_sb_id;
6489 * set the TSS leading client id for TX classfication to the
6490 * leading RSS client id
6492 txq_init->tss_leading_cl_id = BNX2X_FP(sc, 0, cl_id);
6496 * This function performs 2 steps in a queue state machine:
6501 bnx2x_setup_queue(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp, uint8_t leading)
6503 struct ecore_queue_state_params q_params = { NULL };
6504 struct ecore_queue_setup_params *setup_params = &q_params.params.setup;
6507 PMD_DRV_LOG(DEBUG, "setting up queue %d", fp->index);
6509 bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6511 q_params.q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
6513 /* we want to wait for completion in this context */
6514 bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
6516 /* prepare the INIT parameters */
6517 bnx2x_pf_q_prep_init(sc, fp, &q_params.params.init);
6519 /* Set the command */
6520 q_params.cmd = ECORE_Q_CMD_INIT;
6522 /* Change the state to INIT */
6523 rc = ecore_queue_state_change(sc, &q_params);
6525 PMD_DRV_LOG(NOTICE, "Queue(%d) INIT failed", fp->index);
6529 PMD_DRV_LOG(DEBUG, "init complete");
6531 /* now move the Queue to the SETUP state */
6532 memset(setup_params, 0, sizeof(*setup_params));
6534 /* set Queue flags */
6535 setup_params->flags = bnx2x_get_q_flags(sc, leading);
6537 /* set general SETUP parameters */
6538 bnx2x_pf_q_prep_general(sc, fp, &setup_params->gen_params,
6539 FIRST_TX_COS_INDEX);
6541 bnx2x_pf_rx_q_prep(sc, fp,
6542 &setup_params->pause_params,
6543 &setup_params->rxq_params);
6545 bnx2x_pf_tx_q_prep(sc, fp, &setup_params->txq_params, FIRST_TX_COS_INDEX);
6547 /* Set the command */
6548 q_params.cmd = ECORE_Q_CMD_SETUP;
6550 /* change the state to SETUP */
6551 rc = ecore_queue_state_change(sc, &q_params);
6553 PMD_DRV_LOG(NOTICE, "Queue(%d) SETUP failed", fp->index);
6560 static int bnx2x_setup_leading(struct bnx2x_softc *sc)
6563 return bnx2x_setup_queue(sc, &sc->fp[0], TRUE);
6565 return bnx2x_vf_setup_queue(sc, &sc->fp[0], TRUE);
6569 bnx2x_config_rss_pf(struct bnx2x_softc *sc, struct ecore_rss_config_obj *rss_obj,
6570 uint8_t config_hash)
6572 struct ecore_config_rss_params params = { NULL };
6576 * Although RSS is meaningless when there is a single HW queue we
6577 * still need it enabled in order to have HW Rx hash generated.
6580 params.rss_obj = rss_obj;
6582 bnx2x_set_bit(RAMROD_COMP_WAIT, ¶ms.ramrod_flags);
6584 bnx2x_set_bit(ECORE_RSS_MODE_REGULAR, ¶ms.rss_flags);
6586 /* RSS configuration */
6587 bnx2x_set_bit(ECORE_RSS_IPV4, ¶ms.rss_flags);
6588 bnx2x_set_bit(ECORE_RSS_IPV4_TCP, ¶ms.rss_flags);
6589 bnx2x_set_bit(ECORE_RSS_IPV6, ¶ms.rss_flags);
6590 bnx2x_set_bit(ECORE_RSS_IPV6_TCP, ¶ms.rss_flags);
6591 if (rss_obj->udp_rss_v4) {
6592 bnx2x_set_bit(ECORE_RSS_IPV4_UDP, ¶ms.rss_flags);
6594 if (rss_obj->udp_rss_v6) {
6595 bnx2x_set_bit(ECORE_RSS_IPV6_UDP, ¶ms.rss_flags);
6599 params.rss_result_mask = MULTI_MASK;
6601 rte_memcpy(params.ind_table, rss_obj->ind_table,
6602 sizeof(params.ind_table));
6606 for (i = 0; i < sizeof(params.rss_key) / 4; i++) {
6607 params.rss_key[i] = (uint32_t) rte_rand();
6610 bnx2x_set_bit(ECORE_RSS_SET_SRCH, ¶ms.rss_flags);
6614 return ecore_config_rss(sc, ¶ms);
6616 return bnx2x_vf_config_rss(sc, ¶ms);
6619 static int bnx2x_config_rss_eth(struct bnx2x_softc *sc, uint8_t config_hash)
6621 return bnx2x_config_rss_pf(sc, &sc->rss_conf_obj, config_hash);
6624 static int bnx2x_init_rss_pf(struct bnx2x_softc *sc)
6626 uint8_t num_eth_queues = BNX2X_NUM_ETH_QUEUES(sc);
6630 * Prepare the initial contents of the indirection table if
6633 for (i = 0; i < sizeof(sc->rss_conf_obj.ind_table); i++) {
6634 sc->rss_conf_obj.ind_table[i] =
6635 (sc->fp->cl_id + (i % num_eth_queues));
6639 sc->rss_conf_obj.udp_rss_v4 = sc->rss_conf_obj.udp_rss_v6 = 1;
6643 * For 57711 SEARCHER configuration (rss_keys) is
6644 * per-port, so if explicit configuration is needed, do it only
6647 * For 57712 and newer it's a per-function configuration.
6649 return bnx2x_config_rss_eth(sc, sc->port.pmf || !CHIP_IS_E1x(sc));
6653 bnx2x_set_mac_one(struct bnx2x_softc *sc, uint8_t * mac,
6654 struct ecore_vlan_mac_obj *obj, uint8_t set, int mac_type,
6655 unsigned long *ramrod_flags)
6657 struct ecore_vlan_mac_ramrod_params ramrod_param;
6660 memset(&ramrod_param, 0, sizeof(ramrod_param));
6662 /* fill in general parameters */
6663 ramrod_param.vlan_mac_obj = obj;
6664 ramrod_param.ramrod_flags = *ramrod_flags;
6666 /* fill a user request section if needed */
6667 if (!bnx2x_test_bit(RAMROD_CONT, ramrod_flags)) {
6668 rte_memcpy(ramrod_param.user_req.u.mac.mac, mac,
6671 bnx2x_set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
6673 /* Set the command: ADD or DEL */
6674 ramrod_param.user_req.cmd = (set) ? ECORE_VLAN_MAC_ADD :
6678 rc = ecore_config_vlan_mac(sc, &ramrod_param);
6680 if (rc == ECORE_EXISTS) {
6681 PMD_DRV_LOG(INFO, "Failed to schedule ADD operations (EEXIST)");
6682 /* do not treat adding same MAC as error */
6684 } else if (rc < 0) {
6686 "%s MAC failed (%d)", (set ? "Set" : "Delete"), rc);
6692 static int bnx2x_set_eth_mac(struct bnx2x_softc *sc, uint8_t set)
6694 unsigned long ramrod_flags = 0;
6696 PMD_DRV_LOG(DEBUG, "Adding Ethernet MAC");
6698 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
6700 /* Eth MAC is set on RSS leading client (fp[0]) */
6701 return bnx2x_set_mac_one(sc, sc->link_params.mac_addr,
6702 &sc->sp_objs->mac_obj,
6703 set, ECORE_ETH_MAC, &ramrod_flags);
6706 static int bnx2x_get_cur_phy_idx(struct bnx2x_softc *sc)
6708 uint32_t sel_phy_idx = 0;
6710 if (sc->link_params.num_phys <= 1) {
6711 return ELINK_INT_PHY;
6714 if (sc->link_vars.link_up) {
6715 sel_phy_idx = ELINK_EXT_PHY1;
6716 /* In case link is SERDES, check if the ELINK_EXT_PHY2 is the one */
6717 if ((sc->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
6718 (sc->link_params.phy[ELINK_EXT_PHY2].supported &
6719 ELINK_SUPPORTED_FIBRE))
6720 sel_phy_idx = ELINK_EXT_PHY2;
6722 switch (elink_phy_selection(&sc->link_params)) {
6723 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6724 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
6725 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6726 sel_phy_idx = ELINK_EXT_PHY1;
6728 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
6729 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6730 sel_phy_idx = ELINK_EXT_PHY2;
6738 static int bnx2x_get_link_cfg_idx(struct bnx2x_softc *sc)
6740 uint32_t sel_phy_idx = bnx2x_get_cur_phy_idx(sc);
6743 * The selected activated PHY is always after swapping (in case PHY
6744 * swapping is enabled). So when swapping is enabled, we need to reverse
6748 if (sc->link_params.multi_phy_config & PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
6749 if (sel_phy_idx == ELINK_EXT_PHY1)
6750 sel_phy_idx = ELINK_EXT_PHY2;
6751 else if (sel_phy_idx == ELINK_EXT_PHY2)
6752 sel_phy_idx = ELINK_EXT_PHY1;
6755 return ELINK_LINK_CONFIG_IDX(sel_phy_idx);
6758 static void bnx2x_set_requested_fc(struct bnx2x_softc *sc)
6761 * Initialize link parameters structure variables
6762 * It is recommended to turn off RX FC for jumbo frames
6763 * for better performance
6765 if (CHIP_IS_E1x(sc) && (sc->mtu > 5000)) {
6766 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_TX;
6768 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_BOTH;
6772 static void bnx2x_calc_fc_adv(struct bnx2x_softc *sc)
6774 uint8_t cfg_idx = bnx2x_get_link_cfg_idx(sc);
6775 switch (sc->link_vars.ieee_fc &
6776 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
6777 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
6779 sc->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
6783 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
6784 sc->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
6788 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
6789 sc->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
6794 static uint16_t bnx2x_get_mf_speed(struct bnx2x_softc *sc)
6796 uint16_t line_speed = sc->link_vars.line_speed;
6798 uint16_t maxCfg = bnx2x_extract_max_cfg(sc,
6800 mf_info.mf_config[SC_VN
6803 /* calculate the current MAX line speed limit for the MF devices */
6805 line_speed = (line_speed * maxCfg) / 100;
6806 } else { /* SD mode */
6807 uint16_t vn_max_rate = maxCfg * 100;
6809 if (vn_max_rate < line_speed) {
6810 line_speed = vn_max_rate;
6819 bnx2x_fill_report_data(struct bnx2x_softc *sc, struct bnx2x_link_report_data *data)
6821 uint16_t line_speed = bnx2x_get_mf_speed(sc);
6823 memset(data, 0, sizeof(*data));
6825 /* fill the report data with the effective line speed */
6826 data->line_speed = line_speed;
6829 if (!sc->link_vars.link_up || (sc->flags & BNX2X_MF_FUNC_DIS)) {
6830 bnx2x_set_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6831 &data->link_report_flags);
6835 if (sc->link_vars.duplex == DUPLEX_FULL) {
6836 bnx2x_set_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6837 &data->link_report_flags);
6840 /* Rx Flow Control is ON */
6841 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_RX) {
6842 bnx2x_set_bit(BNX2X_LINK_REPORT_RX_FC_ON, &data->link_report_flags);
6845 /* Tx Flow Control is ON */
6846 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
6847 bnx2x_set_bit(BNX2X_LINK_REPORT_TX_FC_ON, &data->link_report_flags);
6851 /* report link status to OS, should be called under phy_lock */
6852 static void bnx2x_link_report(struct bnx2x_softc *sc)
6854 struct bnx2x_link_report_data cur_data;
6858 bnx2x_read_mf_cfg(sc);
6861 /* Read the current link report info */
6862 bnx2x_fill_report_data(sc, &cur_data);
6864 /* Don't report link down or exactly the same link status twice */
6865 if (!memcmp(&cur_data, &sc->last_reported_link, sizeof(cur_data)) ||
6866 (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6867 &sc->last_reported_link.link_report_flags) &&
6868 bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6869 &cur_data.link_report_flags))) {
6875 /* report new link params and remember the state for the next time */
6876 rte_memcpy(&sc->last_reported_link, &cur_data, sizeof(cur_data));
6878 if (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6879 &cur_data.link_report_flags)) {
6880 PMD_DRV_LOG(INFO, "NIC Link is Down");
6882 __rte_unused const char *duplex;
6883 __rte_unused const char *flow;
6885 if (bnx2x_test_and_clear_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6886 &cur_data.link_report_flags)) {
6893 * Handle the FC at the end so that only these flags would be
6894 * possibly set. This way we may easily check if there is no FC
6897 if (cur_data.link_report_flags) {
6898 if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6899 &cur_data.link_report_flags) &&
6900 bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6901 &cur_data.link_report_flags)) {
6902 flow = "ON - receive & transmit";
6903 } else if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6904 &cur_data.link_report_flags) &&
6905 !bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6906 &cur_data.link_report_flags)) {
6907 flow = "ON - receive";
6908 } else if (!bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6909 &cur_data.link_report_flags) &&
6910 bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6911 &cur_data.link_report_flags)) {
6912 flow = "ON - transmit";
6914 flow = "none"; /* possible? */
6921 "NIC Link is Up, %d Mbps %s duplex, Flow control: %s",
6922 cur_data.line_speed, duplex, flow);
6926 void bnx2x_link_status_update(struct bnx2x_softc *sc)
6928 if (sc->state != BNX2X_STATE_OPEN) {
6932 if (IS_PF(sc) && !CHIP_REV_IS_SLOW(sc)) {
6933 elink_link_status_update(&sc->link_params, &sc->link_vars);
6935 sc->port.supported[0] |= (ELINK_SUPPORTED_10baseT_Half |
6936 ELINK_SUPPORTED_10baseT_Full |
6937 ELINK_SUPPORTED_100baseT_Half |
6938 ELINK_SUPPORTED_100baseT_Full |
6939 ELINK_SUPPORTED_1000baseT_Full |
6940 ELINK_SUPPORTED_2500baseX_Full |
6941 ELINK_SUPPORTED_10000baseT_Full |
6942 ELINK_SUPPORTED_TP |
6943 ELINK_SUPPORTED_FIBRE |
6944 ELINK_SUPPORTED_Autoneg |
6945 ELINK_SUPPORTED_Pause |
6946 ELINK_SUPPORTED_Asym_Pause);
6947 sc->port.advertising[0] = sc->port.supported[0];
6949 sc->link_params.sc = sc;
6950 sc->link_params.port = SC_PORT(sc);
6951 sc->link_params.req_duplex[0] = DUPLEX_FULL;
6952 sc->link_params.req_flow_ctrl[0] = ELINK_FLOW_CTRL_NONE;
6953 sc->link_params.req_line_speed[0] = SPEED_10000;
6954 sc->link_params.speed_cap_mask[0] = 0x7f0000;
6955 sc->link_params.switch_cfg = ELINK_SWITCH_CFG_10G;
6957 if (CHIP_REV_IS_FPGA(sc)) {
6958 sc->link_vars.mac_type = ELINK_MAC_TYPE_EMAC;
6959 sc->link_vars.line_speed = ELINK_SPEED_1000;
6960 sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
6961 LINK_STATUS_SPEED_AND_DUPLEX_1000TFD);
6963 sc->link_vars.mac_type = ELINK_MAC_TYPE_BMAC;
6964 sc->link_vars.line_speed = ELINK_SPEED_10000;
6965 sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
6966 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
6969 sc->link_vars.link_up = 1;
6971 sc->link_vars.duplex = DUPLEX_FULL;
6972 sc->link_vars.flow_ctrl = ELINK_FLOW_CTRL_NONE;
6976 NIG_REG_EGRESS_DRAIN0_MODE +
6977 sc->link_params.port * 4, 0);
6978 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
6979 bnx2x_link_report(sc);
6984 if (sc->link_vars.link_up) {
6985 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
6987 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
6989 bnx2x_link_report(sc);
6991 bnx2x_link_report(sc);
6992 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
6996 static int bnx2x_initial_phy_init(struct bnx2x_softc *sc, int load_mode)
6998 int rc, cfg_idx = bnx2x_get_link_cfg_idx(sc);
6999 uint16_t req_line_speed = sc->link_params.req_line_speed[cfg_idx];
7000 struct elink_params *lp = &sc->link_params;
7002 bnx2x_set_requested_fc(sc);
7004 if (load_mode == LOAD_DIAG) {
7005 lp->loopback_mode = ELINK_LOOPBACK_XGXS;
7006 /* Prefer doing PHY loopback at 10G speed, if possible */
7007 if (lp->req_line_speed[cfg_idx] < ELINK_SPEED_10000) {
7008 if (lp->speed_cap_mask[cfg_idx] &
7009 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
7010 lp->req_line_speed[cfg_idx] = ELINK_SPEED_10000;
7012 lp->req_line_speed[cfg_idx] = ELINK_SPEED_1000;
7017 if (load_mode == LOAD_LOOPBACK_EXT) {
7018 lp->loopback_mode = ELINK_LOOPBACK_EXT;
7021 rc = elink_phy_init(&sc->link_params, &sc->link_vars);
7023 bnx2x_calc_fc_adv(sc);
7025 if (sc->link_vars.link_up) {
7026 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7027 bnx2x_link_report(sc);
7030 sc->link_params.req_line_speed[cfg_idx] = req_line_speed;
7034 /* update flags in shmem */
7036 bnx2x_update_drv_flags(struct bnx2x_softc *sc, uint32_t flags, uint32_t set)
7040 if (SHMEM2_HAS(sc, drv_flags)) {
7041 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7042 drv_flags = SHMEM2_RD(sc, drv_flags);
7047 drv_flags &= ~flags;
7050 SHMEM2_WR(sc, drv_flags, drv_flags);
7052 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7056 /* periodic timer callout routine, only runs when the interface is up */
7057 void bnx2x_periodic_callout(struct bnx2x_softc *sc)
7059 if ((sc->state != BNX2X_STATE_OPEN) ||
7060 (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_STOP)) {
7061 PMD_DRV_LOG(WARNING, "periodic callout exit (state=0x%x)",
7065 if (!CHIP_REV_IS_SLOW(sc)) {
7067 * This barrier is needed to ensure the ordering between the writing
7068 * to the sc->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
7073 elink_period_func(&sc->link_params, &sc->link_vars);
7077 if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7078 int mb_idx = SC_FW_MB_IDX(sc);
7082 ++sc->fw_drv_pulse_wr_seq;
7083 sc->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
7085 drv_pulse = sc->fw_drv_pulse_wr_seq;
7086 bnx2x_drv_pulse(sc);
7088 mcp_pulse = (SHMEM_RD(sc, func_mb[mb_idx].mcp_pulse_mb) &
7089 MCP_PULSE_SEQ_MASK);
7092 * The delta between driver pulse and mcp response should
7093 * be 1 (before mcp response) or 0 (after mcp response).
7095 if ((drv_pulse != mcp_pulse) &&
7096 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
7097 /* someone lost a heartbeat... */
7099 "drv_pulse (0x%x) != mcp_pulse (0x%x)",
7100 drv_pulse, mcp_pulse);
7106 /* start the controller */
7107 static __rte_noinline
7108 int bnx2x_nic_load(struct bnx2x_softc *sc)
7111 uint32_t load_code = 0;
7114 PMD_INIT_FUNC_TRACE();
7116 sc->state = BNX2X_STATE_OPENING_WAITING_LOAD;
7119 /* must be called before memory allocation and HW init */
7120 bnx2x_ilt_set_info(sc);
7123 bnx2x_set_fp_rx_buf_size(sc);
7126 if (bnx2x_alloc_mem(sc) != 0) {
7127 sc->state = BNX2X_STATE_CLOSED;
7129 goto bnx2x_nic_load_error0;
7133 if (bnx2x_alloc_fw_stats_mem(sc) != 0) {
7134 sc->state = BNX2X_STATE_CLOSED;
7136 goto bnx2x_nic_load_error0;
7140 rc = bnx2x_vf_init(sc);
7142 sc->state = BNX2X_STATE_ERROR;
7143 goto bnx2x_nic_load_error0;
7148 /* set pf load just before approaching the MCP */
7149 bnx2x_set_pf_load(sc);
7151 /* if MCP exists send load request and analyze response */
7152 if (!BNX2X_NOMCP(sc)) {
7153 /* attempt to load pf */
7154 if (bnx2x_nic_load_request(sc, &load_code) != 0) {
7155 sc->state = BNX2X_STATE_CLOSED;
7157 goto bnx2x_nic_load_error1;
7160 /* what did the MCP say? */
7161 if (bnx2x_nic_load_analyze_req(sc, load_code) != 0) {
7162 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7163 sc->state = BNX2X_STATE_CLOSED;
7165 goto bnx2x_nic_load_error2;
7168 PMD_DRV_LOG(INFO, "Device has no MCP!");
7169 load_code = bnx2x_nic_load_no_mcp(sc);
7172 /* mark PMF if applicable */
7173 bnx2x_nic_load_pmf(sc, load_code);
7175 /* Init Function state controlling object */
7176 bnx2x_init_func_obj(sc);
7179 if (bnx2x_init_hw(sc, load_code) != 0) {
7180 PMD_DRV_LOG(NOTICE, "HW init failed");
7181 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7182 sc->state = BNX2X_STATE_CLOSED;
7184 goto bnx2x_nic_load_error2;
7188 bnx2x_nic_init(sc, load_code);
7190 /* Init per-function objects */
7192 bnx2x_init_objs(sc);
7194 /* set AFEX default VLAN tag to an invalid value */
7195 sc->devinfo.mf_info.afex_def_vlan_tag = -1;
7197 sc->state = BNX2X_STATE_OPENING_WAITING_PORT;
7198 rc = bnx2x_func_start(sc);
7200 PMD_DRV_LOG(NOTICE, "Function start failed!");
7201 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7202 sc->state = BNX2X_STATE_ERROR;
7203 goto bnx2x_nic_load_error3;
7206 /* send LOAD_DONE command to MCP */
7207 if (!BNX2X_NOMCP(sc)) {
7209 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7212 "MCP response failure, aborting");
7213 sc->state = BNX2X_STATE_ERROR;
7215 goto bnx2x_nic_load_error3;
7220 rc = bnx2x_setup_leading(sc);
7222 PMD_DRV_LOG(NOTICE, "Setup leading failed!");
7223 sc->state = BNX2X_STATE_ERROR;
7224 goto bnx2x_nic_load_error3;
7227 FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, i) {
7229 rc = bnx2x_setup_queue(sc, &sc->fp[i], FALSE);
7230 else /* IS_VF(sc) */
7231 rc = bnx2x_vf_setup_queue(sc, &sc->fp[i], FALSE);
7234 PMD_DRV_LOG(NOTICE, "Queue(%d) setup failed", i);
7235 sc->state = BNX2X_STATE_ERROR;
7236 goto bnx2x_nic_load_error3;
7240 rc = bnx2x_init_rss_pf(sc);
7242 PMD_DRV_LOG(NOTICE, "PF RSS init failed");
7243 sc->state = BNX2X_STATE_ERROR;
7244 goto bnx2x_nic_load_error3;
7247 /* now when Clients are configured we are ready to work */
7248 sc->state = BNX2X_STATE_OPEN;
7250 /* Configure a ucast MAC */
7252 rc = bnx2x_set_eth_mac(sc, TRUE);
7253 } else { /* IS_VF(sc) */
7254 rc = bnx2x_vf_set_mac(sc, TRUE);
7258 PMD_DRV_LOG(NOTICE, "Setting Ethernet MAC failed");
7259 sc->state = BNX2X_STATE_ERROR;
7260 goto bnx2x_nic_load_error3;
7264 rc = bnx2x_initial_phy_init(sc, LOAD_OPEN);
7266 sc->state = BNX2X_STATE_ERROR;
7267 goto bnx2x_nic_load_error3;
7271 sc->link_params.feature_config_flags &=
7272 ~ELINK_FEATURE_CONFIG_BOOT_FROM_SAN;
7275 switch (LOAD_OPEN) {
7281 case LOAD_LOOPBACK_EXT:
7282 sc->state = BNX2X_STATE_DIAG;
7290 bnx2x_update_drv_flags(sc, 1 << DRV_FLAGS_PORT_MASK, 0);
7292 bnx2x_link_status_update(sc);
7295 if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
7296 /* mark driver is loaded in shmem2 */
7297 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
7298 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
7300 DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED |
7301 DRV_FLAGS_CAPABILITIES_LOADED_L2));
7304 /* start fast path */
7305 /* Initialize Rx filter */
7306 bnx2x_set_rx_mode(sc);
7308 /* wait for all pending SP commands to complete */
7309 if (IS_PF(sc) && !bnx2x_wait_sp_comp(sc, ~0x0UL)) {
7310 PMD_DRV_LOG(NOTICE, "Timeout waiting for all SPs to complete!");
7311 bnx2x_periodic_stop(sc);
7312 bnx2x_nic_unload(sc, UNLOAD_CLOSE, FALSE);
7316 PMD_DRV_LOG(DEBUG, "NIC successfully loaded");
7320 bnx2x_nic_load_error3:
7323 bnx2x_int_disable_sync(sc, 1);
7325 /* clean out queued objects */
7326 bnx2x_squeeze_objects(sc);
7329 bnx2x_nic_load_error2:
7331 if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7332 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
7333 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
7338 bnx2x_nic_load_error1:
7340 /* clear pf_load status, as it was already set */
7342 bnx2x_clear_pf_load(sc);
7345 bnx2x_nic_load_error0:
7347 bnx2x_free_fw_stats_mem(sc);
7354 * Handles controller initialization.
7356 int bnx2x_init(struct bnx2x_softc *sc)
7358 int other_engine = SC_PATH(sc) ? 0 : 1;
7359 uint8_t other_load_status, load_status;
7360 uint8_t global = FALSE;
7363 /* Check if the driver is still running and bail out if it is. */
7364 if (sc->state != BNX2X_STATE_CLOSED) {
7365 PMD_DRV_LOG(DEBUG, "Init called while driver is running!");
7367 goto bnx2x_init_done;
7370 bnx2x_set_power_state(sc, PCI_PM_D0);
7373 * If parity occurred during the unload, then attentions and/or
7374 * RECOVERY_IN_PROGRESS may still be set. If so we want the first function
7375 * loaded on the current engine to complete the recovery. Parity recovery
7376 * is only relevant for PF driver.
7379 other_load_status = bnx2x_get_load_status(sc, other_engine);
7380 load_status = bnx2x_get_load_status(sc, SC_PATH(sc));
7382 if (!bnx2x_reset_is_done(sc, SC_PATH(sc)) ||
7383 bnx2x_chk_parity_attn(sc, &global, TRUE)) {
7386 * If there are attentions and they are in global blocks, set
7387 * the GLOBAL_RESET bit regardless whether it will be this
7388 * function that will complete the recovery or not.
7391 bnx2x_set_reset_global(sc);
7395 * Only the first function on the current engine should try
7396 * to recover in open. In case of attentions in global blocks
7397 * only the first in the chip should try to recover.
7400 && (!global ||!other_load_status))
7401 && bnx2x_trylock_leader_lock(sc)
7402 && !bnx2x_leader_reset(sc)) {
7404 "Recovered during init");
7408 /* recovery has failed... */
7409 bnx2x_set_power_state(sc, PCI_PM_D3hot);
7411 sc->recovery_state = BNX2X_RECOVERY_FAILED;
7414 "Recovery flow hasn't properly "
7415 "completed yet, try again later. "
7416 "If you still see this message after a "
7417 "few retries then power cycle is required.");
7420 goto bnx2x_init_done;
7425 sc->recovery_state = BNX2X_RECOVERY_DONE;
7427 rc = bnx2x_nic_load(sc);
7432 PMD_DRV_LOG(NOTICE, "Initialization failed, "
7433 "stack notified driver is NOT running!");
7439 static void bnx2x_get_function_num(struct bnx2x_softc *sc)
7444 * Read the ME register to get the function number. The ME register
7445 * holds the relative-function number and absolute-function number. The
7446 * absolute-function number appears only in E2 and above. Before that
7447 * these bits always contained zero, therefore we cannot blindly use them.
7450 val = REG_RD(sc, BAR_ME_REGISTER);
7453 (uint8_t) ((val & ME_REG_PF_NUM) >> ME_REG_PF_NUM_SHIFT);
7455 (uint8_t) ((val & ME_REG_ABS_PF_NUM) >> ME_REG_ABS_PF_NUM_SHIFT) &
7458 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7459 sc->pfunc_abs = ((sc->pfunc_rel << 1) | sc->path_id);
7461 sc->pfunc_abs = (sc->pfunc_rel | sc->path_id);
7465 "Relative function %d, Absolute function %d, Path %d",
7466 sc->pfunc_rel, sc->pfunc_abs, sc->path_id);
7469 static uint32_t bnx2x_get_shmem_mf_cfg_base(struct bnx2x_softc *sc)
7471 uint32_t shmem2_size;
7473 uint32_t mf_cfg_offset_value;
7476 offset = (SHMEM_ADDR(sc, func_mb) +
7477 (MAX_FUNC_NUM * sizeof(struct drv_func_mb)));
7480 if (sc->devinfo.shmem2_base != 0) {
7481 shmem2_size = SHMEM2_RD(sc, size);
7482 if (shmem2_size > offsetof(struct shmem2_region, mf_cfg_addr)) {
7483 mf_cfg_offset_value = SHMEM2_RD(sc, mf_cfg_addr);
7484 if (SHMEM_MF_CFG_ADDR_NONE != mf_cfg_offset_value) {
7485 offset = mf_cfg_offset_value;
7493 static uint32_t bnx2x_pcie_capability_read(struct bnx2x_softc *sc, int reg)
7496 struct bnx2x_pci_cap *caps;
7498 /* ensure PCIe capability is enabled */
7499 caps = pci_find_cap(sc, PCIY_EXPRESS, BNX2X_PCI_CAP);
7501 PMD_DRV_LOG(DEBUG, "Found PCIe capability: "
7502 "id=0x%04X type=0x%04X addr=0x%08X",
7503 caps->id, caps->type, caps->addr);
7504 pci_read(sc, (caps->addr + reg), &ret, 2);
7508 PMD_DRV_LOG(WARNING, "PCIe capability NOT FOUND!!!");
7513 static uint8_t bnx2x_is_pcie_pending(struct bnx2x_softc *sc)
7515 return bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_STA) &
7516 PCIM_EXP_STA_TRANSACTION_PND;
7520 * Walk the PCI capabiites list for the device to find what features are
7521 * supported. These capabilites may be enabled/disabled by firmware so it's
7522 * best to walk the list rather than make assumptions.
7524 static void bnx2x_probe_pci_caps(struct bnx2x_softc *sc)
7526 PMD_INIT_FUNC_TRACE();
7528 struct bnx2x_pci_cap *caps;
7529 uint16_t link_status;
7532 /* check if PCI Power Management is enabled */
7533 caps = pci_find_cap(sc, PCIY_PMG, BNX2X_PCI_CAP);
7535 PMD_DRV_LOG(DEBUG, "Found PM capability: "
7536 "id=0x%04X type=0x%04X addr=0x%08X",
7537 caps->id, caps->type, caps->addr);
7539 sc->devinfo.pcie_cap_flags |= BNX2X_PM_CAPABLE_FLAG;
7540 sc->devinfo.pcie_pm_cap_reg = caps->addr;
7543 link_status = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_LINK_STA);
7545 sc->devinfo.pcie_link_speed = (link_status & PCIM_LINK_STA_SPEED);
7546 sc->devinfo.pcie_link_width =
7547 ((link_status & PCIM_LINK_STA_WIDTH) >> 4);
7549 PMD_DRV_LOG(DEBUG, "PCIe link speed=%d width=%d",
7550 sc->devinfo.pcie_link_speed, sc->devinfo.pcie_link_width);
7552 sc->devinfo.pcie_cap_flags |= BNX2X_PCIE_CAPABLE_FLAG;
7554 /* check if MSI capability is enabled */
7555 caps = pci_find_cap(sc, PCIY_MSI, BNX2X_PCI_CAP);
7557 PMD_DRV_LOG(DEBUG, "Found MSI capability at 0x%04x", reg);
7559 sc->devinfo.pcie_cap_flags |= BNX2X_MSI_CAPABLE_FLAG;
7560 sc->devinfo.pcie_msi_cap_reg = caps->addr;
7563 /* check if MSI-X capability is enabled */
7564 caps = pci_find_cap(sc, PCIY_MSIX, BNX2X_PCI_CAP);
7566 PMD_DRV_LOG(DEBUG, "Found MSI-X capability at 0x%04x", reg);
7568 sc->devinfo.pcie_cap_flags |= BNX2X_MSIX_CAPABLE_FLAG;
7569 sc->devinfo.pcie_msix_cap_reg = caps->addr;
7573 static int bnx2x_get_shmem_mf_cfg_info_sd(struct bnx2x_softc *sc)
7575 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7578 /* get the outer vlan if we're in switch-dependent mode */
7580 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7581 mf_info->ext_id = (uint16_t) val;
7583 mf_info->multi_vnics_mode = 1;
7585 if (!VALID_OVLAN(mf_info->ext_id)) {
7586 PMD_DRV_LOG(NOTICE, "Invalid VLAN (%d)", mf_info->ext_id);
7590 /* get the capabilities */
7591 if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK) ==
7592 FUNC_MF_CFG_PROTOCOL_ISCSI) {
7593 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ISCSI;
7594 } else if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK)
7595 == FUNC_MF_CFG_PROTOCOL_FCOE) {
7596 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_FCOE;
7598 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ETHERNET;
7601 mf_info->vnics_per_port =
7602 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7607 static uint32_t bnx2x_get_shmem_ext_proto_support_flags(struct bnx2x_softc *sc)
7609 uint32_t retval = 0;
7612 val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7614 if (val & MACP_FUNC_CFG_FLAGS_ENABLED) {
7615 if (val & MACP_FUNC_CFG_FLAGS_ETHERNET) {
7616 retval |= MF_PROTO_SUPPORT_ETHERNET;
7618 if (val & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
7619 retval |= MF_PROTO_SUPPORT_ISCSI;
7621 if (val & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
7622 retval |= MF_PROTO_SUPPORT_FCOE;
7629 static int bnx2x_get_shmem_mf_cfg_info_si(struct bnx2x_softc *sc)
7631 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7635 * There is no outer vlan if we're in switch-independent mode.
7636 * If the mac is valid then assume multi-function.
7639 val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7641 mf_info->multi_vnics_mode = ((val & MACP_FUNC_CFG_FLAGS_MASK) != 0);
7643 mf_info->mf_protos_supported =
7644 bnx2x_get_shmem_ext_proto_support_flags(sc);
7646 mf_info->vnics_per_port =
7647 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7652 static int bnx2x_get_shmem_mf_cfg_info_niv(struct bnx2x_softc *sc)
7654 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7656 uint32_t func_config;
7657 uint32_t niv_config;
7659 mf_info->multi_vnics_mode = 1;
7661 e1hov_tag = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7662 func_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7663 niv_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].afex_config);
7666 (uint16_t) ((e1hov_tag & FUNC_MF_CFG_E1HOV_TAG_MASK) >>
7667 FUNC_MF_CFG_E1HOV_TAG_SHIFT);
7669 mf_info->default_vlan =
7670 (uint16_t) ((e1hov_tag & FUNC_MF_CFG_AFEX_VLAN_MASK) >>
7671 FUNC_MF_CFG_AFEX_VLAN_SHIFT);
7673 mf_info->niv_allowed_priorities =
7674 (uint8_t) ((niv_config & FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
7675 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT);
7677 mf_info->niv_default_cos =
7678 (uint8_t) ((func_config & FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
7679 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT);
7681 mf_info->afex_vlan_mode =
7682 ((niv_config & FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
7683 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT);
7685 mf_info->niv_mba_enabled =
7686 ((niv_config & FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK) >>
7687 FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT);
7689 mf_info->mf_protos_supported =
7690 bnx2x_get_shmem_ext_proto_support_flags(sc);
7692 mf_info->vnics_per_port =
7693 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7698 static int bnx2x_check_valid_mf_cfg(struct bnx2x_softc *sc)
7700 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7707 /* various MF mode sanity checks... */
7709 if (mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_HIDE) {
7711 "Enumerated function %d is marked as hidden",
7716 if ((mf_info->vnics_per_port > 1) && !mf_info->multi_vnics_mode) {
7717 PMD_DRV_LOG(NOTICE, "vnics_per_port=%d multi_vnics_mode=%d",
7718 mf_info->vnics_per_port, mf_info->multi_vnics_mode);
7722 if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7723 /* vnic id > 0 must have valid ovlan in switch-dependent mode */
7724 if ((SC_VN(sc) > 0) && !VALID_OVLAN(OVLAN(sc))) {
7725 PMD_DRV_LOG(NOTICE, "mf_mode=SD vnic_id=%d ovlan=%d",
7726 SC_VN(sc), OVLAN(sc));
7730 if (!VALID_OVLAN(OVLAN(sc)) && mf_info->multi_vnics_mode) {
7732 "mf_mode=SD multi_vnics_mode=%d ovlan=%d",
7733 mf_info->multi_vnics_mode, OVLAN(sc));
7738 * Verify all functions are either MF or SF mode. If MF, make sure
7739 * sure that all non-hidden functions have a valid ovlan. If SF,
7740 * make sure that all non-hidden functions have an invalid ovlan.
7742 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7743 mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7744 ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7745 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE) &&
7746 (((mf_info->multi_vnics_mode)
7747 && !VALID_OVLAN(ovlan1))
7748 || ((!mf_info->multi_vnics_mode)
7749 && VALID_OVLAN(ovlan1)))) {
7751 "mf_mode=SD function %d MF config "
7752 "mismatch, multi_vnics_mode=%d ovlan=%d",
7753 i, mf_info->multi_vnics_mode,
7759 /* Verify all funcs on the same port each have a different ovlan. */
7760 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7761 mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7762 ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7763 /* iterate from the next function on the port to the max func */
7764 for (j = i + 2; j < MAX_FUNC_NUM; j += 2) {
7766 MFCFG_RD(sc, func_mf_config[j].config);
7768 MFCFG_RD(sc, func_mf_config[j].e1hov_tag);
7769 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE)
7770 && VALID_OVLAN(ovlan1)
7771 && !(mf_cfg2 & FUNC_MF_CFG_FUNC_HIDE)
7772 && VALID_OVLAN(ovlan2)
7773 && (ovlan1 == ovlan2)) {
7775 "mf_mode=SD functions %d and %d "
7776 "have the same ovlan (%d)",
7783 /* MULTI_FUNCTION_SD */
7787 static int bnx2x_get_mf_cfg_info(struct bnx2x_softc *sc)
7789 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7790 uint32_t val, mac_upper;
7793 /* initialize mf_info defaults */
7794 mf_info->vnics_per_port = 1;
7795 mf_info->multi_vnics_mode = FALSE;
7796 mf_info->path_has_ovlan = FALSE;
7797 mf_info->mf_mode = SINGLE_FUNCTION;
7799 if (!CHIP_IS_MF_CAP(sc)) {
7803 if (sc->devinfo.mf_cfg_base == SHMEM_MF_CFG_ADDR_NONE) {
7804 PMD_DRV_LOG(NOTICE, "Invalid mf_cfg_base!");
7808 /* get the MF mode (switch dependent / independent / single-function) */
7810 val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
7812 switch (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK) {
7813 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
7816 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7818 /* check for legal upper mac bytes */
7819 if (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT) {
7820 mf_info->mf_mode = MULTI_FUNCTION_SI;
7823 "Invalid config for Switch Independent mode");
7828 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
7829 case SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4:
7831 /* get outer vlan configuration */
7832 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7834 if ((val & FUNC_MF_CFG_E1HOV_TAG_MASK) !=
7835 FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
7836 mf_info->mf_mode = MULTI_FUNCTION_SD;
7839 "Invalid config for Switch Dependent mode");
7844 case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
7846 /* not in MF mode, vnics_per_port=1 and multi_vnics_mode=FALSE */
7849 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
7852 * Mark MF mode as NIV if MCP version includes NPAR-SD support
7853 * and the MAC address is valid.
7856 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7858 if ((SHMEM2_HAS(sc, afex_driver_support)) &&
7859 (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT)) {
7860 mf_info->mf_mode = MULTI_FUNCTION_AFEX;
7862 PMD_DRV_LOG(NOTICE, "Invalid config for AFEX mode");
7869 PMD_DRV_LOG(NOTICE, "Unknown MF mode (0x%08x)",
7870 (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK));
7875 /* set path mf_mode (which could be different than function mf_mode) */
7876 if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7877 mf_info->path_has_ovlan = TRUE;
7878 } else if (mf_info->mf_mode == SINGLE_FUNCTION) {
7880 * Decide on path multi vnics mode. If we're not in MF mode and in
7881 * 4-port mode, this is good enough to check vnic-0 of the other port
7884 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7885 uint8_t other_port = !(PORT_ID(sc) & 1);
7886 uint8_t abs_func_other_port =
7887 (SC_PATH(sc) + (2 * other_port));
7892 [abs_func_other_port].e1hov_tag);
7894 mf_info->path_has_ovlan = VALID_OVLAN((uint16_t) val);
7898 if (mf_info->mf_mode == SINGLE_FUNCTION) {
7899 /* invalid MF config */
7900 if (SC_VN(sc) >= 1) {
7901 PMD_DRV_LOG(NOTICE, "VNIC ID >= 1 in SF mode");
7908 /* get the MF configuration */
7909 mf_info->mf_config[SC_VN(sc)] =
7910 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7912 switch (mf_info->mf_mode) {
7913 case MULTI_FUNCTION_SD:
7915 bnx2x_get_shmem_mf_cfg_info_sd(sc);
7918 case MULTI_FUNCTION_SI:
7920 bnx2x_get_shmem_mf_cfg_info_si(sc);
7923 case MULTI_FUNCTION_AFEX:
7925 bnx2x_get_shmem_mf_cfg_info_niv(sc);
7930 PMD_DRV_LOG(NOTICE, "Get MF config failed (mf_mode=0x%08x)",
7935 /* get the congestion management parameters */
7938 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7939 /* get min/max bw */
7940 val = MFCFG_RD(sc, func_mf_config[i].config);
7941 mf_info->min_bw[vnic] =
7942 ((val & FUNC_MF_CFG_MIN_BW_MASK) >>
7943 FUNC_MF_CFG_MIN_BW_SHIFT);
7944 mf_info->max_bw[vnic] =
7945 ((val & FUNC_MF_CFG_MAX_BW_MASK) >>
7946 FUNC_MF_CFG_MAX_BW_SHIFT);
7950 return bnx2x_check_valid_mf_cfg(sc);
7953 static int bnx2x_get_shmem_info(struct bnx2x_softc *sc)
7956 uint32_t mac_hi, mac_lo, val;
7958 PMD_INIT_FUNC_TRACE();
7961 mac_hi = mac_lo = 0;
7963 sc->link_params.sc = sc;
7964 sc->link_params.port = port;
7966 /* get the hardware config info */
7967 sc->devinfo.hw_config = SHMEM_RD(sc, dev_info.shared_hw_config.config);
7968 sc->devinfo.hw_config2 =
7969 SHMEM_RD(sc, dev_info.shared_hw_config.config2);
7971 sc->link_params.hw_led_mode =
7972 ((sc->devinfo.hw_config & SHARED_HW_CFG_LED_MODE_MASK) >>
7973 SHARED_HW_CFG_LED_MODE_SHIFT);
7975 /* get the port feature config */
7977 SHMEM_RD(sc, dev_info.port_feature_config[port].config);
7979 /* get the link params */
7980 sc->link_params.speed_cap_mask[ELINK_INT_PHY] =
7981 SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask)
7982 & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
7983 sc->link_params.speed_cap_mask[ELINK_EXT_PHY1] =
7984 SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask2)
7985 & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
7987 /* get the lane config */
7988 sc->link_params.lane_config =
7989 SHMEM_RD(sc, dev_info.port_hw_config[port].lane_config);
7991 /* get the link config */
7992 val = SHMEM_RD(sc, dev_info.port_feature_config[port].link_config);
7993 sc->port.link_config[ELINK_INT_PHY] = val;
7994 sc->link_params.switch_cfg = (val & PORT_FEATURE_CONNECTED_SWITCH_MASK);
7995 sc->port.link_config[ELINK_EXT_PHY1] =
7996 SHMEM_RD(sc, dev_info.port_feature_config[port].link_config2);
7998 /* get the override preemphasis flag and enable it or turn it off */
7999 val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
8000 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) {
8001 sc->link_params.feature_config_flags |=
8002 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8004 sc->link_params.feature_config_flags &=
8005 ~ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8008 /* get the initial value of the link params */
8009 sc->link_params.multi_phy_config =
8010 SHMEM_RD(sc, dev_info.port_hw_config[port].multi_phy_config);
8012 /* get external phy info */
8013 sc->port.ext_phy_config =
8014 SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
8016 /* get the multifunction configuration */
8017 bnx2x_get_mf_cfg_info(sc);
8019 /* get the mac address */
8022 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
8024 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_lower);
8026 mac_hi = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_upper);
8027 mac_lo = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_lower);
8030 if ((mac_lo == 0) && (mac_hi == 0)) {
8031 *sc->mac_addr_str = 0;
8032 PMD_DRV_LOG(NOTICE, "No Ethernet address programmed!");
8034 sc->link_params.mac_addr[0] = (uint8_t) (mac_hi >> 8);
8035 sc->link_params.mac_addr[1] = (uint8_t) (mac_hi);
8036 sc->link_params.mac_addr[2] = (uint8_t) (mac_lo >> 24);
8037 sc->link_params.mac_addr[3] = (uint8_t) (mac_lo >> 16);
8038 sc->link_params.mac_addr[4] = (uint8_t) (mac_lo >> 8);
8039 sc->link_params.mac_addr[5] = (uint8_t) (mac_lo);
8040 snprintf(sc->mac_addr_str, sizeof(sc->mac_addr_str),
8041 "%02x:%02x:%02x:%02x:%02x:%02x",
8042 sc->link_params.mac_addr[0],
8043 sc->link_params.mac_addr[1],
8044 sc->link_params.mac_addr[2],
8045 sc->link_params.mac_addr[3],
8046 sc->link_params.mac_addr[4],
8047 sc->link_params.mac_addr[5]);
8048 PMD_DRV_LOG(DEBUG, "Ethernet address: %s", sc->mac_addr_str);
8054 static void bnx2x_media_detect(struct bnx2x_softc *sc)
8056 uint32_t phy_idx = bnx2x_get_cur_phy_idx(sc);
8057 switch (sc->link_params.phy[phy_idx].media_type) {
8058 case ELINK_ETH_PHY_SFPP_10G_FIBER:
8059 case ELINK_ETH_PHY_SFP_1G_FIBER:
8060 case ELINK_ETH_PHY_XFP_FIBER:
8061 case ELINK_ETH_PHY_KR:
8062 case ELINK_ETH_PHY_CX4:
8063 PMD_DRV_LOG(INFO, "Found 10GBase-CX4 media.");
8064 sc->media = IFM_10G_CX4;
8066 case ELINK_ETH_PHY_DA_TWINAX:
8067 PMD_DRV_LOG(INFO, "Found 10Gb Twinax media.");
8068 sc->media = IFM_10G_TWINAX;
8070 case ELINK_ETH_PHY_BASE_T:
8071 PMD_DRV_LOG(INFO, "Found 10GBase-T media.");
8072 sc->media = IFM_10G_T;
8074 case ELINK_ETH_PHY_NOT_PRESENT:
8075 PMD_DRV_LOG(INFO, "Media not present.");
8078 case ELINK_ETH_PHY_UNSPECIFIED:
8080 PMD_DRV_LOG(INFO, "Unknown media!");
8086 #define GET_FIELD(value, fname) \
8087 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
8088 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
8089 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
8091 static int bnx2x_get_igu_cam_info(struct bnx2x_softc *sc)
8093 int pfid = SC_FUNC(sc);
8096 uint8_t fid, igu_sb_cnt = 0;
8098 sc->igu_base_sb = 0xff;
8100 if (CHIP_INT_MODE_IS_BC(sc)) {
8102 igu_sb_cnt = sc->igu_sb_cnt;
8103 sc->igu_base_sb = ((CHIP_IS_MODE_4_PORT(sc) ? pfid : vn) *
8105 sc->igu_dsb_id = (E1HVN_MAX * FP_SB_MAX_E1x +
8106 (CHIP_IS_MODE_4_PORT(sc) ? pfid : vn));
8110 /* IGU in normal mode - read CAM */
8112 igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; igu_sb_id++) {
8113 val = REG_RD(sc, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
8114 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) {
8118 if (fid & IGU_FID_ENCODE_IS_PF) {
8119 if ((fid & IGU_FID_PF_NUM_MASK) != pfid) {
8122 if (IGU_VEC(val) == 0) {
8123 /* default status block */
8124 sc->igu_dsb_id = igu_sb_id;
8126 if (sc->igu_base_sb == 0xff) {
8127 sc->igu_base_sb = igu_sb_id;
8135 * Due to new PF resource allocation by MFW T7.4 and above, it's optional
8136 * that number of CAM entries will not be equal to the value advertised in
8137 * PCI. Driver should use the minimal value of both as the actual status
8140 sc->igu_sb_cnt = min(sc->igu_sb_cnt, igu_sb_cnt);
8142 if (igu_sb_cnt == 0) {
8143 PMD_DRV_LOG(ERR, "CAM configuration error");
8151 * Gather various information from the device config space, the device itself,
8152 * shmem, and the user input.
8154 static int bnx2x_get_device_info(struct bnx2x_softc *sc)
8159 /* get the chip revision (chip metal comes from pci config space) */
8160 sc->devinfo.chip_id = sc->link_params.chip_id =
8161 (((REG_RD(sc, MISC_REG_CHIP_NUM) & 0xffff) << 16) |
8162 ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12) |
8163 (((REG_RD(sc, PCICFG_OFFSET + PCI_ID_VAL3) >> 24) & 0xf) << 4) |
8164 ((REG_RD(sc, MISC_REG_BOND_ID) & 0xf) << 0));
8166 /* force 57811 according to MISC register */
8167 if (REG_RD(sc, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
8168 if (CHIP_IS_57810(sc)) {
8169 sc->devinfo.chip_id = ((CHIP_NUM_57811 << 16) |
8171 devinfo.chip_id & 0x0000ffff));
8172 } else if (CHIP_IS_57810_MF(sc)) {
8173 sc->devinfo.chip_id = ((CHIP_NUM_57811_MF << 16) |
8175 devinfo.chip_id & 0x0000ffff));
8177 sc->devinfo.chip_id |= 0x1;
8181 "chip_id=0x%08x (num=0x%04x rev=0x%01x metal=0x%02x bond=0x%01x)",
8182 sc->devinfo.chip_id,
8183 ((sc->devinfo.chip_id >> 16) & 0xffff),
8184 ((sc->devinfo.chip_id >> 12) & 0xf),
8185 ((sc->devinfo.chip_id >> 4) & 0xff),
8186 ((sc->devinfo.chip_id >> 0) & 0xf));
8188 val = (REG_RD(sc, 0x2874) & 0x55);
8189 if ((sc->devinfo.chip_id & 0x1) || (CHIP_IS_E1H(sc) && (val == 0x55))) {
8190 sc->flags |= BNX2X_ONE_PORT_FLAG;
8191 PMD_DRV_LOG(DEBUG, "single port device");
8194 /* set the doorbell size */
8195 sc->doorbell_size = (1 << BNX2X_DB_SHIFT);
8197 /* determine whether the device is in 2 port or 4 port mode */
8198 sc->devinfo.chip_port_mode = CHIP_PORT_MODE_NONE; /* E1h */
8199 if (CHIP_IS_E2E3(sc)) {
8201 * Read port4mode_en_ovwr[0]:
8202 * If 1, four port mode is in port4mode_en_ovwr[1].
8203 * If 0, four port mode is in port4mode_en[0].
8205 val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);
8207 val = ((val >> 1) & 1);
8209 val = REG_RD(sc, MISC_REG_PORT4MODE_EN);
8212 sc->devinfo.chip_port_mode =
8213 (val) ? CHIP_4_PORT_MODE : CHIP_2_PORT_MODE;
8215 PMD_DRV_LOG(DEBUG, "Port mode = %s", (val) ? "4" : "2");
8218 /* get the function and path info for the device */
8219 bnx2x_get_function_num(sc);
8221 /* get the shared memory base address */
8222 sc->devinfo.shmem_base =
8223 sc->link_params.shmem_base = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
8224 sc->devinfo.shmem2_base =
8225 REG_RD(sc, (SC_PATH(sc) ? MISC_REG_GENERIC_CR_1 :
8226 MISC_REG_GENERIC_CR_0));
8228 if (!sc->devinfo.shmem_base) {
8229 /* this should ONLY prevent upcoming shmem reads */
8230 PMD_DRV_LOG(INFO, "MCP not active");
8231 sc->flags |= BNX2X_NO_MCP_FLAG;
8235 /* make sure the shared memory contents are valid */
8236 val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
8237 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) !=
8238 (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) {
8239 PMD_DRV_LOG(NOTICE, "Invalid SHMEM validity signature: 0x%08x",
8244 /* get the bootcode version */
8245 sc->devinfo.bc_ver = SHMEM_RD(sc, dev_info.bc_rev);
8246 snprintf(sc->devinfo.bc_ver_str,
8247 sizeof(sc->devinfo.bc_ver_str),
8249 ((sc->devinfo.bc_ver >> 24) & 0xff),
8250 ((sc->devinfo.bc_ver >> 16) & 0xff),
8251 ((sc->devinfo.bc_ver >> 8) & 0xff));
8252 PMD_DRV_LOG(INFO, "Bootcode version: %s", sc->devinfo.bc_ver_str);
8254 /* get the bootcode shmem address */
8255 sc->devinfo.mf_cfg_base = bnx2x_get_shmem_mf_cfg_base(sc);
8257 /* clean indirect addresses as they're not used */
8258 pci_write_long(sc, PCICFG_GRC_ADDRESS, 0);
8260 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F0, 0);
8261 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F0, 0);
8262 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F0, 0);
8263 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F0, 0);
8264 if (CHIP_IS_E1x(sc)) {
8265 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F1, 0);
8266 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F1, 0);
8267 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F1, 0);
8268 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F1, 0);
8272 /* get the nvram size */
8273 val = REG_RD(sc, MCP_REG_MCPR_NVM_CFG4);
8274 sc->devinfo.flash_size =
8275 (NVRAM_1MB_SIZE << (val & MCPR_NVM_CFG4_FLASH_SIZE));
8277 bnx2x_set_power_state(sc, PCI_PM_D0);
8278 /* get various configuration parameters from shmem */
8279 bnx2x_get_shmem_info(sc);
8281 /* initialize IGU parameters */
8282 if (CHIP_IS_E1x(sc)) {
8283 sc->devinfo.int_block = INT_BLOCK_HC;
8284 sc->igu_dsb_id = DEF_SB_IGU_ID;
8285 sc->igu_base_sb = 0;
8287 sc->devinfo.int_block = INT_BLOCK_IGU;
8289 /* do not allow device reset during IGU info preocessing */
8290 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8292 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
8294 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8297 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
8298 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION, val);
8299 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x7f);
8301 while (tout && REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8306 if (REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8308 "FORCING IGU Normal Mode failed!!!");
8309 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8314 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8315 PMD_DRV_LOG(DEBUG, "IGU Backward Compatible Mode");
8316 sc->devinfo.int_block |= INT_BLOCK_MODE_BW_COMP;
8318 PMD_DRV_LOG(DEBUG, "IGU Normal Mode");
8321 rc = bnx2x_get_igu_cam_info(sc);
8323 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8331 * Get base FW non-default (fast path) status block ID. This value is
8332 * used to initialize the fw_sb_id saved on the fp/queue structure to
8333 * determine the id used by the FW.
8335 if (CHIP_IS_E1x(sc)) {
8337 ((SC_PORT(sc) * FP_SB_MAX_E1x) + SC_L_ID(sc));
8340 * 57712+ - We currently use one FW SB per IGU SB (Rx and Tx of
8341 * the same queue are indicated on the same IGU SB). So we prefer
8342 * FW and IGU SBs to be the same value.
8344 sc->base_fw_ndsb = sc->igu_base_sb;
8347 elink_phy_probe(&sc->link_params);
8353 bnx2x_link_settings_supported(struct bnx2x_softc *sc, uint32_t switch_cfg)
8355 uint32_t cfg_size = 0;
8357 uint8_t port = SC_PORT(sc);
8359 /* aggregation of supported attributes of all external phys */
8360 sc->port.supported[0] = 0;
8361 sc->port.supported[1] = 0;
8363 switch (sc->link_params.num_phys) {
8365 sc->port.supported[0] =
8366 sc->link_params.phy[ELINK_INT_PHY].supported;
8370 sc->port.supported[0] =
8371 sc->link_params.phy[ELINK_EXT_PHY1].supported;
8375 if (sc->link_params.multi_phy_config &
8376 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
8377 sc->port.supported[1] =
8378 sc->link_params.phy[ELINK_EXT_PHY1].supported;
8379 sc->port.supported[0] =
8380 sc->link_params.phy[ELINK_EXT_PHY2].supported;
8382 sc->port.supported[0] =
8383 sc->link_params.phy[ELINK_EXT_PHY1].supported;
8384 sc->port.supported[1] =
8385 sc->link_params.phy[ELINK_EXT_PHY2].supported;
8391 if (!(sc->port.supported[0] || sc->port.supported[1])) {
8393 "Invalid phy config in NVRAM (PHY1=0x%08x PHY2=0x%08x)",
8395 dev_info.port_hw_config
8396 [port].external_phy_config),
8398 dev_info.port_hw_config
8399 [port].external_phy_config2));
8404 sc->port.phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR);
8406 switch (switch_cfg) {
8407 case ELINK_SWITCH_CFG_1G:
8410 NIG_REG_SERDES0_CTRL_PHY_ADDR + port * 0x10);
8412 case ELINK_SWITCH_CFG_10G:
8415 NIG_REG_XGXS0_CTRL_PHY_ADDR + port * 0x18);
8419 "Invalid switch config in"
8420 "link_config=0x%08x",
8421 sc->port.link_config[0]);
8426 PMD_DRV_LOG(INFO, "PHY addr 0x%08x", sc->port.phy_addr);
8428 /* mask what we support according to speed_cap_mask per configuration */
8429 for (idx = 0; idx < cfg_size; idx++) {
8430 if (!(sc->link_params.speed_cap_mask[idx] &
8431 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) {
8432 sc->port.supported[idx] &=
8433 ~ELINK_SUPPORTED_10baseT_Half;
8436 if (!(sc->link_params.speed_cap_mask[idx] &
8437 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) {
8438 sc->port.supported[idx] &=
8439 ~ELINK_SUPPORTED_10baseT_Full;
8442 if (!(sc->link_params.speed_cap_mask[idx] &
8443 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) {
8444 sc->port.supported[idx] &=
8445 ~ELINK_SUPPORTED_100baseT_Half;
8448 if (!(sc->link_params.speed_cap_mask[idx] &
8449 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) {
8450 sc->port.supported[idx] &=
8451 ~ELINK_SUPPORTED_100baseT_Full;
8454 if (!(sc->link_params.speed_cap_mask[idx] &
8455 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) {
8456 sc->port.supported[idx] &=
8457 ~ELINK_SUPPORTED_1000baseT_Full;
8460 if (!(sc->link_params.speed_cap_mask[idx] &
8461 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) {
8462 sc->port.supported[idx] &=
8463 ~ELINK_SUPPORTED_2500baseX_Full;
8466 if (!(sc->link_params.speed_cap_mask[idx] &
8467 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8468 sc->port.supported[idx] &=
8469 ~ELINK_SUPPORTED_10000baseT_Full;
8472 if (!(sc->link_params.speed_cap_mask[idx] &
8473 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) {
8474 sc->port.supported[idx] &=
8475 ~ELINK_SUPPORTED_20000baseKR2_Full;
8479 PMD_DRV_LOG(INFO, "PHY supported 0=0x%08x 1=0x%08x",
8480 sc->port.supported[0], sc->port.supported[1]);
8483 static void bnx2x_link_settings_requested(struct bnx2x_softc *sc)
8485 uint32_t link_config;
8487 uint32_t cfg_size = 0;
8489 sc->port.advertising[0] = 0;
8490 sc->port.advertising[1] = 0;
8492 switch (sc->link_params.num_phys) {
8502 for (idx = 0; idx < cfg_size; idx++) {
8503 sc->link_params.req_duplex[idx] = DUPLEX_FULL;
8504 link_config = sc->port.link_config[idx];
8506 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
8507 case PORT_FEATURE_LINK_SPEED_AUTO:
8508 if (sc->port.supported[idx] & ELINK_SUPPORTED_Autoneg) {
8509 sc->link_params.req_line_speed[idx] =
8510 ELINK_SPEED_AUTO_NEG;
8511 sc->port.advertising[idx] |=
8512 sc->port.supported[idx];
8513 if (sc->link_params.phy[ELINK_EXT_PHY1].type ==
8514 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833)
8515 sc->port.advertising[idx] |=
8516 (ELINK_SUPPORTED_100baseT_Half |
8517 ELINK_SUPPORTED_100baseT_Full);
8519 /* force 10G, no AN */
8520 sc->link_params.req_line_speed[idx] =
8522 sc->port.advertising[idx] |=
8523 (ADVERTISED_10000baseT_Full |
8529 case PORT_FEATURE_LINK_SPEED_10M_FULL:
8531 port.supported[idx] & ELINK_SUPPORTED_10baseT_Full)
8533 sc->link_params.req_line_speed[idx] =
8535 sc->port.advertising[idx] |=
8536 (ADVERTISED_10baseT_Full | ADVERTISED_TP);
8539 "Invalid NVRAM config link_config=0x%08x "
8540 "speed_cap_mask=0x%08x",
8543 link_params.speed_cap_mask[idx]);
8548 case PORT_FEATURE_LINK_SPEED_10M_HALF:
8550 port.supported[idx] & ELINK_SUPPORTED_10baseT_Half)
8552 sc->link_params.req_line_speed[idx] =
8554 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8555 sc->port.advertising[idx] |=
8556 (ADVERTISED_10baseT_Half | ADVERTISED_TP);
8559 "Invalid NVRAM config link_config=0x%08x "
8560 "speed_cap_mask=0x%08x",
8563 link_params.speed_cap_mask[idx]);
8568 case PORT_FEATURE_LINK_SPEED_100M_FULL:
8570 port.supported[idx] & ELINK_SUPPORTED_100baseT_Full)
8572 sc->link_params.req_line_speed[idx] =
8574 sc->port.advertising[idx] |=
8575 (ADVERTISED_100baseT_Full | ADVERTISED_TP);
8578 "Invalid NVRAM config link_config=0x%08x "
8579 "speed_cap_mask=0x%08x",
8582 link_params.speed_cap_mask[idx]);
8587 case PORT_FEATURE_LINK_SPEED_100M_HALF:
8589 port.supported[idx] & ELINK_SUPPORTED_100baseT_Half)
8591 sc->link_params.req_line_speed[idx] =
8593 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8594 sc->port.advertising[idx] |=
8595 (ADVERTISED_100baseT_Half | ADVERTISED_TP);
8598 "Invalid NVRAM config link_config=0x%08x "
8599 "speed_cap_mask=0x%08x",
8602 link_params.speed_cap_mask[idx]);
8607 case PORT_FEATURE_LINK_SPEED_1G:
8608 if (sc->port.supported[idx] &
8609 ELINK_SUPPORTED_1000baseT_Full) {
8610 sc->link_params.req_line_speed[idx] =
8612 sc->port.advertising[idx] |=
8613 (ADVERTISED_1000baseT_Full | ADVERTISED_TP);
8616 "Invalid NVRAM config link_config=0x%08x "
8617 "speed_cap_mask=0x%08x",
8620 link_params.speed_cap_mask[idx]);
8625 case PORT_FEATURE_LINK_SPEED_2_5G:
8626 if (sc->port.supported[idx] &
8627 ELINK_SUPPORTED_2500baseX_Full) {
8628 sc->link_params.req_line_speed[idx] =
8630 sc->port.advertising[idx] |=
8631 (ADVERTISED_2500baseX_Full | ADVERTISED_TP);
8634 "Invalid NVRAM config link_config=0x%08x "
8635 "speed_cap_mask=0x%08x",
8638 link_params.speed_cap_mask[idx]);
8643 case PORT_FEATURE_LINK_SPEED_10G_CX4:
8644 if (sc->port.supported[idx] &
8645 ELINK_SUPPORTED_10000baseT_Full) {
8646 sc->link_params.req_line_speed[idx] =
8648 sc->port.advertising[idx] |=
8649 (ADVERTISED_10000baseT_Full |
8653 "Invalid NVRAM config link_config=0x%08x "
8654 "speed_cap_mask=0x%08x",
8657 link_params.speed_cap_mask[idx]);
8662 case PORT_FEATURE_LINK_SPEED_20G:
8663 sc->link_params.req_line_speed[idx] = ELINK_SPEED_20000;
8668 "Invalid NVRAM config link_config=0x%08x "
8669 "speed_cap_mask=0x%08x", link_config,
8670 sc->link_params.speed_cap_mask[idx]);
8671 sc->link_params.req_line_speed[idx] =
8672 ELINK_SPEED_AUTO_NEG;
8673 sc->port.advertising[idx] = sc->port.supported[idx];
8677 sc->link_params.req_flow_ctrl[idx] =
8678 (link_config & PORT_FEATURE_FLOW_CONTROL_MASK);
8680 if (sc->link_params.req_flow_ctrl[idx] == ELINK_FLOW_CTRL_AUTO) {
8683 port.supported[idx] & ELINK_SUPPORTED_Autoneg)) {
8684 sc->link_params.req_flow_ctrl[idx] =
8685 ELINK_FLOW_CTRL_NONE;
8687 bnx2x_set_requested_fc(sc);
8693 static void bnx2x_get_phy_info(struct bnx2x_softc *sc)
8695 uint8_t port = SC_PORT(sc);
8698 PMD_INIT_FUNC_TRACE();
8700 /* shmem data already read in bnx2x_get_shmem_info() */
8702 bnx2x_link_settings_supported(sc, sc->link_params.switch_cfg);
8703 bnx2x_link_settings_requested(sc);
8705 /* configure link feature according to nvram value */
8707 (((SHMEM_RD(sc, dev_info.port_feature_config[port].eee_power_mode))
8708 & PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
8709 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
8710 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
8711 sc->link_params.eee_mode = (ELINK_EEE_MODE_ADV_LPI |
8712 ELINK_EEE_MODE_ENABLE_LPI |
8713 ELINK_EEE_MODE_OUTPUT_TIME);
8715 sc->link_params.eee_mode = 0;
8718 /* get the media type */
8719 bnx2x_media_detect(sc);
8722 static void bnx2x_set_modes_bitmap(struct bnx2x_softc *sc)
8724 uint32_t flags = MODE_ASIC | MODE_PORT2;
8726 if (CHIP_IS_E2(sc)) {
8728 } else if (CHIP_IS_E3(sc)) {
8730 if (CHIP_REV(sc) == CHIP_REV_Ax) {
8731 flags |= MODE_E3_A0;
8732 } else { /*if (CHIP_REV(sc) == CHIP_REV_Bx) */
8734 flags |= MODE_E3_B0 | MODE_COS3;
8740 switch (sc->devinfo.mf_info.mf_mode) {
8741 case MULTI_FUNCTION_SD:
8742 flags |= MODE_MF_SD;
8744 case MULTI_FUNCTION_SI:
8745 flags |= MODE_MF_SI;
8747 case MULTI_FUNCTION_AFEX:
8748 flags |= MODE_MF_AFEX;
8755 #if defined(__LITTLE_ENDIAN)
8756 flags |= MODE_LITTLE_ENDIAN;
8757 #else /* __BIG_ENDIAN */
8758 flags |= MODE_BIG_ENDIAN;
8761 INIT_MODE_FLAGS(sc) = flags;
8764 int bnx2x_alloc_hsi_mem(struct bnx2x_softc *sc)
8766 struct bnx2x_fastpath *fp;
8771 /************************/
8772 /* DEFAULT STATUS BLOCK */
8773 /************************/
8775 if (bnx2x_dma_alloc(sc, sizeof(struct host_sp_status_block),
8776 &sc->def_sb_dma, "def_sb",
8777 RTE_CACHE_LINE_SIZE) != 0) {
8782 (struct host_sp_status_block *)sc->def_sb_dma.vaddr;
8787 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8788 &sc->eq_dma, "ev_queue",
8789 RTE_CACHE_LINE_SIZE) != 0) {
8794 sc->eq = (union event_ring_elem *)sc->eq_dma.vaddr;
8800 if (bnx2x_dma_alloc(sc, sizeof(struct bnx2x_slowpath),
8802 RTE_CACHE_LINE_SIZE) != 0) {
8808 sc->sp = (struct bnx2x_slowpath *)sc->sp_dma.vaddr;
8810 /*******************/
8811 /* SLOW PATH QUEUE */
8812 /*******************/
8814 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8815 &sc->spq_dma, "sp_queue",
8816 RTE_CACHE_LINE_SIZE) != 0) {
8823 sc->spq = (struct eth_spe *)sc->spq_dma.vaddr;
8825 /***************************/
8826 /* FW DECOMPRESSION BUFFER */
8827 /***************************/
8829 if (bnx2x_dma_alloc(sc, FW_BUF_SIZE, &sc->gz_buf_dma,
8830 "fw_buf", RTE_CACHE_LINE_SIZE) != 0) {
8838 sc->gz_buf = (void *)sc->gz_buf_dma.vaddr;
8845 /* allocate DMA memory for each fastpath structure */
8846 for (i = 0; i < sc->num_queues; i++) {
8851 /*******************/
8852 /* FP STATUS BLOCK */
8853 /*******************/
8855 snprintf(buf, sizeof(buf), "fp_%d_sb", i);
8856 if (bnx2x_dma_alloc(sc, sizeof(union bnx2x_host_hc_status_block),
8857 &fp->sb_dma, buf, RTE_CACHE_LINE_SIZE) != 0) {
8858 PMD_DRV_LOG(NOTICE, "Failed to alloc %s", buf);
8861 if (CHIP_IS_E2E3(sc)) {
8862 fp->status_block.e2_sb =
8863 (struct host_hc_status_block_e2 *)
8866 fp->status_block.e1x_sb =
8867 (struct host_hc_status_block_e1x *)
8876 void bnx2x_free_hsi_mem(struct bnx2x_softc *sc)
8878 struct bnx2x_fastpath *fp;
8881 for (i = 0; i < sc->num_queues; i++) {
8884 /*******************/
8885 /* FP STATUS BLOCK */
8886 /*******************/
8888 memset(&fp->status_block, 0, sizeof(fp->status_block));
8891 /***************************/
8892 /* FW DECOMPRESSION BUFFER */
8893 /***************************/
8897 /*******************/
8898 /* SLOW PATH QUEUE */
8899 /*******************/
8915 /************************/
8916 /* DEFAULT STATUS BLOCK */
8917 /************************/
8924 * Previous driver DMAE transaction may have occurred when pre-boot stage
8925 * ended and boot began. This would invalidate the addresses of the
8926 * transaction, resulting in was-error bit set in the PCI causing all
8927 * hw-to-host PCIe transactions to timeout. If this happened we want to clear
8928 * the interrupt which detected this from the pglueb and the was-done bit
8930 static void bnx2x_prev_interrupted_dmae(struct bnx2x_softc *sc)
8934 if (!CHIP_IS_E1x(sc)) {
8935 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS);
8936 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
8937 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
8943 static int bnx2x_prev_mcp_done(struct bnx2x_softc *sc)
8945 uint32_t rc = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE,
8946 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
8948 PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
8955 static struct bnx2x_prev_list_node *bnx2x_prev_path_get_entry(struct bnx2x_softc *sc)
8957 struct bnx2x_prev_list_node *tmp;
8959 LIST_FOREACH(tmp, &bnx2x_prev_list, node) {
8960 if ((sc->pcie_bus == tmp->bus) &&
8961 (sc->pcie_device == tmp->slot) &&
8962 (SC_PATH(sc) == tmp->path)) {
8970 static uint8_t bnx2x_prev_is_path_marked(struct bnx2x_softc *sc)
8972 struct bnx2x_prev_list_node *tmp;
8975 rte_spinlock_lock(&bnx2x_prev_mtx);
8977 tmp = bnx2x_prev_path_get_entry(sc);
8981 "Path %d/%d/%d was marked by AER",
8982 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
8986 "Path %d/%d/%d was already cleaned from previous drivers",
8987 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
8991 rte_spinlock_unlock(&bnx2x_prev_mtx);
8996 static int bnx2x_prev_mark_path(struct bnx2x_softc *sc, uint8_t after_undi)
8998 struct bnx2x_prev_list_node *tmp;
9000 rte_spinlock_lock(&bnx2x_prev_mtx);
9002 /* Check whether the entry for this path already exists */
9003 tmp = bnx2x_prev_path_get_entry(sc);
9007 "Re-marking AER in path %d/%d/%d",
9008 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9011 "Removing AER indication from path %d/%d/%d",
9012 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9016 rte_spinlock_unlock(&bnx2x_prev_mtx);
9020 rte_spinlock_unlock(&bnx2x_prev_mtx);
9022 /* Create an entry for this path and add it */
9023 tmp = rte_malloc("", sizeof(struct bnx2x_prev_list_node),
9024 RTE_CACHE_LINE_SIZE);
9026 PMD_DRV_LOG(NOTICE, "Failed to allocate 'bnx2x_prev_list_node'");
9030 tmp->bus = sc->pcie_bus;
9031 tmp->slot = sc->pcie_device;
9032 tmp->path = SC_PATH(sc);
9034 tmp->undi = after_undi ? (1 << SC_PORT(sc)) : 0;
9036 rte_spinlock_lock(&bnx2x_prev_mtx);
9038 LIST_INSERT_HEAD(&bnx2x_prev_list, tmp, node);
9040 rte_spinlock_unlock(&bnx2x_prev_mtx);
9045 static int bnx2x_do_flr(struct bnx2x_softc *sc)
9049 /* only E2 and onwards support FLR */
9050 if (CHIP_IS_E1x(sc)) {
9051 PMD_DRV_LOG(WARNING, "FLR not supported in E1H");
9055 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9056 if (sc->devinfo.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9057 PMD_DRV_LOG(WARNING,
9058 "FLR not supported by BC_VER: 0x%08x",
9059 sc->devinfo.bc_ver);
9063 /* Wait for Transaction Pending bit clean */
9064 for (i = 0; i < 4; i++) {
9066 DELAY(((1 << (i - 1)) * 100) * 1000);
9069 if (!bnx2x_is_pcie_pending(sc)) {
9074 PMD_DRV_LOG(NOTICE, "PCIE transaction is not cleared, "
9075 "proceeding with reset anyway");
9078 bnx2x_fw_command(sc, DRV_MSG_CODE_INITIATE_FLR, 0);
9083 struct bnx2x_mac_vals {
9091 uint32_t bmac_val[2];
9095 bnx2x_prev_unload_close_mac(struct bnx2x_softc *sc, struct bnx2x_mac_vals *vals)
9097 uint32_t val, base_addr, offset, mask, reset_reg;
9098 uint8_t mac_stopped = FALSE;
9099 uint8_t port = SC_PORT(sc);
9100 uint32_t wb_data[2];
9102 /* reset addresses as they also mark which values were changed */
9103 vals->bmac_addr = 0;
9104 vals->umac_addr = 0;
9105 vals->xmac_addr = 0;
9106 vals->emac_addr = 0;
9108 reset_reg = REG_RD(sc, MISC_REG_RESET_REG_2);
9110 if (!CHIP_IS_E3(sc)) {
9111 val = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9112 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9113 if ((mask & reset_reg) && val) {
9114 base_addr = SC_PORT(sc) ? NIG_REG_INGRESS_BMAC1_MEM
9115 : NIG_REG_INGRESS_BMAC0_MEM;
9116 offset = CHIP_IS_E2(sc) ? BIGMAC2_REGISTER_BMAC_CONTROL
9117 : BIGMAC_REGISTER_BMAC_CONTROL;
9120 * use rd/wr since we cannot use dmae. This is safe
9121 * since MCP won't access the bus due to the request
9122 * to unload, and no function on the path can be
9123 * loaded at this time.
9125 wb_data[0] = REG_RD(sc, base_addr + offset);
9126 wb_data[1] = REG_RD(sc, base_addr + offset + 0x4);
9127 vals->bmac_addr = base_addr + offset;
9128 vals->bmac_val[0] = wb_data[0];
9129 vals->bmac_val[1] = wb_data[1];
9130 wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE;
9131 REG_WR(sc, vals->bmac_addr, wb_data[0]);
9132 REG_WR(sc, vals->bmac_addr + 0x4, wb_data[1]);
9135 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + SC_PORT(sc) * 4;
9136 vals->emac_val = REG_RD(sc, vals->emac_addr);
9137 REG_WR(sc, vals->emac_addr, 0);
9140 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9141 base_addr = SC_PORT(sc) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9142 val = REG_RD(sc, base_addr + XMAC_REG_PFC_CTRL_HI);
9143 REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9145 REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9147 vals->xmac_addr = base_addr + XMAC_REG_CTRL;
9148 vals->xmac_val = REG_RD(sc, vals->xmac_addr);
9149 REG_WR(sc, vals->xmac_addr, 0);
9153 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9154 if (mask & reset_reg) {
9155 base_addr = SC_PORT(sc) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9156 vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
9157 vals->umac_val = REG_RD(sc, vals->umac_addr);
9158 REG_WR(sc, vals->umac_addr, 0);
9168 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9169 #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
9170 #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
9171 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
9174 bnx2x_prev_unload_undi_inc(struct bnx2x_softc *sc, uint8_t port, uint8_t inc)
9177 uint32_t tmp_reg = REG_RD(sc, BNX2X_PREV_UNDI_PROD_ADDR(port));
9179 rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9180 bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9182 tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9183 REG_WR(sc, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9186 static int bnx2x_prev_unload_common(struct bnx2x_softc *sc)
9188 uint32_t reset_reg, tmp_reg = 0, rc;
9189 uint8_t prev_undi = FALSE;
9190 struct bnx2x_mac_vals mac_vals;
9191 uint32_t timer_count = 1000;
9195 * It is possible a previous function received 'common' answer,
9196 * but hasn't loaded yet, therefore creating a scenario of
9197 * multiple functions receiving 'common' on the same path.
9199 memset(&mac_vals, 0, sizeof(mac_vals));
9201 if (bnx2x_prev_is_path_marked(sc)) {
9202 return bnx2x_prev_mcp_done(sc);
9205 reset_reg = REG_RD(sc, MISC_REG_RESET_REG_1);
9207 /* Reset should be performed after BRB is emptied */
9208 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
9209 /* Close the MAC Rx to prevent BRB from filling up */
9210 bnx2x_prev_unload_close_mac(sc, &mac_vals);
9212 /* close LLH filters towards the BRB */
9213 elink_set_rx_filter(&sc->link_params, 0);
9216 * Check if the UNDI driver was previously loaded.
9217 * UNDI driver initializes CID offset for normal bell to 0x7
9219 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
9220 tmp_reg = REG_RD(sc, DORQ_REG_NORM_CID_OFST);
9221 if (tmp_reg == 0x7) {
9222 PMD_DRV_LOG(DEBUG, "UNDI previously loaded");
9224 /* clear the UNDI indication */
9225 REG_WR(sc, DORQ_REG_NORM_CID_OFST, 0);
9226 /* clear possible idle check errors */
9227 REG_RD(sc, NIG_REG_NIG_INT_STS_CLR_0);
9231 /* wait until BRB is empty */
9232 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9233 while (timer_count) {
9236 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9241 PMD_DRV_LOG(DEBUG, "BRB still has 0x%08x", tmp_reg);
9243 /* reset timer as long as BRB actually gets emptied */
9244 if (prev_brb > tmp_reg) {
9250 /* If UNDI resides in memory, manually increment it */
9252 bnx2x_prev_unload_undi_inc(sc, SC_PORT(sc), 1);
9259 PMD_DRV_LOG(NOTICE, "Failed to empty BRB");
9263 /* No packets are in the pipeline, path is ready for reset */
9264 bnx2x_reset_common(sc);
9266 if (mac_vals.xmac_addr) {
9267 REG_WR(sc, mac_vals.xmac_addr, mac_vals.xmac_val);
9269 if (mac_vals.umac_addr) {
9270 REG_WR(sc, mac_vals.umac_addr, mac_vals.umac_val);
9272 if (mac_vals.emac_addr) {
9273 REG_WR(sc, mac_vals.emac_addr, mac_vals.emac_val);
9275 if (mac_vals.bmac_addr) {
9276 REG_WR(sc, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
9277 REG_WR(sc, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
9280 rc = bnx2x_prev_mark_path(sc, prev_undi);
9282 bnx2x_prev_mcp_done(sc);
9286 return bnx2x_prev_mcp_done(sc);
9289 static int bnx2x_prev_unload_uncommon(struct bnx2x_softc *sc)
9293 /* Test if previous unload process was already finished for this path */
9294 if (bnx2x_prev_is_path_marked(sc)) {
9295 return bnx2x_prev_mcp_done(sc);
9299 * If function has FLR capabilities, and existing FW version matches
9300 * the one required, then FLR will be sufficient to clean any residue
9301 * left by previous driver
9303 rc = bnx2x_nic_load_analyze_req(sc, FW_MSG_CODE_DRV_LOAD_FUNCTION);
9305 /* fw version is good */
9306 rc = bnx2x_do_flr(sc);
9310 /* FLR was performed */
9314 PMD_DRV_LOG(INFO, "Could not FLR");
9316 /* Close the MCP request, return failure */
9317 rc = bnx2x_prev_mcp_done(sc);
9319 rc = BNX2X_PREV_WAIT_NEEDED;
9325 static int bnx2x_prev_unload(struct bnx2x_softc *sc)
9327 int time_counter = 10;
9328 uint32_t fw, hw_lock_reg, hw_lock_val;
9332 * Clear HW from errors which may have resulted from an interrupted
9335 bnx2x_prev_interrupted_dmae(sc);
9337 /* Release previously held locks */
9338 if (SC_FUNC(sc) <= 5)
9339 hw_lock_reg = (MISC_REG_DRIVER_CONTROL_1 + SC_FUNC(sc) * 8);
9342 (MISC_REG_DRIVER_CONTROL_7 + (SC_FUNC(sc) - 6) * 8);
9344 hw_lock_val = (REG_RD(sc, hw_lock_reg));
9346 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
9347 REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
9348 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << SC_PORT(sc)));
9350 REG_WR(sc, hw_lock_reg, 0xffffffff);
9353 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(sc, MCP_REG_MCPR_ACCESS_LOCK)) {
9354 REG_WR(sc, MCP_REG_MCPR_ACCESS_LOCK, 0);
9358 /* Lock MCP using an unload request */
9359 fw = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
9361 PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
9366 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
9367 rc = bnx2x_prev_unload_common(sc);
9371 /* non-common reply from MCP might require looping */
9372 rc = bnx2x_prev_unload_uncommon(sc);
9373 if (rc != BNX2X_PREV_WAIT_NEEDED) {
9378 } while (--time_counter);
9380 if (!time_counter || rc) {
9381 PMD_DRV_LOG(NOTICE, "Failed to unload previous driver!");
9389 bnx2x_dcbx_set_state(struct bnx2x_softc *sc, uint8_t dcb_on, uint32_t dcbx_enabled)
9391 if (!CHIP_IS_E1x(sc)) {
9392 sc->dcb_state = dcb_on;
9393 sc->dcbx_enabled = dcbx_enabled;
9395 sc->dcb_state = FALSE;
9396 sc->dcbx_enabled = BNX2X_DCBX_ENABLED_INVALID;
9399 "DCB state [%s:%s]",
9400 dcb_on ? "ON" : "OFF",
9401 (dcbx_enabled == BNX2X_DCBX_ENABLED_OFF) ? "user-mode" :
9403 BNX2X_DCBX_ENABLED_ON_NEG_OFF) ? "on-chip static"
9405 BNX2X_DCBX_ENABLED_ON_NEG_ON) ?
9406 "on-chip with negotiation" : "invalid");
9409 static int bnx2x_set_qm_cid_count(struct bnx2x_softc *sc)
9411 int cid_count = BNX2X_L2_MAX_CID(sc);
9413 if (CNIC_SUPPORT(sc)) {
9414 cid_count += CNIC_CID_MAX;
9417 return roundup(cid_count, QM_CID_ROUND);
9420 static void bnx2x_init_multi_cos(struct bnx2x_softc *sc)
9424 uint32_t pri_map = 0;
9426 for (pri = 0; pri < BNX2X_MAX_PRIORITY; pri++) {
9427 cos = ((pri_map & (0xf << (pri * 4))) >> (pri * 4));
9428 if (cos < sc->max_cos) {
9429 sc->prio_to_cos[pri] = cos;
9431 PMD_DRV_LOG(WARNING,
9432 "Invalid COS %d for priority %d "
9433 "(max COS is %d), setting to 0", cos, pri,
9435 sc->prio_to_cos[pri] = 0;
9440 static int bnx2x_pci_get_caps(struct bnx2x_softc *sc)
9447 struct bnx2x_pci_cap *cap;
9449 cap = sc->pci_caps = rte_zmalloc("caps", sizeof(struct bnx2x_pci_cap),
9450 RTE_CACHE_LINE_SIZE);
9452 PMD_DRV_LOG(NOTICE, "Failed to allocate memory");
9457 pci_read(sc, PCI_STATUS, &status, 2);
9458 if (!(status & PCI_STATUS_CAP_LIST)) {
9460 pci_read(sc, PCIR_STATUS, &status, 2);
9461 if (!(status & PCIM_STATUS_CAPPRESENT)) {
9463 PMD_DRV_LOG(NOTICE, "PCIe capability reading failed");
9468 pci_read(sc, PCI_CAPABILITY_LIST, &pci_cap.next, 1);
9470 pci_read(sc, PCIR_CAP_PTR, &pci_cap.next, 1);
9472 while (pci_cap.next) {
9473 cap->addr = pci_cap.next & ~3;
9474 pci_read(sc, pci_cap.next & ~3, &pci_cap, 2);
9475 if (pci_cap.id == 0xff)
9477 cap->id = pci_cap.id;
9478 cap->type = BNX2X_PCI_CAP;
9479 cap->next = rte_zmalloc("pci_cap",
9480 sizeof(struct bnx2x_pci_cap),
9481 RTE_CACHE_LINE_SIZE);
9483 PMD_DRV_LOG(NOTICE, "Failed to allocate memory");
9492 static void bnx2x_init_rte(struct bnx2x_softc *sc)
9495 sc->max_tx_queues = min(BNX2X_VF_MAX_QUEUES_PER_VF,
9497 sc->max_rx_queues = min(BNX2X_VF_MAX_QUEUES_PER_VF,
9500 sc->max_rx_queues = BNX2X_MAX_RSS_COUNT(sc);
9501 sc->max_tx_queues = sc->max_rx_queues;
9505 #define FW_HEADER_LEN 104
9506 #define FW_NAME_57711 "/lib/firmware/bnx2x/bnx2x-e1h-7.2.51.0.fw"
9507 #define FW_NAME_57810 "/lib/firmware/bnx2x/bnx2x-e2-7.2.51.0.fw"
9509 void bnx2x_load_firmware(struct bnx2x_softc *sc)
9515 fwname = sc->devinfo.device_id == CHIP_NUM_57711
9516 ? FW_NAME_57711 : FW_NAME_57810;
9517 f = open(fwname, O_RDONLY);
9519 PMD_DRV_LOG(NOTICE, "Can't open firmware file");
9523 if (fstat(f, &st) < 0) {
9524 PMD_DRV_LOG(NOTICE, "Can't stat firmware file");
9529 sc->firmware = rte_zmalloc("bnx2x_fw", st.st_size, RTE_CACHE_LINE_SIZE);
9530 if (!sc->firmware) {
9531 PMD_DRV_LOG(NOTICE, "Can't allocate memory for firmware");
9536 if (read(f, sc->firmware, st.st_size) != st.st_size) {
9537 PMD_DRV_LOG(NOTICE, "Can't read firmware data");
9543 sc->fw_len = st.st_size;
9544 if (sc->fw_len < FW_HEADER_LEN) {
9545 PMD_DRV_LOG(NOTICE, "Invalid fw size: %" PRIu64, sc->fw_len);
9548 PMD_DRV_LOG(DEBUG, "fw_len = %" PRIu64, sc->fw_len);
9552 bnx2x_data_to_init_ops(uint8_t * data, struct raw_op *dst, uint32_t len)
9554 uint32_t *src = (uint32_t *) data;
9557 for (i = 0, j = 0; i < len / 8; ++i, j += 2) {
9558 tmp = rte_be_to_cpu_32(src[j]);
9559 dst[i].op = (tmp >> 24) & 0xFF;
9560 dst[i].offset = tmp & 0xFFFFFF;
9561 dst[i].raw_data = rte_be_to_cpu_32(src[j + 1]);
9566 bnx2x_data_to_init_offsets(uint8_t * data, uint16_t * dst, uint32_t len)
9568 uint16_t *src = (uint16_t *) data;
9571 for (i = 0; i < len / 2; ++i)
9572 dst[i] = rte_be_to_cpu_16(src[i]);
9575 static void bnx2x_data_to_init_data(uint8_t * data, uint32_t * dst, uint32_t len)
9577 uint32_t *src = (uint32_t *) data;
9580 for (i = 0; i < len / 4; ++i)
9581 dst[i] = rte_be_to_cpu_32(src[i]);
9584 static void bnx2x_data_to_iro_array(uint8_t * data, struct iro *dst, uint32_t len)
9586 uint32_t *src = (uint32_t *) data;
9589 for (i = 0, j = 0; i < len / sizeof(struct iro); ++i, ++j) {
9590 dst[i].base = rte_be_to_cpu_32(src[j++]);
9591 tmp = rte_be_to_cpu_32(src[j]);
9592 dst[i].m1 = (tmp >> 16) & 0xFFFF;
9593 dst[i].m2 = tmp & 0xFFFF;
9595 tmp = rte_be_to_cpu_32(src[j]);
9596 dst[i].m3 = (tmp >> 16) & 0xFFFF;
9597 dst[i].size = tmp & 0xFFFF;
9602 * Device attach function.
9604 * Allocates device resources, performs secondary chip identification, and
9605 * initializes driver instance variables. This function is called from driver
9606 * load after a successful probe.
9609 * 0 = Success, >0 = Failure
9611 int bnx2x_attach(struct bnx2x_softc *sc)
9615 PMD_DRV_LOG(DEBUG, "Starting attach...");
9617 rc = bnx2x_pci_get_caps(sc);
9619 PMD_DRV_LOG(NOTICE, "PCIe caps reading was failed");
9623 sc->state = BNX2X_STATE_CLOSED;
9625 pci_write_long(sc, PCICFG_GRC_ADDRESS, PCICFG_VENDOR_ID_OFFSET);
9627 sc->igu_base_addr = IS_VF(sc) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
9629 /* get PCI capabilites */
9630 bnx2x_probe_pci_caps(sc);
9632 if (sc->devinfo.pcie_msix_cap_reg != 0) {
9635 (sc->devinfo.pcie_msix_cap_reg + PCIR_MSIX_CTRL), &val,
9637 sc->igu_sb_cnt = (val & PCIM_MSIXCTRL_TABLE_SIZE) + 1;
9642 /* Init RTE stuff */
9646 /* Enable internal target-read (in case we are probed after PF
9647 * FLR). Must be done prior to any BAR read access. Only for
9650 if (!CHIP_IS_E1x(sc)) {
9651 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ,
9656 /* get device info and set params */
9657 if (bnx2x_get_device_info(sc) != 0) {
9658 PMD_DRV_LOG(NOTICE, "getting device info");
9662 /* get phy settings from shmem and 'and' against admin settings */
9663 bnx2x_get_phy_info(sc);
9665 /* Left mac of VF unfilled, PF should set it for VF */
9666 memset(sc->link_params.mac_addr, 0, ETHER_ADDR_LEN);
9671 /* set the default MTU (changed via ifconfig) */
9672 sc->mtu = ETHER_MTU;
9674 bnx2x_set_modes_bitmap(sc);
9676 /* need to reset chip if UNDI was active */
9677 if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
9680 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
9681 DRV_MSG_SEQ_NUMBER_MASK);
9682 bnx2x_prev_unload(sc);
9685 bnx2x_dcbx_set_state(sc, FALSE, BNX2X_DCBX_ENABLED_OFF);
9687 /* calculate qm_cid_count */
9688 sc->qm_cid_count = bnx2x_set_qm_cid_count(sc);
9691 bnx2x_init_multi_cos(sc);
9697 bnx2x_igu_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t segment,
9698 uint16_t index, uint8_t op, uint8_t update)
9700 uint32_t igu_addr = sc->igu_base_addr;
9701 igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
9702 bnx2x_igu_ack_sb_gen(sc, segment, index, op, update, igu_addr);
9706 bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t storm,
9707 uint16_t index, uint8_t op, uint8_t update)
9709 if (unlikely(sc->devinfo.int_block == INT_BLOCK_HC))
9710 bnx2x_hc_ack_sb(sc, igu_sb_id, storm, index, op, update);
9713 if (CHIP_INT_MODE_IS_BC(sc)) {
9715 } else if (igu_sb_id != sc->igu_dsb_id) {
9716 segment = IGU_SEG_ACCESS_DEF;
9717 } else if (storm == ATTENTION_ID) {
9718 segment = IGU_SEG_ACCESS_ATTN;
9720 segment = IGU_SEG_ACCESS_DEF;
9722 bnx2x_igu_ack_sb(sc, igu_sb_id, segment, index, op, update);
9727 bnx2x_igu_clear_sb_gen(struct bnx2x_softc *sc, uint8_t func, uint8_t idu_sb_id,
9730 uint32_t data, ctl, cnt = 100;
9731 uint32_t igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
9732 uint32_t igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
9733 uint32_t igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP +
9734 (idu_sb_id / 32) * 4;
9735 uint32_t sb_bit = 1 << (idu_sb_id % 32);
9736 uint32_t func_encode = func |
9737 (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
9738 uint32_t addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
9740 /* Not supported in BC mode */
9741 if (CHIP_INT_MODE_IS_BC(sc)) {
9745 data = ((IGU_USE_REGISTER_cstorm_type_0_sb_cleanup <<
9746 IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
9747 IGU_REGULAR_CLEANUP_SET | IGU_REGULAR_BCLEANUP);
9749 ctl = ((addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT) |
9750 (func_encode << IGU_CTRL_REG_FID_SHIFT) |
9751 (IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT));
9753 REG_WR(sc, igu_addr_data, data);
9757 PMD_DRV_LOG(DEBUG, "write 0x%08x to IGU(via GRC) addr 0x%x",
9759 REG_WR(sc, igu_addr_ctl, ctl);
9763 /* wait for clean up to finish */
9764 while (!(REG_RD(sc, igu_addr_ack) & sb_bit) && --cnt) {
9768 if (!(REG_RD(sc, igu_addr_ack) & sb_bit)) {
9770 "Unable to finish IGU cleanup: "
9771 "idu_sb_id %d offset %d bit %d (cnt %d)",
9772 idu_sb_id, idu_sb_id / 32, idu_sb_id % 32, cnt);
9776 static void bnx2x_igu_clear_sb(struct bnx2x_softc *sc, uint8_t idu_sb_id)
9778 bnx2x_igu_clear_sb_gen(sc, SC_FUNC(sc), idu_sb_id, TRUE /*PF*/);
9781 /*******************/
9782 /* ECORE CALLBACKS */
9783 /*******************/
9785 static void bnx2x_reset_common(struct bnx2x_softc *sc)
9787 uint32_t val = 0x1400;
9789 PMD_INIT_FUNC_TRACE();
9792 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR),
9795 if (CHIP_IS_E3(sc)) {
9796 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
9797 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
9800 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR), val);
9803 static void bnx2x_common_init_phy(struct bnx2x_softc *sc)
9805 uint32_t shmem_base[2];
9806 uint32_t shmem2_base[2];
9808 /* Avoid common init in case MFW supports LFA */
9809 if (SHMEM2_RD(sc, size) >
9810 (uint32_t) offsetof(struct shmem2_region,
9811 lfa_host_addr[SC_PORT(sc)])) {
9815 shmem_base[0] = sc->devinfo.shmem_base;
9816 shmem2_base[0] = sc->devinfo.shmem2_base;
9818 if (!CHIP_IS_E1x(sc)) {
9819 shmem_base[1] = SHMEM2_RD(sc, other_shmem_base_addr);
9820 shmem2_base[1] = SHMEM2_RD(sc, other_shmem2_base_addr);
9823 elink_common_init_phy(sc, shmem_base, shmem2_base,
9824 sc->devinfo.chip_id, 0);
9827 static void bnx2x_pf_disable(struct bnx2x_softc *sc)
9829 uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
9831 val &= ~IGU_PF_CONF_FUNC_EN;
9833 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
9834 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
9835 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 0);
9838 static void bnx2x_init_pxp(struct bnx2x_softc *sc)
9841 int r_order, w_order;
9843 devctl = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_CTL);
9845 w_order = ((devctl & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5);
9846 r_order = ((devctl & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12);
9848 ecore_init_pxp_arb(sc, r_order, w_order);
9851 static uint32_t bnx2x_get_pretend_reg(struct bnx2x_softc *sc)
9853 uint32_t base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9854 uint32_t stride = (PXP2_REG_PGL_PRETEND_FUNC_F1 - base);
9855 return base + (SC_ABS_FUNC(sc)) * stride;
9859 * Called only on E1H or E2.
9860 * When pretending to be PF, the pretend value is the function number 0..7.
9861 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
9864 static int bnx2x_pretend_func(struct bnx2x_softc *sc, uint16_t pretend_func_val)
9866 uint32_t pretend_reg;
9868 if (CHIP_IS_E1H(sc) && (pretend_func_val > E1H_FUNC_MAX))
9871 /* get my own pretend register */
9872 pretend_reg = bnx2x_get_pretend_reg(sc);
9873 REG_WR(sc, pretend_reg, pretend_func_val);
9874 REG_RD(sc, pretend_reg);
9878 static void bnx2x_setup_fan_failure_detection(struct bnx2x_softc *sc)
9885 val = (SHMEM_RD(sc, dev_info.shared_hw_config.config2) &
9886 SHARED_HW_CFG_FAN_FAILURE_MASK);
9888 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) {
9892 * The fan failure mechanism is usually related to the PHY type since
9893 * the power consumption of the board is affected by the PHY. Currently,
9894 * fan is required for most designs with SFX7101, BNX2X8727 and BNX2X8481.
9896 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) {
9897 for (port = PORT_0; port < PORT_MAX; port++) {
9898 is_required |= elink_fan_failure_det_req(sc,
9902 devinfo.shmem2_base,
9907 if (is_required == 0) {
9911 /* Fan failure is indicated by SPIO 5 */
9912 bnx2x_set_spio(sc, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
9914 /* set to active low mode */
9915 val = REG_RD(sc, MISC_REG_SPIO_INT);
9916 val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
9917 REG_WR(sc, MISC_REG_SPIO_INT, val);
9919 /* enable interrupt to signal the IGU */
9920 val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
9921 val |= MISC_SPIO_SPIO5;
9922 REG_WR(sc, MISC_REG_SPIO_EVENT_EN, val);
9925 static void bnx2x_enable_blocks_attention(struct bnx2x_softc *sc)
9929 REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0);
9930 if (!CHIP_IS_E1x(sc)) {
9931 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0x40);
9933 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0);
9935 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
9936 REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
9938 * mask read length error interrupts in brb for parser
9939 * (parsing unit and 'checksum and crc' unit)
9940 * these errors are legal (PU reads fixed length and CAC can cause
9941 * read length error on truncated packets)
9943 REG_WR(sc, BRB1_REG_BRB1_INT_MASK, 0xFC00);
9944 REG_WR(sc, QM_REG_QM_INT_MASK, 0);
9945 REG_WR(sc, TM_REG_TM_INT_MASK, 0);
9946 REG_WR(sc, XSDM_REG_XSDM_INT_MASK_0, 0);
9947 REG_WR(sc, XSDM_REG_XSDM_INT_MASK_1, 0);
9948 REG_WR(sc, XCM_REG_XCM_INT_MASK, 0);
9949 /* REG_WR(sc, XSEM_REG_XSEM_INT_MASK_0, 0); */
9950 /* REG_WR(sc, XSEM_REG_XSEM_INT_MASK_1, 0); */
9951 REG_WR(sc, USDM_REG_USDM_INT_MASK_0, 0);
9952 REG_WR(sc, USDM_REG_USDM_INT_MASK_1, 0);
9953 REG_WR(sc, UCM_REG_UCM_INT_MASK, 0);
9954 /* REG_WR(sc, USEM_REG_USEM_INT_MASK_0, 0); */
9955 /* REG_WR(sc, USEM_REG_USEM_INT_MASK_1, 0); */
9956 REG_WR(sc, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
9957 REG_WR(sc, CSDM_REG_CSDM_INT_MASK_0, 0);
9958 REG_WR(sc, CSDM_REG_CSDM_INT_MASK_1, 0);
9959 REG_WR(sc, CCM_REG_CCM_INT_MASK, 0);
9960 /* REG_WR(sc, CSEM_REG_CSEM_INT_MASK_0, 0); */
9961 /* REG_WR(sc, CSEM_REG_CSEM_INT_MASK_1, 0); */
9963 val = (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
9964 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
9965 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN);
9966 if (!CHIP_IS_E1x(sc)) {
9967 val |= (PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
9968 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED);
9970 REG_WR(sc, PXP2_REG_PXP2_INT_MASK_0, val);
9972 REG_WR(sc, TSDM_REG_TSDM_INT_MASK_0, 0);
9973 REG_WR(sc, TSDM_REG_TSDM_INT_MASK_1, 0);
9974 REG_WR(sc, TCM_REG_TCM_INT_MASK, 0);
9975 /* REG_WR(sc, TSEM_REG_TSEM_INT_MASK_0, 0); */
9977 if (!CHIP_IS_E1x(sc)) {
9978 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
9979 REG_WR(sc, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
9982 REG_WR(sc, CDU_REG_CDU_INT_MASK, 0);
9983 REG_WR(sc, DMAE_REG_DMAE_INT_MASK, 0);
9984 /* REG_WR(sc, MISC_REG_MISC_INT_MASK, 0); */
9985 REG_WR(sc, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
9989 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
9991 * @sc: driver handle
9993 static int bnx2x_init_hw_common(struct bnx2x_softc *sc)
9995 uint8_t abs_func_id;
9998 PMD_DRV_LOG(DEBUG, "starting common init for func %d", SC_ABS_FUNC(sc));
10001 * take the RESET lock to protect undi_unload flow from accessing
10002 * registers while we are resetting the chip
10004 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10006 bnx2x_reset_common(sc);
10008 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET), 0xffffffff);
10011 if (CHIP_IS_E3(sc)) {
10012 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
10013 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
10016 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET), val);
10018 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10020 ecore_init_block(sc, BLOCK_MISC, PHASE_COMMON);
10022 if (!CHIP_IS_E1x(sc)) {
10024 * 4-port mode or 2-port mode we need to turn off master-enable for
10025 * everyone. After that we turn it back on for self. So, we disregard
10026 * multi-function, and always disable all functions on the given path,
10027 * this means 0,2,4,6 for path 0 and 1,3,5,7 for path 1
10029 for (abs_func_id = SC_PATH(sc);
10030 abs_func_id < (E2_FUNC_MAX * 2); abs_func_id += 2) {
10031 if (abs_func_id == SC_ABS_FUNC(sc)) {
10033 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
10038 bnx2x_pretend_func(sc, abs_func_id);
10040 /* clear pf enable */
10041 bnx2x_pf_disable(sc);
10043 bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10047 ecore_init_block(sc, BLOCK_PXP, PHASE_COMMON);
10049 ecore_init_block(sc, BLOCK_PXP2, PHASE_COMMON);
10050 bnx2x_init_pxp(sc);
10052 #ifdef __BIG_ENDIAN
10053 REG_WR(sc, PXP2_REG_RQ_QM_ENDIAN_M, 1);
10054 REG_WR(sc, PXP2_REG_RQ_TM_ENDIAN_M, 1);
10055 REG_WR(sc, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
10056 REG_WR(sc, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
10057 REG_WR(sc, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
10058 /* make sure this value is 0 */
10059 REG_WR(sc, PXP2_REG_RQ_HC_ENDIAN_M, 0);
10061 //REG_WR(sc, PXP2_REG_RD_PBF_SWAP_MODE, 1);
10062 REG_WR(sc, PXP2_REG_RD_QM_SWAP_MODE, 1);
10063 REG_WR(sc, PXP2_REG_RD_TM_SWAP_MODE, 1);
10064 REG_WR(sc, PXP2_REG_RD_SRC_SWAP_MODE, 1);
10065 REG_WR(sc, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
10068 ecore_ilt_init_page_size(sc, INITOP_SET);
10070 if (CHIP_REV_IS_FPGA(sc) && CHIP_IS_E1H(sc)) {
10071 REG_WR(sc, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
10074 /* let the HW do it's magic... */
10077 /* finish PXP init */
10079 val = REG_RD(sc, PXP2_REG_RQ_CFG_DONE);
10081 PMD_DRV_LOG(NOTICE, "PXP2 CFG failed");
10084 val = REG_RD(sc, PXP2_REG_RD_INIT_DONE);
10086 PMD_DRV_LOG(NOTICE, "PXP2 RD_INIT failed");
10091 * Timer bug workaround for E2 only. We need to set the entire ILT to have
10092 * entries with value "0" and valid bit on. This needs to be done by the
10093 * first PF that is loaded in a path (i.e. common phase)
10095 if (!CHIP_IS_E1x(sc)) {
10097 * In E2 there is a bug in the timers block that can cause function 6 / 7
10098 * (i.e. vnic3) to start even if it is marked as "scan-off".
10099 * This occurs when a different function (func2,3) is being marked
10100 * as "scan-off". Real-life scenario for example: if a driver is being
10101 * load-unloaded while func6,7 are down. This will cause the timer to access
10102 * the ilt, translate to a logical address and send a request to read/write.
10103 * Since the ilt for the function that is down is not valid, this will cause
10104 * a translation error which is unrecoverable.
10105 * The Workaround is intended to make sure that when this happens nothing
10106 * fatal will occur. The workaround:
10107 * 1. First PF driver which loads on a path will:
10108 * a. After taking the chip out of reset, by using pretend,
10109 * it will write "0" to the following registers of
10111 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10112 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
10113 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
10114 * And for itself it will write '1' to
10115 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
10116 * dmae-operations (writing to pram for example.)
10117 * note: can be done for only function 6,7 but cleaner this
10119 * b. Write zero+valid to the entire ILT.
10120 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
10121 * VNIC3 (of that port). The range allocated will be the
10122 * entire ILT. This is needed to prevent ILT range error.
10123 * 2. Any PF driver load flow:
10124 * a. ILT update with the physical addresses of the allocated
10126 * b. Wait 20msec. - note that this timeout is needed to make
10127 * sure there are no requests in one of the PXP internal
10128 * queues with "old" ILT addresses.
10129 * c. PF enable in the PGLC.
10130 * d. Clear the was_error of the PF in the PGLC. (could have
10131 * occurred while driver was down)
10132 * e. PF enable in the CFC (WEAK + STRONG)
10133 * f. Timers scan enable
10134 * 3. PF driver unload flow:
10135 * a. Clear the Timers scan_en.
10136 * b. Polling for scan_on=0 for that PF.
10137 * c. Clear the PF enable bit in the PXP.
10138 * d. Clear the PF enable in the CFC (WEAK + STRONG)
10139 * e. Write zero+valid to all ILT entries (The valid bit must
10141 * f. If this is VNIC 3 of a port then also init
10142 * first_timers_ilt_entry to zero and last_timers_ilt_entry
10143 * to the last enrty in the ILT.
10146 * Currently the PF error in the PGLC is non recoverable.
10147 * In the future the there will be a recovery routine for this error.
10148 * Currently attention is masked.
10149 * Having an MCP lock on the load/unload process does not guarantee that
10150 * there is no Timer disable during Func6/7 enable. This is because the
10151 * Timers scan is currently being cleared by the MCP on FLR.
10152 * Step 2.d can be done only for PF6/7 and the driver can also check if
10153 * there is error before clearing it. But the flow above is simpler and
10155 * All ILT entries are written by zero+valid and not just PF6/7
10156 * ILT entries since in the future the ILT entries allocation for
10157 * PF-s might be dynamic.
10159 struct ilt_client_info ilt_cli;
10160 struct ecore_ilt ilt;
10162 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
10163 memset(&ilt, 0, sizeof(struct ecore_ilt));
10165 /* initialize dummy TM client */
10167 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
10168 ilt_cli.client_num = ILT_CLIENT_TM;
10171 * Step 1: set zeroes to all ilt page entries with valid bit on
10172 * Step 2: set the timers first/last ilt entry to point
10173 * to the entire range to prevent ILT range error for 3rd/4th
10174 * vnic (this code assumes existence of the vnic)
10176 * both steps performed by call to ecore_ilt_client_init_op()
10177 * with dummy TM client
10179 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
10180 * and his brother are split registers
10183 bnx2x_pretend_func(sc, (SC_PATH(sc) + 6));
10184 ecore_ilt_client_init_op_ilt(sc, &ilt, &ilt_cli, INITOP_CLEAR);
10185 bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10187 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
10188 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
10189 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
10192 REG_WR(sc, PXP2_REG_RQ_DISABLE_INPUTS, 0);
10193 REG_WR(sc, PXP2_REG_RD_DISABLE_INPUTS, 0);
10195 if (!CHIP_IS_E1x(sc)) {
10198 ecore_init_block(sc, BLOCK_PGLUE_B, PHASE_COMMON);
10199 ecore_init_block(sc, BLOCK_ATC, PHASE_COMMON);
10201 /* let the HW do it's magic... */
10204 val = REG_RD(sc, ATC_REG_ATC_INIT_DONE);
10205 } while (factor-- && (val != 1));
10208 PMD_DRV_LOG(NOTICE, "ATC_INIT failed");
10213 ecore_init_block(sc, BLOCK_DMAE, PHASE_COMMON);
10215 /* clean the DMAE memory */
10216 sc->dmae_ready = 1;
10217 ecore_init_fill(sc, TSEM_REG_PRAM, 0, 8);
10219 ecore_init_block(sc, BLOCK_TCM, PHASE_COMMON);
10221 ecore_init_block(sc, BLOCK_UCM, PHASE_COMMON);
10223 ecore_init_block(sc, BLOCK_CCM, PHASE_COMMON);
10225 ecore_init_block(sc, BLOCK_XCM, PHASE_COMMON);
10227 bnx2x_read_dmae(sc, XSEM_REG_PASSIVE_BUFFER, 3);
10228 bnx2x_read_dmae(sc, CSEM_REG_PASSIVE_BUFFER, 3);
10229 bnx2x_read_dmae(sc, TSEM_REG_PASSIVE_BUFFER, 3);
10230 bnx2x_read_dmae(sc, USEM_REG_PASSIVE_BUFFER, 3);
10232 ecore_init_block(sc, BLOCK_QM, PHASE_COMMON);
10234 /* QM queues pointers table */
10235 ecore_qm_init_ptr_table(sc, sc->qm_cid_count, INITOP_SET);
10237 /* soft reset pulse */
10238 REG_WR(sc, QM_REG_SOFT_RESET, 1);
10239 REG_WR(sc, QM_REG_SOFT_RESET, 0);
10241 if (CNIC_SUPPORT(sc))
10242 ecore_init_block(sc, BLOCK_TM, PHASE_COMMON);
10244 ecore_init_block(sc, BLOCK_DORQ, PHASE_COMMON);
10245 REG_WR(sc, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
10247 if (!CHIP_REV_IS_SLOW(sc)) {
10248 /* enable hw interrupt from doorbell Q */
10249 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
10252 ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON);
10254 ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON);
10255 REG_WR(sc, PRS_REG_A_PRSU_20, 0xf);
10256 REG_WR(sc, PRS_REG_E1HOV_MODE, sc->devinfo.mf_info.path_has_ovlan);
10258 if (!CHIP_IS_E1x(sc) && !CHIP_IS_E3B0(sc)) {
10259 if (IS_MF_AFEX(sc)) {
10261 * configure that AFEX and VLAN headers must be
10262 * received in AFEX mode
10264 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC, 0xE);
10265 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS, 0xA);
10266 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
10267 REG_WR(sc, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
10268 REG_WR(sc, PRS_REG_TAG_LEN_0, 0x4);
10271 * Bit-map indicating which L2 hdrs may appear
10272 * after the basic Ethernet header
10274 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC,
10275 sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10279 ecore_init_block(sc, BLOCK_TSDM, PHASE_COMMON);
10280 ecore_init_block(sc, BLOCK_CSDM, PHASE_COMMON);
10281 ecore_init_block(sc, BLOCK_USDM, PHASE_COMMON);
10282 ecore_init_block(sc, BLOCK_XSDM, PHASE_COMMON);
10284 if (!CHIP_IS_E1x(sc)) {
10285 /* reset VFC memories */
10286 REG_WR(sc, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10287 VFC_MEMORIES_RST_REG_CAM_RST |
10288 VFC_MEMORIES_RST_REG_RAM_RST);
10289 REG_WR(sc, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10290 VFC_MEMORIES_RST_REG_CAM_RST |
10291 VFC_MEMORIES_RST_REG_RAM_RST);
10296 ecore_init_block(sc, BLOCK_TSEM, PHASE_COMMON);
10297 ecore_init_block(sc, BLOCK_USEM, PHASE_COMMON);
10298 ecore_init_block(sc, BLOCK_CSEM, PHASE_COMMON);
10299 ecore_init_block(sc, BLOCK_XSEM, PHASE_COMMON);
10301 /* sync semi rtc */
10302 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x80000000);
10303 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x80000000);
10305 ecore_init_block(sc, BLOCK_UPB, PHASE_COMMON);
10306 ecore_init_block(sc, BLOCK_XPB, PHASE_COMMON);
10307 ecore_init_block(sc, BLOCK_PBF, PHASE_COMMON);
10309 if (!CHIP_IS_E1x(sc)) {
10310 if (IS_MF_AFEX(sc)) {
10312 * configure that AFEX and VLAN headers must be
10313 * sent in AFEX mode
10315 REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC, 0xE);
10316 REG_WR(sc, PBF_REG_MUST_HAVE_HDRS, 0xA);
10317 REG_WR(sc, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
10318 REG_WR(sc, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
10319 REG_WR(sc, PBF_REG_TAG_LEN_0, 0x4);
10321 REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC,
10322 sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10326 REG_WR(sc, SRC_REG_SOFT_RST, 1);
10328 ecore_init_block(sc, BLOCK_SRC, PHASE_COMMON);
10330 if (CNIC_SUPPORT(sc)) {
10331 REG_WR(sc, SRC_REG_KEYSEARCH_0, 0x63285672);
10332 REG_WR(sc, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
10333 REG_WR(sc, SRC_REG_KEYSEARCH_2, 0x223aef9b);
10334 REG_WR(sc, SRC_REG_KEYSEARCH_3, 0x26001e3a);
10335 REG_WR(sc, SRC_REG_KEYSEARCH_4, 0x7ae91116);
10336 REG_WR(sc, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
10337 REG_WR(sc, SRC_REG_KEYSEARCH_6, 0x298d8adf);
10338 REG_WR(sc, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
10339 REG_WR(sc, SRC_REG_KEYSEARCH_8, 0x1830f82f);
10340 REG_WR(sc, SRC_REG_KEYSEARCH_9, 0x01e46be7);
10342 REG_WR(sc, SRC_REG_SOFT_RST, 0);
10344 if (sizeof(union cdu_context) != 1024) {
10345 /* we currently assume that a context is 1024 bytes */
10346 PMD_DRV_LOG(NOTICE,
10347 "please adjust the size of cdu_context(%ld)",
10348 (long)sizeof(union cdu_context));
10351 ecore_init_block(sc, BLOCK_CDU, PHASE_COMMON);
10352 val = (4 << 24) + (0 << 12) + 1024;
10353 REG_WR(sc, CDU_REG_CDU_GLOBAL_PARAMS, val);
10355 ecore_init_block(sc, BLOCK_CFC, PHASE_COMMON);
10357 REG_WR(sc, CFC_REG_INIT_REG, 0x7FF);
10358 /* enable context validation interrupt from CFC */
10359 REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
10361 /* set the thresholds to prevent CFC/CDU race */
10362 REG_WR(sc, CFC_REG_DEBUG0, 0x20020000);
10363 ecore_init_block(sc, BLOCK_HC, PHASE_COMMON);
10365 if (!CHIP_IS_E1x(sc) && BNX2X_NOMCP(sc)) {
10366 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x36);
10369 ecore_init_block(sc, BLOCK_IGU, PHASE_COMMON);
10370 ecore_init_block(sc, BLOCK_MISC_AEU, PHASE_COMMON);
10372 /* Reset PCIE errors for debug */
10373 REG_WR(sc, 0x2814, 0xffffffff);
10374 REG_WR(sc, 0x3820, 0xffffffff);
10376 if (!CHIP_IS_E1x(sc)) {
10377 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
10378 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
10379 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
10380 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
10381 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
10382 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
10383 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
10384 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
10385 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
10386 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
10387 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
10390 ecore_init_block(sc, BLOCK_NIG, PHASE_COMMON);
10392 /* in E3 this done in per-port section */
10393 if (!CHIP_IS_E3(sc))
10394 REG_WR(sc, NIG_REG_LLH_MF_MODE, IS_MF(sc));
10396 if (CHIP_IS_E1H(sc)) {
10397 /* not applicable for E2 (and above ...) */
10398 REG_WR(sc, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(sc));
10401 if (CHIP_REV_IS_SLOW(sc)) {
10405 /* finish CFC init */
10406 val = reg_poll(sc, CFC_REG_LL_INIT_DONE, 1, 100, 10);
10408 PMD_DRV_LOG(NOTICE, "CFC LL_INIT failed");
10411 val = reg_poll(sc, CFC_REG_AC_INIT_DONE, 1, 100, 10);
10413 PMD_DRV_LOG(NOTICE, "CFC AC_INIT failed");
10416 val = reg_poll(sc, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
10418 PMD_DRV_LOG(NOTICE, "CFC CAM_INIT failed");
10421 REG_WR(sc, CFC_REG_DEBUG0, 0);
10423 bnx2x_setup_fan_failure_detection(sc);
10425 /* clear PXP2 attentions */
10426 REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
10428 bnx2x_enable_blocks_attention(sc);
10430 if (!CHIP_REV_IS_SLOW(sc)) {
10431 ecore_enable_blocks_parity(sc);
10434 if (!BNX2X_NOMCP(sc)) {
10435 if (CHIP_IS_E1x(sc)) {
10436 bnx2x_common_init_phy(sc);
10444 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
10446 * @sc: driver handle
10448 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc)
10450 int rc = bnx2x_init_hw_common(sc);
10456 /* In E2 2-PORT mode, same ext phy is used for the two paths */
10457 if (!BNX2X_NOMCP(sc)) {
10458 bnx2x_common_init_phy(sc);
10464 static int bnx2x_init_hw_port(struct bnx2x_softc *sc)
10466 int port = SC_PORT(sc);
10467 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
10468 uint32_t low, high;
10471 PMD_DRV_LOG(DEBUG, "starting port init for port %d", port);
10473 REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
10475 ecore_init_block(sc, BLOCK_MISC, init_phase);
10476 ecore_init_block(sc, BLOCK_PXP, init_phase);
10477 ecore_init_block(sc, BLOCK_PXP2, init_phase);
10480 * Timers bug workaround: disables the pf_master bit in pglue at
10481 * common phase, we need to enable it here before any dmae access are
10482 * attempted. Therefore we manually added the enable-master to the
10483 * port phase (it also happens in the function phase)
10485 if (!CHIP_IS_E1x(sc)) {
10486 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
10489 ecore_init_block(sc, BLOCK_ATC, init_phase);
10490 ecore_init_block(sc, BLOCK_DMAE, init_phase);
10491 ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
10492 ecore_init_block(sc, BLOCK_QM, init_phase);
10494 ecore_init_block(sc, BLOCK_TCM, init_phase);
10495 ecore_init_block(sc, BLOCK_UCM, init_phase);
10496 ecore_init_block(sc, BLOCK_CCM, init_phase);
10497 ecore_init_block(sc, BLOCK_XCM, init_phase);
10499 /* QM cid (connection) count */
10500 ecore_qm_init_cid_count(sc, sc->qm_cid_count, INITOP_SET);
10502 if (CNIC_SUPPORT(sc)) {
10503 ecore_init_block(sc, BLOCK_TM, init_phase);
10504 REG_WR(sc, TM_REG_LIN0_SCAN_TIME + port * 4, 20);
10505 REG_WR(sc, TM_REG_LIN0_MAX_ACTIVE_CID + port * 4, 31);
10508 ecore_init_block(sc, BLOCK_DORQ, init_phase);
10510 ecore_init_block(sc, BLOCK_BRB1, init_phase);
10512 if (CHIP_IS_E1H(sc)) {
10514 low = (BNX2X_ONE_PORT(sc) ? 160 : 246);
10515 } else if (sc->mtu > 4096) {
10516 if (BNX2X_ONE_PORT(sc)) {
10520 /* (24*1024 + val*4)/256 */
10521 low = (96 + (val / 64) + ((val % 64) ? 1 : 0));
10524 low = (BNX2X_ONE_PORT(sc) ? 80 : 160);
10526 high = (low + 56); /* 14*1024/256 */
10527 REG_WR(sc, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port * 4, low);
10528 REG_WR(sc, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port * 4, high);
10531 if (CHIP_IS_MODE_4_PORT(sc)) {
10532 REG_WR(sc, SC_PORT(sc) ?
10533 BRB1_REG_MAC_GUARANTIED_1 :
10534 BRB1_REG_MAC_GUARANTIED_0, 40);
10537 ecore_init_block(sc, BLOCK_PRS, init_phase);
10538 if (CHIP_IS_E3B0(sc)) {
10539 if (IS_MF_AFEX(sc)) {
10540 /* configure headers for AFEX mode */
10542 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_1,
10544 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_1,
10546 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_1, 0xA);
10548 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10550 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_0,
10552 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
10555 /* Ovlan exists only if we are in multi-function +
10556 * switch-dependent mode, in switch-independent there
10557 * is no ovlan headers
10559 REG_WR(sc, SC_PORT(sc) ?
10560 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
10561 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10562 (sc->devinfo.mf_info.path_has_ovlan ? 7 : 6));
10566 ecore_init_block(sc, BLOCK_TSDM, init_phase);
10567 ecore_init_block(sc, BLOCK_CSDM, init_phase);
10568 ecore_init_block(sc, BLOCK_USDM, init_phase);
10569 ecore_init_block(sc, BLOCK_XSDM, init_phase);
10571 ecore_init_block(sc, BLOCK_TSEM, init_phase);
10572 ecore_init_block(sc, BLOCK_USEM, init_phase);
10573 ecore_init_block(sc, BLOCK_CSEM, init_phase);
10574 ecore_init_block(sc, BLOCK_XSEM, init_phase);
10576 ecore_init_block(sc, BLOCK_UPB, init_phase);
10577 ecore_init_block(sc, BLOCK_XPB, init_phase);
10579 ecore_init_block(sc, BLOCK_PBF, init_phase);
10581 if (CHIP_IS_E1x(sc)) {
10582 /* configure PBF to work without PAUSE mtu 9000 */
10583 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 0);
10585 /* update threshold */
10586 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, (9040 / 16));
10587 /* update init credit */
10588 REG_WR(sc, PBF_REG_P0_INIT_CRD + port * 4,
10589 (9040 / 16) + 553 - 22);
10591 /* probe changes */
10592 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 1);
10594 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0);
10597 if (CNIC_SUPPORT(sc)) {
10598 ecore_init_block(sc, BLOCK_SRC, init_phase);
10601 ecore_init_block(sc, BLOCK_CDU, init_phase);
10602 ecore_init_block(sc, BLOCK_CFC, init_phase);
10603 ecore_init_block(sc, BLOCK_HC, init_phase);
10604 ecore_init_block(sc, BLOCK_IGU, init_phase);
10605 ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
10606 /* init aeu_mask_attn_func_0/1:
10607 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
10608 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
10609 * bits 4-7 are used for "per vn group attention" */
10610 val = IS_MF(sc) ? 0xF7 : 0x7;
10612 REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, val);
10614 ecore_init_block(sc, BLOCK_NIG, init_phase);
10616 if (!CHIP_IS_E1x(sc)) {
10617 /* Bit-map indicating which L2 hdrs may appear after the
10618 * basic Ethernet header
10620 if (IS_MF_AFEX(sc)) {
10621 REG_WR(sc, SC_PORT(sc) ?
10622 NIG_REG_P1_HDRS_AFTER_BASIC :
10623 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
10625 REG_WR(sc, SC_PORT(sc) ?
10626 NIG_REG_P1_HDRS_AFTER_BASIC :
10627 NIG_REG_P0_HDRS_AFTER_BASIC,
10628 IS_MF_SD(sc) ? 7 : 6);
10631 if (CHIP_IS_E3(sc)) {
10632 REG_WR(sc, SC_PORT(sc) ?
10633 NIG_REG_LLH1_MF_MODE :
10634 NIG_REG_LLH_MF_MODE, IS_MF(sc));
10637 if (!CHIP_IS_E3(sc)) {
10638 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1);
10641 /* 0x2 disable mf_ov, 0x1 enable */
10642 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port * 4,
10643 (IS_MF_SD(sc) ? 0x1 : 0x2));
10645 if (!CHIP_IS_E1x(sc)) {
10647 switch (sc->devinfo.mf_info.mf_mode) {
10648 case MULTI_FUNCTION_SD:
10651 case MULTI_FUNCTION_SI:
10652 case MULTI_FUNCTION_AFEX:
10657 REG_WR(sc, (SC_PORT(sc) ? NIG_REG_LLH1_CLS_TYPE :
10658 NIG_REG_LLH0_CLS_TYPE), val);
10660 REG_WR(sc, NIG_REG_LLFC_ENABLE_0 + port * 4, 0);
10661 REG_WR(sc, NIG_REG_LLFC_OUT_EN_0 + port * 4, 0);
10662 REG_WR(sc, NIG_REG_PAUSE_ENABLE_0 + port * 4, 1);
10664 /* If SPIO5 is set to generate interrupts, enable it for this port */
10665 val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
10666 if (val & MISC_SPIO_SPIO5) {
10667 uint32_t reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
10668 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
10669 val = REG_RD(sc, reg_addr);
10670 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
10671 REG_WR(sc, reg_addr, val);
10678 bnx2x_flr_clnup_reg_poll(struct bnx2x_softc *sc, uint32_t reg,
10679 uint32_t expected, uint32_t poll_count)
10681 uint32_t cur_cnt = poll_count;
10684 while ((val = REG_RD(sc, reg)) != expected && cur_cnt--) {
10685 DELAY(FLR_WAIT_INTERVAL);
10692 bnx2x_flr_clnup_poll_hw_counter(struct bnx2x_softc *sc, uint32_t reg,
10693 __rte_unused const char *msg, uint32_t poll_cnt)
10695 uint32_t val = bnx2x_flr_clnup_reg_poll(sc, reg, 0, poll_cnt);
10698 PMD_DRV_LOG(NOTICE, "%s usage count=%d", msg, val);
10705 /* Common routines with VF FLR cleanup */
10706 static uint32_t bnx2x_flr_clnup_poll_count(struct bnx2x_softc *sc)
10708 /* adjust polling timeout */
10709 if (CHIP_REV_IS_EMUL(sc)) {
10710 return FLR_POLL_CNT * 2000;
10713 if (CHIP_REV_IS_FPGA(sc)) {
10714 return FLR_POLL_CNT * 120;
10717 return FLR_POLL_CNT;
10720 static int bnx2x_poll_hw_usage_counters(struct bnx2x_softc *sc, uint32_t poll_cnt)
10722 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
10723 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10724 CFC_REG_NUM_LCIDS_INSIDE_PF,
10725 "CFC PF usage counter timed out",
10730 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
10731 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10732 DORQ_REG_PF_USAGE_CNT,
10733 "DQ PF usage counter timed out",
10738 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
10739 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10740 QM_REG_PF_USG_CNT_0 + 4 * SC_FUNC(sc),
10741 "QM PF usage counter timed out",
10746 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
10747 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10748 TM_REG_LIN0_VNIC_UC + 4 * SC_PORT(sc),
10749 "Timers VNIC usage counter timed out",
10754 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10755 TM_REG_LIN0_NUM_SCANS +
10757 "Timers NUM_SCANS usage counter timed out",
10762 /* Wait DMAE PF usage counter to zero */
10763 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10764 dmae_reg_go_c[INIT_DMAE_C(sc)],
10765 "DMAE dommand register timed out",
10773 #define OP_GEN_PARAM(param) \
10774 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
10775 #define OP_GEN_TYPE(type) \
10776 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
10777 #define OP_GEN_AGG_VECT(index) \
10778 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
10781 bnx2x_send_final_clnup(struct bnx2x_softc *sc, uint8_t clnup_func,
10784 uint32_t op_gen_command = 0;
10785 uint32_t comp_addr = (BAR_CSTRORM_INTMEM +
10786 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func));
10789 if (REG_RD(sc, comp_addr)) {
10790 PMD_DRV_LOG(NOTICE,
10791 "Cleanup complete was not 0 before sending");
10795 op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
10796 op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
10797 op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
10798 op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
10800 REG_WR(sc, XSDM_REG_OPERATION_GEN, op_gen_command);
10802 if (bnx2x_flr_clnup_reg_poll(sc, comp_addr, 1, poll_cnt) != 1) {
10803 PMD_DRV_LOG(NOTICE, "FW final cleanup did not succeed");
10804 PMD_DRV_LOG(DEBUG, "At timeout completion address contained %x",
10805 (REG_RD(sc, comp_addr)));
10806 rte_panic("FLR cleanup failed");
10810 /* Zero completion for nxt FLR */
10811 REG_WR(sc, comp_addr, 0);
10817 bnx2x_pbf_pN_buf_flushed(struct bnx2x_softc *sc, struct pbf_pN_buf_regs *regs,
10818 uint32_t poll_count)
10820 uint32_t init_crd, crd, crd_start, crd_freed, crd_freed_start;
10821 uint32_t cur_cnt = poll_count;
10823 crd_freed = crd_freed_start = REG_RD(sc, regs->crd_freed);
10824 crd = crd_start = REG_RD(sc, regs->crd);
10825 init_crd = REG_RD(sc, regs->init_crd);
10827 while ((crd != init_crd) &&
10828 ((uint32_t) ((int32_t) crd_freed - (int32_t) crd_freed_start) <
10829 (init_crd - crd_start))) {
10831 DELAY(FLR_WAIT_INTERVAL);
10832 crd = REG_RD(sc, regs->crd);
10833 crd_freed = REG_RD(sc, regs->crd_freed);
10841 bnx2x_pbf_pN_cmd_flushed(struct bnx2x_softc *sc, struct pbf_pN_cmd_regs *regs,
10842 uint32_t poll_count)
10844 uint32_t occup, to_free, freed, freed_start;
10845 uint32_t cur_cnt = poll_count;
10847 occup = to_free = REG_RD(sc, regs->lines_occup);
10848 freed = freed_start = REG_RD(sc, regs->lines_freed);
10851 ((uint32_t) ((int32_t) freed - (int32_t) freed_start) <
10854 DELAY(FLR_WAIT_INTERVAL);
10855 occup = REG_RD(sc, regs->lines_occup);
10856 freed = REG_RD(sc, regs->lines_freed);
10863 static void bnx2x_tx_hw_flushed(struct bnx2x_softc *sc, uint32_t poll_count)
10865 struct pbf_pN_cmd_regs cmd_regs[] = {
10866 {0, (CHIP_IS_E3B0(sc)) ?
10867 PBF_REG_TQ_OCCUPANCY_Q0 : PBF_REG_P0_TQ_OCCUPANCY,
10868 (CHIP_IS_E3B0(sc)) ?
10869 PBF_REG_TQ_LINES_FREED_CNT_Q0 : PBF_REG_P0_TQ_LINES_FREED_CNT},
10870 {1, (CHIP_IS_E3B0(sc)) ?
10871 PBF_REG_TQ_OCCUPANCY_Q1 : PBF_REG_P1_TQ_OCCUPANCY,
10872 (CHIP_IS_E3B0(sc)) ?
10873 PBF_REG_TQ_LINES_FREED_CNT_Q1 : PBF_REG_P1_TQ_LINES_FREED_CNT},
10874 {4, (CHIP_IS_E3B0(sc)) ?
10875 PBF_REG_TQ_OCCUPANCY_LB_Q : PBF_REG_P4_TQ_OCCUPANCY,
10876 (CHIP_IS_E3B0(sc)) ?
10877 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
10878 PBF_REG_P4_TQ_LINES_FREED_CNT}
10881 struct pbf_pN_buf_regs buf_regs[] = {
10882 {0, (CHIP_IS_E3B0(sc)) ?
10883 PBF_REG_INIT_CRD_Q0 : PBF_REG_P0_INIT_CRD,
10884 (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q0 : PBF_REG_P0_CREDIT,
10885 (CHIP_IS_E3B0(sc)) ?
10886 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
10887 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
10888 {1, (CHIP_IS_E3B0(sc)) ?
10889 PBF_REG_INIT_CRD_Q1 : PBF_REG_P1_INIT_CRD,
10890 (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q1 : PBF_REG_P1_CREDIT,
10891 (CHIP_IS_E3B0(sc)) ?
10892 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
10893 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
10894 {4, (CHIP_IS_E3B0(sc)) ?
10895 PBF_REG_INIT_CRD_LB_Q : PBF_REG_P4_INIT_CRD,
10896 (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_LB_Q : PBF_REG_P4_CREDIT,
10897 (CHIP_IS_E3B0(sc)) ?
10898 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
10899 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
10904 /* Verify the command queues are flushed P0, P1, P4 */
10905 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) {
10906 bnx2x_pbf_pN_cmd_flushed(sc, &cmd_regs[i], poll_count);
10909 /* Verify the transmission buffers are flushed P0, P1, P4 */
10910 for (i = 0; i < ARRAY_SIZE(buf_regs); i++) {
10911 bnx2x_pbf_pN_buf_flushed(sc, &buf_regs[i], poll_count);
10915 static void bnx2x_hw_enable_status(struct bnx2x_softc *sc)
10917 __rte_unused uint32_t val;
10919 val = REG_RD(sc, CFC_REG_WEAK_ENABLE_PF);
10920 PMD_DRV_LOG(DEBUG, "CFC_REG_WEAK_ENABLE_PF is 0x%x", val);
10922 val = REG_RD(sc, PBF_REG_DISABLE_PF);
10923 PMD_DRV_LOG(DEBUG, "PBF_REG_DISABLE_PF is 0x%x", val);
10925 val = REG_RD(sc, IGU_REG_PCI_PF_MSI_EN);
10926 PMD_DRV_LOG(DEBUG, "IGU_REG_PCI_PF_MSI_EN is 0x%x", val);
10928 val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_EN);
10929 PMD_DRV_LOG(DEBUG, "IGU_REG_PCI_PF_MSIX_EN is 0x%x", val);
10931 val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
10932 PMD_DRV_LOG(DEBUG, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x", val);
10934 val = REG_RD(sc, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
10935 PMD_DRV_LOG(DEBUG, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x", val);
10937 val = REG_RD(sc, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
10938 PMD_DRV_LOG(DEBUG, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x", val);
10940 val = REG_RD(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
10941 PMD_DRV_LOG(DEBUG, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x",
10946 * bnx2x_pf_flr_clnup
10947 * a. re-enable target read on the PF
10948 * b. poll cfc per function usgae counter
10949 * c. poll the qm perfunction usage counter
10950 * d. poll the tm per function usage counter
10951 * e. poll the tm per function scan-done indication
10952 * f. clear the dmae channel associated wit hthe PF
10953 * g. zero the igu 'trailing edge' and 'leading edge' regs (attentions)
10954 * h. call the common flr cleanup code with -1 (pf indication)
10956 static int bnx2x_pf_flr_clnup(struct bnx2x_softc *sc)
10958 uint32_t poll_cnt = bnx2x_flr_clnup_poll_count(sc);
10960 /* Re-enable PF target read access */
10961 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
10963 /* Poll HW usage counters */
10964 if (bnx2x_poll_hw_usage_counters(sc, poll_cnt)) {
10968 /* Zero the igu 'trailing edge' and 'leading edge' */
10970 /* Send the FW cleanup command */
10971 if (bnx2x_send_final_clnup(sc, (uint8_t) SC_FUNC(sc), poll_cnt)) {
10977 /* Verify TX hw is flushed */
10978 bnx2x_tx_hw_flushed(sc, poll_cnt);
10980 /* Wait 100ms (not adjusted according to platform) */
10983 /* Verify no pending pci transactions */
10984 if (bnx2x_is_pcie_pending(sc)) {
10985 PMD_DRV_LOG(NOTICE, "PCIE Transactions still pending");
10989 bnx2x_hw_enable_status(sc);
10992 * Master enable - Due to WB DMAE writes performed before this
10993 * register is re-initialized as part of the regular function init
10995 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11000 static int bnx2x_init_hw_func(struct bnx2x_softc *sc)
11002 int port = SC_PORT(sc);
11003 int func = SC_FUNC(sc);
11004 int init_phase = PHASE_PF0 + func;
11005 struct ecore_ilt *ilt = sc->ilt;
11006 uint16_t cdu_ilt_start;
11007 uint32_t addr, val;
11008 uint32_t main_mem_base, main_mem_size, main_mem_prty_clr;
11009 int main_mem_width, rc;
11012 PMD_DRV_LOG(DEBUG, "starting func init for func %d", func);
11015 if (!CHIP_IS_E1x(sc)) {
11016 rc = bnx2x_pf_flr_clnup(sc);
11018 PMD_DRV_LOG(NOTICE, "FLR cleanup failed!");
11023 /* set MSI reconfigure capability */
11024 if (sc->devinfo.int_block == INT_BLOCK_HC) {
11025 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
11026 val = REG_RD(sc, addr);
11027 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
11028 REG_WR(sc, addr, val);
11031 ecore_init_block(sc, BLOCK_PXP, init_phase);
11032 ecore_init_block(sc, BLOCK_PXP2, init_phase);
11035 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
11037 for (i = 0; i < L2_ILT_LINES(sc); i++) {
11038 ilt->lines[cdu_ilt_start + i].page = sc->context[i].vcxt;
11039 ilt->lines[cdu_ilt_start + i].page_mapping =
11040 (rte_iova_t)sc->context[i].vcxt_dma.paddr;
11041 ilt->lines[cdu_ilt_start + i].size = sc->context[i].size;
11043 ecore_ilt_init_op(sc, INITOP_SET);
11045 REG_WR(sc, PRS_REG_NIC_MODE, 1);
11047 if (!CHIP_IS_E1x(sc)) {
11048 uint32_t pf_conf = IGU_PF_CONF_FUNC_EN;
11050 /* Turn on a single ISR mode in IGU if driver is going to use
11053 if ((sc->interrupt_mode != INTR_MODE_MSIX)
11054 || (sc->interrupt_mode != INTR_MODE_SINGLE_MSIX)) {
11055 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
11059 * Timers workaround bug: function init part.
11060 * Need to wait 20msec after initializing ILT,
11061 * needed to make sure there are no requests in
11062 * one of the PXP internal queues with "old" ILT addresses
11067 * Master enable - Due to WB DMAE writes performed before this
11068 * register is re-initialized as part of the regular function
11071 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11072 /* Enable the function in IGU */
11073 REG_WR(sc, IGU_REG_PF_CONFIGURATION, pf_conf);
11076 sc->dmae_ready = 1;
11078 ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
11080 if (!CHIP_IS_E1x(sc))
11081 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
11083 ecore_init_block(sc, BLOCK_ATC, init_phase);
11084 ecore_init_block(sc, BLOCK_DMAE, init_phase);
11085 ecore_init_block(sc, BLOCK_NIG, init_phase);
11086 ecore_init_block(sc, BLOCK_SRC, init_phase);
11087 ecore_init_block(sc, BLOCK_MISC, init_phase);
11088 ecore_init_block(sc, BLOCK_TCM, init_phase);
11089 ecore_init_block(sc, BLOCK_UCM, init_phase);
11090 ecore_init_block(sc, BLOCK_CCM, init_phase);
11091 ecore_init_block(sc, BLOCK_XCM, init_phase);
11092 ecore_init_block(sc, BLOCK_TSEM, init_phase);
11093 ecore_init_block(sc, BLOCK_USEM, init_phase);
11094 ecore_init_block(sc, BLOCK_CSEM, init_phase);
11095 ecore_init_block(sc, BLOCK_XSEM, init_phase);
11097 if (!CHIP_IS_E1x(sc))
11098 REG_WR(sc, QM_REG_PF_EN, 1);
11100 if (!CHIP_IS_E1x(sc)) {
11101 REG_WR(sc, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11102 REG_WR(sc, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11103 REG_WR(sc, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11104 REG_WR(sc, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11106 ecore_init_block(sc, BLOCK_QM, init_phase);
11108 ecore_init_block(sc, BLOCK_TM, init_phase);
11109 ecore_init_block(sc, BLOCK_DORQ, init_phase);
11111 ecore_init_block(sc, BLOCK_BRB1, init_phase);
11112 ecore_init_block(sc, BLOCK_PRS, init_phase);
11113 ecore_init_block(sc, BLOCK_TSDM, init_phase);
11114 ecore_init_block(sc, BLOCK_CSDM, init_phase);
11115 ecore_init_block(sc, BLOCK_USDM, init_phase);
11116 ecore_init_block(sc, BLOCK_XSDM, init_phase);
11117 ecore_init_block(sc, BLOCK_UPB, init_phase);
11118 ecore_init_block(sc, BLOCK_XPB, init_phase);
11119 ecore_init_block(sc, BLOCK_PBF, init_phase);
11120 if (!CHIP_IS_E1x(sc))
11121 REG_WR(sc, PBF_REG_DISABLE_PF, 0);
11123 ecore_init_block(sc, BLOCK_CDU, init_phase);
11125 ecore_init_block(sc, BLOCK_CFC, init_phase);
11127 if (!CHIP_IS_E1x(sc))
11128 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 1);
11131 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
11132 REG_WR(sc, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8, OVLAN(sc));
11135 ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
11137 /* HC init per function */
11138 if (sc->devinfo.int_block == INT_BLOCK_HC) {
11139 if (CHIP_IS_E1H(sc)) {
11140 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11142 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11143 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11145 ecore_init_block(sc, BLOCK_HC, init_phase);
11148 uint32_t num_segs, sb_idx, prod_offset;
11150 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11152 if (!CHIP_IS_E1x(sc)) {
11153 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11154 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11157 ecore_init_block(sc, BLOCK_IGU, init_phase);
11159 if (!CHIP_IS_E1x(sc)) {
11163 * E2 mode: address 0-135 match to the mapping memory;
11164 * 136 - PF0 default prod; 137 - PF1 default prod;
11165 * 138 - PF2 default prod; 139 - PF3 default prod;
11166 * 140 - PF0 attn prod; 141 - PF1 attn prod;
11167 * 142 - PF2 attn prod; 143 - PF3 attn prod;
11168 * 144-147 reserved.
11170 * E1.5 mode - In backward compatible mode;
11171 * for non default SB; each even line in the memory
11172 * holds the U producer and each odd line hold
11173 * the C producer. The first 128 producers are for
11174 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
11175 * producers are for the DSB for each PF.
11176 * Each PF has five segments: (the order inside each
11177 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
11178 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
11179 * 144-147 attn prods;
11181 /* non-default-status-blocks */
11182 num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11183 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
11184 for (sb_idx = 0; sb_idx < sc->igu_sb_cnt; sb_idx++) {
11185 prod_offset = (sc->igu_base_sb + sb_idx) *
11188 for (i = 0; i < num_segs; i++) {
11189 addr = IGU_REG_PROD_CONS_MEMORY +
11190 (prod_offset + i) * 4;
11191 REG_WR(sc, addr, 0);
11193 /* send consumer update with value 0 */
11194 bnx2x_ack_sb(sc, sc->igu_base_sb + sb_idx,
11195 USTORM_ID, 0, IGU_INT_NOP, 1);
11196 bnx2x_igu_clear_sb(sc, sc->igu_base_sb + sb_idx);
11199 /* default-status-blocks */
11200 num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11201 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
11203 if (CHIP_IS_MODE_4_PORT(sc))
11204 dsb_idx = SC_FUNC(sc);
11206 dsb_idx = SC_VN(sc);
11208 prod_offset = (CHIP_INT_MODE_IS_BC(sc) ?
11209 IGU_BC_BASE_DSB_PROD + dsb_idx :
11210 IGU_NORM_BASE_DSB_PROD + dsb_idx);
11213 * igu prods come in chunks of E1HVN_MAX (4) -
11214 * does not matters what is the current chip mode
11216 for (i = 0; i < (num_segs * E1HVN_MAX); i += E1HVN_MAX) {
11217 addr = IGU_REG_PROD_CONS_MEMORY +
11218 (prod_offset + i) * 4;
11219 REG_WR(sc, addr, 0);
11221 /* send consumer update with 0 */
11222 if (CHIP_INT_MODE_IS_BC(sc)) {
11223 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11224 USTORM_ID, 0, IGU_INT_NOP, 1);
11225 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11226 CSTORM_ID, 0, IGU_INT_NOP, 1);
11227 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11228 XSTORM_ID, 0, IGU_INT_NOP, 1);
11229 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11230 TSTORM_ID, 0, IGU_INT_NOP, 1);
11231 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11232 ATTENTION_ID, 0, IGU_INT_NOP, 1);
11234 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11235 USTORM_ID, 0, IGU_INT_NOP, 1);
11236 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11237 ATTENTION_ID, 0, IGU_INT_NOP, 1);
11239 bnx2x_igu_clear_sb(sc, sc->igu_dsb_id);
11241 /* !!! these should become driver const once
11242 rf-tool supports split-68 const */
11243 REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
11244 REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
11245 REG_WR(sc, IGU_REG_SB_MASK_LSB, 0);
11246 REG_WR(sc, IGU_REG_SB_MASK_MSB, 0);
11247 REG_WR(sc, IGU_REG_PBA_STATUS_LSB, 0);
11248 REG_WR(sc, IGU_REG_PBA_STATUS_MSB, 0);
11252 /* Reset PCIE errors for debug */
11253 REG_WR(sc, 0x2114, 0xffffffff);
11254 REG_WR(sc, 0x2120, 0xffffffff);
11256 if (CHIP_IS_E1x(sc)) {
11257 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords */
11258 main_mem_base = HC_REG_MAIN_MEMORY +
11259 SC_PORT(sc) * (main_mem_size * 4);
11260 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
11261 main_mem_width = 8;
11263 val = REG_RD(sc, main_mem_prty_clr);
11266 "Parity errors in HC block during function init (0x%x)!",
11270 /* Clear "false" parity errors in MSI-X table */
11271 for (i = main_mem_base;
11272 i < main_mem_base + main_mem_size * 4;
11273 i += main_mem_width) {
11274 bnx2x_read_dmae(sc, i, main_mem_width / 4);
11275 bnx2x_write_dmae(sc, BNX2X_SP_MAPPING(sc, wb_data),
11276 i, main_mem_width / 4);
11278 /* Clear HC parity attention */
11279 REG_RD(sc, main_mem_prty_clr);
11282 /* Enable STORMs SP logging */
11283 REG_WR8(sc, BAR_USTRORM_INTMEM +
11284 USTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11285 REG_WR8(sc, BAR_TSTRORM_INTMEM +
11286 TSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11287 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11288 CSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11289 REG_WR8(sc, BAR_XSTRORM_INTMEM +
11290 XSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11292 elink_phy_probe(&sc->link_params);
11297 static void bnx2x_link_reset(struct bnx2x_softc *sc)
11299 if (!BNX2X_NOMCP(sc)) {
11300 elink_lfa_reset(&sc->link_params, &sc->link_vars);
11302 if (!CHIP_REV_IS_SLOW(sc)) {
11303 PMD_DRV_LOG(WARNING,
11304 "Bootcode is missing - cannot reset link");
11309 static void bnx2x_reset_port(struct bnx2x_softc *sc)
11311 int port = SC_PORT(sc);
11314 /* reset physical Link */
11315 bnx2x_link_reset(sc);
11317 REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
11319 /* Do not rcv packets to BRB */
11320 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + port * 4, 0x0);
11321 /* Do not direct rcv packets that are not for MCP to the BRB */
11322 REG_WR(sc, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
11323 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
11325 /* Configure AEU */
11326 REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, 0);
11330 /* Check for BRB port occupancy */
11331 val = REG_RD(sc, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port * 4);
11334 "BRB1 is not empty, %d blocks are occupied", val);
11338 static void bnx2x_ilt_wr(struct bnx2x_softc *sc, uint32_t index, rte_iova_t addr)
11341 uint32_t wb_write[2];
11343 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index * 8;
11345 wb_write[0] = ONCHIP_ADDR1(addr);
11346 wb_write[1] = ONCHIP_ADDR2(addr);
11347 REG_WR_DMAE(sc, reg, wb_write, 2);
11350 static void bnx2x_clear_func_ilt(struct bnx2x_softc *sc, uint32_t func)
11352 uint32_t i, base = FUNC_ILT_BASE(func);
11353 for (i = base; i < base + ILT_PER_FUNC; i++) {
11354 bnx2x_ilt_wr(sc, i, 0);
11358 static void bnx2x_reset_func(struct bnx2x_softc *sc)
11360 struct bnx2x_fastpath *fp;
11361 int port = SC_PORT(sc);
11362 int func = SC_FUNC(sc);
11365 /* Disable the function in the FW */
11366 REG_WR8(sc, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
11367 REG_WR8(sc, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
11368 REG_WR8(sc, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
11369 REG_WR8(sc, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
11372 FOR_EACH_ETH_QUEUE(sc, i) {
11374 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11375 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
11380 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11381 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), SB_DISABLED);
11383 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) {
11384 REG_WR(sc, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
11388 /* Configure IGU */
11389 if (sc->devinfo.int_block == INT_BLOCK_HC) {
11390 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11391 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11393 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11394 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11397 if (CNIC_LOADED(sc)) {
11398 /* Disable Timer scan */
11399 REG_WR(sc, TM_REG_EN_LINEAR0_TIMER + port * 4, 0);
11401 * Wait for at least 10ms and up to 2 second for the timers
11404 for (i = 0; i < 200; i++) {
11406 if (!REG_RD(sc, TM_REG_LIN0_SCAN_ON + port * 4))
11412 bnx2x_clear_func_ilt(sc, func);
11415 * Timers workaround bug for E2: if this is vnic-3,
11416 * we need to set the entire ilt range for this timers.
11418 if (!CHIP_IS_E1x(sc) && SC_VN(sc) == 3) {
11419 struct ilt_client_info ilt_cli;
11420 /* use dummy TM client */
11421 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
11423 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
11424 ilt_cli.client_num = ILT_CLIENT_TM;
11426 ecore_ilt_boundry_init_op(sc, &ilt_cli, 0);
11429 /* this assumes that reset_port() called before reset_func() */
11430 if (!CHIP_IS_E1x(sc)) {
11431 bnx2x_pf_disable(sc);
11434 sc->dmae_ready = 0;
11437 static void bnx2x_release_firmware(struct bnx2x_softc *sc)
11439 rte_free(sc->init_ops);
11440 rte_free(sc->init_ops_offsets);
11441 rte_free(sc->init_data);
11442 rte_free(sc->iro_array);
11445 static int bnx2x_init_firmware(struct bnx2x_softc *sc)
11448 uint8_t *p = sc->firmware;
11451 for (i = 0; i < 24; ++i)
11452 off[i] = rte_be_to_cpu_32(*((uint32_t *) sc->firmware + i));
11455 sc->init_ops = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11458 bnx2x_data_to_init_ops(p + off[1], sc->init_ops, len);
11461 sc->init_ops_offsets = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11462 if (!sc->init_ops_offsets)
11464 bnx2x_data_to_init_offsets(p + off[3], sc->init_ops_offsets, len);
11467 sc->init_data = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11468 if (!sc->init_data)
11470 bnx2x_data_to_init_data(p + off[5], sc->init_data, len);
11472 sc->tsem_int_table_data = p + off[7];
11473 sc->tsem_pram_data = p + off[9];
11474 sc->usem_int_table_data = p + off[11];
11475 sc->usem_pram_data = p + off[13];
11476 sc->csem_int_table_data = p + off[15];
11477 sc->csem_pram_data = p + off[17];
11478 sc->xsem_int_table_data = p + off[19];
11479 sc->xsem_pram_data = p + off[21];
11482 sc->iro_array = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11483 if (!sc->iro_array)
11485 bnx2x_data_to_iro_array(p + off[23], sc->iro_array, len);
11490 bnx2x_release_firmware(sc);
11494 static int cut_gzip_prefix(const uint8_t * zbuf, int len)
11496 #define MIN_PREFIX_SIZE (10)
11498 int n = MIN_PREFIX_SIZE;
11501 if (!(zbuf[0] == 0x1f && zbuf[1] == 0x8b && zbuf[2] == Z_DEFLATED) ||
11502 len <= MIN_PREFIX_SIZE) {
11506 /* optional extra fields are present */
11507 if (zbuf[3] & 0x4) {
11514 /* file name is present */
11515 if (zbuf[3] & 0x8) {
11516 while ((zbuf[n++] != 0) && (n < len)) ;
11522 static int ecore_gunzip(struct bnx2x_softc *sc, const uint8_t * zbuf, int len)
11525 int data_begin = cut_gzip_prefix(zbuf, len);
11527 PMD_DRV_LOG(DEBUG, "ecore_gunzip %d", len);
11529 if (data_begin <= 0) {
11530 PMD_DRV_LOG(NOTICE, "bad gzip prefix");
11534 memset(&zlib_stream, 0, sizeof(zlib_stream));
11535 zlib_stream.next_in = zbuf + data_begin;
11536 zlib_stream.avail_in = len - data_begin;
11537 zlib_stream.next_out = sc->gz_buf;
11538 zlib_stream.avail_out = FW_BUF_SIZE;
11540 ret = inflateInit2(&zlib_stream, -MAX_WBITS);
11542 PMD_DRV_LOG(NOTICE, "zlib inflateInit2 error");
11546 ret = inflate(&zlib_stream, Z_FINISH);
11547 if ((ret != Z_STREAM_END) && (ret != Z_OK)) {
11548 PMD_DRV_LOG(NOTICE, "zlib inflate error: %d %s", ret,
11552 sc->gz_outlen = zlib_stream.total_out;
11553 if (sc->gz_outlen & 0x3) {
11554 PMD_DRV_LOG(NOTICE, "firmware is not aligned. gz_outlen == %d",
11557 sc->gz_outlen >>= 2;
11559 inflateEnd(&zlib_stream);
11561 if (ret == Z_STREAM_END)
11568 ecore_write_dmae_phys_len(struct bnx2x_softc *sc, rte_iova_t phys_addr,
11569 uint32_t addr, uint32_t len)
11571 bnx2x_write_dmae_phys_len(sc, phys_addr, addr, len);
11575 ecore_storm_memset_struct(struct bnx2x_softc *sc, uint32_t addr, size_t size,
11579 for (i = 0; i < size / 4; i++) {
11580 REG_WR(sc, addr + (i * 4), data[i]);
11584 static const char *get_ext_phy_type(uint32_t ext_phy_type)
11586 uint32_t phy_type_idx = ext_phy_type >> 8;
11587 static const char *types[] =
11588 { "DIRECT", "BNX2X-8071", "BNX2X-8072", "BNX2X-8073",
11589 "BNX2X-8705", "BNX2X-8706", "BNX2X-8726", "BNX2X-8481", "SFX-7101",
11591 "BNX2X-8727-NOC", "BNX2X-84823", "NOT_CONN", "FAILURE"
11594 if (phy_type_idx < 12)
11595 return types[phy_type_idx];
11596 else if (PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN == ext_phy_type)
11602 static const char *get_state(uint32_t state)
11604 uint32_t state_idx = state >> 12;
11605 static const char *states[] = { "CLOSED", "OPENING_WAIT4_LOAD",
11606 "OPENING_WAIT4_PORT", "OPEN", "CLOSING_WAIT4_HALT",
11607 "CLOSING_WAIT4_DELETE", "CLOSING_WAIT4_UNLOAD",
11608 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
11609 "UNKNOWN", "DISABLED", "DIAG", "ERROR", "UNDEFINED"
11612 if (state_idx <= 0xF)
11613 return states[state_idx];
11615 return states[0x10];
11618 static const char *get_recovery_state(uint32_t state)
11620 static const char *states[] = { "NONE", "DONE", "INIT",
11621 "WAIT", "FAILED", "NIC_LOADING"
11623 return states[state];
11626 static const char *get_rx_mode(uint32_t mode)
11628 static const char *modes[] = { "NONE", "NORMAL", "ALLMULTI",
11629 "PROMISC", "MAX_MULTICAST", "ERROR"
11633 return modes[mode];
11634 else if (BNX2X_MAX_MULTICAST == mode)
11640 #define BNX2X_INFO_STR_MAX 256
11641 static const char *get_bnx2x_flags(uint32_t flags)
11644 static const char *flag[] = { "ONE_PORT ", "NO_ISCSI ",
11645 "NO_FCOE ", "NO_WOL ", "USING_DAC ", "USING_MSIX ",
11646 "USING_MSI ", "DISABLE_MSI ", "UNKNOWN ", "NO_MCP ",
11647 "SAFC_TX_FLAG ", "MF_FUNC_DIS ", "TX_SWITCHING "
11649 static char flag_str[BNX2X_INFO_STR_MAX];
11650 memset(flag_str, 0, BNX2X_INFO_STR_MAX);
11652 for (i = 0; i < 5; i++)
11653 if (flags & (1 << i)) {
11654 strcat(flag_str, flag[i]);
11658 static char unknown[BNX2X_INFO_STR_MAX];
11659 snprintf(unknown, 32, "Unknown flag mask %x", flags);
11660 strcat(flag_str, unknown);
11666 * Prints useful adapter info.
11668 void bnx2x_print_adapter_info(struct bnx2x_softc *sc)
11671 __rte_unused uint32_t ext_phy_type;
11673 PMD_INIT_FUNC_TRACE();
11674 if (sc->link_vars.phy_flags & PHY_XGXS_FLAG)
11675 ext_phy_type = ELINK_XGXS_EXT_PHY_TYPE(REG_RD(sc,
11680 dev_info.port_hw_config
11681 [0].external_phy_config)));
11683 ext_phy_type = ELINK_SERDES_EXT_PHY_TYPE(REG_RD(sc,
11689 dev_info.port_hw_config
11690 [0].external_phy_config)));
11692 PMD_INIT_LOG(DEBUG, "\n\n===================================\n");
11693 /* Hardware chip info. */
11694 PMD_INIT_LOG(DEBUG, "%12s : %#08x", "ASIC", sc->devinfo.chip_id);
11695 PMD_INIT_LOG(DEBUG, "%12s : %c%d", "Rev", (CHIP_REV(sc) >> 12) + 'A',
11696 (CHIP_METAL(sc) >> 4));
11699 PMD_INIT_LOG(DEBUG, "%12s : %d, ", "Bus PCIe", sc->devinfo.pcie_link_width);
11700 switch (sc->devinfo.pcie_link_speed) {
11702 PMD_INIT_LOG(DEBUG, "%23s", "2.5 Gbps");
11705 PMD_INIT_LOG(DEBUG, "%21s", "5 Gbps");
11708 PMD_INIT_LOG(DEBUG, "%21s", "8 Gbps");
11711 PMD_INIT_LOG(DEBUG, "%33s", "Unknown link speed");
11714 /* Device features. */
11715 PMD_INIT_LOG(DEBUG, "%12s : ", "Flags");
11717 /* Miscellaneous flags. */
11718 if (sc->devinfo.pcie_cap_flags & BNX2X_MSI_CAPABLE_FLAG) {
11719 PMD_INIT_LOG(DEBUG, "%18s", "MSI");
11723 if (sc->devinfo.pcie_cap_flags & BNX2X_MSIX_CAPABLE_FLAG) {
11725 PMD_INIT_LOG(DEBUG, "|");
11726 PMD_INIT_LOG(DEBUG, "%20s", "MSI-X");
11731 PMD_INIT_LOG(DEBUG, "%12s : ", "Queues");
11732 switch (sc->sp->rss_rdata.rss_mode) {
11733 case ETH_RSS_MODE_DISABLED:
11734 PMD_INIT_LOG(DEBUG, "%19s", "None");
11736 case ETH_RSS_MODE_REGULAR:
11737 PMD_INIT_LOG(DEBUG, "%18s : %d", "RSS", sc->num_queues);
11740 PMD_INIT_LOG(DEBUG, "%22s", "Unknown");
11745 /* RTE and Driver versions */
11746 PMD_INIT_LOG(DEBUG, "%12s : %s", "DPDK",
11748 PMD_INIT_LOG(DEBUG, "%12s : %s", "Driver",
11749 bnx2x_pmd_version());
11751 /* Firmware versions and device features. */
11752 PMD_INIT_LOG(DEBUG, "%12s : %d.%d.%d",
11754 BNX2X_5710_FW_MAJOR_VERSION,
11755 BNX2X_5710_FW_MINOR_VERSION,
11756 BNX2X_5710_FW_REVISION_VERSION);
11757 PMD_INIT_LOG(DEBUG, "%12s : %s",
11758 "Bootcode", sc->devinfo.bc_ver_str);
11760 PMD_INIT_LOG(DEBUG, "\n\n===================================\n");
11761 PMD_INIT_LOG(DEBUG, "%12s : %u", "Bnx2x Func", sc->pcie_func);
11762 PMD_INIT_LOG(DEBUG, "%12s : %s", "Bnx2x Flags", get_bnx2x_flags(sc->flags));
11763 PMD_INIT_LOG(DEBUG, "%12s : %s", "DMAE Is",
11764 (sc->dmae_ready ? "Ready" : "Not Ready"));
11765 PMD_INIT_LOG(DEBUG, "%12s : %s", "OVLAN", (OVLAN(sc) ? "YES" : "NO"));
11766 PMD_INIT_LOG(DEBUG, "%12s : %s", "MF", (IS_MF(sc) ? "YES" : "NO"));
11767 PMD_INIT_LOG(DEBUG, "%12s : %u", "MTU", sc->mtu);
11768 PMD_INIT_LOG(DEBUG, "%12s : %s", "PHY Type", get_ext_phy_type(ext_phy_type));
11769 PMD_INIT_LOG(DEBUG, "%12s : %x:%x:%x:%x:%x:%x", "MAC Addr",
11770 sc->link_params.mac_addr[0],
11771 sc->link_params.mac_addr[1],
11772 sc->link_params.mac_addr[2],
11773 sc->link_params.mac_addr[3],
11774 sc->link_params.mac_addr[4],
11775 sc->link_params.mac_addr[5]);
11776 PMD_INIT_LOG(DEBUG, "%12s : %s", "RX Mode", get_rx_mode(sc->rx_mode));
11777 PMD_INIT_LOG(DEBUG, "%12s : %s", "State", get_state(sc->state));
11778 if (sc->recovery_state)
11779 PMD_INIT_LOG(DEBUG, "%12s : %s", "Recovery",
11780 get_recovery_state(sc->recovery_state));
11781 PMD_INIT_LOG(DEBUG, "%12s : CQ = %lx, EQ = %lx", "SPQ Left",
11782 sc->cq_spq_left, sc->eq_spq_left);
11783 PMD_INIT_LOG(DEBUG, "%12s : %x", "Switch", sc->link_params.switch_cfg);
11784 PMD_INIT_LOG(DEBUG, "\n\n===================================\n");