2 * Copyright (c) 2007-2013 Broadcom Corporation.
4 * Eric Davis <edavis@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
6 * Gary Zambrano <zambrano@broadcom.com>
8 * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
9 * Copyright (c) 2015 QLogic Corporation.
10 * All rights reserved.
13 * See LICENSE.bnx2x_pmd for copyright and licensing details.
16 #define BNX2X_DRIVER_VERSION "1.78.18"
19 #include "bnx2x_vfpf.h"
21 #include "ecore_init.h"
22 #include "ecore_init_ops.h"
24 #include "rte_version.h"
25 #include "rte_pci_dev_ids.h"
27 #include <sys/types.h>
32 #define BNX2X_PMD_VER_PREFIX "BNX2X PMD"
33 #define BNX2X_PMD_VERSION_MAJOR 1
34 #define BNX2X_PMD_VERSION_MINOR 0
35 #define BNX2X_PMD_VERSION_PATCH 0
37 static inline const char *
38 bnx2x_pmd_version(void)
40 static char version[32];
42 snprintf(version, sizeof(version), "%s %s_%d.%d.%d",
45 BNX2X_PMD_VERSION_MAJOR,
46 BNX2X_PMD_VERSION_MINOR,
47 BNX2X_PMD_VERSION_PATCH);
52 static z_stream zlib_stream;
54 #define EVL_VLID_MASK 0x0FFF
56 #define BNX2X_DEF_SB_ATT_IDX 0x0001
57 #define BNX2X_DEF_SB_IDX 0x0002
60 * FLR Support - bnx2x_pf_flr_clnup() is called during nic_load in the per
61 * function HW initialization.
63 #define FLR_WAIT_USEC 10000 /* 10 msecs */
64 #define FLR_WAIT_INTERVAL 50 /* usecs */
65 #define FLR_POLL_CNT (FLR_WAIT_USEC / FLR_WAIT_INTERVAL) /* 200 */
67 struct pbf_pN_buf_regs {
74 struct pbf_pN_cmd_regs {
80 /* resources needed for unloading a previously loaded device */
82 #define BNX2X_PREV_WAIT_NEEDED 1
83 rte_spinlock_t bnx2x_prev_mtx;
84 struct bnx2x_prev_list_node {
85 LIST_ENTRY(bnx2x_prev_list_node) node;
93 static LIST_HEAD(, bnx2x_prev_list_node) bnx2x_prev_list
94 = LIST_HEAD_INITIALIZER(bnx2x_prev_list);
96 static int load_count[2][3] = { { 0 } };
97 /* per-path: 0-common, 1-port0, 2-port1 */
99 static void bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg,
101 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc);
102 static void storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng,
104 static void bnx2x_set_reset_global(struct bnx2x_softc *sc);
105 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc);
106 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine);
107 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc);
108 static uint8_t bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global,
110 static void bnx2x_int_disable(struct bnx2x_softc *sc);
111 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc);
112 static void bnx2x_pf_disable(struct bnx2x_softc *sc);
113 static void bnx2x_update_rx_prod(struct bnx2x_softc *sc,
114 struct bnx2x_fastpath *fp,
115 uint16_t rx_bd_prod, uint16_t rx_cq_prod);
116 static void bnx2x_link_report(struct bnx2x_softc *sc);
117 void bnx2x_link_status_update(struct bnx2x_softc *sc);
118 static int bnx2x_alloc_mem(struct bnx2x_softc *sc);
119 static void bnx2x_free_mem(struct bnx2x_softc *sc);
120 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc);
121 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc);
122 static __attribute__ ((noinline))
123 int bnx2x_nic_load(struct bnx2x_softc *sc);
125 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc);
126 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp, int scan_fp);
127 static void bnx2x_periodic_stop(struct bnx2x_softc *sc);
128 static void bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id,
129 uint8_t storm, uint16_t index, uint8_t op,
132 int bnx2x_test_bit(int nr, volatile unsigned long *addr)
137 res = ((*addr) & (1UL << nr)) != 0;
142 void bnx2x_set_bit(unsigned int nr, volatile unsigned long *addr)
144 __sync_fetch_and_or(addr, (1UL << nr));
147 void bnx2x_clear_bit(int nr, volatile unsigned long *addr)
149 __sync_fetch_and_and(addr, ~(1UL << nr));
152 int bnx2x_test_and_clear_bit(int nr, volatile unsigned long *addr)
154 unsigned long mask = (1UL << nr);
155 return __sync_fetch_and_and(addr, ~mask) & mask;
158 int bnx2x_cmpxchg(volatile int *addr, int old, int new)
160 return __sync_val_compare_and_swap(addr, old, new);
164 bnx2x_dma_alloc(struct bnx2x_softc *sc, size_t size, struct bnx2x_dma *dma,
165 const char *msg, uint32_t align)
167 char mz_name[RTE_MEMZONE_NAMESIZE];
168 const struct rte_memzone *z;
172 sprintf(mz_name, "bnx2x%d_%s_%" PRIx64, SC_ABS_FUNC(sc), msg,
173 rte_get_timer_cycles());
175 sprintf(mz_name, "bnx2x%d_%s_%" PRIx64, sc->pcie_device, msg,
176 rte_get_timer_cycles());
178 /* Caller must take care that strlen(mz_name) < RTE_MEMZONE_NAMESIZE */
179 z = rte_memzone_reserve_aligned(mz_name, (uint64_t) (size),
180 rte_lcore_to_socket_id(rte_lcore_id()),
183 PMD_DRV_LOG(ERR, "DMA alloc failed for %s", msg);
186 dma->paddr = (uint64_t) z->phys_addr;
187 dma->vaddr = z->addr;
189 PMD_DRV_LOG(DEBUG, "%s: virt=%p phys=%" PRIx64, msg, dma->vaddr, dma->paddr);
194 static int bnx2x_acquire_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
196 uint32_t lock_status;
197 uint32_t resource_bit = (1 << resource);
198 int func = SC_FUNC(sc);
199 uint32_t hw_lock_control_reg;
202 PMD_INIT_FUNC_TRACE();
204 /* validate the resource is within range */
205 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
207 "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
213 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
215 hw_lock_control_reg =
216 (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
219 /* validate the resource is not already taken */
220 lock_status = REG_RD(sc, hw_lock_control_reg);
221 if (lock_status & resource_bit) {
223 "resource in use (status 0x%x bit 0x%x)",
224 lock_status, resource_bit);
228 /* try every 5ms for 5 seconds */
229 for (cnt = 0; cnt < 1000; cnt++) {
230 REG_WR(sc, (hw_lock_control_reg + 4), resource_bit);
231 lock_status = REG_RD(sc, hw_lock_control_reg);
232 if (lock_status & resource_bit) {
238 PMD_DRV_LOG(NOTICE, "Resource lock timeout!");
242 static int bnx2x_release_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
244 uint32_t lock_status;
245 uint32_t resource_bit = (1 << resource);
246 int func = SC_FUNC(sc);
247 uint32_t hw_lock_control_reg;
249 PMD_INIT_FUNC_TRACE();
251 /* validate the resource is within range */
252 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
254 "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
260 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
262 hw_lock_control_reg =
263 (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
266 /* validate the resource is currently taken */
267 lock_status = REG_RD(sc, hw_lock_control_reg);
268 if (!(lock_status & resource_bit)) {
270 "resource not in use (status 0x%x bit 0x%x)",
271 lock_status, resource_bit);
275 REG_WR(sc, hw_lock_control_reg, resource_bit);
279 /* copy command into DMAE command memory and set DMAE command Go */
280 void bnx2x_post_dmae(struct bnx2x_softc *sc, struct dmae_command *dmae, int idx)
285 cmd_offset = (DMAE_REG_CMD_MEM + (sizeof(struct dmae_command) * idx));
286 for (i = 0; i < ((sizeof(struct dmae_command) / 4)); i++) {
287 REG_WR(sc, (cmd_offset + (i * 4)), *(((uint32_t *) dmae) + i));
290 REG_WR(sc, dmae_reg_go_c[idx], 1);
293 uint32_t bnx2x_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type)
295 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
296 DMAE_COMMAND_C_TYPE_ENABLE);
299 uint32_t bnx2x_dmae_opcode_clr_src_reset(uint32_t opcode)
301 return opcode & ~DMAE_COMMAND_SRC_RESET;
305 bnx2x_dmae_opcode(struct bnx2x_softc * sc, uint8_t src_type, uint8_t dst_type,
306 uint8_t with_comp, uint8_t comp_type)
310 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
311 (dst_type << DMAE_COMMAND_DST_SHIFT));
313 opcode |= (DMAE_COMMAND_SRC_RESET | DMAE_COMMAND_DST_RESET);
315 opcode |= (SC_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
317 opcode |= ((SC_VN(sc) << DMAE_COMMAND_E1HVN_SHIFT) |
318 (SC_VN(sc) << DMAE_COMMAND_DST_VN_SHIFT));
320 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
323 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
325 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
329 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
336 bnx2x_prep_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae,
337 uint8_t src_type, uint8_t dst_type)
339 memset(dmae, 0, sizeof(struct dmae_command));
342 dmae->opcode = bnx2x_dmae_opcode(sc, src_type, dst_type,
343 TRUE, DMAE_COMP_PCI);
345 /* fill in the completion parameters */
346 dmae->comp_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_comp));
347 dmae->comp_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_comp));
348 dmae->comp_val = DMAE_COMP_VAL;
351 /* issue a DMAE command over the init channel and wait for completion */
353 bnx2x_issue_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae)
355 uint32_t *wb_comp = BNX2X_SP(sc, wb_comp);
356 int timeout = CHIP_REV_IS_SLOW(sc) ? 400000 : 4000;
358 /* reset completion */
361 /* post the command on the channel used for initializations */
362 bnx2x_post_dmae(sc, dmae, INIT_DMAE_C(sc));
364 /* wait for completion */
367 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
369 (sc->recovery_state != BNX2X_RECOVERY_DONE &&
370 sc->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
371 PMD_DRV_LOG(INFO, "DMAE timeout!");
379 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
380 PMD_DRV_LOG(INFO, "DMAE PCI error!");
381 return DMAE_PCI_ERROR;
387 void bnx2x_read_dmae(struct bnx2x_softc *sc, uint32_t src_addr, uint32_t len32)
389 struct dmae_command dmae;
394 if (!sc->dmae_ready) {
395 data = BNX2X_SP(sc, wb_data[0]);
397 for (i = 0; i < len32; i++) {
398 data[i] = REG_RD(sc, (src_addr + (i * 4)));
404 /* set opcode and fixed command fields */
405 bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
407 /* fill in addresses and len */
408 dmae.src_addr_lo = (src_addr >> 2); /* GRC addr has dword resolution */
409 dmae.src_addr_hi = 0;
410 dmae.dst_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_data));
411 dmae.dst_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_data));
414 /* issue the command and wait for completion */
415 if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
416 rte_panic("DMAE failed (%d)", rc);
421 bnx2x_write_dmae(struct bnx2x_softc *sc, phys_addr_t dma_addr, uint32_t dst_addr,
424 struct dmae_command dmae;
427 if (!sc->dmae_ready) {
428 ecore_init_str_wr(sc, dst_addr, BNX2X_SP(sc, wb_data[0]), len32);
432 /* set opcode and fixed command fields */
433 bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
435 /* fill in addresses and len */
436 dmae.src_addr_lo = U64_LO(dma_addr);
437 dmae.src_addr_hi = U64_HI(dma_addr);
438 dmae.dst_addr_lo = (dst_addr >> 2); /* GRC addr has dword resolution */
439 dmae.dst_addr_hi = 0;
442 /* issue the command and wait for completion */
443 if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
444 rte_panic("DMAE failed (%d)", rc);
449 bnx2x_write_dmae_phys_len(struct bnx2x_softc *sc, phys_addr_t phys_addr,
450 uint32_t addr, uint32_t len)
452 uint32_t dmae_wr_max = DMAE_LEN32_WR_MAX(sc);
455 while (len > dmae_wr_max) {
456 bnx2x_write_dmae(sc, (phys_addr + offset), /* src DMA address */
457 (addr + offset), /* dst GRC address */
459 offset += (dmae_wr_max * 4);
463 bnx2x_write_dmae(sc, (phys_addr + offset), /* src DMA address */
464 (addr + offset), /* dst GRC address */
469 bnx2x_set_ctx_validation(struct bnx2x_softc *sc, struct eth_context *cxt,
472 /* ustorm cxt validation */
473 cxt->ustorm_ag_context.cdu_usage =
474 CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
475 CDU_REGION_NUMBER_UCM_AG,
476 ETH_CONNECTION_TYPE);
477 /* xcontext validation */
478 cxt->xstorm_ag_context.cdu_reserved =
479 CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
480 CDU_REGION_NUMBER_XCM_AG,
481 ETH_CONNECTION_TYPE);
485 bnx2x_storm_memset_hc_timeout(struct bnx2x_softc *sc, uint8_t fw_sb_id,
486 uint8_t sb_index, uint8_t ticks)
489 (BAR_CSTRORM_INTMEM +
490 CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(fw_sb_id, sb_index));
492 REG_WR8(sc, addr, ticks);
496 bnx2x_storm_memset_hc_disable(struct bnx2x_softc *sc, uint16_t fw_sb_id,
497 uint8_t sb_index, uint8_t disable)
499 uint32_t enable_flag =
500 (disable) ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
502 (BAR_CSTRORM_INTMEM +
503 CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(fw_sb_id, sb_index));
507 flags = REG_RD8(sc, addr);
508 flags &= ~HC_INDEX_DATA_HC_ENABLED;
509 flags |= enable_flag;
510 REG_WR8(sc, addr, flags);
514 bnx2x_update_coalesce_sb_index(struct bnx2x_softc *sc, uint8_t fw_sb_id,
515 uint8_t sb_index, uint8_t disable, uint16_t usec)
517 uint8_t ticks = (usec / 4);
519 bnx2x_storm_memset_hc_timeout(sc, fw_sb_id, sb_index, ticks);
521 disable = (disable) ? 1 : ((usec) ? 0 : 1);
522 bnx2x_storm_memset_hc_disable(sc, fw_sb_id, sb_index, disable);
525 uint32_t elink_cb_reg_read(struct bnx2x_softc *sc, uint32_t reg_addr)
527 return REG_RD(sc, reg_addr);
530 void elink_cb_reg_write(struct bnx2x_softc *sc, uint32_t reg_addr, uint32_t val)
532 REG_WR(sc, reg_addr, val);
536 elink_cb_event_log(__rte_unused struct bnx2x_softc *sc,
537 __rte_unused const elink_log_id_t elink_log_id, ...)
539 PMD_DRV_LOG(DEBUG, "ELINK EVENT LOG (%d)", elink_log_id);
542 static int bnx2x_set_spio(struct bnx2x_softc *sc, int spio, uint32_t mode)
546 /* Only 2 SPIOs are configurable */
547 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
548 PMD_DRV_LOG(NOTICE, "Invalid SPIO 0x%x", spio);
552 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
554 /* read SPIO and mask except the float bits */
555 spio_reg = (REG_RD(sc, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
558 case MISC_SPIO_OUTPUT_LOW:
559 /* clear FLOAT and set CLR */
560 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
561 spio_reg |= (spio << MISC_SPIO_CLR_POS);
564 case MISC_SPIO_OUTPUT_HIGH:
565 /* clear FLOAT and set SET */
566 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
567 spio_reg |= (spio << MISC_SPIO_SET_POS);
570 case MISC_SPIO_INPUT_HI_Z:
572 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
579 REG_WR(sc, MISC_REG_SPIO, spio_reg);
580 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
585 static int bnx2x_gpio_read(struct bnx2x_softc *sc, int gpio_num, uint8_t port)
587 /* The GPIO should be swapped if swap register is set and active */
588 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
589 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
590 int gpio_shift = gpio_num;
592 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
594 uint32_t gpio_mask = (1 << gpio_shift);
597 if (gpio_num > MISC_REGISTERS_GPIO_3) {
598 PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
602 /* read GPIO value */
603 gpio_reg = REG_RD(sc, MISC_REG_GPIO);
605 /* get the requested pin value */
606 return ((gpio_reg & gpio_mask) == gpio_mask) ? 1 : 0;
610 bnx2x_gpio_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode, uint8_t port)
612 /* The GPIO should be swapped if swap register is set and active */
613 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
614 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
615 int gpio_shift = gpio_num;
617 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
619 uint32_t gpio_mask = (1 << gpio_shift);
622 if (gpio_num > MISC_REGISTERS_GPIO_3) {
623 PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
627 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
629 /* read GPIO and mask except the float bits */
630 gpio_reg = (REG_RD(sc, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
633 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
634 /* clear FLOAT and set CLR */
635 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
636 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
639 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
640 /* clear FLOAT and set SET */
641 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
642 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
645 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
647 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
654 REG_WR(sc, MISC_REG_GPIO, gpio_reg);
655 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
661 bnx2x_gpio_mult_write(struct bnx2x_softc *sc, uint8_t pins, uint32_t mode)
665 /* any port swapping should be handled by caller */
667 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
669 /* read GPIO and mask except the float bits */
670 gpio_reg = REG_RD(sc, MISC_REG_GPIO);
671 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
672 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
673 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
676 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
678 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
681 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
683 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
686 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
688 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
692 PMD_DRV_LOG(NOTICE, "Invalid GPIO mode assignment %d", mode);
693 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
697 REG_WR(sc, MISC_REG_GPIO, gpio_reg);
698 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
704 bnx2x_gpio_int_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode,
707 /* The GPIO should be swapped if swap register is set and active */
708 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
709 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
710 int gpio_shift = gpio_num;
712 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
714 uint32_t gpio_mask = (1 << gpio_shift);
717 if (gpio_num > MISC_REGISTERS_GPIO_3) {
718 PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
722 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
725 gpio_reg = REG_RD(sc, MISC_REG_GPIO_INT);
728 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
729 /* clear SET and set CLR */
730 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
731 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
734 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
735 /* clear CLR and set SET */
736 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
737 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
744 REG_WR(sc, MISC_REG_GPIO_INT, gpio_reg);
745 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
751 elink_cb_gpio_read(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t port)
753 return bnx2x_gpio_read(sc, gpio_num, port);
756 uint8_t elink_cb_gpio_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode, /* 0=low 1=high */
759 return bnx2x_gpio_write(sc, gpio_num, mode, port);
763 elink_cb_gpio_mult_write(struct bnx2x_softc * sc, uint8_t pins,
764 uint8_t mode /* 0=low 1=high */ )
766 return bnx2x_gpio_mult_write(sc, pins, mode);
769 uint8_t elink_cb_gpio_int_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode, /* 0=low 1=high */
772 return bnx2x_gpio_int_write(sc, gpio_num, mode, port);
775 void elink_cb_notify_link_changed(struct bnx2x_softc *sc)
777 REG_WR(sc, (MISC_REG_AEU_GENERAL_ATTN_12 +
778 (SC_FUNC(sc) * sizeof(uint32_t))), 1);
781 /* send the MCP a request, block until there is a reply */
783 elink_cb_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
785 int mb_idx = SC_FW_MB_IDX(sc);
789 uint8_t delay = CHIP_REV_IS_SLOW(sc) ? 100 : 10;
792 SHMEM_WR(sc, func_mb[mb_idx].drv_mb_param, param);
793 SHMEM_WR(sc, func_mb[mb_idx].drv_mb_header, (command | seq));
796 "wrote command 0x%08x to FW MB param 0x%08x",
797 (command | seq), param);
799 /* Let the FW do it's magic. GIve it up to 5 seconds... */
802 rc = SHMEM_RD(sc, func_mb[mb_idx].fw_mb_header);
803 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
805 /* is this a reply to our command? */
806 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) {
807 rc &= FW_MSG_CODE_MASK;
810 PMD_DRV_LOG(NOTICE, "FW failed to respond!");
818 bnx2x_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
820 return elink_cb_fw_command(sc, command, param);
824 __storm_memset_dma_mapping(struct bnx2x_softc *sc, uint32_t addr,
827 REG_WR(sc, addr, U64_LO(mapping));
828 REG_WR(sc, (addr + 4), U64_HI(mapping));
832 storm_memset_spq_addr(struct bnx2x_softc *sc, phys_addr_t mapping,
835 uint32_t addr = (XSEM_REG_FAST_MEMORY +
836 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid));
837 __storm_memset_dma_mapping(sc, addr, mapping);
841 storm_memset_vf_to_pf(struct bnx2x_softc *sc, uint16_t abs_fid, uint16_t pf_id)
843 REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid)),
845 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid)),
847 REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid)),
849 REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid)),
854 storm_memset_func_en(struct bnx2x_softc *sc, uint16_t abs_fid, uint8_t enable)
856 REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid)),
858 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid)),
860 REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid)),
862 REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid)),
867 storm_memset_eq_data(struct bnx2x_softc *sc, struct event_ring_data *eq_data,
873 addr = (BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid));
874 size = sizeof(struct event_ring_data);
875 ecore_storm_memset_struct(sc, addr, size, (uint32_t *) eq_data);
879 storm_memset_eq_prod(struct bnx2x_softc *sc, uint16_t eq_prod, uint16_t pfid)
881 uint32_t addr = (BAR_CSTRORM_INTMEM +
882 CSTORM_EVENT_RING_PROD_OFFSET(pfid));
883 REG_WR16(sc, addr, eq_prod);
887 * Post a slowpath command.
889 * A slowpath command is used to propogate a configuration change through
890 * the controller in a controlled manner, allowing each STORM processor and
891 * other H/W blocks to phase in the change. The commands sent on the
892 * slowpath are referred to as ramrods. Depending on the ramrod used the
893 * completion of the ramrod will occur in different ways. Here's a
894 * breakdown of ramrods and how they complete:
896 * RAMROD_CMD_ID_ETH_PORT_SETUP
897 * Used to setup the leading connection on a port. Completes on the
898 * Receive Completion Queue (RCQ) of that port (typically fp[0]).
900 * RAMROD_CMD_ID_ETH_CLIENT_SETUP
901 * Used to setup an additional connection on a port. Completes on the
902 * RCQ of the multi-queue/RSS connection being initialized.
904 * RAMROD_CMD_ID_ETH_STAT_QUERY
905 * Used to force the storm processors to update the statistics database
906 * in host memory. This ramrod is send on the leading connection CID and
907 * completes as an index increment of the CSTORM on the default status
910 * RAMROD_CMD_ID_ETH_UPDATE
911 * Used to update the state of the leading connection, usually to udpate
912 * the RSS indirection table. Completes on the RCQ of the leading
913 * connection. (Not currently used under FreeBSD until OS support becomes
916 * RAMROD_CMD_ID_ETH_HALT
917 * Used when tearing down a connection prior to driver unload. Completes
918 * on the RCQ of the multi-queue/RSS connection being torn down. Don't
919 * use this on the leading connection.
921 * RAMROD_CMD_ID_ETH_SET_MAC
922 * Sets the Unicast/Broadcast/Multicast used by the port. Completes on
923 * the RCQ of the leading connection.
925 * RAMROD_CMD_ID_ETH_CFC_DEL
926 * Used when tearing down a conneciton prior to driver unload. Completes
927 * on the RCQ of the leading connection (since the current connection
928 * has been completely removed from controller memory).
930 * RAMROD_CMD_ID_ETH_PORT_DEL
931 * Used to tear down the leading connection prior to driver unload,
932 * typically fp[0]. Completes as an index increment of the CSTORM on the
933 * default status block.
935 * RAMROD_CMD_ID_ETH_FORWARD_SETUP
936 * Used for connection offload. Completes on the RCQ of the multi-queue
937 * RSS connection that is being offloaded. (Not currently used under
940 * There can only be one command pending per function.
943 * 0 = Success, !0 = Failure.
946 /* must be called under the spq lock */
947 static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x_softc *sc)
949 struct eth_spe *next_spe = sc->spq_prod_bd;
951 if (sc->spq_prod_bd == sc->spq_last_bd) {
952 /* wrap back to the first eth_spq */
953 sc->spq_prod_bd = sc->spq;
954 sc->spq_prod_idx = 0;
963 /* must be called under the spq lock */
964 static void bnx2x_sp_prod_update(struct bnx2x_softc *sc)
966 int func = SC_FUNC(sc);
969 * Make sure that BD data is updated before writing the producer.
970 * BD data is written to the memory, the producer is read from the
971 * memory, thus we need a full memory barrier to ensure the ordering.
975 REG_WR16(sc, (BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func)),
982 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
984 * @cmd: command to check
985 * @cmd_type: command type
987 static int bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
989 if ((cmd_type == NONE_CONNECTION_TYPE) ||
990 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
991 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
992 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
993 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
994 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
995 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) {
1003 * bnx2x_sp_post - place a single command on an SP ring
1005 * @sc: driver handle
1006 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
1007 * @cid: SW CID the command is related to
1008 * @data_hi: command private data address (high 32 bits)
1009 * @data_lo: command private data address (low 32 bits)
1010 * @cmd_type: command type (e.g. NONE, ETH)
1012 * SP data is handled as if it's always an address pair, thus data fields are
1013 * not swapped to little endian in upper functions. Instead this function swaps
1014 * data as if it's two uint32 fields.
1017 bnx2x_sp_post(struct bnx2x_softc *sc, int command, int cid, uint32_t data_hi,
1018 uint32_t data_lo, int cmd_type)
1020 struct eth_spe *spe;
1024 common = bnx2x_is_contextless_ramrod(command, cmd_type);
1027 if (!atomic_load_acq_long(&sc->eq_spq_left)) {
1028 PMD_DRV_LOG(INFO, "EQ ring is full!");
1032 if (!atomic_load_acq_long(&sc->cq_spq_left)) {
1033 PMD_DRV_LOG(INFO, "SPQ ring is full!");
1038 spe = bnx2x_sp_get_next(sc);
1040 /* CID needs port number to be encoded int it */
1041 spe->hdr.conn_and_cmd_data =
1042 htole32((command << SPE_HDR_CMD_ID_SHIFT) | HW_CID(sc, cid));
1044 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
1046 /* TBD: Check if it works for VFs */
1047 type |= ((SC_FUNC(sc) << SPE_HDR_FUNCTION_ID_SHIFT) &
1048 SPE_HDR_FUNCTION_ID);
1050 spe->hdr.type = htole16(type);
1052 spe->data.update_data_addr.hi = htole32(data_hi);
1053 spe->data.update_data_addr.lo = htole32(data_lo);
1056 * It's ok if the actual decrement is issued towards the memory
1057 * somewhere between the lock and unlock. Thus no more explict
1058 * memory barrier is needed.
1061 atomic_subtract_acq_long(&sc->eq_spq_left, 1);
1063 atomic_subtract_acq_long(&sc->cq_spq_left, 1);
1067 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x"
1068 "data (%x:%x) type(0x%x) left (CQ, EQ) (%lx,%lx)",
1070 (uint32_t) U64_HI(sc->spq_dma.paddr),
1071 (uint32_t) (U64_LO(sc->spq_dma.paddr) +
1072 (uint8_t *) sc->spq_prod_bd -
1073 (uint8_t *) sc->spq), command, common,
1074 HW_CID(sc, cid), data_hi, data_lo, type,
1075 atomic_load_acq_long(&sc->cq_spq_left),
1076 atomic_load_acq_long(&sc->eq_spq_left));
1078 bnx2x_sp_prod_update(sc);
1083 static void bnx2x_drv_pulse(struct bnx2x_softc *sc)
1085 SHMEM_WR(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb,
1086 sc->fw_drv_pulse_wr_seq);
1089 static int bnx2x_tx_queue_has_work(const struct bnx2x_fastpath *fp)
1092 struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1094 if (unlikely(!txq)) {
1095 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1099 mb(); /* status block fields can change */
1100 hw_cons = le16toh(*fp->tx_cons_sb);
1101 return hw_cons != txq->tx_pkt_head;
1104 static uint8_t bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
1106 /* expand this for multi-cos if ever supported */
1107 return bnx2x_tx_queue_has_work(fp);
1110 static int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
1112 uint16_t rx_cq_cons_sb;
1113 struct bnx2x_rx_queue *rxq;
1114 rxq = fp->sc->rx_queues[fp->index];
1115 if (unlikely(!rxq)) {
1116 PMD_RX_LOG(ERR, "ERROR: RX queue is NULL");
1120 mb(); /* status block fields can change */
1121 rx_cq_cons_sb = le16toh(*fp->rx_cq_cons_sb);
1122 if (unlikely((rx_cq_cons_sb & MAX_RCQ_ENTRIES(rxq)) ==
1123 MAX_RCQ_ENTRIES(rxq)))
1125 return rxq->rx_cq_head != rx_cq_cons_sb;
1129 bnx2x_sp_event(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
1130 union eth_rx_cqe *rr_cqe)
1132 #ifdef RTE_LIBRTE_BNX2X_DEBUG
1133 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1135 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1136 enum ecore_queue_cmd drv_cmd = ECORE_Q_CMD_MAX;
1137 struct ecore_queue_sp_obj *q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
1140 "fp=%d cid=%d got ramrod #%d state is %x type is %d",
1141 fp->index, cid, command, sc->state,
1142 rr_cqe->ramrod_cqe.ramrod_type);
1145 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1146 PMD_DRV_LOG(DEBUG, "got UPDATE ramrod. CID %d", cid);
1147 drv_cmd = ECORE_Q_CMD_UPDATE;
1150 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1151 PMD_DRV_LOG(DEBUG, "got MULTI[%d] setup ramrod", cid);
1152 drv_cmd = ECORE_Q_CMD_SETUP;
1155 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1156 PMD_DRV_LOG(DEBUG, "got MULTI[%d] tx-only setup ramrod", cid);
1157 drv_cmd = ECORE_Q_CMD_SETUP_TX_ONLY;
1160 case (RAMROD_CMD_ID_ETH_HALT):
1161 PMD_DRV_LOG(DEBUG, "got MULTI[%d] halt ramrod", cid);
1162 drv_cmd = ECORE_Q_CMD_HALT;
1165 case (RAMROD_CMD_ID_ETH_TERMINATE):
1166 PMD_DRV_LOG(DEBUG, "got MULTI[%d] teminate ramrod", cid);
1167 drv_cmd = ECORE_Q_CMD_TERMINATE;
1170 case (RAMROD_CMD_ID_ETH_EMPTY):
1171 PMD_DRV_LOG(DEBUG, "got MULTI[%d] empty ramrod", cid);
1172 drv_cmd = ECORE_Q_CMD_EMPTY;
1177 "ERROR: unexpected MC reply (%d)"
1178 "on fp[%d]", command, fp->index);
1182 if ((drv_cmd != ECORE_Q_CMD_MAX) &&
1183 q_obj->complete_cmd(sc, q_obj, drv_cmd)) {
1185 * q_obj->complete_cmd() failure means that this was
1186 * an unexpected completion.
1188 * In this case we don't want to increase the sc->spq_left
1189 * because apparently we haven't sent this command the first
1192 // rte_panic("Unexpected SP completion");
1196 atomic_add_acq_long(&sc->cq_spq_left, 1);
1198 PMD_DRV_LOG(DEBUG, "sc->cq_spq_left 0x%lx",
1199 atomic_load_acq_long(&sc->cq_spq_left));
1202 static uint8_t bnx2x_rxeof(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
1204 struct bnx2x_rx_queue *rxq;
1205 uint16_t bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
1206 uint16_t hw_cq_cons, sw_cq_cons, sw_cq_prod;
1208 rxq = sc->rx_queues[fp->index];
1210 PMD_RX_LOG(ERR, "RX queue %d is NULL", fp->index);
1214 /* CQ "next element" is of the size of the regular element */
1215 hw_cq_cons = le16toh(*fp->rx_cq_cons_sb);
1216 if (unlikely((hw_cq_cons & USABLE_RCQ_ENTRIES_PER_PAGE) ==
1217 USABLE_RCQ_ENTRIES_PER_PAGE)) {
1221 bd_cons = rxq->rx_bd_head;
1222 bd_prod = rxq->rx_bd_tail;
1223 bd_prod_fw = bd_prod;
1224 sw_cq_cons = rxq->rx_cq_head;
1225 sw_cq_prod = rxq->rx_cq_tail;
1228 * Memory barrier necessary as speculative reads of the rx
1229 * buffer can be ahead of the index in the status block
1233 while (sw_cq_cons != hw_cq_cons) {
1234 union eth_rx_cqe *cqe;
1235 struct eth_fast_path_rx_cqe *cqe_fp;
1236 uint8_t cqe_fp_flags;
1237 enum eth_rx_cqe_type cqe_fp_type;
1239 comp_ring_cons = RCQ_ENTRY(sw_cq_cons, rxq);
1240 bd_prod = RX_BD(bd_prod, rxq);
1241 bd_cons = RX_BD(bd_cons, rxq);
1243 cqe = &rxq->cq_ring[comp_ring_cons];
1244 cqe_fp = &cqe->fast_path_cqe;
1245 cqe_fp_flags = cqe_fp->type_error_flags;
1246 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
1248 /* is this a slowpath msg? */
1249 if (CQE_TYPE_SLOW(cqe_fp_type)) {
1250 bnx2x_sp_event(sc, fp, cqe);
1254 /* is this an error packet? */
1255 if (unlikely(cqe_fp_flags &
1256 ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG)) {
1257 PMD_RX_LOG(DEBUG, "flags 0x%x rx packet %u",
1258 cqe_fp_flags, sw_cq_cons);
1262 PMD_RX_LOG(DEBUG, "Dropping fastpath called from attn poller!");
1265 bd_cons = NEXT_RX_BD(bd_cons);
1266 bd_prod = NEXT_RX_BD(bd_prod);
1267 bd_prod_fw = NEXT_RX_BD(bd_prod_fw);
1270 sw_cq_prod = NEXT_RCQ_IDX(sw_cq_prod);
1271 sw_cq_cons = NEXT_RCQ_IDX(sw_cq_cons);
1273 } /* while work to do */
1275 rxq->rx_bd_head = bd_cons;
1276 rxq->rx_bd_tail = bd_prod_fw;
1277 rxq->rx_cq_head = sw_cq_cons;
1278 rxq->rx_cq_tail = sw_cq_prod;
1280 /* Update producers */
1281 bnx2x_update_rx_prod(sc, fp, bd_prod_fw, sw_cq_prod);
1283 return sw_cq_cons != hw_cq_cons;
1287 bnx2x_free_tx_pkt(__rte_unused struct bnx2x_fastpath *fp, struct bnx2x_tx_queue *txq,
1288 uint16_t pkt_idx, uint16_t bd_idx)
1290 struct eth_tx_start_bd *tx_start_bd =
1291 &txq->tx_ring[TX_BD(bd_idx, txq)].start_bd;
1292 uint16_t nbd = rte_le_to_cpu_16(tx_start_bd->nbd);
1293 struct rte_mbuf *tx_mbuf = txq->sw_ring[TX_BD(pkt_idx, txq)];
1295 if (likely(tx_mbuf != NULL)) {
1296 rte_pktmbuf_free(tx_mbuf);
1298 PMD_RX_LOG(ERR, "fp[%02d] lost mbuf %lu",
1299 fp->index, (unsigned long)TX_BD(pkt_idx, txq));
1302 txq->sw_ring[TX_BD(pkt_idx, txq)] = NULL;
1303 txq->nb_tx_avail += nbd;
1306 bd_idx = NEXT_TX_BD(bd_idx);
1311 /* processes transmit completions */
1312 uint8_t bnx2x_txeof(__rte_unused struct bnx2x_softc * sc, struct bnx2x_fastpath * fp)
1314 uint16_t bd_cons, hw_cons, sw_cons;
1315 __rte_unused uint16_t tx_bd_avail;
1317 struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1319 if (unlikely(!txq)) {
1320 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1324 bd_cons = txq->tx_bd_head;
1325 hw_cons = rte_le_to_cpu_16(*fp->tx_cons_sb);
1326 sw_cons = txq->tx_pkt_head;
1328 while (sw_cons != hw_cons) {
1329 bd_cons = bnx2x_free_tx_pkt(fp, txq, sw_cons, bd_cons);
1333 txq->tx_pkt_head = sw_cons;
1334 txq->tx_bd_head = bd_cons;
1336 tx_bd_avail = txq->nb_tx_avail;
1338 PMD_TX_LOG(DEBUG, "fp[%02d] avail=%u cons_sb=%u, "
1339 "pkt_head=%u pkt_tail=%u bd_head=%u bd_tail=%u",
1340 fp->index, tx_bd_avail, hw_cons,
1341 txq->tx_pkt_head, txq->tx_pkt_tail,
1342 txq->tx_bd_head, txq->tx_bd_tail);
1346 static void bnx2x_drain_tx_queues(struct bnx2x_softc *sc)
1348 struct bnx2x_fastpath *fp;
1351 /* wait until all TX fastpath tasks have completed */
1352 for (i = 0; i < sc->num_queues; i++) {
1357 while (bnx2x_has_tx_work(fp)) {
1358 bnx2x_txeof(sc, fp);
1362 "Timeout waiting for fp[%d] "
1363 "transmits to complete!", i);
1364 rte_panic("tx drain failure");
1378 bnx2x_del_all_macs(struct bnx2x_softc *sc, struct ecore_vlan_mac_obj *mac_obj,
1379 int mac_type, uint8_t wait_for_comp)
1381 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1384 /* wait for completion of requested */
1385 if (wait_for_comp) {
1386 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1389 /* Set the mac type of addresses we want to clear */
1390 bnx2x_set_bit(mac_type, &vlan_mac_flags);
1392 rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1394 PMD_DRV_LOG(ERR, "Failed to delete MACs (%d)", rc);
1400 bnx2x_fill_accept_flags(struct bnx2x_softc *sc, uint32_t rx_mode,
1401 unsigned long *rx_accept_flags,
1402 unsigned long *tx_accept_flags)
1404 /* Clear the flags first */
1405 *rx_accept_flags = 0;
1406 *tx_accept_flags = 0;
1409 case BNX2X_RX_MODE_NONE:
1411 * 'drop all' supersedes any accept flags that may have been
1412 * passed to the function.
1416 case BNX2X_RX_MODE_NORMAL:
1417 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1418 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, rx_accept_flags);
1419 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1421 /* internal switching mode */
1422 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1423 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, tx_accept_flags);
1424 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1428 case BNX2X_RX_MODE_ALLMULTI:
1429 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1430 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1431 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1433 /* internal switching mode */
1434 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1435 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1436 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1440 case BNX2X_RX_MODE_PROMISC:
1442 * According to deffinition of SI mode, iface in promisc mode
1443 * should receive matched and unmatched (in resolution of port)
1446 bnx2x_set_bit(ECORE_ACCEPT_UNMATCHED, rx_accept_flags);
1447 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1448 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1449 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1451 /* internal switching mode */
1452 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1453 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1456 bnx2x_set_bit(ECORE_ACCEPT_ALL_UNICAST, tx_accept_flags);
1458 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1464 PMD_RX_LOG(ERR, "Unknown rx_mode (%d)", rx_mode);
1468 /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
1469 if (rx_mode != BNX2X_RX_MODE_NONE) {
1470 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, rx_accept_flags);
1471 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, tx_accept_flags);
1478 bnx2x_set_q_rx_mode(struct bnx2x_softc *sc, uint8_t cl_id,
1479 unsigned long rx_mode_flags,
1480 unsigned long rx_accept_flags,
1481 unsigned long tx_accept_flags, unsigned long ramrod_flags)
1483 struct ecore_rx_mode_ramrod_params ramrod_param;
1486 memset(&ramrod_param, 0, sizeof(ramrod_param));
1488 /* Prepare ramrod parameters */
1489 ramrod_param.cid = 0;
1490 ramrod_param.cl_id = cl_id;
1491 ramrod_param.rx_mode_obj = &sc->rx_mode_obj;
1492 ramrod_param.func_id = SC_FUNC(sc);
1494 ramrod_param.pstate = &sc->sp_state;
1495 ramrod_param.state = ECORE_FILTER_RX_MODE_PENDING;
1497 ramrod_param.rdata = BNX2X_SP(sc, rx_mode_rdata);
1498 ramrod_param.rdata_mapping =
1499 (phys_addr_t)BNX2X_SP_MAPPING(sc, rx_mode_rdata),
1500 bnx2x_set_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
1502 ramrod_param.ramrod_flags = ramrod_flags;
1503 ramrod_param.rx_mode_flags = rx_mode_flags;
1505 ramrod_param.rx_accept_flags = rx_accept_flags;
1506 ramrod_param.tx_accept_flags = tx_accept_flags;
1508 rc = ecore_config_rx_mode(sc, &ramrod_param);
1510 PMD_RX_LOG(ERR, "Set rx_mode %d failed", sc->rx_mode);
1517 int bnx2x_set_storm_rx_mode(struct bnx2x_softc *sc)
1519 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
1520 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
1523 rc = bnx2x_fill_accept_flags(sc, sc->rx_mode, &rx_accept_flags,
1529 bnx2x_set_bit(RAMROD_RX, &ramrod_flags);
1530 bnx2x_set_bit(RAMROD_TX, &ramrod_flags);
1531 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1533 return bnx2x_set_q_rx_mode(sc, sc->fp[0].cl_id, rx_mode_flags,
1534 rx_accept_flags, tx_accept_flags,
1538 /* returns the "mcp load_code" according to global load_count array */
1539 static int bnx2x_nic_load_no_mcp(struct bnx2x_softc *sc)
1541 int path = SC_PATH(sc);
1542 int port = SC_PORT(sc);
1544 PMD_DRV_LOG(INFO, "NO MCP - load counts[%d] %d, %d, %d",
1545 path, load_count[path][0], load_count[path][1],
1546 load_count[path][2]);
1548 load_count[path][0]++;
1549 load_count[path][1 + port]++;
1550 PMD_DRV_LOG(INFO, "NO MCP - new load counts[%d] %d, %d, %d",
1551 path, load_count[path][0], load_count[path][1],
1552 load_count[path][2]);
1553 if (load_count[path][0] == 1)
1554 return FW_MSG_CODE_DRV_LOAD_COMMON;
1555 else if (load_count[path][1 + port] == 1)
1556 return FW_MSG_CODE_DRV_LOAD_PORT;
1558 return FW_MSG_CODE_DRV_LOAD_FUNCTION;
1561 /* returns the "mcp load_code" according to global load_count array */
1562 static int bnx2x_nic_unload_no_mcp(struct bnx2x_softc *sc)
1564 int port = SC_PORT(sc);
1565 int path = SC_PATH(sc);
1567 PMD_DRV_LOG(INFO, "NO MCP - load counts[%d] %d, %d, %d",
1568 path, load_count[path][0], load_count[path][1],
1569 load_count[path][2]);
1570 load_count[path][0]--;
1571 load_count[path][1 + port]--;
1572 PMD_DRV_LOG(INFO, "NO MCP - new load counts[%d] %d, %d, %d",
1573 path, load_count[path][0], load_count[path][1],
1574 load_count[path][2]);
1575 if (load_count[path][0] == 0) {
1576 return FW_MSG_CODE_DRV_UNLOAD_COMMON;
1577 } else if (load_count[path][1 + port] == 0) {
1578 return FW_MSG_CODE_DRV_UNLOAD_PORT;
1580 return FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
1584 /* request unload mode from the MCP: COMMON, PORT or FUNCTION */
1585 static uint32_t bnx2x_send_unload_req(struct bnx2x_softc *sc, int unload_mode)
1587 uint32_t reset_code = 0;
1589 /* Select the UNLOAD request mode */
1590 if (unload_mode == UNLOAD_NORMAL) {
1591 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1593 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1596 /* Send the request to the MCP */
1597 if (!BNX2X_NOMCP(sc)) {
1598 reset_code = bnx2x_fw_command(sc, reset_code, 0);
1600 reset_code = bnx2x_nic_unload_no_mcp(sc);
1606 /* send UNLOAD_DONE command to the MCP */
1607 static void bnx2x_send_unload_done(struct bnx2x_softc *sc, uint8_t keep_link)
1609 uint32_t reset_param =
1610 keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
1612 /* Report UNLOAD_DONE to MCP */
1613 if (!BNX2X_NOMCP(sc)) {
1614 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
1618 static int bnx2x_func_wait_started(struct bnx2x_softc *sc)
1622 if (!sc->port.pmf) {
1627 * (assumption: No Attention from MCP at this stage)
1628 * PMF probably in the middle of TX disable/enable transaction
1629 * 1. Sync IRS for default SB
1630 * 2. Sync SP queue - this guarantees us that attention handling started
1631 * 3. Wait, that TX disable/enable transaction completes
1633 * 1+2 guarantee that if DCBX attention was scheduled it already changed
1634 * pending bit of transaction from STARTED-->TX_STOPPED, if we already
1635 * received completion for the transaction the state is TX_STOPPED.
1636 * State will return to STARTED after completion of TX_STOPPED-->STARTED
1640 while (ecore_func_get_state(sc, &sc->func_obj) !=
1641 ECORE_F_STATE_STARTED && tout--) {
1645 if (ecore_func_get_state(sc, &sc->func_obj) != ECORE_F_STATE_STARTED) {
1647 * Failed to complete the transaction in a "good way"
1648 * Force both transactions with CLR bit.
1650 struct ecore_func_state_params func_params = { NULL };
1652 PMD_DRV_LOG(NOTICE, "Unexpected function state! "
1653 "Forcing STARTED-->TX_STOPPED-->STARTED");
1655 func_params.f_obj = &sc->func_obj;
1656 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1658 /* STARTED-->TX_STOPPED */
1659 func_params.cmd = ECORE_F_CMD_TX_STOP;
1660 ecore_func_state_change(sc, &func_params);
1662 /* TX_STOPPED-->STARTED */
1663 func_params.cmd = ECORE_F_CMD_TX_START;
1664 return ecore_func_state_change(sc, &func_params);
1670 static int bnx2x_stop_queue(struct bnx2x_softc *sc, int index)
1672 struct bnx2x_fastpath *fp = &sc->fp[index];
1673 struct ecore_queue_state_params q_params = { NULL };
1676 PMD_DRV_LOG(DEBUG, "stopping queue %d cid %d", index, fp->index);
1678 q_params.q_obj = &sc->sp_objs[fp->index].q_obj;
1679 /* We want to wait for completion in this context */
1680 bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
1682 /* Stop the primary connection: */
1684 /* ...halt the connection */
1685 q_params.cmd = ECORE_Q_CMD_HALT;
1686 rc = ecore_queue_state_change(sc, &q_params);
1691 /* ...terminate the connection */
1692 q_params.cmd = ECORE_Q_CMD_TERMINATE;
1693 memset(&q_params.params.terminate, 0,
1694 sizeof(q_params.params.terminate));
1695 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
1696 rc = ecore_queue_state_change(sc, &q_params);
1701 /* ...delete cfc entry */
1702 q_params.cmd = ECORE_Q_CMD_CFC_DEL;
1703 memset(&q_params.params.cfc_del, 0, sizeof(q_params.params.cfc_del));
1704 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
1705 return ecore_queue_state_change(sc, &q_params);
1708 /* wait for the outstanding SP commands */
1709 static uint8_t bnx2x_wait_sp_comp(struct bnx2x_softc *sc, unsigned long mask)
1712 int tout = 5000; /* wait for 5 secs tops */
1716 if (!(atomic_load_acq_long(&sc->sp_state) & mask)) {
1725 tmp = atomic_load_acq_long(&sc->sp_state);
1727 PMD_DRV_LOG(INFO, "Filtering completion timed out: "
1728 "sp_state 0x%lx, mask 0x%lx", tmp, mask);
1735 static int bnx2x_func_stop(struct bnx2x_softc *sc)
1737 struct ecore_func_state_params func_params = { NULL };
1740 /* prepare parameters for function state transitions */
1741 bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1742 func_params.f_obj = &sc->func_obj;
1743 func_params.cmd = ECORE_F_CMD_STOP;
1746 * Try to stop the function the 'good way'. If it fails (in case
1747 * of a parity error during bnx2x_chip_cleanup()) and we are
1748 * not in a debug mode, perform a state transaction in order to
1749 * enable further HW_RESET transaction.
1751 rc = ecore_func_state_change(sc, &func_params);
1753 PMD_DRV_LOG(NOTICE, "FUNC_STOP ramrod failed. "
1754 "Running a dry transaction");
1755 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1756 return ecore_func_state_change(sc, &func_params);
1762 static int bnx2x_reset_hw(struct bnx2x_softc *sc, uint32_t load_code)
1764 struct ecore_func_state_params func_params = { NULL };
1766 /* Prepare parameters for function state transitions */
1767 bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1769 func_params.f_obj = &sc->func_obj;
1770 func_params.cmd = ECORE_F_CMD_HW_RESET;
1772 func_params.params.hw_init.load_phase = load_code;
1774 return ecore_func_state_change(sc, &func_params);
1777 static void bnx2x_int_disable_sync(struct bnx2x_softc *sc, int disable_hw)
1780 /* prevent the HW from sending interrupts */
1781 bnx2x_int_disable(sc);
1786 bnx2x_chip_cleanup(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1788 int port = SC_PORT(sc);
1789 struct ecore_mcast_ramrod_params rparam = { NULL };
1790 uint32_t reset_code;
1793 bnx2x_drain_tx_queues(sc);
1795 /* give HW time to discard old tx messages */
1798 /* Clean all ETH MACs */
1799 rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_ETH_MAC,
1802 PMD_DRV_LOG(NOTICE, "Failed to delete all ETH MACs (%d)", rc);
1805 /* Clean up UC list */
1806 rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_UC_LIST_MAC,
1809 PMD_DRV_LOG(NOTICE, "Failed to delete UC MACs list (%d)", rc);
1813 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
1815 /* Set "drop all" to stop Rx */
1818 * We need to take the if_maddr_lock() here in order to prevent
1819 * a race between the completion code and this code.
1822 if (bnx2x_test_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) {
1823 bnx2x_set_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state);
1825 bnx2x_set_storm_rx_mode(sc);
1828 /* Clean up multicast configuration */
1829 rparam.mcast_obj = &sc->mcast_obj;
1830 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1833 "Failed to send DEL MCAST command (%d)", rc);
1837 * Send the UNLOAD_REQUEST to the MCP. This will return if
1838 * this function should perform FUNCTION, PORT, or COMMON HW
1841 reset_code = bnx2x_send_unload_req(sc, unload_mode);
1844 * (assumption: No Attention from MCP at this stage)
1845 * PMF probably in the middle of TX disable/enable transaction
1847 rc = bnx2x_func_wait_started(sc);
1849 PMD_DRV_LOG(NOTICE, "bnx2x_func_wait_started failed");
1853 * Close multi and leading connections
1854 * Completions for ramrods are collected in a synchronous way
1856 for (i = 0; i < sc->num_queues; i++) {
1857 if (bnx2x_stop_queue(sc, i)) {
1863 * If SP settings didn't get completed so far - something
1864 * very wrong has happen.
1866 if (!bnx2x_wait_sp_comp(sc, ~0x0UL)) {
1867 PMD_DRV_LOG(NOTICE, "Common slow path ramrods got stuck!");
1872 rc = bnx2x_func_stop(sc);
1874 PMD_DRV_LOG(NOTICE, "Function stop failed!");
1877 /* disable HW interrupts */
1878 bnx2x_int_disable_sync(sc, TRUE);
1880 /* Reset the chip */
1881 rc = bnx2x_reset_hw(sc, reset_code);
1883 PMD_DRV_LOG(NOTICE, "Hardware reset failed");
1886 /* Report UNLOAD_DONE to MCP */
1887 bnx2x_send_unload_done(sc, keep_link);
1890 static void bnx2x_disable_close_the_gate(struct bnx2x_softc *sc)
1894 PMD_DRV_LOG(DEBUG, "Disabling 'close the gates'");
1896 val = REG_RD(sc, MISC_REG_AEU_GENERAL_MASK);
1897 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
1898 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
1899 REG_WR(sc, MISC_REG_AEU_GENERAL_MASK, val);
1903 * Cleans the object that have internal lists without sending
1904 * ramrods. Should be run when interrutps are disabled.
1906 static void bnx2x_squeeze_objects(struct bnx2x_softc *sc)
1908 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1909 struct ecore_mcast_ramrod_params rparam = { NULL };
1910 struct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj;
1913 /* Cleanup MACs' object first... */
1915 /* Wait for completion of requested */
1916 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1917 /* Perform a dry cleanup */
1918 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &ramrod_flags);
1920 /* Clean ETH primary MAC */
1921 bnx2x_set_bit(ECORE_ETH_MAC, &vlan_mac_flags);
1922 rc = mac_obj->delete_all(sc, &sc->sp_objs->mac_obj, &vlan_mac_flags,
1925 PMD_DRV_LOG(NOTICE, "Failed to clean ETH MACs (%d)", rc);
1928 /* Cleanup UC list */
1930 bnx2x_set_bit(ECORE_UC_LIST_MAC, &vlan_mac_flags);
1931 rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1933 PMD_DRV_LOG(NOTICE, "Failed to clean UC list MACs (%d)", rc);
1936 /* Now clean mcast object... */
1938 rparam.mcast_obj = &sc->mcast_obj;
1939 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags);
1941 /* Add a DEL command... */
1942 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1945 "Failed to send DEL MCAST command (%d)", rc);
1948 /* now wait until all pending commands are cleared */
1950 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
1954 "Failed to clean MCAST object (%d)", rc);
1958 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
1962 /* stop the controller */
1963 __attribute__ ((noinline))
1965 bnx2x_nic_unload(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1967 uint8_t global = FALSE;
1970 PMD_DRV_LOG(DEBUG, "Starting NIC unload...");
1972 /* stop the periodic callout */
1973 bnx2x_periodic_stop(sc);
1975 /* mark driver as unloaded in shmem2 */
1976 if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
1977 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
1978 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
1979 val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
1982 if (IS_PF(sc) && sc->recovery_state != BNX2X_RECOVERY_DONE &&
1983 (sc->state == BNX2X_STATE_CLOSED || sc->state == BNX2X_STATE_ERROR)) {
1985 * We can get here if the driver has been unloaded
1986 * during parity error recovery and is either waiting for a
1987 * leader to complete or for other functions to unload and
1988 * then ifconfig down has been issued. In this case we want to
1989 * unload and let other functions to complete a recovery
1992 sc->recovery_state = BNX2X_RECOVERY_DONE;
1994 bnx2x_release_leader_lock(sc);
1997 PMD_DRV_LOG(NOTICE, "Can't unload in closed or error state");
2002 * Nothing to do during unload if previous bnx2x_nic_load()
2003 * did not completed succesfully - all resourses are released.
2005 if ((sc->state == BNX2X_STATE_CLOSED) || (sc->state == BNX2X_STATE_ERROR)) {
2009 sc->state = BNX2X_STATE_CLOSING_WAITING_HALT;
2012 sc->rx_mode = BNX2X_RX_MODE_NONE;
2013 bnx2x_set_rx_mode(sc);
2017 /* set ALWAYS_ALIVE bit in shmem */
2018 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2020 bnx2x_drv_pulse(sc);
2022 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2023 bnx2x_save_statistics(sc);
2026 /* wait till consumers catch up with producers in all queues */
2027 bnx2x_drain_tx_queues(sc);
2029 /* if VF indicate to PF this function is going down (PF will delete sp
2030 * elements and clear initializations
2033 bnx2x_vf_unload(sc);
2034 } else if (unload_mode != UNLOAD_RECOVERY) {
2035 /* if this is a normal/close unload need to clean up chip */
2036 bnx2x_chip_cleanup(sc, unload_mode, keep_link);
2038 /* Send the UNLOAD_REQUEST to the MCP */
2039 bnx2x_send_unload_req(sc, unload_mode);
2042 * Prevent transactions to host from the functions on the
2043 * engine that doesn't reset global blocks in case of global
2044 * attention once gloabl blocks are reset and gates are opened
2045 * (the engine which leader will perform the recovery
2048 if (!CHIP_IS_E1x(sc)) {
2049 bnx2x_pf_disable(sc);
2052 /* disable HW interrupts */
2053 bnx2x_int_disable_sync(sc, TRUE);
2055 /* Report UNLOAD_DONE to MCP */
2056 bnx2x_send_unload_done(sc, FALSE);
2060 * At this stage no more interrupts will arrive so we may safely clean
2061 * the queue'able objects here in case they failed to get cleaned so far.
2064 bnx2x_squeeze_objects(sc);
2067 /* There should be no more pending SP commands at this stage */
2076 bnx2x_free_fw_stats_mem(sc);
2078 sc->state = BNX2X_STATE_CLOSED;
2081 * Check if there are pending parity attentions. If there are - set
2082 * RECOVERY_IN_PROGRESS.
2084 if (IS_PF(sc) && bnx2x_chk_parity_attn(sc, &global, FALSE)) {
2085 bnx2x_set_reset_in_progress(sc);
2087 /* Set RESET_IS_GLOBAL if needed */
2089 bnx2x_set_reset_global(sc);
2094 * The last driver must disable a "close the gate" if there is no
2095 * parity attention or "process kill" pending.
2097 if (IS_PF(sc) && !bnx2x_clear_pf_load(sc) &&
2098 bnx2x_reset_is_done(sc, SC_PATH(sc))) {
2099 bnx2x_disable_close_the_gate(sc);
2102 PMD_DRV_LOG(DEBUG, "Ended NIC unload");
2108 * Encapsulte an mbuf cluster into the tx bd chain and makes the memory
2109 * visible to the controller.
2111 * If an mbuf is submitted to this routine and cannot be given to the
2112 * controller (e.g. it has too many fragments) then the function may free
2113 * the mbuf and return to the caller.
2118 * Note the side effect that an mbuf may be freed if it causes a problem.
2120 void bnx2x_tx_encap(struct bnx2x_tx_queue *txq, struct rte_mbuf **m_head,
2123 struct rte_mbuf *m0;
2124 struct eth_tx_start_bd *tx_start_bd;
2125 uint16_t bd_prod, pkt_prod;
2127 struct bnx2x_softc *sc;
2129 struct bnx2x_fastpath *fp;
2132 fp = &sc->fp[txq->queue_id];
2134 bd_prod = txq->tx_bd_tail;
2135 pkt_prod = txq->tx_pkt_tail;
2137 for (m_tx = 0; m_tx < m_pkts; m_tx++) {
2141 txq->sw_ring[TX_BD(pkt_prod, txq)] = m0;
2143 tx_start_bd = &txq->tx_ring[TX_BD(bd_prod, txq)].start_bd;
2146 rte_cpu_to_le_64(rte_mbuf_data_dma_addr(m0));
2147 tx_start_bd->nbytes = rte_cpu_to_le_16(m0->data_len);
2148 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2149 tx_start_bd->general_data =
2150 (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
2152 tx_start_bd->nbd = rte_cpu_to_le_16(2);
2154 if (m0->ol_flags & PKT_TX_VLAN_PKT) {
2155 tx_start_bd->vlan_or_ethertype =
2156 rte_cpu_to_le_16(m0->vlan_tci);
2157 tx_start_bd->bd_flags.as_bitfield |=
2158 (X_ETH_OUTBAND_VLAN <<
2159 ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT);
2162 tx_start_bd->vlan_or_ethertype =
2163 rte_cpu_to_le_16(pkt_prod);
2165 struct ether_hdr *eh
2166 = rte_pktmbuf_mtod(m0, struct ether_hdr *);
2168 tx_start_bd->vlan_or_ethertype
2169 = rte_cpu_to_le_16(rte_be_to_cpu_16(eh->ether_type));
2173 bd_prod = NEXT_TX_BD(bd_prod);
2175 struct eth_tx_parse_bd_e2 *tx_parse_bd;
2176 const struct ether_hdr *eh = rte_pktmbuf_mtod(m0, struct ether_hdr *);
2177 uint8_t mac_type = UNICAST_ADDRESS;
2180 &txq->tx_ring[TX_BD(bd_prod, txq)].parse_bd_e2;
2181 if (is_multicast_ether_addr(&eh->d_addr)) {
2182 if (is_broadcast_ether_addr(&eh->d_addr))
2183 mac_type = BROADCAST_ADDRESS;
2185 mac_type = MULTICAST_ADDRESS;
2187 tx_parse_bd->parsing_data =
2188 (mac_type << ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT);
2190 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_hi,
2191 &eh->d_addr.addr_bytes[0], 2);
2192 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_mid,
2193 &eh->d_addr.addr_bytes[2], 2);
2194 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_lo,
2195 &eh->d_addr.addr_bytes[4], 2);
2196 rte_memcpy(&tx_parse_bd->data.mac_addr.src_hi,
2197 &eh->s_addr.addr_bytes[0], 2);
2198 rte_memcpy(&tx_parse_bd->data.mac_addr.src_mid,
2199 &eh->s_addr.addr_bytes[2], 2);
2200 rte_memcpy(&tx_parse_bd->data.mac_addr.src_lo,
2201 &eh->s_addr.addr_bytes[4], 2);
2203 tx_parse_bd->data.mac_addr.dst_hi =
2204 rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_hi);
2205 tx_parse_bd->data.mac_addr.dst_mid =
2206 rte_cpu_to_be_16(tx_parse_bd->data.
2208 tx_parse_bd->data.mac_addr.dst_lo =
2209 rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_lo);
2210 tx_parse_bd->data.mac_addr.src_hi =
2211 rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_hi);
2212 tx_parse_bd->data.mac_addr.src_mid =
2213 rte_cpu_to_be_16(tx_parse_bd->data.
2215 tx_parse_bd->data.mac_addr.src_lo =
2216 rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_lo);
2219 "PBD dst %x %x %x src %x %x %x p_data %x",
2220 tx_parse_bd->data.mac_addr.dst_hi,
2221 tx_parse_bd->data.mac_addr.dst_mid,
2222 tx_parse_bd->data.mac_addr.dst_lo,
2223 tx_parse_bd->data.mac_addr.src_hi,
2224 tx_parse_bd->data.mac_addr.src_mid,
2225 tx_parse_bd->data.mac_addr.src_lo,
2226 tx_parse_bd->parsing_data);
2230 "start bd: nbytes %d flags %x vlan %x\n",
2231 tx_start_bd->nbytes,
2232 tx_start_bd->bd_flags.as_bitfield,
2233 tx_start_bd->vlan_or_ethertype);
2235 bd_prod = NEXT_TX_BD(bd_prod);
2238 if (TX_IDX(bd_prod) < 2) {
2243 txq->nb_tx_avail -= m_pkts << 1;
2244 txq->tx_bd_tail = bd_prod;
2245 txq->tx_pkt_tail = pkt_prod;
2248 fp->tx_db.data.prod += (m_pkts << 1) + nbds;
2249 DOORBELL(sc, txq->queue_id, fp->tx_db.raw);
2253 static uint16_t bnx2x_cid_ilt_lines(struct bnx2x_softc *sc)
2255 return L2_ILT_LINES(sc);
2258 static void bnx2x_ilt_set_info(struct bnx2x_softc *sc)
2260 struct ilt_client_info *ilt_client;
2261 struct ecore_ilt *ilt = sc->ilt;
2264 PMD_INIT_FUNC_TRACE();
2266 ilt->start_line = FUNC_ILT_BASE(SC_FUNC(sc));
2269 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
2270 ilt_client->client_num = ILT_CLIENT_CDU;
2271 ilt_client->page_size = CDU_ILT_PAGE_SZ;
2272 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
2273 ilt_client->start = line;
2274 line += bnx2x_cid_ilt_lines(sc);
2276 if (CNIC_SUPPORT(sc)) {
2277 line += CNIC_ILT_LINES;
2280 ilt_client->end = (line - 1);
2283 if (QM_INIT(sc->qm_cid_count)) {
2284 ilt_client = &ilt->clients[ILT_CLIENT_QM];
2285 ilt_client->client_num = ILT_CLIENT_QM;
2286 ilt_client->page_size = QM_ILT_PAGE_SZ;
2287 ilt_client->flags = 0;
2288 ilt_client->start = line;
2290 /* 4 bytes for each cid */
2291 line += DIV_ROUND_UP(sc->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
2294 ilt_client->end = (line - 1);
2297 if (CNIC_SUPPORT(sc)) {
2299 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
2300 ilt_client->client_num = ILT_CLIENT_SRC;
2301 ilt_client->page_size = SRC_ILT_PAGE_SZ;
2302 ilt_client->flags = 0;
2303 ilt_client->start = line;
2304 line += SRC_ILT_LINES;
2305 ilt_client->end = (line - 1);
2308 ilt_client = &ilt->clients[ILT_CLIENT_TM];
2309 ilt_client->client_num = ILT_CLIENT_TM;
2310 ilt_client->page_size = TM_ILT_PAGE_SZ;
2311 ilt_client->flags = 0;
2312 ilt_client->start = line;
2313 line += TM_ILT_LINES;
2314 ilt_client->end = (line - 1);
2317 assert((line <= ILT_MAX_LINES));
2320 static void bnx2x_set_fp_rx_buf_size(struct bnx2x_softc *sc)
2324 for (i = 0; i < sc->num_queues; i++) {
2325 /* get the Rx buffer size for RX frames */
2326 sc->fp[i].rx_buf_size =
2327 (IP_HEADER_ALIGNMENT_PADDING + ETH_OVERHEAD + sc->mtu);
2331 int bnx2x_alloc_ilt_mem(struct bnx2x_softc *sc)
2334 sc->ilt = rte_malloc("", sizeof(struct ecore_ilt), RTE_CACHE_LINE_SIZE);
2336 return sc->ilt == NULL;
2339 static int bnx2x_alloc_ilt_lines_mem(struct bnx2x_softc *sc)
2341 sc->ilt->lines = rte_calloc("",
2342 sizeof(struct ilt_line), ILT_MAX_LINES,
2343 RTE_CACHE_LINE_SIZE);
2344 return sc->ilt->lines == NULL;
2347 void bnx2x_free_ilt_mem(struct bnx2x_softc *sc)
2353 static void bnx2x_free_ilt_lines_mem(struct bnx2x_softc *sc)
2355 if (sc->ilt->lines != NULL) {
2356 rte_free(sc->ilt->lines);
2357 sc->ilt->lines = NULL;
2361 static void bnx2x_free_mem(struct bnx2x_softc *sc)
2365 for (i = 0; i < L2_ILT_LINES(sc); i++) {
2366 sc->context[i].vcxt = NULL;
2367 sc->context[i].size = 0;
2370 ecore_ilt_mem_op(sc, ILT_MEMOP_FREE);
2372 bnx2x_free_ilt_lines_mem(sc);
2375 static int bnx2x_alloc_mem(struct bnx2x_softc *sc)
2380 char cdu_name[RTE_MEMZONE_NAMESIZE];
2383 * Allocate memory for CDU context:
2384 * This memory is allocated separately and not in the generic ILT
2385 * functions because CDU differs in few aspects:
2386 * 1. There can be multiple entities allocating memory for context -
2387 * regular L2, CNIC, and SRIOV drivers. Each separately controls
2388 * its own ILT lines.
2389 * 2. Since CDU page-size is not a single 4KB page (which is the case
2390 * for the other ILT clients), to be efficient we want to support
2391 * allocation of sub-page-size in the last entry.
2392 * 3. Context pointers are used by the driver to pass to FW / update
2393 * the context (for the other ILT clients the pointers are used just to
2394 * free the memory during unload).
2396 context_size = (sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(sc));
2397 for (i = 0, allocated = 0; allocated < context_size; i++) {
2398 sc->context[i].size = min(CDU_ILT_PAGE_SZ,
2399 (context_size - allocated));
2401 snprintf(cdu_name, sizeof(cdu_name), "cdu_%d", i);
2402 if (bnx2x_dma_alloc(sc, sc->context[i].size,
2403 &sc->context[i].vcxt_dma,
2404 cdu_name, BNX2X_PAGE_SIZE) != 0) {
2409 sc->context[i].vcxt =
2410 (union cdu_context *)sc->context[i].vcxt_dma.vaddr;
2412 allocated += sc->context[i].size;
2415 bnx2x_alloc_ilt_lines_mem(sc);
2417 if (ecore_ilt_mem_op(sc, ILT_MEMOP_ALLOC)) {
2418 PMD_DRV_LOG(NOTICE, "ecore_ilt_mem_op ILT_MEMOP_ALLOC failed");
2426 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc)
2428 sc->fw_stats_num = 0;
2430 sc->fw_stats_req_size = 0;
2431 sc->fw_stats_req = NULL;
2432 sc->fw_stats_req_mapping = 0;
2434 sc->fw_stats_data_size = 0;
2435 sc->fw_stats_data = NULL;
2436 sc->fw_stats_data_mapping = 0;
2439 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc)
2441 uint8_t num_queue_stats;
2442 int num_groups, vf_headroom = 0;
2444 /* number of queues for statistics is number of eth queues */
2445 num_queue_stats = BNX2X_NUM_ETH_QUEUES(sc);
2448 * Total number of FW statistics requests =
2449 * 1 for port stats + 1 for PF stats + num of queues
2451 sc->fw_stats_num = (2 + num_queue_stats);
2454 * Request is built from stats_query_header and an array of
2455 * stats_query_cmd_group each of which contains STATS_QUERY_CMD_COUNT
2456 * rules. The real number or requests is configured in the
2457 * stats_query_header.
2459 num_groups = (sc->fw_stats_num + vf_headroom) / STATS_QUERY_CMD_COUNT;
2460 if ((sc->fw_stats_num + vf_headroom) % STATS_QUERY_CMD_COUNT)
2463 sc->fw_stats_req_size =
2464 (sizeof(struct stats_query_header) +
2465 (num_groups * sizeof(struct stats_query_cmd_group)));
2468 * Data for statistics requests + stats_counter.
2469 * stats_counter holds per-STORM counters that are incremented when
2470 * STORM has finished with the current request. Memory for FCoE
2471 * offloaded statistics are counted anyway, even if they will not be sent.
2472 * VF stats are not accounted for here as the data of VF stats is stored
2473 * in memory allocated by the VF, not here.
2475 sc->fw_stats_data_size =
2476 (sizeof(struct stats_counter) +
2477 sizeof(struct per_port_stats) + sizeof(struct per_pf_stats) +
2478 /* sizeof(struct fcoe_statistics_params) + */
2479 (sizeof(struct per_queue_stats) * num_queue_stats));
2481 if (bnx2x_dma_alloc(sc, (sc->fw_stats_req_size + sc->fw_stats_data_size),
2482 &sc->fw_stats_dma, "fw_stats",
2483 RTE_CACHE_LINE_SIZE) != 0) {
2484 bnx2x_free_fw_stats_mem(sc);
2488 /* set up the shortcuts */
2490 sc->fw_stats_req = (struct bnx2x_fw_stats_req *)sc->fw_stats_dma.vaddr;
2491 sc->fw_stats_req_mapping = sc->fw_stats_dma.paddr;
2494 (struct bnx2x_fw_stats_data *)((uint8_t *) sc->fw_stats_dma.vaddr +
2495 sc->fw_stats_req_size);
2496 sc->fw_stats_data_mapping = (sc->fw_stats_dma.paddr +
2497 sc->fw_stats_req_size);
2504 * 0-7 - Engine0 load counter.
2505 * 8-15 - Engine1 load counter.
2506 * 16 - Engine0 RESET_IN_PROGRESS bit.
2507 * 17 - Engine1 RESET_IN_PROGRESS bit.
2508 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active
2509 * function on the engine
2510 * 19 - Engine1 ONE_IS_LOADED.
2511 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
2512 * leader to complete (check for both RESET_IN_PROGRESS bits and not
2513 * for just the one belonging to its engine).
2515 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
2516 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
2517 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
2518 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
2519 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
2520 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
2521 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
2522 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
2524 /* set the GLOBAL_RESET bit, should be run under rtnl lock */
2525 static void bnx2x_set_reset_global(struct bnx2x_softc *sc)
2528 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2529 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2530 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
2531 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2534 /* clear the GLOBAL_RESET bit, should be run under rtnl lock */
2535 static void bnx2x_clear_reset_global(struct bnx2x_softc *sc)
2538 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2539 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2540 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
2541 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2544 /* checks the GLOBAL_RESET bit, should be run under rtnl lock */
2545 static uint8_t bnx2x_reset_is_global(struct bnx2x_softc *sc)
2547 return REG_RD(sc, BNX2X_RECOVERY_GLOB_REG) & BNX2X_GLOBAL_RESET_BIT;
2550 /* clear RESET_IN_PROGRESS bit for the engine, should be run under rtnl lock */
2551 static void bnx2x_set_reset_done(struct bnx2x_softc *sc)
2554 uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2555 BNX2X_PATH0_RST_IN_PROG_BIT;
2557 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2559 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2562 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2564 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2567 /* set RESET_IN_PROGRESS for the engine, should be run under rtnl lock */
2568 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc)
2571 uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2572 BNX2X_PATH0_RST_IN_PROG_BIT;
2574 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2576 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2579 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2581 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2584 /* check RESET_IN_PROGRESS bit for an engine, should be run under rtnl lock */
2585 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine)
2587 uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2588 uint32_t bit = engine ? BNX2X_PATH1_RST_IN_PROG_BIT :
2589 BNX2X_PATH0_RST_IN_PROG_BIT;
2591 /* return false if bit is set */
2592 return (val & bit) ? FALSE : TRUE;
2595 /* get the load status for an engine, should be run under rtnl lock */
2596 static uint8_t bnx2x_get_load_status(struct bnx2x_softc *sc, int engine)
2598 uint32_t mask = engine ? BNX2X_PATH1_LOAD_CNT_MASK :
2599 BNX2X_PATH0_LOAD_CNT_MASK;
2600 uint32_t shift = engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2601 BNX2X_PATH0_LOAD_CNT_SHIFT;
2602 uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2604 val = ((val & mask) >> shift);
2609 /* set pf load mark */
2610 static void bnx2x_set_pf_load(struct bnx2x_softc *sc)
2614 uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2615 BNX2X_PATH0_LOAD_CNT_MASK;
2616 uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2617 BNX2X_PATH0_LOAD_CNT_SHIFT;
2619 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2621 PMD_INIT_FUNC_TRACE();
2623 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2625 /* get the current counter value */
2626 val1 = ((val & mask) >> shift);
2628 /* set bit of this PF */
2629 val1 |= (1 << SC_ABS_FUNC(sc));
2631 /* clear the old value */
2634 /* set the new one */
2635 val |= ((val1 << shift) & mask);
2637 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2639 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2642 /* clear pf load mark */
2643 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc)
2646 uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2647 BNX2X_PATH0_LOAD_CNT_MASK;
2648 uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2649 BNX2X_PATH0_LOAD_CNT_SHIFT;
2651 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2652 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2654 /* get the current counter value */
2655 val1 = (val & mask) >> shift;
2657 /* clear bit of that PF */
2658 val1 &= ~(1 << SC_ABS_FUNC(sc));
2660 /* clear the old value */
2663 /* set the new one */
2664 val |= ((val1 << shift) & mask);
2666 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2667 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2671 /* send load requrest to mcp and analyze response */
2672 static int bnx2x_nic_load_request(struct bnx2x_softc *sc, uint32_t * load_code)
2674 PMD_INIT_FUNC_TRACE();
2678 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
2679 DRV_MSG_SEQ_NUMBER_MASK);
2681 PMD_DRV_LOG(DEBUG, "initial fw_seq 0x%04x", sc->fw_seq);
2684 /* get the current FW pulse sequence */
2685 sc->fw_drv_pulse_wr_seq =
2686 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb) &
2687 DRV_PULSE_SEQ_MASK);
2689 /* set ALWAYS_ALIVE bit in shmem */
2690 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2691 bnx2x_drv_pulse(sc);
2695 (*load_code) = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
2696 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
2698 /* if the MCP fails to respond we must abort */
2699 if (!(*load_code)) {
2700 PMD_DRV_LOG(NOTICE, "MCP response failure!");
2704 /* if MCP refused then must abort */
2705 if ((*load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED) {
2706 PMD_DRV_LOG(NOTICE, "MCP refused load request");
2714 * Check whether another PF has already loaded FW to chip. In virtualized
2715 * environments a pf from anoth VM may have already initialized the device
2716 * including loading FW.
2718 static int bnx2x_nic_load_analyze_req(struct bnx2x_softc *sc, uint32_t load_code)
2720 uint32_t my_fw, loaded_fw;
2722 /* is another pf loaded on this engine? */
2723 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
2724 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
2725 /* build my FW version dword */
2726 my_fw = (BNX2X_5710_FW_MAJOR_VERSION +
2727 (BNX2X_5710_FW_MINOR_VERSION << 8) +
2728 (BNX2X_5710_FW_REVISION_VERSION << 16) +
2729 (BNX2X_5710_FW_ENGINEERING_VERSION << 24));
2731 /* read loaded FW from chip */
2732 loaded_fw = REG_RD(sc, XSEM_REG_PRAM);
2733 PMD_DRV_LOG(DEBUG, "loaded FW 0x%08x / my FW 0x%08x",
2736 /* abort nic load if version mismatch */
2737 if (my_fw != loaded_fw) {
2739 "FW 0x%08x already loaded (mine is 0x%08x)",
2748 /* mark PMF if applicable */
2749 static void bnx2x_nic_load_pmf(struct bnx2x_softc *sc, uint32_t load_code)
2751 uint32_t ncsi_oem_data_addr;
2753 PMD_INIT_FUNC_TRACE();
2755 if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
2756 (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
2757 (load_code == FW_MSG_CODE_DRV_LOAD_PORT)) {
2759 * Barrier here for ordering between the writing to sc->port.pmf here
2760 * and reading it from the periodic task.
2768 PMD_DRV_LOG(DEBUG, "pmf %d", sc->port.pmf);
2770 if (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) {
2771 if (SHMEM2_HAS(sc, ncsi_oem_data_addr)) {
2772 ncsi_oem_data_addr = SHMEM2_RD(sc, ncsi_oem_data_addr);
2773 if (ncsi_oem_data_addr) {
2775 (ncsi_oem_data_addr +
2776 offsetof(struct glob_ncsi_oem_data,
2777 driver_version)), 0);
2783 static void bnx2x_read_mf_cfg(struct bnx2x_softc *sc)
2785 int n = (CHIP_IS_MODE_4_PORT(sc) ? 2 : 1);
2789 if (BNX2X_NOMCP(sc)) {
2790 return; /* what should be the default bvalue in this case */
2794 * The formula for computing the absolute function number is...
2795 * For 2 port configuration (4 functions per port):
2796 * abs_func = 2 * vn + SC_PORT + SC_PATH
2797 * For 4 port configuration (2 functions per port):
2798 * abs_func = 4 * vn + 2 * SC_PORT + SC_PATH
2800 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
2801 abs_func = (n * (2 * vn + SC_PORT(sc)) + SC_PATH(sc));
2802 if (abs_func >= E1H_FUNC_MAX) {
2805 sc->devinfo.mf_info.mf_config[vn] =
2806 MFCFG_RD(sc, func_mf_config[abs_func].config);
2809 if (sc->devinfo.mf_info.mf_config[SC_VN(sc)] &
2810 FUNC_MF_CFG_FUNC_DISABLED) {
2811 PMD_DRV_LOG(DEBUG, "mf_cfg function disabled");
2812 sc->flags |= BNX2X_MF_FUNC_DIS;
2814 PMD_DRV_LOG(DEBUG, "mf_cfg function enabled");
2815 sc->flags &= ~BNX2X_MF_FUNC_DIS;
2819 /* acquire split MCP access lock register */
2820 static int bnx2x_acquire_alr(struct bnx2x_softc *sc)
2824 for (j = 0; j < 1000; j++) {
2826 REG_WR(sc, GRCBASE_MCP + 0x9c, val);
2827 val = REG_RD(sc, GRCBASE_MCP + 0x9c);
2828 if (val & (1L << 31))
2834 if (!(val & (1L << 31))) {
2835 PMD_DRV_LOG(NOTICE, "Cannot acquire MCP access lock register");
2842 /* release split MCP access lock register */
2843 static void bnx2x_release_alr(struct bnx2x_softc *sc)
2845 REG_WR(sc, GRCBASE_MCP + 0x9c, 0);
2848 static void bnx2x_fan_failure(struct bnx2x_softc *sc)
2850 int port = SC_PORT(sc);
2851 uint32_t ext_phy_config;
2853 /* mark the failure */
2855 SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
2857 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2858 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
2859 SHMEM_WR(sc, dev_info.port_hw_config[port].external_phy_config,
2862 /* log the failure */
2864 "Fan Failure has caused the driver to shutdown "
2865 "the card to prevent permanent damage. "
2866 "Please contact OEM Support for assistance");
2868 rte_panic("Schedule task to handle fan failure");
2871 /* this function is called upon a link interrupt */
2872 static void bnx2x_link_attn(struct bnx2x_softc *sc)
2874 uint32_t pause_enabled = 0;
2875 struct host_port_stats *pstats;
2878 /* Make sure that we are synced with the current statistics */
2879 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2881 elink_link_update(&sc->link_params, &sc->link_vars);
2883 if (sc->link_vars.link_up) {
2885 /* dropless flow control */
2886 if (sc->dropless_fc) {
2889 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
2894 (BAR_USTRORM_INTMEM +
2895 USTORM_ETH_PAUSE_ENABLED_OFFSET(SC_PORT(sc))),
2899 if (sc->link_vars.mac_type != ELINK_MAC_TYPE_EMAC) {
2900 pstats = BNX2X_SP(sc, port_stats);
2901 /* reset old mac stats */
2902 memset(&(pstats->mac_stx[0]), 0,
2903 sizeof(struct mac_stx));
2906 if (sc->state == BNX2X_STATE_OPEN) {
2907 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
2911 if (sc->link_vars.link_up && sc->link_vars.line_speed) {
2912 cmng_fns = bnx2x_get_cmng_fns_mode(sc);
2914 if (cmng_fns != CMNG_FNS_NONE) {
2915 bnx2x_cmng_fns_init(sc, FALSE, cmng_fns);
2916 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
2920 bnx2x_link_report(sc);
2923 bnx2x_link_sync_notify(sc);
2927 static void bnx2x_attn_int_asserted(struct bnx2x_softc *sc, uint32_t asserted)
2929 int port = SC_PORT(sc);
2930 uint32_t aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2931 MISC_REG_AEU_MASK_ATTN_FUNC_0;
2932 uint32_t nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2933 NIG_REG_MASK_INTERRUPT_PORT0;
2935 uint32_t nig_mask = 0;
2940 if (sc->attn_state & asserted) {
2941 PMD_DRV_LOG(ERR, "IGU ERROR attn=0x%08x", asserted);
2944 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2946 aeu_mask = REG_RD(sc, aeu_addr);
2948 aeu_mask &= ~(asserted & 0x3ff);
2950 REG_WR(sc, aeu_addr, aeu_mask);
2952 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2954 sc->attn_state |= asserted;
2956 if (asserted & ATTN_HARD_WIRED_MASK) {
2957 if (asserted & ATTN_NIG_FOR_FUNC) {
2959 /* save nig interrupt mask */
2960 nig_mask = REG_RD(sc, nig_int_mask_addr);
2962 /* If nig_mask is not set, no need to call the update function */
2964 REG_WR(sc, nig_int_mask_addr, 0);
2966 bnx2x_link_attn(sc);
2969 /* handle unicore attn? */
2972 if (asserted & ATTN_SW_TIMER_4_FUNC) {
2973 PMD_DRV_LOG(DEBUG, "ATTN_SW_TIMER_4_FUNC!");
2976 if (asserted & GPIO_2_FUNC) {
2977 PMD_DRV_LOG(DEBUG, "GPIO_2_FUNC!");
2980 if (asserted & GPIO_3_FUNC) {
2981 PMD_DRV_LOG(DEBUG, "GPIO_3_FUNC!");
2984 if (asserted & GPIO_4_FUNC) {
2985 PMD_DRV_LOG(DEBUG, "GPIO_4_FUNC!");
2989 if (asserted & ATTN_GENERAL_ATTN_1) {
2990 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_1!");
2991 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
2993 if (asserted & ATTN_GENERAL_ATTN_2) {
2994 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_2!");
2995 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
2997 if (asserted & ATTN_GENERAL_ATTN_3) {
2998 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_3!");
2999 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3002 if (asserted & ATTN_GENERAL_ATTN_4) {
3003 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_4!");
3004 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3006 if (asserted & ATTN_GENERAL_ATTN_5) {
3007 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_5!");
3008 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3010 if (asserted & ATTN_GENERAL_ATTN_6) {
3011 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_6!");
3012 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3017 if (sc->devinfo.int_block == INT_BLOCK_HC) {
3019 (HC_REG_COMMAND_REG + port * 32 +
3020 COMMAND_REG_ATTN_BITS_SET);
3022 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER * 8);
3025 PMD_DRV_LOG(DEBUG, "about to mask 0x%08x at %s addr 0x%08x",
3027 (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
3029 REG_WR(sc, reg_addr, asserted);
3031 /* now set back the mask */
3032 if (asserted & ATTN_NIG_FOR_FUNC) {
3034 * Verify that IGU ack through BAR was written before restoring
3035 * NIG mask. This loop should exit after 2-3 iterations max.
3037 if (sc->devinfo.int_block != INT_BLOCK_HC) {
3042 REG_RD(sc, IGU_REG_ATTENTION_ACK_BITS);
3043 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0)
3044 && (++cnt < MAX_IGU_ATTN_ACK_TO));
3048 "Failed to verify IGU ack on time");
3054 REG_WR(sc, nig_int_mask_addr, nig_mask);
3060 bnx2x_print_next_block(__rte_unused struct bnx2x_softc *sc, __rte_unused int idx,
3061 __rte_unused const char *blk)
3063 PMD_DRV_LOG(INFO, "%s%s", idx ? ", " : "", blk);
3067 bnx2x_check_blocks_with_parity0(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3070 uint32_t cur_bit = 0;
3073 for (i = 0; sig; i++) {
3074 cur_bit = ((uint32_t) 0x1 << i);
3075 if (sig & cur_bit) {
3077 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3079 bnx2x_print_next_block(sc, par_num++,
3082 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3084 bnx2x_print_next_block(sc, par_num++,
3087 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3089 bnx2x_print_next_block(sc, par_num++,
3092 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3094 bnx2x_print_next_block(sc, par_num++,
3097 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3099 bnx2x_print_next_block(sc, par_num++,
3102 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3104 bnx2x_print_next_block(sc, par_num++,
3107 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3109 bnx2x_print_next_block(sc, par_num++,
3123 bnx2x_check_blocks_with_parity1(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3124 uint8_t * global, uint8_t print)
3127 uint32_t cur_bit = 0;
3128 for (i = 0; sig; i++) {
3129 cur_bit = ((uint32_t) 0x1 << i);
3130 if (sig & cur_bit) {
3132 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3134 bnx2x_print_next_block(sc, par_num++,
3137 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3139 bnx2x_print_next_block(sc, par_num++,
3142 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3144 bnx2x_print_next_block(sc, par_num++,
3147 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3149 bnx2x_print_next_block(sc, par_num++,
3152 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
3154 bnx2x_print_next_block(sc, par_num++,
3157 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3159 bnx2x_print_next_block(sc, par_num++,
3162 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3164 bnx2x_print_next_block(sc, par_num++,
3167 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
3169 bnx2x_print_next_block(sc, par_num++,
3172 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3174 bnx2x_print_next_block(sc, par_num++,
3178 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3180 bnx2x_print_next_block(sc, par_num++,
3183 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3185 bnx2x_print_next_block(sc, par_num++,
3188 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
3190 bnx2x_print_next_block(sc, par_num++,
3193 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3195 bnx2x_print_next_block(sc, par_num++,
3198 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3200 bnx2x_print_next_block(sc, par_num++,
3203 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3205 bnx2x_print_next_block(sc, par_num++,
3208 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
3210 bnx2x_print_next_block(sc, par_num++,
3224 bnx2x_check_blocks_with_parity2(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3227 uint32_t cur_bit = 0;
3230 for (i = 0; sig; i++) {
3231 cur_bit = ((uint32_t) 0x1 << i);
3232 if (sig & cur_bit) {
3234 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3236 bnx2x_print_next_block(sc, par_num++,
3239 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3241 bnx2x_print_next_block(sc, par_num++,
3244 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3246 bnx2x_print_next_block(sc, par_num++,
3247 "PXPPCICLOCKCLIENT");
3249 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3251 bnx2x_print_next_block(sc, par_num++,
3254 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3256 bnx2x_print_next_block(sc, par_num++,
3259 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
3261 bnx2x_print_next_block(sc, par_num++,
3264 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3266 bnx2x_print_next_block(sc, par_num++,
3269 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3271 bnx2x_print_next_block(sc, par_num++,
3285 bnx2x_check_blocks_with_parity3(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3286 uint8_t * global, uint8_t print)
3288 uint32_t cur_bit = 0;
3291 for (i = 0; sig; i++) {
3292 cur_bit = ((uint32_t) 0x1 << i);
3293 if (sig & cur_bit) {
3295 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3297 bnx2x_print_next_block(sc, par_num++,
3301 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3303 bnx2x_print_next_block(sc, par_num++,
3307 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3309 bnx2x_print_next_block(sc, par_num++,
3313 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3315 bnx2x_print_next_block(sc, par_num++,
3330 bnx2x_check_blocks_with_parity4(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3333 uint32_t cur_bit = 0;
3336 for (i = 0; sig; i++) {
3337 cur_bit = ((uint32_t) 0x1 << i);
3338 if (sig & cur_bit) {
3340 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
3342 bnx2x_print_next_block(sc, par_num++,
3345 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
3347 bnx2x_print_next_block(sc, par_num++,
3361 bnx2x_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print,
3366 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
3367 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
3368 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
3369 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
3370 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
3372 "Parity error: HW block parity attention:"
3373 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x",
3374 (uint32_t) (sig[0] & HW_PRTY_ASSERT_SET_0),
3375 (uint32_t) (sig[1] & HW_PRTY_ASSERT_SET_1),
3376 (uint32_t) (sig[2] & HW_PRTY_ASSERT_SET_2),
3377 (uint32_t) (sig[3] & HW_PRTY_ASSERT_SET_3),
3378 (uint32_t) (sig[4] & HW_PRTY_ASSERT_SET_4));
3381 PMD_DRV_LOG(INFO, "Parity errors detected in blocks: ");
3384 bnx2x_check_blocks_with_parity0(sc, sig[0] &
3385 HW_PRTY_ASSERT_SET_0,
3388 bnx2x_check_blocks_with_parity1(sc, sig[1] &
3389 HW_PRTY_ASSERT_SET_1,
3390 par_num, global, print);
3392 bnx2x_check_blocks_with_parity2(sc, sig[2] &
3393 HW_PRTY_ASSERT_SET_2,
3396 bnx2x_check_blocks_with_parity3(sc, sig[3] &
3397 HW_PRTY_ASSERT_SET_3,
3398 par_num, global, print);
3400 bnx2x_check_blocks_with_parity4(sc, sig[4] &
3401 HW_PRTY_ASSERT_SET_4,
3405 PMD_DRV_LOG(INFO, "");
3414 bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print)
3416 struct attn_route attn = { {0} };
3417 int port = SC_PORT(sc);
3419 attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
3420 attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
3421 attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
3422 attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
3424 if (!CHIP_IS_E1x(sc))
3426 REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
3428 return bnx2x_parity_attn(sc, global, print, attn.sig);
3431 static void bnx2x_attn_int_deasserted4(struct bnx2x_softc *sc, uint32_t attn)
3435 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
3436 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
3437 PMD_DRV_LOG(INFO, "ERROR: PGLUE hw attention 0x%08x", val);
3438 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
3440 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR");
3441 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
3443 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR");
3444 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
3446 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN");
3447 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
3449 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN");
3451 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
3453 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN");
3455 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
3457 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN");
3458 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
3460 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN");
3461 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
3463 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN");
3464 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
3466 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW");
3469 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
3470 val = REG_RD(sc, ATC_REG_ATC_INT_STS_CLR);
3471 PMD_DRV_LOG(INFO, "ERROR: ATC hw attention 0x%08x", val);
3472 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
3474 "ERROR: ATC_ATC_INT_STS_REG_ADDRESS_ERROR");
3475 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
3477 "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND");
3478 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
3480 "ERROR: ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS");
3481 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
3483 "ERROR: ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT");
3484 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
3486 "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR");
3487 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
3489 "ERROR: ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU");
3492 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3493 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
3495 "ERROR: FATAL parity attention set4 0x%08x",
3497 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
3499 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
3503 static void bnx2x_e1h_disable(struct bnx2x_softc *sc)
3505 int port = SC_PORT(sc);
3507 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
3510 static void bnx2x_e1h_enable(struct bnx2x_softc *sc)
3512 int port = SC_PORT(sc);
3514 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3518 * called due to MCP event (on pmf):
3519 * reread new bandwidth configuration
3521 * notify others function about the change
3523 static void bnx2x_config_mf_bw(struct bnx2x_softc *sc)
3525 if (sc->link_vars.link_up) {
3526 bnx2x_cmng_fns_init(sc, TRUE, CMNG_FNS_MINMAX);
3527 bnx2x_link_sync_notify(sc);
3530 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
3533 static void bnx2x_set_mf_bw(struct bnx2x_softc *sc)
3535 bnx2x_config_mf_bw(sc);
3536 bnx2x_fw_command(sc, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3539 static void bnx2x_handle_eee_event(struct bnx2x_softc *sc)
3541 bnx2x_fw_command(sc, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3544 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3546 static void bnx2x_drv_info_ether_stat(struct bnx2x_softc *sc)
3548 struct eth_stats_info *ether_stat = &sc->sp->drv_info_to_mcp.ether_stat;
3550 strncpy(ether_stat->version, BNX2X_DRIVER_VERSION,
3551 ETH_STAT_INFO_VERSION_LEN);
3553 sc->sp_objs[0].mac_obj.get_n_elements(sc, &sc->sp_objs[0].mac_obj,
3554 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3555 ether_stat->mac_local + MAC_PAD,
3558 ether_stat->mtu_size = sc->mtu;
3560 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3561 ether_stat->promiscuous_mode = 0; // (flags & PROMISC) ? 1 : 0;
3563 ether_stat->txq_size = sc->tx_ring_size;
3564 ether_stat->rxq_size = sc->rx_ring_size;
3567 static void bnx2x_handle_drv_info_req(struct bnx2x_softc *sc)
3569 enum drv_info_opcode op_code;
3570 uint32_t drv_info_ctl = SHMEM2_RD(sc, drv_info_control);
3572 /* if drv_info version supported by MFW doesn't match - send NACK */
3573 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3574 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3578 op_code = ((drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3579 DRV_INFO_CONTROL_OP_CODE_SHIFT);
3581 memset(&sc->sp->drv_info_to_mcp, 0, sizeof(union drv_info_to_mcp));
3584 case ETH_STATS_OPCODE:
3585 bnx2x_drv_info_ether_stat(sc);
3587 case FCOE_STATS_OPCODE:
3588 case ISCSI_STATS_OPCODE:
3590 /* if op code isn't supported - send NACK */
3591 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3596 * If we got drv_info attn from MFW then these fields are defined in
3599 SHMEM2_WR(sc, drv_info_host_addr_lo,
3600 U64_LO(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3601 SHMEM2_WR(sc, drv_info_host_addr_hi,
3602 U64_HI(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3604 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3607 static void bnx2x_dcc_event(struct bnx2x_softc *sc, uint32_t dcc_event)
3609 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3611 * This is the only place besides the function initialization
3612 * where the sc->flags can change so it is done without any
3616 mf_info.mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_DISABLED) {
3617 PMD_DRV_LOG(DEBUG, "mf_cfg function disabled");
3618 sc->flags |= BNX2X_MF_FUNC_DIS;
3619 bnx2x_e1h_disable(sc);
3621 PMD_DRV_LOG(DEBUG, "mf_cfg function enabled");
3622 sc->flags &= ~BNX2X_MF_FUNC_DIS;
3623 bnx2x_e1h_enable(sc);
3625 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3628 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3629 bnx2x_config_mf_bw(sc);
3630 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3633 /* Report results to MCP */
3635 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_FAILURE, 0);
3637 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_OK, 0);
3640 static void bnx2x_pmf_update(struct bnx2x_softc *sc)
3642 int port = SC_PORT(sc);
3648 * We need the mb() to ensure the ordering between the writing to
3649 * sc->port.pmf here and reading it from the bnx2x_periodic_task().
3653 /* enable nig attention */
3654 val = (0xff0f | (1 << (SC_VN(sc) + 4)));
3655 if (sc->devinfo.int_block == INT_BLOCK_HC) {
3656 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, val);
3657 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, val);
3658 } else if (!CHIP_IS_E1x(sc)) {
3659 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
3660 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
3663 bnx2x_stats_handle(sc, STATS_EVENT_PMF);
3666 static int bnx2x_mc_assert(struct bnx2x_softc *sc)
3670 __rte_unused uint32_t row0, row1, row2, row3;
3674 REG_RD8(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_INDEX_OFFSET);
3676 PMD_DRV_LOG(ERR, "XSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3678 /* print the asserts */
3679 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3683 BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i));
3686 BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3690 BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3694 BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3697 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3699 "XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3700 i, row3, row2, row1, row0);
3709 REG_RD8(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_INDEX_OFFSET);
3711 PMD_DRV_LOG(ERR, "TSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3714 /* print the asserts */
3715 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3719 BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i));
3722 BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3726 BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3730 BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3733 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3735 "TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3736 i, row3, row2, row1, row0);
3745 REG_RD8(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_INDEX_OFFSET);
3747 PMD_DRV_LOG(ERR, "CSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3750 /* print the asserts */
3751 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3755 BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i));
3758 BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3762 BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3766 BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3769 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3771 "CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3772 i, row3, row2, row1, row0);
3781 REG_RD8(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_INDEX_OFFSET);
3783 PMD_DRV_LOG(ERR, "USTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3786 /* print the asserts */
3787 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3791 BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i));
3794 BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3798 BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3802 BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3805 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3807 "USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3808 i, row3, row2, row1, row0);
3818 static void bnx2x_attn_int_deasserted3(struct bnx2x_softc *sc, uint32_t attn)
3820 int func = SC_FUNC(sc);
3823 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3825 if (attn & BNX2X_PMF_LINK_ASSERT(sc)) {
3827 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
3828 bnx2x_read_mf_cfg(sc);
3829 sc->devinfo.mf_info.mf_config[SC_VN(sc)] =
3831 func_mf_config[SC_ABS_FUNC(sc)].config);
3833 SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_status);
3835 if (val & DRV_STATUS_DCC_EVENT_MASK)
3838 DRV_STATUS_DCC_EVENT_MASK));
3840 if (val & DRV_STATUS_SET_MF_BW)
3841 bnx2x_set_mf_bw(sc);
3843 if (val & DRV_STATUS_DRV_INFO_REQ)
3844 bnx2x_handle_drv_info_req(sc);
3846 if ((sc->port.pmf == 0) && (val & DRV_STATUS_PMF))
3847 bnx2x_pmf_update(sc);
3849 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
3850 bnx2x_handle_eee_event(sc);
3852 if (sc->link_vars.periodic_flags &
3853 ELINK_PERIODIC_FLAGS_LINK_EVENT) {
3854 /* sync with link */
3855 sc->link_vars.periodic_flags &=
3856 ~ELINK_PERIODIC_FLAGS_LINK_EVENT;
3858 bnx2x_link_sync_notify(sc);
3860 bnx2x_link_report(sc);
3864 * Always call it here: bnx2x_link_report() will
3865 * prevent the link indication duplication.
3867 bnx2x_link_status_update(sc);
3869 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3871 PMD_DRV_LOG(ERR, "MC assert!");
3872 bnx2x_mc_assert(sc);
3873 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3874 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3875 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3876 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3877 rte_panic("MC assert!");
3879 } else if (attn & BNX2X_MCP_ASSERT) {
3881 PMD_DRV_LOG(ERR, "MCP assert!");
3882 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3886 "Unknown HW assert! (attn 0x%08x)", attn);
3890 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3891 PMD_DRV_LOG(ERR, "LATCHED attention 0x%08x (masked)", attn);
3892 if (attn & BNX2X_GRC_TIMEOUT) {
3893 val = REG_RD(sc, MISC_REG_GRC_TIMEOUT_ATTN);
3894 PMD_DRV_LOG(ERR, "GRC time-out 0x%08x", val);
3896 if (attn & BNX2X_GRC_RSV) {
3897 val = REG_RD(sc, MISC_REG_GRC_RSV_ATTN);
3898 PMD_DRV_LOG(ERR, "GRC reserved 0x%08x", val);
3900 REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3904 static void bnx2x_attn_int_deasserted2(struct bnx2x_softc *sc, uint32_t attn)
3906 int port = SC_PORT(sc);
3908 uint32_t val0, mask0, val1, mask1;
3911 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3912 val = REG_RD(sc, CFC_REG_CFC_INT_STS_CLR);
3913 PMD_DRV_LOG(ERR, "CFC hw attention 0x%08x", val);
3914 /* CFC error attention */
3916 PMD_DRV_LOG(ERR, "FATAL error from CFC");
3920 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3921 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_0);
3922 PMD_DRV_LOG(ERR, "PXP hw attention-0 0x%08x", val);
3923 /* RQ_USDMDP_FIFO_OVERFLOW */
3924 if (val & 0x18000) {
3925 PMD_DRV_LOG(ERR, "FATAL error from PXP");
3928 if (!CHIP_IS_E1x(sc)) {
3929 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_1);
3930 PMD_DRV_LOG(ERR, "PXP hw attention-1 0x%08x", val);
3933 #define PXP2_EOP_ERROR_BIT PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR
3934 #define AEU_PXP2_HW_INT_BIT AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT
3936 if (attn & AEU_PXP2_HW_INT_BIT) {
3937 /* CQ47854 workaround do not panic on
3938 * PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3940 if (!CHIP_IS_E1x(sc)) {
3941 mask0 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_0);
3942 val1 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_1);
3943 mask1 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_1);
3944 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_0);
3946 * If the olny PXP2_EOP_ERROR_BIT is set in
3947 * STS0 and STS1 - clear it
3949 * probably we lose additional attentions between
3950 * STS0 and STS_CLR0, in this case user will not
3951 * be notified about them
3953 if (val0 & mask0 & PXP2_EOP_ERROR_BIT &&
3955 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
3957 /* print the register, since no one can restore it */
3959 "PXP2_REG_PXP2_INT_STS_CLR_0 0x%08x", val0);
3962 * if PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3965 if (val0 & PXP2_EOP_ERROR_BIT) {
3966 PMD_DRV_LOG(ERR, "PXP2_WR_PGLUE_EOP_ERROR");
3969 * if only PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR is
3970 * set then clear attention from PXP2 block without panic
3972 if (((val0 & mask0) == PXP2_EOP_ERROR_BIT) &&
3973 ((val1 & mask1) == 0))
3974 attn &= ~AEU_PXP2_HW_INT_BIT;
3979 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3980 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3981 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3983 val = REG_RD(sc, reg_offset);
3984 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3985 REG_WR(sc, reg_offset, val);
3988 "FATAL HW block attention set2 0x%x",
3989 (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_2));
3990 rte_panic("HW block attention set2");
3994 static void bnx2x_attn_int_deasserted1(struct bnx2x_softc *sc, uint32_t attn)
3996 int port = SC_PORT(sc);
4000 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
4001 val = REG_RD(sc, DORQ_REG_DORQ_INT_STS_CLR);
4002 PMD_DRV_LOG(ERR, "DB hw attention 0x%08x", val);
4003 /* DORQ discard attention */
4005 PMD_DRV_LOG(ERR, "FATAL error from DORQ");
4009 if (attn & HW_INTERRUT_ASSERT_SET_1) {
4010 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4011 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4013 val = REG_RD(sc, reg_offset);
4014 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4015 REG_WR(sc, reg_offset, val);
4018 "FATAL HW block attention set1 0x%08x",
4019 (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_1));
4020 rte_panic("HW block attention set1");
4024 static void bnx2x_attn_int_deasserted0(struct bnx2x_softc *sc, uint32_t attn)
4026 int port = SC_PORT(sc);
4030 reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4031 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
4033 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4034 val = REG_RD(sc, reg_offset);
4035 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4036 REG_WR(sc, reg_offset, val);
4038 PMD_DRV_LOG(WARNING, "SPIO5 hw attention");
4040 /* Fan failure attention */
4041 elink_hw_reset_phy(&sc->link_params);
4042 bnx2x_fan_failure(sc);
4045 if ((attn & sc->link_vars.aeu_int_mask) && sc->port.pmf) {
4046 elink_handle_module_detect_int(&sc->link_params);
4049 if (attn & HW_INTERRUT_ASSERT_SET_0) {
4050 val = REG_RD(sc, reg_offset);
4051 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4052 REG_WR(sc, reg_offset, val);
4054 rte_panic("FATAL HW block attention set0 0x%lx",
4055 (attn & HW_INTERRUT_ASSERT_SET_0));
4059 static void bnx2x_attn_int_deasserted(struct bnx2x_softc *sc, uint32_t deasserted)
4061 struct attn_route attn;
4062 struct attn_route *group_mask;
4063 int port = SC_PORT(sc);
4068 uint8_t global = FALSE;
4071 * Need to take HW lock because MCP or other port might also
4072 * try to handle this event.
4074 bnx2x_acquire_alr(sc);
4076 if (bnx2x_chk_parity_attn(sc, &global, TRUE)) {
4077 sc->recovery_state = BNX2X_RECOVERY_INIT;
4079 /* disable HW interrupts */
4080 bnx2x_int_disable(sc);
4081 bnx2x_release_alr(sc);
4085 attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
4086 attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
4087 attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
4088 attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
4089 if (!CHIP_IS_E1x(sc)) {
4091 REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
4096 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4097 if (deasserted & (1 << index)) {
4098 group_mask = &sc->attn_group[index];
4100 bnx2x_attn_int_deasserted4(sc,
4102 sig[4] & group_mask->sig[4]);
4103 bnx2x_attn_int_deasserted3(sc,
4105 sig[3] & group_mask->sig[3]);
4106 bnx2x_attn_int_deasserted1(sc,
4108 sig[1] & group_mask->sig[1]);
4109 bnx2x_attn_int_deasserted2(sc,
4111 sig[2] & group_mask->sig[2]);
4112 bnx2x_attn_int_deasserted0(sc,
4114 sig[0] & group_mask->sig[0]);
4118 bnx2x_release_alr(sc);
4120 if (sc->devinfo.int_block == INT_BLOCK_HC) {
4121 reg_addr = (HC_REG_COMMAND_REG + port * 32 +
4122 COMMAND_REG_ATTN_BITS_CLR);
4124 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER * 8);
4129 "about to mask 0x%08x at %s addr 0x%08x", val,
4130 (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
4132 REG_WR(sc, reg_addr, val);
4134 if (~sc->attn_state & deasserted) {
4135 PMD_DRV_LOG(ERR, "IGU error");
4138 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4139 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4141 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4143 aeu_mask = REG_RD(sc, reg_addr);
4145 aeu_mask |= (deasserted & 0x3ff);
4147 REG_WR(sc, reg_addr, aeu_mask);
4148 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4150 sc->attn_state &= ~deasserted;
4153 static void bnx2x_attn_int(struct bnx2x_softc *sc)
4155 /* read local copy of bits */
4156 uint32_t attn_bits = le32toh(sc->def_sb->atten_status_block.attn_bits);
4158 le32toh(sc->def_sb->atten_status_block.attn_bits_ack);
4159 uint32_t attn_state = sc->attn_state;
4161 /* look for changed bits */
4162 uint32_t asserted = attn_bits & ~attn_ack & ~attn_state;
4163 uint32_t deasserted = ~attn_bits & attn_ack & attn_state;
4166 "attn_bits 0x%08x attn_ack 0x%08x asserted 0x%08x deasserted 0x%08x",
4167 attn_bits, attn_ack, asserted, deasserted);
4169 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) {
4170 PMD_DRV_LOG(ERR, "BAD attention state");
4173 /* handle bits that were raised */
4175 bnx2x_attn_int_asserted(sc, asserted);
4179 bnx2x_attn_int_deasserted(sc, deasserted);
4183 static uint16_t bnx2x_update_dsb_idx(struct bnx2x_softc *sc)
4185 struct host_sp_status_block *def_sb = sc->def_sb;
4188 mb(); /* status block is written to by the chip */
4190 if (sc->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
4191 sc->def_att_idx = def_sb->atten_status_block.attn_bits_index;
4192 rc |= BNX2X_DEF_SB_ATT_IDX;
4195 if (sc->def_idx != def_sb->sp_sb.running_index) {
4196 sc->def_idx = def_sb->sp_sb.running_index;
4197 rc |= BNX2X_DEF_SB_IDX;
4205 static struct ecore_queue_sp_obj *bnx2x_cid_to_q_obj(struct bnx2x_softc *sc,
4208 return &sc->sp_objs[CID_TO_FP(cid, sc)].q_obj;
4211 static void bnx2x_handle_mcast_eqe(struct bnx2x_softc *sc)
4213 struct ecore_mcast_ramrod_params rparam;
4216 memset(&rparam, 0, sizeof(rparam));
4218 rparam.mcast_obj = &sc->mcast_obj;
4220 /* clear pending state for the last command */
4221 sc->mcast_obj.raw.clear_pending(&sc->mcast_obj.raw);
4223 /* if there are pending mcast commands - send them */
4224 if (sc->mcast_obj.check_pending(&sc->mcast_obj)) {
4225 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
4228 "Failed to send pending mcast commands (%d)",
4235 bnx2x_handle_classification_eqe(struct bnx2x_softc *sc, union event_ring_elem *elem)
4237 unsigned long ramrod_flags = 0;
4239 uint32_t cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4240 struct ecore_vlan_mac_obj *vlan_mac_obj;
4242 /* always push next commands out, don't wait here */
4243 bnx2x_set_bit(RAMROD_CONT, &ramrod_flags);
4245 switch (le32toh(elem->message.data.eth_event.echo) >> BNX2X_SWCID_SHIFT) {
4246 case ECORE_FILTER_MAC_PENDING:
4247 PMD_DRV_LOG(DEBUG, "Got SETUP_MAC completions");
4248 vlan_mac_obj = &sc->sp_objs[cid].mac_obj;
4251 case ECORE_FILTER_MCAST_PENDING:
4252 PMD_DRV_LOG(DEBUG, "Got SETUP_MCAST completions");
4253 bnx2x_handle_mcast_eqe(sc);
4257 PMD_DRV_LOG(NOTICE, "Unsupported classification command: %d",
4258 elem->message.data.eth_event.echo);
4262 rc = vlan_mac_obj->complete(sc, vlan_mac_obj, elem, &ramrod_flags);
4265 PMD_DRV_LOG(NOTICE, "Failed to schedule new commands (%d)", rc);
4266 } else if (rc > 0) {
4267 PMD_DRV_LOG(DEBUG, "Scheduled next pending commands...");
4271 static void bnx2x_handle_rx_mode_eqe(struct bnx2x_softc *sc)
4273 bnx2x_clear_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
4275 /* send rx_mode command again if was requested */
4276 if (bnx2x_test_and_clear_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state)) {
4277 bnx2x_set_storm_rx_mode(sc);
4281 static void bnx2x_update_eq_prod(struct bnx2x_softc *sc, uint16_t prod)
4283 storm_memset_eq_prod(sc, prod, SC_FUNC(sc));
4284 wmb(); /* keep prod updates ordered */
4287 static void bnx2x_eq_int(struct bnx2x_softc *sc)
4289 uint16_t hw_cons, sw_cons, sw_prod;
4290 union event_ring_elem *elem;
4295 struct ecore_queue_sp_obj *q_obj;
4296 struct ecore_func_sp_obj *f_obj = &sc->func_obj;
4297 struct ecore_raw_obj *rss_raw = &sc->rss_conf_obj.raw;
4299 hw_cons = le16toh(*sc->eq_cons_sb);
4302 * The hw_cons range is 1-255, 257 - the sw_cons range is 0-254, 256.
4303 * when we get to the next-page we need to adjust so the loop
4304 * condition below will be met. The next element is the size of a
4305 * regular element and hence incrementing by 1
4307 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) {
4312 * This function may never run in parallel with itself for a
4313 * specific sc and no need for a read memory barrier here.
4315 sw_cons = sc->eq_cons;
4316 sw_prod = sc->eq_prod;
4320 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4322 elem = &sc->eq[EQ_DESC(sw_cons)];
4324 /* elem CID originates from FW, actually LE */
4325 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4326 opcode = elem->message.opcode;
4328 /* handle eq element */
4330 case EVENT_RING_OPCODE_STAT_QUERY:
4331 PMD_DEBUG_PERIODIC_LOG(DEBUG, "got statistics completion event %d",
4333 /* nothing to do with stats comp */
4336 case EVENT_RING_OPCODE_CFC_DEL:
4337 /* handle according to cid range */
4338 /* we may want to verify here that the sc state is HALTING */
4339 PMD_DRV_LOG(DEBUG, "got delete ramrod for MULTI[%d]",
4341 q_obj = bnx2x_cid_to_q_obj(sc, cid);
4342 if (q_obj->complete_cmd(sc, q_obj, ECORE_Q_CMD_CFC_DEL)) {
4347 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4348 PMD_DRV_LOG(DEBUG, "got STOP TRAFFIC");
4349 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_STOP)) {
4354 case EVENT_RING_OPCODE_START_TRAFFIC:
4355 PMD_DRV_LOG(DEBUG, "got START TRAFFIC");
4356 if (f_obj->complete_cmd
4357 (sc, f_obj, ECORE_F_CMD_TX_START)) {
4362 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
4363 echo = elem->message.data.function_update_event.echo;
4364 if (echo == SWITCH_UPDATE) {
4366 "got FUNC_SWITCH_UPDATE ramrod");
4367 if (f_obj->complete_cmd(sc, f_obj,
4368 ECORE_F_CMD_SWITCH_UPDATE))
4374 "AFEX: ramrod completed FUNCTION_UPDATE");
4375 f_obj->complete_cmd(sc, f_obj,
4376 ECORE_F_CMD_AFEX_UPDATE);
4380 case EVENT_RING_OPCODE_FORWARD_SETUP:
4381 q_obj = &bnx2x_fwd_sp_obj(sc, q_obj);
4382 if (q_obj->complete_cmd(sc, q_obj,
4383 ECORE_Q_CMD_SETUP_TX_ONLY)) {
4388 case EVENT_RING_OPCODE_FUNCTION_START:
4389 PMD_DRV_LOG(DEBUG, "got FUNC_START ramrod");
4390 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_START)) {
4395 case EVENT_RING_OPCODE_FUNCTION_STOP:
4396 PMD_DRV_LOG(DEBUG, "got FUNC_STOP ramrod");
4397 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_STOP)) {
4403 switch (opcode | sc->state) {
4404 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPEN):
4405 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPENING_WAITING_PORT):
4407 elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4408 PMD_DRV_LOG(DEBUG, "got RSS_UPDATE ramrod. CID %d",
4410 rss_raw->clear_pending(rss_raw);
4413 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4414 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4415 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_CLOSING_WAITING_HALT):
4416 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_OPEN):
4417 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_DIAG):
4418 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4420 "got (un)set mac ramrod");
4421 bnx2x_handle_classification_eqe(sc, elem);
4424 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_OPEN):
4425 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_DIAG):
4426 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4428 "got mcast ramrod");
4429 bnx2x_handle_mcast_eqe(sc);
4432 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_OPEN):
4433 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_DIAG):
4434 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4436 "got rx_mode ramrod");
4437 bnx2x_handle_rx_mode_eqe(sc);
4441 /* unknown event log error and continue */
4442 PMD_DRV_LOG(INFO, "Unknown EQ event %d, sc->state 0x%x",
4443 elem->message.opcode, sc->state);
4451 atomic_add_acq_long(&sc->eq_spq_left, spqe_cnt);
4453 sc->eq_cons = sw_cons;
4454 sc->eq_prod = sw_prod;
4456 /* make sure that above mem writes were issued towards the memory */
4459 /* update producer */
4460 bnx2x_update_eq_prod(sc, sc->eq_prod);
4463 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc)
4468 /* what work needs to be performed? */
4469 status = bnx2x_update_dsb_idx(sc);
4472 if (status & BNX2X_DEF_SB_ATT_IDX) {
4473 PMD_DRV_LOG(DEBUG, "---> ATTN INTR <---");
4475 status &= ~BNX2X_DEF_SB_ATT_IDX;
4479 /* SP events: STAT_QUERY and others */
4480 if (status & BNX2X_DEF_SB_IDX) {
4481 /* handle EQ completions */
4482 PMD_DEBUG_PERIODIC_LOG(DEBUG, "---> EQ INTR <---");
4484 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
4485 le16toh(sc->def_idx), IGU_INT_NOP, 1);
4486 status &= ~BNX2X_DEF_SB_IDX;
4489 /* if status is non zero then something went wrong */
4490 if (unlikely(status)) {
4492 "Got an unknown SP interrupt! (0x%04x)", status);
4495 /* ack status block only if something was actually handled */
4496 bnx2x_ack_sb(sc, sc->igu_dsb_id, ATTENTION_ID,
4497 le16toh(sc->def_att_idx), IGU_INT_ENABLE, 1);
4502 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp, int scan_fp)
4504 struct bnx2x_softc *sc = fp->sc;
4505 uint8_t more_rx = FALSE;
4507 /* update the fastpath index */
4508 bnx2x_update_fp_sb_idx(fp);
4511 if (bnx2x_has_rx_work(fp)) {
4512 more_rx = bnx2x_rxeof(sc, fp);
4516 /* still more work to do */
4517 bnx2x_handle_fp_tq(fp, scan_fp);
4522 bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
4523 le16toh(fp->fp_hc_idx), IGU_INT_ENABLE, 1);
4527 * Legacy interrupt entry point.
4529 * Verifies that the controller generated the interrupt and
4530 * then calls a separate routine to handle the various
4531 * interrupt causes: link, RX, and TX.
4533 int bnx2x_intr_legacy(struct bnx2x_softc *sc, int scan_fp)
4535 struct bnx2x_fastpath *fp;
4536 uint32_t status, mask;
4540 * 0 for ustorm, 1 for cstorm
4541 * the bits returned from ack_int() are 0-15
4542 * bit 0 = attention status block
4543 * bit 1 = fast path status block
4544 * a mask of 0x2 or more = tx/rx event
4545 * a mask of 1 = slow path event
4548 status = bnx2x_ack_int(sc);
4550 /* the interrupt is not for us */
4551 if (unlikely(status == 0)) {
4555 PMD_DEBUG_PERIODIC_LOG(DEBUG, "Interrupt status 0x%04x", status);
4556 //bnx2x_dump_status_block(sc);
4558 FOR_EACH_ETH_QUEUE(sc, i) {
4560 mask = (0x2 << (fp->index + CNIC_SUPPORT(sc)));
4561 if (status & mask) {
4562 bnx2x_handle_fp_tq(fp, scan_fp);
4567 if (unlikely(status & 0x1)) {
4568 rc = bnx2x_handle_sp_tq(sc);
4572 if (unlikely(status)) {
4573 PMD_DRV_LOG(WARNING,
4574 "Unexpected fastpath status (0x%08x)!", status);
4580 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc);
4581 static int bnx2x_init_hw_common(struct bnx2x_softc *sc);
4582 static int bnx2x_init_hw_port(struct bnx2x_softc *sc);
4583 static int bnx2x_init_hw_func(struct bnx2x_softc *sc);
4584 static void bnx2x_reset_common(struct bnx2x_softc *sc);
4585 static void bnx2x_reset_port(struct bnx2x_softc *sc);
4586 static void bnx2x_reset_func(struct bnx2x_softc *sc);
4587 static int bnx2x_init_firmware(struct bnx2x_softc *sc);
4588 static void bnx2x_release_firmware(struct bnx2x_softc *sc);
4591 ecore_func_sp_drv_ops bnx2x_func_sp_drv = {
4592 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
4593 .init_hw_cmn = bnx2x_init_hw_common,
4594 .init_hw_port = bnx2x_init_hw_port,
4595 .init_hw_func = bnx2x_init_hw_func,
4597 .reset_hw_cmn = bnx2x_reset_common,
4598 .reset_hw_port = bnx2x_reset_port,
4599 .reset_hw_func = bnx2x_reset_func,
4601 .init_fw = bnx2x_init_firmware,
4602 .release_fw = bnx2x_release_firmware,
4605 static void bnx2x_init_func_obj(struct bnx2x_softc *sc)
4609 PMD_INIT_FUNC_TRACE();
4611 ecore_init_func_obj(sc,
4613 BNX2X_SP(sc, func_rdata),
4614 (phys_addr_t)BNX2X_SP_MAPPING(sc, func_rdata),
4615 BNX2X_SP(sc, func_afex_rdata),
4616 (phys_addr_t)BNX2X_SP_MAPPING(sc, func_afex_rdata),
4617 &bnx2x_func_sp_drv);
4620 static int bnx2x_init_hw(struct bnx2x_softc *sc, uint32_t load_code)
4622 struct ecore_func_state_params func_params = { NULL };
4625 PMD_INIT_FUNC_TRACE();
4627 /* prepare the parameters for function state transitions */
4628 bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
4630 func_params.f_obj = &sc->func_obj;
4631 func_params.cmd = ECORE_F_CMD_HW_INIT;
4633 func_params.params.hw_init.load_phase = load_code;
4636 * Via a plethora of function pointers, we will eventually reach
4637 * bnx2x_init_hw_common(), bnx2x_init_hw_port(), or bnx2x_init_hw_func().
4639 rc = ecore_func_state_change(sc, &func_params);
4645 bnx2x_fill(struct bnx2x_softc *sc, uint32_t addr, int fill, uint32_t len)
4649 if (!(len % 4) && !(addr % 4)) {
4650 for (i = 0; i < len; i += 4) {
4651 REG_WR(sc, (addr + i), fill);
4654 for (i = 0; i < len; i++) {
4655 REG_WR8(sc, (addr + i), fill);
4660 /* writes FP SP data to FW - data_size in dwords */
4662 bnx2x_wr_fp_sb_data(struct bnx2x_softc *sc, int fw_sb_id, uint32_t * sb_data_p,
4667 for (index = 0; index < data_size; index++) {
4669 (BAR_CSTRORM_INTMEM +
4670 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
4671 (sizeof(uint32_t) * index)), *(sb_data_p + index));
4675 static void bnx2x_zero_fp_sb(struct bnx2x_softc *sc, int fw_sb_id)
4677 struct hc_status_block_data_e2 sb_data_e2;
4678 struct hc_status_block_data_e1x sb_data_e1x;
4679 uint32_t *sb_data_p;
4680 uint32_t data_size = 0;
4682 if (!CHIP_IS_E1x(sc)) {
4683 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4684 sb_data_e2.common.state = SB_DISABLED;
4685 sb_data_e2.common.p_func.vf_valid = FALSE;
4686 sb_data_p = (uint32_t *) & sb_data_e2;
4687 data_size = (sizeof(struct hc_status_block_data_e2) /
4690 memset(&sb_data_e1x, 0,
4691 sizeof(struct hc_status_block_data_e1x));
4692 sb_data_e1x.common.state = SB_DISABLED;
4693 sb_data_e1x.common.p_func.vf_valid = FALSE;
4694 sb_data_p = (uint32_t *) & sb_data_e1x;
4695 data_size = (sizeof(struct hc_status_block_data_e1x) /
4699 bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4702 (BAR_CSTRORM_INTMEM + CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id)), 0,
4703 CSTORM_STATUS_BLOCK_SIZE);
4704 bnx2x_fill(sc, (BAR_CSTRORM_INTMEM + CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id)),
4705 0, CSTORM_SYNC_BLOCK_SIZE);
4709 bnx2x_wr_sp_sb_data(struct bnx2x_softc *sc,
4710 struct hc_sp_status_block_data *sp_sb_data)
4715 i < (sizeof(struct hc_sp_status_block_data) / sizeof(uint32_t));
4718 (BAR_CSTRORM_INTMEM +
4719 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(SC_FUNC(sc)) +
4720 (i * sizeof(uint32_t))),
4721 *((uint32_t *) sp_sb_data + i));
4725 static void bnx2x_zero_sp_sb(struct bnx2x_softc *sc)
4727 struct hc_sp_status_block_data sp_sb_data;
4729 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4731 sp_sb_data.state = SB_DISABLED;
4732 sp_sb_data.p_func.vf_valid = FALSE;
4734 bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
4737 (BAR_CSTRORM_INTMEM +
4738 CSTORM_SP_STATUS_BLOCK_OFFSET(SC_FUNC(sc))),
4739 0, CSTORM_SP_STATUS_BLOCK_SIZE);
4741 (BAR_CSTRORM_INTMEM +
4742 CSTORM_SP_SYNC_BLOCK_OFFSET(SC_FUNC(sc))),
4743 0, CSTORM_SP_SYNC_BLOCK_SIZE);
4747 bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, int igu_sb_id,
4750 hc_sm->igu_sb_id = igu_sb_id;
4751 hc_sm->igu_seg_id = igu_seg_id;
4752 hc_sm->timer_value = 0xFF;
4753 hc_sm->time_to_expire = 0xFFFFFFFF;
4756 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
4758 /* zero out state machine indices */
4761 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4764 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4765 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
4766 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
4767 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
4772 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
4773 (SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4776 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
4777 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4778 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
4779 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4780 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
4781 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4782 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
4783 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4787 bnx2x_init_sb(struct bnx2x_softc *sc, phys_addr_t busaddr, int vfid,
4788 uint8_t vf_valid, int fw_sb_id, int igu_sb_id)
4790 struct hc_status_block_data_e2 sb_data_e2;
4791 struct hc_status_block_data_e1x sb_data_e1x;
4792 struct hc_status_block_sm *hc_sm_p;
4793 uint32_t *sb_data_p;
4797 if (CHIP_INT_MODE_IS_BC(sc)) {
4798 igu_seg_id = HC_SEG_ACCESS_NORM;
4800 igu_seg_id = IGU_SEG_ACCESS_NORM;
4803 bnx2x_zero_fp_sb(sc, fw_sb_id);
4805 if (!CHIP_IS_E1x(sc)) {
4806 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4807 sb_data_e2.common.state = SB_ENABLED;
4808 sb_data_e2.common.p_func.pf_id = SC_FUNC(sc);
4809 sb_data_e2.common.p_func.vf_id = vfid;
4810 sb_data_e2.common.p_func.vf_valid = vf_valid;
4811 sb_data_e2.common.p_func.vnic_id = SC_VN(sc);
4812 sb_data_e2.common.same_igu_sb_1b = TRUE;
4813 sb_data_e2.common.host_sb_addr.hi = U64_HI(busaddr);
4814 sb_data_e2.common.host_sb_addr.lo = U64_LO(busaddr);
4815 hc_sm_p = sb_data_e2.common.state_machine;
4816 sb_data_p = (uint32_t *) & sb_data_e2;
4817 data_size = (sizeof(struct hc_status_block_data_e2) /
4819 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
4821 memset(&sb_data_e1x, 0,
4822 sizeof(struct hc_status_block_data_e1x));
4823 sb_data_e1x.common.state = SB_ENABLED;
4824 sb_data_e1x.common.p_func.pf_id = SC_FUNC(sc);
4825 sb_data_e1x.common.p_func.vf_id = 0xff;
4826 sb_data_e1x.common.p_func.vf_valid = FALSE;
4827 sb_data_e1x.common.p_func.vnic_id = SC_VN(sc);
4828 sb_data_e1x.common.same_igu_sb_1b = TRUE;
4829 sb_data_e1x.common.host_sb_addr.hi = U64_HI(busaddr);
4830 sb_data_e1x.common.host_sb_addr.lo = U64_LO(busaddr);
4831 hc_sm_p = sb_data_e1x.common.state_machine;
4832 sb_data_p = (uint32_t *) & sb_data_e1x;
4833 data_size = (sizeof(struct hc_status_block_data_e1x) /
4835 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
4838 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], igu_sb_id, igu_seg_id);
4839 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], igu_sb_id, igu_seg_id);
4841 /* write indices to HW - PCI guarantees endianity of regpairs */
4842 bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4845 static uint8_t bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp)
4847 if (CHIP_IS_E1x(fp->sc)) {
4848 return fp->cl_id + SC_PORT(fp->sc) * ETH_MAX_RX_CLIENTS_E1H;
4855 bnx2x_rx_ustorm_prods_offset(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
4857 uint32_t offset = BAR_USTRORM_INTMEM;
4860 return PXP_VF_ADDR_USDM_QUEUES_START +
4861 (sc->acquire_resp.resc.hw_qid[fp->index] *
4862 sizeof(struct ustorm_queue_zone_data));
4863 } else if (!CHIP_IS_E1x(sc)) {
4864 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
4866 offset += USTORM_RX_PRODS_E1X_OFFSET(SC_PORT(sc), fp->cl_id);
4872 static void bnx2x_init_eth_fp(struct bnx2x_softc *sc, int idx)
4874 struct bnx2x_fastpath *fp = &sc->fp[idx];
4875 uint32_t cids[ECORE_MULTI_TX_COS] = { 0 };
4876 unsigned long q_type = 0;
4882 fp->igu_sb_id = (sc->igu_base_sb + idx + CNIC_SUPPORT(sc));
4883 fp->fw_sb_id = (sc->base_fw_ndsb + idx + CNIC_SUPPORT(sc));
4885 if (CHIP_IS_E1x(sc))
4886 fp->cl_id = SC_L_ID(sc) + idx;
4888 /* want client ID same as IGU SB ID for non-E1 */
4889 fp->cl_id = fp->igu_sb_id;
4890 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
4892 /* setup sb indices */
4893 if (!CHIP_IS_E1x(sc)) {
4894 fp->sb_index_values = fp->status_block.e2_sb->sb.index_values;
4895 fp->sb_running_index = fp->status_block.e2_sb->sb.running_index;
4897 fp->sb_index_values = fp->status_block.e1x_sb->sb.index_values;
4898 fp->sb_running_index =
4899 fp->status_block.e1x_sb->sb.running_index;
4903 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(sc, fp);
4905 fp->rx_cq_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS];
4907 for (cos = 0; cos < sc->max_cos; cos++) {
4910 fp->tx_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0];
4912 /* nothing more for a VF to do */
4917 bnx2x_init_sb(sc, fp->sb_dma.paddr, BNX2X_VF_ID_INVALID, FALSE,
4918 fp->fw_sb_id, fp->igu_sb_id);
4920 bnx2x_update_fp_sb_idx(fp);
4922 /* Configure Queue State object */
4923 bnx2x_set_bit(ECORE_Q_TYPE_HAS_RX, &q_type);
4924 bnx2x_set_bit(ECORE_Q_TYPE_HAS_TX, &q_type);
4926 ecore_init_queue_obj(sc,
4927 &sc->sp_objs[idx].q_obj,
4932 BNX2X_SP(sc, q_rdata),
4933 (phys_addr_t)BNX2X_SP_MAPPING(sc, q_rdata),
4936 /* configure classification DBs */
4937 ecore_init_mac_obj(sc,
4938 &sc->sp_objs[idx].mac_obj,
4942 BNX2X_SP(sc, mac_rdata),
4943 (phys_addr_t)BNX2X_SP_MAPPING(sc, mac_rdata),
4944 ECORE_FILTER_MAC_PENDING, &sc->sp_state,
4945 ECORE_OBJ_TYPE_RX_TX, &sc->macs_pool);
4949 bnx2x_update_rx_prod(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
4950 uint16_t rx_bd_prod, uint16_t rx_cq_prod)
4952 union ustorm_eth_rx_producers rx_prods;
4955 /* update producers */
4956 rx_prods.prod.bd_prod = rx_bd_prod;
4957 rx_prods.prod.cqe_prod = rx_cq_prod;
4958 rx_prods.prod.reserved = 0;
4961 * Make sure that the BD and SGE data is updated before updating the
4962 * producers since FW might read the BD/SGE right after the producer
4964 * This is only applicable for weak-ordered memory model archs such
4965 * as IA-64. The following barrier is also mandatory since FW will
4966 * assumes BDs must have buffers.
4970 for (i = 0; i < (sizeof(rx_prods) / 4); i++) {
4972 (fp->ustorm_rx_prods_offset + (i * 4)),
4973 rx_prods.raw_data[i]);
4976 wmb(); /* keep prod updates ordered */
4979 static void bnx2x_init_rx_rings(struct bnx2x_softc *sc)
4981 struct bnx2x_fastpath *fp;
4983 struct bnx2x_rx_queue *rxq;
4985 for (i = 0; i < sc->num_queues; i++) {
4987 rxq = sc->rx_queues[fp->index];
4989 PMD_RX_LOG(ERR, "RX queue is NULL");
4993 rxq->rx_bd_head = 0;
4994 rxq->rx_bd_tail = rxq->nb_rx_desc;
4995 rxq->rx_cq_head = 0;
4996 rxq->rx_cq_tail = TOTAL_RCQ_ENTRIES(rxq);
4997 *fp->rx_cq_cons_sb = 0;
5000 * Activate the BD ring...
5001 * Warning, this will generate an interrupt (to the TSTORM)
5002 * so this can only be done after the chip is initialized
5004 bnx2x_update_rx_prod(sc, fp, rxq->rx_bd_tail, rxq->rx_cq_tail);
5012 static void bnx2x_init_tx_ring_one(struct bnx2x_fastpath *fp)
5014 struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
5016 fp->tx_db.data.header.header = 1 << DOORBELL_HDR_DB_TYPE_SHIFT;
5017 fp->tx_db.data.zero_fill1 = 0;
5018 fp->tx_db.data.prod = 0;
5021 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
5025 txq->tx_pkt_tail = 0;
5026 txq->tx_pkt_head = 0;
5027 txq->tx_bd_tail = 0;
5028 txq->tx_bd_head = 0;
5031 static void bnx2x_init_tx_rings(struct bnx2x_softc *sc)
5035 for (i = 0; i < sc->num_queues; i++) {
5036 bnx2x_init_tx_ring_one(&sc->fp[i]);
5040 static void bnx2x_init_def_sb(struct bnx2x_softc *sc)
5042 struct host_sp_status_block *def_sb = sc->def_sb;
5043 phys_addr_t mapping = sc->def_sb_dma.paddr;
5044 int igu_sp_sb_index;
5046 int port = SC_PORT(sc);
5047 int func = SC_FUNC(sc);
5048 int reg_offset, reg_offset_en5;
5051 struct hc_sp_status_block_data sp_sb_data;
5053 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5055 if (CHIP_INT_MODE_IS_BC(sc)) {
5056 igu_sp_sb_index = DEF_SB_IGU_ID;
5057 igu_seg_id = HC_SEG_ACCESS_DEF;
5059 igu_sp_sb_index = sc->igu_dsb_id;
5060 igu_seg_id = IGU_SEG_ACCESS_DEF;
5064 section = ((uint64_t) mapping +
5065 offsetof(struct host_sp_status_block, atten_status_block));
5066 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5069 reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5070 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
5072 reg_offset_en5 = (port) ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5073 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0;
5075 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5076 /* take care of sig[0]..sig[4] */
5077 for (sindex = 0; sindex < 4; sindex++) {
5078 sc->attn_group[index].sig[sindex] =
5080 (reg_offset + (sindex * 0x4) +
5084 if (!CHIP_IS_E1x(sc)) {
5086 * enable5 is separate from the rest of the registers,
5087 * and the address skip is 4 and not 16 between the
5090 sc->attn_group[index].sig[4] =
5091 REG_RD(sc, (reg_offset_en5 + (0x4 * index)));
5093 sc->attn_group[index].sig[4] = 0;
5097 if (sc->devinfo.int_block == INT_BLOCK_HC) {
5099 port ? HC_REG_ATTN_MSG1_ADDR_L : HC_REG_ATTN_MSG0_ADDR_L;
5100 REG_WR(sc, reg_offset, U64_LO(section));
5101 REG_WR(sc, (reg_offset + 4), U64_HI(section));
5102 } else if (!CHIP_IS_E1x(sc)) {
5103 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5104 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5107 section = ((uint64_t) mapping +
5108 offsetof(struct host_sp_status_block, sp_sb));
5110 bnx2x_zero_sp_sb(sc);
5112 /* PCI guarantees endianity of regpair */
5113 sp_sb_data.state = SB_ENABLED;
5114 sp_sb_data.host_sb_addr.lo = U64_LO(section);
5115 sp_sb_data.host_sb_addr.hi = U64_HI(section);
5116 sp_sb_data.igu_sb_id = igu_sp_sb_index;
5117 sp_sb_data.igu_seg_id = igu_seg_id;
5118 sp_sb_data.p_func.pf_id = func;
5119 sp_sb_data.p_func.vnic_id = SC_VN(sc);
5120 sp_sb_data.p_func.vf_id = 0xff;
5122 bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
5124 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5127 static void bnx2x_init_sp_ring(struct bnx2x_softc *sc)
5129 atomic_store_rel_long(&sc->cq_spq_left, MAX_SPQ_PENDING);
5130 sc->spq_prod_idx = 0;
5132 &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_ETH_DEF_CONS];
5133 sc->spq_prod_bd = sc->spq;
5134 sc->spq_last_bd = (sc->spq_prod_bd + MAX_SP_DESC_CNT);
5137 static void bnx2x_init_eq_ring(struct bnx2x_softc *sc)
5139 union event_ring_elem *elem;
5142 for (i = 1; i <= NUM_EQ_PAGES; i++) {
5143 elem = &sc->eq[EQ_DESC_CNT_PAGE * i - 1];
5145 elem->next_page.addr.hi = htole32(U64_HI(sc->eq_dma.paddr +
5147 (i % NUM_EQ_PAGES)));
5148 elem->next_page.addr.lo = htole32(U64_LO(sc->eq_dma.paddr +
5150 (i % NUM_EQ_PAGES)));
5154 sc->eq_prod = NUM_EQ_DESC;
5155 sc->eq_cons_sb = &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_EQ_CONS];
5157 atomic_store_rel_long(&sc->eq_spq_left,
5158 (min((MAX_SP_DESC_CNT - MAX_SPQ_PENDING),
5162 static void bnx2x_init_internal_common(struct bnx2x_softc *sc)
5168 * In switch independent mode, the TSTORM needs to accept
5169 * packets that failed classification, since approximate match
5170 * mac addresses aren't written to NIG LLH.
5173 (BAR_TSTRORM_INTMEM +
5174 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 2);
5177 (BAR_TSTRORM_INTMEM +
5178 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 0);
5181 * Zero this manually as its initialization is currently missing
5184 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) {
5186 (BAR_USTRORM_INTMEM + USTORM_AGG_DATA_OFFSET + (i * 4)),
5190 if (!CHIP_IS_E1x(sc)) {
5191 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET),
5192 CHIP_INT_MODE_IS_BC(sc) ? HC_IGU_BC_MODE :
5197 static void bnx2x_init_internal(struct bnx2x_softc *sc, uint32_t load_code)
5199 switch (load_code) {
5200 case FW_MSG_CODE_DRV_LOAD_COMMON:
5201 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5202 bnx2x_init_internal_common(sc);
5205 case FW_MSG_CODE_DRV_LOAD_PORT:
5209 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5210 /* internal memory per function is initialized inside bnx2x_pf_init */
5214 PMD_DRV_LOG(NOTICE, "Unknown load_code (0x%x) from MCP",
5221 storm_memset_func_cfg(struct bnx2x_softc *sc,
5222 struct tstorm_eth_function_common_config *tcfg,
5228 addr = (BAR_TSTRORM_INTMEM +
5229 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid));
5230 size = sizeof(struct tstorm_eth_function_common_config);
5231 ecore_storm_memset_struct(sc, addr, size, (uint32_t *) tcfg);
5234 static void bnx2x_func_init(struct bnx2x_softc *sc, struct bnx2x_func_init_params *p)
5236 struct tstorm_eth_function_common_config tcfg = { 0 };
5238 if (CHIP_IS_E1x(sc)) {
5239 storm_memset_func_cfg(sc, &tcfg, p->func_id);
5242 /* Enable the function in the FW */
5243 storm_memset_vf_to_pf(sc, p->func_id, p->pf_id);
5244 storm_memset_func_en(sc, p->func_id, 1);
5247 if (p->func_flgs & FUNC_FLG_SPQ) {
5248 storm_memset_spq_addr(sc, p->spq_map, p->func_id);
5250 (XSEM_REG_FAST_MEMORY +
5251 XSTORM_SPQ_PROD_OFFSET(p->func_id)), p->spq_prod);
5256 * Calculates the sum of vn_min_rates.
5257 * It's needed for further normalizing of the min_rates.
5259 * sum of vn_min_rates.
5261 * 0 - if all the min_rates are 0.
5262 * In the later case fainess algorithm should be deactivated.
5263 * If all min rates are not zero then those that are zeroes will be set to 1.
5265 static void bnx2x_calc_vn_min(struct bnx2x_softc *sc, struct cmng_init_input *input)
5268 uint32_t vn_min_rate;
5272 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5273 vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5274 vn_min_rate = (((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
5275 FUNC_MF_CFG_MIN_BW_SHIFT) * 100);
5277 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5278 /* skip hidden VNs */
5280 } else if (!vn_min_rate) {
5281 /* If min rate is zero - set it to 100 */
5282 vn_min_rate = DEF_MIN_RATE;
5287 input->vnic_min_rate[vn] = vn_min_rate;
5290 /* if ETS or all min rates are zeros - disable fairness */
5292 input->flags.cmng_enables &= ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5294 input->flags.cmng_enables |= CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5299 bnx2x_extract_max_cfg(__rte_unused struct bnx2x_softc *sc, uint32_t mf_cfg)
5301 uint16_t max_cfg = ((mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
5302 FUNC_MF_CFG_MAX_BW_SHIFT);
5306 "Max BW configured to 0 - using 100 instead");
5314 bnx2x_calc_vn_max(struct bnx2x_softc *sc, int vn, struct cmng_init_input *input)
5316 uint16_t vn_max_rate;
5317 uint32_t vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5320 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5323 max_cfg = bnx2x_extract_max_cfg(sc, vn_cfg);
5326 /* max_cfg in percents of linkspeed */
5328 ((sc->link_vars.line_speed * max_cfg) / 100);
5329 } else { /* SD modes */
5330 /* max_cfg is absolute in 100Mb units */
5331 vn_max_rate = (max_cfg * 100);
5335 input->vnic_max_rate[vn] = vn_max_rate;
5339 bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg, uint8_t cmng_type)
5341 struct cmng_init_input input;
5344 memset(&input, 0, sizeof(struct cmng_init_input));
5346 input.port_rate = sc->link_vars.line_speed;
5348 if (cmng_type == CMNG_FNS_MINMAX) {
5349 /* read mf conf from shmem */
5351 bnx2x_read_mf_cfg(sc);
5354 /* get VN min rate and enable fairness if not 0 */
5355 bnx2x_calc_vn_min(sc, &input);
5357 /* get VN max rate */
5359 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5360 bnx2x_calc_vn_max(sc, vn, &input);
5364 /* always enable rate shaping and fairness */
5365 input.flags.cmng_enables |= CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
5367 ecore_init_cmng(&input, &sc->cmng);
5372 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc)
5374 if (CHIP_REV_IS_SLOW(sc)) {
5375 return CMNG_FNS_NONE;
5379 return CMNG_FNS_MINMAX;
5382 return CMNG_FNS_NONE;
5386 storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng, uint8_t port)
5393 addr = (BAR_XSTRORM_INTMEM + XSTORM_CMNG_PER_PORT_VARS_OFFSET(port));
5394 size = sizeof(struct cmng_struct_per_port);
5395 ecore_storm_memset_struct(sc, addr, size, (uint32_t *) & cmng->port);
5397 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5398 func = func_by_vn(sc, vn);
5400 addr = (BAR_XSTRORM_INTMEM +
5401 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func));
5402 size = sizeof(struct rate_shaping_vars_per_vn);
5403 ecore_storm_memset_struct(sc, addr, size,
5404 (uint32_t *) & cmng->
5405 vnic.vnic_max_rate[vn]);
5407 addr = (BAR_XSTRORM_INTMEM +
5408 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func));
5409 size = sizeof(struct fairness_vars_per_vn);
5410 ecore_storm_memset_struct(sc, addr, size,
5411 (uint32_t *) & cmng->
5412 vnic.vnic_min_rate[vn]);
5416 static void bnx2x_pf_init(struct bnx2x_softc *sc)
5418 struct bnx2x_func_init_params func_init;
5419 struct event_ring_data eq_data;
5422 memset(&eq_data, 0, sizeof(struct event_ring_data));
5423 memset(&func_init, 0, sizeof(struct bnx2x_func_init_params));
5425 if (!CHIP_IS_E1x(sc)) {
5426 /* reset IGU PF statistics: MSIX + ATTN */
5429 (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5430 (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5431 ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5435 (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5436 (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5437 (BNX2X_IGU_STAS_MSG_PF_CNT * 4) +
5438 ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5442 /* function setup flags */
5443 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
5445 func_init.func_flgs = flags;
5446 func_init.pf_id = SC_FUNC(sc);
5447 func_init.func_id = SC_FUNC(sc);
5448 func_init.spq_map = sc->spq_dma.paddr;
5449 func_init.spq_prod = sc->spq_prod_idx;
5451 bnx2x_func_init(sc, &func_init);
5453 memset(&sc->cmng, 0, sizeof(struct cmng_struct_per_port));
5456 * Congestion management values depend on the link rate.
5457 * There is no active link so initial link rate is set to 10Gbps.
5458 * When the link comes up the congestion management values are
5459 * re-calculated according to the actual link rate.
5461 sc->link_vars.line_speed = SPEED_10000;
5462 bnx2x_cmng_fns_init(sc, TRUE, bnx2x_get_cmng_fns_mode(sc));
5464 /* Only the PMF sets the HW */
5466 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
5469 /* init Event Queue - PCI bus guarantees correct endainity */
5470 eq_data.base_addr.hi = U64_HI(sc->eq_dma.paddr);
5471 eq_data.base_addr.lo = U64_LO(sc->eq_dma.paddr);
5472 eq_data.producer = sc->eq_prod;
5473 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
5474 eq_data.sb_id = DEF_SB_ID;
5475 storm_memset_eq_data(sc, &eq_data, SC_FUNC(sc));
5478 static void bnx2x_hc_int_enable(struct bnx2x_softc *sc)
5480 int port = SC_PORT(sc);
5481 uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5482 uint32_t val = REG_RD(sc, addr);
5483 uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5484 || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5485 uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5486 uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5489 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5490 HC_CONFIG_0_REG_INT_LINE_EN_0);
5491 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5492 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5494 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
5497 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
5498 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5499 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5500 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5502 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5503 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5504 HC_CONFIG_0_REG_INT_LINE_EN_0 |
5505 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5507 REG_WR(sc, addr, val);
5509 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
5512 REG_WR(sc, addr, val);
5514 /* ensure that HC_CONFIG is written before leading/trailing edge config */
5517 /* init leading/trailing edge */
5519 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5521 /* enable nig and gpio3 attention */
5528 REG_WR(sc, (HC_REG_TRAILING_EDGE_0 + port * 8), val);
5529 REG_WR(sc, (HC_REG_LEADING_EDGE_0 + port * 8), val);
5531 /* make sure that interrupts are indeed enabled from here on */
5535 static void bnx2x_igu_int_enable(struct bnx2x_softc *sc)
5538 uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5539 || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5540 uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5541 uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5543 val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5546 val &= ~(IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5547 val |= (IGU_PF_CONF_MSI_MSIX_EN | IGU_PF_CONF_ATTN_BIT_EN);
5549 val |= IGU_PF_CONF_SINGLE_ISR_EN;
5552 val &= ~IGU_PF_CONF_INT_LINE_EN;
5553 val |= (IGU_PF_CONF_MSI_MSIX_EN |
5554 IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5556 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
5557 val |= (IGU_PF_CONF_INT_LINE_EN |
5558 IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5561 /* clean previous status - need to configure igu prior to ack */
5562 if ((!msix) || single_msix) {
5563 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5567 val |= IGU_PF_CONF_FUNC_EN;
5569 PMD_DRV_LOG(DEBUG, "write 0x%x to IGU mode %s",
5570 val, ((msix) ? "MSI-X" : ((msi) ? "MSI" : "INTx")));
5572 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5576 /* init leading/trailing edge */
5578 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5580 /* enable nig and gpio3 attention */
5587 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
5588 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
5590 /* make sure that interrupts are indeed enabled from here on */
5594 static void bnx2x_int_enable(struct bnx2x_softc *sc)
5596 if (sc->devinfo.int_block == INT_BLOCK_HC) {
5597 bnx2x_hc_int_enable(sc);
5599 bnx2x_igu_int_enable(sc);
5603 static void bnx2x_hc_int_disable(struct bnx2x_softc *sc)
5605 int port = SC_PORT(sc);
5606 uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5607 uint32_t val = REG_RD(sc, addr);
5609 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5610 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5611 HC_CONFIG_0_REG_INT_LINE_EN_0 | HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5612 /* flush all outstanding writes */
5615 REG_WR(sc, addr, val);
5616 if (REG_RD(sc, addr) != val) {
5617 PMD_DRV_LOG(ERR, "proper val not read from HC IGU!");
5621 static void bnx2x_igu_int_disable(struct bnx2x_softc *sc)
5623 uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5625 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
5626 IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_ATTN_BIT_EN);
5628 PMD_DRV_LOG(DEBUG, "write %x to IGU", val);
5630 /* flush all outstanding writes */
5633 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5634 if (REG_RD(sc, IGU_REG_PF_CONFIGURATION) != val) {
5635 PMD_DRV_LOG(ERR, "proper val not read from IGU!");
5639 static void bnx2x_int_disable(struct bnx2x_softc *sc)
5641 if (sc->devinfo.int_block == INT_BLOCK_HC) {
5642 bnx2x_hc_int_disable(sc);
5644 bnx2x_igu_int_disable(sc);
5648 static void bnx2x_nic_init(struct bnx2x_softc *sc, int load_code)
5652 PMD_INIT_FUNC_TRACE();
5654 for (i = 0; i < sc->num_queues; i++) {
5655 bnx2x_init_eth_fp(sc, i);
5658 rmb(); /* ensure status block indices were read */
5660 bnx2x_init_rx_rings(sc);
5661 bnx2x_init_tx_rings(sc);
5664 bnx2x_memset_stats(sc);
5668 /* initialize MOD_ABS interrupts */
5669 elink_init_mod_abs_int(sc, &sc->link_vars,
5670 sc->devinfo.chip_id,
5671 sc->devinfo.shmem_base,
5672 sc->devinfo.shmem2_base, SC_PORT(sc));
5674 bnx2x_init_def_sb(sc);
5675 bnx2x_update_dsb_idx(sc);
5676 bnx2x_init_sp_ring(sc);
5677 bnx2x_init_eq_ring(sc);
5678 bnx2x_init_internal(sc, load_code);
5680 bnx2x_stats_init(sc);
5682 /* flush all before enabling interrupts */
5685 bnx2x_int_enable(sc);
5687 /* check for SPIO5 */
5688 bnx2x_attn_int_deasserted0(sc,
5690 (MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
5692 AEU_INPUTS_ATTN_BITS_SPIO5);
5695 static void bnx2x_init_objs(struct bnx2x_softc *sc)
5697 /* mcast rules must be added to tx if tx switching is enabled */
5698 ecore_obj_type o_type;
5699 if (sc->flags & BNX2X_TX_SWITCHING)
5700 o_type = ECORE_OBJ_TYPE_RX_TX;
5702 o_type = ECORE_OBJ_TYPE_RX;
5704 /* RX_MODE controlling object */
5705 ecore_init_rx_mode_obj(sc, &sc->rx_mode_obj);
5707 /* multicast configuration controlling object */
5708 ecore_init_mcast_obj(sc,
5714 BNX2X_SP(sc, mcast_rdata),
5715 (phys_addr_t)BNX2X_SP_MAPPING(sc, mcast_rdata),
5716 ECORE_FILTER_MCAST_PENDING,
5717 &sc->sp_state, o_type);
5719 /* Setup CAM credit pools */
5720 ecore_init_mac_credit_pool(sc,
5723 CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5724 VNICS_PER_PATH(sc));
5726 ecore_init_vlan_credit_pool(sc,
5728 SC_ABS_FUNC(sc) >> 1,
5729 CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5730 VNICS_PER_PATH(sc));
5732 /* RSS configuration object */
5733 ecore_init_rss_config_obj(&sc->rss_conf_obj,
5738 BNX2X_SP(sc, rss_rdata),
5739 (phys_addr_t)BNX2X_SP_MAPPING(sc, rss_rdata),
5740 ECORE_FILTER_RSS_CONF_PENDING,
5741 &sc->sp_state, ECORE_OBJ_TYPE_RX);
5745 * Initialize the function. This must be called before sending CLIENT_SETUP
5746 * for the first client.
5748 static int bnx2x_func_start(struct bnx2x_softc *sc)
5750 struct ecore_func_state_params func_params = { NULL };
5751 struct ecore_func_start_params *start_params =
5752 &func_params.params.start;
5754 /* Prepare parameters for function state transitions */
5755 bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
5757 func_params.f_obj = &sc->func_obj;
5758 func_params.cmd = ECORE_F_CMD_START;
5760 /* Function parameters */
5761 start_params->mf_mode = sc->devinfo.mf_info.mf_mode;
5762 start_params->sd_vlan_tag = OVLAN(sc);
5764 if (CHIP_IS_E2(sc) || CHIP_IS_E3(sc)) {
5765 start_params->network_cos_mode = STATIC_COS;
5766 } else { /* CHIP_IS_E1X */
5767 start_params->network_cos_mode = FW_WRR;
5770 start_params->gre_tunnel_mode = 0;
5771 start_params->gre_tunnel_rss = 0;
5773 return ecore_func_state_change(sc, &func_params);
5776 static int bnx2x_set_power_state(struct bnx2x_softc *sc, uint8_t state)
5780 /* If there is no power capability, silently succeed */
5781 if (!(sc->devinfo.pcie_cap_flags & BNX2X_PM_CAPABLE_FLAG)) {
5782 PMD_DRV_LOG(WARNING, "No power capability");
5786 pci_read(sc, (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS), &pmcsr,
5792 (sc->devinfo.pcie_pm_cap_reg +
5794 ((pmcsr & ~PCIM_PSTAT_DMASK) | PCIM_PSTAT_PME));
5796 if (pmcsr & PCIM_PSTAT_DMASK) {
5797 /* delay required during transition out of D3hot */
5804 /* don't shut down the power for emulation and FPGA */
5805 if (CHIP_REV_IS_SLOW(sc)) {
5809 pmcsr &= ~PCIM_PSTAT_DMASK;
5810 pmcsr |= PCIM_PSTAT_D3;
5813 pmcsr |= PCIM_PSTAT_PMEENABLE;
5817 (sc->devinfo.pcie_pm_cap_reg +
5818 PCIR_POWER_STATUS), pmcsr);
5821 * No more memory access after this point until device is brought back
5827 PMD_DRV_LOG(NOTICE, "Can't support PCI power state = %d",
5835 /* return true if succeeded to acquire the lock */
5836 static uint8_t bnx2x_trylock_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
5838 uint32_t lock_status;
5839 uint32_t resource_bit = (1 << resource);
5840 int func = SC_FUNC(sc);
5841 uint32_t hw_lock_control_reg;
5843 /* Validating that the resource is within range */
5844 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
5846 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)",
5847 resource, HW_LOCK_MAX_RESOURCE_VALUE);
5852 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func * 8);
5854 hw_lock_control_reg =
5855 (MISC_REG_DRIVER_CONTROL_7 + (func - 6) * 8);
5858 /* try to acquire the lock */
5859 REG_WR(sc, hw_lock_control_reg + 4, resource_bit);
5860 lock_status = REG_RD(sc, hw_lock_control_reg);
5861 if (lock_status & resource_bit) {
5865 PMD_DRV_LOG(NOTICE, "Failed to get a resource lock 0x%x", resource);
5871 * Get the recovery leader resource id according to the engine this function
5872 * belongs to. Currently only only 2 engines is supported.
5874 static int bnx2x_get_leader_lock_resource(struct bnx2x_softc *sc)
5877 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
5879 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
5883 /* try to acquire a leader lock for current engine */
5884 static uint8_t bnx2x_trylock_leader_lock(struct bnx2x_softc *sc)
5886 return bnx2x_trylock_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5889 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc)
5891 return bnx2x_release_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5894 /* close gates #2, #3 and #4 */
5895 static void bnx2x_set_234_gates(struct bnx2x_softc *sc, uint8_t close)
5899 /* gates #2 and #4a are closed/opened */
5901 REG_WR(sc, PXP_REG_HST_DISCARD_DOORBELLS, ! !close);
5903 REG_WR(sc, PXP_REG_HST_DISCARD_INTERNAL_WRITES, ! !close);
5906 if (CHIP_IS_E1x(sc)) {
5907 /* prevent interrupts from HC on both ports */
5908 val = REG_RD(sc, HC_REG_CONFIG_1);
5910 REG_WR(sc, HC_REG_CONFIG_1, (val & ~(uint32_t)
5911 HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5913 REG_WR(sc, HC_REG_CONFIG_1,
5914 (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5916 val = REG_RD(sc, HC_REG_CONFIG_0);
5918 REG_WR(sc, HC_REG_CONFIG_0, (val & ~(uint32_t)
5919 HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5921 REG_WR(sc, HC_REG_CONFIG_0,
5922 (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5925 /* Prevent incomming interrupts in IGU */
5926 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
5929 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5931 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5933 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5935 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5941 /* poll for pending writes bit, it should get cleared in no more than 1s */
5942 static int bnx2x_er_poll_igu_vq(struct bnx2x_softc *sc)
5944 uint32_t cnt = 1000;
5945 uint32_t pend_bits = 0;
5948 pend_bits = REG_RD(sc, IGU_REG_PENDING_BITS_STATUS);
5950 if (pend_bits == 0) {
5955 } while (cnt-- > 0);
5958 PMD_DRV_LOG(NOTICE, "Still pending IGU requests bits=0x%08x!",
5966 #define SHARED_MF_CLP_MAGIC 0x80000000 /* 'magic' bit */
5968 static void bnx2x_clp_reset_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
5970 /* Do some magic... */
5971 uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
5972 *magic_val = val & SHARED_MF_CLP_MAGIC;
5973 MFCFG_WR(sc, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
5976 /* restore the value of the 'magic' bit */
5977 static void bnx2x_clp_reset_done(struct bnx2x_softc *sc, uint32_t magic_val)
5979 /* Restore the 'magic' bit value... */
5980 uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
5981 MFCFG_WR(sc, shared_mf_config.clp_mb,
5982 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
5985 /* prepare for MCP reset, takes care of CLP configurations */
5986 static void bnx2x_reset_mcp_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
5989 uint32_t validity_offset;
5991 /* set `magic' bit in order to save MF config */
5992 bnx2x_clp_reset_prep(sc, magic_val);
5994 /* get shmem offset */
5995 shmem = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
5997 offsetof(struct shmem_region, validity_map[SC_PORT(sc)]);
5999 /* Clear validity map flags */
6001 REG_WR(sc, shmem + validity_offset, 0);
6005 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
6006 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
6008 static void bnx2x_mcp_wait_one(struct bnx2x_softc *sc)
6010 /* special handling for emulation and FPGA (10 times longer) */
6011 if (CHIP_REV_IS_SLOW(sc)) {
6012 DELAY((MCP_ONE_TIMEOUT * 10) * 1000);
6014 DELAY((MCP_ONE_TIMEOUT) * 1000);
6018 /* initialize shmem_base and waits for validity signature to appear */
6019 static int bnx2x_init_shmem(struct bnx2x_softc *sc)
6025 sc->devinfo.shmem_base =
6026 sc->link_params.shmem_base =
6027 REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
6029 if (sc->devinfo.shmem_base) {
6030 val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
6031 if (val & SHR_MEM_VALIDITY_MB)
6035 bnx2x_mcp_wait_one(sc);
6037 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
6039 PMD_DRV_LOG(NOTICE, "BAD MCP validity signature");
6044 static int bnx2x_reset_mcp_comp(struct bnx2x_softc *sc, uint32_t magic_val)
6046 int rc = bnx2x_init_shmem(sc);
6048 /* Restore the `magic' bit value */
6049 bnx2x_clp_reset_done(sc, magic_val);
6054 static void bnx2x_pxp_prep(struct bnx2x_softc *sc)
6056 REG_WR(sc, PXP2_REG_RD_START_INIT, 0);
6057 REG_WR(sc, PXP2_REG_RQ_RBC_DONE, 0);
6062 * Reset the whole chip except for:
6064 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by one reset bit)
6066 * - MISC (including AEU)
6070 static void bnx2x_process_kill_chip_reset(struct bnx2x_softc *sc, uint8_t global)
6072 uint32_t not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
6073 uint32_t global_bits2, stay_reset2;
6076 * Bits that have to be set in reset_mask2 if we want to reset 'global'
6077 * (per chip) blocks.
6080 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
6081 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
6084 * Don't reset the following blocks.
6085 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
6086 * reset, as in 4 port device they might still be owned
6087 * by the MCP (there is only one leader per path).
6090 MISC_REGISTERS_RESET_REG_1_RST_HC |
6091 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
6092 MISC_REGISTERS_RESET_REG_1_RST_PXP;
6095 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
6096 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
6097 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
6098 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
6099 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
6100 MISC_REGISTERS_RESET_REG_2_RST_GRC |
6101 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
6102 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
6103 MISC_REGISTERS_RESET_REG_2_RST_ATC |
6104 MISC_REGISTERS_RESET_REG_2_PGLC |
6105 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
6106 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
6107 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
6108 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
6109 MISC_REGISTERS_RESET_REG_2_UMAC0 | MISC_REGISTERS_RESET_REG_2_UMAC1;
6112 * Keep the following blocks in reset:
6113 * - all xxMACs are handled by the elink code.
6116 MISC_REGISTERS_RESET_REG_2_XMAC |
6117 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
6119 /* Full reset masks according to the chip */
6120 reset_mask1 = 0xffffffff;
6122 if (CHIP_IS_E1H(sc))
6123 reset_mask2 = 0x1ffff;
6124 else if (CHIP_IS_E2(sc))
6125 reset_mask2 = 0xfffff;
6126 else /* CHIP_IS_E3 */
6127 reset_mask2 = 0x3ffffff;
6129 /* Don't reset global blocks unless we need to */
6131 reset_mask2 &= ~global_bits2;
6134 * In case of attention in the QM, we need to reset PXP
6135 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
6136 * because otherwise QM reset would release 'close the gates' shortly
6137 * before resetting the PXP, then the PSWRQ would send a write
6138 * request to PGLUE. Then when PXP is reset, PGLUE would try to
6139 * read the payload data from PSWWR, but PSWWR would not
6140 * respond. The write queue in PGLUE would stuck, dmae commands
6141 * would not return. Therefore it's important to reset the second
6142 * reset register (containing the
6143 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
6144 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
6147 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
6148 reset_mask2 & (~not_reset_mask2));
6150 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6151 reset_mask1 & (~not_reset_mask1));
6156 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
6157 reset_mask2 & (~stay_reset2));
6162 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
6166 static int bnx2x_process_kill(struct bnx2x_softc *sc, uint8_t global)
6170 uint32_t sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
6171 uint32_t tags_63_32 = 0;
6173 /* Empty the Tetris buffer, wait for 1s */
6175 sr_cnt = REG_RD(sc, PXP2_REG_RD_SR_CNT);
6176 blk_cnt = REG_RD(sc, PXP2_REG_RD_BLK_CNT);
6177 port_is_idle_0 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_0);
6178 port_is_idle_1 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_1);
6179 pgl_exp_rom2 = REG_RD(sc, PXP2_REG_PGL_EXP_ROM2);
6180 if (CHIP_IS_E3(sc)) {
6181 tags_63_32 = REG_RD(sc, PGLUE_B_REG_TAGS_63_32);
6184 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
6185 ((port_is_idle_0 & 0x1) == 0x1) &&
6186 ((port_is_idle_1 & 0x1) == 0x1) &&
6187 (pgl_exp_rom2 == 0xffffffff) &&
6188 (!CHIP_IS_E3(sc) || (tags_63_32 == 0xffffffff)))
6191 } while (cnt-- > 0);
6195 "ERROR: Tetris buffer didn't get empty or there "
6196 "are still outstanding read requests after 1s! "
6197 "sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, "
6198 "port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x",
6199 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
6206 /* Close gates #2, #3 and #4 */
6207 bnx2x_set_234_gates(sc, TRUE);
6209 /* Poll for IGU VQs for 57712 and newer chips */
6210 if (!CHIP_IS_E1x(sc) && bnx2x_er_poll_igu_vq(sc)) {
6214 /* clear "unprepared" bit */
6215 REG_WR(sc, MISC_REG_UNPREPARED, 0);
6218 /* Make sure all is written to the chip before the reset */
6222 * Wait for 1ms to empty GLUE and PCI-E core queues,
6223 * PSWHST, GRC and PSWRD Tetris buffer.
6227 /* Prepare to chip reset: */
6230 bnx2x_reset_mcp_prep(sc, &val);
6237 /* reset the chip */
6238 bnx2x_process_kill_chip_reset(sc, global);
6241 /* Recover after reset: */
6243 if (global && bnx2x_reset_mcp_comp(sc, val)) {
6247 /* Open the gates #2, #3 and #4 */
6248 bnx2x_set_234_gates(sc, FALSE);
6253 static int bnx2x_leader_reset(struct bnx2x_softc *sc)
6256 uint8_t global = bnx2x_reset_is_global(sc);
6260 * If not going to reset MCP, load "fake" driver to reset HW while
6261 * driver is owner of the HW.
6263 if (!global && !BNX2X_NOMCP(sc)) {
6264 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
6265 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
6267 PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
6269 goto exit_leader_reset;
6272 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
6273 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
6275 "MCP unexpected response, aborting");
6277 goto exit_leader_reset2;
6280 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
6282 PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
6284 goto exit_leader_reset2;
6288 /* try to recover after the failure */
6289 if (bnx2x_process_kill(sc, global)) {
6290 PMD_DRV_LOG(NOTICE, "Something bad occurred on engine %d!",
6293 goto exit_leader_reset2;
6297 * Clear the RESET_IN_PROGRESS and RESET_GLOBAL bits and update the driver
6300 bnx2x_set_reset_done(sc);
6302 bnx2x_clear_reset_global(sc);
6307 /* unload "fake driver" if it was loaded */
6308 if (!global &&!BNX2X_NOMCP(sc)) {
6309 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
6310 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
6316 bnx2x_release_leader_lock(sc);
6323 * prepare INIT transition, parameters configured:
6324 * - HC configuration
6325 * - Queue's CDU context
6328 bnx2x_pf_q_prep_init(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6329 struct ecore_queue_init_params *init_params)
6332 int cxt_index, cxt_offset;
6334 bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->rx.flags);
6335 bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->tx.flags);
6337 bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->rx.flags);
6338 bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->tx.flags);
6341 init_params->rx.hc_rate =
6342 sc->hc_rx_ticks ? (1000000 / sc->hc_rx_ticks) : 0;
6343 init_params->tx.hc_rate =
6344 sc->hc_tx_ticks ? (1000000 / sc->hc_tx_ticks) : 0;
6347 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = fp->fw_sb_id;
6349 /* CQ index among the SB indices */
6350 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6351 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
6353 /* set maximum number of COSs supported by this queue */
6354 init_params->max_cos = sc->max_cos;
6356 /* set the context pointers queue object */
6357 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
6358 cxt_index = fp->index / ILT_PAGE_CIDS;
6359 cxt_offset = fp->index - (cxt_index * ILT_PAGE_CIDS);
6360 init_params->cxts[cos] =
6361 &sc->context[cxt_index].vcxt[cxt_offset].eth;
6365 /* set flags that are common for the Tx-only and not normal connections */
6366 static unsigned long
6367 bnx2x_get_common_flags(struct bnx2x_softc *sc, uint8_t zero_stats)
6369 unsigned long flags = 0;
6371 /* PF driver will always initialize the Queue to an ACTIVE state */
6372 bnx2x_set_bit(ECORE_Q_FLG_ACTIVE, &flags);
6375 * tx only connections collect statistics (on the same index as the
6376 * parent connection). The statistics are zeroed when the parent
6377 * connection is initialized.
6380 bnx2x_set_bit(ECORE_Q_FLG_STATS, &flags);
6382 bnx2x_set_bit(ECORE_Q_FLG_ZERO_STATS, &flags);
6386 * tx only connections can support tx-switching, though their
6387 * CoS-ness doesn't survive the loopback
6389 if (sc->flags & BNX2X_TX_SWITCHING) {
6390 bnx2x_set_bit(ECORE_Q_FLG_TX_SWITCH, &flags);
6393 bnx2x_set_bit(ECORE_Q_FLG_PCSUM_ON_PKT, &flags);
6398 static unsigned long bnx2x_get_q_flags(struct bnx2x_softc *sc, uint8_t leading)
6400 unsigned long flags = 0;
6403 bnx2x_set_bit(ECORE_Q_FLG_OV, &flags);
6407 bnx2x_set_bit(ECORE_Q_FLG_LEADING_RSS, &flags);
6408 bnx2x_set_bit(ECORE_Q_FLG_MCAST, &flags);
6411 bnx2x_set_bit(ECORE_Q_FLG_VLAN, &flags);
6413 /* merge with common flags */
6414 return flags | bnx2x_get_common_flags(sc, TRUE);
6418 bnx2x_pf_q_prep_general(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6419 struct ecore_general_setup_params *gen_init, uint8_t cos)
6421 gen_init->stat_id = bnx2x_stats_id(fp);
6422 gen_init->spcl_id = fp->cl_id;
6423 gen_init->mtu = sc->mtu;
6424 gen_init->cos = cos;
6428 bnx2x_pf_rx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6429 struct rxq_pause_params *pause,
6430 struct ecore_rxq_setup_params *rxq_init)
6432 struct bnx2x_rx_queue *rxq;
6434 rxq = sc->rx_queues[fp->index];
6436 PMD_RX_LOG(ERR, "RX queue is NULL");
6440 pause->bd_th_lo = BD_TH_LO(sc);
6441 pause->bd_th_hi = BD_TH_HI(sc);
6443 pause->rcq_th_lo = RCQ_TH_LO(sc);
6444 pause->rcq_th_hi = RCQ_TH_HI(sc);
6446 /* validate rings have enough entries to cross high thresholds */
6447 if (sc->dropless_fc &&
6448 pause->bd_th_hi + FW_PREFETCH_CNT > sc->rx_ring_size) {
6449 PMD_DRV_LOG(WARNING, "rx bd ring threshold limit");
6452 if (sc->dropless_fc &&
6453 pause->rcq_th_hi + FW_PREFETCH_CNT > USABLE_RCQ_ENTRIES(rxq)) {
6454 PMD_DRV_LOG(WARNING, "rcq ring threshold limit");
6460 rxq_init->dscr_map = (phys_addr_t)rxq->rx_ring_phys_addr;
6461 rxq_init->rcq_map = (phys_addr_t)rxq->cq_ring_phys_addr;
6462 rxq_init->rcq_np_map = (phys_addr_t)(rxq->cq_ring_phys_addr +
6466 * This should be a maximum number of data bytes that may be
6467 * placed on the BD (not including paddings).
6469 rxq_init->buf_sz = (fp->rx_buf_size - IP_HEADER_ALIGNMENT_PADDING);
6471 rxq_init->cl_qzone_id = fp->cl_qzone_id;
6472 rxq_init->rss_engine_id = SC_FUNC(sc);
6473 rxq_init->mcast_engine_id = SC_FUNC(sc);
6475 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
6476 rxq_init->fw_sb_id = fp->fw_sb_id;
6478 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6481 * configure silent vlan removal
6482 * if multi function mode is afex, then mask default vlan
6484 if (IS_MF_AFEX(sc)) {
6485 rxq_init->silent_removal_value =
6486 sc->devinfo.mf_info.afex_def_vlan_tag;
6487 rxq_init->silent_removal_mask = EVL_VLID_MASK;
6492 bnx2x_pf_tx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6493 struct ecore_txq_setup_params *txq_init, uint8_t cos)
6495 struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
6498 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
6501 txq_init->dscr_map = (phys_addr_t)txq->tx_ring_phys_addr;
6502 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
6503 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
6504 txq_init->fw_sb_id = fp->fw_sb_id;
6507 * set the TSS leading client id for TX classfication to the
6508 * leading RSS client id
6510 txq_init->tss_leading_cl_id = BNX2X_FP(sc, 0, cl_id);
6514 * This function performs 2 steps in a queue state machine:
6519 bnx2x_setup_queue(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp, uint8_t leading)
6521 struct ecore_queue_state_params q_params = { NULL };
6522 struct ecore_queue_setup_params *setup_params = &q_params.params.setup;
6525 PMD_DRV_LOG(DEBUG, "setting up queue %d", fp->index);
6527 bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6529 q_params.q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
6531 /* we want to wait for completion in this context */
6532 bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
6534 /* prepare the INIT parameters */
6535 bnx2x_pf_q_prep_init(sc, fp, &q_params.params.init);
6537 /* Set the command */
6538 q_params.cmd = ECORE_Q_CMD_INIT;
6540 /* Change the state to INIT */
6541 rc = ecore_queue_state_change(sc, &q_params);
6543 PMD_DRV_LOG(NOTICE, "Queue(%d) INIT failed", fp->index);
6547 PMD_DRV_LOG(DEBUG, "init complete");
6549 /* now move the Queue to the SETUP state */
6550 memset(setup_params, 0, sizeof(*setup_params));
6552 /* set Queue flags */
6553 setup_params->flags = bnx2x_get_q_flags(sc, leading);
6555 /* set general SETUP parameters */
6556 bnx2x_pf_q_prep_general(sc, fp, &setup_params->gen_params,
6557 FIRST_TX_COS_INDEX);
6559 bnx2x_pf_rx_q_prep(sc, fp,
6560 &setup_params->pause_params,
6561 &setup_params->rxq_params);
6563 bnx2x_pf_tx_q_prep(sc, fp, &setup_params->txq_params, FIRST_TX_COS_INDEX);
6565 /* Set the command */
6566 q_params.cmd = ECORE_Q_CMD_SETUP;
6568 /* change the state to SETUP */
6569 rc = ecore_queue_state_change(sc, &q_params);
6571 PMD_DRV_LOG(NOTICE, "Queue(%d) SETUP failed", fp->index);
6578 static int bnx2x_setup_leading(struct bnx2x_softc *sc)
6581 return bnx2x_setup_queue(sc, &sc->fp[0], TRUE);
6583 return bnx2x_vf_setup_queue(sc, &sc->fp[0], TRUE);
6587 bnx2x_config_rss_pf(struct bnx2x_softc *sc, struct ecore_rss_config_obj *rss_obj,
6588 uint8_t config_hash)
6590 struct ecore_config_rss_params params = { NULL };
6594 * Although RSS is meaningless when there is a single HW queue we
6595 * still need it enabled in order to have HW Rx hash generated.
6598 params.rss_obj = rss_obj;
6600 bnx2x_set_bit(RAMROD_COMP_WAIT, ¶ms.ramrod_flags);
6602 bnx2x_set_bit(ECORE_RSS_MODE_REGULAR, ¶ms.rss_flags);
6604 /* RSS configuration */
6605 bnx2x_set_bit(ECORE_RSS_IPV4, ¶ms.rss_flags);
6606 bnx2x_set_bit(ECORE_RSS_IPV4_TCP, ¶ms.rss_flags);
6607 bnx2x_set_bit(ECORE_RSS_IPV6, ¶ms.rss_flags);
6608 bnx2x_set_bit(ECORE_RSS_IPV6_TCP, ¶ms.rss_flags);
6609 if (rss_obj->udp_rss_v4) {
6610 bnx2x_set_bit(ECORE_RSS_IPV4_UDP, ¶ms.rss_flags);
6612 if (rss_obj->udp_rss_v6) {
6613 bnx2x_set_bit(ECORE_RSS_IPV6_UDP, ¶ms.rss_flags);
6617 params.rss_result_mask = MULTI_MASK;
6619 (void)rte_memcpy(params.ind_table, rss_obj->ind_table,
6620 sizeof(params.ind_table));
6624 for (i = 0; i < sizeof(params.rss_key) / 4; i++) {
6625 params.rss_key[i] = (uint32_t) rte_rand();
6628 bnx2x_set_bit(ECORE_RSS_SET_SRCH, ¶ms.rss_flags);
6632 return ecore_config_rss(sc, ¶ms);
6634 return bnx2x_vf_config_rss(sc, ¶ms);
6637 static int bnx2x_config_rss_eth(struct bnx2x_softc *sc, uint8_t config_hash)
6639 return bnx2x_config_rss_pf(sc, &sc->rss_conf_obj, config_hash);
6642 static int bnx2x_init_rss_pf(struct bnx2x_softc *sc)
6644 uint8_t num_eth_queues = BNX2X_NUM_ETH_QUEUES(sc);
6648 * Prepare the initial contents of the indirection table if
6651 for (i = 0; i < sizeof(sc->rss_conf_obj.ind_table); i++) {
6652 sc->rss_conf_obj.ind_table[i] =
6653 (sc->fp->cl_id + (i % num_eth_queues));
6657 sc->rss_conf_obj.udp_rss_v4 = sc->rss_conf_obj.udp_rss_v6 = 1;
6661 * For 57711 SEARCHER configuration (rss_keys) is
6662 * per-port, so if explicit configuration is needed, do it only
6665 * For 57712 and newer it's a per-function configuration.
6667 return bnx2x_config_rss_eth(sc, sc->port.pmf || !CHIP_IS_E1x(sc));
6671 bnx2x_set_mac_one(struct bnx2x_softc *sc, uint8_t * mac,
6672 struct ecore_vlan_mac_obj *obj, uint8_t set, int mac_type,
6673 unsigned long *ramrod_flags)
6675 struct ecore_vlan_mac_ramrod_params ramrod_param;
6678 memset(&ramrod_param, 0, sizeof(ramrod_param));
6680 /* fill in general parameters */
6681 ramrod_param.vlan_mac_obj = obj;
6682 ramrod_param.ramrod_flags = *ramrod_flags;
6684 /* fill a user request section if needed */
6685 if (!bnx2x_test_bit(RAMROD_CONT, ramrod_flags)) {
6686 (void)rte_memcpy(ramrod_param.user_req.u.mac.mac, mac,
6689 bnx2x_set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
6691 /* Set the command: ADD or DEL */
6692 ramrod_param.user_req.cmd = (set) ? ECORE_VLAN_MAC_ADD :
6696 rc = ecore_config_vlan_mac(sc, &ramrod_param);
6698 if (rc == ECORE_EXISTS) {
6699 PMD_DRV_LOG(INFO, "Failed to schedule ADD operations (EEXIST)");
6700 /* do not treat adding same MAC as error */
6702 } else if (rc < 0) {
6704 "%s MAC failed (%d)", (set ? "Set" : "Delete"), rc);
6710 static int bnx2x_set_eth_mac(struct bnx2x_softc *sc, uint8_t set)
6712 unsigned long ramrod_flags = 0;
6714 PMD_DRV_LOG(DEBUG, "Adding Ethernet MAC");
6716 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
6718 /* Eth MAC is set on RSS leading client (fp[0]) */
6719 return bnx2x_set_mac_one(sc, sc->link_params.mac_addr,
6720 &sc->sp_objs->mac_obj,
6721 set, ECORE_ETH_MAC, &ramrod_flags);
6724 static int bnx2x_get_cur_phy_idx(struct bnx2x_softc *sc)
6726 uint32_t sel_phy_idx = 0;
6728 if (sc->link_params.num_phys <= 1) {
6729 return ELINK_INT_PHY;
6732 if (sc->link_vars.link_up) {
6733 sel_phy_idx = ELINK_EXT_PHY1;
6734 /* In case link is SERDES, check if the ELINK_EXT_PHY2 is the one */
6735 if ((sc->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
6736 (sc->link_params.phy[ELINK_EXT_PHY2].supported &
6737 ELINK_SUPPORTED_FIBRE))
6738 sel_phy_idx = ELINK_EXT_PHY2;
6740 switch (elink_phy_selection(&sc->link_params)) {
6741 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6742 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
6743 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6744 sel_phy_idx = ELINK_EXT_PHY1;
6746 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
6747 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6748 sel_phy_idx = ELINK_EXT_PHY2;
6756 static int bnx2x_get_link_cfg_idx(struct bnx2x_softc *sc)
6758 uint32_t sel_phy_idx = bnx2x_get_cur_phy_idx(sc);
6761 * The selected activated PHY is always after swapping (in case PHY
6762 * swapping is enabled). So when swapping is enabled, we need to reverse
6766 if (sc->link_params.multi_phy_config & PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
6767 if (sel_phy_idx == ELINK_EXT_PHY1)
6768 sel_phy_idx = ELINK_EXT_PHY2;
6769 else if (sel_phy_idx == ELINK_EXT_PHY2)
6770 sel_phy_idx = ELINK_EXT_PHY1;
6773 return ELINK_LINK_CONFIG_IDX(sel_phy_idx);
6776 static void bnx2x_set_requested_fc(struct bnx2x_softc *sc)
6779 * Initialize link parameters structure variables
6780 * It is recommended to turn off RX FC for jumbo frames
6781 * for better performance
6783 if (CHIP_IS_E1x(sc) && (sc->mtu > 5000)) {
6784 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_TX;
6786 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_BOTH;
6790 static void bnx2x_calc_fc_adv(struct bnx2x_softc *sc)
6792 uint8_t cfg_idx = bnx2x_get_link_cfg_idx(sc);
6793 switch (sc->link_vars.ieee_fc &
6794 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
6795 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
6797 sc->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
6801 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
6802 sc->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
6806 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
6807 sc->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
6812 static uint16_t bnx2x_get_mf_speed(struct bnx2x_softc *sc)
6814 uint16_t line_speed = sc->link_vars.line_speed;
6816 uint16_t maxCfg = bnx2x_extract_max_cfg(sc,
6818 mf_info.mf_config[SC_VN
6821 /* calculate the current MAX line speed limit for the MF devices */
6823 line_speed = (line_speed * maxCfg) / 100;
6824 } else { /* SD mode */
6825 uint16_t vn_max_rate = maxCfg * 100;
6827 if (vn_max_rate < line_speed) {
6828 line_speed = vn_max_rate;
6837 bnx2x_fill_report_data(struct bnx2x_softc *sc, struct bnx2x_link_report_data *data)
6839 uint16_t line_speed = bnx2x_get_mf_speed(sc);
6841 memset(data, 0, sizeof(*data));
6843 /* fill the report data with the effective line speed */
6844 data->line_speed = line_speed;
6847 if (!sc->link_vars.link_up || (sc->flags & BNX2X_MF_FUNC_DIS)) {
6848 bnx2x_set_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6849 &data->link_report_flags);
6853 if (sc->link_vars.duplex == DUPLEX_FULL) {
6854 bnx2x_set_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6855 &data->link_report_flags);
6858 /* Rx Flow Control is ON */
6859 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_RX) {
6860 bnx2x_set_bit(BNX2X_LINK_REPORT_RX_FC_ON, &data->link_report_flags);
6863 /* Tx Flow Control is ON */
6864 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
6865 bnx2x_set_bit(BNX2X_LINK_REPORT_TX_FC_ON, &data->link_report_flags);
6869 /* report link status to OS, should be called under phy_lock */
6870 static void bnx2x_link_report(struct bnx2x_softc *sc)
6872 struct bnx2x_link_report_data cur_data;
6876 bnx2x_read_mf_cfg(sc);
6879 /* Read the current link report info */
6880 bnx2x_fill_report_data(sc, &cur_data);
6882 /* Don't report link down or exactly the same link status twice */
6883 if (!memcmp(&cur_data, &sc->last_reported_link, sizeof(cur_data)) ||
6884 (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6885 &sc->last_reported_link.link_report_flags) &&
6886 bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6887 &cur_data.link_report_flags))) {
6893 /* report new link params and remember the state for the next time */
6894 (void)rte_memcpy(&sc->last_reported_link, &cur_data, sizeof(cur_data));
6896 if (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6897 &cur_data.link_report_flags)) {
6898 PMD_DRV_LOG(INFO, "NIC Link is Down");
6900 __rte_unused const char *duplex;
6901 __rte_unused const char *flow;
6903 if (bnx2x_test_and_clear_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6904 &cur_data.link_report_flags)) {
6911 * Handle the FC at the end so that only these flags would be
6912 * possibly set. This way we may easily check if there is no FC
6915 if (cur_data.link_report_flags) {
6916 if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6917 &cur_data.link_report_flags) &&
6918 bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6919 &cur_data.link_report_flags)) {
6920 flow = "ON - receive & transmit";
6921 } else if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6922 &cur_data.link_report_flags) &&
6923 !bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6924 &cur_data.link_report_flags)) {
6925 flow = "ON - receive";
6926 } else if (!bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6927 &cur_data.link_report_flags) &&
6928 bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6929 &cur_data.link_report_flags)) {
6930 flow = "ON - transmit";
6932 flow = "none"; /* possible? */
6939 "NIC Link is Up, %d Mbps %s duplex, Flow control: %s",
6940 cur_data.line_speed, duplex, flow);
6944 void bnx2x_link_status_update(struct bnx2x_softc *sc)
6946 if (sc->state != BNX2X_STATE_OPEN) {
6950 if (IS_PF(sc) && !CHIP_REV_IS_SLOW(sc)) {
6951 elink_link_status_update(&sc->link_params, &sc->link_vars);
6953 sc->port.supported[0] |= (ELINK_SUPPORTED_10baseT_Half |
6954 ELINK_SUPPORTED_10baseT_Full |
6955 ELINK_SUPPORTED_100baseT_Half |
6956 ELINK_SUPPORTED_100baseT_Full |
6957 ELINK_SUPPORTED_1000baseT_Full |
6958 ELINK_SUPPORTED_2500baseX_Full |
6959 ELINK_SUPPORTED_10000baseT_Full |
6960 ELINK_SUPPORTED_TP |
6961 ELINK_SUPPORTED_FIBRE |
6962 ELINK_SUPPORTED_Autoneg |
6963 ELINK_SUPPORTED_Pause |
6964 ELINK_SUPPORTED_Asym_Pause);
6965 sc->port.advertising[0] = sc->port.supported[0];
6967 sc->link_params.sc = sc;
6968 sc->link_params.port = SC_PORT(sc);
6969 sc->link_params.req_duplex[0] = DUPLEX_FULL;
6970 sc->link_params.req_flow_ctrl[0] = ELINK_FLOW_CTRL_NONE;
6971 sc->link_params.req_line_speed[0] = SPEED_10000;
6972 sc->link_params.speed_cap_mask[0] = 0x7f0000;
6973 sc->link_params.switch_cfg = ELINK_SWITCH_CFG_10G;
6975 if (CHIP_REV_IS_FPGA(sc)) {
6976 sc->link_vars.mac_type = ELINK_MAC_TYPE_EMAC;
6977 sc->link_vars.line_speed = ELINK_SPEED_1000;
6978 sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
6979 LINK_STATUS_SPEED_AND_DUPLEX_1000TFD);
6981 sc->link_vars.mac_type = ELINK_MAC_TYPE_BMAC;
6982 sc->link_vars.line_speed = ELINK_SPEED_10000;
6983 sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
6984 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
6987 sc->link_vars.link_up = 1;
6989 sc->link_vars.duplex = DUPLEX_FULL;
6990 sc->link_vars.flow_ctrl = ELINK_FLOW_CTRL_NONE;
6994 NIG_REG_EGRESS_DRAIN0_MODE +
6995 sc->link_params.port * 4, 0);
6996 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
6997 bnx2x_link_report(sc);
7002 if (sc->link_vars.link_up) {
7003 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7005 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
7007 bnx2x_link_report(sc);
7009 bnx2x_link_report(sc);
7010 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7014 static void bnx2x_periodic_start(struct bnx2x_softc *sc)
7016 atomic_store_rel_long(&sc->periodic_flags, PERIODIC_GO);
7019 static void bnx2x_periodic_stop(struct bnx2x_softc *sc)
7021 atomic_store_rel_long(&sc->periodic_flags, PERIODIC_STOP);
7024 static int bnx2x_initial_phy_init(struct bnx2x_softc *sc, int load_mode)
7026 int rc, cfg_idx = bnx2x_get_link_cfg_idx(sc);
7027 uint16_t req_line_speed = sc->link_params.req_line_speed[cfg_idx];
7028 struct elink_params *lp = &sc->link_params;
7030 bnx2x_set_requested_fc(sc);
7032 if (CHIP_REV_IS_SLOW(sc)) {
7033 uint32_t bond = CHIP_BOND_ID(sc);
7036 if (CHIP_IS_E2(sc) && CHIP_IS_MODE_4_PORT(sc)) {
7037 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC;
7038 } else if (bond & 0x4) {
7039 if (CHIP_IS_E3(sc)) {
7040 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC;
7042 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC;
7044 } else if (bond & 0x8) {
7045 if (CHIP_IS_E3(sc)) {
7046 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_UMAC;
7048 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC;
7052 /* disable EMAC for E3 and above */
7054 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC;
7057 sc->link_params.feature_config_flags |= feat;
7060 if (load_mode == LOAD_DIAG) {
7061 lp->loopback_mode = ELINK_LOOPBACK_XGXS;
7062 /* Prefer doing PHY loopback at 10G speed, if possible */
7063 if (lp->req_line_speed[cfg_idx] < ELINK_SPEED_10000) {
7064 if (lp->speed_cap_mask[cfg_idx] &
7065 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
7066 lp->req_line_speed[cfg_idx] = ELINK_SPEED_10000;
7068 lp->req_line_speed[cfg_idx] = ELINK_SPEED_1000;
7073 if (load_mode == LOAD_LOOPBACK_EXT) {
7074 lp->loopback_mode = ELINK_LOOPBACK_EXT;
7077 rc = elink_phy_init(&sc->link_params, &sc->link_vars);
7079 bnx2x_calc_fc_adv(sc);
7081 if (sc->link_vars.link_up) {
7082 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7083 bnx2x_link_report(sc);
7086 if (!CHIP_REV_IS_SLOW(sc)) {
7087 bnx2x_periodic_start(sc);
7090 sc->link_params.req_line_speed[cfg_idx] = req_line_speed;
7094 /* update flags in shmem */
7096 bnx2x_update_drv_flags(struct bnx2x_softc *sc, uint32_t flags, uint32_t set)
7100 if (SHMEM2_HAS(sc, drv_flags)) {
7101 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7102 drv_flags = SHMEM2_RD(sc, drv_flags);
7107 drv_flags &= ~flags;
7110 SHMEM2_WR(sc, drv_flags, drv_flags);
7112 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7116 /* periodic timer callout routine, only runs when the interface is up */
7117 void bnx2x_periodic_callout(struct bnx2x_softc *sc)
7119 if ((sc->state != BNX2X_STATE_OPEN) ||
7120 (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_STOP)) {
7121 PMD_DRV_LOG(WARNING, "periodic callout exit (state=0x%x)",
7125 if (!CHIP_REV_IS_SLOW(sc)) {
7127 * This barrier is needed to ensure the ordering between the writing
7128 * to the sc->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
7133 elink_period_func(&sc->link_params, &sc->link_vars);
7137 if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7138 int mb_idx = SC_FW_MB_IDX(sc);
7142 ++sc->fw_drv_pulse_wr_seq;
7143 sc->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
7145 drv_pulse = sc->fw_drv_pulse_wr_seq;
7146 bnx2x_drv_pulse(sc);
7148 mcp_pulse = (SHMEM_RD(sc, func_mb[mb_idx].mcp_pulse_mb) &
7149 MCP_PULSE_SEQ_MASK);
7152 * The delta between driver pulse and mcp response should
7153 * be 1 (before mcp response) or 0 (after mcp response).
7155 if ((drv_pulse != mcp_pulse) &&
7156 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
7157 /* someone lost a heartbeat... */
7159 "drv_pulse (0x%x) != mcp_pulse (0x%x)",
7160 drv_pulse, mcp_pulse);
7166 /* start the controller */
7167 static __attribute__ ((noinline))
7168 int bnx2x_nic_load(struct bnx2x_softc *sc)
7171 uint32_t load_code = 0;
7174 PMD_INIT_FUNC_TRACE();
7176 sc->state = BNX2X_STATE_OPENING_WAITING_LOAD;
7179 /* must be called before memory allocation and HW init */
7180 bnx2x_ilt_set_info(sc);
7183 bnx2x_set_fp_rx_buf_size(sc);
7186 if (bnx2x_alloc_mem(sc) != 0) {
7187 sc->state = BNX2X_STATE_CLOSED;
7189 goto bnx2x_nic_load_error0;
7193 if (bnx2x_alloc_fw_stats_mem(sc) != 0) {
7194 sc->state = BNX2X_STATE_CLOSED;
7196 goto bnx2x_nic_load_error0;
7200 rc = bnx2x_vf_init(sc);
7202 sc->state = BNX2X_STATE_ERROR;
7203 goto bnx2x_nic_load_error0;
7208 /* set pf load just before approaching the MCP */
7209 bnx2x_set_pf_load(sc);
7211 /* if MCP exists send load request and analyze response */
7212 if (!BNX2X_NOMCP(sc)) {
7213 /* attempt to load pf */
7214 if (bnx2x_nic_load_request(sc, &load_code) != 0) {
7215 sc->state = BNX2X_STATE_CLOSED;
7217 goto bnx2x_nic_load_error1;
7220 /* what did the MCP say? */
7221 if (bnx2x_nic_load_analyze_req(sc, load_code) != 0) {
7222 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7223 sc->state = BNX2X_STATE_CLOSED;
7225 goto bnx2x_nic_load_error2;
7228 PMD_DRV_LOG(INFO, "Device has no MCP!");
7229 load_code = bnx2x_nic_load_no_mcp(sc);
7232 /* mark PMF if applicable */
7233 bnx2x_nic_load_pmf(sc, load_code);
7235 /* Init Function state controlling object */
7236 bnx2x_init_func_obj(sc);
7239 if (bnx2x_init_hw(sc, load_code) != 0) {
7240 PMD_DRV_LOG(NOTICE, "HW init failed");
7241 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7242 sc->state = BNX2X_STATE_CLOSED;
7244 goto bnx2x_nic_load_error2;
7248 bnx2x_nic_init(sc, load_code);
7250 /* Init per-function objects */
7252 bnx2x_init_objs(sc);
7254 /* set AFEX default VLAN tag to an invalid value */
7255 sc->devinfo.mf_info.afex_def_vlan_tag = -1;
7257 sc->state = BNX2X_STATE_OPENING_WAITING_PORT;
7258 rc = bnx2x_func_start(sc);
7260 PMD_DRV_LOG(NOTICE, "Function start failed!");
7261 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7262 sc->state = BNX2X_STATE_ERROR;
7263 goto bnx2x_nic_load_error3;
7266 /* send LOAD_DONE command to MCP */
7267 if (!BNX2X_NOMCP(sc)) {
7269 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7272 "MCP response failure, aborting");
7273 sc->state = BNX2X_STATE_ERROR;
7275 goto bnx2x_nic_load_error3;
7280 rc = bnx2x_setup_leading(sc);
7282 PMD_DRV_LOG(NOTICE, "Setup leading failed!");
7283 sc->state = BNX2X_STATE_ERROR;
7284 goto bnx2x_nic_load_error3;
7287 FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, i) {
7289 rc = bnx2x_setup_queue(sc, &sc->fp[i], FALSE);
7290 else /* IS_VF(sc) */
7291 rc = bnx2x_vf_setup_queue(sc, &sc->fp[i], FALSE);
7294 PMD_DRV_LOG(NOTICE, "Queue(%d) setup failed", i);
7295 sc->state = BNX2X_STATE_ERROR;
7296 goto bnx2x_nic_load_error3;
7300 rc = bnx2x_init_rss_pf(sc);
7302 PMD_DRV_LOG(NOTICE, "PF RSS init failed");
7303 sc->state = BNX2X_STATE_ERROR;
7304 goto bnx2x_nic_load_error3;
7307 /* now when Clients are configured we are ready to work */
7308 sc->state = BNX2X_STATE_OPEN;
7310 /* Configure a ucast MAC */
7312 rc = bnx2x_set_eth_mac(sc, TRUE);
7313 } else { /* IS_VF(sc) */
7314 rc = bnx2x_vf_set_mac(sc, TRUE);
7318 PMD_DRV_LOG(NOTICE, "Setting Ethernet MAC failed");
7319 sc->state = BNX2X_STATE_ERROR;
7320 goto bnx2x_nic_load_error3;
7324 rc = bnx2x_initial_phy_init(sc, LOAD_OPEN);
7326 sc->state = BNX2X_STATE_ERROR;
7327 goto bnx2x_nic_load_error3;
7331 sc->link_params.feature_config_flags &=
7332 ~ELINK_FEATURE_CONFIG_BOOT_FROM_SAN;
7335 switch (LOAD_OPEN) {
7341 case LOAD_LOOPBACK_EXT:
7342 sc->state = BNX2X_STATE_DIAG;
7350 bnx2x_update_drv_flags(sc, 1 << DRV_FLAGS_PORT_MASK, 0);
7352 bnx2x_link_status_update(sc);
7355 if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
7356 /* mark driver is loaded in shmem2 */
7357 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
7358 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
7360 DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED |
7361 DRV_FLAGS_CAPABILITIES_LOADED_L2));
7364 /* start fast path */
7365 /* Initialize Rx filter */
7366 bnx2x_set_rx_mode(sc);
7368 /* wait for all pending SP commands to complete */
7369 if (IS_PF(sc) && !bnx2x_wait_sp_comp(sc, ~0x0UL)) {
7370 PMD_DRV_LOG(NOTICE, "Timeout waiting for all SPs to complete!");
7371 bnx2x_periodic_stop(sc);
7372 bnx2x_nic_unload(sc, UNLOAD_CLOSE, FALSE);
7376 PMD_DRV_LOG(DEBUG, "NIC successfully loaded");
7380 bnx2x_nic_load_error3:
7383 bnx2x_int_disable_sync(sc, 1);
7385 /* clean out queued objects */
7386 bnx2x_squeeze_objects(sc);
7389 bnx2x_nic_load_error2:
7391 if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7392 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
7393 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
7398 bnx2x_nic_load_error1:
7400 /* clear pf_load status, as it was already set */
7402 bnx2x_clear_pf_load(sc);
7405 bnx2x_nic_load_error0:
7407 bnx2x_free_fw_stats_mem(sc);
7414 * Handles controller initialization.
7416 int bnx2x_init(struct bnx2x_softc *sc)
7418 int other_engine = SC_PATH(sc) ? 0 : 1;
7419 uint8_t other_load_status, load_status;
7420 uint8_t global = FALSE;
7423 /* Check if the driver is still running and bail out if it is. */
7424 if (sc->state != BNX2X_STATE_CLOSED) {
7425 PMD_DRV_LOG(DEBUG, "Init called while driver is running!");
7427 goto bnx2x_init_done;
7430 bnx2x_set_power_state(sc, PCI_PM_D0);
7433 * If parity occurred during the unload, then attentions and/or
7434 * RECOVERY_IN_PROGRESS may still be set. If so we want the first function
7435 * loaded on the current engine to complete the recovery. Parity recovery
7436 * is only relevant for PF driver.
7439 other_load_status = bnx2x_get_load_status(sc, other_engine);
7440 load_status = bnx2x_get_load_status(sc, SC_PATH(sc));
7442 if (!bnx2x_reset_is_done(sc, SC_PATH(sc)) ||
7443 bnx2x_chk_parity_attn(sc, &global, TRUE)) {
7446 * If there are attentions and they are in global blocks, set
7447 * the GLOBAL_RESET bit regardless whether it will be this
7448 * function that will complete the recovery or not.
7451 bnx2x_set_reset_global(sc);
7455 * Only the first function on the current engine should try
7456 * to recover in open. In case of attentions in global blocks
7457 * only the first in the chip should try to recover.
7460 && (!global ||!other_load_status))
7461 && bnx2x_trylock_leader_lock(sc)
7462 && !bnx2x_leader_reset(sc)) {
7464 "Recovered during init");
7468 /* recovery has failed... */
7469 bnx2x_set_power_state(sc, PCI_PM_D3hot);
7471 sc->recovery_state = BNX2X_RECOVERY_FAILED;
7474 "Recovery flow hasn't properly "
7475 "completed yet, try again later. "
7476 "If you still see this message after a "
7477 "few retries then power cycle is required.");
7480 goto bnx2x_init_done;
7485 sc->recovery_state = BNX2X_RECOVERY_DONE;
7487 rc = bnx2x_nic_load(sc);
7492 PMD_DRV_LOG(NOTICE, "Initialization failed, "
7493 "stack notified driver is NOT running!");
7499 static void bnx2x_get_function_num(struct bnx2x_softc *sc)
7504 * Read the ME register to get the function number. The ME register
7505 * holds the relative-function number and absolute-function number. The
7506 * absolute-function number appears only in E2 and above. Before that
7507 * these bits always contained zero, therefore we cannot blindly use them.
7510 val = REG_RD(sc, BAR_ME_REGISTER);
7513 (uint8_t) ((val & ME_REG_PF_NUM) >> ME_REG_PF_NUM_SHIFT);
7515 (uint8_t) ((val & ME_REG_ABS_PF_NUM) >> ME_REG_ABS_PF_NUM_SHIFT) &
7518 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7519 sc->pfunc_abs = ((sc->pfunc_rel << 1) | sc->path_id);
7521 sc->pfunc_abs = (sc->pfunc_rel | sc->path_id);
7525 "Relative function %d, Absolute function %d, Path %d",
7526 sc->pfunc_rel, sc->pfunc_abs, sc->path_id);
7529 static uint32_t bnx2x_get_shmem_mf_cfg_base(struct bnx2x_softc *sc)
7531 uint32_t shmem2_size;
7533 uint32_t mf_cfg_offset_value;
7536 offset = (SHMEM_ADDR(sc, func_mb) +
7537 (MAX_FUNC_NUM * sizeof(struct drv_func_mb)));
7540 if (sc->devinfo.shmem2_base != 0) {
7541 shmem2_size = SHMEM2_RD(sc, size);
7542 if (shmem2_size > offsetof(struct shmem2_region, mf_cfg_addr)) {
7543 mf_cfg_offset_value = SHMEM2_RD(sc, mf_cfg_addr);
7544 if (SHMEM_MF_CFG_ADDR_NONE != mf_cfg_offset_value) {
7545 offset = mf_cfg_offset_value;
7553 static uint32_t bnx2x_pcie_capability_read(struct bnx2x_softc *sc, int reg)
7556 struct bnx2x_pci_cap *caps;
7558 /* ensure PCIe capability is enabled */
7559 caps = pci_find_cap(sc, PCIY_EXPRESS, BNX2X_PCI_CAP);
7561 PMD_DRV_LOG(DEBUG, "Found PCIe capability: "
7562 "id=0x%04X type=0x%04X addr=0x%08X",
7563 caps->id, caps->type, caps->addr);
7564 pci_read(sc, (caps->addr + reg), &ret, 2);
7568 PMD_DRV_LOG(WARNING, "PCIe capability NOT FOUND!!!");
7573 static uint8_t bnx2x_is_pcie_pending(struct bnx2x_softc *sc)
7575 return bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_STA) &
7576 PCIM_EXP_STA_TRANSACTION_PND;
7580 * Walk the PCI capabiites list for the device to find what features are
7581 * supported. These capabilites may be enabled/disabled by firmware so it's
7582 * best to walk the list rather than make assumptions.
7584 static void bnx2x_probe_pci_caps(struct bnx2x_softc *sc)
7586 PMD_INIT_FUNC_TRACE();
7588 struct bnx2x_pci_cap *caps;
7589 uint16_t link_status;
7590 #ifdef RTE_LIBRTE_BNX2X_DEBUG
7594 /* check if PCI Power Management is enabled */
7595 caps = pci_find_cap(sc, PCIY_PMG, BNX2X_PCI_CAP);
7597 PMD_DRV_LOG(DEBUG, "Found PM capability: "
7598 "id=0x%04X type=0x%04X addr=0x%08X",
7599 caps->id, caps->type, caps->addr);
7601 sc->devinfo.pcie_cap_flags |= BNX2X_PM_CAPABLE_FLAG;
7602 sc->devinfo.pcie_pm_cap_reg = caps->addr;
7605 link_status = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_LINK_STA);
7607 sc->devinfo.pcie_link_speed = (link_status & PCIM_LINK_STA_SPEED);
7608 sc->devinfo.pcie_link_width =
7609 ((link_status & PCIM_LINK_STA_WIDTH) >> 4);
7611 PMD_DRV_LOG(DEBUG, "PCIe link speed=%d width=%d",
7612 sc->devinfo.pcie_link_speed, sc->devinfo.pcie_link_width);
7614 sc->devinfo.pcie_cap_flags |= BNX2X_PCIE_CAPABLE_FLAG;
7616 /* check if MSI capability is enabled */
7617 caps = pci_find_cap(sc, PCIY_MSI, BNX2X_PCI_CAP);
7619 PMD_DRV_LOG(DEBUG, "Found MSI capability at 0x%04x", reg);
7621 sc->devinfo.pcie_cap_flags |= BNX2X_MSI_CAPABLE_FLAG;
7622 sc->devinfo.pcie_msi_cap_reg = caps->addr;
7625 /* check if MSI-X capability is enabled */
7626 caps = pci_find_cap(sc, PCIY_MSIX, BNX2X_PCI_CAP);
7628 PMD_DRV_LOG(DEBUG, "Found MSI-X capability at 0x%04x", reg);
7630 sc->devinfo.pcie_cap_flags |= BNX2X_MSIX_CAPABLE_FLAG;
7631 sc->devinfo.pcie_msix_cap_reg = caps->addr;
7635 static int bnx2x_get_shmem_mf_cfg_info_sd(struct bnx2x_softc *sc)
7637 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7640 /* get the outer vlan if we're in switch-dependent mode */
7642 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7643 mf_info->ext_id = (uint16_t) val;
7645 mf_info->multi_vnics_mode = 1;
7647 if (!VALID_OVLAN(mf_info->ext_id)) {
7648 PMD_DRV_LOG(NOTICE, "Invalid VLAN (%d)", mf_info->ext_id);
7652 /* get the capabilities */
7653 if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK) ==
7654 FUNC_MF_CFG_PROTOCOL_ISCSI) {
7655 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ISCSI;
7656 } else if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK)
7657 == FUNC_MF_CFG_PROTOCOL_FCOE) {
7658 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_FCOE;
7660 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ETHERNET;
7663 mf_info->vnics_per_port =
7664 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7669 static uint32_t bnx2x_get_shmem_ext_proto_support_flags(struct bnx2x_softc *sc)
7671 uint32_t retval = 0;
7674 val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7676 if (val & MACP_FUNC_CFG_FLAGS_ENABLED) {
7677 if (val & MACP_FUNC_CFG_FLAGS_ETHERNET) {
7678 retval |= MF_PROTO_SUPPORT_ETHERNET;
7680 if (val & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
7681 retval |= MF_PROTO_SUPPORT_ISCSI;
7683 if (val & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
7684 retval |= MF_PROTO_SUPPORT_FCOE;
7691 static int bnx2x_get_shmem_mf_cfg_info_si(struct bnx2x_softc *sc)
7693 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7697 * There is no outer vlan if we're in switch-independent mode.
7698 * If the mac is valid then assume multi-function.
7701 val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7703 mf_info->multi_vnics_mode = ((val & MACP_FUNC_CFG_FLAGS_MASK) != 0);
7705 mf_info->mf_protos_supported =
7706 bnx2x_get_shmem_ext_proto_support_flags(sc);
7708 mf_info->vnics_per_port =
7709 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7714 static int bnx2x_get_shmem_mf_cfg_info_niv(struct bnx2x_softc *sc)
7716 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7718 uint32_t func_config;
7719 uint32_t niv_config;
7721 mf_info->multi_vnics_mode = 1;
7723 e1hov_tag = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7724 func_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7725 niv_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].afex_config);
7728 (uint16_t) ((e1hov_tag & FUNC_MF_CFG_E1HOV_TAG_MASK) >>
7729 FUNC_MF_CFG_E1HOV_TAG_SHIFT);
7731 mf_info->default_vlan =
7732 (uint16_t) ((e1hov_tag & FUNC_MF_CFG_AFEX_VLAN_MASK) >>
7733 FUNC_MF_CFG_AFEX_VLAN_SHIFT);
7735 mf_info->niv_allowed_priorities =
7736 (uint8_t) ((niv_config & FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
7737 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT);
7739 mf_info->niv_default_cos =
7740 (uint8_t) ((func_config & FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
7741 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT);
7743 mf_info->afex_vlan_mode =
7744 ((niv_config & FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
7745 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT);
7747 mf_info->niv_mba_enabled =
7748 ((niv_config & FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK) >>
7749 FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT);
7751 mf_info->mf_protos_supported =
7752 bnx2x_get_shmem_ext_proto_support_flags(sc);
7754 mf_info->vnics_per_port =
7755 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7760 static int bnx2x_check_valid_mf_cfg(struct bnx2x_softc *sc)
7762 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7769 /* various MF mode sanity checks... */
7771 if (mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_HIDE) {
7773 "Enumerated function %d is marked as hidden",
7778 if ((mf_info->vnics_per_port > 1) && !mf_info->multi_vnics_mode) {
7779 PMD_DRV_LOG(NOTICE, "vnics_per_port=%d multi_vnics_mode=%d",
7780 mf_info->vnics_per_port, mf_info->multi_vnics_mode);
7784 if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7785 /* vnic id > 0 must have valid ovlan in switch-dependent mode */
7786 if ((SC_VN(sc) > 0) && !VALID_OVLAN(OVLAN(sc))) {
7787 PMD_DRV_LOG(NOTICE, "mf_mode=SD vnic_id=%d ovlan=%d",
7788 SC_VN(sc), OVLAN(sc));
7792 if (!VALID_OVLAN(OVLAN(sc)) && mf_info->multi_vnics_mode) {
7794 "mf_mode=SD multi_vnics_mode=%d ovlan=%d",
7795 mf_info->multi_vnics_mode, OVLAN(sc));
7800 * Verify all functions are either MF or SF mode. If MF, make sure
7801 * sure that all non-hidden functions have a valid ovlan. If SF,
7802 * make sure that all non-hidden functions have an invalid ovlan.
7804 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7805 mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7806 ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7807 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE) &&
7808 (((mf_info->multi_vnics_mode)
7809 && !VALID_OVLAN(ovlan1))
7810 || ((!mf_info->multi_vnics_mode)
7811 && VALID_OVLAN(ovlan1)))) {
7813 "mf_mode=SD function %d MF config "
7814 "mismatch, multi_vnics_mode=%d ovlan=%d",
7815 i, mf_info->multi_vnics_mode,
7821 /* Verify all funcs on the same port each have a different ovlan. */
7822 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7823 mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7824 ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7825 /* iterate from the next function on the port to the max func */
7826 for (j = i + 2; j < MAX_FUNC_NUM; j += 2) {
7828 MFCFG_RD(sc, func_mf_config[j].config);
7830 MFCFG_RD(sc, func_mf_config[j].e1hov_tag);
7831 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE)
7832 && VALID_OVLAN(ovlan1)
7833 && !(mf_cfg2 & FUNC_MF_CFG_FUNC_HIDE)
7834 && VALID_OVLAN(ovlan2)
7835 && (ovlan1 == ovlan2)) {
7837 "mf_mode=SD functions %d and %d "
7838 "have the same ovlan (%d)",
7845 /* MULTI_FUNCTION_SD */
7849 static int bnx2x_get_mf_cfg_info(struct bnx2x_softc *sc)
7851 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7852 uint32_t val, mac_upper;
7855 /* initialize mf_info defaults */
7856 mf_info->vnics_per_port = 1;
7857 mf_info->multi_vnics_mode = FALSE;
7858 mf_info->path_has_ovlan = FALSE;
7859 mf_info->mf_mode = SINGLE_FUNCTION;
7861 if (!CHIP_IS_MF_CAP(sc)) {
7865 if (sc->devinfo.mf_cfg_base == SHMEM_MF_CFG_ADDR_NONE) {
7866 PMD_DRV_LOG(NOTICE, "Invalid mf_cfg_base!");
7870 /* get the MF mode (switch dependent / independent / single-function) */
7872 val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
7874 switch (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK) {
7875 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
7878 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7880 /* check for legal upper mac bytes */
7881 if (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT) {
7882 mf_info->mf_mode = MULTI_FUNCTION_SI;
7885 "Invalid config for Switch Independent mode");
7890 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
7891 case SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4:
7893 /* get outer vlan configuration */
7894 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7896 if ((val & FUNC_MF_CFG_E1HOV_TAG_MASK) !=
7897 FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
7898 mf_info->mf_mode = MULTI_FUNCTION_SD;
7901 "Invalid config for Switch Dependent mode");
7906 case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
7908 /* not in MF mode, vnics_per_port=1 and multi_vnics_mode=FALSE */
7911 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
7914 * Mark MF mode as NIV if MCP version includes NPAR-SD support
7915 * and the MAC address is valid.
7918 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7920 if ((SHMEM2_HAS(sc, afex_driver_support)) &&
7921 (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT)) {
7922 mf_info->mf_mode = MULTI_FUNCTION_AFEX;
7924 PMD_DRV_LOG(NOTICE, "Invalid config for AFEX mode");
7931 PMD_DRV_LOG(NOTICE, "Unknown MF mode (0x%08x)",
7932 (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK));
7937 /* set path mf_mode (which could be different than function mf_mode) */
7938 if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7939 mf_info->path_has_ovlan = TRUE;
7940 } else if (mf_info->mf_mode == SINGLE_FUNCTION) {
7942 * Decide on path multi vnics mode. If we're not in MF mode and in
7943 * 4-port mode, this is good enough to check vnic-0 of the other port
7946 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7947 uint8_t other_port = !(PORT_ID(sc) & 1);
7948 uint8_t abs_func_other_port =
7949 (SC_PATH(sc) + (2 * other_port));
7954 [abs_func_other_port].e1hov_tag);
7956 mf_info->path_has_ovlan = VALID_OVLAN((uint16_t) val);
7960 if (mf_info->mf_mode == SINGLE_FUNCTION) {
7961 /* invalid MF config */
7962 if (SC_VN(sc) >= 1) {
7963 PMD_DRV_LOG(NOTICE, "VNIC ID >= 1 in SF mode");
7970 /* get the MF configuration */
7971 mf_info->mf_config[SC_VN(sc)] =
7972 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7974 switch (mf_info->mf_mode) {
7975 case MULTI_FUNCTION_SD:
7977 bnx2x_get_shmem_mf_cfg_info_sd(sc);
7980 case MULTI_FUNCTION_SI:
7982 bnx2x_get_shmem_mf_cfg_info_si(sc);
7985 case MULTI_FUNCTION_AFEX:
7987 bnx2x_get_shmem_mf_cfg_info_niv(sc);
7992 PMD_DRV_LOG(NOTICE, "Get MF config failed (mf_mode=0x%08x)",
7997 /* get the congestion management parameters */
8000 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
8001 /* get min/max bw */
8002 val = MFCFG_RD(sc, func_mf_config[i].config);
8003 mf_info->min_bw[vnic] =
8004 ((val & FUNC_MF_CFG_MIN_BW_MASK) >>
8005 FUNC_MF_CFG_MIN_BW_SHIFT);
8006 mf_info->max_bw[vnic] =
8007 ((val & FUNC_MF_CFG_MAX_BW_MASK) >>
8008 FUNC_MF_CFG_MAX_BW_SHIFT);
8012 return bnx2x_check_valid_mf_cfg(sc);
8015 static int bnx2x_get_shmem_info(struct bnx2x_softc *sc)
8018 uint32_t mac_hi, mac_lo, val;
8020 PMD_INIT_FUNC_TRACE();
8023 mac_hi = mac_lo = 0;
8025 sc->link_params.sc = sc;
8026 sc->link_params.port = port;
8028 /* get the hardware config info */
8029 sc->devinfo.hw_config = SHMEM_RD(sc, dev_info.shared_hw_config.config);
8030 sc->devinfo.hw_config2 =
8031 SHMEM_RD(sc, dev_info.shared_hw_config.config2);
8033 sc->link_params.hw_led_mode =
8034 ((sc->devinfo.hw_config & SHARED_HW_CFG_LED_MODE_MASK) >>
8035 SHARED_HW_CFG_LED_MODE_SHIFT);
8037 /* get the port feature config */
8039 SHMEM_RD(sc, dev_info.port_feature_config[port].config);
8041 /* get the link params */
8042 sc->link_params.speed_cap_mask[ELINK_INT_PHY] =
8043 SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask)
8044 & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
8045 sc->link_params.speed_cap_mask[ELINK_EXT_PHY1] =
8046 SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask2)
8047 & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
8049 /* get the lane config */
8050 sc->link_params.lane_config =
8051 SHMEM_RD(sc, dev_info.port_hw_config[port].lane_config);
8053 /* get the link config */
8054 val = SHMEM_RD(sc, dev_info.port_feature_config[port].link_config);
8055 sc->port.link_config[ELINK_INT_PHY] = val;
8056 sc->link_params.switch_cfg = (val & PORT_FEATURE_CONNECTED_SWITCH_MASK);
8057 sc->port.link_config[ELINK_EXT_PHY1] =
8058 SHMEM_RD(sc, dev_info.port_feature_config[port].link_config2);
8060 /* get the override preemphasis flag and enable it or turn it off */
8061 val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
8062 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) {
8063 sc->link_params.feature_config_flags |=
8064 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8066 sc->link_params.feature_config_flags &=
8067 ~ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8070 /* get the initial value of the link params */
8071 sc->link_params.multi_phy_config =
8072 SHMEM_RD(sc, dev_info.port_hw_config[port].multi_phy_config);
8074 /* get external phy info */
8075 sc->port.ext_phy_config =
8076 SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
8078 /* get the multifunction configuration */
8079 bnx2x_get_mf_cfg_info(sc);
8081 /* get the mac address */
8084 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
8086 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_lower);
8088 mac_hi = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_upper);
8089 mac_lo = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_lower);
8092 if ((mac_lo == 0) && (mac_hi == 0)) {
8093 *sc->mac_addr_str = 0;
8094 PMD_DRV_LOG(NOTICE, "No Ethernet address programmed!");
8096 sc->link_params.mac_addr[0] = (uint8_t) (mac_hi >> 8);
8097 sc->link_params.mac_addr[1] = (uint8_t) (mac_hi);
8098 sc->link_params.mac_addr[2] = (uint8_t) (mac_lo >> 24);
8099 sc->link_params.mac_addr[3] = (uint8_t) (mac_lo >> 16);
8100 sc->link_params.mac_addr[4] = (uint8_t) (mac_lo >> 8);
8101 sc->link_params.mac_addr[5] = (uint8_t) (mac_lo);
8102 snprintf(sc->mac_addr_str, sizeof(sc->mac_addr_str),
8103 "%02x:%02x:%02x:%02x:%02x:%02x",
8104 sc->link_params.mac_addr[0],
8105 sc->link_params.mac_addr[1],
8106 sc->link_params.mac_addr[2],
8107 sc->link_params.mac_addr[3],
8108 sc->link_params.mac_addr[4],
8109 sc->link_params.mac_addr[5]);
8110 PMD_DRV_LOG(DEBUG, "Ethernet address: %s", sc->mac_addr_str);
8116 static void bnx2x_media_detect(struct bnx2x_softc *sc)
8118 uint32_t phy_idx = bnx2x_get_cur_phy_idx(sc);
8119 switch (sc->link_params.phy[phy_idx].media_type) {
8120 case ELINK_ETH_PHY_SFPP_10G_FIBER:
8121 case ELINK_ETH_PHY_SFP_1G_FIBER:
8122 case ELINK_ETH_PHY_XFP_FIBER:
8123 case ELINK_ETH_PHY_KR:
8124 case ELINK_ETH_PHY_CX4:
8125 PMD_DRV_LOG(INFO, "Found 10GBase-CX4 media.");
8126 sc->media = IFM_10G_CX4;
8128 case ELINK_ETH_PHY_DA_TWINAX:
8129 PMD_DRV_LOG(INFO, "Found 10Gb Twinax media.");
8130 sc->media = IFM_10G_TWINAX;
8132 case ELINK_ETH_PHY_BASE_T:
8133 PMD_DRV_LOG(INFO, "Found 10GBase-T media.");
8134 sc->media = IFM_10G_T;
8136 case ELINK_ETH_PHY_NOT_PRESENT:
8137 PMD_DRV_LOG(INFO, "Media not present.");
8140 case ELINK_ETH_PHY_UNSPECIFIED:
8142 PMD_DRV_LOG(INFO, "Unknown media!");
8148 #define GET_FIELD(value, fname) \
8149 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
8150 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
8151 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
8153 static int bnx2x_get_igu_cam_info(struct bnx2x_softc *sc)
8155 int pfid = SC_FUNC(sc);
8158 uint8_t fid, igu_sb_cnt = 0;
8160 sc->igu_base_sb = 0xff;
8162 if (CHIP_INT_MODE_IS_BC(sc)) {
8164 igu_sb_cnt = sc->igu_sb_cnt;
8165 sc->igu_base_sb = ((CHIP_IS_MODE_4_PORT(sc) ? pfid : vn) *
8167 sc->igu_dsb_id = (E1HVN_MAX * FP_SB_MAX_E1x +
8168 (CHIP_IS_MODE_4_PORT(sc) ? pfid : vn));
8172 /* IGU in normal mode - read CAM */
8174 igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; igu_sb_id++) {
8175 val = REG_RD(sc, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
8176 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) {
8180 if ((fid & IGU_FID_ENCODE_IS_PF)) {
8181 if ((fid & IGU_FID_PF_NUM_MASK) != pfid) {
8184 if (IGU_VEC(val) == 0) {
8185 /* default status block */
8186 sc->igu_dsb_id = igu_sb_id;
8188 if (sc->igu_base_sb == 0xff) {
8189 sc->igu_base_sb = igu_sb_id;
8197 * Due to new PF resource allocation by MFW T7.4 and above, it's optional
8198 * that number of CAM entries will not be equal to the value advertised in
8199 * PCI. Driver should use the minimal value of both as the actual status
8202 sc->igu_sb_cnt = min(sc->igu_sb_cnt, igu_sb_cnt);
8204 if (igu_sb_cnt == 0) {
8205 PMD_DRV_LOG(ERR, "CAM configuration error");
8213 * Gather various information from the device config space, the device itself,
8214 * shmem, and the user input.
8216 static int bnx2x_get_device_info(struct bnx2x_softc *sc)
8221 /* get the chip revision (chip metal comes from pci config space) */
8222 sc->devinfo.chip_id = sc->link_params.chip_id =
8223 (((REG_RD(sc, MISC_REG_CHIP_NUM) & 0xffff) << 16) |
8224 ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12) |
8225 (((REG_RD(sc, PCICFG_OFFSET + PCI_ID_VAL3) >> 24) & 0xf) << 4) |
8226 ((REG_RD(sc, MISC_REG_BOND_ID) & 0xf) << 0));
8228 /* force 57811 according to MISC register */
8229 if (REG_RD(sc, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
8230 if (CHIP_IS_57810(sc)) {
8231 sc->devinfo.chip_id = ((CHIP_NUM_57811 << 16) |
8233 devinfo.chip_id & 0x0000ffff));
8234 } else if (CHIP_IS_57810_MF(sc)) {
8235 sc->devinfo.chip_id = ((CHIP_NUM_57811_MF << 16) |
8237 devinfo.chip_id & 0x0000ffff));
8239 sc->devinfo.chip_id |= 0x1;
8243 "chip_id=0x%08x (num=0x%04x rev=0x%01x metal=0x%02x bond=0x%01x)",
8244 sc->devinfo.chip_id,
8245 ((sc->devinfo.chip_id >> 16) & 0xffff),
8246 ((sc->devinfo.chip_id >> 12) & 0xf),
8247 ((sc->devinfo.chip_id >> 4) & 0xff),
8248 ((sc->devinfo.chip_id >> 0) & 0xf));
8250 val = (REG_RD(sc, 0x2874) & 0x55);
8251 if ((sc->devinfo.chip_id & 0x1) || (CHIP_IS_E1H(sc) && (val == 0x55))) {
8252 sc->flags |= BNX2X_ONE_PORT_FLAG;
8253 PMD_DRV_LOG(DEBUG, "single port device");
8256 /* set the doorbell size */
8257 sc->doorbell_size = (1 << BNX2X_DB_SHIFT);
8259 /* determine whether the device is in 2 port or 4 port mode */
8260 sc->devinfo.chip_port_mode = CHIP_PORT_MODE_NONE; /* E1h */
8261 if (CHIP_IS_E2E3(sc)) {
8263 * Read port4mode_en_ovwr[0]:
8264 * If 1, four port mode is in port4mode_en_ovwr[1].
8265 * If 0, four port mode is in port4mode_en[0].
8267 val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);
8269 val = ((val >> 1) & 1);
8271 val = REG_RD(sc, MISC_REG_PORT4MODE_EN);
8274 sc->devinfo.chip_port_mode =
8275 (val) ? CHIP_4_PORT_MODE : CHIP_2_PORT_MODE;
8277 PMD_DRV_LOG(DEBUG, "Port mode = %s", (val) ? "4" : "2");
8280 /* get the function and path info for the device */
8281 bnx2x_get_function_num(sc);
8283 /* get the shared memory base address */
8284 sc->devinfo.shmem_base =
8285 sc->link_params.shmem_base = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
8286 sc->devinfo.shmem2_base =
8287 REG_RD(sc, (SC_PATH(sc) ? MISC_REG_GENERIC_CR_1 :
8288 MISC_REG_GENERIC_CR_0));
8290 if (!sc->devinfo.shmem_base) {
8291 /* this should ONLY prevent upcoming shmem reads */
8292 PMD_DRV_LOG(INFO, "MCP not active");
8293 sc->flags |= BNX2X_NO_MCP_FLAG;
8297 /* make sure the shared memory contents are valid */
8298 val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
8299 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) !=
8300 (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) {
8301 PMD_DRV_LOG(NOTICE, "Invalid SHMEM validity signature: 0x%08x",
8306 /* get the bootcode version */
8307 sc->devinfo.bc_ver = SHMEM_RD(sc, dev_info.bc_rev);
8308 snprintf(sc->devinfo.bc_ver_str,
8309 sizeof(sc->devinfo.bc_ver_str),
8311 ((sc->devinfo.bc_ver >> 24) & 0xff),
8312 ((sc->devinfo.bc_ver >> 16) & 0xff),
8313 ((sc->devinfo.bc_ver >> 8) & 0xff));
8314 PMD_DRV_LOG(INFO, "Bootcode version: %s", sc->devinfo.bc_ver_str);
8316 /* get the bootcode shmem address */
8317 sc->devinfo.mf_cfg_base = bnx2x_get_shmem_mf_cfg_base(sc);
8319 /* clean indirect addresses as they're not used */
8320 pci_write_long(sc, PCICFG_GRC_ADDRESS, 0);
8322 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F0, 0);
8323 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F0, 0);
8324 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F0, 0);
8325 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F0, 0);
8326 if (CHIP_IS_E1x(sc)) {
8327 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F1, 0);
8328 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F1, 0);
8329 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F1, 0);
8330 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F1, 0);
8334 * Enable internal target-read (in case we are probed after PF
8335 * FLR). Must be done prior to any BAR read access. Only for
8338 if (!CHIP_IS_E1x(sc)) {
8339 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ,
8344 /* get the nvram size */
8345 val = REG_RD(sc, MCP_REG_MCPR_NVM_CFG4);
8346 sc->devinfo.flash_size =
8347 (NVRAM_1MB_SIZE << (val & MCPR_NVM_CFG4_FLASH_SIZE));
8349 bnx2x_set_power_state(sc, PCI_PM_D0);
8350 /* get various configuration parameters from shmem */
8351 bnx2x_get_shmem_info(sc);
8353 /* initialize IGU parameters */
8354 if (CHIP_IS_E1x(sc)) {
8355 sc->devinfo.int_block = INT_BLOCK_HC;
8356 sc->igu_dsb_id = DEF_SB_IGU_ID;
8357 sc->igu_base_sb = 0;
8359 sc->devinfo.int_block = INT_BLOCK_IGU;
8361 /* do not allow device reset during IGU info preocessing */
8362 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8364 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
8366 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8369 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
8370 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION, val);
8371 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x7f);
8373 while (tout && REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8378 if (REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8380 "FORCING IGU Normal Mode failed!!!");
8381 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8386 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8387 PMD_DRV_LOG(DEBUG, "IGU Backward Compatible Mode");
8388 sc->devinfo.int_block |= INT_BLOCK_MODE_BW_COMP;
8390 PMD_DRV_LOG(DEBUG, "IGU Normal Mode");
8393 rc = bnx2x_get_igu_cam_info(sc);
8395 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8403 * Get base FW non-default (fast path) status block ID. This value is
8404 * used to initialize the fw_sb_id saved on the fp/queue structure to
8405 * determine the id used by the FW.
8407 if (CHIP_IS_E1x(sc)) {
8409 ((SC_PORT(sc) * FP_SB_MAX_E1x) + SC_L_ID(sc));
8412 * 57712+ - We currently use one FW SB per IGU SB (Rx and Tx of
8413 * the same queue are indicated on the same IGU SB). So we prefer
8414 * FW and IGU SBs to be the same value.
8416 sc->base_fw_ndsb = sc->igu_base_sb;
8419 elink_phy_probe(&sc->link_params);
8425 bnx2x_link_settings_supported(struct bnx2x_softc *sc, uint32_t switch_cfg)
8427 uint32_t cfg_size = 0;
8429 uint8_t port = SC_PORT(sc);
8431 /* aggregation of supported attributes of all external phys */
8432 sc->port.supported[0] = 0;
8433 sc->port.supported[1] = 0;
8435 switch (sc->link_params.num_phys) {
8437 sc->port.supported[0] =
8438 sc->link_params.phy[ELINK_INT_PHY].supported;
8442 sc->port.supported[0] =
8443 sc->link_params.phy[ELINK_EXT_PHY1].supported;
8447 if (sc->link_params.multi_phy_config &
8448 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
8449 sc->port.supported[1] =
8450 sc->link_params.phy[ELINK_EXT_PHY1].supported;
8451 sc->port.supported[0] =
8452 sc->link_params.phy[ELINK_EXT_PHY2].supported;
8454 sc->port.supported[0] =
8455 sc->link_params.phy[ELINK_EXT_PHY1].supported;
8456 sc->port.supported[1] =
8457 sc->link_params.phy[ELINK_EXT_PHY2].supported;
8463 if (!(sc->port.supported[0] || sc->port.supported[1])) {
8465 "Invalid phy config in NVRAM (PHY1=0x%08x PHY2=0x%08x)",
8467 dev_info.port_hw_config
8468 [port].external_phy_config),
8470 dev_info.port_hw_config
8471 [port].external_phy_config2));
8476 sc->port.phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR);
8478 switch (switch_cfg) {
8479 case ELINK_SWITCH_CFG_1G:
8482 NIG_REG_SERDES0_CTRL_PHY_ADDR + port * 0x10);
8484 case ELINK_SWITCH_CFG_10G:
8487 NIG_REG_XGXS0_CTRL_PHY_ADDR + port * 0x18);
8491 "Invalid switch config in"
8492 "link_config=0x%08x",
8493 sc->port.link_config[0]);
8498 PMD_DRV_LOG(INFO, "PHY addr 0x%08x", sc->port.phy_addr);
8500 /* mask what we support according to speed_cap_mask per configuration */
8501 for (idx = 0; idx < cfg_size; idx++) {
8502 if (!(sc->link_params.speed_cap_mask[idx] &
8503 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) {
8504 sc->port.supported[idx] &=
8505 ~ELINK_SUPPORTED_10baseT_Half;
8508 if (!(sc->link_params.speed_cap_mask[idx] &
8509 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) {
8510 sc->port.supported[idx] &=
8511 ~ELINK_SUPPORTED_10baseT_Full;
8514 if (!(sc->link_params.speed_cap_mask[idx] &
8515 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) {
8516 sc->port.supported[idx] &=
8517 ~ELINK_SUPPORTED_100baseT_Half;
8520 if (!(sc->link_params.speed_cap_mask[idx] &
8521 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) {
8522 sc->port.supported[idx] &=
8523 ~ELINK_SUPPORTED_100baseT_Full;
8526 if (!(sc->link_params.speed_cap_mask[idx] &
8527 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) {
8528 sc->port.supported[idx] &=
8529 ~ELINK_SUPPORTED_1000baseT_Full;
8532 if (!(sc->link_params.speed_cap_mask[idx] &
8533 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) {
8534 sc->port.supported[idx] &=
8535 ~ELINK_SUPPORTED_2500baseX_Full;
8538 if (!(sc->link_params.speed_cap_mask[idx] &
8539 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8540 sc->port.supported[idx] &=
8541 ~ELINK_SUPPORTED_10000baseT_Full;
8544 if (!(sc->link_params.speed_cap_mask[idx] &
8545 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) {
8546 sc->port.supported[idx] &=
8547 ~ELINK_SUPPORTED_20000baseKR2_Full;
8551 PMD_DRV_LOG(INFO, "PHY supported 0=0x%08x 1=0x%08x",
8552 sc->port.supported[0], sc->port.supported[1]);
8555 static void bnx2x_link_settings_requested(struct bnx2x_softc *sc)
8557 uint32_t link_config;
8559 uint32_t cfg_size = 0;
8561 sc->port.advertising[0] = 0;
8562 sc->port.advertising[1] = 0;
8564 switch (sc->link_params.num_phys) {
8574 for (idx = 0; idx < cfg_size; idx++) {
8575 sc->link_params.req_duplex[idx] = DUPLEX_FULL;
8576 link_config = sc->port.link_config[idx];
8578 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
8579 case PORT_FEATURE_LINK_SPEED_AUTO:
8580 if (sc->port.supported[idx] & ELINK_SUPPORTED_Autoneg) {
8581 sc->link_params.req_line_speed[idx] =
8582 ELINK_SPEED_AUTO_NEG;
8583 sc->port.advertising[idx] |=
8584 sc->port.supported[idx];
8585 if (sc->link_params.phy[ELINK_EXT_PHY1].type ==
8586 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833)
8587 sc->port.advertising[idx] |=
8588 (ELINK_SUPPORTED_100baseT_Half |
8589 ELINK_SUPPORTED_100baseT_Full);
8591 /* force 10G, no AN */
8592 sc->link_params.req_line_speed[idx] =
8594 sc->port.advertising[idx] |=
8595 (ADVERTISED_10000baseT_Full |
8601 case PORT_FEATURE_LINK_SPEED_10M_FULL:
8603 port.supported[idx] & ELINK_SUPPORTED_10baseT_Full)
8605 sc->link_params.req_line_speed[idx] =
8607 sc->port.advertising[idx] |=
8608 (ADVERTISED_10baseT_Full | ADVERTISED_TP);
8611 "Invalid NVRAM config link_config=0x%08x "
8612 "speed_cap_mask=0x%08x",
8615 link_params.speed_cap_mask[idx]);
8620 case PORT_FEATURE_LINK_SPEED_10M_HALF:
8622 port.supported[idx] & ELINK_SUPPORTED_10baseT_Half)
8624 sc->link_params.req_line_speed[idx] =
8626 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8627 sc->port.advertising[idx] |=
8628 (ADVERTISED_10baseT_Half | ADVERTISED_TP);
8631 "Invalid NVRAM config link_config=0x%08x "
8632 "speed_cap_mask=0x%08x",
8635 link_params.speed_cap_mask[idx]);
8640 case PORT_FEATURE_LINK_SPEED_100M_FULL:
8642 port.supported[idx] & ELINK_SUPPORTED_100baseT_Full)
8644 sc->link_params.req_line_speed[idx] =
8646 sc->port.advertising[idx] |=
8647 (ADVERTISED_100baseT_Full | ADVERTISED_TP);
8650 "Invalid NVRAM config link_config=0x%08x "
8651 "speed_cap_mask=0x%08x",
8654 link_params.speed_cap_mask[idx]);
8659 case PORT_FEATURE_LINK_SPEED_100M_HALF:
8661 port.supported[idx] & ELINK_SUPPORTED_100baseT_Half)
8663 sc->link_params.req_line_speed[idx] =
8665 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8666 sc->port.advertising[idx] |=
8667 (ADVERTISED_100baseT_Half | ADVERTISED_TP);
8670 "Invalid NVRAM config link_config=0x%08x "
8671 "speed_cap_mask=0x%08x",
8674 link_params.speed_cap_mask[idx]);
8679 case PORT_FEATURE_LINK_SPEED_1G:
8680 if (sc->port.supported[idx] &
8681 ELINK_SUPPORTED_1000baseT_Full) {
8682 sc->link_params.req_line_speed[idx] =
8684 sc->port.advertising[idx] |=
8685 (ADVERTISED_1000baseT_Full | ADVERTISED_TP);
8688 "Invalid NVRAM config link_config=0x%08x "
8689 "speed_cap_mask=0x%08x",
8692 link_params.speed_cap_mask[idx]);
8697 case PORT_FEATURE_LINK_SPEED_2_5G:
8698 if (sc->port.supported[idx] &
8699 ELINK_SUPPORTED_2500baseX_Full) {
8700 sc->link_params.req_line_speed[idx] =
8702 sc->port.advertising[idx] |=
8703 (ADVERTISED_2500baseX_Full | ADVERTISED_TP);
8706 "Invalid NVRAM config link_config=0x%08x "
8707 "speed_cap_mask=0x%08x",
8710 link_params.speed_cap_mask[idx]);
8715 case PORT_FEATURE_LINK_SPEED_10G_CX4:
8716 if (sc->port.supported[idx] &
8717 ELINK_SUPPORTED_10000baseT_Full) {
8718 sc->link_params.req_line_speed[idx] =
8720 sc->port.advertising[idx] |=
8721 (ADVERTISED_10000baseT_Full |
8725 "Invalid NVRAM config link_config=0x%08x "
8726 "speed_cap_mask=0x%08x",
8729 link_params.speed_cap_mask[idx]);
8734 case PORT_FEATURE_LINK_SPEED_20G:
8735 sc->link_params.req_line_speed[idx] = ELINK_SPEED_20000;
8740 "Invalid NVRAM config link_config=0x%08x "
8741 "speed_cap_mask=0x%08x", link_config,
8742 sc->link_params.speed_cap_mask[idx]);
8743 sc->link_params.req_line_speed[idx] =
8744 ELINK_SPEED_AUTO_NEG;
8745 sc->port.advertising[idx] = sc->port.supported[idx];
8749 sc->link_params.req_flow_ctrl[idx] =
8750 (link_config & PORT_FEATURE_FLOW_CONTROL_MASK);
8752 if (sc->link_params.req_flow_ctrl[idx] == ELINK_FLOW_CTRL_AUTO) {
8755 port.supported[idx] & ELINK_SUPPORTED_Autoneg)) {
8756 sc->link_params.req_flow_ctrl[idx] =
8757 ELINK_FLOW_CTRL_NONE;
8759 bnx2x_set_requested_fc(sc);
8765 static void bnx2x_get_phy_info(struct bnx2x_softc *sc)
8767 uint8_t port = SC_PORT(sc);
8770 PMD_INIT_FUNC_TRACE();
8772 /* shmem data already read in bnx2x_get_shmem_info() */
8774 bnx2x_link_settings_supported(sc, sc->link_params.switch_cfg);
8775 bnx2x_link_settings_requested(sc);
8777 /* configure link feature according to nvram value */
8779 (((SHMEM_RD(sc, dev_info.port_feature_config[port].eee_power_mode))
8780 & PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
8781 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
8782 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
8783 sc->link_params.eee_mode = (ELINK_EEE_MODE_ADV_LPI |
8784 ELINK_EEE_MODE_ENABLE_LPI |
8785 ELINK_EEE_MODE_OUTPUT_TIME);
8787 sc->link_params.eee_mode = 0;
8790 /* get the media type */
8791 bnx2x_media_detect(sc);
8794 static void bnx2x_set_modes_bitmap(struct bnx2x_softc *sc)
8796 uint32_t flags = MODE_ASIC | MODE_PORT2;
8798 if (CHIP_IS_E2(sc)) {
8800 } else if (CHIP_IS_E3(sc)) {
8802 if (CHIP_REV(sc) == CHIP_REV_Ax) {
8803 flags |= MODE_E3_A0;
8804 } else { /*if (CHIP_REV(sc) == CHIP_REV_Bx) */
8806 flags |= MODE_E3_B0 | MODE_COS3;
8812 switch (sc->devinfo.mf_info.mf_mode) {
8813 case MULTI_FUNCTION_SD:
8814 flags |= MODE_MF_SD;
8816 case MULTI_FUNCTION_SI:
8817 flags |= MODE_MF_SI;
8819 case MULTI_FUNCTION_AFEX:
8820 flags |= MODE_MF_AFEX;
8827 #if defined(__LITTLE_ENDIAN)
8828 flags |= MODE_LITTLE_ENDIAN;
8829 #else /* __BIG_ENDIAN */
8830 flags |= MODE_BIG_ENDIAN;
8833 INIT_MODE_FLAGS(sc) = flags;
8836 int bnx2x_alloc_hsi_mem(struct bnx2x_softc *sc)
8838 struct bnx2x_fastpath *fp;
8843 /************************/
8844 /* DEFAULT STATUS BLOCK */
8845 /************************/
8847 if (bnx2x_dma_alloc(sc, sizeof(struct host_sp_status_block),
8848 &sc->def_sb_dma, "def_sb",
8849 RTE_CACHE_LINE_SIZE) != 0) {
8854 (struct host_sp_status_block *)sc->def_sb_dma.vaddr;
8859 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8860 &sc->eq_dma, "ev_queue",
8861 RTE_CACHE_LINE_SIZE) != 0) {
8866 sc->eq = (union event_ring_elem *)sc->eq_dma.vaddr;
8872 if (bnx2x_dma_alloc(sc, sizeof(struct bnx2x_slowpath),
8874 RTE_CACHE_LINE_SIZE) != 0) {
8880 sc->sp = (struct bnx2x_slowpath *)sc->sp_dma.vaddr;
8882 /*******************/
8883 /* SLOW PATH QUEUE */
8884 /*******************/
8886 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8887 &sc->spq_dma, "sp_queue",
8888 RTE_CACHE_LINE_SIZE) != 0) {
8895 sc->spq = (struct eth_spe *)sc->spq_dma.vaddr;
8897 /***************************/
8898 /* FW DECOMPRESSION BUFFER */
8899 /***************************/
8901 if (bnx2x_dma_alloc(sc, FW_BUF_SIZE, &sc->gz_buf_dma,
8902 "fw_dec_buf", RTE_CACHE_LINE_SIZE) != 0) {
8910 sc->gz_buf = (void *)sc->gz_buf_dma.vaddr;
8917 /* allocate DMA memory for each fastpath structure */
8918 for (i = 0; i < sc->num_queues; i++) {
8923 /*******************/
8924 /* FP STATUS BLOCK */
8925 /*******************/
8927 snprintf(buf, sizeof(buf), "fp_%d_sb", i);
8928 if (bnx2x_dma_alloc(sc, sizeof(union bnx2x_host_hc_status_block),
8929 &fp->sb_dma, buf, RTE_CACHE_LINE_SIZE) != 0) {
8930 PMD_DRV_LOG(NOTICE, "Failed to alloc %s", buf);
8933 if (CHIP_IS_E2E3(sc)) {
8934 fp->status_block.e2_sb =
8935 (struct host_hc_status_block_e2 *)
8938 fp->status_block.e1x_sb =
8939 (struct host_hc_status_block_e1x *)
8948 void bnx2x_free_hsi_mem(struct bnx2x_softc *sc)
8950 struct bnx2x_fastpath *fp;
8953 for (i = 0; i < sc->num_queues; i++) {
8956 /*******************/
8957 /* FP STATUS BLOCK */
8958 /*******************/
8960 memset(&fp->status_block, 0, sizeof(fp->status_block));
8963 /***************************/
8964 /* FW DECOMPRESSION BUFFER */
8965 /***************************/
8969 /*******************/
8970 /* SLOW PATH QUEUE */
8971 /*******************/
8987 /************************/
8988 /* DEFAULT STATUS BLOCK */
8989 /************************/
8996 * Previous driver DMAE transaction may have occurred when pre-boot stage
8997 * ended and boot began. This would invalidate the addresses of the
8998 * transaction, resulting in was-error bit set in the PCI causing all
8999 * hw-to-host PCIe transactions to timeout. If this happened we want to clear
9000 * the interrupt which detected this from the pglueb and the was-done bit
9002 static void bnx2x_prev_interrupted_dmae(struct bnx2x_softc *sc)
9006 if (!CHIP_IS_E1x(sc)) {
9007 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS);
9008 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
9009 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
9015 static int bnx2x_prev_mcp_done(struct bnx2x_softc *sc)
9017 uint32_t rc = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE,
9018 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
9020 PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
9027 static struct bnx2x_prev_list_node *bnx2x_prev_path_get_entry(struct bnx2x_softc *sc)
9029 struct bnx2x_prev_list_node *tmp;
9031 LIST_FOREACH(tmp, &bnx2x_prev_list, node) {
9032 if ((sc->pcie_bus == tmp->bus) &&
9033 (sc->pcie_device == tmp->slot) &&
9034 (SC_PATH(sc) == tmp->path)) {
9042 static uint8_t bnx2x_prev_is_path_marked(struct bnx2x_softc *sc)
9044 struct bnx2x_prev_list_node *tmp;
9047 rte_spinlock_lock(&bnx2x_prev_mtx);
9049 tmp = bnx2x_prev_path_get_entry(sc);
9053 "Path %d/%d/%d was marked by AER",
9054 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9058 "Path %d/%d/%d was already cleaned from previous drivers",
9059 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9063 rte_spinlock_unlock(&bnx2x_prev_mtx);
9068 static int bnx2x_prev_mark_path(struct bnx2x_softc *sc, uint8_t after_undi)
9070 struct bnx2x_prev_list_node *tmp;
9072 rte_spinlock_lock(&bnx2x_prev_mtx);
9074 /* Check whether the entry for this path already exists */
9075 tmp = bnx2x_prev_path_get_entry(sc);
9079 "Re-marking AER in path %d/%d/%d",
9080 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9083 "Removing AER indication from path %d/%d/%d",
9084 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9088 rte_spinlock_unlock(&bnx2x_prev_mtx);
9092 rte_spinlock_unlock(&bnx2x_prev_mtx);
9094 /* Create an entry for this path and add it */
9095 tmp = rte_malloc("", sizeof(struct bnx2x_prev_list_node),
9096 RTE_CACHE_LINE_SIZE);
9098 PMD_DRV_LOG(NOTICE, "Failed to allocate 'bnx2x_prev_list_node'");
9102 tmp->bus = sc->pcie_bus;
9103 tmp->slot = sc->pcie_device;
9104 tmp->path = SC_PATH(sc);
9106 tmp->undi = after_undi ? (1 << SC_PORT(sc)) : 0;
9108 rte_spinlock_lock(&bnx2x_prev_mtx);
9110 LIST_INSERT_HEAD(&bnx2x_prev_list, tmp, node);
9112 rte_spinlock_unlock(&bnx2x_prev_mtx);
9117 static int bnx2x_do_flr(struct bnx2x_softc *sc)
9121 /* only E2 and onwards support FLR */
9122 if (CHIP_IS_E1x(sc)) {
9123 PMD_DRV_LOG(WARNING, "FLR not supported in E1H");
9127 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9128 if (sc->devinfo.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9129 PMD_DRV_LOG(WARNING,
9130 "FLR not supported by BC_VER: 0x%08x",
9131 sc->devinfo.bc_ver);
9135 /* Wait for Transaction Pending bit clean */
9136 for (i = 0; i < 4; i++) {
9138 DELAY(((1 << (i - 1)) * 100) * 1000);
9141 if (!bnx2x_is_pcie_pending(sc)) {
9146 PMD_DRV_LOG(NOTICE, "PCIE transaction is not cleared, "
9147 "proceeding with reset anyway");
9150 bnx2x_fw_command(sc, DRV_MSG_CODE_INITIATE_FLR, 0);
9155 struct bnx2x_mac_vals {
9163 uint32_t bmac_val[2];
9167 bnx2x_prev_unload_close_mac(struct bnx2x_softc *sc, struct bnx2x_mac_vals *vals)
9169 uint32_t val, base_addr, offset, mask, reset_reg;
9170 uint8_t mac_stopped = FALSE;
9171 uint8_t port = SC_PORT(sc);
9172 uint32_t wb_data[2];
9174 /* reset addresses as they also mark which values were changed */
9175 vals->bmac_addr = 0;
9176 vals->umac_addr = 0;
9177 vals->xmac_addr = 0;
9178 vals->emac_addr = 0;
9180 reset_reg = REG_RD(sc, MISC_REG_RESET_REG_2);
9182 if (!CHIP_IS_E3(sc)) {
9183 val = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9184 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9185 if ((mask & reset_reg) && val) {
9186 base_addr = SC_PORT(sc) ? NIG_REG_INGRESS_BMAC1_MEM
9187 : NIG_REG_INGRESS_BMAC0_MEM;
9188 offset = CHIP_IS_E2(sc) ? BIGMAC2_REGISTER_BMAC_CONTROL
9189 : BIGMAC_REGISTER_BMAC_CONTROL;
9192 * use rd/wr since we cannot use dmae. This is safe
9193 * since MCP won't access the bus due to the request
9194 * to unload, and no function on the path can be
9195 * loaded at this time.
9197 wb_data[0] = REG_RD(sc, base_addr + offset);
9198 wb_data[1] = REG_RD(sc, base_addr + offset + 0x4);
9199 vals->bmac_addr = base_addr + offset;
9200 vals->bmac_val[0] = wb_data[0];
9201 vals->bmac_val[1] = wb_data[1];
9202 wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE;
9203 REG_WR(sc, vals->bmac_addr, wb_data[0]);
9204 REG_WR(sc, vals->bmac_addr + 0x4, wb_data[1]);
9207 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + SC_PORT(sc) * 4;
9208 vals->emac_val = REG_RD(sc, vals->emac_addr);
9209 REG_WR(sc, vals->emac_addr, 0);
9212 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9213 base_addr = SC_PORT(sc) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9214 val = REG_RD(sc, base_addr + XMAC_REG_PFC_CTRL_HI);
9215 REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9217 REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9219 vals->xmac_addr = base_addr + XMAC_REG_CTRL;
9220 vals->xmac_val = REG_RD(sc, vals->xmac_addr);
9221 REG_WR(sc, vals->xmac_addr, 0);
9225 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9226 if (mask & reset_reg) {
9227 base_addr = SC_PORT(sc) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9228 vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
9229 vals->umac_val = REG_RD(sc, vals->umac_addr);
9230 REG_WR(sc, vals->umac_addr, 0);
9240 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9241 #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
9242 #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
9243 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
9246 bnx2x_prev_unload_undi_inc(struct bnx2x_softc *sc, uint8_t port, uint8_t inc)
9249 uint32_t tmp_reg = REG_RD(sc, BNX2X_PREV_UNDI_PROD_ADDR(port));
9251 rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9252 bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9254 tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9255 REG_WR(sc, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9258 static int bnx2x_prev_unload_common(struct bnx2x_softc *sc)
9260 uint32_t reset_reg, tmp_reg = 0, rc;
9261 uint8_t prev_undi = FALSE;
9262 struct bnx2x_mac_vals mac_vals;
9263 uint32_t timer_count = 1000;
9267 * It is possible a previous function received 'common' answer,
9268 * but hasn't loaded yet, therefore creating a scenario of
9269 * multiple functions receiving 'common' on the same path.
9271 memset(&mac_vals, 0, sizeof(mac_vals));
9273 if (bnx2x_prev_is_path_marked(sc)) {
9274 return bnx2x_prev_mcp_done(sc);
9277 reset_reg = REG_RD(sc, MISC_REG_RESET_REG_1);
9279 /* Reset should be performed after BRB is emptied */
9280 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
9281 /* Close the MAC Rx to prevent BRB from filling up */
9282 bnx2x_prev_unload_close_mac(sc, &mac_vals);
9284 /* close LLH filters towards the BRB */
9285 elink_set_rx_filter(&sc->link_params, 0);
9288 * Check if the UNDI driver was previously loaded.
9289 * UNDI driver initializes CID offset for normal bell to 0x7
9291 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
9292 tmp_reg = REG_RD(sc, DORQ_REG_NORM_CID_OFST);
9293 if (tmp_reg == 0x7) {
9294 PMD_DRV_LOG(DEBUG, "UNDI previously loaded");
9296 /* clear the UNDI indication */
9297 REG_WR(sc, DORQ_REG_NORM_CID_OFST, 0);
9298 /* clear possible idle check errors */
9299 REG_RD(sc, NIG_REG_NIG_INT_STS_CLR_0);
9303 /* wait until BRB is empty */
9304 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9305 while (timer_count) {
9308 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9313 PMD_DRV_LOG(DEBUG, "BRB still has 0x%08x", tmp_reg);
9315 /* reset timer as long as BRB actually gets emptied */
9316 if (prev_brb > tmp_reg) {
9322 /* If UNDI resides in memory, manually increment it */
9324 bnx2x_prev_unload_undi_inc(sc, SC_PORT(sc), 1);
9331 PMD_DRV_LOG(NOTICE, "Failed to empty BRB");
9335 /* No packets are in the pipeline, path is ready for reset */
9336 bnx2x_reset_common(sc);
9338 if (mac_vals.xmac_addr) {
9339 REG_WR(sc, mac_vals.xmac_addr, mac_vals.xmac_val);
9341 if (mac_vals.umac_addr) {
9342 REG_WR(sc, mac_vals.umac_addr, mac_vals.umac_val);
9344 if (mac_vals.emac_addr) {
9345 REG_WR(sc, mac_vals.emac_addr, mac_vals.emac_val);
9347 if (mac_vals.bmac_addr) {
9348 REG_WR(sc, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
9349 REG_WR(sc, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
9352 rc = bnx2x_prev_mark_path(sc, prev_undi);
9354 bnx2x_prev_mcp_done(sc);
9358 return bnx2x_prev_mcp_done(sc);
9361 static int bnx2x_prev_unload_uncommon(struct bnx2x_softc *sc)
9365 /* Test if previous unload process was already finished for this path */
9366 if (bnx2x_prev_is_path_marked(sc)) {
9367 return bnx2x_prev_mcp_done(sc);
9371 * If function has FLR capabilities, and existing FW version matches
9372 * the one required, then FLR will be sufficient to clean any residue
9373 * left by previous driver
9375 rc = bnx2x_nic_load_analyze_req(sc, FW_MSG_CODE_DRV_LOAD_FUNCTION);
9377 /* fw version is good */
9378 rc = bnx2x_do_flr(sc);
9382 /* FLR was performed */
9386 PMD_DRV_LOG(INFO, "Could not FLR");
9388 /* Close the MCP request, return failure */
9389 rc = bnx2x_prev_mcp_done(sc);
9391 rc = BNX2X_PREV_WAIT_NEEDED;
9397 static int bnx2x_prev_unload(struct bnx2x_softc *sc)
9399 int time_counter = 10;
9400 uint32_t fw, hw_lock_reg, hw_lock_val;
9404 * Clear HW from errors which may have resulted from an interrupted
9407 bnx2x_prev_interrupted_dmae(sc);
9409 /* Release previously held locks */
9410 if (SC_FUNC(sc) <= 5)
9411 hw_lock_reg = (MISC_REG_DRIVER_CONTROL_1 + SC_FUNC(sc) * 8);
9414 (MISC_REG_DRIVER_CONTROL_7 + (SC_FUNC(sc) - 6) * 8);
9416 hw_lock_val = (REG_RD(sc, hw_lock_reg));
9418 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
9419 REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
9420 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << SC_PORT(sc)));
9422 REG_WR(sc, hw_lock_reg, 0xffffffff);
9425 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(sc, MCP_REG_MCPR_ACCESS_LOCK)) {
9426 REG_WR(sc, MCP_REG_MCPR_ACCESS_LOCK, 0);
9430 /* Lock MCP using an unload request */
9431 fw = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
9433 PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
9438 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
9439 rc = bnx2x_prev_unload_common(sc);
9443 /* non-common reply from MCP might require looping */
9444 rc = bnx2x_prev_unload_uncommon(sc);
9445 if (rc != BNX2X_PREV_WAIT_NEEDED) {
9450 } while (--time_counter);
9452 if (!time_counter || rc) {
9453 PMD_DRV_LOG(NOTICE, "Failed to unload previous driver!");
9461 bnx2x_dcbx_set_state(struct bnx2x_softc *sc, uint8_t dcb_on, uint32_t dcbx_enabled)
9463 if (!CHIP_IS_E1x(sc)) {
9464 sc->dcb_state = dcb_on;
9465 sc->dcbx_enabled = dcbx_enabled;
9467 sc->dcb_state = FALSE;
9468 sc->dcbx_enabled = BNX2X_DCBX_ENABLED_INVALID;
9471 "DCB state [%s:%s]",
9472 dcb_on ? "ON" : "OFF",
9473 (dcbx_enabled == BNX2X_DCBX_ENABLED_OFF) ? "user-mode" :
9475 BNX2X_DCBX_ENABLED_ON_NEG_OFF) ? "on-chip static"
9477 BNX2X_DCBX_ENABLED_ON_NEG_ON) ?
9478 "on-chip with negotiation" : "invalid");
9481 static int bnx2x_set_qm_cid_count(struct bnx2x_softc *sc)
9483 int cid_count = BNX2X_L2_MAX_CID(sc);
9485 if (CNIC_SUPPORT(sc)) {
9486 cid_count += CNIC_CID_MAX;
9489 return roundup(cid_count, QM_CID_ROUND);
9492 static void bnx2x_init_multi_cos(struct bnx2x_softc *sc)
9496 uint32_t pri_map = 0;
9498 for (pri = 0; pri < BNX2X_MAX_PRIORITY; pri++) {
9499 cos = ((pri_map & (0xf << (pri * 4))) >> (pri * 4));
9500 if (cos < sc->max_cos) {
9501 sc->prio_to_cos[pri] = cos;
9503 PMD_DRV_LOG(WARNING,
9504 "Invalid COS %d for priority %d "
9505 "(max COS is %d), setting to 0", cos, pri,
9507 sc->prio_to_cos[pri] = 0;
9512 static int bnx2x_pci_get_caps(struct bnx2x_softc *sc)
9519 struct bnx2x_pci_cap *cap;
9521 cap = sc->pci_caps = rte_zmalloc("caps", sizeof(struct bnx2x_pci_cap),
9522 RTE_CACHE_LINE_SIZE);
9524 PMD_DRV_LOG(NOTICE, "Failed to allocate memory");
9529 pci_read(sc, PCI_STATUS, &status, 2);
9530 if (!(status & PCI_STATUS_CAP_LIST)) {
9532 pci_read(sc, PCIR_STATUS, &status, 2);
9533 if (!(status & PCIM_STATUS_CAPPRESENT)) {
9535 PMD_DRV_LOG(NOTICE, "PCIe capability reading failed");
9540 pci_read(sc, PCI_CAPABILITY_LIST, &pci_cap.next, 1);
9542 pci_read(sc, PCIR_CAP_PTR, &pci_cap.next, 1);
9544 while (pci_cap.next) {
9545 cap->addr = pci_cap.next & ~3;
9546 pci_read(sc, pci_cap.next & ~3, &pci_cap, 2);
9547 if (pci_cap.id == 0xff)
9549 cap->id = pci_cap.id;
9550 cap->type = BNX2X_PCI_CAP;
9551 cap->next = rte_zmalloc("pci_cap",
9552 sizeof(struct bnx2x_pci_cap),
9553 RTE_CACHE_LINE_SIZE);
9555 PMD_DRV_LOG(NOTICE, "Failed to allocate memory");
9564 static void bnx2x_init_rte(struct bnx2x_softc *sc)
9567 sc->max_tx_queues = BNX2X_VF_MAX_QUEUES_PER_VF;
9568 sc->max_rx_queues = BNX2X_VF_MAX_QUEUES_PER_VF;
9570 sc->max_tx_queues = 128;
9571 sc->max_rx_queues = 128;
9575 #define FW_HEADER_LEN 104
9576 #define FW_NAME_57711 "/lib/firmware/bnx2x/bnx2x-e1h-7.2.51.0.fw"
9577 #define FW_NAME_57810 "/lib/firmware/bnx2x/bnx2x-e2-7.2.51.0.fw"
9579 void bnx2x_load_firmware(struct bnx2x_softc *sc)
9585 fwname = sc->devinfo.device_id == BNX2X_DEV_ID_57711
9586 ? FW_NAME_57711 : FW_NAME_57810;
9587 f = open(fwname, O_RDONLY);
9589 PMD_DRV_LOG(NOTICE, "Can't open firmware file");
9593 if (fstat(f, &st) < 0) {
9594 PMD_DRV_LOG(NOTICE, "Can't stat firmware file");
9599 sc->firmware = rte_zmalloc("bnx2x_fw", st.st_size, RTE_CACHE_LINE_SIZE);
9600 if (!sc->firmware) {
9601 PMD_DRV_LOG(NOTICE, "Can't allocate memory for firmware");
9606 if (read(f, sc->firmware, st.st_size) != st.st_size) {
9607 PMD_DRV_LOG(NOTICE, "Can't read firmware data");
9613 sc->fw_len = st.st_size;
9614 if (sc->fw_len < FW_HEADER_LEN) {
9615 PMD_DRV_LOG(NOTICE, "Invalid fw size: %" PRIu64, sc->fw_len);
9618 PMD_DRV_LOG(DEBUG, "fw_len = %" PRIu64, sc->fw_len);
9622 bnx2x_data_to_init_ops(uint8_t * data, struct raw_op *dst, uint32_t len)
9624 uint32_t *src = (uint32_t *) data;
9627 for (i = 0, j = 0; i < len / 8; ++i, j += 2) {
9628 tmp = rte_be_to_cpu_32(src[j]);
9629 dst[i].op = (tmp >> 24) & 0xFF;
9630 dst[i].offset = tmp & 0xFFFFFF;
9631 dst[i].raw_data = rte_be_to_cpu_32(src[j + 1]);
9636 bnx2x_data_to_init_offsets(uint8_t * data, uint16_t * dst, uint32_t len)
9638 uint16_t *src = (uint16_t *) data;
9641 for (i = 0; i < len / 2; ++i)
9642 dst[i] = rte_be_to_cpu_16(src[i]);
9645 static void bnx2x_data_to_init_data(uint8_t * data, uint32_t * dst, uint32_t len)
9647 uint32_t *src = (uint32_t *) data;
9650 for (i = 0; i < len / 4; ++i)
9651 dst[i] = rte_be_to_cpu_32(src[i]);
9654 static void bnx2x_data_to_iro_array(uint8_t * data, struct iro *dst, uint32_t len)
9656 uint32_t *src = (uint32_t *) data;
9659 for (i = 0, j = 0; i < len / sizeof(struct iro); ++i, ++j) {
9660 dst[i].base = rte_be_to_cpu_32(src[j++]);
9661 tmp = rte_be_to_cpu_32(src[j]);
9662 dst[i].m1 = (tmp >> 16) & 0xFFFF;
9663 dst[i].m2 = tmp & 0xFFFF;
9665 tmp = rte_be_to_cpu_32(src[j]);
9666 dst[i].m3 = (tmp >> 16) & 0xFFFF;
9667 dst[i].size = tmp & 0xFFFF;
9672 * Device attach function.
9674 * Allocates device resources, performs secondary chip identification, and
9675 * initializes driver instance variables. This function is called from driver
9676 * load after a successful probe.
9679 * 0 = Success, >0 = Failure
9681 int bnx2x_attach(struct bnx2x_softc *sc)
9685 PMD_DRV_LOG(DEBUG, "Starting attach...");
9687 rc = bnx2x_pci_get_caps(sc);
9689 PMD_DRV_LOG(NOTICE, "PCIe caps reading was failed");
9693 sc->state = BNX2X_STATE_CLOSED;
9695 /* Init RTE stuff */
9698 pci_write_long(sc, PCICFG_GRC_ADDRESS, PCICFG_VENDOR_ID_OFFSET);
9700 sc->igu_base_addr = IS_VF(sc) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
9702 /* get PCI capabilites */
9703 bnx2x_probe_pci_caps(sc);
9705 if (sc->devinfo.pcie_msix_cap_reg != 0) {
9708 (sc->devinfo.pcie_msix_cap_reg + PCIR_MSIX_CTRL), &val,
9710 sc->igu_sb_cnt = (val & PCIM_MSIXCTRL_TABLE_SIZE);
9716 /* get device info and set params */
9717 if (bnx2x_get_device_info(sc) != 0) {
9718 PMD_DRV_LOG(NOTICE, "getting device info");
9722 /* get phy settings from shmem and 'and' against admin settings */
9723 bnx2x_get_phy_info(sc);
9725 /* Left mac of VF unfilled, PF should set it for VF */
9726 memset(sc->link_params.mac_addr, 0, ETHER_ADDR_LEN);
9731 /* set the default MTU (changed via ifconfig) */
9732 sc->mtu = ETHER_MTU;
9734 bnx2x_set_modes_bitmap(sc);
9736 /* need to reset chip if UNDI was active */
9737 if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
9740 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
9741 DRV_MSG_SEQ_NUMBER_MASK);
9742 bnx2x_prev_unload(sc);
9745 bnx2x_dcbx_set_state(sc, FALSE, BNX2X_DCBX_ENABLED_OFF);
9747 /* calculate qm_cid_count */
9748 sc->qm_cid_count = bnx2x_set_qm_cid_count(sc);
9751 bnx2x_init_multi_cos(sc);
9757 bnx2x_igu_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t segment,
9758 uint16_t index, uint8_t op, uint8_t update)
9760 uint32_t igu_addr = sc->igu_base_addr;
9761 igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
9762 bnx2x_igu_ack_sb_gen(sc, segment, index, op, update, igu_addr);
9766 bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t storm,
9767 uint16_t index, uint8_t op, uint8_t update)
9769 if (unlikely(sc->devinfo.int_block == INT_BLOCK_HC))
9770 bnx2x_hc_ack_sb(sc, igu_sb_id, storm, index, op, update);
9773 if (CHIP_INT_MODE_IS_BC(sc)) {
9775 } else if (igu_sb_id != sc->igu_dsb_id) {
9776 segment = IGU_SEG_ACCESS_DEF;
9777 } else if (storm == ATTENTION_ID) {
9778 segment = IGU_SEG_ACCESS_ATTN;
9780 segment = IGU_SEG_ACCESS_DEF;
9782 bnx2x_igu_ack_sb(sc, igu_sb_id, segment, index, op, update);
9787 bnx2x_igu_clear_sb_gen(struct bnx2x_softc *sc, uint8_t func, uint8_t idu_sb_id,
9790 uint32_t data, ctl, cnt = 100;
9791 uint32_t igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
9792 uint32_t igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
9793 uint32_t igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP +
9794 (idu_sb_id / 32) * 4;
9795 uint32_t sb_bit = 1 << (idu_sb_id % 32);
9796 uint32_t func_encode = func |
9797 (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
9798 uint32_t addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
9800 /* Not supported in BC mode */
9801 if (CHIP_INT_MODE_IS_BC(sc)) {
9805 data = ((IGU_USE_REGISTER_cstorm_type_0_sb_cleanup <<
9806 IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
9807 IGU_REGULAR_CLEANUP_SET | IGU_REGULAR_BCLEANUP);
9809 ctl = ((addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT) |
9810 (func_encode << IGU_CTRL_REG_FID_SHIFT) |
9811 (IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT));
9813 REG_WR(sc, igu_addr_data, data);
9817 PMD_DRV_LOG(DEBUG, "write 0x%08x to IGU(via GRC) addr 0x%x",
9819 REG_WR(sc, igu_addr_ctl, ctl);
9823 /* wait for clean up to finish */
9824 while (!(REG_RD(sc, igu_addr_ack) & sb_bit) && --cnt) {
9828 if (!(REG_RD(sc, igu_addr_ack) & sb_bit)) {
9830 "Unable to finish IGU cleanup: "
9831 "idu_sb_id %d offset %d bit %d (cnt %d)",
9832 idu_sb_id, idu_sb_id / 32, idu_sb_id % 32, cnt);
9836 static void bnx2x_igu_clear_sb(struct bnx2x_softc *sc, uint8_t idu_sb_id)
9838 bnx2x_igu_clear_sb_gen(sc, SC_FUNC(sc), idu_sb_id, TRUE /*PF*/);
9841 /*******************/
9842 /* ECORE CALLBACKS */
9843 /*******************/
9845 static void bnx2x_reset_common(struct bnx2x_softc *sc)
9847 uint32_t val = 0x1400;
9849 PMD_INIT_FUNC_TRACE();
9852 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR),
9855 if (CHIP_IS_E3(sc)) {
9856 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
9857 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
9860 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR), val);
9863 static void bnx2x_common_init_phy(struct bnx2x_softc *sc)
9865 uint32_t shmem_base[2];
9866 uint32_t shmem2_base[2];
9868 /* Avoid common init in case MFW supports LFA */
9869 if (SHMEM2_RD(sc, size) >
9870 (uint32_t) offsetof(struct shmem2_region,
9871 lfa_host_addr[SC_PORT(sc)])) {
9875 shmem_base[0] = sc->devinfo.shmem_base;
9876 shmem2_base[0] = sc->devinfo.shmem2_base;
9878 if (!CHIP_IS_E1x(sc)) {
9879 shmem_base[1] = SHMEM2_RD(sc, other_shmem_base_addr);
9880 shmem2_base[1] = SHMEM2_RD(sc, other_shmem2_base_addr);
9883 elink_common_init_phy(sc, shmem_base, shmem2_base,
9884 sc->devinfo.chip_id, 0);
9887 static void bnx2x_pf_disable(struct bnx2x_softc *sc)
9889 uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
9891 val &= ~IGU_PF_CONF_FUNC_EN;
9893 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
9894 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
9895 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 0);
9898 static void bnx2x_init_pxp(struct bnx2x_softc *sc)
9901 int r_order, w_order;
9903 devctl = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_CTL);
9905 w_order = ((devctl & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5);
9906 r_order = ((devctl & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12);
9908 ecore_init_pxp_arb(sc, r_order, w_order);
9911 static uint32_t bnx2x_get_pretend_reg(struct bnx2x_softc *sc)
9913 uint32_t base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9914 uint32_t stride = (PXP2_REG_PGL_PRETEND_FUNC_F1 - base);
9915 return base + (SC_ABS_FUNC(sc)) * stride;
9919 * Called only on E1H or E2.
9920 * When pretending to be PF, the pretend value is the function number 0..7.
9921 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
9924 static int bnx2x_pretend_func(struct bnx2x_softc *sc, uint16_t pretend_func_val)
9926 uint32_t pretend_reg;
9928 if (CHIP_IS_E1H(sc) && (pretend_func_val > E1H_FUNC_MAX))
9931 /* get my own pretend register */
9932 pretend_reg = bnx2x_get_pretend_reg(sc);
9933 REG_WR(sc, pretend_reg, pretend_func_val);
9934 REG_RD(sc, pretend_reg);
9938 static void bnx2x_setup_fan_failure_detection(struct bnx2x_softc *sc)
9945 val = (SHMEM_RD(sc, dev_info.shared_hw_config.config2) &
9946 SHARED_HW_CFG_FAN_FAILURE_MASK);
9948 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) {
9952 * The fan failure mechanism is usually related to the PHY type since
9953 * the power consumption of the board is affected by the PHY. Currently,
9954 * fan is required for most designs with SFX7101, BNX2X8727 and BNX2X8481.
9956 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) {
9957 for (port = PORT_0; port < PORT_MAX; port++) {
9958 is_required |= elink_fan_failure_det_req(sc,
9962 devinfo.shmem2_base,
9967 if (is_required == 0) {
9971 /* Fan failure is indicated by SPIO 5 */
9972 bnx2x_set_spio(sc, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
9974 /* set to active low mode */
9975 val = REG_RD(sc, MISC_REG_SPIO_INT);
9976 val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
9977 REG_WR(sc, MISC_REG_SPIO_INT, val);
9979 /* enable interrupt to signal the IGU */
9980 val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
9981 val |= MISC_SPIO_SPIO5;
9982 REG_WR(sc, MISC_REG_SPIO_EVENT_EN, val);
9985 static void bnx2x_enable_blocks_attention(struct bnx2x_softc *sc)
9989 REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0);
9990 if (!CHIP_IS_E1x(sc)) {
9991 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0x40);
9993 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0);
9995 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
9996 REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
9998 * mask read length error interrupts in brb for parser
9999 * (parsing unit and 'checksum and crc' unit)
10000 * these errors are legal (PU reads fixed length and CAC can cause
10001 * read length error on truncated packets)
10003 REG_WR(sc, BRB1_REG_BRB1_INT_MASK, 0xFC00);
10004 REG_WR(sc, QM_REG_QM_INT_MASK, 0);
10005 REG_WR(sc, TM_REG_TM_INT_MASK, 0);
10006 REG_WR(sc, XSDM_REG_XSDM_INT_MASK_0, 0);
10007 REG_WR(sc, XSDM_REG_XSDM_INT_MASK_1, 0);
10008 REG_WR(sc, XCM_REG_XCM_INT_MASK, 0);
10009 /* REG_WR(sc, XSEM_REG_XSEM_INT_MASK_0, 0); */
10010 /* REG_WR(sc, XSEM_REG_XSEM_INT_MASK_1, 0); */
10011 REG_WR(sc, USDM_REG_USDM_INT_MASK_0, 0);
10012 REG_WR(sc, USDM_REG_USDM_INT_MASK_1, 0);
10013 REG_WR(sc, UCM_REG_UCM_INT_MASK, 0);
10014 /* REG_WR(sc, USEM_REG_USEM_INT_MASK_0, 0); */
10015 /* REG_WR(sc, USEM_REG_USEM_INT_MASK_1, 0); */
10016 REG_WR(sc, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
10017 REG_WR(sc, CSDM_REG_CSDM_INT_MASK_0, 0);
10018 REG_WR(sc, CSDM_REG_CSDM_INT_MASK_1, 0);
10019 REG_WR(sc, CCM_REG_CCM_INT_MASK, 0);
10020 /* REG_WR(sc, CSEM_REG_CSEM_INT_MASK_0, 0); */
10021 /* REG_WR(sc, CSEM_REG_CSEM_INT_MASK_1, 0); */
10023 val = (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
10024 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
10025 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN);
10026 if (!CHIP_IS_E1x(sc)) {
10027 val |= (PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
10028 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED);
10030 REG_WR(sc, PXP2_REG_PXP2_INT_MASK_0, val);
10032 REG_WR(sc, TSDM_REG_TSDM_INT_MASK_0, 0);
10033 REG_WR(sc, TSDM_REG_TSDM_INT_MASK_1, 0);
10034 REG_WR(sc, TCM_REG_TCM_INT_MASK, 0);
10035 /* REG_WR(sc, TSEM_REG_TSEM_INT_MASK_0, 0); */
10037 if (!CHIP_IS_E1x(sc)) {
10038 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
10039 REG_WR(sc, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
10042 REG_WR(sc, CDU_REG_CDU_INT_MASK, 0);
10043 REG_WR(sc, DMAE_REG_DMAE_INT_MASK, 0);
10044 /* REG_WR(sc, MISC_REG_MISC_INT_MASK, 0); */
10045 REG_WR(sc, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
10049 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
10051 * @sc: driver handle
10053 static int bnx2x_init_hw_common(struct bnx2x_softc *sc)
10055 uint8_t abs_func_id;
10058 PMD_DRV_LOG(DEBUG, "starting common init for func %d", SC_ABS_FUNC(sc));
10061 * take the RESET lock to protect undi_unload flow from accessing
10062 * registers while we are resetting the chip
10064 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10066 bnx2x_reset_common(sc);
10068 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET), 0xffffffff);
10071 if (CHIP_IS_E3(sc)) {
10072 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
10073 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
10076 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET), val);
10078 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10080 ecore_init_block(sc, BLOCK_MISC, PHASE_COMMON);
10082 if (!CHIP_IS_E1x(sc)) {
10084 * 4-port mode or 2-port mode we need to turn off master-enable for
10085 * everyone. After that we turn it back on for self. So, we disregard
10086 * multi-function, and always disable all functions on the given path,
10087 * this means 0,2,4,6 for path 0 and 1,3,5,7 for path 1
10089 for (abs_func_id = SC_PATH(sc);
10090 abs_func_id < (E2_FUNC_MAX * 2); abs_func_id += 2) {
10091 if (abs_func_id == SC_ABS_FUNC(sc)) {
10093 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
10098 bnx2x_pretend_func(sc, abs_func_id);
10100 /* clear pf enable */
10101 bnx2x_pf_disable(sc);
10103 bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10107 ecore_init_block(sc, BLOCK_PXP, PHASE_COMMON);
10109 ecore_init_block(sc, BLOCK_PXP2, PHASE_COMMON);
10110 bnx2x_init_pxp(sc);
10112 #ifdef __BIG_ENDIAN
10113 REG_WR(sc, PXP2_REG_RQ_QM_ENDIAN_M, 1);
10114 REG_WR(sc, PXP2_REG_RQ_TM_ENDIAN_M, 1);
10115 REG_WR(sc, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
10116 REG_WR(sc, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
10117 REG_WR(sc, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
10118 /* make sure this value is 0 */
10119 REG_WR(sc, PXP2_REG_RQ_HC_ENDIAN_M, 0);
10121 //REG_WR(sc, PXP2_REG_RD_PBF_SWAP_MODE, 1);
10122 REG_WR(sc, PXP2_REG_RD_QM_SWAP_MODE, 1);
10123 REG_WR(sc, PXP2_REG_RD_TM_SWAP_MODE, 1);
10124 REG_WR(sc, PXP2_REG_RD_SRC_SWAP_MODE, 1);
10125 REG_WR(sc, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
10128 ecore_ilt_init_page_size(sc, INITOP_SET);
10130 if (CHIP_REV_IS_FPGA(sc) && CHIP_IS_E1H(sc)) {
10131 REG_WR(sc, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
10134 /* let the HW do it's magic... */
10137 /* finish PXP init */
10139 val = REG_RD(sc, PXP2_REG_RQ_CFG_DONE);
10141 PMD_DRV_LOG(NOTICE, "PXP2 CFG failed");
10144 val = REG_RD(sc, PXP2_REG_RD_INIT_DONE);
10146 PMD_DRV_LOG(NOTICE, "PXP2 RD_INIT failed");
10151 * Timer bug workaround for E2 only. We need to set the entire ILT to have
10152 * entries with value "0" and valid bit on. This needs to be done by the
10153 * first PF that is loaded in a path (i.e. common phase)
10155 if (!CHIP_IS_E1x(sc)) {
10157 * In E2 there is a bug in the timers block that can cause function 6 / 7
10158 * (i.e. vnic3) to start even if it is marked as "scan-off".
10159 * This occurs when a different function (func2,3) is being marked
10160 * as "scan-off". Real-life scenario for example: if a driver is being
10161 * load-unloaded while func6,7 are down. This will cause the timer to access
10162 * the ilt, translate to a logical address and send a request to read/write.
10163 * Since the ilt for the function that is down is not valid, this will cause
10164 * a translation error which is unrecoverable.
10165 * The Workaround is intended to make sure that when this happens nothing
10166 * fatal will occur. The workaround:
10167 * 1. First PF driver which loads on a path will:
10168 * a. After taking the chip out of reset, by using pretend,
10169 * it will write "0" to the following registers of
10171 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10172 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
10173 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
10174 * And for itself it will write '1' to
10175 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
10176 * dmae-operations (writing to pram for example.)
10177 * note: can be done for only function 6,7 but cleaner this
10179 * b. Write zero+valid to the entire ILT.
10180 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
10181 * VNIC3 (of that port). The range allocated will be the
10182 * entire ILT. This is needed to prevent ILT range error.
10183 * 2. Any PF driver load flow:
10184 * a. ILT update with the physical addresses of the allocated
10186 * b. Wait 20msec. - note that this timeout is needed to make
10187 * sure there are no requests in one of the PXP internal
10188 * queues with "old" ILT addresses.
10189 * c. PF enable in the PGLC.
10190 * d. Clear the was_error of the PF in the PGLC. (could have
10191 * occurred while driver was down)
10192 * e. PF enable in the CFC (WEAK + STRONG)
10193 * f. Timers scan enable
10194 * 3. PF driver unload flow:
10195 * a. Clear the Timers scan_en.
10196 * b. Polling for scan_on=0 for that PF.
10197 * c. Clear the PF enable bit in the PXP.
10198 * d. Clear the PF enable in the CFC (WEAK + STRONG)
10199 * e. Write zero+valid to all ILT entries (The valid bit must
10201 * f. If this is VNIC 3 of a port then also init
10202 * first_timers_ilt_entry to zero and last_timers_ilt_entry
10203 * to the last enrty in the ILT.
10206 * Currently the PF error in the PGLC is non recoverable.
10207 * In the future the there will be a recovery routine for this error.
10208 * Currently attention is masked.
10209 * Having an MCP lock on the load/unload process does not guarantee that
10210 * there is no Timer disable during Func6/7 enable. This is because the
10211 * Timers scan is currently being cleared by the MCP on FLR.
10212 * Step 2.d can be done only for PF6/7 and the driver can also check if
10213 * there is error before clearing it. But the flow above is simpler and
10215 * All ILT entries are written by zero+valid and not just PF6/7
10216 * ILT entries since in the future the ILT entries allocation for
10217 * PF-s might be dynamic.
10219 struct ilt_client_info ilt_cli;
10220 struct ecore_ilt ilt;
10222 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
10223 memset(&ilt, 0, sizeof(struct ecore_ilt));
10225 /* initialize dummy TM client */
10227 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
10228 ilt_cli.client_num = ILT_CLIENT_TM;
10231 * Step 1: set zeroes to all ilt page entries with valid bit on
10232 * Step 2: set the timers first/last ilt entry to point
10233 * to the entire range to prevent ILT range error for 3rd/4th
10234 * vnic (this code assumes existence of the vnic)
10236 * both steps performed by call to ecore_ilt_client_init_op()
10237 * with dummy TM client
10239 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
10240 * and his brother are split registers
10243 bnx2x_pretend_func(sc, (SC_PATH(sc) + 6));
10244 ecore_ilt_client_init_op_ilt(sc, &ilt, &ilt_cli, INITOP_CLEAR);
10245 bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10247 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
10248 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
10249 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
10252 REG_WR(sc, PXP2_REG_RQ_DISABLE_INPUTS, 0);
10253 REG_WR(sc, PXP2_REG_RD_DISABLE_INPUTS, 0);
10255 if (!CHIP_IS_E1x(sc)) {
10258 ecore_init_block(sc, BLOCK_PGLUE_B, PHASE_COMMON);
10259 ecore_init_block(sc, BLOCK_ATC, PHASE_COMMON);
10261 /* let the HW do it's magic... */
10264 val = REG_RD(sc, ATC_REG_ATC_INIT_DONE);
10265 } while (factor-- && (val != 1));
10268 PMD_DRV_LOG(NOTICE, "ATC_INIT failed");
10273 ecore_init_block(sc, BLOCK_DMAE, PHASE_COMMON);
10275 /* clean the DMAE memory */
10276 sc->dmae_ready = 1;
10277 ecore_init_fill(sc, TSEM_REG_PRAM, 0, 8);
10279 ecore_init_block(sc, BLOCK_TCM, PHASE_COMMON);
10281 ecore_init_block(sc, BLOCK_UCM, PHASE_COMMON);
10283 ecore_init_block(sc, BLOCK_CCM, PHASE_COMMON);
10285 ecore_init_block(sc, BLOCK_XCM, PHASE_COMMON);
10287 bnx2x_read_dmae(sc, XSEM_REG_PASSIVE_BUFFER, 3);
10288 bnx2x_read_dmae(sc, CSEM_REG_PASSIVE_BUFFER, 3);
10289 bnx2x_read_dmae(sc, TSEM_REG_PASSIVE_BUFFER, 3);
10290 bnx2x_read_dmae(sc, USEM_REG_PASSIVE_BUFFER, 3);
10292 ecore_init_block(sc, BLOCK_QM, PHASE_COMMON);
10294 /* QM queues pointers table */
10295 ecore_qm_init_ptr_table(sc, sc->qm_cid_count, INITOP_SET);
10297 /* soft reset pulse */
10298 REG_WR(sc, QM_REG_SOFT_RESET, 1);
10299 REG_WR(sc, QM_REG_SOFT_RESET, 0);
10301 if (CNIC_SUPPORT(sc))
10302 ecore_init_block(sc, BLOCK_TM, PHASE_COMMON);
10304 ecore_init_block(sc, BLOCK_DORQ, PHASE_COMMON);
10305 REG_WR(sc, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
10307 if (!CHIP_REV_IS_SLOW(sc)) {
10308 /* enable hw interrupt from doorbell Q */
10309 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
10312 ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON);
10314 ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON);
10315 REG_WR(sc, PRS_REG_A_PRSU_20, 0xf);
10316 REG_WR(sc, PRS_REG_E1HOV_MODE, sc->devinfo.mf_info.path_has_ovlan);
10318 if (!CHIP_IS_E1x(sc) && !CHIP_IS_E3B0(sc)) {
10319 if (IS_MF_AFEX(sc)) {
10321 * configure that AFEX and VLAN headers must be
10322 * received in AFEX mode
10324 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC, 0xE);
10325 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS, 0xA);
10326 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
10327 REG_WR(sc, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
10328 REG_WR(sc, PRS_REG_TAG_LEN_0, 0x4);
10331 * Bit-map indicating which L2 hdrs may appear
10332 * after the basic Ethernet header
10334 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC,
10335 sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10339 ecore_init_block(sc, BLOCK_TSDM, PHASE_COMMON);
10340 ecore_init_block(sc, BLOCK_CSDM, PHASE_COMMON);
10341 ecore_init_block(sc, BLOCK_USDM, PHASE_COMMON);
10342 ecore_init_block(sc, BLOCK_XSDM, PHASE_COMMON);
10344 if (!CHIP_IS_E1x(sc)) {
10345 /* reset VFC memories */
10346 REG_WR(sc, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10347 VFC_MEMORIES_RST_REG_CAM_RST |
10348 VFC_MEMORIES_RST_REG_RAM_RST);
10349 REG_WR(sc, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10350 VFC_MEMORIES_RST_REG_CAM_RST |
10351 VFC_MEMORIES_RST_REG_RAM_RST);
10356 ecore_init_block(sc, BLOCK_TSEM, PHASE_COMMON);
10357 ecore_init_block(sc, BLOCK_USEM, PHASE_COMMON);
10358 ecore_init_block(sc, BLOCK_CSEM, PHASE_COMMON);
10359 ecore_init_block(sc, BLOCK_XSEM, PHASE_COMMON);
10361 /* sync semi rtc */
10362 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x80000000);
10363 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x80000000);
10365 ecore_init_block(sc, BLOCK_UPB, PHASE_COMMON);
10366 ecore_init_block(sc, BLOCK_XPB, PHASE_COMMON);
10367 ecore_init_block(sc, BLOCK_PBF, PHASE_COMMON);
10369 if (!CHIP_IS_E1x(sc)) {
10370 if (IS_MF_AFEX(sc)) {
10372 * configure that AFEX and VLAN headers must be
10373 * sent in AFEX mode
10375 REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC, 0xE);
10376 REG_WR(sc, PBF_REG_MUST_HAVE_HDRS, 0xA);
10377 REG_WR(sc, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
10378 REG_WR(sc, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
10379 REG_WR(sc, PBF_REG_TAG_LEN_0, 0x4);
10381 REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC,
10382 sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10386 REG_WR(sc, SRC_REG_SOFT_RST, 1);
10388 ecore_init_block(sc, BLOCK_SRC, PHASE_COMMON);
10390 if (CNIC_SUPPORT(sc)) {
10391 REG_WR(sc, SRC_REG_KEYSEARCH_0, 0x63285672);
10392 REG_WR(sc, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
10393 REG_WR(sc, SRC_REG_KEYSEARCH_2, 0x223aef9b);
10394 REG_WR(sc, SRC_REG_KEYSEARCH_3, 0x26001e3a);
10395 REG_WR(sc, SRC_REG_KEYSEARCH_4, 0x7ae91116);
10396 REG_WR(sc, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
10397 REG_WR(sc, SRC_REG_KEYSEARCH_6, 0x298d8adf);
10398 REG_WR(sc, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
10399 REG_WR(sc, SRC_REG_KEYSEARCH_8, 0x1830f82f);
10400 REG_WR(sc, SRC_REG_KEYSEARCH_9, 0x01e46be7);
10402 REG_WR(sc, SRC_REG_SOFT_RST, 0);
10404 if (sizeof(union cdu_context) != 1024) {
10405 /* we currently assume that a context is 1024 bytes */
10406 PMD_DRV_LOG(NOTICE,
10407 "please adjust the size of cdu_context(%ld)",
10408 (long)sizeof(union cdu_context));
10411 ecore_init_block(sc, BLOCK_CDU, PHASE_COMMON);
10412 val = (4 << 24) + (0 << 12) + 1024;
10413 REG_WR(sc, CDU_REG_CDU_GLOBAL_PARAMS, val);
10415 ecore_init_block(sc, BLOCK_CFC, PHASE_COMMON);
10417 REG_WR(sc, CFC_REG_INIT_REG, 0x7FF);
10418 /* enable context validation interrupt from CFC */
10419 REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
10421 /* set the thresholds to prevent CFC/CDU race */
10422 REG_WR(sc, CFC_REG_DEBUG0, 0x20020000);
10423 ecore_init_block(sc, BLOCK_HC, PHASE_COMMON);
10425 if (!CHIP_IS_E1x(sc) && BNX2X_NOMCP(sc)) {
10426 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x36);
10429 ecore_init_block(sc, BLOCK_IGU, PHASE_COMMON);
10430 ecore_init_block(sc, BLOCK_MISC_AEU, PHASE_COMMON);
10432 /* Reset PCIE errors for debug */
10433 REG_WR(sc, 0x2814, 0xffffffff);
10434 REG_WR(sc, 0x3820, 0xffffffff);
10436 if (!CHIP_IS_E1x(sc)) {
10437 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
10438 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
10439 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
10440 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
10441 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
10442 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
10443 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
10444 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
10445 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
10446 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
10447 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
10450 ecore_init_block(sc, BLOCK_NIG, PHASE_COMMON);
10452 /* in E3 this done in per-port section */
10453 if (!CHIP_IS_E3(sc))
10454 REG_WR(sc, NIG_REG_LLH_MF_MODE, IS_MF(sc));
10456 if (CHIP_IS_E1H(sc)) {
10457 /* not applicable for E2 (and above ...) */
10458 REG_WR(sc, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(sc));
10461 if (CHIP_REV_IS_SLOW(sc)) {
10465 /* finish CFC init */
10466 val = reg_poll(sc, CFC_REG_LL_INIT_DONE, 1, 100, 10);
10468 PMD_DRV_LOG(NOTICE, "CFC LL_INIT failed");
10471 val = reg_poll(sc, CFC_REG_AC_INIT_DONE, 1, 100, 10);
10473 PMD_DRV_LOG(NOTICE, "CFC AC_INIT failed");
10476 val = reg_poll(sc, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
10478 PMD_DRV_LOG(NOTICE, "CFC CAM_INIT failed");
10481 REG_WR(sc, CFC_REG_DEBUG0, 0);
10483 bnx2x_setup_fan_failure_detection(sc);
10485 /* clear PXP2 attentions */
10486 REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
10488 bnx2x_enable_blocks_attention(sc);
10490 if (!CHIP_REV_IS_SLOW(sc)) {
10491 ecore_enable_blocks_parity(sc);
10494 if (!BNX2X_NOMCP(sc)) {
10495 if (CHIP_IS_E1x(sc)) {
10496 bnx2x_common_init_phy(sc);
10504 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
10506 * @sc: driver handle
10508 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc)
10510 int rc = bnx2x_init_hw_common(sc);
10516 /* In E2 2-PORT mode, same ext phy is used for the two paths */
10517 if (!BNX2X_NOMCP(sc)) {
10518 bnx2x_common_init_phy(sc);
10524 static int bnx2x_init_hw_port(struct bnx2x_softc *sc)
10526 int port = SC_PORT(sc);
10527 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
10528 uint32_t low, high;
10531 PMD_DRV_LOG(DEBUG, "starting port init for port %d", port);
10533 REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
10535 ecore_init_block(sc, BLOCK_MISC, init_phase);
10536 ecore_init_block(sc, BLOCK_PXP, init_phase);
10537 ecore_init_block(sc, BLOCK_PXP2, init_phase);
10540 * Timers bug workaround: disables the pf_master bit in pglue at
10541 * common phase, we need to enable it here before any dmae access are
10542 * attempted. Therefore we manually added the enable-master to the
10543 * port phase (it also happens in the function phase)
10545 if (!CHIP_IS_E1x(sc)) {
10546 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
10549 ecore_init_block(sc, BLOCK_ATC, init_phase);
10550 ecore_init_block(sc, BLOCK_DMAE, init_phase);
10551 ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
10552 ecore_init_block(sc, BLOCK_QM, init_phase);
10554 ecore_init_block(sc, BLOCK_TCM, init_phase);
10555 ecore_init_block(sc, BLOCK_UCM, init_phase);
10556 ecore_init_block(sc, BLOCK_CCM, init_phase);
10557 ecore_init_block(sc, BLOCK_XCM, init_phase);
10559 /* QM cid (connection) count */
10560 ecore_qm_init_cid_count(sc, sc->qm_cid_count, INITOP_SET);
10562 if (CNIC_SUPPORT(sc)) {
10563 ecore_init_block(sc, BLOCK_TM, init_phase);
10564 REG_WR(sc, TM_REG_LIN0_SCAN_TIME + port * 4, 20);
10565 REG_WR(sc, TM_REG_LIN0_MAX_ACTIVE_CID + port * 4, 31);
10568 ecore_init_block(sc, BLOCK_DORQ, init_phase);
10570 ecore_init_block(sc, BLOCK_BRB1, init_phase);
10572 if (CHIP_IS_E1H(sc)) {
10574 low = (BNX2X_ONE_PORT(sc) ? 160 : 246);
10575 } else if (sc->mtu > 4096) {
10576 if (BNX2X_ONE_PORT(sc)) {
10580 /* (24*1024 + val*4)/256 */
10581 low = (96 + (val / 64) + ((val % 64) ? 1 : 0));
10584 low = (BNX2X_ONE_PORT(sc) ? 80 : 160);
10586 high = (low + 56); /* 14*1024/256 */
10587 REG_WR(sc, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port * 4, low);
10588 REG_WR(sc, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port * 4, high);
10591 if (CHIP_IS_MODE_4_PORT(sc)) {
10592 REG_WR(sc, SC_PORT(sc) ?
10593 BRB1_REG_MAC_GUARANTIED_1 :
10594 BRB1_REG_MAC_GUARANTIED_0, 40);
10597 ecore_init_block(sc, BLOCK_PRS, init_phase);
10598 if (CHIP_IS_E3B0(sc)) {
10599 if (IS_MF_AFEX(sc)) {
10600 /* configure headers for AFEX mode */
10602 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_1,
10604 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_1,
10606 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_1, 0xA);
10608 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10610 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_0,
10612 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
10615 /* Ovlan exists only if we are in multi-function +
10616 * switch-dependent mode, in switch-independent there
10617 * is no ovlan headers
10619 REG_WR(sc, SC_PORT(sc) ?
10620 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
10621 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10622 (sc->devinfo.mf_info.path_has_ovlan ? 7 : 6));
10626 ecore_init_block(sc, BLOCK_TSDM, init_phase);
10627 ecore_init_block(sc, BLOCK_CSDM, init_phase);
10628 ecore_init_block(sc, BLOCK_USDM, init_phase);
10629 ecore_init_block(sc, BLOCK_XSDM, init_phase);
10631 ecore_init_block(sc, BLOCK_TSEM, init_phase);
10632 ecore_init_block(sc, BLOCK_USEM, init_phase);
10633 ecore_init_block(sc, BLOCK_CSEM, init_phase);
10634 ecore_init_block(sc, BLOCK_XSEM, init_phase);
10636 ecore_init_block(sc, BLOCK_UPB, init_phase);
10637 ecore_init_block(sc, BLOCK_XPB, init_phase);
10639 ecore_init_block(sc, BLOCK_PBF, init_phase);
10641 if (CHIP_IS_E1x(sc)) {
10642 /* configure PBF to work without PAUSE mtu 9000 */
10643 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 0);
10645 /* update threshold */
10646 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, (9040 / 16));
10647 /* update init credit */
10648 REG_WR(sc, PBF_REG_P0_INIT_CRD + port * 4,
10649 (9040 / 16) + 553 - 22);
10651 /* probe changes */
10652 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 1);
10654 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0);
10657 if (CNIC_SUPPORT(sc)) {
10658 ecore_init_block(sc, BLOCK_SRC, init_phase);
10661 ecore_init_block(sc, BLOCK_CDU, init_phase);
10662 ecore_init_block(sc, BLOCK_CFC, init_phase);
10663 ecore_init_block(sc, BLOCK_HC, init_phase);
10664 ecore_init_block(sc, BLOCK_IGU, init_phase);
10665 ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
10666 /* init aeu_mask_attn_func_0/1:
10667 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
10668 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
10669 * bits 4-7 are used for "per vn group attention" */
10670 val = IS_MF(sc) ? 0xF7 : 0x7;
10672 REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, val);
10674 ecore_init_block(sc, BLOCK_NIG, init_phase);
10676 if (!CHIP_IS_E1x(sc)) {
10677 /* Bit-map indicating which L2 hdrs may appear after the
10678 * basic Ethernet header
10680 if (IS_MF_AFEX(sc)) {
10681 REG_WR(sc, SC_PORT(sc) ?
10682 NIG_REG_P1_HDRS_AFTER_BASIC :
10683 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
10685 REG_WR(sc, SC_PORT(sc) ?
10686 NIG_REG_P1_HDRS_AFTER_BASIC :
10687 NIG_REG_P0_HDRS_AFTER_BASIC,
10688 IS_MF_SD(sc) ? 7 : 6);
10691 if (CHIP_IS_E3(sc)) {
10692 REG_WR(sc, SC_PORT(sc) ?
10693 NIG_REG_LLH1_MF_MODE :
10694 NIG_REG_LLH_MF_MODE, IS_MF(sc));
10697 if (!CHIP_IS_E3(sc)) {
10698 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1);
10701 /* 0x2 disable mf_ov, 0x1 enable */
10702 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port * 4,
10703 (IS_MF_SD(sc) ? 0x1 : 0x2));
10705 if (!CHIP_IS_E1x(sc)) {
10707 switch (sc->devinfo.mf_info.mf_mode) {
10708 case MULTI_FUNCTION_SD:
10711 case MULTI_FUNCTION_SI:
10712 case MULTI_FUNCTION_AFEX:
10717 REG_WR(sc, (SC_PORT(sc) ? NIG_REG_LLH1_CLS_TYPE :
10718 NIG_REG_LLH0_CLS_TYPE), val);
10720 REG_WR(sc, NIG_REG_LLFC_ENABLE_0 + port * 4, 0);
10721 REG_WR(sc, NIG_REG_LLFC_OUT_EN_0 + port * 4, 0);
10722 REG_WR(sc, NIG_REG_PAUSE_ENABLE_0 + port * 4, 1);
10724 /* If SPIO5 is set to generate interrupts, enable it for this port */
10725 val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
10726 if (val & MISC_SPIO_SPIO5) {
10727 uint32_t reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
10728 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
10729 val = REG_RD(sc, reg_addr);
10730 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
10731 REG_WR(sc, reg_addr, val);
10738 bnx2x_flr_clnup_reg_poll(struct bnx2x_softc *sc, uint32_t reg,
10739 uint32_t expected, uint32_t poll_count)
10741 uint32_t cur_cnt = poll_count;
10744 while ((val = REG_RD(sc, reg)) != expected && cur_cnt--) {
10745 DELAY(FLR_WAIT_INTERVAL);
10752 bnx2x_flr_clnup_poll_hw_counter(struct bnx2x_softc *sc, uint32_t reg,
10753 __rte_unused const char *msg, uint32_t poll_cnt)
10755 uint32_t val = bnx2x_flr_clnup_reg_poll(sc, reg, 0, poll_cnt);
10758 PMD_DRV_LOG(NOTICE, "%s usage count=%d", msg, val);
10765 /* Common routines with VF FLR cleanup */
10766 static uint32_t bnx2x_flr_clnup_poll_count(struct bnx2x_softc *sc)
10768 /* adjust polling timeout */
10769 if (CHIP_REV_IS_EMUL(sc)) {
10770 return FLR_POLL_CNT * 2000;
10773 if (CHIP_REV_IS_FPGA(sc)) {
10774 return FLR_POLL_CNT * 120;
10777 return FLR_POLL_CNT;
10780 static int bnx2x_poll_hw_usage_counters(struct bnx2x_softc *sc, uint32_t poll_cnt)
10782 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
10783 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10784 CFC_REG_NUM_LCIDS_INSIDE_PF,
10785 "CFC PF usage counter timed out",
10790 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
10791 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10792 DORQ_REG_PF_USAGE_CNT,
10793 "DQ PF usage counter timed out",
10798 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
10799 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10800 QM_REG_PF_USG_CNT_0 + 4 * SC_FUNC(sc),
10801 "QM PF usage counter timed out",
10806 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
10807 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10808 TM_REG_LIN0_VNIC_UC + 4 * SC_PORT(sc),
10809 "Timers VNIC usage counter timed out",
10814 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10815 TM_REG_LIN0_NUM_SCANS +
10817 "Timers NUM_SCANS usage counter timed out",
10822 /* Wait DMAE PF usage counter to zero */
10823 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10824 dmae_reg_go_c[INIT_DMAE_C(sc)],
10825 "DMAE dommand register timed out",
10833 #define OP_GEN_PARAM(param) \
10834 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
10835 #define OP_GEN_TYPE(type) \
10836 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
10837 #define OP_GEN_AGG_VECT(index) \
10838 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
10841 bnx2x_send_final_clnup(struct bnx2x_softc *sc, uint8_t clnup_func,
10844 uint32_t op_gen_command = 0;
10845 uint32_t comp_addr = (BAR_CSTRORM_INTMEM +
10846 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func));
10849 if (REG_RD(sc, comp_addr)) {
10850 PMD_DRV_LOG(NOTICE,
10851 "Cleanup complete was not 0 before sending");
10855 op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
10856 op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
10857 op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
10858 op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
10860 REG_WR(sc, XSDM_REG_OPERATION_GEN, op_gen_command);
10862 if (bnx2x_flr_clnup_reg_poll(sc, comp_addr, 1, poll_cnt) != 1) {
10863 PMD_DRV_LOG(NOTICE, "FW final cleanup did not succeed");
10864 PMD_DRV_LOG(DEBUG, "At timeout completion address contained %x",
10865 (REG_RD(sc, comp_addr)));
10866 rte_panic("FLR cleanup failed");
10870 /* Zero completion for nxt FLR */
10871 REG_WR(sc, comp_addr, 0);
10877 bnx2x_pbf_pN_buf_flushed(struct bnx2x_softc *sc, struct pbf_pN_buf_regs *regs,
10878 uint32_t poll_count)
10880 uint32_t init_crd, crd, crd_start, crd_freed, crd_freed_start;
10881 uint32_t cur_cnt = poll_count;
10883 crd_freed = crd_freed_start = REG_RD(sc, regs->crd_freed);
10884 crd = crd_start = REG_RD(sc, regs->crd);
10885 init_crd = REG_RD(sc, regs->init_crd);
10887 while ((crd != init_crd) &&
10888 ((uint32_t) ((int32_t) crd_freed - (int32_t) crd_freed_start) <
10889 (init_crd - crd_start))) {
10891 DELAY(FLR_WAIT_INTERVAL);
10892 crd = REG_RD(sc, regs->crd);
10893 crd_freed = REG_RD(sc, regs->crd_freed);
10901 bnx2x_pbf_pN_cmd_flushed(struct bnx2x_softc *sc, struct pbf_pN_cmd_regs *regs,
10902 uint32_t poll_count)
10904 uint32_t occup, to_free, freed, freed_start;
10905 uint32_t cur_cnt = poll_count;
10907 occup = to_free = REG_RD(sc, regs->lines_occup);
10908 freed = freed_start = REG_RD(sc, regs->lines_freed);
10911 ((uint32_t) ((int32_t) freed - (int32_t) freed_start) <
10914 DELAY(FLR_WAIT_INTERVAL);
10915 occup = REG_RD(sc, regs->lines_occup);
10916 freed = REG_RD(sc, regs->lines_freed);
10923 static void bnx2x_tx_hw_flushed(struct bnx2x_softc *sc, uint32_t poll_count)
10925 struct pbf_pN_cmd_regs cmd_regs[] = {
10926 {0, (CHIP_IS_E3B0(sc)) ?
10927 PBF_REG_TQ_OCCUPANCY_Q0 : PBF_REG_P0_TQ_OCCUPANCY,
10928 (CHIP_IS_E3B0(sc)) ?
10929 PBF_REG_TQ_LINES_FREED_CNT_Q0 : PBF_REG_P0_TQ_LINES_FREED_CNT},
10930 {1, (CHIP_IS_E3B0(sc)) ?
10931 PBF_REG_TQ_OCCUPANCY_Q1 : PBF_REG_P1_TQ_OCCUPANCY,
10932 (CHIP_IS_E3B0(sc)) ?
10933 PBF_REG_TQ_LINES_FREED_CNT_Q1 : PBF_REG_P1_TQ_LINES_FREED_CNT},
10934 {4, (CHIP_IS_E3B0(sc)) ?
10935 PBF_REG_TQ_OCCUPANCY_LB_Q : PBF_REG_P4_TQ_OCCUPANCY,
10936 (CHIP_IS_E3B0(sc)) ?
10937 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
10938 PBF_REG_P4_TQ_LINES_FREED_CNT}
10941 struct pbf_pN_buf_regs buf_regs[] = {
10942 {0, (CHIP_IS_E3B0(sc)) ?
10943 PBF_REG_INIT_CRD_Q0 : PBF_REG_P0_INIT_CRD,
10944 (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q0 : PBF_REG_P0_CREDIT,
10945 (CHIP_IS_E3B0(sc)) ?
10946 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
10947 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
10948 {1, (CHIP_IS_E3B0(sc)) ?
10949 PBF_REG_INIT_CRD_Q1 : PBF_REG_P1_INIT_CRD,
10950 (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q1 : PBF_REG_P1_CREDIT,
10951 (CHIP_IS_E3B0(sc)) ?
10952 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
10953 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
10954 {4, (CHIP_IS_E3B0(sc)) ?
10955 PBF_REG_INIT_CRD_LB_Q : PBF_REG_P4_INIT_CRD,
10956 (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_LB_Q : PBF_REG_P4_CREDIT,
10957 (CHIP_IS_E3B0(sc)) ?
10958 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
10959 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
10964 /* Verify the command queues are flushed P0, P1, P4 */
10965 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) {
10966 bnx2x_pbf_pN_cmd_flushed(sc, &cmd_regs[i], poll_count);
10969 /* Verify the transmission buffers are flushed P0, P1, P4 */
10970 for (i = 0; i < ARRAY_SIZE(buf_regs); i++) {
10971 bnx2x_pbf_pN_buf_flushed(sc, &buf_regs[i], poll_count);
10975 static void bnx2x_hw_enable_status(struct bnx2x_softc *sc)
10977 __rte_unused uint32_t val;
10979 val = REG_RD(sc, CFC_REG_WEAK_ENABLE_PF);
10980 PMD_DRV_LOG(DEBUG, "CFC_REG_WEAK_ENABLE_PF is 0x%x", val);
10982 val = REG_RD(sc, PBF_REG_DISABLE_PF);
10983 PMD_DRV_LOG(DEBUG, "PBF_REG_DISABLE_PF is 0x%x", val);
10985 val = REG_RD(sc, IGU_REG_PCI_PF_MSI_EN);
10986 PMD_DRV_LOG(DEBUG, "IGU_REG_PCI_PF_MSI_EN is 0x%x", val);
10988 val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_EN);
10989 PMD_DRV_LOG(DEBUG, "IGU_REG_PCI_PF_MSIX_EN is 0x%x", val);
10991 val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
10992 PMD_DRV_LOG(DEBUG, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x", val);
10994 val = REG_RD(sc, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
10995 PMD_DRV_LOG(DEBUG, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x", val);
10997 val = REG_RD(sc, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
10998 PMD_DRV_LOG(DEBUG, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x", val);
11000 val = REG_RD(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
11001 PMD_DRV_LOG(DEBUG, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x",
11006 * bnx2x_pf_flr_clnup
11007 * a. re-enable target read on the PF
11008 * b. poll cfc per function usgae counter
11009 * c. poll the qm perfunction usage counter
11010 * d. poll the tm per function usage counter
11011 * e. poll the tm per function scan-done indication
11012 * f. clear the dmae channel associated wit hthe PF
11013 * g. zero the igu 'trailing edge' and 'leading edge' regs (attentions)
11014 * h. call the common flr cleanup code with -1 (pf indication)
11016 static int bnx2x_pf_flr_clnup(struct bnx2x_softc *sc)
11018 uint32_t poll_cnt = bnx2x_flr_clnup_poll_count(sc);
11020 /* Re-enable PF target read access */
11021 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
11023 /* Poll HW usage counters */
11024 if (bnx2x_poll_hw_usage_counters(sc, poll_cnt)) {
11028 /* Zero the igu 'trailing edge' and 'leading edge' */
11030 /* Send the FW cleanup command */
11031 if (bnx2x_send_final_clnup(sc, (uint8_t) SC_FUNC(sc), poll_cnt)) {
11037 /* Verify TX hw is flushed */
11038 bnx2x_tx_hw_flushed(sc, poll_cnt);
11040 /* Wait 100ms (not adjusted according to platform) */
11043 /* Verify no pending pci transactions */
11044 if (bnx2x_is_pcie_pending(sc)) {
11045 PMD_DRV_LOG(NOTICE, "PCIE Transactions still pending");
11049 bnx2x_hw_enable_status(sc);
11052 * Master enable - Due to WB DMAE writes performed before this
11053 * register is re-initialized as part of the regular function init
11055 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11060 static int bnx2x_init_hw_func(struct bnx2x_softc *sc)
11062 int port = SC_PORT(sc);
11063 int func = SC_FUNC(sc);
11064 int init_phase = PHASE_PF0 + func;
11065 struct ecore_ilt *ilt = sc->ilt;
11066 uint16_t cdu_ilt_start;
11067 uint32_t addr, val;
11068 uint32_t main_mem_base, main_mem_size, main_mem_prty_clr;
11069 int main_mem_width, rc;
11072 PMD_DRV_LOG(DEBUG, "starting func init for func %d", func);
11075 if (!CHIP_IS_E1x(sc)) {
11076 rc = bnx2x_pf_flr_clnup(sc);
11078 PMD_DRV_LOG(NOTICE, "FLR cleanup failed!");
11083 /* set MSI reconfigure capability */
11084 if (sc->devinfo.int_block == INT_BLOCK_HC) {
11085 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
11086 val = REG_RD(sc, addr);
11087 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
11088 REG_WR(sc, addr, val);
11091 ecore_init_block(sc, BLOCK_PXP, init_phase);
11092 ecore_init_block(sc, BLOCK_PXP2, init_phase);
11095 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
11097 for (i = 0; i < L2_ILT_LINES(sc); i++) {
11098 ilt->lines[cdu_ilt_start + i].page = sc->context[i].vcxt;
11099 ilt->lines[cdu_ilt_start + i].page_mapping =
11100 (phys_addr_t)sc->context[i].vcxt_dma.paddr;
11101 ilt->lines[cdu_ilt_start + i].size = sc->context[i].size;
11103 ecore_ilt_init_op(sc, INITOP_SET);
11105 REG_WR(sc, PRS_REG_NIC_MODE, 1);
11107 if (!CHIP_IS_E1x(sc)) {
11108 uint32_t pf_conf = IGU_PF_CONF_FUNC_EN;
11110 /* Turn on a single ISR mode in IGU if driver is going to use
11113 if ((sc->interrupt_mode != INTR_MODE_MSIX)
11114 || (sc->interrupt_mode != INTR_MODE_SINGLE_MSIX)) {
11115 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
11119 * Timers workaround bug: function init part.
11120 * Need to wait 20msec after initializing ILT,
11121 * needed to make sure there are no requests in
11122 * one of the PXP internal queues with "old" ILT addresses
11127 * Master enable - Due to WB DMAE writes performed before this
11128 * register is re-initialized as part of the regular function
11131 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11132 /* Enable the function in IGU */
11133 REG_WR(sc, IGU_REG_PF_CONFIGURATION, pf_conf);
11136 sc->dmae_ready = 1;
11138 ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
11140 if (!CHIP_IS_E1x(sc))
11141 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
11143 ecore_init_block(sc, BLOCK_ATC, init_phase);
11144 ecore_init_block(sc, BLOCK_DMAE, init_phase);
11145 ecore_init_block(sc, BLOCK_NIG, init_phase);
11146 ecore_init_block(sc, BLOCK_SRC, init_phase);
11147 ecore_init_block(sc, BLOCK_MISC, init_phase);
11148 ecore_init_block(sc, BLOCK_TCM, init_phase);
11149 ecore_init_block(sc, BLOCK_UCM, init_phase);
11150 ecore_init_block(sc, BLOCK_CCM, init_phase);
11151 ecore_init_block(sc, BLOCK_XCM, init_phase);
11152 ecore_init_block(sc, BLOCK_TSEM, init_phase);
11153 ecore_init_block(sc, BLOCK_USEM, init_phase);
11154 ecore_init_block(sc, BLOCK_CSEM, init_phase);
11155 ecore_init_block(sc, BLOCK_XSEM, init_phase);
11157 if (!CHIP_IS_E1x(sc))
11158 REG_WR(sc, QM_REG_PF_EN, 1);
11160 if (!CHIP_IS_E1x(sc)) {
11161 REG_WR(sc, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11162 REG_WR(sc, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11163 REG_WR(sc, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11164 REG_WR(sc, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11166 ecore_init_block(sc, BLOCK_QM, init_phase);
11168 ecore_init_block(sc, BLOCK_TM, init_phase);
11169 ecore_init_block(sc, BLOCK_DORQ, init_phase);
11171 ecore_init_block(sc, BLOCK_BRB1, init_phase);
11172 ecore_init_block(sc, BLOCK_PRS, init_phase);
11173 ecore_init_block(sc, BLOCK_TSDM, init_phase);
11174 ecore_init_block(sc, BLOCK_CSDM, init_phase);
11175 ecore_init_block(sc, BLOCK_USDM, init_phase);
11176 ecore_init_block(sc, BLOCK_XSDM, init_phase);
11177 ecore_init_block(sc, BLOCK_UPB, init_phase);
11178 ecore_init_block(sc, BLOCK_XPB, init_phase);
11179 ecore_init_block(sc, BLOCK_PBF, init_phase);
11180 if (!CHIP_IS_E1x(sc))
11181 REG_WR(sc, PBF_REG_DISABLE_PF, 0);
11183 ecore_init_block(sc, BLOCK_CDU, init_phase);
11185 ecore_init_block(sc, BLOCK_CFC, init_phase);
11187 if (!CHIP_IS_E1x(sc))
11188 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 1);
11191 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
11192 REG_WR(sc, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8, OVLAN(sc));
11195 ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
11197 /* HC init per function */
11198 if (sc->devinfo.int_block == INT_BLOCK_HC) {
11199 if (CHIP_IS_E1H(sc)) {
11200 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11202 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11203 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11205 ecore_init_block(sc, BLOCK_HC, init_phase);
11208 uint32_t num_segs, sb_idx, prod_offset;
11210 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11212 if (!CHIP_IS_E1x(sc)) {
11213 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11214 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11217 ecore_init_block(sc, BLOCK_IGU, init_phase);
11219 if (!CHIP_IS_E1x(sc)) {
11223 * E2 mode: address 0-135 match to the mapping memory;
11224 * 136 - PF0 default prod; 137 - PF1 default prod;
11225 * 138 - PF2 default prod; 139 - PF3 default prod;
11226 * 140 - PF0 attn prod; 141 - PF1 attn prod;
11227 * 142 - PF2 attn prod; 143 - PF3 attn prod;
11228 * 144-147 reserved.
11230 * E1.5 mode - In backward compatible mode;
11231 * for non default SB; each even line in the memory
11232 * holds the U producer and each odd line hold
11233 * the C producer. The first 128 producers are for
11234 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
11235 * producers are for the DSB for each PF.
11236 * Each PF has five segments: (the order inside each
11237 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
11238 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
11239 * 144-147 attn prods;
11241 /* non-default-status-blocks */
11242 num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11243 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
11244 for (sb_idx = 0; sb_idx < sc->igu_sb_cnt; sb_idx++) {
11245 prod_offset = (sc->igu_base_sb + sb_idx) *
11248 for (i = 0; i < num_segs; i++) {
11249 addr = IGU_REG_PROD_CONS_MEMORY +
11250 (prod_offset + i) * 4;
11251 REG_WR(sc, addr, 0);
11253 /* send consumer update with value 0 */
11254 bnx2x_ack_sb(sc, sc->igu_base_sb + sb_idx,
11255 USTORM_ID, 0, IGU_INT_NOP, 1);
11256 bnx2x_igu_clear_sb(sc, sc->igu_base_sb + sb_idx);
11259 /* default-status-blocks */
11260 num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11261 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
11263 if (CHIP_IS_MODE_4_PORT(sc))
11264 dsb_idx = SC_FUNC(sc);
11266 dsb_idx = SC_VN(sc);
11268 prod_offset = (CHIP_INT_MODE_IS_BC(sc) ?
11269 IGU_BC_BASE_DSB_PROD + dsb_idx :
11270 IGU_NORM_BASE_DSB_PROD + dsb_idx);
11273 * igu prods come in chunks of E1HVN_MAX (4) -
11274 * does not matters what is the current chip mode
11276 for (i = 0; i < (num_segs * E1HVN_MAX); i += E1HVN_MAX) {
11277 addr = IGU_REG_PROD_CONS_MEMORY +
11278 (prod_offset + i) * 4;
11279 REG_WR(sc, addr, 0);
11281 /* send consumer update with 0 */
11282 if (CHIP_INT_MODE_IS_BC(sc)) {
11283 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11284 USTORM_ID, 0, IGU_INT_NOP, 1);
11285 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11286 CSTORM_ID, 0, IGU_INT_NOP, 1);
11287 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11288 XSTORM_ID, 0, IGU_INT_NOP, 1);
11289 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11290 TSTORM_ID, 0, IGU_INT_NOP, 1);
11291 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11292 ATTENTION_ID, 0, IGU_INT_NOP, 1);
11294 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11295 USTORM_ID, 0, IGU_INT_NOP, 1);
11296 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11297 ATTENTION_ID, 0, IGU_INT_NOP, 1);
11299 bnx2x_igu_clear_sb(sc, sc->igu_dsb_id);
11301 /* !!! these should become driver const once
11302 rf-tool supports split-68 const */
11303 REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
11304 REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
11305 REG_WR(sc, IGU_REG_SB_MASK_LSB, 0);
11306 REG_WR(sc, IGU_REG_SB_MASK_MSB, 0);
11307 REG_WR(sc, IGU_REG_PBA_STATUS_LSB, 0);
11308 REG_WR(sc, IGU_REG_PBA_STATUS_MSB, 0);
11312 /* Reset PCIE errors for debug */
11313 REG_WR(sc, 0x2114, 0xffffffff);
11314 REG_WR(sc, 0x2120, 0xffffffff);
11316 if (CHIP_IS_E1x(sc)) {
11317 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords */
11318 main_mem_base = HC_REG_MAIN_MEMORY +
11319 SC_PORT(sc) * (main_mem_size * 4);
11320 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
11321 main_mem_width = 8;
11323 val = REG_RD(sc, main_mem_prty_clr);
11326 "Parity errors in HC block during function init (0x%x)!",
11330 /* Clear "false" parity errors in MSI-X table */
11331 for (i = main_mem_base;
11332 i < main_mem_base + main_mem_size * 4;
11333 i += main_mem_width) {
11334 bnx2x_read_dmae(sc, i, main_mem_width / 4);
11335 bnx2x_write_dmae(sc, BNX2X_SP_MAPPING(sc, wb_data),
11336 i, main_mem_width / 4);
11338 /* Clear HC parity attention */
11339 REG_RD(sc, main_mem_prty_clr);
11342 /* Enable STORMs SP logging */
11343 REG_WR8(sc, BAR_USTRORM_INTMEM +
11344 USTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11345 REG_WR8(sc, BAR_TSTRORM_INTMEM +
11346 TSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11347 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11348 CSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11349 REG_WR8(sc, BAR_XSTRORM_INTMEM +
11350 XSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11352 elink_phy_probe(&sc->link_params);
11357 static void bnx2x_link_reset(struct bnx2x_softc *sc)
11359 if (!BNX2X_NOMCP(sc)) {
11360 elink_lfa_reset(&sc->link_params, &sc->link_vars);
11362 if (!CHIP_REV_IS_SLOW(sc)) {
11363 PMD_DRV_LOG(WARNING,
11364 "Bootcode is missing - cannot reset link");
11369 static void bnx2x_reset_port(struct bnx2x_softc *sc)
11371 int port = SC_PORT(sc);
11374 /* reset physical Link */
11375 bnx2x_link_reset(sc);
11377 REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
11379 /* Do not rcv packets to BRB */
11380 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + port * 4, 0x0);
11381 /* Do not direct rcv packets that are not for MCP to the BRB */
11382 REG_WR(sc, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
11383 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
11385 /* Configure AEU */
11386 REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, 0);
11390 /* Check for BRB port occupancy */
11391 val = REG_RD(sc, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port * 4);
11394 "BRB1 is not empty, %d blocks are occupied", val);
11398 static void bnx2x_ilt_wr(struct bnx2x_softc *sc, uint32_t index, phys_addr_t addr)
11401 uint32_t wb_write[2];
11403 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index * 8;
11405 wb_write[0] = ONCHIP_ADDR1(addr);
11406 wb_write[1] = ONCHIP_ADDR2(addr);
11407 REG_WR_DMAE(sc, reg, wb_write, 2);
11410 static void bnx2x_clear_func_ilt(struct bnx2x_softc *sc, uint32_t func)
11412 uint32_t i, base = FUNC_ILT_BASE(func);
11413 for (i = base; i < base + ILT_PER_FUNC; i++) {
11414 bnx2x_ilt_wr(sc, i, 0);
11418 static void bnx2x_reset_func(struct bnx2x_softc *sc)
11420 struct bnx2x_fastpath *fp;
11421 int port = SC_PORT(sc);
11422 int func = SC_FUNC(sc);
11425 /* Disable the function in the FW */
11426 REG_WR8(sc, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
11427 REG_WR8(sc, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
11428 REG_WR8(sc, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
11429 REG_WR8(sc, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
11432 FOR_EACH_ETH_QUEUE(sc, i) {
11434 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11435 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
11440 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11441 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), SB_DISABLED);
11443 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) {
11444 REG_WR(sc, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
11448 /* Configure IGU */
11449 if (sc->devinfo.int_block == INT_BLOCK_HC) {
11450 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11451 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11453 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11454 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11457 if (CNIC_LOADED(sc)) {
11458 /* Disable Timer scan */
11459 REG_WR(sc, TM_REG_EN_LINEAR0_TIMER + port * 4, 0);
11461 * Wait for at least 10ms and up to 2 second for the timers
11464 for (i = 0; i < 200; i++) {
11466 if (!REG_RD(sc, TM_REG_LIN0_SCAN_ON + port * 4))
11472 bnx2x_clear_func_ilt(sc, func);
11475 * Timers workaround bug for E2: if this is vnic-3,
11476 * we need to set the entire ilt range for this timers.
11478 if (!CHIP_IS_E1x(sc) && SC_VN(sc) == 3) {
11479 struct ilt_client_info ilt_cli;
11480 /* use dummy TM client */
11481 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
11483 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
11484 ilt_cli.client_num = ILT_CLIENT_TM;
11486 ecore_ilt_boundry_init_op(sc, &ilt_cli, 0);
11489 /* this assumes that reset_port() called before reset_func() */
11490 if (!CHIP_IS_E1x(sc)) {
11491 bnx2x_pf_disable(sc);
11494 sc->dmae_ready = 0;
11497 static void bnx2x_release_firmware(struct bnx2x_softc *sc)
11499 rte_free(sc->init_ops);
11500 rte_free(sc->init_ops_offsets);
11501 rte_free(sc->init_data);
11502 rte_free(sc->iro_array);
11505 static int bnx2x_init_firmware(struct bnx2x_softc *sc)
11508 uint8_t *p = sc->firmware;
11511 for (i = 0; i < 24; ++i)
11512 off[i] = rte_be_to_cpu_32(*((uint32_t *) sc->firmware + i));
11515 sc->init_ops = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11518 bnx2x_data_to_init_ops(p + off[1], sc->init_ops, len);
11521 sc->init_ops_offsets = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11522 if (!sc->init_ops_offsets)
11524 bnx2x_data_to_init_offsets(p + off[3], sc->init_ops_offsets, len);
11527 sc->init_data = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11528 if (!sc->init_data)
11530 bnx2x_data_to_init_data(p + off[5], sc->init_data, len);
11532 sc->tsem_int_table_data = p + off[7];
11533 sc->tsem_pram_data = p + off[9];
11534 sc->usem_int_table_data = p + off[11];
11535 sc->usem_pram_data = p + off[13];
11536 sc->csem_int_table_data = p + off[15];
11537 sc->csem_pram_data = p + off[17];
11538 sc->xsem_int_table_data = p + off[19];
11539 sc->xsem_pram_data = p + off[21];
11542 sc->iro_array = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11543 if (!sc->iro_array)
11545 bnx2x_data_to_iro_array(p + off[23], sc->iro_array, len);
11550 bnx2x_release_firmware(sc);
11554 static int cut_gzip_prefix(const uint8_t * zbuf, int len)
11556 #define MIN_PREFIX_SIZE (10)
11558 int n = MIN_PREFIX_SIZE;
11561 if (!(zbuf[0] == 0x1f && zbuf[1] == 0x8b && zbuf[2] == Z_DEFLATED) ||
11562 len <= MIN_PREFIX_SIZE) {
11566 /* optional extra fields are present */
11567 if (zbuf[3] & 0x4) {
11574 /* file name is present */
11575 if (zbuf[3] & 0x8) {
11576 while ((zbuf[n++] != 0) && (n < len)) ;
11582 static int ecore_gunzip(struct bnx2x_softc *sc, const uint8_t * zbuf, int len)
11585 int data_begin = cut_gzip_prefix(zbuf, len);
11587 PMD_DRV_LOG(DEBUG, "ecore_gunzip %d", len);
11589 if (data_begin <= 0) {
11590 PMD_DRV_LOG(NOTICE, "bad gzip prefix");
11594 memset(&zlib_stream, 0, sizeof(zlib_stream));
11595 zlib_stream.next_in = zbuf + data_begin;
11596 zlib_stream.avail_in = len - data_begin;
11597 zlib_stream.next_out = sc->gz_buf;
11598 zlib_stream.avail_out = FW_BUF_SIZE;
11600 ret = inflateInit2(&zlib_stream, -MAX_WBITS);
11602 PMD_DRV_LOG(NOTICE, "zlib inflateInit2 error");
11606 ret = inflate(&zlib_stream, Z_FINISH);
11607 if ((ret != Z_STREAM_END) && (ret != Z_OK)) {
11608 PMD_DRV_LOG(NOTICE, "zlib inflate error: %d %s", ret,
11612 sc->gz_outlen = zlib_stream.total_out;
11613 if (sc->gz_outlen & 0x3) {
11614 PMD_DRV_LOG(NOTICE, "firmware is not aligned. gz_outlen == %d",
11617 sc->gz_outlen >>= 2;
11619 inflateEnd(&zlib_stream);
11621 if (ret == Z_STREAM_END)
11628 ecore_write_dmae_phys_len(struct bnx2x_softc *sc, phys_addr_t phys_addr,
11629 uint32_t addr, uint32_t len)
11631 bnx2x_write_dmae_phys_len(sc, phys_addr, addr, len);
11635 ecore_storm_memset_struct(struct bnx2x_softc *sc, uint32_t addr, size_t size,
11639 for (i = 0; i < size / 4; i++) {
11640 REG_WR(sc, addr + (i * 4), data[i]);
11644 static const char *get_ext_phy_type(uint32_t ext_phy_type)
11646 uint32_t phy_type_idx = ext_phy_type >> 8;
11647 static const char *types[] =
11648 { "DIRECT", "BNX2X-8071", "BNX2X-8072", "BNX2X-8073",
11649 "BNX2X-8705", "BNX2X-8706", "BNX2X-8726", "BNX2X-8481", "SFX-7101",
11651 "BNX2X-8727-NOC", "BNX2X-84823", "NOT_CONN", "FAILURE"
11654 if (phy_type_idx < 12)
11655 return types[phy_type_idx];
11656 else if (PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN == ext_phy_type)
11662 static const char *get_state(uint32_t state)
11664 uint32_t state_idx = state >> 12;
11665 static const char *states[] = { "CLOSED", "OPENING_WAIT4_LOAD",
11666 "OPENING_WAIT4_PORT", "OPEN", "CLOSING_WAIT4_HALT",
11667 "CLOSING_WAIT4_DELETE", "CLOSING_WAIT4_UNLOAD",
11668 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
11669 "UNKNOWN", "DISABLED", "DIAG", "ERROR", "UNDEFINED"
11672 if (state_idx <= 0xF)
11673 return states[state_idx];
11675 return states[0x10];
11678 static const char *get_recovery_state(uint32_t state)
11680 static const char *states[] = { "NONE", "DONE", "INIT",
11681 "WAIT", "FAILED", "NIC_LOADING"
11683 return states[state];
11686 static const char *get_rx_mode(uint32_t mode)
11688 static const char *modes[] = { "NONE", "NORMAL", "ALLMULTI",
11689 "PROMISC", "MAX_MULTICAST", "ERROR"
11693 return modes[mode];
11694 else if (BNX2X_MAX_MULTICAST == mode)
11700 #define BNX2X_INFO_STR_MAX 256
11701 static const char *get_bnx2x_flags(uint32_t flags)
11704 static const char *flag[] = { "ONE_PORT ", "NO_ISCSI ",
11705 "NO_FCOE ", "NO_WOL ", "USING_DAC ", "USING_MSIX ",
11706 "USING_MSI ", "DISABLE_MSI ", "UNKNOWN ", "NO_MCP ",
11707 "SAFC_TX_FLAG ", "MF_FUNC_DIS ", "TX_SWITCHING "
11709 static char flag_str[BNX2X_INFO_STR_MAX];
11710 memset(flag_str, 0, BNX2X_INFO_STR_MAX);
11712 for (i = 0; i < 5; i++)
11713 if (flags & (1 << i)) {
11714 strcat(flag_str, flag[i]);
11718 static char unknown[BNX2X_INFO_STR_MAX];
11719 snprintf(unknown, 32, "Unknown flag mask %x", flags);
11720 strcat(flag_str, unknown);
11726 * Prints useful adapter info.
11728 void bnx2x_print_adapter_info(struct bnx2x_softc *sc)
11731 __rte_unused uint32_t ext_phy_type;
11733 PMD_INIT_FUNC_TRACE();
11734 if (sc->link_vars.phy_flags & PHY_XGXS_FLAG)
11735 ext_phy_type = ELINK_XGXS_EXT_PHY_TYPE(REG_RD(sc,
11740 dev_info.port_hw_config
11741 [0].external_phy_config)));
11743 ext_phy_type = ELINK_SERDES_EXT_PHY_TYPE(REG_RD(sc,
11749 dev_info.port_hw_config
11750 [0].external_phy_config)));
11752 PMD_INIT_LOG(DEBUG, "\n\n===================================\n");
11753 /* Hardware chip info. */
11754 PMD_INIT_LOG(DEBUG, "%12s : %#08x", "ASIC", sc->devinfo.chip_id);
11755 PMD_INIT_LOG(DEBUG, "%12s : %c%d", "Rev", (CHIP_REV(sc) >> 12) + 'A',
11756 (CHIP_METAL(sc) >> 4));
11759 PMD_INIT_LOG(DEBUG, "%12s : %d, ", "Bus PCIe", sc->devinfo.pcie_link_width);
11760 switch (sc->devinfo.pcie_link_speed) {
11762 PMD_INIT_LOG(DEBUG, "%23s", "2.5 Gbps");
11765 PMD_INIT_LOG(DEBUG, "%21s", "5 Gbps");
11768 PMD_INIT_LOG(DEBUG, "%21s", "8 Gbps");
11771 PMD_INIT_LOG(DEBUG, "%33s", "Unknown link speed");
11774 /* Device features. */
11775 PMD_INIT_LOG(DEBUG, "%12s : ", "Flags");
11777 /* Miscellaneous flags. */
11778 if (sc->devinfo.pcie_cap_flags & BNX2X_MSI_CAPABLE_FLAG) {
11779 PMD_INIT_LOG(DEBUG, "%18s", "MSI");
11783 if (sc->devinfo.pcie_cap_flags & BNX2X_MSIX_CAPABLE_FLAG) {
11785 PMD_INIT_LOG(DEBUG, "|");
11786 PMD_INIT_LOG(DEBUG, "%20s", "MSI-X");
11791 PMD_INIT_LOG(DEBUG, "%12s : ", "Queues");
11792 switch (sc->sp->rss_rdata.rss_mode) {
11793 case ETH_RSS_MODE_DISABLED:
11794 PMD_INIT_LOG(DEBUG, "%19s", "None");
11796 case ETH_RSS_MODE_REGULAR:
11797 PMD_INIT_LOG(DEBUG, "%18s : %d", "RSS", sc->num_queues);
11800 PMD_INIT_LOG(DEBUG, "%22s", "Unknown");
11805 /* RTE and Driver versions */
11806 PMD_INIT_LOG(DEBUG, "%12s : %s", "DPDK",
11808 PMD_INIT_LOG(DEBUG, "%12s : %s", "Driver",
11809 bnx2x_pmd_version());
11811 /* Firmware versions and device features. */
11812 PMD_INIT_LOG(DEBUG, "%12s : %d.%d.%d",
11814 BNX2X_5710_FW_MAJOR_VERSION,
11815 BNX2X_5710_FW_MINOR_VERSION,
11816 BNX2X_5710_FW_REVISION_VERSION);
11817 PMD_INIT_LOG(DEBUG, "%12s : %s",
11818 "Bootcode", sc->devinfo.bc_ver_str);
11820 PMD_INIT_LOG(DEBUG, "\n\n===================================\n");
11821 PMD_INIT_LOG(DEBUG, "%12s : %u", "Bnx2x Func", sc->pcie_func);
11822 PMD_INIT_LOG(DEBUG, "%12s : %s", "Bnx2x Flags", get_bnx2x_flags(sc->flags));
11823 PMD_INIT_LOG(DEBUG, "%12s : %s", "DMAE Is",
11824 (sc->dmae_ready ? "Ready" : "Not Ready"));
11825 PMD_INIT_LOG(DEBUG, "%12s : %s", "OVLAN", (OVLAN(sc) ? "YES" : "NO"));
11826 PMD_INIT_LOG(DEBUG, "%12s : %s", "MF", (IS_MF(sc) ? "YES" : "NO"));
11827 PMD_INIT_LOG(DEBUG, "%12s : %u", "MTU", sc->mtu);
11828 PMD_INIT_LOG(DEBUG, "%12s : %s", "PHY Type", get_ext_phy_type(ext_phy_type));
11829 PMD_INIT_LOG(DEBUG, "%12s : %x:%x:%x:%x:%x:%x", "MAC Addr",
11830 sc->link_params.mac_addr[0],
11831 sc->link_params.mac_addr[1],
11832 sc->link_params.mac_addr[2],
11833 sc->link_params.mac_addr[3],
11834 sc->link_params.mac_addr[4],
11835 sc->link_params.mac_addr[5]);
11836 PMD_INIT_LOG(DEBUG, "%12s : %s", "RX Mode", get_rx_mode(sc->rx_mode));
11837 PMD_INIT_LOG(DEBUG, "%12s : %s", "State", get_state(sc->state));
11838 if (sc->recovery_state)
11839 PMD_INIT_LOG(DEBUG, "%12s : %s", "Recovery",
11840 get_recovery_state(sc->recovery_state));
11841 PMD_INIT_LOG(DEBUG, "%12s : CQ = %lx, EQ = %lx", "SPQ Left",
11842 sc->cq_spq_left, sc->eq_spq_left);
11843 PMD_INIT_LOG(DEBUG, "%12s : %x", "Switch", sc->link_params.switch_cfg);
11844 PMD_INIT_LOG(DEBUG, "\n\n===================================\n");