drivers/net/bnx2x/bnx2x.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2007-2013 Broadcom Corporation.
   3  *
   4  * Eric Davis        <edavis@broadcom.com>
   5  * David Christensen <davidch@broadcom.com>
   6  * Gary Zambrano     <zambrano@broadcom.com>
   7  *
   8  * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
   9  * Copyright (c) 2015-2018 Cavium Inc.
  10  * All rights reserved.
  11  * www.cavium.com
  12  */
  13
  14 #define BNX2X_DRIVER_VERSION "1.78.18"
  15
  16 #include "bnx2x.h"
  17 #include "bnx2x_vfpf.h"
  18 #include "ecore_sp.h"
  19 #include "ecore_init.h"
  20 #include "ecore_init_ops.h"
  21
  22 #include "rte_version.h"
  23
  24 #include <sys/types.h>
  25 #include <sys/stat.h>
  26 #include <arpa/inet.h>
  27 #include <fcntl.h>
  28 #include <zlib.h>
  29 #include <rte_bitops.h>
  30 #include <rte_string_fns.h>
  31
  32 #define BNX2X_PMD_VER_PREFIX "BNX2X PMD"
  33 #define BNX2X_PMD_VERSION_MAJOR 1
  34 #define BNX2X_PMD_VERSION_MINOR 1
  35 #define BNX2X_PMD_VERSION_REVISION 0
  36 #define BNX2X_PMD_VERSION_PATCH 1
  37
  38 static inline const char *
  39 bnx2x_pmd_version(void)
  40 {
  41         static char version[32];
  42
  43         snprintf(version, sizeof(version), "%s %s_%d.%d.%d.%d",
  44                         BNX2X_PMD_VER_PREFIX,
  45                         BNX2X_DRIVER_VERSION,
  46                         BNX2X_PMD_VERSION_MAJOR,
  47                         BNX2X_PMD_VERSION_MINOR,
  48                         BNX2X_PMD_VERSION_REVISION,
  49                         BNX2X_PMD_VERSION_PATCH);
  50
  51         return version;
  52 }
  53
  54 static z_stream zlib_stream;
  55
  56 #define EVL_VLID_MASK 0x0FFF
  57
  58 #define BNX2X_DEF_SB_ATT_IDX 0x0001
  59 #define BNX2X_DEF_SB_IDX     0x0002
  60
  61 /*
  62  * FLR Support - bnx2x_pf_flr_clnup() is called during nic_load in the per
  63  * function HW initialization.
  64  */
  65 #define FLR_WAIT_USEC     10000 /* 10 msecs */
  66 #define FLR_WAIT_INTERVAL 50    /* usecs */
  67 #define FLR_POLL_CNT      (FLR_WAIT_USEC / FLR_WAIT_INTERVAL)   /* 200 */
  68
  69 struct pbf_pN_buf_regs {
  70         int pN;
  71         uint32_t init_crd;
  72         uint32_t crd;
  73         uint32_t crd_freed;
  74 };
  75
  76 struct pbf_pN_cmd_regs {
  77         int pN;
  78         uint32_t lines_occup;
  79         uint32_t lines_freed;
  80 };
  81
  82 /* resources needed for unloading a previously loaded device */
  83
  84 #define BNX2X_PREV_WAIT_NEEDED 1
  85 rte_spinlock_t bnx2x_prev_mtx;
  86 struct bnx2x_prev_list_node {
  87         LIST_ENTRY(bnx2x_prev_list_node) node;
  88         uint8_t bus;
  89         uint8_t slot;
  90         uint8_t path;
  91         uint8_t aer;
  92         uint8_t undi;
  93 };
  94
  95 static LIST_HEAD(, bnx2x_prev_list_node) bnx2x_prev_list
  96         = LIST_HEAD_INITIALIZER(bnx2x_prev_list);
  97
  98 static int load_count[2][3] = { { 0 } };
  99         /* per-path: 0-common, 1-port0, 2-port1 */
 100
 101 static void bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg,
 102                                 uint8_t cmng_type);
 103 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc);
 104 static void storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng,
 105                               uint8_t port);
 106 static void bnx2x_set_reset_global(struct bnx2x_softc *sc);
 107 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc);
 108 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine);
 109 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc);
 110 static uint8_t bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global,
 111                                      uint8_t print);
 112 static void bnx2x_int_disable(struct bnx2x_softc *sc);
 113 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc);
 114 static void bnx2x_pf_disable(struct bnx2x_softc *sc);
 115 static void bnx2x_update_rx_prod(struct bnx2x_softc *sc,
 116                                  struct bnx2x_fastpath *fp,
 117                                  uint16_t rx_bd_prod, uint16_t rx_cq_prod);
 118 static void bnx2x_link_report_locked(struct bnx2x_softc *sc);
 119 static void bnx2x_link_report(struct bnx2x_softc *sc);
 120 void bnx2x_link_status_update(struct bnx2x_softc *sc);
 121 static int bnx2x_alloc_mem(struct bnx2x_softc *sc);
 122 static void bnx2x_free_mem(struct bnx2x_softc *sc);
 123 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc);
 124 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc);
 125 static __rte_noinline
 126 int bnx2x_nic_load(struct bnx2x_softc *sc);
 127
 128 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc);
 129 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp);
 130 static void bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id,
 131                          uint8_t storm, uint16_t index, uint8_t op,
 132                          uint8_t update);
 133
 134 int bnx2x_cmpxchg(volatile int *addr, int old, int new)
 135 {
 136         return __sync_val_compare_and_swap(addr, old, new);
 137 }
 138
 139 int
 140 bnx2x_dma_alloc(struct bnx2x_softc *sc, size_t size, struct bnx2x_dma *dma,
 141               const char *msg, uint32_t align)
 142 {
 143         char mz_name[RTE_MEMZONE_NAMESIZE];
 144         const struct rte_memzone *z;
 145
 146         dma->sc = sc;
 147         if (IS_PF(sc))
 148                 snprintf(mz_name, sizeof(mz_name), "bnx2x%d_%s_%" PRIx64, SC_ABS_FUNC(sc), msg,
 149                         rte_get_timer_cycles());
 150         else
 151                 snprintf(mz_name, sizeof(mz_name), "bnx2x%d_%s_%" PRIx64, sc->pcie_device, msg,
 152                         rte_get_timer_cycles());
 153
 154         /* Caller must take care that strlen(mz_name) < RTE_MEMZONE_NAMESIZE */
 155         z = rte_memzone_reserve_aligned(mz_name, (uint64_t)size,
 156                                         SOCKET_ID_ANY,
 157                                         RTE_MEMZONE_IOVA_CONTIG, align);
 158         if (z == NULL) {
 159                 PMD_DRV_LOG(ERR, sc, "DMA alloc failed for %s", msg);
 160                 return -ENOMEM;
 161         }
 162         dma->paddr = (uint64_t) z->iova;
 163         dma->vaddr = z->addr;
 164         dma->mzone = (const void *)z;
 165
 166         PMD_DRV_LOG(DEBUG, sc,
 167                     "%s: virt=%p phys=%" PRIx64, msg, dma->vaddr, dma->paddr);
 168
 169         return 0;
 170 }
 171
 172 void bnx2x_dma_free(struct bnx2x_dma *dma)
 173 {
 174         if (dma->mzone == NULL)
 175                 return;
 176
 177         rte_memzone_free((const struct rte_memzone *)dma->mzone);
 178         dma->sc = NULL;
 179         dma->paddr = 0;
 180         dma->vaddr = NULL;
 181         dma->nseg = 0;
 182         dma->mzone = NULL;
 183 }
 184
 185 static int bnx2x_acquire_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
 186 {
 187         uint32_t lock_status;
 188         uint32_t resource_bit = (1 << resource);
 189         int func = SC_FUNC(sc);
 190         uint32_t hw_lock_control_reg;
 191         int cnt;
 192
 193 #ifndef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
 194         if (resource)
 195                 PMD_INIT_FUNC_TRACE(sc);
 196 #else
 197         PMD_INIT_FUNC_TRACE(sc);
 198 #endif
 199
 200         /* validate the resource is within range */
 201         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
 202                 PMD_DRV_LOG(NOTICE, sc,
 203                             "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
 204                             resource);
 205                 return -1;
 206         }
 207
 208         if (func <= 5) {
 209                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
 210         } else {
 211                 hw_lock_control_reg =
 212                     (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
 213         }
 214
 215         /* validate the resource is not already taken */
 216         lock_status = REG_RD(sc, hw_lock_control_reg);
 217         if (lock_status & resource_bit) {
 218                 PMD_DRV_LOG(NOTICE, sc,
 219                             "resource in use (status 0x%x bit 0x%x)",
 220                             lock_status, resource_bit);
 221                 return -1;
 222         }
 223
 224         /* try every 5ms for 5 seconds */
 225         for (cnt = 0; cnt < 1000; cnt++) {
 226                 REG_WR(sc, (hw_lock_control_reg + 4), resource_bit);
 227                 lock_status = REG_RD(sc, hw_lock_control_reg);
 228                 if (lock_status & resource_bit) {
 229                         return 0;
 230                 }
 231                 DELAY(5000);
 232         }
 233
 234         PMD_DRV_LOG(NOTICE, sc, "Resource 0x%x resource_bit 0x%x lock timeout!",
 235                     resource, resource_bit);
 236         return -1;
 237 }
 238
 239 static int bnx2x_release_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
 240 {
 241         uint32_t lock_status;
 242         uint32_t resource_bit = (1 << resource);
 243         int func = SC_FUNC(sc);
 244         uint32_t hw_lock_control_reg;
 245
 246 #ifndef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
 247         if (resource)
 248                 PMD_INIT_FUNC_TRACE(sc);
 249 #else
 250         PMD_INIT_FUNC_TRACE(sc);
 251 #endif
 252
 253         /* validate the resource is within range */
 254         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
 255                 PMD_DRV_LOG(NOTICE, sc,
 256                             "(resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE)"
 257                             " resource_bit 0x%x", resource, resource_bit);
 258                 return -1;
 259         }
 260
 261         if (func <= 5) {
 262                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
 263         } else {
 264                 hw_lock_control_reg =
 265                     (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
 266         }
 267
 268         /* validate the resource is currently taken */
 269         lock_status = REG_RD(sc, hw_lock_control_reg);
 270         if (!(lock_status & resource_bit)) {
 271                 PMD_DRV_LOG(NOTICE, sc,
 272                             "resource not in use (status 0x%x bit 0x%x)",
 273                             lock_status, resource_bit);
 274                 return -1;
 275         }
 276
 277         REG_WR(sc, hw_lock_control_reg, resource_bit);
 278         return 0;
 279 }
 280
 281 static void bnx2x_acquire_phy_lock(struct bnx2x_softc *sc)
 282 {
 283         BNX2X_PHY_LOCK(sc);
 284         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_MDIO);
 285 }
 286
 287 static void bnx2x_release_phy_lock(struct bnx2x_softc *sc)
 288 {
 289         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_MDIO);
 290         BNX2X_PHY_UNLOCK(sc);
 291 }
 292
 293 /* copy command into DMAE command memory and set DMAE command Go */
 294 void bnx2x_post_dmae(struct bnx2x_softc *sc, struct dmae_command *dmae, int idx)
 295 {
 296         uint32_t cmd_offset;
 297         uint32_t i;
 298
 299         cmd_offset = (DMAE_REG_CMD_MEM + (sizeof(struct dmae_command) * idx));
 300         for (i = 0; i < ((sizeof(struct dmae_command) / 4)); i++) {
 301                 REG_WR(sc, (cmd_offset + (i * 4)), *(((uint32_t *) dmae) + i));
 302         }
 303
 304         REG_WR(sc, dmae_reg_go_c[idx], 1);
 305 }
 306
 307 uint32_t bnx2x_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type)
 308 {
 309         return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
 310                           DMAE_COMMAND_C_TYPE_ENABLE);
 311 }
 312
 313 uint32_t bnx2x_dmae_opcode_clr_src_reset(uint32_t opcode)
 314 {
 315         return opcode & ~DMAE_COMMAND_SRC_RESET;
 316 }
 317
 318 uint32_t
 319 bnx2x_dmae_opcode(struct bnx2x_softc * sc, uint8_t src_type, uint8_t dst_type,
 320                 uint8_t with_comp, uint8_t comp_type)
 321 {
 322         uint32_t opcode = 0;
 323
 324         opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
 325                    (dst_type << DMAE_COMMAND_DST_SHIFT));
 326
 327         opcode |= (DMAE_COMMAND_SRC_RESET | DMAE_COMMAND_DST_RESET);
 328
 329         opcode |= (SC_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
 330
 331         opcode |= ((SC_VN(sc) << DMAE_COMMAND_E1HVN_SHIFT) |
 332                    (SC_VN(sc) << DMAE_COMMAND_DST_VN_SHIFT));
 333
 334         opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
 335
 336 #ifdef __BIG_ENDIAN
 337         opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
 338 #else
 339         opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
 340 #endif
 341
 342         if (with_comp) {
 343                 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
 344         }
 345
 346         return opcode;
 347 }
 348
 349 static void
 350 bnx2x_prep_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae,
 351                         uint8_t src_type, uint8_t dst_type)
 352 {
 353         memset(dmae, 0, sizeof(struct dmae_command));
 354
 355         /* set the opcode */
 356         dmae->opcode = bnx2x_dmae_opcode(sc, src_type, dst_type,
 357                                        TRUE, DMAE_COMP_PCI);
 358
 359         /* fill in the completion parameters */
 360         dmae->comp_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_comp));
 361         dmae->comp_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_comp));
 362         dmae->comp_val = DMAE_COMP_VAL;
 363 }
 364
 365 /* issue a DMAE command over the init channel and wait for completion */
 366 static int
 367 bnx2x_issue_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae)
 368 {
 369         uint32_t *wb_comp = BNX2X_SP(sc, wb_comp);
 370         int timeout = CHIP_REV_IS_SLOW(sc) ? 400000 : 4000;
 371
 372         /* reset completion */
 373         *wb_comp = 0;
 374
 375         /* post the command on the channel used for initializations */
 376         bnx2x_post_dmae(sc, dmae, INIT_DMAE_C(sc));
 377
 378         /* wait for completion */
 379         DELAY(500);
 380
 381         while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
 382                 if (!timeout ||
 383                     (sc->recovery_state != BNX2X_RECOVERY_DONE &&
 384                      sc->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
 385                         PMD_DRV_LOG(INFO, sc, "DMAE timeout!");
 386                         return DMAE_TIMEOUT;
 387                 }
 388
 389                 timeout--;
 390                 DELAY(50);
 391         }
 392
 393         if (*wb_comp & DMAE_PCI_ERR_FLAG) {
 394                 PMD_DRV_LOG(INFO, sc, "DMAE PCI error!");
 395                 return DMAE_PCI_ERROR;
 396         }
 397
 398         return 0;
 399 }
 400
 401 void bnx2x_read_dmae(struct bnx2x_softc *sc, uint32_t src_addr, uint32_t len32)
 402 {
 403         struct dmae_command dmae;
 404         uint32_t *data;
 405         uint32_t i;
 406         int rc;
 407
 408         if (!sc->dmae_ready) {
 409                 data = BNX2X_SP(sc, wb_data[0]);
 410
 411                 for (i = 0; i < len32; i++) {
 412                         data[i] = REG_RD(sc, (src_addr + (i * 4)));
 413                 }
 414
 415                 return;
 416         }
 417
 418         /* set opcode and fixed command fields */
 419         bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
 420
 421         /* fill in addresses and len */
 422         dmae.src_addr_lo = (src_addr >> 2);     /* GRC addr has dword resolution */
 423         dmae.src_addr_hi = 0;
 424         dmae.dst_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_data));
 425         dmae.dst_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_data));
 426         dmae.len = len32;
 427
 428         /* issue the command and wait for completion */
 429         if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
 430                 rte_panic("DMAE failed (%d)", rc);
 431         };
 432 }
 433
 434 void
 435 bnx2x_write_dmae(struct bnx2x_softc *sc, rte_iova_t dma_addr, uint32_t dst_addr,
 436                uint32_t len32)
 437 {
 438         struct dmae_command dmae;
 439         int rc;
 440
 441         if (!sc->dmae_ready) {
 442                 ecore_init_str_wr(sc, dst_addr, BNX2X_SP(sc, wb_data[0]), len32);
 443                 return;
 444         }
 445
 446         /* set opcode and fixed command fields */
 447         bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
 448
 449         /* fill in addresses and len */
 450         dmae.src_addr_lo = U64_LO(dma_addr);
 451         dmae.src_addr_hi = U64_HI(dma_addr);
 452         dmae.dst_addr_lo = (dst_addr >> 2);     /* GRC addr has dword resolution */
 453         dmae.dst_addr_hi = 0;
 454         dmae.len = len32;
 455
 456         /* issue the command and wait for completion */
 457         if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
 458                 rte_panic("DMAE failed (%d)", rc);
 459         }
 460 }
 461
 462 static void
 463 bnx2x_write_dmae_phys_len(struct bnx2x_softc *sc, rte_iova_t phys_addr,
 464                         uint32_t addr, uint32_t len)
 465 {
 466         uint32_t dmae_wr_max = DMAE_LEN32_WR_MAX(sc);
 467         uint32_t offset = 0;
 468
 469         while (len > dmae_wr_max) {
 470                 bnx2x_write_dmae(sc, (phys_addr + offset),      /* src DMA address */
 471                                (addr + offset), /* dst GRC address */
 472                                dmae_wr_max);
 473                 offset += (dmae_wr_max * 4);
 474                 len -= dmae_wr_max;
 475         }
 476
 477         bnx2x_write_dmae(sc, (phys_addr + offset),      /* src DMA address */
 478                        (addr + offset), /* dst GRC address */
 479                        len);
 480 }
 481
 482 void
 483 bnx2x_set_ctx_validation(struct bnx2x_softc *sc, struct eth_context *cxt,
 484                        uint32_t cid)
 485 {
 486         /* ustorm cxt validation */
 487         cxt->ustorm_ag_context.cdu_usage =
 488             CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
 489                                    CDU_REGION_NUMBER_UCM_AG,
 490                                    ETH_CONNECTION_TYPE);
 491         /* xcontext validation */
 492         cxt->xstorm_ag_context.cdu_reserved =
 493             CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
 494                                    CDU_REGION_NUMBER_XCM_AG,
 495                                    ETH_CONNECTION_TYPE);
 496 }
 497
 498 static void
 499 bnx2x_storm_memset_hc_timeout(struct bnx2x_softc *sc, uint8_t fw_sb_id,
 500                             uint8_t sb_index, uint8_t ticks)
 501 {
 502         uint32_t addr =
 503             (BAR_CSTRORM_INTMEM +
 504              CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(fw_sb_id, sb_index));
 505
 506         REG_WR8(sc, addr, ticks);
 507 }
 508
 509 static void
 510 bnx2x_storm_memset_hc_disable(struct bnx2x_softc *sc, uint16_t fw_sb_id,
 511                             uint8_t sb_index, uint8_t disable)
 512 {
 513         uint32_t enable_flag =
 514             (disable) ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
 515         uint32_t addr =
 516             (BAR_CSTRORM_INTMEM +
 517              CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(fw_sb_id, sb_index));
 518         uint8_t flags;
 519
 520         /* clear and set */
 521         flags = REG_RD8(sc, addr);
 522         flags &= ~HC_INDEX_DATA_HC_ENABLED;
 523         flags |= enable_flag;
 524         REG_WR8(sc, addr, flags);
 525 }
 526
 527 void
 528 bnx2x_update_coalesce_sb_index(struct bnx2x_softc *sc, uint8_t fw_sb_id,
 529                              uint8_t sb_index, uint8_t disable, uint16_t usec)
 530 {
 531         uint8_t ticks = (usec / 4);
 532
 533         bnx2x_storm_memset_hc_timeout(sc, fw_sb_id, sb_index, ticks);
 534
 535         disable = (disable) ? 1 : ((usec) ? 0 : 1);
 536         bnx2x_storm_memset_hc_disable(sc, fw_sb_id, sb_index, disable);
 537 }
 538
 539 uint32_t elink_cb_reg_read(struct bnx2x_softc *sc, uint32_t reg_addr)
 540 {
 541         return REG_RD(sc, reg_addr);
 542 }
 543
 544 void elink_cb_reg_write(struct bnx2x_softc *sc, uint32_t reg_addr, uint32_t val)
 545 {
 546         REG_WR(sc, reg_addr, val);
 547 }
 548
 549 void
 550 elink_cb_event_log(__rte_unused struct bnx2x_softc *sc,
 551                    __rte_unused const elink_log_id_t elink_log_id, ...)
 552 {
 553         PMD_DRV_LOG(DEBUG, sc, "ELINK EVENT LOG (%d)", elink_log_id);
 554 }
 555
 556 static int bnx2x_set_spio(struct bnx2x_softc *sc, int spio, uint32_t mode)
 557 {
 558         uint32_t spio_reg;
 559
 560         /* Only 2 SPIOs are configurable */
 561         if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
 562                 PMD_DRV_LOG(NOTICE, sc, "Invalid SPIO 0x%x", spio);
 563                 return -1;
 564         }
 565
 566         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
 567
 568         /* read SPIO and mask except the float bits */
 569         spio_reg = (REG_RD(sc, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
 570
 571         switch (mode) {
 572         case MISC_SPIO_OUTPUT_LOW:
 573                 /* clear FLOAT and set CLR */
 574                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
 575                 spio_reg |= (spio << MISC_SPIO_CLR_POS);
 576                 break;
 577
 578         case MISC_SPIO_OUTPUT_HIGH:
 579                 /* clear FLOAT and set SET */
 580                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
 581                 spio_reg |= (spio << MISC_SPIO_SET_POS);
 582                 break;
 583
 584         case MISC_SPIO_INPUT_HI_Z:
 585                 /* set FLOAT */
 586                 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
 587                 break;
 588
 589         default:
 590                 break;
 591         }
 592
 593         REG_WR(sc, MISC_REG_SPIO, spio_reg);
 594         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
 595
 596         return 0;
 597 }
 598
 599 static int bnx2x_gpio_read(struct bnx2x_softc *sc, int gpio_num, uint8_t port)
 600 {
 601         /* The GPIO should be swapped if swap register is set and active */
 602         int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
 603                           REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
 604         int gpio_shift = gpio_num;
 605         if (gpio_port)
 606                 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
 607
 608         uint32_t gpio_mask = (1 << gpio_shift);
 609         uint32_t gpio_reg;
 610
 611         if (gpio_num > MISC_REGISTERS_GPIO_3) {
 612                 PMD_DRV_LOG(NOTICE, sc, "Invalid GPIO %d", gpio_num);
 613                 return -1;
 614         }
 615
 616         /* read GPIO value */
 617         gpio_reg = REG_RD(sc, MISC_REG_GPIO);
 618
 619         /* get the requested pin value */
 620         return ((gpio_reg & gpio_mask) == gpio_mask) ? 1 : 0;
 621 }
 622
 623 static int
 624 bnx2x_gpio_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode, uint8_t port)
 625 {
 626         /* The GPIO should be swapped if swap register is set and active */
 627         int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
 628                           REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
 629         int gpio_shift = gpio_num;
 630         if (gpio_port)
 631                 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
 632
 633         uint32_t gpio_mask = (1 << gpio_shift);
 634         uint32_t gpio_reg;
 635
 636         if (gpio_num > MISC_REGISTERS_GPIO_3) {
 637                 PMD_DRV_LOG(NOTICE, sc, "Invalid GPIO %d", gpio_num);
 638                 return -1;
 639         }
 640
 641         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 642
 643         /* read GPIO and mask except the float bits */
 644         gpio_reg = (REG_RD(sc, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
 645
 646         switch (mode) {
 647         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
 648                 /* clear FLOAT and set CLR */
 649                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
 650                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
 651                 break;
 652
 653         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
 654                 /* clear FLOAT and set SET */
 655                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
 656                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
 657                 break;
 658
 659         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
 660                 /* set FLOAT */
 661                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
 662                 break;
 663
 664         default:
 665                 break;
 666         }
 667
 668         REG_WR(sc, MISC_REG_GPIO, gpio_reg);
 669         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 670
 671         return 0;
 672 }
 673
 674 static int
 675 bnx2x_gpio_mult_write(struct bnx2x_softc *sc, uint8_t pins, uint32_t mode)
 676 {
 677         uint32_t gpio_reg;
 678
 679         /* any port swapping should be handled by caller */
 680
 681         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 682
 683         /* read GPIO and mask except the float bits */
 684         gpio_reg = REG_RD(sc, MISC_REG_GPIO);
 685         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
 686         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
 687         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
 688
 689         switch (mode) {
 690         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
 691                 /* set CLR */
 692                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
 693                 break;
 694
 695         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
 696                 /* set SET */
 697                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
 698                 break;
 699
 700         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
 701                 /* set FLOAT */
 702                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
 703                 break;
 704
 705         default:
 706                 PMD_DRV_LOG(NOTICE, sc,
 707                             "Invalid GPIO mode assignment %d", mode);
 708                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 709                 return -1;
 710         }
 711
 712         REG_WR(sc, MISC_REG_GPIO, gpio_reg);
 713         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 714
 715         return 0;
 716 }
 717
 718 static int
 719 bnx2x_gpio_int_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode,
 720                    uint8_t port)
 721 {
 722         /* The GPIO should be swapped if swap register is set and active */
 723         int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
 724                           REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
 725         int gpio_shift = gpio_num;
 726         if (gpio_port)
 727                 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
 728
 729         uint32_t gpio_mask = (1 << gpio_shift);
 730         uint32_t gpio_reg;
 731
 732         if (gpio_num > MISC_REGISTERS_GPIO_3) {
 733                 PMD_DRV_LOG(NOTICE, sc, "Invalid GPIO %d", gpio_num);
 734                 return -1;
 735         }
 736
 737         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 738
 739         /* read GPIO int */
 740         gpio_reg = REG_RD(sc, MISC_REG_GPIO_INT);
 741
 742         switch (mode) {
 743         case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
 744                 /* clear SET and set CLR */
 745                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
 746                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
 747                 break;
 748
 749         case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
 750                 /* clear CLR and set SET */
 751                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
 752                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
 753                 break;
 754
 755         default:
 756                 break;
 757         }
 758
 759         REG_WR(sc, MISC_REG_GPIO_INT, gpio_reg);
 760         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 761
 762         return 0;
 763 }
 764
 765 uint32_t
 766 elink_cb_gpio_read(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t port)
 767 {
 768         return bnx2x_gpio_read(sc, gpio_num, port);
 769 }
 770
 771 uint8_t elink_cb_gpio_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode,   /* 0=low 1=high */
 772                             uint8_t port)
 773 {
 774         return bnx2x_gpio_write(sc, gpio_num, mode, port);
 775 }
 776
 777 uint8_t
 778 elink_cb_gpio_mult_write(struct bnx2x_softc * sc, uint8_t pins,
 779                          uint8_t mode /* 0=low 1=high */ )
 780 {
 781         return bnx2x_gpio_mult_write(sc, pins, mode);
 782 }
 783
 784 uint8_t elink_cb_gpio_int_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode,       /* 0=low 1=high */
 785                                 uint8_t port)
 786 {
 787         return bnx2x_gpio_int_write(sc, gpio_num, mode, port);
 788 }
 789
 790 void elink_cb_notify_link_changed(struct bnx2x_softc *sc)
 791 {
 792         REG_WR(sc, (MISC_REG_AEU_GENERAL_ATTN_12 +
 793                     (SC_FUNC(sc) * sizeof(uint32_t))), 1);
 794 }
 795
 796 /* send the MCP a request, block until there is a reply */
 797 uint32_t
 798 elink_cb_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
 799 {
 800         int mb_idx = SC_FW_MB_IDX(sc);
 801         uint32_t seq;
 802         uint32_t rc = 0;
 803         uint32_t cnt = 1;
 804         uint8_t delay = CHIP_REV_IS_SLOW(sc) ? 100 : 10;
 805
 806         seq = ++sc->fw_seq;
 807         SHMEM_WR(sc, func_mb[mb_idx].drv_mb_param, param);
 808         SHMEM_WR(sc, func_mb[mb_idx].drv_mb_header, (command | seq));
 809
 810         PMD_DRV_LOG(DEBUG, sc,
 811                     "wrote command 0x%08x to FW MB param 0x%08x",
 812                     (command | seq), param);
 813
 814         /* Let the FW do it's magic. GIve it up to 5 seconds... */
 815         do {
 816                 DELAY(delay * 1000);
 817                 rc = SHMEM_RD(sc, func_mb[mb_idx].fw_mb_header);
 818         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
 819
 820         /* is this a reply to our command? */
 821         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) {
 822                 rc &= FW_MSG_CODE_MASK;
 823         } else {
 824                 /* Ruh-roh! */
 825                 PMD_DRV_LOG(NOTICE, sc, "FW failed to respond!");
 826                 rc = 0;
 827         }
 828
 829         return rc;
 830 }
 831
 832 static uint32_t
 833 bnx2x_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
 834 {
 835         return elink_cb_fw_command(sc, command, param);
 836 }
 837
 838 static void
 839 __storm_memset_dma_mapping(struct bnx2x_softc *sc, uint32_t addr,
 840                            rte_iova_t mapping)
 841 {
 842         REG_WR(sc, addr, U64_LO(mapping));
 843         REG_WR(sc, (addr + 4), U64_HI(mapping));
 844 }
 845
 846 static void
 847 storm_memset_spq_addr(struct bnx2x_softc *sc, rte_iova_t mapping,
 848                       uint16_t abs_fid)
 849 {
 850         uint32_t addr = (XSEM_REG_FAST_MEMORY +
 851                          XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid));
 852         __storm_memset_dma_mapping(sc, addr, mapping);
 853 }
 854
 855 static void
 856 storm_memset_vf_to_pf(struct bnx2x_softc *sc, uint16_t abs_fid, uint16_t pf_id)
 857 {
 858         REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid)),
 859                 pf_id);
 860         REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid)),
 861                 pf_id);
 862         REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid)),
 863                 pf_id);
 864         REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid)),
 865                 pf_id);
 866 }
 867
 868 static void
 869 storm_memset_func_en(struct bnx2x_softc *sc, uint16_t abs_fid, uint8_t enable)
 870 {
 871         REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid)),
 872                 enable);
 873         REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid)),
 874                 enable);
 875         REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid)),
 876                 enable);
 877         REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid)),
 878                 enable);
 879 }
 880
 881 static void
 882 storm_memset_eq_data(struct bnx2x_softc *sc, struct event_ring_data *eq_data,
 883                      uint16_t pfid)
 884 {
 885         uint32_t addr;
 886         size_t size;
 887
 888         addr = (BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid));
 889         size = sizeof(struct event_ring_data);
 890         ecore_storm_memset_struct(sc, addr, size, (uint32_t *) eq_data);
 891 }
 892
 893 static void
 894 storm_memset_eq_prod(struct bnx2x_softc *sc, uint16_t eq_prod, uint16_t pfid)
 895 {
 896         uint32_t addr = (BAR_CSTRORM_INTMEM +
 897                          CSTORM_EVENT_RING_PROD_OFFSET(pfid));
 898         REG_WR16(sc, addr, eq_prod);
 899 }
 900
 901 /*
 902  * Post a slowpath command.
 903  *
 904  * A slowpath command is used to propagate a configuration change through
 905  * the controller in a controlled manner, allowing each STORM processor and
 906  * other H/W blocks to phase in the change.  The commands sent on the
 907  * slowpath are referred to as ramrods.  Depending on the ramrod used the
 908  * completion of the ramrod will occur in different ways.  Here's a
 909  * breakdown of ramrods and how they complete:
 910  *
 911  * RAMROD_CMD_ID_ETH_PORT_SETUP
 912  *   Used to setup the leading connection on a port.  Completes on the
 913  *   Receive Completion Queue (RCQ) of that port (typically fp[0]).
 914  *
 915  * RAMROD_CMD_ID_ETH_CLIENT_SETUP
 916  *   Used to setup an additional connection on a port.  Completes on the
 917  *   RCQ of the multi-queue/RSS connection being initialized.
 918  *
 919  * RAMROD_CMD_ID_ETH_STAT_QUERY
 920  *   Used to force the storm processors to update the statistics database
 921  *   in host memory.  This ramrod is send on the leading connection CID and
 922  *   completes as an index increment of the CSTORM on the default status
 923  *   block.
 924  *
 925  * RAMROD_CMD_ID_ETH_UPDATE
 926  *   Used to update the state of the leading connection, usually to udpate
 927  *   the RSS indirection table.  Completes on the RCQ of the leading
 928  *   connection. (Not currently used under FreeBSD until OS support becomes
 929  *   available.)
 930  *
 931  * RAMROD_CMD_ID_ETH_HALT
 932  *   Used when tearing down a connection prior to driver unload.  Completes
 933  *   on the RCQ of the multi-queue/RSS connection being torn down.  Don't
 934  *   use this on the leading connection.
 935  *
 936  * RAMROD_CMD_ID_ETH_SET_MAC
 937  *   Sets the Unicast/Broadcast/Multicast used by the port.  Completes on
 938  *   the RCQ of the leading connection.
 939  *
 940  * RAMROD_CMD_ID_ETH_CFC_DEL
 941  *   Used when tearing down a conneciton prior to driver unload.  Completes
 942  *   on the RCQ of the leading connection (since the current connection
 943  *   has been completely removed from controller memory).
 944  *
 945  * RAMROD_CMD_ID_ETH_PORT_DEL
 946  *   Used to tear down the leading connection prior to driver unload,
 947  *   typically fp[0].  Completes as an index increment of the CSTORM on the
 948  *   default status block.
 949  *
 950  * RAMROD_CMD_ID_ETH_FORWARD_SETUP
 951  *   Used for connection offload.  Completes on the RCQ of the multi-queue
 952  *   RSS connection that is being offloaded.  (Not currently used under
 953  *   FreeBSD.)
 954  *
 955  * There can only be one command pending per function.
 956  *
 957  * Returns:
 958  *   0 = Success, !0 = Failure.
 959  */
 960
 961 /* must be called under the spq lock */
 962 static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x_softc *sc)
 963 {
 964         struct eth_spe *next_spe = sc->spq_prod_bd;
 965
 966         if (sc->spq_prod_bd == sc->spq_last_bd) {
 967                 /* wrap back to the first eth_spq */
 968                 sc->spq_prod_bd = sc->spq;
 969                 sc->spq_prod_idx = 0;
 970         } else {
 971                 sc->spq_prod_bd++;
 972                 sc->spq_prod_idx++;
 973         }
 974
 975         return next_spe;
 976 }
 977
 978 /* must be called under the spq lock */
 979 static void bnx2x_sp_prod_update(struct bnx2x_softc *sc)
 980 {
 981         int func = SC_FUNC(sc);
 982
 983         /*
 984          * Make sure that BD data is updated before writing the producer.
 985          * BD data is written to the memory, the producer is read from the
 986          * memory, thus we need a full memory barrier to ensure the ordering.
 987          */
 988         mb();
 989
 990         REG_WR16(sc, (BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func)),
 991                  sc->spq_prod_idx);
 992
 993         mb();
 994 }
 995
 996 /**
 997  * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
 998  *
 999  * @cmd:      command to check
1000  * @cmd_type: command type
1001  */
1002 static int bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
1003 {
1004         if ((cmd_type == NONE_CONNECTION_TYPE) ||
1005             (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
1006             (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
1007             (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
1008             (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
1009             (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
1010             (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) {
1011                 return TRUE;
1012         } else {
1013                 return FALSE;
1014         }
1015 }
1016
1017 /**
1018  * bnx2x_sp_post - place a single command on an SP ring
1019  *
1020  * @sc:         driver handle
1021  * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
1022  * @cid:        SW CID the command is related to
1023  * @data_hi:    command private data address (high 32 bits)
1024  * @data_lo:    command private data address (low 32 bits)
1025  * @cmd_type:   command type (e.g. NONE, ETH)
1026  *
1027  * SP data is handled as if it's always an address pair, thus data fields are
1028  * not swapped to little endian in upper functions. Instead this function swaps
1029  * data as if it's two uint32 fields.
1030  */
1031 int
1032 bnx2x_sp_post(struct bnx2x_softc *sc, int command, int cid, uint32_t data_hi,
1033             uint32_t data_lo, int cmd_type)
1034 {
1035         struct eth_spe *spe;
1036         uint16_t type;
1037         int common;
1038
1039         common = bnx2x_is_contextless_ramrod(command, cmd_type);
1040
1041         if (common) {
1042                 if (!atomic_load_acq_long(&sc->eq_spq_left)) {
1043                         PMD_DRV_LOG(INFO, sc, "EQ ring is full!");
1044                         return -1;
1045                 }
1046         } else {
1047                 if (!atomic_load_acq_long(&sc->cq_spq_left)) {
1048                         PMD_DRV_LOG(INFO, sc, "SPQ ring is full!");
1049                         return -1;
1050                 }
1051         }
1052
1053         spe = bnx2x_sp_get_next(sc);
1054
1055         /* CID needs port number to be encoded int it */
1056         spe->hdr.conn_and_cmd_data =
1057             htole32((command << SPE_HDR_CMD_ID_SHIFT) | HW_CID(sc, cid));
1058
1059         type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
1060
1061         /* TBD: Check if it works for VFs */
1062         type |= ((SC_FUNC(sc) << SPE_HDR_FUNCTION_ID_SHIFT) &
1063                  SPE_HDR_FUNCTION_ID);
1064
1065         spe->hdr.type = htole16(type);
1066
1067         spe->data.update_data_addr.hi = htole32(data_hi);
1068         spe->data.update_data_addr.lo = htole32(data_lo);
1069
1070         /*
1071          * It's ok if the actual decrement is issued towards the memory
1072          * somewhere between the lock and unlock. Thus no more explict
1073          * memory barrier is needed.
1074          */
1075         if (common) {
1076                 atomic_subtract_acq_long(&sc->eq_spq_left, 1);
1077         } else {
1078                 atomic_subtract_acq_long(&sc->cq_spq_left, 1);
1079         }
1080
1081         PMD_DRV_LOG(DEBUG, sc,
1082                     "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x"
1083                     "data (%x:%x) type(0x%x) left (CQ, EQ) (%lx,%lx)",
1084                     sc->spq_prod_idx,
1085                     (uint32_t) U64_HI(sc->spq_dma.paddr),
1086                     (uint32_t) (U64_LO(sc->spq_dma.paddr) +
1087                                 (uint8_t *) sc->spq_prod_bd -
1088                                 (uint8_t *) sc->spq), command, common,
1089                     HW_CID(sc, cid), data_hi, data_lo, type,
1090                     atomic_load_acq_long(&sc->cq_spq_left),
1091                     atomic_load_acq_long(&sc->eq_spq_left));
1092
1093         /* RAMROD completion is processed in bnx2x_intr_legacy()
1094          * which can run from different contexts.
1095          * Ask bnx2x_intr_intr() to process RAMROD
1096          * completion whenever it gets scheduled.
1097          */
1098         rte_atomic32_set(&sc->scan_fp, 1);
1099         bnx2x_sp_prod_update(sc);
1100
1101         return 0;
1102 }
1103
1104 static void bnx2x_drv_pulse(struct bnx2x_softc *sc)
1105 {
1106         SHMEM_WR(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb,
1107                  sc->fw_drv_pulse_wr_seq);
1108 }
1109
1110 static int bnx2x_tx_queue_has_work(const struct bnx2x_fastpath *fp)
1111 {
1112         uint16_t hw_cons;
1113         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1114
1115         if (unlikely(!txq)) {
1116                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1117                 return 0;
1118         }
1119
1120         mb();                   /* status block fields can change */
1121         hw_cons = le16toh(*fp->tx_cons_sb);
1122         return hw_cons != txq->tx_pkt_head;
1123 }
1124
1125 static uint8_t bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
1126 {
1127         /* expand this for multi-cos if ever supported */
1128         return bnx2x_tx_queue_has_work(fp);
1129 }
1130
1131 static int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
1132 {
1133         uint16_t rx_cq_cons_sb;
1134         struct bnx2x_rx_queue *rxq;
1135         rxq = fp->sc->rx_queues[fp->index];
1136         if (unlikely(!rxq)) {
1137                 PMD_RX_LOG(ERR, "ERROR: RX queue is NULL");
1138                 return 0;
1139         }
1140
1141         mb();                   /* status block fields can change */
1142         rx_cq_cons_sb = le16toh(*fp->rx_cq_cons_sb);
1143         if (unlikely((rx_cq_cons_sb & MAX_RCQ_ENTRIES(rxq)) ==
1144                      MAX_RCQ_ENTRIES(rxq)))
1145                 rx_cq_cons_sb++;
1146
1147         PMD_RX_LOG(DEBUG, "hw CQ cons = %d, sw CQ cons = %d",
1148                    rx_cq_cons_sb, rxq->rx_cq_head);
1149
1150         return rxq->rx_cq_head != rx_cq_cons_sb;
1151 }
1152
1153 static void
1154 bnx2x_sp_event(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
1155              union eth_rx_cqe *rr_cqe)
1156 {
1157         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1158         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1159         enum ecore_queue_cmd drv_cmd = ECORE_Q_CMD_MAX;
1160         struct ecore_queue_sp_obj *q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
1161
1162         PMD_DRV_LOG(DEBUG, sc,
1163                     "fp=%d cid=%d got ramrod #%d state is %x type is %d",
1164                     fp->index, cid, command, sc->state,
1165                     rr_cqe->ramrod_cqe.ramrod_type);
1166
1167         switch (command) {
1168         case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1169                 PMD_DRV_LOG(DEBUG, sc, "got UPDATE ramrod. CID %d", cid);
1170                 drv_cmd = ECORE_Q_CMD_UPDATE;
1171                 break;
1172
1173         case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1174                 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] setup ramrod", cid);
1175                 drv_cmd = ECORE_Q_CMD_SETUP;
1176                 break;
1177
1178         case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1179                 PMD_DRV_LOG(DEBUG, sc,
1180                             "got MULTI[%d] tx-only setup ramrod", cid);
1181                 drv_cmd = ECORE_Q_CMD_SETUP_TX_ONLY;
1182                 break;
1183
1184         case (RAMROD_CMD_ID_ETH_HALT):
1185                 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] halt ramrod", cid);
1186                 drv_cmd = ECORE_Q_CMD_HALT;
1187                 break;
1188
1189         case (RAMROD_CMD_ID_ETH_TERMINATE):
1190                 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] teminate ramrod", cid);
1191                 drv_cmd = ECORE_Q_CMD_TERMINATE;
1192                 break;
1193
1194         case (RAMROD_CMD_ID_ETH_EMPTY):
1195                 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] empty ramrod", cid);
1196                 drv_cmd = ECORE_Q_CMD_EMPTY;
1197                 break;
1198
1199         default:
1200                 PMD_DRV_LOG(DEBUG, sc,
1201                             "ERROR: unexpected MC reply (%d)"
1202                             "on fp[%d]", command, fp->index);
1203                 return;
1204         }
1205
1206         if ((drv_cmd != ECORE_Q_CMD_MAX) &&
1207             q_obj->complete_cmd(sc, q_obj, drv_cmd)) {
1208                 /*
1209                  * q_obj->complete_cmd() failure means that this was
1210                  * an unexpected completion.
1211                  *
1212                  * In this case we don't want to increase the sc->spq_left
1213                  * because apparently we haven't sent this command the first
1214                  * place.
1215                  */
1216                 // rte_panic("Unexpected SP completion");
1217                 return;
1218         }
1219
1220         atomic_add_acq_long(&sc->cq_spq_left, 1);
1221
1222         PMD_DRV_LOG(DEBUG, sc, "sc->cq_spq_left 0x%lx",
1223                     atomic_load_acq_long(&sc->cq_spq_left));
1224 }
1225
1226 static uint8_t bnx2x_rxeof(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
1227 {
1228         struct bnx2x_rx_queue *rxq;
1229         uint16_t bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
1230         uint16_t hw_cq_cons, sw_cq_cons, sw_cq_prod;
1231
1232         rte_spinlock_lock(&(fp)->rx_mtx);
1233
1234         rxq = sc->rx_queues[fp->index];
1235         if (!rxq) {
1236                 PMD_RX_LOG(ERR, "RX queue %d is NULL", fp->index);
1237                 rte_spinlock_unlock(&(fp)->rx_mtx);
1238                 return 0;
1239         }
1240
1241         /* CQ "next element" is of the size of the regular element */
1242         hw_cq_cons = le16toh(*fp->rx_cq_cons_sb);
1243         if (unlikely((hw_cq_cons & USABLE_RCQ_ENTRIES_PER_PAGE) ==
1244                      USABLE_RCQ_ENTRIES_PER_PAGE)) {
1245                 hw_cq_cons++;
1246         }
1247
1248         bd_cons = rxq->rx_bd_head;
1249         bd_prod = rxq->rx_bd_tail;
1250         bd_prod_fw = bd_prod;
1251         sw_cq_cons = rxq->rx_cq_head;
1252         sw_cq_prod = rxq->rx_cq_tail;
1253
1254         /*
1255          * Memory barrier necessary as speculative reads of the rx
1256          * buffer can be ahead of the index in the status block
1257          */
1258         rmb();
1259
1260         while (sw_cq_cons != hw_cq_cons) {
1261                 union eth_rx_cqe *cqe;
1262                 struct eth_fast_path_rx_cqe *cqe_fp;
1263                 uint8_t cqe_fp_flags;
1264                 enum eth_rx_cqe_type cqe_fp_type;
1265
1266                 comp_ring_cons = RCQ_ENTRY(sw_cq_cons, rxq);
1267                 bd_prod = RX_BD(bd_prod, rxq);
1268                 bd_cons = RX_BD(bd_cons, rxq);
1269
1270                 cqe = &rxq->cq_ring[comp_ring_cons];
1271                 cqe_fp = &cqe->fast_path_cqe;
1272                 cqe_fp_flags = cqe_fp->type_error_flags;
1273                 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
1274
1275                 /* is this a slowpath msg? */
1276                 if (CQE_TYPE_SLOW(cqe_fp_type)) {
1277                         bnx2x_sp_event(sc, fp, cqe);
1278                         goto next_cqe;
1279                 }
1280
1281                 /* is this an error packet? */
1282                 if (unlikely(cqe_fp_flags &
1283                              ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG)) {
1284                         PMD_RX_LOG(DEBUG, "flags 0x%x rx packet %u",
1285                                    cqe_fp_flags, sw_cq_cons);
1286                         goto next_rx;
1287                 }
1288
1289                 PMD_RX_LOG(DEBUG, "Dropping fastpath called from attn poller!");
1290
1291 next_rx:
1292                 bd_cons = NEXT_RX_BD(bd_cons);
1293                 bd_prod = NEXT_RX_BD(bd_prod);
1294                 bd_prod_fw = NEXT_RX_BD(bd_prod_fw);
1295
1296 next_cqe:
1297                 sw_cq_prod = NEXT_RCQ_IDX(sw_cq_prod);
1298                 sw_cq_cons = NEXT_RCQ_IDX(sw_cq_cons);
1299
1300         }                       /* while work to do */
1301
1302         rxq->rx_bd_head = bd_cons;
1303         rxq->rx_bd_tail = bd_prod_fw;
1304         rxq->rx_cq_head = sw_cq_cons;
1305         rxq->rx_cq_tail = sw_cq_prod;
1306
1307         PMD_RX_LOG(DEBUG, "BD prod = %d, sw CQ prod = %d",
1308                    bd_prod_fw, sw_cq_prod);
1309
1310         /* Update producers */
1311         bnx2x_update_rx_prod(sc, fp, bd_prod_fw, sw_cq_prod);
1312
1313         rte_spinlock_unlock(&(fp)->rx_mtx);
1314
1315         return sw_cq_cons != hw_cq_cons;
1316 }
1317
1318 static uint16_t
1319 bnx2x_free_tx_pkt(__rte_unused struct bnx2x_fastpath *fp, struct bnx2x_tx_queue *txq,
1320                 uint16_t pkt_idx, uint16_t bd_idx)
1321 {
1322         struct eth_tx_start_bd *tx_start_bd =
1323             &txq->tx_ring[TX_BD(bd_idx, txq)].start_bd;
1324         uint16_t nbd = rte_le_to_cpu_16(tx_start_bd->nbd);
1325         struct rte_mbuf *tx_mbuf = txq->sw_ring[TX_BD(pkt_idx, txq)];
1326
1327         if (likely(tx_mbuf != NULL)) {
1328                 rte_pktmbuf_free_seg(tx_mbuf);
1329         } else {
1330                 PMD_RX_LOG(ERR, "fp[%02d] lost mbuf %lu",
1331                            fp->index, (unsigned long)TX_BD(pkt_idx, txq));
1332         }
1333
1334         txq->sw_ring[TX_BD(pkt_idx, txq)] = NULL;
1335         txq->nb_tx_avail += nbd;
1336
1337         while (nbd--)
1338                 bd_idx = NEXT_TX_BD(bd_idx);
1339
1340         return bd_idx;
1341 }
1342
1343 /* processes transmit completions */
1344 uint8_t bnx2x_txeof(__rte_unused struct bnx2x_softc * sc, struct bnx2x_fastpath * fp)
1345 {
1346         uint16_t bd_cons, hw_cons, sw_cons;
1347         __rte_unused uint16_t tx_bd_avail;
1348
1349         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1350
1351         if (unlikely(!txq)) {
1352                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1353                 return 0;
1354         }
1355
1356         bd_cons = txq->tx_bd_head;
1357         hw_cons = rte_le_to_cpu_16(*fp->tx_cons_sb);
1358         sw_cons = txq->tx_pkt_head;
1359
1360         while (sw_cons != hw_cons) {
1361                 bd_cons = bnx2x_free_tx_pkt(fp, txq, sw_cons, bd_cons);
1362                 sw_cons++;
1363         }
1364
1365         txq->tx_pkt_head = sw_cons;
1366         txq->tx_bd_head = bd_cons;
1367
1368         tx_bd_avail = txq->nb_tx_avail;
1369
1370         PMD_TX_LOG(DEBUG, "fp[%02d] avail=%u cons_sb=%u, "
1371                    "pkt_head=%u pkt_tail=%u bd_head=%u bd_tail=%u",
1372                    fp->index, tx_bd_avail, hw_cons,
1373                    txq->tx_pkt_head, txq->tx_pkt_tail,
1374                    txq->tx_bd_head, txq->tx_bd_tail);
1375         return TRUE;
1376 }
1377
1378 static void bnx2x_drain_tx_queues(struct bnx2x_softc *sc)
1379 {
1380         struct bnx2x_fastpath *fp;
1381         int i, count;
1382
1383         /* wait until all TX fastpath tasks have completed */
1384         for (i = 0; i < sc->num_queues; i++) {
1385                 fp = &sc->fp[i];
1386
1387                 count = 1000;
1388
1389                 while (bnx2x_has_tx_work(fp)) {
1390                         bnx2x_txeof(sc, fp);
1391
1392                         if (count == 0) {
1393                                 PMD_TX_LOG(ERR,
1394                                            "Timeout waiting for fp[%d] "
1395                                            "transmits to complete!", i);
1396                                 rte_panic("tx drain failure");
1397                                 return;
1398                         }
1399
1400                         count--;
1401                         DELAY(1000);
1402                         rmb();
1403                 }
1404         }
1405
1406         return;
1407 }
1408
1409 static int
1410 bnx2x_del_all_macs(struct bnx2x_softc *sc, struct ecore_vlan_mac_obj *mac_obj,
1411                  int mac_type, uint8_t wait_for_comp)
1412 {
1413         uint32_t ramrod_flags = 0, vlan_mac_flags = 0;
1414         int rc;
1415
1416         /* wait for completion of requested */
1417         if (wait_for_comp) {
1418                 rte_bit_relaxed_set32(RAMROD_COMP_WAIT, &ramrod_flags);
1419         }
1420
1421         /* Set the mac type of addresses we want to clear */
1422         rte_bit_relaxed_set32(mac_type, &vlan_mac_flags);
1423
1424         rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1425         if (rc < 0)
1426                 PMD_DRV_LOG(ERR, sc, "Failed to delete MACs (%d)", rc);
1427
1428         return rc;
1429 }
1430
1431 static int
1432 bnx2x_fill_accept_flags(struct bnx2x_softc *sc, uint32_t rx_mode,
1433                         uint32_t *rx_accept_flags, uint32_t *tx_accept_flags)
1434 {
1435         /* Clear the flags first */
1436         *rx_accept_flags = 0;
1437         *tx_accept_flags = 0;
1438
1439         switch (rx_mode) {
1440         case BNX2X_RX_MODE_NONE:
1441                 /*
1442                  * 'drop all' supersedes any accept flags that may have been
1443                  * passed to the function.
1444                  */
1445                 break;
1446
1447         case BNX2X_RX_MODE_NORMAL:
1448                 rte_bit_relaxed_set32(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1449                 rte_bit_relaxed_set32(ECORE_ACCEPT_MULTICAST, rx_accept_flags);
1450                 rte_bit_relaxed_set32(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1451
1452                 /* internal switching mode */
1453                 rte_bit_relaxed_set32(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1454                 rte_bit_relaxed_set32(ECORE_ACCEPT_MULTICAST, tx_accept_flags);
1455                 rte_bit_relaxed_set32(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1456
1457                 break;
1458
1459         case BNX2X_RX_MODE_ALLMULTI:
1460                 rte_bit_relaxed_set32(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1461                 rte_bit_relaxed_set32(ECORE_ACCEPT_ALL_MULTICAST,
1462                                       rx_accept_flags);
1463                 rte_bit_relaxed_set32(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1464
1465                 /* internal switching mode */
1466                 rte_bit_relaxed_set32(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1467                 rte_bit_relaxed_set32(ECORE_ACCEPT_ALL_MULTICAST,
1468                                       tx_accept_flags);
1469                 rte_bit_relaxed_set32(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1470
1471                 break;
1472
1473         case BNX2X_RX_MODE_ALLMULTI_PROMISC:
1474         case BNX2X_RX_MODE_PROMISC:
1475                 /*
1476                  * According to deffinition of SI mode, iface in promisc mode
1477                  * should receive matched and unmatched (in resolution of port)
1478                  * unicast packets.
1479                  */
1480                 rte_bit_relaxed_set32(ECORE_ACCEPT_UNMATCHED, rx_accept_flags);
1481                 rte_bit_relaxed_set32(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1482                 rte_bit_relaxed_set32(ECORE_ACCEPT_ALL_MULTICAST,
1483                                       rx_accept_flags);
1484                 rte_bit_relaxed_set32(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1485
1486                 /* internal switching mode */
1487                 rte_bit_relaxed_set32(ECORE_ACCEPT_ALL_MULTICAST,
1488                                       tx_accept_flags);
1489                 rte_bit_relaxed_set32(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1490
1491                 if (IS_MF_SI(sc)) {
1492                         rte_bit_relaxed_set32(ECORE_ACCEPT_ALL_UNICAST,
1493                                         tx_accept_flags);
1494                 } else {
1495                         rte_bit_relaxed_set32(ECORE_ACCEPT_UNICAST,
1496                                               tx_accept_flags);
1497                 }
1498
1499                 break;
1500
1501         default:
1502                 PMD_RX_LOG(ERR, "Unknown rx_mode (%d)", rx_mode);
1503                 return -1;
1504         }
1505
1506         /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
1507         if (rx_mode != BNX2X_RX_MODE_NONE) {
1508                 rte_bit_relaxed_set32(ECORE_ACCEPT_ANY_VLAN, rx_accept_flags);
1509                 rte_bit_relaxed_set32(ECORE_ACCEPT_ANY_VLAN, tx_accept_flags);
1510         }
1511
1512         return 0;
1513 }
1514
1515 static int
1516 bnx2x_set_q_rx_mode(struct bnx2x_softc *sc, uint8_t cl_id,
1517                   unsigned long rx_mode_flags,
1518                   unsigned long rx_accept_flags,
1519                   unsigned long tx_accept_flags, unsigned long ramrod_flags)
1520 {
1521         struct ecore_rx_mode_ramrod_params ramrod_param;
1522         int rc;
1523
1524         memset(&ramrod_param, 0, sizeof(ramrod_param));
1525
1526         /* Prepare ramrod parameters */
1527         ramrod_param.cid = 0;
1528         ramrod_param.cl_id = cl_id;
1529         ramrod_param.rx_mode_obj = &sc->rx_mode_obj;
1530         ramrod_param.func_id = SC_FUNC(sc);
1531
1532         ramrod_param.pstate = &sc->sp_state;
1533         ramrod_param.state = ECORE_FILTER_RX_MODE_PENDING;
1534
1535         ramrod_param.rdata = BNX2X_SP(sc, rx_mode_rdata);
1536         ramrod_param.rdata_mapping =
1537             (rte_iova_t)BNX2X_SP_MAPPING(sc, rx_mode_rdata),
1538             rte_bit_relaxed_set32(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
1539
1540         ramrod_param.ramrod_flags = ramrod_flags;
1541         ramrod_param.rx_mode_flags = rx_mode_flags;
1542
1543         ramrod_param.rx_accept_flags = rx_accept_flags;
1544         ramrod_param.tx_accept_flags = tx_accept_flags;
1545
1546         rc = ecore_config_rx_mode(sc, &ramrod_param);
1547         if (rc < 0) {
1548                 PMD_RX_LOG(ERR, "Set rx_mode %d failed", sc->rx_mode);
1549                 return rc;
1550         }
1551
1552         return 0;
1553 }
1554
1555 int bnx2x_set_storm_rx_mode(struct bnx2x_softc *sc)
1556 {
1557         uint32_t rx_mode_flags = 0, ramrod_flags = 0;
1558         uint32_t rx_accept_flags = 0, tx_accept_flags = 0;
1559         int rc;
1560
1561         rc = bnx2x_fill_accept_flags(sc, sc->rx_mode, &rx_accept_flags,
1562                                    &tx_accept_flags);
1563         if (rc) {
1564                 return rc;
1565         }
1566
1567         rte_bit_relaxed_set32(RAMROD_RX, &ramrod_flags);
1568         rte_bit_relaxed_set32(RAMROD_TX, &ramrod_flags);
1569         rte_bit_relaxed_set32(RAMROD_COMP_WAIT, &ramrod_flags);
1570
1571         return bnx2x_set_q_rx_mode(sc, sc->fp[0].cl_id, rx_mode_flags,
1572                                  rx_accept_flags, tx_accept_flags,
1573                                  ramrod_flags);
1574 }
1575
1576 /* returns the "mcp load_code" according to global load_count array */
1577 static int bnx2x_nic_load_no_mcp(struct bnx2x_softc *sc)
1578 {
1579         int path = SC_PATH(sc);
1580         int port = SC_PORT(sc);
1581
1582         PMD_DRV_LOG(INFO, sc, "NO MCP - load counts[%d]      %d, %d, %d",
1583                     path, load_count[path][0], load_count[path][1],
1584                     load_count[path][2]);
1585
1586         load_count[path][0]++;
1587         load_count[path][1 + port]++;
1588         PMD_DRV_LOG(INFO, sc, "NO MCP - new load counts[%d]  %d, %d, %d",
1589                     path, load_count[path][0], load_count[path][1],
1590                     load_count[path][2]);
1591         if (load_count[path][0] == 1)
1592                 return FW_MSG_CODE_DRV_LOAD_COMMON;
1593         else if (load_count[path][1 + port] == 1)
1594                 return FW_MSG_CODE_DRV_LOAD_PORT;
1595         else
1596                 return FW_MSG_CODE_DRV_LOAD_FUNCTION;
1597 }
1598
1599 /* returns the "mcp load_code" according to global load_count array */
1600 static int bnx2x_nic_unload_no_mcp(struct bnx2x_softc *sc)
1601 {
1602         int port = SC_PORT(sc);
1603         int path = SC_PATH(sc);
1604
1605         PMD_DRV_LOG(INFO, sc, "NO MCP - load counts[%d]      %d, %d, %d",
1606                     path, load_count[path][0], load_count[path][1],
1607                     load_count[path][2]);
1608         load_count[path][0]--;
1609         load_count[path][1 + port]--;
1610         PMD_DRV_LOG(INFO, sc, "NO MCP - new load counts[%d]  %d, %d, %d",
1611                     path, load_count[path][0], load_count[path][1],
1612                     load_count[path][2]);
1613         if (load_count[path][0] == 0) {
1614                 return FW_MSG_CODE_DRV_UNLOAD_COMMON;
1615         } else if (load_count[path][1 + port] == 0) {
1616                 return FW_MSG_CODE_DRV_UNLOAD_PORT;
1617         } else {
1618                 return FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
1619         }
1620 }
1621
1622 /* request unload mode from the MCP: COMMON, PORT or FUNCTION */
1623 static uint32_t bnx2x_send_unload_req(struct bnx2x_softc *sc, int unload_mode)
1624 {
1625         uint32_t reset_code = 0;
1626
1627         /* Select the UNLOAD request mode */
1628         if (unload_mode == UNLOAD_NORMAL) {
1629                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1630         } else {
1631                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1632         }
1633
1634         /* Send the request to the MCP */
1635         if (!BNX2X_NOMCP(sc)) {
1636                 reset_code = bnx2x_fw_command(sc, reset_code, 0);
1637         } else {
1638                 reset_code = bnx2x_nic_unload_no_mcp(sc);
1639         }
1640
1641         return reset_code;
1642 }
1643
1644 /* send UNLOAD_DONE command to the MCP */
1645 static void bnx2x_send_unload_done(struct bnx2x_softc *sc, uint8_t keep_link)
1646 {
1647         uint32_t reset_param =
1648             keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
1649
1650         /* Report UNLOAD_DONE to MCP */
1651         if (!BNX2X_NOMCP(sc)) {
1652                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
1653         }
1654 }
1655
1656 static int bnx2x_func_wait_started(struct bnx2x_softc *sc)
1657 {
1658         int tout = 50;
1659
1660         if (!sc->port.pmf) {
1661                 return 0;
1662         }
1663
1664         /*
1665          * (assumption: No Attention from MCP at this stage)
1666          * PMF probably in the middle of TX disable/enable transaction
1667          * 1. Sync IRS for default SB
1668          * 2. Sync SP queue - this guarantees us that attention handling started
1669          * 3. Wait, that TX disable/enable transaction completes
1670          *
1671          * 1+2 guarantee that if DCBX attention was scheduled it already changed
1672          * pending bit of transaction from STARTED-->TX_STOPPED, if we already
1673          * received completion for the transaction the state is TX_STOPPED.
1674          * State will return to STARTED after completion of TX_STOPPED-->STARTED
1675          * transaction.
1676          */
1677
1678         while (ecore_func_get_state(sc, &sc->func_obj) !=
1679                ECORE_F_STATE_STARTED && tout--) {
1680                 DELAY(20000);
1681         }
1682
1683         if (ecore_func_get_state(sc, &sc->func_obj) != ECORE_F_STATE_STARTED) {
1684                 /*
1685                  * Failed to complete the transaction in a "good way"
1686                  * Force both transactions with CLR bit.
1687                  */
1688                 struct ecore_func_state_params func_params = { NULL };
1689
1690                 PMD_DRV_LOG(NOTICE, sc, "Unexpected function state! "
1691                             "Forcing STARTED-->TX_STOPPED-->STARTED");
1692
1693                 func_params.f_obj = &sc->func_obj;
1694                 rte_bit_relaxed_set32(RAMROD_DRV_CLR_ONLY,
1695                                       &func_params.ramrod_flags);
1696
1697                 /* STARTED-->TX_STOPPED */
1698                 func_params.cmd = ECORE_F_CMD_TX_STOP;
1699                 ecore_func_state_change(sc, &func_params);
1700
1701                 /* TX_STOPPED-->STARTED */
1702                 func_params.cmd = ECORE_F_CMD_TX_START;
1703                 return ecore_func_state_change(sc, &func_params);
1704         }
1705
1706         return 0;
1707 }
1708
1709 static int bnx2x_stop_queue(struct bnx2x_softc *sc, int index)
1710 {
1711         struct bnx2x_fastpath *fp = &sc->fp[index];
1712         struct ecore_queue_state_params q_params = { NULL };
1713         int rc;
1714
1715         PMD_DRV_LOG(DEBUG, sc, "stopping queue %d cid %d", index, fp->index);
1716
1717         q_params.q_obj = &sc->sp_objs[fp->index].q_obj;
1718         /* We want to wait for completion in this context */
1719         rte_bit_relaxed_set32(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
1720
1721         /* Stop the primary connection: */
1722
1723         /* ...halt the connection */
1724         q_params.cmd = ECORE_Q_CMD_HALT;
1725         rc = ecore_queue_state_change(sc, &q_params);
1726         if (rc) {
1727                 return rc;
1728         }
1729
1730         /* ...terminate the connection */
1731         q_params.cmd = ECORE_Q_CMD_TERMINATE;
1732         memset(&q_params.params.terminate, 0,
1733                sizeof(q_params.params.terminate));
1734         q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
1735         rc = ecore_queue_state_change(sc, &q_params);
1736         if (rc) {
1737                 return rc;
1738         }
1739
1740         /* ...delete cfc entry */
1741         q_params.cmd = ECORE_Q_CMD_CFC_DEL;
1742         memset(&q_params.params.cfc_del, 0, sizeof(q_params.params.cfc_del));
1743         q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
1744         return ecore_queue_state_change(sc, &q_params);
1745 }
1746
1747 /* wait for the outstanding SP commands */
1748 static uint8_t bnx2x_wait_sp_comp(struct bnx2x_softc *sc, uint32_t mask)
1749 {
1750         uint32_t tmp;
1751         int tout = 5000;        /* wait for 5 secs tops */
1752
1753         while (tout--) {
1754                 mb();
1755                 if (!(atomic_load_acq_int(&sc->sp_state) & mask))
1756                         return TRUE;
1757
1758                 DELAY(1000);
1759         }
1760
1761         mb();
1762
1763         tmp = atomic_load_acq_int(&sc->sp_state);
1764         if (tmp & mask) {
1765                 PMD_DRV_LOG(INFO, sc, "Filtering completion timed out: "
1766                             "sp_state 0x%x, mask 0x%x", tmp, mask);
1767                 return FALSE;
1768         }
1769
1770         return FALSE;
1771 }
1772
1773 static int bnx2x_func_stop(struct bnx2x_softc *sc)
1774 {
1775         struct ecore_func_state_params func_params = { NULL };
1776         int rc;
1777
1778         /* prepare parameters for function state transitions */
1779         rte_bit_relaxed_set32(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1780         func_params.f_obj = &sc->func_obj;
1781         func_params.cmd = ECORE_F_CMD_STOP;
1782
1783         /*
1784          * Try to stop the function the 'good way'. If it fails (in case
1785          * of a parity error during bnx2x_chip_cleanup()) and we are
1786          * not in a debug mode, perform a state transaction in order to
1787          * enable further HW_RESET transaction.
1788          */
1789         rc = ecore_func_state_change(sc, &func_params);
1790         if (rc) {
1791                 PMD_DRV_LOG(NOTICE, sc, "FUNC_STOP ramrod failed. "
1792                             "Running a dry transaction");
1793                 rte_bit_relaxed_set32(RAMROD_DRV_CLR_ONLY,
1794                                       &func_params.ramrod_flags);
1795                 return ecore_func_state_change(sc, &func_params);
1796         }
1797
1798         return 0;
1799 }
1800
1801 static int bnx2x_reset_hw(struct bnx2x_softc *sc, uint32_t load_code)
1802 {
1803         struct ecore_func_state_params func_params = { NULL };
1804
1805         /* Prepare parameters for function state transitions */
1806         rte_bit_relaxed_set32(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1807
1808         func_params.f_obj = &sc->func_obj;
1809         func_params.cmd = ECORE_F_CMD_HW_RESET;
1810
1811         func_params.params.hw_init.load_phase = load_code;
1812
1813         return ecore_func_state_change(sc, &func_params);
1814 }
1815
1816 static void bnx2x_int_disable_sync(struct bnx2x_softc *sc, int disable_hw)
1817 {
1818         if (disable_hw) {
1819                 /* prevent the HW from sending interrupts */
1820                 bnx2x_int_disable(sc);
1821         }
1822 }
1823
1824 static void
1825 bnx2x_chip_cleanup(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1826 {
1827         int port = SC_PORT(sc);
1828         struct ecore_mcast_ramrod_params rparam = { NULL };
1829         uint32_t reset_code;
1830         int i, rc = 0;
1831
1832         bnx2x_drain_tx_queues(sc);
1833
1834         /* give HW time to discard old tx messages */
1835         DELAY(1000);
1836
1837         /* Clean all ETH MACs */
1838         rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_ETH_MAC,
1839                               FALSE);
1840         if (rc < 0) {
1841                 PMD_DRV_LOG(NOTICE, sc,
1842                             "Failed to delete all ETH MACs (%d)", rc);
1843         }
1844
1845         /* Clean up UC list  */
1846         rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_UC_LIST_MAC,
1847                               TRUE);
1848         if (rc < 0) {
1849                 PMD_DRV_LOG(NOTICE, sc,
1850                             "Failed to delete UC MACs list (%d)", rc);
1851         }
1852
1853         /* Disable LLH */
1854         REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
1855
1856         /* Set "drop all" to stop Rx */
1857
1858         /*
1859          * We need to take the if_maddr_lock() here in order to prevent
1860          * a race between the completion code and this code.
1861          */
1862
1863         if (rte_bit_relaxed_get32(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state))
1864                 rte_bit_relaxed_set32(ECORE_FILTER_RX_MODE_SCHED,
1865                                       &sc->sp_state);
1866         else
1867                 bnx2x_set_storm_rx_mode(sc);
1868
1869         /* Clean up multicast configuration */
1870         rparam.mcast_obj = &sc->mcast_obj;
1871         rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1872         if (rc < 0) {
1873                 PMD_DRV_LOG(NOTICE, sc,
1874                             "Failed to send DEL MCAST command (%d)", rc);
1875         }
1876
1877         /*
1878          * Send the UNLOAD_REQUEST to the MCP. This will return if
1879          * this function should perform FUNCTION, PORT, or COMMON HW
1880          * reset.
1881          */
1882         reset_code = bnx2x_send_unload_req(sc, unload_mode);
1883
1884         /*
1885          * (assumption: No Attention from MCP at this stage)
1886          * PMF probably in the middle of TX disable/enable transaction
1887          */
1888         rc = bnx2x_func_wait_started(sc);
1889         if (rc) {
1890                 PMD_DRV_LOG(NOTICE, sc, "bnx2x_func_wait_started failed");
1891         }
1892
1893         /*
1894          * Close multi and leading connections
1895          * Completions for ramrods are collected in a synchronous way
1896          */
1897         for (i = 0; i < sc->num_queues; i++) {
1898                 if (bnx2x_stop_queue(sc, i)) {
1899                         goto unload_error;
1900                 }
1901         }
1902
1903         /*
1904          * If SP settings didn't get completed so far - something
1905          * very wrong has happen.
1906          */
1907         if (!bnx2x_wait_sp_comp(sc, ~0x0U))
1908                 PMD_DRV_LOG(NOTICE, sc, "Common slow path ramrods got stuck!");
1909
1910 unload_error:
1911
1912         rc = bnx2x_func_stop(sc);
1913         if (rc) {
1914                 PMD_DRV_LOG(NOTICE, sc, "Function stop failed!");
1915         }
1916
1917         /* disable HW interrupts */
1918         bnx2x_int_disable_sync(sc, TRUE);
1919
1920         /* Reset the chip */
1921         rc = bnx2x_reset_hw(sc, reset_code);
1922         if (rc) {
1923                 PMD_DRV_LOG(NOTICE, sc, "Hardware reset failed");
1924         }
1925
1926         /* Report UNLOAD_DONE to MCP */
1927         bnx2x_send_unload_done(sc, keep_link);
1928 }
1929
1930 static void bnx2x_disable_close_the_gate(struct bnx2x_softc *sc)
1931 {
1932         uint32_t val;
1933
1934         PMD_DRV_LOG(DEBUG, sc, "Disabling 'close the gates'");
1935
1936         val = REG_RD(sc, MISC_REG_AEU_GENERAL_MASK);
1937         val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
1938                  MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
1939         REG_WR(sc, MISC_REG_AEU_GENERAL_MASK, val);
1940 }
1941
1942 /*
1943  * Cleans the object that have internal lists without sending
1944  * ramrods. Should be run when interrutps are disabled.
1945  */
1946 static void bnx2x_squeeze_objects(struct bnx2x_softc *sc)
1947 {
1948         uint32_t ramrod_flags = 0, vlan_mac_flags = 0;
1949         struct ecore_mcast_ramrod_params rparam = { NULL };
1950         struct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj;
1951         int rc;
1952
1953         /* Cleanup MACs' object first... */
1954
1955         /* Wait for completion of requested */
1956         rte_bit_relaxed_set32(RAMROD_COMP_WAIT, &ramrod_flags);
1957         /* Perform a dry cleanup */
1958         rte_bit_relaxed_set32(RAMROD_DRV_CLR_ONLY, &ramrod_flags);
1959
1960         /* Clean ETH primary MAC */
1961         rte_bit_relaxed_set32(ECORE_ETH_MAC, &vlan_mac_flags);
1962         rc = mac_obj->delete_all(sc, &sc->sp_objs->mac_obj, &vlan_mac_flags,
1963                                  &ramrod_flags);
1964         if (rc != 0) {
1965                 PMD_DRV_LOG(NOTICE, sc, "Failed to clean ETH MACs (%d)", rc);
1966         }
1967
1968         /* Cleanup UC list */
1969         vlan_mac_flags = 0;
1970         rte_bit_relaxed_set32(ECORE_UC_LIST_MAC, &vlan_mac_flags);
1971         rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1972         if (rc != 0) {
1973                 PMD_DRV_LOG(NOTICE, sc,
1974                             "Failed to clean UC list MACs (%d)", rc);
1975         }
1976
1977         /* Now clean mcast object... */
1978
1979         rparam.mcast_obj = &sc->mcast_obj;
1980         rte_bit_relaxed_set32(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags);
1981
1982         /* Add a DEL command... */
1983         rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1984         if (rc < 0) {
1985                 PMD_DRV_LOG(NOTICE, sc,
1986                             "Failed to send DEL MCAST command (%d)", rc);
1987         }
1988
1989         /* now wait until all pending commands are cleared */
1990
1991         rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
1992         while (rc != 0) {
1993                 if (rc < 0) {
1994                         PMD_DRV_LOG(NOTICE, sc,
1995                                     "Failed to clean MCAST object (%d)", rc);
1996                         return;
1997                 }
1998
1999                 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
2000         }
2001 }
2002
2003 /* stop the controller */
2004 __rte_noinline
2005 int
2006 bnx2x_nic_unload(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
2007 {
2008         uint8_t global = FALSE;
2009         uint32_t val;
2010
2011         PMD_INIT_FUNC_TRACE(sc);
2012
2013         PMD_DRV_LOG(DEBUG, sc, "Starting NIC unload...");
2014
2015         /* mark driver as unloaded in shmem2 */
2016         if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
2017                 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
2018                 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
2019                           val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
2020         }
2021
2022         if (IS_PF(sc) && sc->recovery_state != BNX2X_RECOVERY_DONE &&
2023             (sc->state == BNX2X_STATE_CLOSED || sc->state == BNX2X_STATE_ERROR)) {
2024                 /*
2025                  * We can get here if the driver has been unloaded
2026                  * during parity error recovery and is either waiting for a
2027                  * leader to complete or for other functions to unload and
2028                  * then ifconfig down has been issued. In this case we want to
2029                  * unload and let other functions to complete a recovery
2030                  * process.
2031                  */
2032                 sc->recovery_state = BNX2X_RECOVERY_DONE;
2033                 sc->is_leader = 0;
2034                 bnx2x_release_leader_lock(sc);
2035                 mb();
2036
2037                 PMD_DRV_LOG(NOTICE, sc, "Can't unload in closed or error state");
2038                 return -1;
2039         }
2040
2041         /*
2042          * Nothing to do during unload if previous bnx2x_nic_load()
2043          * did not completed successfully - all resourses are released.
2044          */
2045         if ((sc->state == BNX2X_STATE_CLOSED) || (sc->state == BNX2X_STATE_ERROR)) {
2046                 return 0;
2047         }
2048
2049         sc->state = BNX2X_STATE_CLOSING_WAITING_HALT;
2050         mb();
2051
2052         sc->rx_mode = BNX2X_RX_MODE_NONE;
2053         bnx2x_set_rx_mode(sc);
2054         mb();
2055
2056         if (IS_PF(sc)) {
2057                 /* set ALWAYS_ALIVE bit in shmem */
2058                 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2059
2060                 bnx2x_drv_pulse(sc);
2061
2062                 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2063                 bnx2x_save_statistics(sc);
2064         }
2065
2066         /* wait till consumers catch up with producers in all queues */
2067         bnx2x_drain_tx_queues(sc);
2068
2069         /* if VF indicate to PF this function is going down (PF will delete sp
2070          * elements and clear initializations
2071          */
2072         if (IS_VF(sc)) {
2073                 bnx2x_vf_unload(sc);
2074         } else if (unload_mode != UNLOAD_RECOVERY) {
2075                 /* if this is a normal/close unload need to clean up chip */
2076                 bnx2x_chip_cleanup(sc, unload_mode, keep_link);
2077         } else {
2078                 /* Send the UNLOAD_REQUEST to the MCP */
2079                 bnx2x_send_unload_req(sc, unload_mode);
2080
2081                 /*
2082                  * Prevent transactions to host from the functions on the
2083                  * engine that doesn't reset global blocks in case of global
2084                  * attention once gloabl blocks are reset and gates are opened
2085                  * (the engine which leader will perform the recovery
2086                  * last).
2087                  */
2088                 if (!CHIP_IS_E1x(sc)) {
2089                         bnx2x_pf_disable(sc);
2090                 }
2091
2092                 /* disable HW interrupts */
2093                 bnx2x_int_disable_sync(sc, TRUE);
2094
2095                 /* Report UNLOAD_DONE to MCP */
2096                 bnx2x_send_unload_done(sc, FALSE);
2097         }
2098
2099         /*
2100          * At this stage no more interrupts will arrive so we may safely clean
2101          * the queue'able objects here in case they failed to get cleaned so far.
2102          */
2103         if (IS_PF(sc)) {
2104                 bnx2x_squeeze_objects(sc);
2105         }
2106
2107         /* There should be no more pending SP commands at this stage */
2108         sc->sp_state = 0;
2109
2110         sc->port.pmf = 0;
2111
2112         if (IS_PF(sc)) {
2113                 bnx2x_free_mem(sc);
2114         }
2115
2116         /* free the host hardware/software hsi structures */
2117         bnx2x_free_hsi_mem(sc);
2118
2119         bnx2x_free_fw_stats_mem(sc);
2120
2121         sc->state = BNX2X_STATE_CLOSED;
2122
2123         /*
2124          * Check if there are pending parity attentions. If there are - set
2125          * RECOVERY_IN_PROGRESS.
2126          */
2127         if (IS_PF(sc) && bnx2x_chk_parity_attn(sc, &global, FALSE)) {
2128                 bnx2x_set_reset_in_progress(sc);
2129
2130                 /* Set RESET_IS_GLOBAL if needed */
2131                 if (global) {
2132                         bnx2x_set_reset_global(sc);
2133                 }
2134         }
2135
2136         /*
2137          * The last driver must disable a "close the gate" if there is no
2138          * parity attention or "process kill" pending.
2139          */
2140         if (IS_PF(sc) && !bnx2x_clear_pf_load(sc) &&
2141             bnx2x_reset_is_done(sc, SC_PATH(sc))) {
2142                 bnx2x_disable_close_the_gate(sc);
2143         }
2144
2145         PMD_DRV_LOG(DEBUG, sc, "Ended NIC unload");
2146
2147         return 0;
2148 }
2149
2150 /*
2151  * Encapsulte an mbuf cluster into the tx bd chain and makes the memory
2152  * visible to the controller.
2153  *
2154  * If an mbuf is submitted to this routine and cannot be given to the
2155  * controller (e.g. it has too many fragments) then the function may free
2156  * the mbuf and return to the caller.
2157  *
2158  * Returns:
2159  *     int: Number of TX BDs used for the mbuf
2160  *
2161  *   Note the side effect that an mbuf may be freed if it causes a problem.
2162  */
2163 int bnx2x_tx_encap(struct bnx2x_tx_queue *txq, struct rte_mbuf *m0)
2164 {
2165         struct eth_tx_start_bd *tx_start_bd;
2166         uint16_t bd_prod, pkt_prod;
2167         struct bnx2x_softc *sc;
2168         uint32_t nbds = 0;
2169
2170         sc = txq->sc;
2171         bd_prod = txq->tx_bd_tail;
2172         pkt_prod = txq->tx_pkt_tail;
2173
2174         txq->sw_ring[TX_BD(pkt_prod, txq)] = m0;
2175
2176         tx_start_bd = &txq->tx_ring[TX_BD(bd_prod, txq)].start_bd;
2177
2178         tx_start_bd->addr_lo =
2179             rte_cpu_to_le_32(U64_LO(rte_mbuf_data_iova(m0)));
2180         tx_start_bd->addr_hi =
2181             rte_cpu_to_le_32(U64_HI(rte_mbuf_data_iova(m0)));
2182         tx_start_bd->nbytes = rte_cpu_to_le_16(m0->data_len);
2183         tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2184         tx_start_bd->general_data =
2185             (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
2186
2187         tx_start_bd->nbd = rte_cpu_to_le_16(2);
2188
2189         if (m0->ol_flags & PKT_TX_VLAN_PKT) {
2190                 tx_start_bd->vlan_or_ethertype =
2191                     rte_cpu_to_le_16(m0->vlan_tci);
2192                 tx_start_bd->bd_flags.as_bitfield |=
2193                     (X_ETH_OUTBAND_VLAN <<
2194                      ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT);
2195         } else {
2196                 if (IS_PF(sc))
2197                         tx_start_bd->vlan_or_ethertype =
2198                             rte_cpu_to_le_16(pkt_prod);
2199                 else {
2200                         /* when transmitting in a vf, start bd
2201                          * must hold the ethertype for fw to enforce it
2202                          */
2203                         struct rte_ether_hdr *eh =
2204                             rte_pktmbuf_mtod(m0, struct rte_ether_hdr *);
2205
2206                         /* Still need to consider inband vlan for enforced */
2207                         if (eh->ether_type ==
2208                                         rte_cpu_to_be_16(RTE_ETHER_TYPE_VLAN)) {
2209                                 struct rte_vlan_hdr *vh =
2210                                         (struct rte_vlan_hdr *)(eh + 1);
2211                                 tx_start_bd->bd_flags.as_bitfield |=
2212                                         (X_ETH_INBAND_VLAN <<
2213                                         ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT);
2214                                 tx_start_bd->vlan_or_ethertype =
2215                                         rte_cpu_to_le_16(ntohs(vh->vlan_tci));
2216                         } else {
2217                                 tx_start_bd->vlan_or_ethertype =
2218                                         (rte_cpu_to_le_16
2219                                         (rte_be_to_cpu_16(eh->ether_type)));
2220                         }
2221                 }
2222         }
2223
2224         bd_prod = NEXT_TX_BD(bd_prod);
2225         if (IS_VF(sc)) {
2226                 struct eth_tx_parse_bd_e2 *tx_parse_bd;
2227                 const struct rte_ether_hdr *eh =
2228                     rte_pktmbuf_mtod(m0, struct rte_ether_hdr *);
2229                 uint8_t mac_type = UNICAST_ADDRESS;
2230
2231                 tx_parse_bd =
2232                     &txq->tx_ring[TX_BD(bd_prod, txq)].parse_bd_e2;
2233                 if (rte_is_multicast_ether_addr(&eh->d_addr)) {
2234                         if (rte_is_broadcast_ether_addr(&eh->d_addr))
2235                                 mac_type = BROADCAST_ADDRESS;
2236                         else
2237                                 mac_type = MULTICAST_ADDRESS;
2238                 }
2239                 tx_parse_bd->parsing_data =
2240                     (mac_type << ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT);
2241
2242                 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_hi,
2243                            &eh->d_addr.addr_bytes[0], 2);
2244                 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_mid,
2245                            &eh->d_addr.addr_bytes[2], 2);
2246                 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_lo,
2247                            &eh->d_addr.addr_bytes[4], 2);
2248                 rte_memcpy(&tx_parse_bd->data.mac_addr.src_hi,
2249                            &eh->s_addr.addr_bytes[0], 2);
2250                 rte_memcpy(&tx_parse_bd->data.mac_addr.src_mid,
2251                            &eh->s_addr.addr_bytes[2], 2);
2252                 rte_memcpy(&tx_parse_bd->data.mac_addr.src_lo,
2253                            &eh->s_addr.addr_bytes[4], 2);
2254
2255                 tx_parse_bd->data.mac_addr.dst_hi =
2256                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_hi);
2257                 tx_parse_bd->data.mac_addr.dst_mid =
2258                     rte_cpu_to_be_16(tx_parse_bd->data.
2259                                      mac_addr.dst_mid);
2260                 tx_parse_bd->data.mac_addr.dst_lo =
2261                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_lo);
2262                 tx_parse_bd->data.mac_addr.src_hi =
2263                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_hi);
2264                 tx_parse_bd->data.mac_addr.src_mid =
2265                     rte_cpu_to_be_16(tx_parse_bd->data.
2266                                      mac_addr.src_mid);
2267                 tx_parse_bd->data.mac_addr.src_lo =
2268                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_lo);
2269
2270                 PMD_TX_LOG(DEBUG,
2271                            "PBD dst %x %x %x src %x %x %x p_data %x",
2272                            tx_parse_bd->data.mac_addr.dst_hi,
2273                            tx_parse_bd->data.mac_addr.dst_mid,
2274                            tx_parse_bd->data.mac_addr.dst_lo,
2275                            tx_parse_bd->data.mac_addr.src_hi,
2276                            tx_parse_bd->data.mac_addr.src_mid,
2277                            tx_parse_bd->data.mac_addr.src_lo,
2278                            tx_parse_bd->parsing_data);
2279         }
2280
2281         PMD_TX_LOG(DEBUG,
2282                    "start bd: nbytes %d flags %x vlan %x",
2283                    tx_start_bd->nbytes,
2284                    tx_start_bd->bd_flags.as_bitfield,
2285                    tx_start_bd->vlan_or_ethertype);
2286
2287         bd_prod = NEXT_TX_BD(bd_prod);
2288         pkt_prod++;
2289
2290         if (TX_IDX(bd_prod) < 2)
2291                 nbds++;
2292
2293         txq->nb_tx_avail -= 2;
2294         txq->tx_bd_tail = bd_prod;
2295         txq->tx_pkt_tail = pkt_prod;
2296
2297         return nbds + 2;
2298 }
2299
2300 static uint16_t bnx2x_cid_ilt_lines(struct bnx2x_softc *sc)
2301 {
2302         return L2_ILT_LINES(sc);
2303 }
2304
2305 static void bnx2x_ilt_set_info(struct bnx2x_softc *sc)
2306 {
2307         struct ilt_client_info *ilt_client;
2308         struct ecore_ilt *ilt = sc->ilt;
2309         uint16_t line = 0;
2310
2311         PMD_INIT_FUNC_TRACE(sc);
2312
2313         ilt->start_line = FUNC_ILT_BASE(SC_FUNC(sc));
2314
2315         /* CDU */
2316         ilt_client = &ilt->clients[ILT_CLIENT_CDU];
2317         ilt_client->client_num = ILT_CLIENT_CDU;
2318         ilt_client->page_size = CDU_ILT_PAGE_SZ;
2319         ilt_client->flags = ILT_CLIENT_SKIP_MEM;
2320         ilt_client->start = line;
2321         line += bnx2x_cid_ilt_lines(sc);
2322
2323         if (CNIC_SUPPORT(sc)) {
2324                 line += CNIC_ILT_LINES;
2325         }
2326
2327         ilt_client->end = (line - 1);
2328
2329         /* QM */
2330         if (QM_INIT(sc->qm_cid_count)) {
2331                 ilt_client = &ilt->clients[ILT_CLIENT_QM];
2332                 ilt_client->client_num = ILT_CLIENT_QM;
2333                 ilt_client->page_size = QM_ILT_PAGE_SZ;
2334                 ilt_client->flags = 0;
2335                 ilt_client->start = line;
2336
2337                 /* 4 bytes for each cid */
2338                 line += DIV_ROUND_UP(sc->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
2339                                      QM_ILT_PAGE_SZ);
2340
2341                 ilt_client->end = (line - 1);
2342         }
2343
2344         if (CNIC_SUPPORT(sc)) {
2345                 /* SRC */
2346                 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
2347                 ilt_client->client_num = ILT_CLIENT_SRC;
2348                 ilt_client->page_size = SRC_ILT_PAGE_SZ;
2349                 ilt_client->flags = 0;
2350                 ilt_client->start = line;
2351                 line += SRC_ILT_LINES;
2352                 ilt_client->end = (line - 1);
2353
2354                 /* TM */
2355                 ilt_client = &ilt->clients[ILT_CLIENT_TM];
2356                 ilt_client->client_num = ILT_CLIENT_TM;
2357                 ilt_client->page_size = TM_ILT_PAGE_SZ;
2358                 ilt_client->flags = 0;
2359                 ilt_client->start = line;
2360                 line += TM_ILT_LINES;
2361                 ilt_client->end = (line - 1);
2362         }
2363
2364         assert((line <= ILT_MAX_LINES));
2365 }
2366
2367 static void bnx2x_set_fp_rx_buf_size(struct bnx2x_softc *sc)
2368 {
2369         int i;
2370
2371         for (i = 0; i < sc->num_queues; i++) {
2372                 /* get the Rx buffer size for RX frames */
2373                 sc->fp[i].rx_buf_size =
2374                     (IP_HEADER_ALIGNMENT_PADDING + ETH_OVERHEAD + sc->mtu);
2375         }
2376 }
2377
2378 int bnx2x_alloc_ilt_mem(struct bnx2x_softc *sc)
2379 {
2380
2381         sc->ilt = rte_malloc("", sizeof(struct ecore_ilt), RTE_CACHE_LINE_SIZE);
2382
2383         return sc->ilt == NULL;
2384 }
2385
2386 static int bnx2x_alloc_ilt_lines_mem(struct bnx2x_softc *sc)
2387 {
2388         sc->ilt->lines = rte_calloc("",
2389                                     sizeof(struct ilt_line), ILT_MAX_LINES,
2390                                     RTE_CACHE_LINE_SIZE);
2391         return sc->ilt->lines == NULL;
2392 }
2393
2394 void bnx2x_free_ilt_mem(struct bnx2x_softc *sc)
2395 {
2396         rte_free(sc->ilt);
2397         sc->ilt = NULL;
2398 }
2399
2400 static void bnx2x_free_ilt_lines_mem(struct bnx2x_softc *sc)
2401 {
2402         if (sc->ilt->lines != NULL) {
2403                 rte_free(sc->ilt->lines);
2404                 sc->ilt->lines = NULL;
2405         }
2406 }
2407
2408 static void bnx2x_free_mem(struct bnx2x_softc *sc)
2409 {
2410         uint32_t i;
2411
2412         for (i = 0; i < L2_ILT_LINES(sc); i++) {
2413                 sc->context[i].vcxt = NULL;
2414                 sc->context[i].size = 0;
2415         }
2416
2417         ecore_ilt_mem_op(sc, ILT_MEMOP_FREE);
2418
2419         bnx2x_free_ilt_lines_mem(sc);
2420 }
2421
2422 static int bnx2x_alloc_mem(struct bnx2x_softc *sc)
2423 {
2424         int context_size;
2425         int allocated;
2426         int i;
2427         char cdu_name[RTE_MEMZONE_NAMESIZE];
2428
2429         /*
2430          * Allocate memory for CDU context:
2431          * This memory is allocated separately and not in the generic ILT
2432          * functions because CDU differs in few aspects:
2433          * 1. There can be multiple entities allocating memory for context -
2434          * regular L2, CNIC, and SRIOV drivers. Each separately controls
2435          * its own ILT lines.
2436          * 2. Since CDU page-size is not a single 4KB page (which is the case
2437          * for the other ILT clients), to be efficient we want to support
2438          * allocation of sub-page-size in the last entry.
2439          * 3. Context pointers are used by the driver to pass to FW / update
2440          * the context (for the other ILT clients the pointers are used just to
2441          * free the memory during unload).
2442          */
2443         context_size = (sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(sc));
2444         for (i = 0, allocated = 0; allocated < context_size; i++) {
2445                 sc->context[i].size = min(CDU_ILT_PAGE_SZ,
2446                                           (context_size - allocated));
2447
2448                 snprintf(cdu_name, sizeof(cdu_name), "cdu_%d", i);
2449                 if (bnx2x_dma_alloc(sc, sc->context[i].size,
2450                                   &sc->context[i].vcxt_dma,
2451                                   cdu_name, BNX2X_PAGE_SIZE) != 0) {
2452                         bnx2x_free_mem(sc);
2453                         return -1;
2454                 }
2455
2456                 sc->context[i].vcxt =
2457                     (union cdu_context *)sc->context[i].vcxt_dma.vaddr;
2458
2459                 allocated += sc->context[i].size;
2460         }
2461
2462         bnx2x_alloc_ilt_lines_mem(sc);
2463
2464         if (ecore_ilt_mem_op(sc, ILT_MEMOP_ALLOC)) {
2465                 PMD_DRV_LOG(NOTICE, sc, "ecore_ilt_mem_op ILT_MEMOP_ALLOC failed");
2466                 bnx2x_free_mem(sc);
2467                 return -1;
2468         }
2469
2470         return 0;
2471 }
2472
2473 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc)
2474 {
2475         bnx2x_dma_free(&sc->fw_stats_dma);
2476         sc->fw_stats_num = 0;
2477
2478         sc->fw_stats_req_size = 0;
2479         sc->fw_stats_req = NULL;
2480         sc->fw_stats_req_mapping = 0;
2481
2482         sc->fw_stats_data_size = 0;
2483         sc->fw_stats_data = NULL;
2484         sc->fw_stats_data_mapping = 0;
2485 }
2486
2487 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc)
2488 {
2489         uint8_t num_queue_stats;
2490         int num_groups, vf_headroom = 0;
2491
2492         /* number of queues for statistics is number of eth queues */
2493         num_queue_stats = BNX2X_NUM_ETH_QUEUES(sc);
2494
2495         /*
2496          * Total number of FW statistics requests =
2497          *   1 for port stats + 1 for PF stats + num of queues
2498          */
2499         sc->fw_stats_num = (2 + num_queue_stats);
2500
2501         /*
2502          * Request is built from stats_query_header and an array of
2503          * stats_query_cmd_group each of which contains STATS_QUERY_CMD_COUNT
2504          * rules. The real number or requests is configured in the
2505          * stats_query_header.
2506          */
2507         num_groups = (sc->fw_stats_num + vf_headroom) / STATS_QUERY_CMD_COUNT;
2508         if ((sc->fw_stats_num + vf_headroom) % STATS_QUERY_CMD_COUNT)
2509                 num_groups++;
2510
2511         sc->fw_stats_req_size =
2512             (sizeof(struct stats_query_header) +
2513              (num_groups * sizeof(struct stats_query_cmd_group)));
2514
2515         /*
2516          * Data for statistics requests + stats_counter.
2517          * stats_counter holds per-STORM counters that are incremented when
2518          * STORM has finished with the current request. Memory for FCoE
2519          * offloaded statistics are counted anyway, even if they will not be sent.
2520          * VF stats are not accounted for here as the data of VF stats is stored
2521          * in memory allocated by the VF, not here.
2522          */
2523         sc->fw_stats_data_size =
2524             (sizeof(struct stats_counter) +
2525              sizeof(struct per_port_stats) + sizeof(struct per_pf_stats) +
2526              /* sizeof(struct fcoe_statistics_params) + */
2527              (sizeof(struct per_queue_stats) * num_queue_stats));
2528
2529         if (bnx2x_dma_alloc(sc, (sc->fw_stats_req_size + sc->fw_stats_data_size),
2530                           &sc->fw_stats_dma, "fw_stats",
2531                           RTE_CACHE_LINE_SIZE) != 0) {
2532                 bnx2x_free_fw_stats_mem(sc);
2533                 return -1;
2534         }
2535
2536         /* set up the shortcuts */
2537
2538         sc->fw_stats_req = (struct bnx2x_fw_stats_req *)sc->fw_stats_dma.vaddr;
2539         sc->fw_stats_req_mapping = sc->fw_stats_dma.paddr;
2540
2541         sc->fw_stats_data =
2542             (struct bnx2x_fw_stats_data *)((uint8_t *) sc->fw_stats_dma.vaddr +
2543                                          sc->fw_stats_req_size);
2544         sc->fw_stats_data_mapping = (sc->fw_stats_dma.paddr +
2545                                      sc->fw_stats_req_size);
2546
2547         return 0;
2548 }
2549
2550 /*
2551  * Bits map:
2552  * 0-7  - Engine0 load counter.
2553  * 8-15 - Engine1 load counter.
2554  * 16   - Engine0 RESET_IN_PROGRESS bit.
2555  * 17   - Engine1 RESET_IN_PROGRESS bit.
2556  * 18   - Engine0 ONE_IS_LOADED. Set when there is at least one active
2557  *        function on the engine
2558  * 19   - Engine1 ONE_IS_LOADED.
2559  * 20   - Chip reset flow bit. When set none-leader must wait for both engines
2560  *        leader to complete (check for both RESET_IN_PROGRESS bits and not
2561  *        for just the one belonging to its engine).
2562  */
2563 #define BNX2X_RECOVERY_GLOB_REG     MISC_REG_GENERIC_POR_1
2564 #define BNX2X_PATH0_LOAD_CNT_MASK   0x000000ff
2565 #define BNX2X_PATH0_LOAD_CNT_SHIFT  0
2566 #define BNX2X_PATH1_LOAD_CNT_MASK   0x0000ff00
2567 #define BNX2X_PATH1_LOAD_CNT_SHIFT  8
2568 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
2569 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
2570 #define BNX2X_GLOBAL_RESET_BIT      0x00040000
2571
2572 /* set the GLOBAL_RESET bit, should be run under rtnl lock */
2573 static void bnx2x_set_reset_global(struct bnx2x_softc *sc)
2574 {
2575         uint32_t val;
2576         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2577         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2578         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
2579         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2580 }
2581
2582 /* clear the GLOBAL_RESET bit, should be run under rtnl lock */
2583 static void bnx2x_clear_reset_global(struct bnx2x_softc *sc)
2584 {
2585         uint32_t val;
2586         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2587         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2588         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
2589         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2590 }
2591
2592 /* checks the GLOBAL_RESET bit, should be run under rtnl lock */
2593 static uint8_t bnx2x_reset_is_global(struct bnx2x_softc *sc)
2594 {
2595         return REG_RD(sc, BNX2X_RECOVERY_GLOB_REG) & BNX2X_GLOBAL_RESET_BIT;
2596 }
2597
2598 /* clear RESET_IN_PROGRESS bit for the engine, should be run under rtnl lock */
2599 static void bnx2x_set_reset_done(struct bnx2x_softc *sc)
2600 {
2601         uint32_t val;
2602         uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2603             BNX2X_PATH0_RST_IN_PROG_BIT;
2604
2605         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2606
2607         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2608         /* Clear the bit */
2609         val &= ~bit;
2610         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2611
2612         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2613 }
2614
2615 /* set RESET_IN_PROGRESS for the engine, should be run under rtnl lock */
2616 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc)
2617 {
2618         uint32_t val;
2619         uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2620             BNX2X_PATH0_RST_IN_PROG_BIT;
2621
2622         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2623
2624         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2625         /* Set the bit */
2626         val |= bit;
2627         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2628
2629         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2630 }
2631
2632 /* check RESET_IN_PROGRESS bit for an engine, should be run under rtnl lock */
2633 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine)
2634 {
2635         uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2636         uint32_t bit = engine ? BNX2X_PATH1_RST_IN_PROG_BIT :
2637             BNX2X_PATH0_RST_IN_PROG_BIT;
2638
2639         /* return false if bit is set */
2640         return (val & bit) ? FALSE : TRUE;
2641 }
2642
2643 /* get the load status for an engine, should be run under rtnl lock */
2644 static uint8_t bnx2x_get_load_status(struct bnx2x_softc *sc, int engine)
2645 {
2646         uint32_t mask = engine ? BNX2X_PATH1_LOAD_CNT_MASK :
2647             BNX2X_PATH0_LOAD_CNT_MASK;
2648         uint32_t shift = engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2649             BNX2X_PATH0_LOAD_CNT_SHIFT;
2650         uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2651
2652         val = ((val & mask) >> shift);
2653
2654         return val != 0;
2655 }
2656
2657 /* set pf load mark */
2658 static void bnx2x_set_pf_load(struct bnx2x_softc *sc)
2659 {
2660         uint32_t val;
2661         uint32_t val1;
2662         uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2663             BNX2X_PATH0_LOAD_CNT_MASK;
2664         uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2665             BNX2X_PATH0_LOAD_CNT_SHIFT;
2666
2667         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2668
2669         PMD_INIT_FUNC_TRACE(sc);
2670
2671         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2672
2673         /* get the current counter value */
2674         val1 = ((val & mask) >> shift);
2675
2676         /* set bit of this PF */
2677         val1 |= (1 << SC_ABS_FUNC(sc));
2678
2679         /* clear the old value */
2680         val &= ~mask;
2681
2682         /* set the new one */
2683         val |= ((val1 << shift) & mask);
2684
2685         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2686
2687         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2688 }
2689
2690 /* clear pf load mark */
2691 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc)
2692 {
2693         uint32_t val1, val;
2694         uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2695             BNX2X_PATH0_LOAD_CNT_MASK;
2696         uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2697             BNX2X_PATH0_LOAD_CNT_SHIFT;
2698
2699         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2700         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2701
2702         /* get the current counter value */
2703         val1 = (val & mask) >> shift;
2704
2705         /* clear bit of that PF */
2706         val1 &= ~(1 << SC_ABS_FUNC(sc));
2707
2708         /* clear the old value */
2709         val &= ~mask;
2710
2711         /* set the new one */
2712         val |= ((val1 << shift) & mask);
2713
2714         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2715         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2716         return val1 != 0;
2717 }
2718
2719 /* send load requrest to mcp and analyze response */
2720 static int bnx2x_nic_load_request(struct bnx2x_softc *sc, uint32_t * load_code)
2721 {
2722         PMD_INIT_FUNC_TRACE(sc);
2723
2724         /* init fw_seq */
2725         sc->fw_seq =
2726             (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
2727              DRV_MSG_SEQ_NUMBER_MASK);
2728
2729         PMD_DRV_LOG(DEBUG, sc, "initial fw_seq 0x%04x", sc->fw_seq);
2730
2731 #ifdef BNX2X_PULSE
2732         /* get the current FW pulse sequence */
2733         sc->fw_drv_pulse_wr_seq =
2734             (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb) &
2735              DRV_PULSE_SEQ_MASK);
2736 #else
2737         /* set ALWAYS_ALIVE bit in shmem */
2738         sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2739         bnx2x_drv_pulse(sc);
2740 #endif
2741
2742         /* load request */
2743         (*load_code) = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
2744                                       DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
2745
2746         /* if the MCP fails to respond we must abort */
2747         if (!(*load_code)) {
2748                 PMD_DRV_LOG(NOTICE, sc, "MCP response failure!");
2749                 return -1;
2750         }
2751
2752         /* if MCP refused then must abort */
2753         if ((*load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED) {
2754                 PMD_DRV_LOG(NOTICE, sc, "MCP refused load request");
2755                 return -1;
2756         }
2757
2758         return 0;
2759 }
2760
2761 /*
2762  * Check whether another PF has already loaded FW to chip. In virtualized
2763  * environments a pf from anoth VM may have already initialized the device
2764  * including loading FW.
2765  */
2766 static int bnx2x_nic_load_analyze_req(struct bnx2x_softc *sc, uint32_t load_code)
2767 {
2768         uint32_t my_fw, loaded_fw;
2769
2770         /* is another pf loaded on this engine? */
2771         if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
2772             (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
2773                 /* build my FW version dword */
2774                 my_fw = (BNX2X_5710_FW_MAJOR_VERSION +
2775                          (BNX2X_5710_FW_MINOR_VERSION << 8) +
2776                          (BNX2X_5710_FW_REVISION_VERSION << 16) +
2777                          (BNX2X_5710_FW_ENGINEERING_VERSION << 24));
2778
2779                 /* read loaded FW from chip */
2780                 loaded_fw = REG_RD(sc, XSEM_REG_PRAM);
2781                 PMD_DRV_LOG(DEBUG, sc, "loaded FW 0x%08x / my FW 0x%08x",
2782                             loaded_fw, my_fw);
2783
2784                 /* abort nic load if version mismatch */
2785                 if (my_fw != loaded_fw) {
2786                         PMD_DRV_LOG(NOTICE, sc,
2787                                     "FW 0x%08x already loaded (mine is 0x%08x)",
2788                                     loaded_fw, my_fw);
2789                         return -1;
2790                 }
2791         }
2792
2793         return 0;
2794 }
2795
2796 /* mark PMF if applicable */
2797 static void bnx2x_nic_load_pmf(struct bnx2x_softc *sc, uint32_t load_code)
2798 {
2799         uint32_t ncsi_oem_data_addr;
2800
2801         PMD_INIT_FUNC_TRACE(sc);
2802
2803         if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
2804             (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
2805             (load_code == FW_MSG_CODE_DRV_LOAD_PORT)) {
2806                 /*
2807                  * Barrier here for ordering between the writing to sc->port.pmf here
2808                  * and reading it from the periodic task.
2809                  */
2810                 sc->port.pmf = 1;
2811                 mb();
2812         } else {
2813                 sc->port.pmf = 0;
2814         }
2815
2816         PMD_DRV_LOG(DEBUG, sc, "pmf %d", sc->port.pmf);
2817
2818         if (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) {
2819                 if (SHMEM2_HAS(sc, ncsi_oem_data_addr)) {
2820                         ncsi_oem_data_addr = SHMEM2_RD(sc, ncsi_oem_data_addr);
2821                         if (ncsi_oem_data_addr) {
2822                                 REG_WR(sc,
2823                                        (ncsi_oem_data_addr +
2824                                         offsetof(struct glob_ncsi_oem_data,
2825                                                  driver_version)), 0);
2826                         }
2827                 }
2828         }
2829 }
2830
2831 static void bnx2x_read_mf_cfg(struct bnx2x_softc *sc)
2832 {
2833         int n = (CHIP_IS_MODE_4_PORT(sc) ? 2 : 1);
2834         int abs_func;
2835         int vn;
2836
2837         if (BNX2X_NOMCP(sc)) {
2838                 return;         /* what should be the default bvalue in this case */
2839         }
2840
2841         /*
2842          * The formula for computing the absolute function number is...
2843          * For 2 port configuration (4 functions per port):
2844          *   abs_func = 2 * vn + SC_PORT + SC_PATH
2845          * For 4 port configuration (2 functions per port):
2846          *   abs_func = 4 * vn + 2 * SC_PORT + SC_PATH
2847          */
2848         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
2849                 abs_func = (n * (2 * vn + SC_PORT(sc)) + SC_PATH(sc));
2850                 if (abs_func >= E1H_FUNC_MAX) {
2851                         break;
2852                 }
2853                 sc->devinfo.mf_info.mf_config[vn] =
2854                     MFCFG_RD(sc, func_mf_config[abs_func].config);
2855         }
2856
2857         if (sc->devinfo.mf_info.mf_config[SC_VN(sc)] &
2858             FUNC_MF_CFG_FUNC_DISABLED) {
2859                 PMD_DRV_LOG(DEBUG, sc, "mf_cfg function disabled");
2860                 sc->flags |= BNX2X_MF_FUNC_DIS;
2861         } else {
2862                 PMD_DRV_LOG(DEBUG, sc, "mf_cfg function enabled");
2863                 sc->flags &= ~BNX2X_MF_FUNC_DIS;
2864         }
2865 }
2866
2867 /* acquire split MCP access lock register */
2868 static int bnx2x_acquire_alr(struct bnx2x_softc *sc)
2869 {
2870         uint32_t j, val;
2871
2872         for (j = 0; j < 1000; j++) {
2873                 val = (1UL << 31);
2874                 REG_WR(sc, GRCBASE_MCP + 0x9c, val);
2875                 val = REG_RD(sc, GRCBASE_MCP + 0x9c);
2876                 if (val & (1L << 31))
2877                         break;
2878
2879                 DELAY(5000);
2880         }
2881
2882         if (!(val & (1L << 31))) {
2883                 PMD_DRV_LOG(NOTICE, sc, "Cannot acquire MCP access lock register");
2884                 return -1;
2885         }
2886
2887         return 0;
2888 }
2889
2890 /* release split MCP access lock register */
2891 static void bnx2x_release_alr(struct bnx2x_softc *sc)
2892 {
2893         REG_WR(sc, GRCBASE_MCP + 0x9c, 0);
2894 }
2895
2896 static void bnx2x_fan_failure(struct bnx2x_softc *sc)
2897 {
2898         int port = SC_PORT(sc);
2899         uint32_t ext_phy_config;
2900
2901         /* mark the failure */
2902         ext_phy_config =
2903             SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
2904
2905         ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2906         ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
2907         SHMEM_WR(sc, dev_info.port_hw_config[port].external_phy_config,
2908                  ext_phy_config);
2909
2910         /* log the failure */
2911         PMD_DRV_LOG(INFO, sc,
2912                     "Fan Failure has caused the driver to shutdown "
2913                     "the card to prevent permanent damage. "
2914                     "Please contact OEM Support for assistance");
2915
2916         rte_panic("Schedule task to handle fan failure");
2917 }
2918
2919 /* this function is called upon a link interrupt */
2920 static void bnx2x_link_attn(struct bnx2x_softc *sc)
2921 {
2922         uint32_t pause_enabled = 0;
2923         struct host_port_stats *pstats;
2924         int cmng_fns;
2925
2926         /* Make sure that we are synced with the current statistics */
2927         bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2928
2929         elink_link_update(&sc->link_params, &sc->link_vars);
2930
2931         if (sc->link_vars.link_up) {
2932
2933                 /* dropless flow control */
2934                 if (sc->dropless_fc) {
2935                         pause_enabled = 0;
2936
2937                         if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
2938                                 pause_enabled = 1;
2939                         }
2940
2941                         REG_WR(sc,
2942                                (BAR_USTRORM_INTMEM +
2943                                 USTORM_ETH_PAUSE_ENABLED_OFFSET(SC_PORT(sc))),
2944                                pause_enabled);
2945                 }
2946
2947                 if (sc->link_vars.mac_type != ELINK_MAC_TYPE_EMAC) {
2948                         pstats = BNX2X_SP(sc, port_stats);
2949                         /* reset old mac stats */
2950                         memset(&(pstats->mac_stx[0]), 0,
2951                                sizeof(struct mac_stx));
2952                 }
2953
2954                 if (sc->state == BNX2X_STATE_OPEN) {
2955                         bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
2956                 }
2957         }
2958
2959         if (sc->link_vars.link_up && sc->link_vars.line_speed) {
2960                 cmng_fns = bnx2x_get_cmng_fns_mode(sc);
2961
2962                 if (cmng_fns != CMNG_FNS_NONE) {
2963                         bnx2x_cmng_fns_init(sc, FALSE, cmng_fns);
2964                         storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
2965                 }
2966         }
2967
2968         bnx2x_link_report_locked(sc);
2969
2970         if (IS_MF(sc)) {
2971                 bnx2x_link_sync_notify(sc);
2972         }
2973 }
2974
2975 static void bnx2x_attn_int_asserted(struct bnx2x_softc *sc, uint32_t asserted)
2976 {
2977         int port = SC_PORT(sc);
2978         uint32_t aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2979             MISC_REG_AEU_MASK_ATTN_FUNC_0;
2980         uint32_t nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2981             NIG_REG_MASK_INTERRUPT_PORT0;
2982         uint32_t aeu_mask;
2983         uint32_t nig_mask = 0;
2984         uint32_t reg_addr;
2985         uint32_t igu_acked;
2986         uint32_t cnt;
2987
2988         if (sc->attn_state & asserted) {
2989                 PMD_DRV_LOG(ERR, sc, "IGU ERROR attn=0x%08x", asserted);
2990         }
2991
2992         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2993
2994         aeu_mask = REG_RD(sc, aeu_addr);
2995
2996         aeu_mask &= ~(asserted & 0x3ff);
2997
2998         REG_WR(sc, aeu_addr, aeu_mask);
2999
3000         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3001
3002         sc->attn_state |= asserted;
3003
3004         if (asserted & ATTN_HARD_WIRED_MASK) {
3005                 if (asserted & ATTN_NIG_FOR_FUNC) {
3006
3007                         bnx2x_acquire_phy_lock(sc);
3008                         /* save nig interrupt mask */
3009                         nig_mask = REG_RD(sc, nig_int_mask_addr);
3010
3011                         /* If nig_mask is not set, no need to call the update function */
3012                         if (nig_mask) {
3013                                 REG_WR(sc, nig_int_mask_addr, 0);
3014
3015                                 bnx2x_link_attn(sc);
3016                         }
3017
3018                         /* handle unicore attn? */
3019                 }
3020
3021                 if (asserted & ATTN_SW_TIMER_4_FUNC) {
3022                         PMD_DRV_LOG(DEBUG, sc, "ATTN_SW_TIMER_4_FUNC!");
3023                 }
3024
3025                 if (asserted & GPIO_2_FUNC) {
3026                         PMD_DRV_LOG(DEBUG, sc, "GPIO_2_FUNC!");
3027                 }
3028
3029                 if (asserted & GPIO_3_FUNC) {
3030                         PMD_DRV_LOG(DEBUG, sc, "GPIO_3_FUNC!");
3031                 }
3032
3033                 if (asserted & GPIO_4_FUNC) {
3034                         PMD_DRV_LOG(DEBUG, sc, "GPIO_4_FUNC!");
3035                 }
3036
3037                 if (port == 0) {
3038                         if (asserted & ATTN_GENERAL_ATTN_1) {
3039                                 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_1!");
3040                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3041                         }
3042                         if (asserted & ATTN_GENERAL_ATTN_2) {
3043                                 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_2!");
3044                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3045                         }
3046                         if (asserted & ATTN_GENERAL_ATTN_3) {
3047                                 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_3!");
3048                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3049                         }
3050                 } else {
3051                         if (asserted & ATTN_GENERAL_ATTN_4) {
3052                                 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_4!");
3053                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3054                         }
3055                         if (asserted & ATTN_GENERAL_ATTN_5) {
3056                                 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_5!");
3057                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3058                         }
3059                         if (asserted & ATTN_GENERAL_ATTN_6) {
3060                                 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_6!");
3061                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3062                         }
3063                 }
3064         }
3065         /* hardwired */
3066         if (sc->devinfo.int_block == INT_BLOCK_HC) {
3067                 reg_addr =
3068                     (HC_REG_COMMAND_REG + port * 32 +
3069                      COMMAND_REG_ATTN_BITS_SET);
3070         } else {
3071                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER * 8);
3072         }
3073
3074         PMD_DRV_LOG(DEBUG, sc, "about to mask 0x%08x at %s addr 0x%08x",
3075                     asserted,
3076                     (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
3077                     reg_addr);
3078         REG_WR(sc, reg_addr, asserted);
3079
3080         /* now set back the mask */
3081         if (asserted & ATTN_NIG_FOR_FUNC) {
3082                 /*
3083                  * Verify that IGU ack through BAR was written before restoring
3084                  * NIG mask. This loop should exit after 2-3 iterations max.
3085                  */
3086                 if (sc->devinfo.int_block != INT_BLOCK_HC) {
3087                         cnt = 0;
3088
3089                         do {
3090                                 igu_acked =
3091                                     REG_RD(sc, IGU_REG_ATTENTION_ACK_BITS);
3092                         } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0)
3093                                  && (++cnt < MAX_IGU_ATTN_ACK_TO));
3094
3095                         if (!igu_acked) {
3096                                 PMD_DRV_LOG(ERR, sc,
3097                                             "Failed to verify IGU ack on time");
3098                         }
3099
3100                         mb();
3101                 }
3102
3103                 REG_WR(sc, nig_int_mask_addr, nig_mask);
3104
3105                 bnx2x_release_phy_lock(sc);
3106         }
3107 }
3108
3109 static void
3110 bnx2x_print_next_block(__rte_unused struct bnx2x_softc *sc, __rte_unused int idx,
3111                      __rte_unused const char *blk)
3112 {
3113         PMD_DRV_LOG(INFO, sc, "%s%s", idx ? ", " : "", blk);
3114 }
3115
3116 static int
3117 bnx2x_check_blocks_with_parity0(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3118                               uint8_t print)
3119 {
3120         uint32_t cur_bit = 0;
3121         int i = 0;
3122
3123         for (i = 0; sig; i++) {
3124                 cur_bit = ((uint32_t) 0x1 << i);
3125                 if (sig & cur_bit) {
3126                         switch (cur_bit) {
3127                         case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3128                                 if (print)
3129                                         bnx2x_print_next_block(sc, par_num++,
3130                                                              "BRB");
3131                                 break;
3132                         case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3133                                 if (print)
3134                                         bnx2x_print_next_block(sc, par_num++,
3135                                                              "PARSER");
3136                                 break;
3137                         case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3138                                 if (print)
3139                                         bnx2x_print_next_block(sc, par_num++,
3140                                                              "TSDM");
3141                                 break;
3142                         case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3143                                 if (print)
3144                                         bnx2x_print_next_block(sc, par_num++,
3145                                                              "SEARCHER");
3146                                 break;
3147                         case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3148                                 if (print)
3149                                         bnx2x_print_next_block(sc, par_num++,
3150                                                              "TCM");
3151                                 break;
3152                         case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3153                                 if (print)
3154                                         bnx2x_print_next_block(sc, par_num++,
3155                                                              "TSEMI");
3156                                 break;
3157                         case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3158                                 if (print)
3159                                         bnx2x_print_next_block(sc, par_num++,
3160                                                              "XPB");
3161                                 break;
3162                         }
3163
3164                         /* Clear the bit */
3165                         sig &= ~cur_bit;
3166                 }
3167         }
3168
3169         return par_num;
3170 }
3171
3172 static int
3173 bnx2x_check_blocks_with_parity1(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3174                               uint8_t * global, uint8_t print)
3175 {
3176         int i = 0;
3177         uint32_t cur_bit = 0;
3178         for (i = 0; sig; i++) {
3179                 cur_bit = ((uint32_t) 0x1 << i);
3180                 if (sig & cur_bit) {
3181                         switch (cur_bit) {
3182                         case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3183                                 if (print)
3184                                         bnx2x_print_next_block(sc, par_num++,
3185                                                              "PBF");
3186                                 break;
3187                         case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3188                                 if (print)
3189                                         bnx2x_print_next_block(sc, par_num++,
3190                                                              "QM");
3191                                 break;
3192                         case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3193                                 if (print)
3194                                         bnx2x_print_next_block(sc, par_num++,
3195                                                              "TM");
3196                                 break;
3197                         case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3198                                 if (print)
3199                                         bnx2x_print_next_block(sc, par_num++,
3200                                                              "XSDM");
3201                                 break;
3202                         case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
3203                                 if (print)
3204                                         bnx2x_print_next_block(sc, par_num++,
3205                                                              "XCM");
3206                                 break;
3207                         case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3208                                 if (print)
3209                                         bnx2x_print_next_block(sc, par_num++,
3210                                                              "XSEMI");
3211                                 break;
3212                         case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3213                                 if (print)
3214                                         bnx2x_print_next_block(sc, par_num++,
3215                                                              "DOORBELLQ");
3216                                 break;
3217                         case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
3218                                 if (print)
3219                                         bnx2x_print_next_block(sc, par_num++,
3220                                                              "NIG");
3221                                 break;
3222                         case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3223                                 if (print)
3224                                         bnx2x_print_next_block(sc, par_num++,
3225                                                              "VAUX PCI CORE");
3226                                 *global = TRUE;
3227                                 break;
3228                         case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3229                                 if (print)
3230                                         bnx2x_print_next_block(sc, par_num++,
3231                                                              "DEBUG");
3232                                 break;
3233                         case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3234                                 if (print)
3235                                         bnx2x_print_next_block(sc, par_num++,
3236                                                              "USDM");
3237                                 break;
3238                         case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
3239                                 if (print)
3240                                         bnx2x_print_next_block(sc, par_num++,
3241                                                              "UCM");
3242                                 break;
3243                         case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3244                                 if (print)
3245                                         bnx2x_print_next_block(sc, par_num++,
3246                                                              "USEMI");
3247                                 break;
3248                         case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3249                                 if (print)
3250                                         bnx2x_print_next_block(sc, par_num++,
3251                                                              "UPB");
3252                                 break;
3253                         case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3254                                 if (print)
3255                                         bnx2x_print_next_block(sc, par_num++,
3256                                                              "CSDM");
3257                                 break;
3258                         case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
3259                                 if (print)
3260                                         bnx2x_print_next_block(sc, par_num++,
3261                                                              "CCM");
3262                                 break;
3263                         }
3264
3265                         /* Clear the bit */
3266                         sig &= ~cur_bit;
3267                 }
3268         }
3269
3270         return par_num;
3271 }
3272
3273 static int
3274 bnx2x_check_blocks_with_parity2(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3275                               uint8_t print)
3276 {
3277         uint32_t cur_bit = 0;
3278         int i = 0;
3279
3280         for (i = 0; sig; i++) {
3281                 cur_bit = ((uint32_t) 0x1 << i);
3282                 if (sig & cur_bit) {
3283                         switch (cur_bit) {
3284                         case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3285                                 if (print)
3286                                         bnx2x_print_next_block(sc, par_num++,
3287                                                              "CSEMI");
3288                                 break;
3289                         case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3290                                 if (print)
3291                                         bnx2x_print_next_block(sc, par_num++,
3292                                                              "PXP");
3293                                 break;
3294                         case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3295                                 if (print)
3296                                         bnx2x_print_next_block(sc, par_num++,
3297                                                              "PXPPCICLOCKCLIENT");
3298                                 break;
3299                         case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3300                                 if (print)
3301                                         bnx2x_print_next_block(sc, par_num++,
3302                                                              "CFC");
3303                                 break;
3304                         case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3305                                 if (print)
3306                                         bnx2x_print_next_block(sc, par_num++,
3307                                                              "CDU");
3308                                 break;
3309                         case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
3310                                 if (print)
3311                                         bnx2x_print_next_block(sc, par_num++,
3312                                                              "DMAE");
3313                                 break;
3314                         case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3315                                 if (print)
3316                                         bnx2x_print_next_block(sc, par_num++,
3317                                                              "IGU");
3318                                 break;
3319                         case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3320                                 if (print)
3321                                         bnx2x_print_next_block(sc, par_num++,
3322                                                              "MISC");
3323                                 break;
3324                         }
3325
3326                         /* Clear the bit */
3327                         sig &= ~cur_bit;
3328                 }
3329         }
3330
3331         return par_num;
3332 }
3333
3334 static int
3335 bnx2x_check_blocks_with_parity3(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3336                               uint8_t * global, uint8_t print)
3337 {
3338         uint32_t cur_bit = 0;
3339         int i = 0;
3340
3341         for (i = 0; sig; i++) {
3342                 cur_bit = ((uint32_t) 0x1 << i);
3343                 if (sig & cur_bit) {
3344                         switch (cur_bit) {
3345                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3346                                 if (print)
3347                                         bnx2x_print_next_block(sc, par_num++,
3348                                                              "MCP ROM");
3349                                 *global = TRUE;
3350                                 break;
3351                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3352                                 if (print)
3353                                         bnx2x_print_next_block(sc, par_num++,
3354                                                              "MCP UMP RX");
3355                                 *global = TRUE;
3356                                 break;
3357                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3358                                 if (print)
3359                                         bnx2x_print_next_block(sc, par_num++,
3360                                                              "MCP UMP TX");
3361                                 *global = TRUE;
3362                                 break;
3363                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3364                                 if (print)
3365                                         bnx2x_print_next_block(sc, par_num++,
3366                                                              "MCP SCPAD");
3367                                 *global = TRUE;
3368                                 break;
3369                         }
3370
3371                         /* Clear the bit */
3372                         sig &= ~cur_bit;
3373                 }
3374         }
3375
3376         return par_num;
3377 }
3378
3379 static int
3380 bnx2x_check_blocks_with_parity4(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3381                               uint8_t print)
3382 {
3383         uint32_t cur_bit = 0;
3384         int i = 0;
3385
3386         for (i = 0; sig; i++) {
3387                 cur_bit = ((uint32_t) 0x1 << i);
3388                 if (sig & cur_bit) {
3389                         switch (cur_bit) {
3390                         case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
3391                                 if (print)
3392                                         bnx2x_print_next_block(sc, par_num++,
3393                                                              "PGLUE_B");
3394                                 break;
3395                         case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
3396                                 if (print)
3397                                         bnx2x_print_next_block(sc, par_num++,
3398                                                              "ATC");
3399                                 break;
3400                         }
3401
3402                         /* Clear the bit */
3403                         sig &= ~cur_bit;
3404                 }
3405         }
3406
3407         return par_num;
3408 }
3409
3410 static uint8_t
3411 bnx2x_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print,
3412                 uint32_t * sig)
3413 {
3414         int par_num = 0;
3415
3416         if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
3417             (sig[1] & HW_PRTY_ASSERT_SET_1) ||
3418             (sig[2] & HW_PRTY_ASSERT_SET_2) ||
3419             (sig[3] & HW_PRTY_ASSERT_SET_3) ||
3420             (sig[4] & HW_PRTY_ASSERT_SET_4)) {
3421                 PMD_DRV_LOG(ERR, sc,
3422                             "Parity error: HW block parity attention:"
3423                             "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x",
3424                             (uint32_t) (sig[0] & HW_PRTY_ASSERT_SET_0),
3425                             (uint32_t) (sig[1] & HW_PRTY_ASSERT_SET_1),
3426                             (uint32_t) (sig[2] & HW_PRTY_ASSERT_SET_2),
3427                             (uint32_t) (sig[3] & HW_PRTY_ASSERT_SET_3),
3428                             (uint32_t) (sig[4] & HW_PRTY_ASSERT_SET_4));
3429
3430                 if (print)
3431                         PMD_DRV_LOG(INFO, sc, "Parity errors detected in blocks: ");
3432
3433                 par_num =
3434                     bnx2x_check_blocks_with_parity0(sc, sig[0] &
3435                                                   HW_PRTY_ASSERT_SET_0,
3436                                                   par_num, print);
3437                 par_num =
3438                     bnx2x_check_blocks_with_parity1(sc, sig[1] &
3439                                                   HW_PRTY_ASSERT_SET_1,
3440                                                   par_num, global, print);
3441                 par_num =
3442                     bnx2x_check_blocks_with_parity2(sc, sig[2] &
3443                                                   HW_PRTY_ASSERT_SET_2,
3444                                                   par_num, print);
3445                 par_num =
3446                     bnx2x_check_blocks_with_parity3(sc, sig[3] &
3447                                                   HW_PRTY_ASSERT_SET_3,
3448                                                   par_num, global, print);
3449                 par_num =
3450                     bnx2x_check_blocks_with_parity4(sc, sig[4] &
3451                                                   HW_PRTY_ASSERT_SET_4,
3452                                                   par_num, print);
3453
3454                 if (print)
3455                         PMD_DRV_LOG(INFO, sc, "");
3456
3457                 return TRUE;
3458         }
3459
3460         return FALSE;
3461 }
3462
3463 static uint8_t
3464 bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print)
3465 {
3466         struct attn_route attn = { {0} };
3467         int port = SC_PORT(sc);
3468
3469         attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
3470         attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
3471         attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
3472         attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
3473
3474         if (!CHIP_IS_E1x(sc))
3475                 attn.sig[4] =
3476                     REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
3477
3478         return bnx2x_parity_attn(sc, global, print, attn.sig);
3479 }
3480
3481 static void bnx2x_attn_int_deasserted4(struct bnx2x_softc *sc, uint32_t attn)
3482 {
3483         uint32_t val;
3484
3485         if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
3486                 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
3487                 PMD_DRV_LOG(INFO, sc, "ERROR: PGLUE hw attention 0x%08x", val);
3488                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
3489                         PMD_DRV_LOG(INFO, sc,
3490                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR");
3491                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
3492                         PMD_DRV_LOG(INFO, sc,
3493                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR");
3494                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
3495                         PMD_DRV_LOG(INFO, sc,
3496                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN");
3497                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
3498                         PMD_DRV_LOG(INFO, sc,
3499                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN");
3500                 if (val &
3501                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
3502                         PMD_DRV_LOG(INFO, sc,
3503                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN");
3504                 if (val &
3505                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
3506                         PMD_DRV_LOG(INFO, sc,
3507                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN");
3508                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
3509                         PMD_DRV_LOG(INFO, sc,
3510                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN");
3511                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
3512                         PMD_DRV_LOG(INFO, sc,
3513                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN");
3514                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
3515                         PMD_DRV_LOG(INFO, sc,
3516                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW");
3517         }
3518
3519         if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
3520                 val = REG_RD(sc, ATC_REG_ATC_INT_STS_CLR);
3521                 PMD_DRV_LOG(INFO, sc, "ERROR: ATC hw attention 0x%08x", val);
3522                 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
3523                         PMD_DRV_LOG(INFO, sc,
3524                                     "ERROR: ATC_ATC_INT_STS_REG_ADDRESS_ERROR");
3525                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
3526                         PMD_DRV_LOG(INFO, sc,
3527                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND");
3528                 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
3529                         PMD_DRV_LOG(INFO, sc,
3530                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS");
3531                 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
3532                         PMD_DRV_LOG(INFO, sc,
3533                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT");
3534                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
3535                         PMD_DRV_LOG(INFO, sc,
3536                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR");
3537                 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
3538                         PMD_DRV_LOG(INFO, sc,
3539                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU");
3540         }
3541
3542         if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3543                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
3544                 PMD_DRV_LOG(INFO, sc,
3545                             "ERROR: FATAL parity attention set4 0x%08x",
3546                             (uint32_t) (attn &
3547                                         (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
3548                                          |
3549                                          AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
3550         }
3551 }
3552
3553 static void bnx2x_e1h_disable(struct bnx2x_softc *sc)
3554 {
3555         int port = SC_PORT(sc);
3556
3557         REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
3558 }
3559
3560 static void bnx2x_e1h_enable(struct bnx2x_softc *sc)
3561 {
3562         int port = SC_PORT(sc);
3563
3564         REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3565 }
3566
3567 /*
3568  * called due to MCP event (on pmf):
3569  *   reread new bandwidth configuration
3570  *   configure FW
3571  *   notify others function about the change
3572  */
3573 static void bnx2x_config_mf_bw(struct bnx2x_softc *sc)
3574 {
3575         if (sc->link_vars.link_up) {
3576                 bnx2x_cmng_fns_init(sc, TRUE, CMNG_FNS_MINMAX);
3577                 bnx2x_link_sync_notify(sc);
3578         }
3579
3580         storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
3581 }
3582
3583 static void bnx2x_set_mf_bw(struct bnx2x_softc *sc)
3584 {
3585         bnx2x_config_mf_bw(sc);
3586         bnx2x_fw_command(sc, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3587 }
3588
3589 static void bnx2x_handle_eee_event(struct bnx2x_softc *sc)
3590 {
3591         bnx2x_fw_command(sc, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3592 }
3593
3594 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3595
3596 static void bnx2x_drv_info_ether_stat(struct bnx2x_softc *sc)
3597 {
3598         struct eth_stats_info *ether_stat = &sc->sp->drv_info_to_mcp.ether_stat;
3599
3600         strncpy(ether_stat->version, BNX2X_DRIVER_VERSION,
3601                 ETH_STAT_INFO_VERSION_LEN);
3602
3603         sc->sp_objs[0].mac_obj.get_n_elements(sc, &sc->sp_objs[0].mac_obj,
3604                                               DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3605                                               ether_stat->mac_local + MAC_PAD,
3606                                               MAC_PAD, ETH_ALEN);
3607
3608         ether_stat->mtu_size = sc->mtu;
3609
3610         ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3611         ether_stat->promiscuous_mode = 0;       // (flags & PROMISC) ? 1 : 0;
3612
3613         ether_stat->txq_size = sc->tx_ring_size;
3614         ether_stat->rxq_size = sc->rx_ring_size;
3615 }
3616
3617 static void bnx2x_handle_drv_info_req(struct bnx2x_softc *sc)
3618 {
3619         enum drv_info_opcode op_code;
3620         uint32_t drv_info_ctl = SHMEM2_RD(sc, drv_info_control);
3621
3622         /* if drv_info version supported by MFW doesn't match - send NACK */
3623         if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3624                 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3625                 return;
3626         }
3627
3628         op_code = ((drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3629                    DRV_INFO_CONTROL_OP_CODE_SHIFT);
3630
3631         memset(&sc->sp->drv_info_to_mcp, 0, sizeof(union drv_info_to_mcp));
3632
3633         switch (op_code) {
3634         case ETH_STATS_OPCODE:
3635                 bnx2x_drv_info_ether_stat(sc);
3636                 break;
3637         case FCOE_STATS_OPCODE:
3638         case ISCSI_STATS_OPCODE:
3639         default:
3640                 /* if op code isn't supported - send NACK */
3641                 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3642                 return;
3643         }
3644
3645         /*
3646          * If we got drv_info attn from MFW then these fields are defined in
3647          * shmem2 for sure
3648          */
3649         SHMEM2_WR(sc, drv_info_host_addr_lo,
3650                   U64_LO(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3651         SHMEM2_WR(sc, drv_info_host_addr_hi,
3652                   U64_HI(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3653
3654         bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3655 }
3656
3657 static void bnx2x_dcc_event(struct bnx2x_softc *sc, uint32_t dcc_event)
3658 {
3659         if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3660 /*
3661  * This is the only place besides the function initialization
3662  * where the sc->flags can change so it is done without any
3663  * locks
3664  */
3665                 if (sc->devinfo.
3666                     mf_info.mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_DISABLED) {
3667                         PMD_DRV_LOG(DEBUG, sc, "mf_cfg function disabled");
3668                         sc->flags |= BNX2X_MF_FUNC_DIS;
3669                         bnx2x_e1h_disable(sc);
3670                 } else {
3671                         PMD_DRV_LOG(DEBUG, sc, "mf_cfg function enabled");
3672                         sc->flags &= ~BNX2X_MF_FUNC_DIS;
3673                         bnx2x_e1h_enable(sc);
3674                 }
3675                 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3676         }
3677
3678         if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3679                 bnx2x_config_mf_bw(sc);
3680                 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3681         }
3682
3683         /* Report results to MCP */
3684         if (dcc_event)
3685                 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_FAILURE, 0);
3686         else
3687                 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_OK, 0);
3688 }
3689
3690 static void bnx2x_pmf_update(struct bnx2x_softc *sc)
3691 {
3692         int port = SC_PORT(sc);
3693         uint32_t val;
3694
3695         sc->port.pmf = 1;
3696
3697         /*
3698          * We need the mb() to ensure the ordering between the writing to
3699          * sc->port.pmf here and reading it from the bnx2x_periodic_task().
3700          */
3701         mb();
3702
3703         /* enable nig attention */
3704         val = (0xff0f | (1 << (SC_VN(sc) + 4)));
3705         if (sc->devinfo.int_block == INT_BLOCK_HC) {
3706                 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, val);
3707                 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, val);
3708         } else if (!CHIP_IS_E1x(sc)) {
3709                 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
3710                 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
3711         }
3712
3713         bnx2x_stats_handle(sc, STATS_EVENT_PMF);
3714 }
3715
3716 static int bnx2x_mc_assert(struct bnx2x_softc *sc)
3717 {
3718         char last_idx;
3719         int i, rc = 0;
3720         __rte_unused uint32_t row0, row1, row2, row3;
3721
3722         /* XSTORM */
3723         last_idx =
3724             REG_RD8(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_INDEX_OFFSET);
3725         if (last_idx)
3726                 PMD_DRV_LOG(ERR, sc, "XSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3727
3728         /* print the asserts */
3729         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3730
3731                 row0 =
3732                     REG_RD(sc,
3733                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i));
3734                 row1 =
3735                     REG_RD(sc,
3736                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3737                            4);
3738                 row2 =
3739                     REG_RD(sc,
3740                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3741                            8);
3742                 row3 =
3743                     REG_RD(sc,
3744                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3745                            12);
3746
3747                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3748                         PMD_DRV_LOG(ERR, sc,
3749                                     "XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3750                                     i, row3, row2, row1, row0);
3751                         rc++;
3752                 } else {
3753                         break;
3754                 }
3755         }
3756
3757         /* TSTORM */
3758         last_idx =
3759             REG_RD8(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_INDEX_OFFSET);
3760         if (last_idx) {
3761                 PMD_DRV_LOG(ERR, sc, "TSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3762         }
3763
3764         /* print the asserts */
3765         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3766
3767                 row0 =
3768                     REG_RD(sc,
3769                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i));
3770                 row1 =
3771                     REG_RD(sc,
3772                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3773                            4);
3774                 row2 =
3775                     REG_RD(sc,
3776                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3777                            8);
3778                 row3 =
3779                     REG_RD(sc,
3780                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3781                            12);
3782
3783                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3784                         PMD_DRV_LOG(ERR, sc,
3785                                     "TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3786                                     i, row3, row2, row1, row0);
3787                         rc++;
3788                 } else {
3789                         break;
3790                 }
3791         }
3792
3793         /* CSTORM */
3794         last_idx =
3795             REG_RD8(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_INDEX_OFFSET);
3796         if (last_idx) {
3797                 PMD_DRV_LOG(ERR, sc, "CSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3798         }
3799
3800         /* print the asserts */
3801         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3802
3803                 row0 =
3804                     REG_RD(sc,
3805                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i));
3806                 row1 =
3807                     REG_RD(sc,
3808                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3809                            4);
3810                 row2 =
3811                     REG_RD(sc,
3812                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3813                            8);
3814                 row3 =
3815                     REG_RD(sc,
3816                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3817                            12);
3818
3819                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3820                         PMD_DRV_LOG(ERR, sc,
3821                                     "CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3822                                     i, row3, row2, row1, row0);
3823                         rc++;
3824                 } else {
3825                         break;
3826                 }
3827         }
3828
3829         /* USTORM */
3830         last_idx =
3831             REG_RD8(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_INDEX_OFFSET);
3832         if (last_idx) {
3833                 PMD_DRV_LOG(ERR, sc, "USTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3834         }
3835
3836         /* print the asserts */
3837         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3838
3839                 row0 =
3840                     REG_RD(sc,
3841                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i));
3842                 row1 =
3843                     REG_RD(sc,
3844                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3845                            4);
3846                 row2 =
3847                     REG_RD(sc,
3848                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3849                            8);
3850                 row3 =
3851                     REG_RD(sc,
3852                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3853                            12);
3854
3855                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3856                         PMD_DRV_LOG(ERR, sc,
3857                                     "USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3858                                     i, row3, row2, row1, row0);
3859                         rc++;
3860                 } else {
3861                         break;
3862                 }
3863         }
3864
3865         return rc;
3866 }
3867
3868 static void bnx2x_attn_int_deasserted3(struct bnx2x_softc *sc, uint32_t attn)
3869 {
3870         int func = SC_FUNC(sc);
3871         uint32_t val;
3872
3873         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3874
3875                 if (attn & BNX2X_PMF_LINK_ASSERT(sc)) {
3876
3877                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
3878                         bnx2x_read_mf_cfg(sc);
3879                         sc->devinfo.mf_info.mf_config[SC_VN(sc)] =
3880                             MFCFG_RD(sc,
3881                                      func_mf_config[SC_ABS_FUNC(sc)].config);
3882                         val =
3883                             SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_status);
3884
3885                         if (val & DRV_STATUS_DCC_EVENT_MASK)
3886                                 bnx2x_dcc_event(sc,
3887                                               (val &
3888                                                DRV_STATUS_DCC_EVENT_MASK));
3889
3890                         if (val & DRV_STATUS_SET_MF_BW)
3891                                 bnx2x_set_mf_bw(sc);
3892
3893                         if (val & DRV_STATUS_DRV_INFO_REQ)
3894                                 bnx2x_handle_drv_info_req(sc);
3895
3896                         if ((sc->port.pmf == 0) && (val & DRV_STATUS_PMF))
3897                                 bnx2x_pmf_update(sc);
3898
3899                         if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
3900                                 bnx2x_handle_eee_event(sc);
3901
3902                         if (sc->link_vars.periodic_flags &
3903                             ELINK_PERIODIC_FLAGS_LINK_EVENT) {
3904                                 /* sync with link */
3905                                 bnx2x_acquire_phy_lock(sc);
3906                                 sc->link_vars.periodic_flags &=
3907                                     ~ELINK_PERIODIC_FLAGS_LINK_EVENT;
3908                                 bnx2x_release_phy_lock(sc);
3909                                 if (IS_MF(sc)) {
3910                                         bnx2x_link_sync_notify(sc);
3911                                 }
3912                                 bnx2x_link_report(sc);
3913                         }
3914
3915                         /*
3916                          * Always call it here: bnx2x_link_report() will
3917                          * prevent the link indication duplication.
3918                          */
3919                         bnx2x_link_status_update(sc);
3920
3921                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3922
3923                         PMD_DRV_LOG(ERR, sc, "MC assert!");
3924                         bnx2x_mc_assert(sc);
3925                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3926                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3927                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3928                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3929                         rte_panic("MC assert!");
3930
3931                 } else if (attn & BNX2X_MCP_ASSERT) {
3932
3933                         PMD_DRV_LOG(ERR, sc, "MCP assert!");
3934                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3935
3936                 } else {
3937                         PMD_DRV_LOG(ERR, sc,
3938                                     "Unknown HW assert! (attn 0x%08x)", attn);
3939                 }
3940         }
3941
3942         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3943                 PMD_DRV_LOG(ERR, sc, "LATCHED attention 0x%08x (masked)", attn);
3944                 if (attn & BNX2X_GRC_TIMEOUT) {
3945                         val = REG_RD(sc, MISC_REG_GRC_TIMEOUT_ATTN);
3946                         PMD_DRV_LOG(ERR, sc, "GRC time-out 0x%08x", val);
3947                 }
3948                 if (attn & BNX2X_GRC_RSV) {
3949                         val = REG_RD(sc, MISC_REG_GRC_RSV_ATTN);
3950                         PMD_DRV_LOG(ERR, sc, "GRC reserved 0x%08x", val);
3951                 }
3952                 REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3953         }
3954 }
3955
3956 static void bnx2x_attn_int_deasserted2(struct bnx2x_softc *sc, uint32_t attn)
3957 {
3958         int port = SC_PORT(sc);
3959         int reg_offset;
3960         uint32_t val0, mask0, val1, mask1;
3961         uint32_t val;
3962
3963         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3964                 val = REG_RD(sc, CFC_REG_CFC_INT_STS_CLR);
3965                 PMD_DRV_LOG(ERR, sc, "CFC hw attention 0x%08x", val);
3966 /* CFC error attention */
3967                 if (val & 0x2) {
3968                         PMD_DRV_LOG(ERR, sc, "FATAL error from CFC");
3969                 }
3970         }
3971
3972         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3973                 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_0);
3974                 PMD_DRV_LOG(ERR, sc, "PXP hw attention-0 0x%08x", val);
3975 /* RQ_USDMDP_FIFO_OVERFLOW */
3976                 if (val & 0x18000) {
3977                         PMD_DRV_LOG(ERR, sc, "FATAL error from PXP");
3978                 }
3979
3980                 if (!CHIP_IS_E1x(sc)) {
3981                         val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_1);
3982                         PMD_DRV_LOG(ERR, sc, "PXP hw attention-1 0x%08x", val);
3983                 }
3984         }
3985 #define PXP2_EOP_ERROR_BIT  PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR
3986 #define AEU_PXP2_HW_INT_BIT AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT
3987
3988         if (attn & AEU_PXP2_HW_INT_BIT) {
3989 /*  CQ47854 workaround do not panic on
3990  *  PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3991  */
3992                 if (!CHIP_IS_E1x(sc)) {
3993                         mask0 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_0);
3994                         val1 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_1);
3995                         mask1 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_1);
3996                         val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_0);
3997                         /*
3998                          * If the only PXP2_EOP_ERROR_BIT is set in
3999                          * STS0 and STS1 - clear it
4000                          *
4001                          * probably we lose additional attentions between
4002                          * STS0 and STS_CLR0, in this case user will not
4003                          * be notified about them
4004                          */
4005                         if (val0 & mask0 & PXP2_EOP_ERROR_BIT &&
4006                             !(val1 & mask1))
4007                                 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
4008
4009                         /* print the register, since no one can restore it */
4010                         PMD_DRV_LOG(ERR, sc,
4011                                     "PXP2_REG_PXP2_INT_STS_CLR_0 0x%08x", val0);
4012
4013                         /*
4014                          * if PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
4015                          * then notify
4016                          */
4017                         if (val0 & PXP2_EOP_ERROR_BIT) {
4018                                 PMD_DRV_LOG(ERR, sc, "PXP2_WR_PGLUE_EOP_ERROR");
4019
4020                                 /*
4021                                  * if only PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR is
4022                                  * set then clear attention from PXP2 block without panic
4023                                  */
4024                                 if (((val0 & mask0) == PXP2_EOP_ERROR_BIT) &&
4025                                     ((val1 & mask1) == 0))
4026                                         attn &= ~AEU_PXP2_HW_INT_BIT;
4027                         }
4028                 }
4029         }
4030
4031         if (attn & HW_INTERRUT_ASSERT_SET_2) {
4032                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
4033                               MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
4034
4035                 val = REG_RD(sc, reg_offset);
4036                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
4037                 REG_WR(sc, reg_offset, val);
4038
4039                 PMD_DRV_LOG(ERR, sc,
4040                             "FATAL HW block attention set2 0x%x",
4041                             (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_2));
4042                 rte_panic("HW block attention set2");
4043         }
4044 }
4045
4046 static void bnx2x_attn_int_deasserted1(struct bnx2x_softc *sc, uint32_t attn)
4047 {
4048         int port = SC_PORT(sc);
4049         int reg_offset;
4050         uint32_t val;
4051
4052         if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
4053                 val = REG_RD(sc, DORQ_REG_DORQ_INT_STS_CLR);
4054                 PMD_DRV_LOG(ERR, sc, "DB hw attention 0x%08x", val);
4055 /* DORQ discard attention */
4056                 if (val & 0x2) {
4057                         PMD_DRV_LOG(ERR, sc, "FATAL error from DORQ");
4058                 }
4059         }
4060
4061         if (attn & HW_INTERRUT_ASSERT_SET_1) {
4062                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4063                               MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4064
4065                 val = REG_RD(sc, reg_offset);
4066                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4067                 REG_WR(sc, reg_offset, val);
4068
4069                 PMD_DRV_LOG(ERR, sc,
4070                             "FATAL HW block attention set1 0x%08x",
4071                             (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_1));
4072                 rte_panic("HW block attention set1");
4073         }
4074 }
4075
4076 static void bnx2x_attn_int_deasserted0(struct bnx2x_softc *sc, uint32_t attn)
4077 {
4078         int port = SC_PORT(sc);
4079         int reg_offset;
4080         uint32_t val;
4081
4082         reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4083             MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
4084
4085         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4086                 val = REG_RD(sc, reg_offset);
4087                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4088                 REG_WR(sc, reg_offset, val);
4089
4090                 PMD_DRV_LOG(WARNING, sc, "SPIO5 hw attention");
4091
4092 /* Fan failure attention */
4093                 elink_hw_reset_phy(&sc->link_params);
4094                 bnx2x_fan_failure(sc);
4095         }
4096
4097         if ((attn & sc->link_vars.aeu_int_mask) && sc->port.pmf) {
4098                 bnx2x_acquire_phy_lock(sc);
4099                 elink_handle_module_detect_int(&sc->link_params);
4100                 bnx2x_release_phy_lock(sc);
4101         }
4102
4103         if (attn & HW_INTERRUT_ASSERT_SET_0) {
4104                 val = REG_RD(sc, reg_offset);
4105                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4106                 REG_WR(sc, reg_offset, val);
4107
4108                 rte_panic("FATAL HW block attention set0 0x%lx",
4109                           (attn & (unsigned long)HW_INTERRUT_ASSERT_SET_0));
4110         }
4111 }
4112
4113 static void bnx2x_attn_int_deasserted(struct bnx2x_softc *sc, uint32_t deasserted)
4114 {
4115         struct attn_route attn;
4116         struct attn_route *group_mask;
4117         int port = SC_PORT(sc);
4118         int index;
4119         uint32_t reg_addr;
4120         uint32_t val;
4121         uint32_t aeu_mask;
4122         uint8_t global = FALSE;
4123
4124         /*
4125          * Need to take HW lock because MCP or other port might also
4126          * try to handle this event.
4127          */
4128         bnx2x_acquire_alr(sc);
4129
4130         if (bnx2x_chk_parity_attn(sc, &global, TRUE)) {
4131                 sc->recovery_state = BNX2X_RECOVERY_INIT;
4132
4133 /* disable HW interrupts */
4134                 bnx2x_int_disable(sc);
4135                 bnx2x_release_alr(sc);
4136                 return;
4137         }
4138
4139         attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
4140         attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
4141         attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
4142         attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
4143         if (!CHIP_IS_E1x(sc)) {
4144                 attn.sig[4] =
4145                     REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
4146         } else {
4147                 attn.sig[4] = 0;
4148         }
4149
4150         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4151                 if (deasserted & (1 << index)) {
4152                         group_mask = &sc->attn_group[index];
4153
4154                         bnx2x_attn_int_deasserted4(sc,
4155                                                  attn.
4156                                                  sig[4] & group_mask->sig[4]);
4157                         bnx2x_attn_int_deasserted3(sc,
4158                                                  attn.
4159                                                  sig[3] & group_mask->sig[3]);
4160                         bnx2x_attn_int_deasserted1(sc,
4161                                                  attn.
4162                                                  sig[1] & group_mask->sig[1]);
4163                         bnx2x_attn_int_deasserted2(sc,
4164                                                  attn.
4165                                                  sig[2] & group_mask->sig[2]);
4166                         bnx2x_attn_int_deasserted0(sc,
4167                                                  attn.
4168                                                  sig[0] & group_mask->sig[0]);
4169                 }
4170         }
4171
4172         bnx2x_release_alr(sc);
4173
4174         if (sc->devinfo.int_block == INT_BLOCK_HC) {
4175                 reg_addr = (HC_REG_COMMAND_REG + port * 32 +
4176                             COMMAND_REG_ATTN_BITS_CLR);
4177         } else {
4178                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER * 8);
4179         }
4180
4181         val = ~deasserted;
4182         PMD_DRV_LOG(DEBUG, sc,
4183                     "about to mask 0x%08x at %s addr 0x%08x", val,
4184                     (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
4185                     reg_addr);
4186         REG_WR(sc, reg_addr, val);
4187
4188         if (~sc->attn_state & deasserted) {
4189                 PMD_DRV_LOG(ERR, sc, "IGU error");
4190         }
4191
4192         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4193             MISC_REG_AEU_MASK_ATTN_FUNC_0;
4194
4195         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4196
4197         aeu_mask = REG_RD(sc, reg_addr);
4198
4199         aeu_mask |= (deasserted & 0x3ff);
4200
4201         REG_WR(sc, reg_addr, aeu_mask);
4202         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4203
4204         sc->attn_state &= ~deasserted;
4205 }
4206
4207 static void bnx2x_attn_int(struct bnx2x_softc *sc)
4208 {
4209         /* read local copy of bits */
4210         uint32_t attn_bits = le32toh(sc->def_sb->atten_status_block.attn_bits);
4211         uint32_t attn_ack =
4212             le32toh(sc->def_sb->atten_status_block.attn_bits_ack);
4213         uint32_t attn_state = sc->attn_state;
4214
4215         /* look for changed bits */
4216         uint32_t asserted = attn_bits & ~attn_ack & ~attn_state;
4217         uint32_t deasserted = ~attn_bits & attn_ack & attn_state;
4218
4219         PMD_DRV_LOG(DEBUG, sc,
4220                     "attn_bits 0x%08x attn_ack 0x%08x asserted 0x%08x deasserted 0x%08x",
4221                     attn_bits, attn_ack, asserted, deasserted);
4222
4223         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) {
4224                 PMD_DRV_LOG(ERR, sc, "BAD attention state");
4225         }
4226
4227         /* handle bits that were raised */
4228         if (asserted) {
4229                 bnx2x_attn_int_asserted(sc, asserted);
4230         }
4231
4232         if (deasserted) {
4233                 bnx2x_attn_int_deasserted(sc, deasserted);
4234         }
4235 }
4236
4237 static uint16_t bnx2x_update_dsb_idx(struct bnx2x_softc *sc)
4238 {
4239         struct host_sp_status_block *def_sb = sc->def_sb;
4240         uint16_t rc = 0;
4241
4242         if (!def_sb)
4243                 return 0;
4244
4245         mb();                   /* status block is written to by the chip */
4246
4247         if (sc->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
4248                 sc->def_att_idx = def_sb->atten_status_block.attn_bits_index;
4249                 rc |= BNX2X_DEF_SB_ATT_IDX;
4250         }
4251
4252         if (sc->def_idx != def_sb->sp_sb.running_index) {
4253                 sc->def_idx = def_sb->sp_sb.running_index;
4254                 rc |= BNX2X_DEF_SB_IDX;
4255         }
4256
4257         mb();
4258
4259         return rc;
4260 }
4261
4262 static struct ecore_queue_sp_obj *bnx2x_cid_to_q_obj(struct bnx2x_softc *sc,
4263                                                           uint32_t cid)
4264 {
4265         return &sc->sp_objs[CID_TO_FP(cid, sc)].q_obj;
4266 }
4267
4268 static void bnx2x_handle_mcast_eqe(struct bnx2x_softc *sc)
4269 {
4270         struct ecore_mcast_ramrod_params rparam;
4271         int rc;
4272
4273         memset(&rparam, 0, sizeof(rparam));
4274
4275         rparam.mcast_obj = &sc->mcast_obj;
4276
4277         /* clear pending state for the last command */
4278         sc->mcast_obj.raw.clear_pending(&sc->mcast_obj.raw);
4279
4280         /* if there are pending mcast commands - send them */
4281         if (sc->mcast_obj.check_pending(&sc->mcast_obj)) {
4282                 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
4283                 if (rc < 0) {
4284                         PMD_DRV_LOG(INFO, sc,
4285                                     "Failed to send pending mcast commands (%d)",
4286                                     rc);
4287                 }
4288         }
4289 }
4290
4291 static void
4292 bnx2x_handle_classification_eqe(struct bnx2x_softc *sc, union event_ring_elem *elem)
4293 {
4294         uint32_t ramrod_flags = 0;
4295         int rc = 0;
4296         uint32_t cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4297         struct ecore_vlan_mac_obj *vlan_mac_obj;
4298
4299         /* always push next commands out, don't wait here */
4300         rte_bit_relaxed_set32(RAMROD_CONT, &ramrod_flags);
4301
4302         switch (le32toh(elem->message.data.eth_event.echo) >> BNX2X_SWCID_SHIFT) {
4303         case ECORE_FILTER_MAC_PENDING:
4304                 PMD_DRV_LOG(DEBUG, sc, "Got SETUP_MAC completions");
4305                 vlan_mac_obj = &sc->sp_objs[cid].mac_obj;
4306                 break;
4307
4308         case ECORE_FILTER_MCAST_PENDING:
4309                 PMD_DRV_LOG(DEBUG, sc, "Got SETUP_MCAST completions");
4310                 bnx2x_handle_mcast_eqe(sc);
4311                 return;
4312
4313         default:
4314                 PMD_DRV_LOG(NOTICE, sc, "Unsupported classification command: %d",
4315                             elem->message.data.eth_event.echo);
4316                 return;
4317         }
4318
4319         rc = vlan_mac_obj->complete(sc, vlan_mac_obj, elem, &ramrod_flags);
4320
4321         if (rc < 0) {
4322                 PMD_DRV_LOG(NOTICE, sc,
4323                             "Failed to schedule new commands (%d)", rc);
4324         } else if (rc > 0) {
4325                 PMD_DRV_LOG(DEBUG, sc, "Scheduled next pending commands...");
4326         }
4327 }
4328
4329 static void bnx2x_handle_rx_mode_eqe(struct bnx2x_softc *sc)
4330 {
4331         rte_bit_relaxed_clear32(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
4332
4333         /* send rx_mode command again if was requested */
4334         if (rte_bit_relaxed_test_and_clear32(ECORE_FILTER_RX_MODE_SCHED,
4335                                                 &sc->sp_state))
4336                 bnx2x_set_storm_rx_mode(sc);
4337 }
4338
4339 static void bnx2x_update_eq_prod(struct bnx2x_softc *sc, uint16_t prod)
4340 {
4341         storm_memset_eq_prod(sc, prod, SC_FUNC(sc));
4342         wmb();                  /* keep prod updates ordered */
4343 }
4344
4345 static void bnx2x_eq_int(struct bnx2x_softc *sc)
4346 {
4347         uint16_t hw_cons, sw_cons, sw_prod;
4348         union event_ring_elem *elem;
4349         uint8_t echo;
4350         uint32_t cid;
4351         uint8_t opcode;
4352         int spqe_cnt = 0;
4353         struct ecore_queue_sp_obj *q_obj;
4354         struct ecore_func_sp_obj *f_obj = &sc->func_obj;
4355         struct ecore_raw_obj *rss_raw = &sc->rss_conf_obj.raw;
4356
4357         hw_cons = le16toh(*sc->eq_cons_sb);
4358
4359         /*
4360          * The hw_cons range is 1-255, 257 - the sw_cons range is 0-254, 256.
4361          * when we get to the next-page we need to adjust so the loop
4362          * condition below will be met. The next element is the size of a
4363          * regular element and hence incrementing by 1
4364          */
4365         if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) {
4366                 hw_cons++;
4367         }
4368
4369         /*
4370          * This function may never run in parallel with itself for a
4371          * specific sc and no need for a read memory barrier here.
4372          */
4373         sw_cons = sc->eq_cons;
4374         sw_prod = sc->eq_prod;
4375
4376         for (;
4377              sw_cons != hw_cons;
4378              sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4379
4380                 elem = &sc->eq[EQ_DESC(sw_cons)];
4381
4382 /* elem CID originates from FW, actually LE */
4383                 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4384                 opcode = elem->message.opcode;
4385
4386 /* handle eq element */
4387                 switch (opcode) {
4388                 case EVENT_RING_OPCODE_STAT_QUERY:
4389                         PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "got statistics completion event %d",
4390                                     sc->stats_comp++);
4391                         /* nothing to do with stats comp */
4392                         goto next_spqe;
4393
4394                 case EVENT_RING_OPCODE_CFC_DEL:
4395                         /* handle according to cid range */
4396                         /* we may want to verify here that the sc state is HALTING */
4397                         PMD_DRV_LOG(DEBUG, sc, "got delete ramrod for MULTI[%d]",
4398                                     cid);
4399                         q_obj = bnx2x_cid_to_q_obj(sc, cid);
4400                         if (q_obj->complete_cmd(sc, q_obj, ECORE_Q_CMD_CFC_DEL)) {
4401                                 break;
4402                         }
4403                         goto next_spqe;
4404
4405                 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4406                         PMD_DRV_LOG(DEBUG, sc, "got STOP TRAFFIC");
4407                         if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_STOP)) {
4408                                 break;
4409                         }
4410                         goto next_spqe;
4411
4412                 case EVENT_RING_OPCODE_START_TRAFFIC:
4413                         PMD_DRV_LOG(DEBUG, sc, "got START TRAFFIC");
4414                         if (f_obj->complete_cmd
4415                             (sc, f_obj, ECORE_F_CMD_TX_START)) {
4416                                 break;
4417                         }
4418                         goto next_spqe;
4419
4420                 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
4421                         echo = elem->message.data.function_update_event.echo;
4422                         if (echo == SWITCH_UPDATE) {
4423                                 PMD_DRV_LOG(DEBUG, sc,
4424                                             "got FUNC_SWITCH_UPDATE ramrod");
4425                                 if (f_obj->complete_cmd(sc, f_obj,
4426                                                         ECORE_F_CMD_SWITCH_UPDATE))
4427                                 {
4428                                         break;
4429                                 }
4430                         } else {
4431                                 PMD_DRV_LOG(DEBUG, sc,
4432                                             "AFEX: ramrod completed FUNCTION_UPDATE");
4433                                 f_obj->complete_cmd(sc, f_obj,
4434                                                     ECORE_F_CMD_AFEX_UPDATE);
4435                         }
4436                         goto next_spqe;
4437
4438                 case EVENT_RING_OPCODE_FORWARD_SETUP:
4439                         q_obj = &bnx2x_fwd_sp_obj(sc, q_obj);
4440                         if (q_obj->complete_cmd(sc, q_obj,
4441                                                 ECORE_Q_CMD_SETUP_TX_ONLY)) {
4442                                 break;
4443                         }
4444                         goto next_spqe;
4445
4446                 case EVENT_RING_OPCODE_FUNCTION_START:
4447                         PMD_DRV_LOG(DEBUG, sc, "got FUNC_START ramrod");
4448                         if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_START)) {
4449                                 break;
4450                         }
4451                         goto next_spqe;
4452
4453                 case EVENT_RING_OPCODE_FUNCTION_STOP:
4454                         PMD_DRV_LOG(DEBUG, sc, "got FUNC_STOP ramrod");
4455                         if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_STOP)) {
4456                                 break;
4457                         }
4458                         goto next_spqe;
4459                 }
4460
4461                 switch (opcode | sc->state) {
4462                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPEN):
4463                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPENING_WAITING_PORT):
4464                         cid =
4465                             elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4466                         PMD_DRV_LOG(DEBUG, sc, "got RSS_UPDATE ramrod. CID %d",
4467                                     cid);
4468                         rss_raw->clear_pending(rss_raw);
4469                         break;
4470
4471                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4472                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4473                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_CLOSING_WAITING_HALT):
4474                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_OPEN):
4475                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_DIAG):
4476                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4477                         PMD_DRV_LOG(DEBUG, sc,
4478                                     "got (un)set mac ramrod");
4479                         bnx2x_handle_classification_eqe(sc, elem);
4480                         break;
4481
4482                 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_OPEN):
4483                 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_DIAG):
4484                 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4485                         PMD_DRV_LOG(DEBUG, sc,
4486                                     "got mcast ramrod");
4487                         bnx2x_handle_mcast_eqe(sc);
4488                         break;
4489
4490                 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_OPEN):
4491                 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_DIAG):
4492                 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4493                         PMD_DRV_LOG(DEBUG, sc,
4494                                     "got rx_mode ramrod");
4495                         bnx2x_handle_rx_mode_eqe(sc);
4496                         break;
4497
4498                 default:
4499                         /* unknown event log error and continue */
4500                         PMD_DRV_LOG(INFO, sc, "Unknown EQ event %d, sc->state 0x%x",
4501                                     elem->message.opcode, sc->state);
4502                 }
4503
4504 next_spqe:
4505                 spqe_cnt++;
4506         }                       /* for */
4507
4508         mb();
4509         atomic_add_acq_long(&sc->eq_spq_left, spqe_cnt);
4510
4511         sc->eq_cons = sw_cons;
4512         sc->eq_prod = sw_prod;
4513
4514         /* make sure that above mem writes were issued towards the memory */
4515         wmb();
4516
4517         /* update producer */
4518         bnx2x_update_eq_prod(sc, sc->eq_prod);
4519 }
4520
4521 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc)
4522 {
4523         uint16_t status;
4524         int rc = 0;
4525
4526         PMD_DRV_LOG(DEBUG, sc, "---> SP TASK <---");
4527
4528         /* what work needs to be performed? */
4529         status = bnx2x_update_dsb_idx(sc);
4530
4531         PMD_DRV_LOG(DEBUG, sc, "dsb status 0x%04x", status);
4532
4533         /* HW attentions */
4534         if (status & BNX2X_DEF_SB_ATT_IDX) {
4535                 PMD_DRV_LOG(DEBUG, sc, "---> ATTN INTR <---");
4536                 bnx2x_attn_int(sc);
4537                 status &= ~BNX2X_DEF_SB_ATT_IDX;
4538                 rc = 1;
4539         }
4540
4541         /* SP events: STAT_QUERY and others */
4542         if (status & BNX2X_DEF_SB_IDX) {
4543 /* handle EQ completions */
4544                 PMD_DRV_LOG(DEBUG, sc, "---> EQ INTR <---");
4545                 bnx2x_eq_int(sc);
4546                 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
4547                            le16toh(sc->def_idx), IGU_INT_NOP, 1);
4548                 status &= ~BNX2X_DEF_SB_IDX;
4549         }
4550
4551         /* if status is non zero then something went wrong */
4552         if (unlikely(status)) {
4553                 PMD_DRV_LOG(INFO, sc,
4554                             "Got an unknown SP interrupt! (0x%04x)", status);
4555         }
4556
4557         /* ack status block only if something was actually handled */
4558         bnx2x_ack_sb(sc, sc->igu_dsb_id, ATTENTION_ID,
4559                    le16toh(sc->def_att_idx), IGU_INT_ENABLE, 1);
4560
4561         return rc;
4562 }
4563
4564 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp)
4565 {
4566         struct bnx2x_softc *sc = fp->sc;
4567         uint8_t more_rx = FALSE;
4568
4569         /* Make sure FP is initialized */
4570         if (!fp->sb_running_index)
4571                 return;
4572
4573         PMD_DEBUG_PERIODIC_LOG(DEBUG, sc,
4574                                "---> FP TASK QUEUE (%d) <--", fp->index);
4575
4576         /* update the fastpath index */
4577         bnx2x_update_fp_sb_idx(fp);
4578
4579         if (rte_atomic32_read(&sc->scan_fp) == 1) {
4580                 if (bnx2x_has_rx_work(fp)) {
4581                         more_rx = bnx2x_rxeof(sc, fp);
4582                 }
4583
4584                 if (more_rx) {
4585                         /* still more work to do */
4586                         bnx2x_handle_fp_tq(fp);
4587                         return;
4588                 }
4589                 /* We have completed slow path completion, clear the flag */
4590                 rte_atomic32_set(&sc->scan_fp, 0);
4591         }
4592
4593         bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
4594                    le16toh(fp->fp_hc_idx), IGU_INT_ENABLE, 1);
4595 }
4596
4597 /*
4598  * Legacy interrupt entry point.
4599  *
4600  * Verifies that the controller generated the interrupt and
4601  * then calls a separate routine to handle the various
4602  * interrupt causes: link, RX, and TX.
4603  */
4604 int bnx2x_intr_legacy(struct bnx2x_softc *sc)
4605 {
4606         struct bnx2x_fastpath *fp;
4607         uint32_t status, mask;
4608         int i, rc = 0;
4609
4610         /*
4611          * 0 for ustorm, 1 for cstorm
4612          * the bits returned from ack_int() are 0-15
4613          * bit 0 = attention status block
4614          * bit 1 = fast path status block
4615          * a mask of 0x2 or more = tx/rx event
4616          * a mask of 1 = slow path event
4617          */
4618
4619         status = bnx2x_ack_int(sc);
4620
4621         /* the interrupt is not for us */
4622         if (unlikely(status == 0)) {
4623                 return 0;
4624         }
4625
4626         PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "Interrupt status 0x%04x", status);
4627         //bnx2x_dump_status_block(sc);
4628
4629         FOR_EACH_ETH_QUEUE(sc, i) {
4630                 fp = &sc->fp[i];
4631                 mask = (0x2 << (fp->index + CNIC_SUPPORT(sc)));
4632                 if (status & mask) {
4633                 /* acknowledge and disable further fastpath interrupts */
4634                         bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
4635                                      0, IGU_INT_DISABLE, 0);
4636                         bnx2x_handle_fp_tq(fp);
4637                         status &= ~mask;
4638                 }
4639         }
4640
4641         if (unlikely(status & 0x1)) {
4642                 /* acknowledge and disable further slowpath interrupts */
4643                 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
4644                              0, IGU_INT_DISABLE, 0);
4645                 rc = bnx2x_handle_sp_tq(sc);
4646                 status &= ~0x1;
4647         }
4648
4649         if (unlikely(status)) {
4650                 PMD_DRV_LOG(WARNING, sc,
4651                             "Unexpected fastpath status (0x%08x)!", status);
4652         }
4653
4654         return rc;
4655 }
4656
4657 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc);
4658 static int bnx2x_init_hw_common(struct bnx2x_softc *sc);
4659 static int bnx2x_init_hw_port(struct bnx2x_softc *sc);
4660 static int bnx2x_init_hw_func(struct bnx2x_softc *sc);
4661 static void bnx2x_reset_common(struct bnx2x_softc *sc);
4662 static void bnx2x_reset_port(struct bnx2x_softc *sc);
4663 static void bnx2x_reset_func(struct bnx2x_softc *sc);
4664 static int bnx2x_init_firmware(struct bnx2x_softc *sc);
4665 static void bnx2x_release_firmware(struct bnx2x_softc *sc);
4666
4667 static struct
4668 ecore_func_sp_drv_ops bnx2x_func_sp_drv = {
4669         .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
4670         .init_hw_cmn = bnx2x_init_hw_common,
4671         .init_hw_port = bnx2x_init_hw_port,
4672         .init_hw_func = bnx2x_init_hw_func,
4673
4674         .reset_hw_cmn = bnx2x_reset_common,
4675         .reset_hw_port = bnx2x_reset_port,
4676         .reset_hw_func = bnx2x_reset_func,
4677
4678         .init_fw = bnx2x_init_firmware,
4679         .release_fw = bnx2x_release_firmware,
4680 };
4681
4682 static void bnx2x_init_func_obj(struct bnx2x_softc *sc)
4683 {
4684         sc->dmae_ready = 0;
4685
4686         PMD_INIT_FUNC_TRACE(sc);
4687
4688         ecore_init_func_obj(sc,
4689                             &sc->func_obj,
4690                             BNX2X_SP(sc, func_rdata),
4691                             (rte_iova_t)BNX2X_SP_MAPPING(sc, func_rdata),
4692                             BNX2X_SP(sc, func_afex_rdata),
4693                             (rte_iova_t)BNX2X_SP_MAPPING(sc, func_afex_rdata),
4694                             &bnx2x_func_sp_drv);
4695 }
4696
4697 static int bnx2x_init_hw(struct bnx2x_softc *sc, uint32_t load_code)
4698 {
4699         struct ecore_func_state_params func_params = { NULL };
4700         int rc;
4701
4702         PMD_INIT_FUNC_TRACE(sc);
4703
4704         /* prepare the parameters for function state transitions */
4705         rte_bit_relaxed_set32(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
4706
4707         func_params.f_obj = &sc->func_obj;
4708         func_params.cmd = ECORE_F_CMD_HW_INIT;
4709
4710         func_params.params.hw_init.load_phase = load_code;
4711
4712         /*
4713          * Via a plethora of function pointers, we will eventually reach
4714          * bnx2x_init_hw_common(), bnx2x_init_hw_port(), or bnx2x_init_hw_func().
4715          */
4716         rc = ecore_func_state_change(sc, &func_params);
4717
4718         return rc;
4719 }
4720
4721 static void
4722 bnx2x_fill(struct bnx2x_softc *sc, uint32_t addr, int fill, uint32_t len)
4723 {
4724         uint32_t i;
4725
4726         if (!(len % 4) && !(addr % 4)) {
4727                 for (i = 0; i < len; i += 4) {
4728                         REG_WR(sc, (addr + i), fill);
4729                 }
4730         } else {
4731                 for (i = 0; i < len; i++) {
4732                         REG_WR8(sc, (addr + i), fill);
4733                 }
4734         }
4735 }
4736
4737 /* writes FP SP data to FW - data_size in dwords */
4738 static void
4739 bnx2x_wr_fp_sb_data(struct bnx2x_softc *sc, int fw_sb_id, uint32_t * sb_data_p,
4740                   uint32_t data_size)
4741 {
4742         uint32_t index;
4743
4744         for (index = 0; index < data_size; index++) {
4745                 REG_WR(sc,
4746                        (BAR_CSTRORM_INTMEM +
4747                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
4748                         (sizeof(uint32_t) * index)), *(sb_data_p + index));
4749         }
4750 }
4751
4752 static void bnx2x_zero_fp_sb(struct bnx2x_softc *sc, int fw_sb_id)
4753 {
4754         struct hc_status_block_data_e2 sb_data_e2;
4755         struct hc_status_block_data_e1x sb_data_e1x;
4756         uint32_t *sb_data_p;
4757         uint32_t data_size = 0;
4758
4759         if (!CHIP_IS_E1x(sc)) {
4760                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4761                 sb_data_e2.common.state = SB_DISABLED;
4762                 sb_data_e2.common.p_func.vf_valid = FALSE;
4763                 sb_data_p = (uint32_t *) & sb_data_e2;
4764                 data_size = (sizeof(struct hc_status_block_data_e2) /
4765                              sizeof(uint32_t));
4766         } else {
4767                 memset(&sb_data_e1x, 0,
4768                        sizeof(struct hc_status_block_data_e1x));
4769                 sb_data_e1x.common.state = SB_DISABLED;
4770                 sb_data_e1x.common.p_func.vf_valid = FALSE;
4771                 sb_data_p = (uint32_t *) & sb_data_e1x;
4772                 data_size = (sizeof(struct hc_status_block_data_e1x) /
4773                              sizeof(uint32_t));
4774         }
4775
4776         bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4777
4778         bnx2x_fill(sc,
4779                  (BAR_CSTRORM_INTMEM + CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id)), 0,
4780                  CSTORM_STATUS_BLOCK_SIZE);
4781         bnx2x_fill(sc, (BAR_CSTRORM_INTMEM + CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id)),
4782                  0, CSTORM_SYNC_BLOCK_SIZE);
4783 }
4784
4785 static void
4786 bnx2x_wr_sp_sb_data(struct bnx2x_softc *sc,
4787                   struct hc_sp_status_block_data *sp_sb_data)
4788 {
4789         uint32_t i;
4790
4791         for (i = 0;
4792              i < (sizeof(struct hc_sp_status_block_data) / sizeof(uint32_t));
4793              i++) {
4794                 REG_WR(sc,
4795                        (BAR_CSTRORM_INTMEM +
4796                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(SC_FUNC(sc)) +
4797                         (i * sizeof(uint32_t))),
4798                        *((uint32_t *) sp_sb_data + i));
4799         }
4800 }
4801
4802 static void bnx2x_zero_sp_sb(struct bnx2x_softc *sc)
4803 {
4804         struct hc_sp_status_block_data sp_sb_data;
4805
4806         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4807
4808         sp_sb_data.state = SB_DISABLED;
4809         sp_sb_data.p_func.vf_valid = FALSE;
4810
4811         bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
4812
4813         bnx2x_fill(sc,
4814                  (BAR_CSTRORM_INTMEM +
4815                   CSTORM_SP_STATUS_BLOCK_OFFSET(SC_FUNC(sc))),
4816                  0, CSTORM_SP_STATUS_BLOCK_SIZE);
4817         bnx2x_fill(sc,
4818                  (BAR_CSTRORM_INTMEM +
4819                   CSTORM_SP_SYNC_BLOCK_OFFSET(SC_FUNC(sc))),
4820                  0, CSTORM_SP_SYNC_BLOCK_SIZE);
4821 }
4822
4823 static void
4824 bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, int igu_sb_id,
4825                              int igu_seg_id)
4826 {
4827         hc_sm->igu_sb_id = igu_sb_id;
4828         hc_sm->igu_seg_id = igu_seg_id;
4829         hc_sm->timer_value = 0xFF;
4830         hc_sm->time_to_expire = 0xFFFFFFFF;
4831 }
4832
4833 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
4834 {
4835         /* zero out state machine indices */
4836
4837         /* rx indices */
4838         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4839
4840         /* tx indices */
4841         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4842         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
4843         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
4844         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
4845
4846         /* map indices */
4847
4848         /* rx indices */
4849         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
4850             (SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4851
4852         /* tx indices */
4853         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
4854             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4855         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
4856             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4857         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
4858             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4859         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
4860             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4861 }
4862
4863 static void
4864 bnx2x_init_sb(struct bnx2x_softc *sc, rte_iova_t busaddr, int vfid,
4865             uint8_t vf_valid, int fw_sb_id, int igu_sb_id)
4866 {
4867         struct hc_status_block_data_e2 sb_data_e2;
4868         struct hc_status_block_data_e1x sb_data_e1x;
4869         struct hc_status_block_sm *hc_sm_p;
4870         uint32_t *sb_data_p;
4871         int igu_seg_id;
4872         int data_size;
4873
4874         if (CHIP_INT_MODE_IS_BC(sc)) {
4875                 igu_seg_id = HC_SEG_ACCESS_NORM;
4876         } else {
4877                 igu_seg_id = IGU_SEG_ACCESS_NORM;
4878         }
4879
4880         bnx2x_zero_fp_sb(sc, fw_sb_id);
4881
4882         if (!CHIP_IS_E1x(sc)) {
4883                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4884                 sb_data_e2.common.state = SB_ENABLED;
4885                 sb_data_e2.common.p_func.pf_id = SC_FUNC(sc);
4886                 sb_data_e2.common.p_func.vf_id = vfid;
4887                 sb_data_e2.common.p_func.vf_valid = vf_valid;
4888                 sb_data_e2.common.p_func.vnic_id = SC_VN(sc);
4889                 sb_data_e2.common.same_igu_sb_1b = TRUE;
4890                 sb_data_e2.common.host_sb_addr.hi = U64_HI(busaddr);
4891                 sb_data_e2.common.host_sb_addr.lo = U64_LO(busaddr);
4892                 hc_sm_p = sb_data_e2.common.state_machine;
4893                 sb_data_p = (uint32_t *) & sb_data_e2;
4894                 data_size = (sizeof(struct hc_status_block_data_e2) /
4895                              sizeof(uint32_t));
4896                 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
4897         } else {
4898                 memset(&sb_data_e1x, 0,
4899                        sizeof(struct hc_status_block_data_e1x));
4900                 sb_data_e1x.common.state = SB_ENABLED;
4901                 sb_data_e1x.common.p_func.pf_id = SC_FUNC(sc);
4902                 sb_data_e1x.common.p_func.vf_id = 0xff;
4903                 sb_data_e1x.common.p_func.vf_valid = FALSE;
4904                 sb_data_e1x.common.p_func.vnic_id = SC_VN(sc);
4905                 sb_data_e1x.common.same_igu_sb_1b = TRUE;
4906                 sb_data_e1x.common.host_sb_addr.hi = U64_HI(busaddr);
4907                 sb_data_e1x.common.host_sb_addr.lo = U64_LO(busaddr);
4908                 hc_sm_p = sb_data_e1x.common.state_machine;
4909                 sb_data_p = (uint32_t *) & sb_data_e1x;
4910                 data_size = (sizeof(struct hc_status_block_data_e1x) /
4911                              sizeof(uint32_t));
4912                 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
4913         }
4914
4915         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], igu_sb_id, igu_seg_id);
4916         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], igu_sb_id, igu_seg_id);
4917
4918         /* write indices to HW - PCI guarantees endianity of regpairs */
4919         bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4920 }
4921
4922 static uint8_t bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp)
4923 {
4924         if (CHIP_IS_E1x(fp->sc)) {
4925                 return fp->cl_id + SC_PORT(fp->sc) * ETH_MAX_RX_CLIENTS_E1H;
4926         } else {
4927                 return fp->cl_id;
4928         }
4929 }
4930
4931 static uint32_t
4932 bnx2x_rx_ustorm_prods_offset(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
4933 {
4934         uint32_t offset = BAR_USTRORM_INTMEM;
4935
4936         if (IS_VF(sc)) {
4937                 return PXP_VF_ADDR_USDM_QUEUES_START +
4938                         (sc->acquire_resp.resc.hw_qid[fp->index] *
4939                          sizeof(struct ustorm_queue_zone_data));
4940         } else if (!CHIP_IS_E1x(sc)) {
4941                 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
4942         } else {
4943                 offset += USTORM_RX_PRODS_E1X_OFFSET(SC_PORT(sc), fp->cl_id);
4944         }
4945
4946         return offset;
4947 }
4948
4949 static void bnx2x_init_eth_fp(struct bnx2x_softc *sc, int idx)
4950 {
4951         struct bnx2x_fastpath *fp = &sc->fp[idx];
4952         uint32_t cids[ECORE_MULTI_TX_COS] = { 0 };
4953         uint32_t q_type = 0;
4954         int cos;
4955
4956         fp->sc = sc;
4957         fp->index = idx;
4958
4959         fp->igu_sb_id = (sc->igu_base_sb + idx + CNIC_SUPPORT(sc));
4960         fp->fw_sb_id = (sc->base_fw_ndsb + idx + CNIC_SUPPORT(sc));
4961
4962         if (CHIP_IS_E1x(sc))
4963                 fp->cl_id = SC_L_ID(sc) + idx;
4964         else
4965 /* want client ID same as IGU SB ID for non-E1 */
4966                 fp->cl_id = fp->igu_sb_id;
4967         fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
4968
4969         /* setup sb indices */
4970         if (!CHIP_IS_E1x(sc)) {
4971                 fp->sb_index_values = fp->status_block.e2_sb->sb.index_values;
4972                 fp->sb_running_index = fp->status_block.e2_sb->sb.running_index;
4973         } else {
4974                 fp->sb_index_values = fp->status_block.e1x_sb->sb.index_values;
4975                 fp->sb_running_index =
4976                     fp->status_block.e1x_sb->sb.running_index;
4977         }
4978
4979         /* init shortcut */
4980         fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(sc, fp);
4981
4982         fp->rx_cq_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS];
4983
4984         for (cos = 0; cos < sc->max_cos; cos++) {
4985                 cids[cos] = idx;
4986         }
4987         fp->tx_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0];
4988
4989         /* nothing more for a VF to do */
4990         if (IS_VF(sc)) {
4991                 return;
4992         }
4993
4994         bnx2x_init_sb(sc, fp->sb_dma.paddr, BNX2X_VF_ID_INVALID, FALSE,
4995                     fp->fw_sb_id, fp->igu_sb_id);
4996
4997         bnx2x_update_fp_sb_idx(fp);
4998
4999         /* Configure Queue State object */
5000         rte_bit_relaxed_set32(ECORE_Q_TYPE_HAS_RX, &q_type);
5001         rte_bit_relaxed_set32(ECORE_Q_TYPE_HAS_TX, &q_type);
5002
5003         ecore_init_queue_obj(sc,
5004                              &sc->sp_objs[idx].q_obj,
5005                              fp->cl_id,
5006                              cids,
5007                              sc->max_cos,
5008                              SC_FUNC(sc),
5009                              BNX2X_SP(sc, q_rdata),
5010                              (rte_iova_t)BNX2X_SP_MAPPING(sc, q_rdata),
5011                              q_type);
5012
5013         /* configure classification DBs */
5014         ecore_init_mac_obj(sc,
5015                            &sc->sp_objs[idx].mac_obj,
5016                            fp->cl_id,
5017                            idx,
5018                            SC_FUNC(sc),
5019                            BNX2X_SP(sc, mac_rdata),
5020                            (rte_iova_t)BNX2X_SP_MAPPING(sc, mac_rdata),
5021                            ECORE_FILTER_MAC_PENDING, &sc->sp_state,
5022                            ECORE_OBJ_TYPE_RX_TX, &sc->macs_pool);
5023 }
5024
5025 static void
5026 bnx2x_update_rx_prod(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
5027                    uint16_t rx_bd_prod, uint16_t rx_cq_prod)
5028 {
5029         struct ustorm_eth_rx_producers rx_prods;
5030         uint32_t i;
5031
5032         memset(&rx_prods, 0, sizeof(rx_prods));
5033
5034         /* update producers */
5035         rx_prods.bd_prod = rx_bd_prod;
5036         rx_prods.cqe_prod = rx_cq_prod;
5037
5038         /*
5039          * Make sure that the BD and SGE data is updated before updating the
5040          * producers since FW might read the BD/SGE right after the producer
5041          * is updated.
5042          * This is only applicable for weak-ordered memory model archs such
5043          * as IA-64. The following barrier is also mandatory since FW will
5044          * assumes BDs must have buffers.
5045          */
5046         wmb();
5047
5048         for (i = 0; i < (sizeof(rx_prods) / 4); i++) {
5049                 REG_WR(sc, (fp->ustorm_rx_prods_offset + (i * 4)),
5050                        ((uint32_t *)&rx_prods)[i]);
5051         }
5052
5053         wmb();                  /* keep prod updates ordered */
5054 }
5055
5056 static void bnx2x_init_rx_rings(struct bnx2x_softc *sc)
5057 {
5058         struct bnx2x_fastpath *fp;
5059         int i;
5060         struct bnx2x_rx_queue *rxq;
5061
5062         for (i = 0; i < sc->num_queues; i++) {
5063                 fp = &sc->fp[i];
5064                 rxq = sc->rx_queues[fp->index];
5065                 if (!rxq) {
5066                         PMD_RX_LOG(ERR, "RX queue is NULL");
5067                         return;
5068                 }
5069
5070                 rxq->rx_bd_head = 0;
5071                 rxq->rx_bd_tail = rxq->nb_rx_desc;
5072                 rxq->rx_cq_head = 0;
5073                 rxq->rx_cq_tail = TOTAL_RCQ_ENTRIES(rxq);
5074                 *fp->rx_cq_cons_sb = 0;
5075
5076                 /*
5077                  * Activate the BD ring...
5078                  * Warning, this will generate an interrupt (to the TSTORM)
5079                  * so this can only be done after the chip is initialized
5080                  */
5081                 bnx2x_update_rx_prod(sc, fp, rxq->rx_bd_tail, rxq->rx_cq_tail);
5082
5083                 if (i != 0) {
5084                         continue;
5085                 }
5086         }
5087 }
5088
5089 static void bnx2x_init_tx_ring_one(struct bnx2x_fastpath *fp)
5090 {
5091         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
5092
5093         fp->tx_db.data.header.header = 1 << DOORBELL_HDR_DB_TYPE_SHIFT;
5094         fp->tx_db.data.zero_fill1 = 0;
5095         fp->tx_db.data.prod = 0;
5096
5097         if (!txq) {
5098                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
5099                 return;
5100         }
5101
5102         txq->tx_pkt_tail = 0;
5103         txq->tx_pkt_head = 0;
5104         txq->tx_bd_tail = 0;
5105         txq->tx_bd_head = 0;
5106 }
5107
5108 static void bnx2x_init_tx_rings(struct bnx2x_softc *sc)
5109 {
5110         int i;
5111
5112         for (i = 0; i < sc->num_queues; i++) {
5113                 bnx2x_init_tx_ring_one(&sc->fp[i]);
5114         }
5115 }
5116
5117 static void bnx2x_init_def_sb(struct bnx2x_softc *sc)
5118 {
5119         struct host_sp_status_block *def_sb = sc->def_sb;
5120         rte_iova_t mapping = sc->def_sb_dma.paddr;
5121         int igu_sp_sb_index;
5122         int igu_seg_id;
5123         int port = SC_PORT(sc);
5124         int func = SC_FUNC(sc);
5125         int reg_offset, reg_offset_en5;
5126         uint64_t section;
5127         int index, sindex;
5128         struct hc_sp_status_block_data sp_sb_data;
5129
5130         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5131
5132         if (CHIP_INT_MODE_IS_BC(sc)) {
5133                 igu_sp_sb_index = DEF_SB_IGU_ID;
5134                 igu_seg_id = HC_SEG_ACCESS_DEF;
5135         } else {
5136                 igu_sp_sb_index = sc->igu_dsb_id;
5137                 igu_seg_id = IGU_SEG_ACCESS_DEF;
5138         }
5139
5140         /* attentions */
5141         section = ((uint64_t) mapping +
5142                    offsetof(struct host_sp_status_block, atten_status_block));
5143         def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5144         sc->attn_state = 0;
5145
5146         reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5147             MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
5148
5149         reg_offset_en5 = (port) ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5150             MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0;
5151
5152         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5153 /* take care of sig[0]..sig[4] */
5154                 for (sindex = 0; sindex < 4; sindex++) {
5155                         sc->attn_group[index].sig[sindex] =
5156                             REG_RD(sc,
5157                                    (reg_offset + (sindex * 0x4) +
5158                                     (0x10 * index)));
5159                 }
5160
5161                 if (!CHIP_IS_E1x(sc)) {
5162                         /*
5163                          * enable5 is separate from the rest of the registers,
5164                          * and the address skip is 4 and not 16 between the
5165                          * different groups
5166                          */
5167                         sc->attn_group[index].sig[4] =
5168                             REG_RD(sc, (reg_offset_en5 + (0x4 * index)));
5169                 } else {
5170                         sc->attn_group[index].sig[4] = 0;
5171                 }
5172         }
5173
5174         if (sc->devinfo.int_block == INT_BLOCK_HC) {
5175                 reg_offset =
5176                     port ? HC_REG_ATTN_MSG1_ADDR_L : HC_REG_ATTN_MSG0_ADDR_L;
5177                 REG_WR(sc, reg_offset, U64_LO(section));
5178                 REG_WR(sc, (reg_offset + 4), U64_HI(section));
5179         } else if (!CHIP_IS_E1x(sc)) {
5180                 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5181                 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5182         }
5183
5184         section = ((uint64_t) mapping +
5185                    offsetof(struct host_sp_status_block, sp_sb));
5186
5187         bnx2x_zero_sp_sb(sc);
5188
5189         /* PCI guarantees endianity of regpair */
5190         sp_sb_data.state = SB_ENABLED;
5191         sp_sb_data.host_sb_addr.lo = U64_LO(section);
5192         sp_sb_data.host_sb_addr.hi = U64_HI(section);
5193         sp_sb_data.igu_sb_id = igu_sp_sb_index;
5194         sp_sb_data.igu_seg_id = igu_seg_id;
5195         sp_sb_data.p_func.pf_id = func;
5196         sp_sb_data.p_func.vnic_id = SC_VN(sc);
5197         sp_sb_data.p_func.vf_id = 0xff;
5198
5199         bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
5200
5201         bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5202 }
5203
5204 static void bnx2x_init_sp_ring(struct bnx2x_softc *sc)
5205 {
5206         atomic_store_rel_long(&sc->cq_spq_left, MAX_SPQ_PENDING);
5207         sc->spq_prod_idx = 0;
5208         sc->dsb_sp_prod =
5209             &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_ETH_DEF_CONS];
5210         sc->spq_prod_bd = sc->spq;
5211         sc->spq_last_bd = (sc->spq_prod_bd + MAX_SP_DESC_CNT);
5212 }
5213
5214 static void bnx2x_init_eq_ring(struct bnx2x_softc *sc)
5215 {
5216         union event_ring_elem *elem;
5217         int i;
5218
5219         for (i = 1; i <= NUM_EQ_PAGES; i++) {
5220                 elem = &sc->eq[EQ_DESC_CNT_PAGE * i - 1];
5221
5222                 elem->next_page.addr.hi = htole32(U64_HI(sc->eq_dma.paddr +
5223                                                          BNX2X_PAGE_SIZE *
5224                                                          (i % NUM_EQ_PAGES)));
5225                 elem->next_page.addr.lo = htole32(U64_LO(sc->eq_dma.paddr +
5226                                                          BNX2X_PAGE_SIZE *
5227                                                          (i % NUM_EQ_PAGES)));
5228         }
5229
5230         sc->eq_cons = 0;
5231         sc->eq_prod = NUM_EQ_DESC;
5232         sc->eq_cons_sb = &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_EQ_CONS];
5233
5234         atomic_store_rel_long(&sc->eq_spq_left,
5235                               (min((MAX_SP_DESC_CNT - MAX_SPQ_PENDING),
5236                                    NUM_EQ_DESC) - 1));
5237 }
5238
5239 static void bnx2x_init_internal_common(struct bnx2x_softc *sc)
5240 {
5241         int i;
5242
5243         /*
5244          * Zero this manually as its initialization is currently missing
5245          * in the initTool.
5246          */
5247         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) {
5248                 REG_WR(sc,
5249                        (BAR_USTRORM_INTMEM + USTORM_AGG_DATA_OFFSET + (i * 4)),
5250                        0);
5251         }
5252
5253         if (!CHIP_IS_E1x(sc)) {
5254                 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET),
5255                         CHIP_INT_MODE_IS_BC(sc) ? HC_IGU_BC_MODE :
5256                         HC_IGU_NBC_MODE);
5257         }
5258 }
5259
5260 static void bnx2x_init_internal(struct bnx2x_softc *sc, uint32_t load_code)
5261 {
5262         switch (load_code) {
5263         case FW_MSG_CODE_DRV_LOAD_COMMON:
5264         case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5265                 bnx2x_init_internal_common(sc);
5266                 /* no break */
5267
5268         case FW_MSG_CODE_DRV_LOAD_PORT:
5269                 /* nothing to do */
5270                 /* no break */
5271
5272         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5273                 /* internal memory per function is initialized inside bnx2x_pf_init */
5274                 break;
5275
5276         default:
5277                 PMD_DRV_LOG(NOTICE, sc, "Unknown load_code (0x%x) from MCP",
5278                             load_code);
5279                 break;
5280         }
5281 }
5282
5283 static void
5284 storm_memset_func_cfg(struct bnx2x_softc *sc,
5285                       struct tstorm_eth_function_common_config *tcfg,
5286                       uint16_t abs_fid)
5287 {
5288         uint32_t addr;
5289         size_t size;
5290
5291         addr = (BAR_TSTRORM_INTMEM +
5292                 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid));
5293         size = sizeof(struct tstorm_eth_function_common_config);
5294         ecore_storm_memset_struct(sc, addr, size, (uint32_t *) tcfg);
5295 }
5296
5297 static void bnx2x_func_init(struct bnx2x_softc *sc, struct bnx2x_func_init_params *p)
5298 {
5299         struct tstorm_eth_function_common_config tcfg = { 0 };
5300
5301         if (CHIP_IS_E1x(sc)) {
5302                 storm_memset_func_cfg(sc, &tcfg, p->func_id);
5303         }
5304
5305         /* Enable the function in the FW */
5306         storm_memset_vf_to_pf(sc, p->func_id, p->pf_id);
5307         storm_memset_func_en(sc, p->func_id, 1);
5308
5309         /* spq */
5310         if (p->func_flgs & FUNC_FLG_SPQ) {
5311                 storm_memset_spq_addr(sc, p->spq_map, p->func_id);
5312                 REG_WR(sc,
5313                        (XSEM_REG_FAST_MEMORY +
5314                         XSTORM_SPQ_PROD_OFFSET(p->func_id)), p->spq_prod);
5315         }
5316 }
5317
5318 /*
5319  * Calculates the sum of vn_min_rates.
5320  * It's needed for further normalizing of the min_rates.
5321  * Returns:
5322  *   sum of vn_min_rates.
5323  *     or
5324  *   0 - if all the min_rates are 0.
5325  * In the later case fainess algorithm should be deactivated.
5326  * If all min rates are not zero then those that are zeroes will be set to 1.
5327  */
5328 static void bnx2x_calc_vn_min(struct bnx2x_softc *sc, struct cmng_init_input *input)
5329 {
5330         uint32_t vn_cfg;
5331         uint32_t vn_min_rate;
5332         int all_zero = 1;
5333         int vn;
5334
5335         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5336                 vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5337                 vn_min_rate = (((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
5338                                 FUNC_MF_CFG_MIN_BW_SHIFT) * 100);
5339
5340                 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5341                         /* skip hidden VNs */
5342                         vn_min_rate = 0;
5343                 } else if (!vn_min_rate) {
5344                         /* If min rate is zero - set it to 100 */
5345                         vn_min_rate = DEF_MIN_RATE;
5346                 } else {
5347                         all_zero = 0;
5348                 }
5349
5350                 input->vnic_min_rate[vn] = vn_min_rate;
5351         }
5352
5353         /* if ETS or all min rates are zeros - disable fairness */
5354         if (all_zero) {
5355                 input->flags.cmng_enables &= ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5356         } else {
5357                 input->flags.cmng_enables |= CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5358         }
5359 }
5360
5361 static uint16_t
5362 bnx2x_extract_max_cfg(__rte_unused struct bnx2x_softc *sc, uint32_t mf_cfg)
5363 {
5364         uint16_t max_cfg = ((mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
5365                             FUNC_MF_CFG_MAX_BW_SHIFT);
5366
5367         if (!max_cfg) {
5368                 PMD_DRV_LOG(DEBUG, sc,
5369                             "Max BW configured to 0 - using 100 instead");
5370                 max_cfg = 100;
5371         }
5372
5373         return max_cfg;
5374 }
5375
5376 static void
5377 bnx2x_calc_vn_max(struct bnx2x_softc *sc, int vn, struct cmng_init_input *input)
5378 {
5379         uint16_t vn_max_rate;
5380         uint32_t vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5381         uint32_t max_cfg;
5382
5383         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5384                 vn_max_rate = 0;
5385         } else {
5386                 max_cfg = bnx2x_extract_max_cfg(sc, vn_cfg);
5387
5388                 if (IS_MF_SI(sc)) {
5389                         /* max_cfg in percents of linkspeed */
5390                         vn_max_rate =
5391                             ((sc->link_vars.line_speed * max_cfg) / 100);
5392                 } else {        /* SD modes */
5393                         /* max_cfg is absolute in 100Mb units */
5394                         vn_max_rate = (max_cfg * 100);
5395                 }
5396         }
5397
5398         input->vnic_max_rate[vn] = vn_max_rate;
5399 }
5400
5401 static void
5402 bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg, uint8_t cmng_type)
5403 {
5404         struct cmng_init_input input;
5405         int vn;
5406
5407         memset(&input, 0, sizeof(struct cmng_init_input));
5408
5409         input.port_rate = sc->link_vars.line_speed;
5410
5411         if (cmng_type == CMNG_FNS_MINMAX) {
5412 /* read mf conf from shmem */
5413                 if (read_cfg) {
5414                         bnx2x_read_mf_cfg(sc);
5415                 }
5416
5417 /* get VN min rate and enable fairness if not 0 */
5418                 bnx2x_calc_vn_min(sc, &input);
5419
5420 /* get VN max rate */
5421                 if (sc->port.pmf) {
5422                         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5423                                 bnx2x_calc_vn_max(sc, vn, &input);
5424                         }
5425                 }
5426
5427 /* always enable rate shaping and fairness */
5428                 input.flags.cmng_enables |= CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
5429
5430                 ecore_init_cmng(&input, &sc->cmng);
5431                 return;
5432         }
5433 }
5434
5435 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc)
5436 {
5437         if (CHIP_REV_IS_SLOW(sc)) {
5438                 return CMNG_FNS_NONE;
5439         }
5440
5441         if (IS_MF(sc)) {
5442                 return CMNG_FNS_MINMAX;
5443         }
5444
5445         return CMNG_FNS_NONE;
5446 }
5447
5448 static void
5449 storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng, uint8_t port)
5450 {
5451         int vn;
5452         int func;
5453         uint32_t addr;
5454         size_t size;
5455
5456         addr = (BAR_XSTRORM_INTMEM + XSTORM_CMNG_PER_PORT_VARS_OFFSET(port));
5457         size = sizeof(struct cmng_struct_per_port);
5458         ecore_storm_memset_struct(sc, addr, size, (uint32_t *) & cmng->port);
5459
5460         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5461                 func = func_by_vn(sc, vn);
5462
5463                 addr = (BAR_XSTRORM_INTMEM +
5464                         XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func));
5465                 size = sizeof(struct rate_shaping_vars_per_vn);
5466                 ecore_storm_memset_struct(sc, addr, size,
5467                                           (uint32_t *) & cmng->
5468                                           vnic.vnic_max_rate[vn]);
5469
5470                 addr = (BAR_XSTRORM_INTMEM +
5471                         XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func));
5472                 size = sizeof(struct fairness_vars_per_vn);
5473                 ecore_storm_memset_struct(sc, addr, size,
5474                                           (uint32_t *) & cmng->
5475                                           vnic.vnic_min_rate[vn]);
5476         }
5477 }
5478
5479 static void bnx2x_pf_init(struct bnx2x_softc *sc)
5480 {
5481         struct bnx2x_func_init_params func_init;
5482         struct event_ring_data eq_data;
5483         uint16_t flags;
5484
5485         memset(&eq_data, 0, sizeof(struct event_ring_data));
5486         memset(&func_init, 0, sizeof(struct bnx2x_func_init_params));
5487
5488         if (!CHIP_IS_E1x(sc)) {
5489 /* reset IGU PF statistics: MSIX + ATTN */
5490 /* PF */
5491                 REG_WR(sc,
5492                        (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5493                         (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5494                         ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5495                          4)), 0);
5496 /* ATTN */
5497                 REG_WR(sc,
5498                        (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5499                         (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5500                         (BNX2X_IGU_STAS_MSG_PF_CNT * 4) +
5501                         ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5502                          4)), 0);
5503         }
5504
5505         /* function setup flags */
5506         flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
5507
5508         func_init.func_flgs = flags;
5509         func_init.pf_id = SC_FUNC(sc);
5510         func_init.func_id = SC_FUNC(sc);
5511         func_init.spq_map = sc->spq_dma.paddr;
5512         func_init.spq_prod = sc->spq_prod_idx;
5513
5514         bnx2x_func_init(sc, &func_init);
5515
5516         memset(&sc->cmng, 0, sizeof(struct cmng_struct_per_port));
5517
5518         /*
5519          * Congestion management values depend on the link rate.
5520          * There is no active link so initial link rate is set to 10Gbps.
5521          * When the link comes up the congestion management values are
5522          * re-calculated according to the actual link rate.
5523          */
5524         sc->link_vars.line_speed = SPEED_10000;
5525         bnx2x_cmng_fns_init(sc, TRUE, bnx2x_get_cmng_fns_mode(sc));
5526
5527         /* Only the PMF sets the HW */
5528         if (sc->port.pmf) {
5529                 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
5530         }
5531
5532         /* init Event Queue - PCI bus guarantees correct endainity */
5533         eq_data.base_addr.hi = U64_HI(sc->eq_dma.paddr);
5534         eq_data.base_addr.lo = U64_LO(sc->eq_dma.paddr);
5535         eq_data.producer = sc->eq_prod;
5536         eq_data.index_id = HC_SP_INDEX_EQ_CONS;
5537         eq_data.sb_id = DEF_SB_ID;
5538         storm_memset_eq_data(sc, &eq_data, SC_FUNC(sc));
5539 }
5540
5541 static void bnx2x_hc_int_enable(struct bnx2x_softc *sc)
5542 {
5543         int port = SC_PORT(sc);
5544         uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5545         uint32_t val = REG_RD(sc, addr);
5546         uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5547             || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5548         uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5549         uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5550
5551         if (msix) {
5552                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5553                          HC_CONFIG_0_REG_INT_LINE_EN_0);
5554                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5555                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5556                 if (single_msix) {
5557                         val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
5558                 }
5559         } else if (msi) {
5560                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
5561                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5562                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5563                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5564         } else {
5565                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5566                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5567                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
5568                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5569
5570                 REG_WR(sc, addr, val);
5571
5572                 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
5573         }
5574
5575         REG_WR(sc, addr, val);
5576
5577         /* ensure that HC_CONFIG is written before leading/trailing edge config */
5578         mb();
5579
5580         /* init leading/trailing edge */
5581         if (IS_MF(sc)) {
5582                 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5583                 if (sc->port.pmf) {
5584                         /* enable nig and gpio3 attention */
5585                         val |= 0x1100;
5586                 }
5587         } else {
5588                 val = 0xffff;
5589         }
5590
5591         REG_WR(sc, (HC_REG_TRAILING_EDGE_0 + port * 8), val);
5592         REG_WR(sc, (HC_REG_LEADING_EDGE_0 + port * 8), val);
5593
5594         /* make sure that interrupts are indeed enabled from here on */
5595         mb();
5596 }
5597
5598 static void bnx2x_igu_int_enable(struct bnx2x_softc *sc)
5599 {
5600         uint32_t val;
5601         uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5602             || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5603         uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5604         uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5605
5606         val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5607
5608         if (msix) {
5609                 val &= ~(IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5610                 val |= (IGU_PF_CONF_MSI_MSIX_EN | IGU_PF_CONF_ATTN_BIT_EN);
5611                 if (single_msix) {
5612                         val |= IGU_PF_CONF_SINGLE_ISR_EN;
5613                 }
5614         } else if (msi) {
5615                 val &= ~IGU_PF_CONF_INT_LINE_EN;
5616                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
5617                         IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5618         } else {
5619                 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
5620                 val |= (IGU_PF_CONF_INT_LINE_EN |
5621                         IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5622         }
5623
5624         /* clean previous status - need to configure igu prior to ack */
5625         if ((!msix) || single_msix) {
5626                 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5627                 bnx2x_ack_int(sc);
5628         }
5629
5630         val |= IGU_PF_CONF_FUNC_EN;
5631
5632         PMD_DRV_LOG(DEBUG, sc, "write 0x%x to IGU mode %s",
5633                     val, ((msix) ? "MSI-X" : ((msi) ? "MSI" : "INTx")));
5634
5635         REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5636
5637         mb();
5638
5639         /* init leading/trailing edge */
5640         if (IS_MF(sc)) {
5641                 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5642                 if (sc->port.pmf) {
5643                         /* enable nig and gpio3 attention */
5644                         val |= 0x1100;
5645                 }
5646         } else {
5647                 val = 0xffff;
5648         }
5649
5650         REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
5651         REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
5652
5653         /* make sure that interrupts are indeed enabled from here on */
5654         mb();
5655 }
5656
5657 static void bnx2x_int_enable(struct bnx2x_softc *sc)
5658 {
5659         if (sc->devinfo.int_block == INT_BLOCK_HC) {
5660                 bnx2x_hc_int_enable(sc);
5661         } else {
5662                 bnx2x_igu_int_enable(sc);
5663         }
5664 }
5665
5666 static void bnx2x_hc_int_disable(struct bnx2x_softc *sc)
5667 {
5668         int port = SC_PORT(sc);
5669         uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5670         uint32_t val = REG_RD(sc, addr);
5671
5672         val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5673                  HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5674                  HC_CONFIG_0_REG_INT_LINE_EN_0 | HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5675         /* flush all outstanding writes */
5676         mb();
5677
5678         REG_WR(sc, addr, val);
5679         if (REG_RD(sc, addr) != val) {
5680                 PMD_DRV_LOG(ERR, sc, "proper val not read from HC IGU!");
5681         }
5682 }
5683
5684 static void bnx2x_igu_int_disable(struct bnx2x_softc *sc)
5685 {
5686         uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5687
5688         val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
5689                  IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_ATTN_BIT_EN);
5690
5691         PMD_DRV_LOG(DEBUG, sc, "write %x to IGU", val);
5692
5693         /* flush all outstanding writes */
5694         mb();
5695
5696         REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5697         if (REG_RD(sc, IGU_REG_PF_CONFIGURATION) != val) {
5698                 PMD_DRV_LOG(ERR, sc, "proper val not read from IGU!");
5699         }
5700 }
5701
5702 static void bnx2x_int_disable(struct bnx2x_softc *sc)
5703 {
5704         if (sc->devinfo.int_block == INT_BLOCK_HC) {
5705                 bnx2x_hc_int_disable(sc);
5706         } else {
5707                 bnx2x_igu_int_disable(sc);
5708         }
5709 }
5710
5711 static void bnx2x_nic_init(struct bnx2x_softc *sc, int load_code)
5712 {
5713         int i;
5714
5715         PMD_INIT_FUNC_TRACE(sc);
5716
5717         for (i = 0; i < sc->num_queues; i++) {
5718                 bnx2x_init_eth_fp(sc, i);
5719         }
5720
5721         rmb();                  /* ensure status block indices were read */
5722
5723         bnx2x_init_rx_rings(sc);
5724         bnx2x_init_tx_rings(sc);
5725
5726         if (IS_VF(sc)) {
5727                 bnx2x_memset_stats(sc);
5728                 return;
5729         }
5730
5731         /* initialize MOD_ABS interrupts */
5732         elink_init_mod_abs_int(sc, &sc->link_vars,
5733                                sc->devinfo.chip_id,
5734                                sc->devinfo.shmem_base,
5735                                sc->devinfo.shmem2_base, SC_PORT(sc));
5736
5737         bnx2x_init_def_sb(sc);
5738         bnx2x_update_dsb_idx(sc);
5739         bnx2x_init_sp_ring(sc);
5740         bnx2x_init_eq_ring(sc);
5741         bnx2x_init_internal(sc, load_code);
5742         bnx2x_pf_init(sc);
5743         bnx2x_stats_init(sc);
5744
5745         /* flush all before enabling interrupts */
5746         mb();
5747
5748         bnx2x_int_enable(sc);
5749
5750         /* check for SPIO5 */
5751         bnx2x_attn_int_deasserted0(sc,
5752                                  REG_RD(sc,
5753                                         (MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
5754                                          SC_PORT(sc) * 4)) &
5755                                  AEU_INPUTS_ATTN_BITS_SPIO5);
5756 }
5757
5758 static void bnx2x_init_objs(struct bnx2x_softc *sc)
5759 {
5760         /* mcast rules must be added to tx if tx switching is enabled */
5761         ecore_obj_type o_type;
5762         if (sc->flags & BNX2X_TX_SWITCHING)
5763                 o_type = ECORE_OBJ_TYPE_RX_TX;
5764         else
5765                 o_type = ECORE_OBJ_TYPE_RX;
5766
5767         /* RX_MODE controlling object */
5768         ecore_init_rx_mode_obj(sc, &sc->rx_mode_obj);
5769
5770         /* multicast configuration controlling object */
5771         ecore_init_mcast_obj(sc,
5772                              &sc->mcast_obj,
5773                              sc->fp[0].cl_id,
5774                              sc->fp[0].index,
5775                              SC_FUNC(sc),
5776                              SC_FUNC(sc),
5777                              BNX2X_SP(sc, mcast_rdata),
5778                              (rte_iova_t)BNX2X_SP_MAPPING(sc, mcast_rdata),
5779                              ECORE_FILTER_MCAST_PENDING,
5780                              &sc->sp_state, o_type);
5781
5782         /* Setup CAM credit pools */
5783         ecore_init_mac_credit_pool(sc,
5784                                    &sc->macs_pool,
5785                                    SC_FUNC(sc),
5786                                    CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5787                                    VNICS_PER_PATH(sc));
5788
5789         ecore_init_vlan_credit_pool(sc,
5790                                     &sc->vlans_pool,
5791                                     SC_ABS_FUNC(sc) >> 1,
5792                                     CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5793                                     VNICS_PER_PATH(sc));
5794
5795         /* RSS configuration object */
5796         ecore_init_rss_config_obj(sc, &sc->rss_conf_obj, sc->fp->cl_id,
5797                                   sc->fp->index, SC_FUNC(sc), SC_FUNC(sc),
5798                                   BNX2X_SP(sc, rss_rdata),
5799                                   (rte_iova_t)BNX2X_SP_MAPPING(sc, rss_rdata),
5800                                   ECORE_FILTER_RSS_CONF_PENDING, &sc->sp_state,
5801                                   ECORE_OBJ_TYPE_RX);
5802 }
5803
5804 /*
5805  * Initialize the function. This must be called before sending CLIENT_SETUP
5806  * for the first client.
5807  */
5808 static int bnx2x_func_start(struct bnx2x_softc *sc)
5809 {
5810         struct ecore_func_state_params func_params = { NULL };
5811         struct ecore_func_start_params *start_params =
5812             &func_params.params.start;
5813
5814         /* Prepare parameters for function state transitions */
5815         rte_bit_relaxed_set32(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
5816
5817         func_params.f_obj = &sc->func_obj;
5818         func_params.cmd = ECORE_F_CMD_START;
5819
5820         /* Function parameters */
5821         start_params->mf_mode = sc->devinfo.mf_info.mf_mode;
5822         start_params->sd_vlan_tag = OVLAN(sc);
5823
5824         if (CHIP_IS_E2(sc) || CHIP_IS_E3(sc)) {
5825                 start_params->network_cos_mode = STATIC_COS;
5826         } else {                /* CHIP_IS_E1X */
5827                 start_params->network_cos_mode = FW_WRR;
5828         }
5829
5830         return ecore_func_state_change(sc, &func_params);
5831 }
5832
5833 static int bnx2x_set_power_state(struct bnx2x_softc *sc, uint8_t state)
5834 {
5835         uint16_t pmcsr;
5836
5837         /* If there is no power capability, silently succeed */
5838         if (!(sc->devinfo.pcie_cap_flags & BNX2X_PM_CAPABLE_FLAG)) {
5839                 PMD_DRV_LOG(INFO, sc, "No power capability");
5840                 return 0;
5841         }
5842
5843         pci_read(sc, (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS), &pmcsr,
5844                  2);
5845
5846         switch (state) {
5847         case PCI_PM_D0:
5848                 pci_write_word(sc,
5849                                (sc->devinfo.pcie_pm_cap_reg +
5850                                 PCIR_POWER_STATUS),
5851                                ((pmcsr & ~PCIM_PSTAT_DMASK) | PCIM_PSTAT_PME));
5852
5853                 if (pmcsr & PCIM_PSTAT_DMASK) {
5854                         /* delay required during transition out of D3hot */
5855                         DELAY(20000);
5856                 }
5857
5858                 break;
5859
5860         case PCI_PM_D3hot:
5861                 /* don't shut down the power for emulation and FPGA */
5862                 if (CHIP_REV_IS_SLOW(sc)) {
5863                         return 0;
5864                 }
5865
5866                 pmcsr &= ~PCIM_PSTAT_DMASK;
5867                 pmcsr |= PCIM_PSTAT_D3;
5868
5869                 if (sc->wol) {
5870                         pmcsr |= PCIM_PSTAT_PMEENABLE;
5871                 }
5872
5873                 pci_write_long(sc,
5874                                (sc->devinfo.pcie_pm_cap_reg +
5875                                 PCIR_POWER_STATUS), pmcsr);
5876
5877                 /*
5878                  * No more memory access after this point until device is brought back
5879                  * to D0 state.
5880                  */
5881                 break;
5882
5883         default:
5884                 PMD_DRV_LOG(NOTICE, sc, "Can't support PCI power state = %d",
5885                             state);
5886                 return -1;
5887         }
5888
5889         return 0;
5890 }
5891
5892 /* return true if succeeded to acquire the lock */
5893 static uint8_t bnx2x_trylock_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
5894 {
5895         uint32_t lock_status;
5896         uint32_t resource_bit = (1 << resource);
5897         int func = SC_FUNC(sc);
5898         uint32_t hw_lock_control_reg;
5899
5900         /* Validating that the resource is within range */
5901         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
5902                 PMD_DRV_LOG(INFO, sc,
5903                             "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)",
5904                             resource, HW_LOCK_MAX_RESOURCE_VALUE);
5905                 return FALSE;
5906         }
5907
5908         if (func <= 5) {
5909                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func * 8);
5910         } else {
5911                 hw_lock_control_reg =
5912                     (MISC_REG_DRIVER_CONTROL_7 + (func - 6) * 8);
5913         }
5914
5915         /* try to acquire the lock */
5916         REG_WR(sc, hw_lock_control_reg + 4, resource_bit);
5917         lock_status = REG_RD(sc, hw_lock_control_reg);
5918         if (lock_status & resource_bit) {
5919                 return TRUE;
5920         }
5921
5922         PMD_DRV_LOG(NOTICE, sc, "Failed to get a resource lock 0x%x", resource);
5923
5924         return FALSE;
5925 }
5926
5927 /*
5928  * Get the recovery leader resource id according to the engine this function
5929  * belongs to. Currently only only 2 engines is supported.
5930  */
5931 static int bnx2x_get_leader_lock_resource(struct bnx2x_softc *sc)
5932 {
5933         if (SC_PATH(sc)) {
5934                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
5935         } else {
5936                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
5937         }
5938 }
5939
5940 /* try to acquire a leader lock for current engine */
5941 static uint8_t bnx2x_trylock_leader_lock(struct bnx2x_softc *sc)
5942 {
5943         return bnx2x_trylock_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5944 }
5945
5946 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc)
5947 {
5948         return bnx2x_release_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5949 }
5950
5951 /* close gates #2, #3 and #4 */
5952 static void bnx2x_set_234_gates(struct bnx2x_softc *sc, uint8_t close)
5953 {
5954         uint32_t val;
5955
5956         /* gates #2 and #4a are closed/opened */
5957         /* #4 */
5958         REG_WR(sc, PXP_REG_HST_DISCARD_DOORBELLS, ! !close);
5959         /* #2 */
5960         REG_WR(sc, PXP_REG_HST_DISCARD_INTERNAL_WRITES, ! !close);
5961
5962         /* #3 */
5963         if (CHIP_IS_E1x(sc)) {
5964 /* prevent interrupts from HC on both ports */
5965                 val = REG_RD(sc, HC_REG_CONFIG_1);
5966                 if (close)
5967                         REG_WR(sc, HC_REG_CONFIG_1, (val & ~(uint32_t)
5968                                                      HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5969                 else
5970                         REG_WR(sc, HC_REG_CONFIG_1,
5971                                (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5972
5973                 val = REG_RD(sc, HC_REG_CONFIG_0);
5974                 if (close)
5975                         REG_WR(sc, HC_REG_CONFIG_0, (val & ~(uint32_t)
5976                                                      HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5977                 else
5978                         REG_WR(sc, HC_REG_CONFIG_0,
5979                                (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5980
5981         } else {
5982 /* Prevent incoming interrupts in IGU */
5983                 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
5984
5985                 if (close)
5986                         REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5987                                (val & ~(uint32_t)
5988                                 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5989                 else
5990                         REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5991                                (val |
5992                                 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5993         }
5994
5995         wmb();
5996 }
5997
5998 /* poll for pending writes bit, it should get cleared in no more than 1s */
5999 static int bnx2x_er_poll_igu_vq(struct bnx2x_softc *sc)
6000 {
6001         uint32_t cnt = 1000;
6002         uint32_t pend_bits = 0;
6003
6004         do {
6005                 pend_bits = REG_RD(sc, IGU_REG_PENDING_BITS_STATUS);
6006
6007                 if (pend_bits == 0) {
6008                         break;
6009                 }
6010
6011                 DELAY(1000);
6012         } while (cnt-- > 0);
6013
6014         if (cnt <= 0) {
6015                 PMD_DRV_LOG(NOTICE, sc, "Still pending IGU requests bits=0x%08x!",
6016                             pend_bits);
6017                 return -1;
6018         }
6019
6020         return 0;
6021 }
6022
6023 #define SHARED_MF_CLP_MAGIC  0x80000000 /* 'magic' bit */
6024
6025 static void bnx2x_clp_reset_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
6026 {
6027         /* Do some magic... */
6028         uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
6029         *magic_val = val & SHARED_MF_CLP_MAGIC;
6030         MFCFG_WR(sc, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
6031 }
6032
6033 /* restore the value of the 'magic' bit */
6034 static void bnx2x_clp_reset_done(struct bnx2x_softc *sc, uint32_t magic_val)
6035 {
6036         /* Restore the 'magic' bit value... */
6037         uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
6038         MFCFG_WR(sc, shared_mf_config.clp_mb,
6039                  (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
6040 }
6041
6042 /* prepare for MCP reset, takes care of CLP configurations */
6043 static void bnx2x_reset_mcp_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
6044 {
6045         uint32_t shmem;
6046         uint32_t validity_offset;
6047
6048         /* set `magic' bit in order to save MF config */
6049         bnx2x_clp_reset_prep(sc, magic_val);
6050
6051         /* get shmem offset */
6052         shmem = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
6053         validity_offset =
6054             offsetof(struct shmem_region, validity_map[SC_PORT(sc)]);
6055
6056         /* Clear validity map flags */
6057         if (shmem > 0) {
6058                 REG_WR(sc, shmem + validity_offset, 0);
6059         }
6060 }
6061
6062 #define MCP_TIMEOUT      5000   /* 5 seconds (in ms) */
6063 #define MCP_ONE_TIMEOUT  100    /* 100 ms */
6064
6065 static void bnx2x_mcp_wait_one(struct bnx2x_softc *sc)
6066 {
6067         /* special handling for emulation and FPGA (10 times longer) */
6068         if (CHIP_REV_IS_SLOW(sc)) {
6069                 DELAY((MCP_ONE_TIMEOUT * 10) * 1000);
6070         } else {
6071                 DELAY((MCP_ONE_TIMEOUT) * 1000);
6072         }
6073 }
6074
6075 /* initialize shmem_base and waits for validity signature to appear */
6076 static int bnx2x_init_shmem(struct bnx2x_softc *sc)
6077 {
6078         int cnt = 0;
6079         uint32_t val = 0;
6080
6081         do {
6082                 sc->devinfo.shmem_base =
6083                     sc->link_params.shmem_base =
6084                     REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
6085
6086                 if (sc->devinfo.shmem_base) {
6087                         val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
6088                         if (val & SHR_MEM_VALIDITY_MB)
6089                                 return 0;
6090                 }
6091
6092                 bnx2x_mcp_wait_one(sc);
6093
6094         } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
6095
6096         PMD_DRV_LOG(NOTICE, sc, "BAD MCP validity signature");
6097
6098         return -1;
6099 }
6100
6101 static int bnx2x_reset_mcp_comp(struct bnx2x_softc *sc, uint32_t magic_val)
6102 {
6103         int rc = bnx2x_init_shmem(sc);
6104
6105         /* Restore the `magic' bit value */
6106         bnx2x_clp_reset_done(sc, magic_val);
6107
6108         return rc;
6109 }
6110
6111 static void bnx2x_pxp_prep(struct bnx2x_softc *sc)
6112 {
6113         REG_WR(sc, PXP2_REG_RD_START_INIT, 0);
6114         REG_WR(sc, PXP2_REG_RQ_RBC_DONE, 0);
6115         wmb();
6116 }
6117
6118 /*
6119  * Reset the whole chip except for:
6120  *      - PCIE core
6121  *      - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by one reset bit)
6122  *      - IGU
6123  *      - MISC (including AEU)
6124  *      - GRC
6125  *      - RBCN, RBCP
6126  */
6127 static void bnx2x_process_kill_chip_reset(struct bnx2x_softc *sc, uint8_t global)
6128 {
6129         uint32_t not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
6130         uint32_t global_bits2, stay_reset2;
6131
6132         /*
6133          * Bits that have to be set in reset_mask2 if we want to reset 'global'
6134          * (per chip) blocks.
6135          */
6136         global_bits2 =
6137             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
6138             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
6139
6140         /*
6141          * Don't reset the following blocks.
6142          * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
6143          *            reset, as in 4 port device they might still be owned
6144          *            by the MCP (there is only one leader per path).
6145          */
6146         not_reset_mask1 =
6147             MISC_REGISTERS_RESET_REG_1_RST_HC |
6148             MISC_REGISTERS_RESET_REG_1_RST_PXPV |
6149             MISC_REGISTERS_RESET_REG_1_RST_PXP;
6150
6151         not_reset_mask2 =
6152             MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
6153             MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
6154             MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
6155             MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
6156             MISC_REGISTERS_RESET_REG_2_RST_RBCN |
6157             MISC_REGISTERS_RESET_REG_2_RST_GRC |
6158             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
6159             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
6160             MISC_REGISTERS_RESET_REG_2_RST_ATC |
6161             MISC_REGISTERS_RESET_REG_2_PGLC |
6162             MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
6163             MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
6164             MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
6165             MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
6166             MISC_REGISTERS_RESET_REG_2_UMAC0 | MISC_REGISTERS_RESET_REG_2_UMAC1;
6167
6168         /*
6169          * Keep the following blocks in reset:
6170          *  - all xxMACs are handled by the elink code.
6171          */
6172         stay_reset2 =
6173             MISC_REGISTERS_RESET_REG_2_XMAC |
6174             MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
6175
6176         /* Full reset masks according to the chip */
6177         reset_mask1 = 0xffffffff;
6178
6179         if (CHIP_IS_E1H(sc))
6180                 reset_mask2 = 0x1ffff;
6181         else if (CHIP_IS_E2(sc))
6182                 reset_mask2 = 0xfffff;
6183         else                    /* CHIP_IS_E3 */
6184                 reset_mask2 = 0x3ffffff;
6185
6186         /* Don't reset global blocks unless we need to */
6187         if (!global)
6188                 reset_mask2 &= ~global_bits2;
6189
6190         /*
6191          * In case of attention in the QM, we need to reset PXP
6192          * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
6193          * because otherwise QM reset would release 'close the gates' shortly
6194          * before resetting the PXP, then the PSWRQ would send a write
6195          * request to PGLUE. Then when PXP is reset, PGLUE would try to
6196          * read the payload data from PSWWR, but PSWWR would not
6197          * respond. The write queue in PGLUE would stuck, dmae commands
6198          * would not return. Therefore it's important to reset the second
6199          * reset register (containing the
6200          * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
6201          * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
6202          * bit).
6203          */
6204         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
6205                reset_mask2 & (~not_reset_mask2));
6206
6207         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6208                reset_mask1 & (~not_reset_mask1));
6209
6210         mb();
6211         wmb();
6212
6213         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
6214                reset_mask2 & (~stay_reset2));
6215
6216         mb();
6217         wmb();
6218
6219         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
6220         wmb();
6221 }
6222
6223 static int bnx2x_process_kill(struct bnx2x_softc *sc, uint8_t global)
6224 {
6225         int cnt = 1000;
6226         uint32_t val = 0;
6227         uint32_t sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
6228         uint32_t tags_63_32 = 0;
6229
6230         /* Empty the Tetris buffer, wait for 1s */
6231         do {
6232                 sr_cnt = REG_RD(sc, PXP2_REG_RD_SR_CNT);
6233                 blk_cnt = REG_RD(sc, PXP2_REG_RD_BLK_CNT);
6234                 port_is_idle_0 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_0);
6235                 port_is_idle_1 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_1);
6236                 pgl_exp_rom2 = REG_RD(sc, PXP2_REG_PGL_EXP_ROM2);
6237                 if (CHIP_IS_E3(sc)) {
6238                         tags_63_32 = REG_RD(sc, PGLUE_B_REG_TAGS_63_32);
6239                 }
6240
6241                 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
6242                     ((port_is_idle_0 & 0x1) == 0x1) &&
6243                     ((port_is_idle_1 & 0x1) == 0x1) &&
6244                     (pgl_exp_rom2 == 0xffffffff) &&
6245                     (!CHIP_IS_E3(sc) || (tags_63_32 == 0xffffffff)))
6246                         break;
6247                 DELAY(1000);
6248         } while (cnt-- > 0);
6249
6250         if (cnt <= 0) {
6251                 PMD_DRV_LOG(NOTICE, sc,
6252                             "ERROR: Tetris buffer didn't get empty or there "
6253                             "are still outstanding read requests after 1s! "
6254                             "sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, "
6255                             "port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x",
6256                             sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
6257                             pgl_exp_rom2);
6258                 return -1;
6259         }
6260
6261         mb();
6262
6263         /* Close gates #2, #3 and #4 */
6264         bnx2x_set_234_gates(sc, TRUE);
6265
6266         /* Poll for IGU VQs for 57712 and newer chips */
6267         if (!CHIP_IS_E1x(sc) && bnx2x_er_poll_igu_vq(sc)) {
6268                 return -1;
6269         }
6270
6271         /* clear "unprepared" bit */
6272         REG_WR(sc, MISC_REG_UNPREPARED, 0);
6273         mb();
6274
6275         /* Make sure all is written to the chip before the reset */
6276         wmb();
6277
6278         /*
6279          * Wait for 1ms to empty GLUE and PCI-E core queues,
6280          * PSWHST, GRC and PSWRD Tetris buffer.
6281          */
6282         DELAY(1000);
6283
6284         /* Prepare to chip reset: */
6285         /* MCP */
6286         if (global) {
6287                 bnx2x_reset_mcp_prep(sc, &val);
6288         }
6289
6290         /* PXP */
6291         bnx2x_pxp_prep(sc);
6292         mb();
6293
6294         /* reset the chip */
6295         bnx2x_process_kill_chip_reset(sc, global);
6296         mb();
6297
6298         /* Recover after reset: */
6299         /* MCP */
6300         if (global && bnx2x_reset_mcp_comp(sc, val)) {
6301                 return -1;
6302         }
6303
6304         /* Open the gates #2, #3 and #4 */
6305         bnx2x_set_234_gates(sc, FALSE);
6306
6307         return 0;
6308 }
6309
6310 static int bnx2x_leader_reset(struct bnx2x_softc *sc)
6311 {
6312         int rc = 0;
6313         uint8_t global = bnx2x_reset_is_global(sc);
6314         uint32_t load_code;
6315
6316         /*
6317          * If not going to reset MCP, load "fake" driver to reset HW while
6318          * driver is owner of the HW.
6319          */
6320         if (!global && !BNX2X_NOMCP(sc)) {
6321                 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
6322                                            DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
6323                 if (!load_code) {
6324                         PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
6325                         rc = -1;
6326                         goto exit_leader_reset;
6327                 }
6328
6329                 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
6330                     (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
6331                         PMD_DRV_LOG(NOTICE, sc,
6332                                     "MCP unexpected response, aborting");
6333                         rc = -1;
6334                         goto exit_leader_reset2;
6335                 }
6336
6337                 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
6338                 if (!load_code) {
6339                         PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
6340                         rc = -1;
6341                         goto exit_leader_reset2;
6342                 }
6343         }
6344
6345         /* try to recover after the failure */
6346         if (bnx2x_process_kill(sc, global)) {
6347                 PMD_DRV_LOG(NOTICE, sc, "Something bad occurred on engine %d!",
6348                             SC_PATH(sc));
6349                 rc = -1;
6350                 goto exit_leader_reset2;
6351         }
6352
6353         /*
6354          * Clear the RESET_IN_PROGRESS and RESET_GLOBAL bits and update the driver
6355          * state.
6356          */
6357         bnx2x_set_reset_done(sc);
6358         if (global) {
6359                 bnx2x_clear_reset_global(sc);
6360         }
6361
6362 exit_leader_reset2:
6363
6364         /* unload "fake driver" if it was loaded */
6365         if (!global &&!BNX2X_NOMCP(sc)) {
6366                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
6367                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
6368         }
6369
6370 exit_leader_reset:
6371
6372         sc->is_leader = 0;
6373         bnx2x_release_leader_lock(sc);
6374
6375         mb();
6376         return rc;
6377 }
6378
6379 /*
6380  * prepare INIT transition, parameters configured:
6381  *   - HC configuration
6382  *   - Queue's CDU context
6383  */
6384 static void
6385 bnx2x_pf_q_prep_init(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6386                    struct ecore_queue_init_params *init_params)
6387 {
6388         uint8_t cos;
6389         int cxt_index, cxt_offset;
6390
6391         rte_bit_relaxed_set32(ECORE_Q_FLG_HC, &init_params->rx.flags);
6392         rte_bit_relaxed_set32(ECORE_Q_FLG_HC, &init_params->tx.flags);
6393
6394         rte_bit_relaxed_set32(ECORE_Q_FLG_HC_EN, &init_params->rx.flags);
6395         rte_bit_relaxed_set32(ECORE_Q_FLG_HC_EN, &init_params->tx.flags);
6396
6397         /* HC rate */
6398         init_params->rx.hc_rate =
6399             sc->hc_rx_ticks ? (1000000 / sc->hc_rx_ticks) : 0;
6400         init_params->tx.hc_rate =
6401             sc->hc_tx_ticks ? (1000000 / sc->hc_tx_ticks) : 0;
6402
6403         /* FW SB ID */
6404         init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = fp->fw_sb_id;
6405
6406         /* CQ index among the SB indices */
6407         init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6408         init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
6409
6410         /* set maximum number of COSs supported by this queue */
6411         init_params->max_cos = sc->max_cos;
6412
6413         /* set the context pointers queue object */
6414         for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
6415                 cxt_index = fp->index / ILT_PAGE_CIDS;
6416                 cxt_offset = fp->index - (cxt_index * ILT_PAGE_CIDS);
6417                 init_params->cxts[cos] =
6418                     &sc->context[cxt_index].vcxt[cxt_offset].eth;
6419         }
6420 }
6421
6422 /* set flags that are common for the Tx-only and not normal connections */
6423 static unsigned long
6424 bnx2x_get_common_flags(struct bnx2x_softc *sc, uint8_t zero_stats)
6425 {
6426         uint32_t flags = 0;
6427
6428         /* PF driver will always initialize the Queue to an ACTIVE state */
6429         rte_bit_relaxed_set32(ECORE_Q_FLG_ACTIVE, &flags);
6430
6431         /*
6432          * tx only connections collect statistics (on the same index as the
6433          * parent connection). The statistics are zeroed when the parent
6434          * connection is initialized.
6435          */
6436
6437         rte_bit_relaxed_set32(ECORE_Q_FLG_STATS, &flags);
6438         if (zero_stats) {
6439                 rte_bit_relaxed_set32(ECORE_Q_FLG_ZERO_STATS, &flags);
6440         }
6441
6442         /*
6443          * tx only connections can support tx-switching, though their
6444          * CoS-ness doesn't survive the loopback
6445          */
6446         if (sc->flags & BNX2X_TX_SWITCHING) {
6447                 rte_bit_relaxed_set32(ECORE_Q_FLG_TX_SWITCH, &flags);
6448         }
6449
6450         rte_bit_relaxed_set32(ECORE_Q_FLG_PCSUM_ON_PKT, &flags);
6451
6452         return flags;
6453 }
6454
6455 static unsigned long bnx2x_get_q_flags(struct bnx2x_softc *sc, uint8_t leading)
6456 {
6457         uint32_t flags = 0;
6458
6459         if (IS_MF_SD(sc)) {
6460                 rte_bit_relaxed_set32(ECORE_Q_FLG_OV, &flags);
6461         }
6462
6463         if (leading) {
6464                 rte_bit_relaxed_set32(ECORE_Q_FLG_LEADING_RSS, &flags);
6465                 rte_bit_relaxed_set32(ECORE_Q_FLG_MCAST, &flags);
6466         }
6467
6468         rte_bit_relaxed_set32(ECORE_Q_FLG_VLAN, &flags);
6469
6470         /* merge with common flags */
6471         return flags | bnx2x_get_common_flags(sc, TRUE);
6472 }
6473
6474 static void
6475 bnx2x_pf_q_prep_general(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6476                       struct ecore_general_setup_params *gen_init, uint8_t cos)
6477 {
6478         gen_init->stat_id = bnx2x_stats_id(fp);
6479         gen_init->spcl_id = fp->cl_id;
6480         gen_init->mtu = sc->mtu;
6481         gen_init->cos = cos;
6482 }
6483
6484 static void
6485 bnx2x_pf_rx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6486                  struct rxq_pause_params *pause,
6487                  struct ecore_rxq_setup_params *rxq_init)
6488 {
6489         struct bnx2x_rx_queue *rxq;
6490
6491         rxq = sc->rx_queues[fp->index];
6492         if (!rxq) {
6493                 PMD_RX_LOG(ERR, "RX queue is NULL");
6494                 return;
6495         }
6496         /* pause */
6497         pause->bd_th_lo = BD_TH_LO(sc);
6498         pause->bd_th_hi = BD_TH_HI(sc);
6499
6500         pause->rcq_th_lo = RCQ_TH_LO(sc);
6501         pause->rcq_th_hi = RCQ_TH_HI(sc);
6502
6503         /* validate rings have enough entries to cross high thresholds */
6504         if (sc->dropless_fc &&
6505             pause->bd_th_hi + FW_PREFETCH_CNT > sc->rx_ring_size) {
6506                 PMD_DRV_LOG(WARNING, sc, "rx bd ring threshold limit");
6507         }
6508
6509         if (sc->dropless_fc &&
6510             pause->rcq_th_hi + FW_PREFETCH_CNT > USABLE_RCQ_ENTRIES(rxq)) {
6511                 PMD_DRV_LOG(WARNING, sc, "rcq ring threshold limit");
6512         }
6513
6514         pause->pri_map = 1;
6515
6516         /* rxq setup */
6517         rxq_init->dscr_map = (rte_iova_t)rxq->rx_ring_phys_addr;
6518         rxq_init->rcq_map = (rte_iova_t)rxq->cq_ring_phys_addr;
6519         rxq_init->rcq_np_map = (rte_iova_t)(rxq->cq_ring_phys_addr +
6520                                               BNX2X_PAGE_SIZE);
6521
6522         /*
6523          * This should be a maximum number of data bytes that may be
6524          * placed on the BD (not including paddings).
6525          */
6526         rxq_init->buf_sz = (fp->rx_buf_size - IP_HEADER_ALIGNMENT_PADDING);
6527
6528         rxq_init->cl_qzone_id = fp->cl_qzone_id;
6529         rxq_init->rss_engine_id = SC_FUNC(sc);
6530         rxq_init->mcast_engine_id = SC_FUNC(sc);
6531
6532         rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
6533         rxq_init->fw_sb_id = fp->fw_sb_id;
6534
6535         rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6536
6537         /*
6538          * configure silent vlan removal
6539          * if multi function mode is afex, then mask default vlan
6540          */
6541         if (IS_MF_AFEX(sc)) {
6542                 rxq_init->silent_removal_value =
6543                     sc->devinfo.mf_info.afex_def_vlan_tag;
6544                 rxq_init->silent_removal_mask = EVL_VLID_MASK;
6545         }
6546 }
6547
6548 static void
6549 bnx2x_pf_tx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6550                  struct ecore_txq_setup_params *txq_init, uint8_t cos)
6551 {
6552         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
6553
6554         if (!txq) {
6555                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
6556                 return;
6557         }
6558         txq_init->dscr_map = (rte_iova_t)txq->tx_ring_phys_addr;
6559         txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
6560         txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
6561         txq_init->fw_sb_id = fp->fw_sb_id;
6562
6563         /*
6564          * set the TSS leading client id for TX classfication to the
6565          * leading RSS client id
6566          */
6567         txq_init->tss_leading_cl_id = BNX2X_FP(sc, 0, cl_id);
6568 }
6569
6570 /*
6571  * This function performs 2 steps in a queue state machine:
6572  *   1) RESET->INIT
6573  *   2) INIT->SETUP
6574  */
6575 static int
6576 bnx2x_setup_queue(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp, uint8_t leading)
6577 {
6578         struct ecore_queue_state_params q_params = { NULL };
6579         struct ecore_queue_setup_params *setup_params = &q_params.params.setup;
6580         int rc;
6581
6582         PMD_DRV_LOG(DEBUG, sc, "setting up queue %d", fp->index);
6583
6584         bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6585
6586         q_params.q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
6587
6588         /* we want to wait for completion in this context */
6589         rte_bit_relaxed_set32(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
6590
6591         /* prepare the INIT parameters */
6592         bnx2x_pf_q_prep_init(sc, fp, &q_params.params.init);
6593
6594         /* Set the command */
6595         q_params.cmd = ECORE_Q_CMD_INIT;
6596
6597         /* Change the state to INIT */
6598         rc = ecore_queue_state_change(sc, &q_params);
6599         if (rc) {
6600                 PMD_DRV_LOG(NOTICE, sc, "Queue(%d) INIT failed", fp->index);
6601                 return rc;
6602         }
6603
6604         PMD_DRV_LOG(DEBUG, sc, "init complete");
6605
6606         /* now move the Queue to the SETUP state */
6607         memset(setup_params, 0, sizeof(*setup_params));
6608
6609         /* set Queue flags */
6610         setup_params->flags = bnx2x_get_q_flags(sc, leading);
6611
6612         /* set general SETUP parameters */
6613         bnx2x_pf_q_prep_general(sc, fp, &setup_params->gen_params,
6614                               FIRST_TX_COS_INDEX);
6615
6616         bnx2x_pf_rx_q_prep(sc, fp,
6617                          &setup_params->pause_params,
6618                          &setup_params->rxq_params);
6619
6620         bnx2x_pf_tx_q_prep(sc, fp, &setup_params->txq_params, FIRST_TX_COS_INDEX);
6621
6622         /* Set the command */
6623         q_params.cmd = ECORE_Q_CMD_SETUP;
6624
6625         /* change the state to SETUP */
6626         rc = ecore_queue_state_change(sc, &q_params);
6627         if (rc) {
6628                 PMD_DRV_LOG(NOTICE, sc, "Queue(%d) SETUP failed", fp->index);
6629                 return rc;
6630         }
6631
6632         return rc;
6633 }
6634
6635 static int bnx2x_setup_leading(struct bnx2x_softc *sc)
6636 {
6637         if (IS_PF(sc))
6638                 return bnx2x_setup_queue(sc, &sc->fp[0], TRUE);
6639         else                    /* VF */
6640                 return bnx2x_vf_setup_queue(sc, &sc->fp[0], TRUE);
6641 }
6642
6643 static int
6644 bnx2x_config_rss_pf(struct bnx2x_softc *sc, struct ecore_rss_config_obj *rss_obj,
6645                   uint8_t config_hash)
6646 {
6647         struct ecore_config_rss_params params = { NULL };
6648         uint32_t i;
6649
6650         /*
6651          * Although RSS is meaningless when there is a single HW queue we
6652          * still need it enabled in order to have HW Rx hash generated.
6653          */
6654
6655         params.rss_obj = rss_obj;
6656
6657         rte_bit_relaxed_set32(RAMROD_COMP_WAIT, &params.ramrod_flags);
6658
6659         rte_bit_relaxed_set32(ECORE_RSS_MODE_REGULAR, &params.rss_flags);
6660
6661         /* RSS configuration */
6662         rte_bit_relaxed_set32(ECORE_RSS_IPV4, &params.rss_flags);
6663         rte_bit_relaxed_set32(ECORE_RSS_IPV4_TCP, &params.rss_flags);
6664         rte_bit_relaxed_set32(ECORE_RSS_IPV6, &params.rss_flags);
6665         rte_bit_relaxed_set32(ECORE_RSS_IPV6_TCP, &params.rss_flags);
6666         if (rss_obj->udp_rss_v4) {
6667                 rte_bit_relaxed_set32(ECORE_RSS_IPV4_UDP, &params.rss_flags);
6668         }
6669         if (rss_obj->udp_rss_v6) {
6670                 rte_bit_relaxed_set32(ECORE_RSS_IPV6_UDP, &params.rss_flags);
6671         }
6672
6673         /* Hash bits */
6674         params.rss_result_mask = MULTI_MASK;
6675
6676         rte_memcpy(params.ind_table, rss_obj->ind_table,
6677                          sizeof(params.ind_table));
6678
6679         if (config_hash) {
6680 /* RSS keys */
6681                 for (i = 0; i < sizeof(params.rss_key) / 4; i++) {
6682                         params.rss_key[i] = (uint32_t) rte_rand();
6683                 }
6684
6685                 rte_bit_relaxed_set32(ECORE_RSS_SET_SRCH, &params.rss_flags);
6686         }
6687
6688         if (IS_PF(sc))
6689                 return ecore_config_rss(sc, &params);
6690         else
6691                 return bnx2x_vf_config_rss(sc, &params);
6692 }
6693
6694 static int bnx2x_config_rss_eth(struct bnx2x_softc *sc, uint8_t config_hash)
6695 {
6696         return bnx2x_config_rss_pf(sc, &sc->rss_conf_obj, config_hash);
6697 }
6698
6699 static int bnx2x_init_rss_pf(struct bnx2x_softc *sc)
6700 {
6701         uint8_t num_eth_queues = BNX2X_NUM_ETH_QUEUES(sc);
6702         uint32_t i;
6703
6704         /*
6705          * Prepare the initial contents of the indirection table if
6706          * RSS is enabled
6707          */
6708         for (i = 0; i < sizeof(sc->rss_conf_obj.ind_table); i++) {
6709                 sc->rss_conf_obj.ind_table[i] =
6710                     (sc->fp->cl_id + (i % num_eth_queues));
6711         }
6712
6713         if (sc->udp_rss) {
6714                 sc->rss_conf_obj.udp_rss_v4 = sc->rss_conf_obj.udp_rss_v6 = 1;
6715         }
6716
6717         /*
6718          * For 57711 SEARCHER configuration (rss_keys) is
6719          * per-port, so if explicit configuration is needed, do it only
6720          * for a PMF.
6721          *
6722          * For 57712 and newer it's a per-function configuration.
6723          */
6724         return bnx2x_config_rss_eth(sc, sc->port.pmf || !CHIP_IS_E1x(sc));
6725 }
6726
6727 static int
6728 bnx2x_set_mac_one(struct bnx2x_softc *sc, uint8_t * mac,
6729                 struct ecore_vlan_mac_obj *obj, uint8_t set, int mac_type,
6730                 uint32_t *ramrod_flags)
6731 {
6732         struct ecore_vlan_mac_ramrod_params ramrod_param;
6733         int rc;
6734
6735         memset(&ramrod_param, 0, sizeof(ramrod_param));
6736
6737         /* fill in general parameters */
6738         ramrod_param.vlan_mac_obj = obj;
6739         ramrod_param.ramrod_flags = *ramrod_flags;
6740
6741         /* fill a user request section if needed */
6742         if (!rte_bit_relaxed_get32(RAMROD_CONT, ramrod_flags)) {
6743                 rte_memcpy(ramrod_param.user_req.u.mac.mac, mac,
6744                                  ETH_ALEN);
6745
6746                 rte_bit_relaxed_set32(mac_type,
6747                                       &ramrod_param.user_req.vlan_mac_flags);
6748
6749 /* Set the command: ADD or DEL */
6750                 ramrod_param.user_req.cmd = (set) ? ECORE_VLAN_MAC_ADD :
6751                     ECORE_VLAN_MAC_DEL;
6752         }
6753
6754         rc = ecore_config_vlan_mac(sc, &ramrod_param);
6755
6756         if (rc == ECORE_EXISTS) {
6757                 PMD_DRV_LOG(INFO, sc, "Failed to schedule ADD operations (EEXIST)");
6758 /* do not treat adding same MAC as error */
6759                 rc = 0;
6760         } else if (rc < 0) {
6761                 PMD_DRV_LOG(ERR, sc,
6762                             "%s MAC failed (%d)", (set ? "Set" : "Delete"), rc);
6763         }
6764
6765         return rc;
6766 }
6767
6768 static int bnx2x_set_eth_mac(struct bnx2x_softc *sc, uint8_t set)
6769 {
6770         uint32_t ramrod_flags = 0;
6771
6772         PMD_DRV_LOG(DEBUG, sc, "Adding Ethernet MAC");
6773
6774         rte_bit_relaxed_set32(RAMROD_COMP_WAIT, &ramrod_flags);
6775
6776         /* Eth MAC is set on RSS leading client (fp[0]) */
6777         return bnx2x_set_mac_one(sc, sc->link_params.mac_addr,
6778                                &sc->sp_objs->mac_obj,
6779                                set, ECORE_ETH_MAC, &ramrod_flags);
6780 }
6781
6782 static int bnx2x_get_cur_phy_idx(struct bnx2x_softc *sc)
6783 {
6784         uint32_t sel_phy_idx = 0;
6785
6786         if (sc->link_params.num_phys <= 1) {
6787                 return ELINK_INT_PHY;
6788         }
6789
6790         if (sc->link_vars.link_up) {
6791                 sel_phy_idx = ELINK_EXT_PHY1;
6792 /* In case link is SERDES, check if the ELINK_EXT_PHY2 is the one */
6793                 if ((sc->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
6794                     (sc->link_params.phy[ELINK_EXT_PHY2].supported &
6795                      ELINK_SUPPORTED_FIBRE))
6796                         sel_phy_idx = ELINK_EXT_PHY2;
6797         } else {
6798                 switch (elink_phy_selection(&sc->link_params)) {
6799                 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6800                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
6801                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6802                         sel_phy_idx = ELINK_EXT_PHY1;
6803                         break;
6804                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
6805                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6806                         sel_phy_idx = ELINK_EXT_PHY2;
6807                         break;
6808                 }
6809         }
6810
6811         return sel_phy_idx;
6812 }
6813
6814 static int bnx2x_get_link_cfg_idx(struct bnx2x_softc *sc)
6815 {
6816         uint32_t sel_phy_idx = bnx2x_get_cur_phy_idx(sc);
6817
6818         /*
6819          * The selected activated PHY is always after swapping (in case PHY
6820          * swapping is enabled). So when swapping is enabled, we need to reverse
6821          * the configuration
6822          */
6823
6824         if (sc->link_params.multi_phy_config & PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
6825                 if (sel_phy_idx == ELINK_EXT_PHY1)
6826                         sel_phy_idx = ELINK_EXT_PHY2;
6827                 else if (sel_phy_idx == ELINK_EXT_PHY2)
6828                         sel_phy_idx = ELINK_EXT_PHY1;
6829         }
6830
6831         return ELINK_LINK_CONFIG_IDX(sel_phy_idx);
6832 }
6833
6834 static void bnx2x_set_requested_fc(struct bnx2x_softc *sc)
6835 {
6836         /*
6837          * Initialize link parameters structure variables
6838          * It is recommended to turn off RX FC for jumbo frames
6839          * for better performance
6840          */
6841         if (CHIP_IS_E1x(sc) && (sc->mtu > 5000)) {
6842                 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_TX;
6843         } else {
6844                 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_BOTH;
6845         }
6846 }
6847
6848 static void bnx2x_calc_fc_adv(struct bnx2x_softc *sc)
6849 {
6850         uint8_t cfg_idx = bnx2x_get_link_cfg_idx(sc);
6851         switch (sc->link_vars.ieee_fc &
6852                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
6853         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
6854         default:
6855                 sc->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
6856                                                    ADVERTISED_Pause);
6857                 break;
6858
6859         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
6860                 sc->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
6861                                                   ADVERTISED_Pause);
6862                 break;
6863
6864         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
6865                 sc->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
6866                 break;
6867         }
6868 }
6869
6870 static uint16_t bnx2x_get_mf_speed(struct bnx2x_softc *sc)
6871 {
6872         uint16_t line_speed = sc->link_vars.line_speed;
6873         if (IS_MF(sc)) {
6874                 uint16_t maxCfg = bnx2x_extract_max_cfg(sc,
6875                                                       sc->devinfo.
6876                                                       mf_info.mf_config[SC_VN
6877                                                                         (sc)]);
6878
6879 /* calculate the current MAX line speed limit for the MF devices */
6880                 if (IS_MF_SI(sc)) {
6881                         line_speed = (line_speed * maxCfg) / 100;
6882                 } else {        /* SD mode */
6883                         uint16_t vn_max_rate = maxCfg * 100;
6884
6885                         if (vn_max_rate < line_speed) {
6886                                 line_speed = vn_max_rate;
6887                         }
6888                 }
6889         }
6890
6891         return line_speed;
6892 }
6893
6894 static void
6895 bnx2x_fill_report_data(struct bnx2x_softc *sc, struct bnx2x_link_report_data *data)
6896 {
6897         uint16_t line_speed = bnx2x_get_mf_speed(sc);
6898
6899         memset(data, 0, sizeof(*data));
6900
6901         /* fill the report data with the effective line speed */
6902         data->line_speed = line_speed;
6903
6904         /* Link is down */
6905         if (!sc->link_vars.link_up || (sc->flags & BNX2X_MF_FUNC_DIS)) {
6906                 rte_bit_relaxed_set32(BNX2X_LINK_REPORT_LINK_DOWN,
6907                             &data->link_report_flags);
6908         }
6909
6910         /* Full DUPLEX */
6911         if (sc->link_vars.duplex == DUPLEX_FULL) {
6912                 rte_bit_relaxed_set32(BNX2X_LINK_REPORT_FULL_DUPLEX,
6913                             &data->link_report_flags);
6914         }
6915
6916         /* Rx Flow Control is ON */
6917         if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_RX) {
6918                 rte_bit_relaxed_set32(BNX2X_LINK_REPORT_RX_FC_ON,
6919                                 &data->link_report_flags);
6920         }
6921
6922         /* Tx Flow Control is ON */
6923         if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
6924                 rte_bit_relaxed_set32(BNX2X_LINK_REPORT_TX_FC_ON,
6925                                 &data->link_report_flags);
6926         }
6927 }
6928
6929 /* report link status to OS, should be called under phy_lock */
6930 static void bnx2x_link_report_locked(struct bnx2x_softc *sc)
6931 {
6932         struct bnx2x_link_report_data cur_data;
6933
6934         /* reread mf_cfg */
6935         if (IS_PF(sc)) {
6936                 bnx2x_read_mf_cfg(sc);
6937         }
6938
6939         /* Read the current link report info */
6940         bnx2x_fill_report_data(sc, &cur_data);
6941
6942         /* Don't report link down or exactly the same link status twice */
6943         if (!memcmp(&cur_data, &sc->last_reported_link, sizeof(cur_data)) ||
6944             (rte_bit_relaxed_get32(BNX2X_LINK_REPORT_LINK_DOWN,
6945                           &sc->last_reported_link.link_report_flags) &&
6946              rte_bit_relaxed_get32(BNX2X_LINK_REPORT_LINK_DOWN,
6947                           &cur_data.link_report_flags))) {
6948                 return;
6949         }
6950
6951         ELINK_DEBUG_P2(sc, "Change in link status : cur_data = %x, last_reported_link = %x",
6952                        cur_data.link_report_flags,
6953                        sc->last_reported_link.link_report_flags);
6954
6955         sc->link_cnt++;
6956
6957         ELINK_DEBUG_P1(sc, "link status change count = %x", sc->link_cnt);
6958         /* report new link params and remember the state for the next time */
6959         rte_memcpy(&sc->last_reported_link, &cur_data, sizeof(cur_data));
6960
6961         if (rte_bit_relaxed_get32(BNX2X_LINK_REPORT_LINK_DOWN,
6962                          &cur_data.link_report_flags)) {
6963                 ELINK_DEBUG_P0(sc, "NIC Link is Down");
6964         } else {
6965                 __rte_unused const char *duplex;
6966                 __rte_unused const char *flow;
6967
6968                 if (rte_bit_relaxed_test_and_clear32
6969                                         (BNX2X_LINK_REPORT_FULL_DUPLEX,
6970                                          &cur_data.link_report_flags)) {
6971                         duplex = "full";
6972                                 ELINK_DEBUG_P0(sc, "link set to full duplex");
6973                 } else {
6974                         duplex = "half";
6975                                 ELINK_DEBUG_P0(sc, "link set to half duplex");
6976                 }
6977
6978 /*
6979  * Handle the FC at the end so that only these flags would be
6980  * possibly set. This way we may easily check if there is no FC
6981  * enabled.
6982  */
6983                 if (cur_data.link_report_flags) {
6984                         if (rte_bit_relaxed_get32
6985                                         (BNX2X_LINK_REPORT_RX_FC_ON,
6986                                          &cur_data.link_report_flags) &&
6987                             rte_bit_relaxed_get32(BNX2X_LINK_REPORT_TX_FC_ON,
6988                                          &cur_data.link_report_flags)) {
6989                                 flow = "ON - receive & transmit";
6990                         } else if (rte_bit_relaxed_get32
6991                                                 (BNX2X_LINK_REPORT_RX_FC_ON,
6992                                                  &cur_data.link_report_flags) &&
6993                                    !rte_bit_relaxed_get32
6994                                                 (BNX2X_LINK_REPORT_TX_FC_ON,
6995                                                  &cur_data.link_report_flags)) {
6996                                 flow = "ON - receive";
6997                         } else if (!rte_bit_relaxed_get32
6998                                                 (BNX2X_LINK_REPORT_RX_FC_ON,
6999                                                  &cur_data.link_report_flags) &&
7000                                    rte_bit_relaxed_get32
7001                                                 (BNX2X_LINK_REPORT_TX_FC_ON,
7002                                                  &cur_data.link_report_flags)) {
7003                                 flow = "ON - transmit";
7004                         } else {
7005                                 flow = "none";  /* possible? */
7006                         }
7007                 } else {
7008                         flow = "none";
7009                 }
7010
7011                 PMD_DRV_LOG(INFO, sc,
7012                             "NIC Link is Up, %d Mbps %s duplex, Flow control: %s",
7013                             cur_data.line_speed, duplex, flow);
7014         }
7015 }
7016
7017 static void
7018 bnx2x_link_report(struct bnx2x_softc *sc)
7019 {
7020         bnx2x_acquire_phy_lock(sc);
7021         bnx2x_link_report_locked(sc);
7022         bnx2x_release_phy_lock(sc);
7023 }
7024
7025 void bnx2x_link_status_update(struct bnx2x_softc *sc)
7026 {
7027         if (sc->state != BNX2X_STATE_OPEN) {
7028                 return;
7029         }
7030
7031         if (IS_PF(sc) && !CHIP_REV_IS_SLOW(sc)) {
7032                 elink_link_status_update(&sc->link_params, &sc->link_vars);
7033         } else {
7034                 sc->port.supported[0] |= (ELINK_SUPPORTED_10baseT_Half |
7035                                           ELINK_SUPPORTED_10baseT_Full |
7036                                           ELINK_SUPPORTED_100baseT_Half |
7037                                           ELINK_SUPPORTED_100baseT_Full |
7038                                           ELINK_SUPPORTED_1000baseT_Full |
7039                                           ELINK_SUPPORTED_2500baseX_Full |
7040                                           ELINK_SUPPORTED_10000baseT_Full |
7041                                           ELINK_SUPPORTED_TP |
7042                                           ELINK_SUPPORTED_FIBRE |
7043                                           ELINK_SUPPORTED_Autoneg |
7044                                           ELINK_SUPPORTED_Pause |
7045                                           ELINK_SUPPORTED_Asym_Pause);
7046                 sc->port.advertising[0] = sc->port.supported[0];
7047
7048                 sc->link_params.sc = sc;
7049                 sc->link_params.port = SC_PORT(sc);
7050                 sc->link_params.req_duplex[0] = DUPLEX_FULL;
7051                 sc->link_params.req_flow_ctrl[0] = ELINK_FLOW_CTRL_NONE;
7052                 sc->link_params.req_line_speed[0] = SPEED_10000;
7053                 sc->link_params.speed_cap_mask[0] = 0x7f0000;
7054                 sc->link_params.switch_cfg = ELINK_SWITCH_CFG_10G;
7055
7056                 if (CHIP_REV_IS_FPGA(sc)) {
7057                         sc->link_vars.mac_type = ELINK_MAC_TYPE_EMAC;
7058                         sc->link_vars.line_speed = ELINK_SPEED_1000;
7059                         sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
7060                                                      LINK_STATUS_SPEED_AND_DUPLEX_1000TFD);
7061                 } else {
7062                         sc->link_vars.mac_type = ELINK_MAC_TYPE_BMAC;
7063                         sc->link_vars.line_speed = ELINK_SPEED_10000;
7064                         sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
7065                                                      LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
7066                 }
7067
7068                 sc->link_vars.link_up = 1;
7069
7070                 sc->link_vars.duplex = DUPLEX_FULL;
7071                 sc->link_vars.flow_ctrl = ELINK_FLOW_CTRL_NONE;
7072
7073                 if (IS_PF(sc)) {
7074                         REG_WR(sc,
7075                                NIG_REG_EGRESS_DRAIN0_MODE +
7076                                sc->link_params.port * 4, 0);
7077                         bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7078                         bnx2x_link_report(sc);
7079                 }
7080         }
7081
7082         if (IS_PF(sc)) {
7083                 if (sc->link_vars.link_up) {
7084                         bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7085                 } else {
7086                         bnx2x_stats_handle(sc, STATS_EVENT_STOP);
7087                 }
7088                 bnx2x_link_report(sc);
7089         } else {
7090                 bnx2x_link_report_locked(sc);
7091                 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7092         }
7093 }
7094
7095 static int bnx2x_initial_phy_init(struct bnx2x_softc *sc, int load_mode)
7096 {
7097         int rc, cfg_idx = bnx2x_get_link_cfg_idx(sc);
7098         uint16_t req_line_speed = sc->link_params.req_line_speed[cfg_idx];
7099         struct elink_params *lp = &sc->link_params;
7100
7101         bnx2x_set_requested_fc(sc);
7102
7103         bnx2x_acquire_phy_lock(sc);
7104
7105         if (load_mode == LOAD_DIAG) {
7106                 lp->loopback_mode = ELINK_LOOPBACK_XGXS;
7107 /* Prefer doing PHY loopback at 10G speed, if possible */
7108                 if (lp->req_line_speed[cfg_idx] < ELINK_SPEED_10000) {
7109                         if (lp->speed_cap_mask[cfg_idx] &
7110                             PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
7111                                 lp->req_line_speed[cfg_idx] = ELINK_SPEED_10000;
7112                         } else {
7113                                 lp->req_line_speed[cfg_idx] = ELINK_SPEED_1000;
7114                         }
7115                 }
7116         }
7117
7118         if (load_mode == LOAD_LOOPBACK_EXT) {
7119                 lp->loopback_mode = ELINK_LOOPBACK_EXT;
7120         }
7121
7122         rc = elink_phy_init(&sc->link_params, &sc->link_vars);
7123
7124         bnx2x_release_phy_lock(sc);
7125
7126         bnx2x_calc_fc_adv(sc);
7127
7128         if (sc->link_vars.link_up) {
7129                 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7130                 bnx2x_link_report(sc);
7131         }
7132
7133         sc->link_params.req_line_speed[cfg_idx] = req_line_speed;
7134         return rc;
7135 }
7136
7137 /* update flags in shmem */
7138 static void
7139 bnx2x_update_drv_flags(struct bnx2x_softc *sc, uint32_t flags, uint32_t set)
7140 {
7141         uint32_t drv_flags;
7142
7143         if (SHMEM2_HAS(sc, drv_flags)) {
7144                 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7145                 drv_flags = SHMEM2_RD(sc, drv_flags);
7146
7147                 if (set) {
7148                         drv_flags |= flags;
7149                 } else {
7150                         drv_flags &= ~flags;
7151                 }
7152
7153                 SHMEM2_WR(sc, drv_flags, drv_flags);
7154
7155                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7156         }
7157 }
7158
7159 /* periodic timer callout routine, only runs when the interface is up */
7160 void bnx2x_periodic_callout(struct bnx2x_softc *sc)
7161 {
7162         if ((sc->state != BNX2X_STATE_OPEN) ||
7163             (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_STOP)) {
7164                 PMD_DRV_LOG(DEBUG, sc, "periodic callout exit (state=0x%x)",
7165                             sc->state);
7166                 return;
7167         }
7168         if (!CHIP_REV_IS_SLOW(sc)) {
7169 /*
7170  * This barrier is needed to ensure the ordering between the writing
7171  * to the sc->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
7172  * the reading here.
7173  */
7174                 mb();
7175                 if (sc->port.pmf) {
7176                         bnx2x_acquire_phy_lock(sc);
7177                         elink_period_func(&sc->link_params, &sc->link_vars);
7178                         bnx2x_release_phy_lock(sc);
7179                 }
7180         }
7181 #ifdef BNX2X_PULSE
7182         if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7183                 int mb_idx = SC_FW_MB_IDX(sc);
7184                 uint32_t drv_pulse;
7185                 uint32_t mcp_pulse;
7186
7187                 ++sc->fw_drv_pulse_wr_seq;
7188                 sc->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
7189
7190                 drv_pulse = sc->fw_drv_pulse_wr_seq;
7191                 bnx2x_drv_pulse(sc);
7192
7193                 mcp_pulse = (SHMEM_RD(sc, func_mb[mb_idx].mcp_pulse_mb) &
7194                              MCP_PULSE_SEQ_MASK);
7195
7196 /*
7197  * The delta between driver pulse and mcp response should
7198  * be 1 (before mcp response) or 0 (after mcp response).
7199  */
7200                 if ((drv_pulse != mcp_pulse) &&
7201                     (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
7202                         /* someone lost a heartbeat... */
7203                         PMD_DRV_LOG(ERR, sc,
7204                                     "drv_pulse (0x%x) != mcp_pulse (0x%x)",
7205                                     drv_pulse, mcp_pulse);
7206                 }
7207         }
7208 #endif
7209 }
7210
7211 /* start the controller */
7212 static __rte_noinline
7213 int bnx2x_nic_load(struct bnx2x_softc *sc)
7214 {
7215         uint32_t val;
7216         uint32_t load_code = 0;
7217         int i, rc = 0;
7218
7219         PMD_INIT_FUNC_TRACE(sc);
7220
7221         sc->state = BNX2X_STATE_OPENING_WAITING_LOAD;
7222
7223         if (IS_PF(sc)) {
7224 /* must be called before memory allocation and HW init */
7225                 bnx2x_ilt_set_info(sc);
7226         }
7227
7228         bnx2x_set_fp_rx_buf_size(sc);
7229
7230         if (IS_PF(sc)) {
7231                 if (bnx2x_alloc_mem(sc) != 0) {
7232                         sc->state = BNX2X_STATE_CLOSED;
7233                         rc = -ENOMEM;
7234                         goto bnx2x_nic_load_error0;
7235                 }
7236         }
7237
7238         /* allocate the host hardware/software hsi structures */
7239         if (bnx2x_alloc_hsi_mem(sc) != 0) {
7240                 PMD_DRV_LOG(ERR, sc, "bnx2x_alloc_hsi_mem was failed");
7241                 sc->state = BNX2X_STATE_CLOSED;
7242                 rc = -ENOMEM;
7243                 goto bnx2x_nic_load_error0;
7244         }
7245
7246         if (bnx2x_alloc_fw_stats_mem(sc) != 0) {
7247                 sc->state = BNX2X_STATE_CLOSED;
7248                 rc = -ENOMEM;
7249                 goto bnx2x_nic_load_error0;
7250         }
7251
7252         if (IS_VF(sc)) {
7253                 rc = bnx2x_vf_init(sc);
7254                 if (rc) {
7255                         sc->state = BNX2X_STATE_ERROR;
7256                         goto bnx2x_nic_load_error0;
7257                 }
7258         }
7259
7260         if (IS_PF(sc)) {
7261 /* set pf load just before approaching the MCP */
7262                 bnx2x_set_pf_load(sc);
7263
7264 /* if MCP exists send load request and analyze response */
7265                 if (!BNX2X_NOMCP(sc)) {
7266                         /* attempt to load pf */
7267                         if (bnx2x_nic_load_request(sc, &load_code) != 0) {
7268                                 sc->state = BNX2X_STATE_CLOSED;
7269                                 rc = -ENXIO;
7270                                 goto bnx2x_nic_load_error1;
7271                         }
7272
7273                         /* what did the MCP say? */
7274                         if (bnx2x_nic_load_analyze_req(sc, load_code) != 0) {
7275                                 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7276                                 sc->state = BNX2X_STATE_CLOSED;
7277                                 rc = -ENXIO;
7278                                 goto bnx2x_nic_load_error2;
7279                         }
7280                 } else {
7281                         PMD_DRV_LOG(INFO, sc, "Device has no MCP!");
7282                         load_code = bnx2x_nic_load_no_mcp(sc);
7283                 }
7284
7285 /* mark PMF if applicable */
7286                 bnx2x_nic_load_pmf(sc, load_code);
7287
7288 /* Init Function state controlling object */
7289                 bnx2x_init_func_obj(sc);
7290
7291 /* Initialize HW */
7292                 if (bnx2x_init_hw(sc, load_code) != 0) {
7293                         PMD_DRV_LOG(NOTICE, sc, "HW init failed");
7294                         bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7295                         sc->state = BNX2X_STATE_CLOSED;
7296                         rc = -ENXIO;
7297                         goto bnx2x_nic_load_error2;
7298                 }
7299         }
7300
7301         bnx2x_nic_init(sc, load_code);
7302
7303         /* Init per-function objects */
7304         if (IS_PF(sc)) {
7305                 bnx2x_init_objs(sc);
7306
7307 /* set AFEX default VLAN tag to an invalid value */
7308                 sc->devinfo.mf_info.afex_def_vlan_tag = -1;
7309
7310                 sc->state = BNX2X_STATE_OPENING_WAITING_PORT;
7311                 rc = bnx2x_func_start(sc);
7312                 if (rc) {
7313                         PMD_DRV_LOG(NOTICE, sc, "Function start failed!");
7314                         bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7315                         sc->state = BNX2X_STATE_ERROR;
7316                         goto bnx2x_nic_load_error3;
7317                 }
7318
7319 /* send LOAD_DONE command to MCP */
7320                 if (!BNX2X_NOMCP(sc)) {
7321                         load_code =
7322                             bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7323                         if (!load_code) {
7324                                 PMD_DRV_LOG(NOTICE, sc,
7325                                             "MCP response failure, aborting");
7326                                 sc->state = BNX2X_STATE_ERROR;
7327                                 rc = -ENXIO;
7328                                 goto bnx2x_nic_load_error3;
7329                         }
7330                 }
7331         }
7332
7333         rc = bnx2x_setup_leading(sc);
7334         if (rc) {
7335                 PMD_DRV_LOG(NOTICE, sc, "Setup leading failed!");
7336                 sc->state = BNX2X_STATE_ERROR;
7337                 goto bnx2x_nic_load_error3;
7338         }
7339
7340         FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, i) {
7341                 if (IS_PF(sc))
7342                         rc = bnx2x_setup_queue(sc, &sc->fp[i], FALSE);
7343                 else            /* IS_VF(sc) */
7344                         rc = bnx2x_vf_setup_queue(sc, &sc->fp[i], FALSE);
7345
7346                 if (rc) {
7347                         PMD_DRV_LOG(NOTICE, sc, "Queue(%d) setup failed", i);
7348                         sc->state = BNX2X_STATE_ERROR;
7349                         goto bnx2x_nic_load_error3;
7350                 }
7351         }
7352
7353         rc = bnx2x_init_rss_pf(sc);
7354         if (rc) {
7355                 PMD_DRV_LOG(NOTICE, sc, "PF RSS init failed");
7356                 sc->state = BNX2X_STATE_ERROR;
7357                 goto bnx2x_nic_load_error3;
7358         }
7359
7360         /* now when Clients are configured we are ready to work */
7361         sc->state = BNX2X_STATE_OPEN;
7362
7363         /* Configure a ucast MAC */
7364         if (IS_PF(sc)) {
7365                 rc = bnx2x_set_eth_mac(sc, TRUE);
7366         } else {                /* IS_VF(sc) */
7367                 rc = bnx2x_vf_set_mac(sc, TRUE);
7368         }
7369
7370         if (rc) {
7371                 PMD_DRV_LOG(NOTICE, sc, "Setting Ethernet MAC failed");
7372                 sc->state = BNX2X_STATE_ERROR;
7373                 goto bnx2x_nic_load_error3;
7374         }
7375
7376         if (sc->port.pmf) {
7377                 rc = bnx2x_initial_phy_init(sc, LOAD_OPEN);
7378                 if (rc) {
7379                         sc->state = BNX2X_STATE_ERROR;
7380                         goto bnx2x_nic_load_error3;
7381                 }
7382         }
7383
7384         sc->link_params.feature_config_flags &=
7385             ~ELINK_FEATURE_CONFIG_BOOT_FROM_SAN;
7386
7387         /* start the Tx */
7388         switch (LOAD_OPEN) {
7389         case LOAD_NORMAL:
7390         case LOAD_OPEN:
7391                 break;
7392
7393         case LOAD_DIAG:
7394         case LOAD_LOOPBACK_EXT:
7395                 sc->state = BNX2X_STATE_DIAG;
7396                 break;
7397
7398         default:
7399                 break;
7400         }
7401
7402         if (sc->port.pmf) {
7403                 bnx2x_update_drv_flags(sc, 1 << DRV_FLAGS_PORT_MASK, 0);
7404         } else {
7405                 bnx2x_link_status_update(sc);
7406         }
7407
7408         if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
7409 /* mark driver is loaded in shmem2 */
7410                 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
7411                 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
7412                           (val |
7413                            DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED |
7414                            DRV_FLAGS_CAPABILITIES_LOADED_L2));
7415         }
7416
7417         /* start fast path */
7418         /* Initialize Rx filter */
7419         bnx2x_set_rx_mode(sc);
7420
7421         /* wait for all pending SP commands to complete */
7422         if (IS_PF(sc) && !bnx2x_wait_sp_comp(sc, ~0x0U)) {
7423                 PMD_DRV_LOG(NOTICE, sc, "Timeout waiting for all SPs to complete!");
7424                 bnx2x_periodic_stop(sc);
7425                 bnx2x_nic_unload(sc, UNLOAD_CLOSE, FALSE);
7426                 return -ENXIO;
7427         }
7428
7429         PMD_DRV_LOG(DEBUG, sc, "NIC successfully loaded");
7430
7431         return 0;
7432
7433 bnx2x_nic_load_error3:
7434
7435         if (IS_PF(sc)) {
7436                 bnx2x_int_disable_sync(sc, 1);
7437
7438 /* clean out queued objects */
7439                 bnx2x_squeeze_objects(sc);
7440         }
7441
7442 bnx2x_nic_load_error2:
7443
7444         if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7445                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
7446                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
7447         }
7448
7449         sc->port.pmf = 0;
7450
7451 bnx2x_nic_load_error1:
7452
7453         /* clear pf_load status, as it was already set */
7454         if (IS_PF(sc)) {
7455                 bnx2x_clear_pf_load(sc);
7456         }
7457
7458 bnx2x_nic_load_error0:
7459
7460         bnx2x_free_fw_stats_mem(sc);
7461         bnx2x_free_hsi_mem(sc);
7462         bnx2x_free_mem(sc);
7463
7464         return rc;
7465 }
7466
7467 /*
7468 * Handles controller initialization.
7469 */
7470 int bnx2x_init(struct bnx2x_softc *sc)
7471 {
7472         int other_engine = SC_PATH(sc) ? 0 : 1;
7473         uint8_t other_load_status, load_status;
7474         uint8_t global = FALSE;
7475         int rc;
7476
7477         /* Check if the driver is still running and bail out if it is. */
7478         if (sc->state != BNX2X_STATE_CLOSED) {
7479                 PMD_DRV_LOG(DEBUG, sc, "Init called while driver is running!");
7480                 rc = 0;
7481                 goto bnx2x_init_done;
7482         }
7483
7484         bnx2x_set_power_state(sc, PCI_PM_D0);
7485
7486         /*
7487          * If parity occurred during the unload, then attentions and/or
7488          * RECOVERY_IN_PROGRESS may still be set. If so we want the first function
7489          * loaded on the current engine to complete the recovery. Parity recovery
7490          * is only relevant for PF driver.
7491          */
7492         if (IS_PF(sc)) {
7493                 other_load_status = bnx2x_get_load_status(sc, other_engine);
7494                 load_status = bnx2x_get_load_status(sc, SC_PATH(sc));
7495
7496                 if (!bnx2x_reset_is_done(sc, SC_PATH(sc)) ||
7497                     bnx2x_chk_parity_attn(sc, &global, TRUE)) {
7498                         do {
7499                                 /*
7500                                  * If there are attentions and they are in global blocks, set
7501                                  * the GLOBAL_RESET bit regardless whether it will be this
7502                                  * function that will complete the recovery or not.
7503                                  */
7504                                 if (global) {
7505                                         bnx2x_set_reset_global(sc);
7506                                 }
7507
7508                                 /*
7509                                  * Only the first function on the current engine should try
7510                                  * to recover in open. In case of attentions in global blocks
7511                                  * only the first in the chip should try to recover.
7512                                  */
7513                                 if ((!load_status
7514                                      && (!global ||!other_load_status))
7515                                     && bnx2x_trylock_leader_lock(sc)
7516                                     && !bnx2x_leader_reset(sc)) {
7517                                         PMD_DRV_LOG(INFO, sc,
7518                                                     "Recovered during init");
7519                                         break;
7520                                 }
7521
7522                                 /* recovery has failed... */
7523                                 bnx2x_set_power_state(sc, PCI_PM_D3hot);
7524
7525                                 sc->recovery_state = BNX2X_RECOVERY_FAILED;
7526
7527                                 PMD_DRV_LOG(NOTICE, sc,
7528                                             "Recovery flow hasn't properly "
7529                                             "completed yet, try again later. "
7530                                             "If you still see this message after a "
7531                                             "few retries then power cycle is required.");
7532
7533                                 rc = -ENXIO;
7534                                 goto bnx2x_init_done;
7535                         } while (0);
7536                 }
7537         }
7538
7539         sc->recovery_state = BNX2X_RECOVERY_DONE;
7540
7541         rc = bnx2x_nic_load(sc);
7542
7543 bnx2x_init_done:
7544
7545         if (rc) {
7546                 PMD_DRV_LOG(NOTICE, sc, "Initialization failed, "
7547                             "stack notified driver is NOT running!");
7548         }
7549
7550         return rc;
7551 }
7552
7553 static void bnx2x_get_function_num(struct bnx2x_softc *sc)
7554 {
7555         uint32_t val = 0;
7556
7557         /*
7558          * Read the ME register to get the function number. The ME register
7559          * holds the relative-function number and absolute-function number. The
7560          * absolute-function number appears only in E2 and above. Before that
7561          * these bits always contained zero, therefore we cannot blindly use them.
7562          */
7563
7564         val = REG_RD(sc, BAR_ME_REGISTER);
7565
7566         sc->pfunc_rel =
7567             (uint8_t) ((val & ME_REG_PF_NUM) >> ME_REG_PF_NUM_SHIFT);
7568         sc->path_id =
7569             (uint8_t) ((val & ME_REG_ABS_PF_NUM) >> ME_REG_ABS_PF_NUM_SHIFT) &
7570             1;
7571
7572         if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7573                 sc->pfunc_abs = ((sc->pfunc_rel << 1) | sc->path_id);
7574         } else {
7575                 sc->pfunc_abs = (sc->pfunc_rel | sc->path_id);
7576         }
7577
7578         PMD_DRV_LOG(DEBUG, sc,
7579                     "Relative function %d, Absolute function %d, Path %d",
7580                     sc->pfunc_rel, sc->pfunc_abs, sc->path_id);
7581 }
7582
7583 static uint32_t bnx2x_get_shmem_mf_cfg_base(struct bnx2x_softc *sc)
7584 {
7585         uint32_t shmem2_size;
7586         uint32_t offset;
7587         uint32_t mf_cfg_offset_value;
7588
7589         /* Non 57712 */
7590         offset = (SHMEM_ADDR(sc, func_mb) +
7591                   (MAX_FUNC_NUM * sizeof(struct drv_func_mb)));
7592
7593         /* 57712 plus */
7594         if (sc->devinfo.shmem2_base != 0) {
7595                 shmem2_size = SHMEM2_RD(sc, size);
7596                 if (shmem2_size > offsetof(struct shmem2_region, mf_cfg_addr)) {
7597                         mf_cfg_offset_value = SHMEM2_RD(sc, mf_cfg_addr);
7598                         if (SHMEM_MF_CFG_ADDR_NONE != mf_cfg_offset_value) {
7599                                 offset = mf_cfg_offset_value;
7600                         }
7601                 }
7602         }
7603
7604         return offset;
7605 }
7606
7607 static uint32_t bnx2x_pcie_capability_read(struct bnx2x_softc *sc, int reg)
7608 {
7609         uint32_t ret;
7610         struct bnx2x_pci_cap *caps;
7611
7612         /* ensure PCIe capability is enabled */
7613         caps = pci_find_cap(sc, PCIY_EXPRESS, BNX2X_PCI_CAP);
7614         if (NULL != caps) {
7615                 PMD_DRV_LOG(DEBUG, sc, "Found PCIe capability: "
7616                             "id=0x%04X type=0x%04X addr=0x%08X",
7617                             caps->id, caps->type, caps->addr);
7618                 pci_read(sc, (caps->addr + reg), &ret, 2);
7619                 return ret;
7620         }
7621
7622         PMD_DRV_LOG(WARNING, sc, "PCIe capability NOT FOUND!!!");
7623
7624         return 0;
7625 }
7626
7627 static uint8_t bnx2x_is_pcie_pending(struct bnx2x_softc *sc)
7628 {
7629         return bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_STA) &
7630                 PCIM_EXP_STA_TRANSACTION_PND;
7631 }
7632
7633 /*
7634 * Walk the PCI capabiites list for the device to find what features are
7635 * supported. These capabilites may be enabled/disabled by firmware so it's
7636 * best to walk the list rather than make assumptions.
7637 */
7638 static void bnx2x_probe_pci_caps(struct bnx2x_softc *sc)
7639 {
7640         PMD_INIT_FUNC_TRACE(sc);
7641
7642         struct bnx2x_pci_cap *caps;
7643         uint16_t link_status;
7644         int reg = 0;
7645
7646         /* check if PCI Power Management is enabled */
7647         caps = pci_find_cap(sc, PCIY_PMG, BNX2X_PCI_CAP);
7648         if (NULL != caps) {
7649                 PMD_DRV_LOG(DEBUG, sc, "Found PM capability: "
7650                             "id=0x%04X type=0x%04X addr=0x%08X",
7651                             caps->id, caps->type, caps->addr);
7652
7653                 sc->devinfo.pcie_cap_flags |= BNX2X_PM_CAPABLE_FLAG;
7654                 sc->devinfo.pcie_pm_cap_reg = caps->addr;
7655         }
7656
7657         link_status = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_LINK_STA);
7658
7659         sc->devinfo.pcie_link_speed = (link_status & PCIM_LINK_STA_SPEED);
7660         sc->devinfo.pcie_link_width =
7661             ((link_status & PCIM_LINK_STA_WIDTH) >> 4);
7662
7663         PMD_DRV_LOG(DEBUG, sc, "PCIe link speed=%d width=%d",
7664                     sc->devinfo.pcie_link_speed, sc->devinfo.pcie_link_width);
7665
7666         sc->devinfo.pcie_cap_flags |= BNX2X_PCIE_CAPABLE_FLAG;
7667
7668         /* check if MSI capability is enabled */
7669         caps = pci_find_cap(sc, PCIY_MSI, BNX2X_PCI_CAP);
7670         if (NULL != caps) {
7671                 PMD_DRV_LOG(DEBUG, sc, "Found MSI capability at 0x%04x", reg);
7672
7673                 sc->devinfo.pcie_cap_flags |= BNX2X_MSI_CAPABLE_FLAG;
7674                 sc->devinfo.pcie_msi_cap_reg = caps->addr;
7675         }
7676
7677         /* check if MSI-X capability is enabled */
7678         caps = pci_find_cap(sc, PCIY_MSIX, BNX2X_PCI_CAP);
7679         if (NULL != caps) {
7680                 PMD_DRV_LOG(DEBUG, sc, "Found MSI-X capability at 0x%04x", reg);
7681
7682                 sc->devinfo.pcie_cap_flags |= BNX2X_MSIX_CAPABLE_FLAG;
7683                 sc->devinfo.pcie_msix_cap_reg = caps->addr;
7684         }
7685 }
7686
7687 static int bnx2x_get_shmem_mf_cfg_info_sd(struct bnx2x_softc *sc)
7688 {
7689         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7690         uint32_t val;
7691
7692         /* get the outer vlan if we're in switch-dependent mode */
7693
7694         val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7695         mf_info->ext_id = (uint16_t) val;
7696
7697         mf_info->multi_vnics_mode = 1;
7698
7699         if (!VALID_OVLAN(mf_info->ext_id)) {
7700                 PMD_DRV_LOG(NOTICE, sc, "Invalid VLAN (%d)", mf_info->ext_id);
7701                 return 1;
7702         }
7703
7704         /* get the capabilities */
7705         if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK) ==
7706             FUNC_MF_CFG_PROTOCOL_ISCSI) {
7707                 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ISCSI;
7708         } else if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK)
7709                    == FUNC_MF_CFG_PROTOCOL_FCOE) {
7710                 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_FCOE;
7711         } else {
7712                 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ETHERNET;
7713         }
7714
7715         mf_info->vnics_per_port =
7716             (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7717
7718         return 0;
7719 }
7720
7721 static uint32_t bnx2x_get_shmem_ext_proto_support_flags(struct bnx2x_softc *sc)
7722 {
7723         uint32_t retval = 0;
7724         uint32_t val;
7725
7726         val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7727
7728         if (val & MACP_FUNC_CFG_FLAGS_ENABLED) {
7729                 if (val & MACP_FUNC_CFG_FLAGS_ETHERNET) {
7730                         retval |= MF_PROTO_SUPPORT_ETHERNET;
7731                 }
7732                 if (val & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
7733                         retval |= MF_PROTO_SUPPORT_ISCSI;
7734                 }
7735                 if (val & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
7736                         retval |= MF_PROTO_SUPPORT_FCOE;
7737                 }
7738         }
7739
7740         return retval;
7741 }
7742
7743 static int bnx2x_get_shmem_mf_cfg_info_si(struct bnx2x_softc *sc)
7744 {
7745         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7746         uint32_t val;
7747
7748         /*
7749          * There is no outer vlan if we're in switch-independent mode.
7750          * If the mac is valid then assume multi-function.
7751          */
7752
7753         val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7754
7755         mf_info->multi_vnics_mode = ((val & MACP_FUNC_CFG_FLAGS_MASK) != 0);
7756
7757         mf_info->mf_protos_supported =
7758             bnx2x_get_shmem_ext_proto_support_flags(sc);
7759
7760         mf_info->vnics_per_port =
7761             (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7762
7763         return 0;
7764 }
7765
7766 static int bnx2x_get_shmem_mf_cfg_info_niv(struct bnx2x_softc *sc)
7767 {
7768         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7769         uint32_t e1hov_tag;
7770         uint32_t func_config;
7771         uint32_t niv_config;
7772
7773         mf_info->multi_vnics_mode = 1;
7774
7775         e1hov_tag = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7776         func_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7777         niv_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].afex_config);
7778
7779         mf_info->ext_id =
7780             (uint16_t) ((e1hov_tag & FUNC_MF_CFG_E1HOV_TAG_MASK) >>
7781                         FUNC_MF_CFG_E1HOV_TAG_SHIFT);
7782
7783         mf_info->default_vlan =
7784             (uint16_t) ((e1hov_tag & FUNC_MF_CFG_AFEX_VLAN_MASK) >>
7785                         FUNC_MF_CFG_AFEX_VLAN_SHIFT);
7786
7787         mf_info->niv_allowed_priorities =
7788             (uint8_t) ((niv_config & FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
7789                        FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT);
7790
7791         mf_info->niv_default_cos =
7792             (uint8_t) ((func_config & FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
7793                        FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT);
7794
7795         mf_info->afex_vlan_mode =
7796             ((niv_config & FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
7797              FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT);
7798
7799         mf_info->niv_mba_enabled =
7800             ((niv_config & FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK) >>
7801              FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT);
7802
7803         mf_info->mf_protos_supported =
7804             bnx2x_get_shmem_ext_proto_support_flags(sc);
7805
7806         mf_info->vnics_per_port =
7807             (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7808
7809         return 0;
7810 }
7811
7812 static int bnx2x_check_valid_mf_cfg(struct bnx2x_softc *sc)
7813 {
7814         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7815         uint32_t mf_cfg1;
7816         uint32_t mf_cfg2;
7817         uint32_t ovlan1;
7818         uint32_t ovlan2;
7819         uint8_t i, j;
7820
7821         /* various MF mode sanity checks... */
7822
7823         if (mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_HIDE) {
7824                 PMD_DRV_LOG(NOTICE, sc,
7825                             "Enumerated function %d is marked as hidden",
7826                             SC_PORT(sc));
7827                 return 1;
7828         }
7829
7830         if ((mf_info->vnics_per_port > 1) && !mf_info->multi_vnics_mode) {
7831                 PMD_DRV_LOG(NOTICE, sc, "vnics_per_port=%d multi_vnics_mode=%d",
7832                             mf_info->vnics_per_port, mf_info->multi_vnics_mode);
7833                 return 1;
7834         }
7835
7836         if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7837 /* vnic id > 0 must have valid ovlan in switch-dependent mode */
7838                 if ((SC_VN(sc) > 0) && !VALID_OVLAN(OVLAN(sc))) {
7839                         PMD_DRV_LOG(NOTICE, sc, "mf_mode=SD vnic_id=%d ovlan=%d",
7840                                     SC_VN(sc), OVLAN(sc));
7841                         return 1;
7842                 }
7843
7844                 if (!VALID_OVLAN(OVLAN(sc)) && mf_info->multi_vnics_mode) {
7845                         PMD_DRV_LOG(NOTICE, sc,
7846                                     "mf_mode=SD multi_vnics_mode=%d ovlan=%d",
7847                                     mf_info->multi_vnics_mode, OVLAN(sc));
7848                         return 1;
7849                 }
7850
7851 /*
7852  * Verify all functions are either MF or SF mode. If MF, make sure
7853  * sure that all non-hidden functions have a valid ovlan. If SF,
7854  * make sure that all non-hidden functions have an invalid ovlan.
7855  */
7856                 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7857                         mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7858                         ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7859                         if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE) &&
7860                             (((mf_info->multi_vnics_mode)
7861                               && !VALID_OVLAN(ovlan1))
7862                              || ((!mf_info->multi_vnics_mode)
7863                                  && VALID_OVLAN(ovlan1)))) {
7864                                 PMD_DRV_LOG(NOTICE, sc,
7865                                             "mf_mode=SD function %d MF config "
7866                                             "mismatch, multi_vnics_mode=%d ovlan=%d",
7867                                             i, mf_info->multi_vnics_mode,
7868                                             ovlan1);
7869                                 return 1;
7870                         }
7871                 }
7872
7873 /* Verify all funcs on the same port each have a different ovlan. */
7874                 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7875                         mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7876                         ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7877                         /* iterate from the next function on the port to the max func */
7878                         for (j = i + 2; j < MAX_FUNC_NUM; j += 2) {
7879                                 mf_cfg2 =
7880                                     MFCFG_RD(sc, func_mf_config[j].config);
7881                                 ovlan2 =
7882                                     MFCFG_RD(sc, func_mf_config[j].e1hov_tag);
7883                                 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE)
7884                                     && VALID_OVLAN(ovlan1)
7885                                     && !(mf_cfg2 & FUNC_MF_CFG_FUNC_HIDE)
7886                                     && VALID_OVLAN(ovlan2)
7887                                     && (ovlan1 == ovlan2)) {
7888                                         PMD_DRV_LOG(NOTICE, sc,
7889                                                     "mf_mode=SD functions %d and %d "
7890                                                     "have the same ovlan (%d)",
7891                                                     i, j, ovlan1);
7892                                         return 1;
7893                                 }
7894                         }
7895                 }
7896         }
7897         /* MULTI_FUNCTION_SD */
7898         return 0;
7899 }
7900
7901 static int bnx2x_get_mf_cfg_info(struct bnx2x_softc *sc)
7902 {
7903         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7904         uint32_t val, mac_upper;
7905         uint8_t i, vnic;
7906
7907         /* initialize mf_info defaults */
7908         mf_info->vnics_per_port = 1;
7909         mf_info->multi_vnics_mode = FALSE;
7910         mf_info->path_has_ovlan = FALSE;
7911         mf_info->mf_mode = SINGLE_FUNCTION;
7912
7913         if (!CHIP_IS_MF_CAP(sc)) {
7914                 return 0;
7915         }
7916
7917         if (sc->devinfo.mf_cfg_base == SHMEM_MF_CFG_ADDR_NONE) {
7918                 PMD_DRV_LOG(NOTICE, sc, "Invalid mf_cfg_base!");
7919                 return 1;
7920         }
7921
7922         /* get the MF mode (switch dependent / independent / single-function) */
7923
7924         val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
7925
7926         switch (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK) {
7927         case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
7928
7929                 mac_upper =
7930                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7931
7932                 /* check for legal upper mac bytes */
7933                 if (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT) {
7934                         mf_info->mf_mode = MULTI_FUNCTION_SI;
7935                 } else {
7936                         PMD_DRV_LOG(NOTICE, sc,
7937                                     "Invalid config for Switch Independent mode");
7938                 }
7939
7940                 break;
7941
7942         case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
7943         case SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4:
7944
7945                 /* get outer vlan configuration */
7946                 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7947
7948                 if ((val & FUNC_MF_CFG_E1HOV_TAG_MASK) !=
7949                     FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
7950                         mf_info->mf_mode = MULTI_FUNCTION_SD;
7951                 } else {
7952                         PMD_DRV_LOG(NOTICE, sc,
7953                                     "Invalid config for Switch Dependent mode");
7954                 }
7955
7956                 break;
7957
7958         case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
7959
7960                 /* not in MF mode, vnics_per_port=1 and multi_vnics_mode=FALSE */
7961                 return 0;
7962
7963         case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
7964
7965                 /*
7966                  * Mark MF mode as NIV if MCP version includes NPAR-SD support
7967                  * and the MAC address is valid.
7968                  */
7969                 mac_upper =
7970                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7971
7972                 if ((SHMEM2_HAS(sc, afex_driver_support)) &&
7973                     (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT)) {
7974                         mf_info->mf_mode = MULTI_FUNCTION_AFEX;
7975                 } else {
7976                         PMD_DRV_LOG(NOTICE, sc, "Invalid config for AFEX mode");
7977                 }
7978
7979                 break;
7980
7981         default:
7982
7983                 PMD_DRV_LOG(NOTICE, sc, "Unknown MF mode (0x%08x)",
7984                             (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK));
7985
7986                 return 1;
7987         }
7988
7989         /* set path mf_mode (which could be different than function mf_mode) */
7990         if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7991                 mf_info->path_has_ovlan = TRUE;
7992         } else if (mf_info->mf_mode == SINGLE_FUNCTION) {
7993 /*
7994  * Decide on path multi vnics mode. If we're not in MF mode and in
7995  * 4-port mode, this is good enough to check vnic-0 of the other port
7996  * on the same path
7997  */
7998                 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7999                         uint8_t other_port = !(PORT_ID(sc) & 1);
8000                         uint8_t abs_func_other_port =
8001                             (SC_PATH(sc) + (2 * other_port));
8002
8003                         val =
8004                             MFCFG_RD(sc,
8005                                      func_mf_config
8006                                      [abs_func_other_port].e1hov_tag);
8007
8008                         mf_info->path_has_ovlan = VALID_OVLAN((uint16_t) val);
8009                 }
8010         }
8011
8012         if (mf_info->mf_mode == SINGLE_FUNCTION) {
8013 /* invalid MF config */
8014                 if (SC_VN(sc) >= 1) {
8015                         PMD_DRV_LOG(NOTICE, sc, "VNIC ID >= 1 in SF mode");
8016                         return 1;
8017                 }
8018
8019                 return 0;
8020         }
8021
8022         /* get the MF configuration */
8023         mf_info->mf_config[SC_VN(sc)] =
8024             MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
8025
8026         switch (mf_info->mf_mode) {
8027         case MULTI_FUNCTION_SD:
8028
8029                 bnx2x_get_shmem_mf_cfg_info_sd(sc);
8030                 break;
8031
8032         case MULTI_FUNCTION_SI:
8033
8034                 bnx2x_get_shmem_mf_cfg_info_si(sc);
8035                 break;
8036
8037         case MULTI_FUNCTION_AFEX:
8038
8039                 bnx2x_get_shmem_mf_cfg_info_niv(sc);
8040                 break;
8041
8042         default:
8043
8044                 PMD_DRV_LOG(NOTICE, sc, "Get MF config failed (mf_mode=0x%08x)",
8045                             mf_info->mf_mode);
8046                 return 1;
8047         }
8048
8049         /* get the congestion management parameters */
8050
8051         vnic = 0;
8052         FOREACH_ABS_FUNC_IN_PORT(sc, i) {
8053 /* get min/max bw */
8054                 val = MFCFG_RD(sc, func_mf_config[i].config);
8055                 mf_info->min_bw[vnic] =
8056                     ((val & FUNC_MF_CFG_MIN_BW_MASK) >>
8057                      FUNC_MF_CFG_MIN_BW_SHIFT);
8058                 mf_info->max_bw[vnic] =
8059                     ((val & FUNC_MF_CFG_MAX_BW_MASK) >>
8060                      FUNC_MF_CFG_MAX_BW_SHIFT);
8061                 vnic++;
8062         }
8063
8064         return bnx2x_check_valid_mf_cfg(sc);
8065 }
8066
8067 static int bnx2x_get_shmem_info(struct bnx2x_softc *sc)
8068 {
8069         int port;
8070         uint32_t mac_hi, mac_lo, val;
8071
8072         PMD_INIT_FUNC_TRACE(sc);
8073
8074         port = SC_PORT(sc);
8075         mac_hi = mac_lo = 0;
8076
8077         sc->link_params.sc = sc;
8078         sc->link_params.port = port;
8079
8080         /* get the hardware config info */
8081         sc->devinfo.hw_config = SHMEM_RD(sc, dev_info.shared_hw_config.config);
8082         sc->devinfo.hw_config2 =
8083             SHMEM_RD(sc, dev_info.shared_hw_config.config2);
8084
8085         sc->link_params.hw_led_mode =
8086             ((sc->devinfo.hw_config & SHARED_HW_CFG_LED_MODE_MASK) >>
8087              SHARED_HW_CFG_LED_MODE_SHIFT);
8088
8089         /* get the port feature config */
8090         sc->port.config =
8091             SHMEM_RD(sc, dev_info.port_feature_config[port].config);
8092
8093         /* get the link params */
8094         sc->link_params.speed_cap_mask[ELINK_INT_PHY] =
8095             SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask)
8096             & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
8097         sc->link_params.speed_cap_mask[ELINK_EXT_PHY1] =
8098             SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask2)
8099             & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
8100
8101         /* get the lane config */
8102         sc->link_params.lane_config =
8103             SHMEM_RD(sc, dev_info.port_hw_config[port].lane_config);
8104
8105         /* get the link config */
8106         val = SHMEM_RD(sc, dev_info.port_feature_config[port].link_config);
8107         sc->port.link_config[ELINK_INT_PHY] = val;
8108         sc->link_params.switch_cfg = (val & PORT_FEATURE_CONNECTED_SWITCH_MASK);
8109         sc->port.link_config[ELINK_EXT_PHY1] =
8110             SHMEM_RD(sc, dev_info.port_feature_config[port].link_config2);
8111
8112         /* get the override preemphasis flag and enable it or turn it off */
8113         val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
8114         if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) {
8115                 sc->link_params.feature_config_flags |=
8116                     ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8117         } else {
8118                 sc->link_params.feature_config_flags &=
8119                     ~ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8120         }
8121
8122         val = sc->devinfo.bc_ver >> 8;
8123         if (val < BNX2X_BC_VER) {
8124                 /* for now only warn later we might need to enforce this */
8125                 PMD_DRV_LOG(NOTICE, sc, "This driver needs bc_ver %X but found %X, please upgrade BC\n",
8126                             BNX2X_BC_VER, val);
8127         }
8128         sc->link_params.feature_config_flags |=
8129                                 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
8130                                 ELINK_FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY :
8131                                 0;
8132
8133         sc->link_params.feature_config_flags |=
8134                 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
8135                 ELINK_FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
8136         sc->link_params.feature_config_flags |=
8137                 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
8138                 ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
8139         sc->link_params.feature_config_flags |=
8140                 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
8141                 ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
8142
8143         /* get the initial value of the link params */
8144         sc->link_params.multi_phy_config =
8145             SHMEM_RD(sc, dev_info.port_hw_config[port].multi_phy_config);
8146
8147         /* get external phy info */
8148         sc->port.ext_phy_config =
8149             SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
8150
8151         /* get the multifunction configuration */
8152         bnx2x_get_mf_cfg_info(sc);
8153
8154         /* get the mac address */
8155         if (IS_MF(sc)) {
8156                 mac_hi =
8157                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
8158                 mac_lo =
8159                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_lower);
8160         } else {
8161                 mac_hi = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_upper);
8162                 mac_lo = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_lower);
8163         }
8164
8165         if ((mac_lo == 0) && (mac_hi == 0)) {
8166                 *sc->mac_addr_str = 0;
8167                 PMD_DRV_LOG(NOTICE, sc, "No Ethernet address programmed!");
8168         } else {
8169                 sc->link_params.mac_addr[0] = (uint8_t) (mac_hi >> 8);
8170                 sc->link_params.mac_addr[1] = (uint8_t) (mac_hi);
8171                 sc->link_params.mac_addr[2] = (uint8_t) (mac_lo >> 24);
8172                 sc->link_params.mac_addr[3] = (uint8_t) (mac_lo >> 16);
8173                 sc->link_params.mac_addr[4] = (uint8_t) (mac_lo >> 8);
8174                 sc->link_params.mac_addr[5] = (uint8_t) (mac_lo);
8175                 snprintf(sc->mac_addr_str, sizeof(sc->mac_addr_str),
8176                          "%02x:%02x:%02x:%02x:%02x:%02x",
8177                          sc->link_params.mac_addr[0],
8178                          sc->link_params.mac_addr[1],
8179                          sc->link_params.mac_addr[2],
8180                          sc->link_params.mac_addr[3],
8181                          sc->link_params.mac_addr[4],
8182                          sc->link_params.mac_addr[5]);
8183                 PMD_DRV_LOG(DEBUG, sc,
8184                             "Ethernet address: %s", sc->mac_addr_str);
8185         }
8186
8187         return 0;
8188 }
8189
8190 static void bnx2x_media_detect(struct bnx2x_softc *sc)
8191 {
8192         uint32_t phy_idx = bnx2x_get_cur_phy_idx(sc);
8193         switch (sc->link_params.phy[phy_idx].media_type) {
8194         case ELINK_ETH_PHY_SFPP_10G_FIBER:
8195         case ELINK_ETH_PHY_SFP_1G_FIBER:
8196         case ELINK_ETH_PHY_XFP_FIBER:
8197         case ELINK_ETH_PHY_KR:
8198         case ELINK_ETH_PHY_CX4:
8199                 PMD_DRV_LOG(INFO, sc, "Found 10GBase-CX4 media.");
8200                 sc->media = IFM_10G_CX4;
8201                 break;
8202         case ELINK_ETH_PHY_DA_TWINAX:
8203                 PMD_DRV_LOG(INFO, sc, "Found 10Gb Twinax media.");
8204                 sc->media = IFM_10G_TWINAX;
8205                 break;
8206         case ELINK_ETH_PHY_BASE_T:
8207                 PMD_DRV_LOG(INFO, sc, "Found 10GBase-T media.");
8208                 sc->media = IFM_10G_T;
8209                 break;
8210         case ELINK_ETH_PHY_NOT_PRESENT:
8211                 PMD_DRV_LOG(INFO, sc, "Media not present.");
8212                 sc->media = 0;
8213                 break;
8214         case ELINK_ETH_PHY_UNSPECIFIED:
8215         default:
8216                 PMD_DRV_LOG(INFO, sc, "Unknown media!");
8217                 sc->media = 0;
8218                 break;
8219         }
8220 }
8221
8222 #define GET_FIELD(value, fname)                     \
8223 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
8224 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
8225 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
8226
8227 static int bnx2x_get_igu_cam_info(struct bnx2x_softc *sc)
8228 {
8229         int pfid = SC_FUNC(sc);
8230         int igu_sb_id;
8231         uint32_t val;
8232         uint8_t fid, igu_sb_cnt = 0;
8233
8234         sc->igu_base_sb = 0xff;
8235
8236         if (CHIP_INT_MODE_IS_BC(sc)) {
8237                 int vn = SC_VN(sc);
8238                 igu_sb_cnt = sc->igu_sb_cnt;
8239                 sc->igu_base_sb = ((CHIP_IS_MODE_4_PORT(sc) ? pfid : vn) *
8240                                    FP_SB_MAX_E1x);
8241                 sc->igu_dsb_id = (E1HVN_MAX * FP_SB_MAX_E1x +
8242                                   (CHIP_IS_MODE_4_PORT(sc) ? pfid : vn));
8243                 return 0;
8244         }
8245
8246         /* IGU in normal mode - read CAM */
8247         for (igu_sb_id = 0;
8248              igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; igu_sb_id++) {
8249                 val = REG_RD(sc, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
8250                 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) {
8251                         continue;
8252                 }
8253                 fid = IGU_FID(val);
8254                 if (fid & IGU_FID_ENCODE_IS_PF) {
8255                         if ((fid & IGU_FID_PF_NUM_MASK) != pfid) {
8256                                 continue;
8257                         }
8258                         if (IGU_VEC(val) == 0) {
8259                                 /* default status block */
8260                                 sc->igu_dsb_id = igu_sb_id;
8261                         } else {
8262                                 if (sc->igu_base_sb == 0xff) {
8263                                         sc->igu_base_sb = igu_sb_id;
8264                                 }
8265                                 igu_sb_cnt++;
8266                         }
8267                 }
8268         }
8269
8270         /*
8271          * Due to new PF resource allocation by MFW T7.4 and above, it's optional
8272          * that number of CAM entries will not be equal to the value advertised in
8273          * PCI. Driver should use the minimal value of both as the actual status
8274          * block count
8275          */
8276         sc->igu_sb_cnt = min(sc->igu_sb_cnt, igu_sb_cnt);
8277
8278         if (igu_sb_cnt == 0) {
8279                 PMD_DRV_LOG(ERR, sc, "CAM configuration error");
8280                 return -1;
8281         }
8282
8283         return 0;
8284 }
8285
8286 /*
8287 * Gather various information from the device config space, the device itself,
8288 * shmem, and the user input.
8289 */
8290 static int bnx2x_get_device_info(struct bnx2x_softc *sc)
8291 {
8292         uint32_t val;
8293         int rc;
8294
8295         /* get the chip revision (chip metal comes from pci config space) */
8296         sc->devinfo.chip_id = sc->link_params.chip_id =
8297             (((REG_RD(sc, MISC_REG_CHIP_NUM) & 0xffff) << 16) |
8298              ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12) |
8299              (((REG_RD(sc, PCICFG_OFFSET + PCI_ID_VAL3) >> 24) & 0xf) << 4) |
8300              ((REG_RD(sc, MISC_REG_BOND_ID) & 0xf) << 0));
8301
8302         /* force 57811 according to MISC register */
8303         if (REG_RD(sc, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
8304                 if (CHIP_IS_57810(sc)) {
8305                         sc->devinfo.chip_id = ((CHIP_NUM_57811 << 16) |
8306                                                (sc->
8307                                                 devinfo.chip_id & 0x0000ffff));
8308                 } else if (CHIP_IS_57810_MF(sc)) {
8309                         sc->devinfo.chip_id = ((CHIP_NUM_57811_MF << 16) |
8310                                                (sc->
8311                                                 devinfo.chip_id & 0x0000ffff));
8312                 }
8313                 sc->devinfo.chip_id |= 0x1;
8314         }
8315
8316         PMD_DRV_LOG(DEBUG, sc,
8317                     "chip_id=0x%08x (num=0x%04x rev=0x%01x metal=0x%02x bond=0x%01x)",
8318                     sc->devinfo.chip_id,
8319                     ((sc->devinfo.chip_id >> 16) & 0xffff),
8320                     ((sc->devinfo.chip_id >> 12) & 0xf),
8321                     ((sc->devinfo.chip_id >> 4) & 0xff),
8322                     ((sc->devinfo.chip_id >> 0) & 0xf));
8323
8324         val = (REG_RD(sc, 0x2874) & 0x55);
8325         if ((sc->devinfo.chip_id & 0x1) || (CHIP_IS_E1H(sc) && (val == 0x55))) {
8326                 sc->flags |= BNX2X_ONE_PORT_FLAG;
8327                 PMD_DRV_LOG(DEBUG, sc, "single port device");
8328         }
8329
8330         /* set the doorbell size */
8331         sc->doorbell_size = (1 << BNX2X_DB_SHIFT);
8332
8333         /* determine whether the device is in 2 port or 4 port mode */
8334         sc->devinfo.chip_port_mode = CHIP_PORT_MODE_NONE;       /* E1h */
8335         if (CHIP_IS_E2E3(sc)) {
8336 /*
8337  * Read port4mode_en_ovwr[0]:
8338  *   If 1, four port mode is in port4mode_en_ovwr[1].
8339  *   If 0, four port mode is in port4mode_en[0].
8340  */
8341                 val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);
8342                 if (val & 1) {
8343                         val = ((val >> 1) & 1);
8344                 } else {
8345                         val = REG_RD(sc, MISC_REG_PORT4MODE_EN);
8346                 }
8347
8348                 sc->devinfo.chip_port_mode =
8349                     (val) ? CHIP_4_PORT_MODE : CHIP_2_PORT_MODE;
8350
8351                 PMD_DRV_LOG(DEBUG, sc, "Port mode = %s", (val) ? "4" : "2");
8352         }
8353
8354         /* get the function and path info for the device */
8355         bnx2x_get_function_num(sc);
8356
8357         /* get the shared memory base address */
8358         sc->devinfo.shmem_base =
8359             sc->link_params.shmem_base = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
8360         sc->devinfo.shmem2_base =
8361             REG_RD(sc, (SC_PATH(sc) ? MISC_REG_GENERIC_CR_1 :
8362                         MISC_REG_GENERIC_CR_0));
8363
8364         if (!sc->devinfo.shmem_base) {
8365 /* this should ONLY prevent upcoming shmem reads */
8366                 PMD_DRV_LOG(INFO, sc, "MCP not active");
8367                 sc->flags |= BNX2X_NO_MCP_FLAG;
8368                 return 0;
8369         }
8370
8371         /* make sure the shared memory contents are valid */
8372         val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
8373         if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) !=
8374             (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) {
8375                 PMD_DRV_LOG(NOTICE, sc, "Invalid SHMEM validity signature: 0x%08x",
8376                             val);
8377                 return 0;
8378         }
8379
8380         /* get the bootcode version */
8381         sc->devinfo.bc_ver = SHMEM_RD(sc, dev_info.bc_rev);
8382         snprintf(sc->devinfo.bc_ver_str,
8383                  sizeof(sc->devinfo.bc_ver_str),
8384                  "%d.%d.%d",
8385                  ((sc->devinfo.bc_ver >> 24) & 0xff),
8386                  ((sc->devinfo.bc_ver >> 16) & 0xff),
8387                  ((sc->devinfo.bc_ver >> 8) & 0xff));
8388         PMD_DRV_LOG(DEBUG, sc, "Bootcode version: %s", sc->devinfo.bc_ver_str);
8389
8390         /* get the bootcode shmem address */
8391         sc->devinfo.mf_cfg_base = bnx2x_get_shmem_mf_cfg_base(sc);
8392
8393         /* clean indirect addresses as they're not used */
8394         pci_write_long(sc, PCICFG_GRC_ADDRESS, 0);
8395         if (IS_PF(sc)) {
8396                 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F0, 0);
8397                 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F0, 0);
8398                 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F0, 0);
8399                 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F0, 0);
8400                 if (CHIP_IS_E1x(sc)) {
8401                         REG_WR(sc, PXP2_REG_PGL_ADDR_88_F1, 0);
8402                         REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F1, 0);
8403                         REG_WR(sc, PXP2_REG_PGL_ADDR_90_F1, 0);
8404                         REG_WR(sc, PXP2_REG_PGL_ADDR_94_F1, 0);
8405                 }
8406         }
8407
8408         /* get the nvram size */
8409         val = REG_RD(sc, MCP_REG_MCPR_NVM_CFG4);
8410         sc->devinfo.flash_size =
8411             (NVRAM_1MB_SIZE << (val & MCPR_NVM_CFG4_FLASH_SIZE));
8412
8413         bnx2x_set_power_state(sc, PCI_PM_D0);
8414         /* get various configuration parameters from shmem */
8415         bnx2x_get_shmem_info(sc);
8416
8417         /* initialize IGU parameters */
8418         if (CHIP_IS_E1x(sc)) {
8419                 sc->devinfo.int_block = INT_BLOCK_HC;
8420                 sc->igu_dsb_id = DEF_SB_IGU_ID;
8421                 sc->igu_base_sb = 0;
8422         } else {
8423                 sc->devinfo.int_block = INT_BLOCK_IGU;
8424
8425 /* do not allow device reset during IGU info preocessing */
8426                 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8427
8428                 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
8429
8430                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8431                         int tout = 5000;
8432
8433                         val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
8434                         REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION, val);
8435                         REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x7f);
8436
8437                         while (tout && REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8438                                 tout--;
8439                                 DELAY(1000);
8440                         }
8441
8442                         if (REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8443                                 PMD_DRV_LOG(NOTICE, sc,
8444                                             "FORCING IGU Normal Mode failed!!!");
8445                                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8446                                 return -1;
8447                         }
8448                 }
8449
8450                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8451                         PMD_DRV_LOG(DEBUG, sc, "IGU Backward Compatible Mode");
8452                         sc->devinfo.int_block |= INT_BLOCK_MODE_BW_COMP;
8453                 } else {
8454                         PMD_DRV_LOG(DEBUG, sc, "IGU Normal Mode");
8455                 }
8456
8457                 rc = bnx2x_get_igu_cam_info(sc);
8458
8459                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8460
8461                 if (rc) {
8462                         return rc;
8463                 }
8464         }
8465
8466         /*
8467          * Get base FW non-default (fast path) status block ID. This value is
8468          * used to initialize the fw_sb_id saved on the fp/queue structure to
8469          * determine the id used by the FW.
8470          */
8471         if (CHIP_IS_E1x(sc)) {
8472                 sc->base_fw_ndsb =
8473                     ((SC_PORT(sc) * FP_SB_MAX_E1x) + SC_L_ID(sc));
8474         } else {
8475 /*
8476  * 57712+ - We currently use one FW SB per IGU SB (Rx and Tx of
8477  * the same queue are indicated on the same IGU SB). So we prefer
8478  * FW and IGU SBs to be the same value.
8479  */
8480                 sc->base_fw_ndsb = sc->igu_base_sb;
8481         }
8482
8483         elink_phy_probe(&sc->link_params);
8484
8485         return 0;
8486 }
8487
8488 static void
8489 bnx2x_link_settings_supported(struct bnx2x_softc *sc, uint32_t switch_cfg)
8490 {
8491         uint32_t cfg_size = 0;
8492         uint32_t idx;
8493         uint8_t port = SC_PORT(sc);
8494
8495         /* aggregation of supported attributes of all external phys */
8496         sc->port.supported[0] = 0;
8497         sc->port.supported[1] = 0;
8498
8499         switch (sc->link_params.num_phys) {
8500         case 1:
8501                 sc->port.supported[0] =
8502                     sc->link_params.phy[ELINK_INT_PHY].supported;
8503                 cfg_size = 1;
8504                 break;
8505         case 2:
8506                 sc->port.supported[0] =
8507                     sc->link_params.phy[ELINK_EXT_PHY1].supported;
8508                 cfg_size = 1;
8509                 break;
8510         case 3:
8511                 if (sc->link_params.multi_phy_config &
8512                     PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
8513                         sc->port.supported[1] =
8514                             sc->link_params.phy[ELINK_EXT_PHY1].supported;
8515                         sc->port.supported[0] =
8516                             sc->link_params.phy[ELINK_EXT_PHY2].supported;
8517                 } else {
8518                         sc->port.supported[0] =
8519                             sc->link_params.phy[ELINK_EXT_PHY1].supported;
8520                         sc->port.supported[1] =
8521                             sc->link_params.phy[ELINK_EXT_PHY2].supported;
8522                 }
8523                 cfg_size = 2;
8524                 break;
8525         }
8526
8527         if (!(sc->port.supported[0] || sc->port.supported[1])) {
8528                 PMD_DRV_LOG(ERR, sc,
8529                             "Invalid phy config in NVRAM (PHY1=0x%08x PHY2=0x%08x)",
8530                             SHMEM_RD(sc,
8531                                      dev_info.port_hw_config
8532                                      [port].external_phy_config),
8533                             SHMEM_RD(sc,
8534                                      dev_info.port_hw_config
8535                                      [port].external_phy_config2));
8536                 return;
8537         }
8538
8539         if (CHIP_IS_E3(sc))
8540                 sc->port.phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR);
8541         else {
8542                 switch (switch_cfg) {
8543                 case ELINK_SWITCH_CFG_1G:
8544                         sc->port.phy_addr =
8545                             REG_RD(sc,
8546                                    NIG_REG_SERDES0_CTRL_PHY_ADDR + port * 0x10);
8547                         break;
8548                 case ELINK_SWITCH_CFG_10G:
8549                         sc->port.phy_addr =
8550                             REG_RD(sc,
8551                                    NIG_REG_XGXS0_CTRL_PHY_ADDR + port * 0x18);
8552                         break;
8553                 default:
8554                         PMD_DRV_LOG(ERR, sc,
8555                                     "Invalid switch config in"
8556                                     "link_config=0x%08x",
8557                                     sc->port.link_config[0]);
8558                         return;
8559                 }
8560         }
8561
8562         PMD_DRV_LOG(INFO, sc, "PHY addr 0x%08x", sc->port.phy_addr);
8563
8564         /* mask what we support according to speed_cap_mask per configuration */
8565         for (idx = 0; idx < cfg_size; idx++) {
8566                 if (!(sc->link_params.speed_cap_mask[idx] &
8567                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) {
8568                         sc->port.supported[idx] &=
8569                             ~ELINK_SUPPORTED_10baseT_Half;
8570                 }
8571
8572                 if (!(sc->link_params.speed_cap_mask[idx] &
8573                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) {
8574                         sc->port.supported[idx] &=
8575                             ~ELINK_SUPPORTED_10baseT_Full;
8576                 }
8577
8578                 if (!(sc->link_params.speed_cap_mask[idx] &
8579                       PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) {
8580                         sc->port.supported[idx] &=
8581                             ~ELINK_SUPPORTED_100baseT_Half;
8582                 }
8583
8584                 if (!(sc->link_params.speed_cap_mask[idx] &
8585                       PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) {
8586                         sc->port.supported[idx] &=
8587                             ~ELINK_SUPPORTED_100baseT_Full;
8588                 }
8589
8590                 if (!(sc->link_params.speed_cap_mask[idx] &
8591                       PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) {
8592                         sc->port.supported[idx] &=
8593                             ~ELINK_SUPPORTED_1000baseT_Full;
8594                 }
8595
8596                 if (!(sc->link_params.speed_cap_mask[idx] &
8597                       PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) {
8598                         sc->port.supported[idx] &=
8599                             ~ELINK_SUPPORTED_2500baseX_Full;
8600                 }
8601
8602                 if (!(sc->link_params.speed_cap_mask[idx] &
8603                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8604                         sc->port.supported[idx] &=
8605                             ~ELINK_SUPPORTED_10000baseT_Full;
8606                 }
8607
8608                 if (!(sc->link_params.speed_cap_mask[idx] &
8609                       PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) {
8610                         sc->port.supported[idx] &=
8611                             ~ELINK_SUPPORTED_20000baseKR2_Full;
8612                 }
8613         }
8614
8615         PMD_DRV_LOG(INFO, sc, "PHY supported 0=0x%08x 1=0x%08x",
8616                     sc->port.supported[0], sc->port.supported[1]);
8617 }
8618
8619 static void bnx2x_link_settings_requested(struct bnx2x_softc *sc)
8620 {
8621         uint32_t link_config;
8622         uint32_t idx;
8623         uint32_t cfg_size = 0;
8624
8625         sc->port.advertising[0] = 0;
8626         sc->port.advertising[1] = 0;
8627
8628         switch (sc->link_params.num_phys) {
8629         case 1:
8630         case 2:
8631                 cfg_size = 1;
8632                 break;
8633         case 3:
8634                 cfg_size = 2;
8635                 break;
8636         }
8637
8638         for (idx = 0; idx < cfg_size; idx++) {
8639                 sc->link_params.req_duplex[idx] = DUPLEX_FULL;
8640                 link_config = sc->port.link_config[idx];
8641
8642                 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
8643                 case PORT_FEATURE_LINK_SPEED_AUTO:
8644                         if (sc->port.supported[idx] & ELINK_SUPPORTED_Autoneg) {
8645                                 sc->link_params.req_line_speed[idx] =
8646                                     ELINK_SPEED_AUTO_NEG;
8647                                 sc->port.advertising[idx] |=
8648                                     sc->port.supported[idx];
8649                                 if (sc->link_params.phy[ELINK_EXT_PHY1].type ==
8650                                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833)
8651                                         sc->port.advertising[idx] |=
8652                                             (ELINK_SUPPORTED_100baseT_Half |
8653                                              ELINK_SUPPORTED_100baseT_Full);
8654                         } else {
8655                                 /* force 10G, no AN */
8656                                 sc->link_params.req_line_speed[idx] =
8657                                     ELINK_SPEED_10000;
8658                                 sc->port.advertising[idx] |=
8659                                     (ADVERTISED_10000baseT_Full |
8660                                      ADVERTISED_FIBRE);
8661                                 continue;
8662                         }
8663                         break;
8664
8665                 case PORT_FEATURE_LINK_SPEED_10M_FULL:
8666                         if (sc->
8667                             port.supported[idx] & ELINK_SUPPORTED_10baseT_Full)
8668                         {
8669                                 sc->link_params.req_line_speed[idx] =
8670                                     ELINK_SPEED_10;
8671                                 sc->port.advertising[idx] |=
8672                                     (ADVERTISED_10baseT_Full | ADVERTISED_TP);
8673                         } else {
8674                                 PMD_DRV_LOG(ERR, sc,
8675                                             "Invalid NVRAM config link_config=0x%08x "
8676                                             "speed_cap_mask=0x%08x",
8677                                             link_config,
8678                                             sc->
8679                                             link_params.speed_cap_mask[idx]);
8680                                 return;
8681                         }
8682                         break;
8683
8684                 case PORT_FEATURE_LINK_SPEED_10M_HALF:
8685                         if (sc->
8686                             port.supported[idx] & ELINK_SUPPORTED_10baseT_Half)
8687                         {
8688                                 sc->link_params.req_line_speed[idx] =
8689                                     ELINK_SPEED_10;
8690                                 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8691                                 sc->port.advertising[idx] |=
8692                                     (ADVERTISED_10baseT_Half | ADVERTISED_TP);
8693                         } else {
8694                                 PMD_DRV_LOG(ERR, sc,
8695                                             "Invalid NVRAM config link_config=0x%08x "
8696                                             "speed_cap_mask=0x%08x",
8697                                             link_config,
8698                                             sc->
8699                                             link_params.speed_cap_mask[idx]);
8700                                 return;
8701                         }
8702                         break;
8703
8704                 case PORT_FEATURE_LINK_SPEED_100M_FULL:
8705                         if (sc->
8706                             port.supported[idx] & ELINK_SUPPORTED_100baseT_Full)
8707                         {
8708                                 sc->link_params.req_line_speed[idx] =
8709                                     ELINK_SPEED_100;
8710                                 sc->port.advertising[idx] |=
8711                                     (ADVERTISED_100baseT_Full | ADVERTISED_TP);
8712                         } else {
8713                                 PMD_DRV_LOG(ERR, sc,
8714                                             "Invalid NVRAM config link_config=0x%08x "
8715                                             "speed_cap_mask=0x%08x",
8716                                             link_config,
8717                                             sc->
8718                                             link_params.speed_cap_mask[idx]);
8719                                 return;
8720                         }
8721                         break;
8722
8723                 case PORT_FEATURE_LINK_SPEED_100M_HALF:
8724                         if (sc->
8725                             port.supported[idx] & ELINK_SUPPORTED_100baseT_Half)
8726                         {
8727                                 sc->link_params.req_line_speed[idx] =
8728                                     ELINK_SPEED_100;
8729                                 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8730                                 sc->port.advertising[idx] |=
8731                                     (ADVERTISED_100baseT_Half | ADVERTISED_TP);
8732                         } else {
8733                                 PMD_DRV_LOG(ERR, sc,
8734                                             "Invalid NVRAM config link_config=0x%08x "
8735                                             "speed_cap_mask=0x%08x",
8736                                             link_config,
8737                                             sc->
8738                                             link_params.speed_cap_mask[idx]);
8739                                 return;
8740                         }
8741                         break;
8742
8743                 case PORT_FEATURE_LINK_SPEED_1G:
8744                         if (sc->port.supported[idx] &
8745                             ELINK_SUPPORTED_1000baseT_Full) {
8746                                 sc->link_params.req_line_speed[idx] =
8747                                     ELINK_SPEED_1000;
8748                                 sc->port.advertising[idx] |=
8749                                     (ADVERTISED_1000baseT_Full | ADVERTISED_TP);
8750                         } else {
8751                                 PMD_DRV_LOG(ERR, sc,
8752                                             "Invalid NVRAM config link_config=0x%08x "
8753                                             "speed_cap_mask=0x%08x",
8754                                             link_config,
8755                                             sc->
8756                                             link_params.speed_cap_mask[idx]);
8757                                 return;
8758                         }
8759                         break;
8760
8761                 case PORT_FEATURE_LINK_SPEED_2_5G:
8762                         if (sc->port.supported[idx] &
8763                             ELINK_SUPPORTED_2500baseX_Full) {
8764                                 sc->link_params.req_line_speed[idx] =
8765                                     ELINK_SPEED_2500;
8766                                 sc->port.advertising[idx] |=
8767                                     (ADVERTISED_2500baseX_Full | ADVERTISED_TP);
8768                         } else {
8769                                 PMD_DRV_LOG(ERR, sc,
8770                                             "Invalid NVRAM config link_config=0x%08x "
8771                                             "speed_cap_mask=0x%08x",
8772                                             link_config,
8773                                             sc->
8774                                             link_params.speed_cap_mask[idx]);
8775                                 return;
8776                         }
8777                         break;
8778
8779                 case PORT_FEATURE_LINK_SPEED_10G_CX4:
8780                         if (sc->port.supported[idx] &
8781                             ELINK_SUPPORTED_10000baseT_Full) {
8782                                 sc->link_params.req_line_speed[idx] =
8783                                     ELINK_SPEED_10000;
8784                                 sc->port.advertising[idx] |=
8785                                     (ADVERTISED_10000baseT_Full |
8786                                      ADVERTISED_FIBRE);
8787                         } else {
8788                                 PMD_DRV_LOG(ERR, sc,
8789                                             "Invalid NVRAM config link_config=0x%08x "
8790                                             "speed_cap_mask=0x%08x",
8791                                             link_config,
8792                                             sc->
8793                                             link_params.speed_cap_mask[idx]);
8794                                 return;
8795                         }
8796                         break;
8797
8798                 case PORT_FEATURE_LINK_SPEED_20G:
8799                         sc->link_params.req_line_speed[idx] = ELINK_SPEED_20000;
8800                         break;
8801
8802                 default:
8803                         PMD_DRV_LOG(ERR, sc,
8804                                     "Invalid NVRAM config link_config=0x%08x "
8805                                     "speed_cap_mask=0x%08x", link_config,
8806                                     sc->link_params.speed_cap_mask[idx]);
8807                         sc->link_params.req_line_speed[idx] =
8808                             ELINK_SPEED_AUTO_NEG;
8809                         sc->port.advertising[idx] = sc->port.supported[idx];
8810                         break;
8811                 }
8812
8813                 sc->link_params.req_flow_ctrl[idx] =
8814                     (link_config & PORT_FEATURE_FLOW_CONTROL_MASK);
8815
8816                 if (sc->link_params.req_flow_ctrl[idx] == ELINK_FLOW_CTRL_AUTO) {
8817                         if (!
8818                             (sc->
8819                              port.supported[idx] & ELINK_SUPPORTED_Autoneg)) {
8820                                 sc->link_params.req_flow_ctrl[idx] =
8821                                     ELINK_FLOW_CTRL_NONE;
8822                         } else {
8823                                 bnx2x_set_requested_fc(sc);
8824                         }
8825                 }
8826         }
8827 }
8828
8829 static void bnx2x_get_phy_info(struct bnx2x_softc *sc)
8830 {
8831         uint8_t port = SC_PORT(sc);
8832         uint32_t eee_mode;
8833
8834         PMD_INIT_FUNC_TRACE(sc);
8835
8836         /* shmem data already read in bnx2x_get_shmem_info() */
8837
8838         bnx2x_link_settings_supported(sc, sc->link_params.switch_cfg);
8839         bnx2x_link_settings_requested(sc);
8840
8841         /* configure link feature according to nvram value */
8842         eee_mode =
8843             (((SHMEM_RD(sc, dev_info.port_feature_config[port].eee_power_mode))
8844               & PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
8845              PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
8846         if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
8847                 sc->link_params.eee_mode = (ELINK_EEE_MODE_ADV_LPI |
8848                                             ELINK_EEE_MODE_ENABLE_LPI |
8849                                             ELINK_EEE_MODE_OUTPUT_TIME);
8850         } else {
8851                 sc->link_params.eee_mode = 0;
8852         }
8853
8854         /* get the media type */
8855         bnx2x_media_detect(sc);
8856 }
8857
8858 static void bnx2x_set_modes_bitmap(struct bnx2x_softc *sc)
8859 {
8860         uint32_t flags = MODE_ASIC | MODE_PORT2;
8861
8862         if (CHIP_IS_E2(sc)) {
8863                 flags |= MODE_E2;
8864         } else if (CHIP_IS_E3(sc)) {
8865                 flags |= MODE_E3;
8866                 if (CHIP_REV(sc) == CHIP_REV_Ax) {
8867                         flags |= MODE_E3_A0;
8868                 } else {        /*if (CHIP_REV(sc) == CHIP_REV_Bx) */
8869
8870                         flags |= MODE_E3_B0 | MODE_COS3;
8871                 }
8872         }
8873
8874         if (IS_MF(sc)) {
8875                 flags |= MODE_MF;
8876                 switch (sc->devinfo.mf_info.mf_mode) {
8877                 case MULTI_FUNCTION_SD:
8878                         flags |= MODE_MF_SD;
8879                         break;
8880                 case MULTI_FUNCTION_SI:
8881                         flags |= MODE_MF_SI;
8882                         break;
8883                 case MULTI_FUNCTION_AFEX:
8884                         flags |= MODE_MF_AFEX;
8885                         break;
8886                 }
8887         } else {
8888                 flags |= MODE_SF;
8889         }
8890
8891 #if defined(__LITTLE_ENDIAN)
8892         flags |= MODE_LITTLE_ENDIAN;
8893 #else /* __BIG_ENDIAN */
8894         flags |= MODE_BIG_ENDIAN;
8895 #endif
8896
8897         INIT_MODE_FLAGS(sc) = flags;
8898 }
8899
8900 int bnx2x_alloc_hsi_mem(struct bnx2x_softc *sc)
8901 {
8902         struct bnx2x_fastpath *fp;
8903         char buf[32];
8904         uint32_t i;
8905
8906         if (IS_PF(sc)) {
8907                 /************************/
8908                 /* DEFAULT STATUS BLOCK */
8909                 /************************/
8910
8911                 if (bnx2x_dma_alloc(sc, sizeof(struct host_sp_status_block),
8912                                   &sc->def_sb_dma, "def_sb",
8913                                   RTE_CACHE_LINE_SIZE) != 0) {
8914                         return -1;
8915                 }
8916
8917                 sc->def_sb =
8918                     (struct host_sp_status_block *)sc->def_sb_dma.vaddr;
8919                 /***************/
8920                 /* EVENT QUEUE */
8921                 /***************/
8922
8923                 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8924                                   &sc->eq_dma, "ev_queue",
8925                                   RTE_CACHE_LINE_SIZE) != 0) {
8926                         sc->def_sb = NULL;
8927                         return -1;
8928                 }
8929
8930                 sc->eq = (union event_ring_elem *)sc->eq_dma.vaddr;
8931
8932                 /*************/
8933                 /* SLOW PATH */
8934                 /*************/
8935
8936                 if (bnx2x_dma_alloc(sc, sizeof(struct bnx2x_slowpath),
8937                                   &sc->sp_dma, "sp",
8938                                   RTE_CACHE_LINE_SIZE) != 0) {
8939                         sc->eq = NULL;
8940                         sc->def_sb = NULL;
8941                         return -1;
8942                 }
8943
8944                 sc->sp = (struct bnx2x_slowpath *)sc->sp_dma.vaddr;
8945
8946                 /*******************/
8947                 /* SLOW PATH QUEUE */
8948                 /*******************/
8949
8950                 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8951                                   &sc->spq_dma, "sp_queue",
8952                                   RTE_CACHE_LINE_SIZE) != 0) {
8953                         sc->sp = NULL;
8954                         sc->eq = NULL;
8955                         sc->def_sb = NULL;
8956                         return -1;
8957                 }
8958
8959                 sc->spq = (struct eth_spe *)sc->spq_dma.vaddr;
8960
8961                 /***************************/
8962                 /* FW DECOMPRESSION BUFFER */
8963                 /***************************/
8964
8965                 if (bnx2x_dma_alloc(sc, FW_BUF_SIZE, &sc->gz_buf_dma,
8966                                   "fw_buf", RTE_CACHE_LINE_SIZE) != 0) {
8967                         sc->spq = NULL;
8968                         sc->sp = NULL;
8969                         sc->eq = NULL;
8970                         sc->def_sb = NULL;
8971                         return -1;
8972                 }
8973
8974                 sc->gz_buf = (void *)sc->gz_buf_dma.vaddr;
8975         }
8976
8977         /*************/
8978         /* FASTPATHS */
8979         /*************/
8980
8981         /* allocate DMA memory for each fastpath structure */
8982         for (i = 0; i < sc->num_queues; i++) {
8983                 fp = &sc->fp[i];
8984                 fp->sc = sc;
8985                 fp->index = i;
8986
8987                 /*******************/
8988                 /* FP STATUS BLOCK */
8989                 /*******************/
8990
8991                 snprintf(buf, sizeof(buf), "fp_%d_sb", i);
8992                 if (bnx2x_dma_alloc(sc, sizeof(union bnx2x_host_hc_status_block),
8993                                   &fp->sb_dma, buf, RTE_CACHE_LINE_SIZE) != 0) {
8994                         PMD_DRV_LOG(NOTICE, sc, "Failed to alloc %s", buf);
8995                         return -1;
8996                 } else {
8997                         if (CHIP_IS_E2E3(sc)) {
8998                                 fp->status_block.e2_sb =
8999                                     (struct host_hc_status_block_e2 *)
9000                                     fp->sb_dma.vaddr;
9001                         } else {
9002                                 fp->status_block.e1x_sb =
9003                                     (struct host_hc_status_block_e1x *)
9004                                     fp->sb_dma.vaddr;
9005                         }
9006                 }
9007         }
9008
9009         return 0;
9010 }
9011
9012 void bnx2x_free_hsi_mem(struct bnx2x_softc *sc)
9013 {
9014         struct bnx2x_fastpath *fp;
9015         int i;
9016
9017         for (i = 0; i < sc->num_queues; i++) {
9018                 fp = &sc->fp[i];
9019
9020                 /*******************/
9021                 /* FP STATUS BLOCK */
9022                 /*******************/
9023
9024                 memset(&fp->status_block, 0, sizeof(fp->status_block));
9025                 bnx2x_dma_free(&fp->sb_dma);
9026         }
9027
9028         if (IS_PF(sc)) {
9029                 /***************************/
9030                 /* FW DECOMPRESSION BUFFER */
9031                 /***************************/
9032
9033                 bnx2x_dma_free(&sc->gz_buf_dma);
9034                 sc->gz_buf = NULL;
9035
9036                 /*******************/
9037                 /* SLOW PATH QUEUE */
9038                 /*******************/
9039
9040                 bnx2x_dma_free(&sc->spq_dma);
9041                 sc->spq = NULL;
9042
9043                 /*************/
9044                 /* SLOW PATH */
9045                 /*************/
9046
9047                 bnx2x_dma_free(&sc->sp_dma);
9048                 sc->sp = NULL;
9049
9050                 /***************/
9051                 /* EVENT QUEUE */
9052                 /***************/
9053
9054                 bnx2x_dma_free(&sc->eq_dma);
9055                 sc->eq = NULL;
9056
9057                 /************************/
9058                 /* DEFAULT STATUS BLOCK */
9059                 /************************/
9060
9061                 bnx2x_dma_free(&sc->def_sb_dma);
9062                 sc->def_sb = NULL;
9063         }
9064 }
9065
9066 /*
9067 * Previous driver DMAE transaction may have occurred when pre-boot stage
9068 * ended and boot began. This would invalidate the addresses of the
9069 * transaction, resulting in was-error bit set in the PCI causing all
9070 * hw-to-host PCIe transactions to timeout. If this happened we want to clear
9071 * the interrupt which detected this from the pglueb and the was-done bit
9072 */
9073 static void bnx2x_prev_interrupted_dmae(struct bnx2x_softc *sc)
9074 {
9075         uint32_t val;
9076
9077         if (!CHIP_IS_E1x(sc)) {
9078                 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS);
9079                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
9080                         REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
9081                                1 << SC_FUNC(sc));
9082                 }
9083         }
9084 }
9085
9086 static int bnx2x_prev_mcp_done(struct bnx2x_softc *sc)
9087 {
9088         uint32_t rc = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE,
9089                                      DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
9090         if (!rc) {
9091                 PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
9092                 return -1;
9093         }
9094
9095         return 0;
9096 }
9097
9098 static struct bnx2x_prev_list_node *bnx2x_prev_path_get_entry(struct bnx2x_softc *sc)
9099 {
9100         struct bnx2x_prev_list_node *tmp;
9101
9102         LIST_FOREACH(tmp, &bnx2x_prev_list, node) {
9103                 if ((sc->pcie_bus == tmp->bus) &&
9104                     (sc->pcie_device == tmp->slot) &&
9105                     (SC_PATH(sc) == tmp->path)) {
9106                         return tmp;
9107                 }
9108         }
9109
9110         return NULL;
9111 }
9112
9113 static uint8_t bnx2x_prev_is_path_marked(struct bnx2x_softc *sc)
9114 {
9115         struct bnx2x_prev_list_node *tmp;
9116         int rc = FALSE;
9117
9118         rte_spinlock_lock(&bnx2x_prev_mtx);
9119
9120         tmp = bnx2x_prev_path_get_entry(sc);
9121         if (tmp) {
9122                 if (tmp->aer) {
9123                         PMD_DRV_LOG(DEBUG, sc,
9124                                     "Path %d/%d/%d was marked by AER",
9125                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9126                 } else {
9127                         rc = TRUE;
9128                         PMD_DRV_LOG(DEBUG, sc,
9129                                     "Path %d/%d/%d was already cleaned from previous drivers",
9130                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9131                 }
9132         }
9133
9134         rte_spinlock_unlock(&bnx2x_prev_mtx);
9135
9136         return rc;
9137 }
9138
9139 static int bnx2x_prev_mark_path(struct bnx2x_softc *sc, uint8_t after_undi)
9140 {
9141         struct bnx2x_prev_list_node *tmp;
9142
9143         rte_spinlock_lock(&bnx2x_prev_mtx);
9144
9145         /* Check whether the entry for this path already exists */
9146         tmp = bnx2x_prev_path_get_entry(sc);
9147         if (tmp) {
9148                 if (!tmp->aer) {
9149                         PMD_DRV_LOG(DEBUG, sc,
9150                                     "Re-marking AER in path %d/%d/%d",
9151                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9152                 } else {
9153                         PMD_DRV_LOG(DEBUG, sc,
9154                                     "Removing AER indication from path %d/%d/%d",
9155                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9156                         tmp->aer = 0;
9157                 }
9158
9159                 rte_spinlock_unlock(&bnx2x_prev_mtx);
9160                 return 0;
9161         }
9162
9163         rte_spinlock_unlock(&bnx2x_prev_mtx);
9164
9165         /* Create an entry for this path and add it */
9166         tmp = rte_malloc("", sizeof(struct bnx2x_prev_list_node),
9167                          RTE_CACHE_LINE_SIZE);
9168         if (!tmp) {
9169                 PMD_DRV_LOG(NOTICE, sc, "Failed to allocate 'bnx2x_prev_list_node'");
9170                 return -1;
9171         }
9172
9173         tmp->bus = sc->pcie_bus;
9174         tmp->slot = sc->pcie_device;
9175         tmp->path = SC_PATH(sc);
9176         tmp->aer = 0;
9177         tmp->undi = after_undi ? (1 << SC_PORT(sc)) : 0;
9178
9179         rte_spinlock_lock(&bnx2x_prev_mtx);
9180
9181         LIST_INSERT_HEAD(&bnx2x_prev_list, tmp, node);
9182
9183         rte_spinlock_unlock(&bnx2x_prev_mtx);
9184
9185         return 0;
9186 }
9187
9188 static int bnx2x_do_flr(struct bnx2x_softc *sc)
9189 {
9190         int i;
9191
9192         /* only E2 and onwards support FLR */
9193         if (CHIP_IS_E1x(sc)) {
9194                 PMD_DRV_LOG(WARNING, sc, "FLR not supported in E1H");
9195                 return -1;
9196         }
9197
9198         /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9199         if (sc->devinfo.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9200                 PMD_DRV_LOG(WARNING, sc,
9201                             "FLR not supported by BC_VER: 0x%08x",
9202                             sc->devinfo.bc_ver);
9203                 return -1;
9204         }
9205
9206         /* Wait for Transaction Pending bit clean */
9207         for (i = 0; i < 4; i++) {
9208                 if (i) {
9209                         DELAY(((1 << (i - 1)) * 100) * 1000);
9210                 }
9211
9212                 if (!bnx2x_is_pcie_pending(sc)) {
9213                         goto clear;
9214                 }
9215         }
9216
9217         PMD_DRV_LOG(NOTICE, sc, "PCIE transaction is not cleared, "
9218                     "proceeding with reset anyway");
9219
9220 clear:
9221         bnx2x_fw_command(sc, DRV_MSG_CODE_INITIATE_FLR, 0);
9222
9223         return 0;
9224 }
9225
9226 struct bnx2x_mac_vals {
9227         uint32_t xmac_addr;
9228         uint32_t xmac_val;
9229         uint32_t emac_addr;
9230         uint32_t emac_val;
9231         uint32_t umac_addr;
9232         uint32_t umac_val;
9233         uint32_t bmac_addr;
9234         uint32_t bmac_val[2];
9235 };
9236
9237 static void
9238 bnx2x_prev_unload_close_mac(struct bnx2x_softc *sc, struct bnx2x_mac_vals *vals)
9239 {
9240         uint32_t val, base_addr, offset, mask, reset_reg;
9241         uint8_t mac_stopped = FALSE;
9242         uint8_t port = SC_PORT(sc);
9243         uint32_t wb_data[2];
9244
9245         /* reset addresses as they also mark which values were changed */
9246         vals->bmac_addr = 0;
9247         vals->umac_addr = 0;
9248         vals->xmac_addr = 0;
9249         vals->emac_addr = 0;
9250
9251         reset_reg = REG_RD(sc, MISC_REG_RESET_REG_2);
9252
9253         if (!CHIP_IS_E3(sc)) {
9254                 val = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9255                 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9256                 if ((mask & reset_reg) && val) {
9257                         base_addr = SC_PORT(sc) ? NIG_REG_INGRESS_BMAC1_MEM
9258                             : NIG_REG_INGRESS_BMAC0_MEM;
9259                         offset = CHIP_IS_E2(sc) ? BIGMAC2_REGISTER_BMAC_CONTROL
9260                             : BIGMAC_REGISTER_BMAC_CONTROL;
9261
9262                         /*
9263                          * use rd/wr since we cannot use dmae. This is safe
9264                          * since MCP won't access the bus due to the request
9265                          * to unload, and no function on the path can be
9266                          * loaded at this time.
9267                          */
9268                         wb_data[0] = REG_RD(sc, base_addr + offset);
9269                         wb_data[1] = REG_RD(sc, base_addr + offset + 0x4);
9270                         vals->bmac_addr = base_addr + offset;
9271                         vals->bmac_val[0] = wb_data[0];
9272                         vals->bmac_val[1] = wb_data[1];
9273                         wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE;
9274                         REG_WR(sc, vals->bmac_addr, wb_data[0]);
9275                         REG_WR(sc, vals->bmac_addr + 0x4, wb_data[1]);
9276                 }
9277
9278                 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + SC_PORT(sc) * 4;
9279                 vals->emac_val = REG_RD(sc, vals->emac_addr);
9280                 REG_WR(sc, vals->emac_addr, 0);
9281                 mac_stopped = TRUE;
9282         } else {
9283                 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9284                         base_addr = SC_PORT(sc) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9285                         val = REG_RD(sc, base_addr + XMAC_REG_PFC_CTRL_HI);
9286                         REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9287                                val & ~(1 << 1));
9288                         REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9289                                val | (1 << 1));
9290                         vals->xmac_addr = base_addr + XMAC_REG_CTRL;
9291                         vals->xmac_val = REG_RD(sc, vals->xmac_addr);
9292                         REG_WR(sc, vals->xmac_addr, 0);
9293                         mac_stopped = TRUE;
9294                 }
9295
9296                 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9297                 if (mask & reset_reg) {
9298                         base_addr = SC_PORT(sc) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9299                         vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
9300                         vals->umac_val = REG_RD(sc, vals->umac_addr);
9301                         REG_WR(sc, vals->umac_addr, 0);
9302                         mac_stopped = TRUE;
9303                 }
9304         }
9305
9306         if (mac_stopped) {
9307                 DELAY(20000);
9308         }
9309 }
9310
9311 #define BNX2X_PREV_UNDI_PROD_ADDR(p)  (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9312 #define BNX2X_PREV_UNDI_RCQ(val)      ((val) & 0xffff)
9313 #define BNX2X_PREV_UNDI_BD(val)       ((val) >> 16 & 0xffff)
9314 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
9315
9316 static void
9317 bnx2x_prev_unload_undi_inc(struct bnx2x_softc *sc, uint8_t port, uint8_t inc)
9318 {
9319         uint16_t rcq, bd;
9320         uint32_t tmp_reg = REG_RD(sc, BNX2X_PREV_UNDI_PROD_ADDR(port));
9321
9322         rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9323         bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9324
9325         tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9326         REG_WR(sc, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9327 }
9328
9329 static int bnx2x_prev_unload_common(struct bnx2x_softc *sc)
9330 {
9331         uint32_t reset_reg, tmp_reg = 0, rc;
9332         uint8_t prev_undi = FALSE;
9333         struct bnx2x_mac_vals mac_vals;
9334         uint32_t timer_count = 1000;
9335         uint32_t prev_brb;
9336
9337         /*
9338          * It is possible a previous function received 'common' answer,
9339          * but hasn't loaded yet, therefore creating a scenario of
9340          * multiple functions receiving 'common' on the same path.
9341          */
9342         memset(&mac_vals, 0, sizeof(mac_vals));
9343
9344         if (bnx2x_prev_is_path_marked(sc)) {
9345                 return bnx2x_prev_mcp_done(sc);
9346         }
9347
9348         reset_reg = REG_RD(sc, MISC_REG_RESET_REG_1);
9349
9350         /* Reset should be performed after BRB is emptied */
9351         if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
9352                 /* Close the MAC Rx to prevent BRB from filling up */
9353                 bnx2x_prev_unload_close_mac(sc, &mac_vals);
9354
9355                 /* close LLH filters towards the BRB */
9356                 elink_set_rx_filter(&sc->link_params, 0);
9357
9358                 /*
9359                  * Check if the UNDI driver was previously loaded.
9360                  * UNDI driver initializes CID offset for normal bell to 0x7
9361                  */
9362                 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
9363                         tmp_reg = REG_RD(sc, DORQ_REG_NORM_CID_OFST);
9364                         if (tmp_reg == 0x7) {
9365                                 PMD_DRV_LOG(DEBUG, sc, "UNDI previously loaded");
9366                                 prev_undi = TRUE;
9367                                 /* clear the UNDI indication */
9368                                 REG_WR(sc, DORQ_REG_NORM_CID_OFST, 0);
9369                                 /* clear possible idle check errors */
9370                                 REG_RD(sc, NIG_REG_NIG_INT_STS_CLR_0);
9371                         }
9372                 }
9373
9374                 /* wait until BRB is empty */
9375                 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9376                 while (timer_count) {
9377                         prev_brb = tmp_reg;
9378
9379                         tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9380                         if (!tmp_reg) {
9381                                 break;
9382                         }
9383
9384                         PMD_DRV_LOG(DEBUG, sc, "BRB still has 0x%08x", tmp_reg);
9385
9386                         /* reset timer as long as BRB actually gets emptied */
9387                         if (prev_brb > tmp_reg) {
9388                                 timer_count = 1000;
9389                         } else {
9390                                 timer_count--;
9391                         }
9392
9393                         /* If UNDI resides in memory, manually increment it */
9394                         if (prev_undi) {
9395                                 bnx2x_prev_unload_undi_inc(sc, SC_PORT(sc), 1);
9396                         }
9397
9398                         DELAY(10);
9399                 }
9400
9401                 if (!timer_count) {
9402                         PMD_DRV_LOG(NOTICE, sc, "Failed to empty BRB");
9403                 }
9404         }
9405
9406         /* No packets are in the pipeline, path is ready for reset */
9407         bnx2x_reset_common(sc);
9408
9409         if (mac_vals.xmac_addr) {
9410                 REG_WR(sc, mac_vals.xmac_addr, mac_vals.xmac_val);
9411         }
9412         if (mac_vals.umac_addr) {
9413                 REG_WR(sc, mac_vals.umac_addr, mac_vals.umac_val);
9414         }
9415         if (mac_vals.emac_addr) {
9416                 REG_WR(sc, mac_vals.emac_addr, mac_vals.emac_val);
9417         }
9418         if (mac_vals.bmac_addr) {
9419                 REG_WR(sc, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
9420                 REG_WR(sc, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
9421         }
9422
9423         rc = bnx2x_prev_mark_path(sc, prev_undi);
9424         if (rc) {
9425                 bnx2x_prev_mcp_done(sc);
9426                 return rc;
9427         }
9428
9429         return bnx2x_prev_mcp_done(sc);
9430 }
9431
9432 static int bnx2x_prev_unload_uncommon(struct bnx2x_softc *sc)
9433 {
9434         int rc;
9435
9436         /* Test if previous unload process was already finished for this path */
9437         if (bnx2x_prev_is_path_marked(sc)) {
9438                 return bnx2x_prev_mcp_done(sc);
9439         }
9440
9441         /*
9442          * If function has FLR capabilities, and existing FW version matches
9443          * the one required, then FLR will be sufficient to clean any residue
9444          * left by previous driver
9445          */
9446         rc = bnx2x_nic_load_analyze_req(sc, FW_MSG_CODE_DRV_LOAD_FUNCTION);
9447         if (!rc) {
9448                 /* fw version is good */
9449                 rc = bnx2x_do_flr(sc);
9450         }
9451
9452         if (!rc) {
9453                 /* FLR was performed */
9454                 return 0;
9455         }
9456
9457         PMD_DRV_LOG(INFO, sc, "Could not FLR");
9458
9459         /* Close the MCP request, return failure */
9460         rc = bnx2x_prev_mcp_done(sc);
9461         if (!rc) {
9462                 rc = BNX2X_PREV_WAIT_NEEDED;
9463         }
9464
9465         return rc;
9466 }
9467
9468 static int bnx2x_prev_unload(struct bnx2x_softc *sc)
9469 {
9470         int time_counter = 10;
9471         uint32_t fw, hw_lock_reg, hw_lock_val;
9472         uint32_t rc = 0;
9473
9474         PMD_INIT_FUNC_TRACE(sc);
9475
9476         /*
9477          * Clear HW from errors which may have resulted from an interrupted
9478          * DMAE transaction.
9479          */
9480         bnx2x_prev_interrupted_dmae(sc);
9481
9482         /* Release previously held locks */
9483         hw_lock_reg = (SC_FUNC(sc) <= 5) ?
9484                         (MISC_REG_DRIVER_CONTROL_1 + SC_FUNC(sc) * 8) :
9485                         (MISC_REG_DRIVER_CONTROL_7 + (SC_FUNC(sc) - 6) * 8);
9486
9487         hw_lock_val = (REG_RD(sc, hw_lock_reg));
9488         if (hw_lock_val) {
9489                 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
9490                         PMD_DRV_LOG(DEBUG, sc, "Releasing previously held NVRAM lock\n");
9491                         REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
9492                                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << SC_PORT(sc)));
9493                 }
9494                 PMD_DRV_LOG(DEBUG, sc, "Releasing previously held HW lock\n");
9495                 REG_WR(sc, hw_lock_reg, 0xffffffff);
9496         }
9497
9498         if (MCPR_ACCESS_LOCK_LOCK & REG_RD(sc, MCP_REG_MCPR_ACCESS_LOCK)) {
9499                 PMD_DRV_LOG(DEBUG, sc, "Releasing previously held ALR\n");
9500                 REG_WR(sc, MCP_REG_MCPR_ACCESS_LOCK, 0);
9501         }
9502
9503         do {
9504                 /* Lock MCP using an unload request */
9505                 fw = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
9506                 if (!fw) {
9507                         PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
9508                         rc = -1;
9509                         break;
9510                 }
9511
9512                 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
9513                         rc = bnx2x_prev_unload_common(sc);
9514                         break;
9515                 }
9516
9517                 /* non-common reply from MCP might require looping */
9518                 rc = bnx2x_prev_unload_uncommon(sc);
9519                 if (rc != BNX2X_PREV_WAIT_NEEDED) {
9520                         break;
9521                 }
9522
9523                 DELAY(20000);
9524         } while (--time_counter);
9525
9526         if (!time_counter || rc) {
9527                 PMD_DRV_LOG(NOTICE, sc, "Failed to unload previous driver!");
9528                 rc = -1;
9529         }
9530
9531         return rc;
9532 }
9533
9534 static void
9535 bnx2x_dcbx_set_state(struct bnx2x_softc *sc, uint8_t dcb_on, uint32_t dcbx_enabled)
9536 {
9537         if (!CHIP_IS_E1x(sc)) {
9538                 sc->dcb_state = dcb_on;
9539                 sc->dcbx_enabled = dcbx_enabled;
9540         } else {
9541                 sc->dcb_state = FALSE;
9542                 sc->dcbx_enabled = BNX2X_DCBX_ENABLED_INVALID;
9543         }
9544         PMD_DRV_LOG(DEBUG, sc,
9545                     "DCB state [%s:%s]",
9546                     dcb_on ? "ON" : "OFF",
9547                     (dcbx_enabled == BNX2X_DCBX_ENABLED_OFF) ? "user-mode" :
9548                     (dcbx_enabled ==
9549                      BNX2X_DCBX_ENABLED_ON_NEG_OFF) ? "on-chip static"
9550                     : (dcbx_enabled ==
9551                        BNX2X_DCBX_ENABLED_ON_NEG_ON) ?
9552                     "on-chip with negotiation" : "invalid");
9553 }
9554
9555 static int bnx2x_set_qm_cid_count(struct bnx2x_softc *sc)
9556 {
9557         int cid_count = BNX2X_L2_MAX_CID(sc);
9558
9559         if (CNIC_SUPPORT(sc)) {
9560                 cid_count += CNIC_CID_MAX;
9561         }
9562
9563         return roundup(cid_count, QM_CID_ROUND);
9564 }
9565
9566 static void bnx2x_init_multi_cos(struct bnx2x_softc *sc)
9567 {
9568         int pri, cos;
9569
9570         uint32_t pri_map = 0;
9571
9572         for (pri = 0; pri < BNX2X_MAX_PRIORITY; pri++) {
9573                 cos = ((pri_map & (0xf << (pri * 4))) >> (pri * 4));
9574                 if (cos < sc->max_cos) {
9575                         sc->prio_to_cos[pri] = cos;
9576                 } else {
9577                         PMD_DRV_LOG(WARNING, sc,
9578                                     "Invalid COS %d for priority %d "
9579                                     "(max COS is %d), setting to 0", cos, pri,
9580                                     (sc->max_cos - 1));
9581                         sc->prio_to_cos[pri] = 0;
9582                 }
9583         }
9584 }
9585
9586 static int bnx2x_pci_get_caps(struct bnx2x_softc *sc)
9587 {
9588         struct {
9589                 uint8_t id;
9590                 uint8_t next;
9591         } pci_cap;
9592         uint16_t status;
9593         struct bnx2x_pci_cap *cap;
9594
9595         cap = sc->pci_caps = rte_zmalloc("caps", sizeof(struct bnx2x_pci_cap),
9596                                          RTE_CACHE_LINE_SIZE);
9597         if (!cap) {
9598                 PMD_DRV_LOG(NOTICE, sc, "Failed to allocate memory");
9599                 return -ENOMEM;
9600         }
9601
9602 #ifndef RTE_EXEC_ENV_FREEBSD
9603         pci_read(sc, PCI_STATUS, &status, 2);
9604         if (!(status & PCI_STATUS_CAP_LIST)) {
9605 #else
9606         pci_read(sc, PCIR_STATUS, &status, 2);
9607         if (!(status & PCIM_STATUS_CAPPRESENT)) {
9608 #endif
9609                 PMD_DRV_LOG(NOTICE, sc, "PCIe capability reading failed");
9610                 return -1;
9611         }
9612
9613 #ifndef RTE_EXEC_ENV_FREEBSD
9614         pci_read(sc, PCI_CAPABILITY_LIST, &pci_cap.next, 1);
9615 #else
9616         pci_read(sc, PCIR_CAP_PTR, &pci_cap.next, 1);
9617 #endif
9618         while (pci_cap.next) {
9619                 cap->addr = pci_cap.next & ~3;
9620                 pci_read(sc, pci_cap.next & ~3, &pci_cap, 2);
9621                 if (pci_cap.id == 0xff)
9622                         break;
9623                 cap->id = pci_cap.id;
9624                 cap->type = BNX2X_PCI_CAP;
9625                 cap->next = rte_zmalloc("pci_cap",
9626                                         sizeof(struct bnx2x_pci_cap),
9627                                         RTE_CACHE_LINE_SIZE);
9628                 if (!cap->next) {
9629                         PMD_DRV_LOG(NOTICE, sc, "Failed to allocate memory");
9630                         return -ENOMEM;
9631                 }
9632                 cap = cap->next;
9633         }
9634
9635         return 0;
9636 }
9637
9638 static void bnx2x_init_rte(struct bnx2x_softc *sc)
9639 {
9640         if (IS_VF(sc)) {
9641                 sc->max_tx_queues = min(BNX2X_VF_MAX_QUEUES_PER_VF,
9642                                         sc->igu_sb_cnt);
9643                 sc->max_rx_queues = min(BNX2X_VF_MAX_QUEUES_PER_VF,
9644                                         sc->igu_sb_cnt);
9645         } else {
9646                 sc->max_rx_queues = BNX2X_MAX_RSS_COUNT(sc);
9647                 sc->max_tx_queues = sc->max_rx_queues;
9648         }
9649 }
9650
9651 #define FW_HEADER_LEN 104
9652 #define FW_NAME_57711 "/lib/firmware/bnx2x/bnx2x-e1h-7.13.11.0.fw"
9653 #define FW_NAME_57810 "/lib/firmware/bnx2x/bnx2x-e2-7.13.11.0.fw"
9654
9655 void bnx2x_load_firmware(struct bnx2x_softc *sc)
9656 {
9657         const char *fwname;
9658         int f;
9659         struct stat st;
9660
9661         fwname = sc->devinfo.device_id == CHIP_NUM_57711
9662                 ? FW_NAME_57711 : FW_NAME_57810;
9663         f = open(fwname, O_RDONLY);
9664         if (f < 0) {
9665                 PMD_DRV_LOG(NOTICE, sc, "Can't open firmware file");
9666                 return;
9667         }
9668
9669         if (fstat(f, &st) < 0) {
9670                 PMD_DRV_LOG(NOTICE, sc, "Can't stat firmware file");
9671                 close(f);
9672                 return;
9673         }
9674
9675         sc->firmware = rte_zmalloc("bnx2x_fw", st.st_size, RTE_CACHE_LINE_SIZE);
9676         if (!sc->firmware) {
9677                 PMD_DRV_LOG(NOTICE, sc, "Can't allocate memory for firmware");
9678                 close(f);
9679                 return;
9680         }
9681
9682         if (read(f, sc->firmware, st.st_size) != st.st_size) {
9683                 PMD_DRV_LOG(NOTICE, sc, "Can't read firmware data");
9684                 close(f);
9685                 return;
9686         }
9687         close(f);
9688
9689         sc->fw_len = st.st_size;
9690         if (sc->fw_len < FW_HEADER_LEN) {
9691                 PMD_DRV_LOG(NOTICE, sc,
9692                             "Invalid fw size: %" PRIu64, sc->fw_len);
9693                 return;
9694         }
9695         PMD_DRV_LOG(DEBUG, sc, "fw_len = %" PRIu64, sc->fw_len);
9696 }
9697
9698 static void
9699 bnx2x_data_to_init_ops(uint8_t * data, struct raw_op *dst, uint32_t len)
9700 {
9701         uint32_t *src = (uint32_t *) data;
9702         uint32_t i, j, tmp;
9703
9704         for (i = 0, j = 0; i < len / 8; ++i, j += 2) {
9705                 tmp = rte_be_to_cpu_32(src[j]);
9706                 dst[i].op = (tmp >> 24) & 0xFF;
9707                 dst[i].offset = tmp & 0xFFFFFF;
9708                 dst[i].raw_data = rte_be_to_cpu_32(src[j + 1]);
9709         }
9710 }
9711
9712 static void
9713 bnx2x_data_to_init_offsets(uint8_t * data, uint16_t * dst, uint32_t len)
9714 {
9715         uint16_t *src = (uint16_t *) data;
9716         uint32_t i;
9717
9718         for (i = 0; i < len / 2; ++i)
9719                 dst[i] = rte_be_to_cpu_16(src[i]);
9720 }
9721
9722 static void bnx2x_data_to_init_data(uint8_t * data, uint32_t * dst, uint32_t len)
9723 {
9724         uint32_t *src = (uint32_t *) data;
9725         uint32_t i;
9726
9727         for (i = 0; i < len / 4; ++i)
9728                 dst[i] = rte_be_to_cpu_32(src[i]);
9729 }
9730
9731 static void bnx2x_data_to_iro_array(uint8_t * data, struct iro *dst, uint32_t len)
9732 {
9733         uint32_t *src = (uint32_t *) data;
9734         uint32_t i, j, tmp;
9735
9736         for (i = 0, j = 0; i < len / sizeof(struct iro); ++i, ++j) {
9737                 dst[i].base = rte_be_to_cpu_32(src[j++]);
9738                 tmp = rte_be_to_cpu_32(src[j]);
9739                 dst[i].m1 = (tmp >> 16) & 0xFFFF;
9740                 dst[i].m2 = tmp & 0xFFFF;
9741                 ++j;
9742                 tmp = rte_be_to_cpu_32(src[j]);
9743                 dst[i].m3 = (tmp >> 16) & 0xFFFF;
9744                 dst[i].size = tmp & 0xFFFF;
9745         }
9746 }
9747
9748 /*
9749 * Device attach function.
9750 *
9751 * Allocates device resources, performs secondary chip identification, and
9752 * initializes driver instance variables. This function is called from driver
9753 * load after a successful probe.
9754 *
9755 * Returns:
9756 *   0 = Success, >0 = Failure
9757 */
9758 int bnx2x_attach(struct bnx2x_softc *sc)
9759 {
9760         int rc;
9761
9762         PMD_DRV_LOG(DEBUG, sc, "Starting attach...");
9763
9764         rc = bnx2x_pci_get_caps(sc);
9765         if (rc) {
9766                 PMD_DRV_LOG(NOTICE, sc, "PCIe caps reading was failed");
9767                 return rc;
9768         }
9769
9770         sc->state = BNX2X_STATE_CLOSED;
9771
9772         pci_write_long(sc, PCICFG_GRC_ADDRESS, PCICFG_VENDOR_ID_OFFSET);
9773
9774         sc->igu_base_addr = IS_VF(sc) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
9775
9776         /* get PCI capabilites */
9777         bnx2x_probe_pci_caps(sc);
9778
9779         if (sc->devinfo.pcie_msix_cap_reg != 0) {
9780                 uint32_t val;
9781                 pci_read(sc,
9782                          (sc->devinfo.pcie_msix_cap_reg + PCIR_MSIX_CTRL), &val,
9783                          2);
9784                 sc->igu_sb_cnt = (val & PCIM_MSIXCTRL_TABLE_SIZE) + 1;
9785         } else {
9786                 sc->igu_sb_cnt = 1;
9787         }
9788
9789         /* Init RTE stuff */
9790         bnx2x_init_rte(sc);
9791
9792         if (IS_PF(sc)) {
9793                 /* Enable internal target-read (in case we are probed after PF
9794                  * FLR). Must be done prior to any BAR read access. Only for
9795                  * 57712 and up
9796                  */
9797                 if (!CHIP_IS_E1x(sc)) {
9798                         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ,
9799                                1);
9800                         DELAY(200000);
9801                 }
9802
9803                 /* get device info and set params */
9804                 if (bnx2x_get_device_info(sc) != 0) {
9805                         PMD_DRV_LOG(NOTICE, sc, "getting device info");
9806                         return -ENXIO;
9807                 }
9808
9809 /* get phy settings from shmem and 'and' against admin settings */
9810                 bnx2x_get_phy_info(sc);
9811         } else {
9812                 /* Left mac of VF unfilled, PF should set it for VF */
9813                 memset(sc->link_params.mac_addr, 0, RTE_ETHER_ADDR_LEN);
9814         }
9815
9816         sc->wol = 0;
9817
9818         /* set the default MTU (changed via ifconfig) */
9819         sc->mtu = RTE_ETHER_MTU;
9820
9821         bnx2x_set_modes_bitmap(sc);
9822
9823         /* need to reset chip if UNDI was active */
9824         if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
9825 /* init fw_seq */
9826                 sc->fw_seq =
9827                     (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
9828                      DRV_MSG_SEQ_NUMBER_MASK);
9829                 PMD_DRV_LOG(DEBUG, sc, "prev unload fw_seq 0x%04x",
9830                             sc->fw_seq);
9831                 bnx2x_prev_unload(sc);
9832         }
9833
9834         bnx2x_dcbx_set_state(sc, FALSE, BNX2X_DCBX_ENABLED_OFF);
9835
9836         /* calculate qm_cid_count */
9837         sc->qm_cid_count = bnx2x_set_qm_cid_count(sc);
9838
9839         sc->max_cos = 1;
9840         bnx2x_init_multi_cos(sc);
9841
9842         return 0;
9843 }
9844
9845 static void
9846 bnx2x_igu_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t segment,
9847                uint16_t index, uint8_t op, uint8_t update)
9848 {
9849         uint32_t igu_addr = sc->igu_base_addr;
9850         igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
9851         bnx2x_igu_ack_sb_gen(sc, segment, index, op, update, igu_addr);
9852 }
9853
9854 static void
9855 bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t storm,
9856            uint16_t index, uint8_t op, uint8_t update)
9857 {
9858         if (unlikely(sc->devinfo.int_block == INT_BLOCK_HC))
9859                 bnx2x_hc_ack_sb(sc, igu_sb_id, storm, index, op, update);
9860         else {
9861                 uint8_t segment;
9862                 if (CHIP_INT_MODE_IS_BC(sc)) {
9863                         segment = storm;
9864                 } else if (igu_sb_id != sc->igu_dsb_id) {
9865                         segment = IGU_SEG_ACCESS_DEF;
9866                 } else if (storm == ATTENTION_ID) {
9867                         segment = IGU_SEG_ACCESS_ATTN;
9868                 } else {
9869                         segment = IGU_SEG_ACCESS_DEF;
9870                 }
9871                 bnx2x_igu_ack_sb(sc, igu_sb_id, segment, index, op, update);
9872         }
9873 }
9874
9875 static void
9876 bnx2x_igu_clear_sb_gen(struct bnx2x_softc *sc, uint8_t func, uint8_t idu_sb_id,
9877                      uint8_t is_pf)
9878 {
9879         uint32_t data, ctl, cnt = 100;
9880         uint32_t igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
9881         uint32_t igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
9882         uint32_t igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP +
9883             (idu_sb_id / 32) * 4;
9884         uint32_t sb_bit = 1 << (idu_sb_id % 32);
9885         uint32_t func_encode = func |
9886             (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
9887         uint32_t addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
9888
9889         /* Not supported in BC mode */
9890         if (CHIP_INT_MODE_IS_BC(sc)) {
9891                 return;
9892         }
9893
9894         data = ((IGU_USE_REGISTER_cstorm_type_0_sb_cleanup <<
9895                  IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
9896                 IGU_REGULAR_CLEANUP_SET | IGU_REGULAR_BCLEANUP);
9897
9898         ctl = ((addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT) |
9899                (func_encode << IGU_CTRL_REG_FID_SHIFT) |
9900                (IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT));
9901
9902         REG_WR(sc, igu_addr_data, data);
9903
9904         mb();
9905
9906         PMD_DRV_LOG(DEBUG, sc, "write 0x%08x to IGU(via GRC) addr 0x%x",
9907                     ctl, igu_addr_ctl);
9908         REG_WR(sc, igu_addr_ctl, ctl);
9909
9910         mb();
9911
9912         /* wait for clean up to finish */
9913         while (!(REG_RD(sc, igu_addr_ack) & sb_bit) && --cnt) {
9914                 DELAY(20000);
9915         }
9916
9917         if (!(REG_RD(sc, igu_addr_ack) & sb_bit)) {
9918                 PMD_DRV_LOG(DEBUG, sc,
9919                             "Unable to finish IGU cleanup: "
9920                             "idu_sb_id %d offset %d bit %d (cnt %d)",
9921                             idu_sb_id, idu_sb_id / 32, idu_sb_id % 32, cnt);
9922         }
9923 }
9924
9925 static void bnx2x_igu_clear_sb(struct bnx2x_softc *sc, uint8_t idu_sb_id)
9926 {
9927         bnx2x_igu_clear_sb_gen(sc, SC_FUNC(sc), idu_sb_id, TRUE /*PF*/);
9928 }
9929
9930 /*******************/
9931 /* ECORE CALLBACKS */
9932 /*******************/
9933
9934 static void bnx2x_reset_common(struct bnx2x_softc *sc)
9935 {
9936         uint32_t val = 0x1400;
9937
9938         PMD_INIT_FUNC_TRACE(sc);
9939
9940         /* reset_common */
9941         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR),
9942                0xd3ffff7f);
9943
9944         if (CHIP_IS_E3(sc)) {
9945                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
9946                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
9947         }
9948
9949         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR), val);
9950 }
9951
9952 static void bnx2x_common_init_phy(struct bnx2x_softc *sc)
9953 {
9954         uint32_t shmem_base[2];
9955         uint32_t shmem2_base[2];
9956
9957         /* Avoid common init in case MFW supports LFA */
9958         if (SHMEM2_RD(sc, size) >
9959             (uint32_t) offsetof(struct shmem2_region,
9960                                 lfa_host_addr[SC_PORT(sc)])) {
9961                 return;
9962         }
9963
9964         shmem_base[0] = sc->devinfo.shmem_base;
9965         shmem2_base[0] = sc->devinfo.shmem2_base;
9966
9967         if (!CHIP_IS_E1x(sc)) {
9968                 shmem_base[1] = SHMEM2_RD(sc, other_shmem_base_addr);
9969                 shmem2_base[1] = SHMEM2_RD(sc, other_shmem2_base_addr);
9970         }
9971
9972         bnx2x_acquire_phy_lock(sc);
9973         elink_common_init_phy(sc, shmem_base, shmem2_base,
9974                               sc->devinfo.chip_id, 0);
9975         bnx2x_release_phy_lock(sc);
9976 }
9977
9978 static void bnx2x_pf_disable(struct bnx2x_softc *sc)
9979 {
9980         uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
9981
9982         val &= ~IGU_PF_CONF_FUNC_EN;
9983
9984         REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
9985         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
9986         REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 0);
9987 }
9988
9989 static void bnx2x_init_pxp(struct bnx2x_softc *sc)
9990 {
9991         uint16_t devctl;
9992         int r_order, w_order;
9993
9994         devctl = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_CTL);
9995
9996         w_order = ((devctl & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5);
9997         r_order = ((devctl & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12);
9998
9999         ecore_init_pxp_arb(sc, r_order, w_order);
10000 }
10001
10002 static uint32_t bnx2x_get_pretend_reg(struct bnx2x_softc *sc)
10003 {
10004         uint32_t base = PXP2_REG_PGL_PRETEND_FUNC_F0;
10005         uint32_t stride = (PXP2_REG_PGL_PRETEND_FUNC_F1 - base);
10006         return base + (SC_ABS_FUNC(sc)) * stride;
10007 }
10008
10009 /*
10010  * Called only on E1H or E2.
10011  * When pretending to be PF, the pretend value is the function number 0..7.
10012  * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
10013  * combination.
10014  */
10015 static int bnx2x_pretend_func(struct bnx2x_softc *sc, uint16_t pretend_func_val)
10016 {
10017         uint32_t pretend_reg;
10018
10019         if (CHIP_IS_E1H(sc) && (pretend_func_val > E1H_FUNC_MAX))
10020                 return -1;
10021
10022         /* get my own pretend register */
10023         pretend_reg = bnx2x_get_pretend_reg(sc);
10024         REG_WR(sc, pretend_reg, pretend_func_val);
10025         REG_RD(sc, pretend_reg);
10026         return 0;
10027 }
10028
10029 static void bnx2x_setup_fan_failure_detection(struct bnx2x_softc *sc)
10030 {
10031         int is_required;
10032         uint32_t val;
10033         int port;
10034
10035         is_required = 0;
10036         val = (SHMEM_RD(sc, dev_info.shared_hw_config.config2) &
10037                SHARED_HW_CFG_FAN_FAILURE_MASK);
10038
10039         if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) {
10040                 is_required = 1;
10041         }
10042         /*
10043          * The fan failure mechanism is usually related to the PHY type since
10044          * the power consumption of the board is affected by the PHY. Currently,
10045          * fan is required for most designs with SFX7101, BNX2X8727 and BNX2X8481.
10046          */
10047         else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) {
10048                 for (port = PORT_0; port < PORT_MAX; port++) {
10049                         is_required |= elink_fan_failure_det_req(sc,
10050                                                                  sc->
10051                                                                  devinfo.shmem_base,
10052                                                                  sc->
10053                                                                  devinfo.shmem2_base,
10054                                                                  port);
10055                 }
10056         }
10057
10058         if (is_required == 0) {
10059                 return;
10060         }
10061
10062         /* Fan failure is indicated by SPIO 5 */
10063         bnx2x_set_spio(sc, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
10064
10065         /* set to active low mode */
10066         val = REG_RD(sc, MISC_REG_SPIO_INT);
10067         val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
10068         REG_WR(sc, MISC_REG_SPIO_INT, val);
10069
10070         /* enable interrupt to signal the IGU */
10071         val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
10072         val |= MISC_SPIO_SPIO5;
10073         REG_WR(sc, MISC_REG_SPIO_EVENT_EN, val);
10074 }
10075
10076 static void bnx2x_enable_blocks_attention(struct bnx2x_softc *sc)
10077 {
10078         uint32_t val;
10079
10080         REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0);
10081         if (!CHIP_IS_E1x(sc)) {
10082                 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0x40);
10083         } else {
10084                 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0);
10085         }
10086         REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
10087         REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
10088         /*
10089          * mask read length error interrupts in brb for parser
10090          * (parsing unit and 'checksum and crc' unit)
10091          * these errors are legal (PU reads fixed length and CAC can cause
10092          * read length error on truncated packets)
10093          */
10094         REG_WR(sc, BRB1_REG_BRB1_INT_MASK, 0xFC00);
10095         REG_WR(sc, QM_REG_QM_INT_MASK, 0);
10096         REG_WR(sc, TM_REG_TM_INT_MASK, 0);
10097         REG_WR(sc, XSDM_REG_XSDM_INT_MASK_0, 0);
10098         REG_WR(sc, XSDM_REG_XSDM_INT_MASK_1, 0);
10099         REG_WR(sc, XCM_REG_XCM_INT_MASK, 0);
10100         /*      REG_WR(sc, XSEM_REG_XSEM_INT_MASK_0, 0); */
10101         /*      REG_WR(sc, XSEM_REG_XSEM_INT_MASK_1, 0); */
10102         REG_WR(sc, USDM_REG_USDM_INT_MASK_0, 0);
10103         REG_WR(sc, USDM_REG_USDM_INT_MASK_1, 0);
10104         REG_WR(sc, UCM_REG_UCM_INT_MASK, 0);
10105         /*      REG_WR(sc, USEM_REG_USEM_INT_MASK_0, 0); */
10106         /*      REG_WR(sc, USEM_REG_USEM_INT_MASK_1, 0); */
10107         REG_WR(sc, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
10108         REG_WR(sc, CSDM_REG_CSDM_INT_MASK_0, 0);
10109         REG_WR(sc, CSDM_REG_CSDM_INT_MASK_1, 0);
10110         REG_WR(sc, CCM_REG_CCM_INT_MASK, 0);
10111         /*      REG_WR(sc, CSEM_REG_CSEM_INT_MASK_0, 0); */
10112         /*      REG_WR(sc, CSEM_REG_CSEM_INT_MASK_1, 0); */
10113
10114         val = (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
10115                PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
10116                PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN);
10117         if (!CHIP_IS_E1x(sc)) {
10118                 val |= (PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
10119                         PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED);
10120         }
10121         REG_WR(sc, PXP2_REG_PXP2_INT_MASK_0, val);
10122
10123         REG_WR(sc, TSDM_REG_TSDM_INT_MASK_0, 0);
10124         REG_WR(sc, TSDM_REG_TSDM_INT_MASK_1, 0);
10125         REG_WR(sc, TCM_REG_TCM_INT_MASK, 0);
10126         /*      REG_WR(sc, TSEM_REG_TSEM_INT_MASK_0, 0); */
10127
10128         if (!CHIP_IS_E1x(sc)) {
10129 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
10130                 REG_WR(sc, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
10131         }
10132
10133         REG_WR(sc, CDU_REG_CDU_INT_MASK, 0);
10134         REG_WR(sc, DMAE_REG_DMAE_INT_MASK, 0);
10135         /*      REG_WR(sc, MISC_REG_MISC_INT_MASK, 0); */
10136         REG_WR(sc, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
10137 }
10138
10139 /**
10140  * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
10141  *
10142  * @sc:     driver handle
10143  */
10144 static int bnx2x_init_hw_common(struct bnx2x_softc *sc)
10145 {
10146         uint8_t abs_func_id;
10147         uint32_t val;
10148
10149         PMD_DRV_LOG(DEBUG, sc,
10150                     "starting common init for func %d", SC_ABS_FUNC(sc));
10151
10152         /*
10153          * take the RESET lock to protect undi_unload flow from accessing
10154          * registers while we are resetting the chip
10155          */
10156         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10157
10158         bnx2x_reset_common(sc);
10159
10160         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET), 0xffffffff);
10161
10162         val = 0xfffc;
10163         if (CHIP_IS_E3(sc)) {
10164                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
10165                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
10166         }
10167
10168         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET), val);
10169
10170         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10171
10172         ecore_init_block(sc, BLOCK_MISC, PHASE_COMMON);
10173
10174         if (!CHIP_IS_E1x(sc)) {
10175 /*
10176  * 4-port mode or 2-port mode we need to turn off master-enable for
10177  * everyone. After that we turn it back on for self. So, we disregard
10178  * multi-function, and always disable all functions on the given path,
10179  * this means 0,2,4,6 for path 0 and 1,3,5,7 for path 1
10180  */
10181                 for (abs_func_id = SC_PATH(sc);
10182                      abs_func_id < (E2_FUNC_MAX * 2); abs_func_id += 2) {
10183                         if (abs_func_id == SC_ABS_FUNC(sc)) {
10184                                 REG_WR(sc,
10185                                        PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
10186                                        1);
10187                                 continue;
10188                         }
10189
10190                         bnx2x_pretend_func(sc, abs_func_id);
10191
10192                         /* clear pf enable */
10193                         bnx2x_pf_disable(sc);
10194
10195                         bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10196                 }
10197         }
10198
10199         ecore_init_block(sc, BLOCK_PXP, PHASE_COMMON);
10200
10201         ecore_init_block(sc, BLOCK_PXP2, PHASE_COMMON);
10202         bnx2x_init_pxp(sc);
10203
10204 #ifdef __BIG_ENDIAN
10205         REG_WR(sc, PXP2_REG_RQ_QM_ENDIAN_M, 1);
10206         REG_WR(sc, PXP2_REG_RQ_TM_ENDIAN_M, 1);
10207         REG_WR(sc, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
10208         REG_WR(sc, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
10209         REG_WR(sc, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
10210         /* make sure this value is 0 */
10211         REG_WR(sc, PXP2_REG_RQ_HC_ENDIAN_M, 0);
10212
10213         //REG_WR(sc, PXP2_REG_RD_PBF_SWAP_MODE, 1);
10214         REG_WR(sc, PXP2_REG_RD_QM_SWAP_MODE, 1);
10215         REG_WR(sc, PXP2_REG_RD_TM_SWAP_MODE, 1);
10216         REG_WR(sc, PXP2_REG_RD_SRC_SWAP_MODE, 1);
10217         REG_WR(sc, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
10218 #endif
10219
10220         ecore_ilt_init_page_size(sc, INITOP_SET);
10221
10222         if (CHIP_REV_IS_FPGA(sc) && CHIP_IS_E1H(sc)) {
10223                 REG_WR(sc, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
10224         }
10225
10226         /* let the HW do it's magic... */
10227         DELAY(100000);
10228
10229         /* finish PXP init */
10230
10231         val = REG_RD(sc, PXP2_REG_RQ_CFG_DONE);
10232         if (val != 1) {
10233                 PMD_DRV_LOG(NOTICE, sc, "PXP2 CFG failed");
10234                 return -1;
10235         }
10236         val = REG_RD(sc, PXP2_REG_RD_INIT_DONE);
10237         if (val != 1) {
10238                 PMD_DRV_LOG(NOTICE, sc, "PXP2 RD_INIT failed");
10239                 return -1;
10240         }
10241
10242         /*
10243          * Timer bug workaround for E2 only. We need to set the entire ILT to have
10244          * entries with value "0" and valid bit on. This needs to be done by the
10245          * first PF that is loaded in a path (i.e. common phase)
10246          */
10247         if (!CHIP_IS_E1x(sc)) {
10248 /*
10249  * In E2 there is a bug in the timers block that can cause function 6 / 7
10250  * (i.e. vnic3) to start even if it is marked as "scan-off".
10251  * This occurs when a different function (func2,3) is being marked
10252  * as "scan-off". Real-life scenario for example: if a driver is being
10253  * load-unloaded while func6,7 are down. This will cause the timer to access
10254  * the ilt, translate to a logical address and send a request to read/write.
10255  * Since the ilt for the function that is down is not valid, this will cause
10256  * a translation error which is unrecoverable.
10257  * The Workaround is intended to make sure that when this happens nothing
10258  * fatal will occur. The workaround:
10259  *  1.  First PF driver which loads on a path will:
10260  *      a.  After taking the chip out of reset, by using pretend,
10261  *          it will write "0" to the following registers of
10262  *          the other vnics.
10263  *          REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10264  *          REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
10265  *          REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
10266  *          And for itself it will write '1' to
10267  *          PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
10268  *          dmae-operations (writing to pram for example.)
10269  *          note: can be done for only function 6,7 but cleaner this
10270  *            way.
10271  *      b.  Write zero+valid to the entire ILT.
10272  *      c.  Init the first_timers_ilt_entry, last_timers_ilt_entry of
10273  *          VNIC3 (of that port). The range allocated will be the
10274  *          entire ILT. This is needed to prevent  ILT range error.
10275  *  2.  Any PF driver load flow:
10276  *      a.  ILT update with the physical addresses of the allocated
10277  *          logical pages.
10278  *      b.  Wait 20msec. - note that this timeout is needed to make
10279  *          sure there are no requests in one of the PXP internal
10280  *          queues with "old" ILT addresses.
10281  *      c.  PF enable in the PGLC.
10282  *      d.  Clear the was_error of the PF in the PGLC. (could have
10283  *          occurred while driver was down)
10284  *      e.  PF enable in the CFC (WEAK + STRONG)
10285  *      f.  Timers scan enable
10286  *  3.  PF driver unload flow:
10287  *      a.  Clear the Timers scan_en.
10288  *      b.  Polling for scan_on=0 for that PF.
10289  *      c.  Clear the PF enable bit in the PXP.
10290  *      d.  Clear the PF enable in the CFC (WEAK + STRONG)
10291  *      e.  Write zero+valid to all ILT entries (The valid bit must
10292  *          stay set)
10293  *      f.  If this is VNIC 3 of a port then also init
10294  *          first_timers_ilt_entry to zero and last_timers_ilt_entry
10295  *          to the last enrty in the ILT.
10296  *
10297  *      Notes:
10298  *      Currently the PF error in the PGLC is non recoverable.
10299  *      In the future the there will be a recovery routine for this error.
10300  *      Currently attention is masked.
10301  *      Having an MCP lock on the load/unload process does not guarantee that
10302  *      there is no Timer disable during Func6/7 enable. This is because the
10303  *      Timers scan is currently being cleared by the MCP on FLR.
10304  *      Step 2.d can be done only for PF6/7 and the driver can also check if
10305  *      there is error before clearing it. But the flow above is simpler and
10306  *      more general.
10307  *      All ILT entries are written by zero+valid and not just PF6/7
10308  *      ILT entries since in the future the ILT entries allocation for
10309  *      PF-s might be dynamic.
10310  */
10311                 struct ilt_client_info ilt_cli;
10312                 struct ecore_ilt ilt;
10313
10314                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
10315                 memset(&ilt, 0, sizeof(struct ecore_ilt));
10316
10317 /* initialize dummy TM client */
10318                 ilt_cli.start = 0;
10319                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
10320                 ilt_cli.client_num = ILT_CLIENT_TM;
10321
10322 /*
10323  * Step 1: set zeroes to all ilt page entries with valid bit on
10324  * Step 2: set the timers first/last ilt entry to point
10325  * to the entire range to prevent ILT range error for 3rd/4th
10326  * vnic (this code assumes existence of the vnic)
10327  *
10328  * both steps performed by call to ecore_ilt_client_init_op()
10329  * with dummy TM client
10330  *
10331  * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
10332  * and his brother are split registers
10333  */
10334
10335                 bnx2x_pretend_func(sc, (SC_PATH(sc) + 6));
10336                 ecore_ilt_client_init_op_ilt(sc, &ilt, &ilt_cli, INITOP_CLEAR);
10337                 bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10338
10339                 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
10340                 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
10341                 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
10342         }
10343
10344         REG_WR(sc, PXP2_REG_RQ_DISABLE_INPUTS, 0);
10345         REG_WR(sc, PXP2_REG_RD_DISABLE_INPUTS, 0);
10346
10347         if (!CHIP_IS_E1x(sc)) {
10348                 int factor = 0;
10349
10350                 ecore_init_block(sc, BLOCK_PGLUE_B, PHASE_COMMON);
10351                 ecore_init_block(sc, BLOCK_ATC, PHASE_COMMON);
10352
10353 /* let the HW do it's magic... */
10354                 do {
10355                         DELAY(200000);
10356                         val = REG_RD(sc, ATC_REG_ATC_INIT_DONE);
10357                 } while (factor-- && (val != 1));
10358
10359                 if (val != 1) {
10360                         PMD_DRV_LOG(NOTICE, sc, "ATC_INIT failed");
10361                         return -1;
10362                 }
10363         }
10364
10365         ecore_init_block(sc, BLOCK_DMAE, PHASE_COMMON);
10366
10367         /* clean the DMAE memory */
10368         sc->dmae_ready = 1;
10369         ecore_init_fill(sc, TSEM_REG_PRAM, 0, 8, 1);
10370
10371         ecore_init_block(sc, BLOCK_TCM, PHASE_COMMON);
10372
10373         ecore_init_block(sc, BLOCK_UCM, PHASE_COMMON);
10374
10375         ecore_init_block(sc, BLOCK_CCM, PHASE_COMMON);
10376
10377         ecore_init_block(sc, BLOCK_XCM, PHASE_COMMON);
10378
10379         bnx2x_read_dmae(sc, XSEM_REG_PASSIVE_BUFFER, 3);
10380         bnx2x_read_dmae(sc, CSEM_REG_PASSIVE_BUFFER, 3);
10381         bnx2x_read_dmae(sc, TSEM_REG_PASSIVE_BUFFER, 3);
10382         bnx2x_read_dmae(sc, USEM_REG_PASSIVE_BUFFER, 3);
10383
10384         ecore_init_block(sc, BLOCK_QM, PHASE_COMMON);
10385
10386         /* QM queues pointers table */
10387         ecore_qm_init_ptr_table(sc, sc->qm_cid_count, INITOP_SET);
10388
10389         /* soft reset pulse */
10390         REG_WR(sc, QM_REG_SOFT_RESET, 1);
10391         REG_WR(sc, QM_REG_SOFT_RESET, 0);
10392
10393         if (CNIC_SUPPORT(sc))
10394                 ecore_init_block(sc, BLOCK_TM, PHASE_COMMON);
10395
10396         ecore_init_block(sc, BLOCK_DORQ, PHASE_COMMON);
10397
10398         if (!CHIP_REV_IS_SLOW(sc)) {
10399 /* enable hw interrupt from doorbell Q */
10400                 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
10401         }
10402
10403         ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON);
10404
10405         ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON);
10406         REG_WR(sc, PRS_REG_A_PRSU_20, 0xf);
10407         REG_WR(sc, PRS_REG_E1HOV_MODE, sc->devinfo.mf_info.path_has_ovlan);
10408
10409         if (!CHIP_IS_E1x(sc) && !CHIP_IS_E3B0(sc)) {
10410                 if (IS_MF_AFEX(sc)) {
10411                         /*
10412                          * configure that AFEX and VLAN headers must be
10413                          * received in AFEX mode
10414                          */
10415                         REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC, 0xE);
10416                         REG_WR(sc, PRS_REG_MUST_HAVE_HDRS, 0xA);
10417                         REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
10418                         REG_WR(sc, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
10419                         REG_WR(sc, PRS_REG_TAG_LEN_0, 0x4);
10420                 } else {
10421                         /*
10422                          * Bit-map indicating which L2 hdrs may appear
10423                          * after the basic Ethernet header
10424                          */
10425                         REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC,
10426                                sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10427                 }
10428         }
10429
10430         ecore_init_block(sc, BLOCK_TSDM, PHASE_COMMON);
10431         ecore_init_block(sc, BLOCK_CSDM, PHASE_COMMON);
10432         ecore_init_block(sc, BLOCK_USDM, PHASE_COMMON);
10433         ecore_init_block(sc, BLOCK_XSDM, PHASE_COMMON);
10434
10435         if (!CHIP_IS_E1x(sc)) {
10436 /* reset VFC memories */
10437                 REG_WR(sc, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10438                        VFC_MEMORIES_RST_REG_CAM_RST |
10439                        VFC_MEMORIES_RST_REG_RAM_RST);
10440                 REG_WR(sc, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10441                        VFC_MEMORIES_RST_REG_CAM_RST |
10442                        VFC_MEMORIES_RST_REG_RAM_RST);
10443
10444                 DELAY(20000);
10445         }
10446
10447         ecore_init_block(sc, BLOCK_TSEM, PHASE_COMMON);
10448         ecore_init_block(sc, BLOCK_USEM, PHASE_COMMON);
10449         ecore_init_block(sc, BLOCK_CSEM, PHASE_COMMON);
10450         ecore_init_block(sc, BLOCK_XSEM, PHASE_COMMON);
10451
10452         /* sync semi rtc */
10453         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x80000000);
10454         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x80000000);
10455
10456         ecore_init_block(sc, BLOCK_UPB, PHASE_COMMON);
10457         ecore_init_block(sc, BLOCK_XPB, PHASE_COMMON);
10458         ecore_init_block(sc, BLOCK_PBF, PHASE_COMMON);
10459
10460         if (!CHIP_IS_E1x(sc)) {
10461                 if (IS_MF_AFEX(sc)) {
10462                         /*
10463                          * configure that AFEX and VLAN headers must be
10464                          * sent in AFEX mode
10465                          */
10466                         REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC, 0xE);
10467                         REG_WR(sc, PBF_REG_MUST_HAVE_HDRS, 0xA);
10468                         REG_WR(sc, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
10469                         REG_WR(sc, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
10470                         REG_WR(sc, PBF_REG_TAG_LEN_0, 0x4);
10471                 } else {
10472                         REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC,
10473                                sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10474                 }
10475         }
10476
10477         REG_WR(sc, SRC_REG_SOFT_RST, 1);
10478
10479         ecore_init_block(sc, BLOCK_SRC, PHASE_COMMON);
10480
10481         if (CNIC_SUPPORT(sc)) {
10482                 REG_WR(sc, SRC_REG_KEYSEARCH_0, 0x63285672);
10483                 REG_WR(sc, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
10484                 REG_WR(sc, SRC_REG_KEYSEARCH_2, 0x223aef9b);
10485                 REG_WR(sc, SRC_REG_KEYSEARCH_3, 0x26001e3a);
10486                 REG_WR(sc, SRC_REG_KEYSEARCH_4, 0x7ae91116);
10487                 REG_WR(sc, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
10488                 REG_WR(sc, SRC_REG_KEYSEARCH_6, 0x298d8adf);
10489                 REG_WR(sc, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
10490                 REG_WR(sc, SRC_REG_KEYSEARCH_8, 0x1830f82f);
10491                 REG_WR(sc, SRC_REG_KEYSEARCH_9, 0x01e46be7);
10492         }
10493         REG_WR(sc, SRC_REG_SOFT_RST, 0);
10494
10495         if (sizeof(union cdu_context) != 1024) {
10496 /* we currently assume that a context is 1024 bytes */
10497                 PMD_DRV_LOG(NOTICE, sc,
10498                             "please adjust the size of cdu_context(%ld)",
10499                             (long)sizeof(union cdu_context));
10500         }
10501
10502         ecore_init_block(sc, BLOCK_CDU, PHASE_COMMON);
10503         val = (4 << 24) + (0 << 12) + 1024;
10504         REG_WR(sc, CDU_REG_CDU_GLOBAL_PARAMS, val);
10505
10506         ecore_init_block(sc, BLOCK_CFC, PHASE_COMMON);
10507
10508         REG_WR(sc, CFC_REG_INIT_REG, 0x7FF);
10509         /* enable context validation interrupt from CFC */
10510         REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
10511
10512         /* set the thresholds to prevent CFC/CDU race */
10513         REG_WR(sc, CFC_REG_DEBUG0, 0x20020000);
10514         ecore_init_block(sc, BLOCK_HC, PHASE_COMMON);
10515
10516         if (!CHIP_IS_E1x(sc) && BNX2X_NOMCP(sc)) {
10517                 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x36);
10518         }
10519
10520         ecore_init_block(sc, BLOCK_IGU, PHASE_COMMON);
10521         ecore_init_block(sc, BLOCK_MISC_AEU, PHASE_COMMON);
10522
10523         /* Reset PCIE errors for debug */
10524         REG_WR(sc, 0x2814, 0xffffffff);
10525         REG_WR(sc, 0x3820, 0xffffffff);
10526
10527         if (!CHIP_IS_E1x(sc)) {
10528                 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
10529                        (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
10530                         PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
10531                 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
10532                        (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
10533                         PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
10534                         PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
10535                 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
10536                        (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
10537                         PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
10538                         PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
10539         }
10540
10541         ecore_init_block(sc, BLOCK_NIG, PHASE_COMMON);
10542
10543         /* in E3 this done in per-port section */
10544         if (!CHIP_IS_E3(sc))
10545                 REG_WR(sc, NIG_REG_LLH_MF_MODE, IS_MF(sc));
10546
10547         if (CHIP_IS_E1H(sc)) {
10548 /* not applicable for E2 (and above ...) */
10549                 REG_WR(sc, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(sc));
10550         }
10551
10552         if (CHIP_REV_IS_SLOW(sc)) {
10553                 DELAY(200000);
10554         }
10555
10556         /* finish CFC init */
10557         val = reg_poll(sc, CFC_REG_LL_INIT_DONE, 1, 100, 10);
10558         if (val != 1) {
10559                 PMD_DRV_LOG(NOTICE, sc, "CFC LL_INIT failed");
10560                 return -1;
10561         }
10562         val = reg_poll(sc, CFC_REG_AC_INIT_DONE, 1, 100, 10);
10563         if (val != 1) {
10564                 PMD_DRV_LOG(NOTICE, sc, "CFC AC_INIT failed");
10565                 return -1;
10566         }
10567         val = reg_poll(sc, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
10568         if (val != 1) {
10569                 PMD_DRV_LOG(NOTICE, sc, "CFC CAM_INIT failed");
10570                 return -1;
10571         }
10572         REG_WR(sc, CFC_REG_DEBUG0, 0);
10573
10574         bnx2x_setup_fan_failure_detection(sc);
10575
10576         /* clear PXP2 attentions */
10577         REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
10578
10579         bnx2x_enable_blocks_attention(sc);
10580
10581         if (!CHIP_REV_IS_SLOW(sc)) {
10582                 ecore_enable_blocks_parity(sc);
10583         }
10584
10585         if (!BNX2X_NOMCP(sc)) {
10586                 if (CHIP_IS_E1x(sc)) {
10587                         bnx2x_common_init_phy(sc);
10588                 }
10589         }
10590
10591         return 0;
10592 }
10593
10594 /**
10595  * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
10596  *
10597  * @sc:     driver handle
10598  */
10599 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc)
10600 {
10601         int rc = bnx2x_init_hw_common(sc);
10602
10603         if (rc) {
10604                 return rc;
10605         }
10606
10607         /* In E2 2-PORT mode, same ext phy is used for the two paths */
10608         if (!BNX2X_NOMCP(sc)) {
10609                 bnx2x_common_init_phy(sc);
10610         }
10611
10612         return 0;
10613 }
10614
10615 static int bnx2x_init_hw_port(struct bnx2x_softc *sc)
10616 {
10617         int port = SC_PORT(sc);
10618         int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
10619         uint32_t low, high;
10620         uint32_t val;
10621
10622         PMD_DRV_LOG(DEBUG, sc, "starting port init for port %d", port);
10623
10624         REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
10625
10626         ecore_init_block(sc, BLOCK_MISC, init_phase);
10627         ecore_init_block(sc, BLOCK_PXP, init_phase);
10628         ecore_init_block(sc, BLOCK_PXP2, init_phase);
10629
10630         /*
10631          * Timers bug workaround: disables the pf_master bit in pglue at
10632          * common phase, we need to enable it here before any dmae access are
10633          * attempted. Therefore we manually added the enable-master to the
10634          * port phase (it also happens in the function phase)
10635          */
10636         if (!CHIP_IS_E1x(sc)) {
10637                 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
10638         }
10639
10640         ecore_init_block(sc, BLOCK_ATC, init_phase);
10641         ecore_init_block(sc, BLOCK_DMAE, init_phase);
10642         ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
10643         ecore_init_block(sc, BLOCK_QM, init_phase);
10644
10645         ecore_init_block(sc, BLOCK_TCM, init_phase);
10646         ecore_init_block(sc, BLOCK_UCM, init_phase);
10647         ecore_init_block(sc, BLOCK_CCM, init_phase);
10648         ecore_init_block(sc, BLOCK_XCM, init_phase);
10649
10650         /* QM cid (connection) count */
10651         ecore_qm_init_cid_count(sc, sc->qm_cid_count, INITOP_SET);
10652
10653         if (CNIC_SUPPORT(sc)) {
10654                 ecore_init_block(sc, BLOCK_TM, init_phase);
10655                 REG_WR(sc, TM_REG_LIN0_SCAN_TIME + port * 4, 20);
10656                 REG_WR(sc, TM_REG_LIN0_MAX_ACTIVE_CID + port * 4, 31);
10657         }
10658
10659         ecore_init_block(sc, BLOCK_DORQ, init_phase);
10660
10661         ecore_init_block(sc, BLOCK_BRB1, init_phase);
10662
10663         if (CHIP_IS_E1H(sc)) {
10664                 if (IS_MF(sc)) {
10665                         low = (BNX2X_ONE_PORT(sc) ? 160 : 246);
10666                 } else if (sc->mtu > 4096) {
10667                         if (BNX2X_ONE_PORT(sc)) {
10668                                 low = 160;
10669                         } else {
10670                                 val = sc->mtu;
10671                                 /* (24*1024 + val*4)/256 */
10672                                 low = (96 + (val / 64) + ((val % 64) ? 1 : 0));
10673                         }
10674                 } else {
10675                         low = (BNX2X_ONE_PORT(sc) ? 80 : 160);
10676                 }
10677                 high = (low + 56);      /* 14*1024/256 */
10678                 REG_WR(sc, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port * 4, low);
10679                 REG_WR(sc, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port * 4, high);
10680         }
10681
10682         if (CHIP_IS_MODE_4_PORT(sc)) {
10683                 REG_WR(sc, SC_PORT(sc) ?
10684                        BRB1_REG_MAC_GUARANTIED_1 :
10685                        BRB1_REG_MAC_GUARANTIED_0, 40);
10686         }
10687
10688         ecore_init_block(sc, BLOCK_PRS, init_phase);
10689         if (CHIP_IS_E3B0(sc)) {
10690                 if (IS_MF_AFEX(sc)) {
10691                         /* configure headers for AFEX mode */
10692                         if (SC_PORT(sc)) {
10693                                 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_1,
10694                                        0xE);
10695                                 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_1,
10696                                        0x6);
10697                                 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_1, 0xA);
10698                         } else {
10699                                 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10700                                        0xE);
10701                                 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_0,
10702                                        0x6);
10703                                 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
10704                         }
10705                 } else {
10706                         /* Ovlan exists only if we are in multi-function +
10707                          * switch-dependent mode, in switch-independent there
10708                          * is no ovlan headers
10709                          */
10710                         REG_WR(sc, SC_PORT(sc) ?
10711                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
10712                                PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10713                                (sc->devinfo.mf_info.path_has_ovlan ? 7 : 6));
10714                 }
10715         }
10716
10717         ecore_init_block(sc, BLOCK_TSDM, init_phase);
10718         ecore_init_block(sc, BLOCK_CSDM, init_phase);
10719         ecore_init_block(sc, BLOCK_USDM, init_phase);
10720         ecore_init_block(sc, BLOCK_XSDM, init_phase);
10721
10722         ecore_init_block(sc, BLOCK_TSEM, init_phase);
10723         ecore_init_block(sc, BLOCK_USEM, init_phase);
10724         ecore_init_block(sc, BLOCK_CSEM, init_phase);
10725         ecore_init_block(sc, BLOCK_XSEM, init_phase);
10726
10727         ecore_init_block(sc, BLOCK_UPB, init_phase);
10728         ecore_init_block(sc, BLOCK_XPB, init_phase);
10729
10730         ecore_init_block(sc, BLOCK_PBF, init_phase);
10731
10732         if (CHIP_IS_E1x(sc)) {
10733 /* configure PBF to work without PAUSE mtu 9000 */
10734                 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 0);
10735
10736 /* update threshold */
10737                 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, (9040 / 16));
10738 /* update init credit */
10739                 REG_WR(sc, PBF_REG_P0_INIT_CRD + port * 4,
10740                        (9040 / 16) + 553 - 22);
10741
10742 /* probe changes */
10743                 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 1);
10744                 DELAY(50);
10745                 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0);
10746         }
10747
10748         if (CNIC_SUPPORT(sc)) {
10749                 ecore_init_block(sc, BLOCK_SRC, init_phase);
10750         }
10751
10752         ecore_init_block(sc, BLOCK_CDU, init_phase);
10753         ecore_init_block(sc, BLOCK_CFC, init_phase);
10754         ecore_init_block(sc, BLOCK_HC, init_phase);
10755         ecore_init_block(sc, BLOCK_IGU, init_phase);
10756         ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
10757         /* init aeu_mask_attn_func_0/1:
10758          *  - SF mode: bits 3-7 are masked. only bits 0-2 are in use
10759          *  - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
10760          *             bits 4-7 are used for "per vn group attention" */
10761         val = IS_MF(sc) ? 0xF7 : 0x7;
10762         val |= 0x10;
10763         REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, val);
10764
10765         ecore_init_block(sc, BLOCK_NIG, init_phase);
10766
10767         if (!CHIP_IS_E1x(sc)) {
10768 /* Bit-map indicating which L2 hdrs may appear after the
10769  * basic Ethernet header
10770  */
10771                 if (IS_MF_AFEX(sc)) {
10772                         REG_WR(sc, SC_PORT(sc) ?
10773                                NIG_REG_P1_HDRS_AFTER_BASIC :
10774                                NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
10775                 } else {
10776                         REG_WR(sc, SC_PORT(sc) ?
10777                                NIG_REG_P1_HDRS_AFTER_BASIC :
10778                                NIG_REG_P0_HDRS_AFTER_BASIC,
10779                                IS_MF_SD(sc) ? 7 : 6);
10780                 }
10781
10782                 if (CHIP_IS_E3(sc)) {
10783                         REG_WR(sc, SC_PORT(sc) ?
10784                                NIG_REG_LLH1_MF_MODE :
10785                                NIG_REG_LLH_MF_MODE, IS_MF(sc));
10786                 }
10787         }
10788         if (!CHIP_IS_E3(sc)) {
10789                 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1);
10790         }
10791
10792         /* 0x2 disable mf_ov, 0x1 enable */
10793         REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port * 4,
10794                (IS_MF_SD(sc) ? 0x1 : 0x2));
10795
10796         if (!CHIP_IS_E1x(sc)) {
10797                 val = 0;
10798                 switch (sc->devinfo.mf_info.mf_mode) {
10799                 case MULTI_FUNCTION_SD:
10800                         val = 1;
10801                         break;
10802                 case MULTI_FUNCTION_SI:
10803                 case MULTI_FUNCTION_AFEX:
10804                         val = 2;
10805                         break;
10806                 }
10807
10808                 REG_WR(sc, (SC_PORT(sc) ? NIG_REG_LLH1_CLS_TYPE :
10809                             NIG_REG_LLH0_CLS_TYPE), val);
10810         }
10811         REG_WR(sc, NIG_REG_LLFC_ENABLE_0 + port * 4, 0);
10812         REG_WR(sc, NIG_REG_LLFC_OUT_EN_0 + port * 4, 0);
10813         REG_WR(sc, NIG_REG_PAUSE_ENABLE_0 + port * 4, 1);
10814
10815         /* If SPIO5 is set to generate interrupts, enable it for this port */
10816         val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
10817         if (val & MISC_SPIO_SPIO5) {
10818                 uint32_t reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
10819                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
10820                 val = REG_RD(sc, reg_addr);
10821                 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
10822                 REG_WR(sc, reg_addr, val);
10823         }
10824
10825         return 0;
10826 }
10827
10828 static uint32_t
10829 bnx2x_flr_clnup_reg_poll(struct bnx2x_softc *sc, uint32_t reg,
10830                        uint32_t expected, uint32_t poll_count)
10831 {
10832         uint32_t cur_cnt = poll_count;
10833         uint32_t val;
10834
10835         while ((val = REG_RD(sc, reg)) != expected && cur_cnt--) {
10836                 DELAY(FLR_WAIT_INTERVAL);
10837         }
10838
10839         return val;
10840 }
10841
10842 static int
10843 bnx2x_flr_clnup_poll_hw_counter(struct bnx2x_softc *sc, uint32_t reg,
10844                               __rte_unused const char *msg, uint32_t poll_cnt)
10845 {
10846         uint32_t val = bnx2x_flr_clnup_reg_poll(sc, reg, 0, poll_cnt);
10847
10848         if (val != 0) {
10849                 PMD_DRV_LOG(NOTICE, sc, "%s usage count=%d", msg, val);
10850                 return -1;
10851         }
10852
10853         return 0;
10854 }
10855
10856 /* Common routines with VF FLR cleanup */
10857 static uint32_t bnx2x_flr_clnup_poll_count(struct bnx2x_softc *sc)
10858 {
10859         /* adjust polling timeout */
10860         if (CHIP_REV_IS_EMUL(sc)) {
10861                 return FLR_POLL_CNT * 2000;
10862         }
10863
10864         if (CHIP_REV_IS_FPGA(sc)) {
10865                 return FLR_POLL_CNT * 120;
10866         }
10867
10868         return FLR_POLL_CNT;
10869 }
10870
10871 static int bnx2x_poll_hw_usage_counters(struct bnx2x_softc *sc, uint32_t poll_cnt)
10872 {
10873         /* wait for CFC PF usage-counter to zero (includes all the VFs) */
10874         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10875                                           CFC_REG_NUM_LCIDS_INSIDE_PF,
10876                                           "CFC PF usage counter timed out",
10877                                           poll_cnt)) {
10878                 return -1;
10879         }
10880
10881         /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
10882         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10883                                           DORQ_REG_PF_USAGE_CNT,
10884                                           "DQ PF usage counter timed out",
10885                                           poll_cnt)) {
10886                 return -1;
10887         }
10888
10889         /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
10890         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10891                                           QM_REG_PF_USG_CNT_0 + 4 * SC_FUNC(sc),
10892                                           "QM PF usage counter timed out",
10893                                           poll_cnt)) {
10894                 return -1;
10895         }
10896
10897         /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
10898         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10899                                           TM_REG_LIN0_VNIC_UC + 4 * SC_PORT(sc),
10900                                           "Timers VNIC usage counter timed out",
10901                                           poll_cnt)) {
10902                 return -1;
10903         }
10904
10905         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10906                                           TM_REG_LIN0_NUM_SCANS +
10907                                           4 * SC_PORT(sc),
10908                                           "Timers NUM_SCANS usage counter timed out",
10909                                           poll_cnt)) {
10910                 return -1;
10911         }
10912
10913         /* Wait DMAE PF usage counter to zero */
10914         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10915                                           dmae_reg_go_c[INIT_DMAE_C(sc)],
10916                                           "DMAE dommand register timed out",
10917                                           poll_cnt)) {
10918                 return -1;
10919         }
10920
10921         return 0;
10922 }
10923
10924 #define OP_GEN_PARAM(param)                                            \
10925         (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
10926 #define OP_GEN_TYPE(type)                                           \
10927         (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
10928 #define OP_GEN_AGG_VECT(index)                                             \
10929         (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
10930
10931 static int
10932 bnx2x_send_final_clnup(struct bnx2x_softc *sc, uint8_t clnup_func,
10933                      uint32_t poll_cnt)
10934 {
10935         uint32_t op_gen_command = 0;
10936         uint32_t comp_addr = (BAR_CSTRORM_INTMEM +
10937                               CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func));
10938         int ret = 0;
10939
10940         if (REG_RD(sc, comp_addr)) {
10941                 PMD_DRV_LOG(NOTICE, sc,
10942                             "Cleanup complete was not 0 before sending");
10943                 return -1;
10944         }
10945
10946         op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
10947         op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
10948         op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
10949         op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
10950
10951         REG_WR(sc, XSDM_REG_OPERATION_GEN, op_gen_command);
10952
10953         if (bnx2x_flr_clnup_reg_poll(sc, comp_addr, 1, poll_cnt) != 1) {
10954                 PMD_DRV_LOG(NOTICE, sc, "FW final cleanup did not succeed");
10955                 PMD_DRV_LOG(DEBUG, sc, "At timeout completion address contained %x",
10956                             (REG_RD(sc, comp_addr)));
10957                 rte_panic("FLR cleanup failed");
10958                 return -1;
10959         }
10960
10961         /* Zero completion for nxt FLR */
10962         REG_WR(sc, comp_addr, 0);
10963
10964         return ret;
10965 }
10966
10967 static void
10968 bnx2x_pbf_pN_buf_flushed(struct bnx2x_softc *sc, struct pbf_pN_buf_regs *regs,
10969                        uint32_t poll_count)
10970 {
10971         uint32_t init_crd, crd, crd_start, crd_freed, crd_freed_start;
10972         uint32_t cur_cnt = poll_count;
10973
10974         crd_freed = crd_freed_start = REG_RD(sc, regs->crd_freed);
10975         crd = crd_start = REG_RD(sc, regs->crd);
10976         init_crd = REG_RD(sc, regs->init_crd);
10977
10978         while ((crd != init_crd) &&
10979                ((uint32_t) ((int32_t) crd_freed - (int32_t) crd_freed_start) <
10980                 (init_crd - crd_start))) {
10981                 if (cur_cnt--) {
10982                         DELAY(FLR_WAIT_INTERVAL);
10983                         crd = REG_RD(sc, regs->crd);
10984                         crd_freed = REG_RD(sc, regs->crd_freed);
10985                 } else {
10986                         break;
10987                 }
10988         }
10989 }
10990
10991 static void
10992 bnx2x_pbf_pN_cmd_flushed(struct bnx2x_softc *sc, struct pbf_pN_cmd_regs *regs,
10993                        uint32_t poll_count)
10994 {
10995         uint32_t occup, to_free, freed, freed_start;
10996         uint32_t cur_cnt = poll_count;
10997
10998         occup = to_free = REG_RD(sc, regs->lines_occup);
10999         freed = freed_start = REG_RD(sc, regs->lines_freed);
11000
11001         while (occup &&
11002                ((uint32_t) ((int32_t) freed - (int32_t) freed_start) <
11003                 to_free)) {
11004                 if (cur_cnt--) {
11005                         DELAY(FLR_WAIT_INTERVAL);
11006                         occup = REG_RD(sc, regs->lines_occup);
11007                         freed = REG_RD(sc, regs->lines_freed);
11008                 } else {
11009                         break;
11010                 }
11011         }
11012 }
11013
11014 static void bnx2x_tx_hw_flushed(struct bnx2x_softc *sc, uint32_t poll_count)
11015 {
11016         struct pbf_pN_cmd_regs cmd_regs[] = {
11017                 {0, (CHIP_IS_E3B0(sc)) ?
11018                  PBF_REG_TQ_OCCUPANCY_Q0 : PBF_REG_P0_TQ_OCCUPANCY,
11019                  (CHIP_IS_E3B0(sc)) ?
11020                  PBF_REG_TQ_LINES_FREED_CNT_Q0 : PBF_REG_P0_TQ_LINES_FREED_CNT},
11021                 {1, (CHIP_IS_E3B0(sc)) ?
11022                  PBF_REG_TQ_OCCUPANCY_Q1 : PBF_REG_P1_TQ_OCCUPANCY,
11023                  (CHIP_IS_E3B0(sc)) ?
11024                  PBF_REG_TQ_LINES_FREED_CNT_Q1 : PBF_REG_P1_TQ_LINES_FREED_CNT},
11025                 {4, (CHIP_IS_E3B0(sc)) ?
11026                  PBF_REG_TQ_OCCUPANCY_LB_Q : PBF_REG_P4_TQ_OCCUPANCY,
11027                  (CHIP_IS_E3B0(sc)) ?
11028                  PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
11029                  PBF_REG_P4_TQ_LINES_FREED_CNT}
11030         };
11031
11032         struct pbf_pN_buf_regs buf_regs[] = {
11033                 {0, (CHIP_IS_E3B0(sc)) ?
11034                  PBF_REG_INIT_CRD_Q0 : PBF_REG_P0_INIT_CRD,
11035                  (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q0 : PBF_REG_P0_CREDIT,
11036                  (CHIP_IS_E3B0(sc)) ?
11037                  PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
11038                  PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
11039                 {1, (CHIP_IS_E3B0(sc)) ?
11040                  PBF_REG_INIT_CRD_Q1 : PBF_REG_P1_INIT_CRD,
11041                  (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q1 : PBF_REG_P1_CREDIT,
11042                  (CHIP_IS_E3B0(sc)) ?
11043                  PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
11044                  PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
11045                 {4, (CHIP_IS_E3B0(sc)) ?
11046                  PBF_REG_INIT_CRD_LB_Q : PBF_REG_P4_INIT_CRD,
11047                  (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_LB_Q : PBF_REG_P4_CREDIT,
11048                  (CHIP_IS_E3B0(sc)) ?
11049                  PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
11050                  PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
11051         };
11052
11053         uint32_t i;
11054
11055         /* Verify the command queues are flushed P0, P1, P4 */
11056         for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) {
11057                 bnx2x_pbf_pN_cmd_flushed(sc, &cmd_regs[i], poll_count);
11058         }
11059
11060         /* Verify the transmission buffers are flushed P0, P1, P4 */
11061         for (i = 0; i < ARRAY_SIZE(buf_regs); i++) {
11062                 bnx2x_pbf_pN_buf_flushed(sc, &buf_regs[i], poll_count);
11063         }
11064 }
11065
11066 static void bnx2x_hw_enable_status(struct bnx2x_softc *sc)
11067 {
11068         __rte_unused uint32_t val;
11069
11070         val = REG_RD(sc, CFC_REG_WEAK_ENABLE_PF);
11071         PMD_DRV_LOG(DEBUG, sc, "CFC_REG_WEAK_ENABLE_PF is 0x%x", val);
11072
11073         val = REG_RD(sc, PBF_REG_DISABLE_PF);
11074         PMD_DRV_LOG(DEBUG, sc, "PBF_REG_DISABLE_PF is 0x%x", val);
11075
11076         val = REG_RD(sc, IGU_REG_PCI_PF_MSI_EN);
11077         PMD_DRV_LOG(DEBUG, sc, "IGU_REG_PCI_PF_MSI_EN is 0x%x", val);
11078
11079         val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_EN);
11080         PMD_DRV_LOG(DEBUG, sc, "IGU_REG_PCI_PF_MSIX_EN is 0x%x", val);
11081
11082         val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
11083         PMD_DRV_LOG(DEBUG, sc, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x", val);
11084
11085         val = REG_RD(sc, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
11086         PMD_DRV_LOG(DEBUG, sc,
11087                     "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x", val);
11088
11089         val = REG_RD(sc, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
11090         PMD_DRV_LOG(DEBUG, sc,
11091                     "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x", val);
11092
11093         val = REG_RD(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
11094         PMD_DRV_LOG(DEBUG, sc, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x",
11095                     val);
11096 }
11097
11098 /**
11099  *      bnx2x_pf_flr_clnup
11100  *      a. re-enable target read on the PF
11101  *      b. poll cfc per function usgae counter
11102  *      c. poll the qm perfunction usage counter
11103  *      d. poll the tm per function usage counter
11104  *      e. poll the tm per function scan-done indication
11105  *      f. clear the dmae channel associated wit hthe PF
11106  *      g. zero the igu 'trailing edge' and 'leading edge' regs (attentions)
11107  *      h. call the common flr cleanup code with -1 (pf indication)
11108  */
11109 static int bnx2x_pf_flr_clnup(struct bnx2x_softc *sc)
11110 {
11111         uint32_t poll_cnt = bnx2x_flr_clnup_poll_count(sc);
11112
11113         /* Re-enable PF target read access */
11114         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
11115
11116         /* Poll HW usage counters */
11117         if (bnx2x_poll_hw_usage_counters(sc, poll_cnt)) {
11118                 return -1;
11119         }
11120
11121         /* Zero the igu 'trailing edge' and 'leading edge' */
11122
11123         /* Send the FW cleanup command */
11124         if (bnx2x_send_final_clnup(sc, (uint8_t) SC_FUNC(sc), poll_cnt)) {
11125                 return -1;
11126         }
11127
11128         /* ATC cleanup */
11129
11130         /* Verify TX hw is flushed */
11131         bnx2x_tx_hw_flushed(sc, poll_cnt);
11132
11133         /* Wait 100ms (not adjusted according to platform) */
11134         DELAY(100000);
11135
11136         /* Verify no pending pci transactions */
11137         if (bnx2x_is_pcie_pending(sc)) {
11138                 PMD_DRV_LOG(NOTICE, sc, "PCIE Transactions still pending");
11139         }
11140
11141         /* Debug */
11142         bnx2x_hw_enable_status(sc);
11143
11144         /*
11145          * Master enable - Due to WB DMAE writes performed before this
11146          * register is re-initialized as part of the regular function init
11147          */
11148         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11149
11150         return 0;
11151 }
11152
11153 static int bnx2x_init_hw_func(struct bnx2x_softc *sc)
11154 {
11155         int port = SC_PORT(sc);
11156         int func = SC_FUNC(sc);
11157         int init_phase = PHASE_PF0 + func;
11158         struct ecore_ilt *ilt = sc->ilt;
11159         uint16_t cdu_ilt_start;
11160         uint32_t addr, val;
11161         uint32_t main_mem_base, main_mem_size, main_mem_prty_clr;
11162         int main_mem_width, rc;
11163         uint32_t i;
11164
11165         PMD_DRV_LOG(DEBUG, sc, "starting func init for func %d", func);
11166
11167         /* FLR cleanup */
11168         if (!CHIP_IS_E1x(sc)) {
11169                 rc = bnx2x_pf_flr_clnup(sc);
11170                 if (rc) {
11171                         PMD_DRV_LOG(NOTICE, sc, "FLR cleanup failed!");
11172                         return rc;
11173                 }
11174         }
11175
11176         /* set MSI reconfigure capability */
11177         if (sc->devinfo.int_block == INT_BLOCK_HC) {
11178                 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
11179                 val = REG_RD(sc, addr);
11180                 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
11181                 REG_WR(sc, addr, val);
11182         }
11183
11184         ecore_init_block(sc, BLOCK_PXP, init_phase);
11185         ecore_init_block(sc, BLOCK_PXP2, init_phase);
11186
11187         ilt = sc->ilt;
11188         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
11189
11190         for (i = 0; i < L2_ILT_LINES(sc); i++) {
11191                 ilt->lines[cdu_ilt_start + i].page = sc->context[i].vcxt;
11192                 ilt->lines[cdu_ilt_start + i].page_mapping =
11193                     (rte_iova_t)sc->context[i].vcxt_dma.paddr;
11194                 ilt->lines[cdu_ilt_start + i].size = sc->context[i].size;
11195         }
11196         ecore_ilt_init_op(sc, INITOP_SET);
11197
11198         REG_WR(sc, PRS_REG_NIC_MODE, 1);
11199
11200         if (!CHIP_IS_E1x(sc)) {
11201                 uint32_t pf_conf = IGU_PF_CONF_FUNC_EN;
11202
11203 /* Turn on a single ISR mode in IGU if driver is going to use
11204  * INT#x or MSI
11205  */
11206                 if ((sc->interrupt_mode != INTR_MODE_MSIX)
11207                     || (sc->interrupt_mode != INTR_MODE_SINGLE_MSIX)) {
11208                         pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
11209                 }
11210
11211 /*
11212  * Timers workaround bug: function init part.
11213  * Need to wait 20msec after initializing ILT,
11214  * needed to make sure there are no requests in
11215  * one of the PXP internal queues with "old" ILT addresses
11216  */
11217                 DELAY(20000);
11218
11219 /*
11220  * Master enable - Due to WB DMAE writes performed before this
11221  * register is re-initialized as part of the regular function
11222  * init
11223  */
11224                 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11225 /* Enable the function in IGU */
11226                 REG_WR(sc, IGU_REG_PF_CONFIGURATION, pf_conf);
11227         }
11228
11229         sc->dmae_ready = 1;
11230
11231         ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
11232
11233         if (!CHIP_IS_E1x(sc))
11234                 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
11235
11236         ecore_init_block(sc, BLOCK_ATC, init_phase);
11237         ecore_init_block(sc, BLOCK_DMAE, init_phase);
11238         ecore_init_block(sc, BLOCK_NIG, init_phase);
11239         ecore_init_block(sc, BLOCK_SRC, init_phase);
11240         ecore_init_block(sc, BLOCK_MISC, init_phase);
11241         ecore_init_block(sc, BLOCK_TCM, init_phase);
11242         ecore_init_block(sc, BLOCK_UCM, init_phase);
11243         ecore_init_block(sc, BLOCK_CCM, init_phase);
11244         ecore_init_block(sc, BLOCK_XCM, init_phase);
11245         ecore_init_block(sc, BLOCK_TSEM, init_phase);
11246         ecore_init_block(sc, BLOCK_USEM, init_phase);
11247         ecore_init_block(sc, BLOCK_CSEM, init_phase);
11248         ecore_init_block(sc, BLOCK_XSEM, init_phase);
11249
11250         if (!CHIP_IS_E1x(sc))
11251                 REG_WR(sc, QM_REG_PF_EN, 1);
11252
11253         if (!CHIP_IS_E1x(sc)) {
11254                 REG_WR(sc, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11255                 REG_WR(sc, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11256                 REG_WR(sc, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11257                 REG_WR(sc, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11258         }
11259         ecore_init_block(sc, BLOCK_QM, init_phase);
11260
11261         ecore_init_block(sc, BLOCK_TM, init_phase);
11262         ecore_init_block(sc, BLOCK_DORQ, init_phase);
11263
11264         ecore_init_block(sc, BLOCK_BRB1, init_phase);
11265         ecore_init_block(sc, BLOCK_PRS, init_phase);
11266         ecore_init_block(sc, BLOCK_TSDM, init_phase);
11267         ecore_init_block(sc, BLOCK_CSDM, init_phase);
11268         ecore_init_block(sc, BLOCK_USDM, init_phase);
11269         ecore_init_block(sc, BLOCK_XSDM, init_phase);
11270         ecore_init_block(sc, BLOCK_UPB, init_phase);
11271         ecore_init_block(sc, BLOCK_XPB, init_phase);
11272         ecore_init_block(sc, BLOCK_PBF, init_phase);
11273         if (!CHIP_IS_E1x(sc))
11274                 REG_WR(sc, PBF_REG_DISABLE_PF, 0);
11275
11276         ecore_init_block(sc, BLOCK_CDU, init_phase);
11277
11278         ecore_init_block(sc, BLOCK_CFC, init_phase);
11279
11280         if (!CHIP_IS_E1x(sc))
11281                 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 1);
11282
11283         if (IS_MF(sc)) {
11284                 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
11285                 REG_WR(sc, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8, OVLAN(sc));
11286         }
11287
11288         ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
11289
11290         /* HC init per function */
11291         if (sc->devinfo.int_block == INT_BLOCK_HC) {
11292                 if (CHIP_IS_E1H(sc)) {
11293                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11294
11295                         REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11296                         REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11297                 }
11298                 ecore_init_block(sc, BLOCK_HC, init_phase);
11299
11300         } else {
11301                 uint32_t num_segs, sb_idx, prod_offset;
11302
11303                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11304
11305                 if (!CHIP_IS_E1x(sc)) {
11306                         REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11307                         REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11308                 }
11309
11310                 ecore_init_block(sc, BLOCK_IGU, init_phase);
11311
11312                 if (!CHIP_IS_E1x(sc)) {
11313                         int dsb_idx = 0;
11314         /**
11315          * Producer memory:
11316          * E2 mode: address 0-135 match to the mapping memory;
11317          * 136 - PF0 default prod; 137 - PF1 default prod;
11318          * 138 - PF2 default prod; 139 - PF3 default prod;
11319          * 140 - PF0 attn prod;    141 - PF1 attn prod;
11320          * 142 - PF2 attn prod;    143 - PF3 attn prod;
11321          * 144-147 reserved.
11322          *
11323          * E1.5 mode - In backward compatible mode;
11324          * for non default SB; each even line in the memory
11325          * holds the U producer and each odd line hold
11326          * the C producer. The first 128 producers are for
11327          * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
11328          * producers are for the DSB for each PF.
11329          * Each PF has five segments: (the order inside each
11330          * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
11331          * 132-135 C prods; 136-139 X prods; 140-143 T prods;
11332          * 144-147 attn prods;
11333          */
11334                         /* non-default-status-blocks */
11335                         num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11336                             IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
11337                         for (sb_idx = 0; sb_idx < sc->igu_sb_cnt; sb_idx++) {
11338                                 prod_offset = (sc->igu_base_sb + sb_idx) *
11339                                     num_segs;
11340
11341                                 for (i = 0; i < num_segs; i++) {
11342                                         addr = IGU_REG_PROD_CONS_MEMORY +
11343                                             (prod_offset + i) * 4;
11344                                         REG_WR(sc, addr, 0);
11345                                 }
11346                                 /* send consumer update with value 0 */
11347                                 bnx2x_ack_sb(sc, sc->igu_base_sb + sb_idx,
11348                                            USTORM_ID, 0, IGU_INT_NOP, 1);
11349                                 bnx2x_igu_clear_sb(sc, sc->igu_base_sb + sb_idx);
11350                         }
11351
11352                         /* default-status-blocks */
11353                         num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11354                             IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
11355
11356                         if (CHIP_IS_MODE_4_PORT(sc))
11357                                 dsb_idx = SC_FUNC(sc);
11358                         else
11359                                 dsb_idx = SC_VN(sc);
11360
11361                         prod_offset = (CHIP_INT_MODE_IS_BC(sc) ?
11362                                        IGU_BC_BASE_DSB_PROD + dsb_idx :
11363                                        IGU_NORM_BASE_DSB_PROD + dsb_idx);
11364
11365                         /*
11366                          * igu prods come in chunks of E1HVN_MAX (4) -
11367                          * does not matters what is the current chip mode
11368                          */
11369                         for (i = 0; i < (num_segs * E1HVN_MAX); i += E1HVN_MAX) {
11370                                 addr = IGU_REG_PROD_CONS_MEMORY +
11371                                     (prod_offset + i) * 4;
11372                                 REG_WR(sc, addr, 0);
11373                         }
11374                         /* send consumer update with 0 */
11375                         if (CHIP_INT_MODE_IS_BC(sc)) {
11376                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11377                                            USTORM_ID, 0, IGU_INT_NOP, 1);
11378                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11379                                            CSTORM_ID, 0, IGU_INT_NOP, 1);
11380                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11381                                            XSTORM_ID, 0, IGU_INT_NOP, 1);
11382                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11383                                            TSTORM_ID, 0, IGU_INT_NOP, 1);
11384                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11385                                            ATTENTION_ID, 0, IGU_INT_NOP, 1);
11386                         } else {
11387                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11388                                            USTORM_ID, 0, IGU_INT_NOP, 1);
11389                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11390                                            ATTENTION_ID, 0, IGU_INT_NOP, 1);
11391                         }
11392                         bnx2x_igu_clear_sb(sc, sc->igu_dsb_id);
11393
11394                         /* !!! these should become driver const once
11395                            rf-tool supports split-68 const */
11396                         REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
11397                         REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
11398                         REG_WR(sc, IGU_REG_SB_MASK_LSB, 0);
11399                         REG_WR(sc, IGU_REG_SB_MASK_MSB, 0);
11400                         REG_WR(sc, IGU_REG_PBA_STATUS_LSB, 0);
11401                         REG_WR(sc, IGU_REG_PBA_STATUS_MSB, 0);
11402                 }
11403         }
11404
11405         /* Reset PCIE errors for debug */
11406         REG_WR(sc, 0x2114, 0xffffffff);
11407         REG_WR(sc, 0x2120, 0xffffffff);
11408
11409         if (CHIP_IS_E1x(sc)) {
11410                 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2;    /*dwords */
11411                 main_mem_base = HC_REG_MAIN_MEMORY +
11412                     SC_PORT(sc) * (main_mem_size * 4);
11413                 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
11414                 main_mem_width = 8;
11415
11416                 val = REG_RD(sc, main_mem_prty_clr);
11417                 if (val) {
11418                         PMD_DRV_LOG(DEBUG, sc,
11419                                     "Parity errors in HC block during function init (0x%x)!",
11420                                     val);
11421                 }
11422
11423 /* Clear "false" parity errors in MSI-X table */
11424                 for (i = main_mem_base;
11425                      i < main_mem_base + main_mem_size * 4;
11426                      i += main_mem_width) {
11427                         bnx2x_read_dmae(sc, i, main_mem_width / 4);
11428                         bnx2x_write_dmae(sc, BNX2X_SP_MAPPING(sc, wb_data),
11429                                        i, main_mem_width / 4);
11430                 }
11431 /* Clear HC parity attention */
11432                 REG_RD(sc, main_mem_prty_clr);
11433         }
11434
11435         /* Enable STORMs SP logging */
11436         REG_WR8(sc, BAR_USTRORM_INTMEM +
11437                 USTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11438         REG_WR8(sc, BAR_TSTRORM_INTMEM +
11439                 TSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11440         REG_WR8(sc, BAR_CSTRORM_INTMEM +
11441                 CSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11442         REG_WR8(sc, BAR_XSTRORM_INTMEM +
11443                 XSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11444
11445         elink_phy_probe(&sc->link_params);
11446
11447         return 0;
11448 }
11449
11450 static void bnx2x_link_reset(struct bnx2x_softc *sc)
11451 {
11452         if (!BNX2X_NOMCP(sc)) {
11453                 bnx2x_acquire_phy_lock(sc);
11454                 elink_lfa_reset(&sc->link_params, &sc->link_vars);
11455                 bnx2x_release_phy_lock(sc);
11456         } else {
11457                 if (!CHIP_REV_IS_SLOW(sc)) {
11458                         PMD_DRV_LOG(WARNING, sc,
11459                                     "Bootcode is missing - cannot reset link");
11460                 }
11461         }
11462 }
11463
11464 static void bnx2x_reset_port(struct bnx2x_softc *sc)
11465 {
11466         int port = SC_PORT(sc);
11467         uint32_t val;
11468
11469         /* reset physical Link */
11470         bnx2x_link_reset(sc);
11471
11472         REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
11473
11474         /* Do not rcv packets to BRB */
11475         REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + port * 4, 0x0);
11476         /* Do not direct rcv packets that are not for MCP to the BRB */
11477         REG_WR(sc, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
11478                     NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
11479
11480         /* Configure AEU */
11481         REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, 0);
11482
11483         DELAY(100000);
11484
11485         /* Check for BRB port occupancy */
11486         val = REG_RD(sc, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port * 4);
11487         if (val) {
11488                 PMD_DRV_LOG(DEBUG, sc,
11489                             "BRB1 is not empty, %d blocks are occupied", val);
11490         }
11491 }
11492
11493 static void bnx2x_ilt_wr(struct bnx2x_softc *sc, uint32_t index, rte_iova_t addr)
11494 {
11495         int reg;
11496         uint32_t wb_write[2];
11497
11498         reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index * 8;
11499
11500         wb_write[0] = ONCHIP_ADDR1(addr);
11501         wb_write[1] = ONCHIP_ADDR2(addr);
11502         REG_WR_DMAE(sc, reg, wb_write, 2);
11503 }
11504
11505 static void bnx2x_clear_func_ilt(struct bnx2x_softc *sc, uint32_t func)
11506 {
11507         uint32_t i, base = FUNC_ILT_BASE(func);
11508         for (i = base; i < base + ILT_PER_FUNC; i++) {
11509                 bnx2x_ilt_wr(sc, i, 0);
11510         }
11511 }
11512
11513 static void bnx2x_reset_func(struct bnx2x_softc *sc)
11514 {
11515         struct bnx2x_fastpath *fp;
11516         int port = SC_PORT(sc);
11517         int func = SC_FUNC(sc);
11518         int i;
11519
11520         /* Disable the function in the FW */
11521         REG_WR8(sc, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
11522         REG_WR8(sc, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
11523         REG_WR8(sc, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
11524         REG_WR8(sc, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
11525
11526         /* FP SBs */
11527         FOR_EACH_ETH_QUEUE(sc, i) {
11528                 fp = &sc->fp[i];
11529                 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11530                         CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
11531                         SB_DISABLED);
11532         }
11533
11534         /* SP SB */
11535         REG_WR8(sc, BAR_CSTRORM_INTMEM +
11536                 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), SB_DISABLED);
11537
11538         for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) {
11539                 REG_WR(sc, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
11540                        0);
11541         }
11542
11543         /* Configure IGU */
11544         if (sc->devinfo.int_block == INT_BLOCK_HC) {
11545                 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11546                 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11547         } else {
11548                 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11549                 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11550         }
11551
11552         if (CNIC_LOADED(sc)) {
11553 /* Disable Timer scan */
11554                 REG_WR(sc, TM_REG_EN_LINEAR0_TIMER + port * 4, 0);
11555 /*
11556  * Wait for at least 10ms and up to 2 second for the timers
11557  * scan to complete
11558  */
11559                 for (i = 0; i < 200; i++) {
11560                         DELAY(10000);
11561                         if (!REG_RD(sc, TM_REG_LIN0_SCAN_ON + port * 4))
11562                                 break;
11563                 }
11564         }
11565
11566         /* Clear ILT */
11567         bnx2x_clear_func_ilt(sc, func);
11568
11569         /*
11570          * Timers workaround bug for E2: if this is vnic-3,
11571          * we need to set the entire ilt range for this timers.
11572          */
11573         if (!CHIP_IS_E1x(sc) && SC_VN(sc) == 3) {
11574                 struct ilt_client_info ilt_cli;
11575 /* use dummy TM client */
11576                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
11577                 ilt_cli.start = 0;
11578                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
11579                 ilt_cli.client_num = ILT_CLIENT_TM;
11580
11581                 ecore_ilt_boundary_init_op(sc, &ilt_cli, 0, INITOP_CLEAR);
11582         }
11583
11584         /* this assumes that reset_port() called before reset_func() */
11585         if (!CHIP_IS_E1x(sc)) {
11586                 bnx2x_pf_disable(sc);
11587         }
11588
11589         sc->dmae_ready = 0;
11590 }
11591
11592 static void bnx2x_release_firmware(struct bnx2x_softc *sc)
11593 {
11594         rte_free(sc->init_ops);
11595         rte_free(sc->init_ops_offsets);
11596         rte_free(sc->init_data);
11597         rte_free(sc->iro_array);
11598 }
11599
11600 static int bnx2x_init_firmware(struct bnx2x_softc *sc)
11601 {
11602         uint32_t len, i;
11603         uint8_t *p = sc->firmware;
11604         uint32_t off[24];
11605
11606         for (i = 0; i < 24; ++i)
11607                 off[i] = rte_be_to_cpu_32(*((uint32_t *) sc->firmware + i));
11608
11609         len = off[0];
11610         sc->init_ops = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11611         if (!sc->init_ops)
11612                 goto alloc_failed;
11613         bnx2x_data_to_init_ops(p + off[1], sc->init_ops, len);
11614
11615         len = off[2];
11616         sc->init_ops_offsets = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11617         if (!sc->init_ops_offsets)
11618                 goto alloc_failed;
11619         bnx2x_data_to_init_offsets(p + off[3], sc->init_ops_offsets, len);
11620
11621         len = off[4];
11622         sc->init_data = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11623         if (!sc->init_data)
11624                 goto alloc_failed;
11625         bnx2x_data_to_init_data(p + off[5], sc->init_data, len);
11626
11627         sc->tsem_int_table_data = p + off[7];
11628         sc->tsem_pram_data = p + off[9];
11629         sc->usem_int_table_data = p + off[11];
11630         sc->usem_pram_data = p + off[13];
11631         sc->csem_int_table_data = p + off[15];
11632         sc->csem_pram_data = p + off[17];
11633         sc->xsem_int_table_data = p + off[19];
11634         sc->xsem_pram_data = p + off[21];
11635
11636         len = off[22];
11637         sc->iro_array = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11638         if (!sc->iro_array)
11639                 goto alloc_failed;
11640         bnx2x_data_to_iro_array(p + off[23], sc->iro_array, len);
11641
11642         return 0;
11643
11644 alloc_failed:
11645         bnx2x_release_firmware(sc);
11646         return -1;
11647 }
11648
11649 static int cut_gzip_prefix(const uint8_t * zbuf, int len)
11650 {
11651 #define MIN_PREFIX_SIZE (10)
11652
11653         int n = MIN_PREFIX_SIZE;
11654         uint16_t xlen;
11655
11656         if (!(zbuf[0] == 0x1f && zbuf[1] == 0x8b && zbuf[2] == Z_DEFLATED) ||
11657             len <= MIN_PREFIX_SIZE) {
11658                 return -1;
11659         }
11660
11661         /* optional extra fields are present */
11662         if (zbuf[3] & 0x4) {
11663                 xlen = zbuf[13];
11664                 xlen <<= 8;
11665                 xlen += zbuf[12];
11666
11667                 n += xlen;
11668         }
11669         /* file name is present */
11670         if (zbuf[3] & 0x8) {
11671                 while ((zbuf[n++] != 0) && (n < len)) ;
11672         }
11673
11674         return n;
11675 }
11676
11677 static int ecore_gunzip(struct bnx2x_softc *sc, const uint8_t * zbuf, int len)
11678 {
11679         int ret;
11680         int data_begin = cut_gzip_prefix(zbuf, len);
11681
11682         PMD_DRV_LOG(DEBUG, sc, "ecore_gunzip %d", len);
11683
11684         if (data_begin <= 0) {
11685                 PMD_DRV_LOG(NOTICE, sc, "bad gzip prefix");
11686                 return -1;
11687         }
11688
11689         memset(&zlib_stream, 0, sizeof(zlib_stream));
11690         zlib_stream.next_in = zbuf + data_begin;
11691         zlib_stream.avail_in = len - data_begin;
11692         zlib_stream.next_out = sc->gz_buf;
11693         zlib_stream.avail_out = FW_BUF_SIZE;
11694
11695         ret = inflateInit2(&zlib_stream, -MAX_WBITS);
11696         if (ret != Z_OK) {
11697                 PMD_DRV_LOG(NOTICE, sc, "zlib inflateInit2 error");
11698                 return ret;
11699         }
11700
11701         ret = inflate(&zlib_stream, Z_FINISH);
11702         if ((ret != Z_STREAM_END) && (ret != Z_OK)) {
11703                 PMD_DRV_LOG(NOTICE, sc, "zlib inflate error: %d %s", ret,
11704                             zlib_stream.msg);
11705         }
11706
11707         sc->gz_outlen = zlib_stream.total_out;
11708         if (sc->gz_outlen & 0x3) {
11709                 PMD_DRV_LOG(NOTICE, sc, "firmware is not aligned. gz_outlen == %d",
11710                             sc->gz_outlen);
11711         }
11712         sc->gz_outlen >>= 2;
11713
11714         inflateEnd(&zlib_stream);
11715
11716         if (ret == Z_STREAM_END)
11717                 return 0;
11718
11719         return ret;
11720 }
11721
11722 static void
11723 ecore_write_dmae_phys_len(struct bnx2x_softc *sc, rte_iova_t phys_addr,
11724                           uint32_t addr, uint32_t len)
11725 {
11726         bnx2x_write_dmae_phys_len(sc, phys_addr, addr, len);
11727 }
11728
11729 void
11730 ecore_storm_memset_struct(struct bnx2x_softc *sc, uint32_t addr, size_t size,
11731                           uint32_t * data)
11732 {
11733         uint8_t i;
11734         for (i = 0; i < size / 4; i++) {
11735                 REG_WR(sc, addr + (i * 4), data[i]);
11736         }
11737 }
11738
11739 static const char *get_ext_phy_type(uint32_t ext_phy_type)
11740 {
11741         uint32_t phy_type_idx = ext_phy_type >> 8;
11742         static const char *types[] =
11743             { "DIRECT", "BNX2X-8071", "BNX2X-8072", "BNX2X-8073",
11744                 "BNX2X-8705", "BNX2X-8706", "BNX2X-8726", "BNX2X-8481", "SFX-7101",
11745                 "BNX2X-8727",
11746                 "BNX2X-8727-NOC", "BNX2X-84823", "NOT_CONN", "FAILURE"
11747         };
11748
11749         if (phy_type_idx < 12)
11750                 return types[phy_type_idx];
11751         else if (PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN == ext_phy_type)
11752                 return types[12];
11753         else
11754                 return types[13];
11755 }
11756
11757 static const char *get_state(uint32_t state)
11758 {
11759         uint32_t state_idx = state >> 12;
11760         static const char *states[] = { "CLOSED", "OPENING_WAIT4_LOAD",
11761                 "OPENING_WAIT4_PORT", "OPEN", "CLOSING_WAIT4_HALT",
11762                 "CLOSING_WAIT4_DELETE", "CLOSING_WAIT4_UNLOAD",
11763                 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
11764                 "UNKNOWN", "DISABLED", "DIAG", "ERROR", "UNDEFINED"
11765         };
11766
11767         if (state_idx <= 0xF)
11768                 return states[state_idx];
11769         else
11770                 return states[0x10];
11771 }
11772
11773 static const char *get_recovery_state(uint32_t state)
11774 {
11775         static const char *states[] = { "NONE", "DONE", "INIT",
11776                 "WAIT", "FAILED", "NIC_LOADING"
11777         };
11778         return states[state];
11779 }
11780
11781 static const char *get_rx_mode(uint32_t mode)
11782 {
11783         static const char *modes[] = { "NONE", "NORMAL", "ALLMULTI",
11784                 "PROMISC", "MAX_MULTICAST", "ERROR"
11785         };
11786
11787         if (mode < 0x4)
11788                 return modes[mode];
11789         else if (BNX2X_MAX_MULTICAST == mode)
11790                 return modes[4];
11791         else
11792                 return modes[5];
11793 }
11794
11795 #define BNX2X_INFO_STR_MAX 256
11796 static const char *get_bnx2x_flags(uint32_t flags)
11797 {
11798         int i;
11799         static const char *flag[] = { "ONE_PORT ", "NO_ISCSI ",
11800                 "NO_FCOE ", "NO_WOL ", "USING_DAC ", "USING_MSIX ",
11801                 "USING_MSI ", "DISABLE_MSI ", "UNKNOWN ", "NO_MCP ",
11802                 "SAFC_TX_FLAG ", "MF_FUNC_DIS ", "TX_SWITCHING "
11803         };
11804         static char flag_str[BNX2X_INFO_STR_MAX];
11805         memset(flag_str, 0, BNX2X_INFO_STR_MAX);
11806
11807         for (i = 0; i < 5; i++)
11808                 if (flags & (1 << i)) {
11809                         strlcat(flag_str, flag[i], sizeof(flag_str));
11810                         flags ^= (1 << i);
11811                 }
11812         if (flags) {
11813                 static char unknown[BNX2X_INFO_STR_MAX];
11814                 snprintf(unknown, 32, "Unknown flag mask %x", flags);
11815                 strlcat(flag_str, unknown, sizeof(flag_str));
11816         }
11817         return flag_str;
11818 }
11819
11820 /* Prints useful adapter info. */
11821 void bnx2x_print_adapter_info(struct bnx2x_softc *sc)
11822 {
11823         int i = 0;
11824
11825         PMD_DRV_LOG(INFO, sc, "========================================");
11826         /* DPDK and Driver versions */
11827         PMD_DRV_LOG(INFO, sc, "%12s : %s", "DPDK",
11828                         rte_version());
11829         PMD_DRV_LOG(INFO, sc, "%12s : %s", "Driver",
11830                         bnx2x_pmd_version());
11831         /* Firmware versions. */
11832         PMD_DRV_LOG(INFO, sc, "%12s : %d.%d.%d",
11833                      "Firmware",
11834                      BNX2X_5710_FW_MAJOR_VERSION,
11835                      BNX2X_5710_FW_MINOR_VERSION,
11836                      BNX2X_5710_FW_REVISION_VERSION);
11837         PMD_DRV_LOG(INFO, sc, "%12s : %s",
11838                      "Bootcode", sc->devinfo.bc_ver_str);
11839         /* Hardware chip info. */
11840         PMD_DRV_LOG(INFO, sc, "%12s : %#08x", "ASIC", sc->devinfo.chip_id);
11841         PMD_DRV_LOG(INFO, sc, "%12s : %c%d", "Rev", (CHIP_REV(sc) >> 12) + 'A',
11842                      (CHIP_METAL(sc) >> 4));
11843         /* Bus PCIe info. */
11844         PMD_DRV_LOG(INFO, sc, "%12s : 0x%x", "Vendor Id",
11845                     sc->devinfo.vendor_id);
11846         PMD_DRV_LOG(INFO, sc, "%12s : 0x%x", "Device Id",
11847                     sc->devinfo.device_id);
11848         PMD_DRV_LOG(INFO, sc, "%12s : width x%d, ", "Bus PCIe",
11849                     sc->devinfo.pcie_link_width);
11850         switch (sc->devinfo.pcie_link_speed) {
11851         case 1:
11852                 PMD_DRV_LOG(INFO, sc, "%23s", "2.5 Gbps");
11853                 break;
11854         case 2:
11855                 PMD_DRV_LOG(INFO, sc, "%21s", "5 Gbps");
11856                 break;
11857         case 4:
11858                 PMD_DRV_LOG(INFO, sc, "%21s", "8 Gbps");
11859                 break;
11860         default:
11861                 PMD_DRV_LOG(INFO, sc, "%33s", "Unknown link speed");
11862         }
11863         /* Device features. */
11864         PMD_DRV_LOG(INFO, sc, "%12s : ", "Flags");
11865         /* Miscellaneous flags. */
11866         if (sc->devinfo.pcie_cap_flags & BNX2X_MSI_CAPABLE_FLAG) {
11867                 PMD_DRV_LOG(INFO, sc, "%18s", "MSI");
11868                 i++;
11869         }
11870         if (sc->devinfo.pcie_cap_flags & BNX2X_MSIX_CAPABLE_FLAG) {
11871                 if (i > 0)
11872                         PMD_DRV_LOG(INFO, sc, "|");
11873                 PMD_DRV_LOG(INFO, sc, "%20s", "MSI-X");
11874                 i++;
11875         }
11876         PMD_DRV_LOG(INFO, sc, "%12s : %s", "OVLAN", (OVLAN(sc) ? "YES" : "NO"));
11877         PMD_DRV_LOG(INFO, sc, "%12s : %s", "MF", (IS_MF(sc) ? "YES" : "NO"));
11878         PMD_DRV_LOG(INFO, sc, "========================================");
11879 }
11880
11881 /* Prints useful device info. */
11882 void bnx2x_print_device_info(struct bnx2x_softc *sc)
11883 {
11884         __rte_unused uint32_t ext_phy_type;
11885         uint32_t offset, reg_val;
11886
11887         PMD_INIT_FUNC_TRACE(sc);
11888         offset = offsetof(struct shmem_region,
11889                           dev_info.port_hw_config[0].external_phy_config);
11890         reg_val = REG_RD(sc, sc->devinfo.shmem_base + offset);
11891         if (sc->link_vars.phy_flags & PHY_XGXS_FLAG)
11892                 ext_phy_type = ELINK_XGXS_EXT_PHY_TYPE(reg_val);
11893         else
11894                 ext_phy_type = ELINK_SERDES_EXT_PHY_TYPE(reg_val);
11895
11896         /* Device features. */
11897         PMD_DRV_LOG(INFO, sc, "%12s : %u", "Bnx2x Func", sc->pcie_func);
11898         PMD_DRV_LOG(INFO, sc,
11899                     "%12s : %s", "Bnx2x Flags", get_bnx2x_flags(sc->flags));
11900         PMD_DRV_LOG(INFO, sc, "%12s : %s", "DMAE Is",
11901                      (sc->dmae_ready ? "Ready" : "Not Ready"));
11902         PMD_DRV_LOG(INFO, sc, "%12s : %u", "MTU", sc->mtu);
11903         PMD_DRV_LOG(INFO, sc,
11904                     "%12s : %s", "PHY Type", get_ext_phy_type(ext_phy_type));
11905         PMD_DRV_LOG(INFO, sc, "%12s : %x:%x:%x:%x:%x:%x", "MAC Addr",
11906                         sc->link_params.mac_addr[0],
11907                         sc->link_params.mac_addr[1],
11908                         sc->link_params.mac_addr[2],
11909                         sc->link_params.mac_addr[3],
11910                         sc->link_params.mac_addr[4],
11911                         sc->link_params.mac_addr[5]);
11912         PMD_DRV_LOG(INFO, sc, "%12s : %s", "RX Mode", get_rx_mode(sc->rx_mode));
11913         PMD_DRV_LOG(INFO, sc, "%12s : %s", "State", get_state(sc->state));
11914         if (sc->recovery_state)
11915                 PMD_DRV_LOG(INFO, sc, "%12s : %s", "Recovery",
11916                              get_recovery_state(sc->recovery_state));
11917         /* Queue info. */
11918         if (IS_PF(sc)) {
11919                 switch (sc->sp->rss_rdata.rss_mode) {
11920                 case ETH_RSS_MODE_DISABLED:
11921                         PMD_DRV_LOG(INFO, sc, "%12s : %s", "Queues", "RSS mode - None");
11922                         break;
11923                 case ETH_RSS_MODE_REGULAR:
11924                         PMD_DRV_LOG(INFO, sc, "%12s : %s,", "Queues", "RSS mode - Regular");
11925                         PMD_DRV_LOG(INFO, sc, "%16d", sc->num_queues);
11926                         break;
11927                 default:
11928                         PMD_DRV_LOG(INFO, sc, "%12s : %s", "Queues", "RSS mode - Unknown");
11929                         break;
11930                 }
11931         }
11932         PMD_DRV_LOG(INFO, sc, "%12s : CQ = %lx,  EQ = %lx", "SPQ Left",
11933                      sc->cq_spq_left, sc->eq_spq_left);
11934
11935         PMD_DRV_LOG(INFO, sc,
11936                     "%12s : %x", "Switch", sc->link_params.switch_cfg);
11937         PMD_DRV_LOG(INFO, sc, "pcie_bus=%d, pcie_device=%d",
11938                         sc->pcie_bus, sc->pcie_device);
11939         PMD_DRV_LOG(INFO, sc, "bar0.addr=%p, bar1.addr=%p",
11940                         sc->bar[BAR0].base_addr, sc->bar[BAR1].base_addr);
11941         PMD_DRV_LOG(INFO, sc, "port=%d, path=%d, vnic=%d, func=%d",
11942                         PORT_ID(sc), PATH_ID(sc), VNIC_ID(sc), FUNC_ID(sc));
11943 }