2 * Copyright (c) 2007-2013 Broadcom Corporation.
4 * Eric Davis <edavis@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
6 * Gary Zambrano <zambrano@broadcom.com>
8 * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
9 * Copyright (c) 2015 QLogic Corporation.
10 * All rights reserved.
13 * See LICENSE.bnx2x_pmd for copyright and licensing details.
16 #define BNX2X_DRIVER_VERSION "1.78.18"
19 #include "bnx2x_vfpf.h"
21 #include "ecore_init.h"
22 #include "ecore_init_ops.h"
24 #include "rte_pci_dev_ids.h"
26 #include <sys/types.h>
31 static z_stream zlib_stream;
33 #define EVL_VLID_MASK 0x0FFF
35 #define BNX2X_DEF_SB_ATT_IDX 0x0001
36 #define BNX2X_DEF_SB_IDX 0x0002
39 * FLR Support - bnx2x_pf_flr_clnup() is called during nic_load in the per
40 * function HW initialization.
42 #define FLR_WAIT_USEC 10000 /* 10 msecs */
43 #define FLR_WAIT_INTERVAL 50 /* usecs */
44 #define FLR_POLL_CNT (FLR_WAIT_USEC / FLR_WAIT_INTERVAL) /* 200 */
46 struct pbf_pN_buf_regs {
53 struct pbf_pN_cmd_regs {
59 /* resources needed for unloading a previously loaded device */
61 #define BNX2X_PREV_WAIT_NEEDED 1
62 rte_spinlock_t bnx2x_prev_mtx;
63 struct bnx2x_prev_list_node {
64 LIST_ENTRY(bnx2x_prev_list_node) node;
72 static LIST_HEAD(, bnx2x_prev_list_node) bnx2x_prev_list
73 = LIST_HEAD_INITIALIZER(bnx2x_prev_list);
75 static int load_count[2][3] = { { 0 } };
76 /* per-path: 0-common, 1-port0, 2-port1 */
78 static void bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg,
80 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc);
81 static void storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng,
83 static void bnx2x_set_reset_global(struct bnx2x_softc *sc);
84 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc);
85 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine);
86 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc);
87 static uint8_t bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global,
89 static void bnx2x_int_disable(struct bnx2x_softc *sc);
90 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc);
91 static void bnx2x_pf_disable(struct bnx2x_softc *sc);
92 static void bnx2x_update_rx_prod(struct bnx2x_softc *sc,
93 struct bnx2x_fastpath *fp,
94 uint16_t rx_bd_prod, uint16_t rx_cq_prod);
95 static void bnx2x_link_report(struct bnx2x_softc *sc);
96 void bnx2x_link_status_update(struct bnx2x_softc *sc);
97 static int bnx2x_alloc_mem(struct bnx2x_softc *sc);
98 static void bnx2x_free_mem(struct bnx2x_softc *sc);
99 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc);
100 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc);
101 static __attribute__ ((noinline))
102 int bnx2x_nic_load(struct bnx2x_softc *sc);
104 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc);
105 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp, int scan_fp);
106 static void bnx2x_periodic_stop(struct bnx2x_softc *sc);
107 static void bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id,
108 uint8_t storm, uint16_t index, uint8_t op,
111 int bnx2x_test_bit(int nr, volatile unsigned long *addr)
116 res = ((*addr) & (1UL << nr)) != 0;
121 void bnx2x_set_bit(unsigned int nr, volatile unsigned long *addr)
123 __sync_fetch_and_or(addr, (1UL << nr));
126 void bnx2x_clear_bit(int nr, volatile unsigned long *addr)
128 __sync_fetch_and_and(addr, ~(1UL << nr));
131 int bnx2x_test_and_clear_bit(int nr, volatile unsigned long *addr)
133 unsigned long mask = (1UL << nr);
134 return __sync_fetch_and_and(addr, ~mask) & mask;
137 int bnx2x_cmpxchg(volatile int *addr, int old, int new)
139 return __sync_val_compare_and_swap(addr, old, new);
143 bnx2x_dma_alloc(struct bnx2x_softc *sc, size_t size, struct bnx2x_dma *dma,
144 const char *msg, uint32_t align)
146 char mz_name[RTE_MEMZONE_NAMESIZE];
147 const struct rte_memzone *z;
151 sprintf(mz_name, "bnx2x%d_%s_%" PRIx64, SC_ABS_FUNC(sc), msg,
152 rte_get_timer_cycles());
154 sprintf(mz_name, "bnx2x%d_%s_%" PRIx64, sc->pcie_device, msg,
155 rte_get_timer_cycles());
157 /* Caller must take care that strlen(mz_name) < RTE_MEMZONE_NAMESIZE */
158 z = rte_memzone_reserve_aligned(mz_name, (uint64_t) (size),
159 rte_lcore_to_socket_id(rte_lcore_id()),
162 PMD_DRV_LOG(ERR, "DMA alloc failed for %s", msg);
165 dma->paddr = (uint64_t) z->phys_addr;
166 dma->vaddr = z->addr;
168 PMD_DRV_LOG(DEBUG, "%s: virt=%p phys=%" PRIx64, msg, dma->vaddr, dma->paddr);
173 static int bnx2x_acquire_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
175 uint32_t lock_status;
176 uint32_t resource_bit = (1 << resource);
177 int func = SC_FUNC(sc);
178 uint32_t hw_lock_control_reg;
181 PMD_INIT_FUNC_TRACE();
183 /* validate the resource is within range */
184 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
186 "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
192 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
194 hw_lock_control_reg =
195 (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
198 /* validate the resource is not already taken */
199 lock_status = REG_RD(sc, hw_lock_control_reg);
200 if (lock_status & resource_bit) {
202 "resource in use (status 0x%x bit 0x%x)",
203 lock_status, resource_bit);
207 /* try every 5ms for 5 seconds */
208 for (cnt = 0; cnt < 1000; cnt++) {
209 REG_WR(sc, (hw_lock_control_reg + 4), resource_bit);
210 lock_status = REG_RD(sc, hw_lock_control_reg);
211 if (lock_status & resource_bit) {
217 PMD_DRV_LOG(NOTICE, "Resource lock timeout!");
221 static int bnx2x_release_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
223 uint32_t lock_status;
224 uint32_t resource_bit = (1 << resource);
225 int func = SC_FUNC(sc);
226 uint32_t hw_lock_control_reg;
228 PMD_INIT_FUNC_TRACE();
230 /* validate the resource is within range */
231 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
233 "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
239 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
241 hw_lock_control_reg =
242 (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
245 /* validate the resource is currently taken */
246 lock_status = REG_RD(sc, hw_lock_control_reg);
247 if (!(lock_status & resource_bit)) {
249 "resource not in use (status 0x%x bit 0x%x)",
250 lock_status, resource_bit);
254 REG_WR(sc, hw_lock_control_reg, resource_bit);
258 /* copy command into DMAE command memory and set DMAE command Go */
259 void bnx2x_post_dmae(struct bnx2x_softc *sc, struct dmae_command *dmae, int idx)
264 cmd_offset = (DMAE_REG_CMD_MEM + (sizeof(struct dmae_command) * idx));
265 for (i = 0; i < ((sizeof(struct dmae_command) / 4)); i++) {
266 REG_WR(sc, (cmd_offset + (i * 4)), *(((uint32_t *) dmae) + i));
269 REG_WR(sc, dmae_reg_go_c[idx], 1);
272 uint32_t bnx2x_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type)
274 return (opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
275 DMAE_COMMAND_C_TYPE_ENABLE));
278 uint32_t bnx2x_dmae_opcode_clr_src_reset(uint32_t opcode)
280 return (opcode & ~DMAE_COMMAND_SRC_RESET);
284 bnx2x_dmae_opcode(struct bnx2x_softc * sc, uint8_t src_type, uint8_t dst_type,
285 uint8_t with_comp, uint8_t comp_type)
289 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
290 (dst_type << DMAE_COMMAND_DST_SHIFT));
292 opcode |= (DMAE_COMMAND_SRC_RESET | DMAE_COMMAND_DST_RESET);
294 opcode |= (SC_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
296 opcode |= ((SC_VN(sc) << DMAE_COMMAND_E1HVN_SHIFT) |
297 (SC_VN(sc) << DMAE_COMMAND_DST_VN_SHIFT));
299 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
302 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
304 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
308 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
315 bnx2x_prep_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae,
316 uint8_t src_type, uint8_t dst_type)
318 memset(dmae, 0, sizeof(struct dmae_command));
321 dmae->opcode = bnx2x_dmae_opcode(sc, src_type, dst_type,
322 TRUE, DMAE_COMP_PCI);
324 /* fill in the completion parameters */
325 dmae->comp_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_comp));
326 dmae->comp_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_comp));
327 dmae->comp_val = DMAE_COMP_VAL;
330 /* issue a DMAE command over the init channel and wait for completion */
332 bnx2x_issue_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae)
334 uint32_t *wb_comp = BNX2X_SP(sc, wb_comp);
335 int timeout = CHIP_REV_IS_SLOW(sc) ? 400000 : 4000;
337 /* reset completion */
340 /* post the command on the channel used for initializations */
341 bnx2x_post_dmae(sc, dmae, INIT_DMAE_C(sc));
343 /* wait for completion */
346 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
348 (sc->recovery_state != BNX2X_RECOVERY_DONE &&
349 sc->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
350 PMD_DRV_LOG(INFO, "DMAE timeout!");
358 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
359 PMD_DRV_LOG(INFO, "DMAE PCI error!");
360 return DMAE_PCI_ERROR;
366 void bnx2x_read_dmae(struct bnx2x_softc *sc, uint32_t src_addr, uint32_t len32)
368 struct dmae_command dmae;
373 if (!sc->dmae_ready) {
374 data = BNX2X_SP(sc, wb_data[0]);
376 for (i = 0; i < len32; i++) {
377 data[i] = REG_RD(sc, (src_addr + (i * 4)));
383 /* set opcode and fixed command fields */
384 bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
386 /* fill in addresses and len */
387 dmae.src_addr_lo = (src_addr >> 2); /* GRC addr has dword resolution */
388 dmae.src_addr_hi = 0;
389 dmae.dst_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_data));
390 dmae.dst_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_data));
393 /* issue the command and wait for completion */
394 if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
395 rte_panic("DMAE failed (%d)", rc);
400 bnx2x_write_dmae(struct bnx2x_softc *sc, phys_addr_t dma_addr, uint32_t dst_addr,
403 struct dmae_command dmae;
406 if (!sc->dmae_ready) {
407 ecore_init_str_wr(sc, dst_addr, BNX2X_SP(sc, wb_data[0]), len32);
411 /* set opcode and fixed command fields */
412 bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
414 /* fill in addresses and len */
415 dmae.src_addr_lo = U64_LO(dma_addr);
416 dmae.src_addr_hi = U64_HI(dma_addr);
417 dmae.dst_addr_lo = (dst_addr >> 2); /* GRC addr has dword resolution */
418 dmae.dst_addr_hi = 0;
421 /* issue the command and wait for completion */
422 if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
423 rte_panic("DMAE failed (%d)", rc);
428 bnx2x_write_dmae_phys_len(struct bnx2x_softc *sc, phys_addr_t phys_addr,
429 uint32_t addr, uint32_t len)
431 uint32_t dmae_wr_max = DMAE_LEN32_WR_MAX(sc);
434 while (len > dmae_wr_max) {
435 bnx2x_write_dmae(sc, (phys_addr + offset), /* src DMA address */
436 (addr + offset), /* dst GRC address */
438 offset += (dmae_wr_max * 4);
442 bnx2x_write_dmae(sc, (phys_addr + offset), /* src DMA address */
443 (addr + offset), /* dst GRC address */
448 bnx2x_set_ctx_validation(struct bnx2x_softc *sc, struct eth_context *cxt,
451 /* ustorm cxt validation */
452 cxt->ustorm_ag_context.cdu_usage =
453 CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
454 CDU_REGION_NUMBER_UCM_AG,
455 ETH_CONNECTION_TYPE);
456 /* xcontext validation */
457 cxt->xstorm_ag_context.cdu_reserved =
458 CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
459 CDU_REGION_NUMBER_XCM_AG,
460 ETH_CONNECTION_TYPE);
464 bnx2x_storm_memset_hc_timeout(struct bnx2x_softc *sc, uint8_t fw_sb_id,
465 uint8_t sb_index, uint8_t ticks)
468 (BAR_CSTRORM_INTMEM +
469 CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(fw_sb_id, sb_index));
471 REG_WR8(sc, addr, ticks);
475 bnx2x_storm_memset_hc_disable(struct bnx2x_softc *sc, uint16_t fw_sb_id,
476 uint8_t sb_index, uint8_t disable)
478 uint32_t enable_flag =
479 (disable) ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
481 (BAR_CSTRORM_INTMEM +
482 CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(fw_sb_id, sb_index));
486 flags = REG_RD8(sc, addr);
487 flags &= ~HC_INDEX_DATA_HC_ENABLED;
488 flags |= enable_flag;
489 REG_WR8(sc, addr, flags);
493 bnx2x_update_coalesce_sb_index(struct bnx2x_softc *sc, uint8_t fw_sb_id,
494 uint8_t sb_index, uint8_t disable, uint16_t usec)
496 uint8_t ticks = (usec / 4);
498 bnx2x_storm_memset_hc_timeout(sc, fw_sb_id, sb_index, ticks);
500 disable = (disable) ? 1 : ((usec) ? 0 : 1);
501 bnx2x_storm_memset_hc_disable(sc, fw_sb_id, sb_index, disable);
504 uint32_t elink_cb_reg_read(struct bnx2x_softc *sc, uint32_t reg_addr)
506 return REG_RD(sc, reg_addr);
509 void elink_cb_reg_write(struct bnx2x_softc *sc, uint32_t reg_addr, uint32_t val)
511 REG_WR(sc, reg_addr, val);
515 elink_cb_event_log(__rte_unused struct bnx2x_softc *sc,
516 __rte_unused const elink_log_id_t elink_log_id, ...)
518 PMD_DRV_LOG(DEBUG, "ELINK EVENT LOG (%d)", elink_log_id);
521 static int bnx2x_set_spio(struct bnx2x_softc *sc, int spio, uint32_t mode)
525 /* Only 2 SPIOs are configurable */
526 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
527 PMD_DRV_LOG(NOTICE, "Invalid SPIO 0x%x", spio);
531 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
533 /* read SPIO and mask except the float bits */
534 spio_reg = (REG_RD(sc, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
537 case MISC_SPIO_OUTPUT_LOW:
538 /* clear FLOAT and set CLR */
539 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
540 spio_reg |= (spio << MISC_SPIO_CLR_POS);
543 case MISC_SPIO_OUTPUT_HIGH:
544 /* clear FLOAT and set SET */
545 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
546 spio_reg |= (spio << MISC_SPIO_SET_POS);
549 case MISC_SPIO_INPUT_HI_Z:
551 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
558 REG_WR(sc, MISC_REG_SPIO, spio_reg);
559 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
564 static int bnx2x_gpio_read(struct bnx2x_softc *sc, int gpio_num, uint8_t port)
566 /* The GPIO should be swapped if swap register is set and active */
567 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
568 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
569 int gpio_shift = gpio_num;
571 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
573 uint32_t gpio_mask = (1 << gpio_shift);
576 if (gpio_num > MISC_REGISTERS_GPIO_3) {
577 PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
581 /* read GPIO value */
582 gpio_reg = REG_RD(sc, MISC_REG_GPIO);
584 /* get the requested pin value */
585 return ((gpio_reg & gpio_mask) == gpio_mask) ? 1 : 0;
589 bnx2x_gpio_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode, uint8_t port)
591 /* The GPIO should be swapped if swap register is set and active */
592 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
593 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
594 int gpio_shift = gpio_num;
596 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
598 uint32_t gpio_mask = (1 << gpio_shift);
601 if (gpio_num > MISC_REGISTERS_GPIO_3) {
602 PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
606 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
608 /* read GPIO and mask except the float bits */
609 gpio_reg = (REG_RD(sc, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
612 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
613 /* clear FLOAT and set CLR */
614 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
615 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
618 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
619 /* clear FLOAT and set SET */
620 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
621 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
624 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
626 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
633 REG_WR(sc, MISC_REG_GPIO, gpio_reg);
634 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
640 bnx2x_gpio_mult_write(struct bnx2x_softc *sc, uint8_t pins, uint32_t mode)
644 /* any port swapping should be handled by caller */
646 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
648 /* read GPIO and mask except the float bits */
649 gpio_reg = REG_RD(sc, MISC_REG_GPIO);
650 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
651 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
652 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
655 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
657 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
660 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
662 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
665 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
667 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
671 PMD_DRV_LOG(NOTICE, "Invalid GPIO mode assignment %d", mode);
672 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
676 REG_WR(sc, MISC_REG_GPIO, gpio_reg);
677 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
683 bnx2x_gpio_int_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode,
686 /* The GPIO should be swapped if swap register is set and active */
687 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
688 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
689 int gpio_shift = gpio_num;
691 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
693 uint32_t gpio_mask = (1 << gpio_shift);
696 if (gpio_num > MISC_REGISTERS_GPIO_3) {
697 PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
701 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
704 gpio_reg = REG_RD(sc, MISC_REG_GPIO_INT);
707 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
708 /* clear SET and set CLR */
709 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
710 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
713 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
714 /* clear CLR and set SET */
715 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
716 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
723 REG_WR(sc, MISC_REG_GPIO_INT, gpio_reg);
724 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
730 elink_cb_gpio_read(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t port)
732 return bnx2x_gpio_read(sc, gpio_num, port);
735 uint8_t elink_cb_gpio_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode, /* 0=low 1=high */
738 return bnx2x_gpio_write(sc, gpio_num, mode, port);
742 elink_cb_gpio_mult_write(struct bnx2x_softc * sc, uint8_t pins,
743 uint8_t mode /* 0=low 1=high */ )
745 return bnx2x_gpio_mult_write(sc, pins, mode);
748 uint8_t elink_cb_gpio_int_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode, /* 0=low 1=high */
751 return bnx2x_gpio_int_write(sc, gpio_num, mode, port);
754 void elink_cb_notify_link_changed(struct bnx2x_softc *sc)
756 REG_WR(sc, (MISC_REG_AEU_GENERAL_ATTN_12 +
757 (SC_FUNC(sc) * sizeof(uint32_t))), 1);
760 /* send the MCP a request, block until there is a reply */
762 elink_cb_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
764 int mb_idx = SC_FW_MB_IDX(sc);
768 uint8_t delay = CHIP_REV_IS_SLOW(sc) ? 100 : 10;
771 SHMEM_WR(sc, func_mb[mb_idx].drv_mb_param, param);
772 SHMEM_WR(sc, func_mb[mb_idx].drv_mb_header, (command | seq));
775 "wrote command 0x%08x to FW MB param 0x%08x",
776 (command | seq), param);
778 /* Let the FW do it's magic. GIve it up to 5 seconds... */
781 rc = SHMEM_RD(sc, func_mb[mb_idx].fw_mb_header);
782 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
784 /* is this a reply to our command? */
785 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) {
786 rc &= FW_MSG_CODE_MASK;
789 PMD_DRV_LOG(NOTICE, "FW failed to respond!");
797 bnx2x_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
799 return elink_cb_fw_command(sc, command, param);
803 __storm_memset_dma_mapping(struct bnx2x_softc *sc, uint32_t addr,
806 REG_WR(sc, addr, U64_LO(mapping));
807 REG_WR(sc, (addr + 4), U64_HI(mapping));
811 storm_memset_spq_addr(struct bnx2x_softc *sc, phys_addr_t mapping,
814 uint32_t addr = (XSEM_REG_FAST_MEMORY +
815 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid));
816 __storm_memset_dma_mapping(sc, addr, mapping);
820 storm_memset_vf_to_pf(struct bnx2x_softc *sc, uint16_t abs_fid, uint16_t pf_id)
822 REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid)),
824 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid)),
826 REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid)),
828 REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid)),
833 storm_memset_func_en(struct bnx2x_softc *sc, uint16_t abs_fid, uint8_t enable)
835 REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid)),
837 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid)),
839 REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid)),
841 REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid)),
846 storm_memset_eq_data(struct bnx2x_softc *sc, struct event_ring_data *eq_data,
852 addr = (BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid));
853 size = sizeof(struct event_ring_data);
854 ecore_storm_memset_struct(sc, addr, size, (uint32_t *) eq_data);
858 storm_memset_eq_prod(struct bnx2x_softc *sc, uint16_t eq_prod, uint16_t pfid)
860 uint32_t addr = (BAR_CSTRORM_INTMEM +
861 CSTORM_EVENT_RING_PROD_OFFSET(pfid));
862 REG_WR16(sc, addr, eq_prod);
866 * Post a slowpath command.
868 * A slowpath command is used to propogate a configuration change through
869 * the controller in a controlled manner, allowing each STORM processor and
870 * other H/W blocks to phase in the change. The commands sent on the
871 * slowpath are referred to as ramrods. Depending on the ramrod used the
872 * completion of the ramrod will occur in different ways. Here's a
873 * breakdown of ramrods and how they complete:
875 * RAMROD_CMD_ID_ETH_PORT_SETUP
876 * Used to setup the leading connection on a port. Completes on the
877 * Receive Completion Queue (RCQ) of that port (typically fp[0]).
879 * RAMROD_CMD_ID_ETH_CLIENT_SETUP
880 * Used to setup an additional connection on a port. Completes on the
881 * RCQ of the multi-queue/RSS connection being initialized.
883 * RAMROD_CMD_ID_ETH_STAT_QUERY
884 * Used to force the storm processors to update the statistics database
885 * in host memory. This ramrod is send on the leading connection CID and
886 * completes as an index increment of the CSTORM on the default status
889 * RAMROD_CMD_ID_ETH_UPDATE
890 * Used to update the state of the leading connection, usually to udpate
891 * the RSS indirection table. Completes on the RCQ of the leading
892 * connection. (Not currently used under FreeBSD until OS support becomes
895 * RAMROD_CMD_ID_ETH_HALT
896 * Used when tearing down a connection prior to driver unload. Completes
897 * on the RCQ of the multi-queue/RSS connection being torn down. Don't
898 * use this on the leading connection.
900 * RAMROD_CMD_ID_ETH_SET_MAC
901 * Sets the Unicast/Broadcast/Multicast used by the port. Completes on
902 * the RCQ of the leading connection.
904 * RAMROD_CMD_ID_ETH_CFC_DEL
905 * Used when tearing down a conneciton prior to driver unload. Completes
906 * on the RCQ of the leading connection (since the current connection
907 * has been completely removed from controller memory).
909 * RAMROD_CMD_ID_ETH_PORT_DEL
910 * Used to tear down the leading connection prior to driver unload,
911 * typically fp[0]. Completes as an index increment of the CSTORM on the
912 * default status block.
914 * RAMROD_CMD_ID_ETH_FORWARD_SETUP
915 * Used for connection offload. Completes on the RCQ of the multi-queue
916 * RSS connection that is being offloaded. (Not currently used under
919 * There can only be one command pending per function.
922 * 0 = Success, !0 = Failure.
925 /* must be called under the spq lock */
926 static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x_softc *sc)
928 struct eth_spe *next_spe = sc->spq_prod_bd;
930 if (sc->spq_prod_bd == sc->spq_last_bd) {
931 /* wrap back to the first eth_spq */
932 sc->spq_prod_bd = sc->spq;
933 sc->spq_prod_idx = 0;
942 /* must be called under the spq lock */
943 static void bnx2x_sp_prod_update(struct bnx2x_softc *sc)
945 int func = SC_FUNC(sc);
948 * Make sure that BD data is updated before writing the producer.
949 * BD data is written to the memory, the producer is read from the
950 * memory, thus we need a full memory barrier to ensure the ordering.
954 REG_WR16(sc, (BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func)),
961 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
963 * @cmd: command to check
964 * @cmd_type: command type
966 static int bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
968 if ((cmd_type == NONE_CONNECTION_TYPE) ||
969 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
970 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
971 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
972 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
973 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
974 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) {
982 * bnx2x_sp_post - place a single command on an SP ring
985 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
986 * @cid: SW CID the command is related to
987 * @data_hi: command private data address (high 32 bits)
988 * @data_lo: command private data address (low 32 bits)
989 * @cmd_type: command type (e.g. NONE, ETH)
991 * SP data is handled as if it's always an address pair, thus data fields are
992 * not swapped to little endian in upper functions. Instead this function swaps
993 * data as if it's two uint32 fields.
996 bnx2x_sp_post(struct bnx2x_softc *sc, int command, int cid, uint32_t data_hi,
997 uint32_t data_lo, int cmd_type)
1003 common = bnx2x_is_contextless_ramrod(command, cmd_type);
1006 if (!atomic_load_acq_long(&sc->eq_spq_left)) {
1007 PMD_DRV_LOG(INFO, "EQ ring is full!");
1011 if (!atomic_load_acq_long(&sc->cq_spq_left)) {
1012 PMD_DRV_LOG(INFO, "SPQ ring is full!");
1017 spe = bnx2x_sp_get_next(sc);
1019 /* CID needs port number to be encoded int it */
1020 spe->hdr.conn_and_cmd_data =
1021 htole32((command << SPE_HDR_CMD_ID_SHIFT) | HW_CID(sc, cid));
1023 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
1025 /* TBD: Check if it works for VFs */
1026 type |= ((SC_FUNC(sc) << SPE_HDR_FUNCTION_ID_SHIFT) &
1027 SPE_HDR_FUNCTION_ID);
1029 spe->hdr.type = htole16(type);
1031 spe->data.update_data_addr.hi = htole32(data_hi);
1032 spe->data.update_data_addr.lo = htole32(data_lo);
1035 * It's ok if the actual decrement is issued towards the memory
1036 * somewhere between the lock and unlock. Thus no more explict
1037 * memory barrier is needed.
1040 atomic_subtract_acq_long(&sc->eq_spq_left, 1);
1042 atomic_subtract_acq_long(&sc->cq_spq_left, 1);
1046 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x"
1047 "data (%x:%x) type(0x%x) left (CQ, EQ) (%lx,%lx)",
1049 (uint32_t) U64_HI(sc->spq_dma.paddr),
1050 (uint32_t) (U64_LO(sc->spq_dma.paddr) +
1051 (uint8_t *) sc->spq_prod_bd -
1052 (uint8_t *) sc->spq), command, common,
1053 HW_CID(sc, cid), data_hi, data_lo, type,
1054 atomic_load_acq_long(&sc->cq_spq_left),
1055 atomic_load_acq_long(&sc->eq_spq_left));
1057 bnx2x_sp_prod_update(sc);
1062 static void bnx2x_drv_pulse(struct bnx2x_softc *sc)
1064 SHMEM_WR(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb,
1065 sc->fw_drv_pulse_wr_seq);
1068 static int bnx2x_tx_queue_has_work(const struct bnx2x_fastpath *fp)
1071 struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1073 if (unlikely(!txq)) {
1074 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1078 mb(); /* status block fields can change */
1079 hw_cons = le16toh(*fp->tx_cons_sb);
1080 return (hw_cons != txq->tx_pkt_head);
1083 static uint8_t bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
1085 /* expand this for multi-cos if ever supported */
1086 return bnx2x_tx_queue_has_work(fp);
1089 static int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
1091 uint16_t rx_cq_cons_sb;
1092 struct bnx2x_rx_queue *rxq;
1093 rxq = fp->sc->rx_queues[fp->index];
1094 if (unlikely(!rxq)) {
1095 PMD_RX_LOG(ERR, "ERROR: RX queue is NULL");
1099 mb(); /* status block fields can change */
1100 rx_cq_cons_sb = le16toh(*fp->rx_cq_cons_sb);
1101 if (unlikely((rx_cq_cons_sb & MAX_RCQ_ENTRIES(rxq)) ==
1102 MAX_RCQ_ENTRIES(rxq)))
1104 return (rxq->rx_cq_head != rx_cq_cons_sb);
1108 bnx2x_sp_event(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
1109 union eth_rx_cqe *rr_cqe)
1111 #ifdef RTE_LIBRTE_BNX2X_DEBUG
1112 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1114 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1115 enum ecore_queue_cmd drv_cmd = ECORE_Q_CMD_MAX;
1116 struct ecore_queue_sp_obj *q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
1119 "fp=%d cid=%d got ramrod #%d state is %x type is %d",
1120 fp->index, cid, command, sc->state,
1121 rr_cqe->ramrod_cqe.ramrod_type);
1124 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1125 PMD_DRV_LOG(DEBUG, "got UPDATE ramrod. CID %d", cid);
1126 drv_cmd = ECORE_Q_CMD_UPDATE;
1129 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1130 PMD_DRV_LOG(DEBUG, "got MULTI[%d] setup ramrod", cid);
1131 drv_cmd = ECORE_Q_CMD_SETUP;
1134 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1135 PMD_DRV_LOG(DEBUG, "got MULTI[%d] tx-only setup ramrod", cid);
1136 drv_cmd = ECORE_Q_CMD_SETUP_TX_ONLY;
1139 case (RAMROD_CMD_ID_ETH_HALT):
1140 PMD_DRV_LOG(DEBUG, "got MULTI[%d] halt ramrod", cid);
1141 drv_cmd = ECORE_Q_CMD_HALT;
1144 case (RAMROD_CMD_ID_ETH_TERMINATE):
1145 PMD_DRV_LOG(DEBUG, "got MULTI[%d] teminate ramrod", cid);
1146 drv_cmd = ECORE_Q_CMD_TERMINATE;
1149 case (RAMROD_CMD_ID_ETH_EMPTY):
1150 PMD_DRV_LOG(DEBUG, "got MULTI[%d] empty ramrod", cid);
1151 drv_cmd = ECORE_Q_CMD_EMPTY;
1156 "ERROR: unexpected MC reply (%d)"
1157 "on fp[%d]", command, fp->index);
1161 if ((drv_cmd != ECORE_Q_CMD_MAX) &&
1162 q_obj->complete_cmd(sc, q_obj, drv_cmd)) {
1164 * q_obj->complete_cmd() failure means that this was
1165 * an unexpected completion.
1167 * In this case we don't want to increase the sc->spq_left
1168 * because apparently we haven't sent this command the first
1171 // rte_panic("Unexpected SP completion");
1175 atomic_add_acq_long(&sc->cq_spq_left, 1);
1177 PMD_DRV_LOG(DEBUG, "sc->cq_spq_left 0x%lx",
1178 atomic_load_acq_long(&sc->cq_spq_left));
1181 static uint8_t bnx2x_rxeof(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
1183 struct bnx2x_rx_queue *rxq;
1184 uint16_t bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
1185 uint16_t hw_cq_cons, sw_cq_cons, sw_cq_prod;
1187 rxq = sc->rx_queues[fp->index];
1189 PMD_RX_LOG(ERR, "RX queue %d is NULL", fp->index);
1193 /* CQ "next element" is of the size of the regular element */
1194 hw_cq_cons = le16toh(*fp->rx_cq_cons_sb);
1195 if (unlikely((hw_cq_cons & USABLE_RCQ_ENTRIES_PER_PAGE) ==
1196 USABLE_RCQ_ENTRIES_PER_PAGE)) {
1200 bd_cons = rxq->rx_bd_head;
1201 bd_prod = rxq->rx_bd_tail;
1202 bd_prod_fw = bd_prod;
1203 sw_cq_cons = rxq->rx_cq_head;
1204 sw_cq_prod = rxq->rx_cq_tail;
1207 * Memory barrier necessary as speculative reads of the rx
1208 * buffer can be ahead of the index in the status block
1212 while (sw_cq_cons != hw_cq_cons) {
1213 union eth_rx_cqe *cqe;
1214 struct eth_fast_path_rx_cqe *cqe_fp;
1215 uint8_t cqe_fp_flags;
1216 enum eth_rx_cqe_type cqe_fp_type;
1218 comp_ring_cons = RCQ_ENTRY(sw_cq_cons, rxq);
1219 bd_prod = RX_BD(bd_prod, rxq);
1220 bd_cons = RX_BD(bd_cons, rxq);
1222 cqe = &rxq->cq_ring[comp_ring_cons];
1223 cqe_fp = &cqe->fast_path_cqe;
1224 cqe_fp_flags = cqe_fp->type_error_flags;
1225 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
1227 /* is this a slowpath msg? */
1228 if (CQE_TYPE_SLOW(cqe_fp_type)) {
1229 bnx2x_sp_event(sc, fp, cqe);
1233 /* is this an error packet? */
1234 if (unlikely(cqe_fp_flags &
1235 ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG)) {
1236 PMD_RX_LOG(DEBUG, "flags 0x%x rx packet %u",
1237 cqe_fp_flags, sw_cq_cons);
1241 PMD_RX_LOG(DEBUG, "Dropping fastpath called from attn poller!");
1244 bd_cons = NEXT_RX_BD(bd_cons);
1245 bd_prod = NEXT_RX_BD(bd_prod);
1246 bd_prod_fw = NEXT_RX_BD(bd_prod_fw);
1249 sw_cq_prod = NEXT_RCQ_IDX(sw_cq_prod);
1250 sw_cq_cons = NEXT_RCQ_IDX(sw_cq_cons);
1252 } /* while work to do */
1254 rxq->rx_bd_head = bd_cons;
1255 rxq->rx_bd_tail = bd_prod_fw;
1256 rxq->rx_cq_head = sw_cq_cons;
1257 rxq->rx_cq_tail = sw_cq_prod;
1259 /* Update producers */
1260 bnx2x_update_rx_prod(sc, fp, bd_prod_fw, sw_cq_prod);
1262 return (sw_cq_cons != hw_cq_cons);
1266 bnx2x_free_tx_pkt(__rte_unused struct bnx2x_fastpath *fp, struct bnx2x_tx_queue *txq,
1267 uint16_t pkt_idx, uint16_t bd_idx)
1269 struct eth_tx_start_bd *tx_start_bd =
1270 &txq->tx_ring[TX_BD(bd_idx, txq)].start_bd;
1271 uint16_t nbd = rte_le_to_cpu_16(tx_start_bd->nbd);
1272 struct rte_mbuf *tx_mbuf = txq->sw_ring[TX_BD(pkt_idx, txq)];
1274 if (likely(tx_mbuf != NULL)) {
1275 rte_pktmbuf_free(tx_mbuf);
1277 PMD_RX_LOG(ERR, "fp[%02d] lost mbuf %lu",
1278 fp->index, (unsigned long)TX_BD(pkt_idx, txq));
1281 txq->sw_ring[TX_BD(pkt_idx, txq)] = NULL;
1282 txq->nb_tx_avail += nbd;
1285 bd_idx = NEXT_TX_BD(bd_idx);
1290 /* processes transmit completions */
1291 uint8_t bnx2x_txeof(__rte_unused struct bnx2x_softc * sc, struct bnx2x_fastpath * fp)
1293 uint16_t bd_cons, hw_cons, sw_cons;
1294 __rte_unused uint16_t tx_bd_avail;
1296 struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1298 if (unlikely(!txq)) {
1299 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1303 bd_cons = txq->tx_bd_head;
1304 hw_cons = rte_le_to_cpu_16(*fp->tx_cons_sb);
1305 sw_cons = txq->tx_pkt_head;
1307 while (sw_cons != hw_cons) {
1308 bd_cons = bnx2x_free_tx_pkt(fp, txq, sw_cons, bd_cons);
1312 txq->tx_pkt_head = sw_cons;
1313 txq->tx_bd_head = bd_cons;
1315 tx_bd_avail = txq->nb_tx_avail;
1317 PMD_TX_LOG(DEBUG, "fp[%02d] avail=%u cons_sb=%u, "
1318 "pkt_head=%u pkt_tail=%u bd_head=%u bd_tail=%u",
1319 fp->index, tx_bd_avail, hw_cons,
1320 txq->tx_pkt_head, txq->tx_pkt_tail,
1321 txq->tx_bd_head, txq->tx_bd_tail);
1325 static void bnx2x_drain_tx_queues(struct bnx2x_softc *sc)
1327 struct bnx2x_fastpath *fp;
1330 /* wait until all TX fastpath tasks have completed */
1331 for (i = 0; i < sc->num_queues; i++) {
1336 while (bnx2x_has_tx_work(fp)) {
1337 bnx2x_txeof(sc, fp);
1341 "Timeout waiting for fp[%d] "
1342 "transmits to complete!", i);
1343 rte_panic("tx drain failure");
1357 bnx2x_del_all_macs(struct bnx2x_softc *sc, struct ecore_vlan_mac_obj *mac_obj,
1358 int mac_type, uint8_t wait_for_comp)
1360 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1363 /* wait for completion of requested */
1364 if (wait_for_comp) {
1365 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1368 /* Set the mac type of addresses we want to clear */
1369 bnx2x_set_bit(mac_type, &vlan_mac_flags);
1371 rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1373 PMD_DRV_LOG(ERR, "Failed to delete MACs (%d)", rc);
1379 bnx2x_fill_accept_flags(struct bnx2x_softc *sc, uint32_t rx_mode,
1380 unsigned long *rx_accept_flags,
1381 unsigned long *tx_accept_flags)
1383 /* Clear the flags first */
1384 *rx_accept_flags = 0;
1385 *tx_accept_flags = 0;
1388 case BNX2X_RX_MODE_NONE:
1390 * 'drop all' supersedes any accept flags that may have been
1391 * passed to the function.
1395 case BNX2X_RX_MODE_NORMAL:
1396 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1397 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, rx_accept_flags);
1398 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1400 /* internal switching mode */
1401 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1402 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, tx_accept_flags);
1403 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1407 case BNX2X_RX_MODE_ALLMULTI:
1408 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1409 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1410 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1412 /* internal switching mode */
1413 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1414 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1415 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1419 case BNX2X_RX_MODE_PROMISC:
1421 * According to deffinition of SI mode, iface in promisc mode
1422 * should receive matched and unmatched (in resolution of port)
1425 bnx2x_set_bit(ECORE_ACCEPT_UNMATCHED, rx_accept_flags);
1426 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1427 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1428 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1430 /* internal switching mode */
1431 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1432 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1435 bnx2x_set_bit(ECORE_ACCEPT_ALL_UNICAST, tx_accept_flags);
1437 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1443 PMD_RX_LOG(ERR, "Unknown rx_mode (%d)", rx_mode);
1447 /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
1448 if (rx_mode != BNX2X_RX_MODE_NONE) {
1449 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, rx_accept_flags);
1450 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, tx_accept_flags);
1457 bnx2x_set_q_rx_mode(struct bnx2x_softc *sc, uint8_t cl_id,
1458 unsigned long rx_mode_flags,
1459 unsigned long rx_accept_flags,
1460 unsigned long tx_accept_flags, unsigned long ramrod_flags)
1462 struct ecore_rx_mode_ramrod_params ramrod_param;
1465 memset(&ramrod_param, 0, sizeof(ramrod_param));
1467 /* Prepare ramrod parameters */
1468 ramrod_param.cid = 0;
1469 ramrod_param.cl_id = cl_id;
1470 ramrod_param.rx_mode_obj = &sc->rx_mode_obj;
1471 ramrod_param.func_id = SC_FUNC(sc);
1473 ramrod_param.pstate = &sc->sp_state;
1474 ramrod_param.state = ECORE_FILTER_RX_MODE_PENDING;
1476 ramrod_param.rdata = BNX2X_SP(sc, rx_mode_rdata);
1477 ramrod_param.rdata_mapping =
1478 (phys_addr_t)BNX2X_SP_MAPPING(sc, rx_mode_rdata),
1479 bnx2x_set_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
1481 ramrod_param.ramrod_flags = ramrod_flags;
1482 ramrod_param.rx_mode_flags = rx_mode_flags;
1484 ramrod_param.rx_accept_flags = rx_accept_flags;
1485 ramrod_param.tx_accept_flags = tx_accept_flags;
1487 rc = ecore_config_rx_mode(sc, &ramrod_param);
1489 PMD_RX_LOG(ERR, "Set rx_mode %d failed", sc->rx_mode);
1496 int bnx2x_set_storm_rx_mode(struct bnx2x_softc *sc)
1498 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
1499 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
1502 rc = bnx2x_fill_accept_flags(sc, sc->rx_mode, &rx_accept_flags,
1508 bnx2x_set_bit(RAMROD_RX, &ramrod_flags);
1509 bnx2x_set_bit(RAMROD_TX, &ramrod_flags);
1510 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1512 return bnx2x_set_q_rx_mode(sc, sc->fp[0].cl_id, rx_mode_flags,
1513 rx_accept_flags, tx_accept_flags,
1517 /* returns the "mcp load_code" according to global load_count array */
1518 static int bnx2x_nic_load_no_mcp(struct bnx2x_softc *sc)
1520 int path = SC_PATH(sc);
1521 int port = SC_PORT(sc);
1523 PMD_DRV_LOG(INFO, "NO MCP - load counts[%d] %d, %d, %d",
1524 path, load_count[path][0], load_count[path][1],
1525 load_count[path][2]);
1527 load_count[path][0]++;
1528 load_count[path][1 + port]++;
1529 PMD_DRV_LOG(INFO, "NO MCP - new load counts[%d] %d, %d, %d",
1530 path, load_count[path][0], load_count[path][1],
1531 load_count[path][2]);
1532 if (load_count[path][0] == 1)
1533 return FW_MSG_CODE_DRV_LOAD_COMMON;
1534 else if (load_count[path][1 + port] == 1)
1535 return FW_MSG_CODE_DRV_LOAD_PORT;
1537 return FW_MSG_CODE_DRV_LOAD_FUNCTION;
1540 /* returns the "mcp load_code" according to global load_count array */
1541 static int bnx2x_nic_unload_no_mcp(struct bnx2x_softc *sc)
1543 int port = SC_PORT(sc);
1544 int path = SC_PATH(sc);
1546 PMD_DRV_LOG(INFO, "NO MCP - load counts[%d] %d, %d, %d",
1547 path, load_count[path][0], load_count[path][1],
1548 load_count[path][2]);
1549 load_count[path][0]--;
1550 load_count[path][1 + port]--;
1551 PMD_DRV_LOG(INFO, "NO MCP - new load counts[%d] %d, %d, %d",
1552 path, load_count[path][0], load_count[path][1],
1553 load_count[path][2]);
1554 if (load_count[path][0] == 0) {
1555 return FW_MSG_CODE_DRV_UNLOAD_COMMON;
1556 } else if (load_count[path][1 + port] == 0) {
1557 return FW_MSG_CODE_DRV_UNLOAD_PORT;
1559 return FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
1563 /* request unload mode from the MCP: COMMON, PORT or FUNCTION */
1564 static uint32_t bnx2x_send_unload_req(struct bnx2x_softc *sc, int unload_mode)
1566 uint32_t reset_code = 0;
1568 /* Select the UNLOAD request mode */
1569 if (unload_mode == UNLOAD_NORMAL) {
1570 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1572 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1575 /* Send the request to the MCP */
1576 if (!BNX2X_NOMCP(sc)) {
1577 reset_code = bnx2x_fw_command(sc, reset_code, 0);
1579 reset_code = bnx2x_nic_unload_no_mcp(sc);
1585 /* send UNLOAD_DONE command to the MCP */
1586 static void bnx2x_send_unload_done(struct bnx2x_softc *sc, uint8_t keep_link)
1588 uint32_t reset_param =
1589 keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
1591 /* Report UNLOAD_DONE to MCP */
1592 if (!BNX2X_NOMCP(sc)) {
1593 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
1597 static int bnx2x_func_wait_started(struct bnx2x_softc *sc)
1601 if (!sc->port.pmf) {
1606 * (assumption: No Attention from MCP at this stage)
1607 * PMF probably in the middle of TX disable/enable transaction
1608 * 1. Sync IRS for default SB
1609 * 2. Sync SP queue - this guarantees us that attention handling started
1610 * 3. Wait, that TX disable/enable transaction completes
1612 * 1+2 guarantee that if DCBX attention was scheduled it already changed
1613 * pending bit of transaction from STARTED-->TX_STOPPED, if we already
1614 * received completion for the transaction the state is TX_STOPPED.
1615 * State will return to STARTED after completion of TX_STOPPED-->STARTED
1619 while (ecore_func_get_state(sc, &sc->func_obj) !=
1620 ECORE_F_STATE_STARTED && tout--) {
1624 if (ecore_func_get_state(sc, &sc->func_obj) != ECORE_F_STATE_STARTED) {
1626 * Failed to complete the transaction in a "good way"
1627 * Force both transactions with CLR bit.
1629 struct ecore_func_state_params func_params = { NULL };
1631 PMD_DRV_LOG(NOTICE, "Unexpected function state! "
1632 "Forcing STARTED-->TX_STOPPED-->STARTED");
1634 func_params.f_obj = &sc->func_obj;
1635 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1637 /* STARTED-->TX_STOPPED */
1638 func_params.cmd = ECORE_F_CMD_TX_STOP;
1639 ecore_func_state_change(sc, &func_params);
1641 /* TX_STOPPED-->STARTED */
1642 func_params.cmd = ECORE_F_CMD_TX_START;
1643 return ecore_func_state_change(sc, &func_params);
1649 static int bnx2x_stop_queue(struct bnx2x_softc *sc, int index)
1651 struct bnx2x_fastpath *fp = &sc->fp[index];
1652 struct ecore_queue_state_params q_params = { NULL };
1655 PMD_DRV_LOG(DEBUG, "stopping queue %d cid %d", index, fp->index);
1657 q_params.q_obj = &sc->sp_objs[fp->index].q_obj;
1658 /* We want to wait for completion in this context */
1659 bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
1661 /* Stop the primary connection: */
1663 /* ...halt the connection */
1664 q_params.cmd = ECORE_Q_CMD_HALT;
1665 rc = ecore_queue_state_change(sc, &q_params);
1670 /* ...terminate the connection */
1671 q_params.cmd = ECORE_Q_CMD_TERMINATE;
1672 memset(&q_params.params.terminate, 0,
1673 sizeof(q_params.params.terminate));
1674 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
1675 rc = ecore_queue_state_change(sc, &q_params);
1680 /* ...delete cfc entry */
1681 q_params.cmd = ECORE_Q_CMD_CFC_DEL;
1682 memset(&q_params.params.cfc_del, 0, sizeof(q_params.params.cfc_del));
1683 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
1684 return ecore_queue_state_change(sc, &q_params);
1687 /* wait for the outstanding SP commands */
1688 static uint8_t bnx2x_wait_sp_comp(struct bnx2x_softc *sc, unsigned long mask)
1691 int tout = 5000; /* wait for 5 secs tops */
1695 if (!(atomic_load_acq_long(&sc->sp_state) & mask)) {
1704 tmp = atomic_load_acq_long(&sc->sp_state);
1706 PMD_DRV_LOG(INFO, "Filtering completion timed out: "
1707 "sp_state 0x%lx, mask 0x%lx", tmp, mask);
1714 static int bnx2x_func_stop(struct bnx2x_softc *sc)
1716 struct ecore_func_state_params func_params = { NULL };
1719 /* prepare parameters for function state transitions */
1720 bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1721 func_params.f_obj = &sc->func_obj;
1722 func_params.cmd = ECORE_F_CMD_STOP;
1725 * Try to stop the function the 'good way'. If it fails (in case
1726 * of a parity error during bnx2x_chip_cleanup()) and we are
1727 * not in a debug mode, perform a state transaction in order to
1728 * enable further HW_RESET transaction.
1730 rc = ecore_func_state_change(sc, &func_params);
1732 PMD_DRV_LOG(NOTICE, "FUNC_STOP ramrod failed. "
1733 "Running a dry transaction");
1734 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1735 return ecore_func_state_change(sc, &func_params);
1741 static int bnx2x_reset_hw(struct bnx2x_softc *sc, uint32_t load_code)
1743 struct ecore_func_state_params func_params = { NULL };
1745 /* Prepare parameters for function state transitions */
1746 bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1748 func_params.f_obj = &sc->func_obj;
1749 func_params.cmd = ECORE_F_CMD_HW_RESET;
1751 func_params.params.hw_init.load_phase = load_code;
1753 return ecore_func_state_change(sc, &func_params);
1756 static void bnx2x_int_disable_sync(struct bnx2x_softc *sc, int disable_hw)
1759 /* prevent the HW from sending interrupts */
1760 bnx2x_int_disable(sc);
1765 bnx2x_chip_cleanup(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1767 int port = SC_PORT(sc);
1768 struct ecore_mcast_ramrod_params rparam = { NULL };
1769 uint32_t reset_code;
1772 bnx2x_drain_tx_queues(sc);
1774 /* give HW time to discard old tx messages */
1777 /* Clean all ETH MACs */
1778 rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_ETH_MAC,
1781 PMD_DRV_LOG(NOTICE, "Failed to delete all ETH MACs (%d)", rc);
1784 /* Clean up UC list */
1785 rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_UC_LIST_MAC,
1788 PMD_DRV_LOG(NOTICE, "Failed to delete UC MACs list (%d)", rc);
1792 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
1794 /* Set "drop all" to stop Rx */
1797 * We need to take the if_maddr_lock() here in order to prevent
1798 * a race between the completion code and this code.
1801 if (bnx2x_test_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) {
1802 bnx2x_set_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state);
1804 bnx2x_set_storm_rx_mode(sc);
1807 /* Clean up multicast configuration */
1808 rparam.mcast_obj = &sc->mcast_obj;
1809 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1812 "Failed to send DEL MCAST command (%d)", rc);
1816 * Send the UNLOAD_REQUEST to the MCP. This will return if
1817 * this function should perform FUNCTION, PORT, or COMMON HW
1820 reset_code = bnx2x_send_unload_req(sc, unload_mode);
1823 * (assumption: No Attention from MCP at this stage)
1824 * PMF probably in the middle of TX disable/enable transaction
1826 rc = bnx2x_func_wait_started(sc);
1828 PMD_DRV_LOG(NOTICE, "bnx2x_func_wait_started failed");
1832 * Close multi and leading connections
1833 * Completions for ramrods are collected in a synchronous way
1835 for (i = 0; i < sc->num_queues; i++) {
1836 if (bnx2x_stop_queue(sc, i)) {
1842 * If SP settings didn't get completed so far - something
1843 * very wrong has happen.
1845 if (!bnx2x_wait_sp_comp(sc, ~0x0UL)) {
1846 PMD_DRV_LOG(NOTICE, "Common slow path ramrods got stuck!");
1851 rc = bnx2x_func_stop(sc);
1853 PMD_DRV_LOG(NOTICE, "Function stop failed!");
1856 /* disable HW interrupts */
1857 bnx2x_int_disable_sync(sc, TRUE);
1859 /* Reset the chip */
1860 rc = bnx2x_reset_hw(sc, reset_code);
1862 PMD_DRV_LOG(NOTICE, "Hardware reset failed");
1865 /* Report UNLOAD_DONE to MCP */
1866 bnx2x_send_unload_done(sc, keep_link);
1869 static void bnx2x_disable_close_the_gate(struct bnx2x_softc *sc)
1873 PMD_DRV_LOG(DEBUG, "Disabling 'close the gates'");
1875 val = REG_RD(sc, MISC_REG_AEU_GENERAL_MASK);
1876 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
1877 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
1878 REG_WR(sc, MISC_REG_AEU_GENERAL_MASK, val);
1882 * Cleans the object that have internal lists without sending
1883 * ramrods. Should be run when interrutps are disabled.
1885 static void bnx2x_squeeze_objects(struct bnx2x_softc *sc)
1887 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1888 struct ecore_mcast_ramrod_params rparam = { NULL };
1889 struct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj;
1892 /* Cleanup MACs' object first... */
1894 /* Wait for completion of requested */
1895 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1896 /* Perform a dry cleanup */
1897 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &ramrod_flags);
1899 /* Clean ETH primary MAC */
1900 bnx2x_set_bit(ECORE_ETH_MAC, &vlan_mac_flags);
1901 rc = mac_obj->delete_all(sc, &sc->sp_objs->mac_obj, &vlan_mac_flags,
1904 PMD_DRV_LOG(NOTICE, "Failed to clean ETH MACs (%d)", rc);
1907 /* Cleanup UC list */
1909 bnx2x_set_bit(ECORE_UC_LIST_MAC, &vlan_mac_flags);
1910 rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1912 PMD_DRV_LOG(NOTICE, "Failed to clean UC list MACs (%d)", rc);
1915 /* Now clean mcast object... */
1917 rparam.mcast_obj = &sc->mcast_obj;
1918 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags);
1920 /* Add a DEL command... */
1921 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1924 "Failed to send DEL MCAST command (%d)", rc);
1927 /* now wait until all pending commands are cleared */
1929 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
1933 "Failed to clean MCAST object (%d)", rc);
1937 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
1941 /* stop the controller */
1942 __attribute__ ((noinline))
1944 bnx2x_nic_unload(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1946 uint8_t global = FALSE;
1949 PMD_DRV_LOG(DEBUG, "Starting NIC unload...");
1951 /* stop the periodic callout */
1952 bnx2x_periodic_stop(sc);
1954 /* mark driver as unloaded in shmem2 */
1955 if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
1956 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
1957 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
1958 val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
1961 if (IS_PF(sc) && sc->recovery_state != BNX2X_RECOVERY_DONE &&
1962 (sc->state == BNX2X_STATE_CLOSED || sc->state == BNX2X_STATE_ERROR)) {
1964 * We can get here if the driver has been unloaded
1965 * during parity error recovery and is either waiting for a
1966 * leader to complete or for other functions to unload and
1967 * then ifconfig down has been issued. In this case we want to
1968 * unload and let other functions to complete a recovery
1971 sc->recovery_state = BNX2X_RECOVERY_DONE;
1973 bnx2x_release_leader_lock(sc);
1976 PMD_DRV_LOG(NOTICE, "Can't unload in closed or error state");
1981 * Nothing to do during unload if previous bnx2x_nic_load()
1982 * did not completed succesfully - all resourses are released.
1984 if ((sc->state == BNX2X_STATE_CLOSED) || (sc->state == BNX2X_STATE_ERROR)) {
1988 sc->state = BNX2X_STATE_CLOSING_WAITING_HALT;
1991 sc->rx_mode = BNX2X_RX_MODE_NONE;
1992 bnx2x_set_rx_mode(sc);
1996 /* set ALWAYS_ALIVE bit in shmem */
1997 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
1999 bnx2x_drv_pulse(sc);
2001 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2002 bnx2x_save_statistics(sc);
2005 /* wait till consumers catch up with producers in all queues */
2006 bnx2x_drain_tx_queues(sc);
2008 /* if VF indicate to PF this function is going down (PF will delete sp
2009 * elements and clear initializations
2012 bnx2x_vf_unload(sc);
2013 } else if (unload_mode != UNLOAD_RECOVERY) {
2014 /* if this is a normal/close unload need to clean up chip */
2015 bnx2x_chip_cleanup(sc, unload_mode, keep_link);
2017 /* Send the UNLOAD_REQUEST to the MCP */
2018 bnx2x_send_unload_req(sc, unload_mode);
2021 * Prevent transactions to host from the functions on the
2022 * engine that doesn't reset global blocks in case of global
2023 * attention once gloabl blocks are reset and gates are opened
2024 * (the engine which leader will perform the recovery
2027 if (!CHIP_IS_E1x(sc)) {
2028 bnx2x_pf_disable(sc);
2031 /* disable HW interrupts */
2032 bnx2x_int_disable_sync(sc, TRUE);
2034 /* Report UNLOAD_DONE to MCP */
2035 bnx2x_send_unload_done(sc, FALSE);
2039 * At this stage no more interrupts will arrive so we may safely clean
2040 * the queue'able objects here in case they failed to get cleaned so far.
2043 bnx2x_squeeze_objects(sc);
2046 /* There should be no more pending SP commands at this stage */
2055 bnx2x_free_fw_stats_mem(sc);
2057 sc->state = BNX2X_STATE_CLOSED;
2060 * Check if there are pending parity attentions. If there are - set
2061 * RECOVERY_IN_PROGRESS.
2063 if (IS_PF(sc) && bnx2x_chk_parity_attn(sc, &global, FALSE)) {
2064 bnx2x_set_reset_in_progress(sc);
2066 /* Set RESET_IS_GLOBAL if needed */
2068 bnx2x_set_reset_global(sc);
2073 * The last driver must disable a "close the gate" if there is no
2074 * parity attention or "process kill" pending.
2076 if (IS_PF(sc) && !bnx2x_clear_pf_load(sc) &&
2077 bnx2x_reset_is_done(sc, SC_PATH(sc))) {
2078 bnx2x_disable_close_the_gate(sc);
2081 PMD_DRV_LOG(DEBUG, "Ended NIC unload");
2087 * Encapsulte an mbuf cluster into the tx bd chain and makes the memory
2088 * visible to the controller.
2090 * If an mbuf is submitted to this routine and cannot be given to the
2091 * controller (e.g. it has too many fragments) then the function may free
2092 * the mbuf and return to the caller.
2095 * 0 = Success, !0 = Failure
2096 * Note the side effect that an mbuf may be freed if it causes a problem.
2098 int bnx2x_tx_encap(struct bnx2x_tx_queue *txq, struct rte_mbuf **m_head, int m_pkts)
2100 struct rte_mbuf *m0;
2101 struct eth_tx_start_bd *tx_start_bd;
2102 uint16_t bd_prod, pkt_prod;
2104 struct bnx2x_softc *sc;
2106 struct bnx2x_fastpath *fp;
2109 fp = &sc->fp[txq->queue_id];
2111 bd_prod = txq->tx_bd_tail;
2112 pkt_prod = txq->tx_pkt_tail;
2114 for (m_tx = 0; m_tx < m_pkts; m_tx++) {
2118 if (unlikely(txq->nb_tx_avail < 3)) {
2119 PMD_TX_LOG(ERR, "no enough bds %d/%d",
2120 bd_prod, txq->nb_tx_avail);
2124 txq->sw_ring[TX_BD(pkt_prod, txq)] = m0;
2126 tx_start_bd = &txq->tx_ring[TX_BD(bd_prod, txq)].start_bd;
2129 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR(m0));
2130 tx_start_bd->nbytes = rte_cpu_to_le_16(m0->data_len);
2131 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2132 tx_start_bd->general_data =
2133 (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
2135 tx_start_bd->nbd = rte_cpu_to_le_16(2);
2137 if (m0->ol_flags & PKT_TX_VLAN_PKT) {
2138 tx_start_bd->vlan_or_ethertype =
2139 rte_cpu_to_le_16(m0->vlan_tci);
2140 tx_start_bd->bd_flags.as_bitfield |=
2141 (X_ETH_OUTBAND_VLAN <<
2142 ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT);
2145 tx_start_bd->vlan_or_ethertype =
2146 rte_cpu_to_le_16(pkt_prod);
2148 struct ether_hdr *eh
2149 = rte_pktmbuf_mtod(m0, struct ether_hdr *);
2151 tx_start_bd->vlan_or_ethertype
2152 = rte_cpu_to_le_16(rte_be_to_cpu_16(eh->ether_type));
2156 bd_prod = NEXT_TX_BD(bd_prod);
2158 struct eth_tx_parse_bd_e2 *tx_parse_bd;
2159 const struct ether_hdr *eh = rte_pktmbuf_mtod(m0, struct ether_hdr *);
2160 uint8_t mac_type = UNICAST_ADDRESS;
2163 &txq->tx_ring[TX_BD(bd_prod, txq)].parse_bd_e2;
2164 if (is_multicast_ether_addr(&eh->d_addr)) {
2165 if (is_broadcast_ether_addr(&eh->d_addr))
2166 mac_type = BROADCAST_ADDRESS;
2168 mac_type = MULTICAST_ADDRESS;
2170 tx_parse_bd->parsing_data =
2171 (mac_type << ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT);
2173 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_hi,
2174 &eh->d_addr.addr_bytes[0], 2);
2175 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_mid,
2176 &eh->d_addr.addr_bytes[2], 2);
2177 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_lo,
2178 &eh->d_addr.addr_bytes[4], 2);
2179 rte_memcpy(&tx_parse_bd->data.mac_addr.src_hi,
2180 &eh->s_addr.addr_bytes[0], 2);
2181 rte_memcpy(&tx_parse_bd->data.mac_addr.src_mid,
2182 &eh->s_addr.addr_bytes[2], 2);
2183 rte_memcpy(&tx_parse_bd->data.mac_addr.src_lo,
2184 &eh->s_addr.addr_bytes[4], 2);
2186 tx_parse_bd->data.mac_addr.dst_hi =
2187 rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_hi);
2188 tx_parse_bd->data.mac_addr.dst_mid =
2189 rte_cpu_to_be_16(tx_parse_bd->data.
2191 tx_parse_bd->data.mac_addr.dst_lo =
2192 rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_lo);
2193 tx_parse_bd->data.mac_addr.src_hi =
2194 rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_hi);
2195 tx_parse_bd->data.mac_addr.src_mid =
2196 rte_cpu_to_be_16(tx_parse_bd->data.
2198 tx_parse_bd->data.mac_addr.src_lo =
2199 rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_lo);
2202 "PBD dst %x %x %x src %x %x %x p_data %x",
2203 tx_parse_bd->data.mac_addr.dst_hi,
2204 tx_parse_bd->data.mac_addr.dst_mid,
2205 tx_parse_bd->data.mac_addr.dst_lo,
2206 tx_parse_bd->data.mac_addr.src_hi,
2207 tx_parse_bd->data.mac_addr.src_mid,
2208 tx_parse_bd->data.mac_addr.src_lo,
2209 tx_parse_bd->parsing_data);
2213 "start bd: nbytes %d flags %x vlan %x\n",
2214 tx_start_bd->nbytes,
2215 tx_start_bd->bd_flags.as_bitfield,
2216 tx_start_bd->vlan_or_ethertype);
2218 bd_prod = NEXT_TX_BD(bd_prod);
2221 if (TX_IDX(bd_prod) < 2) {
2226 txq->nb_tx_avail -= m_pkts << 1;
2227 txq->tx_bd_tail = bd_prod;
2228 txq->tx_pkt_tail = pkt_prod;
2231 fp->tx_db.data.prod += (m_pkts << 1) + nbds;
2232 DOORBELL(sc, txq->queue_id, fp->tx_db.raw);
2238 static uint16_t bnx2x_cid_ilt_lines(struct bnx2x_softc *sc)
2240 return L2_ILT_LINES(sc);
2243 static void bnx2x_ilt_set_info(struct bnx2x_softc *sc)
2245 struct ilt_client_info *ilt_client;
2246 struct ecore_ilt *ilt = sc->ilt;
2249 PMD_INIT_FUNC_TRACE();
2251 ilt->start_line = FUNC_ILT_BASE(SC_FUNC(sc));
2254 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
2255 ilt_client->client_num = ILT_CLIENT_CDU;
2256 ilt_client->page_size = CDU_ILT_PAGE_SZ;
2257 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
2258 ilt_client->start = line;
2259 line += bnx2x_cid_ilt_lines(sc);
2261 if (CNIC_SUPPORT(sc)) {
2262 line += CNIC_ILT_LINES;
2265 ilt_client->end = (line - 1);
2268 if (QM_INIT(sc->qm_cid_count)) {
2269 ilt_client = &ilt->clients[ILT_CLIENT_QM];
2270 ilt_client->client_num = ILT_CLIENT_QM;
2271 ilt_client->page_size = QM_ILT_PAGE_SZ;
2272 ilt_client->flags = 0;
2273 ilt_client->start = line;
2275 /* 4 bytes for each cid */
2276 line += DIV_ROUND_UP(sc->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
2279 ilt_client->end = (line - 1);
2282 if (CNIC_SUPPORT(sc)) {
2284 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
2285 ilt_client->client_num = ILT_CLIENT_SRC;
2286 ilt_client->page_size = SRC_ILT_PAGE_SZ;
2287 ilt_client->flags = 0;
2288 ilt_client->start = line;
2289 line += SRC_ILT_LINES;
2290 ilt_client->end = (line - 1);
2293 ilt_client = &ilt->clients[ILT_CLIENT_TM];
2294 ilt_client->client_num = ILT_CLIENT_TM;
2295 ilt_client->page_size = TM_ILT_PAGE_SZ;
2296 ilt_client->flags = 0;
2297 ilt_client->start = line;
2298 line += TM_ILT_LINES;
2299 ilt_client->end = (line - 1);
2302 assert((line <= ILT_MAX_LINES));
2305 static void bnx2x_set_fp_rx_buf_size(struct bnx2x_softc *sc)
2309 for (i = 0; i < sc->num_queues; i++) {
2310 /* get the Rx buffer size for RX frames */
2311 sc->fp[i].rx_buf_size =
2312 (IP_HEADER_ALIGNMENT_PADDING + ETH_OVERHEAD + sc->mtu);
2314 /* get the mbuf allocation size for RX frames */
2315 if (sc->fp[i].rx_buf_size <= MCLBYTES) {
2316 sc->fp[i].mbuf_alloc_size = MCLBYTES;
2317 } else if (sc->fp[i].rx_buf_size <= BNX2X_PAGE_SIZE) {
2318 sc->fp[i].mbuf_alloc_size = PAGE_SIZE;
2320 sc->fp[i].mbuf_alloc_size = MJUM9BYTES;
2325 int bnx2x_alloc_ilt_mem(struct bnx2x_softc *sc)
2328 sc->ilt = rte_malloc("", sizeof(struct ecore_ilt), RTE_CACHE_LINE_SIZE);
2330 return sc->ilt == NULL;
2333 static int bnx2x_alloc_ilt_lines_mem(struct bnx2x_softc *sc)
2335 sc->ilt->lines = rte_calloc("",
2336 sizeof(struct ilt_line), ILT_MAX_LINES,
2337 RTE_CACHE_LINE_SIZE);
2338 return sc->ilt->lines == NULL;
2341 void bnx2x_free_ilt_mem(struct bnx2x_softc *sc)
2347 static void bnx2x_free_ilt_lines_mem(struct bnx2x_softc *sc)
2349 if (sc->ilt->lines != NULL) {
2350 rte_free(sc->ilt->lines);
2351 sc->ilt->lines = NULL;
2355 static void bnx2x_free_mem(struct bnx2x_softc *sc)
2359 for (i = 0; i < L2_ILT_LINES(sc); i++) {
2360 sc->context[i].vcxt = NULL;
2361 sc->context[i].size = 0;
2364 ecore_ilt_mem_op(sc, ILT_MEMOP_FREE);
2366 bnx2x_free_ilt_lines_mem(sc);
2369 static int bnx2x_alloc_mem(struct bnx2x_softc *sc)
2374 char cdu_name[RTE_MEMZONE_NAMESIZE];
2377 * Allocate memory for CDU context:
2378 * This memory is allocated separately and not in the generic ILT
2379 * functions because CDU differs in few aspects:
2380 * 1. There can be multiple entities allocating memory for context -
2381 * regular L2, CNIC, and SRIOV drivers. Each separately controls
2382 * its own ILT lines.
2383 * 2. Since CDU page-size is not a single 4KB page (which is the case
2384 * for the other ILT clients), to be efficient we want to support
2385 * allocation of sub-page-size in the last entry.
2386 * 3. Context pointers are used by the driver to pass to FW / update
2387 * the context (for the other ILT clients the pointers are used just to
2388 * free the memory during unload).
2390 context_size = (sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(sc));
2391 for (i = 0, allocated = 0; allocated < context_size; i++) {
2392 sc->context[i].size = min(CDU_ILT_PAGE_SZ,
2393 (context_size - allocated));
2395 snprintf(cdu_name, sizeof(cdu_name), "cdu_%d", i);
2396 if (bnx2x_dma_alloc(sc, sc->context[i].size,
2397 &sc->context[i].vcxt_dma,
2398 cdu_name, BNX2X_PAGE_SIZE) != 0) {
2403 sc->context[i].vcxt =
2404 (union cdu_context *)sc->context[i].vcxt_dma.vaddr;
2406 allocated += sc->context[i].size;
2409 bnx2x_alloc_ilt_lines_mem(sc);
2411 if (ecore_ilt_mem_op(sc, ILT_MEMOP_ALLOC)) {
2412 PMD_DRV_LOG(NOTICE, "ecore_ilt_mem_op ILT_MEMOP_ALLOC failed");
2420 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc)
2422 sc->fw_stats_num = 0;
2424 sc->fw_stats_req_size = 0;
2425 sc->fw_stats_req = NULL;
2426 sc->fw_stats_req_mapping = 0;
2428 sc->fw_stats_data_size = 0;
2429 sc->fw_stats_data = NULL;
2430 sc->fw_stats_data_mapping = 0;
2433 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc)
2435 uint8_t num_queue_stats;
2436 int num_groups, vf_headroom = 0;
2438 /* number of queues for statistics is number of eth queues */
2439 num_queue_stats = BNX2X_NUM_ETH_QUEUES(sc);
2442 * Total number of FW statistics requests =
2443 * 1 for port stats + 1 for PF stats + num of queues
2445 sc->fw_stats_num = (2 + num_queue_stats);
2448 * Request is built from stats_query_header and an array of
2449 * stats_query_cmd_group each of which contains STATS_QUERY_CMD_COUNT
2450 * rules. The real number or requests is configured in the
2451 * stats_query_header.
2453 num_groups = (sc->fw_stats_num + vf_headroom) / STATS_QUERY_CMD_COUNT;
2454 if ((sc->fw_stats_num + vf_headroom) % STATS_QUERY_CMD_COUNT)
2457 sc->fw_stats_req_size =
2458 (sizeof(struct stats_query_header) +
2459 (num_groups * sizeof(struct stats_query_cmd_group)));
2462 * Data for statistics requests + stats_counter.
2463 * stats_counter holds per-STORM counters that are incremented when
2464 * STORM has finished with the current request. Memory for FCoE
2465 * offloaded statistics are counted anyway, even if they will not be sent.
2466 * VF stats are not accounted for here as the data of VF stats is stored
2467 * in memory allocated by the VF, not here.
2469 sc->fw_stats_data_size =
2470 (sizeof(struct stats_counter) +
2471 sizeof(struct per_port_stats) + sizeof(struct per_pf_stats) +
2472 /* sizeof(struct fcoe_statistics_params) + */
2473 (sizeof(struct per_queue_stats) * num_queue_stats));
2475 if (bnx2x_dma_alloc(sc, (sc->fw_stats_req_size + sc->fw_stats_data_size),
2476 &sc->fw_stats_dma, "fw_stats",
2477 RTE_CACHE_LINE_SIZE) != 0) {
2478 bnx2x_free_fw_stats_mem(sc);
2482 /* set up the shortcuts */
2484 sc->fw_stats_req = (struct bnx2x_fw_stats_req *)sc->fw_stats_dma.vaddr;
2485 sc->fw_stats_req_mapping = sc->fw_stats_dma.paddr;
2488 (struct bnx2x_fw_stats_data *)((uint8_t *) sc->fw_stats_dma.vaddr +
2489 sc->fw_stats_req_size);
2490 sc->fw_stats_data_mapping = (sc->fw_stats_dma.paddr +
2491 sc->fw_stats_req_size);
2498 * 0-7 - Engine0 load counter.
2499 * 8-15 - Engine1 load counter.
2500 * 16 - Engine0 RESET_IN_PROGRESS bit.
2501 * 17 - Engine1 RESET_IN_PROGRESS bit.
2502 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active
2503 * function on the engine
2504 * 19 - Engine1 ONE_IS_LOADED.
2505 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
2506 * leader to complete (check for both RESET_IN_PROGRESS bits and not
2507 * for just the one belonging to its engine).
2509 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
2510 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
2511 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
2512 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
2513 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
2514 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
2515 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
2516 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
2518 /* set the GLOBAL_RESET bit, should be run under rtnl lock */
2519 static void bnx2x_set_reset_global(struct bnx2x_softc *sc)
2522 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2523 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2524 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
2525 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2528 /* clear the GLOBAL_RESET bit, should be run under rtnl lock */
2529 static void bnx2x_clear_reset_global(struct bnx2x_softc *sc)
2532 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2533 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2534 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
2535 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2538 /* checks the GLOBAL_RESET bit, should be run under rtnl lock */
2539 static uint8_t bnx2x_reset_is_global(struct bnx2x_softc *sc)
2541 return (REG_RD(sc, BNX2X_RECOVERY_GLOB_REG) & BNX2X_GLOBAL_RESET_BIT);
2544 /* clear RESET_IN_PROGRESS bit for the engine, should be run under rtnl lock */
2545 static void bnx2x_set_reset_done(struct bnx2x_softc *sc)
2548 uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2549 BNX2X_PATH0_RST_IN_PROG_BIT;
2551 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2553 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2556 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2558 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2561 /* set RESET_IN_PROGRESS for the engine, should be run under rtnl lock */
2562 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc)
2565 uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2566 BNX2X_PATH0_RST_IN_PROG_BIT;
2568 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2570 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2573 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2575 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2578 /* check RESET_IN_PROGRESS bit for an engine, should be run under rtnl lock */
2579 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine)
2581 uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2582 uint32_t bit = engine ? BNX2X_PATH1_RST_IN_PROG_BIT :
2583 BNX2X_PATH0_RST_IN_PROG_BIT;
2585 /* return false if bit is set */
2586 return (val & bit) ? FALSE : TRUE;
2589 /* get the load status for an engine, should be run under rtnl lock */
2590 static uint8_t bnx2x_get_load_status(struct bnx2x_softc *sc, int engine)
2592 uint32_t mask = engine ? BNX2X_PATH1_LOAD_CNT_MASK :
2593 BNX2X_PATH0_LOAD_CNT_MASK;
2594 uint32_t shift = engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2595 BNX2X_PATH0_LOAD_CNT_SHIFT;
2596 uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2598 val = ((val & mask) >> shift);
2603 /* set pf load mark */
2604 static void bnx2x_set_pf_load(struct bnx2x_softc *sc)
2608 uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2609 BNX2X_PATH0_LOAD_CNT_MASK;
2610 uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2611 BNX2X_PATH0_LOAD_CNT_SHIFT;
2613 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2615 PMD_INIT_FUNC_TRACE();
2617 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2619 /* get the current counter value */
2620 val1 = ((val & mask) >> shift);
2622 /* set bit of this PF */
2623 val1 |= (1 << SC_ABS_FUNC(sc));
2625 /* clear the old value */
2628 /* set the new one */
2629 val |= ((val1 << shift) & mask);
2631 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2633 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2636 /* clear pf load mark */
2637 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc)
2640 uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2641 BNX2X_PATH0_LOAD_CNT_MASK;
2642 uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2643 BNX2X_PATH0_LOAD_CNT_SHIFT;
2645 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2646 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2648 /* get the current counter value */
2649 val1 = (val & mask) >> shift;
2651 /* clear bit of that PF */
2652 val1 &= ~(1 << SC_ABS_FUNC(sc));
2654 /* clear the old value */
2657 /* set the new one */
2658 val |= ((val1 << shift) & mask);
2660 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2661 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2665 /* send load requrest to mcp and analyze response */
2666 static int bnx2x_nic_load_request(struct bnx2x_softc *sc, uint32_t * load_code)
2668 PMD_INIT_FUNC_TRACE();
2672 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
2673 DRV_MSG_SEQ_NUMBER_MASK);
2675 PMD_DRV_LOG(DEBUG, "initial fw_seq 0x%04x", sc->fw_seq);
2678 /* get the current FW pulse sequence */
2679 sc->fw_drv_pulse_wr_seq =
2680 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb) &
2681 DRV_PULSE_SEQ_MASK);
2683 /* set ALWAYS_ALIVE bit in shmem */
2684 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2685 bnx2x_drv_pulse(sc);
2689 (*load_code) = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
2690 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
2692 /* if the MCP fails to respond we must abort */
2693 if (!(*load_code)) {
2694 PMD_DRV_LOG(NOTICE, "MCP response failure!");
2698 /* if MCP refused then must abort */
2699 if ((*load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED) {
2700 PMD_DRV_LOG(NOTICE, "MCP refused load request");
2708 * Check whether another PF has already loaded FW to chip. In virtualized
2709 * environments a pf from anoth VM may have already initialized the device
2710 * including loading FW.
2712 static int bnx2x_nic_load_analyze_req(struct bnx2x_softc *sc, uint32_t load_code)
2714 uint32_t my_fw, loaded_fw;
2716 /* is another pf loaded on this engine? */
2717 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
2718 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
2719 /* build my FW version dword */
2720 my_fw = (BNX2X_5710_FW_MAJOR_VERSION +
2721 (BNX2X_5710_FW_MINOR_VERSION << 8) +
2722 (BNX2X_5710_FW_REVISION_VERSION << 16) +
2723 (BNX2X_5710_FW_ENGINEERING_VERSION << 24));
2725 /* read loaded FW from chip */
2726 loaded_fw = REG_RD(sc, XSEM_REG_PRAM);
2727 PMD_DRV_LOG(DEBUG, "loaded FW 0x%08x / my FW 0x%08x",
2730 /* abort nic load if version mismatch */
2731 if (my_fw != loaded_fw) {
2733 "FW 0x%08x already loaded (mine is 0x%08x)",
2742 /* mark PMF if applicable */
2743 static void bnx2x_nic_load_pmf(struct bnx2x_softc *sc, uint32_t load_code)
2745 uint32_t ncsi_oem_data_addr;
2747 PMD_INIT_FUNC_TRACE();
2749 if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
2750 (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
2751 (load_code == FW_MSG_CODE_DRV_LOAD_PORT)) {
2753 * Barrier here for ordering between the writing to sc->port.pmf here
2754 * and reading it from the periodic task.
2762 PMD_DRV_LOG(DEBUG, "pmf %d", sc->port.pmf);
2764 if (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) {
2765 if (SHMEM2_HAS(sc, ncsi_oem_data_addr)) {
2766 ncsi_oem_data_addr = SHMEM2_RD(sc, ncsi_oem_data_addr);
2767 if (ncsi_oem_data_addr) {
2769 (ncsi_oem_data_addr +
2770 offsetof(struct glob_ncsi_oem_data,
2771 driver_version)), 0);
2777 static void bnx2x_read_mf_cfg(struct bnx2x_softc *sc)
2779 int n = (CHIP_IS_MODE_4_PORT(sc) ? 2 : 1);
2783 if (BNX2X_NOMCP(sc)) {
2784 return; /* what should be the default bvalue in this case */
2788 * The formula for computing the absolute function number is...
2789 * For 2 port configuration (4 functions per port):
2790 * abs_func = 2 * vn + SC_PORT + SC_PATH
2791 * For 4 port configuration (2 functions per port):
2792 * abs_func = 4 * vn + 2 * SC_PORT + SC_PATH
2794 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
2795 abs_func = (n * (2 * vn + SC_PORT(sc)) + SC_PATH(sc));
2796 if (abs_func >= E1H_FUNC_MAX) {
2799 sc->devinfo.mf_info.mf_config[vn] =
2800 MFCFG_RD(sc, func_mf_config[abs_func].config);
2803 if (sc->devinfo.mf_info.mf_config[SC_VN(sc)] &
2804 FUNC_MF_CFG_FUNC_DISABLED) {
2805 PMD_DRV_LOG(DEBUG, "mf_cfg function disabled");
2806 sc->flags |= BNX2X_MF_FUNC_DIS;
2808 PMD_DRV_LOG(DEBUG, "mf_cfg function enabled");
2809 sc->flags &= ~BNX2X_MF_FUNC_DIS;
2813 /* acquire split MCP access lock register */
2814 static int bnx2x_acquire_alr(struct bnx2x_softc *sc)
2818 for (j = 0; j < 1000; j++) {
2820 REG_WR(sc, GRCBASE_MCP + 0x9c, val);
2821 val = REG_RD(sc, GRCBASE_MCP + 0x9c);
2822 if (val & (1L << 31))
2828 if (!(val & (1L << 31))) {
2829 PMD_DRV_LOG(NOTICE, "Cannot acquire MCP access lock register");
2836 /* release split MCP access lock register */
2837 static void bnx2x_release_alr(struct bnx2x_softc *sc)
2839 REG_WR(sc, GRCBASE_MCP + 0x9c, 0);
2842 static void bnx2x_fan_failure(struct bnx2x_softc *sc)
2844 int port = SC_PORT(sc);
2845 uint32_t ext_phy_config;
2847 /* mark the failure */
2849 SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
2851 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2852 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
2853 SHMEM_WR(sc, dev_info.port_hw_config[port].external_phy_config,
2856 /* log the failure */
2858 "Fan Failure has caused the driver to shutdown "
2859 "the card to prevent permanent damage. "
2860 "Please contact OEM Support for assistance");
2862 rte_panic("Schedule task to handle fan failure");
2865 /* this function is called upon a link interrupt */
2866 static void bnx2x_link_attn(struct bnx2x_softc *sc)
2868 uint32_t pause_enabled = 0;
2869 struct host_port_stats *pstats;
2872 /* Make sure that we are synced with the current statistics */
2873 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2875 elink_link_update(&sc->link_params, &sc->link_vars);
2877 if (sc->link_vars.link_up) {
2879 /* dropless flow control */
2880 if (sc->dropless_fc) {
2883 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
2888 (BAR_USTRORM_INTMEM +
2889 USTORM_ETH_PAUSE_ENABLED_OFFSET(SC_PORT(sc))),
2893 if (sc->link_vars.mac_type != ELINK_MAC_TYPE_EMAC) {
2894 pstats = BNX2X_SP(sc, port_stats);
2895 /* reset old mac stats */
2896 memset(&(pstats->mac_stx[0]), 0,
2897 sizeof(struct mac_stx));
2900 if (sc->state == BNX2X_STATE_OPEN) {
2901 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
2905 if (sc->link_vars.link_up && sc->link_vars.line_speed) {
2906 cmng_fns = bnx2x_get_cmng_fns_mode(sc);
2908 if (cmng_fns != CMNG_FNS_NONE) {
2909 bnx2x_cmng_fns_init(sc, FALSE, cmng_fns);
2910 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
2914 bnx2x_link_report(sc);
2917 bnx2x_link_sync_notify(sc);
2921 static void bnx2x_attn_int_asserted(struct bnx2x_softc *sc, uint32_t asserted)
2923 int port = SC_PORT(sc);
2924 uint32_t aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2925 MISC_REG_AEU_MASK_ATTN_FUNC_0;
2926 uint32_t nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2927 NIG_REG_MASK_INTERRUPT_PORT0;
2929 uint32_t nig_mask = 0;
2934 if (sc->attn_state & asserted) {
2935 PMD_DRV_LOG(ERR, "IGU ERROR attn=0x%08x", asserted);
2938 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2940 aeu_mask = REG_RD(sc, aeu_addr);
2942 aeu_mask &= ~(asserted & 0x3ff);
2944 REG_WR(sc, aeu_addr, aeu_mask);
2946 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2948 sc->attn_state |= asserted;
2950 if (asserted & ATTN_HARD_WIRED_MASK) {
2951 if (asserted & ATTN_NIG_FOR_FUNC) {
2953 /* save nig interrupt mask */
2954 nig_mask = REG_RD(sc, nig_int_mask_addr);
2956 /* If nig_mask is not set, no need to call the update function */
2958 REG_WR(sc, nig_int_mask_addr, 0);
2960 bnx2x_link_attn(sc);
2963 /* handle unicore attn? */
2966 if (asserted & ATTN_SW_TIMER_4_FUNC) {
2967 PMD_DRV_LOG(DEBUG, "ATTN_SW_TIMER_4_FUNC!");
2970 if (asserted & GPIO_2_FUNC) {
2971 PMD_DRV_LOG(DEBUG, "GPIO_2_FUNC!");
2974 if (asserted & GPIO_3_FUNC) {
2975 PMD_DRV_LOG(DEBUG, "GPIO_3_FUNC!");
2978 if (asserted & GPIO_4_FUNC) {
2979 PMD_DRV_LOG(DEBUG, "GPIO_4_FUNC!");
2983 if (asserted & ATTN_GENERAL_ATTN_1) {
2984 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_1!");
2985 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
2987 if (asserted & ATTN_GENERAL_ATTN_2) {
2988 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_2!");
2989 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
2991 if (asserted & ATTN_GENERAL_ATTN_3) {
2992 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_3!");
2993 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
2996 if (asserted & ATTN_GENERAL_ATTN_4) {
2997 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_4!");
2998 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3000 if (asserted & ATTN_GENERAL_ATTN_5) {
3001 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_5!");
3002 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3004 if (asserted & ATTN_GENERAL_ATTN_6) {
3005 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_6!");
3006 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3011 if (sc->devinfo.int_block == INT_BLOCK_HC) {
3013 (HC_REG_COMMAND_REG + port * 32 +
3014 COMMAND_REG_ATTN_BITS_SET);
3016 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER * 8);
3019 PMD_DRV_LOG(DEBUG, "about to mask 0x%08x at %s addr 0x%08x",
3021 (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
3023 REG_WR(sc, reg_addr, asserted);
3025 /* now set back the mask */
3026 if (asserted & ATTN_NIG_FOR_FUNC) {
3028 * Verify that IGU ack through BAR was written before restoring
3029 * NIG mask. This loop should exit after 2-3 iterations max.
3031 if (sc->devinfo.int_block != INT_BLOCK_HC) {
3036 REG_RD(sc, IGU_REG_ATTENTION_ACK_BITS);
3037 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0)
3038 && (++cnt < MAX_IGU_ATTN_ACK_TO));
3042 "Failed to verify IGU ack on time");
3048 REG_WR(sc, nig_int_mask_addr, nig_mask);
3054 bnx2x_print_next_block(__rte_unused struct bnx2x_softc *sc, __rte_unused int idx,
3055 __rte_unused const char *blk)
3057 PMD_DRV_LOG(INFO, "%s%s", idx ? ", " : "", blk);
3061 bnx2x_check_blocks_with_parity0(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3064 uint32_t cur_bit = 0;
3067 for (i = 0; sig; i++) {
3068 cur_bit = ((uint32_t) 0x1 << i);
3069 if (sig & cur_bit) {
3071 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3073 bnx2x_print_next_block(sc, par_num++,
3076 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3078 bnx2x_print_next_block(sc, par_num++,
3081 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3083 bnx2x_print_next_block(sc, par_num++,
3086 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3088 bnx2x_print_next_block(sc, par_num++,
3091 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3093 bnx2x_print_next_block(sc, par_num++,
3096 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3098 bnx2x_print_next_block(sc, par_num++,
3101 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3103 bnx2x_print_next_block(sc, par_num++,
3117 bnx2x_check_blocks_with_parity1(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3118 uint8_t * global, uint8_t print)
3121 uint32_t cur_bit = 0;
3122 for (i = 0; sig; i++) {
3123 cur_bit = ((uint32_t) 0x1 << i);
3124 if (sig & cur_bit) {
3126 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3128 bnx2x_print_next_block(sc, par_num++,
3131 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3133 bnx2x_print_next_block(sc, par_num++,
3136 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3138 bnx2x_print_next_block(sc, par_num++,
3141 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3143 bnx2x_print_next_block(sc, par_num++,
3146 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
3148 bnx2x_print_next_block(sc, par_num++,
3151 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3153 bnx2x_print_next_block(sc, par_num++,
3156 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3158 bnx2x_print_next_block(sc, par_num++,
3161 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
3163 bnx2x_print_next_block(sc, par_num++,
3166 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3168 bnx2x_print_next_block(sc, par_num++,
3172 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3174 bnx2x_print_next_block(sc, par_num++,
3177 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3179 bnx2x_print_next_block(sc, par_num++,
3182 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
3184 bnx2x_print_next_block(sc, par_num++,
3187 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3189 bnx2x_print_next_block(sc, par_num++,
3192 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3194 bnx2x_print_next_block(sc, par_num++,
3197 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3199 bnx2x_print_next_block(sc, par_num++,
3202 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
3204 bnx2x_print_next_block(sc, par_num++,
3218 bnx2x_check_blocks_with_parity2(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3221 uint32_t cur_bit = 0;
3224 for (i = 0; sig; i++) {
3225 cur_bit = ((uint32_t) 0x1 << i);
3226 if (sig & cur_bit) {
3228 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3230 bnx2x_print_next_block(sc, par_num++,
3233 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3235 bnx2x_print_next_block(sc, par_num++,
3238 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3240 bnx2x_print_next_block(sc, par_num++,
3241 "PXPPCICLOCKCLIENT");
3243 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3245 bnx2x_print_next_block(sc, par_num++,
3248 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3250 bnx2x_print_next_block(sc, par_num++,
3253 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
3255 bnx2x_print_next_block(sc, par_num++,
3258 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3260 bnx2x_print_next_block(sc, par_num++,
3263 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3265 bnx2x_print_next_block(sc, par_num++,
3279 bnx2x_check_blocks_with_parity3(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3280 uint8_t * global, uint8_t print)
3282 uint32_t cur_bit = 0;
3285 for (i = 0; sig; i++) {
3286 cur_bit = ((uint32_t) 0x1 << i);
3287 if (sig & cur_bit) {
3289 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3291 bnx2x_print_next_block(sc, par_num++,
3295 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3297 bnx2x_print_next_block(sc, par_num++,
3301 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3303 bnx2x_print_next_block(sc, par_num++,
3307 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3309 bnx2x_print_next_block(sc, par_num++,
3324 bnx2x_check_blocks_with_parity4(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3327 uint32_t cur_bit = 0;
3330 for (i = 0; sig; i++) {
3331 cur_bit = ((uint32_t) 0x1 << i);
3332 if (sig & cur_bit) {
3334 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
3336 bnx2x_print_next_block(sc, par_num++,
3339 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
3341 bnx2x_print_next_block(sc, par_num++,
3355 bnx2x_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print,
3360 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
3361 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
3362 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
3363 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
3364 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
3366 "Parity error: HW block parity attention:"
3367 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x",
3368 (uint32_t) (sig[0] & HW_PRTY_ASSERT_SET_0),
3369 (uint32_t) (sig[1] & HW_PRTY_ASSERT_SET_1),
3370 (uint32_t) (sig[2] & HW_PRTY_ASSERT_SET_2),
3371 (uint32_t) (sig[3] & HW_PRTY_ASSERT_SET_3),
3372 (uint32_t) (sig[4] & HW_PRTY_ASSERT_SET_4));
3375 PMD_DRV_LOG(INFO, "Parity errors detected in blocks: ");
3378 bnx2x_check_blocks_with_parity0(sc, sig[0] &
3379 HW_PRTY_ASSERT_SET_0,
3382 bnx2x_check_blocks_with_parity1(sc, sig[1] &
3383 HW_PRTY_ASSERT_SET_1,
3384 par_num, global, print);
3386 bnx2x_check_blocks_with_parity2(sc, sig[2] &
3387 HW_PRTY_ASSERT_SET_2,
3390 bnx2x_check_blocks_with_parity3(sc, sig[3] &
3391 HW_PRTY_ASSERT_SET_3,
3392 par_num, global, print);
3394 bnx2x_check_blocks_with_parity4(sc, sig[4] &
3395 HW_PRTY_ASSERT_SET_4,
3399 PMD_DRV_LOG(INFO, "");
3408 bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print)
3410 struct attn_route attn = { {0} };
3411 int port = SC_PORT(sc);
3413 attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
3414 attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
3415 attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
3416 attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
3418 if (!CHIP_IS_E1x(sc))
3420 REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
3422 return bnx2x_parity_attn(sc, global, print, attn.sig);
3425 static void bnx2x_attn_int_deasserted4(struct bnx2x_softc *sc, uint32_t attn)
3429 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
3430 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
3431 PMD_DRV_LOG(INFO, "ERROR: PGLUE hw attention 0x%08x", val);
3432 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
3434 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR");
3435 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
3437 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR");
3438 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
3440 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN");
3441 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
3443 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN");
3445 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
3447 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN");
3449 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
3451 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN");
3452 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
3454 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN");
3455 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
3457 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN");
3458 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
3460 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW");
3463 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
3464 val = REG_RD(sc, ATC_REG_ATC_INT_STS_CLR);
3465 PMD_DRV_LOG(INFO, "ERROR: ATC hw attention 0x%08x", val);
3466 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
3468 "ERROR: ATC_ATC_INT_STS_REG_ADDRESS_ERROR");
3469 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
3471 "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND");
3472 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
3474 "ERROR: ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS");
3475 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
3477 "ERROR: ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT");
3478 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
3480 "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR");
3481 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
3483 "ERROR: ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU");
3486 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3487 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
3489 "ERROR: FATAL parity attention set4 0x%08x",
3491 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
3493 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
3497 static void bnx2x_e1h_disable(struct bnx2x_softc *sc)
3499 int port = SC_PORT(sc);
3501 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
3504 static void bnx2x_e1h_enable(struct bnx2x_softc *sc)
3506 int port = SC_PORT(sc);
3508 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3512 * called due to MCP event (on pmf):
3513 * reread new bandwidth configuration
3515 * notify others function about the change
3517 static void bnx2x_config_mf_bw(struct bnx2x_softc *sc)
3519 if (sc->link_vars.link_up) {
3520 bnx2x_cmng_fns_init(sc, TRUE, CMNG_FNS_MINMAX);
3521 bnx2x_link_sync_notify(sc);
3524 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
3527 static void bnx2x_set_mf_bw(struct bnx2x_softc *sc)
3529 bnx2x_config_mf_bw(sc);
3530 bnx2x_fw_command(sc, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3533 static void bnx2x_handle_eee_event(struct bnx2x_softc *sc)
3535 bnx2x_fw_command(sc, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3538 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3540 static void bnx2x_drv_info_ether_stat(struct bnx2x_softc *sc)
3542 struct eth_stats_info *ether_stat = &sc->sp->drv_info_to_mcp.ether_stat;
3544 strncpy(ether_stat->version, BNX2X_DRIVER_VERSION,
3545 ETH_STAT_INFO_VERSION_LEN);
3547 sc->sp_objs[0].mac_obj.get_n_elements(sc, &sc->sp_objs[0].mac_obj,
3548 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3549 ether_stat->mac_local + MAC_PAD,
3552 ether_stat->mtu_size = sc->mtu;
3554 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3555 ether_stat->promiscuous_mode = 0; // (flags & PROMISC) ? 1 : 0;
3557 ether_stat->txq_size = sc->tx_ring_size;
3558 ether_stat->rxq_size = sc->rx_ring_size;
3561 static void bnx2x_handle_drv_info_req(struct bnx2x_softc *sc)
3563 enum drv_info_opcode op_code;
3564 uint32_t drv_info_ctl = SHMEM2_RD(sc, drv_info_control);
3566 /* if drv_info version supported by MFW doesn't match - send NACK */
3567 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3568 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3572 op_code = ((drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3573 DRV_INFO_CONTROL_OP_CODE_SHIFT);
3575 memset(&sc->sp->drv_info_to_mcp, 0, sizeof(union drv_info_to_mcp));
3578 case ETH_STATS_OPCODE:
3579 bnx2x_drv_info_ether_stat(sc);
3581 case FCOE_STATS_OPCODE:
3582 case ISCSI_STATS_OPCODE:
3584 /* if op code isn't supported - send NACK */
3585 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3590 * If we got drv_info attn from MFW then these fields are defined in
3593 SHMEM2_WR(sc, drv_info_host_addr_lo,
3594 U64_LO(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3595 SHMEM2_WR(sc, drv_info_host_addr_hi,
3596 U64_HI(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3598 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3601 static void bnx2x_dcc_event(struct bnx2x_softc *sc, uint32_t dcc_event)
3603 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3605 * This is the only place besides the function initialization
3606 * where the sc->flags can change so it is done without any
3610 mf_info.mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_DISABLED) {
3611 PMD_DRV_LOG(DEBUG, "mf_cfg function disabled");
3612 sc->flags |= BNX2X_MF_FUNC_DIS;
3613 bnx2x_e1h_disable(sc);
3615 PMD_DRV_LOG(DEBUG, "mf_cfg function enabled");
3616 sc->flags &= ~BNX2X_MF_FUNC_DIS;
3617 bnx2x_e1h_enable(sc);
3619 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3622 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3623 bnx2x_config_mf_bw(sc);
3624 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3627 /* Report results to MCP */
3629 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_FAILURE, 0);
3631 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_OK, 0);
3634 static void bnx2x_pmf_update(struct bnx2x_softc *sc)
3636 int port = SC_PORT(sc);
3642 * We need the mb() to ensure the ordering between the writing to
3643 * sc->port.pmf here and reading it from the bnx2x_periodic_task().
3647 /* enable nig attention */
3648 val = (0xff0f | (1 << (SC_VN(sc) + 4)));
3649 if (sc->devinfo.int_block == INT_BLOCK_HC) {
3650 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, val);
3651 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, val);
3652 } else if (!CHIP_IS_E1x(sc)) {
3653 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
3654 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
3657 bnx2x_stats_handle(sc, STATS_EVENT_PMF);
3660 static int bnx2x_mc_assert(struct bnx2x_softc *sc)
3664 __rte_unused uint32_t row0, row1, row2, row3;
3668 REG_RD8(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_INDEX_OFFSET);
3670 PMD_DRV_LOG(ERR, "XSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3672 /* print the asserts */
3673 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3677 BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i));
3680 BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3684 BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3688 BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3691 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3693 "XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3694 i, row3, row2, row1, row0);
3703 REG_RD8(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_INDEX_OFFSET);
3705 PMD_DRV_LOG(ERR, "TSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3708 /* print the asserts */
3709 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3713 BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i));
3716 BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3720 BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3724 BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3727 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3729 "TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3730 i, row3, row2, row1, row0);
3739 REG_RD8(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_INDEX_OFFSET);
3741 PMD_DRV_LOG(ERR, "CSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3744 /* print the asserts */
3745 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3749 BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i));
3752 BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3756 BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3760 BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3763 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3765 "CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3766 i, row3, row2, row1, row0);
3775 REG_RD8(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_INDEX_OFFSET);
3777 PMD_DRV_LOG(ERR, "USTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3780 /* print the asserts */
3781 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3785 BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i));
3788 BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3792 BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3796 BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3799 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3801 "USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3802 i, row3, row2, row1, row0);
3812 static void bnx2x_attn_int_deasserted3(struct bnx2x_softc *sc, uint32_t attn)
3814 int func = SC_FUNC(sc);
3817 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3819 if (attn & BNX2X_PMF_LINK_ASSERT(sc)) {
3821 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
3822 bnx2x_read_mf_cfg(sc);
3823 sc->devinfo.mf_info.mf_config[SC_VN(sc)] =
3825 func_mf_config[SC_ABS_FUNC(sc)].config);
3827 SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_status);
3829 if (val & DRV_STATUS_DCC_EVENT_MASK)
3832 DRV_STATUS_DCC_EVENT_MASK));
3834 if (val & DRV_STATUS_SET_MF_BW)
3835 bnx2x_set_mf_bw(sc);
3837 if (val & DRV_STATUS_DRV_INFO_REQ)
3838 bnx2x_handle_drv_info_req(sc);
3840 if ((sc->port.pmf == 0) && (val & DRV_STATUS_PMF))
3841 bnx2x_pmf_update(sc);
3843 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
3844 bnx2x_handle_eee_event(sc);
3846 if (sc->link_vars.periodic_flags &
3847 ELINK_PERIODIC_FLAGS_LINK_EVENT) {
3848 /* sync with link */
3849 sc->link_vars.periodic_flags &=
3850 ~ELINK_PERIODIC_FLAGS_LINK_EVENT;
3852 bnx2x_link_sync_notify(sc);
3854 bnx2x_link_report(sc);
3858 * Always call it here: bnx2x_link_report() will
3859 * prevent the link indication duplication.
3861 bnx2x_link_status_update(sc);
3863 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3865 PMD_DRV_LOG(ERR, "MC assert!");
3866 bnx2x_mc_assert(sc);
3867 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3868 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3869 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3870 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3871 rte_panic("MC assert!");
3873 } else if (attn & BNX2X_MCP_ASSERT) {
3875 PMD_DRV_LOG(ERR, "MCP assert!");
3876 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3880 "Unknown HW assert! (attn 0x%08x)", attn);
3884 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3885 PMD_DRV_LOG(ERR, "LATCHED attention 0x%08x (masked)", attn);
3886 if (attn & BNX2X_GRC_TIMEOUT) {
3887 val = REG_RD(sc, MISC_REG_GRC_TIMEOUT_ATTN);
3888 PMD_DRV_LOG(ERR, "GRC time-out 0x%08x", val);
3890 if (attn & BNX2X_GRC_RSV) {
3891 val = REG_RD(sc, MISC_REG_GRC_RSV_ATTN);
3892 PMD_DRV_LOG(ERR, "GRC reserved 0x%08x", val);
3894 REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3898 static void bnx2x_attn_int_deasserted2(struct bnx2x_softc *sc, uint32_t attn)
3900 int port = SC_PORT(sc);
3902 uint32_t val0, mask0, val1, mask1;
3905 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3906 val = REG_RD(sc, CFC_REG_CFC_INT_STS_CLR);
3907 PMD_DRV_LOG(ERR, "CFC hw attention 0x%08x", val);
3908 /* CFC error attention */
3910 PMD_DRV_LOG(ERR, "FATAL error from CFC");
3914 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3915 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_0);
3916 PMD_DRV_LOG(ERR, "PXP hw attention-0 0x%08x", val);
3917 /* RQ_USDMDP_FIFO_OVERFLOW */
3918 if (val & 0x18000) {
3919 PMD_DRV_LOG(ERR, "FATAL error from PXP");
3922 if (!CHIP_IS_E1x(sc)) {
3923 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_1);
3924 PMD_DRV_LOG(ERR, "PXP hw attention-1 0x%08x", val);
3927 #define PXP2_EOP_ERROR_BIT PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR
3928 #define AEU_PXP2_HW_INT_BIT AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT
3930 if (attn & AEU_PXP2_HW_INT_BIT) {
3931 /* CQ47854 workaround do not panic on
3932 * PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3934 if (!CHIP_IS_E1x(sc)) {
3935 mask0 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_0);
3936 val1 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_1);
3937 mask1 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_1);
3938 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_0);
3940 * If the olny PXP2_EOP_ERROR_BIT is set in
3941 * STS0 and STS1 - clear it
3943 * probably we lose additional attentions between
3944 * STS0 and STS_CLR0, in this case user will not
3945 * be notified about them
3947 if (val0 & mask0 & PXP2_EOP_ERROR_BIT &&
3949 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
3951 /* print the register, since no one can restore it */
3953 "PXP2_REG_PXP2_INT_STS_CLR_0 0x%08x", val0);
3956 * if PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3959 if (val0 & PXP2_EOP_ERROR_BIT) {
3960 PMD_DRV_LOG(ERR, "PXP2_WR_PGLUE_EOP_ERROR");
3963 * if only PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR is
3964 * set then clear attention from PXP2 block without panic
3966 if (((val0 & mask0) == PXP2_EOP_ERROR_BIT) &&
3967 ((val1 & mask1) == 0))
3968 attn &= ~AEU_PXP2_HW_INT_BIT;
3973 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3974 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3975 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3977 val = REG_RD(sc, reg_offset);
3978 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3979 REG_WR(sc, reg_offset, val);
3982 "FATAL HW block attention set2 0x%x",
3983 (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_2));
3984 rte_panic("HW block attention set2");
3988 static void bnx2x_attn_int_deasserted1(struct bnx2x_softc *sc, uint32_t attn)
3990 int port = SC_PORT(sc);
3994 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3995 val = REG_RD(sc, DORQ_REG_DORQ_INT_STS_CLR);
3996 PMD_DRV_LOG(ERR, "DB hw attention 0x%08x", val);
3997 /* DORQ discard attention */
3999 PMD_DRV_LOG(ERR, "FATAL error from DORQ");
4003 if (attn & HW_INTERRUT_ASSERT_SET_1) {
4004 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4005 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4007 val = REG_RD(sc, reg_offset);
4008 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4009 REG_WR(sc, reg_offset, val);
4012 "FATAL HW block attention set1 0x%08x",
4013 (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_1));
4014 rte_panic("HW block attention set1");
4018 static void bnx2x_attn_int_deasserted0(struct bnx2x_softc *sc, uint32_t attn)
4020 int port = SC_PORT(sc);
4024 reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4025 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
4027 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4028 val = REG_RD(sc, reg_offset);
4029 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4030 REG_WR(sc, reg_offset, val);
4032 PMD_DRV_LOG(WARNING, "SPIO5 hw attention");
4034 /* Fan failure attention */
4035 elink_hw_reset_phy(&sc->link_params);
4036 bnx2x_fan_failure(sc);
4039 if ((attn & sc->link_vars.aeu_int_mask) && sc->port.pmf) {
4040 elink_handle_module_detect_int(&sc->link_params);
4043 if (attn & HW_INTERRUT_ASSERT_SET_0) {
4044 val = REG_RD(sc, reg_offset);
4045 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4046 REG_WR(sc, reg_offset, val);
4048 rte_panic("FATAL HW block attention set0 0x%lx",
4049 (attn & HW_INTERRUT_ASSERT_SET_0));
4053 static void bnx2x_attn_int_deasserted(struct bnx2x_softc *sc, uint32_t deasserted)
4055 struct attn_route attn;
4056 struct attn_route *group_mask;
4057 int port = SC_PORT(sc);
4062 uint8_t global = FALSE;
4065 * Need to take HW lock because MCP or other port might also
4066 * try to handle this event.
4068 bnx2x_acquire_alr(sc);
4070 if (bnx2x_chk_parity_attn(sc, &global, TRUE)) {
4071 sc->recovery_state = BNX2X_RECOVERY_INIT;
4073 /* disable HW interrupts */
4074 bnx2x_int_disable(sc);
4075 bnx2x_release_alr(sc);
4079 attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
4080 attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
4081 attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
4082 attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
4083 if (!CHIP_IS_E1x(sc)) {
4085 REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
4090 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4091 if (deasserted & (1 << index)) {
4092 group_mask = &sc->attn_group[index];
4094 bnx2x_attn_int_deasserted4(sc,
4096 sig[4] & group_mask->sig[4]);
4097 bnx2x_attn_int_deasserted3(sc,
4099 sig[3] & group_mask->sig[3]);
4100 bnx2x_attn_int_deasserted1(sc,
4102 sig[1] & group_mask->sig[1]);
4103 bnx2x_attn_int_deasserted2(sc,
4105 sig[2] & group_mask->sig[2]);
4106 bnx2x_attn_int_deasserted0(sc,
4108 sig[0] & group_mask->sig[0]);
4112 bnx2x_release_alr(sc);
4114 if (sc->devinfo.int_block == INT_BLOCK_HC) {
4115 reg_addr = (HC_REG_COMMAND_REG + port * 32 +
4116 COMMAND_REG_ATTN_BITS_CLR);
4118 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER * 8);
4123 "about to mask 0x%08x at %s addr 0x%08x", val,
4124 (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
4126 REG_WR(sc, reg_addr, val);
4128 if (~sc->attn_state & deasserted) {
4129 PMD_DRV_LOG(ERR, "IGU error");
4132 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4133 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4135 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4137 aeu_mask = REG_RD(sc, reg_addr);
4139 aeu_mask |= (deasserted & 0x3ff);
4141 REG_WR(sc, reg_addr, aeu_mask);
4142 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4144 sc->attn_state &= ~deasserted;
4147 static void bnx2x_attn_int(struct bnx2x_softc *sc)
4149 /* read local copy of bits */
4150 uint32_t attn_bits = le32toh(sc->def_sb->atten_status_block.attn_bits);
4152 le32toh(sc->def_sb->atten_status_block.attn_bits_ack);
4153 uint32_t attn_state = sc->attn_state;
4155 /* look for changed bits */
4156 uint32_t asserted = attn_bits & ~attn_ack & ~attn_state;
4157 uint32_t deasserted = ~attn_bits & attn_ack & attn_state;
4160 "attn_bits 0x%08x attn_ack 0x%08x asserted 0x%08x deasserted 0x%08x",
4161 attn_bits, attn_ack, asserted, deasserted);
4163 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) {
4164 PMD_DRV_LOG(ERR, "BAD attention state");
4167 /* handle bits that were raised */
4169 bnx2x_attn_int_asserted(sc, asserted);
4173 bnx2x_attn_int_deasserted(sc, deasserted);
4177 static uint16_t bnx2x_update_dsb_idx(struct bnx2x_softc *sc)
4179 struct host_sp_status_block *def_sb = sc->def_sb;
4182 mb(); /* status block is written to by the chip */
4184 if (sc->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
4185 sc->def_att_idx = def_sb->atten_status_block.attn_bits_index;
4186 rc |= BNX2X_DEF_SB_ATT_IDX;
4189 if (sc->def_idx != def_sb->sp_sb.running_index) {
4190 sc->def_idx = def_sb->sp_sb.running_index;
4191 rc |= BNX2X_DEF_SB_IDX;
4199 static struct ecore_queue_sp_obj *bnx2x_cid_to_q_obj(struct bnx2x_softc *sc,
4202 return &sc->sp_objs[CID_TO_FP(cid, sc)].q_obj;
4205 static void bnx2x_handle_mcast_eqe(struct bnx2x_softc *sc)
4207 struct ecore_mcast_ramrod_params rparam;
4210 memset(&rparam, 0, sizeof(rparam));
4212 rparam.mcast_obj = &sc->mcast_obj;
4214 /* clear pending state for the last command */
4215 sc->mcast_obj.raw.clear_pending(&sc->mcast_obj.raw);
4217 /* if there are pending mcast commands - send them */
4218 if (sc->mcast_obj.check_pending(&sc->mcast_obj)) {
4219 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
4222 "Failed to send pending mcast commands (%d)",
4229 bnx2x_handle_classification_eqe(struct bnx2x_softc *sc, union event_ring_elem *elem)
4231 unsigned long ramrod_flags = 0;
4233 uint32_t cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4234 struct ecore_vlan_mac_obj *vlan_mac_obj;
4236 /* always push next commands out, don't wait here */
4237 bnx2x_set_bit(RAMROD_CONT, &ramrod_flags);
4239 switch (le32toh(elem->message.data.eth_event.echo) >> BNX2X_SWCID_SHIFT) {
4240 case ECORE_FILTER_MAC_PENDING:
4241 PMD_DRV_LOG(DEBUG, "Got SETUP_MAC completions");
4242 vlan_mac_obj = &sc->sp_objs[cid].mac_obj;
4245 case ECORE_FILTER_MCAST_PENDING:
4246 PMD_DRV_LOG(DEBUG, "Got SETUP_MCAST completions");
4247 bnx2x_handle_mcast_eqe(sc);
4251 PMD_DRV_LOG(NOTICE, "Unsupported classification command: %d",
4252 elem->message.data.eth_event.echo);
4256 rc = vlan_mac_obj->complete(sc, vlan_mac_obj, elem, &ramrod_flags);
4259 PMD_DRV_LOG(NOTICE, "Failed to schedule new commands (%d)", rc);
4260 } else if (rc > 0) {
4261 PMD_DRV_LOG(DEBUG, "Scheduled next pending commands...");
4265 static void bnx2x_handle_rx_mode_eqe(struct bnx2x_softc *sc)
4267 bnx2x_clear_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
4269 /* send rx_mode command again if was requested */
4270 if (bnx2x_test_and_clear_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state)) {
4271 bnx2x_set_storm_rx_mode(sc);
4275 static void bnx2x_update_eq_prod(struct bnx2x_softc *sc, uint16_t prod)
4277 storm_memset_eq_prod(sc, prod, SC_FUNC(sc));
4278 wmb(); /* keep prod updates ordered */
4281 static void bnx2x_eq_int(struct bnx2x_softc *sc)
4283 uint16_t hw_cons, sw_cons, sw_prod;
4284 union event_ring_elem *elem;
4289 struct ecore_queue_sp_obj *q_obj;
4290 struct ecore_func_sp_obj *f_obj = &sc->func_obj;
4291 struct ecore_raw_obj *rss_raw = &sc->rss_conf_obj.raw;
4293 hw_cons = le16toh(*sc->eq_cons_sb);
4296 * The hw_cons range is 1-255, 257 - the sw_cons range is 0-254, 256.
4297 * when we get to the next-page we need to adjust so the loop
4298 * condition below will be met. The next element is the size of a
4299 * regular element and hence incrementing by 1
4301 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) {
4306 * This function may never run in parallel with itself for a
4307 * specific sc and no need for a read memory barrier here.
4309 sw_cons = sc->eq_cons;
4310 sw_prod = sc->eq_prod;
4314 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4316 elem = &sc->eq[EQ_DESC(sw_cons)];
4318 /* elem CID originates from FW, actually LE */
4319 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4320 opcode = elem->message.opcode;
4322 /* handle eq element */
4324 case EVENT_RING_OPCODE_STAT_QUERY:
4325 PMD_DEBUG_PERIODIC_LOG(DEBUG, "got statistics completion event %d",
4327 /* nothing to do with stats comp */
4330 case EVENT_RING_OPCODE_CFC_DEL:
4331 /* handle according to cid range */
4332 /* we may want to verify here that the sc state is HALTING */
4333 PMD_DRV_LOG(DEBUG, "got delete ramrod for MULTI[%d]",
4335 q_obj = bnx2x_cid_to_q_obj(sc, cid);
4336 if (q_obj->complete_cmd(sc, q_obj, ECORE_Q_CMD_CFC_DEL)) {
4341 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4342 PMD_DRV_LOG(DEBUG, "got STOP TRAFFIC");
4343 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_STOP)) {
4348 case EVENT_RING_OPCODE_START_TRAFFIC:
4349 PMD_DRV_LOG(DEBUG, "got START TRAFFIC");
4350 if (f_obj->complete_cmd
4351 (sc, f_obj, ECORE_F_CMD_TX_START)) {
4356 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
4357 echo = elem->message.data.function_update_event.echo;
4358 if (echo == SWITCH_UPDATE) {
4360 "got FUNC_SWITCH_UPDATE ramrod");
4361 if (f_obj->complete_cmd(sc, f_obj,
4362 ECORE_F_CMD_SWITCH_UPDATE))
4368 "AFEX: ramrod completed FUNCTION_UPDATE");
4369 f_obj->complete_cmd(sc, f_obj,
4370 ECORE_F_CMD_AFEX_UPDATE);
4374 case EVENT_RING_OPCODE_FORWARD_SETUP:
4375 q_obj = &bnx2x_fwd_sp_obj(sc, q_obj);
4376 if (q_obj->complete_cmd(sc, q_obj,
4377 ECORE_Q_CMD_SETUP_TX_ONLY)) {
4382 case EVENT_RING_OPCODE_FUNCTION_START:
4383 PMD_DRV_LOG(DEBUG, "got FUNC_START ramrod");
4384 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_START)) {
4389 case EVENT_RING_OPCODE_FUNCTION_STOP:
4390 PMD_DRV_LOG(DEBUG, "got FUNC_STOP ramrod");
4391 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_STOP)) {
4397 switch (opcode | sc->state) {
4398 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPEN):
4399 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPENING_WAITING_PORT):
4401 elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4402 PMD_DRV_LOG(DEBUG, "got RSS_UPDATE ramrod. CID %d",
4404 rss_raw->clear_pending(rss_raw);
4407 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4408 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4409 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_CLOSING_WAITING_HALT):
4410 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_OPEN):
4411 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_DIAG):
4412 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4414 "got (un)set mac ramrod");
4415 bnx2x_handle_classification_eqe(sc, elem);
4418 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_OPEN):
4419 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_DIAG):
4420 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4422 "got mcast ramrod");
4423 bnx2x_handle_mcast_eqe(sc);
4426 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_OPEN):
4427 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_DIAG):
4428 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4430 "got rx_mode ramrod");
4431 bnx2x_handle_rx_mode_eqe(sc);
4435 /* unknown event log error and continue */
4436 PMD_DRV_LOG(INFO, "Unknown EQ event %d, sc->state 0x%x",
4437 elem->message.opcode, sc->state);
4445 atomic_add_acq_long(&sc->eq_spq_left, spqe_cnt);
4447 sc->eq_cons = sw_cons;
4448 sc->eq_prod = sw_prod;
4450 /* make sure that above mem writes were issued towards the memory */
4453 /* update producer */
4454 bnx2x_update_eq_prod(sc, sc->eq_prod);
4457 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc)
4462 /* what work needs to be performed? */
4463 status = bnx2x_update_dsb_idx(sc);
4466 if (status & BNX2X_DEF_SB_ATT_IDX) {
4467 PMD_DRV_LOG(DEBUG, "---> ATTN INTR <---");
4469 status &= ~BNX2X_DEF_SB_ATT_IDX;
4473 /* SP events: STAT_QUERY and others */
4474 if (status & BNX2X_DEF_SB_IDX) {
4475 /* handle EQ completions */
4476 PMD_DEBUG_PERIODIC_LOG(DEBUG, "---> EQ INTR <---");
4478 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
4479 le16toh(sc->def_idx), IGU_INT_NOP, 1);
4480 status &= ~BNX2X_DEF_SB_IDX;
4483 /* if status is non zero then something went wrong */
4484 if (unlikely(status)) {
4486 "Got an unknown SP interrupt! (0x%04x)", status);
4489 /* ack status block only if something was actually handled */
4490 bnx2x_ack_sb(sc, sc->igu_dsb_id, ATTENTION_ID,
4491 le16toh(sc->def_att_idx), IGU_INT_ENABLE, 1);
4496 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp, int scan_fp)
4498 struct bnx2x_softc *sc = fp->sc;
4499 uint8_t more_rx = FALSE;
4501 /* update the fastpath index */
4502 bnx2x_update_fp_sb_idx(fp);
4505 if (bnx2x_has_rx_work(fp)) {
4506 more_rx = bnx2x_rxeof(sc, fp);
4510 /* still more work to do */
4511 bnx2x_handle_fp_tq(fp, scan_fp);
4516 bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
4517 le16toh(fp->fp_hc_idx), IGU_INT_ENABLE, 1);
4521 * Legacy interrupt entry point.
4523 * Verifies that the controller generated the interrupt and
4524 * then calls a separate routine to handle the various
4525 * interrupt causes: link, RX, and TX.
4527 int bnx2x_intr_legacy(struct bnx2x_softc *sc, int scan_fp)
4529 struct bnx2x_fastpath *fp;
4530 uint32_t status, mask;
4534 * 0 for ustorm, 1 for cstorm
4535 * the bits returned from ack_int() are 0-15
4536 * bit 0 = attention status block
4537 * bit 1 = fast path status block
4538 * a mask of 0x2 or more = tx/rx event
4539 * a mask of 1 = slow path event
4542 status = bnx2x_ack_int(sc);
4544 /* the interrupt is not for us */
4545 if (unlikely(status == 0)) {
4549 PMD_DEBUG_PERIODIC_LOG(DEBUG, "Interrupt status 0x%04x", status);
4550 //bnx2x_dump_status_block(sc);
4552 FOR_EACH_ETH_QUEUE(sc, i) {
4554 mask = (0x2 << (fp->index + CNIC_SUPPORT(sc)));
4555 if (status & mask) {
4556 bnx2x_handle_fp_tq(fp, scan_fp);
4561 if (unlikely(status & 0x1)) {
4562 rc = bnx2x_handle_sp_tq(sc);
4566 if (unlikely(status)) {
4567 PMD_DRV_LOG(WARNING,
4568 "Unexpected fastpath status (0x%08x)!", status);
4574 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc);
4575 static int bnx2x_init_hw_common(struct bnx2x_softc *sc);
4576 static int bnx2x_init_hw_port(struct bnx2x_softc *sc);
4577 static int bnx2x_init_hw_func(struct bnx2x_softc *sc);
4578 static void bnx2x_reset_common(struct bnx2x_softc *sc);
4579 static void bnx2x_reset_port(struct bnx2x_softc *sc);
4580 static void bnx2x_reset_func(struct bnx2x_softc *sc);
4581 static int bnx2x_init_firmware(struct bnx2x_softc *sc);
4582 static void bnx2x_release_firmware(struct bnx2x_softc *sc);
4585 ecore_func_sp_drv_ops bnx2x_func_sp_drv = {
4586 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
4587 .init_hw_cmn = bnx2x_init_hw_common,
4588 .init_hw_port = bnx2x_init_hw_port,
4589 .init_hw_func = bnx2x_init_hw_func,
4591 .reset_hw_cmn = bnx2x_reset_common,
4592 .reset_hw_port = bnx2x_reset_port,
4593 .reset_hw_func = bnx2x_reset_func,
4595 .init_fw = bnx2x_init_firmware,
4596 .release_fw = bnx2x_release_firmware,
4599 static void bnx2x_init_func_obj(struct bnx2x_softc *sc)
4603 PMD_INIT_FUNC_TRACE();
4605 ecore_init_func_obj(sc,
4607 BNX2X_SP(sc, func_rdata),
4608 (phys_addr_t)BNX2X_SP_MAPPING(sc, func_rdata),
4609 BNX2X_SP(sc, func_afex_rdata),
4610 (phys_addr_t)BNX2X_SP_MAPPING(sc, func_afex_rdata),
4611 &bnx2x_func_sp_drv);
4614 static int bnx2x_init_hw(struct bnx2x_softc *sc, uint32_t load_code)
4616 struct ecore_func_state_params func_params = { NULL };
4619 PMD_INIT_FUNC_TRACE();
4621 /* prepare the parameters for function state transitions */
4622 bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
4624 func_params.f_obj = &sc->func_obj;
4625 func_params.cmd = ECORE_F_CMD_HW_INIT;
4627 func_params.params.hw_init.load_phase = load_code;
4630 * Via a plethora of function pointers, we will eventually reach
4631 * bnx2x_init_hw_common(), bnx2x_init_hw_port(), or bnx2x_init_hw_func().
4633 rc = ecore_func_state_change(sc, &func_params);
4639 bnx2x_fill(struct bnx2x_softc *sc, uint32_t addr, int fill, uint32_t len)
4643 if (!(len % 4) && !(addr % 4)) {
4644 for (i = 0; i < len; i += 4) {
4645 REG_WR(sc, (addr + i), fill);
4648 for (i = 0; i < len; i++) {
4649 REG_WR8(sc, (addr + i), fill);
4654 /* writes FP SP data to FW - data_size in dwords */
4656 bnx2x_wr_fp_sb_data(struct bnx2x_softc *sc, int fw_sb_id, uint32_t * sb_data_p,
4661 for (index = 0; index < data_size; index++) {
4663 (BAR_CSTRORM_INTMEM +
4664 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
4665 (sizeof(uint32_t) * index)), *(sb_data_p + index));
4669 static void bnx2x_zero_fp_sb(struct bnx2x_softc *sc, int fw_sb_id)
4671 struct hc_status_block_data_e2 sb_data_e2;
4672 struct hc_status_block_data_e1x sb_data_e1x;
4673 uint32_t *sb_data_p;
4674 uint32_t data_size = 0;
4676 if (!CHIP_IS_E1x(sc)) {
4677 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4678 sb_data_e2.common.state = SB_DISABLED;
4679 sb_data_e2.common.p_func.vf_valid = FALSE;
4680 sb_data_p = (uint32_t *) & sb_data_e2;
4681 data_size = (sizeof(struct hc_status_block_data_e2) /
4684 memset(&sb_data_e1x, 0,
4685 sizeof(struct hc_status_block_data_e1x));
4686 sb_data_e1x.common.state = SB_DISABLED;
4687 sb_data_e1x.common.p_func.vf_valid = FALSE;
4688 sb_data_p = (uint32_t *) & sb_data_e1x;
4689 data_size = (sizeof(struct hc_status_block_data_e1x) /
4693 bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4696 (BAR_CSTRORM_INTMEM + CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id)), 0,
4697 CSTORM_STATUS_BLOCK_SIZE);
4698 bnx2x_fill(sc, (BAR_CSTRORM_INTMEM + CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id)),
4699 0, CSTORM_SYNC_BLOCK_SIZE);
4703 bnx2x_wr_sp_sb_data(struct bnx2x_softc *sc,
4704 struct hc_sp_status_block_data *sp_sb_data)
4709 i < (sizeof(struct hc_sp_status_block_data) / sizeof(uint32_t));
4712 (BAR_CSTRORM_INTMEM +
4713 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(SC_FUNC(sc)) +
4714 (i * sizeof(uint32_t))),
4715 *((uint32_t *) sp_sb_data + i));
4719 static void bnx2x_zero_sp_sb(struct bnx2x_softc *sc)
4721 struct hc_sp_status_block_data sp_sb_data;
4723 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4725 sp_sb_data.state = SB_DISABLED;
4726 sp_sb_data.p_func.vf_valid = FALSE;
4728 bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
4731 (BAR_CSTRORM_INTMEM +
4732 CSTORM_SP_STATUS_BLOCK_OFFSET(SC_FUNC(sc))),
4733 0, CSTORM_SP_STATUS_BLOCK_SIZE);
4735 (BAR_CSTRORM_INTMEM +
4736 CSTORM_SP_SYNC_BLOCK_OFFSET(SC_FUNC(sc))),
4737 0, CSTORM_SP_SYNC_BLOCK_SIZE);
4741 bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, int igu_sb_id,
4744 hc_sm->igu_sb_id = igu_sb_id;
4745 hc_sm->igu_seg_id = igu_seg_id;
4746 hc_sm->timer_value = 0xFF;
4747 hc_sm->time_to_expire = 0xFFFFFFFF;
4750 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
4752 /* zero out state machine indices */
4755 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4758 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4759 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
4760 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
4761 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
4766 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
4767 (SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4770 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
4771 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4772 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
4773 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4774 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
4775 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4776 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
4777 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4781 bnx2x_init_sb(struct bnx2x_softc *sc, phys_addr_t busaddr, int vfid,
4782 uint8_t vf_valid, int fw_sb_id, int igu_sb_id)
4784 struct hc_status_block_data_e2 sb_data_e2;
4785 struct hc_status_block_data_e1x sb_data_e1x;
4786 struct hc_status_block_sm *hc_sm_p;
4787 uint32_t *sb_data_p;
4791 if (CHIP_INT_MODE_IS_BC(sc)) {
4792 igu_seg_id = HC_SEG_ACCESS_NORM;
4794 igu_seg_id = IGU_SEG_ACCESS_NORM;
4797 bnx2x_zero_fp_sb(sc, fw_sb_id);
4799 if (!CHIP_IS_E1x(sc)) {
4800 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4801 sb_data_e2.common.state = SB_ENABLED;
4802 sb_data_e2.common.p_func.pf_id = SC_FUNC(sc);
4803 sb_data_e2.common.p_func.vf_id = vfid;
4804 sb_data_e2.common.p_func.vf_valid = vf_valid;
4805 sb_data_e2.common.p_func.vnic_id = SC_VN(sc);
4806 sb_data_e2.common.same_igu_sb_1b = TRUE;
4807 sb_data_e2.common.host_sb_addr.hi = U64_HI(busaddr);
4808 sb_data_e2.common.host_sb_addr.lo = U64_LO(busaddr);
4809 hc_sm_p = sb_data_e2.common.state_machine;
4810 sb_data_p = (uint32_t *) & sb_data_e2;
4811 data_size = (sizeof(struct hc_status_block_data_e2) /
4813 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
4815 memset(&sb_data_e1x, 0,
4816 sizeof(struct hc_status_block_data_e1x));
4817 sb_data_e1x.common.state = SB_ENABLED;
4818 sb_data_e1x.common.p_func.pf_id = SC_FUNC(sc);
4819 sb_data_e1x.common.p_func.vf_id = 0xff;
4820 sb_data_e1x.common.p_func.vf_valid = FALSE;
4821 sb_data_e1x.common.p_func.vnic_id = SC_VN(sc);
4822 sb_data_e1x.common.same_igu_sb_1b = TRUE;
4823 sb_data_e1x.common.host_sb_addr.hi = U64_HI(busaddr);
4824 sb_data_e1x.common.host_sb_addr.lo = U64_LO(busaddr);
4825 hc_sm_p = sb_data_e1x.common.state_machine;
4826 sb_data_p = (uint32_t *) & sb_data_e1x;
4827 data_size = (sizeof(struct hc_status_block_data_e1x) /
4829 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
4832 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], igu_sb_id, igu_seg_id);
4833 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], igu_sb_id, igu_seg_id);
4835 /* write indices to HW - PCI guarantees endianity of regpairs */
4836 bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4839 static uint8_t bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp)
4841 if (CHIP_IS_E1x(fp->sc)) {
4842 return (fp->cl_id + SC_PORT(fp->sc) * ETH_MAX_RX_CLIENTS_E1H);
4849 bnx2x_rx_ustorm_prods_offset(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
4851 uint32_t offset = BAR_USTRORM_INTMEM;
4854 return (PXP_VF_ADDR_USDM_QUEUES_START +
4855 (sc->acquire_resp.resc.hw_qid[fp->index] *
4856 sizeof(struct ustorm_queue_zone_data)));
4857 } else if (!CHIP_IS_E1x(sc)) {
4858 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
4860 offset += USTORM_RX_PRODS_E1X_OFFSET(SC_PORT(sc), fp->cl_id);
4866 static void bnx2x_init_eth_fp(struct bnx2x_softc *sc, int idx)
4868 struct bnx2x_fastpath *fp = &sc->fp[idx];
4869 uint32_t cids[ECORE_MULTI_TX_COS] = { 0 };
4870 unsigned long q_type = 0;
4876 fp->igu_sb_id = (sc->igu_base_sb + idx + CNIC_SUPPORT(sc));
4877 fp->fw_sb_id = (sc->base_fw_ndsb + idx + CNIC_SUPPORT(sc));
4879 if (CHIP_IS_E1x(sc))
4880 fp->cl_id = SC_L_ID(sc) + idx;
4882 /* want client ID same as IGU SB ID for non-E1 */
4883 fp->cl_id = fp->igu_sb_id;
4884 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
4886 /* setup sb indices */
4887 if (!CHIP_IS_E1x(sc)) {
4888 fp->sb_index_values = fp->status_block.e2_sb->sb.index_values;
4889 fp->sb_running_index = fp->status_block.e2_sb->sb.running_index;
4891 fp->sb_index_values = fp->status_block.e1x_sb->sb.index_values;
4892 fp->sb_running_index =
4893 fp->status_block.e1x_sb->sb.running_index;
4897 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(sc, fp);
4899 fp->rx_cq_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS];
4901 for (cos = 0; cos < sc->max_cos; cos++) {
4904 fp->tx_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0];
4906 /* nothing more for a VF to do */
4911 bnx2x_init_sb(sc, fp->sb_dma.paddr, BNX2X_VF_ID_INVALID, FALSE,
4912 fp->fw_sb_id, fp->igu_sb_id);
4914 bnx2x_update_fp_sb_idx(fp);
4916 /* Configure Queue State object */
4917 bnx2x_set_bit(ECORE_Q_TYPE_HAS_RX, &q_type);
4918 bnx2x_set_bit(ECORE_Q_TYPE_HAS_TX, &q_type);
4920 ecore_init_queue_obj(sc,
4921 &sc->sp_objs[idx].q_obj,
4926 BNX2X_SP(sc, q_rdata),
4927 (phys_addr_t)BNX2X_SP_MAPPING(sc, q_rdata),
4930 /* configure classification DBs */
4931 ecore_init_mac_obj(sc,
4932 &sc->sp_objs[idx].mac_obj,
4936 BNX2X_SP(sc, mac_rdata),
4937 (phys_addr_t)BNX2X_SP_MAPPING(sc, mac_rdata),
4938 ECORE_FILTER_MAC_PENDING, &sc->sp_state,
4939 ECORE_OBJ_TYPE_RX_TX, &sc->macs_pool);
4943 bnx2x_update_rx_prod(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
4944 uint16_t rx_bd_prod, uint16_t rx_cq_prod)
4946 union ustorm_eth_rx_producers rx_prods;
4949 /* update producers */
4950 rx_prods.prod.bd_prod = rx_bd_prod;
4951 rx_prods.prod.cqe_prod = rx_cq_prod;
4952 rx_prods.prod.reserved = 0;
4955 * Make sure that the BD and SGE data is updated before updating the
4956 * producers since FW might read the BD/SGE right after the producer
4958 * This is only applicable for weak-ordered memory model archs such
4959 * as IA-64. The following barrier is also mandatory since FW will
4960 * assumes BDs must have buffers.
4964 for (i = 0; i < (sizeof(rx_prods) / 4); i++) {
4966 (fp->ustorm_rx_prods_offset + (i * 4)),
4967 rx_prods.raw_data[i]);
4970 wmb(); /* keep prod updates ordered */
4973 static void bnx2x_init_rx_rings(struct bnx2x_softc *sc)
4975 struct bnx2x_fastpath *fp;
4977 struct bnx2x_rx_queue *rxq;
4979 for (i = 0; i < sc->num_queues; i++) {
4981 rxq = sc->rx_queues[fp->index];
4983 PMD_RX_LOG(ERR, "RX queue is NULL");
4987 rxq->rx_bd_head = 0;
4988 rxq->rx_bd_tail = rxq->nb_rx_desc;
4989 rxq->rx_cq_head = 0;
4990 rxq->rx_cq_tail = TOTAL_RCQ_ENTRIES(rxq);
4991 *fp->rx_cq_cons_sb = 0;
4994 * Activate the BD ring...
4995 * Warning, this will generate an interrupt (to the TSTORM)
4996 * so this can only be done after the chip is initialized
4998 bnx2x_update_rx_prod(sc, fp, rxq->rx_bd_tail, rxq->rx_cq_tail);
5006 static void bnx2x_init_tx_ring_one(struct bnx2x_fastpath *fp)
5008 struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
5010 fp->tx_db.data.header.header = 1 << DOORBELL_HDR_DB_TYPE_SHIFT;
5011 fp->tx_db.data.zero_fill1 = 0;
5012 fp->tx_db.data.prod = 0;
5015 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
5019 txq->tx_pkt_tail = 0;
5020 txq->tx_pkt_head = 0;
5021 txq->tx_bd_tail = 0;
5022 txq->tx_bd_head = 0;
5025 static void bnx2x_init_tx_rings(struct bnx2x_softc *sc)
5029 for (i = 0; i < sc->num_queues; i++) {
5030 bnx2x_init_tx_ring_one(&sc->fp[i]);
5034 static void bnx2x_init_def_sb(struct bnx2x_softc *sc)
5036 struct host_sp_status_block *def_sb = sc->def_sb;
5037 phys_addr_t mapping = sc->def_sb_dma.paddr;
5038 int igu_sp_sb_index;
5040 int port = SC_PORT(sc);
5041 int func = SC_FUNC(sc);
5042 int reg_offset, reg_offset_en5;
5045 struct hc_sp_status_block_data sp_sb_data;
5047 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5049 if (CHIP_INT_MODE_IS_BC(sc)) {
5050 igu_sp_sb_index = DEF_SB_IGU_ID;
5051 igu_seg_id = HC_SEG_ACCESS_DEF;
5053 igu_sp_sb_index = sc->igu_dsb_id;
5054 igu_seg_id = IGU_SEG_ACCESS_DEF;
5058 section = ((uint64_t) mapping +
5059 offsetof(struct host_sp_status_block, atten_status_block));
5060 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5063 reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5064 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
5066 reg_offset_en5 = (port) ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5067 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0;
5069 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5070 /* take care of sig[0]..sig[4] */
5071 for (sindex = 0; sindex < 4; sindex++) {
5072 sc->attn_group[index].sig[sindex] =
5074 (reg_offset + (sindex * 0x4) +
5078 if (!CHIP_IS_E1x(sc)) {
5080 * enable5 is separate from the rest of the registers,
5081 * and the address skip is 4 and not 16 between the
5084 sc->attn_group[index].sig[4] =
5085 REG_RD(sc, (reg_offset_en5 + (0x4 * index)));
5087 sc->attn_group[index].sig[4] = 0;
5091 if (sc->devinfo.int_block == INT_BLOCK_HC) {
5093 port ? HC_REG_ATTN_MSG1_ADDR_L : HC_REG_ATTN_MSG0_ADDR_L;
5094 REG_WR(sc, reg_offset, U64_LO(section));
5095 REG_WR(sc, (reg_offset + 4), U64_HI(section));
5096 } else if (!CHIP_IS_E1x(sc)) {
5097 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5098 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5101 section = ((uint64_t) mapping +
5102 offsetof(struct host_sp_status_block, sp_sb));
5104 bnx2x_zero_sp_sb(sc);
5106 /* PCI guarantees endianity of regpair */
5107 sp_sb_data.state = SB_ENABLED;
5108 sp_sb_data.host_sb_addr.lo = U64_LO(section);
5109 sp_sb_data.host_sb_addr.hi = U64_HI(section);
5110 sp_sb_data.igu_sb_id = igu_sp_sb_index;
5111 sp_sb_data.igu_seg_id = igu_seg_id;
5112 sp_sb_data.p_func.pf_id = func;
5113 sp_sb_data.p_func.vnic_id = SC_VN(sc);
5114 sp_sb_data.p_func.vf_id = 0xff;
5116 bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
5118 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5121 static void bnx2x_init_sp_ring(struct bnx2x_softc *sc)
5123 atomic_store_rel_long(&sc->cq_spq_left, MAX_SPQ_PENDING);
5124 sc->spq_prod_idx = 0;
5126 &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_ETH_DEF_CONS];
5127 sc->spq_prod_bd = sc->spq;
5128 sc->spq_last_bd = (sc->spq_prod_bd + MAX_SP_DESC_CNT);
5131 static void bnx2x_init_eq_ring(struct bnx2x_softc *sc)
5133 union event_ring_elem *elem;
5136 for (i = 1; i <= NUM_EQ_PAGES; i++) {
5137 elem = &sc->eq[EQ_DESC_CNT_PAGE * i - 1];
5139 elem->next_page.addr.hi = htole32(U64_HI(sc->eq_dma.paddr +
5141 (i % NUM_EQ_PAGES)));
5142 elem->next_page.addr.lo = htole32(U64_LO(sc->eq_dma.paddr +
5144 (i % NUM_EQ_PAGES)));
5148 sc->eq_prod = NUM_EQ_DESC;
5149 sc->eq_cons_sb = &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_EQ_CONS];
5151 atomic_store_rel_long(&sc->eq_spq_left,
5152 (min((MAX_SP_DESC_CNT - MAX_SPQ_PENDING),
5156 static void bnx2x_init_internal_common(struct bnx2x_softc *sc)
5162 * In switch independent mode, the TSTORM needs to accept
5163 * packets that failed classification, since approximate match
5164 * mac addresses aren't written to NIG LLH.
5167 (BAR_TSTRORM_INTMEM +
5168 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 2);
5171 (BAR_TSTRORM_INTMEM +
5172 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 0);
5175 * Zero this manually as its initialization is currently missing
5178 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) {
5180 (BAR_USTRORM_INTMEM + USTORM_AGG_DATA_OFFSET + (i * 4)),
5184 if (!CHIP_IS_E1x(sc)) {
5185 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET),
5186 CHIP_INT_MODE_IS_BC(sc) ? HC_IGU_BC_MODE :
5191 static void bnx2x_init_internal(struct bnx2x_softc *sc, uint32_t load_code)
5193 switch (load_code) {
5194 case FW_MSG_CODE_DRV_LOAD_COMMON:
5195 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5196 bnx2x_init_internal_common(sc);
5199 case FW_MSG_CODE_DRV_LOAD_PORT:
5203 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5204 /* internal memory per function is initialized inside bnx2x_pf_init */
5208 PMD_DRV_LOG(NOTICE, "Unknown load_code (0x%x) from MCP",
5215 storm_memset_func_cfg(struct bnx2x_softc *sc,
5216 struct tstorm_eth_function_common_config *tcfg,
5222 addr = (BAR_TSTRORM_INTMEM +
5223 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid));
5224 size = sizeof(struct tstorm_eth_function_common_config);
5225 ecore_storm_memset_struct(sc, addr, size, (uint32_t *) tcfg);
5228 static void bnx2x_func_init(struct bnx2x_softc *sc, struct bnx2x_func_init_params *p)
5230 struct tstorm_eth_function_common_config tcfg = { 0 };
5232 if (CHIP_IS_E1x(sc)) {
5233 storm_memset_func_cfg(sc, &tcfg, p->func_id);
5236 /* Enable the function in the FW */
5237 storm_memset_vf_to_pf(sc, p->func_id, p->pf_id);
5238 storm_memset_func_en(sc, p->func_id, 1);
5241 if (p->func_flgs & FUNC_FLG_SPQ) {
5242 storm_memset_spq_addr(sc, p->spq_map, p->func_id);
5244 (XSEM_REG_FAST_MEMORY +
5245 XSTORM_SPQ_PROD_OFFSET(p->func_id)), p->spq_prod);
5250 * Calculates the sum of vn_min_rates.
5251 * It's needed for further normalizing of the min_rates.
5253 * sum of vn_min_rates.
5255 * 0 - if all the min_rates are 0.
5256 * In the later case fainess algorithm should be deactivated.
5257 * If all min rates are not zero then those that are zeroes will be set to 1.
5259 static void bnx2x_calc_vn_min(struct bnx2x_softc *sc, struct cmng_init_input *input)
5262 uint32_t vn_min_rate;
5266 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5267 vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5268 vn_min_rate = (((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
5269 FUNC_MF_CFG_MIN_BW_SHIFT) * 100);
5271 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5272 /* skip hidden VNs */
5274 } else if (!vn_min_rate) {
5275 /* If min rate is zero - set it to 100 */
5276 vn_min_rate = DEF_MIN_RATE;
5281 input->vnic_min_rate[vn] = vn_min_rate;
5284 /* if ETS or all min rates are zeros - disable fairness */
5286 input->flags.cmng_enables &= ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5288 input->flags.cmng_enables |= CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5293 bnx2x_extract_max_cfg(__rte_unused struct bnx2x_softc *sc, uint32_t mf_cfg)
5295 uint16_t max_cfg = ((mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
5296 FUNC_MF_CFG_MAX_BW_SHIFT);
5300 "Max BW configured to 0 - using 100 instead");
5308 bnx2x_calc_vn_max(struct bnx2x_softc *sc, int vn, struct cmng_init_input *input)
5310 uint16_t vn_max_rate;
5311 uint32_t vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5314 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5317 max_cfg = bnx2x_extract_max_cfg(sc, vn_cfg);
5320 /* max_cfg in percents of linkspeed */
5322 ((sc->link_vars.line_speed * max_cfg) / 100);
5323 } else { /* SD modes */
5324 /* max_cfg is absolute in 100Mb units */
5325 vn_max_rate = (max_cfg * 100);
5329 input->vnic_max_rate[vn] = vn_max_rate;
5333 bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg, uint8_t cmng_type)
5335 struct cmng_init_input input;
5338 memset(&input, 0, sizeof(struct cmng_init_input));
5340 input.port_rate = sc->link_vars.line_speed;
5342 if (cmng_type == CMNG_FNS_MINMAX) {
5343 /* read mf conf from shmem */
5345 bnx2x_read_mf_cfg(sc);
5348 /* get VN min rate and enable fairness if not 0 */
5349 bnx2x_calc_vn_min(sc, &input);
5351 /* get VN max rate */
5353 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5354 bnx2x_calc_vn_max(sc, vn, &input);
5358 /* always enable rate shaping and fairness */
5359 input.flags.cmng_enables |= CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
5361 ecore_init_cmng(&input, &sc->cmng);
5366 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc)
5368 if (CHIP_REV_IS_SLOW(sc)) {
5369 return CMNG_FNS_NONE;
5373 return CMNG_FNS_MINMAX;
5376 return CMNG_FNS_NONE;
5380 storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng, uint8_t port)
5387 addr = (BAR_XSTRORM_INTMEM + XSTORM_CMNG_PER_PORT_VARS_OFFSET(port));
5388 size = sizeof(struct cmng_struct_per_port);
5389 ecore_storm_memset_struct(sc, addr, size, (uint32_t *) & cmng->port);
5391 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5392 func = func_by_vn(sc, vn);
5394 addr = (BAR_XSTRORM_INTMEM +
5395 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func));
5396 size = sizeof(struct rate_shaping_vars_per_vn);
5397 ecore_storm_memset_struct(sc, addr, size,
5398 (uint32_t *) & cmng->
5399 vnic.vnic_max_rate[vn]);
5401 addr = (BAR_XSTRORM_INTMEM +
5402 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func));
5403 size = sizeof(struct fairness_vars_per_vn);
5404 ecore_storm_memset_struct(sc, addr, size,
5405 (uint32_t *) & cmng->
5406 vnic.vnic_min_rate[vn]);
5410 static void bnx2x_pf_init(struct bnx2x_softc *sc)
5412 struct bnx2x_func_init_params func_init;
5413 struct event_ring_data eq_data;
5416 memset(&eq_data, 0, sizeof(struct event_ring_data));
5417 memset(&func_init, 0, sizeof(struct bnx2x_func_init_params));
5419 if (!CHIP_IS_E1x(sc)) {
5420 /* reset IGU PF statistics: MSIX + ATTN */
5423 (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5424 (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5425 ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5429 (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5430 (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5431 (BNX2X_IGU_STAS_MSG_PF_CNT * 4) +
5432 ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5436 /* function setup flags */
5437 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
5439 func_init.func_flgs = flags;
5440 func_init.pf_id = SC_FUNC(sc);
5441 func_init.func_id = SC_FUNC(sc);
5442 func_init.spq_map = sc->spq_dma.paddr;
5443 func_init.spq_prod = sc->spq_prod_idx;
5445 bnx2x_func_init(sc, &func_init);
5447 memset(&sc->cmng, 0, sizeof(struct cmng_struct_per_port));
5450 * Congestion management values depend on the link rate.
5451 * There is no active link so initial link rate is set to 10Gbps.
5452 * When the link comes up the congestion management values are
5453 * re-calculated according to the actual link rate.
5455 sc->link_vars.line_speed = SPEED_10000;
5456 bnx2x_cmng_fns_init(sc, TRUE, bnx2x_get_cmng_fns_mode(sc));
5458 /* Only the PMF sets the HW */
5460 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
5463 /* init Event Queue - PCI bus guarantees correct endainity */
5464 eq_data.base_addr.hi = U64_HI(sc->eq_dma.paddr);
5465 eq_data.base_addr.lo = U64_LO(sc->eq_dma.paddr);
5466 eq_data.producer = sc->eq_prod;
5467 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
5468 eq_data.sb_id = DEF_SB_ID;
5469 storm_memset_eq_data(sc, &eq_data, SC_FUNC(sc));
5472 static void bnx2x_hc_int_enable(struct bnx2x_softc *sc)
5474 int port = SC_PORT(sc);
5475 uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5476 uint32_t val = REG_RD(sc, addr);
5477 uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5478 || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5479 uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5480 uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5483 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5484 HC_CONFIG_0_REG_INT_LINE_EN_0);
5485 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5486 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5488 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
5491 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
5492 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5493 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5494 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5496 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5497 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5498 HC_CONFIG_0_REG_INT_LINE_EN_0 |
5499 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5501 REG_WR(sc, addr, val);
5503 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
5506 REG_WR(sc, addr, val);
5508 /* ensure that HC_CONFIG is written before leading/trailing edge config */
5511 /* init leading/trailing edge */
5513 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5515 /* enable nig and gpio3 attention */
5522 REG_WR(sc, (HC_REG_TRAILING_EDGE_0 + port * 8), val);
5523 REG_WR(sc, (HC_REG_LEADING_EDGE_0 + port * 8), val);
5525 /* make sure that interrupts are indeed enabled from here on */
5529 static void bnx2x_igu_int_enable(struct bnx2x_softc *sc)
5532 uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5533 || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5534 uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5535 uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5537 val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5540 val &= ~(IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5541 val |= (IGU_PF_CONF_MSI_MSIX_EN | IGU_PF_CONF_ATTN_BIT_EN);
5543 val |= IGU_PF_CONF_SINGLE_ISR_EN;
5546 val &= ~IGU_PF_CONF_INT_LINE_EN;
5547 val |= (IGU_PF_CONF_MSI_MSIX_EN |
5548 IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5550 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
5551 val |= (IGU_PF_CONF_INT_LINE_EN |
5552 IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5555 /* clean previous status - need to configure igu prior to ack */
5556 if ((!msix) || single_msix) {
5557 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5561 val |= IGU_PF_CONF_FUNC_EN;
5563 PMD_DRV_LOG(DEBUG, "write 0x%x to IGU mode %s",
5564 val, ((msix) ? "MSI-X" : ((msi) ? "MSI" : "INTx")));
5566 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5570 /* init leading/trailing edge */
5572 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5574 /* enable nig and gpio3 attention */
5581 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
5582 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
5584 /* make sure that interrupts are indeed enabled from here on */
5588 static void bnx2x_int_enable(struct bnx2x_softc *sc)
5590 if (sc->devinfo.int_block == INT_BLOCK_HC) {
5591 bnx2x_hc_int_enable(sc);
5593 bnx2x_igu_int_enable(sc);
5597 static void bnx2x_hc_int_disable(struct bnx2x_softc *sc)
5599 int port = SC_PORT(sc);
5600 uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5601 uint32_t val = REG_RD(sc, addr);
5603 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5604 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5605 HC_CONFIG_0_REG_INT_LINE_EN_0 | HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5606 /* flush all outstanding writes */
5609 REG_WR(sc, addr, val);
5610 if (REG_RD(sc, addr) != val) {
5611 PMD_DRV_LOG(ERR, "proper val not read from HC IGU!");
5615 static void bnx2x_igu_int_disable(struct bnx2x_softc *sc)
5617 uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5619 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
5620 IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_ATTN_BIT_EN);
5622 PMD_DRV_LOG(DEBUG, "write %x to IGU", val);
5624 /* flush all outstanding writes */
5627 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5628 if (REG_RD(sc, IGU_REG_PF_CONFIGURATION) != val) {
5629 PMD_DRV_LOG(ERR, "proper val not read from IGU!");
5633 static void bnx2x_int_disable(struct bnx2x_softc *sc)
5635 if (sc->devinfo.int_block == INT_BLOCK_HC) {
5636 bnx2x_hc_int_disable(sc);
5638 bnx2x_igu_int_disable(sc);
5642 static void bnx2x_nic_init(struct bnx2x_softc *sc, int load_code)
5646 PMD_INIT_FUNC_TRACE();
5648 for (i = 0; i < sc->num_queues; i++) {
5649 bnx2x_init_eth_fp(sc, i);
5652 rmb(); /* ensure status block indices were read */
5654 bnx2x_init_rx_rings(sc);
5655 bnx2x_init_tx_rings(sc);
5658 bnx2x_memset_stats(sc);
5662 /* initialize MOD_ABS interrupts */
5663 elink_init_mod_abs_int(sc, &sc->link_vars,
5664 sc->devinfo.chip_id,
5665 sc->devinfo.shmem_base,
5666 sc->devinfo.shmem2_base, SC_PORT(sc));
5668 bnx2x_init_def_sb(sc);
5669 bnx2x_update_dsb_idx(sc);
5670 bnx2x_init_sp_ring(sc);
5671 bnx2x_init_eq_ring(sc);
5672 bnx2x_init_internal(sc, load_code);
5674 bnx2x_stats_init(sc);
5676 /* flush all before enabling interrupts */
5679 bnx2x_int_enable(sc);
5681 /* check for SPIO5 */
5682 bnx2x_attn_int_deasserted0(sc,
5684 (MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
5686 AEU_INPUTS_ATTN_BITS_SPIO5);
5689 static void bnx2x_init_objs(struct bnx2x_softc *sc)
5691 /* mcast rules must be added to tx if tx switching is enabled */
5692 ecore_obj_type o_type;
5693 if (sc->flags & BNX2X_TX_SWITCHING)
5694 o_type = ECORE_OBJ_TYPE_RX_TX;
5696 o_type = ECORE_OBJ_TYPE_RX;
5698 /* RX_MODE controlling object */
5699 ecore_init_rx_mode_obj(sc, &sc->rx_mode_obj);
5701 /* multicast configuration controlling object */
5702 ecore_init_mcast_obj(sc,
5708 BNX2X_SP(sc, mcast_rdata),
5709 (phys_addr_t)BNX2X_SP_MAPPING(sc, mcast_rdata),
5710 ECORE_FILTER_MCAST_PENDING,
5711 &sc->sp_state, o_type);
5713 /* Setup CAM credit pools */
5714 ecore_init_mac_credit_pool(sc,
5717 CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5718 VNICS_PER_PATH(sc));
5720 ecore_init_vlan_credit_pool(sc,
5722 SC_ABS_FUNC(sc) >> 1,
5723 CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5724 VNICS_PER_PATH(sc));
5726 /* RSS configuration object */
5727 ecore_init_rss_config_obj(&sc->rss_conf_obj,
5732 BNX2X_SP(sc, rss_rdata),
5733 (phys_addr_t)BNX2X_SP_MAPPING(sc, rss_rdata),
5734 ECORE_FILTER_RSS_CONF_PENDING,
5735 &sc->sp_state, ECORE_OBJ_TYPE_RX);
5739 * Initialize the function. This must be called before sending CLIENT_SETUP
5740 * for the first client.
5742 static int bnx2x_func_start(struct bnx2x_softc *sc)
5744 struct ecore_func_state_params func_params = { NULL };
5745 struct ecore_func_start_params *start_params =
5746 &func_params.params.start;
5748 /* Prepare parameters for function state transitions */
5749 bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
5751 func_params.f_obj = &sc->func_obj;
5752 func_params.cmd = ECORE_F_CMD_START;
5754 /* Function parameters */
5755 start_params->mf_mode = sc->devinfo.mf_info.mf_mode;
5756 start_params->sd_vlan_tag = OVLAN(sc);
5758 if (CHIP_IS_E2(sc) || CHIP_IS_E3(sc)) {
5759 start_params->network_cos_mode = STATIC_COS;
5760 } else { /* CHIP_IS_E1X */
5761 start_params->network_cos_mode = FW_WRR;
5764 start_params->gre_tunnel_mode = 0;
5765 start_params->gre_tunnel_rss = 0;
5767 return ecore_func_state_change(sc, &func_params);
5770 static int bnx2x_set_power_state(struct bnx2x_softc *sc, uint8_t state)
5774 /* If there is no power capability, silently succeed */
5775 if (!(sc->devinfo.pcie_cap_flags & BNX2X_PM_CAPABLE_FLAG)) {
5776 PMD_DRV_LOG(WARNING, "No power capability");
5780 pci_read(sc, (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS), &pmcsr,
5786 (sc->devinfo.pcie_pm_cap_reg +
5788 ((pmcsr & ~PCIM_PSTAT_DMASK) | PCIM_PSTAT_PME));
5790 if (pmcsr & PCIM_PSTAT_DMASK) {
5791 /* delay required during transition out of D3hot */
5798 /* don't shut down the power for emulation and FPGA */
5799 if (CHIP_REV_IS_SLOW(sc)) {
5803 pmcsr &= ~PCIM_PSTAT_DMASK;
5804 pmcsr |= PCIM_PSTAT_D3;
5807 pmcsr |= PCIM_PSTAT_PMEENABLE;
5811 (sc->devinfo.pcie_pm_cap_reg +
5812 PCIR_POWER_STATUS), pmcsr);
5815 * No more memory access after this point until device is brought back
5821 PMD_DRV_LOG(NOTICE, "Can't support PCI power state = %d",
5829 /* return true if succeeded to acquire the lock */
5830 static uint8_t bnx2x_trylock_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
5832 uint32_t lock_status;
5833 uint32_t resource_bit = (1 << resource);
5834 int func = SC_FUNC(sc);
5835 uint32_t hw_lock_control_reg;
5837 /* Validating that the resource is within range */
5838 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
5840 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)",
5841 resource, HW_LOCK_MAX_RESOURCE_VALUE);
5846 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func * 8);
5848 hw_lock_control_reg =
5849 (MISC_REG_DRIVER_CONTROL_7 + (func - 6) * 8);
5852 /* try to acquire the lock */
5853 REG_WR(sc, hw_lock_control_reg + 4, resource_bit);
5854 lock_status = REG_RD(sc, hw_lock_control_reg);
5855 if (lock_status & resource_bit) {
5859 PMD_DRV_LOG(NOTICE, "Failed to get a resource lock 0x%x", resource);
5865 * Get the recovery leader resource id according to the engine this function
5866 * belongs to. Currently only only 2 engines is supported.
5868 static int bnx2x_get_leader_lock_resource(struct bnx2x_softc *sc)
5871 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
5873 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
5877 /* try to acquire a leader lock for current engine */
5878 static uint8_t bnx2x_trylock_leader_lock(struct bnx2x_softc *sc)
5880 return bnx2x_trylock_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5883 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc)
5885 return bnx2x_release_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5888 /* close gates #2, #3 and #4 */
5889 static void bnx2x_set_234_gates(struct bnx2x_softc *sc, uint8_t close)
5893 /* gates #2 and #4a are closed/opened */
5895 REG_WR(sc, PXP_REG_HST_DISCARD_DOORBELLS, ! !close);
5897 REG_WR(sc, PXP_REG_HST_DISCARD_INTERNAL_WRITES, ! !close);
5900 if (CHIP_IS_E1x(sc)) {
5901 /* prevent interrupts from HC on both ports */
5902 val = REG_RD(sc, HC_REG_CONFIG_1);
5904 REG_WR(sc, HC_REG_CONFIG_1, (val & ~(uint32_t)
5905 HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5907 REG_WR(sc, HC_REG_CONFIG_1,
5908 (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5910 val = REG_RD(sc, HC_REG_CONFIG_0);
5912 REG_WR(sc, HC_REG_CONFIG_0, (val & ~(uint32_t)
5913 HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5915 REG_WR(sc, HC_REG_CONFIG_0,
5916 (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5919 /* Prevent incomming interrupts in IGU */
5920 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
5923 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5925 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5927 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5929 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5935 /* poll for pending writes bit, it should get cleared in no more than 1s */
5936 static int bnx2x_er_poll_igu_vq(struct bnx2x_softc *sc)
5938 uint32_t cnt = 1000;
5939 uint32_t pend_bits = 0;
5942 pend_bits = REG_RD(sc, IGU_REG_PENDING_BITS_STATUS);
5944 if (pend_bits == 0) {
5949 } while (cnt-- > 0);
5952 PMD_DRV_LOG(NOTICE, "Still pending IGU requests bits=0x%08x!",
5960 #define SHARED_MF_CLP_MAGIC 0x80000000 /* 'magic' bit */
5962 static void bnx2x_clp_reset_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
5964 /* Do some magic... */
5965 uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
5966 *magic_val = val & SHARED_MF_CLP_MAGIC;
5967 MFCFG_WR(sc, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
5970 /* restore the value of the 'magic' bit */
5971 static void bnx2x_clp_reset_done(struct bnx2x_softc *sc, uint32_t magic_val)
5973 /* Restore the 'magic' bit value... */
5974 uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
5975 MFCFG_WR(sc, shared_mf_config.clp_mb,
5976 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
5979 /* prepare for MCP reset, takes care of CLP configurations */
5980 static void bnx2x_reset_mcp_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
5983 uint32_t validity_offset;
5985 /* set `magic' bit in order to save MF config */
5986 bnx2x_clp_reset_prep(sc, magic_val);
5988 /* get shmem offset */
5989 shmem = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
5991 offsetof(struct shmem_region, validity_map[SC_PORT(sc)]);
5993 /* Clear validity map flags */
5995 REG_WR(sc, shmem + validity_offset, 0);
5999 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
6000 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
6002 static void bnx2x_mcp_wait_one(struct bnx2x_softc *sc)
6004 /* special handling for emulation and FPGA (10 times longer) */
6005 if (CHIP_REV_IS_SLOW(sc)) {
6006 DELAY((MCP_ONE_TIMEOUT * 10) * 1000);
6008 DELAY((MCP_ONE_TIMEOUT) * 1000);
6012 /* initialize shmem_base and waits for validity signature to appear */
6013 static int bnx2x_init_shmem(struct bnx2x_softc *sc)
6019 sc->devinfo.shmem_base =
6020 sc->link_params.shmem_base =
6021 REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
6023 if (sc->devinfo.shmem_base) {
6024 val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
6025 if (val & SHR_MEM_VALIDITY_MB)
6029 bnx2x_mcp_wait_one(sc);
6031 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
6033 PMD_DRV_LOG(NOTICE, "BAD MCP validity signature");
6038 static int bnx2x_reset_mcp_comp(struct bnx2x_softc *sc, uint32_t magic_val)
6040 int rc = bnx2x_init_shmem(sc);
6042 /* Restore the `magic' bit value */
6043 bnx2x_clp_reset_done(sc, magic_val);
6048 static void bnx2x_pxp_prep(struct bnx2x_softc *sc)
6050 REG_WR(sc, PXP2_REG_RD_START_INIT, 0);
6051 REG_WR(sc, PXP2_REG_RQ_RBC_DONE, 0);
6056 * Reset the whole chip except for:
6058 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by one reset bit)
6060 * - MISC (including AEU)
6064 static void bnx2x_process_kill_chip_reset(struct bnx2x_softc *sc, uint8_t global)
6066 uint32_t not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
6067 uint32_t global_bits2, stay_reset2;
6070 * Bits that have to be set in reset_mask2 if we want to reset 'global'
6071 * (per chip) blocks.
6074 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
6075 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
6078 * Don't reset the following blocks.
6079 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
6080 * reset, as in 4 port device they might still be owned
6081 * by the MCP (there is only one leader per path).
6084 MISC_REGISTERS_RESET_REG_1_RST_HC |
6085 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
6086 MISC_REGISTERS_RESET_REG_1_RST_PXP;
6089 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
6090 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
6091 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
6092 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
6093 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
6094 MISC_REGISTERS_RESET_REG_2_RST_GRC |
6095 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
6096 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
6097 MISC_REGISTERS_RESET_REG_2_RST_ATC |
6098 MISC_REGISTERS_RESET_REG_2_PGLC |
6099 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
6100 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
6101 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
6102 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
6103 MISC_REGISTERS_RESET_REG_2_UMAC0 | MISC_REGISTERS_RESET_REG_2_UMAC1;
6106 * Keep the following blocks in reset:
6107 * - all xxMACs are handled by the elink code.
6110 MISC_REGISTERS_RESET_REG_2_XMAC |
6111 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
6113 /* Full reset masks according to the chip */
6114 reset_mask1 = 0xffffffff;
6116 if (CHIP_IS_E1H(sc))
6117 reset_mask2 = 0x1ffff;
6118 else if (CHIP_IS_E2(sc))
6119 reset_mask2 = 0xfffff;
6120 else /* CHIP_IS_E3 */
6121 reset_mask2 = 0x3ffffff;
6123 /* Don't reset global blocks unless we need to */
6125 reset_mask2 &= ~global_bits2;
6128 * In case of attention in the QM, we need to reset PXP
6129 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
6130 * because otherwise QM reset would release 'close the gates' shortly
6131 * before resetting the PXP, then the PSWRQ would send a write
6132 * request to PGLUE. Then when PXP is reset, PGLUE would try to
6133 * read the payload data from PSWWR, but PSWWR would not
6134 * respond. The write queue in PGLUE would stuck, dmae commands
6135 * would not return. Therefore it's important to reset the second
6136 * reset register (containing the
6137 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
6138 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
6141 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
6142 reset_mask2 & (~not_reset_mask2));
6144 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6145 reset_mask1 & (~not_reset_mask1));
6150 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
6151 reset_mask2 & (~stay_reset2));
6156 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
6160 static int bnx2x_process_kill(struct bnx2x_softc *sc, uint8_t global)
6164 uint32_t sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
6165 uint32_t tags_63_32 = 0;
6167 /* Empty the Tetris buffer, wait for 1s */
6169 sr_cnt = REG_RD(sc, PXP2_REG_RD_SR_CNT);
6170 blk_cnt = REG_RD(sc, PXP2_REG_RD_BLK_CNT);
6171 port_is_idle_0 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_0);
6172 port_is_idle_1 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_1);
6173 pgl_exp_rom2 = REG_RD(sc, PXP2_REG_PGL_EXP_ROM2);
6174 if (CHIP_IS_E3(sc)) {
6175 tags_63_32 = REG_RD(sc, PGLUE_B_REG_TAGS_63_32);
6178 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
6179 ((port_is_idle_0 & 0x1) == 0x1) &&
6180 ((port_is_idle_1 & 0x1) == 0x1) &&
6181 (pgl_exp_rom2 == 0xffffffff) &&
6182 (!CHIP_IS_E3(sc) || (tags_63_32 == 0xffffffff)))
6185 } while (cnt-- > 0);
6189 "ERROR: Tetris buffer didn't get empty or there "
6190 "are still outstanding read requests after 1s! "
6191 "sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, "
6192 "port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x",
6193 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
6200 /* Close gates #2, #3 and #4 */
6201 bnx2x_set_234_gates(sc, TRUE);
6203 /* Poll for IGU VQs for 57712 and newer chips */
6204 if (!CHIP_IS_E1x(sc) && bnx2x_er_poll_igu_vq(sc)) {
6208 /* clear "unprepared" bit */
6209 REG_WR(sc, MISC_REG_UNPREPARED, 0);
6212 /* Make sure all is written to the chip before the reset */
6216 * Wait for 1ms to empty GLUE and PCI-E core queues,
6217 * PSWHST, GRC and PSWRD Tetris buffer.
6221 /* Prepare to chip reset: */
6224 bnx2x_reset_mcp_prep(sc, &val);
6231 /* reset the chip */
6232 bnx2x_process_kill_chip_reset(sc, global);
6235 /* Recover after reset: */
6237 if (global && bnx2x_reset_mcp_comp(sc, val)) {
6241 /* Open the gates #2, #3 and #4 */
6242 bnx2x_set_234_gates(sc, FALSE);
6247 static int bnx2x_leader_reset(struct bnx2x_softc *sc)
6250 uint8_t global = bnx2x_reset_is_global(sc);
6254 * If not going to reset MCP, load "fake" driver to reset HW while
6255 * driver is owner of the HW.
6257 if (!global && !BNX2X_NOMCP(sc)) {
6258 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
6259 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
6261 PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
6263 goto exit_leader_reset;
6266 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
6267 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
6269 "MCP unexpected response, aborting");
6271 goto exit_leader_reset2;
6274 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
6276 PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
6278 goto exit_leader_reset2;
6282 /* try to recover after the failure */
6283 if (bnx2x_process_kill(sc, global)) {
6284 PMD_DRV_LOG(NOTICE, "Something bad occurred on engine %d!",
6287 goto exit_leader_reset2;
6291 * Clear the RESET_IN_PROGRESS and RESET_GLOBAL bits and update the driver
6294 bnx2x_set_reset_done(sc);
6296 bnx2x_clear_reset_global(sc);
6301 /* unload "fake driver" if it was loaded */
6302 if (!global &&!BNX2X_NOMCP(sc)) {
6303 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
6304 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
6310 bnx2x_release_leader_lock(sc);
6317 * prepare INIT transition, parameters configured:
6318 * - HC configuration
6319 * - Queue's CDU context
6322 bnx2x_pf_q_prep_init(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6323 struct ecore_queue_init_params *init_params)
6326 int cxt_index, cxt_offset;
6328 bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->rx.flags);
6329 bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->tx.flags);
6331 bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->rx.flags);
6332 bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->tx.flags);
6335 init_params->rx.hc_rate =
6336 sc->hc_rx_ticks ? (1000000 / sc->hc_rx_ticks) : 0;
6337 init_params->tx.hc_rate =
6338 sc->hc_tx_ticks ? (1000000 / sc->hc_tx_ticks) : 0;
6341 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = fp->fw_sb_id;
6343 /* CQ index among the SB indices */
6344 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6345 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
6347 /* set maximum number of COSs supported by this queue */
6348 init_params->max_cos = sc->max_cos;
6350 /* set the context pointers queue object */
6351 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
6352 cxt_index = fp->index / ILT_PAGE_CIDS;
6353 cxt_offset = fp->index - (cxt_index * ILT_PAGE_CIDS);
6354 init_params->cxts[cos] =
6355 &sc->context[cxt_index].vcxt[cxt_offset].eth;
6359 /* set flags that are common for the Tx-only and not normal connections */
6360 static unsigned long
6361 bnx2x_get_common_flags(struct bnx2x_softc *sc, uint8_t zero_stats)
6363 unsigned long flags = 0;
6365 /* PF driver will always initialize the Queue to an ACTIVE state */
6366 bnx2x_set_bit(ECORE_Q_FLG_ACTIVE, &flags);
6369 * tx only connections collect statistics (on the same index as the
6370 * parent connection). The statistics are zeroed when the parent
6371 * connection is initialized.
6374 bnx2x_set_bit(ECORE_Q_FLG_STATS, &flags);
6376 bnx2x_set_bit(ECORE_Q_FLG_ZERO_STATS, &flags);
6380 * tx only connections can support tx-switching, though their
6381 * CoS-ness doesn't survive the loopback
6383 if (sc->flags & BNX2X_TX_SWITCHING) {
6384 bnx2x_set_bit(ECORE_Q_FLG_TX_SWITCH, &flags);
6387 bnx2x_set_bit(ECORE_Q_FLG_PCSUM_ON_PKT, &flags);
6392 static unsigned long bnx2x_get_q_flags(struct bnx2x_softc *sc, uint8_t leading)
6394 unsigned long flags = 0;
6397 bnx2x_set_bit(ECORE_Q_FLG_OV, &flags);
6401 bnx2x_set_bit(ECORE_Q_FLG_LEADING_RSS, &flags);
6402 bnx2x_set_bit(ECORE_Q_FLG_MCAST, &flags);
6405 bnx2x_set_bit(ECORE_Q_FLG_VLAN, &flags);
6407 /* merge with common flags */
6408 return flags | bnx2x_get_common_flags(sc, TRUE);
6412 bnx2x_pf_q_prep_general(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6413 struct ecore_general_setup_params *gen_init, uint8_t cos)
6415 gen_init->stat_id = bnx2x_stats_id(fp);
6416 gen_init->spcl_id = fp->cl_id;
6417 gen_init->mtu = sc->mtu;
6418 gen_init->cos = cos;
6422 bnx2x_pf_rx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6423 struct rxq_pause_params *pause,
6424 struct ecore_rxq_setup_params *rxq_init)
6426 struct bnx2x_rx_queue *rxq;
6428 rxq = sc->rx_queues[fp->index];
6430 PMD_RX_LOG(ERR, "RX queue is NULL");
6434 pause->bd_th_lo = BD_TH_LO(sc);
6435 pause->bd_th_hi = BD_TH_HI(sc);
6437 pause->rcq_th_lo = RCQ_TH_LO(sc);
6438 pause->rcq_th_hi = RCQ_TH_HI(sc);
6440 /* validate rings have enough entries to cross high thresholds */
6441 if (sc->dropless_fc &&
6442 pause->bd_th_hi + FW_PREFETCH_CNT > sc->rx_ring_size) {
6443 PMD_DRV_LOG(WARNING, "rx bd ring threshold limit");
6446 if (sc->dropless_fc &&
6447 pause->rcq_th_hi + FW_PREFETCH_CNT > USABLE_RCQ_ENTRIES(rxq)) {
6448 PMD_DRV_LOG(WARNING, "rcq ring threshold limit");
6454 rxq_init->dscr_map = (phys_addr_t)rxq->rx_ring_phys_addr;
6455 rxq_init->rcq_map = (phys_addr_t)rxq->cq_ring_phys_addr;
6456 rxq_init->rcq_np_map = (phys_addr_t)(rxq->cq_ring_phys_addr +
6460 * This should be a maximum number of data bytes that may be
6461 * placed on the BD (not including paddings).
6463 rxq_init->buf_sz = (fp->rx_buf_size - IP_HEADER_ALIGNMENT_PADDING);
6465 rxq_init->cl_qzone_id = fp->cl_qzone_id;
6466 rxq_init->rss_engine_id = SC_FUNC(sc);
6467 rxq_init->mcast_engine_id = SC_FUNC(sc);
6469 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
6470 rxq_init->fw_sb_id = fp->fw_sb_id;
6472 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6475 * configure silent vlan removal
6476 * if multi function mode is afex, then mask default vlan
6478 if (IS_MF_AFEX(sc)) {
6479 rxq_init->silent_removal_value =
6480 sc->devinfo.mf_info.afex_def_vlan_tag;
6481 rxq_init->silent_removal_mask = EVL_VLID_MASK;
6486 bnx2x_pf_tx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6487 struct ecore_txq_setup_params *txq_init, uint8_t cos)
6489 struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
6492 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
6495 txq_init->dscr_map = (phys_addr_t)txq->tx_ring_phys_addr;
6496 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
6497 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
6498 txq_init->fw_sb_id = fp->fw_sb_id;
6501 * set the TSS leading client id for TX classfication to the
6502 * leading RSS client id
6504 txq_init->tss_leading_cl_id = BNX2X_FP(sc, 0, cl_id);
6508 * This function performs 2 steps in a queue state machine:
6513 bnx2x_setup_queue(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp, uint8_t leading)
6515 struct ecore_queue_state_params q_params = { NULL };
6516 struct ecore_queue_setup_params *setup_params = &q_params.params.setup;
6519 PMD_DRV_LOG(DEBUG, "setting up queue %d", fp->index);
6521 bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6523 q_params.q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
6525 /* we want to wait for completion in this context */
6526 bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
6528 /* prepare the INIT parameters */
6529 bnx2x_pf_q_prep_init(sc, fp, &q_params.params.init);
6531 /* Set the command */
6532 q_params.cmd = ECORE_Q_CMD_INIT;
6534 /* Change the state to INIT */
6535 rc = ecore_queue_state_change(sc, &q_params);
6537 PMD_DRV_LOG(NOTICE, "Queue(%d) INIT failed", fp->index);
6541 PMD_DRV_LOG(DEBUG, "init complete");
6543 /* now move the Queue to the SETUP state */
6544 memset(setup_params, 0, sizeof(*setup_params));
6546 /* set Queue flags */
6547 setup_params->flags = bnx2x_get_q_flags(sc, leading);
6549 /* set general SETUP parameters */
6550 bnx2x_pf_q_prep_general(sc, fp, &setup_params->gen_params,
6551 FIRST_TX_COS_INDEX);
6553 bnx2x_pf_rx_q_prep(sc, fp,
6554 &setup_params->pause_params,
6555 &setup_params->rxq_params);
6557 bnx2x_pf_tx_q_prep(sc, fp, &setup_params->txq_params, FIRST_TX_COS_INDEX);
6559 /* Set the command */
6560 q_params.cmd = ECORE_Q_CMD_SETUP;
6562 /* change the state to SETUP */
6563 rc = ecore_queue_state_change(sc, &q_params);
6565 PMD_DRV_LOG(NOTICE, "Queue(%d) SETUP failed", fp->index);
6572 static int bnx2x_setup_leading(struct bnx2x_softc *sc)
6575 return bnx2x_setup_queue(sc, &sc->fp[0], TRUE);
6577 return bnx2x_vf_setup_queue(sc, &sc->fp[0], TRUE);
6581 bnx2x_config_rss_pf(struct bnx2x_softc *sc, struct ecore_rss_config_obj *rss_obj,
6582 uint8_t config_hash)
6584 struct ecore_config_rss_params params = { NULL };
6588 * Although RSS is meaningless when there is a single HW queue we
6589 * still need it enabled in order to have HW Rx hash generated.
6592 params.rss_obj = rss_obj;
6594 bnx2x_set_bit(RAMROD_COMP_WAIT, ¶ms.ramrod_flags);
6596 bnx2x_set_bit(ECORE_RSS_MODE_REGULAR, ¶ms.rss_flags);
6598 /* RSS configuration */
6599 bnx2x_set_bit(ECORE_RSS_IPV4, ¶ms.rss_flags);
6600 bnx2x_set_bit(ECORE_RSS_IPV4_TCP, ¶ms.rss_flags);
6601 bnx2x_set_bit(ECORE_RSS_IPV6, ¶ms.rss_flags);
6602 bnx2x_set_bit(ECORE_RSS_IPV6_TCP, ¶ms.rss_flags);
6603 if (rss_obj->udp_rss_v4) {
6604 bnx2x_set_bit(ECORE_RSS_IPV4_UDP, ¶ms.rss_flags);
6606 if (rss_obj->udp_rss_v6) {
6607 bnx2x_set_bit(ECORE_RSS_IPV6_UDP, ¶ms.rss_flags);
6611 params.rss_result_mask = MULTI_MASK;
6613 (void)rte_memcpy(params.ind_table, rss_obj->ind_table,
6614 sizeof(params.ind_table));
6618 for (i = 0; i < sizeof(params.rss_key) / 4; i++) {
6619 params.rss_key[i] = (uint32_t) rte_rand();
6622 bnx2x_set_bit(ECORE_RSS_SET_SRCH, ¶ms.rss_flags);
6626 return ecore_config_rss(sc, ¶ms);
6628 return bnx2x_vf_config_rss(sc, ¶ms);
6631 static int bnx2x_config_rss_eth(struct bnx2x_softc *sc, uint8_t config_hash)
6633 return bnx2x_config_rss_pf(sc, &sc->rss_conf_obj, config_hash);
6636 static int bnx2x_init_rss_pf(struct bnx2x_softc *sc)
6638 uint8_t num_eth_queues = BNX2X_NUM_ETH_QUEUES(sc);
6642 * Prepare the initial contents of the indirection table if
6645 for (i = 0; i < sizeof(sc->rss_conf_obj.ind_table); i++) {
6646 sc->rss_conf_obj.ind_table[i] =
6647 (sc->fp->cl_id + (i % num_eth_queues));
6651 sc->rss_conf_obj.udp_rss_v4 = sc->rss_conf_obj.udp_rss_v6 = 1;
6655 * For 57711 SEARCHER configuration (rss_keys) is
6656 * per-port, so if explicit configuration is needed, do it only
6659 * For 57712 and newer it's a per-function configuration.
6661 return bnx2x_config_rss_eth(sc, sc->port.pmf || !CHIP_IS_E1x(sc));
6665 bnx2x_set_mac_one(struct bnx2x_softc *sc, uint8_t * mac,
6666 struct ecore_vlan_mac_obj *obj, uint8_t set, int mac_type,
6667 unsigned long *ramrod_flags)
6669 struct ecore_vlan_mac_ramrod_params ramrod_param;
6672 memset(&ramrod_param, 0, sizeof(ramrod_param));
6674 /* fill in general parameters */
6675 ramrod_param.vlan_mac_obj = obj;
6676 ramrod_param.ramrod_flags = *ramrod_flags;
6678 /* fill a user request section if needed */
6679 if (!bnx2x_test_bit(RAMROD_CONT, ramrod_flags)) {
6680 (void)rte_memcpy(ramrod_param.user_req.u.mac.mac, mac,
6683 bnx2x_set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
6685 /* Set the command: ADD or DEL */
6686 ramrod_param.user_req.cmd = (set) ? ECORE_VLAN_MAC_ADD :
6690 rc = ecore_config_vlan_mac(sc, &ramrod_param);
6692 if (rc == ECORE_EXISTS) {
6693 PMD_DRV_LOG(INFO, "Failed to schedule ADD operations (EEXIST)");
6694 /* do not treat adding same MAC as error */
6696 } else if (rc < 0) {
6698 "%s MAC failed (%d)", (set ? "Set" : "Delete"), rc);
6704 static int bnx2x_set_eth_mac(struct bnx2x_softc *sc, uint8_t set)
6706 unsigned long ramrod_flags = 0;
6708 PMD_DRV_LOG(DEBUG, "Adding Ethernet MAC");
6710 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
6712 /* Eth MAC is set on RSS leading client (fp[0]) */
6713 return bnx2x_set_mac_one(sc, sc->link_params.mac_addr,
6714 &sc->sp_objs->mac_obj,
6715 set, ECORE_ETH_MAC, &ramrod_flags);
6718 static int bnx2x_get_cur_phy_idx(struct bnx2x_softc *sc)
6720 uint32_t sel_phy_idx = 0;
6722 if (sc->link_params.num_phys <= 1) {
6723 return ELINK_INT_PHY;
6726 if (sc->link_vars.link_up) {
6727 sel_phy_idx = ELINK_EXT_PHY1;
6728 /* In case link is SERDES, check if the ELINK_EXT_PHY2 is the one */
6729 if ((sc->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
6730 (sc->link_params.phy[ELINK_EXT_PHY2].supported &
6731 ELINK_SUPPORTED_FIBRE))
6732 sel_phy_idx = ELINK_EXT_PHY2;
6734 switch (elink_phy_selection(&sc->link_params)) {
6735 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6736 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
6737 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6738 sel_phy_idx = ELINK_EXT_PHY1;
6740 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
6741 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6742 sel_phy_idx = ELINK_EXT_PHY2;
6750 static int bnx2x_get_link_cfg_idx(struct bnx2x_softc *sc)
6752 uint32_t sel_phy_idx = bnx2x_get_cur_phy_idx(sc);
6755 * The selected activated PHY is always after swapping (in case PHY
6756 * swapping is enabled). So when swapping is enabled, we need to reverse
6760 if (sc->link_params.multi_phy_config & PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
6761 if (sel_phy_idx == ELINK_EXT_PHY1)
6762 sel_phy_idx = ELINK_EXT_PHY2;
6763 else if (sel_phy_idx == ELINK_EXT_PHY2)
6764 sel_phy_idx = ELINK_EXT_PHY1;
6767 return ELINK_LINK_CONFIG_IDX(sel_phy_idx);
6770 static void bnx2x_set_requested_fc(struct bnx2x_softc *sc)
6773 * Initialize link parameters structure variables
6774 * It is recommended to turn off RX FC for jumbo frames
6775 * for better performance
6777 if (CHIP_IS_E1x(sc) && (sc->mtu > 5000)) {
6778 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_TX;
6780 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_BOTH;
6784 static void bnx2x_calc_fc_adv(struct bnx2x_softc *sc)
6786 uint8_t cfg_idx = bnx2x_get_link_cfg_idx(sc);
6787 switch (sc->link_vars.ieee_fc &
6788 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
6789 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
6791 sc->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
6795 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
6796 sc->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
6800 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
6801 sc->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
6806 static uint16_t bnx2x_get_mf_speed(struct bnx2x_softc *sc)
6808 uint16_t line_speed = sc->link_vars.line_speed;
6810 uint16_t maxCfg = bnx2x_extract_max_cfg(sc,
6812 mf_info.mf_config[SC_VN
6815 /* calculate the current MAX line speed limit for the MF devices */
6817 line_speed = (line_speed * maxCfg) / 100;
6818 } else { /* SD mode */
6819 uint16_t vn_max_rate = maxCfg * 100;
6821 if (vn_max_rate < line_speed) {
6822 line_speed = vn_max_rate;
6831 bnx2x_fill_report_data(struct bnx2x_softc *sc, struct bnx2x_link_report_data *data)
6833 uint16_t line_speed = bnx2x_get_mf_speed(sc);
6835 memset(data, 0, sizeof(*data));
6837 /* fill the report data with the effective line speed */
6838 data->line_speed = line_speed;
6841 if (!sc->link_vars.link_up || (sc->flags & BNX2X_MF_FUNC_DIS)) {
6842 bnx2x_set_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6843 &data->link_report_flags);
6847 if (sc->link_vars.duplex == DUPLEX_FULL) {
6848 bnx2x_set_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6849 &data->link_report_flags);
6852 /* Rx Flow Control is ON */
6853 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_RX) {
6854 bnx2x_set_bit(BNX2X_LINK_REPORT_RX_FC_ON, &data->link_report_flags);
6857 /* Tx Flow Control is ON */
6858 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
6859 bnx2x_set_bit(BNX2X_LINK_REPORT_TX_FC_ON, &data->link_report_flags);
6863 /* report link status to OS, should be called under phy_lock */
6864 static void bnx2x_link_report(struct bnx2x_softc *sc)
6866 struct bnx2x_link_report_data cur_data;
6870 bnx2x_read_mf_cfg(sc);
6873 /* Read the current link report info */
6874 bnx2x_fill_report_data(sc, &cur_data);
6876 /* Don't report link down or exactly the same link status twice */
6877 if (!memcmp(&cur_data, &sc->last_reported_link, sizeof(cur_data)) ||
6878 (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6879 &sc->last_reported_link.link_report_flags) &&
6880 bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6881 &cur_data.link_report_flags))) {
6887 /* report new link params and remember the state for the next time */
6888 (void)rte_memcpy(&sc->last_reported_link, &cur_data, sizeof(cur_data));
6890 if (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6891 &cur_data.link_report_flags)) {
6892 PMD_DRV_LOG(INFO, "NIC Link is Down");
6894 __rte_unused const char *duplex;
6895 __rte_unused const char *flow;
6897 if (bnx2x_test_and_clear_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6898 &cur_data.link_report_flags)) {
6905 * Handle the FC at the end so that only these flags would be
6906 * possibly set. This way we may easily check if there is no FC
6909 if (cur_data.link_report_flags) {
6910 if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6911 &cur_data.link_report_flags) &&
6912 bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6913 &cur_data.link_report_flags)) {
6914 flow = "ON - receive & transmit";
6915 } else if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6916 &cur_data.link_report_flags) &&
6917 !bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6918 &cur_data.link_report_flags)) {
6919 flow = "ON - receive";
6920 } else if (!bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6921 &cur_data.link_report_flags) &&
6922 bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6923 &cur_data.link_report_flags)) {
6924 flow = "ON - transmit";
6926 flow = "none"; /* possible? */
6933 "NIC Link is Up, %d Mbps %s duplex, Flow control: %s",
6934 cur_data.line_speed, duplex, flow);
6938 void bnx2x_link_status_update(struct bnx2x_softc *sc)
6940 if (sc->state != BNX2X_STATE_OPEN) {
6944 if (IS_PF(sc) && !CHIP_REV_IS_SLOW(sc)) {
6945 elink_link_status_update(&sc->link_params, &sc->link_vars);
6947 sc->port.supported[0] |= (ELINK_SUPPORTED_10baseT_Half |
6948 ELINK_SUPPORTED_10baseT_Full |
6949 ELINK_SUPPORTED_100baseT_Half |
6950 ELINK_SUPPORTED_100baseT_Full |
6951 ELINK_SUPPORTED_1000baseT_Full |
6952 ELINK_SUPPORTED_2500baseX_Full |
6953 ELINK_SUPPORTED_10000baseT_Full |
6954 ELINK_SUPPORTED_TP |
6955 ELINK_SUPPORTED_FIBRE |
6956 ELINK_SUPPORTED_Autoneg |
6957 ELINK_SUPPORTED_Pause |
6958 ELINK_SUPPORTED_Asym_Pause);
6959 sc->port.advertising[0] = sc->port.supported[0];
6961 sc->link_params.sc = sc;
6962 sc->link_params.port = SC_PORT(sc);
6963 sc->link_params.req_duplex[0] = DUPLEX_FULL;
6964 sc->link_params.req_flow_ctrl[0] = ELINK_FLOW_CTRL_NONE;
6965 sc->link_params.req_line_speed[0] = SPEED_10000;
6966 sc->link_params.speed_cap_mask[0] = 0x7f0000;
6967 sc->link_params.switch_cfg = ELINK_SWITCH_CFG_10G;
6969 if (CHIP_REV_IS_FPGA(sc)) {
6970 sc->link_vars.mac_type = ELINK_MAC_TYPE_EMAC;
6971 sc->link_vars.line_speed = ELINK_SPEED_1000;
6972 sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
6973 LINK_STATUS_SPEED_AND_DUPLEX_1000TFD);
6975 sc->link_vars.mac_type = ELINK_MAC_TYPE_BMAC;
6976 sc->link_vars.line_speed = ELINK_SPEED_10000;
6977 sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
6978 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
6981 sc->link_vars.link_up = 1;
6983 sc->link_vars.duplex = DUPLEX_FULL;
6984 sc->link_vars.flow_ctrl = ELINK_FLOW_CTRL_NONE;
6988 NIG_REG_EGRESS_DRAIN0_MODE +
6989 sc->link_params.port * 4, 0);
6990 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
6991 bnx2x_link_report(sc);
6996 if (sc->link_vars.link_up) {
6997 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
6999 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
7001 bnx2x_link_report(sc);
7003 bnx2x_link_report(sc);
7004 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7008 static void bnx2x_periodic_start(struct bnx2x_softc *sc)
7010 atomic_store_rel_long(&sc->periodic_flags, PERIODIC_GO);
7013 static void bnx2x_periodic_stop(struct bnx2x_softc *sc)
7015 atomic_store_rel_long(&sc->periodic_flags, PERIODIC_STOP);
7018 static int bnx2x_initial_phy_init(struct bnx2x_softc *sc, int load_mode)
7020 int rc, cfg_idx = bnx2x_get_link_cfg_idx(sc);
7021 uint16_t req_line_speed = sc->link_params.req_line_speed[cfg_idx];
7022 struct elink_params *lp = &sc->link_params;
7024 bnx2x_set_requested_fc(sc);
7026 if (CHIP_REV_IS_SLOW(sc)) {
7027 uint32_t bond = CHIP_BOND_ID(sc);
7030 if (CHIP_IS_E2(sc) && CHIP_IS_MODE_4_PORT(sc)) {
7031 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC;
7032 } else if (bond & 0x4) {
7033 if (CHIP_IS_E3(sc)) {
7034 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC;
7036 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC;
7038 } else if (bond & 0x8) {
7039 if (CHIP_IS_E3(sc)) {
7040 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_UMAC;
7042 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC;
7046 /* disable EMAC for E3 and above */
7048 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC;
7051 sc->link_params.feature_config_flags |= feat;
7054 if (load_mode == LOAD_DIAG) {
7055 lp->loopback_mode = ELINK_LOOPBACK_XGXS;
7056 /* Prefer doing PHY loopback at 10G speed, if possible */
7057 if (lp->req_line_speed[cfg_idx] < ELINK_SPEED_10000) {
7058 if (lp->speed_cap_mask[cfg_idx] &
7059 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
7060 lp->req_line_speed[cfg_idx] = ELINK_SPEED_10000;
7062 lp->req_line_speed[cfg_idx] = ELINK_SPEED_1000;
7067 if (load_mode == LOAD_LOOPBACK_EXT) {
7068 lp->loopback_mode = ELINK_LOOPBACK_EXT;
7071 rc = elink_phy_init(&sc->link_params, &sc->link_vars);
7073 bnx2x_calc_fc_adv(sc);
7075 if (sc->link_vars.link_up) {
7076 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7077 bnx2x_link_report(sc);
7080 if (!CHIP_REV_IS_SLOW(sc)) {
7081 bnx2x_periodic_start(sc);
7084 sc->link_params.req_line_speed[cfg_idx] = req_line_speed;
7088 /* update flags in shmem */
7090 bnx2x_update_drv_flags(struct bnx2x_softc *sc, uint32_t flags, uint32_t set)
7094 if (SHMEM2_HAS(sc, drv_flags)) {
7095 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7096 drv_flags = SHMEM2_RD(sc, drv_flags);
7101 drv_flags &= ~flags;
7104 SHMEM2_WR(sc, drv_flags, drv_flags);
7106 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7110 /* periodic timer callout routine, only runs when the interface is up */
7111 void bnx2x_periodic_callout(struct bnx2x_softc *sc)
7113 if ((sc->state != BNX2X_STATE_OPEN) ||
7114 (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_STOP)) {
7115 PMD_DRV_LOG(WARNING, "periodic callout exit (state=0x%x)",
7119 if (!CHIP_REV_IS_SLOW(sc)) {
7121 * This barrier is needed to ensure the ordering between the writing
7122 * to the sc->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
7127 elink_period_func(&sc->link_params, &sc->link_vars);
7131 if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7132 int mb_idx = SC_FW_MB_IDX(sc);
7136 ++sc->fw_drv_pulse_wr_seq;
7137 sc->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
7139 drv_pulse = sc->fw_drv_pulse_wr_seq;
7140 bnx2x_drv_pulse(sc);
7142 mcp_pulse = (SHMEM_RD(sc, func_mb[mb_idx].mcp_pulse_mb) &
7143 MCP_PULSE_SEQ_MASK);
7146 * The delta between driver pulse and mcp response should
7147 * be 1 (before mcp response) or 0 (after mcp response).
7149 if ((drv_pulse != mcp_pulse) &&
7150 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
7151 /* someone lost a heartbeat... */
7153 "drv_pulse (0x%x) != mcp_pulse (0x%x)",
7154 drv_pulse, mcp_pulse);
7160 /* start the controller */
7161 static __attribute__ ((noinline))
7162 int bnx2x_nic_load(struct bnx2x_softc *sc)
7165 uint32_t load_code = 0;
7168 PMD_INIT_FUNC_TRACE();
7170 sc->state = BNX2X_STATE_OPENING_WAITING_LOAD;
7173 /* must be called before memory allocation and HW init */
7174 bnx2x_ilt_set_info(sc);
7177 bnx2x_set_fp_rx_buf_size(sc);
7180 if (bnx2x_alloc_mem(sc) != 0) {
7181 sc->state = BNX2X_STATE_CLOSED;
7183 goto bnx2x_nic_load_error0;
7187 if (bnx2x_alloc_fw_stats_mem(sc) != 0) {
7188 sc->state = BNX2X_STATE_CLOSED;
7190 goto bnx2x_nic_load_error0;
7194 rc = bnx2x_vf_init(sc);
7196 sc->state = BNX2X_STATE_ERROR;
7197 goto bnx2x_nic_load_error0;
7202 /* set pf load just before approaching the MCP */
7203 bnx2x_set_pf_load(sc);
7205 /* if MCP exists send load request and analyze response */
7206 if (!BNX2X_NOMCP(sc)) {
7207 /* attempt to load pf */
7208 if (bnx2x_nic_load_request(sc, &load_code) != 0) {
7209 sc->state = BNX2X_STATE_CLOSED;
7211 goto bnx2x_nic_load_error1;
7214 /* what did the MCP say? */
7215 if (bnx2x_nic_load_analyze_req(sc, load_code) != 0) {
7216 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7217 sc->state = BNX2X_STATE_CLOSED;
7219 goto bnx2x_nic_load_error2;
7222 PMD_DRV_LOG(INFO, "Device has no MCP!");
7223 load_code = bnx2x_nic_load_no_mcp(sc);
7226 /* mark PMF if applicable */
7227 bnx2x_nic_load_pmf(sc, load_code);
7229 /* Init Function state controlling object */
7230 bnx2x_init_func_obj(sc);
7233 if (bnx2x_init_hw(sc, load_code) != 0) {
7234 PMD_DRV_LOG(NOTICE, "HW init failed");
7235 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7236 sc->state = BNX2X_STATE_CLOSED;
7238 goto bnx2x_nic_load_error2;
7242 bnx2x_nic_init(sc, load_code);
7244 /* Init per-function objects */
7246 bnx2x_init_objs(sc);
7248 /* set AFEX default VLAN tag to an invalid value */
7249 sc->devinfo.mf_info.afex_def_vlan_tag = -1;
7251 sc->state = BNX2X_STATE_OPENING_WAITING_PORT;
7252 rc = bnx2x_func_start(sc);
7254 PMD_DRV_LOG(NOTICE, "Function start failed!");
7255 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7256 sc->state = BNX2X_STATE_ERROR;
7257 goto bnx2x_nic_load_error3;
7260 /* send LOAD_DONE command to MCP */
7261 if (!BNX2X_NOMCP(sc)) {
7263 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7266 "MCP response failure, aborting");
7267 sc->state = BNX2X_STATE_ERROR;
7269 goto bnx2x_nic_load_error3;
7274 rc = bnx2x_setup_leading(sc);
7276 PMD_DRV_LOG(NOTICE, "Setup leading failed!");
7277 sc->state = BNX2X_STATE_ERROR;
7278 goto bnx2x_nic_load_error3;
7281 FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, i) {
7283 rc = bnx2x_setup_queue(sc, &sc->fp[i], FALSE);
7284 else /* IS_VF(sc) */
7285 rc = bnx2x_vf_setup_queue(sc, &sc->fp[i], FALSE);
7288 PMD_DRV_LOG(NOTICE, "Queue(%d) setup failed", i);
7289 sc->state = BNX2X_STATE_ERROR;
7290 goto bnx2x_nic_load_error3;
7294 rc = bnx2x_init_rss_pf(sc);
7296 PMD_DRV_LOG(NOTICE, "PF RSS init failed");
7297 sc->state = BNX2X_STATE_ERROR;
7298 goto bnx2x_nic_load_error3;
7301 /* now when Clients are configured we are ready to work */
7302 sc->state = BNX2X_STATE_OPEN;
7304 /* Configure a ucast MAC */
7306 rc = bnx2x_set_eth_mac(sc, TRUE);
7307 } else { /* IS_VF(sc) */
7308 rc = bnx2x_vf_set_mac(sc, TRUE);
7312 PMD_DRV_LOG(NOTICE, "Setting Ethernet MAC failed");
7313 sc->state = BNX2X_STATE_ERROR;
7314 goto bnx2x_nic_load_error3;
7318 rc = bnx2x_initial_phy_init(sc, LOAD_OPEN);
7320 sc->state = BNX2X_STATE_ERROR;
7321 goto bnx2x_nic_load_error3;
7325 sc->link_params.feature_config_flags &=
7326 ~ELINK_FEATURE_CONFIG_BOOT_FROM_SAN;
7329 switch (LOAD_OPEN) {
7335 case LOAD_LOOPBACK_EXT:
7336 sc->state = BNX2X_STATE_DIAG;
7344 bnx2x_update_drv_flags(sc, 1 << DRV_FLAGS_PORT_MASK, 0);
7346 bnx2x_link_status_update(sc);
7349 if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
7350 /* mark driver is loaded in shmem2 */
7351 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
7352 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
7354 DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED |
7355 DRV_FLAGS_CAPABILITIES_LOADED_L2));
7358 /* start fast path */
7359 /* Initialize Rx filter */
7360 bnx2x_set_rx_mode(sc);
7362 /* wait for all pending SP commands to complete */
7363 if (IS_PF(sc) && !bnx2x_wait_sp_comp(sc, ~0x0UL)) {
7364 PMD_DRV_LOG(NOTICE, "Timeout waiting for all SPs to complete!");
7365 bnx2x_periodic_stop(sc);
7366 bnx2x_nic_unload(sc, UNLOAD_CLOSE, FALSE);
7370 PMD_DRV_LOG(DEBUG, "NIC successfully loaded");
7374 bnx2x_nic_load_error3:
7377 bnx2x_int_disable_sync(sc, 1);
7379 /* clean out queued objects */
7380 bnx2x_squeeze_objects(sc);
7383 bnx2x_nic_load_error2:
7385 if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7386 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
7387 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
7392 bnx2x_nic_load_error1:
7394 /* clear pf_load status, as it was already set */
7396 bnx2x_clear_pf_load(sc);
7399 bnx2x_nic_load_error0:
7401 bnx2x_free_fw_stats_mem(sc);
7408 * Handles controller initialization.
7410 int bnx2x_init(struct bnx2x_softc *sc)
7412 int other_engine = SC_PATH(sc) ? 0 : 1;
7413 uint8_t other_load_status, load_status;
7414 uint8_t global = FALSE;
7417 /* Check if the driver is still running and bail out if it is. */
7418 if (sc->state != BNX2X_STATE_CLOSED) {
7419 PMD_DRV_LOG(DEBUG, "Init called while driver is running!");
7421 goto bnx2x_init_done;
7424 bnx2x_set_power_state(sc, PCI_PM_D0);
7427 * If parity occurred during the unload, then attentions and/or
7428 * RECOVERY_IN_PROGRESS may still be set. If so we want the first function
7429 * loaded on the current engine to complete the recovery. Parity recovery
7430 * is only relevant for PF driver.
7433 other_load_status = bnx2x_get_load_status(sc, other_engine);
7434 load_status = bnx2x_get_load_status(sc, SC_PATH(sc));
7436 if (!bnx2x_reset_is_done(sc, SC_PATH(sc)) ||
7437 bnx2x_chk_parity_attn(sc, &global, TRUE)) {
7440 * If there are attentions and they are in global blocks, set
7441 * the GLOBAL_RESET bit regardless whether it will be this
7442 * function that will complete the recovery or not.
7445 bnx2x_set_reset_global(sc);
7449 * Only the first function on the current engine should try
7450 * to recover in open. In case of attentions in global blocks
7451 * only the first in the chip should try to recover.
7454 && (!global ||!other_load_status))
7455 && bnx2x_trylock_leader_lock(sc)
7456 && !bnx2x_leader_reset(sc)) {
7458 "Recovered during init");
7462 /* recovery has failed... */
7463 bnx2x_set_power_state(sc, PCI_PM_D3hot);
7465 sc->recovery_state = BNX2X_RECOVERY_FAILED;
7468 "Recovery flow hasn't properly "
7469 "completed yet, try again later. "
7470 "If you still see this message after a "
7471 "few retries then power cycle is required.");
7474 goto bnx2x_init_done;
7479 sc->recovery_state = BNX2X_RECOVERY_DONE;
7481 rc = bnx2x_nic_load(sc);
7486 PMD_DRV_LOG(NOTICE, "Initialization failed, "
7487 "stack notified driver is NOT running!");
7493 static void bnx2x_get_function_num(struct bnx2x_softc *sc)
7498 * Read the ME register to get the function number. The ME register
7499 * holds the relative-function number and absolute-function number. The
7500 * absolute-function number appears only in E2 and above. Before that
7501 * these bits always contained zero, therefore we cannot blindly use them.
7504 val = REG_RD(sc, BAR_ME_REGISTER);
7507 (uint8_t) ((val & ME_REG_PF_NUM) >> ME_REG_PF_NUM_SHIFT);
7509 (uint8_t) ((val & ME_REG_ABS_PF_NUM) >> ME_REG_ABS_PF_NUM_SHIFT) &
7512 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7513 sc->pfunc_abs = ((sc->pfunc_rel << 1) | sc->path_id);
7515 sc->pfunc_abs = (sc->pfunc_rel | sc->path_id);
7519 "Relative function %d, Absolute function %d, Path %d",
7520 sc->pfunc_rel, sc->pfunc_abs, sc->path_id);
7523 static uint32_t bnx2x_get_shmem_mf_cfg_base(struct bnx2x_softc *sc)
7525 uint32_t shmem2_size;
7527 uint32_t mf_cfg_offset_value;
7530 offset = (SHMEM_ADDR(sc, func_mb) +
7531 (MAX_FUNC_NUM * sizeof(struct drv_func_mb)));
7534 if (sc->devinfo.shmem2_base != 0) {
7535 shmem2_size = SHMEM2_RD(sc, size);
7536 if (shmem2_size > offsetof(struct shmem2_region, mf_cfg_addr)) {
7537 mf_cfg_offset_value = SHMEM2_RD(sc, mf_cfg_addr);
7538 if (SHMEM_MF_CFG_ADDR_NONE != mf_cfg_offset_value) {
7539 offset = mf_cfg_offset_value;
7547 static uint32_t bnx2x_pcie_capability_read(struct bnx2x_softc *sc, int reg)
7550 struct bnx2x_pci_cap *caps;
7552 /* ensure PCIe capability is enabled */
7553 caps = pci_find_cap(sc, PCIY_EXPRESS, BNX2X_PCI_CAP);
7555 PMD_DRV_LOG(DEBUG, "Found PCIe capability: "
7556 "id=0x%04X type=0x%04X addr=0x%08X",
7557 caps->id, caps->type, caps->addr);
7558 pci_read(sc, (caps->addr + reg), &ret, 2);
7562 PMD_DRV_LOG(WARNING, "PCIe capability NOT FOUND!!!");
7567 static uint8_t bnx2x_is_pcie_pending(struct bnx2x_softc *sc)
7569 return (bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_STA) &
7570 PCIM_EXP_STA_TRANSACTION_PND);
7574 * Walk the PCI capabiites list for the device to find what features are
7575 * supported. These capabilites may be enabled/disabled by firmware so it's
7576 * best to walk the list rather than make assumptions.
7578 static void bnx2x_probe_pci_caps(struct bnx2x_softc *sc)
7580 PMD_INIT_FUNC_TRACE();
7582 struct bnx2x_pci_cap *caps;
7583 uint16_t link_status;
7584 #ifdef RTE_LIBRTE_BNX2X_DEBUG
7588 /* check if PCI Power Management is enabled */
7589 caps = pci_find_cap(sc, PCIY_PMG, BNX2X_PCI_CAP);
7591 PMD_DRV_LOG(DEBUG, "Found PM capability: "
7592 "id=0x%04X type=0x%04X addr=0x%08X",
7593 caps->id, caps->type, caps->addr);
7595 sc->devinfo.pcie_cap_flags |= BNX2X_PM_CAPABLE_FLAG;
7596 sc->devinfo.pcie_pm_cap_reg = caps->addr;
7599 link_status = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_LINK_STA);
7601 sc->devinfo.pcie_link_speed = (link_status & PCIM_LINK_STA_SPEED);
7602 sc->devinfo.pcie_link_width =
7603 ((link_status & PCIM_LINK_STA_WIDTH) >> 4);
7605 PMD_DRV_LOG(DEBUG, "PCIe link speed=%d width=%d",
7606 sc->devinfo.pcie_link_speed, sc->devinfo.pcie_link_width);
7608 sc->devinfo.pcie_cap_flags |= BNX2X_PCIE_CAPABLE_FLAG;
7610 /* check if MSI capability is enabled */
7611 caps = pci_find_cap(sc, PCIY_MSI, BNX2X_PCI_CAP);
7613 PMD_DRV_LOG(DEBUG, "Found MSI capability at 0x%04x", reg);
7615 sc->devinfo.pcie_cap_flags |= BNX2X_MSI_CAPABLE_FLAG;
7616 sc->devinfo.pcie_msi_cap_reg = caps->addr;
7619 /* check if MSI-X capability is enabled */
7620 caps = pci_find_cap(sc, PCIY_MSIX, BNX2X_PCI_CAP);
7622 PMD_DRV_LOG(DEBUG, "Found MSI-X capability at 0x%04x", reg);
7624 sc->devinfo.pcie_cap_flags |= BNX2X_MSIX_CAPABLE_FLAG;
7625 sc->devinfo.pcie_msix_cap_reg = caps->addr;
7629 static int bnx2x_get_shmem_mf_cfg_info_sd(struct bnx2x_softc *sc)
7631 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7634 /* get the outer vlan if we're in switch-dependent mode */
7636 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7637 mf_info->ext_id = (uint16_t) val;
7639 mf_info->multi_vnics_mode = 1;
7641 if (!VALID_OVLAN(mf_info->ext_id)) {
7642 PMD_DRV_LOG(NOTICE, "Invalid VLAN (%d)", mf_info->ext_id);
7646 /* get the capabilities */
7647 if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK) ==
7648 FUNC_MF_CFG_PROTOCOL_ISCSI) {
7649 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ISCSI;
7650 } else if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK)
7651 == FUNC_MF_CFG_PROTOCOL_FCOE) {
7652 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_FCOE;
7654 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ETHERNET;
7657 mf_info->vnics_per_port =
7658 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7663 static uint32_t bnx2x_get_shmem_ext_proto_support_flags(struct bnx2x_softc *sc)
7665 uint32_t retval = 0;
7668 val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7670 if (val & MACP_FUNC_CFG_FLAGS_ENABLED) {
7671 if (val & MACP_FUNC_CFG_FLAGS_ETHERNET) {
7672 retval |= MF_PROTO_SUPPORT_ETHERNET;
7674 if (val & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
7675 retval |= MF_PROTO_SUPPORT_ISCSI;
7677 if (val & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
7678 retval |= MF_PROTO_SUPPORT_FCOE;
7685 static int bnx2x_get_shmem_mf_cfg_info_si(struct bnx2x_softc *sc)
7687 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7691 * There is no outer vlan if we're in switch-independent mode.
7692 * If the mac is valid then assume multi-function.
7695 val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7697 mf_info->multi_vnics_mode = ((val & MACP_FUNC_CFG_FLAGS_MASK) != 0);
7699 mf_info->mf_protos_supported =
7700 bnx2x_get_shmem_ext_proto_support_flags(sc);
7702 mf_info->vnics_per_port =
7703 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7708 static int bnx2x_get_shmem_mf_cfg_info_niv(struct bnx2x_softc *sc)
7710 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7712 uint32_t func_config;
7713 uint32_t niv_config;
7715 mf_info->multi_vnics_mode = 1;
7717 e1hov_tag = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7718 func_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7719 niv_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].afex_config);
7722 (uint16_t) ((e1hov_tag & FUNC_MF_CFG_E1HOV_TAG_MASK) >>
7723 FUNC_MF_CFG_E1HOV_TAG_SHIFT);
7725 mf_info->default_vlan =
7726 (uint16_t) ((e1hov_tag & FUNC_MF_CFG_AFEX_VLAN_MASK) >>
7727 FUNC_MF_CFG_AFEX_VLAN_SHIFT);
7729 mf_info->niv_allowed_priorities =
7730 (uint8_t) ((niv_config & FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
7731 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT);
7733 mf_info->niv_default_cos =
7734 (uint8_t) ((func_config & FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
7735 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT);
7737 mf_info->afex_vlan_mode =
7738 ((niv_config & FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
7739 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT);
7741 mf_info->niv_mba_enabled =
7742 ((niv_config & FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK) >>
7743 FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT);
7745 mf_info->mf_protos_supported =
7746 bnx2x_get_shmem_ext_proto_support_flags(sc);
7748 mf_info->vnics_per_port =
7749 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7754 static int bnx2x_check_valid_mf_cfg(struct bnx2x_softc *sc)
7756 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7763 /* various MF mode sanity checks... */
7765 if (mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_HIDE) {
7767 "Enumerated function %d is marked as hidden",
7772 if ((mf_info->vnics_per_port > 1) && !mf_info->multi_vnics_mode) {
7773 PMD_DRV_LOG(NOTICE, "vnics_per_port=%d multi_vnics_mode=%d",
7774 mf_info->vnics_per_port, mf_info->multi_vnics_mode);
7778 if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7779 /* vnic id > 0 must have valid ovlan in switch-dependent mode */
7780 if ((SC_VN(sc) > 0) && !VALID_OVLAN(OVLAN(sc))) {
7781 PMD_DRV_LOG(NOTICE, "mf_mode=SD vnic_id=%d ovlan=%d",
7782 SC_VN(sc), OVLAN(sc));
7786 if (!VALID_OVLAN(OVLAN(sc)) && mf_info->multi_vnics_mode) {
7788 "mf_mode=SD multi_vnics_mode=%d ovlan=%d",
7789 mf_info->multi_vnics_mode, OVLAN(sc));
7794 * Verify all functions are either MF or SF mode. If MF, make sure
7795 * sure that all non-hidden functions have a valid ovlan. If SF,
7796 * make sure that all non-hidden functions have an invalid ovlan.
7798 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7799 mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7800 ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7801 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE) &&
7802 (((mf_info->multi_vnics_mode)
7803 && !VALID_OVLAN(ovlan1))
7804 || ((!mf_info->multi_vnics_mode)
7805 && VALID_OVLAN(ovlan1)))) {
7807 "mf_mode=SD function %d MF config "
7808 "mismatch, multi_vnics_mode=%d ovlan=%d",
7809 i, mf_info->multi_vnics_mode,
7815 /* Verify all funcs on the same port each have a different ovlan. */
7816 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7817 mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7818 ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7819 /* iterate from the next function on the port to the max func */
7820 for (j = i + 2; j < MAX_FUNC_NUM; j += 2) {
7822 MFCFG_RD(sc, func_mf_config[j].config);
7824 MFCFG_RD(sc, func_mf_config[j].e1hov_tag);
7825 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE)
7826 && VALID_OVLAN(ovlan1)
7827 && !(mf_cfg2 & FUNC_MF_CFG_FUNC_HIDE)
7828 && VALID_OVLAN(ovlan2)
7829 && (ovlan1 == ovlan2)) {
7831 "mf_mode=SD functions %d and %d "
7832 "have the same ovlan (%d)",
7839 /* MULTI_FUNCTION_SD */
7843 static int bnx2x_get_mf_cfg_info(struct bnx2x_softc *sc)
7845 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7846 uint32_t val, mac_upper;
7849 /* initialize mf_info defaults */
7850 mf_info->vnics_per_port = 1;
7851 mf_info->multi_vnics_mode = FALSE;
7852 mf_info->path_has_ovlan = FALSE;
7853 mf_info->mf_mode = SINGLE_FUNCTION;
7855 if (!CHIP_IS_MF_CAP(sc)) {
7859 if (sc->devinfo.mf_cfg_base == SHMEM_MF_CFG_ADDR_NONE) {
7860 PMD_DRV_LOG(NOTICE, "Invalid mf_cfg_base!");
7864 /* get the MF mode (switch dependent / independent / single-function) */
7866 val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
7868 switch (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK) {
7869 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
7872 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7874 /* check for legal upper mac bytes */
7875 if (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT) {
7876 mf_info->mf_mode = MULTI_FUNCTION_SI;
7879 "Invalid config for Switch Independent mode");
7884 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
7885 case SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4:
7887 /* get outer vlan configuration */
7888 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7890 if ((val & FUNC_MF_CFG_E1HOV_TAG_MASK) !=
7891 FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
7892 mf_info->mf_mode = MULTI_FUNCTION_SD;
7895 "Invalid config for Switch Dependent mode");
7900 case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
7902 /* not in MF mode, vnics_per_port=1 and multi_vnics_mode=FALSE */
7905 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
7908 * Mark MF mode as NIV if MCP version includes NPAR-SD support
7909 * and the MAC address is valid.
7912 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7914 if ((SHMEM2_HAS(sc, afex_driver_support)) &&
7915 (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT)) {
7916 mf_info->mf_mode = MULTI_FUNCTION_AFEX;
7918 PMD_DRV_LOG(NOTICE, "Invalid config for AFEX mode");
7925 PMD_DRV_LOG(NOTICE, "Unknown MF mode (0x%08x)",
7926 (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK));
7931 /* set path mf_mode (which could be different than function mf_mode) */
7932 if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7933 mf_info->path_has_ovlan = TRUE;
7934 } else if (mf_info->mf_mode == SINGLE_FUNCTION) {
7936 * Decide on path multi vnics mode. If we're not in MF mode and in
7937 * 4-port mode, this is good enough to check vnic-0 of the other port
7940 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7941 uint8_t other_port = !(PORT_ID(sc) & 1);
7942 uint8_t abs_func_other_port =
7943 (SC_PATH(sc) + (2 * other_port));
7948 [abs_func_other_port].e1hov_tag);
7950 mf_info->path_has_ovlan = VALID_OVLAN((uint16_t) val);
7954 if (mf_info->mf_mode == SINGLE_FUNCTION) {
7955 /* invalid MF config */
7956 if (SC_VN(sc) >= 1) {
7957 PMD_DRV_LOG(NOTICE, "VNIC ID >= 1 in SF mode");
7964 /* get the MF configuration */
7965 mf_info->mf_config[SC_VN(sc)] =
7966 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7968 switch (mf_info->mf_mode) {
7969 case MULTI_FUNCTION_SD:
7971 bnx2x_get_shmem_mf_cfg_info_sd(sc);
7974 case MULTI_FUNCTION_SI:
7976 bnx2x_get_shmem_mf_cfg_info_si(sc);
7979 case MULTI_FUNCTION_AFEX:
7981 bnx2x_get_shmem_mf_cfg_info_niv(sc);
7986 PMD_DRV_LOG(NOTICE, "Get MF config failed (mf_mode=0x%08x)",
7991 /* get the congestion management parameters */
7994 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7995 /* get min/max bw */
7996 val = MFCFG_RD(sc, func_mf_config[i].config);
7997 mf_info->min_bw[vnic] =
7998 ((val & FUNC_MF_CFG_MIN_BW_MASK) >>
7999 FUNC_MF_CFG_MIN_BW_SHIFT);
8000 mf_info->max_bw[vnic] =
8001 ((val & FUNC_MF_CFG_MAX_BW_MASK) >>
8002 FUNC_MF_CFG_MAX_BW_SHIFT);
8006 return bnx2x_check_valid_mf_cfg(sc);
8009 static int bnx2x_get_shmem_info(struct bnx2x_softc *sc)
8012 uint32_t mac_hi, mac_lo, val;
8014 PMD_INIT_FUNC_TRACE();
8017 mac_hi = mac_lo = 0;
8019 sc->link_params.sc = sc;
8020 sc->link_params.port = port;
8022 /* get the hardware config info */
8023 sc->devinfo.hw_config = SHMEM_RD(sc, dev_info.shared_hw_config.config);
8024 sc->devinfo.hw_config2 =
8025 SHMEM_RD(sc, dev_info.shared_hw_config.config2);
8027 sc->link_params.hw_led_mode =
8028 ((sc->devinfo.hw_config & SHARED_HW_CFG_LED_MODE_MASK) >>
8029 SHARED_HW_CFG_LED_MODE_SHIFT);
8031 /* get the port feature config */
8033 SHMEM_RD(sc, dev_info.port_feature_config[port].config);
8035 /* get the link params */
8036 sc->link_params.speed_cap_mask[ELINK_INT_PHY] =
8037 SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask)
8038 & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
8039 sc->link_params.speed_cap_mask[ELINK_EXT_PHY1] =
8040 SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask2)
8041 & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
8043 /* get the lane config */
8044 sc->link_params.lane_config =
8045 SHMEM_RD(sc, dev_info.port_hw_config[port].lane_config);
8047 /* get the link config */
8048 val = SHMEM_RD(sc, dev_info.port_feature_config[port].link_config);
8049 sc->port.link_config[ELINK_INT_PHY] = val;
8050 sc->link_params.switch_cfg = (val & PORT_FEATURE_CONNECTED_SWITCH_MASK);
8051 sc->port.link_config[ELINK_EXT_PHY1] =
8052 SHMEM_RD(sc, dev_info.port_feature_config[port].link_config2);
8054 /* get the override preemphasis flag and enable it or turn it off */
8055 val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
8056 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) {
8057 sc->link_params.feature_config_flags |=
8058 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8060 sc->link_params.feature_config_flags &=
8061 ~ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8064 /* get the initial value of the link params */
8065 sc->link_params.multi_phy_config =
8066 SHMEM_RD(sc, dev_info.port_hw_config[port].multi_phy_config);
8068 /* get external phy info */
8069 sc->port.ext_phy_config =
8070 SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
8072 /* get the multifunction configuration */
8073 bnx2x_get_mf_cfg_info(sc);
8075 /* get the mac address */
8078 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
8080 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_lower);
8082 mac_hi = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_upper);
8083 mac_lo = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_lower);
8086 if ((mac_lo == 0) && (mac_hi == 0)) {
8087 *sc->mac_addr_str = 0;
8088 PMD_DRV_LOG(NOTICE, "No Ethernet address programmed!");
8090 sc->link_params.mac_addr[0] = (uint8_t) (mac_hi >> 8);
8091 sc->link_params.mac_addr[1] = (uint8_t) (mac_hi);
8092 sc->link_params.mac_addr[2] = (uint8_t) (mac_lo >> 24);
8093 sc->link_params.mac_addr[3] = (uint8_t) (mac_lo >> 16);
8094 sc->link_params.mac_addr[4] = (uint8_t) (mac_lo >> 8);
8095 sc->link_params.mac_addr[5] = (uint8_t) (mac_lo);
8096 snprintf(sc->mac_addr_str, sizeof(sc->mac_addr_str),
8097 "%02x:%02x:%02x:%02x:%02x:%02x",
8098 sc->link_params.mac_addr[0],
8099 sc->link_params.mac_addr[1],
8100 sc->link_params.mac_addr[2],
8101 sc->link_params.mac_addr[3],
8102 sc->link_params.mac_addr[4],
8103 sc->link_params.mac_addr[5]);
8104 PMD_DRV_LOG(DEBUG, "Ethernet address: %s", sc->mac_addr_str);
8110 static void bnx2x_media_detect(struct bnx2x_softc *sc)
8112 uint32_t phy_idx = bnx2x_get_cur_phy_idx(sc);
8113 switch (sc->link_params.phy[phy_idx].media_type) {
8114 case ELINK_ETH_PHY_SFPP_10G_FIBER:
8115 case ELINK_ETH_PHY_SFP_1G_FIBER:
8116 case ELINK_ETH_PHY_XFP_FIBER:
8117 case ELINK_ETH_PHY_KR:
8118 case ELINK_ETH_PHY_CX4:
8119 PMD_DRV_LOG(INFO, "Found 10GBase-CX4 media.");
8120 sc->media = IFM_10G_CX4;
8122 case ELINK_ETH_PHY_DA_TWINAX:
8123 PMD_DRV_LOG(INFO, "Found 10Gb Twinax media.");
8124 sc->media = IFM_10G_TWINAX;
8126 case ELINK_ETH_PHY_BASE_T:
8127 PMD_DRV_LOG(INFO, "Found 10GBase-T media.");
8128 sc->media = IFM_10G_T;
8130 case ELINK_ETH_PHY_NOT_PRESENT:
8131 PMD_DRV_LOG(INFO, "Media not present.");
8134 case ELINK_ETH_PHY_UNSPECIFIED:
8136 PMD_DRV_LOG(INFO, "Unknown media!");
8142 #define GET_FIELD(value, fname) \
8143 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
8144 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
8145 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
8147 static int bnx2x_get_igu_cam_info(struct bnx2x_softc *sc)
8149 int pfid = SC_FUNC(sc);
8152 uint8_t fid, igu_sb_cnt = 0;
8154 sc->igu_base_sb = 0xff;
8156 if (CHIP_INT_MODE_IS_BC(sc)) {
8158 igu_sb_cnt = sc->igu_sb_cnt;
8159 sc->igu_base_sb = ((CHIP_IS_MODE_4_PORT(sc) ? pfid : vn) *
8161 sc->igu_dsb_id = (E1HVN_MAX * FP_SB_MAX_E1x +
8162 (CHIP_IS_MODE_4_PORT(sc) ? pfid : vn));
8166 /* IGU in normal mode - read CAM */
8168 igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; igu_sb_id++) {
8169 val = REG_RD(sc, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
8170 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) {
8174 if ((fid & IGU_FID_ENCODE_IS_PF)) {
8175 if ((fid & IGU_FID_PF_NUM_MASK) != pfid) {
8178 if (IGU_VEC(val) == 0) {
8179 /* default status block */
8180 sc->igu_dsb_id = igu_sb_id;
8182 if (sc->igu_base_sb == 0xff) {
8183 sc->igu_base_sb = igu_sb_id;
8191 * Due to new PF resource allocation by MFW T7.4 and above, it's optional
8192 * that number of CAM entries will not be equal to the value advertised in
8193 * PCI. Driver should use the minimal value of both as the actual status
8196 sc->igu_sb_cnt = min(sc->igu_sb_cnt, igu_sb_cnt);
8198 if (igu_sb_cnt == 0) {
8199 PMD_DRV_LOG(ERR, "CAM configuration error");
8207 * Gather various information from the device config space, the device itself,
8208 * shmem, and the user input.
8210 static int bnx2x_get_device_info(struct bnx2x_softc *sc)
8215 /* get the chip revision (chip metal comes from pci config space) */
8216 sc->devinfo.chip_id = sc->link_params.chip_id =
8217 (((REG_RD(sc, MISC_REG_CHIP_NUM) & 0xffff) << 16) |
8218 ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12) |
8219 (((REG_RD(sc, PCICFG_OFFSET + PCI_ID_VAL3) >> 24) & 0xf) << 4) |
8220 ((REG_RD(sc, MISC_REG_BOND_ID) & 0xf) << 0));
8222 /* force 57811 according to MISC register */
8223 if (REG_RD(sc, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
8224 if (CHIP_IS_57810(sc)) {
8225 sc->devinfo.chip_id = ((CHIP_NUM_57811 << 16) |
8227 devinfo.chip_id & 0x0000ffff));
8228 } else if (CHIP_IS_57810_MF(sc)) {
8229 sc->devinfo.chip_id = ((CHIP_NUM_57811_MF << 16) |
8231 devinfo.chip_id & 0x0000ffff));
8233 sc->devinfo.chip_id |= 0x1;
8237 "chip_id=0x%08x (num=0x%04x rev=0x%01x metal=0x%02x bond=0x%01x)",
8238 sc->devinfo.chip_id,
8239 ((sc->devinfo.chip_id >> 16) & 0xffff),
8240 ((sc->devinfo.chip_id >> 12) & 0xf),
8241 ((sc->devinfo.chip_id >> 4) & 0xff),
8242 ((sc->devinfo.chip_id >> 0) & 0xf));
8244 val = (REG_RD(sc, 0x2874) & 0x55);
8245 if ((sc->devinfo.chip_id & 0x1) || (CHIP_IS_E1H(sc) && (val == 0x55))) {
8246 sc->flags |= BNX2X_ONE_PORT_FLAG;
8247 PMD_DRV_LOG(DEBUG, "single port device");
8250 /* set the doorbell size */
8251 sc->doorbell_size = (1 << BNX2X_DB_SHIFT);
8253 /* determine whether the device is in 2 port or 4 port mode */
8254 sc->devinfo.chip_port_mode = CHIP_PORT_MODE_NONE; /* E1h */
8255 if (CHIP_IS_E2E3(sc)) {
8257 * Read port4mode_en_ovwr[0]:
8258 * If 1, four port mode is in port4mode_en_ovwr[1].
8259 * If 0, four port mode is in port4mode_en[0].
8261 val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);
8263 val = ((val >> 1) & 1);
8265 val = REG_RD(sc, MISC_REG_PORT4MODE_EN);
8268 sc->devinfo.chip_port_mode =
8269 (val) ? CHIP_4_PORT_MODE : CHIP_2_PORT_MODE;
8271 PMD_DRV_LOG(DEBUG, "Port mode = %s", (val) ? "4" : "2");
8274 /* get the function and path info for the device */
8275 bnx2x_get_function_num(sc);
8277 /* get the shared memory base address */
8278 sc->devinfo.shmem_base =
8279 sc->link_params.shmem_base = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
8280 sc->devinfo.shmem2_base =
8281 REG_RD(sc, (SC_PATH(sc) ? MISC_REG_GENERIC_CR_1 :
8282 MISC_REG_GENERIC_CR_0));
8284 if (!sc->devinfo.shmem_base) {
8285 /* this should ONLY prevent upcoming shmem reads */
8286 PMD_DRV_LOG(INFO, "MCP not active");
8287 sc->flags |= BNX2X_NO_MCP_FLAG;
8291 /* make sure the shared memory contents are valid */
8292 val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
8293 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) !=
8294 (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) {
8295 PMD_DRV_LOG(NOTICE, "Invalid SHMEM validity signature: 0x%08x",
8300 /* get the bootcode version */
8301 sc->devinfo.bc_ver = SHMEM_RD(sc, dev_info.bc_rev);
8302 snprintf(sc->devinfo.bc_ver_str,
8303 sizeof(sc->devinfo.bc_ver_str),
8305 ((sc->devinfo.bc_ver >> 24) & 0xff),
8306 ((sc->devinfo.bc_ver >> 16) & 0xff),
8307 ((sc->devinfo.bc_ver >> 8) & 0xff));
8308 PMD_DRV_LOG(INFO, "Bootcode version: %s", sc->devinfo.bc_ver_str);
8310 /* get the bootcode shmem address */
8311 sc->devinfo.mf_cfg_base = bnx2x_get_shmem_mf_cfg_base(sc);
8313 /* clean indirect addresses as they're not used */
8314 pci_write_long(sc, PCICFG_GRC_ADDRESS, 0);
8316 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F0, 0);
8317 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F0, 0);
8318 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F0, 0);
8319 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F0, 0);
8320 if (CHIP_IS_E1x(sc)) {
8321 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F1, 0);
8322 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F1, 0);
8323 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F1, 0);
8324 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F1, 0);
8328 * Enable internal target-read (in case we are probed after PF
8329 * FLR). Must be done prior to any BAR read access. Only for
8332 if (!CHIP_IS_E1x(sc)) {
8333 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ,
8338 /* get the nvram size */
8339 val = REG_RD(sc, MCP_REG_MCPR_NVM_CFG4);
8340 sc->devinfo.flash_size =
8341 (NVRAM_1MB_SIZE << (val & MCPR_NVM_CFG4_FLASH_SIZE));
8343 bnx2x_set_power_state(sc, PCI_PM_D0);
8344 /* get various configuration parameters from shmem */
8345 bnx2x_get_shmem_info(sc);
8347 /* initialize IGU parameters */
8348 if (CHIP_IS_E1x(sc)) {
8349 sc->devinfo.int_block = INT_BLOCK_HC;
8350 sc->igu_dsb_id = DEF_SB_IGU_ID;
8351 sc->igu_base_sb = 0;
8353 sc->devinfo.int_block = INT_BLOCK_IGU;
8355 /* do not allow device reset during IGU info preocessing */
8356 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8358 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
8360 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8363 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
8364 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION, val);
8365 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x7f);
8367 while (tout && REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8372 if (REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8374 "FORCING IGU Normal Mode failed!!!");
8375 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8380 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8381 PMD_DRV_LOG(DEBUG, "IGU Backward Compatible Mode");
8382 sc->devinfo.int_block |= INT_BLOCK_MODE_BW_COMP;
8384 PMD_DRV_LOG(DEBUG, "IGU Normal Mode");
8387 rc = bnx2x_get_igu_cam_info(sc);
8389 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8397 * Get base FW non-default (fast path) status block ID. This value is
8398 * used to initialize the fw_sb_id saved on the fp/queue structure to
8399 * determine the id used by the FW.
8401 if (CHIP_IS_E1x(sc)) {
8403 ((SC_PORT(sc) * FP_SB_MAX_E1x) + SC_L_ID(sc));
8406 * 57712+ - We currently use one FW SB per IGU SB (Rx and Tx of
8407 * the same queue are indicated on the same IGU SB). So we prefer
8408 * FW and IGU SBs to be the same value.
8410 sc->base_fw_ndsb = sc->igu_base_sb;
8413 elink_phy_probe(&sc->link_params);
8419 bnx2x_link_settings_supported(struct bnx2x_softc *sc, uint32_t switch_cfg)
8421 uint32_t cfg_size = 0;
8423 uint8_t port = SC_PORT(sc);
8425 /* aggregation of supported attributes of all external phys */
8426 sc->port.supported[0] = 0;
8427 sc->port.supported[1] = 0;
8429 switch (sc->link_params.num_phys) {
8431 sc->port.supported[0] =
8432 sc->link_params.phy[ELINK_INT_PHY].supported;
8436 sc->port.supported[0] =
8437 sc->link_params.phy[ELINK_EXT_PHY1].supported;
8441 if (sc->link_params.multi_phy_config &
8442 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
8443 sc->port.supported[1] =
8444 sc->link_params.phy[ELINK_EXT_PHY1].supported;
8445 sc->port.supported[0] =
8446 sc->link_params.phy[ELINK_EXT_PHY2].supported;
8448 sc->port.supported[0] =
8449 sc->link_params.phy[ELINK_EXT_PHY1].supported;
8450 sc->port.supported[1] =
8451 sc->link_params.phy[ELINK_EXT_PHY2].supported;
8457 if (!(sc->port.supported[0] || sc->port.supported[1])) {
8459 "Invalid phy config in NVRAM (PHY1=0x%08x PHY2=0x%08x)",
8461 dev_info.port_hw_config
8462 [port].external_phy_config),
8464 dev_info.port_hw_config
8465 [port].external_phy_config2));
8470 sc->port.phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR);
8472 switch (switch_cfg) {
8473 case ELINK_SWITCH_CFG_1G:
8476 NIG_REG_SERDES0_CTRL_PHY_ADDR + port * 0x10);
8478 case ELINK_SWITCH_CFG_10G:
8481 NIG_REG_XGXS0_CTRL_PHY_ADDR + port * 0x18);
8485 "Invalid switch config in"
8486 "link_config=0x%08x",
8487 sc->port.link_config[0]);
8492 PMD_DRV_LOG(INFO, "PHY addr 0x%08x", sc->port.phy_addr);
8494 /* mask what we support according to speed_cap_mask per configuration */
8495 for (idx = 0; idx < cfg_size; idx++) {
8496 if (!(sc->link_params.speed_cap_mask[idx] &
8497 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) {
8498 sc->port.supported[idx] &=
8499 ~ELINK_SUPPORTED_10baseT_Half;
8502 if (!(sc->link_params.speed_cap_mask[idx] &
8503 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) {
8504 sc->port.supported[idx] &=
8505 ~ELINK_SUPPORTED_10baseT_Full;
8508 if (!(sc->link_params.speed_cap_mask[idx] &
8509 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) {
8510 sc->port.supported[idx] &=
8511 ~ELINK_SUPPORTED_100baseT_Half;
8514 if (!(sc->link_params.speed_cap_mask[idx] &
8515 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) {
8516 sc->port.supported[idx] &=
8517 ~ELINK_SUPPORTED_100baseT_Full;
8520 if (!(sc->link_params.speed_cap_mask[idx] &
8521 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) {
8522 sc->port.supported[idx] &=
8523 ~ELINK_SUPPORTED_1000baseT_Full;
8526 if (!(sc->link_params.speed_cap_mask[idx] &
8527 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) {
8528 sc->port.supported[idx] &=
8529 ~ELINK_SUPPORTED_2500baseX_Full;
8532 if (!(sc->link_params.speed_cap_mask[idx] &
8533 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8534 sc->port.supported[idx] &=
8535 ~ELINK_SUPPORTED_10000baseT_Full;
8538 if (!(sc->link_params.speed_cap_mask[idx] &
8539 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) {
8540 sc->port.supported[idx] &=
8541 ~ELINK_SUPPORTED_20000baseKR2_Full;
8545 PMD_DRV_LOG(INFO, "PHY supported 0=0x%08x 1=0x%08x",
8546 sc->port.supported[0], sc->port.supported[1]);
8549 static void bnx2x_link_settings_requested(struct bnx2x_softc *sc)
8551 uint32_t link_config;
8553 uint32_t cfg_size = 0;
8555 sc->port.advertising[0] = 0;
8556 sc->port.advertising[1] = 0;
8558 switch (sc->link_params.num_phys) {
8568 for (idx = 0; idx < cfg_size; idx++) {
8569 sc->link_params.req_duplex[idx] = DUPLEX_FULL;
8570 link_config = sc->port.link_config[idx];
8572 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
8573 case PORT_FEATURE_LINK_SPEED_AUTO:
8574 if (sc->port.supported[idx] & ELINK_SUPPORTED_Autoneg) {
8575 sc->link_params.req_line_speed[idx] =
8576 ELINK_SPEED_AUTO_NEG;
8577 sc->port.advertising[idx] |=
8578 sc->port.supported[idx];
8579 if (sc->link_params.phy[ELINK_EXT_PHY1].type ==
8580 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833)
8581 sc->port.advertising[idx] |=
8582 (ELINK_SUPPORTED_100baseT_Half |
8583 ELINK_SUPPORTED_100baseT_Full);
8585 /* force 10G, no AN */
8586 sc->link_params.req_line_speed[idx] =
8588 sc->port.advertising[idx] |=
8589 (ADVERTISED_10000baseT_Full |
8595 case PORT_FEATURE_LINK_SPEED_10M_FULL:
8597 port.supported[idx] & ELINK_SUPPORTED_10baseT_Full)
8599 sc->link_params.req_line_speed[idx] =
8601 sc->port.advertising[idx] |=
8602 (ADVERTISED_10baseT_Full | ADVERTISED_TP);
8605 "Invalid NVRAM config link_config=0x%08x "
8606 "speed_cap_mask=0x%08x",
8609 link_params.speed_cap_mask[idx]);
8614 case PORT_FEATURE_LINK_SPEED_10M_HALF:
8616 port.supported[idx] & ELINK_SUPPORTED_10baseT_Half)
8618 sc->link_params.req_line_speed[idx] =
8620 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8621 sc->port.advertising[idx] |=
8622 (ADVERTISED_10baseT_Half | ADVERTISED_TP);
8625 "Invalid NVRAM config link_config=0x%08x "
8626 "speed_cap_mask=0x%08x",
8629 link_params.speed_cap_mask[idx]);
8634 case PORT_FEATURE_LINK_SPEED_100M_FULL:
8636 port.supported[idx] & ELINK_SUPPORTED_100baseT_Full)
8638 sc->link_params.req_line_speed[idx] =
8640 sc->port.advertising[idx] |=
8641 (ADVERTISED_100baseT_Full | ADVERTISED_TP);
8644 "Invalid NVRAM config link_config=0x%08x "
8645 "speed_cap_mask=0x%08x",
8648 link_params.speed_cap_mask[idx]);
8653 case PORT_FEATURE_LINK_SPEED_100M_HALF:
8655 port.supported[idx] & ELINK_SUPPORTED_100baseT_Half)
8657 sc->link_params.req_line_speed[idx] =
8659 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8660 sc->port.advertising[idx] |=
8661 (ADVERTISED_100baseT_Half | ADVERTISED_TP);
8664 "Invalid NVRAM config link_config=0x%08x "
8665 "speed_cap_mask=0x%08x",
8668 link_params.speed_cap_mask[idx]);
8673 case PORT_FEATURE_LINK_SPEED_1G:
8674 if (sc->port.supported[idx] &
8675 ELINK_SUPPORTED_1000baseT_Full) {
8676 sc->link_params.req_line_speed[idx] =
8678 sc->port.advertising[idx] |=
8679 (ADVERTISED_1000baseT_Full | ADVERTISED_TP);
8682 "Invalid NVRAM config link_config=0x%08x "
8683 "speed_cap_mask=0x%08x",
8686 link_params.speed_cap_mask[idx]);
8691 case PORT_FEATURE_LINK_SPEED_2_5G:
8692 if (sc->port.supported[idx] &
8693 ELINK_SUPPORTED_2500baseX_Full) {
8694 sc->link_params.req_line_speed[idx] =
8696 sc->port.advertising[idx] |=
8697 (ADVERTISED_2500baseX_Full | ADVERTISED_TP);
8700 "Invalid NVRAM config link_config=0x%08x "
8701 "speed_cap_mask=0x%08x",
8704 link_params.speed_cap_mask[idx]);
8709 case PORT_FEATURE_LINK_SPEED_10G_CX4:
8710 if (sc->port.supported[idx] &
8711 ELINK_SUPPORTED_10000baseT_Full) {
8712 sc->link_params.req_line_speed[idx] =
8714 sc->port.advertising[idx] |=
8715 (ADVERTISED_10000baseT_Full |
8719 "Invalid NVRAM config link_config=0x%08x "
8720 "speed_cap_mask=0x%08x",
8723 link_params.speed_cap_mask[idx]);
8728 case PORT_FEATURE_LINK_SPEED_20G:
8729 sc->link_params.req_line_speed[idx] = ELINK_SPEED_20000;
8734 "Invalid NVRAM config link_config=0x%08x "
8735 "speed_cap_mask=0x%08x", link_config,
8736 sc->link_params.speed_cap_mask[idx]);
8737 sc->link_params.req_line_speed[idx] =
8738 ELINK_SPEED_AUTO_NEG;
8739 sc->port.advertising[idx] = sc->port.supported[idx];
8743 sc->link_params.req_flow_ctrl[idx] =
8744 (link_config & PORT_FEATURE_FLOW_CONTROL_MASK);
8746 if (sc->link_params.req_flow_ctrl[idx] == ELINK_FLOW_CTRL_AUTO) {
8749 port.supported[idx] & ELINK_SUPPORTED_Autoneg)) {
8750 sc->link_params.req_flow_ctrl[idx] =
8751 ELINK_FLOW_CTRL_NONE;
8753 bnx2x_set_requested_fc(sc);
8759 static void bnx2x_get_phy_info(struct bnx2x_softc *sc)
8761 uint8_t port = SC_PORT(sc);
8764 PMD_INIT_FUNC_TRACE();
8766 /* shmem data already read in bnx2x_get_shmem_info() */
8768 bnx2x_link_settings_supported(sc, sc->link_params.switch_cfg);
8769 bnx2x_link_settings_requested(sc);
8771 /* configure link feature according to nvram value */
8773 (((SHMEM_RD(sc, dev_info.port_feature_config[port].eee_power_mode))
8774 & PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
8775 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
8776 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
8777 sc->link_params.eee_mode = (ELINK_EEE_MODE_ADV_LPI |
8778 ELINK_EEE_MODE_ENABLE_LPI |
8779 ELINK_EEE_MODE_OUTPUT_TIME);
8781 sc->link_params.eee_mode = 0;
8784 /* get the media type */
8785 bnx2x_media_detect(sc);
8788 static void bnx2x_set_modes_bitmap(struct bnx2x_softc *sc)
8790 uint32_t flags = MODE_ASIC | MODE_PORT2;
8792 if (CHIP_IS_E2(sc)) {
8794 } else if (CHIP_IS_E3(sc)) {
8796 if (CHIP_REV(sc) == CHIP_REV_Ax) {
8797 flags |= MODE_E3_A0;
8798 } else { /*if (CHIP_REV(sc) == CHIP_REV_Bx) */
8800 flags |= MODE_E3_B0 | MODE_COS3;
8806 switch (sc->devinfo.mf_info.mf_mode) {
8807 case MULTI_FUNCTION_SD:
8808 flags |= MODE_MF_SD;
8810 case MULTI_FUNCTION_SI:
8811 flags |= MODE_MF_SI;
8813 case MULTI_FUNCTION_AFEX:
8814 flags |= MODE_MF_AFEX;
8821 #if defined(__LITTLE_ENDIAN)
8822 flags |= MODE_LITTLE_ENDIAN;
8823 #else /* __BIG_ENDIAN */
8824 flags |= MODE_BIG_ENDIAN;
8827 INIT_MODE_FLAGS(sc) = flags;
8830 int bnx2x_alloc_hsi_mem(struct bnx2x_softc *sc)
8832 struct bnx2x_fastpath *fp;
8837 /************************/
8838 /* DEFAULT STATUS BLOCK */
8839 /************************/
8841 if (bnx2x_dma_alloc(sc, sizeof(struct host_sp_status_block),
8842 &sc->def_sb_dma, "def_sb",
8843 RTE_CACHE_LINE_SIZE) != 0) {
8848 (struct host_sp_status_block *)sc->def_sb_dma.vaddr;
8853 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8854 &sc->eq_dma, "ev_queue",
8855 RTE_CACHE_LINE_SIZE) != 0) {
8860 sc->eq = (union event_ring_elem *)sc->eq_dma.vaddr;
8866 if (bnx2x_dma_alloc(sc, sizeof(struct bnx2x_slowpath),
8868 RTE_CACHE_LINE_SIZE) != 0) {
8874 sc->sp = (struct bnx2x_slowpath *)sc->sp_dma.vaddr;
8876 /*******************/
8877 /* SLOW PATH QUEUE */
8878 /*******************/
8880 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8881 &sc->spq_dma, "sp_queue",
8882 RTE_CACHE_LINE_SIZE) != 0) {
8889 sc->spq = (struct eth_spe *)sc->spq_dma.vaddr;
8891 /***************************/
8892 /* FW DECOMPRESSION BUFFER */
8893 /***************************/
8895 if (bnx2x_dma_alloc(sc, FW_BUF_SIZE, &sc->gz_buf_dma,
8896 "fw_dec_buf", RTE_CACHE_LINE_SIZE) != 0) {
8904 sc->gz_buf = (void *)sc->gz_buf_dma.vaddr;
8911 /* allocate DMA memory for each fastpath structure */
8912 for (i = 0; i < sc->num_queues; i++) {
8917 /*******************/
8918 /* FP STATUS BLOCK */
8919 /*******************/
8921 snprintf(buf, sizeof(buf), "fp_%d_sb", i);
8922 if (bnx2x_dma_alloc(sc, sizeof(union bnx2x_host_hc_status_block),
8923 &fp->sb_dma, buf, RTE_CACHE_LINE_SIZE) != 0) {
8924 PMD_DRV_LOG(NOTICE, "Failed to alloc %s", buf);
8927 if (CHIP_IS_E2E3(sc)) {
8928 fp->status_block.e2_sb =
8929 (struct host_hc_status_block_e2 *)
8932 fp->status_block.e1x_sb =
8933 (struct host_hc_status_block_e1x *)
8942 void bnx2x_free_hsi_mem(struct bnx2x_softc *sc)
8944 struct bnx2x_fastpath *fp;
8947 for (i = 0; i < sc->num_queues; i++) {
8950 /*******************/
8951 /* FP STATUS BLOCK */
8952 /*******************/
8954 memset(&fp->status_block, 0, sizeof(fp->status_block));
8957 /***************************/
8958 /* FW DECOMPRESSION BUFFER */
8959 /***************************/
8963 /*******************/
8964 /* SLOW PATH QUEUE */
8965 /*******************/
8981 /************************/
8982 /* DEFAULT STATUS BLOCK */
8983 /************************/
8990 * Previous driver DMAE transaction may have occurred when pre-boot stage
8991 * ended and boot began. This would invalidate the addresses of the
8992 * transaction, resulting in was-error bit set in the PCI causing all
8993 * hw-to-host PCIe transactions to timeout. If this happened we want to clear
8994 * the interrupt which detected this from the pglueb and the was-done bit
8996 static void bnx2x_prev_interrupted_dmae(struct bnx2x_softc *sc)
9000 if (!CHIP_IS_E1x(sc)) {
9001 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS);
9002 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
9003 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
9009 static int bnx2x_prev_mcp_done(struct bnx2x_softc *sc)
9011 uint32_t rc = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE,
9012 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
9014 PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
9021 static struct bnx2x_prev_list_node *bnx2x_prev_path_get_entry(struct bnx2x_softc *sc)
9023 struct bnx2x_prev_list_node *tmp;
9025 LIST_FOREACH(tmp, &bnx2x_prev_list, node) {
9026 if ((sc->pcie_bus == tmp->bus) &&
9027 (sc->pcie_device == tmp->slot) &&
9028 (SC_PATH(sc) == tmp->path)) {
9036 static uint8_t bnx2x_prev_is_path_marked(struct bnx2x_softc *sc)
9038 struct bnx2x_prev_list_node *tmp;
9041 rte_spinlock_lock(&bnx2x_prev_mtx);
9043 tmp = bnx2x_prev_path_get_entry(sc);
9047 "Path %d/%d/%d was marked by AER",
9048 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9052 "Path %d/%d/%d was already cleaned from previous drivers",
9053 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9057 rte_spinlock_unlock(&bnx2x_prev_mtx);
9062 static int bnx2x_prev_mark_path(struct bnx2x_softc *sc, uint8_t after_undi)
9064 struct bnx2x_prev_list_node *tmp;
9066 rte_spinlock_lock(&bnx2x_prev_mtx);
9068 /* Check whether the entry for this path already exists */
9069 tmp = bnx2x_prev_path_get_entry(sc);
9073 "Re-marking AER in path %d/%d/%d",
9074 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9077 "Removing AER indication from path %d/%d/%d",
9078 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9082 rte_spinlock_unlock(&bnx2x_prev_mtx);
9086 rte_spinlock_unlock(&bnx2x_prev_mtx);
9088 /* Create an entry for this path and add it */
9089 tmp = rte_malloc("", sizeof(struct bnx2x_prev_list_node),
9090 RTE_CACHE_LINE_SIZE);
9092 PMD_DRV_LOG(NOTICE, "Failed to allocate 'bnx2x_prev_list_node'");
9096 tmp->bus = sc->pcie_bus;
9097 tmp->slot = sc->pcie_device;
9098 tmp->path = SC_PATH(sc);
9100 tmp->undi = after_undi ? (1 << SC_PORT(sc)) : 0;
9102 rte_spinlock_lock(&bnx2x_prev_mtx);
9104 LIST_INSERT_HEAD(&bnx2x_prev_list, tmp, node);
9106 rte_spinlock_unlock(&bnx2x_prev_mtx);
9111 static int bnx2x_do_flr(struct bnx2x_softc *sc)
9115 /* only E2 and onwards support FLR */
9116 if (CHIP_IS_E1x(sc)) {
9117 PMD_DRV_LOG(WARNING, "FLR not supported in E1H");
9121 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9122 if (sc->devinfo.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9123 PMD_DRV_LOG(WARNING,
9124 "FLR not supported by BC_VER: 0x%08x",
9125 sc->devinfo.bc_ver);
9129 /* Wait for Transaction Pending bit clean */
9130 for (i = 0; i < 4; i++) {
9132 DELAY(((1 << (i - 1)) * 100) * 1000);
9135 if (!bnx2x_is_pcie_pending(sc)) {
9140 PMD_DRV_LOG(NOTICE, "PCIE transaction is not cleared, "
9141 "proceeding with reset anyway");
9144 bnx2x_fw_command(sc, DRV_MSG_CODE_INITIATE_FLR, 0);
9149 struct bnx2x_mac_vals {
9157 uint32_t bmac_val[2];
9161 bnx2x_prev_unload_close_mac(struct bnx2x_softc *sc, struct bnx2x_mac_vals *vals)
9163 uint32_t val, base_addr, offset, mask, reset_reg;
9164 uint8_t mac_stopped = FALSE;
9165 uint8_t port = SC_PORT(sc);
9166 uint32_t wb_data[2];
9168 /* reset addresses as they also mark which values were changed */
9169 vals->bmac_addr = 0;
9170 vals->umac_addr = 0;
9171 vals->xmac_addr = 0;
9172 vals->emac_addr = 0;
9174 reset_reg = REG_RD(sc, MISC_REG_RESET_REG_2);
9176 if (!CHIP_IS_E3(sc)) {
9177 val = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9178 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9179 if ((mask & reset_reg) && val) {
9180 base_addr = SC_PORT(sc) ? NIG_REG_INGRESS_BMAC1_MEM
9181 : NIG_REG_INGRESS_BMAC0_MEM;
9182 offset = CHIP_IS_E2(sc) ? BIGMAC2_REGISTER_BMAC_CONTROL
9183 : BIGMAC_REGISTER_BMAC_CONTROL;
9186 * use rd/wr since we cannot use dmae. This is safe
9187 * since MCP won't access the bus due to the request
9188 * to unload, and no function on the path can be
9189 * loaded at this time.
9191 wb_data[0] = REG_RD(sc, base_addr + offset);
9192 wb_data[1] = REG_RD(sc, base_addr + offset + 0x4);
9193 vals->bmac_addr = base_addr + offset;
9194 vals->bmac_val[0] = wb_data[0];
9195 vals->bmac_val[1] = wb_data[1];
9196 wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE;
9197 REG_WR(sc, vals->bmac_addr, wb_data[0]);
9198 REG_WR(sc, vals->bmac_addr + 0x4, wb_data[1]);
9201 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + SC_PORT(sc) * 4;
9202 vals->emac_val = REG_RD(sc, vals->emac_addr);
9203 REG_WR(sc, vals->emac_addr, 0);
9206 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9207 base_addr = SC_PORT(sc) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9208 val = REG_RD(sc, base_addr + XMAC_REG_PFC_CTRL_HI);
9209 REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9211 REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9213 vals->xmac_addr = base_addr + XMAC_REG_CTRL;
9214 vals->xmac_val = REG_RD(sc, vals->xmac_addr);
9215 REG_WR(sc, vals->xmac_addr, 0);
9219 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9220 if (mask & reset_reg) {
9221 base_addr = SC_PORT(sc) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9222 vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
9223 vals->umac_val = REG_RD(sc, vals->umac_addr);
9224 REG_WR(sc, vals->umac_addr, 0);
9234 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9235 #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
9236 #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
9237 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
9240 bnx2x_prev_unload_undi_inc(struct bnx2x_softc *sc, uint8_t port, uint8_t inc)
9243 uint32_t tmp_reg = REG_RD(sc, BNX2X_PREV_UNDI_PROD_ADDR(port));
9245 rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9246 bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9248 tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9249 REG_WR(sc, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9252 static int bnx2x_prev_unload_common(struct bnx2x_softc *sc)
9254 uint32_t reset_reg, tmp_reg = 0, rc;
9255 uint8_t prev_undi = FALSE;
9256 struct bnx2x_mac_vals mac_vals;
9257 uint32_t timer_count = 1000;
9261 * It is possible a previous function received 'common' answer,
9262 * but hasn't loaded yet, therefore creating a scenario of
9263 * multiple functions receiving 'common' on the same path.
9265 memset(&mac_vals, 0, sizeof(mac_vals));
9267 if (bnx2x_prev_is_path_marked(sc)) {
9268 return bnx2x_prev_mcp_done(sc);
9271 reset_reg = REG_RD(sc, MISC_REG_RESET_REG_1);
9273 /* Reset should be performed after BRB is emptied */
9274 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
9275 /* Close the MAC Rx to prevent BRB from filling up */
9276 bnx2x_prev_unload_close_mac(sc, &mac_vals);
9278 /* close LLH filters towards the BRB */
9279 elink_set_rx_filter(&sc->link_params, 0);
9282 * Check if the UNDI driver was previously loaded.
9283 * UNDI driver initializes CID offset for normal bell to 0x7
9285 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
9286 tmp_reg = REG_RD(sc, DORQ_REG_NORM_CID_OFST);
9287 if (tmp_reg == 0x7) {
9288 PMD_DRV_LOG(DEBUG, "UNDI previously loaded");
9290 /* clear the UNDI indication */
9291 REG_WR(sc, DORQ_REG_NORM_CID_OFST, 0);
9292 /* clear possible idle check errors */
9293 REG_RD(sc, NIG_REG_NIG_INT_STS_CLR_0);
9297 /* wait until BRB is empty */
9298 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9299 while (timer_count) {
9302 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9307 PMD_DRV_LOG(DEBUG, "BRB still has 0x%08x", tmp_reg);
9309 /* reset timer as long as BRB actually gets emptied */
9310 if (prev_brb > tmp_reg) {
9316 /* If UNDI resides in memory, manually increment it */
9318 bnx2x_prev_unload_undi_inc(sc, SC_PORT(sc), 1);
9325 PMD_DRV_LOG(NOTICE, "Failed to empty BRB");
9329 /* No packets are in the pipeline, path is ready for reset */
9330 bnx2x_reset_common(sc);
9332 if (mac_vals.xmac_addr) {
9333 REG_WR(sc, mac_vals.xmac_addr, mac_vals.xmac_val);
9335 if (mac_vals.umac_addr) {
9336 REG_WR(sc, mac_vals.umac_addr, mac_vals.umac_val);
9338 if (mac_vals.emac_addr) {
9339 REG_WR(sc, mac_vals.emac_addr, mac_vals.emac_val);
9341 if (mac_vals.bmac_addr) {
9342 REG_WR(sc, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
9343 REG_WR(sc, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
9346 rc = bnx2x_prev_mark_path(sc, prev_undi);
9348 bnx2x_prev_mcp_done(sc);
9352 return bnx2x_prev_mcp_done(sc);
9355 static int bnx2x_prev_unload_uncommon(struct bnx2x_softc *sc)
9359 /* Test if previous unload process was already finished for this path */
9360 if (bnx2x_prev_is_path_marked(sc)) {
9361 return bnx2x_prev_mcp_done(sc);
9365 * If function has FLR capabilities, and existing FW version matches
9366 * the one required, then FLR will be sufficient to clean any residue
9367 * left by previous driver
9369 rc = bnx2x_nic_load_analyze_req(sc, FW_MSG_CODE_DRV_LOAD_FUNCTION);
9371 /* fw version is good */
9372 rc = bnx2x_do_flr(sc);
9376 /* FLR was performed */
9380 PMD_DRV_LOG(INFO, "Could not FLR");
9382 /* Close the MCP request, return failure */
9383 rc = bnx2x_prev_mcp_done(sc);
9385 rc = BNX2X_PREV_WAIT_NEEDED;
9391 static int bnx2x_prev_unload(struct bnx2x_softc *sc)
9393 int time_counter = 10;
9394 uint32_t fw, hw_lock_reg, hw_lock_val;
9398 * Clear HW from errors which may have resulted from an interrupted
9401 bnx2x_prev_interrupted_dmae(sc);
9403 /* Release previously held locks */
9404 if (SC_FUNC(sc) <= 5)
9405 hw_lock_reg = (MISC_REG_DRIVER_CONTROL_1 + SC_FUNC(sc) * 8);
9408 (MISC_REG_DRIVER_CONTROL_7 + (SC_FUNC(sc) - 6) * 8);
9410 hw_lock_val = (REG_RD(sc, hw_lock_reg));
9412 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
9413 REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
9414 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << SC_PORT(sc)));
9416 REG_WR(sc, hw_lock_reg, 0xffffffff);
9419 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(sc, MCP_REG_MCPR_ACCESS_LOCK)) {
9420 REG_WR(sc, MCP_REG_MCPR_ACCESS_LOCK, 0);
9424 /* Lock MCP using an unload request */
9425 fw = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
9427 PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
9432 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
9433 rc = bnx2x_prev_unload_common(sc);
9437 /* non-common reply from MCP might require looping */
9438 rc = bnx2x_prev_unload_uncommon(sc);
9439 if (rc != BNX2X_PREV_WAIT_NEEDED) {
9444 } while (--time_counter);
9446 if (!time_counter || rc) {
9447 PMD_DRV_LOG(NOTICE, "Failed to unload previous driver!");
9455 bnx2x_dcbx_set_state(struct bnx2x_softc *sc, uint8_t dcb_on, uint32_t dcbx_enabled)
9457 if (!CHIP_IS_E1x(sc)) {
9458 sc->dcb_state = dcb_on;
9459 sc->dcbx_enabled = dcbx_enabled;
9461 sc->dcb_state = FALSE;
9462 sc->dcbx_enabled = BNX2X_DCBX_ENABLED_INVALID;
9465 "DCB state [%s:%s]",
9466 dcb_on ? "ON" : "OFF",
9467 (dcbx_enabled == BNX2X_DCBX_ENABLED_OFF) ? "user-mode" :
9469 BNX2X_DCBX_ENABLED_ON_NEG_OFF) ? "on-chip static"
9471 BNX2X_DCBX_ENABLED_ON_NEG_ON) ?
9472 "on-chip with negotiation" : "invalid");
9475 static int bnx2x_set_qm_cid_count(struct bnx2x_softc *sc)
9477 int cid_count = BNX2X_L2_MAX_CID(sc);
9479 if (CNIC_SUPPORT(sc)) {
9480 cid_count += CNIC_CID_MAX;
9483 return roundup(cid_count, QM_CID_ROUND);
9486 static void bnx2x_init_multi_cos(struct bnx2x_softc *sc)
9490 uint32_t pri_map = 0;
9492 for (pri = 0; pri < BNX2X_MAX_PRIORITY; pri++) {
9493 cos = ((pri_map & (0xf << (pri * 4))) >> (pri * 4));
9494 if (cos < sc->max_cos) {
9495 sc->prio_to_cos[pri] = cos;
9497 PMD_DRV_LOG(WARNING,
9498 "Invalid COS %d for priority %d "
9499 "(max COS is %d), setting to 0", cos, pri,
9501 sc->prio_to_cos[pri] = 0;
9506 static int bnx2x_pci_get_caps(struct bnx2x_softc *sc)
9513 struct bnx2x_pci_cap *cap;
9515 cap = sc->pci_caps = rte_zmalloc("caps", sizeof(struct bnx2x_pci_cap),
9516 RTE_CACHE_LINE_SIZE);
9518 PMD_DRV_LOG(NOTICE, "Failed to allocate memory");
9523 pci_read(sc, PCI_STATUS, &status, 2);
9524 if (!(status & PCI_STATUS_CAP_LIST)) {
9526 pci_read(sc, PCIR_STATUS, &status, 2);
9527 if (!(status & PCIM_STATUS_CAPPRESENT)) {
9529 PMD_DRV_LOG(NOTICE, "PCIe capability reading failed");
9534 pci_read(sc, PCI_CAPABILITY_LIST, &pci_cap.next, 1);
9536 pci_read(sc, PCIR_CAP_PTR, &pci_cap.next, 1);
9538 while (pci_cap.next) {
9539 cap->addr = pci_cap.next & ~3;
9540 pci_read(sc, pci_cap.next & ~3, &pci_cap, 2);
9541 if (pci_cap.id == 0xff)
9543 cap->id = pci_cap.id;
9544 cap->type = BNX2X_PCI_CAP;
9545 cap->next = rte_zmalloc("pci_cap",
9546 sizeof(struct bnx2x_pci_cap),
9547 RTE_CACHE_LINE_SIZE);
9549 PMD_DRV_LOG(NOTICE, "Failed to allocate memory");
9558 static void bnx2x_init_rte(struct bnx2x_softc *sc)
9560 sc->max_tx_queues = 128;
9561 sc->max_rx_queues = 128;
9564 #define FW_HEADER_LEN 104
9565 #define FW_NAME_57711 "/lib/firmware/bnx2x/bnx2x-e1h-7.2.51.0.fw"
9566 #define FW_NAME_57810 "/lib/firmware/bnx2x/bnx2x-e2-7.2.51.0.fw"
9568 void bnx2x_load_firmware(struct bnx2x_softc *sc)
9574 fwname = sc->devinfo.device_id == BNX2X_DEV_ID_57711
9575 ? FW_NAME_57711 : FW_NAME_57810;
9576 f = open(fwname, O_RDONLY);
9578 PMD_DRV_LOG(NOTICE, "Can't open firmware file");
9582 if (fstat(f, &st) < 0) {
9583 PMD_DRV_LOG(NOTICE, "Can't stat firmware file");
9588 sc->firmware = rte_zmalloc("bnx2x_fw", st.st_size, RTE_CACHE_LINE_SIZE);
9589 if (!sc->firmware) {
9590 PMD_DRV_LOG(NOTICE, "Can't allocate memory for firmware");
9595 if (read(f, sc->firmware, st.st_size) != st.st_size) {
9596 PMD_DRV_LOG(NOTICE, "Can't read firmware data");
9602 sc->fw_len = st.st_size;
9603 if (sc->fw_len < FW_HEADER_LEN) {
9604 PMD_DRV_LOG(NOTICE, "Invalid fw size: %" PRIu64, sc->fw_len);
9607 PMD_DRV_LOG(DEBUG, "fw_len = %" PRIu64, sc->fw_len);
9611 bnx2x_data_to_init_ops(uint8_t * data, struct raw_op *dst, uint32_t len)
9613 uint32_t *src = (uint32_t *) data;
9616 for (i = 0, j = 0; i < len / 8; ++i, j += 2) {
9617 tmp = rte_be_to_cpu_32(src[j]);
9618 dst[i].op = (tmp >> 24) & 0xFF;
9619 dst[i].offset = tmp & 0xFFFFFF;
9620 dst[i].raw_data = rte_be_to_cpu_32(src[j + 1]);
9625 bnx2x_data_to_init_offsets(uint8_t * data, uint16_t * dst, uint32_t len)
9627 uint16_t *src = (uint16_t *) data;
9630 for (i = 0; i < len / 2; ++i)
9631 dst[i] = rte_be_to_cpu_16(src[i]);
9634 static void bnx2x_data_to_init_data(uint8_t * data, uint32_t * dst, uint32_t len)
9636 uint32_t *src = (uint32_t *) data;
9639 for (i = 0; i < len / 4; ++i)
9640 dst[i] = rte_be_to_cpu_32(src[i]);
9643 static void bnx2x_data_to_iro_array(uint8_t * data, struct iro *dst, uint32_t len)
9645 uint32_t *src = (uint32_t *) data;
9648 for (i = 0, j = 0; i < len / sizeof(struct iro); ++i, ++j) {
9649 dst[i].base = rte_be_to_cpu_32(src[j++]);
9650 tmp = rte_be_to_cpu_32(src[j]);
9651 dst[i].m1 = (tmp >> 16) & 0xFFFF;
9652 dst[i].m2 = tmp & 0xFFFF;
9654 tmp = rte_be_to_cpu_32(src[j]);
9655 dst[i].m3 = (tmp >> 16) & 0xFFFF;
9656 dst[i].size = tmp & 0xFFFF;
9661 * Device attach function.
9663 * Allocates device resources, performs secondary chip identification, and
9664 * initializes driver instance variables. This function is called from driver
9665 * load after a successful probe.
9668 * 0 = Success, >0 = Failure
9670 int bnx2x_attach(struct bnx2x_softc *sc)
9674 PMD_DRV_LOG(DEBUG, "Starting attach...");
9676 rc = bnx2x_pci_get_caps(sc);
9678 PMD_DRV_LOG(NOTICE, "PCIe caps reading was failed");
9682 sc->state = BNX2X_STATE_CLOSED;
9684 /* Init RTE stuff */
9687 pci_write_long(sc, PCICFG_GRC_ADDRESS, PCICFG_VENDOR_ID_OFFSET);
9689 sc->igu_base_addr = IS_VF(sc) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
9691 /* get PCI capabilites */
9692 bnx2x_probe_pci_caps(sc);
9694 if (sc->devinfo.pcie_msix_cap_reg != 0) {
9697 (sc->devinfo.pcie_msix_cap_reg + PCIR_MSIX_CTRL), &val,
9699 sc->igu_sb_cnt = (val & PCIM_MSIXCTRL_TABLE_SIZE);
9705 /* get device info and set params */
9706 if (bnx2x_get_device_info(sc) != 0) {
9707 PMD_DRV_LOG(NOTICE, "getting device info");
9711 /* get phy settings from shmem and 'and' against admin settings */
9712 bnx2x_get_phy_info(sc);
9714 /* Left mac of VF unfilled, PF should set it for VF */
9715 memset(sc->link_params.mac_addr, 0, ETHER_ADDR_LEN);
9720 /* set the default MTU (changed via ifconfig) */
9721 sc->mtu = ETHER_MTU;
9723 bnx2x_set_modes_bitmap(sc);
9725 /* need to reset chip if UNDI was active */
9726 if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
9729 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
9730 DRV_MSG_SEQ_NUMBER_MASK);
9731 bnx2x_prev_unload(sc);
9734 bnx2x_dcbx_set_state(sc, FALSE, BNX2X_DCBX_ENABLED_OFF);
9736 /* calculate qm_cid_count */
9737 sc->qm_cid_count = bnx2x_set_qm_cid_count(sc);
9740 bnx2x_init_multi_cos(sc);
9746 bnx2x_igu_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t segment,
9747 uint16_t index, uint8_t op, uint8_t update)
9749 uint32_t igu_addr = sc->igu_base_addr;
9750 igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
9751 bnx2x_igu_ack_sb_gen(sc, segment, index, op, update, igu_addr);
9755 bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t storm,
9756 uint16_t index, uint8_t op, uint8_t update)
9758 if (unlikely(sc->devinfo.int_block == INT_BLOCK_HC))
9759 bnx2x_hc_ack_sb(sc, igu_sb_id, storm, index, op, update);
9762 if (CHIP_INT_MODE_IS_BC(sc)) {
9764 } else if (igu_sb_id != sc->igu_dsb_id) {
9765 segment = IGU_SEG_ACCESS_DEF;
9766 } else if (storm == ATTENTION_ID) {
9767 segment = IGU_SEG_ACCESS_ATTN;
9769 segment = IGU_SEG_ACCESS_DEF;
9771 bnx2x_igu_ack_sb(sc, igu_sb_id, segment, index, op, update);
9776 bnx2x_igu_clear_sb_gen(struct bnx2x_softc *sc, uint8_t func, uint8_t idu_sb_id,
9779 uint32_t data, ctl, cnt = 100;
9780 uint32_t igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
9781 uint32_t igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
9782 uint32_t igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP +
9783 (idu_sb_id / 32) * 4;
9784 uint32_t sb_bit = 1 << (idu_sb_id % 32);
9785 uint32_t func_encode = func |
9786 (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
9787 uint32_t addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
9789 /* Not supported in BC mode */
9790 if (CHIP_INT_MODE_IS_BC(sc)) {
9794 data = ((IGU_USE_REGISTER_cstorm_type_0_sb_cleanup <<
9795 IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
9796 IGU_REGULAR_CLEANUP_SET | IGU_REGULAR_BCLEANUP);
9798 ctl = ((addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT) |
9799 (func_encode << IGU_CTRL_REG_FID_SHIFT) |
9800 (IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT));
9802 REG_WR(sc, igu_addr_data, data);
9806 PMD_DRV_LOG(DEBUG, "write 0x%08x to IGU(via GRC) addr 0x%x",
9808 REG_WR(sc, igu_addr_ctl, ctl);
9812 /* wait for clean up to finish */
9813 while (!(REG_RD(sc, igu_addr_ack) & sb_bit) && --cnt) {
9817 if (!(REG_RD(sc, igu_addr_ack) & sb_bit)) {
9819 "Unable to finish IGU cleanup: "
9820 "idu_sb_id %d offset %d bit %d (cnt %d)",
9821 idu_sb_id, idu_sb_id / 32, idu_sb_id % 32, cnt);
9825 static void bnx2x_igu_clear_sb(struct bnx2x_softc *sc, uint8_t idu_sb_id)
9827 bnx2x_igu_clear_sb_gen(sc, SC_FUNC(sc), idu_sb_id, TRUE /*PF*/);
9830 /*******************/
9831 /* ECORE CALLBACKS */
9832 /*******************/
9834 static void bnx2x_reset_common(struct bnx2x_softc *sc)
9836 uint32_t val = 0x1400;
9838 PMD_INIT_FUNC_TRACE();
9841 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR),
9844 if (CHIP_IS_E3(sc)) {
9845 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
9846 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
9849 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR), val);
9852 static void bnx2x_common_init_phy(struct bnx2x_softc *sc)
9854 uint32_t shmem_base[2];
9855 uint32_t shmem2_base[2];
9857 /* Avoid common init in case MFW supports LFA */
9858 if (SHMEM2_RD(sc, size) >
9859 (uint32_t) offsetof(struct shmem2_region,
9860 lfa_host_addr[SC_PORT(sc)])) {
9864 shmem_base[0] = sc->devinfo.shmem_base;
9865 shmem2_base[0] = sc->devinfo.shmem2_base;
9867 if (!CHIP_IS_E1x(sc)) {
9868 shmem_base[1] = SHMEM2_RD(sc, other_shmem_base_addr);
9869 shmem2_base[1] = SHMEM2_RD(sc, other_shmem2_base_addr);
9872 elink_common_init_phy(sc, shmem_base, shmem2_base,
9873 sc->devinfo.chip_id, 0);
9876 static void bnx2x_pf_disable(struct bnx2x_softc *sc)
9878 uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
9880 val &= ~IGU_PF_CONF_FUNC_EN;
9882 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
9883 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
9884 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 0);
9887 static void bnx2x_init_pxp(struct bnx2x_softc *sc)
9890 int r_order, w_order;
9892 devctl = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_CTL);
9894 w_order = ((devctl & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5);
9895 r_order = ((devctl & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12);
9897 ecore_init_pxp_arb(sc, r_order, w_order);
9900 static uint32_t bnx2x_get_pretend_reg(struct bnx2x_softc *sc)
9902 uint32_t base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9903 uint32_t stride = (PXP2_REG_PGL_PRETEND_FUNC_F1 - base);
9904 return (base + (SC_ABS_FUNC(sc)) * stride);
9908 * Called only on E1H or E2.
9909 * When pretending to be PF, the pretend value is the function number 0..7.
9910 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
9913 static int bnx2x_pretend_func(struct bnx2x_softc *sc, uint16_t pretend_func_val)
9915 uint32_t pretend_reg;
9917 if (CHIP_IS_E1H(sc) && (pretend_func_val > E1H_FUNC_MAX))
9920 /* get my own pretend register */
9921 pretend_reg = bnx2x_get_pretend_reg(sc);
9922 REG_WR(sc, pretend_reg, pretend_func_val);
9923 REG_RD(sc, pretend_reg);
9927 static void bnx2x_setup_fan_failure_detection(struct bnx2x_softc *sc)
9934 val = (SHMEM_RD(sc, dev_info.shared_hw_config.config2) &
9935 SHARED_HW_CFG_FAN_FAILURE_MASK);
9937 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) {
9941 * The fan failure mechanism is usually related to the PHY type since
9942 * the power consumption of the board is affected by the PHY. Currently,
9943 * fan is required for most designs with SFX7101, BNX2X8727 and BNX2X8481.
9945 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) {
9946 for (port = PORT_0; port < PORT_MAX; port++) {
9947 is_required |= elink_fan_failure_det_req(sc,
9951 devinfo.shmem2_base,
9956 if (is_required == 0) {
9960 /* Fan failure is indicated by SPIO 5 */
9961 bnx2x_set_spio(sc, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
9963 /* set to active low mode */
9964 val = REG_RD(sc, MISC_REG_SPIO_INT);
9965 val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
9966 REG_WR(sc, MISC_REG_SPIO_INT, val);
9968 /* enable interrupt to signal the IGU */
9969 val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
9970 val |= MISC_SPIO_SPIO5;
9971 REG_WR(sc, MISC_REG_SPIO_EVENT_EN, val);
9974 static void bnx2x_enable_blocks_attention(struct bnx2x_softc *sc)
9978 REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0);
9979 if (!CHIP_IS_E1x(sc)) {
9980 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0x40);
9982 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0);
9984 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
9985 REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
9987 * mask read length error interrupts in brb for parser
9988 * (parsing unit and 'checksum and crc' unit)
9989 * these errors are legal (PU reads fixed length and CAC can cause
9990 * read length error on truncated packets)
9992 REG_WR(sc, BRB1_REG_BRB1_INT_MASK, 0xFC00);
9993 REG_WR(sc, QM_REG_QM_INT_MASK, 0);
9994 REG_WR(sc, TM_REG_TM_INT_MASK, 0);
9995 REG_WR(sc, XSDM_REG_XSDM_INT_MASK_0, 0);
9996 REG_WR(sc, XSDM_REG_XSDM_INT_MASK_1, 0);
9997 REG_WR(sc, XCM_REG_XCM_INT_MASK, 0);
9998 /* REG_WR(sc, XSEM_REG_XSEM_INT_MASK_0, 0); */
9999 /* REG_WR(sc, XSEM_REG_XSEM_INT_MASK_1, 0); */
10000 REG_WR(sc, USDM_REG_USDM_INT_MASK_0, 0);
10001 REG_WR(sc, USDM_REG_USDM_INT_MASK_1, 0);
10002 REG_WR(sc, UCM_REG_UCM_INT_MASK, 0);
10003 /* REG_WR(sc, USEM_REG_USEM_INT_MASK_0, 0); */
10004 /* REG_WR(sc, USEM_REG_USEM_INT_MASK_1, 0); */
10005 REG_WR(sc, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
10006 REG_WR(sc, CSDM_REG_CSDM_INT_MASK_0, 0);
10007 REG_WR(sc, CSDM_REG_CSDM_INT_MASK_1, 0);
10008 REG_WR(sc, CCM_REG_CCM_INT_MASK, 0);
10009 /* REG_WR(sc, CSEM_REG_CSEM_INT_MASK_0, 0); */
10010 /* REG_WR(sc, CSEM_REG_CSEM_INT_MASK_1, 0); */
10012 val = (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
10013 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
10014 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN);
10015 if (!CHIP_IS_E1x(sc)) {
10016 val |= (PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
10017 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED);
10019 REG_WR(sc, PXP2_REG_PXP2_INT_MASK_0, val);
10021 REG_WR(sc, TSDM_REG_TSDM_INT_MASK_0, 0);
10022 REG_WR(sc, TSDM_REG_TSDM_INT_MASK_1, 0);
10023 REG_WR(sc, TCM_REG_TCM_INT_MASK, 0);
10024 /* REG_WR(sc, TSEM_REG_TSEM_INT_MASK_0, 0); */
10026 if (!CHIP_IS_E1x(sc)) {
10027 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
10028 REG_WR(sc, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
10031 REG_WR(sc, CDU_REG_CDU_INT_MASK, 0);
10032 REG_WR(sc, DMAE_REG_DMAE_INT_MASK, 0);
10033 /* REG_WR(sc, MISC_REG_MISC_INT_MASK, 0); */
10034 REG_WR(sc, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
10038 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
10040 * @sc: driver handle
10042 static int bnx2x_init_hw_common(struct bnx2x_softc *sc)
10044 uint8_t abs_func_id;
10047 PMD_DRV_LOG(DEBUG, "starting common init for func %d", SC_ABS_FUNC(sc));
10050 * take the RESET lock to protect undi_unload flow from accessing
10051 * registers while we are resetting the chip
10053 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10055 bnx2x_reset_common(sc);
10057 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET), 0xffffffff);
10060 if (CHIP_IS_E3(sc)) {
10061 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
10062 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
10065 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET), val);
10067 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10069 ecore_init_block(sc, BLOCK_MISC, PHASE_COMMON);
10071 if (!CHIP_IS_E1x(sc)) {
10073 * 4-port mode or 2-port mode we need to turn off master-enable for
10074 * everyone. After that we turn it back on for self. So, we disregard
10075 * multi-function, and always disable all functions on the given path,
10076 * this means 0,2,4,6 for path 0 and 1,3,5,7 for path 1
10078 for (abs_func_id = SC_PATH(sc);
10079 abs_func_id < (E2_FUNC_MAX * 2); abs_func_id += 2) {
10080 if (abs_func_id == SC_ABS_FUNC(sc)) {
10082 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
10087 bnx2x_pretend_func(sc, abs_func_id);
10089 /* clear pf enable */
10090 bnx2x_pf_disable(sc);
10092 bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10096 ecore_init_block(sc, BLOCK_PXP, PHASE_COMMON);
10098 ecore_init_block(sc, BLOCK_PXP2, PHASE_COMMON);
10099 bnx2x_init_pxp(sc);
10101 #ifdef __BIG_ENDIAN
10102 REG_WR(sc, PXP2_REG_RQ_QM_ENDIAN_M, 1);
10103 REG_WR(sc, PXP2_REG_RQ_TM_ENDIAN_M, 1);
10104 REG_WR(sc, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
10105 REG_WR(sc, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
10106 REG_WR(sc, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
10107 /* make sure this value is 0 */
10108 REG_WR(sc, PXP2_REG_RQ_HC_ENDIAN_M, 0);
10110 //REG_WR(sc, PXP2_REG_RD_PBF_SWAP_MODE, 1);
10111 REG_WR(sc, PXP2_REG_RD_QM_SWAP_MODE, 1);
10112 REG_WR(sc, PXP2_REG_RD_TM_SWAP_MODE, 1);
10113 REG_WR(sc, PXP2_REG_RD_SRC_SWAP_MODE, 1);
10114 REG_WR(sc, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
10117 ecore_ilt_init_page_size(sc, INITOP_SET);
10119 if (CHIP_REV_IS_FPGA(sc) && CHIP_IS_E1H(sc)) {
10120 REG_WR(sc, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
10123 /* let the HW do it's magic... */
10126 /* finish PXP init */
10128 val = REG_RD(sc, PXP2_REG_RQ_CFG_DONE);
10130 PMD_DRV_LOG(NOTICE, "PXP2 CFG failed");
10133 val = REG_RD(sc, PXP2_REG_RD_INIT_DONE);
10135 PMD_DRV_LOG(NOTICE, "PXP2 RD_INIT failed");
10140 * Timer bug workaround for E2 only. We need to set the entire ILT to have
10141 * entries with value "0" and valid bit on. This needs to be done by the
10142 * first PF that is loaded in a path (i.e. common phase)
10144 if (!CHIP_IS_E1x(sc)) {
10146 * In E2 there is a bug in the timers block that can cause function 6 / 7
10147 * (i.e. vnic3) to start even if it is marked as "scan-off".
10148 * This occurs when a different function (func2,3) is being marked
10149 * as "scan-off". Real-life scenario for example: if a driver is being
10150 * load-unloaded while func6,7 are down. This will cause the timer to access
10151 * the ilt, translate to a logical address and send a request to read/write.
10152 * Since the ilt for the function that is down is not valid, this will cause
10153 * a translation error which is unrecoverable.
10154 * The Workaround is intended to make sure that when this happens nothing
10155 * fatal will occur. The workaround:
10156 * 1. First PF driver which loads on a path will:
10157 * a. After taking the chip out of reset, by using pretend,
10158 * it will write "0" to the following registers of
10160 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10161 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
10162 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
10163 * And for itself it will write '1' to
10164 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
10165 * dmae-operations (writing to pram for example.)
10166 * note: can be done for only function 6,7 but cleaner this
10168 * b. Write zero+valid to the entire ILT.
10169 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
10170 * VNIC3 (of that port). The range allocated will be the
10171 * entire ILT. This is needed to prevent ILT range error.
10172 * 2. Any PF driver load flow:
10173 * a. ILT update with the physical addresses of the allocated
10175 * b. Wait 20msec. - note that this timeout is needed to make
10176 * sure there are no requests in one of the PXP internal
10177 * queues with "old" ILT addresses.
10178 * c. PF enable in the PGLC.
10179 * d. Clear the was_error of the PF in the PGLC. (could have
10180 * occurred while driver was down)
10181 * e. PF enable in the CFC (WEAK + STRONG)
10182 * f. Timers scan enable
10183 * 3. PF driver unload flow:
10184 * a. Clear the Timers scan_en.
10185 * b. Polling for scan_on=0 for that PF.
10186 * c. Clear the PF enable bit in the PXP.
10187 * d. Clear the PF enable in the CFC (WEAK + STRONG)
10188 * e. Write zero+valid to all ILT entries (The valid bit must
10190 * f. If this is VNIC 3 of a port then also init
10191 * first_timers_ilt_entry to zero and last_timers_ilt_entry
10192 * to the last enrty in the ILT.
10195 * Currently the PF error in the PGLC is non recoverable.
10196 * In the future the there will be a recovery routine for this error.
10197 * Currently attention is masked.
10198 * Having an MCP lock on the load/unload process does not guarantee that
10199 * there is no Timer disable during Func6/7 enable. This is because the
10200 * Timers scan is currently being cleared by the MCP on FLR.
10201 * Step 2.d can be done only for PF6/7 and the driver can also check if
10202 * there is error before clearing it. But the flow above is simpler and
10204 * All ILT entries are written by zero+valid and not just PF6/7
10205 * ILT entries since in the future the ILT entries allocation for
10206 * PF-s might be dynamic.
10208 struct ilt_client_info ilt_cli;
10209 struct ecore_ilt ilt;
10211 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
10212 memset(&ilt, 0, sizeof(struct ecore_ilt));
10214 /* initialize dummy TM client */
10216 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
10217 ilt_cli.client_num = ILT_CLIENT_TM;
10220 * Step 1: set zeroes to all ilt page entries with valid bit on
10221 * Step 2: set the timers first/last ilt entry to point
10222 * to the entire range to prevent ILT range error for 3rd/4th
10223 * vnic (this code assumes existence of the vnic)
10225 * both steps performed by call to ecore_ilt_client_init_op()
10226 * with dummy TM client
10228 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
10229 * and his brother are split registers
10232 bnx2x_pretend_func(sc, (SC_PATH(sc) + 6));
10233 ecore_ilt_client_init_op_ilt(sc, &ilt, &ilt_cli, INITOP_CLEAR);
10234 bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10236 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
10237 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
10238 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
10241 REG_WR(sc, PXP2_REG_RQ_DISABLE_INPUTS, 0);
10242 REG_WR(sc, PXP2_REG_RD_DISABLE_INPUTS, 0);
10244 if (!CHIP_IS_E1x(sc)) {
10247 ecore_init_block(sc, BLOCK_PGLUE_B, PHASE_COMMON);
10248 ecore_init_block(sc, BLOCK_ATC, PHASE_COMMON);
10250 /* let the HW do it's magic... */
10253 val = REG_RD(sc, ATC_REG_ATC_INIT_DONE);
10254 } while (factor-- && (val != 1));
10257 PMD_DRV_LOG(NOTICE, "ATC_INIT failed");
10262 ecore_init_block(sc, BLOCK_DMAE, PHASE_COMMON);
10264 /* clean the DMAE memory */
10265 sc->dmae_ready = 1;
10266 ecore_init_fill(sc, TSEM_REG_PRAM, 0, 8);
10268 ecore_init_block(sc, BLOCK_TCM, PHASE_COMMON);
10270 ecore_init_block(sc, BLOCK_UCM, PHASE_COMMON);
10272 ecore_init_block(sc, BLOCK_CCM, PHASE_COMMON);
10274 ecore_init_block(sc, BLOCK_XCM, PHASE_COMMON);
10276 bnx2x_read_dmae(sc, XSEM_REG_PASSIVE_BUFFER, 3);
10277 bnx2x_read_dmae(sc, CSEM_REG_PASSIVE_BUFFER, 3);
10278 bnx2x_read_dmae(sc, TSEM_REG_PASSIVE_BUFFER, 3);
10279 bnx2x_read_dmae(sc, USEM_REG_PASSIVE_BUFFER, 3);
10281 ecore_init_block(sc, BLOCK_QM, PHASE_COMMON);
10283 /* QM queues pointers table */
10284 ecore_qm_init_ptr_table(sc, sc->qm_cid_count, INITOP_SET);
10286 /* soft reset pulse */
10287 REG_WR(sc, QM_REG_SOFT_RESET, 1);
10288 REG_WR(sc, QM_REG_SOFT_RESET, 0);
10290 if (CNIC_SUPPORT(sc))
10291 ecore_init_block(sc, BLOCK_TM, PHASE_COMMON);
10293 ecore_init_block(sc, BLOCK_DORQ, PHASE_COMMON);
10294 REG_WR(sc, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
10296 if (!CHIP_REV_IS_SLOW(sc)) {
10297 /* enable hw interrupt from doorbell Q */
10298 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
10301 ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON);
10303 ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON);
10304 REG_WR(sc, PRS_REG_A_PRSU_20, 0xf);
10305 REG_WR(sc, PRS_REG_E1HOV_MODE, sc->devinfo.mf_info.path_has_ovlan);
10307 if (!CHIP_IS_E1x(sc) && !CHIP_IS_E3B0(sc)) {
10308 if (IS_MF_AFEX(sc)) {
10310 * configure that AFEX and VLAN headers must be
10311 * received in AFEX mode
10313 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC, 0xE);
10314 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS, 0xA);
10315 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
10316 REG_WR(sc, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
10317 REG_WR(sc, PRS_REG_TAG_LEN_0, 0x4);
10320 * Bit-map indicating which L2 hdrs may appear
10321 * after the basic Ethernet header
10323 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC,
10324 sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10328 ecore_init_block(sc, BLOCK_TSDM, PHASE_COMMON);
10329 ecore_init_block(sc, BLOCK_CSDM, PHASE_COMMON);
10330 ecore_init_block(sc, BLOCK_USDM, PHASE_COMMON);
10331 ecore_init_block(sc, BLOCK_XSDM, PHASE_COMMON);
10333 if (!CHIP_IS_E1x(sc)) {
10334 /* reset VFC memories */
10335 REG_WR(sc, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10336 VFC_MEMORIES_RST_REG_CAM_RST |
10337 VFC_MEMORIES_RST_REG_RAM_RST);
10338 REG_WR(sc, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10339 VFC_MEMORIES_RST_REG_CAM_RST |
10340 VFC_MEMORIES_RST_REG_RAM_RST);
10345 ecore_init_block(sc, BLOCK_TSEM, PHASE_COMMON);
10346 ecore_init_block(sc, BLOCK_USEM, PHASE_COMMON);
10347 ecore_init_block(sc, BLOCK_CSEM, PHASE_COMMON);
10348 ecore_init_block(sc, BLOCK_XSEM, PHASE_COMMON);
10350 /* sync semi rtc */
10351 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x80000000);
10352 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x80000000);
10354 ecore_init_block(sc, BLOCK_UPB, PHASE_COMMON);
10355 ecore_init_block(sc, BLOCK_XPB, PHASE_COMMON);
10356 ecore_init_block(sc, BLOCK_PBF, PHASE_COMMON);
10358 if (!CHIP_IS_E1x(sc)) {
10359 if (IS_MF_AFEX(sc)) {
10361 * configure that AFEX and VLAN headers must be
10362 * sent in AFEX mode
10364 REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC, 0xE);
10365 REG_WR(sc, PBF_REG_MUST_HAVE_HDRS, 0xA);
10366 REG_WR(sc, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
10367 REG_WR(sc, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
10368 REG_WR(sc, PBF_REG_TAG_LEN_0, 0x4);
10370 REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC,
10371 sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10375 REG_WR(sc, SRC_REG_SOFT_RST, 1);
10377 ecore_init_block(sc, BLOCK_SRC, PHASE_COMMON);
10379 if (CNIC_SUPPORT(sc)) {
10380 REG_WR(sc, SRC_REG_KEYSEARCH_0, 0x63285672);
10381 REG_WR(sc, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
10382 REG_WR(sc, SRC_REG_KEYSEARCH_2, 0x223aef9b);
10383 REG_WR(sc, SRC_REG_KEYSEARCH_3, 0x26001e3a);
10384 REG_WR(sc, SRC_REG_KEYSEARCH_4, 0x7ae91116);
10385 REG_WR(sc, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
10386 REG_WR(sc, SRC_REG_KEYSEARCH_6, 0x298d8adf);
10387 REG_WR(sc, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
10388 REG_WR(sc, SRC_REG_KEYSEARCH_8, 0x1830f82f);
10389 REG_WR(sc, SRC_REG_KEYSEARCH_9, 0x01e46be7);
10391 REG_WR(sc, SRC_REG_SOFT_RST, 0);
10393 if (sizeof(union cdu_context) != 1024) {
10394 /* we currently assume that a context is 1024 bytes */
10395 PMD_DRV_LOG(NOTICE,
10396 "please adjust the size of cdu_context(%ld)",
10397 (long)sizeof(union cdu_context));
10400 ecore_init_block(sc, BLOCK_CDU, PHASE_COMMON);
10401 val = (4 << 24) + (0 << 12) + 1024;
10402 REG_WR(sc, CDU_REG_CDU_GLOBAL_PARAMS, val);
10404 ecore_init_block(sc, BLOCK_CFC, PHASE_COMMON);
10406 REG_WR(sc, CFC_REG_INIT_REG, 0x7FF);
10407 /* enable context validation interrupt from CFC */
10408 REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
10410 /* set the thresholds to prevent CFC/CDU race */
10411 REG_WR(sc, CFC_REG_DEBUG0, 0x20020000);
10412 ecore_init_block(sc, BLOCK_HC, PHASE_COMMON);
10414 if (!CHIP_IS_E1x(sc) && BNX2X_NOMCP(sc)) {
10415 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x36);
10418 ecore_init_block(sc, BLOCK_IGU, PHASE_COMMON);
10419 ecore_init_block(sc, BLOCK_MISC_AEU, PHASE_COMMON);
10421 /* Reset PCIE errors for debug */
10422 REG_WR(sc, 0x2814, 0xffffffff);
10423 REG_WR(sc, 0x3820, 0xffffffff);
10425 if (!CHIP_IS_E1x(sc)) {
10426 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
10427 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
10428 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
10429 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
10430 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
10431 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
10432 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
10433 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
10434 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
10435 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
10436 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
10439 ecore_init_block(sc, BLOCK_NIG, PHASE_COMMON);
10441 /* in E3 this done in per-port section */
10442 if (!CHIP_IS_E3(sc))
10443 REG_WR(sc, NIG_REG_LLH_MF_MODE, IS_MF(sc));
10445 if (CHIP_IS_E1H(sc)) {
10446 /* not applicable for E2 (and above ...) */
10447 REG_WR(sc, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(sc));
10450 if (CHIP_REV_IS_SLOW(sc)) {
10454 /* finish CFC init */
10455 val = reg_poll(sc, CFC_REG_LL_INIT_DONE, 1, 100, 10);
10457 PMD_DRV_LOG(NOTICE, "CFC LL_INIT failed");
10460 val = reg_poll(sc, CFC_REG_AC_INIT_DONE, 1, 100, 10);
10462 PMD_DRV_LOG(NOTICE, "CFC AC_INIT failed");
10465 val = reg_poll(sc, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
10467 PMD_DRV_LOG(NOTICE, "CFC CAM_INIT failed");
10470 REG_WR(sc, CFC_REG_DEBUG0, 0);
10472 bnx2x_setup_fan_failure_detection(sc);
10474 /* clear PXP2 attentions */
10475 REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
10477 bnx2x_enable_blocks_attention(sc);
10479 if (!CHIP_REV_IS_SLOW(sc)) {
10480 ecore_enable_blocks_parity(sc);
10483 if (!BNX2X_NOMCP(sc)) {
10484 if (CHIP_IS_E1x(sc)) {
10485 bnx2x_common_init_phy(sc);
10493 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
10495 * @sc: driver handle
10497 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc)
10499 int rc = bnx2x_init_hw_common(sc);
10505 /* In E2 2-PORT mode, same ext phy is used for the two paths */
10506 if (!BNX2X_NOMCP(sc)) {
10507 bnx2x_common_init_phy(sc);
10513 static int bnx2x_init_hw_port(struct bnx2x_softc *sc)
10515 int port = SC_PORT(sc);
10516 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
10517 uint32_t low, high;
10520 PMD_DRV_LOG(DEBUG, "starting port init for port %d", port);
10522 REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
10524 ecore_init_block(sc, BLOCK_MISC, init_phase);
10525 ecore_init_block(sc, BLOCK_PXP, init_phase);
10526 ecore_init_block(sc, BLOCK_PXP2, init_phase);
10529 * Timers bug workaround: disables the pf_master bit in pglue at
10530 * common phase, we need to enable it here before any dmae access are
10531 * attempted. Therefore we manually added the enable-master to the
10532 * port phase (it also happens in the function phase)
10534 if (!CHIP_IS_E1x(sc)) {
10535 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
10538 ecore_init_block(sc, BLOCK_ATC, init_phase);
10539 ecore_init_block(sc, BLOCK_DMAE, init_phase);
10540 ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
10541 ecore_init_block(sc, BLOCK_QM, init_phase);
10543 ecore_init_block(sc, BLOCK_TCM, init_phase);
10544 ecore_init_block(sc, BLOCK_UCM, init_phase);
10545 ecore_init_block(sc, BLOCK_CCM, init_phase);
10546 ecore_init_block(sc, BLOCK_XCM, init_phase);
10548 /* QM cid (connection) count */
10549 ecore_qm_init_cid_count(sc, sc->qm_cid_count, INITOP_SET);
10551 if (CNIC_SUPPORT(sc)) {
10552 ecore_init_block(sc, BLOCK_TM, init_phase);
10553 REG_WR(sc, TM_REG_LIN0_SCAN_TIME + port * 4, 20);
10554 REG_WR(sc, TM_REG_LIN0_MAX_ACTIVE_CID + port * 4, 31);
10557 ecore_init_block(sc, BLOCK_DORQ, init_phase);
10559 ecore_init_block(sc, BLOCK_BRB1, init_phase);
10561 if (CHIP_IS_E1H(sc)) {
10563 low = (BNX2X_ONE_PORT(sc) ? 160 : 246);
10564 } else if (sc->mtu > 4096) {
10565 if (BNX2X_ONE_PORT(sc)) {
10569 /* (24*1024 + val*4)/256 */
10570 low = (96 + (val / 64) + ((val % 64) ? 1 : 0));
10573 low = (BNX2X_ONE_PORT(sc) ? 80 : 160);
10575 high = (low + 56); /* 14*1024/256 */
10576 REG_WR(sc, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port * 4, low);
10577 REG_WR(sc, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port * 4, high);
10580 if (CHIP_IS_MODE_4_PORT(sc)) {
10581 REG_WR(sc, SC_PORT(sc) ?
10582 BRB1_REG_MAC_GUARANTIED_1 :
10583 BRB1_REG_MAC_GUARANTIED_0, 40);
10586 ecore_init_block(sc, BLOCK_PRS, init_phase);
10587 if (CHIP_IS_E3B0(sc)) {
10588 if (IS_MF_AFEX(sc)) {
10589 /* configure headers for AFEX mode */
10591 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_1,
10593 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_1,
10595 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_1, 0xA);
10597 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10599 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_0,
10601 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
10604 /* Ovlan exists only if we are in multi-function +
10605 * switch-dependent mode, in switch-independent there
10606 * is no ovlan headers
10608 REG_WR(sc, SC_PORT(sc) ?
10609 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
10610 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10611 (sc->devinfo.mf_info.path_has_ovlan ? 7 : 6));
10615 ecore_init_block(sc, BLOCK_TSDM, init_phase);
10616 ecore_init_block(sc, BLOCK_CSDM, init_phase);
10617 ecore_init_block(sc, BLOCK_USDM, init_phase);
10618 ecore_init_block(sc, BLOCK_XSDM, init_phase);
10620 ecore_init_block(sc, BLOCK_TSEM, init_phase);
10621 ecore_init_block(sc, BLOCK_USEM, init_phase);
10622 ecore_init_block(sc, BLOCK_CSEM, init_phase);
10623 ecore_init_block(sc, BLOCK_XSEM, init_phase);
10625 ecore_init_block(sc, BLOCK_UPB, init_phase);
10626 ecore_init_block(sc, BLOCK_XPB, init_phase);
10628 ecore_init_block(sc, BLOCK_PBF, init_phase);
10630 if (CHIP_IS_E1x(sc)) {
10631 /* configure PBF to work without PAUSE mtu 9000 */
10632 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 0);
10634 /* update threshold */
10635 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, (9040 / 16));
10636 /* update init credit */
10637 REG_WR(sc, PBF_REG_P0_INIT_CRD + port * 4,
10638 (9040 / 16) + 553 - 22);
10640 /* probe changes */
10641 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 1);
10643 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0);
10646 if (CNIC_SUPPORT(sc)) {
10647 ecore_init_block(sc, BLOCK_SRC, init_phase);
10650 ecore_init_block(sc, BLOCK_CDU, init_phase);
10651 ecore_init_block(sc, BLOCK_CFC, init_phase);
10652 ecore_init_block(sc, BLOCK_HC, init_phase);
10653 ecore_init_block(sc, BLOCK_IGU, init_phase);
10654 ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
10655 /* init aeu_mask_attn_func_0/1:
10656 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
10657 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
10658 * bits 4-7 are used for "per vn group attention" */
10659 val = IS_MF(sc) ? 0xF7 : 0x7;
10661 REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, val);
10663 ecore_init_block(sc, BLOCK_NIG, init_phase);
10665 if (!CHIP_IS_E1x(sc)) {
10666 /* Bit-map indicating which L2 hdrs may appear after the
10667 * basic Ethernet header
10669 if (IS_MF_AFEX(sc)) {
10670 REG_WR(sc, SC_PORT(sc) ?
10671 NIG_REG_P1_HDRS_AFTER_BASIC :
10672 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
10674 REG_WR(sc, SC_PORT(sc) ?
10675 NIG_REG_P1_HDRS_AFTER_BASIC :
10676 NIG_REG_P0_HDRS_AFTER_BASIC,
10677 IS_MF_SD(sc) ? 7 : 6);
10680 if (CHIP_IS_E3(sc)) {
10681 REG_WR(sc, SC_PORT(sc) ?
10682 NIG_REG_LLH1_MF_MODE :
10683 NIG_REG_LLH_MF_MODE, IS_MF(sc));
10686 if (!CHIP_IS_E3(sc)) {
10687 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1);
10690 /* 0x2 disable mf_ov, 0x1 enable */
10691 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port * 4,
10692 (IS_MF_SD(sc) ? 0x1 : 0x2));
10694 if (!CHIP_IS_E1x(sc)) {
10696 switch (sc->devinfo.mf_info.mf_mode) {
10697 case MULTI_FUNCTION_SD:
10700 case MULTI_FUNCTION_SI:
10701 case MULTI_FUNCTION_AFEX:
10706 REG_WR(sc, (SC_PORT(sc) ? NIG_REG_LLH1_CLS_TYPE :
10707 NIG_REG_LLH0_CLS_TYPE), val);
10709 REG_WR(sc, NIG_REG_LLFC_ENABLE_0 + port * 4, 0);
10710 REG_WR(sc, NIG_REG_LLFC_OUT_EN_0 + port * 4, 0);
10711 REG_WR(sc, NIG_REG_PAUSE_ENABLE_0 + port * 4, 1);
10713 /* If SPIO5 is set to generate interrupts, enable it for this port */
10714 val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
10715 if (val & MISC_SPIO_SPIO5) {
10716 uint32_t reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
10717 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
10718 val = REG_RD(sc, reg_addr);
10719 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
10720 REG_WR(sc, reg_addr, val);
10727 bnx2x_flr_clnup_reg_poll(struct bnx2x_softc *sc, uint32_t reg,
10728 uint32_t expected, uint32_t poll_count)
10730 uint32_t cur_cnt = poll_count;
10733 while ((val = REG_RD(sc, reg)) != expected && cur_cnt--) {
10734 DELAY(FLR_WAIT_INTERVAL);
10741 bnx2x_flr_clnup_poll_hw_counter(struct bnx2x_softc *sc, uint32_t reg,
10742 __rte_unused const char *msg, uint32_t poll_cnt)
10744 uint32_t val = bnx2x_flr_clnup_reg_poll(sc, reg, 0, poll_cnt);
10747 PMD_DRV_LOG(NOTICE, "%s usage count=%d", msg, val);
10754 /* Common routines with VF FLR cleanup */
10755 static uint32_t bnx2x_flr_clnup_poll_count(struct bnx2x_softc *sc)
10757 /* adjust polling timeout */
10758 if (CHIP_REV_IS_EMUL(sc)) {
10759 return (FLR_POLL_CNT * 2000);
10762 if (CHIP_REV_IS_FPGA(sc)) {
10763 return (FLR_POLL_CNT * 120);
10766 return FLR_POLL_CNT;
10769 static int bnx2x_poll_hw_usage_counters(struct bnx2x_softc *sc, uint32_t poll_cnt)
10771 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
10772 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10773 CFC_REG_NUM_LCIDS_INSIDE_PF,
10774 "CFC PF usage counter timed out",
10779 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
10780 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10781 DORQ_REG_PF_USAGE_CNT,
10782 "DQ PF usage counter timed out",
10787 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
10788 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10789 QM_REG_PF_USG_CNT_0 + 4 * SC_FUNC(sc),
10790 "QM PF usage counter timed out",
10795 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
10796 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10797 TM_REG_LIN0_VNIC_UC + 4 * SC_PORT(sc),
10798 "Timers VNIC usage counter timed out",
10803 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10804 TM_REG_LIN0_NUM_SCANS +
10806 "Timers NUM_SCANS usage counter timed out",
10811 /* Wait DMAE PF usage counter to zero */
10812 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10813 dmae_reg_go_c[INIT_DMAE_C(sc)],
10814 "DMAE dommand register timed out",
10822 #define OP_GEN_PARAM(param) \
10823 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
10824 #define OP_GEN_TYPE(type) \
10825 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
10826 #define OP_GEN_AGG_VECT(index) \
10827 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
10830 bnx2x_send_final_clnup(struct bnx2x_softc *sc, uint8_t clnup_func,
10833 uint32_t op_gen_command = 0;
10834 uint32_t comp_addr = (BAR_CSTRORM_INTMEM +
10835 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func));
10838 if (REG_RD(sc, comp_addr)) {
10839 PMD_DRV_LOG(NOTICE,
10840 "Cleanup complete was not 0 before sending");
10844 op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
10845 op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
10846 op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
10847 op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
10849 REG_WR(sc, XSDM_REG_OPERATION_GEN, op_gen_command);
10851 if (bnx2x_flr_clnup_reg_poll(sc, comp_addr, 1, poll_cnt) != 1) {
10852 PMD_DRV_LOG(NOTICE, "FW final cleanup did not succeed");
10853 PMD_DRV_LOG(DEBUG, "At timeout completion address contained %x",
10854 (REG_RD(sc, comp_addr)));
10855 rte_panic("FLR cleanup failed");
10859 /* Zero completion for nxt FLR */
10860 REG_WR(sc, comp_addr, 0);
10866 bnx2x_pbf_pN_buf_flushed(struct bnx2x_softc *sc, struct pbf_pN_buf_regs *regs,
10867 uint32_t poll_count)
10869 uint32_t init_crd, crd, crd_start, crd_freed, crd_freed_start;
10870 uint32_t cur_cnt = poll_count;
10872 crd_freed = crd_freed_start = REG_RD(sc, regs->crd_freed);
10873 crd = crd_start = REG_RD(sc, regs->crd);
10874 init_crd = REG_RD(sc, regs->init_crd);
10876 while ((crd != init_crd) &&
10877 ((uint32_t) ((int32_t) crd_freed - (int32_t) crd_freed_start) <
10878 (init_crd - crd_start))) {
10880 DELAY(FLR_WAIT_INTERVAL);
10881 crd = REG_RD(sc, regs->crd);
10882 crd_freed = REG_RD(sc, regs->crd_freed);
10890 bnx2x_pbf_pN_cmd_flushed(struct bnx2x_softc *sc, struct pbf_pN_cmd_regs *regs,
10891 uint32_t poll_count)
10893 uint32_t occup, to_free, freed, freed_start;
10894 uint32_t cur_cnt = poll_count;
10896 occup = to_free = REG_RD(sc, regs->lines_occup);
10897 freed = freed_start = REG_RD(sc, regs->lines_freed);
10900 ((uint32_t) ((int32_t) freed - (int32_t) freed_start) <
10903 DELAY(FLR_WAIT_INTERVAL);
10904 occup = REG_RD(sc, regs->lines_occup);
10905 freed = REG_RD(sc, regs->lines_freed);
10912 static void bnx2x_tx_hw_flushed(struct bnx2x_softc *sc, uint32_t poll_count)
10914 struct pbf_pN_cmd_regs cmd_regs[] = {
10915 {0, (CHIP_IS_E3B0(sc)) ?
10916 PBF_REG_TQ_OCCUPANCY_Q0 : PBF_REG_P0_TQ_OCCUPANCY,
10917 (CHIP_IS_E3B0(sc)) ?
10918 PBF_REG_TQ_LINES_FREED_CNT_Q0 : PBF_REG_P0_TQ_LINES_FREED_CNT},
10919 {1, (CHIP_IS_E3B0(sc)) ?
10920 PBF_REG_TQ_OCCUPANCY_Q1 : PBF_REG_P1_TQ_OCCUPANCY,
10921 (CHIP_IS_E3B0(sc)) ?
10922 PBF_REG_TQ_LINES_FREED_CNT_Q1 : PBF_REG_P1_TQ_LINES_FREED_CNT},
10923 {4, (CHIP_IS_E3B0(sc)) ?
10924 PBF_REG_TQ_OCCUPANCY_LB_Q : PBF_REG_P4_TQ_OCCUPANCY,
10925 (CHIP_IS_E3B0(sc)) ?
10926 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
10927 PBF_REG_P4_TQ_LINES_FREED_CNT}
10930 struct pbf_pN_buf_regs buf_regs[] = {
10931 {0, (CHIP_IS_E3B0(sc)) ?
10932 PBF_REG_INIT_CRD_Q0 : PBF_REG_P0_INIT_CRD,
10933 (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q0 : PBF_REG_P0_CREDIT,
10934 (CHIP_IS_E3B0(sc)) ?
10935 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
10936 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
10937 {1, (CHIP_IS_E3B0(sc)) ?
10938 PBF_REG_INIT_CRD_Q1 : PBF_REG_P1_INIT_CRD,
10939 (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q1 : PBF_REG_P1_CREDIT,
10940 (CHIP_IS_E3B0(sc)) ?
10941 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
10942 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
10943 {4, (CHIP_IS_E3B0(sc)) ?
10944 PBF_REG_INIT_CRD_LB_Q : PBF_REG_P4_INIT_CRD,
10945 (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_LB_Q : PBF_REG_P4_CREDIT,
10946 (CHIP_IS_E3B0(sc)) ?
10947 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
10948 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
10953 /* Verify the command queues are flushed P0, P1, P4 */
10954 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) {
10955 bnx2x_pbf_pN_cmd_flushed(sc, &cmd_regs[i], poll_count);
10958 /* Verify the transmission buffers are flushed P0, P1, P4 */
10959 for (i = 0; i < ARRAY_SIZE(buf_regs); i++) {
10960 bnx2x_pbf_pN_buf_flushed(sc, &buf_regs[i], poll_count);
10964 static void bnx2x_hw_enable_status(struct bnx2x_softc *sc)
10966 __rte_unused uint32_t val;
10968 val = REG_RD(sc, CFC_REG_WEAK_ENABLE_PF);
10969 PMD_DRV_LOG(DEBUG, "CFC_REG_WEAK_ENABLE_PF is 0x%x", val);
10971 val = REG_RD(sc, PBF_REG_DISABLE_PF);
10972 PMD_DRV_LOG(DEBUG, "PBF_REG_DISABLE_PF is 0x%x", val);
10974 val = REG_RD(sc, IGU_REG_PCI_PF_MSI_EN);
10975 PMD_DRV_LOG(DEBUG, "IGU_REG_PCI_PF_MSI_EN is 0x%x", val);
10977 val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_EN);
10978 PMD_DRV_LOG(DEBUG, "IGU_REG_PCI_PF_MSIX_EN is 0x%x", val);
10980 val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
10981 PMD_DRV_LOG(DEBUG, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x", val);
10983 val = REG_RD(sc, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
10984 PMD_DRV_LOG(DEBUG, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x", val);
10986 val = REG_RD(sc, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
10987 PMD_DRV_LOG(DEBUG, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x", val);
10989 val = REG_RD(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
10990 PMD_DRV_LOG(DEBUG, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x",
10995 * bnx2x_pf_flr_clnup
10996 * a. re-enable target read on the PF
10997 * b. poll cfc per function usgae counter
10998 * c. poll the qm perfunction usage counter
10999 * d. poll the tm per function usage counter
11000 * e. poll the tm per function scan-done indication
11001 * f. clear the dmae channel associated wit hthe PF
11002 * g. zero the igu 'trailing edge' and 'leading edge' regs (attentions)
11003 * h. call the common flr cleanup code with -1 (pf indication)
11005 static int bnx2x_pf_flr_clnup(struct bnx2x_softc *sc)
11007 uint32_t poll_cnt = bnx2x_flr_clnup_poll_count(sc);
11009 /* Re-enable PF target read access */
11010 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
11012 /* Poll HW usage counters */
11013 if (bnx2x_poll_hw_usage_counters(sc, poll_cnt)) {
11017 /* Zero the igu 'trailing edge' and 'leading edge' */
11019 /* Send the FW cleanup command */
11020 if (bnx2x_send_final_clnup(sc, (uint8_t) SC_FUNC(sc), poll_cnt)) {
11026 /* Verify TX hw is flushed */
11027 bnx2x_tx_hw_flushed(sc, poll_cnt);
11029 /* Wait 100ms (not adjusted according to platform) */
11032 /* Verify no pending pci transactions */
11033 if (bnx2x_is_pcie_pending(sc)) {
11034 PMD_DRV_LOG(NOTICE, "PCIE Transactions still pending");
11038 bnx2x_hw_enable_status(sc);
11041 * Master enable - Due to WB DMAE writes performed before this
11042 * register is re-initialized as part of the regular function init
11044 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11049 static int bnx2x_init_hw_func(struct bnx2x_softc *sc)
11051 int port = SC_PORT(sc);
11052 int func = SC_FUNC(sc);
11053 int init_phase = PHASE_PF0 + func;
11054 struct ecore_ilt *ilt = sc->ilt;
11055 uint16_t cdu_ilt_start;
11056 uint32_t addr, val;
11057 uint32_t main_mem_base, main_mem_size, main_mem_prty_clr;
11058 int main_mem_width, rc;
11061 PMD_DRV_LOG(DEBUG, "starting func init for func %d", func);
11064 if (!CHIP_IS_E1x(sc)) {
11065 rc = bnx2x_pf_flr_clnup(sc);
11067 PMD_DRV_LOG(NOTICE, "FLR cleanup failed!");
11072 /* set MSI reconfigure capability */
11073 if (sc->devinfo.int_block == INT_BLOCK_HC) {
11074 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
11075 val = REG_RD(sc, addr);
11076 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
11077 REG_WR(sc, addr, val);
11080 ecore_init_block(sc, BLOCK_PXP, init_phase);
11081 ecore_init_block(sc, BLOCK_PXP2, init_phase);
11084 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
11086 for (i = 0; i < L2_ILT_LINES(sc); i++) {
11087 ilt->lines[cdu_ilt_start + i].page = sc->context[i].vcxt;
11088 ilt->lines[cdu_ilt_start + i].page_mapping =
11089 (phys_addr_t)sc->context[i].vcxt_dma.paddr;
11090 ilt->lines[cdu_ilt_start + i].size = sc->context[i].size;
11092 ecore_ilt_init_op(sc, INITOP_SET);
11094 REG_WR(sc, PRS_REG_NIC_MODE, 1);
11096 if (!CHIP_IS_E1x(sc)) {
11097 uint32_t pf_conf = IGU_PF_CONF_FUNC_EN;
11099 /* Turn on a single ISR mode in IGU if driver is going to use
11102 if ((sc->interrupt_mode != INTR_MODE_MSIX)
11103 || (sc->interrupt_mode != INTR_MODE_SINGLE_MSIX)) {
11104 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
11108 * Timers workaround bug: function init part.
11109 * Need to wait 20msec after initializing ILT,
11110 * needed to make sure there are no requests in
11111 * one of the PXP internal queues with "old" ILT addresses
11116 * Master enable - Due to WB DMAE writes performed before this
11117 * register is re-initialized as part of the regular function
11120 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11121 /* Enable the function in IGU */
11122 REG_WR(sc, IGU_REG_PF_CONFIGURATION, pf_conf);
11125 sc->dmae_ready = 1;
11127 ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
11129 if (!CHIP_IS_E1x(sc))
11130 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
11132 ecore_init_block(sc, BLOCK_ATC, init_phase);
11133 ecore_init_block(sc, BLOCK_DMAE, init_phase);
11134 ecore_init_block(sc, BLOCK_NIG, init_phase);
11135 ecore_init_block(sc, BLOCK_SRC, init_phase);
11136 ecore_init_block(sc, BLOCK_MISC, init_phase);
11137 ecore_init_block(sc, BLOCK_TCM, init_phase);
11138 ecore_init_block(sc, BLOCK_UCM, init_phase);
11139 ecore_init_block(sc, BLOCK_CCM, init_phase);
11140 ecore_init_block(sc, BLOCK_XCM, init_phase);
11141 ecore_init_block(sc, BLOCK_TSEM, init_phase);
11142 ecore_init_block(sc, BLOCK_USEM, init_phase);
11143 ecore_init_block(sc, BLOCK_CSEM, init_phase);
11144 ecore_init_block(sc, BLOCK_XSEM, init_phase);
11146 if (!CHIP_IS_E1x(sc))
11147 REG_WR(sc, QM_REG_PF_EN, 1);
11149 if (!CHIP_IS_E1x(sc)) {
11150 REG_WR(sc, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11151 REG_WR(sc, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11152 REG_WR(sc, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11153 REG_WR(sc, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11155 ecore_init_block(sc, BLOCK_QM, init_phase);
11157 ecore_init_block(sc, BLOCK_TM, init_phase);
11158 ecore_init_block(sc, BLOCK_DORQ, init_phase);
11160 ecore_init_block(sc, BLOCK_BRB1, init_phase);
11161 ecore_init_block(sc, BLOCK_PRS, init_phase);
11162 ecore_init_block(sc, BLOCK_TSDM, init_phase);
11163 ecore_init_block(sc, BLOCK_CSDM, init_phase);
11164 ecore_init_block(sc, BLOCK_USDM, init_phase);
11165 ecore_init_block(sc, BLOCK_XSDM, init_phase);
11166 ecore_init_block(sc, BLOCK_UPB, init_phase);
11167 ecore_init_block(sc, BLOCK_XPB, init_phase);
11168 ecore_init_block(sc, BLOCK_PBF, init_phase);
11169 if (!CHIP_IS_E1x(sc))
11170 REG_WR(sc, PBF_REG_DISABLE_PF, 0);
11172 ecore_init_block(sc, BLOCK_CDU, init_phase);
11174 ecore_init_block(sc, BLOCK_CFC, init_phase);
11176 if (!CHIP_IS_E1x(sc))
11177 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 1);
11180 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
11181 REG_WR(sc, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8, OVLAN(sc));
11184 ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
11186 /* HC init per function */
11187 if (sc->devinfo.int_block == INT_BLOCK_HC) {
11188 if (CHIP_IS_E1H(sc)) {
11189 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11191 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11192 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11194 ecore_init_block(sc, BLOCK_HC, init_phase);
11197 uint32_t num_segs, sb_idx, prod_offset;
11199 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11201 if (!CHIP_IS_E1x(sc)) {
11202 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11203 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11206 ecore_init_block(sc, BLOCK_IGU, init_phase);
11208 if (!CHIP_IS_E1x(sc)) {
11212 * E2 mode: address 0-135 match to the mapping memory;
11213 * 136 - PF0 default prod; 137 - PF1 default prod;
11214 * 138 - PF2 default prod; 139 - PF3 default prod;
11215 * 140 - PF0 attn prod; 141 - PF1 attn prod;
11216 * 142 - PF2 attn prod; 143 - PF3 attn prod;
11217 * 144-147 reserved.
11219 * E1.5 mode - In backward compatible mode;
11220 * for non default SB; each even line in the memory
11221 * holds the U producer and each odd line hold
11222 * the C producer. The first 128 producers are for
11223 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
11224 * producers are for the DSB for each PF.
11225 * Each PF has five segments: (the order inside each
11226 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
11227 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
11228 * 144-147 attn prods;
11230 /* non-default-status-blocks */
11231 num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11232 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
11233 for (sb_idx = 0; sb_idx < sc->igu_sb_cnt; sb_idx++) {
11234 prod_offset = (sc->igu_base_sb + sb_idx) *
11237 for (i = 0; i < num_segs; i++) {
11238 addr = IGU_REG_PROD_CONS_MEMORY +
11239 (prod_offset + i) * 4;
11240 REG_WR(sc, addr, 0);
11242 /* send consumer update with value 0 */
11243 bnx2x_ack_sb(sc, sc->igu_base_sb + sb_idx,
11244 USTORM_ID, 0, IGU_INT_NOP, 1);
11245 bnx2x_igu_clear_sb(sc, sc->igu_base_sb + sb_idx);
11248 /* default-status-blocks */
11249 num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11250 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
11252 if (CHIP_IS_MODE_4_PORT(sc))
11253 dsb_idx = SC_FUNC(sc);
11255 dsb_idx = SC_VN(sc);
11257 prod_offset = (CHIP_INT_MODE_IS_BC(sc) ?
11258 IGU_BC_BASE_DSB_PROD + dsb_idx :
11259 IGU_NORM_BASE_DSB_PROD + dsb_idx);
11262 * igu prods come in chunks of E1HVN_MAX (4) -
11263 * does not matters what is the current chip mode
11265 for (i = 0; i < (num_segs * E1HVN_MAX); i += E1HVN_MAX) {
11266 addr = IGU_REG_PROD_CONS_MEMORY +
11267 (prod_offset + i) * 4;
11268 REG_WR(sc, addr, 0);
11270 /* send consumer update with 0 */
11271 if (CHIP_INT_MODE_IS_BC(sc)) {
11272 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11273 USTORM_ID, 0, IGU_INT_NOP, 1);
11274 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11275 CSTORM_ID, 0, IGU_INT_NOP, 1);
11276 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11277 XSTORM_ID, 0, IGU_INT_NOP, 1);
11278 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11279 TSTORM_ID, 0, IGU_INT_NOP, 1);
11280 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11281 ATTENTION_ID, 0, IGU_INT_NOP, 1);
11283 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11284 USTORM_ID, 0, IGU_INT_NOP, 1);
11285 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11286 ATTENTION_ID, 0, IGU_INT_NOP, 1);
11288 bnx2x_igu_clear_sb(sc, sc->igu_dsb_id);
11290 /* !!! these should become driver const once
11291 rf-tool supports split-68 const */
11292 REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
11293 REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
11294 REG_WR(sc, IGU_REG_SB_MASK_LSB, 0);
11295 REG_WR(sc, IGU_REG_SB_MASK_MSB, 0);
11296 REG_WR(sc, IGU_REG_PBA_STATUS_LSB, 0);
11297 REG_WR(sc, IGU_REG_PBA_STATUS_MSB, 0);
11301 /* Reset PCIE errors for debug */
11302 REG_WR(sc, 0x2114, 0xffffffff);
11303 REG_WR(sc, 0x2120, 0xffffffff);
11305 if (CHIP_IS_E1x(sc)) {
11306 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords */
11307 main_mem_base = HC_REG_MAIN_MEMORY +
11308 SC_PORT(sc) * (main_mem_size * 4);
11309 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
11310 main_mem_width = 8;
11312 val = REG_RD(sc, main_mem_prty_clr);
11315 "Parity errors in HC block during function init (0x%x)!",
11319 /* Clear "false" parity errors in MSI-X table */
11320 for (i = main_mem_base;
11321 i < main_mem_base + main_mem_size * 4;
11322 i += main_mem_width) {
11323 bnx2x_read_dmae(sc, i, main_mem_width / 4);
11324 bnx2x_write_dmae(sc, BNX2X_SP_MAPPING(sc, wb_data),
11325 i, main_mem_width / 4);
11327 /* Clear HC parity attention */
11328 REG_RD(sc, main_mem_prty_clr);
11331 /* Enable STORMs SP logging */
11332 REG_WR8(sc, BAR_USTRORM_INTMEM +
11333 USTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11334 REG_WR8(sc, BAR_TSTRORM_INTMEM +
11335 TSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11336 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11337 CSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11338 REG_WR8(sc, BAR_XSTRORM_INTMEM +
11339 XSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11341 elink_phy_probe(&sc->link_params);
11346 static void bnx2x_link_reset(struct bnx2x_softc *sc)
11348 if (!BNX2X_NOMCP(sc)) {
11349 elink_lfa_reset(&sc->link_params, &sc->link_vars);
11351 if (!CHIP_REV_IS_SLOW(sc)) {
11352 PMD_DRV_LOG(WARNING,
11353 "Bootcode is missing - cannot reset link");
11358 static void bnx2x_reset_port(struct bnx2x_softc *sc)
11360 int port = SC_PORT(sc);
11363 /* reset physical Link */
11364 bnx2x_link_reset(sc);
11366 REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
11368 /* Do not rcv packets to BRB */
11369 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + port * 4, 0x0);
11370 /* Do not direct rcv packets that are not for MCP to the BRB */
11371 REG_WR(sc, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
11372 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
11374 /* Configure AEU */
11375 REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, 0);
11379 /* Check for BRB port occupancy */
11380 val = REG_RD(sc, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port * 4);
11383 "BRB1 is not empty, %d blocks are occupied", val);
11387 static void bnx2x_ilt_wr(struct bnx2x_softc *sc, uint32_t index, phys_addr_t addr)
11390 uint32_t wb_write[2];
11392 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index * 8;
11394 wb_write[0] = ONCHIP_ADDR1(addr);
11395 wb_write[1] = ONCHIP_ADDR2(addr);
11396 REG_WR_DMAE(sc, reg, wb_write, 2);
11399 static void bnx2x_clear_func_ilt(struct bnx2x_softc *sc, uint32_t func)
11401 uint32_t i, base = FUNC_ILT_BASE(func);
11402 for (i = base; i < base + ILT_PER_FUNC; i++) {
11403 bnx2x_ilt_wr(sc, i, 0);
11407 static void bnx2x_reset_func(struct bnx2x_softc *sc)
11409 struct bnx2x_fastpath *fp;
11410 int port = SC_PORT(sc);
11411 int func = SC_FUNC(sc);
11414 /* Disable the function in the FW */
11415 REG_WR8(sc, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
11416 REG_WR8(sc, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
11417 REG_WR8(sc, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
11418 REG_WR8(sc, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
11421 FOR_EACH_ETH_QUEUE(sc, i) {
11423 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11424 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
11429 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11430 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), SB_DISABLED);
11432 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) {
11433 REG_WR(sc, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
11437 /* Configure IGU */
11438 if (sc->devinfo.int_block == INT_BLOCK_HC) {
11439 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11440 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11442 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11443 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11446 if (CNIC_LOADED(sc)) {
11447 /* Disable Timer scan */
11448 REG_WR(sc, TM_REG_EN_LINEAR0_TIMER + port * 4, 0);
11450 * Wait for at least 10ms and up to 2 second for the timers
11453 for (i = 0; i < 200; i++) {
11455 if (!REG_RD(sc, TM_REG_LIN0_SCAN_ON + port * 4))
11461 bnx2x_clear_func_ilt(sc, func);
11464 * Timers workaround bug for E2: if this is vnic-3,
11465 * we need to set the entire ilt range for this timers.
11467 if (!CHIP_IS_E1x(sc) && SC_VN(sc) == 3) {
11468 struct ilt_client_info ilt_cli;
11469 /* use dummy TM client */
11470 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
11472 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
11473 ilt_cli.client_num = ILT_CLIENT_TM;
11475 ecore_ilt_boundry_init_op(sc, &ilt_cli, 0);
11478 /* this assumes that reset_port() called before reset_func() */
11479 if (!CHIP_IS_E1x(sc)) {
11480 bnx2x_pf_disable(sc);
11483 sc->dmae_ready = 0;
11486 static void bnx2x_release_firmware(struct bnx2x_softc *sc)
11488 rte_free(sc->init_ops);
11489 rte_free(sc->init_ops_offsets);
11490 rte_free(sc->init_data);
11491 rte_free(sc->iro_array);
11494 static int bnx2x_init_firmware(struct bnx2x_softc *sc)
11497 uint8_t *p = sc->firmware;
11500 for (i = 0; i < 24; ++i)
11501 off[i] = rte_be_to_cpu_32(*((uint32_t *) sc->firmware + i));
11504 sc->init_ops = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11507 bnx2x_data_to_init_ops(p + off[1], sc->init_ops, len);
11510 sc->init_ops_offsets = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11511 if (!sc->init_ops_offsets)
11513 bnx2x_data_to_init_offsets(p + off[3], sc->init_ops_offsets, len);
11516 sc->init_data = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11517 if (!sc->init_data)
11519 bnx2x_data_to_init_data(p + off[5], sc->init_data, len);
11521 sc->tsem_int_table_data = p + off[7];
11522 sc->tsem_pram_data = p + off[9];
11523 sc->usem_int_table_data = p + off[11];
11524 sc->usem_pram_data = p + off[13];
11525 sc->csem_int_table_data = p + off[15];
11526 sc->csem_pram_data = p + off[17];
11527 sc->xsem_int_table_data = p + off[19];
11528 sc->xsem_pram_data = p + off[21];
11531 sc->iro_array = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11532 if (!sc->iro_array)
11534 bnx2x_data_to_iro_array(p + off[23], sc->iro_array, len);
11539 bnx2x_release_firmware(sc);
11543 static int cut_gzip_prefix(const uint8_t * zbuf, int len)
11545 #define MIN_PREFIX_SIZE (10)
11547 int n = MIN_PREFIX_SIZE;
11550 if (!(zbuf[0] == 0x1f && zbuf[1] == 0x8b && zbuf[2] == Z_DEFLATED) ||
11551 len <= MIN_PREFIX_SIZE) {
11555 /* optional extra fields are present */
11556 if (zbuf[3] & 0x4) {
11563 /* file name is present */
11564 if (zbuf[3] & 0x8) {
11565 while ((zbuf[n++] != 0) && (n < len)) ;
11571 static int ecore_gunzip(struct bnx2x_softc *sc, const uint8_t * zbuf, int len)
11574 int data_begin = cut_gzip_prefix(zbuf, len);
11576 PMD_DRV_LOG(DEBUG, "ecore_gunzip %d", len);
11578 if (data_begin <= 0) {
11579 PMD_DRV_LOG(NOTICE, "bad gzip prefix");
11583 memset(&zlib_stream, 0, sizeof(zlib_stream));
11584 zlib_stream.next_in = zbuf + data_begin;
11585 zlib_stream.avail_in = len - data_begin;
11586 zlib_stream.next_out = sc->gz_buf;
11587 zlib_stream.avail_out = FW_BUF_SIZE;
11589 ret = inflateInit2(&zlib_stream, -MAX_WBITS);
11591 PMD_DRV_LOG(NOTICE, "zlib inflateInit2 error");
11595 ret = inflate(&zlib_stream, Z_FINISH);
11596 if ((ret != Z_STREAM_END) && (ret != Z_OK)) {
11597 PMD_DRV_LOG(NOTICE, "zlib inflate error: %d %s", ret,
11601 sc->gz_outlen = zlib_stream.total_out;
11602 if (sc->gz_outlen & 0x3) {
11603 PMD_DRV_LOG(NOTICE, "firmware is not aligned. gz_outlen == %d",
11606 sc->gz_outlen >>= 2;
11608 inflateEnd(&zlib_stream);
11610 if (ret == Z_STREAM_END)
11617 ecore_write_dmae_phys_len(struct bnx2x_softc *sc, phys_addr_t phys_addr,
11618 uint32_t addr, uint32_t len)
11620 bnx2x_write_dmae_phys_len(sc, phys_addr, addr, len);
11624 ecore_storm_memset_struct(struct bnx2x_softc *sc, uint32_t addr, size_t size,
11628 for (i = 0; i < size / 4; i++) {
11629 REG_WR(sc, addr + (i * 4), data[i]);
11633 static const char *get_ext_phy_type(uint32_t ext_phy_type)
11635 uint32_t phy_type_idx = ext_phy_type >> 8;
11636 static const char *types[] =
11637 { "DIRECT", "BNX2X-8071", "BNX2X-8072", "BNX2X-8073",
11638 "BNX2X-8705", "BNX2X-8706", "BNX2X-8726", "BNX2X-8481", "SFX-7101",
11640 "BNX2X-8727-NOC", "BNX2X-84823", "NOT_CONN", "FAILURE"
11643 if (phy_type_idx < 12)
11644 return types[phy_type_idx];
11645 else if (PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN == ext_phy_type)
11651 static const char *get_state(uint32_t state)
11653 uint32_t state_idx = state >> 12;
11654 static const char *states[] = { "CLOSED", "OPENING_WAIT4_LOAD",
11655 "OPENING_WAIT4_PORT", "OPEN", "CLOSING_WAIT4_HALT",
11656 "CLOSING_WAIT4_DELETE", "CLOSING_WAIT4_UNLOAD",
11657 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
11658 "UNKNOWN", "DISABLED", "DIAG", "ERROR", "UNDEFINED"
11661 if (state_idx <= 0xF)
11662 return states[state_idx];
11664 return states[0x10];
11667 static const char *get_recovery_state(uint32_t state)
11669 static const char *states[] = { "NONE", "DONE", "INIT",
11670 "WAIT", "FAILED", "NIC_LOADING"
11672 return states[state];
11675 static const char *get_rx_mode(uint32_t mode)
11677 static const char *modes[] = { "NONE", "NORMAL", "ALLMULTI",
11678 "PROMISC", "MAX_MULTICAST", "ERROR"
11682 return modes[mode];
11683 else if (BNX2X_MAX_MULTICAST == mode)
11689 #define BNX2X_INFO_STR_MAX 256
11690 static const char *get_bnx2x_flags(uint32_t flags)
11693 static const char *flag[] = { "ONE_PORT ", "NO_ISCSI ",
11694 "NO_FCOE ", "NO_WOL ", "USING_DAC ", "USING_MSIX ",
11695 "USING_MSI ", "DISABLE_MSI ", "UNKNOWN ", "NO_MCP ",
11696 "SAFC_TX_FLAG ", "MF_FUNC_DIS ", "TX_SWITCHING "
11698 static char flag_str[BNX2X_INFO_STR_MAX];
11699 memset(flag_str, 0, BNX2X_INFO_STR_MAX);
11701 for (i = 0; i < 5; i++)
11702 if (flags & (1 << i)) {
11703 strcat(flag_str, flag[i]);
11707 static char unknown[BNX2X_INFO_STR_MAX];
11708 snprintf(unknown, 32, "Unknown flag mask %x", flags);
11709 strcat(flag_str, unknown);
11715 * Prints useful adapter info.
11717 void bnx2x_print_adapter_info(struct bnx2x_softc *sc)
11720 __rte_unused uint32_t ext_phy_type;
11722 PMD_INIT_FUNC_TRACE();
11723 if (sc->link_vars.phy_flags & PHY_XGXS_FLAG)
11724 ext_phy_type = ELINK_XGXS_EXT_PHY_TYPE(REG_RD(sc,
11729 dev_info.port_hw_config
11730 [0].external_phy_config)));
11732 ext_phy_type = ELINK_SERDES_EXT_PHY_TYPE(REG_RD(sc,
11738 dev_info.port_hw_config
11739 [0].external_phy_config)));
11741 PMD_INIT_LOG(DEBUG, "\n\n===================================\n");
11742 /* Hardware chip info. */
11743 PMD_INIT_LOG(DEBUG, "%10s : %#08x\n", "ASIC", sc->devinfo.chip_id);
11744 PMD_INIT_LOG(DEBUG, "%10s : %c%d\n", "Rev", (CHIP_REV(sc) >> 12) + 'A',
11745 (CHIP_METAL(sc) >> 4));
11748 PMD_INIT_LOG(DEBUG, "%10s : %d, ", "Bus PCIe", sc->devinfo.pcie_link_width);
11749 switch (sc->devinfo.pcie_link_speed) {
11751 PMD_INIT_LOG(DEBUG, "2.5 Gbps\n");
11754 PMD_INIT_LOG(DEBUG, "5 Gbps\n");
11757 PMD_INIT_LOG(DEBUG, "8 Gbps\n");
11760 PMD_INIT_LOG(DEBUG, "Unknown link speed\n");
11763 /* Device features. */
11764 PMD_INIT_LOG(DEBUG, "%10s : ", "Flags");
11766 /* Miscellaneous flags. */
11767 if (sc->devinfo.pcie_cap_flags & BNX2X_MSI_CAPABLE_FLAG) {
11768 PMD_INIT_LOG(DEBUG, "MSI");
11772 if (sc->devinfo.pcie_cap_flags & BNX2X_MSIX_CAPABLE_FLAG) {
11774 PMD_INIT_LOG(DEBUG, "|");
11775 PMD_INIT_LOG(DEBUG, "MSI-X");
11779 PMD_INIT_LOG(DEBUG, "\n");
11782 PMD_INIT_LOG(DEBUG, "\n%10s : ", "Queues");
11783 switch (sc->sp->rss_rdata.rss_mode) {
11784 case ETH_RSS_MODE_DISABLED:
11785 PMD_INIT_LOG(DEBUG, "None\n");
11787 case ETH_RSS_MODE_REGULAR:
11788 PMD_INIT_LOG(DEBUG, "RSS : %d\n", sc->num_queues);
11791 PMD_INIT_LOG(DEBUG, "Unknown\n");
11796 /* Firmware versions and device features. */
11797 PMD_INIT_LOG(DEBUG, "%10s : %d.%d.%d\n%10s : %s\n",
11799 BNX2X_5710_FW_MAJOR_VERSION,
11800 BNX2X_5710_FW_MINOR_VERSION,
11801 BNX2X_5710_FW_REVISION_VERSION,
11802 "Bootcode", sc->devinfo.bc_ver_str);
11804 PMD_INIT_LOG(DEBUG, "===================================\n");
11805 PMD_INIT_LOG(DEBUG, "%10s : %u\n", "Bnx2x Func", sc->pcie_func);
11806 PMD_INIT_LOG(DEBUG, "%10s : %s\n", "Bnx2x Flags", get_bnx2x_flags(sc->flags));
11807 PMD_INIT_LOG(DEBUG, "%10s : %s\n", "DMAE Is",
11808 (sc->dmae_ready ? "Ready" : "Not Ready"));
11809 PMD_INIT_LOG(DEBUG, "%10s : %s\n", "OVLAN", (OVLAN(sc) ? "YES" : "NO"));
11810 PMD_INIT_LOG(DEBUG, "%10s : %s\n", "MF", (IS_MF(sc) ? "YES" : "NO"));
11811 PMD_INIT_LOG(DEBUG, "%10s : %u\n", "MTU", sc->mtu);
11812 PMD_INIT_LOG(DEBUG, "%10s : %s\n", "PHY Type", get_ext_phy_type(ext_phy_type));
11813 PMD_INIT_LOG(DEBUG, "%10s : ", "MAC Addr");
11814 for (i = 0; i < 6; i++)
11815 PMD_INIT_LOG(DEBUG, "%x%s", sc->link_params.mac_addr[i],
11816 i < 5 ? ":" : "\n");
11817 PMD_INIT_LOG(DEBUG, "%10s : %s\n", "RX Mode", get_rx_mode(sc->rx_mode));
11818 PMD_INIT_LOG(DEBUG, "%10s : %s\n", "State", get_state(sc->state));
11819 if (sc->recovery_state)
11820 PMD_INIT_LOG(DEBUG, "%10s : %s\n", "Recovery",
11821 get_recovery_state(sc->recovery_state));
11822 PMD_INIT_LOG(DEBUG, "%10s : CQ = %lx, EQ = %lx\n", "SPQ Left",
11823 sc->cq_spq_left, sc->eq_spq_left);
11824 PMD_INIT_LOG(DEBUG, "%10s : %x\n", "Switch", sc->link_params.switch_cfg);
11825 PMD_INIT_LOG(DEBUG, "===================================\n\n");