drivers/net/bnx2x/bnx2x.c

   1 /*-
   2  * Copyright (c) 2007-2013 Broadcom Corporation.
   3  *
   4  * Eric Davis        <edavis@broadcom.com>
   5  * David Christensen <davidch@broadcom.com>
   6  * Gary Zambrano     <zambrano@broadcom.com>
   7  *
   8  * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
   9  * Copyright (c) 2015 QLogic Corporation.
  10  * All rights reserved.
  11  * www.qlogic.com
  12  *
  13  * See LICENSE.bnx2x_pmd for copyright and licensing details.
  14  */
  15
  16 #define BNX2X_DRIVER_VERSION "1.78.18"
  17
  18 #include "bnx2x.h"
  19 #include "bnx2x_vfpf.h"
  20 #include "ecore_sp.h"
  21 #include "ecore_init.h"
  22 #include "ecore_init_ops.h"
  23
  24 #include "rte_version.h"
  25 #include "rte_pci_dev_ids.h"
  26
  27 #include <sys/types.h>
  28 #include <sys/stat.h>
  29 #include <fcntl.h>
  30 #include <zlib.h>
  31
  32 #define BNX2X_PMD_VER_PREFIX "BNX2X PMD"
  33 #define BNX2X_PMD_VERSION_MAJOR 1
  34 #define BNX2X_PMD_VERSION_MINOR 0
  35 #define BNX2X_PMD_VERSION_PATCH 0
  36
  37 static inline const char *
  38 bnx2x_pmd_version(void)
  39 {
  40         static char version[32];
  41
  42         snprintf(version, sizeof(version), "%s %s_%d.%d.%d",
  43                         BNX2X_PMD_VER_PREFIX,
  44                         BNX2X_DRIVER_VERSION,
  45                         BNX2X_PMD_VERSION_MAJOR,
  46                         BNX2X_PMD_VERSION_MINOR,
  47                         BNX2X_PMD_VERSION_PATCH);
  48
  49         return version;
  50 }
  51
  52 static z_stream zlib_stream;
  53
  54 #define EVL_VLID_MASK 0x0FFF
  55
  56 #define BNX2X_DEF_SB_ATT_IDX 0x0001
  57 #define BNX2X_DEF_SB_IDX     0x0002
  58
  59 /*
  60  * FLR Support - bnx2x_pf_flr_clnup() is called during nic_load in the per
  61  * function HW initialization.
  62  */
  63 #define FLR_WAIT_USEC     10000 /* 10 msecs */
  64 #define FLR_WAIT_INTERVAL 50    /* usecs */
  65 #define FLR_POLL_CNT      (FLR_WAIT_USEC / FLR_WAIT_INTERVAL)   /* 200 */
  66
  67 struct pbf_pN_buf_regs {
  68         int pN;
  69         uint32_t init_crd;
  70         uint32_t crd;
  71         uint32_t crd_freed;
  72 };
  73
  74 struct pbf_pN_cmd_regs {
  75         int pN;
  76         uint32_t lines_occup;
  77         uint32_t lines_freed;
  78 };
  79
  80 /* resources needed for unloading a previously loaded device */
  81
  82 #define BNX2X_PREV_WAIT_NEEDED 1
  83 rte_spinlock_t bnx2x_prev_mtx;
  84 struct bnx2x_prev_list_node {
  85         LIST_ENTRY(bnx2x_prev_list_node) node;
  86         uint8_t bus;
  87         uint8_t slot;
  88         uint8_t path;
  89         uint8_t aer;
  90         uint8_t undi;
  91 };
  92
  93 static LIST_HEAD(, bnx2x_prev_list_node) bnx2x_prev_list
  94         = LIST_HEAD_INITIALIZER(bnx2x_prev_list);
  95
  96 static int load_count[2][3] = { { 0 } };
  97         /* per-path: 0-common, 1-port0, 2-port1 */
  98
  99 static void bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg,
 100                                 uint8_t cmng_type);
 101 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc);
 102 static void storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng,
 103                               uint8_t port);
 104 static void bnx2x_set_reset_global(struct bnx2x_softc *sc);
 105 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc);
 106 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine);
 107 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc);
 108 static uint8_t bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global,
 109                                      uint8_t print);
 110 static void bnx2x_int_disable(struct bnx2x_softc *sc);
 111 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc);
 112 static void bnx2x_pf_disable(struct bnx2x_softc *sc);
 113 static void bnx2x_update_rx_prod(struct bnx2x_softc *sc,
 114                                  struct bnx2x_fastpath *fp,
 115                                  uint16_t rx_bd_prod, uint16_t rx_cq_prod);
 116 static void bnx2x_link_report(struct bnx2x_softc *sc);
 117 void bnx2x_link_status_update(struct bnx2x_softc *sc);
 118 static int bnx2x_alloc_mem(struct bnx2x_softc *sc);
 119 static void bnx2x_free_mem(struct bnx2x_softc *sc);
 120 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc);
 121 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc);
 122 static __attribute__ ((noinline))
 123 int bnx2x_nic_load(struct bnx2x_softc *sc);
 124
 125 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc);
 126 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp, int scan_fp);
 127 static void bnx2x_periodic_stop(struct bnx2x_softc *sc);
 128 static void bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id,
 129                          uint8_t storm, uint16_t index, uint8_t op,
 130                          uint8_t update);
 131
 132 int bnx2x_test_bit(int nr, volatile unsigned long *addr)
 133 {
 134         int res;
 135
 136         mb();
 137         res = ((*addr) & (1UL << nr)) != 0;
 138         mb();
 139         return res;
 140 }
 141
 142 void bnx2x_set_bit(unsigned int nr, volatile unsigned long *addr)
 143 {
 144         __sync_fetch_and_or(addr, (1UL << nr));
 145 }
 146
 147 void bnx2x_clear_bit(int nr, volatile unsigned long *addr)
 148 {
 149         __sync_fetch_and_and(addr, ~(1UL << nr));
 150 }
 151
 152 int bnx2x_test_and_clear_bit(int nr, volatile unsigned long *addr)
 153 {
 154         unsigned long mask = (1UL << nr);
 155         return __sync_fetch_and_and(addr, ~mask) & mask;
 156 }
 157
 158 int bnx2x_cmpxchg(volatile int *addr, int old, int new)
 159 {
 160         return __sync_val_compare_and_swap(addr, old, new);
 161 }
 162
 163 int
 164 bnx2x_dma_alloc(struct bnx2x_softc *sc, size_t size, struct bnx2x_dma *dma,
 165               const char *msg, uint32_t align)
 166 {
 167         char mz_name[RTE_MEMZONE_NAMESIZE];
 168         const struct rte_memzone *z;
 169
 170         dma->sc = sc;
 171         if (IS_PF(sc))
 172                 sprintf(mz_name, "bnx2x%d_%s_%" PRIx64, SC_ABS_FUNC(sc), msg,
 173                         rte_get_timer_cycles());
 174         else
 175                 sprintf(mz_name, "bnx2x%d_%s_%" PRIx64, sc->pcie_device, msg,
 176                         rte_get_timer_cycles());
 177
 178         /* Caller must take care that strlen(mz_name) < RTE_MEMZONE_NAMESIZE */
 179         z = rte_memzone_reserve_aligned(mz_name, (uint64_t) (size),
 180                                         rte_lcore_to_socket_id(rte_lcore_id()),
 181                                         0, align);
 182         if (z == NULL) {
 183                 PMD_DRV_LOG(ERR, "DMA alloc failed for %s", msg);
 184                 return -ENOMEM;
 185         }
 186         dma->paddr = (uint64_t) z->phys_addr;
 187         dma->vaddr = z->addr;
 188
 189         PMD_DRV_LOG(DEBUG, "%s: virt=%p phys=%" PRIx64, msg, dma->vaddr, dma->paddr);
 190
 191         return 0;
 192 }
 193
 194 static int bnx2x_acquire_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
 195 {
 196         uint32_t lock_status;
 197         uint32_t resource_bit = (1 << resource);
 198         int func = SC_FUNC(sc);
 199         uint32_t hw_lock_control_reg;
 200         int cnt;
 201
 202         PMD_INIT_FUNC_TRACE();
 203
 204         /* validate the resource is within range */
 205         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
 206                 PMD_DRV_LOG(NOTICE,
 207                             "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
 208                             resource);
 209                 return -1;
 210         }
 211
 212         if (func <= 5) {
 213                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
 214         } else {
 215                 hw_lock_control_reg =
 216                     (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
 217         }
 218
 219         /* validate the resource is not already taken */
 220         lock_status = REG_RD(sc, hw_lock_control_reg);
 221         if (lock_status & resource_bit) {
 222                 PMD_DRV_LOG(NOTICE,
 223                             "resource in use (status 0x%x bit 0x%x)",
 224                             lock_status, resource_bit);
 225                 return -1;
 226         }
 227
 228         /* try every 5ms for 5 seconds */
 229         for (cnt = 0; cnt < 1000; cnt++) {
 230                 REG_WR(sc, (hw_lock_control_reg + 4), resource_bit);
 231                 lock_status = REG_RD(sc, hw_lock_control_reg);
 232                 if (lock_status & resource_bit) {
 233                         return 0;
 234                 }
 235                 DELAY(5000);
 236         }
 237
 238         PMD_DRV_LOG(NOTICE, "Resource lock timeout!");
 239         return -1;
 240 }
 241
 242 static int bnx2x_release_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
 243 {
 244         uint32_t lock_status;
 245         uint32_t resource_bit = (1 << resource);
 246         int func = SC_FUNC(sc);
 247         uint32_t hw_lock_control_reg;
 248
 249         PMD_INIT_FUNC_TRACE();
 250
 251         /* validate the resource is within range */
 252         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
 253                 PMD_DRV_LOG(NOTICE,
 254                             "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
 255                             resource);
 256                 return -1;
 257         }
 258
 259         if (func <= 5) {
 260                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
 261         } else {
 262                 hw_lock_control_reg =
 263                     (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
 264         }
 265
 266         /* validate the resource is currently taken */
 267         lock_status = REG_RD(sc, hw_lock_control_reg);
 268         if (!(lock_status & resource_bit)) {
 269                 PMD_DRV_LOG(NOTICE,
 270                             "resource not in use (status 0x%x bit 0x%x)",
 271                             lock_status, resource_bit);
 272                 return -1;
 273         }
 274
 275         REG_WR(sc, hw_lock_control_reg, resource_bit);
 276         return 0;
 277 }
 278
 279 /* copy command into DMAE command memory and set DMAE command Go */
 280 void bnx2x_post_dmae(struct bnx2x_softc *sc, struct dmae_command *dmae, int idx)
 281 {
 282         uint32_t cmd_offset;
 283         uint32_t i;
 284
 285         cmd_offset = (DMAE_REG_CMD_MEM + (sizeof(struct dmae_command) * idx));
 286         for (i = 0; i < ((sizeof(struct dmae_command) / 4)); i++) {
 287                 REG_WR(sc, (cmd_offset + (i * 4)), *(((uint32_t *) dmae) + i));
 288         }
 289
 290         REG_WR(sc, dmae_reg_go_c[idx], 1);
 291 }
 292
 293 uint32_t bnx2x_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type)
 294 {
 295         return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
 296                           DMAE_COMMAND_C_TYPE_ENABLE);
 297 }
 298
 299 uint32_t bnx2x_dmae_opcode_clr_src_reset(uint32_t opcode)
 300 {
 301         return opcode & ~DMAE_COMMAND_SRC_RESET;
 302 }
 303
 304 uint32_t
 305 bnx2x_dmae_opcode(struct bnx2x_softc * sc, uint8_t src_type, uint8_t dst_type,
 306                 uint8_t with_comp, uint8_t comp_type)
 307 {
 308         uint32_t opcode = 0;
 309
 310         opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
 311                    (dst_type << DMAE_COMMAND_DST_SHIFT));
 312
 313         opcode |= (DMAE_COMMAND_SRC_RESET | DMAE_COMMAND_DST_RESET);
 314
 315         opcode |= (SC_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
 316
 317         opcode |= ((SC_VN(sc) << DMAE_COMMAND_E1HVN_SHIFT) |
 318                    (SC_VN(sc) << DMAE_COMMAND_DST_VN_SHIFT));
 319
 320         opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
 321
 322 #ifdef __BIG_ENDIAN
 323         opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
 324 #else
 325         opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
 326 #endif
 327
 328         if (with_comp) {
 329                 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
 330         }
 331
 332         return opcode;
 333 }
 334
 335 static void
 336 bnx2x_prep_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae,
 337                         uint8_t src_type, uint8_t dst_type)
 338 {
 339         memset(dmae, 0, sizeof(struct dmae_command));
 340
 341         /* set the opcode */
 342         dmae->opcode = bnx2x_dmae_opcode(sc, src_type, dst_type,
 343                                        TRUE, DMAE_COMP_PCI);
 344
 345         /* fill in the completion parameters */
 346         dmae->comp_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_comp));
 347         dmae->comp_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_comp));
 348         dmae->comp_val = DMAE_COMP_VAL;
 349 }
 350
 351 /* issue a DMAE command over the init channel and wait for completion */
 352 static int
 353 bnx2x_issue_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae)
 354 {
 355         uint32_t *wb_comp = BNX2X_SP(sc, wb_comp);
 356         int timeout = CHIP_REV_IS_SLOW(sc) ? 400000 : 4000;
 357
 358         /* reset completion */
 359         *wb_comp = 0;
 360
 361         /* post the command on the channel used for initializations */
 362         bnx2x_post_dmae(sc, dmae, INIT_DMAE_C(sc));
 363
 364         /* wait for completion */
 365         DELAY(500);
 366
 367         while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
 368                 if (!timeout ||
 369                     (sc->recovery_state != BNX2X_RECOVERY_DONE &&
 370                      sc->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
 371                         PMD_DRV_LOG(INFO, "DMAE timeout!");
 372                         return DMAE_TIMEOUT;
 373                 }
 374
 375                 timeout--;
 376                 DELAY(50);
 377         }
 378
 379         if (*wb_comp & DMAE_PCI_ERR_FLAG) {
 380                 PMD_DRV_LOG(INFO, "DMAE PCI error!");
 381                 return DMAE_PCI_ERROR;
 382         }
 383
 384         return 0;
 385 }
 386
 387 void bnx2x_read_dmae(struct bnx2x_softc *sc, uint32_t src_addr, uint32_t len32)
 388 {
 389         struct dmae_command dmae;
 390         uint32_t *data;
 391         uint32_t i;
 392         int rc;
 393
 394         if (!sc->dmae_ready) {
 395                 data = BNX2X_SP(sc, wb_data[0]);
 396
 397                 for (i = 0; i < len32; i++) {
 398                         data[i] = REG_RD(sc, (src_addr + (i * 4)));
 399                 }
 400
 401                 return;
 402         }
 403
 404         /* set opcode and fixed command fields */
 405         bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
 406
 407         /* fill in addresses and len */
 408         dmae.src_addr_lo = (src_addr >> 2);     /* GRC addr has dword resolution */
 409         dmae.src_addr_hi = 0;
 410         dmae.dst_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_data));
 411         dmae.dst_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_data));
 412         dmae.len = len32;
 413
 414         /* issue the command and wait for completion */
 415         if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
 416                 rte_panic("DMAE failed (%d)", rc);
 417         };
 418 }
 419
 420 void
 421 bnx2x_write_dmae(struct bnx2x_softc *sc, phys_addr_t dma_addr, uint32_t dst_addr,
 422                uint32_t len32)
 423 {
 424         struct dmae_command dmae;
 425         int rc;
 426
 427         if (!sc->dmae_ready) {
 428                 ecore_init_str_wr(sc, dst_addr, BNX2X_SP(sc, wb_data[0]), len32);
 429                 return;
 430         }
 431
 432         /* set opcode and fixed command fields */
 433         bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
 434
 435         /* fill in addresses and len */
 436         dmae.src_addr_lo = U64_LO(dma_addr);
 437         dmae.src_addr_hi = U64_HI(dma_addr);
 438         dmae.dst_addr_lo = (dst_addr >> 2);     /* GRC addr has dword resolution */
 439         dmae.dst_addr_hi = 0;
 440         dmae.len = len32;
 441
 442         /* issue the command and wait for completion */
 443         if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
 444                 rte_panic("DMAE failed (%d)", rc);
 445         }
 446 }
 447
 448 static void
 449 bnx2x_write_dmae_phys_len(struct bnx2x_softc *sc, phys_addr_t phys_addr,
 450                         uint32_t addr, uint32_t len)
 451 {
 452         uint32_t dmae_wr_max = DMAE_LEN32_WR_MAX(sc);
 453         uint32_t offset = 0;
 454
 455         while (len > dmae_wr_max) {
 456                 bnx2x_write_dmae(sc, (phys_addr + offset),      /* src DMA address */
 457                                (addr + offset), /* dst GRC address */
 458                                dmae_wr_max);
 459                 offset += (dmae_wr_max * 4);
 460                 len -= dmae_wr_max;
 461         }
 462
 463         bnx2x_write_dmae(sc, (phys_addr + offset),      /* src DMA address */
 464                        (addr + offset), /* dst GRC address */
 465                        len);
 466 }
 467
 468 void
 469 bnx2x_set_ctx_validation(struct bnx2x_softc *sc, struct eth_context *cxt,
 470                        uint32_t cid)
 471 {
 472         /* ustorm cxt validation */
 473         cxt->ustorm_ag_context.cdu_usage =
 474             CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
 475                                    CDU_REGION_NUMBER_UCM_AG,
 476                                    ETH_CONNECTION_TYPE);
 477         /* xcontext validation */
 478         cxt->xstorm_ag_context.cdu_reserved =
 479             CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
 480                                    CDU_REGION_NUMBER_XCM_AG,
 481                                    ETH_CONNECTION_TYPE);
 482 }
 483
 484 static void
 485 bnx2x_storm_memset_hc_timeout(struct bnx2x_softc *sc, uint8_t fw_sb_id,
 486                             uint8_t sb_index, uint8_t ticks)
 487 {
 488         uint32_t addr =
 489             (BAR_CSTRORM_INTMEM +
 490              CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(fw_sb_id, sb_index));
 491
 492         REG_WR8(sc, addr, ticks);
 493 }
 494
 495 static void
 496 bnx2x_storm_memset_hc_disable(struct bnx2x_softc *sc, uint16_t fw_sb_id,
 497                             uint8_t sb_index, uint8_t disable)
 498 {
 499         uint32_t enable_flag =
 500             (disable) ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
 501         uint32_t addr =
 502             (BAR_CSTRORM_INTMEM +
 503              CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(fw_sb_id, sb_index));
 504         uint8_t flags;
 505
 506         /* clear and set */
 507         flags = REG_RD8(sc, addr);
 508         flags &= ~HC_INDEX_DATA_HC_ENABLED;
 509         flags |= enable_flag;
 510         REG_WR8(sc, addr, flags);
 511 }
 512
 513 void
 514 bnx2x_update_coalesce_sb_index(struct bnx2x_softc *sc, uint8_t fw_sb_id,
 515                              uint8_t sb_index, uint8_t disable, uint16_t usec)
 516 {
 517         uint8_t ticks = (usec / 4);
 518
 519         bnx2x_storm_memset_hc_timeout(sc, fw_sb_id, sb_index, ticks);
 520
 521         disable = (disable) ? 1 : ((usec) ? 0 : 1);
 522         bnx2x_storm_memset_hc_disable(sc, fw_sb_id, sb_index, disable);
 523 }
 524
 525 uint32_t elink_cb_reg_read(struct bnx2x_softc *sc, uint32_t reg_addr)
 526 {
 527         return REG_RD(sc, reg_addr);
 528 }
 529
 530 void elink_cb_reg_write(struct bnx2x_softc *sc, uint32_t reg_addr, uint32_t val)
 531 {
 532         REG_WR(sc, reg_addr, val);
 533 }
 534
 535 void
 536 elink_cb_event_log(__rte_unused struct bnx2x_softc *sc,
 537                    __rte_unused const elink_log_id_t elink_log_id, ...)
 538 {
 539         PMD_DRV_LOG(DEBUG, "ELINK EVENT LOG (%d)", elink_log_id);
 540 }
 541
 542 static int bnx2x_set_spio(struct bnx2x_softc *sc, int spio, uint32_t mode)
 543 {
 544         uint32_t spio_reg;
 545
 546         /* Only 2 SPIOs are configurable */
 547         if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
 548                 PMD_DRV_LOG(NOTICE, "Invalid SPIO 0x%x", spio);
 549                 return -1;
 550         }
 551
 552         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
 553
 554         /* read SPIO and mask except the float bits */
 555         spio_reg = (REG_RD(sc, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
 556
 557         switch (mode) {
 558         case MISC_SPIO_OUTPUT_LOW:
 559                 /* clear FLOAT and set CLR */
 560                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
 561                 spio_reg |= (spio << MISC_SPIO_CLR_POS);
 562                 break;
 563
 564         case MISC_SPIO_OUTPUT_HIGH:
 565                 /* clear FLOAT and set SET */
 566                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
 567                 spio_reg |= (spio << MISC_SPIO_SET_POS);
 568                 break;
 569
 570         case MISC_SPIO_INPUT_HI_Z:
 571                 /* set FLOAT */
 572                 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
 573                 break;
 574
 575         default:
 576                 break;
 577         }
 578
 579         REG_WR(sc, MISC_REG_SPIO, spio_reg);
 580         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
 581
 582         return 0;
 583 }
 584
 585 static int bnx2x_gpio_read(struct bnx2x_softc *sc, int gpio_num, uint8_t port)
 586 {
 587         /* The GPIO should be swapped if swap register is set and active */
 588         int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
 589                           REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
 590         int gpio_shift = gpio_num;
 591         if (gpio_port)
 592                 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
 593
 594         uint32_t gpio_mask = (1 << gpio_shift);
 595         uint32_t gpio_reg;
 596
 597         if (gpio_num > MISC_REGISTERS_GPIO_3) {
 598                 PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
 599                 return -1;
 600         }
 601
 602         /* read GPIO value */
 603         gpio_reg = REG_RD(sc, MISC_REG_GPIO);
 604
 605         /* get the requested pin value */
 606         return ((gpio_reg & gpio_mask) == gpio_mask) ? 1 : 0;
 607 }
 608
 609 static int
 610 bnx2x_gpio_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode, uint8_t port)
 611 {
 612         /* The GPIO should be swapped if swap register is set and active */
 613         int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
 614                           REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
 615         int gpio_shift = gpio_num;
 616         if (gpio_port)
 617                 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
 618
 619         uint32_t gpio_mask = (1 << gpio_shift);
 620         uint32_t gpio_reg;
 621
 622         if (gpio_num > MISC_REGISTERS_GPIO_3) {
 623                 PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
 624                 return -1;
 625         }
 626
 627         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 628
 629         /* read GPIO and mask except the float bits */
 630         gpio_reg = (REG_RD(sc, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
 631
 632         switch (mode) {
 633         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
 634                 /* clear FLOAT and set CLR */
 635                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
 636                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
 637                 break;
 638
 639         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
 640                 /* clear FLOAT and set SET */
 641                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
 642                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
 643                 break;
 644
 645         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
 646                 /* set FLOAT */
 647                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
 648                 break;
 649
 650         default:
 651                 break;
 652         }
 653
 654         REG_WR(sc, MISC_REG_GPIO, gpio_reg);
 655         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 656
 657         return 0;
 658 }
 659
 660 static int
 661 bnx2x_gpio_mult_write(struct bnx2x_softc *sc, uint8_t pins, uint32_t mode)
 662 {
 663         uint32_t gpio_reg;
 664
 665         /* any port swapping should be handled by caller */
 666
 667         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 668
 669         /* read GPIO and mask except the float bits */
 670         gpio_reg = REG_RD(sc, MISC_REG_GPIO);
 671         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
 672         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
 673         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
 674
 675         switch (mode) {
 676         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
 677                 /* set CLR */
 678                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
 679                 break;
 680
 681         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
 682                 /* set SET */
 683                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
 684                 break;
 685
 686         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
 687                 /* set FLOAT */
 688                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
 689                 break;
 690
 691         default:
 692                 PMD_DRV_LOG(NOTICE, "Invalid GPIO mode assignment %d", mode);
 693                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 694                 return -1;
 695         }
 696
 697         REG_WR(sc, MISC_REG_GPIO, gpio_reg);
 698         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 699
 700         return 0;
 701 }
 702
 703 static int
 704 bnx2x_gpio_int_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode,
 705                    uint8_t port)
 706 {
 707         /* The GPIO should be swapped if swap register is set and active */
 708         int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
 709                           REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
 710         int gpio_shift = gpio_num;
 711         if (gpio_port)
 712                 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
 713
 714         uint32_t gpio_mask = (1 << gpio_shift);
 715         uint32_t gpio_reg;
 716
 717         if (gpio_num > MISC_REGISTERS_GPIO_3) {
 718                 PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
 719                 return -1;
 720         }
 721
 722         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 723
 724         /* read GPIO int */
 725         gpio_reg = REG_RD(sc, MISC_REG_GPIO_INT);
 726
 727         switch (mode) {
 728         case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
 729                 /* clear SET and set CLR */
 730                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
 731                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
 732                 break;
 733
 734         case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
 735                 /* clear CLR and set SET */
 736                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
 737                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
 738                 break;
 739
 740         default:
 741                 break;
 742         }
 743
 744         REG_WR(sc, MISC_REG_GPIO_INT, gpio_reg);
 745         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 746
 747         return 0;
 748 }
 749
 750 uint32_t
 751 elink_cb_gpio_read(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t port)
 752 {
 753         return bnx2x_gpio_read(sc, gpio_num, port);
 754 }
 755
 756 uint8_t elink_cb_gpio_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode,   /* 0=low 1=high */
 757                             uint8_t port)
 758 {
 759         return bnx2x_gpio_write(sc, gpio_num, mode, port);
 760 }
 761
 762 uint8_t
 763 elink_cb_gpio_mult_write(struct bnx2x_softc * sc, uint8_t pins,
 764                          uint8_t mode /* 0=low 1=high */ )
 765 {
 766         return bnx2x_gpio_mult_write(sc, pins, mode);
 767 }
 768
 769 uint8_t elink_cb_gpio_int_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode,       /* 0=low 1=high */
 770                                 uint8_t port)
 771 {
 772         return bnx2x_gpio_int_write(sc, gpio_num, mode, port);
 773 }
 774
 775 void elink_cb_notify_link_changed(struct bnx2x_softc *sc)
 776 {
 777         REG_WR(sc, (MISC_REG_AEU_GENERAL_ATTN_12 +
 778                     (SC_FUNC(sc) * sizeof(uint32_t))), 1);
 779 }
 780
 781 /* send the MCP a request, block until there is a reply */
 782 uint32_t
 783 elink_cb_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
 784 {
 785         int mb_idx = SC_FW_MB_IDX(sc);
 786         uint32_t seq;
 787         uint32_t rc = 0;
 788         uint32_t cnt = 1;
 789         uint8_t delay = CHIP_REV_IS_SLOW(sc) ? 100 : 10;
 790
 791         seq = ++sc->fw_seq;
 792         SHMEM_WR(sc, func_mb[mb_idx].drv_mb_param, param);
 793         SHMEM_WR(sc, func_mb[mb_idx].drv_mb_header, (command | seq));
 794
 795         PMD_DRV_LOG(DEBUG,
 796                     "wrote command 0x%08x to FW MB param 0x%08x",
 797                     (command | seq), param);
 798
 799         /* Let the FW do it's magic. GIve it up to 5 seconds... */
 800         do {
 801                 DELAY(delay * 1000);
 802                 rc = SHMEM_RD(sc, func_mb[mb_idx].fw_mb_header);
 803         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
 804
 805         /* is this a reply to our command? */
 806         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) {
 807                 rc &= FW_MSG_CODE_MASK;
 808         } else {
 809                 /* Ruh-roh! */
 810                 PMD_DRV_LOG(NOTICE, "FW failed to respond!");
 811                 rc = 0;
 812         }
 813
 814         return rc;
 815 }
 816
 817 static uint32_t
 818 bnx2x_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
 819 {
 820         return elink_cb_fw_command(sc, command, param);
 821 }
 822
 823 static void
 824 __storm_memset_dma_mapping(struct bnx2x_softc *sc, uint32_t addr,
 825                            phys_addr_t mapping)
 826 {
 827         REG_WR(sc, addr, U64_LO(mapping));
 828         REG_WR(sc, (addr + 4), U64_HI(mapping));
 829 }
 830
 831 static void
 832 storm_memset_spq_addr(struct bnx2x_softc *sc, phys_addr_t mapping,
 833                       uint16_t abs_fid)
 834 {
 835         uint32_t addr = (XSEM_REG_FAST_MEMORY +
 836                          XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid));
 837         __storm_memset_dma_mapping(sc, addr, mapping);
 838 }
 839
 840 static void
 841 storm_memset_vf_to_pf(struct bnx2x_softc *sc, uint16_t abs_fid, uint16_t pf_id)
 842 {
 843         REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid)),
 844                 pf_id);
 845         REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid)),
 846                 pf_id);
 847         REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid)),
 848                 pf_id);
 849         REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid)),
 850                 pf_id);
 851 }
 852
 853 static void
 854 storm_memset_func_en(struct bnx2x_softc *sc, uint16_t abs_fid, uint8_t enable)
 855 {
 856         REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid)),
 857                 enable);
 858         REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid)),
 859                 enable);
 860         REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid)),
 861                 enable);
 862         REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid)),
 863                 enable);
 864 }
 865
 866 static void
 867 storm_memset_eq_data(struct bnx2x_softc *sc, struct event_ring_data *eq_data,
 868                      uint16_t pfid)
 869 {
 870         uint32_t addr;
 871         size_t size;
 872
 873         addr = (BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid));
 874         size = sizeof(struct event_ring_data);
 875         ecore_storm_memset_struct(sc, addr, size, (uint32_t *) eq_data);
 876 }
 877
 878 static void
 879 storm_memset_eq_prod(struct bnx2x_softc *sc, uint16_t eq_prod, uint16_t pfid)
 880 {
 881         uint32_t addr = (BAR_CSTRORM_INTMEM +
 882                          CSTORM_EVENT_RING_PROD_OFFSET(pfid));
 883         REG_WR16(sc, addr, eq_prod);
 884 }
 885
 886 /*
 887  * Post a slowpath command.
 888  *
 889  * A slowpath command is used to propogate a configuration change through
 890  * the controller in a controlled manner, allowing each STORM processor and
 891  * other H/W blocks to phase in the change.  The commands sent on the
 892  * slowpath are referred to as ramrods.  Depending on the ramrod used the
 893  * completion of the ramrod will occur in different ways.  Here's a
 894  * breakdown of ramrods and how they complete:
 895  *
 896  * RAMROD_CMD_ID_ETH_PORT_SETUP
 897  *   Used to setup the leading connection on a port.  Completes on the
 898  *   Receive Completion Queue (RCQ) of that port (typically fp[0]).
 899  *
 900  * RAMROD_CMD_ID_ETH_CLIENT_SETUP
 901  *   Used to setup an additional connection on a port.  Completes on the
 902  *   RCQ of the multi-queue/RSS connection being initialized.
 903  *
 904  * RAMROD_CMD_ID_ETH_STAT_QUERY
 905  *   Used to force the storm processors to update the statistics database
 906  *   in host memory.  This ramrod is send on the leading connection CID and
 907  *   completes as an index increment of the CSTORM on the default status
 908  *   block.
 909  *
 910  * RAMROD_CMD_ID_ETH_UPDATE
 911  *   Used to update the state of the leading connection, usually to udpate
 912  *   the RSS indirection table.  Completes on the RCQ of the leading
 913  *   connection. (Not currently used under FreeBSD until OS support becomes
 914  *   available.)
 915  *
 916  * RAMROD_CMD_ID_ETH_HALT
 917  *   Used when tearing down a connection prior to driver unload.  Completes
 918  *   on the RCQ of the multi-queue/RSS connection being torn down.  Don't
 919  *   use this on the leading connection.
 920  *
 921  * RAMROD_CMD_ID_ETH_SET_MAC
 922  *   Sets the Unicast/Broadcast/Multicast used by the port.  Completes on
 923  *   the RCQ of the leading connection.
 924  *
 925  * RAMROD_CMD_ID_ETH_CFC_DEL
 926  *   Used when tearing down a conneciton prior to driver unload.  Completes
 927  *   on the RCQ of the leading connection (since the current connection
 928  *   has been completely removed from controller memory).
 929  *
 930  * RAMROD_CMD_ID_ETH_PORT_DEL
 931  *   Used to tear down the leading connection prior to driver unload,
 932  *   typically fp[0].  Completes as an index increment of the CSTORM on the
 933  *   default status block.
 934  *
 935  * RAMROD_CMD_ID_ETH_FORWARD_SETUP
 936  *   Used for connection offload.  Completes on the RCQ of the multi-queue
 937  *   RSS connection that is being offloaded.  (Not currently used under
 938  *   FreeBSD.)
 939  *
 940  * There can only be one command pending per function.
 941  *
 942  * Returns:
 943  *   0 = Success, !0 = Failure.
 944  */
 945
 946 /* must be called under the spq lock */
 947 static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x_softc *sc)
 948 {
 949         struct eth_spe *next_spe = sc->spq_prod_bd;
 950
 951         if (sc->spq_prod_bd == sc->spq_last_bd) {
 952                 /* wrap back to the first eth_spq */
 953                 sc->spq_prod_bd = sc->spq;
 954                 sc->spq_prod_idx = 0;
 955         } else {
 956                 sc->spq_prod_bd++;
 957                 sc->spq_prod_idx++;
 958         }
 959
 960         return next_spe;
 961 }
 962
 963 /* must be called under the spq lock */
 964 static void bnx2x_sp_prod_update(struct bnx2x_softc *sc)
 965 {
 966         int func = SC_FUNC(sc);
 967
 968         /*
 969          * Make sure that BD data is updated before writing the producer.
 970          * BD data is written to the memory, the producer is read from the
 971          * memory, thus we need a full memory barrier to ensure the ordering.
 972          */
 973         mb();
 974
 975         REG_WR16(sc, (BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func)),
 976                  sc->spq_prod_idx);
 977
 978         mb();
 979 }
 980
 981 /**
 982  * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
 983  *
 984  * @cmd:      command to check
 985  * @cmd_type: command type
 986  */
 987 static int bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
 988 {
 989         if ((cmd_type == NONE_CONNECTION_TYPE) ||
 990             (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
 991             (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
 992             (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
 993             (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
 994             (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
 995             (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) {
 996                 return TRUE;
 997         } else {
 998                 return FALSE;
 999         }
1000 }
1001
1002 /**
1003  * bnx2x_sp_post - place a single command on an SP ring
1004  *
1005  * @sc:         driver handle
1006  * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
1007  * @cid:        SW CID the command is related to
1008  * @data_hi:    command private data address (high 32 bits)
1009  * @data_lo:    command private data address (low 32 bits)
1010  * @cmd_type:   command type (e.g. NONE, ETH)
1011  *
1012  * SP data is handled as if it's always an address pair, thus data fields are
1013  * not swapped to little endian in upper functions. Instead this function swaps
1014  * data as if it's two uint32 fields.
1015  */
1016 int
1017 bnx2x_sp_post(struct bnx2x_softc *sc, int command, int cid, uint32_t data_hi,
1018             uint32_t data_lo, int cmd_type)
1019 {
1020         struct eth_spe *spe;
1021         uint16_t type;
1022         int common;
1023
1024         common = bnx2x_is_contextless_ramrod(command, cmd_type);
1025
1026         if (common) {
1027                 if (!atomic_load_acq_long(&sc->eq_spq_left)) {
1028                         PMD_DRV_LOG(INFO, "EQ ring is full!");
1029                         return -1;
1030                 }
1031         } else {
1032                 if (!atomic_load_acq_long(&sc->cq_spq_left)) {
1033                         PMD_DRV_LOG(INFO, "SPQ ring is full!");
1034                         return -1;
1035                 }
1036         }
1037
1038         spe = bnx2x_sp_get_next(sc);
1039
1040         /* CID needs port number to be encoded int it */
1041         spe->hdr.conn_and_cmd_data =
1042             htole32((command << SPE_HDR_CMD_ID_SHIFT) | HW_CID(sc, cid));
1043
1044         type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
1045
1046         /* TBD: Check if it works for VFs */
1047         type |= ((SC_FUNC(sc) << SPE_HDR_FUNCTION_ID_SHIFT) &
1048                  SPE_HDR_FUNCTION_ID);
1049
1050         spe->hdr.type = htole16(type);
1051
1052         spe->data.update_data_addr.hi = htole32(data_hi);
1053         spe->data.update_data_addr.lo = htole32(data_lo);
1054
1055         /*
1056          * It's ok if the actual decrement is issued towards the memory
1057          * somewhere between the lock and unlock. Thus no more explict
1058          * memory barrier is needed.
1059          */
1060         if (common) {
1061                 atomic_subtract_acq_long(&sc->eq_spq_left, 1);
1062         } else {
1063                 atomic_subtract_acq_long(&sc->cq_spq_left, 1);
1064         }
1065
1066         PMD_DRV_LOG(DEBUG,
1067                     "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x"
1068                     "data (%x:%x) type(0x%x) left (CQ, EQ) (%lx,%lx)",
1069                     sc->spq_prod_idx,
1070                     (uint32_t) U64_HI(sc->spq_dma.paddr),
1071                     (uint32_t) (U64_LO(sc->spq_dma.paddr) +
1072                                 (uint8_t *) sc->spq_prod_bd -
1073                                 (uint8_t *) sc->spq), command, common,
1074                     HW_CID(sc, cid), data_hi, data_lo, type,
1075                     atomic_load_acq_long(&sc->cq_spq_left),
1076                     atomic_load_acq_long(&sc->eq_spq_left));
1077
1078         bnx2x_sp_prod_update(sc);
1079
1080         return 0;
1081 }
1082
1083 static void bnx2x_drv_pulse(struct bnx2x_softc *sc)
1084 {
1085         SHMEM_WR(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb,
1086                  sc->fw_drv_pulse_wr_seq);
1087 }
1088
1089 static int bnx2x_tx_queue_has_work(const struct bnx2x_fastpath *fp)
1090 {
1091         uint16_t hw_cons;
1092         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1093
1094         if (unlikely(!txq)) {
1095                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1096                 return 0;
1097         }
1098
1099         mb();                   /* status block fields can change */
1100         hw_cons = le16toh(*fp->tx_cons_sb);
1101         return hw_cons != txq->tx_pkt_head;
1102 }
1103
1104 static uint8_t bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
1105 {
1106         /* expand this for multi-cos if ever supported */
1107         return bnx2x_tx_queue_has_work(fp);
1108 }
1109
1110 static int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
1111 {
1112         uint16_t rx_cq_cons_sb;
1113         struct bnx2x_rx_queue *rxq;
1114         rxq = fp->sc->rx_queues[fp->index];
1115         if (unlikely(!rxq)) {
1116                 PMD_RX_LOG(ERR, "ERROR: RX queue is NULL");
1117                 return 0;
1118         }
1119
1120         mb();                   /* status block fields can change */
1121         rx_cq_cons_sb = le16toh(*fp->rx_cq_cons_sb);
1122         if (unlikely((rx_cq_cons_sb & MAX_RCQ_ENTRIES(rxq)) ==
1123                      MAX_RCQ_ENTRIES(rxq)))
1124                 rx_cq_cons_sb++;
1125         return rxq->rx_cq_head != rx_cq_cons_sb;
1126 }
1127
1128 static void
1129 bnx2x_sp_event(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
1130              union eth_rx_cqe *rr_cqe)
1131 {
1132 #ifdef RTE_LIBRTE_BNX2X_DEBUG
1133         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1134 #endif
1135         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1136         enum ecore_queue_cmd drv_cmd = ECORE_Q_CMD_MAX;
1137         struct ecore_queue_sp_obj *q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
1138
1139         PMD_DRV_LOG(DEBUG,
1140                     "fp=%d cid=%d got ramrod #%d state is %x type is %d",
1141                     fp->index, cid, command, sc->state,
1142                     rr_cqe->ramrod_cqe.ramrod_type);
1143
1144         switch (command) {
1145         case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1146                 PMD_DRV_LOG(DEBUG, "got UPDATE ramrod. CID %d", cid);
1147                 drv_cmd = ECORE_Q_CMD_UPDATE;
1148                 break;
1149
1150         case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1151                 PMD_DRV_LOG(DEBUG, "got MULTI[%d] setup ramrod", cid);
1152                 drv_cmd = ECORE_Q_CMD_SETUP;
1153                 break;
1154
1155         case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1156                 PMD_DRV_LOG(DEBUG, "got MULTI[%d] tx-only setup ramrod", cid);
1157                 drv_cmd = ECORE_Q_CMD_SETUP_TX_ONLY;
1158                 break;
1159
1160         case (RAMROD_CMD_ID_ETH_HALT):
1161                 PMD_DRV_LOG(DEBUG, "got MULTI[%d] halt ramrod", cid);
1162                 drv_cmd = ECORE_Q_CMD_HALT;
1163                 break;
1164
1165         case (RAMROD_CMD_ID_ETH_TERMINATE):
1166                 PMD_DRV_LOG(DEBUG, "got MULTI[%d] teminate ramrod", cid);
1167                 drv_cmd = ECORE_Q_CMD_TERMINATE;
1168                 break;
1169
1170         case (RAMROD_CMD_ID_ETH_EMPTY):
1171                 PMD_DRV_LOG(DEBUG, "got MULTI[%d] empty ramrod", cid);
1172                 drv_cmd = ECORE_Q_CMD_EMPTY;
1173                 break;
1174
1175         default:
1176                 PMD_DRV_LOG(DEBUG,
1177                             "ERROR: unexpected MC reply (%d)"
1178                             "on fp[%d]", command, fp->index);
1179                 return;
1180         }
1181
1182         if ((drv_cmd != ECORE_Q_CMD_MAX) &&
1183             q_obj->complete_cmd(sc, q_obj, drv_cmd)) {
1184                 /*
1185                  * q_obj->complete_cmd() failure means that this was
1186                  * an unexpected completion.
1187                  *
1188                  * In this case we don't want to increase the sc->spq_left
1189                  * because apparently we haven't sent this command the first
1190                  * place.
1191                  */
1192                 // rte_panic("Unexpected SP completion");
1193                 return;
1194         }
1195
1196         atomic_add_acq_long(&sc->cq_spq_left, 1);
1197
1198         PMD_DRV_LOG(DEBUG, "sc->cq_spq_left 0x%lx",
1199                     atomic_load_acq_long(&sc->cq_spq_left));
1200 }
1201
1202 static uint8_t bnx2x_rxeof(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
1203 {
1204         struct bnx2x_rx_queue *rxq;
1205         uint16_t bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
1206         uint16_t hw_cq_cons, sw_cq_cons, sw_cq_prod;
1207
1208         rxq = sc->rx_queues[fp->index];
1209         if (!rxq) {
1210                 PMD_RX_LOG(ERR, "RX queue %d is NULL", fp->index);
1211                 return 0;
1212         }
1213
1214         /* CQ "next element" is of the size of the regular element */
1215         hw_cq_cons = le16toh(*fp->rx_cq_cons_sb);
1216         if (unlikely((hw_cq_cons & USABLE_RCQ_ENTRIES_PER_PAGE) ==
1217                      USABLE_RCQ_ENTRIES_PER_PAGE)) {
1218                 hw_cq_cons++;
1219         }
1220
1221         bd_cons = rxq->rx_bd_head;
1222         bd_prod = rxq->rx_bd_tail;
1223         bd_prod_fw = bd_prod;
1224         sw_cq_cons = rxq->rx_cq_head;
1225         sw_cq_prod = rxq->rx_cq_tail;
1226
1227         /*
1228          * Memory barrier necessary as speculative reads of the rx
1229          * buffer can be ahead of the index in the status block
1230          */
1231         rmb();
1232
1233         while (sw_cq_cons != hw_cq_cons) {
1234                 union eth_rx_cqe *cqe;
1235                 struct eth_fast_path_rx_cqe *cqe_fp;
1236                 uint8_t cqe_fp_flags;
1237                 enum eth_rx_cqe_type cqe_fp_type;
1238
1239                 comp_ring_cons = RCQ_ENTRY(sw_cq_cons, rxq);
1240                 bd_prod = RX_BD(bd_prod, rxq);
1241                 bd_cons = RX_BD(bd_cons, rxq);
1242
1243                 cqe = &rxq->cq_ring[comp_ring_cons];
1244                 cqe_fp = &cqe->fast_path_cqe;
1245                 cqe_fp_flags = cqe_fp->type_error_flags;
1246                 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
1247
1248                 /* is this a slowpath msg? */
1249                 if (CQE_TYPE_SLOW(cqe_fp_type)) {
1250                         bnx2x_sp_event(sc, fp, cqe);
1251                         goto next_cqe;
1252                 }
1253
1254                 /* is this an error packet? */
1255                 if (unlikely(cqe_fp_flags &
1256                              ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG)) {
1257                         PMD_RX_LOG(DEBUG, "flags 0x%x rx packet %u",
1258                                    cqe_fp_flags, sw_cq_cons);
1259                         goto next_rx;
1260                 }
1261
1262                 PMD_RX_LOG(DEBUG, "Dropping fastpath called from attn poller!");
1263
1264 next_rx:
1265                 bd_cons = NEXT_RX_BD(bd_cons);
1266                 bd_prod = NEXT_RX_BD(bd_prod);
1267                 bd_prod_fw = NEXT_RX_BD(bd_prod_fw);
1268
1269 next_cqe:
1270                 sw_cq_prod = NEXT_RCQ_IDX(sw_cq_prod);
1271                 sw_cq_cons = NEXT_RCQ_IDX(sw_cq_cons);
1272
1273         }                       /* while work to do */
1274
1275         rxq->rx_bd_head = bd_cons;
1276         rxq->rx_bd_tail = bd_prod_fw;
1277         rxq->rx_cq_head = sw_cq_cons;
1278         rxq->rx_cq_tail = sw_cq_prod;
1279
1280         /* Update producers */
1281         bnx2x_update_rx_prod(sc, fp, bd_prod_fw, sw_cq_prod);
1282
1283         return sw_cq_cons != hw_cq_cons;
1284 }
1285
1286 static uint16_t
1287 bnx2x_free_tx_pkt(__rte_unused struct bnx2x_fastpath *fp, struct bnx2x_tx_queue *txq,
1288                 uint16_t pkt_idx, uint16_t bd_idx)
1289 {
1290         struct eth_tx_start_bd *tx_start_bd =
1291             &txq->tx_ring[TX_BD(bd_idx, txq)].start_bd;
1292         uint16_t nbd = rte_le_to_cpu_16(tx_start_bd->nbd);
1293         struct rte_mbuf *tx_mbuf = txq->sw_ring[TX_BD(pkt_idx, txq)];
1294
1295         if (likely(tx_mbuf != NULL)) {
1296                 rte_pktmbuf_free(tx_mbuf);
1297         } else {
1298                 PMD_RX_LOG(ERR, "fp[%02d] lost mbuf %lu",
1299                            fp->index, (unsigned long)TX_BD(pkt_idx, txq));
1300         }
1301
1302         txq->sw_ring[TX_BD(pkt_idx, txq)] = NULL;
1303         txq->nb_tx_avail += nbd;
1304
1305         while (nbd--)
1306                 bd_idx = NEXT_TX_BD(bd_idx);
1307
1308         return bd_idx;
1309 }
1310
1311 /* processes transmit completions */
1312 uint8_t bnx2x_txeof(__rte_unused struct bnx2x_softc * sc, struct bnx2x_fastpath * fp)
1313 {
1314         uint16_t bd_cons, hw_cons, sw_cons;
1315         __rte_unused uint16_t tx_bd_avail;
1316
1317         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1318
1319         if (unlikely(!txq)) {
1320                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1321                 return 0;
1322         }
1323
1324         bd_cons = txq->tx_bd_head;
1325         hw_cons = rte_le_to_cpu_16(*fp->tx_cons_sb);
1326         sw_cons = txq->tx_pkt_head;
1327
1328         while (sw_cons != hw_cons) {
1329                 bd_cons = bnx2x_free_tx_pkt(fp, txq, sw_cons, bd_cons);
1330                 sw_cons++;
1331         }
1332
1333         txq->tx_pkt_head = sw_cons;
1334         txq->tx_bd_head = bd_cons;
1335
1336         tx_bd_avail = txq->nb_tx_avail;
1337
1338         PMD_TX_LOG(DEBUG, "fp[%02d] avail=%u cons_sb=%u, "
1339                    "pkt_head=%u pkt_tail=%u bd_head=%u bd_tail=%u",
1340                    fp->index, tx_bd_avail, hw_cons,
1341                    txq->tx_pkt_head, txq->tx_pkt_tail,
1342                    txq->tx_bd_head, txq->tx_bd_tail);
1343         return TRUE;
1344 }
1345
1346 static void bnx2x_drain_tx_queues(struct bnx2x_softc *sc)
1347 {
1348         struct bnx2x_fastpath *fp;
1349         int i, count;
1350
1351         /* wait until all TX fastpath tasks have completed */
1352         for (i = 0; i < sc->num_queues; i++) {
1353                 fp = &sc->fp[i];
1354
1355                 count = 1000;
1356
1357                 while (bnx2x_has_tx_work(fp)) {
1358                         bnx2x_txeof(sc, fp);
1359
1360                         if (count == 0) {
1361                                 PMD_TX_LOG(ERR,
1362                                            "Timeout waiting for fp[%d] "
1363                                            "transmits to complete!", i);
1364                                 rte_panic("tx drain failure");
1365                                 return;
1366                         }
1367
1368                         count--;
1369                         DELAY(1000);
1370                         rmb();
1371                 }
1372         }
1373
1374         return;
1375 }
1376
1377 static int
1378 bnx2x_del_all_macs(struct bnx2x_softc *sc, struct ecore_vlan_mac_obj *mac_obj,
1379                  int mac_type, uint8_t wait_for_comp)
1380 {
1381         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1382         int rc;
1383
1384         /* wait for completion of requested */
1385         if (wait_for_comp) {
1386                 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1387         }
1388
1389         /* Set the mac type of addresses we want to clear */
1390         bnx2x_set_bit(mac_type, &vlan_mac_flags);
1391
1392         rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1393         if (rc < 0)
1394                 PMD_DRV_LOG(ERR, "Failed to delete MACs (%d)", rc);
1395
1396         return rc;
1397 }
1398
1399 int
1400 bnx2x_fill_accept_flags(struct bnx2x_softc *sc, uint32_t rx_mode,
1401                       unsigned long *rx_accept_flags,
1402                       unsigned long *tx_accept_flags)
1403 {
1404         /* Clear the flags first */
1405         *rx_accept_flags = 0;
1406         *tx_accept_flags = 0;
1407
1408         switch (rx_mode) {
1409         case BNX2X_RX_MODE_NONE:
1410                 /*
1411                  * 'drop all' supersedes any accept flags that may have been
1412                  * passed to the function.
1413                  */
1414                 break;
1415
1416         case BNX2X_RX_MODE_NORMAL:
1417                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1418                 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, rx_accept_flags);
1419                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1420
1421                 /* internal switching mode */
1422                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1423                 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, tx_accept_flags);
1424                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1425
1426                 break;
1427
1428         case BNX2X_RX_MODE_ALLMULTI:
1429                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1430                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1431                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1432
1433                 /* internal switching mode */
1434                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1435                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1436                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1437
1438                 break;
1439
1440         case BNX2X_RX_MODE_PROMISC:
1441                 /*
1442                  * According to deffinition of SI mode, iface in promisc mode
1443                  * should receive matched and unmatched (in resolution of port)
1444                  * unicast packets.
1445                  */
1446                 bnx2x_set_bit(ECORE_ACCEPT_UNMATCHED, rx_accept_flags);
1447                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1448                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1449                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1450
1451                 /* internal switching mode */
1452                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1453                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1454
1455                 if (IS_MF_SI(sc)) {
1456                         bnx2x_set_bit(ECORE_ACCEPT_ALL_UNICAST, tx_accept_flags);
1457                 } else {
1458                         bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1459                 }
1460
1461                 break;
1462
1463         default:
1464                 PMD_RX_LOG(ERR, "Unknown rx_mode (%d)", rx_mode);
1465                 return -1;
1466         }
1467
1468         /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
1469         if (rx_mode != BNX2X_RX_MODE_NONE) {
1470                 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, rx_accept_flags);
1471                 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, tx_accept_flags);
1472         }
1473
1474         return 0;
1475 }
1476
1477 static int
1478 bnx2x_set_q_rx_mode(struct bnx2x_softc *sc, uint8_t cl_id,
1479                   unsigned long rx_mode_flags,
1480                   unsigned long rx_accept_flags,
1481                   unsigned long tx_accept_flags, unsigned long ramrod_flags)
1482 {
1483         struct ecore_rx_mode_ramrod_params ramrod_param;
1484         int rc;
1485
1486         memset(&ramrod_param, 0, sizeof(ramrod_param));
1487
1488         /* Prepare ramrod parameters */
1489         ramrod_param.cid = 0;
1490         ramrod_param.cl_id = cl_id;
1491         ramrod_param.rx_mode_obj = &sc->rx_mode_obj;
1492         ramrod_param.func_id = SC_FUNC(sc);
1493
1494         ramrod_param.pstate = &sc->sp_state;
1495         ramrod_param.state = ECORE_FILTER_RX_MODE_PENDING;
1496
1497         ramrod_param.rdata = BNX2X_SP(sc, rx_mode_rdata);
1498         ramrod_param.rdata_mapping =
1499             (phys_addr_t)BNX2X_SP_MAPPING(sc, rx_mode_rdata),
1500             bnx2x_set_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
1501
1502         ramrod_param.ramrod_flags = ramrod_flags;
1503         ramrod_param.rx_mode_flags = rx_mode_flags;
1504
1505         ramrod_param.rx_accept_flags = rx_accept_flags;
1506         ramrod_param.tx_accept_flags = tx_accept_flags;
1507
1508         rc = ecore_config_rx_mode(sc, &ramrod_param);
1509         if (rc < 0) {
1510                 PMD_RX_LOG(ERR, "Set rx_mode %d failed", sc->rx_mode);
1511                 return rc;
1512         }
1513
1514         return 0;
1515 }
1516
1517 int bnx2x_set_storm_rx_mode(struct bnx2x_softc *sc)
1518 {
1519         unsigned long rx_mode_flags = 0, ramrod_flags = 0;
1520         unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
1521         int rc;
1522
1523         rc = bnx2x_fill_accept_flags(sc, sc->rx_mode, &rx_accept_flags,
1524                                    &tx_accept_flags);
1525         if (rc) {
1526                 return rc;
1527         }
1528
1529         bnx2x_set_bit(RAMROD_RX, &ramrod_flags);
1530         bnx2x_set_bit(RAMROD_TX, &ramrod_flags);
1531         bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1532
1533         return bnx2x_set_q_rx_mode(sc, sc->fp[0].cl_id, rx_mode_flags,
1534                                  rx_accept_flags, tx_accept_flags,
1535                                  ramrod_flags);
1536 }
1537
1538 /* returns the "mcp load_code" according to global load_count array */
1539 static int bnx2x_nic_load_no_mcp(struct bnx2x_softc *sc)
1540 {
1541         int path = SC_PATH(sc);
1542         int port = SC_PORT(sc);
1543
1544         PMD_DRV_LOG(INFO, "NO MCP - load counts[%d]      %d, %d, %d",
1545                     path, load_count[path][0], load_count[path][1],
1546                     load_count[path][2]);
1547
1548         load_count[path][0]++;
1549         load_count[path][1 + port]++;
1550         PMD_DRV_LOG(INFO, "NO MCP - new load counts[%d]  %d, %d, %d",
1551                     path, load_count[path][0], load_count[path][1],
1552                     load_count[path][2]);
1553         if (load_count[path][0] == 1)
1554                 return FW_MSG_CODE_DRV_LOAD_COMMON;
1555         else if (load_count[path][1 + port] == 1)
1556                 return FW_MSG_CODE_DRV_LOAD_PORT;
1557         else
1558                 return FW_MSG_CODE_DRV_LOAD_FUNCTION;
1559 }
1560
1561 /* returns the "mcp load_code" according to global load_count array */
1562 static int bnx2x_nic_unload_no_mcp(struct bnx2x_softc *sc)
1563 {
1564         int port = SC_PORT(sc);
1565         int path = SC_PATH(sc);
1566
1567         PMD_DRV_LOG(INFO, "NO MCP - load counts[%d]      %d, %d, %d",
1568                     path, load_count[path][0], load_count[path][1],
1569                     load_count[path][2]);
1570         load_count[path][0]--;
1571         load_count[path][1 + port]--;
1572         PMD_DRV_LOG(INFO, "NO MCP - new load counts[%d]  %d, %d, %d",
1573                     path, load_count[path][0], load_count[path][1],
1574                     load_count[path][2]);
1575         if (load_count[path][0] == 0) {
1576                 return FW_MSG_CODE_DRV_UNLOAD_COMMON;
1577         } else if (load_count[path][1 + port] == 0) {
1578                 return FW_MSG_CODE_DRV_UNLOAD_PORT;
1579         } else {
1580                 return FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
1581         }
1582 }
1583
1584 /* request unload mode from the MCP: COMMON, PORT or FUNCTION */
1585 static uint32_t bnx2x_send_unload_req(struct bnx2x_softc *sc, int unload_mode)
1586 {
1587         uint32_t reset_code = 0;
1588
1589         /* Select the UNLOAD request mode */
1590         if (unload_mode == UNLOAD_NORMAL) {
1591                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1592         } else {
1593                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1594         }
1595
1596         /* Send the request to the MCP */
1597         if (!BNX2X_NOMCP(sc)) {
1598                 reset_code = bnx2x_fw_command(sc, reset_code, 0);
1599         } else {
1600                 reset_code = bnx2x_nic_unload_no_mcp(sc);
1601         }
1602
1603         return reset_code;
1604 }
1605
1606 /* send UNLOAD_DONE command to the MCP */
1607 static void bnx2x_send_unload_done(struct bnx2x_softc *sc, uint8_t keep_link)
1608 {
1609         uint32_t reset_param =
1610             keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
1611
1612         /* Report UNLOAD_DONE to MCP */
1613         if (!BNX2X_NOMCP(sc)) {
1614                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
1615         }
1616 }
1617
1618 static int bnx2x_func_wait_started(struct bnx2x_softc *sc)
1619 {
1620         int tout = 50;
1621
1622         if (!sc->port.pmf) {
1623                 return 0;
1624         }
1625
1626         /*
1627          * (assumption: No Attention from MCP at this stage)
1628          * PMF probably in the middle of TX disable/enable transaction
1629          * 1. Sync IRS for default SB
1630          * 2. Sync SP queue - this guarantees us that attention handling started
1631          * 3. Wait, that TX disable/enable transaction completes
1632          *
1633          * 1+2 guarantee that if DCBX attention was scheduled it already changed
1634          * pending bit of transaction from STARTED-->TX_STOPPED, if we already
1635          * received completion for the transaction the state is TX_STOPPED.
1636          * State will return to STARTED after completion of TX_STOPPED-->STARTED
1637          * transaction.
1638          */
1639
1640         while (ecore_func_get_state(sc, &sc->func_obj) !=
1641                ECORE_F_STATE_STARTED && tout--) {
1642                 DELAY(20000);
1643         }
1644
1645         if (ecore_func_get_state(sc, &sc->func_obj) != ECORE_F_STATE_STARTED) {
1646                 /*
1647                  * Failed to complete the transaction in a "good way"
1648                  * Force both transactions with CLR bit.
1649                  */
1650                 struct ecore_func_state_params func_params = { NULL };
1651
1652                 PMD_DRV_LOG(NOTICE, "Unexpected function state! "
1653                             "Forcing STARTED-->TX_STOPPED-->STARTED");
1654
1655                 func_params.f_obj = &sc->func_obj;
1656                 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1657
1658                 /* STARTED-->TX_STOPPED */
1659                 func_params.cmd = ECORE_F_CMD_TX_STOP;
1660                 ecore_func_state_change(sc, &func_params);
1661
1662                 /* TX_STOPPED-->STARTED */
1663                 func_params.cmd = ECORE_F_CMD_TX_START;
1664                 return ecore_func_state_change(sc, &func_params);
1665         }
1666
1667         return 0;
1668 }
1669
1670 static int bnx2x_stop_queue(struct bnx2x_softc *sc, int index)
1671 {
1672         struct bnx2x_fastpath *fp = &sc->fp[index];
1673         struct ecore_queue_state_params q_params = { NULL };
1674         int rc;
1675
1676         PMD_DRV_LOG(DEBUG, "stopping queue %d cid %d", index, fp->index);
1677
1678         q_params.q_obj = &sc->sp_objs[fp->index].q_obj;
1679         /* We want to wait for completion in this context */
1680         bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
1681
1682         /* Stop the primary connection: */
1683
1684         /* ...halt the connection */
1685         q_params.cmd = ECORE_Q_CMD_HALT;
1686         rc = ecore_queue_state_change(sc, &q_params);
1687         if (rc) {
1688                 return rc;
1689         }
1690
1691         /* ...terminate the connection */
1692         q_params.cmd = ECORE_Q_CMD_TERMINATE;
1693         memset(&q_params.params.terminate, 0,
1694                sizeof(q_params.params.terminate));
1695         q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
1696         rc = ecore_queue_state_change(sc, &q_params);
1697         if (rc) {
1698                 return rc;
1699         }
1700
1701         /* ...delete cfc entry */
1702         q_params.cmd = ECORE_Q_CMD_CFC_DEL;
1703         memset(&q_params.params.cfc_del, 0, sizeof(q_params.params.cfc_del));
1704         q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
1705         return ecore_queue_state_change(sc, &q_params);
1706 }
1707
1708 /* wait for the outstanding SP commands */
1709 static uint8_t bnx2x_wait_sp_comp(struct bnx2x_softc *sc, unsigned long mask)
1710 {
1711         unsigned long tmp;
1712         int tout = 5000;        /* wait for 5 secs tops */
1713
1714         while (tout--) {
1715                 mb();
1716                 if (!(atomic_load_acq_long(&sc->sp_state) & mask)) {
1717                         return TRUE;
1718                 }
1719
1720                 DELAY(1000);
1721         }
1722
1723         mb();
1724
1725         tmp = atomic_load_acq_long(&sc->sp_state);
1726         if (tmp & mask) {
1727                 PMD_DRV_LOG(INFO, "Filtering completion timed out: "
1728                             "sp_state 0x%lx, mask 0x%lx", tmp, mask);
1729                 return FALSE;
1730         }
1731
1732         return FALSE;
1733 }
1734
1735 static int bnx2x_func_stop(struct bnx2x_softc *sc)
1736 {
1737         struct ecore_func_state_params func_params = { NULL };
1738         int rc;
1739
1740         /* prepare parameters for function state transitions */
1741         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1742         func_params.f_obj = &sc->func_obj;
1743         func_params.cmd = ECORE_F_CMD_STOP;
1744
1745         /*
1746          * Try to stop the function the 'good way'. If it fails (in case
1747          * of a parity error during bnx2x_chip_cleanup()) and we are
1748          * not in a debug mode, perform a state transaction in order to
1749          * enable further HW_RESET transaction.
1750          */
1751         rc = ecore_func_state_change(sc, &func_params);
1752         if (rc) {
1753                 PMD_DRV_LOG(NOTICE, "FUNC_STOP ramrod failed. "
1754                             "Running a dry transaction");
1755                 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1756                 return ecore_func_state_change(sc, &func_params);
1757         }
1758
1759         return 0;
1760 }
1761
1762 static int bnx2x_reset_hw(struct bnx2x_softc *sc, uint32_t load_code)
1763 {
1764         struct ecore_func_state_params func_params = { NULL };
1765
1766         /* Prepare parameters for function state transitions */
1767         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1768
1769         func_params.f_obj = &sc->func_obj;
1770         func_params.cmd = ECORE_F_CMD_HW_RESET;
1771
1772         func_params.params.hw_init.load_phase = load_code;
1773
1774         return ecore_func_state_change(sc, &func_params);
1775 }
1776
1777 static void bnx2x_int_disable_sync(struct bnx2x_softc *sc, int disable_hw)
1778 {
1779         if (disable_hw) {
1780                 /* prevent the HW from sending interrupts */
1781                 bnx2x_int_disable(sc);
1782         }
1783 }
1784
1785 static void
1786 bnx2x_chip_cleanup(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1787 {
1788         int port = SC_PORT(sc);
1789         struct ecore_mcast_ramrod_params rparam = { NULL };
1790         uint32_t reset_code;
1791         int i, rc = 0;
1792
1793         bnx2x_drain_tx_queues(sc);
1794
1795         /* give HW time to discard old tx messages */
1796         DELAY(1000);
1797
1798         /* Clean all ETH MACs */
1799         rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_ETH_MAC,
1800                               FALSE);
1801         if (rc < 0) {
1802                 PMD_DRV_LOG(NOTICE, "Failed to delete all ETH MACs (%d)", rc);
1803         }
1804
1805         /* Clean up UC list  */
1806         rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_UC_LIST_MAC,
1807                               TRUE);
1808         if (rc < 0) {
1809                 PMD_DRV_LOG(NOTICE, "Failed to delete UC MACs list (%d)", rc);
1810         }
1811
1812         /* Disable LLH */
1813         REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
1814
1815         /* Set "drop all" to stop Rx */
1816
1817         /*
1818          * We need to take the if_maddr_lock() here in order to prevent
1819          * a race between the completion code and this code.
1820          */
1821
1822         if (bnx2x_test_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) {
1823                 bnx2x_set_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state);
1824         } else {
1825                 bnx2x_set_storm_rx_mode(sc);
1826         }
1827
1828         /* Clean up multicast configuration */
1829         rparam.mcast_obj = &sc->mcast_obj;
1830         rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1831         if (rc < 0) {
1832                 PMD_DRV_LOG(NOTICE,
1833                             "Failed to send DEL MCAST command (%d)", rc);
1834         }
1835
1836         /*
1837          * Send the UNLOAD_REQUEST to the MCP. This will return if
1838          * this function should perform FUNCTION, PORT, or COMMON HW
1839          * reset.
1840          */
1841         reset_code = bnx2x_send_unload_req(sc, unload_mode);
1842
1843         /*
1844          * (assumption: No Attention from MCP at this stage)
1845          * PMF probably in the middle of TX disable/enable transaction
1846          */
1847         rc = bnx2x_func_wait_started(sc);
1848         if (rc) {
1849                 PMD_DRV_LOG(NOTICE, "bnx2x_func_wait_started failed");
1850         }
1851
1852         /*
1853          * Close multi and leading connections
1854          * Completions for ramrods are collected in a synchronous way
1855          */
1856         for (i = 0; i < sc->num_queues; i++) {
1857                 if (bnx2x_stop_queue(sc, i)) {
1858                         goto unload_error;
1859                 }
1860         }
1861
1862         /*
1863          * If SP settings didn't get completed so far - something
1864          * very wrong has happen.
1865          */
1866         if (!bnx2x_wait_sp_comp(sc, ~0x0UL)) {
1867                 PMD_DRV_LOG(NOTICE, "Common slow path ramrods got stuck!");
1868         }
1869
1870 unload_error:
1871
1872         rc = bnx2x_func_stop(sc);
1873         if (rc) {
1874                 PMD_DRV_LOG(NOTICE, "Function stop failed!");
1875         }
1876
1877         /* disable HW interrupts */
1878         bnx2x_int_disable_sync(sc, TRUE);
1879
1880         /* Reset the chip */
1881         rc = bnx2x_reset_hw(sc, reset_code);
1882         if (rc) {
1883                 PMD_DRV_LOG(NOTICE, "Hardware reset failed");
1884         }
1885
1886         /* Report UNLOAD_DONE to MCP */
1887         bnx2x_send_unload_done(sc, keep_link);
1888 }
1889
1890 static void bnx2x_disable_close_the_gate(struct bnx2x_softc *sc)
1891 {
1892         uint32_t val;
1893
1894         PMD_DRV_LOG(DEBUG, "Disabling 'close the gates'");
1895
1896         val = REG_RD(sc, MISC_REG_AEU_GENERAL_MASK);
1897         val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
1898                  MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
1899         REG_WR(sc, MISC_REG_AEU_GENERAL_MASK, val);
1900 }
1901
1902 /*
1903  * Cleans the object that have internal lists without sending
1904  * ramrods. Should be run when interrutps are disabled.
1905  */
1906 static void bnx2x_squeeze_objects(struct bnx2x_softc *sc)
1907 {
1908         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1909         struct ecore_mcast_ramrod_params rparam = { NULL };
1910         struct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj;
1911         int rc;
1912
1913         /* Cleanup MACs' object first... */
1914
1915         /* Wait for completion of requested */
1916         bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1917         /* Perform a dry cleanup */
1918         bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &ramrod_flags);
1919
1920         /* Clean ETH primary MAC */
1921         bnx2x_set_bit(ECORE_ETH_MAC, &vlan_mac_flags);
1922         rc = mac_obj->delete_all(sc, &sc->sp_objs->mac_obj, &vlan_mac_flags,
1923                                  &ramrod_flags);
1924         if (rc != 0) {
1925                 PMD_DRV_LOG(NOTICE, "Failed to clean ETH MACs (%d)", rc);
1926         }
1927
1928         /* Cleanup UC list */
1929         vlan_mac_flags = 0;
1930         bnx2x_set_bit(ECORE_UC_LIST_MAC, &vlan_mac_flags);
1931         rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1932         if (rc != 0) {
1933                 PMD_DRV_LOG(NOTICE, "Failed to clean UC list MACs (%d)", rc);
1934         }
1935
1936         /* Now clean mcast object... */
1937
1938         rparam.mcast_obj = &sc->mcast_obj;
1939         bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags);
1940
1941         /* Add a DEL command... */
1942         rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1943         if (rc < 0) {
1944                 PMD_DRV_LOG(NOTICE,
1945                             "Failed to send DEL MCAST command (%d)", rc);
1946         }
1947
1948         /* now wait until all pending commands are cleared */
1949
1950         rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
1951         while (rc != 0) {
1952                 if (rc < 0) {
1953                         PMD_DRV_LOG(NOTICE,
1954                                     "Failed to clean MCAST object (%d)", rc);
1955                         return;
1956                 }
1957
1958                 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
1959         }
1960 }
1961
1962 /* stop the controller */
1963 __attribute__ ((noinline))
1964 int
1965 bnx2x_nic_unload(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1966 {
1967         uint8_t global = FALSE;
1968         uint32_t val;
1969
1970         PMD_DRV_LOG(DEBUG, "Starting NIC unload...");
1971
1972         /* stop the periodic callout */
1973         bnx2x_periodic_stop(sc);
1974
1975         /* mark driver as unloaded in shmem2 */
1976         if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
1977                 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
1978                 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
1979                           val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
1980         }
1981
1982         if (IS_PF(sc) && sc->recovery_state != BNX2X_RECOVERY_DONE &&
1983             (sc->state == BNX2X_STATE_CLOSED || sc->state == BNX2X_STATE_ERROR)) {
1984                 /*
1985                  * We can get here if the driver has been unloaded
1986                  * during parity error recovery and is either waiting for a
1987                  * leader to complete or for other functions to unload and
1988                  * then ifconfig down has been issued. In this case we want to
1989                  * unload and let other functions to complete a recovery
1990                  * process.
1991                  */
1992                 sc->recovery_state = BNX2X_RECOVERY_DONE;
1993                 sc->is_leader = 0;
1994                 bnx2x_release_leader_lock(sc);
1995                 mb();
1996
1997                 PMD_DRV_LOG(NOTICE, "Can't unload in closed or error state");
1998                 return -1;
1999         }
2000
2001         /*
2002          * Nothing to do during unload if previous bnx2x_nic_load()
2003          * did not completed succesfully - all resourses are released.
2004          */
2005         if ((sc->state == BNX2X_STATE_CLOSED) || (sc->state == BNX2X_STATE_ERROR)) {
2006                 return 0;
2007         }
2008
2009         sc->state = BNX2X_STATE_CLOSING_WAITING_HALT;
2010         mb();
2011
2012         sc->rx_mode = BNX2X_RX_MODE_NONE;
2013         bnx2x_set_rx_mode(sc);
2014         mb();
2015
2016         if (IS_PF(sc)) {
2017                 /* set ALWAYS_ALIVE bit in shmem */
2018                 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2019
2020                 bnx2x_drv_pulse(sc);
2021
2022                 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2023                 bnx2x_save_statistics(sc);
2024         }
2025
2026         /* wait till consumers catch up with producers in all queues */
2027         bnx2x_drain_tx_queues(sc);
2028
2029         /* if VF indicate to PF this function is going down (PF will delete sp
2030          * elements and clear initializations
2031          */
2032         if (IS_VF(sc)) {
2033                 bnx2x_vf_unload(sc);
2034         } else if (unload_mode != UNLOAD_RECOVERY) {
2035                 /* if this is a normal/close unload need to clean up chip */
2036                 bnx2x_chip_cleanup(sc, unload_mode, keep_link);
2037         } else {
2038                 /* Send the UNLOAD_REQUEST to the MCP */
2039                 bnx2x_send_unload_req(sc, unload_mode);
2040
2041                 /*
2042                  * Prevent transactions to host from the functions on the
2043                  * engine that doesn't reset global blocks in case of global
2044                  * attention once gloabl blocks are reset and gates are opened
2045                  * (the engine which leader will perform the recovery
2046                  * last).
2047                  */
2048                 if (!CHIP_IS_E1x(sc)) {
2049                         bnx2x_pf_disable(sc);
2050                 }
2051
2052                 /* disable HW interrupts */
2053                 bnx2x_int_disable_sync(sc, TRUE);
2054
2055                 /* Report UNLOAD_DONE to MCP */
2056                 bnx2x_send_unload_done(sc, FALSE);
2057         }
2058
2059         /*
2060          * At this stage no more interrupts will arrive so we may safely clean
2061          * the queue'able objects here in case they failed to get cleaned so far.
2062          */
2063         if (IS_PF(sc)) {
2064                 bnx2x_squeeze_objects(sc);
2065         }
2066
2067         /* There should be no more pending SP commands at this stage */
2068         sc->sp_state = 0;
2069
2070         sc->port.pmf = 0;
2071
2072         if (IS_PF(sc)) {
2073                 bnx2x_free_mem(sc);
2074         }
2075
2076         bnx2x_free_fw_stats_mem(sc);
2077
2078         sc->state = BNX2X_STATE_CLOSED;
2079
2080         /*
2081          * Check if there are pending parity attentions. If there are - set
2082          * RECOVERY_IN_PROGRESS.
2083          */
2084         if (IS_PF(sc) && bnx2x_chk_parity_attn(sc, &global, FALSE)) {
2085                 bnx2x_set_reset_in_progress(sc);
2086
2087                 /* Set RESET_IS_GLOBAL if needed */
2088                 if (global) {
2089                         bnx2x_set_reset_global(sc);
2090                 }
2091         }
2092
2093         /*
2094          * The last driver must disable a "close the gate" if there is no
2095          * parity attention or "process kill" pending.
2096          */
2097         if (IS_PF(sc) && !bnx2x_clear_pf_load(sc) &&
2098             bnx2x_reset_is_done(sc, SC_PATH(sc))) {
2099                 bnx2x_disable_close_the_gate(sc);
2100         }
2101
2102         PMD_DRV_LOG(DEBUG, "Ended NIC unload");
2103
2104         return 0;
2105 }
2106
2107 /*
2108  * Encapsulte an mbuf cluster into the tx bd chain and makes the memory
2109  * visible to the controller.
2110  *
2111  * If an mbuf is submitted to this routine and cannot be given to the
2112  * controller (e.g. it has too many fragments) then the function may free
2113  * the mbuf and return to the caller.
2114  *
2115  * Returns:
2116  *   0 = Success, !0 = Failure
2117  *   Note the side effect that an mbuf may be freed if it causes a problem.
2118  */
2119 int bnx2x_tx_encap(struct bnx2x_tx_queue *txq, struct rte_mbuf **m_head, int m_pkts)
2120 {
2121         struct rte_mbuf *m0;
2122         struct eth_tx_start_bd *tx_start_bd;
2123         uint16_t bd_prod, pkt_prod;
2124         int m_tx;
2125         struct bnx2x_softc *sc;
2126         uint32_t nbds = 0;
2127         struct bnx2x_fastpath *fp;
2128
2129         sc = txq->sc;
2130         fp = &sc->fp[txq->queue_id];
2131
2132         bd_prod = txq->tx_bd_tail;
2133         pkt_prod = txq->tx_pkt_tail;
2134
2135         for (m_tx = 0; m_tx < m_pkts; m_tx++) {
2136
2137                 m0 = *m_head++;
2138
2139                 if (unlikely(txq->nb_tx_avail < 3)) {
2140                         PMD_TX_LOG(ERR, "no enough bds %d/%d",
2141                                    bd_prod, txq->nb_tx_avail);
2142                         return -ENOMEM;
2143                 }
2144
2145                 txq->sw_ring[TX_BD(pkt_prod, txq)] = m0;
2146
2147                 tx_start_bd = &txq->tx_ring[TX_BD(bd_prod, txq)].start_bd;
2148
2149                 tx_start_bd->addr =
2150                     rte_cpu_to_le_64(rte_mbuf_data_dma_addr(m0));
2151                 tx_start_bd->nbytes = rte_cpu_to_le_16(m0->data_len);
2152                 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2153                 tx_start_bd->general_data =
2154                     (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
2155
2156                 tx_start_bd->nbd = rte_cpu_to_le_16(2);
2157
2158                 if (m0->ol_flags & PKT_TX_VLAN_PKT) {
2159                         tx_start_bd->vlan_or_ethertype =
2160                             rte_cpu_to_le_16(m0->vlan_tci);
2161                         tx_start_bd->bd_flags.as_bitfield |=
2162                             (X_ETH_OUTBAND_VLAN <<
2163                              ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT);
2164                 } else {
2165                         if (IS_PF(sc))
2166                                 tx_start_bd->vlan_or_ethertype =
2167                                     rte_cpu_to_le_16(pkt_prod);
2168                         else {
2169                                 struct ether_hdr *eh
2170                                     = rte_pktmbuf_mtod(m0, struct ether_hdr *);
2171
2172                                 tx_start_bd->vlan_or_ethertype
2173                                     = rte_cpu_to_le_16(rte_be_to_cpu_16(eh->ether_type));
2174                         }
2175                 }
2176
2177                 bd_prod = NEXT_TX_BD(bd_prod);
2178                 if (IS_VF(sc)) {
2179                         struct eth_tx_parse_bd_e2 *tx_parse_bd;
2180                         const struct ether_hdr *eh = rte_pktmbuf_mtod(m0, struct ether_hdr *);
2181                         uint8_t mac_type = UNICAST_ADDRESS;
2182
2183                         tx_parse_bd =
2184                             &txq->tx_ring[TX_BD(bd_prod, txq)].parse_bd_e2;
2185                         if (is_multicast_ether_addr(&eh->d_addr)) {
2186                                 if (is_broadcast_ether_addr(&eh->d_addr))
2187                                         mac_type = BROADCAST_ADDRESS;
2188                                 else
2189                                         mac_type = MULTICAST_ADDRESS;
2190                         }
2191                         tx_parse_bd->parsing_data =
2192                             (mac_type << ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT);
2193
2194                         rte_memcpy(&tx_parse_bd->data.mac_addr.dst_hi,
2195                                    &eh->d_addr.addr_bytes[0], 2);
2196                         rte_memcpy(&tx_parse_bd->data.mac_addr.dst_mid,
2197                                    &eh->d_addr.addr_bytes[2], 2);
2198                         rte_memcpy(&tx_parse_bd->data.mac_addr.dst_lo,
2199                                    &eh->d_addr.addr_bytes[4], 2);
2200                         rte_memcpy(&tx_parse_bd->data.mac_addr.src_hi,
2201                                    &eh->s_addr.addr_bytes[0], 2);
2202                         rte_memcpy(&tx_parse_bd->data.mac_addr.src_mid,
2203                                    &eh->s_addr.addr_bytes[2], 2);
2204                         rte_memcpy(&tx_parse_bd->data.mac_addr.src_lo,
2205                                    &eh->s_addr.addr_bytes[4], 2);
2206
2207                         tx_parse_bd->data.mac_addr.dst_hi =
2208                             rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_hi);
2209                         tx_parse_bd->data.mac_addr.dst_mid =
2210                             rte_cpu_to_be_16(tx_parse_bd->data.
2211                                              mac_addr.dst_mid);
2212                         tx_parse_bd->data.mac_addr.dst_lo =
2213                             rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_lo);
2214                         tx_parse_bd->data.mac_addr.src_hi =
2215                             rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_hi);
2216                         tx_parse_bd->data.mac_addr.src_mid =
2217                             rte_cpu_to_be_16(tx_parse_bd->data.
2218                                              mac_addr.src_mid);
2219                         tx_parse_bd->data.mac_addr.src_lo =
2220                             rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_lo);
2221
2222                         PMD_TX_LOG(DEBUG,
2223                                    "PBD dst %x %x %x src %x %x %x p_data %x",
2224                                    tx_parse_bd->data.mac_addr.dst_hi,
2225                                    tx_parse_bd->data.mac_addr.dst_mid,
2226                                    tx_parse_bd->data.mac_addr.dst_lo,
2227                                    tx_parse_bd->data.mac_addr.src_hi,
2228                                    tx_parse_bd->data.mac_addr.src_mid,
2229                                    tx_parse_bd->data.mac_addr.src_lo,
2230                                    tx_parse_bd->parsing_data);
2231                 }
2232
2233                 PMD_TX_LOG(DEBUG,
2234                            "start bd: nbytes %d flags %x vlan %x\n",
2235                            tx_start_bd->nbytes,
2236                            tx_start_bd->bd_flags.as_bitfield,
2237                            tx_start_bd->vlan_or_ethertype);
2238
2239                 bd_prod = NEXT_TX_BD(bd_prod);
2240                 pkt_prod++;
2241
2242                 if (TX_IDX(bd_prod) < 2) {
2243                         nbds++;
2244                 }
2245         }
2246
2247         txq->nb_tx_avail -= m_pkts << 1;
2248         txq->tx_bd_tail = bd_prod;
2249         txq->tx_pkt_tail = pkt_prod;
2250
2251         mb();
2252         fp->tx_db.data.prod += (m_pkts << 1) + nbds;
2253         DOORBELL(sc, txq->queue_id, fp->tx_db.raw);
2254         mb();
2255
2256         return 0;
2257 }
2258
2259 static uint16_t bnx2x_cid_ilt_lines(struct bnx2x_softc *sc)
2260 {
2261         return L2_ILT_LINES(sc);
2262 }
2263
2264 static void bnx2x_ilt_set_info(struct bnx2x_softc *sc)
2265 {
2266         struct ilt_client_info *ilt_client;
2267         struct ecore_ilt *ilt = sc->ilt;
2268         uint16_t line = 0;
2269
2270         PMD_INIT_FUNC_TRACE();
2271
2272         ilt->start_line = FUNC_ILT_BASE(SC_FUNC(sc));
2273
2274         /* CDU */
2275         ilt_client = &ilt->clients[ILT_CLIENT_CDU];
2276         ilt_client->client_num = ILT_CLIENT_CDU;
2277         ilt_client->page_size = CDU_ILT_PAGE_SZ;
2278         ilt_client->flags = ILT_CLIENT_SKIP_MEM;
2279         ilt_client->start = line;
2280         line += bnx2x_cid_ilt_lines(sc);
2281
2282         if (CNIC_SUPPORT(sc)) {
2283                 line += CNIC_ILT_LINES;
2284         }
2285
2286         ilt_client->end = (line - 1);
2287
2288         /* QM */
2289         if (QM_INIT(sc->qm_cid_count)) {
2290                 ilt_client = &ilt->clients[ILT_CLIENT_QM];
2291                 ilt_client->client_num = ILT_CLIENT_QM;
2292                 ilt_client->page_size = QM_ILT_PAGE_SZ;
2293                 ilt_client->flags = 0;
2294                 ilt_client->start = line;
2295
2296                 /* 4 bytes for each cid */
2297                 line += DIV_ROUND_UP(sc->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
2298                                      QM_ILT_PAGE_SZ);
2299
2300                 ilt_client->end = (line - 1);
2301         }
2302
2303         if (CNIC_SUPPORT(sc)) {
2304                 /* SRC */
2305                 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
2306                 ilt_client->client_num = ILT_CLIENT_SRC;
2307                 ilt_client->page_size = SRC_ILT_PAGE_SZ;
2308                 ilt_client->flags = 0;
2309                 ilt_client->start = line;
2310                 line += SRC_ILT_LINES;
2311                 ilt_client->end = (line - 1);
2312
2313                 /* TM */
2314                 ilt_client = &ilt->clients[ILT_CLIENT_TM];
2315                 ilt_client->client_num = ILT_CLIENT_TM;
2316                 ilt_client->page_size = TM_ILT_PAGE_SZ;
2317                 ilt_client->flags = 0;
2318                 ilt_client->start = line;
2319                 line += TM_ILT_LINES;
2320                 ilt_client->end = (line - 1);
2321         }
2322
2323         assert((line <= ILT_MAX_LINES));
2324 }
2325
2326 static void bnx2x_set_fp_rx_buf_size(struct bnx2x_softc *sc)
2327 {
2328         int i;
2329
2330         for (i = 0; i < sc->num_queues; i++) {
2331                 /* get the Rx buffer size for RX frames */
2332                 sc->fp[i].rx_buf_size =
2333                     (IP_HEADER_ALIGNMENT_PADDING + ETH_OVERHEAD + sc->mtu);
2334         }
2335 }
2336
2337 int bnx2x_alloc_ilt_mem(struct bnx2x_softc *sc)
2338 {
2339
2340         sc->ilt = rte_malloc("", sizeof(struct ecore_ilt), RTE_CACHE_LINE_SIZE);
2341
2342         return sc->ilt == NULL;
2343 }
2344
2345 static int bnx2x_alloc_ilt_lines_mem(struct bnx2x_softc *sc)
2346 {
2347         sc->ilt->lines = rte_calloc("",
2348                                     sizeof(struct ilt_line), ILT_MAX_LINES,
2349                                     RTE_CACHE_LINE_SIZE);
2350         return sc->ilt->lines == NULL;
2351 }
2352
2353 void bnx2x_free_ilt_mem(struct bnx2x_softc *sc)
2354 {
2355         rte_free(sc->ilt);
2356         sc->ilt = NULL;
2357 }
2358
2359 static void bnx2x_free_ilt_lines_mem(struct bnx2x_softc *sc)
2360 {
2361         if (sc->ilt->lines != NULL) {
2362                 rte_free(sc->ilt->lines);
2363                 sc->ilt->lines = NULL;
2364         }
2365 }
2366
2367 static void bnx2x_free_mem(struct bnx2x_softc *sc)
2368 {
2369         uint32_t i;
2370
2371         for (i = 0; i < L2_ILT_LINES(sc); i++) {
2372                 sc->context[i].vcxt = NULL;
2373                 sc->context[i].size = 0;
2374         }
2375
2376         ecore_ilt_mem_op(sc, ILT_MEMOP_FREE);
2377
2378         bnx2x_free_ilt_lines_mem(sc);
2379 }
2380
2381 static int bnx2x_alloc_mem(struct bnx2x_softc *sc)
2382 {
2383         int context_size;
2384         int allocated;
2385         int i;
2386         char cdu_name[RTE_MEMZONE_NAMESIZE];
2387
2388         /*
2389          * Allocate memory for CDU context:
2390          * This memory is allocated separately and not in the generic ILT
2391          * functions because CDU differs in few aspects:
2392          * 1. There can be multiple entities allocating memory for context -
2393          * regular L2, CNIC, and SRIOV drivers. Each separately controls
2394          * its own ILT lines.
2395          * 2. Since CDU page-size is not a single 4KB page (which is the case
2396          * for the other ILT clients), to be efficient we want to support
2397          * allocation of sub-page-size in the last entry.
2398          * 3. Context pointers are used by the driver to pass to FW / update
2399          * the context (for the other ILT clients the pointers are used just to
2400          * free the memory during unload).
2401          */
2402         context_size = (sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(sc));
2403         for (i = 0, allocated = 0; allocated < context_size; i++) {
2404                 sc->context[i].size = min(CDU_ILT_PAGE_SZ,
2405                                           (context_size - allocated));
2406
2407                 snprintf(cdu_name, sizeof(cdu_name), "cdu_%d", i);
2408                 if (bnx2x_dma_alloc(sc, sc->context[i].size,
2409                                   &sc->context[i].vcxt_dma,
2410                                   cdu_name, BNX2X_PAGE_SIZE) != 0) {
2411                         bnx2x_free_mem(sc);
2412                         return -1;
2413                 }
2414
2415                 sc->context[i].vcxt =
2416                     (union cdu_context *)sc->context[i].vcxt_dma.vaddr;
2417
2418                 allocated += sc->context[i].size;
2419         }
2420
2421         bnx2x_alloc_ilt_lines_mem(sc);
2422
2423         if (ecore_ilt_mem_op(sc, ILT_MEMOP_ALLOC)) {
2424                 PMD_DRV_LOG(NOTICE, "ecore_ilt_mem_op ILT_MEMOP_ALLOC failed");
2425                 bnx2x_free_mem(sc);
2426                 return -1;
2427         }
2428
2429         return 0;
2430 }
2431
2432 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc)
2433 {
2434         sc->fw_stats_num = 0;
2435
2436         sc->fw_stats_req_size = 0;
2437         sc->fw_stats_req = NULL;
2438         sc->fw_stats_req_mapping = 0;
2439
2440         sc->fw_stats_data_size = 0;
2441         sc->fw_stats_data = NULL;
2442         sc->fw_stats_data_mapping = 0;
2443 }
2444
2445 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc)
2446 {
2447         uint8_t num_queue_stats;
2448         int num_groups, vf_headroom = 0;
2449
2450         /* number of queues for statistics is number of eth queues */
2451         num_queue_stats = BNX2X_NUM_ETH_QUEUES(sc);
2452
2453         /*
2454          * Total number of FW statistics requests =
2455          *   1 for port stats + 1 for PF stats + num of queues
2456          */
2457         sc->fw_stats_num = (2 + num_queue_stats);
2458
2459         /*
2460          * Request is built from stats_query_header and an array of
2461          * stats_query_cmd_group each of which contains STATS_QUERY_CMD_COUNT
2462          * rules. The real number or requests is configured in the
2463          * stats_query_header.
2464          */
2465         num_groups = (sc->fw_stats_num + vf_headroom) / STATS_QUERY_CMD_COUNT;
2466         if ((sc->fw_stats_num + vf_headroom) % STATS_QUERY_CMD_COUNT)
2467                 num_groups++;
2468
2469         sc->fw_stats_req_size =
2470             (sizeof(struct stats_query_header) +
2471              (num_groups * sizeof(struct stats_query_cmd_group)));
2472
2473         /*
2474          * Data for statistics requests + stats_counter.
2475          * stats_counter holds per-STORM counters that are incremented when
2476          * STORM has finished with the current request. Memory for FCoE
2477          * offloaded statistics are counted anyway, even if they will not be sent.
2478          * VF stats are not accounted for here as the data of VF stats is stored
2479          * in memory allocated by the VF, not here.
2480          */
2481         sc->fw_stats_data_size =
2482             (sizeof(struct stats_counter) +
2483              sizeof(struct per_port_stats) + sizeof(struct per_pf_stats) +
2484              /* sizeof(struct fcoe_statistics_params) + */
2485              (sizeof(struct per_queue_stats) * num_queue_stats));
2486
2487         if (bnx2x_dma_alloc(sc, (sc->fw_stats_req_size + sc->fw_stats_data_size),
2488                           &sc->fw_stats_dma, "fw_stats",
2489                           RTE_CACHE_LINE_SIZE) != 0) {
2490                 bnx2x_free_fw_stats_mem(sc);
2491                 return -1;
2492         }
2493
2494         /* set up the shortcuts */
2495
2496         sc->fw_stats_req = (struct bnx2x_fw_stats_req *)sc->fw_stats_dma.vaddr;
2497         sc->fw_stats_req_mapping = sc->fw_stats_dma.paddr;
2498
2499         sc->fw_stats_data =
2500             (struct bnx2x_fw_stats_data *)((uint8_t *) sc->fw_stats_dma.vaddr +
2501                                          sc->fw_stats_req_size);
2502         sc->fw_stats_data_mapping = (sc->fw_stats_dma.paddr +
2503                                      sc->fw_stats_req_size);
2504
2505         return 0;
2506 }
2507
2508 /*
2509  * Bits map:
2510  * 0-7  - Engine0 load counter.
2511  * 8-15 - Engine1 load counter.
2512  * 16   - Engine0 RESET_IN_PROGRESS bit.
2513  * 17   - Engine1 RESET_IN_PROGRESS bit.
2514  * 18   - Engine0 ONE_IS_LOADED. Set when there is at least one active
2515  *        function on the engine
2516  * 19   - Engine1 ONE_IS_LOADED.
2517  * 20   - Chip reset flow bit. When set none-leader must wait for both engines
2518  *        leader to complete (check for both RESET_IN_PROGRESS bits and not
2519  *        for just the one belonging to its engine).
2520  */
2521 #define BNX2X_RECOVERY_GLOB_REG     MISC_REG_GENERIC_POR_1
2522 #define BNX2X_PATH0_LOAD_CNT_MASK   0x000000ff
2523 #define BNX2X_PATH0_LOAD_CNT_SHIFT  0
2524 #define BNX2X_PATH1_LOAD_CNT_MASK   0x0000ff00
2525 #define BNX2X_PATH1_LOAD_CNT_SHIFT  8
2526 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
2527 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
2528 #define BNX2X_GLOBAL_RESET_BIT      0x00040000
2529
2530 /* set the GLOBAL_RESET bit, should be run under rtnl lock */
2531 static void bnx2x_set_reset_global(struct bnx2x_softc *sc)
2532 {
2533         uint32_t val;
2534         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2535         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2536         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
2537         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2538 }
2539
2540 /* clear the GLOBAL_RESET bit, should be run under rtnl lock */
2541 static void bnx2x_clear_reset_global(struct bnx2x_softc *sc)
2542 {
2543         uint32_t val;
2544         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2545         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2546         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
2547         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2548 }
2549
2550 /* checks the GLOBAL_RESET bit, should be run under rtnl lock */
2551 static uint8_t bnx2x_reset_is_global(struct bnx2x_softc *sc)
2552 {
2553         return REG_RD(sc, BNX2X_RECOVERY_GLOB_REG) & BNX2X_GLOBAL_RESET_BIT;
2554 }
2555
2556 /* clear RESET_IN_PROGRESS bit for the engine, should be run under rtnl lock */
2557 static void bnx2x_set_reset_done(struct bnx2x_softc *sc)
2558 {
2559         uint32_t val;
2560         uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2561             BNX2X_PATH0_RST_IN_PROG_BIT;
2562
2563         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2564
2565         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2566         /* Clear the bit */
2567         val &= ~bit;
2568         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2569
2570         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2571 }
2572
2573 /* set RESET_IN_PROGRESS for the engine, should be run under rtnl lock */
2574 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc)
2575 {
2576         uint32_t val;
2577         uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2578             BNX2X_PATH0_RST_IN_PROG_BIT;
2579
2580         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2581
2582         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2583         /* Set the bit */
2584         val |= bit;
2585         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2586
2587         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2588 }
2589
2590 /* check RESET_IN_PROGRESS bit for an engine, should be run under rtnl lock */
2591 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine)
2592 {
2593         uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2594         uint32_t bit = engine ? BNX2X_PATH1_RST_IN_PROG_BIT :
2595             BNX2X_PATH0_RST_IN_PROG_BIT;
2596
2597         /* return false if bit is set */
2598         return (val & bit) ? FALSE : TRUE;
2599 }
2600
2601 /* get the load status for an engine, should be run under rtnl lock */
2602 static uint8_t bnx2x_get_load_status(struct bnx2x_softc *sc, int engine)
2603 {
2604         uint32_t mask = engine ? BNX2X_PATH1_LOAD_CNT_MASK :
2605             BNX2X_PATH0_LOAD_CNT_MASK;
2606         uint32_t shift = engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2607             BNX2X_PATH0_LOAD_CNT_SHIFT;
2608         uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2609
2610         val = ((val & mask) >> shift);
2611
2612         return val != 0;
2613 }
2614
2615 /* set pf load mark */
2616 static void bnx2x_set_pf_load(struct bnx2x_softc *sc)
2617 {
2618         uint32_t val;
2619         uint32_t val1;
2620         uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2621             BNX2X_PATH0_LOAD_CNT_MASK;
2622         uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2623             BNX2X_PATH0_LOAD_CNT_SHIFT;
2624
2625         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2626
2627         PMD_INIT_FUNC_TRACE();
2628
2629         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2630
2631         /* get the current counter value */
2632         val1 = ((val & mask) >> shift);
2633
2634         /* set bit of this PF */
2635         val1 |= (1 << SC_ABS_FUNC(sc));
2636
2637         /* clear the old value */
2638         val &= ~mask;
2639
2640         /* set the new one */
2641         val |= ((val1 << shift) & mask);
2642
2643         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2644
2645         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2646 }
2647
2648 /* clear pf load mark */
2649 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc)
2650 {
2651         uint32_t val1, val;
2652         uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2653             BNX2X_PATH0_LOAD_CNT_MASK;
2654         uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2655             BNX2X_PATH0_LOAD_CNT_SHIFT;
2656
2657         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2658         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2659
2660         /* get the current counter value */
2661         val1 = (val & mask) >> shift;
2662
2663         /* clear bit of that PF */
2664         val1 &= ~(1 << SC_ABS_FUNC(sc));
2665
2666         /* clear the old value */
2667         val &= ~mask;
2668
2669         /* set the new one */
2670         val |= ((val1 << shift) & mask);
2671
2672         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2673         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2674         return val1 != 0;
2675 }
2676
2677 /* send load requrest to mcp and analyze response */
2678 static int bnx2x_nic_load_request(struct bnx2x_softc *sc, uint32_t * load_code)
2679 {
2680         PMD_INIT_FUNC_TRACE();
2681
2682         /* init fw_seq */
2683         sc->fw_seq =
2684             (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
2685              DRV_MSG_SEQ_NUMBER_MASK);
2686
2687         PMD_DRV_LOG(DEBUG, "initial fw_seq 0x%04x", sc->fw_seq);
2688
2689 #ifdef BNX2X_PULSE
2690         /* get the current FW pulse sequence */
2691         sc->fw_drv_pulse_wr_seq =
2692             (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb) &
2693              DRV_PULSE_SEQ_MASK);
2694 #else
2695         /* set ALWAYS_ALIVE bit in shmem */
2696         sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2697         bnx2x_drv_pulse(sc);
2698 #endif
2699
2700         /* load request */
2701         (*load_code) = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
2702                                       DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
2703
2704         /* if the MCP fails to respond we must abort */
2705         if (!(*load_code)) {
2706                 PMD_DRV_LOG(NOTICE, "MCP response failure!");
2707                 return -1;
2708         }
2709
2710         /* if MCP refused then must abort */
2711         if ((*load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED) {
2712                 PMD_DRV_LOG(NOTICE, "MCP refused load request");
2713                 return -1;
2714         }
2715
2716         return 0;
2717 }
2718
2719 /*
2720  * Check whether another PF has already loaded FW to chip. In virtualized
2721  * environments a pf from anoth VM may have already initialized the device
2722  * including loading FW.
2723  */
2724 static int bnx2x_nic_load_analyze_req(struct bnx2x_softc *sc, uint32_t load_code)
2725 {
2726         uint32_t my_fw, loaded_fw;
2727
2728         /* is another pf loaded on this engine? */
2729         if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
2730             (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
2731                 /* build my FW version dword */
2732                 my_fw = (BNX2X_5710_FW_MAJOR_VERSION +
2733                          (BNX2X_5710_FW_MINOR_VERSION << 8) +
2734                          (BNX2X_5710_FW_REVISION_VERSION << 16) +
2735                          (BNX2X_5710_FW_ENGINEERING_VERSION << 24));
2736
2737                 /* read loaded FW from chip */
2738                 loaded_fw = REG_RD(sc, XSEM_REG_PRAM);
2739                 PMD_DRV_LOG(DEBUG, "loaded FW 0x%08x / my FW 0x%08x",
2740                             loaded_fw, my_fw);
2741
2742                 /* abort nic load if version mismatch */
2743                 if (my_fw != loaded_fw) {
2744                         PMD_DRV_LOG(NOTICE,
2745                                     "FW 0x%08x already loaded (mine is 0x%08x)",
2746                                     loaded_fw, my_fw);
2747                         return -1;
2748                 }
2749         }
2750
2751         return 0;
2752 }
2753
2754 /* mark PMF if applicable */
2755 static void bnx2x_nic_load_pmf(struct bnx2x_softc *sc, uint32_t load_code)
2756 {
2757         uint32_t ncsi_oem_data_addr;
2758
2759         PMD_INIT_FUNC_TRACE();
2760
2761         if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
2762             (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
2763             (load_code == FW_MSG_CODE_DRV_LOAD_PORT)) {
2764                 /*
2765                  * Barrier here for ordering between the writing to sc->port.pmf here
2766                  * and reading it from the periodic task.
2767                  */
2768                 sc->port.pmf = 1;
2769                 mb();
2770         } else {
2771                 sc->port.pmf = 0;
2772         }
2773
2774         PMD_DRV_LOG(DEBUG, "pmf %d", sc->port.pmf);
2775
2776         if (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) {
2777                 if (SHMEM2_HAS(sc, ncsi_oem_data_addr)) {
2778                         ncsi_oem_data_addr = SHMEM2_RD(sc, ncsi_oem_data_addr);
2779                         if (ncsi_oem_data_addr) {
2780                                 REG_WR(sc,
2781                                        (ncsi_oem_data_addr +
2782                                         offsetof(struct glob_ncsi_oem_data,
2783                                                  driver_version)), 0);
2784                         }
2785                 }
2786         }
2787 }
2788
2789 static void bnx2x_read_mf_cfg(struct bnx2x_softc *sc)
2790 {
2791         int n = (CHIP_IS_MODE_4_PORT(sc) ? 2 : 1);
2792         int abs_func;
2793         int vn;
2794
2795         if (BNX2X_NOMCP(sc)) {
2796                 return;         /* what should be the default bvalue in this case */
2797         }
2798
2799         /*
2800          * The formula for computing the absolute function number is...
2801          * For 2 port configuration (4 functions per port):
2802          *   abs_func = 2 * vn + SC_PORT + SC_PATH
2803          * For 4 port configuration (2 functions per port):
2804          *   abs_func = 4 * vn + 2 * SC_PORT + SC_PATH
2805          */
2806         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
2807                 abs_func = (n * (2 * vn + SC_PORT(sc)) + SC_PATH(sc));
2808                 if (abs_func >= E1H_FUNC_MAX) {
2809                         break;
2810                 }
2811                 sc->devinfo.mf_info.mf_config[vn] =
2812                     MFCFG_RD(sc, func_mf_config[abs_func].config);
2813         }
2814
2815         if (sc->devinfo.mf_info.mf_config[SC_VN(sc)] &
2816             FUNC_MF_CFG_FUNC_DISABLED) {
2817                 PMD_DRV_LOG(DEBUG, "mf_cfg function disabled");
2818                 sc->flags |= BNX2X_MF_FUNC_DIS;
2819         } else {
2820                 PMD_DRV_LOG(DEBUG, "mf_cfg function enabled");
2821                 sc->flags &= ~BNX2X_MF_FUNC_DIS;
2822         }
2823 }
2824
2825 /* acquire split MCP access lock register */
2826 static int bnx2x_acquire_alr(struct bnx2x_softc *sc)
2827 {
2828         uint32_t j, val;
2829
2830         for (j = 0; j < 1000; j++) {
2831                 val = (1UL << 31);
2832                 REG_WR(sc, GRCBASE_MCP + 0x9c, val);
2833                 val = REG_RD(sc, GRCBASE_MCP + 0x9c);
2834                 if (val & (1L << 31))
2835                         break;
2836
2837                 DELAY(5000);
2838         }
2839
2840         if (!(val & (1L << 31))) {
2841                 PMD_DRV_LOG(NOTICE, "Cannot acquire MCP access lock register");
2842                 return -1;
2843         }
2844
2845         return 0;
2846 }
2847
2848 /* release split MCP access lock register */
2849 static void bnx2x_release_alr(struct bnx2x_softc *sc)
2850 {
2851         REG_WR(sc, GRCBASE_MCP + 0x9c, 0);
2852 }
2853
2854 static void bnx2x_fan_failure(struct bnx2x_softc *sc)
2855 {
2856         int port = SC_PORT(sc);
2857         uint32_t ext_phy_config;
2858
2859         /* mark the failure */
2860         ext_phy_config =
2861             SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
2862
2863         ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2864         ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
2865         SHMEM_WR(sc, dev_info.port_hw_config[port].external_phy_config,
2866                  ext_phy_config);
2867
2868         /* log the failure */
2869         PMD_DRV_LOG(INFO,
2870                     "Fan Failure has caused the driver to shutdown "
2871                     "the card to prevent permanent damage. "
2872                     "Please contact OEM Support for assistance");
2873
2874         rte_panic("Schedule task to handle fan failure");
2875 }
2876
2877 /* this function is called upon a link interrupt */
2878 static void bnx2x_link_attn(struct bnx2x_softc *sc)
2879 {
2880         uint32_t pause_enabled = 0;
2881         struct host_port_stats *pstats;
2882         int cmng_fns;
2883
2884         /* Make sure that we are synced with the current statistics */
2885         bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2886
2887         elink_link_update(&sc->link_params, &sc->link_vars);
2888
2889         if (sc->link_vars.link_up) {
2890
2891                 /* dropless flow control */
2892                 if (sc->dropless_fc) {
2893                         pause_enabled = 0;
2894
2895                         if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
2896                                 pause_enabled = 1;
2897                         }
2898
2899                         REG_WR(sc,
2900                                (BAR_USTRORM_INTMEM +
2901                                 USTORM_ETH_PAUSE_ENABLED_OFFSET(SC_PORT(sc))),
2902                                pause_enabled);
2903                 }
2904
2905                 if (sc->link_vars.mac_type != ELINK_MAC_TYPE_EMAC) {
2906                         pstats = BNX2X_SP(sc, port_stats);
2907                         /* reset old mac stats */
2908                         memset(&(pstats->mac_stx[0]), 0,
2909                                sizeof(struct mac_stx));
2910                 }
2911
2912                 if (sc->state == BNX2X_STATE_OPEN) {
2913                         bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
2914                 }
2915         }
2916
2917         if (sc->link_vars.link_up && sc->link_vars.line_speed) {
2918                 cmng_fns = bnx2x_get_cmng_fns_mode(sc);
2919
2920                 if (cmng_fns != CMNG_FNS_NONE) {
2921                         bnx2x_cmng_fns_init(sc, FALSE, cmng_fns);
2922                         storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
2923                 }
2924         }
2925
2926         bnx2x_link_report(sc);
2927
2928         if (IS_MF(sc)) {
2929                 bnx2x_link_sync_notify(sc);
2930         }
2931 }
2932
2933 static void bnx2x_attn_int_asserted(struct bnx2x_softc *sc, uint32_t asserted)
2934 {
2935         int port = SC_PORT(sc);
2936         uint32_t aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2937             MISC_REG_AEU_MASK_ATTN_FUNC_0;
2938         uint32_t nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2939             NIG_REG_MASK_INTERRUPT_PORT0;
2940         uint32_t aeu_mask;
2941         uint32_t nig_mask = 0;
2942         uint32_t reg_addr;
2943         uint32_t igu_acked;
2944         uint32_t cnt;
2945
2946         if (sc->attn_state & asserted) {
2947                 PMD_DRV_LOG(ERR, "IGU ERROR attn=0x%08x", asserted);
2948         }
2949
2950         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2951
2952         aeu_mask = REG_RD(sc, aeu_addr);
2953
2954         aeu_mask &= ~(asserted & 0x3ff);
2955
2956         REG_WR(sc, aeu_addr, aeu_mask);
2957
2958         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2959
2960         sc->attn_state |= asserted;
2961
2962         if (asserted & ATTN_HARD_WIRED_MASK) {
2963                 if (asserted & ATTN_NIG_FOR_FUNC) {
2964
2965                         /* save nig interrupt mask */
2966                         nig_mask = REG_RD(sc, nig_int_mask_addr);
2967
2968                         /* If nig_mask is not set, no need to call the update function */
2969                         if (nig_mask) {
2970                                 REG_WR(sc, nig_int_mask_addr, 0);
2971
2972                                 bnx2x_link_attn(sc);
2973                         }
2974
2975                         /* handle unicore attn? */
2976                 }
2977
2978                 if (asserted & ATTN_SW_TIMER_4_FUNC) {
2979                         PMD_DRV_LOG(DEBUG, "ATTN_SW_TIMER_4_FUNC!");
2980                 }
2981
2982                 if (asserted & GPIO_2_FUNC) {
2983                         PMD_DRV_LOG(DEBUG, "GPIO_2_FUNC!");
2984                 }
2985
2986                 if (asserted & GPIO_3_FUNC) {
2987                         PMD_DRV_LOG(DEBUG, "GPIO_3_FUNC!");
2988                 }
2989
2990                 if (asserted & GPIO_4_FUNC) {
2991                         PMD_DRV_LOG(DEBUG, "GPIO_4_FUNC!");
2992                 }
2993
2994                 if (port == 0) {
2995                         if (asserted & ATTN_GENERAL_ATTN_1) {
2996                                 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_1!");
2997                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
2998                         }
2999                         if (asserted & ATTN_GENERAL_ATTN_2) {
3000                                 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_2!");
3001                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3002                         }
3003                         if (asserted & ATTN_GENERAL_ATTN_3) {
3004                                 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_3!");
3005                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3006                         }
3007                 } else {
3008                         if (asserted & ATTN_GENERAL_ATTN_4) {
3009                                 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_4!");
3010                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3011                         }
3012                         if (asserted & ATTN_GENERAL_ATTN_5) {
3013                                 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_5!");
3014                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3015                         }
3016                         if (asserted & ATTN_GENERAL_ATTN_6) {
3017                                 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_6!");
3018                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3019                         }
3020                 }
3021         }
3022         /* hardwired */
3023         if (sc->devinfo.int_block == INT_BLOCK_HC) {
3024                 reg_addr =
3025                     (HC_REG_COMMAND_REG + port * 32 +
3026                      COMMAND_REG_ATTN_BITS_SET);
3027         } else {
3028                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER * 8);
3029         }
3030
3031         PMD_DRV_LOG(DEBUG, "about to mask 0x%08x at %s addr 0x%08x",
3032                     asserted,
3033                     (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
3034                     reg_addr);
3035         REG_WR(sc, reg_addr, asserted);
3036
3037         /* now set back the mask */
3038         if (asserted & ATTN_NIG_FOR_FUNC) {
3039                 /*
3040                  * Verify that IGU ack through BAR was written before restoring
3041                  * NIG mask. This loop should exit after 2-3 iterations max.
3042                  */
3043                 if (sc->devinfo.int_block != INT_BLOCK_HC) {
3044                         cnt = 0;
3045
3046                         do {
3047                                 igu_acked =
3048                                     REG_RD(sc, IGU_REG_ATTENTION_ACK_BITS);
3049                         } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0)
3050                                  && (++cnt < MAX_IGU_ATTN_ACK_TO));
3051
3052                         if (!igu_acked) {
3053                                 PMD_DRV_LOG(ERR,
3054                                             "Failed to verify IGU ack on time");
3055                         }
3056
3057                         mb();
3058                 }
3059
3060                 REG_WR(sc, nig_int_mask_addr, nig_mask);
3061
3062         }
3063 }
3064
3065 static void
3066 bnx2x_print_next_block(__rte_unused struct bnx2x_softc *sc, __rte_unused int idx,
3067                      __rte_unused const char *blk)
3068 {
3069         PMD_DRV_LOG(INFO, "%s%s", idx ? ", " : "", blk);
3070 }
3071
3072 static int
3073 bnx2x_check_blocks_with_parity0(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3074                               uint8_t print)
3075 {
3076         uint32_t cur_bit = 0;
3077         int i = 0;
3078
3079         for (i = 0; sig; i++) {
3080                 cur_bit = ((uint32_t) 0x1 << i);
3081                 if (sig & cur_bit) {
3082                         switch (cur_bit) {
3083                         case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3084                                 if (print)
3085                                         bnx2x_print_next_block(sc, par_num++,
3086                                                              "BRB");
3087                                 break;
3088                         case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3089                                 if (print)
3090                                         bnx2x_print_next_block(sc, par_num++,
3091                                                              "PARSER");
3092                                 break;
3093                         case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3094                                 if (print)
3095                                         bnx2x_print_next_block(sc, par_num++,
3096                                                              "TSDM");
3097                                 break;
3098                         case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3099                                 if (print)
3100                                         bnx2x_print_next_block(sc, par_num++,
3101                                                              "SEARCHER");
3102                                 break;
3103                         case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3104                                 if (print)
3105                                         bnx2x_print_next_block(sc, par_num++,
3106                                                              "TCM");
3107                                 break;
3108                         case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3109                                 if (print)
3110                                         bnx2x_print_next_block(sc, par_num++,
3111                                                              "TSEMI");
3112                                 break;
3113                         case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3114                                 if (print)
3115                                         bnx2x_print_next_block(sc, par_num++,
3116                                                              "XPB");
3117                                 break;
3118                         }
3119
3120                         /* Clear the bit */
3121                         sig &= ~cur_bit;
3122                 }
3123         }
3124
3125         return par_num;
3126 }
3127
3128 static int
3129 bnx2x_check_blocks_with_parity1(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3130                               uint8_t * global, uint8_t print)
3131 {
3132         int i = 0;
3133         uint32_t cur_bit = 0;
3134         for (i = 0; sig; i++) {
3135                 cur_bit = ((uint32_t) 0x1 << i);
3136                 if (sig & cur_bit) {
3137                         switch (cur_bit) {
3138                         case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3139                                 if (print)
3140                                         bnx2x_print_next_block(sc, par_num++,
3141                                                              "PBF");
3142                                 break;
3143                         case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3144                                 if (print)
3145                                         bnx2x_print_next_block(sc, par_num++,
3146                                                              "QM");
3147                                 break;
3148                         case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3149                                 if (print)
3150                                         bnx2x_print_next_block(sc, par_num++,
3151                                                              "TM");
3152                                 break;
3153                         case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3154                                 if (print)
3155                                         bnx2x_print_next_block(sc, par_num++,
3156                                                              "XSDM");
3157                                 break;
3158                         case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
3159                                 if (print)
3160                                         bnx2x_print_next_block(sc, par_num++,
3161                                                              "XCM");
3162                                 break;
3163                         case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3164                                 if (print)
3165                                         bnx2x_print_next_block(sc, par_num++,
3166                                                              "XSEMI");
3167                                 break;
3168                         case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3169                                 if (print)
3170                                         bnx2x_print_next_block(sc, par_num++,
3171                                                              "DOORBELLQ");
3172                                 break;
3173                         case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
3174                                 if (print)
3175                                         bnx2x_print_next_block(sc, par_num++,
3176                                                              "NIG");
3177                                 break;
3178                         case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3179                                 if (print)
3180                                         bnx2x_print_next_block(sc, par_num++,
3181                                                              "VAUX PCI CORE");
3182                                 *global = TRUE;
3183                                 break;
3184                         case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3185                                 if (print)
3186                                         bnx2x_print_next_block(sc, par_num++,
3187                                                              "DEBUG");
3188                                 break;
3189                         case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3190                                 if (print)
3191                                         bnx2x_print_next_block(sc, par_num++,
3192                                                              "USDM");
3193                                 break;
3194                         case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
3195                                 if (print)
3196                                         bnx2x_print_next_block(sc, par_num++,
3197                                                              "UCM");
3198                                 break;
3199                         case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3200                                 if (print)
3201                                         bnx2x_print_next_block(sc, par_num++,
3202                                                              "USEMI");
3203                                 break;
3204                         case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3205                                 if (print)
3206                                         bnx2x_print_next_block(sc, par_num++,
3207                                                              "UPB");
3208                                 break;
3209                         case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3210                                 if (print)
3211                                         bnx2x_print_next_block(sc, par_num++,
3212                                                              "CSDM");
3213                                 break;
3214                         case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
3215                                 if (print)
3216                                         bnx2x_print_next_block(sc, par_num++,
3217                                                              "CCM");
3218                                 break;
3219                         }
3220
3221                         /* Clear the bit */
3222                         sig &= ~cur_bit;
3223                 }
3224         }
3225
3226         return par_num;
3227 }
3228
3229 static int
3230 bnx2x_check_blocks_with_parity2(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3231                               uint8_t print)
3232 {
3233         uint32_t cur_bit = 0;
3234         int i = 0;
3235
3236         for (i = 0; sig; i++) {
3237                 cur_bit = ((uint32_t) 0x1 << i);
3238                 if (sig & cur_bit) {
3239                         switch (cur_bit) {
3240                         case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3241                                 if (print)
3242                                         bnx2x_print_next_block(sc, par_num++,
3243                                                              "CSEMI");
3244                                 break;
3245                         case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3246                                 if (print)
3247                                         bnx2x_print_next_block(sc, par_num++,
3248                                                              "PXP");
3249                                 break;
3250                         case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3251                                 if (print)
3252                                         bnx2x_print_next_block(sc, par_num++,
3253                                                              "PXPPCICLOCKCLIENT");
3254                                 break;
3255                         case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3256                                 if (print)
3257                                         bnx2x_print_next_block(sc, par_num++,
3258                                                              "CFC");
3259                                 break;
3260                         case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3261                                 if (print)
3262                                         bnx2x_print_next_block(sc, par_num++,
3263                                                              "CDU");
3264                                 break;
3265                         case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
3266                                 if (print)
3267                                         bnx2x_print_next_block(sc, par_num++,
3268                                                              "DMAE");
3269                                 break;
3270                         case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3271                                 if (print)
3272                                         bnx2x_print_next_block(sc, par_num++,
3273                                                              "IGU");
3274                                 break;
3275                         case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3276                                 if (print)
3277                                         bnx2x_print_next_block(sc, par_num++,
3278                                                              "MISC");
3279                                 break;
3280                         }
3281
3282                         /* Clear the bit */
3283                         sig &= ~cur_bit;
3284                 }
3285         }
3286
3287         return par_num;
3288 }
3289
3290 static int
3291 bnx2x_check_blocks_with_parity3(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3292                               uint8_t * global, uint8_t print)
3293 {
3294         uint32_t cur_bit = 0;
3295         int i = 0;
3296
3297         for (i = 0; sig; i++) {
3298                 cur_bit = ((uint32_t) 0x1 << i);
3299                 if (sig & cur_bit) {
3300                         switch (cur_bit) {
3301                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3302                                 if (print)
3303                                         bnx2x_print_next_block(sc, par_num++,
3304                                                              "MCP ROM");
3305                                 *global = TRUE;
3306                                 break;
3307                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3308                                 if (print)
3309                                         bnx2x_print_next_block(sc, par_num++,
3310                                                              "MCP UMP RX");
3311                                 *global = TRUE;
3312                                 break;
3313                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3314                                 if (print)
3315                                         bnx2x_print_next_block(sc, par_num++,
3316                                                              "MCP UMP TX");
3317                                 *global = TRUE;
3318                                 break;
3319                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3320                                 if (print)
3321                                         bnx2x_print_next_block(sc, par_num++,
3322                                                              "MCP SCPAD");
3323                                 *global = TRUE;
3324                                 break;
3325                         }
3326
3327                         /* Clear the bit */
3328                         sig &= ~cur_bit;
3329                 }
3330         }
3331
3332         return par_num;
3333 }
3334
3335 static int
3336 bnx2x_check_blocks_with_parity4(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3337                               uint8_t print)
3338 {
3339         uint32_t cur_bit = 0;
3340         int i = 0;
3341
3342         for (i = 0; sig; i++) {
3343                 cur_bit = ((uint32_t) 0x1 << i);
3344                 if (sig & cur_bit) {
3345                         switch (cur_bit) {
3346                         case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
3347                                 if (print)
3348                                         bnx2x_print_next_block(sc, par_num++,
3349                                                              "PGLUE_B");
3350                                 break;
3351                         case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
3352                                 if (print)
3353                                         bnx2x_print_next_block(sc, par_num++,
3354                                                              "ATC");
3355                                 break;
3356                         }
3357
3358                         /* Clear the bit */
3359                         sig &= ~cur_bit;
3360                 }
3361         }
3362
3363         return par_num;
3364 }
3365
3366 static uint8_t
3367 bnx2x_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print,
3368                 uint32_t * sig)
3369 {
3370         int par_num = 0;
3371
3372         if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
3373             (sig[1] & HW_PRTY_ASSERT_SET_1) ||
3374             (sig[2] & HW_PRTY_ASSERT_SET_2) ||
3375             (sig[3] & HW_PRTY_ASSERT_SET_3) ||
3376             (sig[4] & HW_PRTY_ASSERT_SET_4)) {
3377                 PMD_DRV_LOG(ERR,
3378                             "Parity error: HW block parity attention:"
3379                             "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x",
3380                             (uint32_t) (sig[0] & HW_PRTY_ASSERT_SET_0),
3381                             (uint32_t) (sig[1] & HW_PRTY_ASSERT_SET_1),
3382                             (uint32_t) (sig[2] & HW_PRTY_ASSERT_SET_2),
3383                             (uint32_t) (sig[3] & HW_PRTY_ASSERT_SET_3),
3384                             (uint32_t) (sig[4] & HW_PRTY_ASSERT_SET_4));
3385
3386                 if (print)
3387                         PMD_DRV_LOG(INFO, "Parity errors detected in blocks: ");
3388
3389                 par_num =
3390                     bnx2x_check_blocks_with_parity0(sc, sig[0] &
3391                                                   HW_PRTY_ASSERT_SET_0,
3392                                                   par_num, print);
3393                 par_num =
3394                     bnx2x_check_blocks_with_parity1(sc, sig[1] &
3395                                                   HW_PRTY_ASSERT_SET_1,
3396                                                   par_num, global, print);
3397                 par_num =
3398                     bnx2x_check_blocks_with_parity2(sc, sig[2] &
3399                                                   HW_PRTY_ASSERT_SET_2,
3400                                                   par_num, print);
3401                 par_num =
3402                     bnx2x_check_blocks_with_parity3(sc, sig[3] &
3403                                                   HW_PRTY_ASSERT_SET_3,
3404                                                   par_num, global, print);
3405                 par_num =
3406                     bnx2x_check_blocks_with_parity4(sc, sig[4] &
3407                                                   HW_PRTY_ASSERT_SET_4,
3408                                                   par_num, print);
3409
3410                 if (print)
3411                         PMD_DRV_LOG(INFO, "");
3412
3413                 return TRUE;
3414         }
3415
3416         return FALSE;
3417 }
3418
3419 static uint8_t
3420 bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print)
3421 {
3422         struct attn_route attn = { {0} };
3423         int port = SC_PORT(sc);
3424
3425         attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
3426         attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
3427         attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
3428         attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
3429
3430         if (!CHIP_IS_E1x(sc))
3431                 attn.sig[4] =
3432                     REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
3433
3434         return bnx2x_parity_attn(sc, global, print, attn.sig);
3435 }
3436
3437 static void bnx2x_attn_int_deasserted4(struct bnx2x_softc *sc, uint32_t attn)
3438 {
3439         uint32_t val;
3440
3441         if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
3442                 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
3443                 PMD_DRV_LOG(INFO, "ERROR: PGLUE hw attention 0x%08x", val);
3444                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
3445                         PMD_DRV_LOG(INFO,
3446                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR");
3447                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
3448                         PMD_DRV_LOG(INFO,
3449                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR");
3450                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
3451                         PMD_DRV_LOG(INFO,
3452                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN");
3453                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
3454                         PMD_DRV_LOG(INFO,
3455                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN");
3456                 if (val &
3457                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
3458                         PMD_DRV_LOG(INFO,
3459                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN");
3460                 if (val &
3461                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
3462                         PMD_DRV_LOG(INFO,
3463                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN");
3464                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
3465                         PMD_DRV_LOG(INFO,
3466                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN");
3467                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
3468                         PMD_DRV_LOG(INFO,
3469                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN");
3470                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
3471                         PMD_DRV_LOG(INFO,
3472                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW");
3473         }
3474
3475         if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
3476                 val = REG_RD(sc, ATC_REG_ATC_INT_STS_CLR);
3477                 PMD_DRV_LOG(INFO, "ERROR: ATC hw attention 0x%08x", val);
3478                 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
3479                         PMD_DRV_LOG(INFO,
3480                                     "ERROR: ATC_ATC_INT_STS_REG_ADDRESS_ERROR");
3481                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
3482                         PMD_DRV_LOG(INFO,
3483                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND");
3484                 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
3485                         PMD_DRV_LOG(INFO,
3486                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS");
3487                 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
3488                         PMD_DRV_LOG(INFO,
3489                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT");
3490                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
3491                         PMD_DRV_LOG(INFO,
3492                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR");
3493                 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
3494                         PMD_DRV_LOG(INFO,
3495                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU");
3496         }
3497
3498         if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3499                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
3500                 PMD_DRV_LOG(INFO,
3501                             "ERROR: FATAL parity attention set4 0x%08x",
3502                             (uint32_t) (attn &
3503                                         (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
3504                                          |
3505                                          AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
3506         }
3507 }
3508
3509 static void bnx2x_e1h_disable(struct bnx2x_softc *sc)
3510 {
3511         int port = SC_PORT(sc);
3512
3513         REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
3514 }
3515
3516 static void bnx2x_e1h_enable(struct bnx2x_softc *sc)
3517 {
3518         int port = SC_PORT(sc);
3519
3520         REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3521 }
3522
3523 /*
3524  * called due to MCP event (on pmf):
3525  *   reread new bandwidth configuration
3526  *   configure FW
3527  *   notify others function about the change
3528  */
3529 static void bnx2x_config_mf_bw(struct bnx2x_softc *sc)
3530 {
3531         if (sc->link_vars.link_up) {
3532                 bnx2x_cmng_fns_init(sc, TRUE, CMNG_FNS_MINMAX);
3533                 bnx2x_link_sync_notify(sc);
3534         }
3535
3536         storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
3537 }
3538
3539 static void bnx2x_set_mf_bw(struct bnx2x_softc *sc)
3540 {
3541         bnx2x_config_mf_bw(sc);
3542         bnx2x_fw_command(sc, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3543 }
3544
3545 static void bnx2x_handle_eee_event(struct bnx2x_softc *sc)
3546 {
3547         bnx2x_fw_command(sc, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3548 }
3549
3550 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3551
3552 static void bnx2x_drv_info_ether_stat(struct bnx2x_softc *sc)
3553 {
3554         struct eth_stats_info *ether_stat = &sc->sp->drv_info_to_mcp.ether_stat;
3555
3556         strncpy(ether_stat->version, BNX2X_DRIVER_VERSION,
3557                 ETH_STAT_INFO_VERSION_LEN);
3558
3559         sc->sp_objs[0].mac_obj.get_n_elements(sc, &sc->sp_objs[0].mac_obj,
3560                                               DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3561                                               ether_stat->mac_local + MAC_PAD,
3562                                               MAC_PAD, ETH_ALEN);
3563
3564         ether_stat->mtu_size = sc->mtu;
3565
3566         ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3567         ether_stat->promiscuous_mode = 0;       // (flags & PROMISC) ? 1 : 0;
3568
3569         ether_stat->txq_size = sc->tx_ring_size;
3570         ether_stat->rxq_size = sc->rx_ring_size;
3571 }
3572
3573 static void bnx2x_handle_drv_info_req(struct bnx2x_softc *sc)
3574 {
3575         enum drv_info_opcode op_code;
3576         uint32_t drv_info_ctl = SHMEM2_RD(sc, drv_info_control);
3577
3578         /* if drv_info version supported by MFW doesn't match - send NACK */
3579         if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3580                 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3581                 return;
3582         }
3583
3584         op_code = ((drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3585                    DRV_INFO_CONTROL_OP_CODE_SHIFT);
3586
3587         memset(&sc->sp->drv_info_to_mcp, 0, sizeof(union drv_info_to_mcp));
3588
3589         switch (op_code) {
3590         case ETH_STATS_OPCODE:
3591                 bnx2x_drv_info_ether_stat(sc);
3592                 break;
3593         case FCOE_STATS_OPCODE:
3594         case ISCSI_STATS_OPCODE:
3595         default:
3596                 /* if op code isn't supported - send NACK */
3597                 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3598                 return;
3599         }
3600
3601         /*
3602          * If we got drv_info attn from MFW then these fields are defined in
3603          * shmem2 for sure
3604          */
3605         SHMEM2_WR(sc, drv_info_host_addr_lo,
3606                   U64_LO(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3607         SHMEM2_WR(sc, drv_info_host_addr_hi,
3608                   U64_HI(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3609
3610         bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3611 }
3612
3613 static void bnx2x_dcc_event(struct bnx2x_softc *sc, uint32_t dcc_event)
3614 {
3615         if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3616 /*
3617  * This is the only place besides the function initialization
3618  * where the sc->flags can change so it is done without any
3619  * locks
3620  */
3621                 if (sc->devinfo.
3622                     mf_info.mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_DISABLED) {
3623                         PMD_DRV_LOG(DEBUG, "mf_cfg function disabled");
3624                         sc->flags |= BNX2X_MF_FUNC_DIS;
3625                         bnx2x_e1h_disable(sc);
3626                 } else {
3627                         PMD_DRV_LOG(DEBUG, "mf_cfg function enabled");
3628                         sc->flags &= ~BNX2X_MF_FUNC_DIS;
3629                         bnx2x_e1h_enable(sc);
3630                 }
3631                 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3632         }
3633
3634         if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3635                 bnx2x_config_mf_bw(sc);
3636                 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3637         }
3638
3639         /* Report results to MCP */
3640         if (dcc_event)
3641                 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_FAILURE, 0);
3642         else
3643                 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_OK, 0);
3644 }
3645
3646 static void bnx2x_pmf_update(struct bnx2x_softc *sc)
3647 {
3648         int port = SC_PORT(sc);
3649         uint32_t val;
3650
3651         sc->port.pmf = 1;
3652
3653         /*
3654          * We need the mb() to ensure the ordering between the writing to
3655          * sc->port.pmf here and reading it from the bnx2x_periodic_task().
3656          */
3657         mb();
3658
3659         /* enable nig attention */
3660         val = (0xff0f | (1 << (SC_VN(sc) + 4)));
3661         if (sc->devinfo.int_block == INT_BLOCK_HC) {
3662                 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, val);
3663                 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, val);
3664         } else if (!CHIP_IS_E1x(sc)) {
3665                 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
3666                 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
3667         }
3668
3669         bnx2x_stats_handle(sc, STATS_EVENT_PMF);
3670 }
3671
3672 static int bnx2x_mc_assert(struct bnx2x_softc *sc)
3673 {
3674         char last_idx;
3675         int i, rc = 0;
3676         __rte_unused uint32_t row0, row1, row2, row3;
3677
3678         /* XSTORM */
3679         last_idx =
3680             REG_RD8(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_INDEX_OFFSET);
3681         if (last_idx)
3682                 PMD_DRV_LOG(ERR, "XSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3683
3684         /* print the asserts */
3685         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3686
3687                 row0 =
3688                     REG_RD(sc,
3689                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i));
3690                 row1 =
3691                     REG_RD(sc,
3692                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3693                            4);
3694                 row2 =
3695                     REG_RD(sc,
3696                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3697                            8);
3698                 row3 =
3699                     REG_RD(sc,
3700                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3701                            12);
3702
3703                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3704                         PMD_DRV_LOG(ERR,
3705                                     "XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3706                                     i, row3, row2, row1, row0);
3707                         rc++;
3708                 } else {
3709                         break;
3710                 }
3711         }
3712
3713         /* TSTORM */
3714         last_idx =
3715             REG_RD8(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_INDEX_OFFSET);
3716         if (last_idx) {
3717                 PMD_DRV_LOG(ERR, "TSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3718         }
3719
3720         /* print the asserts */
3721         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3722
3723                 row0 =
3724                     REG_RD(sc,
3725                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i));
3726                 row1 =
3727                     REG_RD(sc,
3728                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3729                            4);
3730                 row2 =
3731                     REG_RD(sc,
3732                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3733                            8);
3734                 row3 =
3735                     REG_RD(sc,
3736                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3737                            12);
3738
3739                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3740                         PMD_DRV_LOG(ERR,
3741                                     "TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3742                                     i, row3, row2, row1, row0);
3743                         rc++;
3744                 } else {
3745                         break;
3746                 }
3747         }
3748
3749         /* CSTORM */
3750         last_idx =
3751             REG_RD8(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_INDEX_OFFSET);
3752         if (last_idx) {
3753                 PMD_DRV_LOG(ERR, "CSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3754         }
3755
3756         /* print the asserts */
3757         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3758
3759                 row0 =
3760                     REG_RD(sc,
3761                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i));
3762                 row1 =
3763                     REG_RD(sc,
3764                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3765                            4);
3766                 row2 =
3767                     REG_RD(sc,
3768                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3769                            8);
3770                 row3 =
3771                     REG_RD(sc,
3772                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3773                            12);
3774
3775                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3776                         PMD_DRV_LOG(ERR,
3777                                     "CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3778                                     i, row3, row2, row1, row0);
3779                         rc++;
3780                 } else {
3781                         break;
3782                 }
3783         }
3784
3785         /* USTORM */
3786         last_idx =
3787             REG_RD8(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_INDEX_OFFSET);
3788         if (last_idx) {
3789                 PMD_DRV_LOG(ERR, "USTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3790         }
3791
3792         /* print the asserts */
3793         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3794
3795                 row0 =
3796                     REG_RD(sc,
3797                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i));
3798                 row1 =
3799                     REG_RD(sc,
3800                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3801                            4);
3802                 row2 =
3803                     REG_RD(sc,
3804                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3805                            8);
3806                 row3 =
3807                     REG_RD(sc,
3808                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3809                            12);
3810
3811                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3812                         PMD_DRV_LOG(ERR,
3813                                     "USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3814                                     i, row3, row2, row1, row0);
3815                         rc++;
3816                 } else {
3817                         break;
3818                 }
3819         }
3820
3821         return rc;
3822 }
3823
3824 static void bnx2x_attn_int_deasserted3(struct bnx2x_softc *sc, uint32_t attn)
3825 {
3826         int func = SC_FUNC(sc);
3827         uint32_t val;
3828
3829         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3830
3831                 if (attn & BNX2X_PMF_LINK_ASSERT(sc)) {
3832
3833                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
3834                         bnx2x_read_mf_cfg(sc);
3835                         sc->devinfo.mf_info.mf_config[SC_VN(sc)] =
3836                             MFCFG_RD(sc,
3837                                      func_mf_config[SC_ABS_FUNC(sc)].config);
3838                         val =
3839                             SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_status);
3840
3841                         if (val & DRV_STATUS_DCC_EVENT_MASK)
3842                                 bnx2x_dcc_event(sc,
3843                                               (val &
3844                                                DRV_STATUS_DCC_EVENT_MASK));
3845
3846                         if (val & DRV_STATUS_SET_MF_BW)
3847                                 bnx2x_set_mf_bw(sc);
3848
3849                         if (val & DRV_STATUS_DRV_INFO_REQ)
3850                                 bnx2x_handle_drv_info_req(sc);
3851
3852                         if ((sc->port.pmf == 0) && (val & DRV_STATUS_PMF))
3853                                 bnx2x_pmf_update(sc);
3854
3855                         if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
3856                                 bnx2x_handle_eee_event(sc);
3857
3858                         if (sc->link_vars.periodic_flags &
3859                             ELINK_PERIODIC_FLAGS_LINK_EVENT) {
3860                                 /* sync with link */
3861                                 sc->link_vars.periodic_flags &=
3862                                     ~ELINK_PERIODIC_FLAGS_LINK_EVENT;
3863                                 if (IS_MF(sc)) {
3864                                         bnx2x_link_sync_notify(sc);
3865                                 }
3866                                 bnx2x_link_report(sc);
3867                         }
3868
3869                         /*
3870                          * Always call it here: bnx2x_link_report() will
3871                          * prevent the link indication duplication.
3872                          */
3873                         bnx2x_link_status_update(sc);
3874
3875                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3876
3877                         PMD_DRV_LOG(ERR, "MC assert!");
3878                         bnx2x_mc_assert(sc);
3879                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3880                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3881                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3882                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3883                         rte_panic("MC assert!");
3884
3885                 } else if (attn & BNX2X_MCP_ASSERT) {
3886
3887                         PMD_DRV_LOG(ERR, "MCP assert!");
3888                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3889
3890                 } else {
3891                         PMD_DRV_LOG(ERR,
3892                                     "Unknown HW assert! (attn 0x%08x)", attn);
3893                 }
3894         }
3895
3896         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3897                 PMD_DRV_LOG(ERR, "LATCHED attention 0x%08x (masked)", attn);
3898                 if (attn & BNX2X_GRC_TIMEOUT) {
3899                         val = REG_RD(sc, MISC_REG_GRC_TIMEOUT_ATTN);
3900                         PMD_DRV_LOG(ERR, "GRC time-out 0x%08x", val);
3901                 }
3902                 if (attn & BNX2X_GRC_RSV) {
3903                         val = REG_RD(sc, MISC_REG_GRC_RSV_ATTN);
3904                         PMD_DRV_LOG(ERR, "GRC reserved 0x%08x", val);
3905                 }
3906                 REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3907         }
3908 }
3909
3910 static void bnx2x_attn_int_deasserted2(struct bnx2x_softc *sc, uint32_t attn)
3911 {
3912         int port = SC_PORT(sc);
3913         int reg_offset;
3914         uint32_t val0, mask0, val1, mask1;
3915         uint32_t val;
3916
3917         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3918                 val = REG_RD(sc, CFC_REG_CFC_INT_STS_CLR);
3919                 PMD_DRV_LOG(ERR, "CFC hw attention 0x%08x", val);
3920 /* CFC error attention */
3921                 if (val & 0x2) {
3922                         PMD_DRV_LOG(ERR, "FATAL error from CFC");
3923                 }
3924         }
3925
3926         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3927                 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_0);
3928                 PMD_DRV_LOG(ERR, "PXP hw attention-0 0x%08x", val);
3929 /* RQ_USDMDP_FIFO_OVERFLOW */
3930                 if (val & 0x18000) {
3931                         PMD_DRV_LOG(ERR, "FATAL error from PXP");
3932                 }
3933
3934                 if (!CHIP_IS_E1x(sc)) {
3935                         val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_1);
3936                         PMD_DRV_LOG(ERR, "PXP hw attention-1 0x%08x", val);
3937                 }
3938         }
3939 #define PXP2_EOP_ERROR_BIT  PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR
3940 #define AEU_PXP2_HW_INT_BIT AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT
3941
3942         if (attn & AEU_PXP2_HW_INT_BIT) {
3943 /*  CQ47854 workaround do not panic on
3944  *  PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3945  */
3946                 if (!CHIP_IS_E1x(sc)) {
3947                         mask0 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_0);
3948                         val1 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_1);
3949                         mask1 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_1);
3950                         val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_0);
3951                         /*
3952                          * If the olny PXP2_EOP_ERROR_BIT is set in
3953                          * STS0 and STS1 - clear it
3954                          *
3955                          * probably we lose additional attentions between
3956                          * STS0 and STS_CLR0, in this case user will not
3957                          * be notified about them
3958                          */
3959                         if (val0 & mask0 & PXP2_EOP_ERROR_BIT &&
3960                             !(val1 & mask1))
3961                                 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
3962
3963                         /* print the register, since no one can restore it */
3964                         PMD_DRV_LOG(ERR,
3965                                     "PXP2_REG_PXP2_INT_STS_CLR_0 0x%08x", val0);
3966
3967                         /*
3968                          * if PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3969                          * then notify
3970                          */
3971                         if (val0 & PXP2_EOP_ERROR_BIT) {
3972                                 PMD_DRV_LOG(ERR, "PXP2_WR_PGLUE_EOP_ERROR");
3973
3974                                 /*
3975                                  * if only PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR is
3976                                  * set then clear attention from PXP2 block without panic
3977                                  */
3978                                 if (((val0 & mask0) == PXP2_EOP_ERROR_BIT) &&
3979                                     ((val1 & mask1) == 0))
3980                                         attn &= ~AEU_PXP2_HW_INT_BIT;
3981                         }
3982                 }
3983         }
3984
3985         if (attn & HW_INTERRUT_ASSERT_SET_2) {
3986                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3987                               MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3988
3989                 val = REG_RD(sc, reg_offset);
3990                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3991                 REG_WR(sc, reg_offset, val);
3992
3993                 PMD_DRV_LOG(ERR,
3994                             "FATAL HW block attention set2 0x%x",
3995                             (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_2));
3996                 rte_panic("HW block attention set2");
3997         }
3998 }
3999
4000 static void bnx2x_attn_int_deasserted1(struct bnx2x_softc *sc, uint32_t attn)
4001 {
4002         int port = SC_PORT(sc);
4003         int reg_offset;
4004         uint32_t val;
4005
4006         if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
4007                 val = REG_RD(sc, DORQ_REG_DORQ_INT_STS_CLR);
4008                 PMD_DRV_LOG(ERR, "DB hw attention 0x%08x", val);
4009 /* DORQ discard attention */
4010                 if (val & 0x2) {
4011                         PMD_DRV_LOG(ERR, "FATAL error from DORQ");
4012                 }
4013         }
4014
4015         if (attn & HW_INTERRUT_ASSERT_SET_1) {
4016                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4017                               MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4018
4019                 val = REG_RD(sc, reg_offset);
4020                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4021                 REG_WR(sc, reg_offset, val);
4022
4023                 PMD_DRV_LOG(ERR,
4024                             "FATAL HW block attention set1 0x%08x",
4025                             (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_1));
4026                 rte_panic("HW block attention set1");
4027         }
4028 }
4029
4030 static void bnx2x_attn_int_deasserted0(struct bnx2x_softc *sc, uint32_t attn)
4031 {
4032         int port = SC_PORT(sc);
4033         int reg_offset;
4034         uint32_t val;
4035
4036         reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4037             MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
4038
4039         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4040                 val = REG_RD(sc, reg_offset);
4041                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4042                 REG_WR(sc, reg_offset, val);
4043
4044                 PMD_DRV_LOG(WARNING, "SPIO5 hw attention");
4045
4046 /* Fan failure attention */
4047                 elink_hw_reset_phy(&sc->link_params);
4048                 bnx2x_fan_failure(sc);
4049         }
4050
4051         if ((attn & sc->link_vars.aeu_int_mask) && sc->port.pmf) {
4052                 elink_handle_module_detect_int(&sc->link_params);
4053         }
4054
4055         if (attn & HW_INTERRUT_ASSERT_SET_0) {
4056                 val = REG_RD(sc, reg_offset);
4057                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4058                 REG_WR(sc, reg_offset, val);
4059
4060                 rte_panic("FATAL HW block attention set0 0x%lx",
4061                           (attn & HW_INTERRUT_ASSERT_SET_0));
4062         }
4063 }
4064
4065 static void bnx2x_attn_int_deasserted(struct bnx2x_softc *sc, uint32_t deasserted)
4066 {
4067         struct attn_route attn;
4068         struct attn_route *group_mask;
4069         int port = SC_PORT(sc);
4070         int index;
4071         uint32_t reg_addr;
4072         uint32_t val;
4073         uint32_t aeu_mask;
4074         uint8_t global = FALSE;
4075
4076         /*
4077          * Need to take HW lock because MCP or other port might also
4078          * try to handle this event.
4079          */
4080         bnx2x_acquire_alr(sc);
4081
4082         if (bnx2x_chk_parity_attn(sc, &global, TRUE)) {
4083                 sc->recovery_state = BNX2X_RECOVERY_INIT;
4084
4085 /* disable HW interrupts */
4086                 bnx2x_int_disable(sc);
4087                 bnx2x_release_alr(sc);
4088                 return;
4089         }
4090
4091         attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
4092         attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
4093         attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
4094         attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
4095         if (!CHIP_IS_E1x(sc)) {
4096                 attn.sig[4] =
4097                     REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
4098         } else {
4099                 attn.sig[4] = 0;
4100         }
4101
4102         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4103                 if (deasserted & (1 << index)) {
4104                         group_mask = &sc->attn_group[index];
4105
4106                         bnx2x_attn_int_deasserted4(sc,
4107                                                  attn.
4108                                                  sig[4] & group_mask->sig[4]);
4109                         bnx2x_attn_int_deasserted3(sc,
4110                                                  attn.
4111                                                  sig[3] & group_mask->sig[3]);
4112                         bnx2x_attn_int_deasserted1(sc,
4113                                                  attn.
4114                                                  sig[1] & group_mask->sig[1]);
4115                         bnx2x_attn_int_deasserted2(sc,
4116                                                  attn.
4117                                                  sig[2] & group_mask->sig[2]);
4118                         bnx2x_attn_int_deasserted0(sc,
4119                                                  attn.
4120                                                  sig[0] & group_mask->sig[0]);
4121                 }
4122         }
4123
4124         bnx2x_release_alr(sc);
4125
4126         if (sc->devinfo.int_block == INT_BLOCK_HC) {
4127                 reg_addr = (HC_REG_COMMAND_REG + port * 32 +
4128                             COMMAND_REG_ATTN_BITS_CLR);
4129         } else {
4130                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER * 8);
4131         }
4132
4133         val = ~deasserted;
4134         PMD_DRV_LOG(DEBUG,
4135                     "about to mask 0x%08x at %s addr 0x%08x", val,
4136                     (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
4137                     reg_addr);
4138         REG_WR(sc, reg_addr, val);
4139
4140         if (~sc->attn_state & deasserted) {
4141                 PMD_DRV_LOG(ERR, "IGU error");
4142         }
4143
4144         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4145             MISC_REG_AEU_MASK_ATTN_FUNC_0;
4146
4147         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4148
4149         aeu_mask = REG_RD(sc, reg_addr);
4150
4151         aeu_mask |= (deasserted & 0x3ff);
4152
4153         REG_WR(sc, reg_addr, aeu_mask);
4154         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4155
4156         sc->attn_state &= ~deasserted;
4157 }
4158
4159 static void bnx2x_attn_int(struct bnx2x_softc *sc)
4160 {
4161         /* read local copy of bits */
4162         uint32_t attn_bits = le32toh(sc->def_sb->atten_status_block.attn_bits);
4163         uint32_t attn_ack =
4164             le32toh(sc->def_sb->atten_status_block.attn_bits_ack);
4165         uint32_t attn_state = sc->attn_state;
4166
4167         /* look for changed bits */
4168         uint32_t asserted = attn_bits & ~attn_ack & ~attn_state;
4169         uint32_t deasserted = ~attn_bits & attn_ack & attn_state;
4170
4171         PMD_DRV_LOG(DEBUG,
4172                     "attn_bits 0x%08x attn_ack 0x%08x asserted 0x%08x deasserted 0x%08x",
4173                     attn_bits, attn_ack, asserted, deasserted);
4174
4175         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) {
4176                 PMD_DRV_LOG(ERR, "BAD attention state");
4177         }
4178
4179         /* handle bits that were raised */
4180         if (asserted) {
4181                 bnx2x_attn_int_asserted(sc, asserted);
4182         }
4183
4184         if (deasserted) {
4185                 bnx2x_attn_int_deasserted(sc, deasserted);
4186         }
4187 }
4188
4189 static uint16_t bnx2x_update_dsb_idx(struct bnx2x_softc *sc)
4190 {
4191         struct host_sp_status_block *def_sb = sc->def_sb;
4192         uint16_t rc = 0;
4193
4194         mb();                   /* status block is written to by the chip */
4195
4196         if (sc->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
4197                 sc->def_att_idx = def_sb->atten_status_block.attn_bits_index;
4198                 rc |= BNX2X_DEF_SB_ATT_IDX;
4199         }
4200
4201         if (sc->def_idx != def_sb->sp_sb.running_index) {
4202                 sc->def_idx = def_sb->sp_sb.running_index;
4203                 rc |= BNX2X_DEF_SB_IDX;
4204         }
4205
4206         mb();
4207
4208         return rc;
4209 }
4210
4211 static struct ecore_queue_sp_obj *bnx2x_cid_to_q_obj(struct bnx2x_softc *sc,
4212                                                           uint32_t cid)
4213 {
4214         return &sc->sp_objs[CID_TO_FP(cid, sc)].q_obj;
4215 }
4216
4217 static void bnx2x_handle_mcast_eqe(struct bnx2x_softc *sc)
4218 {
4219         struct ecore_mcast_ramrod_params rparam;
4220         int rc;
4221
4222         memset(&rparam, 0, sizeof(rparam));
4223
4224         rparam.mcast_obj = &sc->mcast_obj;
4225
4226         /* clear pending state for the last command */
4227         sc->mcast_obj.raw.clear_pending(&sc->mcast_obj.raw);
4228
4229         /* if there are pending mcast commands - send them */
4230         if (sc->mcast_obj.check_pending(&sc->mcast_obj)) {
4231                 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
4232                 if (rc < 0) {
4233                         PMD_DRV_LOG(INFO,
4234                                     "Failed to send pending mcast commands (%d)",
4235                                     rc);
4236                 }
4237         }
4238 }
4239
4240 static void
4241 bnx2x_handle_classification_eqe(struct bnx2x_softc *sc, union event_ring_elem *elem)
4242 {
4243         unsigned long ramrod_flags = 0;
4244         int rc = 0;
4245         uint32_t cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4246         struct ecore_vlan_mac_obj *vlan_mac_obj;
4247
4248         /* always push next commands out, don't wait here */
4249         bnx2x_set_bit(RAMROD_CONT, &ramrod_flags);
4250
4251         switch (le32toh(elem->message.data.eth_event.echo) >> BNX2X_SWCID_SHIFT) {
4252         case ECORE_FILTER_MAC_PENDING:
4253                 PMD_DRV_LOG(DEBUG, "Got SETUP_MAC completions");
4254                 vlan_mac_obj = &sc->sp_objs[cid].mac_obj;
4255                 break;
4256
4257         case ECORE_FILTER_MCAST_PENDING:
4258                 PMD_DRV_LOG(DEBUG, "Got SETUP_MCAST completions");
4259                 bnx2x_handle_mcast_eqe(sc);
4260                 return;
4261
4262         default:
4263                 PMD_DRV_LOG(NOTICE, "Unsupported classification command: %d",
4264                             elem->message.data.eth_event.echo);
4265                 return;
4266         }
4267
4268         rc = vlan_mac_obj->complete(sc, vlan_mac_obj, elem, &ramrod_flags);
4269
4270         if (rc < 0) {
4271                 PMD_DRV_LOG(NOTICE, "Failed to schedule new commands (%d)", rc);
4272         } else if (rc > 0) {
4273                 PMD_DRV_LOG(DEBUG, "Scheduled next pending commands...");
4274         }
4275 }
4276
4277 static void bnx2x_handle_rx_mode_eqe(struct bnx2x_softc *sc)
4278 {
4279         bnx2x_clear_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
4280
4281         /* send rx_mode command again if was requested */
4282         if (bnx2x_test_and_clear_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state)) {
4283                 bnx2x_set_storm_rx_mode(sc);
4284         }
4285 }
4286
4287 static void bnx2x_update_eq_prod(struct bnx2x_softc *sc, uint16_t prod)
4288 {
4289         storm_memset_eq_prod(sc, prod, SC_FUNC(sc));
4290         wmb();                  /* keep prod updates ordered */
4291 }
4292
4293 static void bnx2x_eq_int(struct bnx2x_softc *sc)
4294 {
4295         uint16_t hw_cons, sw_cons, sw_prod;
4296         union event_ring_elem *elem;
4297         uint8_t echo;
4298         uint32_t cid;
4299         uint8_t opcode;
4300         int spqe_cnt = 0;
4301         struct ecore_queue_sp_obj *q_obj;
4302         struct ecore_func_sp_obj *f_obj = &sc->func_obj;
4303         struct ecore_raw_obj *rss_raw = &sc->rss_conf_obj.raw;
4304
4305         hw_cons = le16toh(*sc->eq_cons_sb);
4306
4307         /*
4308          * The hw_cons range is 1-255, 257 - the sw_cons range is 0-254, 256.
4309          * when we get to the next-page we need to adjust so the loop
4310          * condition below will be met. The next element is the size of a
4311          * regular element and hence incrementing by 1
4312          */
4313         if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) {
4314                 hw_cons++;
4315         }
4316
4317         /*
4318          * This function may never run in parallel with itself for a
4319          * specific sc and no need for a read memory barrier here.
4320          */
4321         sw_cons = sc->eq_cons;
4322         sw_prod = sc->eq_prod;
4323
4324         for (;
4325              sw_cons != hw_cons;
4326              sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4327
4328                 elem = &sc->eq[EQ_DESC(sw_cons)];
4329
4330 /* elem CID originates from FW, actually LE */
4331                 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4332                 opcode = elem->message.opcode;
4333
4334 /* handle eq element */
4335                 switch (opcode) {
4336                 case EVENT_RING_OPCODE_STAT_QUERY:
4337                         PMD_DEBUG_PERIODIC_LOG(DEBUG, "got statistics completion event %d",
4338                                     sc->stats_comp++);
4339                         /* nothing to do with stats comp */
4340                         goto next_spqe;
4341
4342                 case EVENT_RING_OPCODE_CFC_DEL:
4343                         /* handle according to cid range */
4344                         /* we may want to verify here that the sc state is HALTING */
4345                         PMD_DRV_LOG(DEBUG, "got delete ramrod for MULTI[%d]",
4346                                     cid);
4347                         q_obj = bnx2x_cid_to_q_obj(sc, cid);
4348                         if (q_obj->complete_cmd(sc, q_obj, ECORE_Q_CMD_CFC_DEL)) {
4349                                 break;
4350                         }
4351                         goto next_spqe;
4352
4353                 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4354                         PMD_DRV_LOG(DEBUG, "got STOP TRAFFIC");
4355                         if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_STOP)) {
4356                                 break;
4357                         }
4358                         goto next_spqe;
4359
4360                 case EVENT_RING_OPCODE_START_TRAFFIC:
4361                         PMD_DRV_LOG(DEBUG, "got START TRAFFIC");
4362                         if (f_obj->complete_cmd
4363                             (sc, f_obj, ECORE_F_CMD_TX_START)) {
4364                                 break;
4365                         }
4366                         goto next_spqe;
4367
4368                 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
4369                         echo = elem->message.data.function_update_event.echo;
4370                         if (echo == SWITCH_UPDATE) {
4371                                 PMD_DRV_LOG(DEBUG,
4372                                             "got FUNC_SWITCH_UPDATE ramrod");
4373                                 if (f_obj->complete_cmd(sc, f_obj,
4374                                                         ECORE_F_CMD_SWITCH_UPDATE))
4375                                 {
4376                                         break;
4377                                 }
4378                         } else {
4379                                 PMD_DRV_LOG(DEBUG,
4380                                             "AFEX: ramrod completed FUNCTION_UPDATE");
4381                                 f_obj->complete_cmd(sc, f_obj,
4382                                                     ECORE_F_CMD_AFEX_UPDATE);
4383                         }
4384                         goto next_spqe;
4385
4386                 case EVENT_RING_OPCODE_FORWARD_SETUP:
4387                         q_obj = &bnx2x_fwd_sp_obj(sc, q_obj);
4388                         if (q_obj->complete_cmd(sc, q_obj,
4389                                                 ECORE_Q_CMD_SETUP_TX_ONLY)) {
4390                                 break;
4391                         }
4392                         goto next_spqe;
4393
4394                 case EVENT_RING_OPCODE_FUNCTION_START:
4395                         PMD_DRV_LOG(DEBUG, "got FUNC_START ramrod");
4396                         if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_START)) {
4397                                 break;
4398                         }
4399                         goto next_spqe;
4400
4401                 case EVENT_RING_OPCODE_FUNCTION_STOP:
4402                         PMD_DRV_LOG(DEBUG, "got FUNC_STOP ramrod");
4403                         if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_STOP)) {
4404                                 break;
4405                         }
4406                         goto next_spqe;
4407                 }
4408
4409                 switch (opcode | sc->state) {
4410                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPEN):
4411                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPENING_WAITING_PORT):
4412                         cid =
4413                             elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4414                         PMD_DRV_LOG(DEBUG, "got RSS_UPDATE ramrod. CID %d",
4415                                     cid);
4416                         rss_raw->clear_pending(rss_raw);
4417                         break;
4418
4419                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4420                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4421                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_CLOSING_WAITING_HALT):
4422                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_OPEN):
4423                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_DIAG):
4424                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4425                         PMD_DRV_LOG(DEBUG,
4426                                     "got (un)set mac ramrod");
4427                         bnx2x_handle_classification_eqe(sc, elem);
4428                         break;
4429
4430                 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_OPEN):
4431                 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_DIAG):
4432                 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4433                         PMD_DRV_LOG(DEBUG,
4434                                     "got mcast ramrod");
4435                         bnx2x_handle_mcast_eqe(sc);
4436                         break;
4437
4438                 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_OPEN):
4439                 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_DIAG):
4440                 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4441                         PMD_DRV_LOG(DEBUG,
4442                                     "got rx_mode ramrod");
4443                         bnx2x_handle_rx_mode_eqe(sc);
4444                         break;
4445
4446                 default:
4447                         /* unknown event log error and continue */
4448                         PMD_DRV_LOG(INFO, "Unknown EQ event %d, sc->state 0x%x",
4449                                     elem->message.opcode, sc->state);
4450                 }
4451
4452 next_spqe:
4453                 spqe_cnt++;
4454         }                       /* for */
4455
4456         mb();
4457         atomic_add_acq_long(&sc->eq_spq_left, spqe_cnt);
4458
4459         sc->eq_cons = sw_cons;
4460         sc->eq_prod = sw_prod;
4461
4462         /* make sure that above mem writes were issued towards the memory */
4463         wmb();
4464
4465         /* update producer */
4466         bnx2x_update_eq_prod(sc, sc->eq_prod);
4467 }
4468
4469 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc)
4470 {
4471         uint16_t status;
4472         int rc = 0;
4473
4474         /* what work needs to be performed? */
4475         status = bnx2x_update_dsb_idx(sc);
4476
4477         /* HW attentions */
4478         if (status & BNX2X_DEF_SB_ATT_IDX) {
4479                 PMD_DRV_LOG(DEBUG, "---> ATTN INTR <---");
4480                 bnx2x_attn_int(sc);
4481                 status &= ~BNX2X_DEF_SB_ATT_IDX;
4482                 rc = 1;
4483         }
4484
4485         /* SP events: STAT_QUERY and others */
4486         if (status & BNX2X_DEF_SB_IDX) {
4487 /* handle EQ completions */
4488                 PMD_DEBUG_PERIODIC_LOG(DEBUG, "---> EQ INTR <---");
4489                 bnx2x_eq_int(sc);
4490                 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
4491                            le16toh(sc->def_idx), IGU_INT_NOP, 1);
4492                 status &= ~BNX2X_DEF_SB_IDX;
4493         }
4494
4495         /* if status is non zero then something went wrong */
4496         if (unlikely(status)) {
4497                 PMD_DRV_LOG(INFO,
4498                             "Got an unknown SP interrupt! (0x%04x)", status);
4499         }
4500
4501         /* ack status block only if something was actually handled */
4502         bnx2x_ack_sb(sc, sc->igu_dsb_id, ATTENTION_ID,
4503                    le16toh(sc->def_att_idx), IGU_INT_ENABLE, 1);
4504
4505         return rc;
4506 }
4507
4508 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp, int scan_fp)
4509 {
4510         struct bnx2x_softc *sc = fp->sc;
4511         uint8_t more_rx = FALSE;
4512
4513         /* update the fastpath index */
4514         bnx2x_update_fp_sb_idx(fp);
4515
4516         if (scan_fp) {
4517                 if (bnx2x_has_rx_work(fp)) {
4518                         more_rx = bnx2x_rxeof(sc, fp);
4519                 }
4520
4521                 if (more_rx) {
4522                         /* still more work to do */
4523                         bnx2x_handle_fp_tq(fp, scan_fp);
4524                         return;
4525                 }
4526         }
4527
4528         bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
4529                    le16toh(fp->fp_hc_idx), IGU_INT_ENABLE, 1);
4530 }
4531
4532 /*
4533  * Legacy interrupt entry point.
4534  *
4535  * Verifies that the controller generated the interrupt and
4536  * then calls a separate routine to handle the various
4537  * interrupt causes: link, RX, and TX.
4538  */
4539 int bnx2x_intr_legacy(struct bnx2x_softc *sc, int scan_fp)
4540 {
4541         struct bnx2x_fastpath *fp;
4542         uint32_t status, mask;
4543         int i, rc = 0;
4544
4545         /*
4546          * 0 for ustorm, 1 for cstorm
4547          * the bits returned from ack_int() are 0-15
4548          * bit 0 = attention status block
4549          * bit 1 = fast path status block
4550          * a mask of 0x2 or more = tx/rx event
4551          * a mask of 1 = slow path event
4552          */
4553
4554         status = bnx2x_ack_int(sc);
4555
4556         /* the interrupt is not for us */
4557         if (unlikely(status == 0)) {
4558                 return 0;
4559         }
4560
4561         PMD_DEBUG_PERIODIC_LOG(DEBUG, "Interrupt status 0x%04x", status);
4562         //bnx2x_dump_status_block(sc);
4563
4564         FOR_EACH_ETH_QUEUE(sc, i) {
4565                 fp = &sc->fp[i];
4566                 mask = (0x2 << (fp->index + CNIC_SUPPORT(sc)));
4567                 if (status & mask) {
4568                         bnx2x_handle_fp_tq(fp, scan_fp);
4569                         status &= ~mask;
4570                 }
4571         }
4572
4573         if (unlikely(status & 0x1)) {
4574                 rc = bnx2x_handle_sp_tq(sc);
4575                 status &= ~0x1;
4576         }
4577
4578         if (unlikely(status)) {
4579                 PMD_DRV_LOG(WARNING,
4580                             "Unexpected fastpath status (0x%08x)!", status);
4581         }
4582
4583         return rc;
4584 }
4585
4586 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc);
4587 static int bnx2x_init_hw_common(struct bnx2x_softc *sc);
4588 static int bnx2x_init_hw_port(struct bnx2x_softc *sc);
4589 static int bnx2x_init_hw_func(struct bnx2x_softc *sc);
4590 static void bnx2x_reset_common(struct bnx2x_softc *sc);
4591 static void bnx2x_reset_port(struct bnx2x_softc *sc);
4592 static void bnx2x_reset_func(struct bnx2x_softc *sc);
4593 static int bnx2x_init_firmware(struct bnx2x_softc *sc);
4594 static void bnx2x_release_firmware(struct bnx2x_softc *sc);
4595
4596 static struct
4597 ecore_func_sp_drv_ops bnx2x_func_sp_drv = {
4598         .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
4599         .init_hw_cmn = bnx2x_init_hw_common,
4600         .init_hw_port = bnx2x_init_hw_port,
4601         .init_hw_func = bnx2x_init_hw_func,
4602
4603         .reset_hw_cmn = bnx2x_reset_common,
4604         .reset_hw_port = bnx2x_reset_port,
4605         .reset_hw_func = bnx2x_reset_func,
4606
4607         .init_fw = bnx2x_init_firmware,
4608         .release_fw = bnx2x_release_firmware,
4609 };
4610
4611 static void bnx2x_init_func_obj(struct bnx2x_softc *sc)
4612 {
4613         sc->dmae_ready = 0;
4614
4615         PMD_INIT_FUNC_TRACE();
4616
4617         ecore_init_func_obj(sc,
4618                             &sc->func_obj,
4619                             BNX2X_SP(sc, func_rdata),
4620                             (phys_addr_t)BNX2X_SP_MAPPING(sc, func_rdata),
4621                             BNX2X_SP(sc, func_afex_rdata),
4622                             (phys_addr_t)BNX2X_SP_MAPPING(sc, func_afex_rdata),
4623                             &bnx2x_func_sp_drv);
4624 }
4625
4626 static int bnx2x_init_hw(struct bnx2x_softc *sc, uint32_t load_code)
4627 {
4628         struct ecore_func_state_params func_params = { NULL };
4629         int rc;
4630
4631         PMD_INIT_FUNC_TRACE();
4632
4633         /* prepare the parameters for function state transitions */
4634         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
4635
4636         func_params.f_obj = &sc->func_obj;
4637         func_params.cmd = ECORE_F_CMD_HW_INIT;
4638
4639         func_params.params.hw_init.load_phase = load_code;
4640
4641         /*
4642          * Via a plethora of function pointers, we will eventually reach
4643          * bnx2x_init_hw_common(), bnx2x_init_hw_port(), or bnx2x_init_hw_func().
4644          */
4645         rc = ecore_func_state_change(sc, &func_params);
4646
4647         return rc;
4648 }
4649
4650 static void
4651 bnx2x_fill(struct bnx2x_softc *sc, uint32_t addr, int fill, uint32_t len)
4652 {
4653         uint32_t i;
4654
4655         if (!(len % 4) && !(addr % 4)) {
4656                 for (i = 0; i < len; i += 4) {
4657                         REG_WR(sc, (addr + i), fill);
4658                 }
4659         } else {
4660                 for (i = 0; i < len; i++) {
4661                         REG_WR8(sc, (addr + i), fill);
4662                 }
4663         }
4664 }
4665
4666 /* writes FP SP data to FW - data_size in dwords */
4667 static void
4668 bnx2x_wr_fp_sb_data(struct bnx2x_softc *sc, int fw_sb_id, uint32_t * sb_data_p,
4669                   uint32_t data_size)
4670 {
4671         uint32_t index;
4672
4673         for (index = 0; index < data_size; index++) {
4674                 REG_WR(sc,
4675                        (BAR_CSTRORM_INTMEM +
4676                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
4677                         (sizeof(uint32_t) * index)), *(sb_data_p + index));
4678         }
4679 }
4680
4681 static void bnx2x_zero_fp_sb(struct bnx2x_softc *sc, int fw_sb_id)
4682 {
4683         struct hc_status_block_data_e2 sb_data_e2;
4684         struct hc_status_block_data_e1x sb_data_e1x;
4685         uint32_t *sb_data_p;
4686         uint32_t data_size = 0;
4687
4688         if (!CHIP_IS_E1x(sc)) {
4689                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4690                 sb_data_e2.common.state = SB_DISABLED;
4691                 sb_data_e2.common.p_func.vf_valid = FALSE;
4692                 sb_data_p = (uint32_t *) & sb_data_e2;
4693                 data_size = (sizeof(struct hc_status_block_data_e2) /
4694                              sizeof(uint32_t));
4695         } else {
4696                 memset(&sb_data_e1x, 0,
4697                        sizeof(struct hc_status_block_data_e1x));
4698                 sb_data_e1x.common.state = SB_DISABLED;
4699                 sb_data_e1x.common.p_func.vf_valid = FALSE;
4700                 sb_data_p = (uint32_t *) & sb_data_e1x;
4701                 data_size = (sizeof(struct hc_status_block_data_e1x) /
4702                              sizeof(uint32_t));
4703         }
4704
4705         bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4706
4707         bnx2x_fill(sc,
4708                  (BAR_CSTRORM_INTMEM + CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id)), 0,
4709                  CSTORM_STATUS_BLOCK_SIZE);
4710         bnx2x_fill(sc, (BAR_CSTRORM_INTMEM + CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id)),
4711                  0, CSTORM_SYNC_BLOCK_SIZE);
4712 }
4713
4714 static void
4715 bnx2x_wr_sp_sb_data(struct bnx2x_softc *sc,
4716                   struct hc_sp_status_block_data *sp_sb_data)
4717 {
4718         uint32_t i;
4719
4720         for (i = 0;
4721              i < (sizeof(struct hc_sp_status_block_data) / sizeof(uint32_t));
4722              i++) {
4723                 REG_WR(sc,
4724                        (BAR_CSTRORM_INTMEM +
4725                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(SC_FUNC(sc)) +
4726                         (i * sizeof(uint32_t))),
4727                        *((uint32_t *) sp_sb_data + i));
4728         }
4729 }
4730
4731 static void bnx2x_zero_sp_sb(struct bnx2x_softc *sc)
4732 {
4733         struct hc_sp_status_block_data sp_sb_data;
4734
4735         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4736
4737         sp_sb_data.state = SB_DISABLED;
4738         sp_sb_data.p_func.vf_valid = FALSE;
4739
4740         bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
4741
4742         bnx2x_fill(sc,
4743                  (BAR_CSTRORM_INTMEM +
4744                   CSTORM_SP_STATUS_BLOCK_OFFSET(SC_FUNC(sc))),
4745                  0, CSTORM_SP_STATUS_BLOCK_SIZE);
4746         bnx2x_fill(sc,
4747                  (BAR_CSTRORM_INTMEM +
4748                   CSTORM_SP_SYNC_BLOCK_OFFSET(SC_FUNC(sc))),
4749                  0, CSTORM_SP_SYNC_BLOCK_SIZE);
4750 }
4751
4752 static void
4753 bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, int igu_sb_id,
4754                              int igu_seg_id)
4755 {
4756         hc_sm->igu_sb_id = igu_sb_id;
4757         hc_sm->igu_seg_id = igu_seg_id;
4758         hc_sm->timer_value = 0xFF;
4759         hc_sm->time_to_expire = 0xFFFFFFFF;
4760 }
4761
4762 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
4763 {
4764         /* zero out state machine indices */
4765
4766         /* rx indices */
4767         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4768
4769         /* tx indices */
4770         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4771         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
4772         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
4773         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
4774
4775         /* map indices */
4776
4777         /* rx indices */
4778         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
4779             (SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4780
4781         /* tx indices */
4782         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
4783             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4784         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
4785             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4786         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
4787             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4788         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
4789             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4790 }
4791
4792 static void
4793 bnx2x_init_sb(struct bnx2x_softc *sc, phys_addr_t busaddr, int vfid,
4794             uint8_t vf_valid, int fw_sb_id, int igu_sb_id)
4795 {
4796         struct hc_status_block_data_e2 sb_data_e2;
4797         struct hc_status_block_data_e1x sb_data_e1x;
4798         struct hc_status_block_sm *hc_sm_p;
4799         uint32_t *sb_data_p;
4800         int igu_seg_id;
4801         int data_size;
4802
4803         if (CHIP_INT_MODE_IS_BC(sc)) {
4804                 igu_seg_id = HC_SEG_ACCESS_NORM;
4805         } else {
4806                 igu_seg_id = IGU_SEG_ACCESS_NORM;
4807         }
4808
4809         bnx2x_zero_fp_sb(sc, fw_sb_id);
4810
4811         if (!CHIP_IS_E1x(sc)) {
4812                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4813                 sb_data_e2.common.state = SB_ENABLED;
4814                 sb_data_e2.common.p_func.pf_id = SC_FUNC(sc);
4815                 sb_data_e2.common.p_func.vf_id = vfid;
4816                 sb_data_e2.common.p_func.vf_valid = vf_valid;
4817                 sb_data_e2.common.p_func.vnic_id = SC_VN(sc);
4818                 sb_data_e2.common.same_igu_sb_1b = TRUE;
4819                 sb_data_e2.common.host_sb_addr.hi = U64_HI(busaddr);
4820                 sb_data_e2.common.host_sb_addr.lo = U64_LO(busaddr);
4821                 hc_sm_p = sb_data_e2.common.state_machine;
4822                 sb_data_p = (uint32_t *) & sb_data_e2;
4823                 data_size = (sizeof(struct hc_status_block_data_e2) /
4824                              sizeof(uint32_t));
4825                 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
4826         } else {
4827                 memset(&sb_data_e1x, 0,
4828                        sizeof(struct hc_status_block_data_e1x));
4829                 sb_data_e1x.common.state = SB_ENABLED;
4830                 sb_data_e1x.common.p_func.pf_id = SC_FUNC(sc);
4831                 sb_data_e1x.common.p_func.vf_id = 0xff;
4832                 sb_data_e1x.common.p_func.vf_valid = FALSE;
4833                 sb_data_e1x.common.p_func.vnic_id = SC_VN(sc);
4834                 sb_data_e1x.common.same_igu_sb_1b = TRUE;
4835                 sb_data_e1x.common.host_sb_addr.hi = U64_HI(busaddr);
4836                 sb_data_e1x.common.host_sb_addr.lo = U64_LO(busaddr);
4837                 hc_sm_p = sb_data_e1x.common.state_machine;
4838                 sb_data_p = (uint32_t *) & sb_data_e1x;
4839                 data_size = (sizeof(struct hc_status_block_data_e1x) /
4840                              sizeof(uint32_t));
4841                 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
4842         }
4843
4844         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], igu_sb_id, igu_seg_id);
4845         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], igu_sb_id, igu_seg_id);
4846
4847         /* write indices to HW - PCI guarantees endianity of regpairs */
4848         bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4849 }
4850
4851 static uint8_t bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp)
4852 {
4853         if (CHIP_IS_E1x(fp->sc)) {
4854                 return fp->cl_id + SC_PORT(fp->sc) * ETH_MAX_RX_CLIENTS_E1H;
4855         } else {
4856                 return fp->cl_id;
4857         }
4858 }
4859
4860 static uint32_t
4861 bnx2x_rx_ustorm_prods_offset(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
4862 {
4863         uint32_t offset = BAR_USTRORM_INTMEM;
4864
4865         if (IS_VF(sc)) {
4866                 return PXP_VF_ADDR_USDM_QUEUES_START +
4867                         (sc->acquire_resp.resc.hw_qid[fp->index] *
4868                          sizeof(struct ustorm_queue_zone_data));
4869         } else if (!CHIP_IS_E1x(sc)) {
4870                 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
4871         } else {
4872                 offset += USTORM_RX_PRODS_E1X_OFFSET(SC_PORT(sc), fp->cl_id);
4873         }
4874
4875         return offset;
4876 }
4877
4878 static void bnx2x_init_eth_fp(struct bnx2x_softc *sc, int idx)
4879 {
4880         struct bnx2x_fastpath *fp = &sc->fp[idx];
4881         uint32_t cids[ECORE_MULTI_TX_COS] = { 0 };
4882         unsigned long q_type = 0;
4883         int cos;
4884
4885         fp->sc = sc;
4886         fp->index = idx;
4887
4888         fp->igu_sb_id = (sc->igu_base_sb + idx + CNIC_SUPPORT(sc));
4889         fp->fw_sb_id = (sc->base_fw_ndsb + idx + CNIC_SUPPORT(sc));
4890
4891         if (CHIP_IS_E1x(sc))
4892                 fp->cl_id = SC_L_ID(sc) + idx;
4893         else
4894 /* want client ID same as IGU SB ID for non-E1 */
4895                 fp->cl_id = fp->igu_sb_id;
4896         fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
4897
4898         /* setup sb indices */
4899         if (!CHIP_IS_E1x(sc)) {
4900                 fp->sb_index_values = fp->status_block.e2_sb->sb.index_values;
4901                 fp->sb_running_index = fp->status_block.e2_sb->sb.running_index;
4902         } else {
4903                 fp->sb_index_values = fp->status_block.e1x_sb->sb.index_values;
4904                 fp->sb_running_index =
4905                     fp->status_block.e1x_sb->sb.running_index;
4906         }
4907
4908         /* init shortcut */
4909         fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(sc, fp);
4910
4911         fp->rx_cq_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS];
4912
4913         for (cos = 0; cos < sc->max_cos; cos++) {
4914                 cids[cos] = idx;
4915         }
4916         fp->tx_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0];
4917
4918         /* nothing more for a VF to do */
4919         if (IS_VF(sc)) {
4920                 return;
4921         }
4922
4923         bnx2x_init_sb(sc, fp->sb_dma.paddr, BNX2X_VF_ID_INVALID, FALSE,
4924                     fp->fw_sb_id, fp->igu_sb_id);
4925
4926         bnx2x_update_fp_sb_idx(fp);
4927
4928         /* Configure Queue State object */
4929         bnx2x_set_bit(ECORE_Q_TYPE_HAS_RX, &q_type);
4930         bnx2x_set_bit(ECORE_Q_TYPE_HAS_TX, &q_type);
4931
4932         ecore_init_queue_obj(sc,
4933                              &sc->sp_objs[idx].q_obj,
4934                              fp->cl_id,
4935                              cids,
4936                              sc->max_cos,
4937                              SC_FUNC(sc),
4938                              BNX2X_SP(sc, q_rdata),
4939                              (phys_addr_t)BNX2X_SP_MAPPING(sc, q_rdata),
4940                              q_type);
4941
4942         /* configure classification DBs */
4943         ecore_init_mac_obj(sc,
4944                            &sc->sp_objs[idx].mac_obj,
4945                            fp->cl_id,
4946                            idx,
4947                            SC_FUNC(sc),
4948                            BNX2X_SP(sc, mac_rdata),
4949                            (phys_addr_t)BNX2X_SP_MAPPING(sc, mac_rdata),
4950                            ECORE_FILTER_MAC_PENDING, &sc->sp_state,
4951                            ECORE_OBJ_TYPE_RX_TX, &sc->macs_pool);
4952 }
4953
4954 static void
4955 bnx2x_update_rx_prod(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
4956                    uint16_t rx_bd_prod, uint16_t rx_cq_prod)
4957 {
4958         union ustorm_eth_rx_producers rx_prods;
4959         uint32_t i;
4960
4961         /* update producers */
4962         rx_prods.prod.bd_prod = rx_bd_prod;
4963         rx_prods.prod.cqe_prod = rx_cq_prod;
4964         rx_prods.prod.reserved = 0;
4965
4966         /*
4967          * Make sure that the BD and SGE data is updated before updating the
4968          * producers since FW might read the BD/SGE right after the producer
4969          * is updated.
4970          * This is only applicable for weak-ordered memory model archs such
4971          * as IA-64. The following barrier is also mandatory since FW will
4972          * assumes BDs must have buffers.
4973          */
4974         wmb();
4975
4976         for (i = 0; i < (sizeof(rx_prods) / 4); i++) {
4977                 REG_WR(sc,
4978                        (fp->ustorm_rx_prods_offset + (i * 4)),
4979                        rx_prods.raw_data[i]);
4980         }
4981
4982         wmb();                  /* keep prod updates ordered */
4983 }
4984
4985 static void bnx2x_init_rx_rings(struct bnx2x_softc *sc)
4986 {
4987         struct bnx2x_fastpath *fp;
4988         int i;
4989         struct bnx2x_rx_queue *rxq;
4990
4991         for (i = 0; i < sc->num_queues; i++) {
4992                 fp = &sc->fp[i];
4993                 rxq = sc->rx_queues[fp->index];
4994                 if (!rxq) {
4995                         PMD_RX_LOG(ERR, "RX queue is NULL");
4996                         return;
4997                 }
4998
4999                 rxq->rx_bd_head = 0;
5000                 rxq->rx_bd_tail = rxq->nb_rx_desc;
5001                 rxq->rx_cq_head = 0;
5002                 rxq->rx_cq_tail = TOTAL_RCQ_ENTRIES(rxq);
5003                 *fp->rx_cq_cons_sb = 0;
5004
5005                 /*
5006                  * Activate the BD ring...
5007                  * Warning, this will generate an interrupt (to the TSTORM)
5008                  * so this can only be done after the chip is initialized
5009                  */
5010                 bnx2x_update_rx_prod(sc, fp, rxq->rx_bd_tail, rxq->rx_cq_tail);
5011
5012                 if (i != 0) {
5013                         continue;
5014                 }
5015         }
5016 }
5017
5018 static void bnx2x_init_tx_ring_one(struct bnx2x_fastpath *fp)
5019 {
5020         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
5021
5022         fp->tx_db.data.header.header = 1 << DOORBELL_HDR_DB_TYPE_SHIFT;
5023         fp->tx_db.data.zero_fill1 = 0;
5024         fp->tx_db.data.prod = 0;
5025
5026         if (!txq) {
5027                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
5028                 return;
5029         }
5030
5031         txq->tx_pkt_tail = 0;
5032         txq->tx_pkt_head = 0;
5033         txq->tx_bd_tail = 0;
5034         txq->tx_bd_head = 0;
5035 }
5036
5037 static void bnx2x_init_tx_rings(struct bnx2x_softc *sc)
5038 {
5039         int i;
5040
5041         for (i = 0; i < sc->num_queues; i++) {
5042                 bnx2x_init_tx_ring_one(&sc->fp[i]);
5043         }
5044 }
5045
5046 static void bnx2x_init_def_sb(struct bnx2x_softc *sc)
5047 {
5048         struct host_sp_status_block *def_sb = sc->def_sb;
5049         phys_addr_t mapping = sc->def_sb_dma.paddr;
5050         int igu_sp_sb_index;
5051         int igu_seg_id;
5052         int port = SC_PORT(sc);
5053         int func = SC_FUNC(sc);
5054         int reg_offset, reg_offset_en5;
5055         uint64_t section;
5056         int index, sindex;
5057         struct hc_sp_status_block_data sp_sb_data;
5058
5059         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5060
5061         if (CHIP_INT_MODE_IS_BC(sc)) {
5062                 igu_sp_sb_index = DEF_SB_IGU_ID;
5063                 igu_seg_id = HC_SEG_ACCESS_DEF;
5064         } else {
5065                 igu_sp_sb_index = sc->igu_dsb_id;
5066                 igu_seg_id = IGU_SEG_ACCESS_DEF;
5067         }
5068
5069         /* attentions */
5070         section = ((uint64_t) mapping +
5071                    offsetof(struct host_sp_status_block, atten_status_block));
5072         def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5073         sc->attn_state = 0;
5074
5075         reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5076             MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
5077
5078         reg_offset_en5 = (port) ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5079             MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0;
5080
5081         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5082 /* take care of sig[0]..sig[4] */
5083                 for (sindex = 0; sindex < 4; sindex++) {
5084                         sc->attn_group[index].sig[sindex] =
5085                             REG_RD(sc,
5086                                    (reg_offset + (sindex * 0x4) +
5087                                     (0x10 * index)));
5088                 }
5089
5090                 if (!CHIP_IS_E1x(sc)) {
5091                         /*
5092                          * enable5 is separate from the rest of the registers,
5093                          * and the address skip is 4 and not 16 between the
5094                          * different groups
5095                          */
5096                         sc->attn_group[index].sig[4] =
5097                             REG_RD(sc, (reg_offset_en5 + (0x4 * index)));
5098                 } else {
5099                         sc->attn_group[index].sig[4] = 0;
5100                 }
5101         }
5102
5103         if (sc->devinfo.int_block == INT_BLOCK_HC) {
5104                 reg_offset =
5105                     port ? HC_REG_ATTN_MSG1_ADDR_L : HC_REG_ATTN_MSG0_ADDR_L;
5106                 REG_WR(sc, reg_offset, U64_LO(section));
5107                 REG_WR(sc, (reg_offset + 4), U64_HI(section));
5108         } else if (!CHIP_IS_E1x(sc)) {
5109                 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5110                 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5111         }
5112
5113         section = ((uint64_t) mapping +
5114                    offsetof(struct host_sp_status_block, sp_sb));
5115
5116         bnx2x_zero_sp_sb(sc);
5117
5118         /* PCI guarantees endianity of regpair */
5119         sp_sb_data.state = SB_ENABLED;
5120         sp_sb_data.host_sb_addr.lo = U64_LO(section);
5121         sp_sb_data.host_sb_addr.hi = U64_HI(section);
5122         sp_sb_data.igu_sb_id = igu_sp_sb_index;
5123         sp_sb_data.igu_seg_id = igu_seg_id;
5124         sp_sb_data.p_func.pf_id = func;
5125         sp_sb_data.p_func.vnic_id = SC_VN(sc);
5126         sp_sb_data.p_func.vf_id = 0xff;
5127
5128         bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
5129
5130         bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5131 }
5132
5133 static void bnx2x_init_sp_ring(struct bnx2x_softc *sc)
5134 {
5135         atomic_store_rel_long(&sc->cq_spq_left, MAX_SPQ_PENDING);
5136         sc->spq_prod_idx = 0;
5137         sc->dsb_sp_prod =
5138             &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_ETH_DEF_CONS];
5139         sc->spq_prod_bd = sc->spq;
5140         sc->spq_last_bd = (sc->spq_prod_bd + MAX_SP_DESC_CNT);
5141 }
5142
5143 static void bnx2x_init_eq_ring(struct bnx2x_softc *sc)
5144 {
5145         union event_ring_elem *elem;
5146         int i;
5147
5148         for (i = 1; i <= NUM_EQ_PAGES; i++) {
5149                 elem = &sc->eq[EQ_DESC_CNT_PAGE * i - 1];
5150
5151                 elem->next_page.addr.hi = htole32(U64_HI(sc->eq_dma.paddr +
5152                                                          BNX2X_PAGE_SIZE *
5153                                                          (i % NUM_EQ_PAGES)));
5154                 elem->next_page.addr.lo = htole32(U64_LO(sc->eq_dma.paddr +
5155                                                          BNX2X_PAGE_SIZE *
5156                                                          (i % NUM_EQ_PAGES)));
5157         }
5158
5159         sc->eq_cons = 0;
5160         sc->eq_prod = NUM_EQ_DESC;
5161         sc->eq_cons_sb = &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_EQ_CONS];
5162
5163         atomic_store_rel_long(&sc->eq_spq_left,
5164                               (min((MAX_SP_DESC_CNT - MAX_SPQ_PENDING),
5165                                    NUM_EQ_DESC) - 1));
5166 }
5167
5168 static void bnx2x_init_internal_common(struct bnx2x_softc *sc)
5169 {
5170         int i;
5171
5172         if (IS_MF_SI(sc)) {
5173 /*
5174  * In switch independent mode, the TSTORM needs to accept
5175  * packets that failed classification, since approximate match
5176  * mac addresses aren't written to NIG LLH.
5177  */
5178                 REG_WR8(sc,
5179                         (BAR_TSTRORM_INTMEM +
5180                          TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 2);
5181         } else
5182                 REG_WR8(sc,
5183                         (BAR_TSTRORM_INTMEM +
5184                          TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 0);
5185
5186         /*
5187          * Zero this manually as its initialization is currently missing
5188          * in the initTool.
5189          */
5190         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) {
5191                 REG_WR(sc,
5192                        (BAR_USTRORM_INTMEM + USTORM_AGG_DATA_OFFSET + (i * 4)),
5193                        0);
5194         }
5195
5196         if (!CHIP_IS_E1x(sc)) {
5197                 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET),
5198                         CHIP_INT_MODE_IS_BC(sc) ? HC_IGU_BC_MODE :
5199                         HC_IGU_NBC_MODE);
5200         }
5201 }
5202
5203 static void bnx2x_init_internal(struct bnx2x_softc *sc, uint32_t load_code)
5204 {
5205         switch (load_code) {
5206         case FW_MSG_CODE_DRV_LOAD_COMMON:
5207         case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5208                 bnx2x_init_internal_common(sc);
5209                 /* no break */
5210
5211         case FW_MSG_CODE_DRV_LOAD_PORT:
5212                 /* nothing to do */
5213                 /* no break */
5214
5215         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5216                 /* internal memory per function is initialized inside bnx2x_pf_init */
5217                 break;
5218
5219         default:
5220                 PMD_DRV_LOG(NOTICE, "Unknown load_code (0x%x) from MCP",
5221                             load_code);
5222                 break;
5223         }
5224 }
5225
5226 static void
5227 storm_memset_func_cfg(struct bnx2x_softc *sc,
5228                       struct tstorm_eth_function_common_config *tcfg,
5229                       uint16_t abs_fid)
5230 {
5231         uint32_t addr;
5232         size_t size;
5233
5234         addr = (BAR_TSTRORM_INTMEM +
5235                 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid));
5236         size = sizeof(struct tstorm_eth_function_common_config);
5237         ecore_storm_memset_struct(sc, addr, size, (uint32_t *) tcfg);
5238 }
5239
5240 static void bnx2x_func_init(struct bnx2x_softc *sc, struct bnx2x_func_init_params *p)
5241 {
5242         struct tstorm_eth_function_common_config tcfg = { 0 };
5243
5244         if (CHIP_IS_E1x(sc)) {
5245                 storm_memset_func_cfg(sc, &tcfg, p->func_id);
5246         }
5247
5248         /* Enable the function in the FW */
5249         storm_memset_vf_to_pf(sc, p->func_id, p->pf_id);
5250         storm_memset_func_en(sc, p->func_id, 1);
5251
5252         /* spq */
5253         if (p->func_flgs & FUNC_FLG_SPQ) {
5254                 storm_memset_spq_addr(sc, p->spq_map, p->func_id);
5255                 REG_WR(sc,
5256                        (XSEM_REG_FAST_MEMORY +
5257                         XSTORM_SPQ_PROD_OFFSET(p->func_id)), p->spq_prod);
5258         }
5259 }
5260
5261 /*
5262  * Calculates the sum of vn_min_rates.
5263  * It's needed for further normalizing of the min_rates.
5264  * Returns:
5265  *   sum of vn_min_rates.
5266  *     or
5267  *   0 - if all the min_rates are 0.
5268  * In the later case fainess algorithm should be deactivated.
5269  * If all min rates are not zero then those that are zeroes will be set to 1.
5270  */
5271 static void bnx2x_calc_vn_min(struct bnx2x_softc *sc, struct cmng_init_input *input)
5272 {
5273         uint32_t vn_cfg;
5274         uint32_t vn_min_rate;
5275         int all_zero = 1;
5276         int vn;
5277
5278         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5279                 vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5280                 vn_min_rate = (((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
5281                                 FUNC_MF_CFG_MIN_BW_SHIFT) * 100);
5282
5283                 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5284                         /* skip hidden VNs */
5285                         vn_min_rate = 0;
5286                 } else if (!vn_min_rate) {
5287                         /* If min rate is zero - set it to 100 */
5288                         vn_min_rate = DEF_MIN_RATE;
5289                 } else {
5290                         all_zero = 0;
5291                 }
5292
5293                 input->vnic_min_rate[vn] = vn_min_rate;
5294         }
5295
5296         /* if ETS or all min rates are zeros - disable fairness */
5297         if (all_zero) {
5298                 input->flags.cmng_enables &= ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5299         } else {
5300                 input->flags.cmng_enables |= CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5301         }
5302 }
5303
5304 static uint16_t
5305 bnx2x_extract_max_cfg(__rte_unused struct bnx2x_softc *sc, uint32_t mf_cfg)
5306 {
5307         uint16_t max_cfg = ((mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
5308                             FUNC_MF_CFG_MAX_BW_SHIFT);
5309
5310         if (!max_cfg) {
5311                 PMD_DRV_LOG(DEBUG,
5312                             "Max BW configured to 0 - using 100 instead");
5313                 max_cfg = 100;
5314         }
5315
5316         return max_cfg;
5317 }
5318
5319 static void
5320 bnx2x_calc_vn_max(struct bnx2x_softc *sc, int vn, struct cmng_init_input *input)
5321 {
5322         uint16_t vn_max_rate;
5323         uint32_t vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5324         uint32_t max_cfg;
5325
5326         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5327                 vn_max_rate = 0;
5328         } else {
5329                 max_cfg = bnx2x_extract_max_cfg(sc, vn_cfg);
5330
5331                 if (IS_MF_SI(sc)) {
5332                         /* max_cfg in percents of linkspeed */
5333                         vn_max_rate =
5334                             ((sc->link_vars.line_speed * max_cfg) / 100);
5335                 } else {        /* SD modes */
5336                         /* max_cfg is absolute in 100Mb units */
5337                         vn_max_rate = (max_cfg * 100);
5338                 }
5339         }
5340
5341         input->vnic_max_rate[vn] = vn_max_rate;
5342 }
5343
5344 static void
5345 bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg, uint8_t cmng_type)
5346 {
5347         struct cmng_init_input input;
5348         int vn;
5349
5350         memset(&input, 0, sizeof(struct cmng_init_input));
5351
5352         input.port_rate = sc->link_vars.line_speed;
5353
5354         if (cmng_type == CMNG_FNS_MINMAX) {
5355 /* read mf conf from shmem */
5356                 if (read_cfg) {
5357                         bnx2x_read_mf_cfg(sc);
5358                 }
5359
5360 /* get VN min rate and enable fairness if not 0 */
5361                 bnx2x_calc_vn_min(sc, &input);
5362
5363 /* get VN max rate */
5364                 if (sc->port.pmf) {
5365                         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5366                                 bnx2x_calc_vn_max(sc, vn, &input);
5367                         }
5368                 }
5369
5370 /* always enable rate shaping and fairness */
5371                 input.flags.cmng_enables |= CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
5372
5373                 ecore_init_cmng(&input, &sc->cmng);
5374                 return;
5375         }
5376 }
5377
5378 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc)
5379 {
5380         if (CHIP_REV_IS_SLOW(sc)) {
5381                 return CMNG_FNS_NONE;
5382         }
5383
5384         if (IS_MF(sc)) {
5385                 return CMNG_FNS_MINMAX;
5386         }
5387
5388         return CMNG_FNS_NONE;
5389 }
5390
5391 static void
5392 storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng, uint8_t port)
5393 {
5394         int vn;
5395         int func;
5396         uint32_t addr;
5397         size_t size;
5398
5399         addr = (BAR_XSTRORM_INTMEM + XSTORM_CMNG_PER_PORT_VARS_OFFSET(port));
5400         size = sizeof(struct cmng_struct_per_port);
5401         ecore_storm_memset_struct(sc, addr, size, (uint32_t *) & cmng->port);
5402
5403         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5404                 func = func_by_vn(sc, vn);
5405
5406                 addr = (BAR_XSTRORM_INTMEM +
5407                         XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func));
5408                 size = sizeof(struct rate_shaping_vars_per_vn);
5409                 ecore_storm_memset_struct(sc, addr, size,
5410                                           (uint32_t *) & cmng->
5411                                           vnic.vnic_max_rate[vn]);
5412
5413                 addr = (BAR_XSTRORM_INTMEM +
5414                         XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func));
5415                 size = sizeof(struct fairness_vars_per_vn);
5416                 ecore_storm_memset_struct(sc, addr, size,
5417                                           (uint32_t *) & cmng->
5418                                           vnic.vnic_min_rate[vn]);
5419         }
5420 }
5421
5422 static void bnx2x_pf_init(struct bnx2x_softc *sc)
5423 {
5424         struct bnx2x_func_init_params func_init;
5425         struct event_ring_data eq_data;
5426         uint16_t flags;
5427
5428         memset(&eq_data, 0, sizeof(struct event_ring_data));
5429         memset(&func_init, 0, sizeof(struct bnx2x_func_init_params));
5430
5431         if (!CHIP_IS_E1x(sc)) {
5432 /* reset IGU PF statistics: MSIX + ATTN */
5433 /* PF */
5434                 REG_WR(sc,
5435                        (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5436                         (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5437                         ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5438                          4)), 0);
5439 /* ATTN */
5440                 REG_WR(sc,
5441                        (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5442                         (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5443                         (BNX2X_IGU_STAS_MSG_PF_CNT * 4) +
5444                         ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5445                          4)), 0);
5446         }
5447
5448         /* function setup flags */
5449         flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
5450
5451         func_init.func_flgs = flags;
5452         func_init.pf_id = SC_FUNC(sc);
5453         func_init.func_id = SC_FUNC(sc);
5454         func_init.spq_map = sc->spq_dma.paddr;
5455         func_init.spq_prod = sc->spq_prod_idx;
5456
5457         bnx2x_func_init(sc, &func_init);
5458
5459         memset(&sc->cmng, 0, sizeof(struct cmng_struct_per_port));
5460
5461         /*
5462          * Congestion management values depend on the link rate.
5463          * There is no active link so initial link rate is set to 10Gbps.
5464          * When the link comes up the congestion management values are
5465          * re-calculated according to the actual link rate.
5466          */
5467         sc->link_vars.line_speed = SPEED_10000;
5468         bnx2x_cmng_fns_init(sc, TRUE, bnx2x_get_cmng_fns_mode(sc));
5469
5470         /* Only the PMF sets the HW */
5471         if (sc->port.pmf) {
5472                 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
5473         }
5474
5475         /* init Event Queue - PCI bus guarantees correct endainity */
5476         eq_data.base_addr.hi = U64_HI(sc->eq_dma.paddr);
5477         eq_data.base_addr.lo = U64_LO(sc->eq_dma.paddr);
5478         eq_data.producer = sc->eq_prod;
5479         eq_data.index_id = HC_SP_INDEX_EQ_CONS;
5480         eq_data.sb_id = DEF_SB_ID;
5481         storm_memset_eq_data(sc, &eq_data, SC_FUNC(sc));
5482 }
5483
5484 static void bnx2x_hc_int_enable(struct bnx2x_softc *sc)
5485 {
5486         int port = SC_PORT(sc);
5487         uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5488         uint32_t val = REG_RD(sc, addr);
5489         uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5490             || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5491         uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5492         uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5493
5494         if (msix) {
5495                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5496                          HC_CONFIG_0_REG_INT_LINE_EN_0);
5497                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5498                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5499                 if (single_msix) {
5500                         val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
5501                 }
5502         } else if (msi) {
5503                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
5504                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5505                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5506                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5507         } else {
5508                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5509                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5510                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
5511                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5512
5513                 REG_WR(sc, addr, val);
5514
5515                 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
5516         }
5517
5518         REG_WR(sc, addr, val);
5519
5520         /* ensure that HC_CONFIG is written before leading/trailing edge config */
5521         mb();
5522
5523         /* init leading/trailing edge */
5524         if (IS_MF(sc)) {
5525                 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5526                 if (sc->port.pmf) {
5527                         /* enable nig and gpio3 attention */
5528                         val |= 0x1100;
5529                 }
5530         } else {
5531                 val = 0xffff;
5532         }
5533
5534         REG_WR(sc, (HC_REG_TRAILING_EDGE_0 + port * 8), val);
5535         REG_WR(sc, (HC_REG_LEADING_EDGE_0 + port * 8), val);
5536
5537         /* make sure that interrupts are indeed enabled from here on */
5538         mb();
5539 }
5540
5541 static void bnx2x_igu_int_enable(struct bnx2x_softc *sc)
5542 {
5543         uint32_t val;
5544         uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5545             || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5546         uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5547         uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5548
5549         val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5550
5551         if (msix) {
5552                 val &= ~(IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5553                 val |= (IGU_PF_CONF_MSI_MSIX_EN | IGU_PF_CONF_ATTN_BIT_EN);
5554                 if (single_msix) {
5555                         val |= IGU_PF_CONF_SINGLE_ISR_EN;
5556                 }
5557         } else if (msi) {
5558                 val &= ~IGU_PF_CONF_INT_LINE_EN;
5559                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
5560                         IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5561         } else {
5562                 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
5563                 val |= (IGU_PF_CONF_INT_LINE_EN |
5564                         IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5565         }
5566
5567         /* clean previous status - need to configure igu prior to ack */
5568         if ((!msix) || single_msix) {
5569                 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5570                 bnx2x_ack_int(sc);
5571         }
5572
5573         val |= IGU_PF_CONF_FUNC_EN;
5574
5575         PMD_DRV_LOG(DEBUG, "write 0x%x to IGU mode %s",
5576                     val, ((msix) ? "MSI-X" : ((msi) ? "MSI" : "INTx")));
5577
5578         REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5579
5580         mb();
5581
5582         /* init leading/trailing edge */
5583         if (IS_MF(sc)) {
5584                 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5585                 if (sc->port.pmf) {
5586                         /* enable nig and gpio3 attention */
5587                         val |= 0x1100;
5588                 }
5589         } else {
5590                 val = 0xffff;
5591         }
5592
5593         REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
5594         REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
5595
5596         /* make sure that interrupts are indeed enabled from here on */
5597         mb();
5598 }
5599
5600 static void bnx2x_int_enable(struct bnx2x_softc *sc)
5601 {
5602         if (sc->devinfo.int_block == INT_BLOCK_HC) {
5603                 bnx2x_hc_int_enable(sc);
5604         } else {
5605                 bnx2x_igu_int_enable(sc);
5606         }
5607 }
5608
5609 static void bnx2x_hc_int_disable(struct bnx2x_softc *sc)
5610 {
5611         int port = SC_PORT(sc);
5612         uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5613         uint32_t val = REG_RD(sc, addr);
5614
5615         val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5616                  HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5617                  HC_CONFIG_0_REG_INT_LINE_EN_0 | HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5618         /* flush all outstanding writes */
5619         mb();
5620
5621         REG_WR(sc, addr, val);
5622         if (REG_RD(sc, addr) != val) {
5623                 PMD_DRV_LOG(ERR, "proper val not read from HC IGU!");
5624         }
5625 }
5626
5627 static void bnx2x_igu_int_disable(struct bnx2x_softc *sc)
5628 {
5629         uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5630
5631         val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
5632                  IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_ATTN_BIT_EN);
5633
5634         PMD_DRV_LOG(DEBUG, "write %x to IGU", val);
5635
5636         /* flush all outstanding writes */
5637         mb();
5638
5639         REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5640         if (REG_RD(sc, IGU_REG_PF_CONFIGURATION) != val) {
5641                 PMD_DRV_LOG(ERR, "proper val not read from IGU!");
5642         }
5643 }
5644
5645 static void bnx2x_int_disable(struct bnx2x_softc *sc)
5646 {
5647         if (sc->devinfo.int_block == INT_BLOCK_HC) {
5648                 bnx2x_hc_int_disable(sc);
5649         } else {
5650                 bnx2x_igu_int_disable(sc);
5651         }
5652 }
5653
5654 static void bnx2x_nic_init(struct bnx2x_softc *sc, int load_code)
5655 {
5656         int i;
5657
5658         PMD_INIT_FUNC_TRACE();
5659
5660         for (i = 0; i < sc->num_queues; i++) {
5661                 bnx2x_init_eth_fp(sc, i);
5662         }
5663
5664         rmb();                  /* ensure status block indices were read */
5665
5666         bnx2x_init_rx_rings(sc);
5667         bnx2x_init_tx_rings(sc);
5668
5669         if (IS_VF(sc)) {
5670                 bnx2x_memset_stats(sc);
5671                 return;
5672         }
5673
5674         /* initialize MOD_ABS interrupts */
5675         elink_init_mod_abs_int(sc, &sc->link_vars,
5676                                sc->devinfo.chip_id,
5677                                sc->devinfo.shmem_base,
5678                                sc->devinfo.shmem2_base, SC_PORT(sc));
5679
5680         bnx2x_init_def_sb(sc);
5681         bnx2x_update_dsb_idx(sc);
5682         bnx2x_init_sp_ring(sc);
5683         bnx2x_init_eq_ring(sc);
5684         bnx2x_init_internal(sc, load_code);
5685         bnx2x_pf_init(sc);
5686         bnx2x_stats_init(sc);
5687
5688         /* flush all before enabling interrupts */
5689         mb();
5690
5691         bnx2x_int_enable(sc);
5692
5693         /* check for SPIO5 */
5694         bnx2x_attn_int_deasserted0(sc,
5695                                  REG_RD(sc,
5696                                         (MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
5697                                          SC_PORT(sc) * 4)) &
5698                                  AEU_INPUTS_ATTN_BITS_SPIO5);
5699 }
5700
5701 static void bnx2x_init_objs(struct bnx2x_softc *sc)
5702 {
5703         /* mcast rules must be added to tx if tx switching is enabled */
5704         ecore_obj_type o_type;
5705         if (sc->flags & BNX2X_TX_SWITCHING)
5706                 o_type = ECORE_OBJ_TYPE_RX_TX;
5707         else
5708                 o_type = ECORE_OBJ_TYPE_RX;
5709
5710         /* RX_MODE controlling object */
5711         ecore_init_rx_mode_obj(sc, &sc->rx_mode_obj);
5712
5713         /* multicast configuration controlling object */
5714         ecore_init_mcast_obj(sc,
5715                              &sc->mcast_obj,
5716                              sc->fp[0].cl_id,
5717                              sc->fp[0].index,
5718                              SC_FUNC(sc),
5719                              SC_FUNC(sc),
5720                              BNX2X_SP(sc, mcast_rdata),
5721                              (phys_addr_t)BNX2X_SP_MAPPING(sc, mcast_rdata),
5722                              ECORE_FILTER_MCAST_PENDING,
5723                              &sc->sp_state, o_type);
5724
5725         /* Setup CAM credit pools */
5726         ecore_init_mac_credit_pool(sc,
5727                                    &sc->macs_pool,
5728                                    SC_FUNC(sc),
5729                                    CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5730                                    VNICS_PER_PATH(sc));
5731
5732         ecore_init_vlan_credit_pool(sc,
5733                                     &sc->vlans_pool,
5734                                     SC_ABS_FUNC(sc) >> 1,
5735                                     CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5736                                     VNICS_PER_PATH(sc));
5737
5738         /* RSS configuration object */
5739         ecore_init_rss_config_obj(&sc->rss_conf_obj,
5740                                   sc->fp[0].cl_id,
5741                                   sc->fp[0].index,
5742                                   SC_FUNC(sc),
5743                                   SC_FUNC(sc),
5744                                   BNX2X_SP(sc, rss_rdata),
5745                                   (phys_addr_t)BNX2X_SP_MAPPING(sc, rss_rdata),
5746                                   ECORE_FILTER_RSS_CONF_PENDING,
5747                                   &sc->sp_state, ECORE_OBJ_TYPE_RX);
5748 }
5749
5750 /*
5751  * Initialize the function. This must be called before sending CLIENT_SETUP
5752  * for the first client.
5753  */
5754 static int bnx2x_func_start(struct bnx2x_softc *sc)
5755 {
5756         struct ecore_func_state_params func_params = { NULL };
5757         struct ecore_func_start_params *start_params =
5758             &func_params.params.start;
5759
5760         /* Prepare parameters for function state transitions */
5761         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
5762
5763         func_params.f_obj = &sc->func_obj;
5764         func_params.cmd = ECORE_F_CMD_START;
5765
5766         /* Function parameters */
5767         start_params->mf_mode = sc->devinfo.mf_info.mf_mode;
5768         start_params->sd_vlan_tag = OVLAN(sc);
5769
5770         if (CHIP_IS_E2(sc) || CHIP_IS_E3(sc)) {
5771                 start_params->network_cos_mode = STATIC_COS;
5772         } else {                /* CHIP_IS_E1X */
5773                 start_params->network_cos_mode = FW_WRR;
5774         }
5775
5776         start_params->gre_tunnel_mode = 0;
5777         start_params->gre_tunnel_rss = 0;
5778
5779         return ecore_func_state_change(sc, &func_params);
5780 }
5781
5782 static int bnx2x_set_power_state(struct bnx2x_softc *sc, uint8_t state)
5783 {
5784         uint16_t pmcsr;
5785
5786         /* If there is no power capability, silently succeed */
5787         if (!(sc->devinfo.pcie_cap_flags & BNX2X_PM_CAPABLE_FLAG)) {
5788                 PMD_DRV_LOG(WARNING, "No power capability");
5789                 return 0;
5790         }
5791
5792         pci_read(sc, (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS), &pmcsr,
5793                  2);
5794
5795         switch (state) {
5796         case PCI_PM_D0:
5797                 pci_write_word(sc,
5798                                (sc->devinfo.pcie_pm_cap_reg +
5799                                 PCIR_POWER_STATUS),
5800                                ((pmcsr & ~PCIM_PSTAT_DMASK) | PCIM_PSTAT_PME));
5801
5802                 if (pmcsr & PCIM_PSTAT_DMASK) {
5803                         /* delay required during transition out of D3hot */
5804                         DELAY(20000);
5805                 }
5806
5807                 break;
5808
5809         case PCI_PM_D3hot:
5810                 /* don't shut down the power for emulation and FPGA */
5811                 if (CHIP_REV_IS_SLOW(sc)) {
5812                         return 0;
5813                 }
5814
5815                 pmcsr &= ~PCIM_PSTAT_DMASK;
5816                 pmcsr |= PCIM_PSTAT_D3;
5817
5818                 if (sc->wol) {
5819                         pmcsr |= PCIM_PSTAT_PMEENABLE;
5820                 }
5821
5822                 pci_write_long(sc,
5823                                (sc->devinfo.pcie_pm_cap_reg +
5824                                 PCIR_POWER_STATUS), pmcsr);
5825
5826                 /*
5827                  * No more memory access after this point until device is brought back
5828                  * to D0 state.
5829                  */
5830                 break;
5831
5832         default:
5833                 PMD_DRV_LOG(NOTICE, "Can't support PCI power state = %d",
5834                             state);
5835                 return -1;
5836         }
5837
5838         return 0;
5839 }
5840
5841 /* return true if succeeded to acquire the lock */
5842 static uint8_t bnx2x_trylock_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
5843 {
5844         uint32_t lock_status;
5845         uint32_t resource_bit = (1 << resource);
5846         int func = SC_FUNC(sc);
5847         uint32_t hw_lock_control_reg;
5848
5849         /* Validating that the resource is within range */
5850         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
5851                 PMD_DRV_LOG(INFO,
5852                             "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)",
5853                             resource, HW_LOCK_MAX_RESOURCE_VALUE);
5854                 return FALSE;
5855         }
5856
5857         if (func <= 5) {
5858                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func * 8);
5859         } else {
5860                 hw_lock_control_reg =
5861                     (MISC_REG_DRIVER_CONTROL_7 + (func - 6) * 8);
5862         }
5863
5864         /* try to acquire the lock */
5865         REG_WR(sc, hw_lock_control_reg + 4, resource_bit);
5866         lock_status = REG_RD(sc, hw_lock_control_reg);
5867         if (lock_status & resource_bit) {
5868                 return TRUE;
5869         }
5870
5871         PMD_DRV_LOG(NOTICE, "Failed to get a resource lock 0x%x", resource);
5872
5873         return FALSE;
5874 }
5875
5876 /*
5877  * Get the recovery leader resource id according to the engine this function
5878  * belongs to. Currently only only 2 engines is supported.
5879  */
5880 static int bnx2x_get_leader_lock_resource(struct bnx2x_softc *sc)
5881 {
5882         if (SC_PATH(sc)) {
5883                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
5884         } else {
5885                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
5886         }
5887 }
5888
5889 /* try to acquire a leader lock for current engine */
5890 static uint8_t bnx2x_trylock_leader_lock(struct bnx2x_softc *sc)
5891 {
5892         return bnx2x_trylock_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5893 }
5894
5895 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc)
5896 {
5897         return bnx2x_release_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5898 }
5899
5900 /* close gates #2, #3 and #4 */
5901 static void bnx2x_set_234_gates(struct bnx2x_softc *sc, uint8_t close)
5902 {
5903         uint32_t val;
5904
5905         /* gates #2 and #4a are closed/opened */
5906         /* #4 */
5907         REG_WR(sc, PXP_REG_HST_DISCARD_DOORBELLS, ! !close);
5908         /* #2 */
5909         REG_WR(sc, PXP_REG_HST_DISCARD_INTERNAL_WRITES, ! !close);
5910
5911         /* #3 */
5912         if (CHIP_IS_E1x(sc)) {
5913 /* prevent interrupts from HC on both ports */
5914                 val = REG_RD(sc, HC_REG_CONFIG_1);
5915                 if (close)
5916                         REG_WR(sc, HC_REG_CONFIG_1, (val & ~(uint32_t)
5917                                                      HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5918                 else
5919                         REG_WR(sc, HC_REG_CONFIG_1,
5920                                (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5921
5922                 val = REG_RD(sc, HC_REG_CONFIG_0);
5923                 if (close)
5924                         REG_WR(sc, HC_REG_CONFIG_0, (val & ~(uint32_t)
5925                                                      HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5926                 else
5927                         REG_WR(sc, HC_REG_CONFIG_0,
5928                                (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5929
5930         } else {
5931 /* Prevent incomming interrupts in IGU */
5932                 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
5933
5934                 if (close)
5935                         REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5936                                (val & ~(uint32_t)
5937                                 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5938                 else
5939                         REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5940                                (val |
5941                                 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5942         }
5943
5944         wmb();
5945 }
5946
5947 /* poll for pending writes bit, it should get cleared in no more than 1s */
5948 static int bnx2x_er_poll_igu_vq(struct bnx2x_softc *sc)
5949 {
5950         uint32_t cnt = 1000;
5951         uint32_t pend_bits = 0;
5952
5953         do {
5954                 pend_bits = REG_RD(sc, IGU_REG_PENDING_BITS_STATUS);
5955
5956                 if (pend_bits == 0) {
5957                         break;
5958                 }
5959
5960                 DELAY(1000);
5961         } while (cnt-- > 0);
5962
5963         if (cnt <= 0) {
5964                 PMD_DRV_LOG(NOTICE, "Still pending IGU requests bits=0x%08x!",
5965                             pend_bits);
5966                 return -1;
5967         }
5968
5969         return 0;
5970 }
5971
5972 #define SHARED_MF_CLP_MAGIC  0x80000000 /* 'magic' bit */
5973
5974 static void bnx2x_clp_reset_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
5975 {
5976         /* Do some magic... */
5977         uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
5978         *magic_val = val & SHARED_MF_CLP_MAGIC;
5979         MFCFG_WR(sc, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
5980 }
5981
5982 /* restore the value of the 'magic' bit */
5983 static void bnx2x_clp_reset_done(struct bnx2x_softc *sc, uint32_t magic_val)
5984 {
5985         /* Restore the 'magic' bit value... */
5986         uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
5987         MFCFG_WR(sc, shared_mf_config.clp_mb,
5988                  (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
5989 }
5990
5991 /* prepare for MCP reset, takes care of CLP configurations */
5992 static void bnx2x_reset_mcp_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
5993 {
5994         uint32_t shmem;
5995         uint32_t validity_offset;
5996
5997         /* set `magic' bit in order to save MF config */
5998         bnx2x_clp_reset_prep(sc, magic_val);
5999
6000         /* get shmem offset */
6001         shmem = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
6002         validity_offset =
6003             offsetof(struct shmem_region, validity_map[SC_PORT(sc)]);
6004
6005         /* Clear validity map flags */
6006         if (shmem > 0) {
6007                 REG_WR(sc, shmem + validity_offset, 0);
6008         }
6009 }
6010
6011 #define MCP_TIMEOUT      5000   /* 5 seconds (in ms) */
6012 #define MCP_ONE_TIMEOUT  100    /* 100 ms */
6013
6014 static void bnx2x_mcp_wait_one(struct bnx2x_softc *sc)
6015 {
6016         /* special handling for emulation and FPGA (10 times longer) */
6017         if (CHIP_REV_IS_SLOW(sc)) {
6018                 DELAY((MCP_ONE_TIMEOUT * 10) * 1000);
6019         } else {
6020                 DELAY((MCP_ONE_TIMEOUT) * 1000);
6021         }
6022 }
6023
6024 /* initialize shmem_base and waits for validity signature to appear */
6025 static int bnx2x_init_shmem(struct bnx2x_softc *sc)
6026 {
6027         int cnt = 0;
6028         uint32_t val = 0;
6029
6030         do {
6031                 sc->devinfo.shmem_base =
6032                     sc->link_params.shmem_base =
6033                     REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
6034
6035                 if (sc->devinfo.shmem_base) {
6036                         val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
6037                         if (val & SHR_MEM_VALIDITY_MB)
6038                                 return 0;
6039                 }
6040
6041                 bnx2x_mcp_wait_one(sc);
6042
6043         } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
6044
6045         PMD_DRV_LOG(NOTICE, "BAD MCP validity signature");
6046
6047         return -1;
6048 }
6049
6050 static int bnx2x_reset_mcp_comp(struct bnx2x_softc *sc, uint32_t magic_val)
6051 {
6052         int rc = bnx2x_init_shmem(sc);
6053
6054         /* Restore the `magic' bit value */
6055         bnx2x_clp_reset_done(sc, magic_val);
6056
6057         return rc;
6058 }
6059
6060 static void bnx2x_pxp_prep(struct bnx2x_softc *sc)
6061 {
6062         REG_WR(sc, PXP2_REG_RD_START_INIT, 0);
6063         REG_WR(sc, PXP2_REG_RQ_RBC_DONE, 0);
6064         wmb();
6065 }
6066
6067 /*
6068  * Reset the whole chip except for:
6069  *      - PCIE core
6070  *      - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by one reset bit)
6071  *      - IGU
6072  *      - MISC (including AEU)
6073  *      - GRC
6074  *      - RBCN, RBCP
6075  */
6076 static void bnx2x_process_kill_chip_reset(struct bnx2x_softc *sc, uint8_t global)
6077 {
6078         uint32_t not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
6079         uint32_t global_bits2, stay_reset2;
6080
6081         /*
6082          * Bits that have to be set in reset_mask2 if we want to reset 'global'
6083          * (per chip) blocks.
6084          */
6085         global_bits2 =
6086             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
6087             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
6088
6089         /*
6090          * Don't reset the following blocks.
6091          * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
6092          *            reset, as in 4 port device they might still be owned
6093          *            by the MCP (there is only one leader per path).
6094          */
6095         not_reset_mask1 =
6096             MISC_REGISTERS_RESET_REG_1_RST_HC |
6097             MISC_REGISTERS_RESET_REG_1_RST_PXPV |
6098             MISC_REGISTERS_RESET_REG_1_RST_PXP;
6099
6100         not_reset_mask2 =
6101             MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
6102             MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
6103             MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
6104             MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
6105             MISC_REGISTERS_RESET_REG_2_RST_RBCN |
6106             MISC_REGISTERS_RESET_REG_2_RST_GRC |
6107             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
6108             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
6109             MISC_REGISTERS_RESET_REG_2_RST_ATC |
6110             MISC_REGISTERS_RESET_REG_2_PGLC |
6111             MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
6112             MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
6113             MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
6114             MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
6115             MISC_REGISTERS_RESET_REG_2_UMAC0 | MISC_REGISTERS_RESET_REG_2_UMAC1;
6116
6117         /*
6118          * Keep the following blocks in reset:
6119          *  - all xxMACs are handled by the elink code.
6120          */
6121         stay_reset2 =
6122             MISC_REGISTERS_RESET_REG_2_XMAC |
6123             MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
6124
6125         /* Full reset masks according to the chip */
6126         reset_mask1 = 0xffffffff;
6127
6128         if (CHIP_IS_E1H(sc))
6129                 reset_mask2 = 0x1ffff;
6130         else if (CHIP_IS_E2(sc))
6131                 reset_mask2 = 0xfffff;
6132         else                    /* CHIP_IS_E3 */
6133                 reset_mask2 = 0x3ffffff;
6134
6135         /* Don't reset global blocks unless we need to */
6136         if (!global)
6137                 reset_mask2 &= ~global_bits2;
6138
6139         /*
6140          * In case of attention in the QM, we need to reset PXP
6141          * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
6142          * because otherwise QM reset would release 'close the gates' shortly
6143          * before resetting the PXP, then the PSWRQ would send a write
6144          * request to PGLUE. Then when PXP is reset, PGLUE would try to
6145          * read the payload data from PSWWR, but PSWWR would not
6146          * respond. The write queue in PGLUE would stuck, dmae commands
6147          * would not return. Therefore it's important to reset the second
6148          * reset register (containing the
6149          * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
6150          * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
6151          * bit).
6152          */
6153         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
6154                reset_mask2 & (~not_reset_mask2));
6155
6156         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6157                reset_mask1 & (~not_reset_mask1));
6158
6159         mb();
6160         wmb();
6161
6162         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
6163                reset_mask2 & (~stay_reset2));
6164
6165         mb();
6166         wmb();
6167
6168         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
6169         wmb();
6170 }
6171
6172 static int bnx2x_process_kill(struct bnx2x_softc *sc, uint8_t global)
6173 {
6174         int cnt = 1000;
6175         uint32_t val = 0;
6176         uint32_t sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
6177         uint32_t tags_63_32 = 0;
6178
6179         /* Empty the Tetris buffer, wait for 1s */
6180         do {
6181                 sr_cnt = REG_RD(sc, PXP2_REG_RD_SR_CNT);
6182                 blk_cnt = REG_RD(sc, PXP2_REG_RD_BLK_CNT);
6183                 port_is_idle_0 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_0);
6184                 port_is_idle_1 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_1);
6185                 pgl_exp_rom2 = REG_RD(sc, PXP2_REG_PGL_EXP_ROM2);
6186                 if (CHIP_IS_E3(sc)) {
6187                         tags_63_32 = REG_RD(sc, PGLUE_B_REG_TAGS_63_32);
6188                 }
6189
6190                 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
6191                     ((port_is_idle_0 & 0x1) == 0x1) &&
6192                     ((port_is_idle_1 & 0x1) == 0x1) &&
6193                     (pgl_exp_rom2 == 0xffffffff) &&
6194                     (!CHIP_IS_E3(sc) || (tags_63_32 == 0xffffffff)))
6195                         break;
6196                 DELAY(1000);
6197         } while (cnt-- > 0);
6198
6199         if (cnt <= 0) {
6200                 PMD_DRV_LOG(NOTICE,
6201                             "ERROR: Tetris buffer didn't get empty or there "
6202                             "are still outstanding read requests after 1s! "
6203                             "sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, "
6204                             "port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x",
6205                             sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
6206                             pgl_exp_rom2);
6207                 return -1;
6208         }
6209
6210         mb();
6211
6212         /* Close gates #2, #3 and #4 */
6213         bnx2x_set_234_gates(sc, TRUE);
6214
6215         /* Poll for IGU VQs for 57712 and newer chips */
6216         if (!CHIP_IS_E1x(sc) && bnx2x_er_poll_igu_vq(sc)) {
6217                 return -1;
6218         }
6219
6220         /* clear "unprepared" bit */
6221         REG_WR(sc, MISC_REG_UNPREPARED, 0);
6222         mb();
6223
6224         /* Make sure all is written to the chip before the reset */
6225         wmb();
6226
6227         /*
6228          * Wait for 1ms to empty GLUE and PCI-E core queues,
6229          * PSWHST, GRC and PSWRD Tetris buffer.
6230          */
6231         DELAY(1000);
6232
6233         /* Prepare to chip reset: */
6234         /* MCP */
6235         if (global) {
6236                 bnx2x_reset_mcp_prep(sc, &val);
6237         }
6238
6239         /* PXP */
6240         bnx2x_pxp_prep(sc);
6241         mb();
6242
6243         /* reset the chip */
6244         bnx2x_process_kill_chip_reset(sc, global);
6245         mb();
6246
6247         /* Recover after reset: */
6248         /* MCP */
6249         if (global && bnx2x_reset_mcp_comp(sc, val)) {
6250                 return -1;
6251         }
6252
6253         /* Open the gates #2, #3 and #4 */
6254         bnx2x_set_234_gates(sc, FALSE);
6255
6256         return 0;
6257 }
6258
6259 static int bnx2x_leader_reset(struct bnx2x_softc *sc)
6260 {
6261         int rc = 0;
6262         uint8_t global = bnx2x_reset_is_global(sc);
6263         uint32_t load_code;
6264
6265         /*
6266          * If not going to reset MCP, load "fake" driver to reset HW while
6267          * driver is owner of the HW.
6268          */
6269         if (!global && !BNX2X_NOMCP(sc)) {
6270                 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
6271                                            DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
6272                 if (!load_code) {
6273                         PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
6274                         rc = -1;
6275                         goto exit_leader_reset;
6276                 }
6277
6278                 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
6279                     (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
6280                         PMD_DRV_LOG(NOTICE,
6281                                     "MCP unexpected response, aborting");
6282                         rc = -1;
6283                         goto exit_leader_reset2;
6284                 }
6285
6286                 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
6287                 if (!load_code) {
6288                         PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
6289                         rc = -1;
6290                         goto exit_leader_reset2;
6291                 }
6292         }
6293
6294         /* try to recover after the failure */
6295         if (bnx2x_process_kill(sc, global)) {
6296                 PMD_DRV_LOG(NOTICE, "Something bad occurred on engine %d!",
6297                             SC_PATH(sc));
6298                 rc = -1;
6299                 goto exit_leader_reset2;
6300         }
6301
6302         /*
6303          * Clear the RESET_IN_PROGRESS and RESET_GLOBAL bits and update the driver
6304          * state.
6305          */
6306         bnx2x_set_reset_done(sc);
6307         if (global) {
6308                 bnx2x_clear_reset_global(sc);
6309         }
6310
6311 exit_leader_reset2:
6312
6313         /* unload "fake driver" if it was loaded */
6314         if (!global &&!BNX2X_NOMCP(sc)) {
6315                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
6316                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
6317         }
6318
6319 exit_leader_reset:
6320
6321         sc->is_leader = 0;
6322         bnx2x_release_leader_lock(sc);
6323
6324         mb();
6325         return rc;
6326 }
6327
6328 /*
6329  * prepare INIT transition, parameters configured:
6330  *   - HC configuration
6331  *   - Queue's CDU context
6332  */
6333 static void
6334 bnx2x_pf_q_prep_init(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6335                    struct ecore_queue_init_params *init_params)
6336 {
6337         uint8_t cos;
6338         int cxt_index, cxt_offset;
6339
6340         bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->rx.flags);
6341         bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->tx.flags);
6342
6343         bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->rx.flags);
6344         bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->tx.flags);
6345
6346         /* HC rate */
6347         init_params->rx.hc_rate =
6348             sc->hc_rx_ticks ? (1000000 / sc->hc_rx_ticks) : 0;
6349         init_params->tx.hc_rate =
6350             sc->hc_tx_ticks ? (1000000 / sc->hc_tx_ticks) : 0;
6351
6352         /* FW SB ID */
6353         init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = fp->fw_sb_id;
6354
6355         /* CQ index among the SB indices */
6356         init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6357         init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
6358
6359         /* set maximum number of COSs supported by this queue */
6360         init_params->max_cos = sc->max_cos;
6361
6362         /* set the context pointers queue object */
6363         for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
6364                 cxt_index = fp->index / ILT_PAGE_CIDS;
6365                 cxt_offset = fp->index - (cxt_index * ILT_PAGE_CIDS);
6366                 init_params->cxts[cos] =
6367                     &sc->context[cxt_index].vcxt[cxt_offset].eth;
6368         }
6369 }
6370
6371 /* set flags that are common for the Tx-only and not normal connections */
6372 static unsigned long
6373 bnx2x_get_common_flags(struct bnx2x_softc *sc, uint8_t zero_stats)
6374 {
6375         unsigned long flags = 0;
6376
6377         /* PF driver will always initialize the Queue to an ACTIVE state */
6378         bnx2x_set_bit(ECORE_Q_FLG_ACTIVE, &flags);
6379
6380         /*
6381          * tx only connections collect statistics (on the same index as the
6382          * parent connection). The statistics are zeroed when the parent
6383          * connection is initialized.
6384          */
6385
6386         bnx2x_set_bit(ECORE_Q_FLG_STATS, &flags);
6387         if (zero_stats) {
6388                 bnx2x_set_bit(ECORE_Q_FLG_ZERO_STATS, &flags);
6389         }
6390
6391         /*
6392          * tx only connections can support tx-switching, though their
6393          * CoS-ness doesn't survive the loopback
6394          */
6395         if (sc->flags & BNX2X_TX_SWITCHING) {
6396                 bnx2x_set_bit(ECORE_Q_FLG_TX_SWITCH, &flags);
6397         }
6398
6399         bnx2x_set_bit(ECORE_Q_FLG_PCSUM_ON_PKT, &flags);
6400
6401         return flags;
6402 }
6403
6404 static unsigned long bnx2x_get_q_flags(struct bnx2x_softc *sc, uint8_t leading)
6405 {
6406         unsigned long flags = 0;
6407
6408         if (IS_MF_SD(sc)) {
6409                 bnx2x_set_bit(ECORE_Q_FLG_OV, &flags);
6410         }
6411
6412         if (leading) {
6413                 bnx2x_set_bit(ECORE_Q_FLG_LEADING_RSS, &flags);
6414                 bnx2x_set_bit(ECORE_Q_FLG_MCAST, &flags);
6415         }
6416
6417         bnx2x_set_bit(ECORE_Q_FLG_VLAN, &flags);
6418
6419         /* merge with common flags */
6420         return flags | bnx2x_get_common_flags(sc, TRUE);
6421 }
6422
6423 static void
6424 bnx2x_pf_q_prep_general(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6425                       struct ecore_general_setup_params *gen_init, uint8_t cos)
6426 {
6427         gen_init->stat_id = bnx2x_stats_id(fp);
6428         gen_init->spcl_id = fp->cl_id;
6429         gen_init->mtu = sc->mtu;
6430         gen_init->cos = cos;
6431 }
6432
6433 static void
6434 bnx2x_pf_rx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6435                  struct rxq_pause_params *pause,
6436                  struct ecore_rxq_setup_params *rxq_init)
6437 {
6438         struct bnx2x_rx_queue *rxq;
6439
6440         rxq = sc->rx_queues[fp->index];
6441         if (!rxq) {
6442                 PMD_RX_LOG(ERR, "RX queue is NULL");
6443                 return;
6444         }
6445         /* pause */
6446         pause->bd_th_lo = BD_TH_LO(sc);
6447         pause->bd_th_hi = BD_TH_HI(sc);
6448
6449         pause->rcq_th_lo = RCQ_TH_LO(sc);
6450         pause->rcq_th_hi = RCQ_TH_HI(sc);
6451
6452         /* validate rings have enough entries to cross high thresholds */
6453         if (sc->dropless_fc &&
6454             pause->bd_th_hi + FW_PREFETCH_CNT > sc->rx_ring_size) {
6455                 PMD_DRV_LOG(WARNING, "rx bd ring threshold limit");
6456         }
6457
6458         if (sc->dropless_fc &&
6459             pause->rcq_th_hi + FW_PREFETCH_CNT > USABLE_RCQ_ENTRIES(rxq)) {
6460                 PMD_DRV_LOG(WARNING, "rcq ring threshold limit");
6461         }
6462
6463         pause->pri_map = 1;
6464
6465         /* rxq setup */
6466         rxq_init->dscr_map = (phys_addr_t)rxq->rx_ring_phys_addr;
6467         rxq_init->rcq_map = (phys_addr_t)rxq->cq_ring_phys_addr;
6468         rxq_init->rcq_np_map = (phys_addr_t)(rxq->cq_ring_phys_addr +
6469                                               BNX2X_PAGE_SIZE);
6470
6471         /*
6472          * This should be a maximum number of data bytes that may be
6473          * placed on the BD (not including paddings).
6474          */
6475         rxq_init->buf_sz = (fp->rx_buf_size - IP_HEADER_ALIGNMENT_PADDING);
6476
6477         rxq_init->cl_qzone_id = fp->cl_qzone_id;
6478         rxq_init->rss_engine_id = SC_FUNC(sc);
6479         rxq_init->mcast_engine_id = SC_FUNC(sc);
6480
6481         rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
6482         rxq_init->fw_sb_id = fp->fw_sb_id;
6483
6484         rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6485
6486         /*
6487          * configure silent vlan removal
6488          * if multi function mode is afex, then mask default vlan
6489          */
6490         if (IS_MF_AFEX(sc)) {
6491                 rxq_init->silent_removal_value =
6492                     sc->devinfo.mf_info.afex_def_vlan_tag;
6493                 rxq_init->silent_removal_mask = EVL_VLID_MASK;
6494         }
6495 }
6496
6497 static void
6498 bnx2x_pf_tx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6499                  struct ecore_txq_setup_params *txq_init, uint8_t cos)
6500 {
6501         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
6502
6503         if (!txq) {
6504                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
6505                 return;
6506         }
6507         txq_init->dscr_map = (phys_addr_t)txq->tx_ring_phys_addr;
6508         txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
6509         txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
6510         txq_init->fw_sb_id = fp->fw_sb_id;
6511
6512         /*
6513          * set the TSS leading client id for TX classfication to the
6514          * leading RSS client id
6515          */
6516         txq_init->tss_leading_cl_id = BNX2X_FP(sc, 0, cl_id);
6517 }
6518
6519 /*
6520  * This function performs 2 steps in a queue state machine:
6521  *   1) RESET->INIT
6522  *   2) INIT->SETUP
6523  */
6524 static int
6525 bnx2x_setup_queue(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp, uint8_t leading)
6526 {
6527         struct ecore_queue_state_params q_params = { NULL };
6528         struct ecore_queue_setup_params *setup_params = &q_params.params.setup;
6529         int rc;
6530
6531         PMD_DRV_LOG(DEBUG, "setting up queue %d", fp->index);
6532
6533         bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6534
6535         q_params.q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
6536
6537         /* we want to wait for completion in this context */
6538         bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
6539
6540         /* prepare the INIT parameters */
6541         bnx2x_pf_q_prep_init(sc, fp, &q_params.params.init);
6542
6543         /* Set the command */
6544         q_params.cmd = ECORE_Q_CMD_INIT;
6545
6546         /* Change the state to INIT */
6547         rc = ecore_queue_state_change(sc, &q_params);
6548         if (rc) {
6549                 PMD_DRV_LOG(NOTICE, "Queue(%d) INIT failed", fp->index);
6550                 return rc;
6551         }
6552
6553         PMD_DRV_LOG(DEBUG, "init complete");
6554
6555         /* now move the Queue to the SETUP state */
6556         memset(setup_params, 0, sizeof(*setup_params));
6557
6558         /* set Queue flags */
6559         setup_params->flags = bnx2x_get_q_flags(sc, leading);
6560
6561         /* set general SETUP parameters */
6562         bnx2x_pf_q_prep_general(sc, fp, &setup_params->gen_params,
6563                               FIRST_TX_COS_INDEX);
6564
6565         bnx2x_pf_rx_q_prep(sc, fp,
6566                          &setup_params->pause_params,
6567                          &setup_params->rxq_params);
6568
6569         bnx2x_pf_tx_q_prep(sc, fp, &setup_params->txq_params, FIRST_TX_COS_INDEX);
6570
6571         /* Set the command */
6572         q_params.cmd = ECORE_Q_CMD_SETUP;
6573
6574         /* change the state to SETUP */
6575         rc = ecore_queue_state_change(sc, &q_params);
6576         if (rc) {
6577                 PMD_DRV_LOG(NOTICE, "Queue(%d) SETUP failed", fp->index);
6578                 return rc;
6579         }
6580
6581         return rc;
6582 }
6583
6584 static int bnx2x_setup_leading(struct bnx2x_softc *sc)
6585 {
6586         if (IS_PF(sc))
6587                 return bnx2x_setup_queue(sc, &sc->fp[0], TRUE);
6588         else                    /* VF */
6589                 return bnx2x_vf_setup_queue(sc, &sc->fp[0], TRUE);
6590 }
6591
6592 static int
6593 bnx2x_config_rss_pf(struct bnx2x_softc *sc, struct ecore_rss_config_obj *rss_obj,
6594                   uint8_t config_hash)
6595 {
6596         struct ecore_config_rss_params params = { NULL };
6597         uint32_t i;
6598
6599         /*
6600          * Although RSS is meaningless when there is a single HW queue we
6601          * still need it enabled in order to have HW Rx hash generated.
6602          */
6603
6604         params.rss_obj = rss_obj;
6605
6606         bnx2x_set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
6607
6608         bnx2x_set_bit(ECORE_RSS_MODE_REGULAR, &params.rss_flags);
6609
6610         /* RSS configuration */
6611         bnx2x_set_bit(ECORE_RSS_IPV4, &params.rss_flags);
6612         bnx2x_set_bit(ECORE_RSS_IPV4_TCP, &params.rss_flags);
6613         bnx2x_set_bit(ECORE_RSS_IPV6, &params.rss_flags);
6614         bnx2x_set_bit(ECORE_RSS_IPV6_TCP, &params.rss_flags);
6615         if (rss_obj->udp_rss_v4) {
6616                 bnx2x_set_bit(ECORE_RSS_IPV4_UDP, &params.rss_flags);
6617         }
6618         if (rss_obj->udp_rss_v6) {
6619                 bnx2x_set_bit(ECORE_RSS_IPV6_UDP, &params.rss_flags);
6620         }
6621
6622         /* Hash bits */
6623         params.rss_result_mask = MULTI_MASK;
6624
6625         (void)rte_memcpy(params.ind_table, rss_obj->ind_table,
6626                          sizeof(params.ind_table));
6627
6628         if (config_hash) {
6629 /* RSS keys */
6630                 for (i = 0; i < sizeof(params.rss_key) / 4; i++) {
6631                         params.rss_key[i] = (uint32_t) rte_rand();
6632                 }
6633
6634                 bnx2x_set_bit(ECORE_RSS_SET_SRCH, &params.rss_flags);
6635         }
6636
6637         if (IS_PF(sc))
6638                 return ecore_config_rss(sc, &params);
6639         else
6640                 return bnx2x_vf_config_rss(sc, &params);
6641 }
6642
6643 static int bnx2x_config_rss_eth(struct bnx2x_softc *sc, uint8_t config_hash)
6644 {
6645         return bnx2x_config_rss_pf(sc, &sc->rss_conf_obj, config_hash);
6646 }
6647
6648 static int bnx2x_init_rss_pf(struct bnx2x_softc *sc)
6649 {
6650         uint8_t num_eth_queues = BNX2X_NUM_ETH_QUEUES(sc);
6651         uint32_t i;
6652
6653         /*
6654          * Prepare the initial contents of the indirection table if
6655          * RSS is enabled
6656          */
6657         for (i = 0; i < sizeof(sc->rss_conf_obj.ind_table); i++) {
6658                 sc->rss_conf_obj.ind_table[i] =
6659                     (sc->fp->cl_id + (i % num_eth_queues));
6660         }
6661
6662         if (sc->udp_rss) {
6663                 sc->rss_conf_obj.udp_rss_v4 = sc->rss_conf_obj.udp_rss_v6 = 1;
6664         }
6665
6666         /*
6667          * For 57711 SEARCHER configuration (rss_keys) is
6668          * per-port, so if explicit configuration is needed, do it only
6669          * for a PMF.
6670          *
6671          * For 57712 and newer it's a per-function configuration.
6672          */
6673         return bnx2x_config_rss_eth(sc, sc->port.pmf || !CHIP_IS_E1x(sc));
6674 }
6675
6676 static int
6677 bnx2x_set_mac_one(struct bnx2x_softc *sc, uint8_t * mac,
6678                 struct ecore_vlan_mac_obj *obj, uint8_t set, int mac_type,
6679                 unsigned long *ramrod_flags)
6680 {
6681         struct ecore_vlan_mac_ramrod_params ramrod_param;
6682         int rc;
6683
6684         memset(&ramrod_param, 0, sizeof(ramrod_param));
6685
6686         /* fill in general parameters */
6687         ramrod_param.vlan_mac_obj = obj;
6688         ramrod_param.ramrod_flags = *ramrod_flags;
6689
6690         /* fill a user request section if needed */
6691         if (!bnx2x_test_bit(RAMROD_CONT, ramrod_flags)) {
6692                 (void)rte_memcpy(ramrod_param.user_req.u.mac.mac, mac,
6693                                  ETH_ALEN);
6694
6695                 bnx2x_set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
6696
6697 /* Set the command: ADD or DEL */
6698                 ramrod_param.user_req.cmd = (set) ? ECORE_VLAN_MAC_ADD :
6699                     ECORE_VLAN_MAC_DEL;
6700         }
6701
6702         rc = ecore_config_vlan_mac(sc, &ramrod_param);
6703
6704         if (rc == ECORE_EXISTS) {
6705                 PMD_DRV_LOG(INFO, "Failed to schedule ADD operations (EEXIST)");
6706 /* do not treat adding same MAC as error */
6707                 rc = 0;
6708         } else if (rc < 0) {
6709                 PMD_DRV_LOG(ERR,
6710                             "%s MAC failed (%d)", (set ? "Set" : "Delete"), rc);
6711         }
6712
6713         return rc;
6714 }
6715
6716 static int bnx2x_set_eth_mac(struct bnx2x_softc *sc, uint8_t set)
6717 {
6718         unsigned long ramrod_flags = 0;
6719
6720         PMD_DRV_LOG(DEBUG, "Adding Ethernet MAC");
6721
6722         bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
6723
6724         /* Eth MAC is set on RSS leading client (fp[0]) */
6725         return bnx2x_set_mac_one(sc, sc->link_params.mac_addr,
6726                                &sc->sp_objs->mac_obj,
6727                                set, ECORE_ETH_MAC, &ramrod_flags);
6728 }
6729
6730 static int bnx2x_get_cur_phy_idx(struct bnx2x_softc *sc)
6731 {
6732         uint32_t sel_phy_idx = 0;
6733
6734         if (sc->link_params.num_phys <= 1) {
6735                 return ELINK_INT_PHY;
6736         }
6737
6738         if (sc->link_vars.link_up) {
6739                 sel_phy_idx = ELINK_EXT_PHY1;
6740 /* In case link is SERDES, check if the ELINK_EXT_PHY2 is the one */
6741                 if ((sc->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
6742                     (sc->link_params.phy[ELINK_EXT_PHY2].supported &
6743                      ELINK_SUPPORTED_FIBRE))
6744                         sel_phy_idx = ELINK_EXT_PHY2;
6745         } else {
6746                 switch (elink_phy_selection(&sc->link_params)) {
6747                 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6748                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
6749                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6750                         sel_phy_idx = ELINK_EXT_PHY1;
6751                         break;
6752                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
6753                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6754                         sel_phy_idx = ELINK_EXT_PHY2;
6755                         break;
6756                 }
6757         }
6758
6759         return sel_phy_idx;
6760 }
6761
6762 static int bnx2x_get_link_cfg_idx(struct bnx2x_softc *sc)
6763 {
6764         uint32_t sel_phy_idx = bnx2x_get_cur_phy_idx(sc);
6765
6766         /*
6767          * The selected activated PHY is always after swapping (in case PHY
6768          * swapping is enabled). So when swapping is enabled, we need to reverse
6769          * the configuration
6770          */
6771
6772         if (sc->link_params.multi_phy_config & PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
6773                 if (sel_phy_idx == ELINK_EXT_PHY1)
6774                         sel_phy_idx = ELINK_EXT_PHY2;
6775                 else if (sel_phy_idx == ELINK_EXT_PHY2)
6776                         sel_phy_idx = ELINK_EXT_PHY1;
6777         }
6778
6779         return ELINK_LINK_CONFIG_IDX(sel_phy_idx);
6780 }
6781
6782 static void bnx2x_set_requested_fc(struct bnx2x_softc *sc)
6783 {
6784         /*
6785          * Initialize link parameters structure variables
6786          * It is recommended to turn off RX FC for jumbo frames
6787          * for better performance
6788          */
6789         if (CHIP_IS_E1x(sc) && (sc->mtu > 5000)) {
6790                 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_TX;
6791         } else {
6792                 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_BOTH;
6793         }
6794 }
6795
6796 static void bnx2x_calc_fc_adv(struct bnx2x_softc *sc)
6797 {
6798         uint8_t cfg_idx = bnx2x_get_link_cfg_idx(sc);
6799         switch (sc->link_vars.ieee_fc &
6800                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
6801         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
6802         default:
6803                 sc->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
6804                                                    ADVERTISED_Pause);
6805                 break;
6806
6807         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
6808                 sc->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
6809                                                   ADVERTISED_Pause);
6810                 break;
6811
6812         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
6813                 sc->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
6814                 break;
6815         }
6816 }
6817
6818 static uint16_t bnx2x_get_mf_speed(struct bnx2x_softc *sc)
6819 {
6820         uint16_t line_speed = sc->link_vars.line_speed;
6821         if (IS_MF(sc)) {
6822                 uint16_t maxCfg = bnx2x_extract_max_cfg(sc,
6823                                                       sc->devinfo.
6824                                                       mf_info.mf_config[SC_VN
6825                                                                         (sc)]);
6826
6827 /* calculate the current MAX line speed limit for the MF devices */
6828                 if (IS_MF_SI(sc)) {
6829                         line_speed = (line_speed * maxCfg) / 100;
6830                 } else {        /* SD mode */
6831                         uint16_t vn_max_rate = maxCfg * 100;
6832
6833                         if (vn_max_rate < line_speed) {
6834                                 line_speed = vn_max_rate;
6835                         }
6836                 }
6837         }
6838
6839         return line_speed;
6840 }
6841
6842 static void
6843 bnx2x_fill_report_data(struct bnx2x_softc *sc, struct bnx2x_link_report_data *data)
6844 {
6845         uint16_t line_speed = bnx2x_get_mf_speed(sc);
6846
6847         memset(data, 0, sizeof(*data));
6848
6849         /* fill the report data with the effective line speed */
6850         data->line_speed = line_speed;
6851
6852         /* Link is down */
6853         if (!sc->link_vars.link_up || (sc->flags & BNX2X_MF_FUNC_DIS)) {
6854                 bnx2x_set_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6855                             &data->link_report_flags);
6856         }
6857
6858         /* Full DUPLEX */
6859         if (sc->link_vars.duplex == DUPLEX_FULL) {
6860                 bnx2x_set_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6861                             &data->link_report_flags);
6862         }
6863
6864         /* Rx Flow Control is ON */
6865         if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_RX) {
6866                 bnx2x_set_bit(BNX2X_LINK_REPORT_RX_FC_ON, &data->link_report_flags);
6867         }
6868
6869         /* Tx Flow Control is ON */
6870         if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
6871                 bnx2x_set_bit(BNX2X_LINK_REPORT_TX_FC_ON, &data->link_report_flags);
6872         }
6873 }
6874
6875 /* report link status to OS, should be called under phy_lock */
6876 static void bnx2x_link_report(struct bnx2x_softc *sc)
6877 {
6878         struct bnx2x_link_report_data cur_data;
6879
6880         /* reread mf_cfg */
6881         if (IS_PF(sc)) {
6882                 bnx2x_read_mf_cfg(sc);
6883         }
6884
6885         /* Read the current link report info */
6886         bnx2x_fill_report_data(sc, &cur_data);
6887
6888         /* Don't report link down or exactly the same link status twice */
6889         if (!memcmp(&cur_data, &sc->last_reported_link, sizeof(cur_data)) ||
6890             (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6891                           &sc->last_reported_link.link_report_flags) &&
6892              bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6893                           &cur_data.link_report_flags))) {
6894                 return;
6895         }
6896
6897         sc->link_cnt++;
6898
6899         /* report new link params and remember the state for the next time */
6900         (void)rte_memcpy(&sc->last_reported_link, &cur_data, sizeof(cur_data));
6901
6902         if (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6903                          &cur_data.link_report_flags)) {
6904                 PMD_DRV_LOG(INFO, "NIC Link is Down");
6905         } else {
6906                 __rte_unused const char *duplex;
6907                 __rte_unused const char *flow;
6908
6909                 if (bnx2x_test_and_clear_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6910                                            &cur_data.link_report_flags)) {
6911                         duplex = "full";
6912                 } else {
6913                         duplex = "half";
6914                 }
6915
6916 /*
6917  * Handle the FC at the end so that only these flags would be
6918  * possibly set. This way we may easily check if there is no FC
6919  * enabled.
6920  */
6921                 if (cur_data.link_report_flags) {
6922                         if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6923                                          &cur_data.link_report_flags) &&
6924                             bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6925                                          &cur_data.link_report_flags)) {
6926                                 flow = "ON - receive & transmit";
6927                         } else if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6928                                                 &cur_data.link_report_flags) &&
6929                                    !bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6930                                                  &cur_data.link_report_flags)) {
6931                                 flow = "ON - receive";
6932                         } else if (!bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6933                                                  &cur_data.link_report_flags) &&
6934                                    bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6935                                                 &cur_data.link_report_flags)) {
6936                                 flow = "ON - transmit";
6937                         } else {
6938                                 flow = "none";  /* possible? */
6939                         }
6940                 } else {
6941                         flow = "none";
6942                 }
6943
6944                 PMD_DRV_LOG(INFO,
6945                             "NIC Link is Up, %d Mbps %s duplex, Flow control: %s",
6946                             cur_data.line_speed, duplex, flow);
6947         }
6948 }
6949
6950 void bnx2x_link_status_update(struct bnx2x_softc *sc)
6951 {
6952         if (sc->state != BNX2X_STATE_OPEN) {
6953                 return;
6954         }
6955
6956         if (IS_PF(sc) && !CHIP_REV_IS_SLOW(sc)) {
6957                 elink_link_status_update(&sc->link_params, &sc->link_vars);
6958         } else {
6959                 sc->port.supported[0] |= (ELINK_SUPPORTED_10baseT_Half |
6960                                           ELINK_SUPPORTED_10baseT_Full |
6961                                           ELINK_SUPPORTED_100baseT_Half |
6962                                           ELINK_SUPPORTED_100baseT_Full |
6963                                           ELINK_SUPPORTED_1000baseT_Full |
6964                                           ELINK_SUPPORTED_2500baseX_Full |
6965                                           ELINK_SUPPORTED_10000baseT_Full |
6966                                           ELINK_SUPPORTED_TP |
6967                                           ELINK_SUPPORTED_FIBRE |
6968                                           ELINK_SUPPORTED_Autoneg |
6969                                           ELINK_SUPPORTED_Pause |
6970                                           ELINK_SUPPORTED_Asym_Pause);
6971                 sc->port.advertising[0] = sc->port.supported[0];
6972
6973                 sc->link_params.sc = sc;
6974                 sc->link_params.port = SC_PORT(sc);
6975                 sc->link_params.req_duplex[0] = DUPLEX_FULL;
6976                 sc->link_params.req_flow_ctrl[0] = ELINK_FLOW_CTRL_NONE;
6977                 sc->link_params.req_line_speed[0] = SPEED_10000;
6978                 sc->link_params.speed_cap_mask[0] = 0x7f0000;
6979                 sc->link_params.switch_cfg = ELINK_SWITCH_CFG_10G;
6980
6981                 if (CHIP_REV_IS_FPGA(sc)) {
6982                         sc->link_vars.mac_type = ELINK_MAC_TYPE_EMAC;
6983                         sc->link_vars.line_speed = ELINK_SPEED_1000;
6984                         sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
6985                                                      LINK_STATUS_SPEED_AND_DUPLEX_1000TFD);
6986                 } else {
6987                         sc->link_vars.mac_type = ELINK_MAC_TYPE_BMAC;
6988                         sc->link_vars.line_speed = ELINK_SPEED_10000;
6989                         sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
6990                                                      LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
6991                 }
6992
6993                 sc->link_vars.link_up = 1;
6994
6995                 sc->link_vars.duplex = DUPLEX_FULL;
6996                 sc->link_vars.flow_ctrl = ELINK_FLOW_CTRL_NONE;
6997
6998                 if (IS_PF(sc)) {
6999                         REG_WR(sc,
7000                                NIG_REG_EGRESS_DRAIN0_MODE +
7001                                sc->link_params.port * 4, 0);
7002                         bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7003                         bnx2x_link_report(sc);
7004                 }
7005         }
7006
7007         if (IS_PF(sc)) {
7008                 if (sc->link_vars.link_up) {
7009                         bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7010                 } else {
7011                         bnx2x_stats_handle(sc, STATS_EVENT_STOP);
7012                 }
7013                 bnx2x_link_report(sc);
7014         } else {
7015                 bnx2x_link_report(sc);
7016                 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7017         }
7018 }
7019
7020 static void bnx2x_periodic_start(struct bnx2x_softc *sc)
7021 {
7022         atomic_store_rel_long(&sc->periodic_flags, PERIODIC_GO);
7023 }
7024
7025 static void bnx2x_periodic_stop(struct bnx2x_softc *sc)
7026 {
7027         atomic_store_rel_long(&sc->periodic_flags, PERIODIC_STOP);
7028 }
7029
7030 static int bnx2x_initial_phy_init(struct bnx2x_softc *sc, int load_mode)
7031 {
7032         int rc, cfg_idx = bnx2x_get_link_cfg_idx(sc);
7033         uint16_t req_line_speed = sc->link_params.req_line_speed[cfg_idx];
7034         struct elink_params *lp = &sc->link_params;
7035
7036         bnx2x_set_requested_fc(sc);
7037
7038         if (CHIP_REV_IS_SLOW(sc)) {
7039                 uint32_t bond = CHIP_BOND_ID(sc);
7040                 uint32_t feat = 0;
7041
7042                 if (CHIP_IS_E2(sc) && CHIP_IS_MODE_4_PORT(sc)) {
7043                         feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC;
7044                 } else if (bond & 0x4) {
7045                         if (CHIP_IS_E3(sc)) {
7046                                 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC;
7047                         } else {
7048                                 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC;
7049                         }
7050                 } else if (bond & 0x8) {
7051                         if (CHIP_IS_E3(sc)) {
7052                                 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_UMAC;
7053                         } else {
7054                                 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC;
7055                         }
7056                 }
7057
7058 /* disable EMAC for E3 and above */
7059                 if (bond & 0x2) {
7060                         feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC;
7061                 }
7062
7063                 sc->link_params.feature_config_flags |= feat;
7064         }
7065
7066         if (load_mode == LOAD_DIAG) {
7067                 lp->loopback_mode = ELINK_LOOPBACK_XGXS;
7068 /* Prefer doing PHY loopback at 10G speed, if possible */
7069                 if (lp->req_line_speed[cfg_idx] < ELINK_SPEED_10000) {
7070                         if (lp->speed_cap_mask[cfg_idx] &
7071                             PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
7072                                 lp->req_line_speed[cfg_idx] = ELINK_SPEED_10000;
7073                         } else {
7074                                 lp->req_line_speed[cfg_idx] = ELINK_SPEED_1000;
7075                         }
7076                 }
7077         }
7078
7079         if (load_mode == LOAD_LOOPBACK_EXT) {
7080                 lp->loopback_mode = ELINK_LOOPBACK_EXT;
7081         }
7082
7083         rc = elink_phy_init(&sc->link_params, &sc->link_vars);
7084
7085         bnx2x_calc_fc_adv(sc);
7086
7087         if (sc->link_vars.link_up) {
7088                 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7089                 bnx2x_link_report(sc);
7090         }
7091
7092         if (!CHIP_REV_IS_SLOW(sc)) {
7093                 bnx2x_periodic_start(sc);
7094         }
7095
7096         sc->link_params.req_line_speed[cfg_idx] = req_line_speed;
7097         return rc;
7098 }
7099
7100 /* update flags in shmem */
7101 static void
7102 bnx2x_update_drv_flags(struct bnx2x_softc *sc, uint32_t flags, uint32_t set)
7103 {
7104         uint32_t drv_flags;
7105
7106         if (SHMEM2_HAS(sc, drv_flags)) {
7107                 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7108                 drv_flags = SHMEM2_RD(sc, drv_flags);
7109
7110                 if (set) {
7111                         drv_flags |= flags;
7112                 } else {
7113                         drv_flags &= ~flags;
7114                 }
7115
7116                 SHMEM2_WR(sc, drv_flags, drv_flags);
7117
7118                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7119         }
7120 }
7121
7122 /* periodic timer callout routine, only runs when the interface is up */
7123 void bnx2x_periodic_callout(struct bnx2x_softc *sc)
7124 {
7125         if ((sc->state != BNX2X_STATE_OPEN) ||
7126             (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_STOP)) {
7127                 PMD_DRV_LOG(WARNING, "periodic callout exit (state=0x%x)",
7128                             sc->state);
7129                 return;
7130         }
7131         if (!CHIP_REV_IS_SLOW(sc)) {
7132 /*
7133  * This barrier is needed to ensure the ordering between the writing
7134  * to the sc->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
7135  * the reading here.
7136  */
7137                 mb();
7138                 if (sc->port.pmf) {
7139                         elink_period_func(&sc->link_params, &sc->link_vars);
7140                 }
7141         }
7142 #ifdef BNX2X_PULSE
7143         if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7144                 int mb_idx = SC_FW_MB_IDX(sc);
7145                 uint32_t drv_pulse;
7146                 uint32_t mcp_pulse;
7147
7148                 ++sc->fw_drv_pulse_wr_seq;
7149                 sc->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
7150
7151                 drv_pulse = sc->fw_drv_pulse_wr_seq;
7152                 bnx2x_drv_pulse(sc);
7153
7154                 mcp_pulse = (SHMEM_RD(sc, func_mb[mb_idx].mcp_pulse_mb) &
7155                              MCP_PULSE_SEQ_MASK);
7156
7157 /*
7158  * The delta between driver pulse and mcp response should
7159  * be 1 (before mcp response) or 0 (after mcp response).
7160  */
7161                 if ((drv_pulse != mcp_pulse) &&
7162                     (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
7163                         /* someone lost a heartbeat... */
7164                         PMD_DRV_LOG(ERR,
7165                                     "drv_pulse (0x%x) != mcp_pulse (0x%x)",
7166                                     drv_pulse, mcp_pulse);
7167                 }
7168         }
7169 #endif
7170 }
7171
7172 /* start the controller */
7173 static __attribute__ ((noinline))
7174 int bnx2x_nic_load(struct bnx2x_softc *sc)
7175 {
7176         uint32_t val;
7177         uint32_t load_code = 0;
7178         int i, rc = 0;
7179
7180         PMD_INIT_FUNC_TRACE();
7181
7182         sc->state = BNX2X_STATE_OPENING_WAITING_LOAD;
7183
7184         if (IS_PF(sc)) {
7185 /* must be called before memory allocation and HW init */
7186                 bnx2x_ilt_set_info(sc);
7187         }
7188
7189         bnx2x_set_fp_rx_buf_size(sc);
7190
7191         if (IS_PF(sc)) {
7192                 if (bnx2x_alloc_mem(sc) != 0) {
7193                         sc->state = BNX2X_STATE_CLOSED;
7194                         rc = -ENOMEM;
7195                         goto bnx2x_nic_load_error0;
7196                 }
7197         }
7198
7199         if (bnx2x_alloc_fw_stats_mem(sc) != 0) {
7200                 sc->state = BNX2X_STATE_CLOSED;
7201                 rc = -ENOMEM;
7202                 goto bnx2x_nic_load_error0;
7203         }
7204
7205         if (IS_VF(sc)) {
7206                 rc = bnx2x_vf_init(sc);
7207                 if (rc) {
7208                         sc->state = BNX2X_STATE_ERROR;
7209                         goto bnx2x_nic_load_error0;
7210                 }
7211         }
7212
7213         if (IS_PF(sc)) {
7214 /* set pf load just before approaching the MCP */
7215                 bnx2x_set_pf_load(sc);
7216
7217 /* if MCP exists send load request and analyze response */
7218                 if (!BNX2X_NOMCP(sc)) {
7219                         /* attempt to load pf */
7220                         if (bnx2x_nic_load_request(sc, &load_code) != 0) {
7221                                 sc->state = BNX2X_STATE_CLOSED;
7222                                 rc = -ENXIO;
7223                                 goto bnx2x_nic_load_error1;
7224                         }
7225
7226                         /* what did the MCP say? */
7227                         if (bnx2x_nic_load_analyze_req(sc, load_code) != 0) {
7228                                 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7229                                 sc->state = BNX2X_STATE_CLOSED;
7230                                 rc = -ENXIO;
7231                                 goto bnx2x_nic_load_error2;
7232                         }
7233                 } else {
7234                         PMD_DRV_LOG(INFO, "Device has no MCP!");
7235                         load_code = bnx2x_nic_load_no_mcp(sc);
7236                 }
7237
7238 /* mark PMF if applicable */
7239                 bnx2x_nic_load_pmf(sc, load_code);
7240
7241 /* Init Function state controlling object */
7242                 bnx2x_init_func_obj(sc);
7243
7244 /* Initialize HW */
7245                 if (bnx2x_init_hw(sc, load_code) != 0) {
7246                         PMD_DRV_LOG(NOTICE, "HW init failed");
7247                         bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7248                         sc->state = BNX2X_STATE_CLOSED;
7249                         rc = -ENXIO;
7250                         goto bnx2x_nic_load_error2;
7251                 }
7252         }
7253
7254         bnx2x_nic_init(sc, load_code);
7255
7256         /* Init per-function objects */
7257         if (IS_PF(sc)) {
7258                 bnx2x_init_objs(sc);
7259
7260 /* set AFEX default VLAN tag to an invalid value */
7261                 sc->devinfo.mf_info.afex_def_vlan_tag = -1;
7262
7263                 sc->state = BNX2X_STATE_OPENING_WAITING_PORT;
7264                 rc = bnx2x_func_start(sc);
7265                 if (rc) {
7266                         PMD_DRV_LOG(NOTICE, "Function start failed!");
7267                         bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7268                         sc->state = BNX2X_STATE_ERROR;
7269                         goto bnx2x_nic_load_error3;
7270                 }
7271
7272 /* send LOAD_DONE command to MCP */
7273                 if (!BNX2X_NOMCP(sc)) {
7274                         load_code =
7275                             bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7276                         if (!load_code) {
7277                                 PMD_DRV_LOG(NOTICE,
7278                                             "MCP response failure, aborting");
7279                                 sc->state = BNX2X_STATE_ERROR;
7280                                 rc = -ENXIO;
7281                                 goto bnx2x_nic_load_error3;
7282                         }
7283                 }
7284         }
7285
7286         rc = bnx2x_setup_leading(sc);
7287         if (rc) {
7288                 PMD_DRV_LOG(NOTICE, "Setup leading failed!");
7289                 sc->state = BNX2X_STATE_ERROR;
7290                 goto bnx2x_nic_load_error3;
7291         }
7292
7293         FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, i) {
7294                 if (IS_PF(sc))
7295                         rc = bnx2x_setup_queue(sc, &sc->fp[i], FALSE);
7296                 else            /* IS_VF(sc) */
7297                         rc = bnx2x_vf_setup_queue(sc, &sc->fp[i], FALSE);
7298
7299                 if (rc) {
7300                         PMD_DRV_LOG(NOTICE, "Queue(%d) setup failed", i);
7301                         sc->state = BNX2X_STATE_ERROR;
7302                         goto bnx2x_nic_load_error3;
7303                 }
7304         }
7305
7306         rc = bnx2x_init_rss_pf(sc);
7307         if (rc) {
7308                 PMD_DRV_LOG(NOTICE, "PF RSS init failed");
7309                 sc->state = BNX2X_STATE_ERROR;
7310                 goto bnx2x_nic_load_error3;
7311         }
7312
7313         /* now when Clients are configured we are ready to work */
7314         sc->state = BNX2X_STATE_OPEN;
7315
7316         /* Configure a ucast MAC */
7317         if (IS_PF(sc)) {
7318                 rc = bnx2x_set_eth_mac(sc, TRUE);
7319         } else {                /* IS_VF(sc) */
7320                 rc = bnx2x_vf_set_mac(sc, TRUE);
7321         }
7322
7323         if (rc) {
7324                 PMD_DRV_LOG(NOTICE, "Setting Ethernet MAC failed");
7325                 sc->state = BNX2X_STATE_ERROR;
7326                 goto bnx2x_nic_load_error3;
7327         }
7328
7329         if (sc->port.pmf) {
7330                 rc = bnx2x_initial_phy_init(sc, LOAD_OPEN);
7331                 if (rc) {
7332                         sc->state = BNX2X_STATE_ERROR;
7333                         goto bnx2x_nic_load_error3;
7334                 }
7335         }
7336
7337         sc->link_params.feature_config_flags &=
7338             ~ELINK_FEATURE_CONFIG_BOOT_FROM_SAN;
7339
7340         /* start the Tx */
7341         switch (LOAD_OPEN) {
7342         case LOAD_NORMAL:
7343         case LOAD_OPEN:
7344                 break;
7345
7346         case LOAD_DIAG:
7347         case LOAD_LOOPBACK_EXT:
7348                 sc->state = BNX2X_STATE_DIAG;
7349                 break;
7350
7351         default:
7352                 break;
7353         }
7354
7355         if (sc->port.pmf) {
7356                 bnx2x_update_drv_flags(sc, 1 << DRV_FLAGS_PORT_MASK, 0);
7357         } else {
7358                 bnx2x_link_status_update(sc);
7359         }
7360
7361         if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
7362 /* mark driver is loaded in shmem2 */
7363                 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
7364                 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
7365                           (val |
7366                            DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED |
7367                            DRV_FLAGS_CAPABILITIES_LOADED_L2));
7368         }
7369
7370         /* start fast path */
7371         /* Initialize Rx filter */
7372         bnx2x_set_rx_mode(sc);
7373
7374         /* wait for all pending SP commands to complete */
7375         if (IS_PF(sc) && !bnx2x_wait_sp_comp(sc, ~0x0UL)) {
7376                 PMD_DRV_LOG(NOTICE, "Timeout waiting for all SPs to complete!");
7377                 bnx2x_periodic_stop(sc);
7378                 bnx2x_nic_unload(sc, UNLOAD_CLOSE, FALSE);
7379                 return -ENXIO;
7380         }
7381
7382         PMD_DRV_LOG(DEBUG, "NIC successfully loaded");
7383
7384         return 0;
7385
7386 bnx2x_nic_load_error3:
7387
7388         if (IS_PF(sc)) {
7389                 bnx2x_int_disable_sync(sc, 1);
7390
7391 /* clean out queued objects */
7392                 bnx2x_squeeze_objects(sc);
7393         }
7394
7395 bnx2x_nic_load_error2:
7396
7397         if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7398                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
7399                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
7400         }
7401
7402         sc->port.pmf = 0;
7403
7404 bnx2x_nic_load_error1:
7405
7406         /* clear pf_load status, as it was already set */
7407         if (IS_PF(sc)) {
7408                 bnx2x_clear_pf_load(sc);
7409         }
7410
7411 bnx2x_nic_load_error0:
7412
7413         bnx2x_free_fw_stats_mem(sc);
7414         bnx2x_free_mem(sc);
7415
7416         return rc;
7417 }
7418
7419 /*
7420 * Handles controller initialization.
7421 */
7422 int bnx2x_init(struct bnx2x_softc *sc)
7423 {
7424         int other_engine = SC_PATH(sc) ? 0 : 1;
7425         uint8_t other_load_status, load_status;
7426         uint8_t global = FALSE;
7427         int rc;
7428
7429         /* Check if the driver is still running and bail out if it is. */
7430         if (sc->state != BNX2X_STATE_CLOSED) {
7431                 PMD_DRV_LOG(DEBUG, "Init called while driver is running!");
7432                 rc = 0;
7433                 goto bnx2x_init_done;
7434         }
7435
7436         bnx2x_set_power_state(sc, PCI_PM_D0);
7437
7438         /*
7439          * If parity occurred during the unload, then attentions and/or
7440          * RECOVERY_IN_PROGRESS may still be set. If so we want the first function
7441          * loaded on the current engine to complete the recovery. Parity recovery
7442          * is only relevant for PF driver.
7443          */
7444         if (IS_PF(sc)) {
7445                 other_load_status = bnx2x_get_load_status(sc, other_engine);
7446                 load_status = bnx2x_get_load_status(sc, SC_PATH(sc));
7447
7448                 if (!bnx2x_reset_is_done(sc, SC_PATH(sc)) ||
7449                     bnx2x_chk_parity_attn(sc, &global, TRUE)) {
7450                         do {
7451                                 /*
7452                                  * If there are attentions and they are in global blocks, set
7453                                  * the GLOBAL_RESET bit regardless whether it will be this
7454                                  * function that will complete the recovery or not.
7455                                  */
7456                                 if (global) {
7457                                         bnx2x_set_reset_global(sc);
7458                                 }
7459
7460                                 /*
7461                                  * Only the first function on the current engine should try
7462                                  * to recover in open. In case of attentions in global blocks
7463                                  * only the first in the chip should try to recover.
7464                                  */
7465                                 if ((!load_status
7466                                      && (!global ||!other_load_status))
7467                                     && bnx2x_trylock_leader_lock(sc)
7468                                     && !bnx2x_leader_reset(sc)) {
7469                                         PMD_DRV_LOG(INFO,
7470                                                     "Recovered during init");
7471                                         break;
7472                                 }
7473
7474                                 /* recovery has failed... */
7475                                 bnx2x_set_power_state(sc, PCI_PM_D3hot);
7476
7477                                 sc->recovery_state = BNX2X_RECOVERY_FAILED;
7478
7479                                 PMD_DRV_LOG(NOTICE,
7480                                             "Recovery flow hasn't properly "
7481                                             "completed yet, try again later. "
7482                                             "If you still see this message after a "
7483                                             "few retries then power cycle is required.");
7484
7485                                 rc = -ENXIO;
7486                                 goto bnx2x_init_done;
7487                         } while (0);
7488                 }
7489         }
7490
7491         sc->recovery_state = BNX2X_RECOVERY_DONE;
7492
7493         rc = bnx2x_nic_load(sc);
7494
7495 bnx2x_init_done:
7496
7497         if (rc) {
7498                 PMD_DRV_LOG(NOTICE, "Initialization failed, "
7499                             "stack notified driver is NOT running!");
7500         }
7501
7502         return rc;
7503 }
7504
7505 static void bnx2x_get_function_num(struct bnx2x_softc *sc)
7506 {
7507         uint32_t val = 0;
7508
7509         /*
7510          * Read the ME register to get the function number. The ME register
7511          * holds the relative-function number and absolute-function number. The
7512          * absolute-function number appears only in E2 and above. Before that
7513          * these bits always contained zero, therefore we cannot blindly use them.
7514          */
7515
7516         val = REG_RD(sc, BAR_ME_REGISTER);
7517
7518         sc->pfunc_rel =
7519             (uint8_t) ((val & ME_REG_PF_NUM) >> ME_REG_PF_NUM_SHIFT);
7520         sc->path_id =
7521             (uint8_t) ((val & ME_REG_ABS_PF_NUM) >> ME_REG_ABS_PF_NUM_SHIFT) &
7522             1;
7523
7524         if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7525                 sc->pfunc_abs = ((sc->pfunc_rel << 1) | sc->path_id);
7526         } else {
7527                 sc->pfunc_abs = (sc->pfunc_rel | sc->path_id);
7528         }
7529
7530         PMD_DRV_LOG(DEBUG,
7531                     "Relative function %d, Absolute function %d, Path %d",
7532                     sc->pfunc_rel, sc->pfunc_abs, sc->path_id);
7533 }
7534
7535 static uint32_t bnx2x_get_shmem_mf_cfg_base(struct bnx2x_softc *sc)
7536 {
7537         uint32_t shmem2_size;
7538         uint32_t offset;
7539         uint32_t mf_cfg_offset_value;
7540
7541         /* Non 57712 */
7542         offset = (SHMEM_ADDR(sc, func_mb) +
7543                   (MAX_FUNC_NUM * sizeof(struct drv_func_mb)));
7544
7545         /* 57712 plus */
7546         if (sc->devinfo.shmem2_base != 0) {
7547                 shmem2_size = SHMEM2_RD(sc, size);
7548                 if (shmem2_size > offsetof(struct shmem2_region, mf_cfg_addr)) {
7549                         mf_cfg_offset_value = SHMEM2_RD(sc, mf_cfg_addr);
7550                         if (SHMEM_MF_CFG_ADDR_NONE != mf_cfg_offset_value) {
7551                                 offset = mf_cfg_offset_value;
7552                         }
7553                 }
7554         }
7555
7556         return offset;
7557 }
7558
7559 static uint32_t bnx2x_pcie_capability_read(struct bnx2x_softc *sc, int reg)
7560 {
7561         uint32_t ret;
7562         struct bnx2x_pci_cap *caps;
7563
7564         /* ensure PCIe capability is enabled */
7565         caps = pci_find_cap(sc, PCIY_EXPRESS, BNX2X_PCI_CAP);
7566         if (NULL != caps) {
7567                 PMD_DRV_LOG(DEBUG, "Found PCIe capability: "
7568                             "id=0x%04X type=0x%04X addr=0x%08X",
7569                             caps->id, caps->type, caps->addr);
7570                 pci_read(sc, (caps->addr + reg), &ret, 2);
7571                 return ret;
7572         }
7573
7574         PMD_DRV_LOG(WARNING, "PCIe capability NOT FOUND!!!");
7575
7576         return 0;
7577 }
7578
7579 static uint8_t bnx2x_is_pcie_pending(struct bnx2x_softc *sc)
7580 {
7581         return bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_STA) &
7582                 PCIM_EXP_STA_TRANSACTION_PND;
7583 }
7584
7585 /*
7586 * Walk the PCI capabiites list for the device to find what features are
7587 * supported. These capabilites may be enabled/disabled by firmware so it's
7588 * best to walk the list rather than make assumptions.
7589 */
7590 static void bnx2x_probe_pci_caps(struct bnx2x_softc *sc)
7591 {
7592         PMD_INIT_FUNC_TRACE();
7593
7594         struct bnx2x_pci_cap *caps;
7595         uint16_t link_status;
7596 #ifdef RTE_LIBRTE_BNX2X_DEBUG
7597         int reg = 0;
7598 #endif
7599
7600         /* check if PCI Power Management is enabled */
7601         caps = pci_find_cap(sc, PCIY_PMG, BNX2X_PCI_CAP);
7602         if (NULL != caps) {
7603                 PMD_DRV_LOG(DEBUG, "Found PM capability: "
7604                             "id=0x%04X type=0x%04X addr=0x%08X",
7605                             caps->id, caps->type, caps->addr);
7606
7607                 sc->devinfo.pcie_cap_flags |= BNX2X_PM_CAPABLE_FLAG;
7608                 sc->devinfo.pcie_pm_cap_reg = caps->addr;
7609         }
7610
7611         link_status = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_LINK_STA);
7612
7613         sc->devinfo.pcie_link_speed = (link_status & PCIM_LINK_STA_SPEED);
7614         sc->devinfo.pcie_link_width =
7615             ((link_status & PCIM_LINK_STA_WIDTH) >> 4);
7616
7617         PMD_DRV_LOG(DEBUG, "PCIe link speed=%d width=%d",
7618                     sc->devinfo.pcie_link_speed, sc->devinfo.pcie_link_width);
7619
7620         sc->devinfo.pcie_cap_flags |= BNX2X_PCIE_CAPABLE_FLAG;
7621
7622         /* check if MSI capability is enabled */
7623         caps = pci_find_cap(sc, PCIY_MSI, BNX2X_PCI_CAP);
7624         if (NULL != caps) {
7625                 PMD_DRV_LOG(DEBUG, "Found MSI capability at 0x%04x", reg);
7626
7627                 sc->devinfo.pcie_cap_flags |= BNX2X_MSI_CAPABLE_FLAG;
7628                 sc->devinfo.pcie_msi_cap_reg = caps->addr;
7629         }
7630
7631         /* check if MSI-X capability is enabled */
7632         caps = pci_find_cap(sc, PCIY_MSIX, BNX2X_PCI_CAP);
7633         if (NULL != caps) {
7634                 PMD_DRV_LOG(DEBUG, "Found MSI-X capability at 0x%04x", reg);
7635
7636                 sc->devinfo.pcie_cap_flags |= BNX2X_MSIX_CAPABLE_FLAG;
7637                 sc->devinfo.pcie_msix_cap_reg = caps->addr;
7638         }
7639 }
7640
7641 static int bnx2x_get_shmem_mf_cfg_info_sd(struct bnx2x_softc *sc)
7642 {
7643         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7644         uint32_t val;
7645
7646         /* get the outer vlan if we're in switch-dependent mode */
7647
7648         val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7649         mf_info->ext_id = (uint16_t) val;
7650
7651         mf_info->multi_vnics_mode = 1;
7652
7653         if (!VALID_OVLAN(mf_info->ext_id)) {
7654                 PMD_DRV_LOG(NOTICE, "Invalid VLAN (%d)", mf_info->ext_id);
7655                 return 1;
7656         }
7657
7658         /* get the capabilities */
7659         if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK) ==
7660             FUNC_MF_CFG_PROTOCOL_ISCSI) {
7661                 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ISCSI;
7662         } else if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK)
7663                    == FUNC_MF_CFG_PROTOCOL_FCOE) {
7664                 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_FCOE;
7665         } else {
7666                 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ETHERNET;
7667         }
7668
7669         mf_info->vnics_per_port =
7670             (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7671
7672         return 0;
7673 }
7674
7675 static uint32_t bnx2x_get_shmem_ext_proto_support_flags(struct bnx2x_softc *sc)
7676 {
7677         uint32_t retval = 0;
7678         uint32_t val;
7679
7680         val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7681
7682         if (val & MACP_FUNC_CFG_FLAGS_ENABLED) {
7683                 if (val & MACP_FUNC_CFG_FLAGS_ETHERNET) {
7684                         retval |= MF_PROTO_SUPPORT_ETHERNET;
7685                 }
7686                 if (val & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
7687                         retval |= MF_PROTO_SUPPORT_ISCSI;
7688                 }
7689                 if (val & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
7690                         retval |= MF_PROTO_SUPPORT_FCOE;
7691                 }
7692         }
7693
7694         return retval;
7695 }
7696
7697 static int bnx2x_get_shmem_mf_cfg_info_si(struct bnx2x_softc *sc)
7698 {
7699         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7700         uint32_t val;
7701
7702         /*
7703          * There is no outer vlan if we're in switch-independent mode.
7704          * If the mac is valid then assume multi-function.
7705          */
7706
7707         val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7708
7709         mf_info->multi_vnics_mode = ((val & MACP_FUNC_CFG_FLAGS_MASK) != 0);
7710
7711         mf_info->mf_protos_supported =
7712             bnx2x_get_shmem_ext_proto_support_flags(sc);
7713
7714         mf_info->vnics_per_port =
7715             (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7716
7717         return 0;
7718 }
7719
7720 static int bnx2x_get_shmem_mf_cfg_info_niv(struct bnx2x_softc *sc)
7721 {
7722         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7723         uint32_t e1hov_tag;
7724         uint32_t func_config;
7725         uint32_t niv_config;
7726
7727         mf_info->multi_vnics_mode = 1;
7728
7729         e1hov_tag = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7730         func_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7731         niv_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].afex_config);
7732
7733         mf_info->ext_id =
7734             (uint16_t) ((e1hov_tag & FUNC_MF_CFG_E1HOV_TAG_MASK) >>
7735                         FUNC_MF_CFG_E1HOV_TAG_SHIFT);
7736
7737         mf_info->default_vlan =
7738             (uint16_t) ((e1hov_tag & FUNC_MF_CFG_AFEX_VLAN_MASK) >>
7739                         FUNC_MF_CFG_AFEX_VLAN_SHIFT);
7740
7741         mf_info->niv_allowed_priorities =
7742             (uint8_t) ((niv_config & FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
7743                        FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT);
7744
7745         mf_info->niv_default_cos =
7746             (uint8_t) ((func_config & FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
7747                        FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT);
7748
7749         mf_info->afex_vlan_mode =
7750             ((niv_config & FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
7751              FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT);
7752
7753         mf_info->niv_mba_enabled =
7754             ((niv_config & FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK) >>
7755              FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT);
7756
7757         mf_info->mf_protos_supported =
7758             bnx2x_get_shmem_ext_proto_support_flags(sc);
7759
7760         mf_info->vnics_per_port =
7761             (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7762
7763         return 0;
7764 }
7765
7766 static int bnx2x_check_valid_mf_cfg(struct bnx2x_softc *sc)
7767 {
7768         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7769         uint32_t mf_cfg1;
7770         uint32_t mf_cfg2;
7771         uint32_t ovlan1;
7772         uint32_t ovlan2;
7773         uint8_t i, j;
7774
7775         /* various MF mode sanity checks... */
7776
7777         if (mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_HIDE) {
7778                 PMD_DRV_LOG(NOTICE,
7779                             "Enumerated function %d is marked as hidden",
7780                             SC_PORT(sc));
7781                 return 1;
7782         }
7783
7784         if ((mf_info->vnics_per_port > 1) && !mf_info->multi_vnics_mode) {
7785                 PMD_DRV_LOG(NOTICE, "vnics_per_port=%d multi_vnics_mode=%d",
7786                             mf_info->vnics_per_port, mf_info->multi_vnics_mode);
7787                 return 1;
7788         }
7789
7790         if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7791 /* vnic id > 0 must have valid ovlan in switch-dependent mode */
7792                 if ((SC_VN(sc) > 0) && !VALID_OVLAN(OVLAN(sc))) {
7793                         PMD_DRV_LOG(NOTICE, "mf_mode=SD vnic_id=%d ovlan=%d",
7794                                     SC_VN(sc), OVLAN(sc));
7795                         return 1;
7796                 }
7797
7798                 if (!VALID_OVLAN(OVLAN(sc)) && mf_info->multi_vnics_mode) {
7799                         PMD_DRV_LOG(NOTICE,
7800                                     "mf_mode=SD multi_vnics_mode=%d ovlan=%d",
7801                                     mf_info->multi_vnics_mode, OVLAN(sc));
7802                         return 1;
7803                 }
7804
7805 /*
7806  * Verify all functions are either MF or SF mode. If MF, make sure
7807  * sure that all non-hidden functions have a valid ovlan. If SF,
7808  * make sure that all non-hidden functions have an invalid ovlan.
7809  */
7810                 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7811                         mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7812                         ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7813                         if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE) &&
7814                             (((mf_info->multi_vnics_mode)
7815                               && !VALID_OVLAN(ovlan1))
7816                              || ((!mf_info->multi_vnics_mode)
7817                                  && VALID_OVLAN(ovlan1)))) {
7818                                 PMD_DRV_LOG(NOTICE,
7819                                             "mf_mode=SD function %d MF config "
7820                                             "mismatch, multi_vnics_mode=%d ovlan=%d",
7821                                             i, mf_info->multi_vnics_mode,
7822                                             ovlan1);
7823                                 return 1;
7824                         }
7825                 }
7826
7827 /* Verify all funcs on the same port each have a different ovlan. */
7828                 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7829                         mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7830                         ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7831                         /* iterate from the next function on the port to the max func */
7832                         for (j = i + 2; j < MAX_FUNC_NUM; j += 2) {
7833                                 mf_cfg2 =
7834                                     MFCFG_RD(sc, func_mf_config[j].config);
7835                                 ovlan2 =
7836                                     MFCFG_RD(sc, func_mf_config[j].e1hov_tag);
7837                                 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE)
7838                                     && VALID_OVLAN(ovlan1)
7839                                     && !(mf_cfg2 & FUNC_MF_CFG_FUNC_HIDE)
7840                                     && VALID_OVLAN(ovlan2)
7841                                     && (ovlan1 == ovlan2)) {
7842                                         PMD_DRV_LOG(NOTICE,
7843                                                     "mf_mode=SD functions %d and %d "
7844                                                     "have the same ovlan (%d)",
7845                                                     i, j, ovlan1);
7846                                         return 1;
7847                                 }
7848                         }
7849                 }
7850         }
7851         /* MULTI_FUNCTION_SD */
7852         return 0;
7853 }
7854
7855 static int bnx2x_get_mf_cfg_info(struct bnx2x_softc *sc)
7856 {
7857         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7858         uint32_t val, mac_upper;
7859         uint8_t i, vnic;
7860
7861         /* initialize mf_info defaults */
7862         mf_info->vnics_per_port = 1;
7863         mf_info->multi_vnics_mode = FALSE;
7864         mf_info->path_has_ovlan = FALSE;
7865         mf_info->mf_mode = SINGLE_FUNCTION;
7866
7867         if (!CHIP_IS_MF_CAP(sc)) {
7868                 return 0;
7869         }
7870
7871         if (sc->devinfo.mf_cfg_base == SHMEM_MF_CFG_ADDR_NONE) {
7872                 PMD_DRV_LOG(NOTICE, "Invalid mf_cfg_base!");
7873                 return 1;
7874         }
7875
7876         /* get the MF mode (switch dependent / independent / single-function) */
7877
7878         val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
7879
7880         switch (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK) {
7881         case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
7882
7883                 mac_upper =
7884                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7885
7886                 /* check for legal upper mac bytes */
7887                 if (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT) {
7888                         mf_info->mf_mode = MULTI_FUNCTION_SI;
7889                 } else {
7890                         PMD_DRV_LOG(NOTICE,
7891                                     "Invalid config for Switch Independent mode");
7892                 }
7893
7894                 break;
7895
7896         case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
7897         case SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4:
7898
7899                 /* get outer vlan configuration */
7900                 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7901
7902                 if ((val & FUNC_MF_CFG_E1HOV_TAG_MASK) !=
7903                     FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
7904                         mf_info->mf_mode = MULTI_FUNCTION_SD;
7905                 } else {
7906                         PMD_DRV_LOG(NOTICE,
7907                                     "Invalid config for Switch Dependent mode");
7908                 }
7909
7910                 break;
7911
7912         case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
7913
7914                 /* not in MF mode, vnics_per_port=1 and multi_vnics_mode=FALSE */
7915                 return 0;
7916
7917         case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
7918
7919                 /*
7920                  * Mark MF mode as NIV if MCP version includes NPAR-SD support
7921                  * and the MAC address is valid.
7922                  */
7923                 mac_upper =
7924                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7925
7926                 if ((SHMEM2_HAS(sc, afex_driver_support)) &&
7927                     (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT)) {
7928                         mf_info->mf_mode = MULTI_FUNCTION_AFEX;
7929                 } else {
7930                         PMD_DRV_LOG(NOTICE, "Invalid config for AFEX mode");
7931                 }
7932
7933                 break;
7934
7935         default:
7936
7937                 PMD_DRV_LOG(NOTICE, "Unknown MF mode (0x%08x)",
7938                             (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK));
7939
7940                 return 1;
7941         }
7942
7943         /* set path mf_mode (which could be different than function mf_mode) */
7944         if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7945                 mf_info->path_has_ovlan = TRUE;
7946         } else if (mf_info->mf_mode == SINGLE_FUNCTION) {
7947 /*
7948  * Decide on path multi vnics mode. If we're not in MF mode and in
7949  * 4-port mode, this is good enough to check vnic-0 of the other port
7950  * on the same path
7951  */
7952                 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7953                         uint8_t other_port = !(PORT_ID(sc) & 1);
7954                         uint8_t abs_func_other_port =
7955                             (SC_PATH(sc) + (2 * other_port));
7956
7957                         val =
7958                             MFCFG_RD(sc,
7959                                      func_mf_config
7960                                      [abs_func_other_port].e1hov_tag);
7961
7962                         mf_info->path_has_ovlan = VALID_OVLAN((uint16_t) val);
7963                 }
7964         }
7965
7966         if (mf_info->mf_mode == SINGLE_FUNCTION) {
7967 /* invalid MF config */
7968                 if (SC_VN(sc) >= 1) {
7969                         PMD_DRV_LOG(NOTICE, "VNIC ID >= 1 in SF mode");
7970                         return 1;
7971                 }
7972
7973                 return 0;
7974         }
7975
7976         /* get the MF configuration */
7977         mf_info->mf_config[SC_VN(sc)] =
7978             MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7979
7980         switch (mf_info->mf_mode) {
7981         case MULTI_FUNCTION_SD:
7982
7983                 bnx2x_get_shmem_mf_cfg_info_sd(sc);
7984                 break;
7985
7986         case MULTI_FUNCTION_SI:
7987
7988                 bnx2x_get_shmem_mf_cfg_info_si(sc);
7989                 break;
7990
7991         case MULTI_FUNCTION_AFEX:
7992
7993                 bnx2x_get_shmem_mf_cfg_info_niv(sc);
7994                 break;
7995
7996         default:
7997
7998                 PMD_DRV_LOG(NOTICE, "Get MF config failed (mf_mode=0x%08x)",
7999                             mf_info->mf_mode);
8000                 return 1;
8001         }
8002
8003         /* get the congestion management parameters */
8004
8005         vnic = 0;
8006         FOREACH_ABS_FUNC_IN_PORT(sc, i) {
8007 /* get min/max bw */
8008                 val = MFCFG_RD(sc, func_mf_config[i].config);
8009                 mf_info->min_bw[vnic] =
8010                     ((val & FUNC_MF_CFG_MIN_BW_MASK) >>
8011                      FUNC_MF_CFG_MIN_BW_SHIFT);
8012                 mf_info->max_bw[vnic] =
8013                     ((val & FUNC_MF_CFG_MAX_BW_MASK) >>
8014                      FUNC_MF_CFG_MAX_BW_SHIFT);
8015                 vnic++;
8016         }
8017
8018         return bnx2x_check_valid_mf_cfg(sc);
8019 }
8020
8021 static int bnx2x_get_shmem_info(struct bnx2x_softc *sc)
8022 {
8023         int port;
8024         uint32_t mac_hi, mac_lo, val;
8025
8026         PMD_INIT_FUNC_TRACE();
8027
8028         port = SC_PORT(sc);
8029         mac_hi = mac_lo = 0;
8030
8031         sc->link_params.sc = sc;
8032         sc->link_params.port = port;
8033
8034         /* get the hardware config info */
8035         sc->devinfo.hw_config = SHMEM_RD(sc, dev_info.shared_hw_config.config);
8036         sc->devinfo.hw_config2 =
8037             SHMEM_RD(sc, dev_info.shared_hw_config.config2);
8038
8039         sc->link_params.hw_led_mode =
8040             ((sc->devinfo.hw_config & SHARED_HW_CFG_LED_MODE_MASK) >>
8041              SHARED_HW_CFG_LED_MODE_SHIFT);
8042
8043         /* get the port feature config */
8044         sc->port.config =
8045             SHMEM_RD(sc, dev_info.port_feature_config[port].config);
8046
8047         /* get the link params */
8048         sc->link_params.speed_cap_mask[ELINK_INT_PHY] =
8049             SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask)
8050             & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
8051         sc->link_params.speed_cap_mask[ELINK_EXT_PHY1] =
8052             SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask2)
8053             & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
8054
8055         /* get the lane config */
8056         sc->link_params.lane_config =
8057             SHMEM_RD(sc, dev_info.port_hw_config[port].lane_config);
8058
8059         /* get the link config */
8060         val = SHMEM_RD(sc, dev_info.port_feature_config[port].link_config);
8061         sc->port.link_config[ELINK_INT_PHY] = val;
8062         sc->link_params.switch_cfg = (val & PORT_FEATURE_CONNECTED_SWITCH_MASK);
8063         sc->port.link_config[ELINK_EXT_PHY1] =
8064             SHMEM_RD(sc, dev_info.port_feature_config[port].link_config2);
8065
8066         /* get the override preemphasis flag and enable it or turn it off */
8067         val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
8068         if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) {
8069                 sc->link_params.feature_config_flags |=
8070                     ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8071         } else {
8072                 sc->link_params.feature_config_flags &=
8073                     ~ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8074         }
8075
8076         /* get the initial value of the link params */
8077         sc->link_params.multi_phy_config =
8078             SHMEM_RD(sc, dev_info.port_hw_config[port].multi_phy_config);
8079
8080         /* get external phy info */
8081         sc->port.ext_phy_config =
8082             SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
8083
8084         /* get the multifunction configuration */
8085         bnx2x_get_mf_cfg_info(sc);
8086
8087         /* get the mac address */
8088         if (IS_MF(sc)) {
8089                 mac_hi =
8090                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
8091                 mac_lo =
8092                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_lower);
8093         } else {
8094                 mac_hi = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_upper);
8095                 mac_lo = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_lower);
8096         }
8097
8098         if ((mac_lo == 0) && (mac_hi == 0)) {
8099                 *sc->mac_addr_str = 0;
8100                 PMD_DRV_LOG(NOTICE, "No Ethernet address programmed!");
8101         } else {
8102                 sc->link_params.mac_addr[0] = (uint8_t) (mac_hi >> 8);
8103                 sc->link_params.mac_addr[1] = (uint8_t) (mac_hi);
8104                 sc->link_params.mac_addr[2] = (uint8_t) (mac_lo >> 24);
8105                 sc->link_params.mac_addr[3] = (uint8_t) (mac_lo >> 16);
8106                 sc->link_params.mac_addr[4] = (uint8_t) (mac_lo >> 8);
8107                 sc->link_params.mac_addr[5] = (uint8_t) (mac_lo);
8108                 snprintf(sc->mac_addr_str, sizeof(sc->mac_addr_str),
8109                          "%02x:%02x:%02x:%02x:%02x:%02x",
8110                          sc->link_params.mac_addr[0],
8111                          sc->link_params.mac_addr[1],
8112                          sc->link_params.mac_addr[2],
8113                          sc->link_params.mac_addr[3],
8114                          sc->link_params.mac_addr[4],
8115                          sc->link_params.mac_addr[5]);
8116                 PMD_DRV_LOG(DEBUG, "Ethernet address: %s", sc->mac_addr_str);
8117         }
8118
8119         return 0;
8120 }
8121
8122 static void bnx2x_media_detect(struct bnx2x_softc *sc)
8123 {
8124         uint32_t phy_idx = bnx2x_get_cur_phy_idx(sc);
8125         switch (sc->link_params.phy[phy_idx].media_type) {
8126         case ELINK_ETH_PHY_SFPP_10G_FIBER:
8127         case ELINK_ETH_PHY_SFP_1G_FIBER:
8128         case ELINK_ETH_PHY_XFP_FIBER:
8129         case ELINK_ETH_PHY_KR:
8130         case ELINK_ETH_PHY_CX4:
8131                 PMD_DRV_LOG(INFO, "Found 10GBase-CX4 media.");
8132                 sc->media = IFM_10G_CX4;
8133                 break;
8134         case ELINK_ETH_PHY_DA_TWINAX:
8135                 PMD_DRV_LOG(INFO, "Found 10Gb Twinax media.");
8136                 sc->media = IFM_10G_TWINAX;
8137                 break;
8138         case ELINK_ETH_PHY_BASE_T:
8139                 PMD_DRV_LOG(INFO, "Found 10GBase-T media.");
8140                 sc->media = IFM_10G_T;
8141                 break;
8142         case ELINK_ETH_PHY_NOT_PRESENT:
8143                 PMD_DRV_LOG(INFO, "Media not present.");
8144                 sc->media = 0;
8145                 break;
8146         case ELINK_ETH_PHY_UNSPECIFIED:
8147         default:
8148                 PMD_DRV_LOG(INFO, "Unknown media!");
8149                 sc->media = 0;
8150                 break;
8151         }
8152 }
8153
8154 #define GET_FIELD(value, fname)                     \
8155 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
8156 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
8157 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
8158
8159 static int bnx2x_get_igu_cam_info(struct bnx2x_softc *sc)
8160 {
8161         int pfid = SC_FUNC(sc);
8162         int igu_sb_id;
8163         uint32_t val;
8164         uint8_t fid, igu_sb_cnt = 0;
8165
8166         sc->igu_base_sb = 0xff;
8167
8168         if (CHIP_INT_MODE_IS_BC(sc)) {
8169                 int vn = SC_VN(sc);
8170                 igu_sb_cnt = sc->igu_sb_cnt;
8171                 sc->igu_base_sb = ((CHIP_IS_MODE_4_PORT(sc) ? pfid : vn) *
8172                                    FP_SB_MAX_E1x);
8173                 sc->igu_dsb_id = (E1HVN_MAX * FP_SB_MAX_E1x +
8174                                   (CHIP_IS_MODE_4_PORT(sc) ? pfid : vn));
8175                 return 0;
8176         }
8177
8178         /* IGU in normal mode - read CAM */
8179         for (igu_sb_id = 0;
8180              igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; igu_sb_id++) {
8181                 val = REG_RD(sc, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
8182                 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) {
8183                         continue;
8184                 }
8185                 fid = IGU_FID(val);
8186                 if ((fid & IGU_FID_ENCODE_IS_PF)) {
8187                         if ((fid & IGU_FID_PF_NUM_MASK) != pfid) {
8188                                 continue;
8189                         }
8190                         if (IGU_VEC(val) == 0) {
8191                                 /* default status block */
8192                                 sc->igu_dsb_id = igu_sb_id;
8193                         } else {
8194                                 if (sc->igu_base_sb == 0xff) {
8195                                         sc->igu_base_sb = igu_sb_id;
8196                                 }
8197                                 igu_sb_cnt++;
8198                         }
8199                 }
8200         }
8201
8202         /*
8203          * Due to new PF resource allocation by MFW T7.4 and above, it's optional
8204          * that number of CAM entries will not be equal to the value advertised in
8205          * PCI. Driver should use the minimal value of both as the actual status
8206          * block count
8207          */
8208         sc->igu_sb_cnt = min(sc->igu_sb_cnt, igu_sb_cnt);
8209
8210         if (igu_sb_cnt == 0) {
8211                 PMD_DRV_LOG(ERR, "CAM configuration error");
8212                 return -1;
8213         }
8214
8215         return 0;
8216 }
8217
8218 /*
8219 * Gather various information from the device config space, the device itself,
8220 * shmem, and the user input.
8221 */
8222 static int bnx2x_get_device_info(struct bnx2x_softc *sc)
8223 {
8224         uint32_t val;
8225         int rc;
8226
8227         /* get the chip revision (chip metal comes from pci config space) */
8228         sc->devinfo.chip_id = sc->link_params.chip_id =
8229             (((REG_RD(sc, MISC_REG_CHIP_NUM) & 0xffff) << 16) |
8230              ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12) |
8231              (((REG_RD(sc, PCICFG_OFFSET + PCI_ID_VAL3) >> 24) & 0xf) << 4) |
8232              ((REG_RD(sc, MISC_REG_BOND_ID) & 0xf) << 0));
8233
8234         /* force 57811 according to MISC register */
8235         if (REG_RD(sc, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
8236                 if (CHIP_IS_57810(sc)) {
8237                         sc->devinfo.chip_id = ((CHIP_NUM_57811 << 16) |
8238                                                (sc->
8239                                                 devinfo.chip_id & 0x0000ffff));
8240                 } else if (CHIP_IS_57810_MF(sc)) {
8241                         sc->devinfo.chip_id = ((CHIP_NUM_57811_MF << 16) |
8242                                                (sc->
8243                                                 devinfo.chip_id & 0x0000ffff));
8244                 }
8245                 sc->devinfo.chip_id |= 0x1;
8246         }
8247
8248         PMD_DRV_LOG(DEBUG,
8249                     "chip_id=0x%08x (num=0x%04x rev=0x%01x metal=0x%02x bond=0x%01x)",
8250                     sc->devinfo.chip_id,
8251                     ((sc->devinfo.chip_id >> 16) & 0xffff),
8252                     ((sc->devinfo.chip_id >> 12) & 0xf),
8253                     ((sc->devinfo.chip_id >> 4) & 0xff),
8254                     ((sc->devinfo.chip_id >> 0) & 0xf));
8255
8256         val = (REG_RD(sc, 0x2874) & 0x55);
8257         if ((sc->devinfo.chip_id & 0x1) || (CHIP_IS_E1H(sc) && (val == 0x55))) {
8258                 sc->flags |= BNX2X_ONE_PORT_FLAG;
8259                 PMD_DRV_LOG(DEBUG, "single port device");
8260         }
8261
8262         /* set the doorbell size */
8263         sc->doorbell_size = (1 << BNX2X_DB_SHIFT);
8264
8265         /* determine whether the device is in 2 port or 4 port mode */
8266         sc->devinfo.chip_port_mode = CHIP_PORT_MODE_NONE;       /* E1h */
8267         if (CHIP_IS_E2E3(sc)) {
8268 /*
8269  * Read port4mode_en_ovwr[0]:
8270  *   If 1, four port mode is in port4mode_en_ovwr[1].
8271  *   If 0, four port mode is in port4mode_en[0].
8272  */
8273                 val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);
8274                 if (val & 1) {
8275                         val = ((val >> 1) & 1);
8276                 } else {
8277                         val = REG_RD(sc, MISC_REG_PORT4MODE_EN);
8278                 }
8279
8280                 sc->devinfo.chip_port_mode =
8281                     (val) ? CHIP_4_PORT_MODE : CHIP_2_PORT_MODE;
8282
8283                 PMD_DRV_LOG(DEBUG, "Port mode = %s", (val) ? "4" : "2");
8284         }
8285
8286         /* get the function and path info for the device */
8287         bnx2x_get_function_num(sc);
8288
8289         /* get the shared memory base address */
8290         sc->devinfo.shmem_base =
8291             sc->link_params.shmem_base = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
8292         sc->devinfo.shmem2_base =
8293             REG_RD(sc, (SC_PATH(sc) ? MISC_REG_GENERIC_CR_1 :
8294                         MISC_REG_GENERIC_CR_0));
8295
8296         if (!sc->devinfo.shmem_base) {
8297 /* this should ONLY prevent upcoming shmem reads */
8298                 PMD_DRV_LOG(INFO, "MCP not active");
8299                 sc->flags |= BNX2X_NO_MCP_FLAG;
8300                 return 0;
8301         }
8302
8303         /* make sure the shared memory contents are valid */
8304         val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
8305         if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) !=
8306             (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) {
8307                 PMD_DRV_LOG(NOTICE, "Invalid SHMEM validity signature: 0x%08x",
8308                             val);
8309                 return 0;
8310         }
8311
8312         /* get the bootcode version */
8313         sc->devinfo.bc_ver = SHMEM_RD(sc, dev_info.bc_rev);
8314         snprintf(sc->devinfo.bc_ver_str,
8315                  sizeof(sc->devinfo.bc_ver_str),
8316                  "%d.%d.%d",
8317                  ((sc->devinfo.bc_ver >> 24) & 0xff),
8318                  ((sc->devinfo.bc_ver >> 16) & 0xff),
8319                  ((sc->devinfo.bc_ver >> 8) & 0xff));
8320         PMD_DRV_LOG(INFO, "Bootcode version: %s", sc->devinfo.bc_ver_str);
8321
8322         /* get the bootcode shmem address */
8323         sc->devinfo.mf_cfg_base = bnx2x_get_shmem_mf_cfg_base(sc);
8324
8325         /* clean indirect addresses as they're not used */
8326         pci_write_long(sc, PCICFG_GRC_ADDRESS, 0);
8327         if (IS_PF(sc)) {
8328                 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F0, 0);
8329                 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F0, 0);
8330                 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F0, 0);
8331                 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F0, 0);
8332                 if (CHIP_IS_E1x(sc)) {
8333                         REG_WR(sc, PXP2_REG_PGL_ADDR_88_F1, 0);
8334                         REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F1, 0);
8335                         REG_WR(sc, PXP2_REG_PGL_ADDR_90_F1, 0);
8336                         REG_WR(sc, PXP2_REG_PGL_ADDR_94_F1, 0);
8337                 }
8338
8339 /*
8340  * Enable internal target-read (in case we are probed after PF
8341  * FLR). Must be done prior to any BAR read access. Only for
8342  * 57712 and up
8343  */
8344                 if (!CHIP_IS_E1x(sc)) {
8345                         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ,
8346                                1);
8347                 }
8348         }
8349
8350         /* get the nvram size */
8351         val = REG_RD(sc, MCP_REG_MCPR_NVM_CFG4);
8352         sc->devinfo.flash_size =
8353             (NVRAM_1MB_SIZE << (val & MCPR_NVM_CFG4_FLASH_SIZE));
8354
8355         bnx2x_set_power_state(sc, PCI_PM_D0);
8356         /* get various configuration parameters from shmem */
8357         bnx2x_get_shmem_info(sc);
8358
8359         /* initialize IGU parameters */
8360         if (CHIP_IS_E1x(sc)) {
8361                 sc->devinfo.int_block = INT_BLOCK_HC;
8362                 sc->igu_dsb_id = DEF_SB_IGU_ID;
8363                 sc->igu_base_sb = 0;
8364         } else {
8365                 sc->devinfo.int_block = INT_BLOCK_IGU;
8366
8367 /* do not allow device reset during IGU info preocessing */
8368                 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8369
8370                 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
8371
8372                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8373                         int tout = 5000;
8374
8375                         val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
8376                         REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION, val);
8377                         REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x7f);
8378
8379                         while (tout && REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8380                                 tout--;
8381                                 DELAY(1000);
8382                         }
8383
8384                         if (REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8385                                 PMD_DRV_LOG(NOTICE,
8386                                             "FORCING IGU Normal Mode failed!!!");
8387                                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8388                                 return -1;
8389                         }
8390                 }
8391
8392                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8393                         PMD_DRV_LOG(DEBUG, "IGU Backward Compatible Mode");
8394                         sc->devinfo.int_block |= INT_BLOCK_MODE_BW_COMP;
8395                 } else {
8396                         PMD_DRV_LOG(DEBUG, "IGU Normal Mode");
8397                 }
8398
8399                 rc = bnx2x_get_igu_cam_info(sc);
8400
8401                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8402
8403                 if (rc) {
8404                         return rc;
8405                 }
8406         }
8407
8408         /*
8409          * Get base FW non-default (fast path) status block ID. This value is
8410          * used to initialize the fw_sb_id saved on the fp/queue structure to
8411          * determine the id used by the FW.
8412          */
8413         if (CHIP_IS_E1x(sc)) {
8414                 sc->base_fw_ndsb =
8415                     ((SC_PORT(sc) * FP_SB_MAX_E1x) + SC_L_ID(sc));
8416         } else {
8417 /*
8418  * 57712+ - We currently use one FW SB per IGU SB (Rx and Tx of
8419  * the same queue are indicated on the same IGU SB). So we prefer
8420  * FW and IGU SBs to be the same value.
8421  */
8422                 sc->base_fw_ndsb = sc->igu_base_sb;
8423         }
8424
8425         elink_phy_probe(&sc->link_params);
8426
8427         return 0;
8428 }
8429
8430 static void
8431 bnx2x_link_settings_supported(struct bnx2x_softc *sc, uint32_t switch_cfg)
8432 {
8433         uint32_t cfg_size = 0;
8434         uint32_t idx;
8435         uint8_t port = SC_PORT(sc);
8436
8437         /* aggregation of supported attributes of all external phys */
8438         sc->port.supported[0] = 0;
8439         sc->port.supported[1] = 0;
8440
8441         switch (sc->link_params.num_phys) {
8442         case 1:
8443                 sc->port.supported[0] =
8444                     sc->link_params.phy[ELINK_INT_PHY].supported;
8445                 cfg_size = 1;
8446                 break;
8447         case 2:
8448                 sc->port.supported[0] =
8449                     sc->link_params.phy[ELINK_EXT_PHY1].supported;
8450                 cfg_size = 1;
8451                 break;
8452         case 3:
8453                 if (sc->link_params.multi_phy_config &
8454                     PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
8455                         sc->port.supported[1] =
8456                             sc->link_params.phy[ELINK_EXT_PHY1].supported;
8457                         sc->port.supported[0] =
8458                             sc->link_params.phy[ELINK_EXT_PHY2].supported;
8459                 } else {
8460                         sc->port.supported[0] =
8461                             sc->link_params.phy[ELINK_EXT_PHY1].supported;
8462                         sc->port.supported[1] =
8463                             sc->link_params.phy[ELINK_EXT_PHY2].supported;
8464                 }
8465                 cfg_size = 2;
8466                 break;
8467         }
8468
8469         if (!(sc->port.supported[0] || sc->port.supported[1])) {
8470                 PMD_DRV_LOG(ERR,
8471                             "Invalid phy config in NVRAM (PHY1=0x%08x PHY2=0x%08x)",
8472                             SHMEM_RD(sc,
8473                                      dev_info.port_hw_config
8474                                      [port].external_phy_config),
8475                             SHMEM_RD(sc,
8476                                      dev_info.port_hw_config
8477                                      [port].external_phy_config2));
8478                 return;
8479         }
8480
8481         if (CHIP_IS_E3(sc))
8482                 sc->port.phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR);
8483         else {
8484                 switch (switch_cfg) {
8485                 case ELINK_SWITCH_CFG_1G:
8486                         sc->port.phy_addr =
8487                             REG_RD(sc,
8488                                    NIG_REG_SERDES0_CTRL_PHY_ADDR + port * 0x10);
8489                         break;
8490                 case ELINK_SWITCH_CFG_10G:
8491                         sc->port.phy_addr =
8492                             REG_RD(sc,
8493                                    NIG_REG_XGXS0_CTRL_PHY_ADDR + port * 0x18);
8494                         break;
8495                 default:
8496                         PMD_DRV_LOG(ERR,
8497                                     "Invalid switch config in"
8498                                     "link_config=0x%08x",
8499                                     sc->port.link_config[0]);
8500                         return;
8501                 }
8502         }
8503
8504         PMD_DRV_LOG(INFO, "PHY addr 0x%08x", sc->port.phy_addr);
8505
8506         /* mask what we support according to speed_cap_mask per configuration */
8507         for (idx = 0; idx < cfg_size; idx++) {
8508                 if (!(sc->link_params.speed_cap_mask[idx] &
8509                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) {
8510                         sc->port.supported[idx] &=
8511                             ~ELINK_SUPPORTED_10baseT_Half;
8512                 }
8513
8514                 if (!(sc->link_params.speed_cap_mask[idx] &
8515                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) {
8516                         sc->port.supported[idx] &=
8517                             ~ELINK_SUPPORTED_10baseT_Full;
8518                 }
8519
8520                 if (!(sc->link_params.speed_cap_mask[idx] &
8521                       PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) {
8522                         sc->port.supported[idx] &=
8523                             ~ELINK_SUPPORTED_100baseT_Half;
8524                 }
8525
8526                 if (!(sc->link_params.speed_cap_mask[idx] &
8527                       PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) {
8528                         sc->port.supported[idx] &=
8529                             ~ELINK_SUPPORTED_100baseT_Full;
8530                 }
8531
8532                 if (!(sc->link_params.speed_cap_mask[idx] &
8533                       PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) {
8534                         sc->port.supported[idx] &=
8535                             ~ELINK_SUPPORTED_1000baseT_Full;
8536                 }
8537
8538                 if (!(sc->link_params.speed_cap_mask[idx] &
8539                       PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) {
8540                         sc->port.supported[idx] &=
8541                             ~ELINK_SUPPORTED_2500baseX_Full;
8542                 }
8543
8544                 if (!(sc->link_params.speed_cap_mask[idx] &
8545                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8546                         sc->port.supported[idx] &=
8547                             ~ELINK_SUPPORTED_10000baseT_Full;
8548                 }
8549
8550                 if (!(sc->link_params.speed_cap_mask[idx] &
8551                       PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) {
8552                         sc->port.supported[idx] &=
8553                             ~ELINK_SUPPORTED_20000baseKR2_Full;
8554                 }
8555         }
8556
8557         PMD_DRV_LOG(INFO, "PHY supported 0=0x%08x 1=0x%08x",
8558                     sc->port.supported[0], sc->port.supported[1]);
8559 }
8560
8561 static void bnx2x_link_settings_requested(struct bnx2x_softc *sc)
8562 {
8563         uint32_t link_config;
8564         uint32_t idx;
8565         uint32_t cfg_size = 0;
8566
8567         sc->port.advertising[0] = 0;
8568         sc->port.advertising[1] = 0;
8569
8570         switch (sc->link_params.num_phys) {
8571         case 1:
8572         case 2:
8573                 cfg_size = 1;
8574                 break;
8575         case 3:
8576                 cfg_size = 2;
8577                 break;
8578         }
8579
8580         for (idx = 0; idx < cfg_size; idx++) {
8581                 sc->link_params.req_duplex[idx] = DUPLEX_FULL;
8582                 link_config = sc->port.link_config[idx];
8583
8584                 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
8585                 case PORT_FEATURE_LINK_SPEED_AUTO:
8586                         if (sc->port.supported[idx] & ELINK_SUPPORTED_Autoneg) {
8587                                 sc->link_params.req_line_speed[idx] =
8588                                     ELINK_SPEED_AUTO_NEG;
8589                                 sc->port.advertising[idx] |=
8590                                     sc->port.supported[idx];
8591                                 if (sc->link_params.phy[ELINK_EXT_PHY1].type ==
8592                                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833)
8593                                         sc->port.advertising[idx] |=
8594                                             (ELINK_SUPPORTED_100baseT_Half |
8595                                              ELINK_SUPPORTED_100baseT_Full);
8596                         } else {
8597                                 /* force 10G, no AN */
8598                                 sc->link_params.req_line_speed[idx] =
8599                                     ELINK_SPEED_10000;
8600                                 sc->port.advertising[idx] |=
8601                                     (ADVERTISED_10000baseT_Full |
8602                                      ADVERTISED_FIBRE);
8603                                 continue;
8604                         }
8605                         break;
8606
8607                 case PORT_FEATURE_LINK_SPEED_10M_FULL:
8608                         if (sc->
8609                             port.supported[idx] & ELINK_SUPPORTED_10baseT_Full)
8610                         {
8611                                 sc->link_params.req_line_speed[idx] =
8612                                     ELINK_SPEED_10;
8613                                 sc->port.advertising[idx] |=
8614                                     (ADVERTISED_10baseT_Full | ADVERTISED_TP);
8615                         } else {
8616                                 PMD_DRV_LOG(ERR,
8617                                             "Invalid NVRAM config link_config=0x%08x "
8618                                             "speed_cap_mask=0x%08x",
8619                                             link_config,
8620                                             sc->
8621                                             link_params.speed_cap_mask[idx]);
8622                                 return;
8623                         }
8624                         break;
8625
8626                 case PORT_FEATURE_LINK_SPEED_10M_HALF:
8627                         if (sc->
8628                             port.supported[idx] & ELINK_SUPPORTED_10baseT_Half)
8629                         {
8630                                 sc->link_params.req_line_speed[idx] =
8631                                     ELINK_SPEED_10;
8632                                 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8633                                 sc->port.advertising[idx] |=
8634                                     (ADVERTISED_10baseT_Half | ADVERTISED_TP);
8635                         } else {
8636                                 PMD_DRV_LOG(ERR,
8637                                             "Invalid NVRAM config link_config=0x%08x "
8638                                             "speed_cap_mask=0x%08x",
8639                                             link_config,
8640                                             sc->
8641                                             link_params.speed_cap_mask[idx]);
8642                                 return;
8643                         }
8644                         break;
8645
8646                 case PORT_FEATURE_LINK_SPEED_100M_FULL:
8647                         if (sc->
8648                             port.supported[idx] & ELINK_SUPPORTED_100baseT_Full)
8649                         {
8650                                 sc->link_params.req_line_speed[idx] =
8651                                     ELINK_SPEED_100;
8652                                 sc->port.advertising[idx] |=
8653                                     (ADVERTISED_100baseT_Full | ADVERTISED_TP);
8654                         } else {
8655                                 PMD_DRV_LOG(ERR,
8656                                             "Invalid NVRAM config link_config=0x%08x "
8657                                             "speed_cap_mask=0x%08x",
8658                                             link_config,
8659                                             sc->
8660                                             link_params.speed_cap_mask[idx]);
8661                                 return;
8662                         }
8663                         break;
8664
8665                 case PORT_FEATURE_LINK_SPEED_100M_HALF:
8666                         if (sc->
8667                             port.supported[idx] & ELINK_SUPPORTED_100baseT_Half)
8668                         {
8669                                 sc->link_params.req_line_speed[idx] =
8670                                     ELINK_SPEED_100;
8671                                 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8672                                 sc->port.advertising[idx] |=
8673                                     (ADVERTISED_100baseT_Half | ADVERTISED_TP);
8674                         } else {
8675                                 PMD_DRV_LOG(ERR,
8676                                             "Invalid NVRAM config link_config=0x%08x "
8677                                             "speed_cap_mask=0x%08x",
8678                                             link_config,
8679                                             sc->
8680                                             link_params.speed_cap_mask[idx]);
8681                                 return;
8682                         }
8683                         break;
8684
8685                 case PORT_FEATURE_LINK_SPEED_1G:
8686                         if (sc->port.supported[idx] &
8687                             ELINK_SUPPORTED_1000baseT_Full) {
8688                                 sc->link_params.req_line_speed[idx] =
8689                                     ELINK_SPEED_1000;
8690                                 sc->port.advertising[idx] |=
8691                                     (ADVERTISED_1000baseT_Full | ADVERTISED_TP);
8692                         } else {
8693                                 PMD_DRV_LOG(ERR,
8694                                             "Invalid NVRAM config link_config=0x%08x "
8695                                             "speed_cap_mask=0x%08x",
8696                                             link_config,
8697                                             sc->
8698                                             link_params.speed_cap_mask[idx]);
8699                                 return;
8700                         }
8701                         break;
8702
8703                 case PORT_FEATURE_LINK_SPEED_2_5G:
8704                         if (sc->port.supported[idx] &
8705                             ELINK_SUPPORTED_2500baseX_Full) {
8706                                 sc->link_params.req_line_speed[idx] =
8707                                     ELINK_SPEED_2500;
8708                                 sc->port.advertising[idx] |=
8709                                     (ADVERTISED_2500baseX_Full | ADVERTISED_TP);
8710                         } else {
8711                                 PMD_DRV_LOG(ERR,
8712                                             "Invalid NVRAM config link_config=0x%08x "
8713                                             "speed_cap_mask=0x%08x",
8714                                             link_config,
8715                                             sc->
8716                                             link_params.speed_cap_mask[idx]);
8717                                 return;
8718                         }
8719                         break;
8720
8721                 case PORT_FEATURE_LINK_SPEED_10G_CX4:
8722                         if (sc->port.supported[idx] &
8723                             ELINK_SUPPORTED_10000baseT_Full) {
8724                                 sc->link_params.req_line_speed[idx] =
8725                                     ELINK_SPEED_10000;
8726                                 sc->port.advertising[idx] |=
8727                                     (ADVERTISED_10000baseT_Full |
8728                                      ADVERTISED_FIBRE);
8729                         } else {
8730                                 PMD_DRV_LOG(ERR,
8731                                             "Invalid NVRAM config link_config=0x%08x "
8732                                             "speed_cap_mask=0x%08x",
8733                                             link_config,
8734                                             sc->
8735                                             link_params.speed_cap_mask[idx]);
8736                                 return;
8737                         }
8738                         break;
8739
8740                 case PORT_FEATURE_LINK_SPEED_20G:
8741                         sc->link_params.req_line_speed[idx] = ELINK_SPEED_20000;
8742                         break;
8743
8744                 default:
8745                         PMD_DRV_LOG(ERR,
8746                                     "Invalid NVRAM config link_config=0x%08x "
8747                                     "speed_cap_mask=0x%08x", link_config,
8748                                     sc->link_params.speed_cap_mask[idx]);
8749                         sc->link_params.req_line_speed[idx] =
8750                             ELINK_SPEED_AUTO_NEG;
8751                         sc->port.advertising[idx] = sc->port.supported[idx];
8752                         break;
8753                 }
8754
8755                 sc->link_params.req_flow_ctrl[idx] =
8756                     (link_config & PORT_FEATURE_FLOW_CONTROL_MASK);
8757
8758                 if (sc->link_params.req_flow_ctrl[idx] == ELINK_FLOW_CTRL_AUTO) {
8759                         if (!
8760                             (sc->
8761                              port.supported[idx] & ELINK_SUPPORTED_Autoneg)) {
8762                                 sc->link_params.req_flow_ctrl[idx] =
8763                                     ELINK_FLOW_CTRL_NONE;
8764                         } else {
8765                                 bnx2x_set_requested_fc(sc);
8766                         }
8767                 }
8768         }
8769 }
8770
8771 static void bnx2x_get_phy_info(struct bnx2x_softc *sc)
8772 {
8773         uint8_t port = SC_PORT(sc);
8774         uint32_t eee_mode;
8775
8776         PMD_INIT_FUNC_TRACE();
8777
8778         /* shmem data already read in bnx2x_get_shmem_info() */
8779
8780         bnx2x_link_settings_supported(sc, sc->link_params.switch_cfg);
8781         bnx2x_link_settings_requested(sc);
8782
8783         /* configure link feature according to nvram value */
8784         eee_mode =
8785             (((SHMEM_RD(sc, dev_info.port_feature_config[port].eee_power_mode))
8786               & PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
8787              PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
8788         if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
8789                 sc->link_params.eee_mode = (ELINK_EEE_MODE_ADV_LPI |
8790                                             ELINK_EEE_MODE_ENABLE_LPI |
8791                                             ELINK_EEE_MODE_OUTPUT_TIME);
8792         } else {
8793                 sc->link_params.eee_mode = 0;
8794         }
8795
8796         /* get the media type */
8797         bnx2x_media_detect(sc);
8798 }
8799
8800 static void bnx2x_set_modes_bitmap(struct bnx2x_softc *sc)
8801 {
8802         uint32_t flags = MODE_ASIC | MODE_PORT2;
8803
8804         if (CHIP_IS_E2(sc)) {
8805                 flags |= MODE_E2;
8806         } else if (CHIP_IS_E3(sc)) {
8807                 flags |= MODE_E3;
8808                 if (CHIP_REV(sc) == CHIP_REV_Ax) {
8809                         flags |= MODE_E3_A0;
8810                 } else {        /*if (CHIP_REV(sc) == CHIP_REV_Bx) */
8811
8812                         flags |= MODE_E3_B0 | MODE_COS3;
8813                 }
8814         }
8815
8816         if (IS_MF(sc)) {
8817                 flags |= MODE_MF;
8818                 switch (sc->devinfo.mf_info.mf_mode) {
8819                 case MULTI_FUNCTION_SD:
8820                         flags |= MODE_MF_SD;
8821                         break;
8822                 case MULTI_FUNCTION_SI:
8823                         flags |= MODE_MF_SI;
8824                         break;
8825                 case MULTI_FUNCTION_AFEX:
8826                         flags |= MODE_MF_AFEX;
8827                         break;
8828                 }
8829         } else {
8830                 flags |= MODE_SF;
8831         }
8832
8833 #if defined(__LITTLE_ENDIAN)
8834         flags |= MODE_LITTLE_ENDIAN;
8835 #else /* __BIG_ENDIAN */
8836         flags |= MODE_BIG_ENDIAN;
8837 #endif
8838
8839         INIT_MODE_FLAGS(sc) = flags;
8840 }
8841
8842 int bnx2x_alloc_hsi_mem(struct bnx2x_softc *sc)
8843 {
8844         struct bnx2x_fastpath *fp;
8845         char buf[32];
8846         uint32_t i;
8847
8848         if (IS_PF(sc)) {
8849 /************************/
8850 /* DEFAULT STATUS BLOCK */
8851 /************************/
8852
8853                 if (bnx2x_dma_alloc(sc, sizeof(struct host_sp_status_block),
8854                                   &sc->def_sb_dma, "def_sb",
8855                                   RTE_CACHE_LINE_SIZE) != 0) {
8856                         return -1;
8857                 }
8858
8859                 sc->def_sb =
8860                     (struct host_sp_status_block *)sc->def_sb_dma.vaddr;
8861 /***************/
8862 /* EVENT QUEUE */
8863 /***************/
8864
8865                 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8866                                   &sc->eq_dma, "ev_queue",
8867                                   RTE_CACHE_LINE_SIZE) != 0) {
8868                         sc->def_sb = NULL;
8869                         return -1;
8870                 }
8871
8872                 sc->eq = (union event_ring_elem *)sc->eq_dma.vaddr;
8873
8874 /*************/
8875 /* SLOW PATH */
8876 /*************/
8877
8878                 if (bnx2x_dma_alloc(sc, sizeof(struct bnx2x_slowpath),
8879                                   &sc->sp_dma, "sp",
8880                                   RTE_CACHE_LINE_SIZE) != 0) {
8881                         sc->eq = NULL;
8882                         sc->def_sb = NULL;
8883                         return -1;
8884                 }
8885
8886                 sc->sp = (struct bnx2x_slowpath *)sc->sp_dma.vaddr;
8887
8888 /*******************/
8889 /* SLOW PATH QUEUE */
8890 /*******************/
8891
8892                 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8893                                   &sc->spq_dma, "sp_queue",
8894                                   RTE_CACHE_LINE_SIZE) != 0) {
8895                         sc->sp = NULL;
8896                         sc->eq = NULL;
8897                         sc->def_sb = NULL;
8898                         return -1;
8899                 }
8900
8901                 sc->spq = (struct eth_spe *)sc->spq_dma.vaddr;
8902
8903 /***************************/
8904 /* FW DECOMPRESSION BUFFER */
8905 /***************************/
8906
8907                 if (bnx2x_dma_alloc(sc, FW_BUF_SIZE, &sc->gz_buf_dma,
8908                                   "fw_dec_buf", RTE_CACHE_LINE_SIZE) != 0) {
8909                         sc->spq = NULL;
8910                         sc->sp = NULL;
8911                         sc->eq = NULL;
8912                         sc->def_sb = NULL;
8913                         return -1;
8914                 }
8915
8916                 sc->gz_buf = (void *)sc->gz_buf_dma.vaddr;
8917         }
8918
8919         /*************/
8920         /* FASTPATHS */
8921         /*************/
8922
8923         /* allocate DMA memory for each fastpath structure */
8924         for (i = 0; i < sc->num_queues; i++) {
8925                 fp = &sc->fp[i];
8926                 fp->sc = sc;
8927                 fp->index = i;
8928
8929 /*******************/
8930 /* FP STATUS BLOCK */
8931 /*******************/
8932
8933                 snprintf(buf, sizeof(buf), "fp_%d_sb", i);
8934                 if (bnx2x_dma_alloc(sc, sizeof(union bnx2x_host_hc_status_block),
8935                                   &fp->sb_dma, buf, RTE_CACHE_LINE_SIZE) != 0) {
8936                         PMD_DRV_LOG(NOTICE, "Failed to alloc %s", buf);
8937                         return -1;
8938                 } else {
8939                         if (CHIP_IS_E2E3(sc)) {
8940                                 fp->status_block.e2_sb =
8941                                     (struct host_hc_status_block_e2 *)
8942                                     fp->sb_dma.vaddr;
8943                         } else {
8944                                 fp->status_block.e1x_sb =
8945                                     (struct host_hc_status_block_e1x *)
8946                                     fp->sb_dma.vaddr;
8947                         }
8948                 }
8949         }
8950
8951         return 0;
8952 }
8953
8954 void bnx2x_free_hsi_mem(struct bnx2x_softc *sc)
8955 {
8956         struct bnx2x_fastpath *fp;
8957         int i;
8958
8959         for (i = 0; i < sc->num_queues; i++) {
8960                 fp = &sc->fp[i];
8961
8962 /*******************/
8963 /* FP STATUS BLOCK */
8964 /*******************/
8965
8966                 memset(&fp->status_block, 0, sizeof(fp->status_block));
8967         }
8968
8969         /***************************/
8970         /* FW DECOMPRESSION BUFFER */
8971         /***************************/
8972
8973         sc->gz_buf = NULL;
8974
8975         /*******************/
8976         /* SLOW PATH QUEUE */
8977         /*******************/
8978
8979         sc->spq = NULL;
8980
8981         /*************/
8982         /* SLOW PATH */
8983         /*************/
8984
8985         sc->sp = NULL;
8986
8987         /***************/
8988         /* EVENT QUEUE */
8989         /***************/
8990
8991         sc->eq = NULL;
8992
8993         /************************/
8994         /* DEFAULT STATUS BLOCK */
8995         /************************/
8996
8997         sc->def_sb = NULL;
8998
8999 }
9000
9001 /*
9002 * Previous driver DMAE transaction may have occurred when pre-boot stage
9003 * ended and boot began. This would invalidate the addresses of the
9004 * transaction, resulting in was-error bit set in the PCI causing all
9005 * hw-to-host PCIe transactions to timeout. If this happened we want to clear
9006 * the interrupt which detected this from the pglueb and the was-done bit
9007 */
9008 static void bnx2x_prev_interrupted_dmae(struct bnx2x_softc *sc)
9009 {
9010         uint32_t val;
9011
9012         if (!CHIP_IS_E1x(sc)) {
9013                 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS);
9014                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
9015                         REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
9016                                1 << SC_FUNC(sc));
9017                 }
9018         }
9019 }
9020
9021 static int bnx2x_prev_mcp_done(struct bnx2x_softc *sc)
9022 {
9023         uint32_t rc = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE,
9024                                      DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
9025         if (!rc) {
9026                 PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
9027                 return -1;
9028         }
9029
9030         return 0;
9031 }
9032
9033 static struct bnx2x_prev_list_node *bnx2x_prev_path_get_entry(struct bnx2x_softc *sc)
9034 {
9035         struct bnx2x_prev_list_node *tmp;
9036
9037         LIST_FOREACH(tmp, &bnx2x_prev_list, node) {
9038                 if ((sc->pcie_bus == tmp->bus) &&
9039                     (sc->pcie_device == tmp->slot) &&
9040                     (SC_PATH(sc) == tmp->path)) {
9041                         return tmp;
9042                 }
9043         }
9044
9045         return NULL;
9046 }
9047
9048 static uint8_t bnx2x_prev_is_path_marked(struct bnx2x_softc *sc)
9049 {
9050         struct bnx2x_prev_list_node *tmp;
9051         int rc = FALSE;
9052
9053         rte_spinlock_lock(&bnx2x_prev_mtx);
9054
9055         tmp = bnx2x_prev_path_get_entry(sc);
9056         if (tmp) {
9057                 if (tmp->aer) {
9058                         PMD_DRV_LOG(DEBUG,
9059                                     "Path %d/%d/%d was marked by AER",
9060                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9061                 } else {
9062                         rc = TRUE;
9063                         PMD_DRV_LOG(DEBUG,
9064                                     "Path %d/%d/%d was already cleaned from previous drivers",
9065                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9066                 }
9067         }
9068
9069         rte_spinlock_unlock(&bnx2x_prev_mtx);
9070
9071         return rc;
9072 }
9073
9074 static int bnx2x_prev_mark_path(struct bnx2x_softc *sc, uint8_t after_undi)
9075 {
9076         struct bnx2x_prev_list_node *tmp;
9077
9078         rte_spinlock_lock(&bnx2x_prev_mtx);
9079
9080         /* Check whether the entry for this path already exists */
9081         tmp = bnx2x_prev_path_get_entry(sc);
9082         if (tmp) {
9083                 if (!tmp->aer) {
9084                         PMD_DRV_LOG(DEBUG,
9085                                     "Re-marking AER in path %d/%d/%d",
9086                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9087                 } else {
9088                         PMD_DRV_LOG(DEBUG,
9089                                     "Removing AER indication from path %d/%d/%d",
9090                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9091                         tmp->aer = 0;
9092                 }
9093
9094                 rte_spinlock_unlock(&bnx2x_prev_mtx);
9095                 return 0;
9096         }
9097
9098         rte_spinlock_unlock(&bnx2x_prev_mtx);
9099
9100         /* Create an entry for this path and add it */
9101         tmp = rte_malloc("", sizeof(struct bnx2x_prev_list_node),
9102                          RTE_CACHE_LINE_SIZE);
9103         if (!tmp) {
9104                 PMD_DRV_LOG(NOTICE, "Failed to allocate 'bnx2x_prev_list_node'");
9105                 return -1;
9106         }
9107
9108         tmp->bus = sc->pcie_bus;
9109         tmp->slot = sc->pcie_device;
9110         tmp->path = SC_PATH(sc);
9111         tmp->aer = 0;
9112         tmp->undi = after_undi ? (1 << SC_PORT(sc)) : 0;
9113
9114         rte_spinlock_lock(&bnx2x_prev_mtx);
9115
9116         LIST_INSERT_HEAD(&bnx2x_prev_list, tmp, node);
9117
9118         rte_spinlock_unlock(&bnx2x_prev_mtx);
9119
9120         return 0;
9121 }
9122
9123 static int bnx2x_do_flr(struct bnx2x_softc *sc)
9124 {
9125         int i;
9126
9127         /* only E2 and onwards support FLR */
9128         if (CHIP_IS_E1x(sc)) {
9129                 PMD_DRV_LOG(WARNING, "FLR not supported in E1H");
9130                 return -1;
9131         }
9132
9133         /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9134         if (sc->devinfo.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9135                 PMD_DRV_LOG(WARNING,
9136                             "FLR not supported by BC_VER: 0x%08x",
9137                             sc->devinfo.bc_ver);
9138                 return -1;
9139         }
9140
9141         /* Wait for Transaction Pending bit clean */
9142         for (i = 0; i < 4; i++) {
9143                 if (i) {
9144                         DELAY(((1 << (i - 1)) * 100) * 1000);
9145                 }
9146
9147                 if (!bnx2x_is_pcie_pending(sc)) {
9148                         goto clear;
9149                 }
9150         }
9151
9152         PMD_DRV_LOG(NOTICE, "PCIE transaction is not cleared, "
9153                     "proceeding with reset anyway");
9154
9155 clear:
9156         bnx2x_fw_command(sc, DRV_MSG_CODE_INITIATE_FLR, 0);
9157
9158         return 0;
9159 }
9160
9161 struct bnx2x_mac_vals {
9162         uint32_t xmac_addr;
9163         uint32_t xmac_val;
9164         uint32_t emac_addr;
9165         uint32_t emac_val;
9166         uint32_t umac_addr;
9167         uint32_t umac_val;
9168         uint32_t bmac_addr;
9169         uint32_t bmac_val[2];
9170 };
9171
9172 static void
9173 bnx2x_prev_unload_close_mac(struct bnx2x_softc *sc, struct bnx2x_mac_vals *vals)
9174 {
9175         uint32_t val, base_addr, offset, mask, reset_reg;
9176         uint8_t mac_stopped = FALSE;
9177         uint8_t port = SC_PORT(sc);
9178         uint32_t wb_data[2];
9179
9180         /* reset addresses as they also mark which values were changed */
9181         vals->bmac_addr = 0;
9182         vals->umac_addr = 0;
9183         vals->xmac_addr = 0;
9184         vals->emac_addr = 0;
9185
9186         reset_reg = REG_RD(sc, MISC_REG_RESET_REG_2);
9187
9188         if (!CHIP_IS_E3(sc)) {
9189                 val = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9190                 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9191                 if ((mask & reset_reg) && val) {
9192                         base_addr = SC_PORT(sc) ? NIG_REG_INGRESS_BMAC1_MEM
9193                             : NIG_REG_INGRESS_BMAC0_MEM;
9194                         offset = CHIP_IS_E2(sc) ? BIGMAC2_REGISTER_BMAC_CONTROL
9195                             : BIGMAC_REGISTER_BMAC_CONTROL;
9196
9197                         /*
9198                          * use rd/wr since we cannot use dmae. This is safe
9199                          * since MCP won't access the bus due to the request
9200                          * to unload, and no function on the path can be
9201                          * loaded at this time.
9202                          */
9203                         wb_data[0] = REG_RD(sc, base_addr + offset);
9204                         wb_data[1] = REG_RD(sc, base_addr + offset + 0x4);
9205                         vals->bmac_addr = base_addr + offset;
9206                         vals->bmac_val[0] = wb_data[0];
9207                         vals->bmac_val[1] = wb_data[1];
9208                         wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE;
9209                         REG_WR(sc, vals->bmac_addr, wb_data[0]);
9210                         REG_WR(sc, vals->bmac_addr + 0x4, wb_data[1]);
9211                 }
9212
9213                 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + SC_PORT(sc) * 4;
9214                 vals->emac_val = REG_RD(sc, vals->emac_addr);
9215                 REG_WR(sc, vals->emac_addr, 0);
9216                 mac_stopped = TRUE;
9217         } else {
9218                 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9219                         base_addr = SC_PORT(sc) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9220                         val = REG_RD(sc, base_addr + XMAC_REG_PFC_CTRL_HI);
9221                         REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9222                                val & ~(1 << 1));
9223                         REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9224                                val | (1 << 1));
9225                         vals->xmac_addr = base_addr + XMAC_REG_CTRL;
9226                         vals->xmac_val = REG_RD(sc, vals->xmac_addr);
9227                         REG_WR(sc, vals->xmac_addr, 0);
9228                         mac_stopped = TRUE;
9229                 }
9230
9231                 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9232                 if (mask & reset_reg) {
9233                         base_addr = SC_PORT(sc) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9234                         vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
9235                         vals->umac_val = REG_RD(sc, vals->umac_addr);
9236                         REG_WR(sc, vals->umac_addr, 0);
9237                         mac_stopped = TRUE;
9238                 }
9239         }
9240
9241         if (mac_stopped) {
9242                 DELAY(20000);
9243         }
9244 }
9245
9246 #define BNX2X_PREV_UNDI_PROD_ADDR(p)  (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9247 #define BNX2X_PREV_UNDI_RCQ(val)      ((val) & 0xffff)
9248 #define BNX2X_PREV_UNDI_BD(val)       ((val) >> 16 & 0xffff)
9249 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
9250
9251 static void
9252 bnx2x_prev_unload_undi_inc(struct bnx2x_softc *sc, uint8_t port, uint8_t inc)
9253 {
9254         uint16_t rcq, bd;
9255         uint32_t tmp_reg = REG_RD(sc, BNX2X_PREV_UNDI_PROD_ADDR(port));
9256
9257         rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9258         bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9259
9260         tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9261         REG_WR(sc, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9262 }
9263
9264 static int bnx2x_prev_unload_common(struct bnx2x_softc *sc)
9265 {
9266         uint32_t reset_reg, tmp_reg = 0, rc;
9267         uint8_t prev_undi = FALSE;
9268         struct bnx2x_mac_vals mac_vals;
9269         uint32_t timer_count = 1000;
9270         uint32_t prev_brb;
9271
9272         /*
9273          * It is possible a previous function received 'common' answer,
9274          * but hasn't loaded yet, therefore creating a scenario of
9275          * multiple functions receiving 'common' on the same path.
9276          */
9277         memset(&mac_vals, 0, sizeof(mac_vals));
9278
9279         if (bnx2x_prev_is_path_marked(sc)) {
9280                 return bnx2x_prev_mcp_done(sc);
9281         }
9282
9283         reset_reg = REG_RD(sc, MISC_REG_RESET_REG_1);
9284
9285         /* Reset should be performed after BRB is emptied */
9286         if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
9287                 /* Close the MAC Rx to prevent BRB from filling up */
9288                 bnx2x_prev_unload_close_mac(sc, &mac_vals);
9289
9290                 /* close LLH filters towards the BRB */
9291                 elink_set_rx_filter(&sc->link_params, 0);
9292
9293                 /*
9294                  * Check if the UNDI driver was previously loaded.
9295                  * UNDI driver initializes CID offset for normal bell to 0x7
9296                  */
9297                 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
9298                         tmp_reg = REG_RD(sc, DORQ_REG_NORM_CID_OFST);
9299                         if (tmp_reg == 0x7) {
9300                                 PMD_DRV_LOG(DEBUG, "UNDI previously loaded");
9301                                 prev_undi = TRUE;
9302                                 /* clear the UNDI indication */
9303                                 REG_WR(sc, DORQ_REG_NORM_CID_OFST, 0);
9304                                 /* clear possible idle check errors */
9305                                 REG_RD(sc, NIG_REG_NIG_INT_STS_CLR_0);
9306                         }
9307                 }
9308
9309                 /* wait until BRB is empty */
9310                 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9311                 while (timer_count) {
9312                         prev_brb = tmp_reg;
9313
9314                         tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9315                         if (!tmp_reg) {
9316                                 break;
9317                         }
9318
9319                         PMD_DRV_LOG(DEBUG, "BRB still has 0x%08x", tmp_reg);
9320
9321                         /* reset timer as long as BRB actually gets emptied */
9322                         if (prev_brb > tmp_reg) {
9323                                 timer_count = 1000;
9324                         } else {
9325                                 timer_count--;
9326                         }
9327
9328                         /* If UNDI resides in memory, manually increment it */
9329                         if (prev_undi) {
9330                                 bnx2x_prev_unload_undi_inc(sc, SC_PORT(sc), 1);
9331                         }
9332
9333                         DELAY(10);
9334                 }
9335
9336                 if (!timer_count) {
9337                         PMD_DRV_LOG(NOTICE, "Failed to empty BRB");
9338                 }
9339         }
9340
9341         /* No packets are in the pipeline, path is ready for reset */
9342         bnx2x_reset_common(sc);
9343
9344         if (mac_vals.xmac_addr) {
9345                 REG_WR(sc, mac_vals.xmac_addr, mac_vals.xmac_val);
9346         }
9347         if (mac_vals.umac_addr) {
9348                 REG_WR(sc, mac_vals.umac_addr, mac_vals.umac_val);
9349         }
9350         if (mac_vals.emac_addr) {
9351                 REG_WR(sc, mac_vals.emac_addr, mac_vals.emac_val);
9352         }
9353         if (mac_vals.bmac_addr) {
9354                 REG_WR(sc, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
9355                 REG_WR(sc, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
9356         }
9357
9358         rc = bnx2x_prev_mark_path(sc, prev_undi);
9359         if (rc) {
9360                 bnx2x_prev_mcp_done(sc);
9361                 return rc;
9362         }
9363
9364         return bnx2x_prev_mcp_done(sc);
9365 }
9366
9367 static int bnx2x_prev_unload_uncommon(struct bnx2x_softc *sc)
9368 {
9369         int rc;
9370
9371         /* Test if previous unload process was already finished for this path */
9372         if (bnx2x_prev_is_path_marked(sc)) {
9373                 return bnx2x_prev_mcp_done(sc);
9374         }
9375
9376         /*
9377          * If function has FLR capabilities, and existing FW version matches
9378          * the one required, then FLR will be sufficient to clean any residue
9379          * left by previous driver
9380          */
9381         rc = bnx2x_nic_load_analyze_req(sc, FW_MSG_CODE_DRV_LOAD_FUNCTION);
9382         if (!rc) {
9383                 /* fw version is good */
9384                 rc = bnx2x_do_flr(sc);
9385         }
9386
9387         if (!rc) {
9388                 /* FLR was performed */
9389                 return 0;
9390         }
9391
9392         PMD_DRV_LOG(INFO, "Could not FLR");
9393
9394         /* Close the MCP request, return failure */
9395         rc = bnx2x_prev_mcp_done(sc);
9396         if (!rc) {
9397                 rc = BNX2X_PREV_WAIT_NEEDED;
9398         }
9399
9400         return rc;
9401 }
9402
9403 static int bnx2x_prev_unload(struct bnx2x_softc *sc)
9404 {
9405         int time_counter = 10;
9406         uint32_t fw, hw_lock_reg, hw_lock_val;
9407         uint32_t rc = 0;
9408
9409         /*
9410          * Clear HW from errors which may have resulted from an interrupted
9411          * DMAE transaction.
9412          */
9413         bnx2x_prev_interrupted_dmae(sc);
9414
9415         /* Release previously held locks */
9416         if (SC_FUNC(sc) <= 5)
9417                 hw_lock_reg = (MISC_REG_DRIVER_CONTROL_1 + SC_FUNC(sc) * 8);
9418         else
9419                 hw_lock_reg =
9420                     (MISC_REG_DRIVER_CONTROL_7 + (SC_FUNC(sc) - 6) * 8);
9421
9422         hw_lock_val = (REG_RD(sc, hw_lock_reg));
9423         if (hw_lock_val) {
9424                 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
9425                         REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
9426                                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << SC_PORT(sc)));
9427                 }
9428                 REG_WR(sc, hw_lock_reg, 0xffffffff);
9429         }
9430
9431         if (MCPR_ACCESS_LOCK_LOCK & REG_RD(sc, MCP_REG_MCPR_ACCESS_LOCK)) {
9432                 REG_WR(sc, MCP_REG_MCPR_ACCESS_LOCK, 0);
9433         }
9434
9435         do {
9436                 /* Lock MCP using an unload request */
9437                 fw = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
9438                 if (!fw) {
9439                         PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
9440                         rc = -1;
9441                         break;
9442                 }
9443
9444                 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
9445                         rc = bnx2x_prev_unload_common(sc);
9446                         break;
9447                 }
9448
9449                 /* non-common reply from MCP might require looping */
9450                 rc = bnx2x_prev_unload_uncommon(sc);
9451                 if (rc != BNX2X_PREV_WAIT_NEEDED) {
9452                         break;
9453                 }
9454
9455                 DELAY(20000);
9456         } while (--time_counter);
9457
9458         if (!time_counter || rc) {
9459                 PMD_DRV_LOG(NOTICE, "Failed to unload previous driver!");
9460                 rc = -1;
9461         }
9462
9463         return rc;
9464 }
9465
9466 static void
9467 bnx2x_dcbx_set_state(struct bnx2x_softc *sc, uint8_t dcb_on, uint32_t dcbx_enabled)
9468 {
9469         if (!CHIP_IS_E1x(sc)) {
9470                 sc->dcb_state = dcb_on;
9471                 sc->dcbx_enabled = dcbx_enabled;
9472         } else {
9473                 sc->dcb_state = FALSE;
9474                 sc->dcbx_enabled = BNX2X_DCBX_ENABLED_INVALID;
9475         }
9476         PMD_DRV_LOG(DEBUG,
9477                     "DCB state [%s:%s]",
9478                     dcb_on ? "ON" : "OFF",
9479                     (dcbx_enabled == BNX2X_DCBX_ENABLED_OFF) ? "user-mode" :
9480                     (dcbx_enabled ==
9481                      BNX2X_DCBX_ENABLED_ON_NEG_OFF) ? "on-chip static"
9482                     : (dcbx_enabled ==
9483                        BNX2X_DCBX_ENABLED_ON_NEG_ON) ?
9484                     "on-chip with negotiation" : "invalid");
9485 }
9486
9487 static int bnx2x_set_qm_cid_count(struct bnx2x_softc *sc)
9488 {
9489         int cid_count = BNX2X_L2_MAX_CID(sc);
9490
9491         if (CNIC_SUPPORT(sc)) {
9492                 cid_count += CNIC_CID_MAX;
9493         }
9494
9495         return roundup(cid_count, QM_CID_ROUND);
9496 }
9497
9498 static void bnx2x_init_multi_cos(struct bnx2x_softc *sc)
9499 {
9500         int pri, cos;
9501
9502         uint32_t pri_map = 0;
9503
9504         for (pri = 0; pri < BNX2X_MAX_PRIORITY; pri++) {
9505                 cos = ((pri_map & (0xf << (pri * 4))) >> (pri * 4));
9506                 if (cos < sc->max_cos) {
9507                         sc->prio_to_cos[pri] = cos;
9508                 } else {
9509                         PMD_DRV_LOG(WARNING,
9510                                     "Invalid COS %d for priority %d "
9511                                     "(max COS is %d), setting to 0", cos, pri,
9512                                     (sc->max_cos - 1));
9513                         sc->prio_to_cos[pri] = 0;
9514                 }
9515         }
9516 }
9517
9518 static int bnx2x_pci_get_caps(struct bnx2x_softc *sc)
9519 {
9520         struct {
9521                 uint8_t id;
9522                 uint8_t next;
9523         } pci_cap;
9524         uint16_t status;
9525         struct bnx2x_pci_cap *cap;
9526
9527         cap = sc->pci_caps = rte_zmalloc("caps", sizeof(struct bnx2x_pci_cap),
9528                                          RTE_CACHE_LINE_SIZE);
9529         if (!cap) {
9530                 PMD_DRV_LOG(NOTICE, "Failed to allocate memory");
9531                 return -ENOMEM;
9532         }
9533
9534 #ifndef __FreeBSD__
9535         pci_read(sc, PCI_STATUS, &status, 2);
9536         if (!(status & PCI_STATUS_CAP_LIST)) {
9537 #else
9538         pci_read(sc, PCIR_STATUS, &status, 2);
9539         if (!(status & PCIM_STATUS_CAPPRESENT)) {
9540 #endif
9541                 PMD_DRV_LOG(NOTICE, "PCIe capability reading failed");
9542                 return -1;
9543         }
9544
9545 #ifndef __FreeBSD__
9546         pci_read(sc, PCI_CAPABILITY_LIST, &pci_cap.next, 1);
9547 #else
9548         pci_read(sc, PCIR_CAP_PTR, &pci_cap.next, 1);
9549 #endif
9550         while (pci_cap.next) {
9551                 cap->addr = pci_cap.next & ~3;
9552                 pci_read(sc, pci_cap.next & ~3, &pci_cap, 2);
9553                 if (pci_cap.id == 0xff)
9554                         break;
9555                 cap->id = pci_cap.id;
9556                 cap->type = BNX2X_PCI_CAP;
9557                 cap->next = rte_zmalloc("pci_cap",
9558                                         sizeof(struct bnx2x_pci_cap),
9559                                         RTE_CACHE_LINE_SIZE);
9560                 if (!cap->next) {
9561                         PMD_DRV_LOG(NOTICE, "Failed to allocate memory");
9562                         return -ENOMEM;
9563                 }
9564                 cap = cap->next;
9565         }
9566
9567         return 0;
9568 }
9569
9570 static void bnx2x_init_rte(struct bnx2x_softc *sc)
9571 {
9572         if (IS_VF(sc)) {
9573                 sc->max_tx_queues = BNX2X_VF_MAX_QUEUES_PER_VF;
9574                 sc->max_rx_queues = BNX2X_VF_MAX_QUEUES_PER_VF;
9575         } else {
9576                 sc->max_tx_queues = 128;
9577                 sc->max_rx_queues = 128;
9578         }
9579 }
9580
9581 #define FW_HEADER_LEN 104
9582 #define FW_NAME_57711 "/lib/firmware/bnx2x/bnx2x-e1h-7.2.51.0.fw"
9583 #define FW_NAME_57810 "/lib/firmware/bnx2x/bnx2x-e2-7.2.51.0.fw"
9584
9585 void bnx2x_load_firmware(struct bnx2x_softc *sc)
9586 {
9587         const char *fwname;
9588         int f;
9589         struct stat st;
9590
9591         fwname = sc->devinfo.device_id == BNX2X_DEV_ID_57711
9592                 ? FW_NAME_57711 : FW_NAME_57810;
9593         f = open(fwname, O_RDONLY);
9594         if (f < 0) {
9595                 PMD_DRV_LOG(NOTICE, "Can't open firmware file");
9596                 return;
9597         }
9598
9599         if (fstat(f, &st) < 0) {
9600                 PMD_DRV_LOG(NOTICE, "Can't stat firmware file");
9601                 close(f);
9602                 return;
9603         }
9604
9605         sc->firmware = rte_zmalloc("bnx2x_fw", st.st_size, RTE_CACHE_LINE_SIZE);
9606         if (!sc->firmware) {
9607                 PMD_DRV_LOG(NOTICE, "Can't allocate memory for firmware");
9608                 close(f);
9609                 return;
9610         }
9611
9612         if (read(f, sc->firmware, st.st_size) != st.st_size) {
9613                 PMD_DRV_LOG(NOTICE, "Can't read firmware data");
9614                 close(f);
9615                 return;
9616         }
9617         close(f);
9618
9619         sc->fw_len = st.st_size;
9620         if (sc->fw_len < FW_HEADER_LEN) {
9621                 PMD_DRV_LOG(NOTICE, "Invalid fw size: %" PRIu64, sc->fw_len);
9622                 return;
9623         }
9624         PMD_DRV_LOG(DEBUG, "fw_len = %" PRIu64, sc->fw_len);
9625 }
9626
9627 static void
9628 bnx2x_data_to_init_ops(uint8_t * data, struct raw_op *dst, uint32_t len)
9629 {
9630         uint32_t *src = (uint32_t *) data;
9631         uint32_t i, j, tmp;
9632
9633         for (i = 0, j = 0; i < len / 8; ++i, j += 2) {
9634                 tmp = rte_be_to_cpu_32(src[j]);
9635                 dst[i].op = (tmp >> 24) & 0xFF;
9636                 dst[i].offset = tmp & 0xFFFFFF;
9637                 dst[i].raw_data = rte_be_to_cpu_32(src[j + 1]);
9638         }
9639 }
9640
9641 static void
9642 bnx2x_data_to_init_offsets(uint8_t * data, uint16_t * dst, uint32_t len)
9643 {
9644         uint16_t *src = (uint16_t *) data;
9645         uint32_t i;
9646
9647         for (i = 0; i < len / 2; ++i)
9648                 dst[i] = rte_be_to_cpu_16(src[i]);
9649 }
9650
9651 static void bnx2x_data_to_init_data(uint8_t * data, uint32_t * dst, uint32_t len)
9652 {
9653         uint32_t *src = (uint32_t *) data;
9654         uint32_t i;
9655
9656         for (i = 0; i < len / 4; ++i)
9657                 dst[i] = rte_be_to_cpu_32(src[i]);
9658 }
9659
9660 static void bnx2x_data_to_iro_array(uint8_t * data, struct iro *dst, uint32_t len)
9661 {
9662         uint32_t *src = (uint32_t *) data;
9663         uint32_t i, j, tmp;
9664
9665         for (i = 0, j = 0; i < len / sizeof(struct iro); ++i, ++j) {
9666                 dst[i].base = rte_be_to_cpu_32(src[j++]);
9667                 tmp = rte_be_to_cpu_32(src[j]);
9668                 dst[i].m1 = (tmp >> 16) & 0xFFFF;
9669                 dst[i].m2 = tmp & 0xFFFF;
9670                 ++j;
9671                 tmp = rte_be_to_cpu_32(src[j]);
9672                 dst[i].m3 = (tmp >> 16) & 0xFFFF;
9673                 dst[i].size = tmp & 0xFFFF;
9674         }
9675 }
9676
9677 /*
9678 * Device attach function.
9679 *
9680 * Allocates device resources, performs secondary chip identification, and
9681 * initializes driver instance variables. This function is called from driver
9682 * load after a successful probe.
9683 *
9684 * Returns:
9685 *   0 = Success, >0 = Failure
9686 */
9687 int bnx2x_attach(struct bnx2x_softc *sc)
9688 {
9689         int rc;
9690
9691         PMD_DRV_LOG(DEBUG, "Starting attach...");
9692
9693         rc = bnx2x_pci_get_caps(sc);
9694         if (rc) {
9695                 PMD_DRV_LOG(NOTICE, "PCIe caps reading was failed");
9696                 return rc;
9697         }
9698
9699         sc->state = BNX2X_STATE_CLOSED;
9700
9701         /* Init RTE stuff */
9702         bnx2x_init_rte(sc);
9703
9704         pci_write_long(sc, PCICFG_GRC_ADDRESS, PCICFG_VENDOR_ID_OFFSET);
9705
9706         sc->igu_base_addr = IS_VF(sc) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
9707
9708         /* get PCI capabilites */
9709         bnx2x_probe_pci_caps(sc);
9710
9711         if (sc->devinfo.pcie_msix_cap_reg != 0) {
9712                 uint32_t val;
9713                 pci_read(sc,
9714                          (sc->devinfo.pcie_msix_cap_reg + PCIR_MSIX_CTRL), &val,
9715                          2);
9716                 sc->igu_sb_cnt = (val & PCIM_MSIXCTRL_TABLE_SIZE);
9717         } else {
9718                 sc->igu_sb_cnt = 1;
9719         }
9720
9721         if (IS_PF(sc)) {
9722 /* get device info and set params */
9723                 if (bnx2x_get_device_info(sc) != 0) {
9724                         PMD_DRV_LOG(NOTICE, "getting device info");
9725                         return -ENXIO;
9726                 }
9727
9728 /* get phy settings from shmem and 'and' against admin settings */
9729                 bnx2x_get_phy_info(sc);
9730         } else {
9731 /* Left mac of VF unfilled, PF should set it for VF */
9732                 memset(sc->link_params.mac_addr, 0, ETHER_ADDR_LEN);
9733         }
9734
9735         sc->wol = 0;
9736
9737         /* set the default MTU (changed via ifconfig) */
9738         sc->mtu = ETHER_MTU;
9739
9740         bnx2x_set_modes_bitmap(sc);
9741
9742         /* need to reset chip if UNDI was active */
9743         if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
9744 /* init fw_seq */
9745                 sc->fw_seq =
9746                     (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
9747                      DRV_MSG_SEQ_NUMBER_MASK);
9748                 bnx2x_prev_unload(sc);
9749         }
9750
9751         bnx2x_dcbx_set_state(sc, FALSE, BNX2X_DCBX_ENABLED_OFF);
9752
9753         /* calculate qm_cid_count */
9754         sc->qm_cid_count = bnx2x_set_qm_cid_count(sc);
9755
9756         sc->max_cos = 1;
9757         bnx2x_init_multi_cos(sc);
9758
9759         return 0;
9760 }
9761
9762 static void
9763 bnx2x_igu_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t segment,
9764                uint16_t index, uint8_t op, uint8_t update)
9765 {
9766         uint32_t igu_addr = sc->igu_base_addr;
9767         igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
9768         bnx2x_igu_ack_sb_gen(sc, segment, index, op, update, igu_addr);
9769 }
9770
9771 static void
9772 bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t storm,
9773            uint16_t index, uint8_t op, uint8_t update)
9774 {
9775         if (unlikely(sc->devinfo.int_block == INT_BLOCK_HC))
9776                 bnx2x_hc_ack_sb(sc, igu_sb_id, storm, index, op, update);
9777         else {
9778                 uint8_t segment;
9779                 if (CHIP_INT_MODE_IS_BC(sc)) {
9780                         segment = storm;
9781                 } else if (igu_sb_id != sc->igu_dsb_id) {
9782                         segment = IGU_SEG_ACCESS_DEF;
9783                 } else if (storm == ATTENTION_ID) {
9784                         segment = IGU_SEG_ACCESS_ATTN;
9785                 } else {
9786                         segment = IGU_SEG_ACCESS_DEF;
9787                 }
9788                 bnx2x_igu_ack_sb(sc, igu_sb_id, segment, index, op, update);
9789         }
9790 }
9791
9792 static void
9793 bnx2x_igu_clear_sb_gen(struct bnx2x_softc *sc, uint8_t func, uint8_t idu_sb_id,
9794                      uint8_t is_pf)
9795 {
9796         uint32_t data, ctl, cnt = 100;
9797         uint32_t igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
9798         uint32_t igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
9799         uint32_t igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP +
9800             (idu_sb_id / 32) * 4;
9801         uint32_t sb_bit = 1 << (idu_sb_id % 32);
9802         uint32_t func_encode = func |
9803             (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
9804         uint32_t addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
9805
9806         /* Not supported in BC mode */
9807         if (CHIP_INT_MODE_IS_BC(sc)) {
9808                 return;
9809         }
9810
9811         data = ((IGU_USE_REGISTER_cstorm_type_0_sb_cleanup <<
9812                  IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
9813                 IGU_REGULAR_CLEANUP_SET | IGU_REGULAR_BCLEANUP);
9814
9815         ctl = ((addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT) |
9816                (func_encode << IGU_CTRL_REG_FID_SHIFT) |
9817                (IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT));
9818
9819         REG_WR(sc, igu_addr_data, data);
9820
9821         mb();
9822
9823         PMD_DRV_LOG(DEBUG, "write 0x%08x to IGU(via GRC) addr 0x%x",
9824                     ctl, igu_addr_ctl);
9825         REG_WR(sc, igu_addr_ctl, ctl);
9826
9827         mb();
9828
9829         /* wait for clean up to finish */
9830         while (!(REG_RD(sc, igu_addr_ack) & sb_bit) && --cnt) {
9831                 DELAY(20000);
9832         }
9833
9834         if (!(REG_RD(sc, igu_addr_ack) & sb_bit)) {
9835                 PMD_DRV_LOG(DEBUG,
9836                             "Unable to finish IGU cleanup: "
9837                             "idu_sb_id %d offset %d bit %d (cnt %d)",
9838                             idu_sb_id, idu_sb_id / 32, idu_sb_id % 32, cnt);
9839         }
9840 }
9841
9842 static void bnx2x_igu_clear_sb(struct bnx2x_softc *sc, uint8_t idu_sb_id)
9843 {
9844         bnx2x_igu_clear_sb_gen(sc, SC_FUNC(sc), idu_sb_id, TRUE /*PF*/);
9845 }
9846
9847 /*******************/
9848 /* ECORE CALLBACKS */
9849 /*******************/
9850
9851 static void bnx2x_reset_common(struct bnx2x_softc *sc)
9852 {
9853         uint32_t val = 0x1400;
9854
9855         PMD_INIT_FUNC_TRACE();
9856
9857         /* reset_common */
9858         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR),
9859                0xd3ffff7f);
9860
9861         if (CHIP_IS_E3(sc)) {
9862                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
9863                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
9864         }
9865
9866         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR), val);
9867 }
9868
9869 static void bnx2x_common_init_phy(struct bnx2x_softc *sc)
9870 {
9871         uint32_t shmem_base[2];
9872         uint32_t shmem2_base[2];
9873
9874         /* Avoid common init in case MFW supports LFA */
9875         if (SHMEM2_RD(sc, size) >
9876             (uint32_t) offsetof(struct shmem2_region,
9877                                 lfa_host_addr[SC_PORT(sc)])) {
9878                 return;
9879         }
9880
9881         shmem_base[0] = sc->devinfo.shmem_base;
9882         shmem2_base[0] = sc->devinfo.shmem2_base;
9883
9884         if (!CHIP_IS_E1x(sc)) {
9885                 shmem_base[1] = SHMEM2_RD(sc, other_shmem_base_addr);
9886                 shmem2_base[1] = SHMEM2_RD(sc, other_shmem2_base_addr);
9887         }
9888
9889         elink_common_init_phy(sc, shmem_base, shmem2_base,
9890                               sc->devinfo.chip_id, 0);
9891 }
9892
9893 static void bnx2x_pf_disable(struct bnx2x_softc *sc)
9894 {
9895         uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
9896
9897         val &= ~IGU_PF_CONF_FUNC_EN;
9898
9899         REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
9900         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
9901         REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 0);
9902 }
9903
9904 static void bnx2x_init_pxp(struct bnx2x_softc *sc)
9905 {
9906         uint16_t devctl;
9907         int r_order, w_order;
9908
9909         devctl = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_CTL);
9910
9911         w_order = ((devctl & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5);
9912         r_order = ((devctl & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12);
9913
9914         ecore_init_pxp_arb(sc, r_order, w_order);
9915 }
9916
9917 static uint32_t bnx2x_get_pretend_reg(struct bnx2x_softc *sc)
9918 {
9919         uint32_t base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9920         uint32_t stride = (PXP2_REG_PGL_PRETEND_FUNC_F1 - base);
9921         return base + (SC_ABS_FUNC(sc)) * stride;
9922 }
9923
9924 /*
9925  * Called only on E1H or E2.
9926  * When pretending to be PF, the pretend value is the function number 0..7.
9927  * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
9928  * combination.
9929  */
9930 static int bnx2x_pretend_func(struct bnx2x_softc *sc, uint16_t pretend_func_val)
9931 {
9932         uint32_t pretend_reg;
9933
9934         if (CHIP_IS_E1H(sc) && (pretend_func_val > E1H_FUNC_MAX))
9935                 return -1;
9936
9937         /* get my own pretend register */
9938         pretend_reg = bnx2x_get_pretend_reg(sc);
9939         REG_WR(sc, pretend_reg, pretend_func_val);
9940         REG_RD(sc, pretend_reg);
9941         return 0;
9942 }
9943
9944 static void bnx2x_setup_fan_failure_detection(struct bnx2x_softc *sc)
9945 {
9946         int is_required;
9947         uint32_t val;
9948         int port;
9949
9950         is_required = 0;
9951         val = (SHMEM_RD(sc, dev_info.shared_hw_config.config2) &
9952                SHARED_HW_CFG_FAN_FAILURE_MASK);
9953
9954         if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) {
9955                 is_required = 1;
9956         }
9957         /*
9958          * The fan failure mechanism is usually related to the PHY type since
9959          * the power consumption of the board is affected by the PHY. Currently,
9960          * fan is required for most designs with SFX7101, BNX2X8727 and BNX2X8481.
9961          */
9962         else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) {
9963                 for (port = PORT_0; port < PORT_MAX; port++) {
9964                         is_required |= elink_fan_failure_det_req(sc,
9965                                                                  sc->
9966                                                                  devinfo.shmem_base,
9967                                                                  sc->
9968                                                                  devinfo.shmem2_base,
9969                                                                  port);
9970                 }
9971         }
9972
9973         if (is_required == 0) {
9974                 return;
9975         }
9976
9977         /* Fan failure is indicated by SPIO 5 */
9978         bnx2x_set_spio(sc, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
9979
9980         /* set to active low mode */
9981         val = REG_RD(sc, MISC_REG_SPIO_INT);
9982         val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
9983         REG_WR(sc, MISC_REG_SPIO_INT, val);
9984
9985         /* enable interrupt to signal the IGU */
9986         val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
9987         val |= MISC_SPIO_SPIO5;
9988         REG_WR(sc, MISC_REG_SPIO_EVENT_EN, val);
9989 }
9990
9991 static void bnx2x_enable_blocks_attention(struct bnx2x_softc *sc)
9992 {
9993         uint32_t val;
9994
9995         REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0);
9996         if (!CHIP_IS_E1x(sc)) {
9997                 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0x40);
9998         } else {
9999                 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0);
10000         }
10001         REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
10002         REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
10003         /*
10004          * mask read length error interrupts in brb for parser
10005          * (parsing unit and 'checksum and crc' unit)
10006          * these errors are legal (PU reads fixed length and CAC can cause
10007          * read length error on truncated packets)
10008          */
10009         REG_WR(sc, BRB1_REG_BRB1_INT_MASK, 0xFC00);
10010         REG_WR(sc, QM_REG_QM_INT_MASK, 0);
10011         REG_WR(sc, TM_REG_TM_INT_MASK, 0);
10012         REG_WR(sc, XSDM_REG_XSDM_INT_MASK_0, 0);
10013         REG_WR(sc, XSDM_REG_XSDM_INT_MASK_1, 0);
10014         REG_WR(sc, XCM_REG_XCM_INT_MASK, 0);
10015         /*      REG_WR(sc, XSEM_REG_XSEM_INT_MASK_0, 0); */
10016         /*      REG_WR(sc, XSEM_REG_XSEM_INT_MASK_1, 0); */
10017         REG_WR(sc, USDM_REG_USDM_INT_MASK_0, 0);
10018         REG_WR(sc, USDM_REG_USDM_INT_MASK_1, 0);
10019         REG_WR(sc, UCM_REG_UCM_INT_MASK, 0);
10020         /*      REG_WR(sc, USEM_REG_USEM_INT_MASK_0, 0); */
10021         /*      REG_WR(sc, USEM_REG_USEM_INT_MASK_1, 0); */
10022         REG_WR(sc, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
10023         REG_WR(sc, CSDM_REG_CSDM_INT_MASK_0, 0);
10024         REG_WR(sc, CSDM_REG_CSDM_INT_MASK_1, 0);
10025         REG_WR(sc, CCM_REG_CCM_INT_MASK, 0);
10026         /*      REG_WR(sc, CSEM_REG_CSEM_INT_MASK_0, 0); */
10027         /*      REG_WR(sc, CSEM_REG_CSEM_INT_MASK_1, 0); */
10028
10029         val = (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
10030                PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
10031                PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN);
10032         if (!CHIP_IS_E1x(sc)) {
10033                 val |= (PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
10034                         PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED);
10035         }
10036         REG_WR(sc, PXP2_REG_PXP2_INT_MASK_0, val);
10037
10038         REG_WR(sc, TSDM_REG_TSDM_INT_MASK_0, 0);
10039         REG_WR(sc, TSDM_REG_TSDM_INT_MASK_1, 0);
10040         REG_WR(sc, TCM_REG_TCM_INT_MASK, 0);
10041         /*      REG_WR(sc, TSEM_REG_TSEM_INT_MASK_0, 0); */
10042
10043         if (!CHIP_IS_E1x(sc)) {
10044 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
10045                 REG_WR(sc, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
10046         }
10047
10048         REG_WR(sc, CDU_REG_CDU_INT_MASK, 0);
10049         REG_WR(sc, DMAE_REG_DMAE_INT_MASK, 0);
10050         /*      REG_WR(sc, MISC_REG_MISC_INT_MASK, 0); */
10051         REG_WR(sc, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
10052 }
10053
10054 /**
10055  * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
10056  *
10057  * @sc:     driver handle
10058  */
10059 static int bnx2x_init_hw_common(struct bnx2x_softc *sc)
10060 {
10061         uint8_t abs_func_id;
10062         uint32_t val;
10063
10064         PMD_DRV_LOG(DEBUG, "starting common init for func %d", SC_ABS_FUNC(sc));
10065
10066         /*
10067          * take the RESET lock to protect undi_unload flow from accessing
10068          * registers while we are resetting the chip
10069          */
10070         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10071
10072         bnx2x_reset_common(sc);
10073
10074         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET), 0xffffffff);
10075
10076         val = 0xfffc;
10077         if (CHIP_IS_E3(sc)) {
10078                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
10079                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
10080         }
10081
10082         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET), val);
10083
10084         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10085
10086         ecore_init_block(sc, BLOCK_MISC, PHASE_COMMON);
10087
10088         if (!CHIP_IS_E1x(sc)) {
10089 /*
10090  * 4-port mode or 2-port mode we need to turn off master-enable for
10091  * everyone. After that we turn it back on for self. So, we disregard
10092  * multi-function, and always disable all functions on the given path,
10093  * this means 0,2,4,6 for path 0 and 1,3,5,7 for path 1
10094  */
10095                 for (abs_func_id = SC_PATH(sc);
10096                      abs_func_id < (E2_FUNC_MAX * 2); abs_func_id += 2) {
10097                         if (abs_func_id == SC_ABS_FUNC(sc)) {
10098                                 REG_WR(sc,
10099                                        PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
10100                                        1);
10101                                 continue;
10102                         }
10103
10104                         bnx2x_pretend_func(sc, abs_func_id);
10105
10106                         /* clear pf enable */
10107                         bnx2x_pf_disable(sc);
10108
10109                         bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10110                 }
10111         }
10112
10113         ecore_init_block(sc, BLOCK_PXP, PHASE_COMMON);
10114
10115         ecore_init_block(sc, BLOCK_PXP2, PHASE_COMMON);
10116         bnx2x_init_pxp(sc);
10117
10118 #ifdef __BIG_ENDIAN
10119         REG_WR(sc, PXP2_REG_RQ_QM_ENDIAN_M, 1);
10120         REG_WR(sc, PXP2_REG_RQ_TM_ENDIAN_M, 1);
10121         REG_WR(sc, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
10122         REG_WR(sc, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
10123         REG_WR(sc, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
10124         /* make sure this value is 0 */
10125         REG_WR(sc, PXP2_REG_RQ_HC_ENDIAN_M, 0);
10126
10127         //REG_WR(sc, PXP2_REG_RD_PBF_SWAP_MODE, 1);
10128         REG_WR(sc, PXP2_REG_RD_QM_SWAP_MODE, 1);
10129         REG_WR(sc, PXP2_REG_RD_TM_SWAP_MODE, 1);
10130         REG_WR(sc, PXP2_REG_RD_SRC_SWAP_MODE, 1);
10131         REG_WR(sc, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
10132 #endif
10133
10134         ecore_ilt_init_page_size(sc, INITOP_SET);
10135
10136         if (CHIP_REV_IS_FPGA(sc) && CHIP_IS_E1H(sc)) {
10137                 REG_WR(sc, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
10138         }
10139
10140         /* let the HW do it's magic... */
10141         DELAY(100000);
10142
10143         /* finish PXP init */
10144
10145         val = REG_RD(sc, PXP2_REG_RQ_CFG_DONE);
10146         if (val != 1) {
10147                 PMD_DRV_LOG(NOTICE, "PXP2 CFG failed");
10148                 return -1;
10149         }
10150         val = REG_RD(sc, PXP2_REG_RD_INIT_DONE);
10151         if (val != 1) {
10152                 PMD_DRV_LOG(NOTICE, "PXP2 RD_INIT failed");
10153                 return -1;
10154         }
10155
10156         /*
10157          * Timer bug workaround for E2 only. We need to set the entire ILT to have
10158          * entries with value "0" and valid bit on. This needs to be done by the
10159          * first PF that is loaded in a path (i.e. common phase)
10160          */
10161         if (!CHIP_IS_E1x(sc)) {
10162 /*
10163  * In E2 there is a bug in the timers block that can cause function 6 / 7
10164  * (i.e. vnic3) to start even if it is marked as "scan-off".
10165  * This occurs when a different function (func2,3) is being marked
10166  * as "scan-off". Real-life scenario for example: if a driver is being
10167  * load-unloaded while func6,7 are down. This will cause the timer to access
10168  * the ilt, translate to a logical address and send a request to read/write.
10169  * Since the ilt for the function that is down is not valid, this will cause
10170  * a translation error which is unrecoverable.
10171  * The Workaround is intended to make sure that when this happens nothing
10172  * fatal will occur. The workaround:
10173  *  1.  First PF driver which loads on a path will:
10174  *      a.  After taking the chip out of reset, by using pretend,
10175  *          it will write "0" to the following registers of
10176  *          the other vnics.
10177  *          REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10178  *          REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
10179  *          REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
10180  *          And for itself it will write '1' to
10181  *          PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
10182  *          dmae-operations (writing to pram for example.)
10183  *          note: can be done for only function 6,7 but cleaner this
10184  *            way.
10185  *      b.  Write zero+valid to the entire ILT.
10186  *      c.  Init the first_timers_ilt_entry, last_timers_ilt_entry of
10187  *          VNIC3 (of that port). The range allocated will be the
10188  *          entire ILT. This is needed to prevent  ILT range error.
10189  *  2.  Any PF driver load flow:
10190  *      a.  ILT update with the physical addresses of the allocated
10191  *          logical pages.
10192  *      b.  Wait 20msec. - note that this timeout is needed to make
10193  *          sure there are no requests in one of the PXP internal
10194  *          queues with "old" ILT addresses.
10195  *      c.  PF enable in the PGLC.
10196  *      d.  Clear the was_error of the PF in the PGLC. (could have
10197  *          occurred while driver was down)
10198  *      e.  PF enable in the CFC (WEAK + STRONG)
10199  *      f.  Timers scan enable
10200  *  3.  PF driver unload flow:
10201  *      a.  Clear the Timers scan_en.
10202  *      b.  Polling for scan_on=0 for that PF.
10203  *      c.  Clear the PF enable bit in the PXP.
10204  *      d.  Clear the PF enable in the CFC (WEAK + STRONG)
10205  *      e.  Write zero+valid to all ILT entries (The valid bit must
10206  *          stay set)
10207  *      f.  If this is VNIC 3 of a port then also init
10208  *          first_timers_ilt_entry to zero and last_timers_ilt_entry
10209  *          to the last enrty in the ILT.
10210  *
10211  *      Notes:
10212  *      Currently the PF error in the PGLC is non recoverable.
10213  *      In the future the there will be a recovery routine for this error.
10214  *      Currently attention is masked.
10215  *      Having an MCP lock on the load/unload process does not guarantee that
10216  *      there is no Timer disable during Func6/7 enable. This is because the
10217  *      Timers scan is currently being cleared by the MCP on FLR.
10218  *      Step 2.d can be done only for PF6/7 and the driver can also check if
10219  *      there is error before clearing it. But the flow above is simpler and
10220  *      more general.
10221  *      All ILT entries are written by zero+valid and not just PF6/7
10222  *      ILT entries since in the future the ILT entries allocation for
10223  *      PF-s might be dynamic.
10224  */
10225                 struct ilt_client_info ilt_cli;
10226                 struct ecore_ilt ilt;
10227
10228                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
10229                 memset(&ilt, 0, sizeof(struct ecore_ilt));
10230
10231 /* initialize dummy TM client */
10232                 ilt_cli.start = 0;
10233                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
10234                 ilt_cli.client_num = ILT_CLIENT_TM;
10235
10236 /*
10237  * Step 1: set zeroes to all ilt page entries with valid bit on
10238  * Step 2: set the timers first/last ilt entry to point
10239  * to the entire range to prevent ILT range error for 3rd/4th
10240  * vnic (this code assumes existence of the vnic)
10241  *
10242  * both steps performed by call to ecore_ilt_client_init_op()
10243  * with dummy TM client
10244  *
10245  * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
10246  * and his brother are split registers
10247  */
10248
10249                 bnx2x_pretend_func(sc, (SC_PATH(sc) + 6));
10250                 ecore_ilt_client_init_op_ilt(sc, &ilt, &ilt_cli, INITOP_CLEAR);
10251                 bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10252
10253                 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
10254                 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
10255                 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
10256         }
10257
10258         REG_WR(sc, PXP2_REG_RQ_DISABLE_INPUTS, 0);
10259         REG_WR(sc, PXP2_REG_RD_DISABLE_INPUTS, 0);
10260
10261         if (!CHIP_IS_E1x(sc)) {
10262                 int factor = 0;
10263
10264                 ecore_init_block(sc, BLOCK_PGLUE_B, PHASE_COMMON);
10265                 ecore_init_block(sc, BLOCK_ATC, PHASE_COMMON);
10266
10267 /* let the HW do it's magic... */
10268                 do {
10269                         DELAY(200000);
10270                         val = REG_RD(sc, ATC_REG_ATC_INIT_DONE);
10271                 } while (factor-- && (val != 1));
10272
10273                 if (val != 1) {
10274                         PMD_DRV_LOG(NOTICE, "ATC_INIT failed");
10275                         return -1;
10276                 }
10277         }
10278
10279         ecore_init_block(sc, BLOCK_DMAE, PHASE_COMMON);
10280
10281         /* clean the DMAE memory */
10282         sc->dmae_ready = 1;
10283         ecore_init_fill(sc, TSEM_REG_PRAM, 0, 8);
10284
10285         ecore_init_block(sc, BLOCK_TCM, PHASE_COMMON);
10286
10287         ecore_init_block(sc, BLOCK_UCM, PHASE_COMMON);
10288
10289         ecore_init_block(sc, BLOCK_CCM, PHASE_COMMON);
10290
10291         ecore_init_block(sc, BLOCK_XCM, PHASE_COMMON);
10292
10293         bnx2x_read_dmae(sc, XSEM_REG_PASSIVE_BUFFER, 3);
10294         bnx2x_read_dmae(sc, CSEM_REG_PASSIVE_BUFFER, 3);
10295         bnx2x_read_dmae(sc, TSEM_REG_PASSIVE_BUFFER, 3);
10296         bnx2x_read_dmae(sc, USEM_REG_PASSIVE_BUFFER, 3);
10297
10298         ecore_init_block(sc, BLOCK_QM, PHASE_COMMON);
10299
10300         /* QM queues pointers table */
10301         ecore_qm_init_ptr_table(sc, sc->qm_cid_count, INITOP_SET);
10302
10303         /* soft reset pulse */
10304         REG_WR(sc, QM_REG_SOFT_RESET, 1);
10305         REG_WR(sc, QM_REG_SOFT_RESET, 0);
10306
10307         if (CNIC_SUPPORT(sc))
10308                 ecore_init_block(sc, BLOCK_TM, PHASE_COMMON);
10309
10310         ecore_init_block(sc, BLOCK_DORQ, PHASE_COMMON);
10311         REG_WR(sc, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
10312
10313         if (!CHIP_REV_IS_SLOW(sc)) {
10314 /* enable hw interrupt from doorbell Q */
10315                 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
10316         }
10317
10318         ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON);
10319
10320         ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON);
10321         REG_WR(sc, PRS_REG_A_PRSU_20, 0xf);
10322         REG_WR(sc, PRS_REG_E1HOV_MODE, sc->devinfo.mf_info.path_has_ovlan);
10323
10324         if (!CHIP_IS_E1x(sc) && !CHIP_IS_E3B0(sc)) {
10325                 if (IS_MF_AFEX(sc)) {
10326                         /*
10327                          * configure that AFEX and VLAN headers must be
10328                          * received in AFEX mode
10329                          */
10330                         REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC, 0xE);
10331                         REG_WR(sc, PRS_REG_MUST_HAVE_HDRS, 0xA);
10332                         REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
10333                         REG_WR(sc, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
10334                         REG_WR(sc, PRS_REG_TAG_LEN_0, 0x4);
10335                 } else {
10336                         /*
10337                          * Bit-map indicating which L2 hdrs may appear
10338                          * after the basic Ethernet header
10339                          */
10340                         REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC,
10341                                sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10342                 }
10343         }
10344
10345         ecore_init_block(sc, BLOCK_TSDM, PHASE_COMMON);
10346         ecore_init_block(sc, BLOCK_CSDM, PHASE_COMMON);
10347         ecore_init_block(sc, BLOCK_USDM, PHASE_COMMON);
10348         ecore_init_block(sc, BLOCK_XSDM, PHASE_COMMON);
10349
10350         if (!CHIP_IS_E1x(sc)) {
10351 /* reset VFC memories */
10352                 REG_WR(sc, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10353                        VFC_MEMORIES_RST_REG_CAM_RST |
10354                        VFC_MEMORIES_RST_REG_RAM_RST);
10355                 REG_WR(sc, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10356                        VFC_MEMORIES_RST_REG_CAM_RST |
10357                        VFC_MEMORIES_RST_REG_RAM_RST);
10358
10359                 DELAY(20000);
10360         }
10361
10362         ecore_init_block(sc, BLOCK_TSEM, PHASE_COMMON);
10363         ecore_init_block(sc, BLOCK_USEM, PHASE_COMMON);
10364         ecore_init_block(sc, BLOCK_CSEM, PHASE_COMMON);
10365         ecore_init_block(sc, BLOCK_XSEM, PHASE_COMMON);
10366
10367         /* sync semi rtc */
10368         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x80000000);
10369         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x80000000);
10370
10371         ecore_init_block(sc, BLOCK_UPB, PHASE_COMMON);
10372         ecore_init_block(sc, BLOCK_XPB, PHASE_COMMON);
10373         ecore_init_block(sc, BLOCK_PBF, PHASE_COMMON);
10374
10375         if (!CHIP_IS_E1x(sc)) {
10376                 if (IS_MF_AFEX(sc)) {
10377                         /*
10378                          * configure that AFEX and VLAN headers must be
10379                          * sent in AFEX mode
10380                          */
10381                         REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC, 0xE);
10382                         REG_WR(sc, PBF_REG_MUST_HAVE_HDRS, 0xA);
10383                         REG_WR(sc, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
10384                         REG_WR(sc, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
10385                         REG_WR(sc, PBF_REG_TAG_LEN_0, 0x4);
10386                 } else {
10387                         REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC,
10388                                sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10389                 }
10390         }
10391
10392         REG_WR(sc, SRC_REG_SOFT_RST, 1);
10393
10394         ecore_init_block(sc, BLOCK_SRC, PHASE_COMMON);
10395
10396         if (CNIC_SUPPORT(sc)) {
10397                 REG_WR(sc, SRC_REG_KEYSEARCH_0, 0x63285672);
10398                 REG_WR(sc, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
10399                 REG_WR(sc, SRC_REG_KEYSEARCH_2, 0x223aef9b);
10400                 REG_WR(sc, SRC_REG_KEYSEARCH_3, 0x26001e3a);
10401                 REG_WR(sc, SRC_REG_KEYSEARCH_4, 0x7ae91116);
10402                 REG_WR(sc, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
10403                 REG_WR(sc, SRC_REG_KEYSEARCH_6, 0x298d8adf);
10404                 REG_WR(sc, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
10405                 REG_WR(sc, SRC_REG_KEYSEARCH_8, 0x1830f82f);
10406                 REG_WR(sc, SRC_REG_KEYSEARCH_9, 0x01e46be7);
10407         }
10408         REG_WR(sc, SRC_REG_SOFT_RST, 0);
10409
10410         if (sizeof(union cdu_context) != 1024) {
10411 /* we currently assume that a context is 1024 bytes */
10412                 PMD_DRV_LOG(NOTICE,
10413                             "please adjust the size of cdu_context(%ld)",
10414                             (long)sizeof(union cdu_context));
10415         }
10416
10417         ecore_init_block(sc, BLOCK_CDU, PHASE_COMMON);
10418         val = (4 << 24) + (0 << 12) + 1024;
10419         REG_WR(sc, CDU_REG_CDU_GLOBAL_PARAMS, val);
10420
10421         ecore_init_block(sc, BLOCK_CFC, PHASE_COMMON);
10422
10423         REG_WR(sc, CFC_REG_INIT_REG, 0x7FF);
10424         /* enable context validation interrupt from CFC */
10425         REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
10426
10427         /* set the thresholds to prevent CFC/CDU race */
10428         REG_WR(sc, CFC_REG_DEBUG0, 0x20020000);
10429         ecore_init_block(sc, BLOCK_HC, PHASE_COMMON);
10430
10431         if (!CHIP_IS_E1x(sc) && BNX2X_NOMCP(sc)) {
10432                 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x36);
10433         }
10434
10435         ecore_init_block(sc, BLOCK_IGU, PHASE_COMMON);
10436         ecore_init_block(sc, BLOCK_MISC_AEU, PHASE_COMMON);
10437
10438         /* Reset PCIE errors for debug */
10439         REG_WR(sc, 0x2814, 0xffffffff);
10440         REG_WR(sc, 0x3820, 0xffffffff);
10441
10442         if (!CHIP_IS_E1x(sc)) {
10443                 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
10444                        (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
10445                         PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
10446                 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
10447                        (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
10448                         PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
10449                         PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
10450                 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
10451                        (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
10452                         PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
10453                         PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
10454         }
10455
10456         ecore_init_block(sc, BLOCK_NIG, PHASE_COMMON);
10457
10458         /* in E3 this done in per-port section */
10459         if (!CHIP_IS_E3(sc))
10460                 REG_WR(sc, NIG_REG_LLH_MF_MODE, IS_MF(sc));
10461
10462         if (CHIP_IS_E1H(sc)) {
10463 /* not applicable for E2 (and above ...) */
10464                 REG_WR(sc, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(sc));
10465         }
10466
10467         if (CHIP_REV_IS_SLOW(sc)) {
10468                 DELAY(200000);
10469         }
10470
10471         /* finish CFC init */
10472         val = reg_poll(sc, CFC_REG_LL_INIT_DONE, 1, 100, 10);
10473         if (val != 1) {
10474                 PMD_DRV_LOG(NOTICE, "CFC LL_INIT failed");
10475                 return -1;
10476         }
10477         val = reg_poll(sc, CFC_REG_AC_INIT_DONE, 1, 100, 10);
10478         if (val != 1) {
10479                 PMD_DRV_LOG(NOTICE, "CFC AC_INIT failed");
10480                 return -1;
10481         }
10482         val = reg_poll(sc, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
10483         if (val != 1) {
10484                 PMD_DRV_LOG(NOTICE, "CFC CAM_INIT failed");
10485                 return -1;
10486         }
10487         REG_WR(sc, CFC_REG_DEBUG0, 0);
10488
10489         bnx2x_setup_fan_failure_detection(sc);
10490
10491         /* clear PXP2 attentions */
10492         REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
10493
10494         bnx2x_enable_blocks_attention(sc);
10495
10496         if (!CHIP_REV_IS_SLOW(sc)) {
10497                 ecore_enable_blocks_parity(sc);
10498         }
10499
10500         if (!BNX2X_NOMCP(sc)) {
10501                 if (CHIP_IS_E1x(sc)) {
10502                         bnx2x_common_init_phy(sc);
10503                 }
10504         }
10505
10506         return 0;
10507 }
10508
10509 /**
10510  * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
10511  *
10512  * @sc:     driver handle
10513  */
10514 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc)
10515 {
10516         int rc = bnx2x_init_hw_common(sc);
10517
10518         if (rc) {
10519                 return rc;
10520         }
10521
10522         /* In E2 2-PORT mode, same ext phy is used for the two paths */
10523         if (!BNX2X_NOMCP(sc)) {
10524                 bnx2x_common_init_phy(sc);
10525         }
10526
10527         return 0;
10528 }
10529
10530 static int bnx2x_init_hw_port(struct bnx2x_softc *sc)
10531 {
10532         int port = SC_PORT(sc);
10533         int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
10534         uint32_t low, high;
10535         uint32_t val;
10536
10537         PMD_DRV_LOG(DEBUG, "starting port init for port %d", port);
10538
10539         REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
10540
10541         ecore_init_block(sc, BLOCK_MISC, init_phase);
10542         ecore_init_block(sc, BLOCK_PXP, init_phase);
10543         ecore_init_block(sc, BLOCK_PXP2, init_phase);
10544
10545         /*
10546          * Timers bug workaround: disables the pf_master bit in pglue at
10547          * common phase, we need to enable it here before any dmae access are
10548          * attempted. Therefore we manually added the enable-master to the
10549          * port phase (it also happens in the function phase)
10550          */
10551         if (!CHIP_IS_E1x(sc)) {
10552                 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
10553         }
10554
10555         ecore_init_block(sc, BLOCK_ATC, init_phase);
10556         ecore_init_block(sc, BLOCK_DMAE, init_phase);
10557         ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
10558         ecore_init_block(sc, BLOCK_QM, init_phase);
10559
10560         ecore_init_block(sc, BLOCK_TCM, init_phase);
10561         ecore_init_block(sc, BLOCK_UCM, init_phase);
10562         ecore_init_block(sc, BLOCK_CCM, init_phase);
10563         ecore_init_block(sc, BLOCK_XCM, init_phase);
10564
10565         /* QM cid (connection) count */
10566         ecore_qm_init_cid_count(sc, sc->qm_cid_count, INITOP_SET);
10567
10568         if (CNIC_SUPPORT(sc)) {
10569                 ecore_init_block(sc, BLOCK_TM, init_phase);
10570                 REG_WR(sc, TM_REG_LIN0_SCAN_TIME + port * 4, 20);
10571                 REG_WR(sc, TM_REG_LIN0_MAX_ACTIVE_CID + port * 4, 31);
10572         }
10573
10574         ecore_init_block(sc, BLOCK_DORQ, init_phase);
10575
10576         ecore_init_block(sc, BLOCK_BRB1, init_phase);
10577
10578         if (CHIP_IS_E1H(sc)) {
10579                 if (IS_MF(sc)) {
10580                         low = (BNX2X_ONE_PORT(sc) ? 160 : 246);
10581                 } else if (sc->mtu > 4096) {
10582                         if (BNX2X_ONE_PORT(sc)) {
10583                                 low = 160;
10584                         } else {
10585                                 val = sc->mtu;
10586                                 /* (24*1024 + val*4)/256 */
10587                                 low = (96 + (val / 64) + ((val % 64) ? 1 : 0));
10588                         }
10589                 } else {
10590                         low = (BNX2X_ONE_PORT(sc) ? 80 : 160);
10591                 }
10592                 high = (low + 56);      /* 14*1024/256 */
10593                 REG_WR(sc, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port * 4, low);
10594                 REG_WR(sc, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port * 4, high);
10595         }
10596
10597         if (CHIP_IS_MODE_4_PORT(sc)) {
10598                 REG_WR(sc, SC_PORT(sc) ?
10599                        BRB1_REG_MAC_GUARANTIED_1 :
10600                        BRB1_REG_MAC_GUARANTIED_0, 40);
10601         }
10602
10603         ecore_init_block(sc, BLOCK_PRS, init_phase);
10604         if (CHIP_IS_E3B0(sc)) {
10605                 if (IS_MF_AFEX(sc)) {
10606                         /* configure headers for AFEX mode */
10607                         if (SC_PORT(sc)) {
10608                                 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_1,
10609                                        0xE);
10610                                 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_1,
10611                                        0x6);
10612                                 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_1, 0xA);
10613                         } else {
10614                                 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10615                                        0xE);
10616                                 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_0,
10617                                        0x6);
10618                                 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
10619                         }
10620                 } else {
10621                         /* Ovlan exists only if we are in multi-function +
10622                          * switch-dependent mode, in switch-independent there
10623                          * is no ovlan headers
10624                          */
10625                         REG_WR(sc, SC_PORT(sc) ?
10626                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
10627                                PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10628                                (sc->devinfo.mf_info.path_has_ovlan ? 7 : 6));
10629                 }
10630         }
10631
10632         ecore_init_block(sc, BLOCK_TSDM, init_phase);
10633         ecore_init_block(sc, BLOCK_CSDM, init_phase);
10634         ecore_init_block(sc, BLOCK_USDM, init_phase);
10635         ecore_init_block(sc, BLOCK_XSDM, init_phase);
10636
10637         ecore_init_block(sc, BLOCK_TSEM, init_phase);
10638         ecore_init_block(sc, BLOCK_USEM, init_phase);
10639         ecore_init_block(sc, BLOCK_CSEM, init_phase);
10640         ecore_init_block(sc, BLOCK_XSEM, init_phase);
10641
10642         ecore_init_block(sc, BLOCK_UPB, init_phase);
10643         ecore_init_block(sc, BLOCK_XPB, init_phase);
10644
10645         ecore_init_block(sc, BLOCK_PBF, init_phase);
10646
10647         if (CHIP_IS_E1x(sc)) {
10648 /* configure PBF to work without PAUSE mtu 9000 */
10649                 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 0);
10650
10651 /* update threshold */
10652                 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, (9040 / 16));
10653 /* update init credit */
10654                 REG_WR(sc, PBF_REG_P0_INIT_CRD + port * 4,
10655                        (9040 / 16) + 553 - 22);
10656
10657 /* probe changes */
10658                 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 1);
10659                 DELAY(50);
10660                 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0);
10661         }
10662
10663         if (CNIC_SUPPORT(sc)) {
10664                 ecore_init_block(sc, BLOCK_SRC, init_phase);
10665         }
10666
10667         ecore_init_block(sc, BLOCK_CDU, init_phase);
10668         ecore_init_block(sc, BLOCK_CFC, init_phase);
10669         ecore_init_block(sc, BLOCK_HC, init_phase);
10670         ecore_init_block(sc, BLOCK_IGU, init_phase);
10671         ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
10672         /* init aeu_mask_attn_func_0/1:
10673          *  - SF mode: bits 3-7 are masked. only bits 0-2 are in use
10674          *  - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
10675          *             bits 4-7 are used for "per vn group attention" */
10676         val = IS_MF(sc) ? 0xF7 : 0x7;
10677         val |= 0x10;
10678         REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, val);
10679
10680         ecore_init_block(sc, BLOCK_NIG, init_phase);
10681
10682         if (!CHIP_IS_E1x(sc)) {
10683 /* Bit-map indicating which L2 hdrs may appear after the
10684  * basic Ethernet header
10685  */
10686                 if (IS_MF_AFEX(sc)) {
10687                         REG_WR(sc, SC_PORT(sc) ?
10688                                NIG_REG_P1_HDRS_AFTER_BASIC :
10689                                NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
10690                 } else {
10691                         REG_WR(sc, SC_PORT(sc) ?
10692                                NIG_REG_P1_HDRS_AFTER_BASIC :
10693                                NIG_REG_P0_HDRS_AFTER_BASIC,
10694                                IS_MF_SD(sc) ? 7 : 6);
10695                 }
10696
10697                 if (CHIP_IS_E3(sc)) {
10698                         REG_WR(sc, SC_PORT(sc) ?
10699                                NIG_REG_LLH1_MF_MODE :
10700                                NIG_REG_LLH_MF_MODE, IS_MF(sc));
10701                 }
10702         }
10703         if (!CHIP_IS_E3(sc)) {
10704                 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1);
10705         }
10706
10707         /* 0x2 disable mf_ov, 0x1 enable */
10708         REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port * 4,
10709                (IS_MF_SD(sc) ? 0x1 : 0x2));
10710
10711         if (!CHIP_IS_E1x(sc)) {
10712                 val = 0;
10713                 switch (sc->devinfo.mf_info.mf_mode) {
10714                 case MULTI_FUNCTION_SD:
10715                         val = 1;
10716                         break;
10717                 case MULTI_FUNCTION_SI:
10718                 case MULTI_FUNCTION_AFEX:
10719                         val = 2;
10720                         break;
10721                 }
10722
10723                 REG_WR(sc, (SC_PORT(sc) ? NIG_REG_LLH1_CLS_TYPE :
10724                             NIG_REG_LLH0_CLS_TYPE), val);
10725         }
10726         REG_WR(sc, NIG_REG_LLFC_ENABLE_0 + port * 4, 0);
10727         REG_WR(sc, NIG_REG_LLFC_OUT_EN_0 + port * 4, 0);
10728         REG_WR(sc, NIG_REG_PAUSE_ENABLE_0 + port * 4, 1);
10729
10730         /* If SPIO5 is set to generate interrupts, enable it for this port */
10731         val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
10732         if (val & MISC_SPIO_SPIO5) {
10733                 uint32_t reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
10734                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
10735                 val = REG_RD(sc, reg_addr);
10736                 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
10737                 REG_WR(sc, reg_addr, val);
10738         }
10739
10740         return 0;
10741 }
10742
10743 static uint32_t
10744 bnx2x_flr_clnup_reg_poll(struct bnx2x_softc *sc, uint32_t reg,
10745                        uint32_t expected, uint32_t poll_count)
10746 {
10747         uint32_t cur_cnt = poll_count;
10748         uint32_t val;
10749
10750         while ((val = REG_RD(sc, reg)) != expected && cur_cnt--) {
10751                 DELAY(FLR_WAIT_INTERVAL);
10752         }
10753
10754         return val;
10755 }
10756
10757 static int
10758 bnx2x_flr_clnup_poll_hw_counter(struct bnx2x_softc *sc, uint32_t reg,
10759                               __rte_unused const char *msg, uint32_t poll_cnt)
10760 {
10761         uint32_t val = bnx2x_flr_clnup_reg_poll(sc, reg, 0, poll_cnt);
10762
10763         if (val != 0) {
10764                 PMD_DRV_LOG(NOTICE, "%s usage count=%d", msg, val);
10765                 return -1;
10766         }
10767
10768         return 0;
10769 }
10770
10771 /* Common routines with VF FLR cleanup */
10772 static uint32_t bnx2x_flr_clnup_poll_count(struct bnx2x_softc *sc)
10773 {
10774         /* adjust polling timeout */
10775         if (CHIP_REV_IS_EMUL(sc)) {
10776                 return FLR_POLL_CNT * 2000;
10777         }
10778
10779         if (CHIP_REV_IS_FPGA(sc)) {
10780                 return FLR_POLL_CNT * 120;
10781         }
10782
10783         return FLR_POLL_CNT;
10784 }
10785
10786 static int bnx2x_poll_hw_usage_counters(struct bnx2x_softc *sc, uint32_t poll_cnt)
10787 {
10788         /* wait for CFC PF usage-counter to zero (includes all the VFs) */
10789         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10790                                           CFC_REG_NUM_LCIDS_INSIDE_PF,
10791                                           "CFC PF usage counter timed out",
10792                                           poll_cnt)) {
10793                 return -1;
10794         }
10795
10796         /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
10797         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10798                                           DORQ_REG_PF_USAGE_CNT,
10799                                           "DQ PF usage counter timed out",
10800                                           poll_cnt)) {
10801                 return -1;
10802         }
10803
10804         /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
10805         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10806                                           QM_REG_PF_USG_CNT_0 + 4 * SC_FUNC(sc),
10807                                           "QM PF usage counter timed out",
10808                                           poll_cnt)) {
10809                 return -1;
10810         }
10811
10812         /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
10813         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10814                                           TM_REG_LIN0_VNIC_UC + 4 * SC_PORT(sc),
10815                                           "Timers VNIC usage counter timed out",
10816                                           poll_cnt)) {
10817                 return -1;
10818         }
10819
10820         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10821                                           TM_REG_LIN0_NUM_SCANS +
10822                                           4 * SC_PORT(sc),
10823                                           "Timers NUM_SCANS usage counter timed out",
10824                                           poll_cnt)) {
10825                 return -1;
10826         }
10827
10828         /* Wait DMAE PF usage counter to zero */
10829         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10830                                           dmae_reg_go_c[INIT_DMAE_C(sc)],
10831                                           "DMAE dommand register timed out",
10832                                           poll_cnt)) {
10833                 return -1;
10834         }
10835
10836         return 0;
10837 }
10838
10839 #define OP_GEN_PARAM(param)                                            \
10840         (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
10841 #define OP_GEN_TYPE(type)                                           \
10842         (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
10843 #define OP_GEN_AGG_VECT(index)                                             \
10844         (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
10845
10846 static int
10847 bnx2x_send_final_clnup(struct bnx2x_softc *sc, uint8_t clnup_func,
10848                      uint32_t poll_cnt)
10849 {
10850         uint32_t op_gen_command = 0;
10851         uint32_t comp_addr = (BAR_CSTRORM_INTMEM +
10852                               CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func));
10853         int ret = 0;
10854
10855         if (REG_RD(sc, comp_addr)) {
10856                 PMD_DRV_LOG(NOTICE,
10857                             "Cleanup complete was not 0 before sending");
10858                 return -1;
10859         }
10860
10861         op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
10862         op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
10863         op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
10864         op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
10865
10866         REG_WR(sc, XSDM_REG_OPERATION_GEN, op_gen_command);
10867
10868         if (bnx2x_flr_clnup_reg_poll(sc, comp_addr, 1, poll_cnt) != 1) {
10869                 PMD_DRV_LOG(NOTICE, "FW final cleanup did not succeed");
10870                 PMD_DRV_LOG(DEBUG, "At timeout completion address contained %x",
10871                             (REG_RD(sc, comp_addr)));
10872                 rte_panic("FLR cleanup failed");
10873                 return -1;
10874         }
10875
10876         /* Zero completion for nxt FLR */
10877         REG_WR(sc, comp_addr, 0);
10878
10879         return ret;
10880 }
10881
10882 static void
10883 bnx2x_pbf_pN_buf_flushed(struct bnx2x_softc *sc, struct pbf_pN_buf_regs *regs,
10884                        uint32_t poll_count)
10885 {
10886         uint32_t init_crd, crd, crd_start, crd_freed, crd_freed_start;
10887         uint32_t cur_cnt = poll_count;
10888
10889         crd_freed = crd_freed_start = REG_RD(sc, regs->crd_freed);
10890         crd = crd_start = REG_RD(sc, regs->crd);
10891         init_crd = REG_RD(sc, regs->init_crd);
10892
10893         while ((crd != init_crd) &&
10894                ((uint32_t) ((int32_t) crd_freed - (int32_t) crd_freed_start) <
10895                 (init_crd - crd_start))) {
10896                 if (cur_cnt--) {
10897                         DELAY(FLR_WAIT_INTERVAL);
10898                         crd = REG_RD(sc, regs->crd);
10899                         crd_freed = REG_RD(sc, regs->crd_freed);
10900                 } else {
10901                         break;
10902                 }
10903         }
10904 }
10905
10906 static void
10907 bnx2x_pbf_pN_cmd_flushed(struct bnx2x_softc *sc, struct pbf_pN_cmd_regs *regs,
10908                        uint32_t poll_count)
10909 {
10910         uint32_t occup, to_free, freed, freed_start;
10911         uint32_t cur_cnt = poll_count;
10912
10913         occup = to_free = REG_RD(sc, regs->lines_occup);
10914         freed = freed_start = REG_RD(sc, regs->lines_freed);
10915
10916         while (occup &&
10917                ((uint32_t) ((int32_t) freed - (int32_t) freed_start) <
10918                 to_free)) {
10919                 if (cur_cnt--) {
10920                         DELAY(FLR_WAIT_INTERVAL);
10921                         occup = REG_RD(sc, regs->lines_occup);
10922                         freed = REG_RD(sc, regs->lines_freed);
10923                 } else {
10924                         break;
10925                 }
10926         }
10927 }
10928
10929 static void bnx2x_tx_hw_flushed(struct bnx2x_softc *sc, uint32_t poll_count)
10930 {
10931         struct pbf_pN_cmd_regs cmd_regs[] = {
10932                 {0, (CHIP_IS_E3B0(sc)) ?
10933                  PBF_REG_TQ_OCCUPANCY_Q0 : PBF_REG_P0_TQ_OCCUPANCY,
10934                  (CHIP_IS_E3B0(sc)) ?
10935                  PBF_REG_TQ_LINES_FREED_CNT_Q0 : PBF_REG_P0_TQ_LINES_FREED_CNT},
10936                 {1, (CHIP_IS_E3B0(sc)) ?
10937                  PBF_REG_TQ_OCCUPANCY_Q1 : PBF_REG_P1_TQ_OCCUPANCY,
10938                  (CHIP_IS_E3B0(sc)) ?
10939                  PBF_REG_TQ_LINES_FREED_CNT_Q1 : PBF_REG_P1_TQ_LINES_FREED_CNT},
10940                 {4, (CHIP_IS_E3B0(sc)) ?
10941                  PBF_REG_TQ_OCCUPANCY_LB_Q : PBF_REG_P4_TQ_OCCUPANCY,
10942                  (CHIP_IS_E3B0(sc)) ?
10943                  PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
10944                  PBF_REG_P4_TQ_LINES_FREED_CNT}
10945         };
10946
10947         struct pbf_pN_buf_regs buf_regs[] = {
10948                 {0, (CHIP_IS_E3B0(sc)) ?
10949                  PBF_REG_INIT_CRD_Q0 : PBF_REG_P0_INIT_CRD,
10950                  (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q0 : PBF_REG_P0_CREDIT,
10951                  (CHIP_IS_E3B0(sc)) ?
10952                  PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
10953                  PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
10954                 {1, (CHIP_IS_E3B0(sc)) ?
10955                  PBF_REG_INIT_CRD_Q1 : PBF_REG_P1_INIT_CRD,
10956                  (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q1 : PBF_REG_P1_CREDIT,
10957                  (CHIP_IS_E3B0(sc)) ?
10958                  PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
10959                  PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
10960                 {4, (CHIP_IS_E3B0(sc)) ?
10961                  PBF_REG_INIT_CRD_LB_Q : PBF_REG_P4_INIT_CRD,
10962                  (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_LB_Q : PBF_REG_P4_CREDIT,
10963                  (CHIP_IS_E3B0(sc)) ?
10964                  PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
10965                  PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
10966         };
10967
10968         uint32_t i;
10969
10970         /* Verify the command queues are flushed P0, P1, P4 */
10971         for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) {
10972                 bnx2x_pbf_pN_cmd_flushed(sc, &cmd_regs[i], poll_count);
10973         }
10974
10975         /* Verify the transmission buffers are flushed P0, P1, P4 */
10976         for (i = 0; i < ARRAY_SIZE(buf_regs); i++) {
10977                 bnx2x_pbf_pN_buf_flushed(sc, &buf_regs[i], poll_count);
10978         }
10979 }
10980
10981 static void bnx2x_hw_enable_status(struct bnx2x_softc *sc)
10982 {
10983         __rte_unused uint32_t val;
10984
10985         val = REG_RD(sc, CFC_REG_WEAK_ENABLE_PF);
10986         PMD_DRV_LOG(DEBUG, "CFC_REG_WEAK_ENABLE_PF is 0x%x", val);
10987
10988         val = REG_RD(sc, PBF_REG_DISABLE_PF);
10989         PMD_DRV_LOG(DEBUG, "PBF_REG_DISABLE_PF is 0x%x", val);
10990
10991         val = REG_RD(sc, IGU_REG_PCI_PF_MSI_EN);
10992         PMD_DRV_LOG(DEBUG, "IGU_REG_PCI_PF_MSI_EN is 0x%x", val);
10993
10994         val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_EN);
10995         PMD_DRV_LOG(DEBUG, "IGU_REG_PCI_PF_MSIX_EN is 0x%x", val);
10996
10997         val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
10998         PMD_DRV_LOG(DEBUG, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x", val);
10999
11000         val = REG_RD(sc, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
11001         PMD_DRV_LOG(DEBUG, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x", val);
11002
11003         val = REG_RD(sc, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
11004         PMD_DRV_LOG(DEBUG, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x", val);
11005
11006         val = REG_RD(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
11007         PMD_DRV_LOG(DEBUG, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x",
11008                     val);
11009 }
11010
11011 /**
11012  *      bnx2x_pf_flr_clnup
11013  *      a. re-enable target read on the PF
11014  *      b. poll cfc per function usgae counter
11015  *      c. poll the qm perfunction usage counter
11016  *      d. poll the tm per function usage counter
11017  *      e. poll the tm per function scan-done indication
11018  *      f. clear the dmae channel associated wit hthe PF
11019  *      g. zero the igu 'trailing edge' and 'leading edge' regs (attentions)
11020  *      h. call the common flr cleanup code with -1 (pf indication)
11021  */
11022 static int bnx2x_pf_flr_clnup(struct bnx2x_softc *sc)
11023 {
11024         uint32_t poll_cnt = bnx2x_flr_clnup_poll_count(sc);
11025
11026         /* Re-enable PF target read access */
11027         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
11028
11029         /* Poll HW usage counters */
11030         if (bnx2x_poll_hw_usage_counters(sc, poll_cnt)) {
11031                 return -1;
11032         }
11033
11034         /* Zero the igu 'trailing edge' and 'leading edge' */
11035
11036         /* Send the FW cleanup command */
11037         if (bnx2x_send_final_clnup(sc, (uint8_t) SC_FUNC(sc), poll_cnt)) {
11038                 return -1;
11039         }
11040
11041         /* ATC cleanup */
11042
11043         /* Verify TX hw is flushed */
11044         bnx2x_tx_hw_flushed(sc, poll_cnt);
11045
11046         /* Wait 100ms (not adjusted according to platform) */
11047         DELAY(100000);
11048
11049         /* Verify no pending pci transactions */
11050         if (bnx2x_is_pcie_pending(sc)) {
11051                 PMD_DRV_LOG(NOTICE, "PCIE Transactions still pending");
11052         }
11053
11054         /* Debug */
11055         bnx2x_hw_enable_status(sc);
11056
11057         /*
11058          * Master enable - Due to WB DMAE writes performed before this
11059          * register is re-initialized as part of the regular function init
11060          */
11061         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11062
11063         return 0;
11064 }
11065
11066 static int bnx2x_init_hw_func(struct bnx2x_softc *sc)
11067 {
11068         int port = SC_PORT(sc);
11069         int func = SC_FUNC(sc);
11070         int init_phase = PHASE_PF0 + func;
11071         struct ecore_ilt *ilt = sc->ilt;
11072         uint16_t cdu_ilt_start;
11073         uint32_t addr, val;
11074         uint32_t main_mem_base, main_mem_size, main_mem_prty_clr;
11075         int main_mem_width, rc;
11076         uint32_t i;
11077
11078         PMD_DRV_LOG(DEBUG, "starting func init for func %d", func);
11079
11080         /* FLR cleanup */
11081         if (!CHIP_IS_E1x(sc)) {
11082                 rc = bnx2x_pf_flr_clnup(sc);
11083                 if (rc) {
11084                         PMD_DRV_LOG(NOTICE, "FLR cleanup failed!");
11085                         return rc;
11086                 }
11087         }
11088
11089         /* set MSI reconfigure capability */
11090         if (sc->devinfo.int_block == INT_BLOCK_HC) {
11091                 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
11092                 val = REG_RD(sc, addr);
11093                 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
11094                 REG_WR(sc, addr, val);
11095         }
11096
11097         ecore_init_block(sc, BLOCK_PXP, init_phase);
11098         ecore_init_block(sc, BLOCK_PXP2, init_phase);
11099
11100         ilt = sc->ilt;
11101         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
11102
11103         for (i = 0; i < L2_ILT_LINES(sc); i++) {
11104                 ilt->lines[cdu_ilt_start + i].page = sc->context[i].vcxt;
11105                 ilt->lines[cdu_ilt_start + i].page_mapping =
11106                     (phys_addr_t)sc->context[i].vcxt_dma.paddr;
11107                 ilt->lines[cdu_ilt_start + i].size = sc->context[i].size;
11108         }
11109         ecore_ilt_init_op(sc, INITOP_SET);
11110
11111         REG_WR(sc, PRS_REG_NIC_MODE, 1);
11112
11113         if (!CHIP_IS_E1x(sc)) {
11114                 uint32_t pf_conf = IGU_PF_CONF_FUNC_EN;
11115
11116 /* Turn on a single ISR mode in IGU if driver is going to use
11117  * INT#x or MSI
11118  */
11119                 if ((sc->interrupt_mode != INTR_MODE_MSIX)
11120                     || (sc->interrupt_mode != INTR_MODE_SINGLE_MSIX)) {
11121                         pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
11122                 }
11123
11124 /*
11125  * Timers workaround bug: function init part.
11126  * Need to wait 20msec after initializing ILT,
11127  * needed to make sure there are no requests in
11128  * one of the PXP internal queues with "old" ILT addresses
11129  */
11130                 DELAY(20000);
11131
11132 /*
11133  * Master enable - Due to WB DMAE writes performed before this
11134  * register is re-initialized as part of the regular function
11135  * init
11136  */
11137                 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11138 /* Enable the function in IGU */
11139                 REG_WR(sc, IGU_REG_PF_CONFIGURATION, pf_conf);
11140         }
11141
11142         sc->dmae_ready = 1;
11143
11144         ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
11145
11146         if (!CHIP_IS_E1x(sc))
11147                 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
11148
11149         ecore_init_block(sc, BLOCK_ATC, init_phase);
11150         ecore_init_block(sc, BLOCK_DMAE, init_phase);
11151         ecore_init_block(sc, BLOCK_NIG, init_phase);
11152         ecore_init_block(sc, BLOCK_SRC, init_phase);
11153         ecore_init_block(sc, BLOCK_MISC, init_phase);
11154         ecore_init_block(sc, BLOCK_TCM, init_phase);
11155         ecore_init_block(sc, BLOCK_UCM, init_phase);
11156         ecore_init_block(sc, BLOCK_CCM, init_phase);
11157         ecore_init_block(sc, BLOCK_XCM, init_phase);
11158         ecore_init_block(sc, BLOCK_TSEM, init_phase);
11159         ecore_init_block(sc, BLOCK_USEM, init_phase);
11160         ecore_init_block(sc, BLOCK_CSEM, init_phase);
11161         ecore_init_block(sc, BLOCK_XSEM, init_phase);
11162
11163         if (!CHIP_IS_E1x(sc))
11164                 REG_WR(sc, QM_REG_PF_EN, 1);
11165
11166         if (!CHIP_IS_E1x(sc)) {
11167                 REG_WR(sc, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11168                 REG_WR(sc, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11169                 REG_WR(sc, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11170                 REG_WR(sc, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11171         }
11172         ecore_init_block(sc, BLOCK_QM, init_phase);
11173
11174         ecore_init_block(sc, BLOCK_TM, init_phase);
11175         ecore_init_block(sc, BLOCK_DORQ, init_phase);
11176
11177         ecore_init_block(sc, BLOCK_BRB1, init_phase);
11178         ecore_init_block(sc, BLOCK_PRS, init_phase);
11179         ecore_init_block(sc, BLOCK_TSDM, init_phase);
11180         ecore_init_block(sc, BLOCK_CSDM, init_phase);
11181         ecore_init_block(sc, BLOCK_USDM, init_phase);
11182         ecore_init_block(sc, BLOCK_XSDM, init_phase);
11183         ecore_init_block(sc, BLOCK_UPB, init_phase);
11184         ecore_init_block(sc, BLOCK_XPB, init_phase);
11185         ecore_init_block(sc, BLOCK_PBF, init_phase);
11186         if (!CHIP_IS_E1x(sc))
11187                 REG_WR(sc, PBF_REG_DISABLE_PF, 0);
11188
11189         ecore_init_block(sc, BLOCK_CDU, init_phase);
11190
11191         ecore_init_block(sc, BLOCK_CFC, init_phase);
11192
11193         if (!CHIP_IS_E1x(sc))
11194                 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 1);
11195
11196         if (IS_MF(sc)) {
11197                 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
11198                 REG_WR(sc, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8, OVLAN(sc));
11199         }
11200
11201         ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
11202
11203         /* HC init per function */
11204         if (sc->devinfo.int_block == INT_BLOCK_HC) {
11205                 if (CHIP_IS_E1H(sc)) {
11206                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11207
11208                         REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11209                         REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11210                 }
11211                 ecore_init_block(sc, BLOCK_HC, init_phase);
11212
11213         } else {
11214                 uint32_t num_segs, sb_idx, prod_offset;
11215
11216                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11217
11218                 if (!CHIP_IS_E1x(sc)) {
11219                         REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11220                         REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11221                 }
11222
11223                 ecore_init_block(sc, BLOCK_IGU, init_phase);
11224
11225                 if (!CHIP_IS_E1x(sc)) {
11226                         int dsb_idx = 0;
11227         /**
11228          * Producer memory:
11229          * E2 mode: address 0-135 match to the mapping memory;
11230          * 136 - PF0 default prod; 137 - PF1 default prod;
11231          * 138 - PF2 default prod; 139 - PF3 default prod;
11232          * 140 - PF0 attn prod;    141 - PF1 attn prod;
11233          * 142 - PF2 attn prod;    143 - PF3 attn prod;
11234          * 144-147 reserved.
11235          *
11236          * E1.5 mode - In backward compatible mode;
11237          * for non default SB; each even line in the memory
11238          * holds the U producer and each odd line hold
11239          * the C producer. The first 128 producers are for
11240          * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
11241          * producers are for the DSB for each PF.
11242          * Each PF has five segments: (the order inside each
11243          * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
11244          * 132-135 C prods; 136-139 X prods; 140-143 T prods;
11245          * 144-147 attn prods;
11246          */
11247                         /* non-default-status-blocks */
11248                         num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11249                             IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
11250                         for (sb_idx = 0; sb_idx < sc->igu_sb_cnt; sb_idx++) {
11251                                 prod_offset = (sc->igu_base_sb + sb_idx) *
11252                                     num_segs;
11253
11254                                 for (i = 0; i < num_segs; i++) {
11255                                         addr = IGU_REG_PROD_CONS_MEMORY +
11256                                             (prod_offset + i) * 4;
11257                                         REG_WR(sc, addr, 0);
11258                                 }
11259                                 /* send consumer update with value 0 */
11260                                 bnx2x_ack_sb(sc, sc->igu_base_sb + sb_idx,
11261                                            USTORM_ID, 0, IGU_INT_NOP, 1);
11262                                 bnx2x_igu_clear_sb(sc, sc->igu_base_sb + sb_idx);
11263                         }
11264
11265                         /* default-status-blocks */
11266                         num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11267                             IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
11268
11269                         if (CHIP_IS_MODE_4_PORT(sc))
11270                                 dsb_idx = SC_FUNC(sc);
11271                         else
11272                                 dsb_idx = SC_VN(sc);
11273
11274                         prod_offset = (CHIP_INT_MODE_IS_BC(sc) ?
11275                                        IGU_BC_BASE_DSB_PROD + dsb_idx :
11276                                        IGU_NORM_BASE_DSB_PROD + dsb_idx);
11277
11278                         /*
11279                          * igu prods come in chunks of E1HVN_MAX (4) -
11280                          * does not matters what is the current chip mode
11281                          */
11282                         for (i = 0; i < (num_segs * E1HVN_MAX); i += E1HVN_MAX) {
11283                                 addr = IGU_REG_PROD_CONS_MEMORY +
11284                                     (prod_offset + i) * 4;
11285                                 REG_WR(sc, addr, 0);
11286                         }
11287                         /* send consumer update with 0 */
11288                         if (CHIP_INT_MODE_IS_BC(sc)) {
11289                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11290                                            USTORM_ID, 0, IGU_INT_NOP, 1);
11291                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11292                                            CSTORM_ID, 0, IGU_INT_NOP, 1);
11293                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11294                                            XSTORM_ID, 0, IGU_INT_NOP, 1);
11295                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11296                                            TSTORM_ID, 0, IGU_INT_NOP, 1);
11297                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11298                                            ATTENTION_ID, 0, IGU_INT_NOP, 1);
11299                         } else {
11300                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11301                                            USTORM_ID, 0, IGU_INT_NOP, 1);
11302                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11303                                            ATTENTION_ID, 0, IGU_INT_NOP, 1);
11304                         }
11305                         bnx2x_igu_clear_sb(sc, sc->igu_dsb_id);
11306
11307                         /* !!! these should become driver const once
11308                            rf-tool supports split-68 const */
11309                         REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
11310                         REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
11311                         REG_WR(sc, IGU_REG_SB_MASK_LSB, 0);
11312                         REG_WR(sc, IGU_REG_SB_MASK_MSB, 0);
11313                         REG_WR(sc, IGU_REG_PBA_STATUS_LSB, 0);
11314                         REG_WR(sc, IGU_REG_PBA_STATUS_MSB, 0);
11315                 }
11316         }
11317
11318         /* Reset PCIE errors for debug */
11319         REG_WR(sc, 0x2114, 0xffffffff);
11320         REG_WR(sc, 0x2120, 0xffffffff);
11321
11322         if (CHIP_IS_E1x(sc)) {
11323                 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2;    /*dwords */
11324                 main_mem_base = HC_REG_MAIN_MEMORY +
11325                     SC_PORT(sc) * (main_mem_size * 4);
11326                 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
11327                 main_mem_width = 8;
11328
11329                 val = REG_RD(sc, main_mem_prty_clr);
11330                 if (val) {
11331                         PMD_DRV_LOG(DEBUG,
11332                                     "Parity errors in HC block during function init (0x%x)!",
11333                                     val);
11334                 }
11335
11336 /* Clear "false" parity errors in MSI-X table */
11337                 for (i = main_mem_base;
11338                      i < main_mem_base + main_mem_size * 4;
11339                      i += main_mem_width) {
11340                         bnx2x_read_dmae(sc, i, main_mem_width / 4);
11341                         bnx2x_write_dmae(sc, BNX2X_SP_MAPPING(sc, wb_data),
11342                                        i, main_mem_width / 4);
11343                 }
11344 /* Clear HC parity attention */
11345                 REG_RD(sc, main_mem_prty_clr);
11346         }
11347
11348         /* Enable STORMs SP logging */
11349         REG_WR8(sc, BAR_USTRORM_INTMEM +
11350                 USTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11351         REG_WR8(sc, BAR_TSTRORM_INTMEM +
11352                 TSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11353         REG_WR8(sc, BAR_CSTRORM_INTMEM +
11354                 CSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11355         REG_WR8(sc, BAR_XSTRORM_INTMEM +
11356                 XSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11357
11358         elink_phy_probe(&sc->link_params);
11359
11360         return 0;
11361 }
11362
11363 static void bnx2x_link_reset(struct bnx2x_softc *sc)
11364 {
11365         if (!BNX2X_NOMCP(sc)) {
11366                 elink_lfa_reset(&sc->link_params, &sc->link_vars);
11367         } else {
11368                 if (!CHIP_REV_IS_SLOW(sc)) {
11369                         PMD_DRV_LOG(WARNING,
11370                                     "Bootcode is missing - cannot reset link");
11371                 }
11372         }
11373 }
11374
11375 static void bnx2x_reset_port(struct bnx2x_softc *sc)
11376 {
11377         int port = SC_PORT(sc);
11378         uint32_t val;
11379
11380         /* reset physical Link */
11381         bnx2x_link_reset(sc);
11382
11383         REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
11384
11385         /* Do not rcv packets to BRB */
11386         REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + port * 4, 0x0);
11387         /* Do not direct rcv packets that are not for MCP to the BRB */
11388         REG_WR(sc, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
11389                     NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
11390
11391         /* Configure AEU */
11392         REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, 0);
11393
11394         DELAY(100000);
11395
11396         /* Check for BRB port occupancy */
11397         val = REG_RD(sc, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port * 4);
11398         if (val) {
11399                 PMD_DRV_LOG(DEBUG,
11400                             "BRB1 is not empty, %d blocks are occupied", val);
11401         }
11402 }
11403
11404 static void bnx2x_ilt_wr(struct bnx2x_softc *sc, uint32_t index, phys_addr_t addr)
11405 {
11406         int reg;
11407         uint32_t wb_write[2];
11408
11409         reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index * 8;
11410
11411         wb_write[0] = ONCHIP_ADDR1(addr);
11412         wb_write[1] = ONCHIP_ADDR2(addr);
11413         REG_WR_DMAE(sc, reg, wb_write, 2);
11414 }
11415
11416 static void bnx2x_clear_func_ilt(struct bnx2x_softc *sc, uint32_t func)
11417 {
11418         uint32_t i, base = FUNC_ILT_BASE(func);
11419         for (i = base; i < base + ILT_PER_FUNC; i++) {
11420                 bnx2x_ilt_wr(sc, i, 0);
11421         }
11422 }
11423
11424 static void bnx2x_reset_func(struct bnx2x_softc *sc)
11425 {
11426         struct bnx2x_fastpath *fp;
11427         int port = SC_PORT(sc);
11428         int func = SC_FUNC(sc);
11429         int i;
11430
11431         /* Disable the function in the FW */
11432         REG_WR8(sc, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
11433         REG_WR8(sc, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
11434         REG_WR8(sc, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
11435         REG_WR8(sc, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
11436
11437         /* FP SBs */
11438         FOR_EACH_ETH_QUEUE(sc, i) {
11439                 fp = &sc->fp[i];
11440                 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11441                         CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
11442                         SB_DISABLED);
11443         }
11444
11445         /* SP SB */
11446         REG_WR8(sc, BAR_CSTRORM_INTMEM +
11447                 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), SB_DISABLED);
11448
11449         for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) {
11450                 REG_WR(sc, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
11451                        0);
11452         }
11453
11454         /* Configure IGU */
11455         if (sc->devinfo.int_block == INT_BLOCK_HC) {
11456                 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11457                 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11458         } else {
11459                 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11460                 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11461         }
11462
11463         if (CNIC_LOADED(sc)) {
11464 /* Disable Timer scan */
11465                 REG_WR(sc, TM_REG_EN_LINEAR0_TIMER + port * 4, 0);
11466 /*
11467  * Wait for at least 10ms and up to 2 second for the timers
11468  * scan to complete
11469  */
11470                 for (i = 0; i < 200; i++) {
11471                         DELAY(10000);
11472                         if (!REG_RD(sc, TM_REG_LIN0_SCAN_ON + port * 4))
11473                                 break;
11474                 }
11475         }
11476
11477         /* Clear ILT */
11478         bnx2x_clear_func_ilt(sc, func);
11479
11480         /*
11481          * Timers workaround bug for E2: if this is vnic-3,
11482          * we need to set the entire ilt range for this timers.
11483          */
11484         if (!CHIP_IS_E1x(sc) && SC_VN(sc) == 3) {
11485                 struct ilt_client_info ilt_cli;
11486 /* use dummy TM client */
11487                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
11488                 ilt_cli.start = 0;
11489                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
11490                 ilt_cli.client_num = ILT_CLIENT_TM;
11491
11492                 ecore_ilt_boundry_init_op(sc, &ilt_cli, 0);
11493         }
11494
11495         /* this assumes that reset_port() called before reset_func() */
11496         if (!CHIP_IS_E1x(sc)) {
11497                 bnx2x_pf_disable(sc);
11498         }
11499
11500         sc->dmae_ready = 0;
11501 }
11502
11503 static void bnx2x_release_firmware(struct bnx2x_softc *sc)
11504 {
11505         rte_free(sc->init_ops);
11506         rte_free(sc->init_ops_offsets);
11507         rte_free(sc->init_data);
11508         rte_free(sc->iro_array);
11509 }
11510
11511 static int bnx2x_init_firmware(struct bnx2x_softc *sc)
11512 {
11513         uint32_t len, i;
11514         uint8_t *p = sc->firmware;
11515         uint32_t off[24];
11516
11517         for (i = 0; i < 24; ++i)
11518                 off[i] = rte_be_to_cpu_32(*((uint32_t *) sc->firmware + i));
11519
11520         len = off[0];
11521         sc->init_ops = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11522         if (!sc->init_ops)
11523                 goto alloc_failed;
11524         bnx2x_data_to_init_ops(p + off[1], sc->init_ops, len);
11525
11526         len = off[2];
11527         sc->init_ops_offsets = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11528         if (!sc->init_ops_offsets)
11529                 goto alloc_failed;
11530         bnx2x_data_to_init_offsets(p + off[3], sc->init_ops_offsets, len);
11531
11532         len = off[4];
11533         sc->init_data = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11534         if (!sc->init_data)
11535                 goto alloc_failed;
11536         bnx2x_data_to_init_data(p + off[5], sc->init_data, len);
11537
11538         sc->tsem_int_table_data = p + off[7];
11539         sc->tsem_pram_data = p + off[9];
11540         sc->usem_int_table_data = p + off[11];
11541         sc->usem_pram_data = p + off[13];
11542         sc->csem_int_table_data = p + off[15];
11543         sc->csem_pram_data = p + off[17];
11544         sc->xsem_int_table_data = p + off[19];
11545         sc->xsem_pram_data = p + off[21];
11546
11547         len = off[22];
11548         sc->iro_array = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11549         if (!sc->iro_array)
11550                 goto alloc_failed;
11551         bnx2x_data_to_iro_array(p + off[23], sc->iro_array, len);
11552
11553         return 0;
11554
11555 alloc_failed:
11556         bnx2x_release_firmware(sc);
11557         return -1;
11558 }
11559
11560 static int cut_gzip_prefix(const uint8_t * zbuf, int len)
11561 {
11562 #define MIN_PREFIX_SIZE (10)
11563
11564         int n = MIN_PREFIX_SIZE;
11565         uint16_t xlen;
11566
11567         if (!(zbuf[0] == 0x1f && zbuf[1] == 0x8b && zbuf[2] == Z_DEFLATED) ||
11568             len <= MIN_PREFIX_SIZE) {
11569                 return -1;
11570         }
11571
11572         /* optional extra fields are present */
11573         if (zbuf[3] & 0x4) {
11574                 xlen = zbuf[13];
11575                 xlen <<= 8;
11576                 xlen += zbuf[12];
11577
11578                 n += xlen;
11579         }
11580         /* file name is present */
11581         if (zbuf[3] & 0x8) {
11582                 while ((zbuf[n++] != 0) && (n < len)) ;
11583         }
11584
11585         return n;
11586 }
11587
11588 static int ecore_gunzip(struct bnx2x_softc *sc, const uint8_t * zbuf, int len)
11589 {
11590         int ret;
11591         int data_begin = cut_gzip_prefix(zbuf, len);
11592
11593         PMD_DRV_LOG(DEBUG, "ecore_gunzip %d", len);
11594
11595         if (data_begin <= 0) {
11596                 PMD_DRV_LOG(NOTICE, "bad gzip prefix");
11597                 return -1;
11598         }
11599
11600         memset(&zlib_stream, 0, sizeof(zlib_stream));
11601         zlib_stream.next_in = zbuf + data_begin;
11602         zlib_stream.avail_in = len - data_begin;
11603         zlib_stream.next_out = sc->gz_buf;
11604         zlib_stream.avail_out = FW_BUF_SIZE;
11605
11606         ret = inflateInit2(&zlib_stream, -MAX_WBITS);
11607         if (ret != Z_OK) {
11608                 PMD_DRV_LOG(NOTICE, "zlib inflateInit2 error");
11609                 return ret;
11610         }
11611
11612         ret = inflate(&zlib_stream, Z_FINISH);
11613         if ((ret != Z_STREAM_END) && (ret != Z_OK)) {
11614                 PMD_DRV_LOG(NOTICE, "zlib inflate error: %d %s", ret,
11615                             zlib_stream.msg);
11616         }
11617
11618         sc->gz_outlen = zlib_stream.total_out;
11619         if (sc->gz_outlen & 0x3) {
11620                 PMD_DRV_LOG(NOTICE, "firmware is not aligned. gz_outlen == %d",
11621                             sc->gz_outlen);
11622         }
11623         sc->gz_outlen >>= 2;
11624
11625         inflateEnd(&zlib_stream);
11626
11627         if (ret == Z_STREAM_END)
11628                 return 0;
11629
11630         return ret;
11631 }
11632
11633 static void
11634 ecore_write_dmae_phys_len(struct bnx2x_softc *sc, phys_addr_t phys_addr,
11635                           uint32_t addr, uint32_t len)
11636 {
11637         bnx2x_write_dmae_phys_len(sc, phys_addr, addr, len);
11638 }
11639
11640 void
11641 ecore_storm_memset_struct(struct bnx2x_softc *sc, uint32_t addr, size_t size,
11642                           uint32_t * data)
11643 {
11644         uint8_t i;
11645         for (i = 0; i < size / 4; i++) {
11646                 REG_WR(sc, addr + (i * 4), data[i]);
11647         }
11648 }
11649
11650 static const char *get_ext_phy_type(uint32_t ext_phy_type)
11651 {
11652         uint32_t phy_type_idx = ext_phy_type >> 8;
11653         static const char *types[] =
11654             { "DIRECT", "BNX2X-8071", "BNX2X-8072", "BNX2X-8073",
11655                 "BNX2X-8705", "BNX2X-8706", "BNX2X-8726", "BNX2X-8481", "SFX-7101",
11656                 "BNX2X-8727",
11657                 "BNX2X-8727-NOC", "BNX2X-84823", "NOT_CONN", "FAILURE"
11658         };
11659
11660         if (phy_type_idx < 12)
11661                 return types[phy_type_idx];
11662         else if (PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN == ext_phy_type)
11663                 return types[12];
11664         else
11665                 return types[13];
11666 }
11667
11668 static const char *get_state(uint32_t state)
11669 {
11670         uint32_t state_idx = state >> 12;
11671         static const char *states[] = { "CLOSED", "OPENING_WAIT4_LOAD",
11672                 "OPENING_WAIT4_PORT", "OPEN", "CLOSING_WAIT4_HALT",
11673                 "CLOSING_WAIT4_DELETE", "CLOSING_WAIT4_UNLOAD",
11674                 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
11675                 "UNKNOWN", "DISABLED", "DIAG", "ERROR", "UNDEFINED"
11676         };
11677
11678         if (state_idx <= 0xF)
11679                 return states[state_idx];
11680         else
11681                 return states[0x10];
11682 }
11683
11684 static const char *get_recovery_state(uint32_t state)
11685 {
11686         static const char *states[] = { "NONE", "DONE", "INIT",
11687                 "WAIT", "FAILED", "NIC_LOADING"
11688         };
11689         return states[state];
11690 }
11691
11692 static const char *get_rx_mode(uint32_t mode)
11693 {
11694         static const char *modes[] = { "NONE", "NORMAL", "ALLMULTI",
11695                 "PROMISC", "MAX_MULTICAST", "ERROR"
11696         };
11697
11698         if (mode < 0x4)
11699                 return modes[mode];
11700         else if (BNX2X_MAX_MULTICAST == mode)
11701                 return modes[4];
11702         else
11703                 return modes[5];
11704 }
11705
11706 #define BNX2X_INFO_STR_MAX 256
11707 static const char *get_bnx2x_flags(uint32_t flags)
11708 {
11709         int i;
11710         static const char *flag[] = { "ONE_PORT ", "NO_ISCSI ",
11711                 "NO_FCOE ", "NO_WOL ", "USING_DAC ", "USING_MSIX ",
11712                 "USING_MSI ", "DISABLE_MSI ", "UNKNOWN ", "NO_MCP ",
11713                 "SAFC_TX_FLAG ", "MF_FUNC_DIS ", "TX_SWITCHING "
11714         };
11715         static char flag_str[BNX2X_INFO_STR_MAX];
11716         memset(flag_str, 0, BNX2X_INFO_STR_MAX);
11717
11718         for (i = 0; i < 5; i++)
11719                 if (flags & (1 << i)) {
11720                         strcat(flag_str, flag[i]);
11721                         flags ^= (1 << i);
11722                 }
11723         if (flags) {
11724                 static char unknown[BNX2X_INFO_STR_MAX];
11725                 snprintf(unknown, 32, "Unknown flag mask %x", flags);
11726                 strcat(flag_str, unknown);
11727         }
11728         return flag_str;
11729 }
11730
11731 /*
11732  * Prints useful adapter info.
11733  */
11734 void bnx2x_print_adapter_info(struct bnx2x_softc *sc)
11735 {
11736         int i = 0;
11737         __rte_unused uint32_t ext_phy_type;
11738
11739         PMD_INIT_FUNC_TRACE();
11740         if (sc->link_vars.phy_flags & PHY_XGXS_FLAG)
11741                 ext_phy_type = ELINK_XGXS_EXT_PHY_TYPE(REG_RD(sc,
11742                                                               sc->
11743                                                               devinfo.shmem_base
11744                                                               + offsetof(struct
11745                                                                          shmem_region,
11746                                                                          dev_info.port_hw_config
11747                                                                          [0].external_phy_config)));
11748         else
11749                 ext_phy_type = ELINK_SERDES_EXT_PHY_TYPE(REG_RD(sc,
11750                                                                 sc->
11751                                                                 devinfo.shmem_base
11752                                                                 +
11753                                                                 offsetof(struct
11754                                                                          shmem_region,
11755                                                                          dev_info.port_hw_config
11756                                                                          [0].external_phy_config)));
11757
11758         PMD_INIT_LOG(DEBUG, "\n\n===================================\n");
11759         /* Hardware chip info. */
11760         PMD_INIT_LOG(DEBUG, "%12s : %#08x", "ASIC", sc->devinfo.chip_id);
11761         PMD_INIT_LOG(DEBUG, "%12s : %c%d", "Rev", (CHIP_REV(sc) >> 12) + 'A',
11762                      (CHIP_METAL(sc) >> 4));
11763
11764         /* Bus info. */
11765         PMD_INIT_LOG(DEBUG, "%12s : %d, ", "Bus PCIe", sc->devinfo.pcie_link_width);
11766         switch (sc->devinfo.pcie_link_speed) {
11767         case 1:
11768                 PMD_INIT_LOG(DEBUG, "%23s", "2.5 Gbps");
11769                 break;
11770         case 2:
11771                 PMD_INIT_LOG(DEBUG, "%21s", "5 Gbps");
11772                 break;
11773         case 4:
11774                 PMD_INIT_LOG(DEBUG, "%21s", "8 Gbps");
11775                 break;
11776         default:
11777                 PMD_INIT_LOG(DEBUG, "%33s", "Unknown link speed");
11778         }
11779
11780         /* Device features. */
11781         PMD_INIT_LOG(DEBUG, "%12s : ", "Flags");
11782
11783         /* Miscellaneous flags. */
11784         if (sc->devinfo.pcie_cap_flags & BNX2X_MSI_CAPABLE_FLAG) {
11785                 PMD_INIT_LOG(DEBUG, "%18s", "MSI");
11786                 i++;
11787         }
11788
11789         if (sc->devinfo.pcie_cap_flags & BNX2X_MSIX_CAPABLE_FLAG) {
11790                 if (i > 0)
11791                         PMD_INIT_LOG(DEBUG, "|");
11792                 PMD_INIT_LOG(DEBUG, "%20s", "MSI-X");
11793                 i++;
11794         }
11795
11796         if (IS_PF(sc)) {
11797                 PMD_INIT_LOG(DEBUG, "%12s : ", "Queues");
11798                 switch (sc->sp->rss_rdata.rss_mode) {
11799                 case ETH_RSS_MODE_DISABLED:
11800                         PMD_INIT_LOG(DEBUG, "%19s", "None");
11801                         break;
11802                 case ETH_RSS_MODE_REGULAR:
11803                         PMD_INIT_LOG(DEBUG, "%18s : %d", "RSS", sc->num_queues);
11804                         break;
11805                 default:
11806                         PMD_INIT_LOG(DEBUG, "%22s", "Unknown");
11807                         break;
11808                 }
11809         }
11810
11811         /* RTE and Driver versions */
11812         PMD_INIT_LOG(DEBUG, "%12s : %s", "DPDK",
11813                      rte_version());
11814         PMD_INIT_LOG(DEBUG, "%12s : %s", "Driver",
11815                      bnx2x_pmd_version());
11816
11817         /* Firmware versions and device features. */
11818         PMD_INIT_LOG(DEBUG, "%12s : %d.%d.%d",
11819                      "Firmware",
11820                      BNX2X_5710_FW_MAJOR_VERSION,
11821                      BNX2X_5710_FW_MINOR_VERSION,
11822                      BNX2X_5710_FW_REVISION_VERSION);
11823         PMD_INIT_LOG(DEBUG, "%12s : %s",
11824                      "Bootcode", sc->devinfo.bc_ver_str);
11825
11826         PMD_INIT_LOG(DEBUG, "\n\n===================================\n");
11827         PMD_INIT_LOG(DEBUG, "%12s : %u", "Bnx2x Func", sc->pcie_func);
11828         PMD_INIT_LOG(DEBUG, "%12s : %s", "Bnx2x Flags", get_bnx2x_flags(sc->flags));
11829         PMD_INIT_LOG(DEBUG, "%12s : %s", "DMAE Is",
11830                      (sc->dmae_ready ? "Ready" : "Not Ready"));
11831         PMD_INIT_LOG(DEBUG, "%12s : %s", "OVLAN", (OVLAN(sc) ? "YES" : "NO"));
11832         PMD_INIT_LOG(DEBUG, "%12s : %s", "MF", (IS_MF(sc) ? "YES" : "NO"));
11833         PMD_INIT_LOG(DEBUG, "%12s : %u", "MTU", sc->mtu);
11834         PMD_INIT_LOG(DEBUG, "%12s : %s", "PHY Type", get_ext_phy_type(ext_phy_type));
11835         PMD_INIT_LOG(DEBUG, "%12s : %x:%x:%x:%x:%x:%x", "MAC Addr",
11836                         sc->link_params.mac_addr[0],
11837                         sc->link_params.mac_addr[1],
11838                         sc->link_params.mac_addr[2],
11839                         sc->link_params.mac_addr[3],
11840                         sc->link_params.mac_addr[4],
11841                         sc->link_params.mac_addr[5]);
11842         PMD_INIT_LOG(DEBUG, "%12s : %s", "RX Mode", get_rx_mode(sc->rx_mode));
11843         PMD_INIT_LOG(DEBUG, "%12s : %s", "State", get_state(sc->state));
11844         if (sc->recovery_state)
11845                 PMD_INIT_LOG(DEBUG, "%12s : %s", "Recovery",
11846                              get_recovery_state(sc->recovery_state));
11847         PMD_INIT_LOG(DEBUG, "%12s : CQ = %lx,  EQ = %lx", "SPQ Left",
11848                      sc->cq_spq_left, sc->eq_spq_left);
11849         PMD_INIT_LOG(DEBUG, "%12s : %x", "Switch", sc->link_params.switch_cfg);
11850         PMD_INIT_LOG(DEBUG, "\n\n===================================\n");
11851 }