1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2007-2013 Broadcom Corporation.
4 * Eric Davis <edavis@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
6 * Gary Zambrano <zambrano@broadcom.com>
8 * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
9 * Copyright (c) 2015-2018 Cavium Inc.
10 * All rights reserved.
14 #define BNX2X_DRIVER_VERSION "1.78.18"
17 #include "bnx2x_vfpf.h"
19 #include "ecore_init.h"
20 #include "ecore_init_ops.h"
22 #include "rte_version.h"
24 #include <sys/types.h>
28 #include <rte_string_fns.h>
30 #define BNX2X_PMD_VER_PREFIX "BNX2X PMD"
31 #define BNX2X_PMD_VERSION_MAJOR 1
32 #define BNX2X_PMD_VERSION_MINOR 0
33 #define BNX2X_PMD_VERSION_REVISION 7
34 #define BNX2X_PMD_VERSION_PATCH 1
36 static inline const char *
37 bnx2x_pmd_version(void)
39 static char version[32];
41 snprintf(version, sizeof(version), "%s %s_%d.%d.%d.%d",
44 BNX2X_PMD_VERSION_MAJOR,
45 BNX2X_PMD_VERSION_MINOR,
46 BNX2X_PMD_VERSION_REVISION,
47 BNX2X_PMD_VERSION_PATCH);
52 static z_stream zlib_stream;
54 #define EVL_VLID_MASK 0x0FFF
56 #define BNX2X_DEF_SB_ATT_IDX 0x0001
57 #define BNX2X_DEF_SB_IDX 0x0002
60 * FLR Support - bnx2x_pf_flr_clnup() is called during nic_load in the per
61 * function HW initialization.
63 #define FLR_WAIT_USEC 10000 /* 10 msecs */
64 #define FLR_WAIT_INTERVAL 50 /* usecs */
65 #define FLR_POLL_CNT (FLR_WAIT_USEC / FLR_WAIT_INTERVAL) /* 200 */
67 struct pbf_pN_buf_regs {
74 struct pbf_pN_cmd_regs {
80 /* resources needed for unloading a previously loaded device */
82 #define BNX2X_PREV_WAIT_NEEDED 1
83 rte_spinlock_t bnx2x_prev_mtx;
84 struct bnx2x_prev_list_node {
85 LIST_ENTRY(bnx2x_prev_list_node) node;
93 static LIST_HEAD(, bnx2x_prev_list_node) bnx2x_prev_list
94 = LIST_HEAD_INITIALIZER(bnx2x_prev_list);
96 static int load_count[2][3] = { { 0 } };
97 /* per-path: 0-common, 1-port0, 2-port1 */
99 static void bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg,
101 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc);
102 static void storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng,
104 static void bnx2x_set_reset_global(struct bnx2x_softc *sc);
105 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc);
106 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine);
107 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc);
108 static uint8_t bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global,
110 static void bnx2x_int_disable(struct bnx2x_softc *sc);
111 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc);
112 static void bnx2x_pf_disable(struct bnx2x_softc *sc);
113 static void bnx2x_update_rx_prod(struct bnx2x_softc *sc,
114 struct bnx2x_fastpath *fp,
115 uint16_t rx_bd_prod, uint16_t rx_cq_prod);
116 static void bnx2x_link_report_locked(struct bnx2x_softc *sc);
117 static void bnx2x_link_report(struct bnx2x_softc *sc);
118 void bnx2x_link_status_update(struct bnx2x_softc *sc);
119 static int bnx2x_alloc_mem(struct bnx2x_softc *sc);
120 static void bnx2x_free_mem(struct bnx2x_softc *sc);
121 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc);
122 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc);
123 static __rte_noinline
124 int bnx2x_nic_load(struct bnx2x_softc *sc);
126 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc);
127 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp);
128 static void bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id,
129 uint8_t storm, uint16_t index, uint8_t op,
132 int bnx2x_test_bit(int nr, volatile unsigned long *addr)
137 res = ((*addr) & (1UL << nr)) != 0;
142 void bnx2x_set_bit(unsigned int nr, volatile unsigned long *addr)
144 __sync_fetch_and_or(addr, (1UL << nr));
147 void bnx2x_clear_bit(int nr, volatile unsigned long *addr)
149 __sync_fetch_and_and(addr, ~(1UL << nr));
152 int bnx2x_test_and_clear_bit(int nr, volatile unsigned long *addr)
154 unsigned long mask = (1UL << nr);
155 return __sync_fetch_and_and(addr, ~mask) & mask;
158 int bnx2x_cmpxchg(volatile int *addr, int old, int new)
160 return __sync_val_compare_and_swap(addr, old, new);
164 bnx2x_dma_alloc(struct bnx2x_softc *sc, size_t size, struct bnx2x_dma *dma,
165 const char *msg, uint32_t align)
167 char mz_name[RTE_MEMZONE_NAMESIZE];
168 const struct rte_memzone *z;
172 snprintf(mz_name, sizeof(mz_name), "bnx2x%d_%s_%" PRIx64, SC_ABS_FUNC(sc), msg,
173 rte_get_timer_cycles());
175 snprintf(mz_name, sizeof(mz_name), "bnx2x%d_%s_%" PRIx64, sc->pcie_device, msg,
176 rte_get_timer_cycles());
178 /* Caller must take care that strlen(mz_name) < RTE_MEMZONE_NAMESIZE */
179 z = rte_memzone_reserve_aligned(mz_name, (uint64_t)size,
181 RTE_MEMZONE_IOVA_CONTIG, align);
183 PMD_DRV_LOG(ERR, sc, "DMA alloc failed for %s", msg);
186 dma->paddr = (uint64_t) z->iova;
187 dma->vaddr = z->addr;
188 dma->mzone = (const void *)z;
190 PMD_DRV_LOG(DEBUG, sc,
191 "%s: virt=%p phys=%" PRIx64, msg, dma->vaddr, dma->paddr);
196 void bnx2x_dma_free(struct bnx2x_dma *dma)
198 if (dma->mzone == NULL)
201 rte_memzone_free((const struct rte_memzone *)dma->mzone);
209 static int bnx2x_acquire_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
211 uint32_t lock_status;
212 uint32_t resource_bit = (1 << resource);
213 int func = SC_FUNC(sc);
214 uint32_t hw_lock_control_reg;
217 #ifndef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
219 PMD_INIT_FUNC_TRACE(sc);
221 PMD_INIT_FUNC_TRACE(sc);
224 /* validate the resource is within range */
225 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
226 PMD_DRV_LOG(NOTICE, sc,
227 "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
233 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
235 hw_lock_control_reg =
236 (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
239 /* validate the resource is not already taken */
240 lock_status = REG_RD(sc, hw_lock_control_reg);
241 if (lock_status & resource_bit) {
242 PMD_DRV_LOG(NOTICE, sc,
243 "resource in use (status 0x%x bit 0x%x)",
244 lock_status, resource_bit);
248 /* try every 5ms for 5 seconds */
249 for (cnt = 0; cnt < 1000; cnt++) {
250 REG_WR(sc, (hw_lock_control_reg + 4), resource_bit);
251 lock_status = REG_RD(sc, hw_lock_control_reg);
252 if (lock_status & resource_bit) {
258 PMD_DRV_LOG(NOTICE, sc, "Resource 0x%x resource_bit 0x%x lock timeout!",
259 resource, resource_bit);
263 static int bnx2x_release_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
265 uint32_t lock_status;
266 uint32_t resource_bit = (1 << resource);
267 int func = SC_FUNC(sc);
268 uint32_t hw_lock_control_reg;
270 #ifndef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
272 PMD_INIT_FUNC_TRACE(sc);
274 PMD_INIT_FUNC_TRACE(sc);
277 /* validate the resource is within range */
278 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
279 PMD_DRV_LOG(NOTICE, sc,
280 "(resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE)"
281 " resource_bit 0x%x", resource, resource_bit);
286 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
288 hw_lock_control_reg =
289 (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
292 /* validate the resource is currently taken */
293 lock_status = REG_RD(sc, hw_lock_control_reg);
294 if (!(lock_status & resource_bit)) {
295 PMD_DRV_LOG(NOTICE, sc,
296 "resource not in use (status 0x%x bit 0x%x)",
297 lock_status, resource_bit);
301 REG_WR(sc, hw_lock_control_reg, resource_bit);
305 static void bnx2x_acquire_phy_lock(struct bnx2x_softc *sc)
308 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_MDIO);
311 static void bnx2x_release_phy_lock(struct bnx2x_softc *sc)
313 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_MDIO);
314 BNX2X_PHY_UNLOCK(sc);
317 /* copy command into DMAE command memory and set DMAE command Go */
318 void bnx2x_post_dmae(struct bnx2x_softc *sc, struct dmae_command *dmae, int idx)
323 cmd_offset = (DMAE_REG_CMD_MEM + (sizeof(struct dmae_command) * idx));
324 for (i = 0; i < ((sizeof(struct dmae_command) / 4)); i++) {
325 REG_WR(sc, (cmd_offset + (i * 4)), *(((uint32_t *) dmae) + i));
328 REG_WR(sc, dmae_reg_go_c[idx], 1);
331 uint32_t bnx2x_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type)
333 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
334 DMAE_COMMAND_C_TYPE_ENABLE);
337 uint32_t bnx2x_dmae_opcode_clr_src_reset(uint32_t opcode)
339 return opcode & ~DMAE_COMMAND_SRC_RESET;
343 bnx2x_dmae_opcode(struct bnx2x_softc * sc, uint8_t src_type, uint8_t dst_type,
344 uint8_t with_comp, uint8_t comp_type)
348 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
349 (dst_type << DMAE_COMMAND_DST_SHIFT));
351 opcode |= (DMAE_COMMAND_SRC_RESET | DMAE_COMMAND_DST_RESET);
353 opcode |= (SC_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
355 opcode |= ((SC_VN(sc) << DMAE_COMMAND_E1HVN_SHIFT) |
356 (SC_VN(sc) << DMAE_COMMAND_DST_VN_SHIFT));
358 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
361 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
363 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
367 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
374 bnx2x_prep_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae,
375 uint8_t src_type, uint8_t dst_type)
377 memset(dmae, 0, sizeof(struct dmae_command));
380 dmae->opcode = bnx2x_dmae_opcode(sc, src_type, dst_type,
381 TRUE, DMAE_COMP_PCI);
383 /* fill in the completion parameters */
384 dmae->comp_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_comp));
385 dmae->comp_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_comp));
386 dmae->comp_val = DMAE_COMP_VAL;
389 /* issue a DMAE command over the init channel and wait for completion */
391 bnx2x_issue_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae)
393 uint32_t *wb_comp = BNX2X_SP(sc, wb_comp);
394 int timeout = CHIP_REV_IS_SLOW(sc) ? 400000 : 4000;
396 /* reset completion */
399 /* post the command on the channel used for initializations */
400 bnx2x_post_dmae(sc, dmae, INIT_DMAE_C(sc));
402 /* wait for completion */
405 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
407 (sc->recovery_state != BNX2X_RECOVERY_DONE &&
408 sc->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
409 PMD_DRV_LOG(INFO, sc, "DMAE timeout!");
417 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
418 PMD_DRV_LOG(INFO, sc, "DMAE PCI error!");
419 return DMAE_PCI_ERROR;
425 void bnx2x_read_dmae(struct bnx2x_softc *sc, uint32_t src_addr, uint32_t len32)
427 struct dmae_command dmae;
432 if (!sc->dmae_ready) {
433 data = BNX2X_SP(sc, wb_data[0]);
435 for (i = 0; i < len32; i++) {
436 data[i] = REG_RD(sc, (src_addr + (i * 4)));
442 /* set opcode and fixed command fields */
443 bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
445 /* fill in addresses and len */
446 dmae.src_addr_lo = (src_addr >> 2); /* GRC addr has dword resolution */
447 dmae.src_addr_hi = 0;
448 dmae.dst_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_data));
449 dmae.dst_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_data));
452 /* issue the command and wait for completion */
453 if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
454 rte_panic("DMAE failed (%d)", rc);
459 bnx2x_write_dmae(struct bnx2x_softc *sc, rte_iova_t dma_addr, uint32_t dst_addr,
462 struct dmae_command dmae;
465 if (!sc->dmae_ready) {
466 ecore_init_str_wr(sc, dst_addr, BNX2X_SP(sc, wb_data[0]), len32);
470 /* set opcode and fixed command fields */
471 bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
473 /* fill in addresses and len */
474 dmae.src_addr_lo = U64_LO(dma_addr);
475 dmae.src_addr_hi = U64_HI(dma_addr);
476 dmae.dst_addr_lo = (dst_addr >> 2); /* GRC addr has dword resolution */
477 dmae.dst_addr_hi = 0;
480 /* issue the command and wait for completion */
481 if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
482 rte_panic("DMAE failed (%d)", rc);
487 bnx2x_write_dmae_phys_len(struct bnx2x_softc *sc, rte_iova_t phys_addr,
488 uint32_t addr, uint32_t len)
490 uint32_t dmae_wr_max = DMAE_LEN32_WR_MAX(sc);
493 while (len > dmae_wr_max) {
494 bnx2x_write_dmae(sc, (phys_addr + offset), /* src DMA address */
495 (addr + offset), /* dst GRC address */
497 offset += (dmae_wr_max * 4);
501 bnx2x_write_dmae(sc, (phys_addr + offset), /* src DMA address */
502 (addr + offset), /* dst GRC address */
507 bnx2x_set_ctx_validation(struct bnx2x_softc *sc, struct eth_context *cxt,
510 /* ustorm cxt validation */
511 cxt->ustorm_ag_context.cdu_usage =
512 CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
513 CDU_REGION_NUMBER_UCM_AG,
514 ETH_CONNECTION_TYPE);
515 /* xcontext validation */
516 cxt->xstorm_ag_context.cdu_reserved =
517 CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
518 CDU_REGION_NUMBER_XCM_AG,
519 ETH_CONNECTION_TYPE);
523 bnx2x_storm_memset_hc_timeout(struct bnx2x_softc *sc, uint8_t fw_sb_id,
524 uint8_t sb_index, uint8_t ticks)
527 (BAR_CSTRORM_INTMEM +
528 CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(fw_sb_id, sb_index));
530 REG_WR8(sc, addr, ticks);
534 bnx2x_storm_memset_hc_disable(struct bnx2x_softc *sc, uint16_t fw_sb_id,
535 uint8_t sb_index, uint8_t disable)
537 uint32_t enable_flag =
538 (disable) ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
540 (BAR_CSTRORM_INTMEM +
541 CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(fw_sb_id, sb_index));
545 flags = REG_RD8(sc, addr);
546 flags &= ~HC_INDEX_DATA_HC_ENABLED;
547 flags |= enable_flag;
548 REG_WR8(sc, addr, flags);
552 bnx2x_update_coalesce_sb_index(struct bnx2x_softc *sc, uint8_t fw_sb_id,
553 uint8_t sb_index, uint8_t disable, uint16_t usec)
555 uint8_t ticks = (usec / 4);
557 bnx2x_storm_memset_hc_timeout(sc, fw_sb_id, sb_index, ticks);
559 disable = (disable) ? 1 : ((usec) ? 0 : 1);
560 bnx2x_storm_memset_hc_disable(sc, fw_sb_id, sb_index, disable);
563 uint32_t elink_cb_reg_read(struct bnx2x_softc *sc, uint32_t reg_addr)
565 return REG_RD(sc, reg_addr);
568 void elink_cb_reg_write(struct bnx2x_softc *sc, uint32_t reg_addr, uint32_t val)
570 REG_WR(sc, reg_addr, val);
574 elink_cb_event_log(__rte_unused struct bnx2x_softc *sc,
575 __rte_unused const elink_log_id_t elink_log_id, ...)
577 PMD_DRV_LOG(DEBUG, sc, "ELINK EVENT LOG (%d)", elink_log_id);
580 static int bnx2x_set_spio(struct bnx2x_softc *sc, int spio, uint32_t mode)
584 /* Only 2 SPIOs are configurable */
585 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
586 PMD_DRV_LOG(NOTICE, sc, "Invalid SPIO 0x%x", spio);
590 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
592 /* read SPIO and mask except the float bits */
593 spio_reg = (REG_RD(sc, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
596 case MISC_SPIO_OUTPUT_LOW:
597 /* clear FLOAT and set CLR */
598 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
599 spio_reg |= (spio << MISC_SPIO_CLR_POS);
602 case MISC_SPIO_OUTPUT_HIGH:
603 /* clear FLOAT and set SET */
604 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
605 spio_reg |= (spio << MISC_SPIO_SET_POS);
608 case MISC_SPIO_INPUT_HI_Z:
610 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
617 REG_WR(sc, MISC_REG_SPIO, spio_reg);
618 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
623 static int bnx2x_gpio_read(struct bnx2x_softc *sc, int gpio_num, uint8_t port)
625 /* The GPIO should be swapped if swap register is set and active */
626 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
627 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
628 int gpio_shift = gpio_num;
630 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
632 uint32_t gpio_mask = (1 << gpio_shift);
635 if (gpio_num > MISC_REGISTERS_GPIO_3) {
636 PMD_DRV_LOG(NOTICE, sc, "Invalid GPIO %d", gpio_num);
640 /* read GPIO value */
641 gpio_reg = REG_RD(sc, MISC_REG_GPIO);
643 /* get the requested pin value */
644 return ((gpio_reg & gpio_mask) == gpio_mask) ? 1 : 0;
648 bnx2x_gpio_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode, uint8_t port)
650 /* The GPIO should be swapped if swap register is set and active */
651 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
652 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
653 int gpio_shift = gpio_num;
655 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
657 uint32_t gpio_mask = (1 << gpio_shift);
660 if (gpio_num > MISC_REGISTERS_GPIO_3) {
661 PMD_DRV_LOG(NOTICE, sc, "Invalid GPIO %d", gpio_num);
665 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
667 /* read GPIO and mask except the float bits */
668 gpio_reg = (REG_RD(sc, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
671 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
672 /* clear FLOAT and set CLR */
673 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
674 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
677 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
678 /* clear FLOAT and set SET */
679 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
680 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
683 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
685 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
692 REG_WR(sc, MISC_REG_GPIO, gpio_reg);
693 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
699 bnx2x_gpio_mult_write(struct bnx2x_softc *sc, uint8_t pins, uint32_t mode)
703 /* any port swapping should be handled by caller */
705 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
707 /* read GPIO and mask except the float bits */
708 gpio_reg = REG_RD(sc, MISC_REG_GPIO);
709 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
710 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
711 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
714 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
716 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
719 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
721 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
724 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
726 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
730 PMD_DRV_LOG(NOTICE, sc,
731 "Invalid GPIO mode assignment %d", mode);
732 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
736 REG_WR(sc, MISC_REG_GPIO, gpio_reg);
737 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
743 bnx2x_gpio_int_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode,
746 /* The GPIO should be swapped if swap register is set and active */
747 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
748 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
749 int gpio_shift = gpio_num;
751 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
753 uint32_t gpio_mask = (1 << gpio_shift);
756 if (gpio_num > MISC_REGISTERS_GPIO_3) {
757 PMD_DRV_LOG(NOTICE, sc, "Invalid GPIO %d", gpio_num);
761 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
764 gpio_reg = REG_RD(sc, MISC_REG_GPIO_INT);
767 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
768 /* clear SET and set CLR */
769 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
770 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
773 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
774 /* clear CLR and set SET */
775 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
776 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
783 REG_WR(sc, MISC_REG_GPIO_INT, gpio_reg);
784 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
790 elink_cb_gpio_read(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t port)
792 return bnx2x_gpio_read(sc, gpio_num, port);
795 uint8_t elink_cb_gpio_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode, /* 0=low 1=high */
798 return bnx2x_gpio_write(sc, gpio_num, mode, port);
802 elink_cb_gpio_mult_write(struct bnx2x_softc * sc, uint8_t pins,
803 uint8_t mode /* 0=low 1=high */ )
805 return bnx2x_gpio_mult_write(sc, pins, mode);
808 uint8_t elink_cb_gpio_int_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode, /* 0=low 1=high */
811 return bnx2x_gpio_int_write(sc, gpio_num, mode, port);
814 void elink_cb_notify_link_changed(struct bnx2x_softc *sc)
816 REG_WR(sc, (MISC_REG_AEU_GENERAL_ATTN_12 +
817 (SC_FUNC(sc) * sizeof(uint32_t))), 1);
820 /* send the MCP a request, block until there is a reply */
822 elink_cb_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
824 int mb_idx = SC_FW_MB_IDX(sc);
828 uint8_t delay = CHIP_REV_IS_SLOW(sc) ? 100 : 10;
831 SHMEM_WR(sc, func_mb[mb_idx].drv_mb_param, param);
832 SHMEM_WR(sc, func_mb[mb_idx].drv_mb_header, (command | seq));
834 PMD_DRV_LOG(DEBUG, sc,
835 "wrote command 0x%08x to FW MB param 0x%08x",
836 (command | seq), param);
838 /* Let the FW do it's magic. GIve it up to 5 seconds... */
841 rc = SHMEM_RD(sc, func_mb[mb_idx].fw_mb_header);
842 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
844 /* is this a reply to our command? */
845 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) {
846 rc &= FW_MSG_CODE_MASK;
849 PMD_DRV_LOG(NOTICE, sc, "FW failed to respond!");
857 bnx2x_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
859 return elink_cb_fw_command(sc, command, param);
863 __storm_memset_dma_mapping(struct bnx2x_softc *sc, uint32_t addr,
866 REG_WR(sc, addr, U64_LO(mapping));
867 REG_WR(sc, (addr + 4), U64_HI(mapping));
871 storm_memset_spq_addr(struct bnx2x_softc *sc, rte_iova_t mapping,
874 uint32_t addr = (XSEM_REG_FAST_MEMORY +
875 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid));
876 __storm_memset_dma_mapping(sc, addr, mapping);
880 storm_memset_vf_to_pf(struct bnx2x_softc *sc, uint16_t abs_fid, uint16_t pf_id)
882 REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid)),
884 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid)),
886 REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid)),
888 REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid)),
893 storm_memset_func_en(struct bnx2x_softc *sc, uint16_t abs_fid, uint8_t enable)
895 REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid)),
897 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid)),
899 REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid)),
901 REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid)),
906 storm_memset_eq_data(struct bnx2x_softc *sc, struct event_ring_data *eq_data,
912 addr = (BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid));
913 size = sizeof(struct event_ring_data);
914 ecore_storm_memset_struct(sc, addr, size, (uint32_t *) eq_data);
918 storm_memset_eq_prod(struct bnx2x_softc *sc, uint16_t eq_prod, uint16_t pfid)
920 uint32_t addr = (BAR_CSTRORM_INTMEM +
921 CSTORM_EVENT_RING_PROD_OFFSET(pfid));
922 REG_WR16(sc, addr, eq_prod);
926 * Post a slowpath command.
928 * A slowpath command is used to propagate a configuration change through
929 * the controller in a controlled manner, allowing each STORM processor and
930 * other H/W blocks to phase in the change. The commands sent on the
931 * slowpath are referred to as ramrods. Depending on the ramrod used the
932 * completion of the ramrod will occur in different ways. Here's a
933 * breakdown of ramrods and how they complete:
935 * RAMROD_CMD_ID_ETH_PORT_SETUP
936 * Used to setup the leading connection on a port. Completes on the
937 * Receive Completion Queue (RCQ) of that port (typically fp[0]).
939 * RAMROD_CMD_ID_ETH_CLIENT_SETUP
940 * Used to setup an additional connection on a port. Completes on the
941 * RCQ of the multi-queue/RSS connection being initialized.
943 * RAMROD_CMD_ID_ETH_STAT_QUERY
944 * Used to force the storm processors to update the statistics database
945 * in host memory. This ramrod is send on the leading connection CID and
946 * completes as an index increment of the CSTORM on the default status
949 * RAMROD_CMD_ID_ETH_UPDATE
950 * Used to update the state of the leading connection, usually to udpate
951 * the RSS indirection table. Completes on the RCQ of the leading
952 * connection. (Not currently used under FreeBSD until OS support becomes
955 * RAMROD_CMD_ID_ETH_HALT
956 * Used when tearing down a connection prior to driver unload. Completes
957 * on the RCQ of the multi-queue/RSS connection being torn down. Don't
958 * use this on the leading connection.
960 * RAMROD_CMD_ID_ETH_SET_MAC
961 * Sets the Unicast/Broadcast/Multicast used by the port. Completes on
962 * the RCQ of the leading connection.
964 * RAMROD_CMD_ID_ETH_CFC_DEL
965 * Used when tearing down a conneciton prior to driver unload. Completes
966 * on the RCQ of the leading connection (since the current connection
967 * has been completely removed from controller memory).
969 * RAMROD_CMD_ID_ETH_PORT_DEL
970 * Used to tear down the leading connection prior to driver unload,
971 * typically fp[0]. Completes as an index increment of the CSTORM on the
972 * default status block.
974 * RAMROD_CMD_ID_ETH_FORWARD_SETUP
975 * Used for connection offload. Completes on the RCQ of the multi-queue
976 * RSS connection that is being offloaded. (Not currently used under
979 * There can only be one command pending per function.
982 * 0 = Success, !0 = Failure.
985 /* must be called under the spq lock */
986 static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x_softc *sc)
988 struct eth_spe *next_spe = sc->spq_prod_bd;
990 if (sc->spq_prod_bd == sc->spq_last_bd) {
991 /* wrap back to the first eth_spq */
992 sc->spq_prod_bd = sc->spq;
993 sc->spq_prod_idx = 0;
1002 /* must be called under the spq lock */
1003 static void bnx2x_sp_prod_update(struct bnx2x_softc *sc)
1005 int func = SC_FUNC(sc);
1008 * Make sure that BD data is updated before writing the producer.
1009 * BD data is written to the memory, the producer is read from the
1010 * memory, thus we need a full memory barrier to ensure the ordering.
1014 REG_WR16(sc, (BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func)),
1021 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
1023 * @cmd: command to check
1024 * @cmd_type: command type
1026 static int bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
1028 if ((cmd_type == NONE_CONNECTION_TYPE) ||
1029 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
1030 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
1031 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
1032 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
1033 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
1034 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) {
1042 * bnx2x_sp_post - place a single command on an SP ring
1044 * @sc: driver handle
1045 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
1046 * @cid: SW CID the command is related to
1047 * @data_hi: command private data address (high 32 bits)
1048 * @data_lo: command private data address (low 32 bits)
1049 * @cmd_type: command type (e.g. NONE, ETH)
1051 * SP data is handled as if it's always an address pair, thus data fields are
1052 * not swapped to little endian in upper functions. Instead this function swaps
1053 * data as if it's two uint32 fields.
1056 bnx2x_sp_post(struct bnx2x_softc *sc, int command, int cid, uint32_t data_hi,
1057 uint32_t data_lo, int cmd_type)
1059 struct eth_spe *spe;
1063 common = bnx2x_is_contextless_ramrod(command, cmd_type);
1066 if (!atomic_load_acq_long(&sc->eq_spq_left)) {
1067 PMD_DRV_LOG(INFO, sc, "EQ ring is full!");
1071 if (!atomic_load_acq_long(&sc->cq_spq_left)) {
1072 PMD_DRV_LOG(INFO, sc, "SPQ ring is full!");
1077 spe = bnx2x_sp_get_next(sc);
1079 /* CID needs port number to be encoded int it */
1080 spe->hdr.conn_and_cmd_data =
1081 htole32((command << SPE_HDR_CMD_ID_SHIFT) | HW_CID(sc, cid));
1083 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
1085 /* TBD: Check if it works for VFs */
1086 type |= ((SC_FUNC(sc) << SPE_HDR_FUNCTION_ID_SHIFT) &
1087 SPE_HDR_FUNCTION_ID);
1089 spe->hdr.type = htole16(type);
1091 spe->data.update_data_addr.hi = htole32(data_hi);
1092 spe->data.update_data_addr.lo = htole32(data_lo);
1095 * It's ok if the actual decrement is issued towards the memory
1096 * somewhere between the lock and unlock. Thus no more explict
1097 * memory barrier is needed.
1100 atomic_subtract_acq_long(&sc->eq_spq_left, 1);
1102 atomic_subtract_acq_long(&sc->cq_spq_left, 1);
1105 PMD_DRV_LOG(DEBUG, sc,
1106 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x"
1107 "data (%x:%x) type(0x%x) left (CQ, EQ) (%lx,%lx)",
1109 (uint32_t) U64_HI(sc->spq_dma.paddr),
1110 (uint32_t) (U64_LO(sc->spq_dma.paddr) +
1111 (uint8_t *) sc->spq_prod_bd -
1112 (uint8_t *) sc->spq), command, common,
1113 HW_CID(sc, cid), data_hi, data_lo, type,
1114 atomic_load_acq_long(&sc->cq_spq_left),
1115 atomic_load_acq_long(&sc->eq_spq_left));
1117 /* RAMROD completion is processed in bnx2x_intr_legacy()
1118 * which can run from different contexts.
1119 * Ask bnx2x_intr_intr() to process RAMROD
1120 * completion whenever it gets scheduled.
1122 rte_atomic32_set(&sc->scan_fp, 1);
1123 bnx2x_sp_prod_update(sc);
1128 static void bnx2x_drv_pulse(struct bnx2x_softc *sc)
1130 SHMEM_WR(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb,
1131 sc->fw_drv_pulse_wr_seq);
1134 static int bnx2x_tx_queue_has_work(const struct bnx2x_fastpath *fp)
1137 struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1139 if (unlikely(!txq)) {
1140 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1144 mb(); /* status block fields can change */
1145 hw_cons = le16toh(*fp->tx_cons_sb);
1146 return hw_cons != txq->tx_pkt_head;
1149 static uint8_t bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
1151 /* expand this for multi-cos if ever supported */
1152 return bnx2x_tx_queue_has_work(fp);
1155 static int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
1157 uint16_t rx_cq_cons_sb;
1158 struct bnx2x_rx_queue *rxq;
1159 rxq = fp->sc->rx_queues[fp->index];
1160 if (unlikely(!rxq)) {
1161 PMD_RX_LOG(ERR, "ERROR: RX queue is NULL");
1165 mb(); /* status block fields can change */
1166 rx_cq_cons_sb = le16toh(*fp->rx_cq_cons_sb);
1167 if (unlikely((rx_cq_cons_sb & MAX_RCQ_ENTRIES(rxq)) ==
1168 MAX_RCQ_ENTRIES(rxq)))
1170 return rxq->rx_cq_head != rx_cq_cons_sb;
1174 bnx2x_sp_event(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
1175 union eth_rx_cqe *rr_cqe)
1177 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1178 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1179 enum ecore_queue_cmd drv_cmd = ECORE_Q_CMD_MAX;
1180 struct ecore_queue_sp_obj *q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
1182 PMD_DRV_LOG(DEBUG, sc,
1183 "fp=%d cid=%d got ramrod #%d state is %x type is %d",
1184 fp->index, cid, command, sc->state,
1185 rr_cqe->ramrod_cqe.ramrod_type);
1188 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1189 PMD_DRV_LOG(DEBUG, sc, "got UPDATE ramrod. CID %d", cid);
1190 drv_cmd = ECORE_Q_CMD_UPDATE;
1193 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1194 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] setup ramrod", cid);
1195 drv_cmd = ECORE_Q_CMD_SETUP;
1198 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1199 PMD_DRV_LOG(DEBUG, sc,
1200 "got MULTI[%d] tx-only setup ramrod", cid);
1201 drv_cmd = ECORE_Q_CMD_SETUP_TX_ONLY;
1204 case (RAMROD_CMD_ID_ETH_HALT):
1205 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] halt ramrod", cid);
1206 drv_cmd = ECORE_Q_CMD_HALT;
1209 case (RAMROD_CMD_ID_ETH_TERMINATE):
1210 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] teminate ramrod", cid);
1211 drv_cmd = ECORE_Q_CMD_TERMINATE;
1214 case (RAMROD_CMD_ID_ETH_EMPTY):
1215 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] empty ramrod", cid);
1216 drv_cmd = ECORE_Q_CMD_EMPTY;
1220 PMD_DRV_LOG(DEBUG, sc,
1221 "ERROR: unexpected MC reply (%d)"
1222 "on fp[%d]", command, fp->index);
1226 if ((drv_cmd != ECORE_Q_CMD_MAX) &&
1227 q_obj->complete_cmd(sc, q_obj, drv_cmd)) {
1229 * q_obj->complete_cmd() failure means that this was
1230 * an unexpected completion.
1232 * In this case we don't want to increase the sc->spq_left
1233 * because apparently we haven't sent this command the first
1236 // rte_panic("Unexpected SP completion");
1240 atomic_add_acq_long(&sc->cq_spq_left, 1);
1242 PMD_DRV_LOG(DEBUG, sc, "sc->cq_spq_left 0x%lx",
1243 atomic_load_acq_long(&sc->cq_spq_left));
1246 static uint8_t bnx2x_rxeof(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
1248 struct bnx2x_rx_queue *rxq;
1249 uint16_t bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
1250 uint16_t hw_cq_cons, sw_cq_cons, sw_cq_prod;
1252 rxq = sc->rx_queues[fp->index];
1254 PMD_RX_LOG(ERR, "RX queue %d is NULL", fp->index);
1258 /* CQ "next element" is of the size of the regular element */
1259 hw_cq_cons = le16toh(*fp->rx_cq_cons_sb);
1260 if (unlikely((hw_cq_cons & USABLE_RCQ_ENTRIES_PER_PAGE) ==
1261 USABLE_RCQ_ENTRIES_PER_PAGE)) {
1265 bd_cons = rxq->rx_bd_head;
1266 bd_prod = rxq->rx_bd_tail;
1267 bd_prod_fw = bd_prod;
1268 sw_cq_cons = rxq->rx_cq_head;
1269 sw_cq_prod = rxq->rx_cq_tail;
1272 * Memory barrier necessary as speculative reads of the rx
1273 * buffer can be ahead of the index in the status block
1277 while (sw_cq_cons != hw_cq_cons) {
1278 union eth_rx_cqe *cqe;
1279 struct eth_fast_path_rx_cqe *cqe_fp;
1280 uint8_t cqe_fp_flags;
1281 enum eth_rx_cqe_type cqe_fp_type;
1283 comp_ring_cons = RCQ_ENTRY(sw_cq_cons, rxq);
1284 bd_prod = RX_BD(bd_prod, rxq);
1285 bd_cons = RX_BD(bd_cons, rxq);
1287 cqe = &rxq->cq_ring[comp_ring_cons];
1288 cqe_fp = &cqe->fast_path_cqe;
1289 cqe_fp_flags = cqe_fp->type_error_flags;
1290 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
1292 /* is this a slowpath msg? */
1293 if (CQE_TYPE_SLOW(cqe_fp_type)) {
1294 bnx2x_sp_event(sc, fp, cqe);
1298 /* is this an error packet? */
1299 if (unlikely(cqe_fp_flags &
1300 ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG)) {
1301 PMD_RX_LOG(DEBUG, "flags 0x%x rx packet %u",
1302 cqe_fp_flags, sw_cq_cons);
1306 PMD_RX_LOG(DEBUG, "Dropping fastpath called from attn poller!");
1309 bd_cons = NEXT_RX_BD(bd_cons);
1310 bd_prod = NEXT_RX_BD(bd_prod);
1311 bd_prod_fw = NEXT_RX_BD(bd_prod_fw);
1314 sw_cq_prod = NEXT_RCQ_IDX(sw_cq_prod);
1315 sw_cq_cons = NEXT_RCQ_IDX(sw_cq_cons);
1317 } /* while work to do */
1319 rxq->rx_bd_head = bd_cons;
1320 rxq->rx_bd_tail = bd_prod_fw;
1321 rxq->rx_cq_head = sw_cq_cons;
1322 rxq->rx_cq_tail = sw_cq_prod;
1324 /* Update producers */
1325 bnx2x_update_rx_prod(sc, fp, bd_prod_fw, sw_cq_prod);
1327 return sw_cq_cons != hw_cq_cons;
1331 bnx2x_free_tx_pkt(__rte_unused struct bnx2x_fastpath *fp, struct bnx2x_tx_queue *txq,
1332 uint16_t pkt_idx, uint16_t bd_idx)
1334 struct eth_tx_start_bd *tx_start_bd =
1335 &txq->tx_ring[TX_BD(bd_idx, txq)].start_bd;
1336 uint16_t nbd = rte_le_to_cpu_16(tx_start_bd->nbd);
1337 struct rte_mbuf *tx_mbuf = txq->sw_ring[TX_BD(pkt_idx, txq)];
1339 if (likely(tx_mbuf != NULL)) {
1340 rte_pktmbuf_free_seg(tx_mbuf);
1342 PMD_RX_LOG(ERR, "fp[%02d] lost mbuf %lu",
1343 fp->index, (unsigned long)TX_BD(pkt_idx, txq));
1346 txq->sw_ring[TX_BD(pkt_idx, txq)] = NULL;
1347 txq->nb_tx_avail += nbd;
1350 bd_idx = NEXT_TX_BD(bd_idx);
1355 /* processes transmit completions */
1356 uint8_t bnx2x_txeof(__rte_unused struct bnx2x_softc * sc, struct bnx2x_fastpath * fp)
1358 uint16_t bd_cons, hw_cons, sw_cons;
1359 __rte_unused uint16_t tx_bd_avail;
1361 struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1363 if (unlikely(!txq)) {
1364 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1368 bd_cons = txq->tx_bd_head;
1369 hw_cons = rte_le_to_cpu_16(*fp->tx_cons_sb);
1370 sw_cons = txq->tx_pkt_head;
1372 while (sw_cons != hw_cons) {
1373 bd_cons = bnx2x_free_tx_pkt(fp, txq, sw_cons, bd_cons);
1377 txq->tx_pkt_head = sw_cons;
1378 txq->tx_bd_head = bd_cons;
1380 tx_bd_avail = txq->nb_tx_avail;
1382 PMD_TX_LOG(DEBUG, "fp[%02d] avail=%u cons_sb=%u, "
1383 "pkt_head=%u pkt_tail=%u bd_head=%u bd_tail=%u",
1384 fp->index, tx_bd_avail, hw_cons,
1385 txq->tx_pkt_head, txq->tx_pkt_tail,
1386 txq->tx_bd_head, txq->tx_bd_tail);
1390 static void bnx2x_drain_tx_queues(struct bnx2x_softc *sc)
1392 struct bnx2x_fastpath *fp;
1395 /* wait until all TX fastpath tasks have completed */
1396 for (i = 0; i < sc->num_queues; i++) {
1401 while (bnx2x_has_tx_work(fp)) {
1402 bnx2x_txeof(sc, fp);
1406 "Timeout waiting for fp[%d] "
1407 "transmits to complete!", i);
1408 rte_panic("tx drain failure");
1422 bnx2x_del_all_macs(struct bnx2x_softc *sc, struct ecore_vlan_mac_obj *mac_obj,
1423 int mac_type, uint8_t wait_for_comp)
1425 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1428 /* wait for completion of requested */
1429 if (wait_for_comp) {
1430 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1433 /* Set the mac type of addresses we want to clear */
1434 bnx2x_set_bit(mac_type, &vlan_mac_flags);
1436 rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1438 PMD_DRV_LOG(ERR, sc, "Failed to delete MACs (%d)", rc);
1444 bnx2x_fill_accept_flags(struct bnx2x_softc *sc, uint32_t rx_mode,
1445 unsigned long *rx_accept_flags,
1446 unsigned long *tx_accept_flags)
1448 /* Clear the flags first */
1449 *rx_accept_flags = 0;
1450 *tx_accept_flags = 0;
1453 case BNX2X_RX_MODE_NONE:
1455 * 'drop all' supersedes any accept flags that may have been
1456 * passed to the function.
1460 case BNX2X_RX_MODE_NORMAL:
1461 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1462 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, rx_accept_flags);
1463 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1465 /* internal switching mode */
1466 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1467 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, tx_accept_flags);
1468 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1472 case BNX2X_RX_MODE_ALLMULTI:
1473 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1474 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1475 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1477 /* internal switching mode */
1478 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1479 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1480 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1484 case BNX2X_RX_MODE_ALLMULTI_PROMISC:
1485 case BNX2X_RX_MODE_PROMISC:
1487 * According to deffinition of SI mode, iface in promisc mode
1488 * should receive matched and unmatched (in resolution of port)
1491 bnx2x_set_bit(ECORE_ACCEPT_UNMATCHED, rx_accept_flags);
1492 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1493 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1494 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1496 /* internal switching mode */
1497 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1498 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1501 bnx2x_set_bit(ECORE_ACCEPT_ALL_UNICAST, tx_accept_flags);
1503 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1509 PMD_RX_LOG(ERR, "Unknown rx_mode (%d)", rx_mode);
1513 /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
1514 if (rx_mode != BNX2X_RX_MODE_NONE) {
1515 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, rx_accept_flags);
1516 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, tx_accept_flags);
1523 bnx2x_set_q_rx_mode(struct bnx2x_softc *sc, uint8_t cl_id,
1524 unsigned long rx_mode_flags,
1525 unsigned long rx_accept_flags,
1526 unsigned long tx_accept_flags, unsigned long ramrod_flags)
1528 struct ecore_rx_mode_ramrod_params ramrod_param;
1531 memset(&ramrod_param, 0, sizeof(ramrod_param));
1533 /* Prepare ramrod parameters */
1534 ramrod_param.cid = 0;
1535 ramrod_param.cl_id = cl_id;
1536 ramrod_param.rx_mode_obj = &sc->rx_mode_obj;
1537 ramrod_param.func_id = SC_FUNC(sc);
1539 ramrod_param.pstate = &sc->sp_state;
1540 ramrod_param.state = ECORE_FILTER_RX_MODE_PENDING;
1542 ramrod_param.rdata = BNX2X_SP(sc, rx_mode_rdata);
1543 ramrod_param.rdata_mapping =
1544 (rte_iova_t)BNX2X_SP_MAPPING(sc, rx_mode_rdata),
1545 bnx2x_set_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
1547 ramrod_param.ramrod_flags = ramrod_flags;
1548 ramrod_param.rx_mode_flags = rx_mode_flags;
1550 ramrod_param.rx_accept_flags = rx_accept_flags;
1551 ramrod_param.tx_accept_flags = tx_accept_flags;
1553 rc = ecore_config_rx_mode(sc, &ramrod_param);
1555 PMD_RX_LOG(ERR, "Set rx_mode %d failed", sc->rx_mode);
1562 int bnx2x_set_storm_rx_mode(struct bnx2x_softc *sc)
1564 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
1565 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
1568 rc = bnx2x_fill_accept_flags(sc, sc->rx_mode, &rx_accept_flags,
1574 bnx2x_set_bit(RAMROD_RX, &ramrod_flags);
1575 bnx2x_set_bit(RAMROD_TX, &ramrod_flags);
1576 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1578 return bnx2x_set_q_rx_mode(sc, sc->fp[0].cl_id, rx_mode_flags,
1579 rx_accept_flags, tx_accept_flags,
1583 /* returns the "mcp load_code" according to global load_count array */
1584 static int bnx2x_nic_load_no_mcp(struct bnx2x_softc *sc)
1586 int path = SC_PATH(sc);
1587 int port = SC_PORT(sc);
1589 PMD_DRV_LOG(INFO, sc, "NO MCP - load counts[%d] %d, %d, %d",
1590 path, load_count[path][0], load_count[path][1],
1591 load_count[path][2]);
1593 load_count[path][0]++;
1594 load_count[path][1 + port]++;
1595 PMD_DRV_LOG(INFO, sc, "NO MCP - new load counts[%d] %d, %d, %d",
1596 path, load_count[path][0], load_count[path][1],
1597 load_count[path][2]);
1598 if (load_count[path][0] == 1)
1599 return FW_MSG_CODE_DRV_LOAD_COMMON;
1600 else if (load_count[path][1 + port] == 1)
1601 return FW_MSG_CODE_DRV_LOAD_PORT;
1603 return FW_MSG_CODE_DRV_LOAD_FUNCTION;
1606 /* returns the "mcp load_code" according to global load_count array */
1607 static int bnx2x_nic_unload_no_mcp(struct bnx2x_softc *sc)
1609 int port = SC_PORT(sc);
1610 int path = SC_PATH(sc);
1612 PMD_DRV_LOG(INFO, sc, "NO MCP - load counts[%d] %d, %d, %d",
1613 path, load_count[path][0], load_count[path][1],
1614 load_count[path][2]);
1615 load_count[path][0]--;
1616 load_count[path][1 + port]--;
1617 PMD_DRV_LOG(INFO, sc, "NO MCP - new load counts[%d] %d, %d, %d",
1618 path, load_count[path][0], load_count[path][1],
1619 load_count[path][2]);
1620 if (load_count[path][0] == 0) {
1621 return FW_MSG_CODE_DRV_UNLOAD_COMMON;
1622 } else if (load_count[path][1 + port] == 0) {
1623 return FW_MSG_CODE_DRV_UNLOAD_PORT;
1625 return FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
1629 /* request unload mode from the MCP: COMMON, PORT or FUNCTION */
1630 static uint32_t bnx2x_send_unload_req(struct bnx2x_softc *sc, int unload_mode)
1632 uint32_t reset_code = 0;
1634 /* Select the UNLOAD request mode */
1635 if (unload_mode == UNLOAD_NORMAL) {
1636 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1638 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1641 /* Send the request to the MCP */
1642 if (!BNX2X_NOMCP(sc)) {
1643 reset_code = bnx2x_fw_command(sc, reset_code, 0);
1645 reset_code = bnx2x_nic_unload_no_mcp(sc);
1651 /* send UNLOAD_DONE command to the MCP */
1652 static void bnx2x_send_unload_done(struct bnx2x_softc *sc, uint8_t keep_link)
1654 uint32_t reset_param =
1655 keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
1657 /* Report UNLOAD_DONE to MCP */
1658 if (!BNX2X_NOMCP(sc)) {
1659 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
1663 static int bnx2x_func_wait_started(struct bnx2x_softc *sc)
1667 if (!sc->port.pmf) {
1672 * (assumption: No Attention from MCP at this stage)
1673 * PMF probably in the middle of TX disable/enable transaction
1674 * 1. Sync IRS for default SB
1675 * 2. Sync SP queue - this guarantees us that attention handling started
1676 * 3. Wait, that TX disable/enable transaction completes
1678 * 1+2 guarantee that if DCBX attention was scheduled it already changed
1679 * pending bit of transaction from STARTED-->TX_STOPPED, if we already
1680 * received completion for the transaction the state is TX_STOPPED.
1681 * State will return to STARTED after completion of TX_STOPPED-->STARTED
1685 while (ecore_func_get_state(sc, &sc->func_obj) !=
1686 ECORE_F_STATE_STARTED && tout--) {
1690 if (ecore_func_get_state(sc, &sc->func_obj) != ECORE_F_STATE_STARTED) {
1692 * Failed to complete the transaction in a "good way"
1693 * Force both transactions with CLR bit.
1695 struct ecore_func_state_params func_params = { NULL };
1697 PMD_DRV_LOG(NOTICE, sc, "Unexpected function state! "
1698 "Forcing STARTED-->TX_STOPPED-->STARTED");
1700 func_params.f_obj = &sc->func_obj;
1701 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1703 /* STARTED-->TX_STOPPED */
1704 func_params.cmd = ECORE_F_CMD_TX_STOP;
1705 ecore_func_state_change(sc, &func_params);
1707 /* TX_STOPPED-->STARTED */
1708 func_params.cmd = ECORE_F_CMD_TX_START;
1709 return ecore_func_state_change(sc, &func_params);
1715 static int bnx2x_stop_queue(struct bnx2x_softc *sc, int index)
1717 struct bnx2x_fastpath *fp = &sc->fp[index];
1718 struct ecore_queue_state_params q_params = { NULL };
1721 PMD_DRV_LOG(DEBUG, sc, "stopping queue %d cid %d", index, fp->index);
1723 q_params.q_obj = &sc->sp_objs[fp->index].q_obj;
1724 /* We want to wait for completion in this context */
1725 bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
1727 /* Stop the primary connection: */
1729 /* ...halt the connection */
1730 q_params.cmd = ECORE_Q_CMD_HALT;
1731 rc = ecore_queue_state_change(sc, &q_params);
1736 /* ...terminate the connection */
1737 q_params.cmd = ECORE_Q_CMD_TERMINATE;
1738 memset(&q_params.params.terminate, 0,
1739 sizeof(q_params.params.terminate));
1740 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
1741 rc = ecore_queue_state_change(sc, &q_params);
1746 /* ...delete cfc entry */
1747 q_params.cmd = ECORE_Q_CMD_CFC_DEL;
1748 memset(&q_params.params.cfc_del, 0, sizeof(q_params.params.cfc_del));
1749 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
1750 return ecore_queue_state_change(sc, &q_params);
1753 /* wait for the outstanding SP commands */
1754 static uint8_t bnx2x_wait_sp_comp(struct bnx2x_softc *sc, unsigned long mask)
1757 int tout = 5000; /* wait for 5 secs tops */
1761 if (!(atomic_load_acq_long(&sc->sp_state) & mask)) {
1770 tmp = atomic_load_acq_long(&sc->sp_state);
1772 PMD_DRV_LOG(INFO, sc, "Filtering completion timed out: "
1773 "sp_state 0x%lx, mask 0x%lx", tmp, mask);
1780 static int bnx2x_func_stop(struct bnx2x_softc *sc)
1782 struct ecore_func_state_params func_params = { NULL };
1785 /* prepare parameters for function state transitions */
1786 bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1787 func_params.f_obj = &sc->func_obj;
1788 func_params.cmd = ECORE_F_CMD_STOP;
1791 * Try to stop the function the 'good way'. If it fails (in case
1792 * of a parity error during bnx2x_chip_cleanup()) and we are
1793 * not in a debug mode, perform a state transaction in order to
1794 * enable further HW_RESET transaction.
1796 rc = ecore_func_state_change(sc, &func_params);
1798 PMD_DRV_LOG(NOTICE, sc, "FUNC_STOP ramrod failed. "
1799 "Running a dry transaction");
1800 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1801 return ecore_func_state_change(sc, &func_params);
1807 static int bnx2x_reset_hw(struct bnx2x_softc *sc, uint32_t load_code)
1809 struct ecore_func_state_params func_params = { NULL };
1811 /* Prepare parameters for function state transitions */
1812 bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1814 func_params.f_obj = &sc->func_obj;
1815 func_params.cmd = ECORE_F_CMD_HW_RESET;
1817 func_params.params.hw_init.load_phase = load_code;
1819 return ecore_func_state_change(sc, &func_params);
1822 static void bnx2x_int_disable_sync(struct bnx2x_softc *sc, int disable_hw)
1825 /* prevent the HW from sending interrupts */
1826 bnx2x_int_disable(sc);
1831 bnx2x_chip_cleanup(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1833 int port = SC_PORT(sc);
1834 struct ecore_mcast_ramrod_params rparam = { NULL };
1835 uint32_t reset_code;
1838 bnx2x_drain_tx_queues(sc);
1840 /* give HW time to discard old tx messages */
1843 /* Clean all ETH MACs */
1844 rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_ETH_MAC,
1847 PMD_DRV_LOG(NOTICE, sc,
1848 "Failed to delete all ETH MACs (%d)", rc);
1851 /* Clean up UC list */
1852 rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_UC_LIST_MAC,
1855 PMD_DRV_LOG(NOTICE, sc,
1856 "Failed to delete UC MACs list (%d)", rc);
1860 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
1862 /* Set "drop all" to stop Rx */
1865 * We need to take the if_maddr_lock() here in order to prevent
1866 * a race between the completion code and this code.
1869 if (bnx2x_test_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) {
1870 bnx2x_set_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state);
1872 bnx2x_set_storm_rx_mode(sc);
1875 /* Clean up multicast configuration */
1876 rparam.mcast_obj = &sc->mcast_obj;
1877 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1879 PMD_DRV_LOG(NOTICE, sc,
1880 "Failed to send DEL MCAST command (%d)", rc);
1884 * Send the UNLOAD_REQUEST to the MCP. This will return if
1885 * this function should perform FUNCTION, PORT, or COMMON HW
1888 reset_code = bnx2x_send_unload_req(sc, unload_mode);
1891 * (assumption: No Attention from MCP at this stage)
1892 * PMF probably in the middle of TX disable/enable transaction
1894 rc = bnx2x_func_wait_started(sc);
1896 PMD_DRV_LOG(NOTICE, sc, "bnx2x_func_wait_started failed");
1900 * Close multi and leading connections
1901 * Completions for ramrods are collected in a synchronous way
1903 for (i = 0; i < sc->num_queues; i++) {
1904 if (bnx2x_stop_queue(sc, i)) {
1910 * If SP settings didn't get completed so far - something
1911 * very wrong has happen.
1913 if (!bnx2x_wait_sp_comp(sc, ~0x0UL)) {
1914 PMD_DRV_LOG(NOTICE, sc, "Common slow path ramrods got stuck!");
1919 rc = bnx2x_func_stop(sc);
1921 PMD_DRV_LOG(NOTICE, sc, "Function stop failed!");
1924 /* disable HW interrupts */
1925 bnx2x_int_disable_sync(sc, TRUE);
1927 /* Reset the chip */
1928 rc = bnx2x_reset_hw(sc, reset_code);
1930 PMD_DRV_LOG(NOTICE, sc, "Hardware reset failed");
1933 /* Report UNLOAD_DONE to MCP */
1934 bnx2x_send_unload_done(sc, keep_link);
1937 static void bnx2x_disable_close_the_gate(struct bnx2x_softc *sc)
1941 PMD_DRV_LOG(DEBUG, sc, "Disabling 'close the gates'");
1943 val = REG_RD(sc, MISC_REG_AEU_GENERAL_MASK);
1944 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
1945 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
1946 REG_WR(sc, MISC_REG_AEU_GENERAL_MASK, val);
1950 * Cleans the object that have internal lists without sending
1951 * ramrods. Should be run when interrutps are disabled.
1953 static void bnx2x_squeeze_objects(struct bnx2x_softc *sc)
1955 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1956 struct ecore_mcast_ramrod_params rparam = { NULL };
1957 struct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj;
1960 /* Cleanup MACs' object first... */
1962 /* Wait for completion of requested */
1963 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1964 /* Perform a dry cleanup */
1965 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &ramrod_flags);
1967 /* Clean ETH primary MAC */
1968 bnx2x_set_bit(ECORE_ETH_MAC, &vlan_mac_flags);
1969 rc = mac_obj->delete_all(sc, &sc->sp_objs->mac_obj, &vlan_mac_flags,
1972 PMD_DRV_LOG(NOTICE, sc, "Failed to clean ETH MACs (%d)", rc);
1975 /* Cleanup UC list */
1977 bnx2x_set_bit(ECORE_UC_LIST_MAC, &vlan_mac_flags);
1978 rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1980 PMD_DRV_LOG(NOTICE, sc,
1981 "Failed to clean UC list MACs (%d)", rc);
1984 /* Now clean mcast object... */
1986 rparam.mcast_obj = &sc->mcast_obj;
1987 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags);
1989 /* Add a DEL command... */
1990 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1992 PMD_DRV_LOG(NOTICE, sc,
1993 "Failed to send DEL MCAST command (%d)", rc);
1996 /* now wait until all pending commands are cleared */
1998 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
2001 PMD_DRV_LOG(NOTICE, sc,
2002 "Failed to clean MCAST object (%d)", rc);
2006 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
2010 /* stop the controller */
2013 bnx2x_nic_unload(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
2015 uint8_t global = FALSE;
2018 PMD_INIT_FUNC_TRACE(sc);
2020 PMD_DRV_LOG(DEBUG, sc, "Starting NIC unload...");
2022 /* mark driver as unloaded in shmem2 */
2023 if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
2024 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
2025 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
2026 val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
2029 if (IS_PF(sc) && sc->recovery_state != BNX2X_RECOVERY_DONE &&
2030 (sc->state == BNX2X_STATE_CLOSED || sc->state == BNX2X_STATE_ERROR)) {
2032 * We can get here if the driver has been unloaded
2033 * during parity error recovery and is either waiting for a
2034 * leader to complete or for other functions to unload and
2035 * then ifconfig down has been issued. In this case we want to
2036 * unload and let other functions to complete a recovery
2039 sc->recovery_state = BNX2X_RECOVERY_DONE;
2041 bnx2x_release_leader_lock(sc);
2044 PMD_DRV_LOG(NOTICE, sc, "Can't unload in closed or error state");
2049 * Nothing to do during unload if previous bnx2x_nic_load()
2050 * did not completed successfully - all resourses are released.
2052 if ((sc->state == BNX2X_STATE_CLOSED) || (sc->state == BNX2X_STATE_ERROR)) {
2056 sc->state = BNX2X_STATE_CLOSING_WAITING_HALT;
2059 sc->rx_mode = BNX2X_RX_MODE_NONE;
2060 bnx2x_set_rx_mode(sc);
2064 /* set ALWAYS_ALIVE bit in shmem */
2065 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2067 bnx2x_drv_pulse(sc);
2069 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2070 bnx2x_save_statistics(sc);
2073 /* wait till consumers catch up with producers in all queues */
2074 bnx2x_drain_tx_queues(sc);
2076 /* if VF indicate to PF this function is going down (PF will delete sp
2077 * elements and clear initializations
2080 bnx2x_vf_unload(sc);
2081 } else if (unload_mode != UNLOAD_RECOVERY) {
2082 /* if this is a normal/close unload need to clean up chip */
2083 bnx2x_chip_cleanup(sc, unload_mode, keep_link);
2085 /* Send the UNLOAD_REQUEST to the MCP */
2086 bnx2x_send_unload_req(sc, unload_mode);
2089 * Prevent transactions to host from the functions on the
2090 * engine that doesn't reset global blocks in case of global
2091 * attention once gloabl blocks are reset and gates are opened
2092 * (the engine which leader will perform the recovery
2095 if (!CHIP_IS_E1x(sc)) {
2096 bnx2x_pf_disable(sc);
2099 /* disable HW interrupts */
2100 bnx2x_int_disable_sync(sc, TRUE);
2102 /* Report UNLOAD_DONE to MCP */
2103 bnx2x_send_unload_done(sc, FALSE);
2107 * At this stage no more interrupts will arrive so we may safely clean
2108 * the queue'able objects here in case they failed to get cleaned so far.
2111 bnx2x_squeeze_objects(sc);
2114 /* There should be no more pending SP commands at this stage */
2123 bnx2x_free_fw_stats_mem(sc);
2125 sc->state = BNX2X_STATE_CLOSED;
2128 * Check if there are pending parity attentions. If there are - set
2129 * RECOVERY_IN_PROGRESS.
2131 if (IS_PF(sc) && bnx2x_chk_parity_attn(sc, &global, FALSE)) {
2132 bnx2x_set_reset_in_progress(sc);
2134 /* Set RESET_IS_GLOBAL if needed */
2136 bnx2x_set_reset_global(sc);
2141 * The last driver must disable a "close the gate" if there is no
2142 * parity attention or "process kill" pending.
2144 if (IS_PF(sc) && !bnx2x_clear_pf_load(sc) &&
2145 bnx2x_reset_is_done(sc, SC_PATH(sc))) {
2146 bnx2x_disable_close_the_gate(sc);
2149 PMD_DRV_LOG(DEBUG, sc, "Ended NIC unload");
2155 * Encapsulte an mbuf cluster into the tx bd chain and makes the memory
2156 * visible to the controller.
2158 * If an mbuf is submitted to this routine and cannot be given to the
2159 * controller (e.g. it has too many fragments) then the function may free
2160 * the mbuf and return to the caller.
2163 * int: Number of TX BDs used for the mbuf
2165 * Note the side effect that an mbuf may be freed if it causes a problem.
2167 int bnx2x_tx_encap(struct bnx2x_tx_queue *txq, struct rte_mbuf *m0)
2169 struct eth_tx_start_bd *tx_start_bd;
2170 uint16_t bd_prod, pkt_prod;
2171 struct bnx2x_softc *sc;
2175 bd_prod = txq->tx_bd_tail;
2176 pkt_prod = txq->tx_pkt_tail;
2178 txq->sw_ring[TX_BD(pkt_prod, txq)] = m0;
2180 tx_start_bd = &txq->tx_ring[TX_BD(bd_prod, txq)].start_bd;
2183 rte_cpu_to_le_64(rte_mbuf_data_iova(m0));
2184 tx_start_bd->nbytes = rte_cpu_to_le_16(m0->data_len);
2185 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2186 tx_start_bd->general_data =
2187 (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
2189 tx_start_bd->nbd = rte_cpu_to_le_16(2);
2191 if (m0->ol_flags & PKT_TX_VLAN_PKT) {
2192 tx_start_bd->vlan_or_ethertype =
2193 rte_cpu_to_le_16(m0->vlan_tci);
2194 tx_start_bd->bd_flags.as_bitfield |=
2195 (X_ETH_OUTBAND_VLAN <<
2196 ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT);
2199 tx_start_bd->vlan_or_ethertype =
2200 rte_cpu_to_le_16(pkt_prod);
2202 struct rte_ether_hdr *eh =
2203 rte_pktmbuf_mtod(m0, struct rte_ether_hdr *);
2205 tx_start_bd->vlan_or_ethertype =
2206 rte_cpu_to_le_16(rte_be_to_cpu_16(eh->ether_type));
2210 bd_prod = NEXT_TX_BD(bd_prod);
2212 struct eth_tx_parse_bd_e2 *tx_parse_bd;
2213 const struct rte_ether_hdr *eh =
2214 rte_pktmbuf_mtod(m0, struct rte_ether_hdr *);
2215 uint8_t mac_type = UNICAST_ADDRESS;
2218 &txq->tx_ring[TX_BD(bd_prod, txq)].parse_bd_e2;
2219 if (rte_is_multicast_ether_addr(&eh->d_addr)) {
2220 if (rte_is_broadcast_ether_addr(&eh->d_addr))
2221 mac_type = BROADCAST_ADDRESS;
2223 mac_type = MULTICAST_ADDRESS;
2225 tx_parse_bd->parsing_data =
2226 (mac_type << ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT);
2228 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_hi,
2229 &eh->d_addr.addr_bytes[0], 2);
2230 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_mid,
2231 &eh->d_addr.addr_bytes[2], 2);
2232 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_lo,
2233 &eh->d_addr.addr_bytes[4], 2);
2234 rte_memcpy(&tx_parse_bd->data.mac_addr.src_hi,
2235 &eh->s_addr.addr_bytes[0], 2);
2236 rte_memcpy(&tx_parse_bd->data.mac_addr.src_mid,
2237 &eh->s_addr.addr_bytes[2], 2);
2238 rte_memcpy(&tx_parse_bd->data.mac_addr.src_lo,
2239 &eh->s_addr.addr_bytes[4], 2);
2241 tx_parse_bd->data.mac_addr.dst_hi =
2242 rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_hi);
2243 tx_parse_bd->data.mac_addr.dst_mid =
2244 rte_cpu_to_be_16(tx_parse_bd->data.
2246 tx_parse_bd->data.mac_addr.dst_lo =
2247 rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_lo);
2248 tx_parse_bd->data.mac_addr.src_hi =
2249 rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_hi);
2250 tx_parse_bd->data.mac_addr.src_mid =
2251 rte_cpu_to_be_16(tx_parse_bd->data.
2253 tx_parse_bd->data.mac_addr.src_lo =
2254 rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_lo);
2257 "PBD dst %x %x %x src %x %x %x p_data %x",
2258 tx_parse_bd->data.mac_addr.dst_hi,
2259 tx_parse_bd->data.mac_addr.dst_mid,
2260 tx_parse_bd->data.mac_addr.dst_lo,
2261 tx_parse_bd->data.mac_addr.src_hi,
2262 tx_parse_bd->data.mac_addr.src_mid,
2263 tx_parse_bd->data.mac_addr.src_lo,
2264 tx_parse_bd->parsing_data);
2268 "start bd: nbytes %d flags %x vlan %x",
2269 tx_start_bd->nbytes,
2270 tx_start_bd->bd_flags.as_bitfield,
2271 tx_start_bd->vlan_or_ethertype);
2273 bd_prod = NEXT_TX_BD(bd_prod);
2276 if (TX_IDX(bd_prod) < 2)
2279 txq->nb_tx_avail -= 2;
2280 txq->tx_bd_tail = bd_prod;
2281 txq->tx_pkt_tail = pkt_prod;
2286 static uint16_t bnx2x_cid_ilt_lines(struct bnx2x_softc *sc)
2288 return L2_ILT_LINES(sc);
2291 static void bnx2x_ilt_set_info(struct bnx2x_softc *sc)
2293 struct ilt_client_info *ilt_client;
2294 struct ecore_ilt *ilt = sc->ilt;
2297 PMD_INIT_FUNC_TRACE(sc);
2299 ilt->start_line = FUNC_ILT_BASE(SC_FUNC(sc));
2302 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
2303 ilt_client->client_num = ILT_CLIENT_CDU;
2304 ilt_client->page_size = CDU_ILT_PAGE_SZ;
2305 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
2306 ilt_client->start = line;
2307 line += bnx2x_cid_ilt_lines(sc);
2309 if (CNIC_SUPPORT(sc)) {
2310 line += CNIC_ILT_LINES;
2313 ilt_client->end = (line - 1);
2316 if (QM_INIT(sc->qm_cid_count)) {
2317 ilt_client = &ilt->clients[ILT_CLIENT_QM];
2318 ilt_client->client_num = ILT_CLIENT_QM;
2319 ilt_client->page_size = QM_ILT_PAGE_SZ;
2320 ilt_client->flags = 0;
2321 ilt_client->start = line;
2323 /* 4 bytes for each cid */
2324 line += DIV_ROUND_UP(sc->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
2327 ilt_client->end = (line - 1);
2330 if (CNIC_SUPPORT(sc)) {
2332 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
2333 ilt_client->client_num = ILT_CLIENT_SRC;
2334 ilt_client->page_size = SRC_ILT_PAGE_SZ;
2335 ilt_client->flags = 0;
2336 ilt_client->start = line;
2337 line += SRC_ILT_LINES;
2338 ilt_client->end = (line - 1);
2341 ilt_client = &ilt->clients[ILT_CLIENT_TM];
2342 ilt_client->client_num = ILT_CLIENT_TM;
2343 ilt_client->page_size = TM_ILT_PAGE_SZ;
2344 ilt_client->flags = 0;
2345 ilt_client->start = line;
2346 line += TM_ILT_LINES;
2347 ilt_client->end = (line - 1);
2350 assert((line <= ILT_MAX_LINES));
2353 static void bnx2x_set_fp_rx_buf_size(struct bnx2x_softc *sc)
2357 for (i = 0; i < sc->num_queues; i++) {
2358 /* get the Rx buffer size for RX frames */
2359 sc->fp[i].rx_buf_size =
2360 (IP_HEADER_ALIGNMENT_PADDING + ETH_OVERHEAD + sc->mtu);
2364 int bnx2x_alloc_ilt_mem(struct bnx2x_softc *sc)
2367 sc->ilt = rte_malloc("", sizeof(struct ecore_ilt), RTE_CACHE_LINE_SIZE);
2369 return sc->ilt == NULL;
2372 static int bnx2x_alloc_ilt_lines_mem(struct bnx2x_softc *sc)
2374 sc->ilt->lines = rte_calloc("",
2375 sizeof(struct ilt_line), ILT_MAX_LINES,
2376 RTE_CACHE_LINE_SIZE);
2377 return sc->ilt->lines == NULL;
2380 void bnx2x_free_ilt_mem(struct bnx2x_softc *sc)
2386 static void bnx2x_free_ilt_lines_mem(struct bnx2x_softc *sc)
2388 if (sc->ilt->lines != NULL) {
2389 rte_free(sc->ilt->lines);
2390 sc->ilt->lines = NULL;
2394 static void bnx2x_free_mem(struct bnx2x_softc *sc)
2398 for (i = 0; i < L2_ILT_LINES(sc); i++) {
2399 sc->context[i].vcxt = NULL;
2400 sc->context[i].size = 0;
2403 ecore_ilt_mem_op(sc, ILT_MEMOP_FREE);
2405 bnx2x_free_ilt_lines_mem(sc);
2407 /* free the host hardware/software hsi structures */
2408 bnx2x_free_hsi_mem(sc);
2411 static int bnx2x_alloc_mem(struct bnx2x_softc *sc)
2416 char cdu_name[RTE_MEMZONE_NAMESIZE];
2419 * Allocate memory for CDU context:
2420 * This memory is allocated separately and not in the generic ILT
2421 * functions because CDU differs in few aspects:
2422 * 1. There can be multiple entities allocating memory for context -
2423 * regular L2, CNIC, and SRIOV drivers. Each separately controls
2424 * its own ILT lines.
2425 * 2. Since CDU page-size is not a single 4KB page (which is the case
2426 * for the other ILT clients), to be efficient we want to support
2427 * allocation of sub-page-size in the last entry.
2428 * 3. Context pointers are used by the driver to pass to FW / update
2429 * the context (for the other ILT clients the pointers are used just to
2430 * free the memory during unload).
2432 context_size = (sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(sc));
2433 for (i = 0, allocated = 0; allocated < context_size; i++) {
2434 sc->context[i].size = min(CDU_ILT_PAGE_SZ,
2435 (context_size - allocated));
2437 snprintf(cdu_name, sizeof(cdu_name), "cdu_%d", i);
2438 if (bnx2x_dma_alloc(sc, sc->context[i].size,
2439 &sc->context[i].vcxt_dma,
2440 cdu_name, BNX2X_PAGE_SIZE) != 0) {
2445 sc->context[i].vcxt =
2446 (union cdu_context *)sc->context[i].vcxt_dma.vaddr;
2448 allocated += sc->context[i].size;
2451 bnx2x_alloc_ilt_lines_mem(sc);
2453 if (ecore_ilt_mem_op(sc, ILT_MEMOP_ALLOC)) {
2454 PMD_DRV_LOG(NOTICE, sc, "ecore_ilt_mem_op ILT_MEMOP_ALLOC failed");
2459 /* allocate the host hardware/software hsi structures */
2460 if (bnx2x_alloc_hsi_mem(sc) != 0) {
2461 PMD_DRV_LOG(ERR, sc, "bnx2x_alloc_hsi_mem was failed");
2469 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc)
2471 bnx2x_dma_free(&sc->fw_stats_dma);
2472 sc->fw_stats_num = 0;
2474 sc->fw_stats_req_size = 0;
2475 sc->fw_stats_req = NULL;
2476 sc->fw_stats_req_mapping = 0;
2478 sc->fw_stats_data_size = 0;
2479 sc->fw_stats_data = NULL;
2480 sc->fw_stats_data_mapping = 0;
2483 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc)
2485 uint8_t num_queue_stats;
2486 int num_groups, vf_headroom = 0;
2488 /* number of queues for statistics is number of eth queues */
2489 num_queue_stats = BNX2X_NUM_ETH_QUEUES(sc);
2492 * Total number of FW statistics requests =
2493 * 1 for port stats + 1 for PF stats + num of queues
2495 sc->fw_stats_num = (2 + num_queue_stats);
2498 * Request is built from stats_query_header and an array of
2499 * stats_query_cmd_group each of which contains STATS_QUERY_CMD_COUNT
2500 * rules. The real number or requests is configured in the
2501 * stats_query_header.
2503 num_groups = (sc->fw_stats_num + vf_headroom) / STATS_QUERY_CMD_COUNT;
2504 if ((sc->fw_stats_num + vf_headroom) % STATS_QUERY_CMD_COUNT)
2507 sc->fw_stats_req_size =
2508 (sizeof(struct stats_query_header) +
2509 (num_groups * sizeof(struct stats_query_cmd_group)));
2512 * Data for statistics requests + stats_counter.
2513 * stats_counter holds per-STORM counters that are incremented when
2514 * STORM has finished with the current request. Memory for FCoE
2515 * offloaded statistics are counted anyway, even if they will not be sent.
2516 * VF stats are not accounted for here as the data of VF stats is stored
2517 * in memory allocated by the VF, not here.
2519 sc->fw_stats_data_size =
2520 (sizeof(struct stats_counter) +
2521 sizeof(struct per_port_stats) + sizeof(struct per_pf_stats) +
2522 /* sizeof(struct fcoe_statistics_params) + */
2523 (sizeof(struct per_queue_stats) * num_queue_stats));
2525 if (bnx2x_dma_alloc(sc, (sc->fw_stats_req_size + sc->fw_stats_data_size),
2526 &sc->fw_stats_dma, "fw_stats",
2527 RTE_CACHE_LINE_SIZE) != 0) {
2528 bnx2x_free_fw_stats_mem(sc);
2532 /* set up the shortcuts */
2534 sc->fw_stats_req = (struct bnx2x_fw_stats_req *)sc->fw_stats_dma.vaddr;
2535 sc->fw_stats_req_mapping = sc->fw_stats_dma.paddr;
2538 (struct bnx2x_fw_stats_data *)((uint8_t *) sc->fw_stats_dma.vaddr +
2539 sc->fw_stats_req_size);
2540 sc->fw_stats_data_mapping = (sc->fw_stats_dma.paddr +
2541 sc->fw_stats_req_size);
2548 * 0-7 - Engine0 load counter.
2549 * 8-15 - Engine1 load counter.
2550 * 16 - Engine0 RESET_IN_PROGRESS bit.
2551 * 17 - Engine1 RESET_IN_PROGRESS bit.
2552 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active
2553 * function on the engine
2554 * 19 - Engine1 ONE_IS_LOADED.
2555 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
2556 * leader to complete (check for both RESET_IN_PROGRESS bits and not
2557 * for just the one belonging to its engine).
2559 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
2560 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
2561 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
2562 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
2563 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
2564 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
2565 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
2566 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
2568 /* set the GLOBAL_RESET bit, should be run under rtnl lock */
2569 static void bnx2x_set_reset_global(struct bnx2x_softc *sc)
2572 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2573 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2574 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
2575 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2578 /* clear the GLOBAL_RESET bit, should be run under rtnl lock */
2579 static void bnx2x_clear_reset_global(struct bnx2x_softc *sc)
2582 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2583 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2584 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
2585 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2588 /* checks the GLOBAL_RESET bit, should be run under rtnl lock */
2589 static uint8_t bnx2x_reset_is_global(struct bnx2x_softc *sc)
2591 return REG_RD(sc, BNX2X_RECOVERY_GLOB_REG) & BNX2X_GLOBAL_RESET_BIT;
2594 /* clear RESET_IN_PROGRESS bit for the engine, should be run under rtnl lock */
2595 static void bnx2x_set_reset_done(struct bnx2x_softc *sc)
2598 uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2599 BNX2X_PATH0_RST_IN_PROG_BIT;
2601 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2603 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2606 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2608 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2611 /* set RESET_IN_PROGRESS for the engine, should be run under rtnl lock */
2612 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc)
2615 uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2616 BNX2X_PATH0_RST_IN_PROG_BIT;
2618 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2620 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2623 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2625 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2628 /* check RESET_IN_PROGRESS bit for an engine, should be run under rtnl lock */
2629 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine)
2631 uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2632 uint32_t bit = engine ? BNX2X_PATH1_RST_IN_PROG_BIT :
2633 BNX2X_PATH0_RST_IN_PROG_BIT;
2635 /* return false if bit is set */
2636 return (val & bit) ? FALSE : TRUE;
2639 /* get the load status for an engine, should be run under rtnl lock */
2640 static uint8_t bnx2x_get_load_status(struct bnx2x_softc *sc, int engine)
2642 uint32_t mask = engine ? BNX2X_PATH1_LOAD_CNT_MASK :
2643 BNX2X_PATH0_LOAD_CNT_MASK;
2644 uint32_t shift = engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2645 BNX2X_PATH0_LOAD_CNT_SHIFT;
2646 uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2648 val = ((val & mask) >> shift);
2653 /* set pf load mark */
2654 static void bnx2x_set_pf_load(struct bnx2x_softc *sc)
2658 uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2659 BNX2X_PATH0_LOAD_CNT_MASK;
2660 uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2661 BNX2X_PATH0_LOAD_CNT_SHIFT;
2663 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2665 PMD_INIT_FUNC_TRACE(sc);
2667 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2669 /* get the current counter value */
2670 val1 = ((val & mask) >> shift);
2672 /* set bit of this PF */
2673 val1 |= (1 << SC_ABS_FUNC(sc));
2675 /* clear the old value */
2678 /* set the new one */
2679 val |= ((val1 << shift) & mask);
2681 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2683 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2686 /* clear pf load mark */
2687 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc)
2690 uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2691 BNX2X_PATH0_LOAD_CNT_MASK;
2692 uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2693 BNX2X_PATH0_LOAD_CNT_SHIFT;
2695 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2696 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2698 /* get the current counter value */
2699 val1 = (val & mask) >> shift;
2701 /* clear bit of that PF */
2702 val1 &= ~(1 << SC_ABS_FUNC(sc));
2704 /* clear the old value */
2707 /* set the new one */
2708 val |= ((val1 << shift) & mask);
2710 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2711 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2715 /* send load requrest to mcp and analyze response */
2716 static int bnx2x_nic_load_request(struct bnx2x_softc *sc, uint32_t * load_code)
2718 PMD_INIT_FUNC_TRACE(sc);
2722 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
2723 DRV_MSG_SEQ_NUMBER_MASK);
2725 PMD_DRV_LOG(DEBUG, sc, "initial fw_seq 0x%04x", sc->fw_seq);
2728 /* get the current FW pulse sequence */
2729 sc->fw_drv_pulse_wr_seq =
2730 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb) &
2731 DRV_PULSE_SEQ_MASK);
2733 /* set ALWAYS_ALIVE bit in shmem */
2734 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2735 bnx2x_drv_pulse(sc);
2739 (*load_code) = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
2740 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
2742 /* if the MCP fails to respond we must abort */
2743 if (!(*load_code)) {
2744 PMD_DRV_LOG(NOTICE, sc, "MCP response failure!");
2748 /* if MCP refused then must abort */
2749 if ((*load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED) {
2750 PMD_DRV_LOG(NOTICE, sc, "MCP refused load request");
2758 * Check whether another PF has already loaded FW to chip. In virtualized
2759 * environments a pf from anoth VM may have already initialized the device
2760 * including loading FW.
2762 static int bnx2x_nic_load_analyze_req(struct bnx2x_softc *sc, uint32_t load_code)
2764 uint32_t my_fw, loaded_fw;
2766 /* is another pf loaded on this engine? */
2767 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
2768 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
2769 /* build my FW version dword */
2770 my_fw = (BNX2X_5710_FW_MAJOR_VERSION +
2771 (BNX2X_5710_FW_MINOR_VERSION << 8) +
2772 (BNX2X_5710_FW_REVISION_VERSION << 16) +
2773 (BNX2X_5710_FW_ENGINEERING_VERSION << 24));
2775 /* read loaded FW from chip */
2776 loaded_fw = REG_RD(sc, XSEM_REG_PRAM);
2777 PMD_DRV_LOG(DEBUG, sc, "loaded FW 0x%08x / my FW 0x%08x",
2780 /* abort nic load if version mismatch */
2781 if (my_fw != loaded_fw) {
2782 PMD_DRV_LOG(NOTICE, sc,
2783 "FW 0x%08x already loaded (mine is 0x%08x)",
2792 /* mark PMF if applicable */
2793 static void bnx2x_nic_load_pmf(struct bnx2x_softc *sc, uint32_t load_code)
2795 uint32_t ncsi_oem_data_addr;
2797 PMD_INIT_FUNC_TRACE(sc);
2799 if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
2800 (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
2801 (load_code == FW_MSG_CODE_DRV_LOAD_PORT)) {
2803 * Barrier here for ordering between the writing to sc->port.pmf here
2804 * and reading it from the periodic task.
2812 PMD_DRV_LOG(DEBUG, sc, "pmf %d", sc->port.pmf);
2814 if (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) {
2815 if (SHMEM2_HAS(sc, ncsi_oem_data_addr)) {
2816 ncsi_oem_data_addr = SHMEM2_RD(sc, ncsi_oem_data_addr);
2817 if (ncsi_oem_data_addr) {
2819 (ncsi_oem_data_addr +
2820 offsetof(struct glob_ncsi_oem_data,
2821 driver_version)), 0);
2827 static void bnx2x_read_mf_cfg(struct bnx2x_softc *sc)
2829 int n = (CHIP_IS_MODE_4_PORT(sc) ? 2 : 1);
2833 if (BNX2X_NOMCP(sc)) {
2834 return; /* what should be the default bvalue in this case */
2838 * The formula for computing the absolute function number is...
2839 * For 2 port configuration (4 functions per port):
2840 * abs_func = 2 * vn + SC_PORT + SC_PATH
2841 * For 4 port configuration (2 functions per port):
2842 * abs_func = 4 * vn + 2 * SC_PORT + SC_PATH
2844 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
2845 abs_func = (n * (2 * vn + SC_PORT(sc)) + SC_PATH(sc));
2846 if (abs_func >= E1H_FUNC_MAX) {
2849 sc->devinfo.mf_info.mf_config[vn] =
2850 MFCFG_RD(sc, func_mf_config[abs_func].config);
2853 if (sc->devinfo.mf_info.mf_config[SC_VN(sc)] &
2854 FUNC_MF_CFG_FUNC_DISABLED) {
2855 PMD_DRV_LOG(DEBUG, sc, "mf_cfg function disabled");
2856 sc->flags |= BNX2X_MF_FUNC_DIS;
2858 PMD_DRV_LOG(DEBUG, sc, "mf_cfg function enabled");
2859 sc->flags &= ~BNX2X_MF_FUNC_DIS;
2863 /* acquire split MCP access lock register */
2864 static int bnx2x_acquire_alr(struct bnx2x_softc *sc)
2868 for (j = 0; j < 1000; j++) {
2870 REG_WR(sc, GRCBASE_MCP + 0x9c, val);
2871 val = REG_RD(sc, GRCBASE_MCP + 0x9c);
2872 if (val & (1L << 31))
2878 if (!(val & (1L << 31))) {
2879 PMD_DRV_LOG(NOTICE, sc, "Cannot acquire MCP access lock register");
2886 /* release split MCP access lock register */
2887 static void bnx2x_release_alr(struct bnx2x_softc *sc)
2889 REG_WR(sc, GRCBASE_MCP + 0x9c, 0);
2892 static void bnx2x_fan_failure(struct bnx2x_softc *sc)
2894 int port = SC_PORT(sc);
2895 uint32_t ext_phy_config;
2897 /* mark the failure */
2899 SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
2901 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2902 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
2903 SHMEM_WR(sc, dev_info.port_hw_config[port].external_phy_config,
2906 /* log the failure */
2907 PMD_DRV_LOG(INFO, sc,
2908 "Fan Failure has caused the driver to shutdown "
2909 "the card to prevent permanent damage. "
2910 "Please contact OEM Support for assistance");
2912 rte_panic("Schedule task to handle fan failure");
2915 /* this function is called upon a link interrupt */
2916 static void bnx2x_link_attn(struct bnx2x_softc *sc)
2918 uint32_t pause_enabled = 0;
2919 struct host_port_stats *pstats;
2922 /* Make sure that we are synced with the current statistics */
2923 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2925 elink_link_update(&sc->link_params, &sc->link_vars);
2927 if (sc->link_vars.link_up) {
2929 /* dropless flow control */
2930 if (sc->dropless_fc) {
2933 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
2938 (BAR_USTRORM_INTMEM +
2939 USTORM_ETH_PAUSE_ENABLED_OFFSET(SC_PORT(sc))),
2943 if (sc->link_vars.mac_type != ELINK_MAC_TYPE_EMAC) {
2944 pstats = BNX2X_SP(sc, port_stats);
2945 /* reset old mac stats */
2946 memset(&(pstats->mac_stx[0]), 0,
2947 sizeof(struct mac_stx));
2950 if (sc->state == BNX2X_STATE_OPEN) {
2951 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
2955 if (sc->link_vars.link_up && sc->link_vars.line_speed) {
2956 cmng_fns = bnx2x_get_cmng_fns_mode(sc);
2958 if (cmng_fns != CMNG_FNS_NONE) {
2959 bnx2x_cmng_fns_init(sc, FALSE, cmng_fns);
2960 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
2964 bnx2x_link_report_locked(sc);
2967 bnx2x_link_sync_notify(sc);
2971 static void bnx2x_attn_int_asserted(struct bnx2x_softc *sc, uint32_t asserted)
2973 int port = SC_PORT(sc);
2974 uint32_t aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2975 MISC_REG_AEU_MASK_ATTN_FUNC_0;
2976 uint32_t nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2977 NIG_REG_MASK_INTERRUPT_PORT0;
2979 uint32_t nig_mask = 0;
2984 if (sc->attn_state & asserted) {
2985 PMD_DRV_LOG(ERR, sc, "IGU ERROR attn=0x%08x", asserted);
2988 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2990 aeu_mask = REG_RD(sc, aeu_addr);
2992 aeu_mask &= ~(asserted & 0x3ff);
2994 REG_WR(sc, aeu_addr, aeu_mask);
2996 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2998 sc->attn_state |= asserted;
3000 if (asserted & ATTN_HARD_WIRED_MASK) {
3001 if (asserted & ATTN_NIG_FOR_FUNC) {
3003 bnx2x_acquire_phy_lock(sc);
3004 /* save nig interrupt mask */
3005 nig_mask = REG_RD(sc, nig_int_mask_addr);
3007 /* If nig_mask is not set, no need to call the update function */
3009 REG_WR(sc, nig_int_mask_addr, 0);
3011 bnx2x_link_attn(sc);
3014 /* handle unicore attn? */
3017 if (asserted & ATTN_SW_TIMER_4_FUNC) {
3018 PMD_DRV_LOG(DEBUG, sc, "ATTN_SW_TIMER_4_FUNC!");
3021 if (asserted & GPIO_2_FUNC) {
3022 PMD_DRV_LOG(DEBUG, sc, "GPIO_2_FUNC!");
3025 if (asserted & GPIO_3_FUNC) {
3026 PMD_DRV_LOG(DEBUG, sc, "GPIO_3_FUNC!");
3029 if (asserted & GPIO_4_FUNC) {
3030 PMD_DRV_LOG(DEBUG, sc, "GPIO_4_FUNC!");
3034 if (asserted & ATTN_GENERAL_ATTN_1) {
3035 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_1!");
3036 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3038 if (asserted & ATTN_GENERAL_ATTN_2) {
3039 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_2!");
3040 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3042 if (asserted & ATTN_GENERAL_ATTN_3) {
3043 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_3!");
3044 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3047 if (asserted & ATTN_GENERAL_ATTN_4) {
3048 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_4!");
3049 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3051 if (asserted & ATTN_GENERAL_ATTN_5) {
3052 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_5!");
3053 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3055 if (asserted & ATTN_GENERAL_ATTN_6) {
3056 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_6!");
3057 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3062 if (sc->devinfo.int_block == INT_BLOCK_HC) {
3064 (HC_REG_COMMAND_REG + port * 32 +
3065 COMMAND_REG_ATTN_BITS_SET);
3067 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER * 8);
3070 PMD_DRV_LOG(DEBUG, sc, "about to mask 0x%08x at %s addr 0x%08x",
3072 (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
3074 REG_WR(sc, reg_addr, asserted);
3076 /* now set back the mask */
3077 if (asserted & ATTN_NIG_FOR_FUNC) {
3079 * Verify that IGU ack through BAR was written before restoring
3080 * NIG mask. This loop should exit after 2-3 iterations max.
3082 if (sc->devinfo.int_block != INT_BLOCK_HC) {
3087 REG_RD(sc, IGU_REG_ATTENTION_ACK_BITS);
3088 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0)
3089 && (++cnt < MAX_IGU_ATTN_ACK_TO));
3092 PMD_DRV_LOG(ERR, sc,
3093 "Failed to verify IGU ack on time");
3099 REG_WR(sc, nig_int_mask_addr, nig_mask);
3101 bnx2x_release_phy_lock(sc);
3106 bnx2x_print_next_block(__rte_unused struct bnx2x_softc *sc, __rte_unused int idx,
3107 __rte_unused const char *blk)
3109 PMD_DRV_LOG(INFO, sc, "%s%s", idx ? ", " : "", blk);
3113 bnx2x_check_blocks_with_parity0(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3116 uint32_t cur_bit = 0;
3119 for (i = 0; sig; i++) {
3120 cur_bit = ((uint32_t) 0x1 << i);
3121 if (sig & cur_bit) {
3123 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3125 bnx2x_print_next_block(sc, par_num++,
3128 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3130 bnx2x_print_next_block(sc, par_num++,
3133 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3135 bnx2x_print_next_block(sc, par_num++,
3138 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3140 bnx2x_print_next_block(sc, par_num++,
3143 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3145 bnx2x_print_next_block(sc, par_num++,
3148 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3150 bnx2x_print_next_block(sc, par_num++,
3153 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3155 bnx2x_print_next_block(sc, par_num++,
3169 bnx2x_check_blocks_with_parity1(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3170 uint8_t * global, uint8_t print)
3173 uint32_t cur_bit = 0;
3174 for (i = 0; sig; i++) {
3175 cur_bit = ((uint32_t) 0x1 << i);
3176 if (sig & cur_bit) {
3178 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3180 bnx2x_print_next_block(sc, par_num++,
3183 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3185 bnx2x_print_next_block(sc, par_num++,
3188 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3190 bnx2x_print_next_block(sc, par_num++,
3193 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3195 bnx2x_print_next_block(sc, par_num++,
3198 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
3200 bnx2x_print_next_block(sc, par_num++,
3203 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3205 bnx2x_print_next_block(sc, par_num++,
3208 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3210 bnx2x_print_next_block(sc, par_num++,
3213 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
3215 bnx2x_print_next_block(sc, par_num++,
3218 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3220 bnx2x_print_next_block(sc, par_num++,
3224 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3226 bnx2x_print_next_block(sc, par_num++,
3229 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3231 bnx2x_print_next_block(sc, par_num++,
3234 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
3236 bnx2x_print_next_block(sc, par_num++,
3239 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3241 bnx2x_print_next_block(sc, par_num++,
3244 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3246 bnx2x_print_next_block(sc, par_num++,
3249 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3251 bnx2x_print_next_block(sc, par_num++,
3254 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
3256 bnx2x_print_next_block(sc, par_num++,
3270 bnx2x_check_blocks_with_parity2(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3273 uint32_t cur_bit = 0;
3276 for (i = 0; sig; i++) {
3277 cur_bit = ((uint32_t) 0x1 << i);
3278 if (sig & cur_bit) {
3280 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3282 bnx2x_print_next_block(sc, par_num++,
3285 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3287 bnx2x_print_next_block(sc, par_num++,
3290 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3292 bnx2x_print_next_block(sc, par_num++,
3293 "PXPPCICLOCKCLIENT");
3295 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3297 bnx2x_print_next_block(sc, par_num++,
3300 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3302 bnx2x_print_next_block(sc, par_num++,
3305 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
3307 bnx2x_print_next_block(sc, par_num++,
3310 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3312 bnx2x_print_next_block(sc, par_num++,
3315 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3317 bnx2x_print_next_block(sc, par_num++,
3331 bnx2x_check_blocks_with_parity3(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3332 uint8_t * global, uint8_t print)
3334 uint32_t cur_bit = 0;
3337 for (i = 0; sig; i++) {
3338 cur_bit = ((uint32_t) 0x1 << i);
3339 if (sig & cur_bit) {
3341 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3343 bnx2x_print_next_block(sc, par_num++,
3347 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3349 bnx2x_print_next_block(sc, par_num++,
3353 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3355 bnx2x_print_next_block(sc, par_num++,
3359 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3361 bnx2x_print_next_block(sc, par_num++,
3376 bnx2x_check_blocks_with_parity4(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3379 uint32_t cur_bit = 0;
3382 for (i = 0; sig; i++) {
3383 cur_bit = ((uint32_t) 0x1 << i);
3384 if (sig & cur_bit) {
3386 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
3388 bnx2x_print_next_block(sc, par_num++,
3391 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
3393 bnx2x_print_next_block(sc, par_num++,
3407 bnx2x_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print,
3412 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
3413 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
3414 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
3415 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
3416 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
3417 PMD_DRV_LOG(ERR, sc,
3418 "Parity error: HW block parity attention:"
3419 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x",
3420 (uint32_t) (sig[0] & HW_PRTY_ASSERT_SET_0),
3421 (uint32_t) (sig[1] & HW_PRTY_ASSERT_SET_1),
3422 (uint32_t) (sig[2] & HW_PRTY_ASSERT_SET_2),
3423 (uint32_t) (sig[3] & HW_PRTY_ASSERT_SET_3),
3424 (uint32_t) (sig[4] & HW_PRTY_ASSERT_SET_4));
3427 PMD_DRV_LOG(INFO, sc, "Parity errors detected in blocks: ");
3430 bnx2x_check_blocks_with_parity0(sc, sig[0] &
3431 HW_PRTY_ASSERT_SET_0,
3434 bnx2x_check_blocks_with_parity1(sc, sig[1] &
3435 HW_PRTY_ASSERT_SET_1,
3436 par_num, global, print);
3438 bnx2x_check_blocks_with_parity2(sc, sig[2] &
3439 HW_PRTY_ASSERT_SET_2,
3442 bnx2x_check_blocks_with_parity3(sc, sig[3] &
3443 HW_PRTY_ASSERT_SET_3,
3444 par_num, global, print);
3446 bnx2x_check_blocks_with_parity4(sc, sig[4] &
3447 HW_PRTY_ASSERT_SET_4,
3451 PMD_DRV_LOG(INFO, sc, "");
3460 bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print)
3462 struct attn_route attn = { {0} };
3463 int port = SC_PORT(sc);
3465 attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
3466 attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
3467 attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
3468 attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
3470 if (!CHIP_IS_E1x(sc))
3472 REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
3474 return bnx2x_parity_attn(sc, global, print, attn.sig);
3477 static void bnx2x_attn_int_deasserted4(struct bnx2x_softc *sc, uint32_t attn)
3481 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
3482 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
3483 PMD_DRV_LOG(INFO, sc, "ERROR: PGLUE hw attention 0x%08x", val);
3484 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
3485 PMD_DRV_LOG(INFO, sc,
3486 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR");
3487 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
3488 PMD_DRV_LOG(INFO, sc,
3489 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR");
3490 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
3491 PMD_DRV_LOG(INFO, sc,
3492 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN");
3493 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
3494 PMD_DRV_LOG(INFO, sc,
3495 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN");
3497 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
3498 PMD_DRV_LOG(INFO, sc,
3499 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN");
3501 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
3502 PMD_DRV_LOG(INFO, sc,
3503 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN");
3504 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
3505 PMD_DRV_LOG(INFO, sc,
3506 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN");
3507 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
3508 PMD_DRV_LOG(INFO, sc,
3509 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN");
3510 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
3511 PMD_DRV_LOG(INFO, sc,
3512 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW");
3515 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
3516 val = REG_RD(sc, ATC_REG_ATC_INT_STS_CLR);
3517 PMD_DRV_LOG(INFO, sc, "ERROR: ATC hw attention 0x%08x", val);
3518 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
3519 PMD_DRV_LOG(INFO, sc,
3520 "ERROR: ATC_ATC_INT_STS_REG_ADDRESS_ERROR");
3521 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
3522 PMD_DRV_LOG(INFO, sc,
3523 "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND");
3524 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
3525 PMD_DRV_LOG(INFO, sc,
3526 "ERROR: ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS");
3527 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
3528 PMD_DRV_LOG(INFO, sc,
3529 "ERROR: ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT");
3530 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
3531 PMD_DRV_LOG(INFO, sc,
3532 "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR");
3533 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
3534 PMD_DRV_LOG(INFO, sc,
3535 "ERROR: ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU");
3538 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3539 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
3540 PMD_DRV_LOG(INFO, sc,
3541 "ERROR: FATAL parity attention set4 0x%08x",
3543 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
3545 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
3549 static void bnx2x_e1h_disable(struct bnx2x_softc *sc)
3551 int port = SC_PORT(sc);
3553 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
3556 static void bnx2x_e1h_enable(struct bnx2x_softc *sc)
3558 int port = SC_PORT(sc);
3560 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3564 * called due to MCP event (on pmf):
3565 * reread new bandwidth configuration
3567 * notify others function about the change
3569 static void bnx2x_config_mf_bw(struct bnx2x_softc *sc)
3571 if (sc->link_vars.link_up) {
3572 bnx2x_cmng_fns_init(sc, TRUE, CMNG_FNS_MINMAX);
3573 bnx2x_link_sync_notify(sc);
3576 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
3579 static void bnx2x_set_mf_bw(struct bnx2x_softc *sc)
3581 bnx2x_config_mf_bw(sc);
3582 bnx2x_fw_command(sc, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3585 static void bnx2x_handle_eee_event(struct bnx2x_softc *sc)
3587 bnx2x_fw_command(sc, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3590 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3592 static void bnx2x_drv_info_ether_stat(struct bnx2x_softc *sc)
3594 struct eth_stats_info *ether_stat = &sc->sp->drv_info_to_mcp.ether_stat;
3596 strncpy(ether_stat->version, BNX2X_DRIVER_VERSION,
3597 ETH_STAT_INFO_VERSION_LEN);
3599 sc->sp_objs[0].mac_obj.get_n_elements(sc, &sc->sp_objs[0].mac_obj,
3600 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3601 ether_stat->mac_local + MAC_PAD,
3604 ether_stat->mtu_size = sc->mtu;
3606 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3607 ether_stat->promiscuous_mode = 0; // (flags & PROMISC) ? 1 : 0;
3609 ether_stat->txq_size = sc->tx_ring_size;
3610 ether_stat->rxq_size = sc->rx_ring_size;
3613 static void bnx2x_handle_drv_info_req(struct bnx2x_softc *sc)
3615 enum drv_info_opcode op_code;
3616 uint32_t drv_info_ctl = SHMEM2_RD(sc, drv_info_control);
3618 /* if drv_info version supported by MFW doesn't match - send NACK */
3619 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3620 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3624 op_code = ((drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3625 DRV_INFO_CONTROL_OP_CODE_SHIFT);
3627 memset(&sc->sp->drv_info_to_mcp, 0, sizeof(union drv_info_to_mcp));
3630 case ETH_STATS_OPCODE:
3631 bnx2x_drv_info_ether_stat(sc);
3633 case FCOE_STATS_OPCODE:
3634 case ISCSI_STATS_OPCODE:
3636 /* if op code isn't supported - send NACK */
3637 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3642 * If we got drv_info attn from MFW then these fields are defined in
3645 SHMEM2_WR(sc, drv_info_host_addr_lo,
3646 U64_LO(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3647 SHMEM2_WR(sc, drv_info_host_addr_hi,
3648 U64_HI(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3650 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3653 static void bnx2x_dcc_event(struct bnx2x_softc *sc, uint32_t dcc_event)
3655 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3657 * This is the only place besides the function initialization
3658 * where the sc->flags can change so it is done without any
3662 mf_info.mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_DISABLED) {
3663 PMD_DRV_LOG(DEBUG, sc, "mf_cfg function disabled");
3664 sc->flags |= BNX2X_MF_FUNC_DIS;
3665 bnx2x_e1h_disable(sc);
3667 PMD_DRV_LOG(DEBUG, sc, "mf_cfg function enabled");
3668 sc->flags &= ~BNX2X_MF_FUNC_DIS;
3669 bnx2x_e1h_enable(sc);
3671 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3674 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3675 bnx2x_config_mf_bw(sc);
3676 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3679 /* Report results to MCP */
3681 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_FAILURE, 0);
3683 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_OK, 0);
3686 static void bnx2x_pmf_update(struct bnx2x_softc *sc)
3688 int port = SC_PORT(sc);
3694 * We need the mb() to ensure the ordering between the writing to
3695 * sc->port.pmf here and reading it from the bnx2x_periodic_task().
3699 /* enable nig attention */
3700 val = (0xff0f | (1 << (SC_VN(sc) + 4)));
3701 if (sc->devinfo.int_block == INT_BLOCK_HC) {
3702 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, val);
3703 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, val);
3704 } else if (!CHIP_IS_E1x(sc)) {
3705 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
3706 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
3709 bnx2x_stats_handle(sc, STATS_EVENT_PMF);
3712 static int bnx2x_mc_assert(struct bnx2x_softc *sc)
3716 __rte_unused uint32_t row0, row1, row2, row3;
3720 REG_RD8(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_INDEX_OFFSET);
3722 PMD_DRV_LOG(ERR, sc, "XSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3724 /* print the asserts */
3725 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3729 BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i));
3732 BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3736 BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3740 BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3743 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3744 PMD_DRV_LOG(ERR, sc,
3745 "XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3746 i, row3, row2, row1, row0);
3755 REG_RD8(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_INDEX_OFFSET);
3757 PMD_DRV_LOG(ERR, sc, "TSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3760 /* print the asserts */
3761 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3765 BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i));
3768 BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3772 BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3776 BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3779 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3780 PMD_DRV_LOG(ERR, sc,
3781 "TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3782 i, row3, row2, row1, row0);
3791 REG_RD8(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_INDEX_OFFSET);
3793 PMD_DRV_LOG(ERR, sc, "CSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3796 /* print the asserts */
3797 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3801 BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i));
3804 BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3808 BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3812 BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3815 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3816 PMD_DRV_LOG(ERR, sc,
3817 "CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3818 i, row3, row2, row1, row0);
3827 REG_RD8(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_INDEX_OFFSET);
3829 PMD_DRV_LOG(ERR, sc, "USTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3832 /* print the asserts */
3833 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3837 BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i));
3840 BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3844 BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3848 BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3851 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3852 PMD_DRV_LOG(ERR, sc,
3853 "USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3854 i, row3, row2, row1, row0);
3864 static void bnx2x_attn_int_deasserted3(struct bnx2x_softc *sc, uint32_t attn)
3866 int func = SC_FUNC(sc);
3869 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3871 if (attn & BNX2X_PMF_LINK_ASSERT(sc)) {
3873 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
3874 bnx2x_read_mf_cfg(sc);
3875 sc->devinfo.mf_info.mf_config[SC_VN(sc)] =
3877 func_mf_config[SC_ABS_FUNC(sc)].config);
3879 SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_status);
3881 if (val & DRV_STATUS_DCC_EVENT_MASK)
3884 DRV_STATUS_DCC_EVENT_MASK));
3886 if (val & DRV_STATUS_SET_MF_BW)
3887 bnx2x_set_mf_bw(sc);
3889 if (val & DRV_STATUS_DRV_INFO_REQ)
3890 bnx2x_handle_drv_info_req(sc);
3892 if ((sc->port.pmf == 0) && (val & DRV_STATUS_PMF))
3893 bnx2x_pmf_update(sc);
3895 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
3896 bnx2x_handle_eee_event(sc);
3898 if (sc->link_vars.periodic_flags &
3899 ELINK_PERIODIC_FLAGS_LINK_EVENT) {
3900 /* sync with link */
3901 bnx2x_acquire_phy_lock(sc);
3902 sc->link_vars.periodic_flags &=
3903 ~ELINK_PERIODIC_FLAGS_LINK_EVENT;
3904 bnx2x_release_phy_lock(sc);
3906 bnx2x_link_sync_notify(sc);
3908 bnx2x_link_report(sc);
3912 * Always call it here: bnx2x_link_report() will
3913 * prevent the link indication duplication.
3915 bnx2x_link_status_update(sc);
3917 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3919 PMD_DRV_LOG(ERR, sc, "MC assert!");
3920 bnx2x_mc_assert(sc);
3921 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3922 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3923 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3924 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3925 rte_panic("MC assert!");
3927 } else if (attn & BNX2X_MCP_ASSERT) {
3929 PMD_DRV_LOG(ERR, sc, "MCP assert!");
3930 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3933 PMD_DRV_LOG(ERR, sc,
3934 "Unknown HW assert! (attn 0x%08x)", attn);
3938 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3939 PMD_DRV_LOG(ERR, sc, "LATCHED attention 0x%08x (masked)", attn);
3940 if (attn & BNX2X_GRC_TIMEOUT) {
3941 val = REG_RD(sc, MISC_REG_GRC_TIMEOUT_ATTN);
3942 PMD_DRV_LOG(ERR, sc, "GRC time-out 0x%08x", val);
3944 if (attn & BNX2X_GRC_RSV) {
3945 val = REG_RD(sc, MISC_REG_GRC_RSV_ATTN);
3946 PMD_DRV_LOG(ERR, sc, "GRC reserved 0x%08x", val);
3948 REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3952 static void bnx2x_attn_int_deasserted2(struct bnx2x_softc *sc, uint32_t attn)
3954 int port = SC_PORT(sc);
3956 uint32_t val0, mask0, val1, mask1;
3959 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3960 val = REG_RD(sc, CFC_REG_CFC_INT_STS_CLR);
3961 PMD_DRV_LOG(ERR, sc, "CFC hw attention 0x%08x", val);
3962 /* CFC error attention */
3964 PMD_DRV_LOG(ERR, sc, "FATAL error from CFC");
3968 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3969 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_0);
3970 PMD_DRV_LOG(ERR, sc, "PXP hw attention-0 0x%08x", val);
3971 /* RQ_USDMDP_FIFO_OVERFLOW */
3972 if (val & 0x18000) {
3973 PMD_DRV_LOG(ERR, sc, "FATAL error from PXP");
3976 if (!CHIP_IS_E1x(sc)) {
3977 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_1);
3978 PMD_DRV_LOG(ERR, sc, "PXP hw attention-1 0x%08x", val);
3981 #define PXP2_EOP_ERROR_BIT PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR
3982 #define AEU_PXP2_HW_INT_BIT AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT
3984 if (attn & AEU_PXP2_HW_INT_BIT) {
3985 /* CQ47854 workaround do not panic on
3986 * PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3988 if (!CHIP_IS_E1x(sc)) {
3989 mask0 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_0);
3990 val1 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_1);
3991 mask1 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_1);
3992 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_0);
3994 * If the only PXP2_EOP_ERROR_BIT is set in
3995 * STS0 and STS1 - clear it
3997 * probably we lose additional attentions between
3998 * STS0 and STS_CLR0, in this case user will not
3999 * be notified about them
4001 if (val0 & mask0 & PXP2_EOP_ERROR_BIT &&
4003 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
4005 /* print the register, since no one can restore it */
4006 PMD_DRV_LOG(ERR, sc,
4007 "PXP2_REG_PXP2_INT_STS_CLR_0 0x%08x", val0);
4010 * if PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
4013 if (val0 & PXP2_EOP_ERROR_BIT) {
4014 PMD_DRV_LOG(ERR, sc, "PXP2_WR_PGLUE_EOP_ERROR");
4017 * if only PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR is
4018 * set then clear attention from PXP2 block without panic
4020 if (((val0 & mask0) == PXP2_EOP_ERROR_BIT) &&
4021 ((val1 & mask1) == 0))
4022 attn &= ~AEU_PXP2_HW_INT_BIT;
4027 if (attn & HW_INTERRUT_ASSERT_SET_2) {
4028 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
4029 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
4031 val = REG_RD(sc, reg_offset);
4032 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
4033 REG_WR(sc, reg_offset, val);
4035 PMD_DRV_LOG(ERR, sc,
4036 "FATAL HW block attention set2 0x%x",
4037 (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_2));
4038 rte_panic("HW block attention set2");
4042 static void bnx2x_attn_int_deasserted1(struct bnx2x_softc *sc, uint32_t attn)
4044 int port = SC_PORT(sc);
4048 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
4049 val = REG_RD(sc, DORQ_REG_DORQ_INT_STS_CLR);
4050 PMD_DRV_LOG(ERR, sc, "DB hw attention 0x%08x", val);
4051 /* DORQ discard attention */
4053 PMD_DRV_LOG(ERR, sc, "FATAL error from DORQ");
4057 if (attn & HW_INTERRUT_ASSERT_SET_1) {
4058 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4059 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4061 val = REG_RD(sc, reg_offset);
4062 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4063 REG_WR(sc, reg_offset, val);
4065 PMD_DRV_LOG(ERR, sc,
4066 "FATAL HW block attention set1 0x%08x",
4067 (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_1));
4068 rte_panic("HW block attention set1");
4072 static void bnx2x_attn_int_deasserted0(struct bnx2x_softc *sc, uint32_t attn)
4074 int port = SC_PORT(sc);
4078 reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4079 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
4081 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4082 val = REG_RD(sc, reg_offset);
4083 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4084 REG_WR(sc, reg_offset, val);
4086 PMD_DRV_LOG(WARNING, sc, "SPIO5 hw attention");
4088 /* Fan failure attention */
4089 elink_hw_reset_phy(&sc->link_params);
4090 bnx2x_fan_failure(sc);
4093 if ((attn & sc->link_vars.aeu_int_mask) && sc->port.pmf) {
4094 bnx2x_acquire_phy_lock(sc);
4095 elink_handle_module_detect_int(&sc->link_params);
4096 bnx2x_release_phy_lock(sc);
4099 if (attn & HW_INTERRUT_ASSERT_SET_0) {
4100 val = REG_RD(sc, reg_offset);
4101 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4102 REG_WR(sc, reg_offset, val);
4104 rte_panic("FATAL HW block attention set0 0x%lx",
4105 (attn & HW_INTERRUT_ASSERT_SET_0));
4109 static void bnx2x_attn_int_deasserted(struct bnx2x_softc *sc, uint32_t deasserted)
4111 struct attn_route attn;
4112 struct attn_route *group_mask;
4113 int port = SC_PORT(sc);
4118 uint8_t global = FALSE;
4121 * Need to take HW lock because MCP or other port might also
4122 * try to handle this event.
4124 bnx2x_acquire_alr(sc);
4126 if (bnx2x_chk_parity_attn(sc, &global, TRUE)) {
4127 sc->recovery_state = BNX2X_RECOVERY_INIT;
4129 /* disable HW interrupts */
4130 bnx2x_int_disable(sc);
4131 bnx2x_release_alr(sc);
4135 attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
4136 attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
4137 attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
4138 attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
4139 if (!CHIP_IS_E1x(sc)) {
4141 REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
4146 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4147 if (deasserted & (1 << index)) {
4148 group_mask = &sc->attn_group[index];
4150 bnx2x_attn_int_deasserted4(sc,
4152 sig[4] & group_mask->sig[4]);
4153 bnx2x_attn_int_deasserted3(sc,
4155 sig[3] & group_mask->sig[3]);
4156 bnx2x_attn_int_deasserted1(sc,
4158 sig[1] & group_mask->sig[1]);
4159 bnx2x_attn_int_deasserted2(sc,
4161 sig[2] & group_mask->sig[2]);
4162 bnx2x_attn_int_deasserted0(sc,
4164 sig[0] & group_mask->sig[0]);
4168 bnx2x_release_alr(sc);
4170 if (sc->devinfo.int_block == INT_BLOCK_HC) {
4171 reg_addr = (HC_REG_COMMAND_REG + port * 32 +
4172 COMMAND_REG_ATTN_BITS_CLR);
4174 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER * 8);
4178 PMD_DRV_LOG(DEBUG, sc,
4179 "about to mask 0x%08x at %s addr 0x%08x", val,
4180 (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
4182 REG_WR(sc, reg_addr, val);
4184 if (~sc->attn_state & deasserted) {
4185 PMD_DRV_LOG(ERR, sc, "IGU error");
4188 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4189 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4191 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4193 aeu_mask = REG_RD(sc, reg_addr);
4195 aeu_mask |= (deasserted & 0x3ff);
4197 REG_WR(sc, reg_addr, aeu_mask);
4198 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4200 sc->attn_state &= ~deasserted;
4203 static void bnx2x_attn_int(struct bnx2x_softc *sc)
4205 /* read local copy of bits */
4206 uint32_t attn_bits = le32toh(sc->def_sb->atten_status_block.attn_bits);
4208 le32toh(sc->def_sb->atten_status_block.attn_bits_ack);
4209 uint32_t attn_state = sc->attn_state;
4211 /* look for changed bits */
4212 uint32_t asserted = attn_bits & ~attn_ack & ~attn_state;
4213 uint32_t deasserted = ~attn_bits & attn_ack & attn_state;
4215 PMD_DRV_LOG(DEBUG, sc,
4216 "attn_bits 0x%08x attn_ack 0x%08x asserted 0x%08x deasserted 0x%08x",
4217 attn_bits, attn_ack, asserted, deasserted);
4219 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) {
4220 PMD_DRV_LOG(ERR, sc, "BAD attention state");
4223 /* handle bits that were raised */
4225 bnx2x_attn_int_asserted(sc, asserted);
4229 bnx2x_attn_int_deasserted(sc, deasserted);
4233 static uint16_t bnx2x_update_dsb_idx(struct bnx2x_softc *sc)
4235 struct host_sp_status_block *def_sb = sc->def_sb;
4241 mb(); /* status block is written to by the chip */
4243 if (sc->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
4244 sc->def_att_idx = def_sb->atten_status_block.attn_bits_index;
4245 rc |= BNX2X_DEF_SB_ATT_IDX;
4248 if (sc->def_idx != def_sb->sp_sb.running_index) {
4249 sc->def_idx = def_sb->sp_sb.running_index;
4250 rc |= BNX2X_DEF_SB_IDX;
4258 static struct ecore_queue_sp_obj *bnx2x_cid_to_q_obj(struct bnx2x_softc *sc,
4261 return &sc->sp_objs[CID_TO_FP(cid, sc)].q_obj;
4264 static void bnx2x_handle_mcast_eqe(struct bnx2x_softc *sc)
4266 struct ecore_mcast_ramrod_params rparam;
4269 memset(&rparam, 0, sizeof(rparam));
4271 rparam.mcast_obj = &sc->mcast_obj;
4273 /* clear pending state for the last command */
4274 sc->mcast_obj.raw.clear_pending(&sc->mcast_obj.raw);
4276 /* if there are pending mcast commands - send them */
4277 if (sc->mcast_obj.check_pending(&sc->mcast_obj)) {
4278 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
4280 PMD_DRV_LOG(INFO, sc,
4281 "Failed to send pending mcast commands (%d)",
4288 bnx2x_handle_classification_eqe(struct bnx2x_softc *sc, union event_ring_elem *elem)
4290 unsigned long ramrod_flags = 0;
4292 uint32_t cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4293 struct ecore_vlan_mac_obj *vlan_mac_obj;
4295 /* always push next commands out, don't wait here */
4296 bnx2x_set_bit(RAMROD_CONT, &ramrod_flags);
4298 switch (le32toh(elem->message.data.eth_event.echo) >> BNX2X_SWCID_SHIFT) {
4299 case ECORE_FILTER_MAC_PENDING:
4300 PMD_DRV_LOG(DEBUG, sc, "Got SETUP_MAC completions");
4301 vlan_mac_obj = &sc->sp_objs[cid].mac_obj;
4304 case ECORE_FILTER_MCAST_PENDING:
4305 PMD_DRV_LOG(DEBUG, sc, "Got SETUP_MCAST completions");
4306 bnx2x_handle_mcast_eqe(sc);
4310 PMD_DRV_LOG(NOTICE, sc, "Unsupported classification command: %d",
4311 elem->message.data.eth_event.echo);
4315 rc = vlan_mac_obj->complete(sc, vlan_mac_obj, elem, &ramrod_flags);
4318 PMD_DRV_LOG(NOTICE, sc,
4319 "Failed to schedule new commands (%d)", rc);
4320 } else if (rc > 0) {
4321 PMD_DRV_LOG(DEBUG, sc, "Scheduled next pending commands...");
4325 static void bnx2x_handle_rx_mode_eqe(struct bnx2x_softc *sc)
4327 bnx2x_clear_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
4329 /* send rx_mode command again if was requested */
4330 if (bnx2x_test_and_clear_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state)) {
4331 bnx2x_set_storm_rx_mode(sc);
4335 static void bnx2x_update_eq_prod(struct bnx2x_softc *sc, uint16_t prod)
4337 storm_memset_eq_prod(sc, prod, SC_FUNC(sc));
4338 wmb(); /* keep prod updates ordered */
4341 static void bnx2x_eq_int(struct bnx2x_softc *sc)
4343 uint16_t hw_cons, sw_cons, sw_prod;
4344 union event_ring_elem *elem;
4349 struct ecore_queue_sp_obj *q_obj;
4350 struct ecore_func_sp_obj *f_obj = &sc->func_obj;
4351 struct ecore_raw_obj *rss_raw = &sc->rss_conf_obj.raw;
4353 hw_cons = le16toh(*sc->eq_cons_sb);
4356 * The hw_cons range is 1-255, 257 - the sw_cons range is 0-254, 256.
4357 * when we get to the next-page we need to adjust so the loop
4358 * condition below will be met. The next element is the size of a
4359 * regular element and hence incrementing by 1
4361 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) {
4366 * This function may never run in parallel with itself for a
4367 * specific sc and no need for a read memory barrier here.
4369 sw_cons = sc->eq_cons;
4370 sw_prod = sc->eq_prod;
4374 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4376 elem = &sc->eq[EQ_DESC(sw_cons)];
4378 /* elem CID originates from FW, actually LE */
4379 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4380 opcode = elem->message.opcode;
4382 /* handle eq element */
4384 case EVENT_RING_OPCODE_STAT_QUERY:
4385 PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "got statistics completion event %d",
4387 /* nothing to do with stats comp */
4390 case EVENT_RING_OPCODE_CFC_DEL:
4391 /* handle according to cid range */
4392 /* we may want to verify here that the sc state is HALTING */
4393 PMD_DRV_LOG(DEBUG, sc, "got delete ramrod for MULTI[%d]",
4395 q_obj = bnx2x_cid_to_q_obj(sc, cid);
4396 if (q_obj->complete_cmd(sc, q_obj, ECORE_Q_CMD_CFC_DEL)) {
4401 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4402 PMD_DRV_LOG(DEBUG, sc, "got STOP TRAFFIC");
4403 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_STOP)) {
4408 case EVENT_RING_OPCODE_START_TRAFFIC:
4409 PMD_DRV_LOG(DEBUG, sc, "got START TRAFFIC");
4410 if (f_obj->complete_cmd
4411 (sc, f_obj, ECORE_F_CMD_TX_START)) {
4416 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
4417 echo = elem->message.data.function_update_event.echo;
4418 if (echo == SWITCH_UPDATE) {
4419 PMD_DRV_LOG(DEBUG, sc,
4420 "got FUNC_SWITCH_UPDATE ramrod");
4421 if (f_obj->complete_cmd(sc, f_obj,
4422 ECORE_F_CMD_SWITCH_UPDATE))
4427 PMD_DRV_LOG(DEBUG, sc,
4428 "AFEX: ramrod completed FUNCTION_UPDATE");
4429 f_obj->complete_cmd(sc, f_obj,
4430 ECORE_F_CMD_AFEX_UPDATE);
4434 case EVENT_RING_OPCODE_FORWARD_SETUP:
4435 q_obj = &bnx2x_fwd_sp_obj(sc, q_obj);
4436 if (q_obj->complete_cmd(sc, q_obj,
4437 ECORE_Q_CMD_SETUP_TX_ONLY)) {
4442 case EVENT_RING_OPCODE_FUNCTION_START:
4443 PMD_DRV_LOG(DEBUG, sc, "got FUNC_START ramrod");
4444 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_START)) {
4449 case EVENT_RING_OPCODE_FUNCTION_STOP:
4450 PMD_DRV_LOG(DEBUG, sc, "got FUNC_STOP ramrod");
4451 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_STOP)) {
4457 switch (opcode | sc->state) {
4458 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPEN):
4459 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPENING_WAITING_PORT):
4461 elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4462 PMD_DRV_LOG(DEBUG, sc, "got RSS_UPDATE ramrod. CID %d",
4464 rss_raw->clear_pending(rss_raw);
4467 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4468 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4469 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_CLOSING_WAITING_HALT):
4470 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_OPEN):
4471 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_DIAG):
4472 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4473 PMD_DRV_LOG(DEBUG, sc,
4474 "got (un)set mac ramrod");
4475 bnx2x_handle_classification_eqe(sc, elem);
4478 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_OPEN):
4479 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_DIAG):
4480 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4481 PMD_DRV_LOG(DEBUG, sc,
4482 "got mcast ramrod");
4483 bnx2x_handle_mcast_eqe(sc);
4486 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_OPEN):
4487 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_DIAG):
4488 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4489 PMD_DRV_LOG(DEBUG, sc,
4490 "got rx_mode ramrod");
4491 bnx2x_handle_rx_mode_eqe(sc);
4495 /* unknown event log error and continue */
4496 PMD_DRV_LOG(INFO, sc, "Unknown EQ event %d, sc->state 0x%x",
4497 elem->message.opcode, sc->state);
4505 atomic_add_acq_long(&sc->eq_spq_left, spqe_cnt);
4507 sc->eq_cons = sw_cons;
4508 sc->eq_prod = sw_prod;
4510 /* make sure that above mem writes were issued towards the memory */
4513 /* update producer */
4514 bnx2x_update_eq_prod(sc, sc->eq_prod);
4517 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc)
4522 PMD_DRV_LOG(DEBUG, sc, "---> SP TASK <---");
4524 /* what work needs to be performed? */
4525 status = bnx2x_update_dsb_idx(sc);
4527 PMD_DRV_LOG(DEBUG, sc, "dsb status 0x%04x", status);
4530 if (status & BNX2X_DEF_SB_ATT_IDX) {
4531 PMD_DRV_LOG(DEBUG, sc, "---> ATTN INTR <---");
4533 status &= ~BNX2X_DEF_SB_ATT_IDX;
4537 /* SP events: STAT_QUERY and others */
4538 if (status & BNX2X_DEF_SB_IDX) {
4539 /* handle EQ completions */
4540 PMD_DRV_LOG(DEBUG, sc, "---> EQ INTR <---");
4542 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
4543 le16toh(sc->def_idx), IGU_INT_NOP, 1);
4544 status &= ~BNX2X_DEF_SB_IDX;
4547 /* if status is non zero then something went wrong */
4548 if (unlikely(status)) {
4549 PMD_DRV_LOG(INFO, sc,
4550 "Got an unknown SP interrupt! (0x%04x)", status);
4553 /* ack status block only if something was actually handled */
4554 bnx2x_ack_sb(sc, sc->igu_dsb_id, ATTENTION_ID,
4555 le16toh(sc->def_att_idx), IGU_INT_ENABLE, 1);
4560 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp)
4562 struct bnx2x_softc *sc = fp->sc;
4563 uint8_t more_rx = FALSE;
4565 /* Make sure FP is initialized */
4566 if (!fp->sb_running_index)
4569 PMD_DEBUG_PERIODIC_LOG(DEBUG, sc,
4570 "---> FP TASK QUEUE (%d) <--", fp->index);
4572 /* update the fastpath index */
4573 bnx2x_update_fp_sb_idx(fp);
4575 if (rte_atomic32_read(&sc->scan_fp) == 1) {
4576 if (bnx2x_has_rx_work(fp)) {
4577 more_rx = bnx2x_rxeof(sc, fp);
4581 /* still more work to do */
4582 bnx2x_handle_fp_tq(fp);
4587 /* Assuming we have completed slow path completion, clear the flag */
4588 rte_atomic32_set(&sc->scan_fp, 0);
4589 bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
4590 le16toh(fp->fp_hc_idx), IGU_INT_ENABLE, 1);
4594 * Legacy interrupt entry point.
4596 * Verifies that the controller generated the interrupt and
4597 * then calls a separate routine to handle the various
4598 * interrupt causes: link, RX, and TX.
4600 int bnx2x_intr_legacy(struct bnx2x_softc *sc)
4602 struct bnx2x_fastpath *fp;
4603 uint32_t status, mask;
4607 * 0 for ustorm, 1 for cstorm
4608 * the bits returned from ack_int() are 0-15
4609 * bit 0 = attention status block
4610 * bit 1 = fast path status block
4611 * a mask of 0x2 or more = tx/rx event
4612 * a mask of 1 = slow path event
4615 status = bnx2x_ack_int(sc);
4617 /* the interrupt is not for us */
4618 if (unlikely(status == 0)) {
4622 PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "Interrupt status 0x%04x", status);
4623 //bnx2x_dump_status_block(sc);
4625 FOR_EACH_ETH_QUEUE(sc, i) {
4627 mask = (0x2 << (fp->index + CNIC_SUPPORT(sc)));
4628 if (status & mask) {
4629 /* acknowledge and disable further fastpath interrupts */
4630 bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
4631 0, IGU_INT_DISABLE, 0);
4632 bnx2x_handle_fp_tq(fp);
4637 if (unlikely(status & 0x1)) {
4638 /* acknowledge and disable further slowpath interrupts */
4639 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
4640 0, IGU_INT_DISABLE, 0);
4641 rc = bnx2x_handle_sp_tq(sc);
4645 if (unlikely(status)) {
4646 PMD_DRV_LOG(WARNING, sc,
4647 "Unexpected fastpath status (0x%08x)!", status);
4653 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc);
4654 static int bnx2x_init_hw_common(struct bnx2x_softc *sc);
4655 static int bnx2x_init_hw_port(struct bnx2x_softc *sc);
4656 static int bnx2x_init_hw_func(struct bnx2x_softc *sc);
4657 static void bnx2x_reset_common(struct bnx2x_softc *sc);
4658 static void bnx2x_reset_port(struct bnx2x_softc *sc);
4659 static void bnx2x_reset_func(struct bnx2x_softc *sc);
4660 static int bnx2x_init_firmware(struct bnx2x_softc *sc);
4661 static void bnx2x_release_firmware(struct bnx2x_softc *sc);
4664 ecore_func_sp_drv_ops bnx2x_func_sp_drv = {
4665 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
4666 .init_hw_cmn = bnx2x_init_hw_common,
4667 .init_hw_port = bnx2x_init_hw_port,
4668 .init_hw_func = bnx2x_init_hw_func,
4670 .reset_hw_cmn = bnx2x_reset_common,
4671 .reset_hw_port = bnx2x_reset_port,
4672 .reset_hw_func = bnx2x_reset_func,
4674 .init_fw = bnx2x_init_firmware,
4675 .release_fw = bnx2x_release_firmware,
4678 static void bnx2x_init_func_obj(struct bnx2x_softc *sc)
4682 PMD_INIT_FUNC_TRACE(sc);
4684 ecore_init_func_obj(sc,
4686 BNX2X_SP(sc, func_rdata),
4687 (rte_iova_t)BNX2X_SP_MAPPING(sc, func_rdata),
4688 BNX2X_SP(sc, func_afex_rdata),
4689 (rte_iova_t)BNX2X_SP_MAPPING(sc, func_afex_rdata),
4690 &bnx2x_func_sp_drv);
4693 static int bnx2x_init_hw(struct bnx2x_softc *sc, uint32_t load_code)
4695 struct ecore_func_state_params func_params = { NULL };
4698 PMD_INIT_FUNC_TRACE(sc);
4700 /* prepare the parameters for function state transitions */
4701 bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
4703 func_params.f_obj = &sc->func_obj;
4704 func_params.cmd = ECORE_F_CMD_HW_INIT;
4706 func_params.params.hw_init.load_phase = load_code;
4709 * Via a plethora of function pointers, we will eventually reach
4710 * bnx2x_init_hw_common(), bnx2x_init_hw_port(), or bnx2x_init_hw_func().
4712 rc = ecore_func_state_change(sc, &func_params);
4718 bnx2x_fill(struct bnx2x_softc *sc, uint32_t addr, int fill, uint32_t len)
4722 if (!(len % 4) && !(addr % 4)) {
4723 for (i = 0; i < len; i += 4) {
4724 REG_WR(sc, (addr + i), fill);
4727 for (i = 0; i < len; i++) {
4728 REG_WR8(sc, (addr + i), fill);
4733 /* writes FP SP data to FW - data_size in dwords */
4735 bnx2x_wr_fp_sb_data(struct bnx2x_softc *sc, int fw_sb_id, uint32_t * sb_data_p,
4740 for (index = 0; index < data_size; index++) {
4742 (BAR_CSTRORM_INTMEM +
4743 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
4744 (sizeof(uint32_t) * index)), *(sb_data_p + index));
4748 static void bnx2x_zero_fp_sb(struct bnx2x_softc *sc, int fw_sb_id)
4750 struct hc_status_block_data_e2 sb_data_e2;
4751 struct hc_status_block_data_e1x sb_data_e1x;
4752 uint32_t *sb_data_p;
4753 uint32_t data_size = 0;
4755 if (!CHIP_IS_E1x(sc)) {
4756 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4757 sb_data_e2.common.state = SB_DISABLED;
4758 sb_data_e2.common.p_func.vf_valid = FALSE;
4759 sb_data_p = (uint32_t *) & sb_data_e2;
4760 data_size = (sizeof(struct hc_status_block_data_e2) /
4763 memset(&sb_data_e1x, 0,
4764 sizeof(struct hc_status_block_data_e1x));
4765 sb_data_e1x.common.state = SB_DISABLED;
4766 sb_data_e1x.common.p_func.vf_valid = FALSE;
4767 sb_data_p = (uint32_t *) & sb_data_e1x;
4768 data_size = (sizeof(struct hc_status_block_data_e1x) /
4772 bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4775 (BAR_CSTRORM_INTMEM + CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id)), 0,
4776 CSTORM_STATUS_BLOCK_SIZE);
4777 bnx2x_fill(sc, (BAR_CSTRORM_INTMEM + CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id)),
4778 0, CSTORM_SYNC_BLOCK_SIZE);
4782 bnx2x_wr_sp_sb_data(struct bnx2x_softc *sc,
4783 struct hc_sp_status_block_data *sp_sb_data)
4788 i < (sizeof(struct hc_sp_status_block_data) / sizeof(uint32_t));
4791 (BAR_CSTRORM_INTMEM +
4792 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(SC_FUNC(sc)) +
4793 (i * sizeof(uint32_t))),
4794 *((uint32_t *) sp_sb_data + i));
4798 static void bnx2x_zero_sp_sb(struct bnx2x_softc *sc)
4800 struct hc_sp_status_block_data sp_sb_data;
4802 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4804 sp_sb_data.state = SB_DISABLED;
4805 sp_sb_data.p_func.vf_valid = FALSE;
4807 bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
4810 (BAR_CSTRORM_INTMEM +
4811 CSTORM_SP_STATUS_BLOCK_OFFSET(SC_FUNC(sc))),
4812 0, CSTORM_SP_STATUS_BLOCK_SIZE);
4814 (BAR_CSTRORM_INTMEM +
4815 CSTORM_SP_SYNC_BLOCK_OFFSET(SC_FUNC(sc))),
4816 0, CSTORM_SP_SYNC_BLOCK_SIZE);
4820 bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, int igu_sb_id,
4823 hc_sm->igu_sb_id = igu_sb_id;
4824 hc_sm->igu_seg_id = igu_seg_id;
4825 hc_sm->timer_value = 0xFF;
4826 hc_sm->time_to_expire = 0xFFFFFFFF;
4829 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
4831 /* zero out state machine indices */
4834 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4837 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4838 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
4839 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
4840 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
4845 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
4846 (SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4849 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
4850 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4851 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
4852 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4853 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
4854 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4855 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
4856 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4860 bnx2x_init_sb(struct bnx2x_softc *sc, rte_iova_t busaddr, int vfid,
4861 uint8_t vf_valid, int fw_sb_id, int igu_sb_id)
4863 struct hc_status_block_data_e2 sb_data_e2;
4864 struct hc_status_block_data_e1x sb_data_e1x;
4865 struct hc_status_block_sm *hc_sm_p;
4866 uint32_t *sb_data_p;
4870 if (CHIP_INT_MODE_IS_BC(sc)) {
4871 igu_seg_id = HC_SEG_ACCESS_NORM;
4873 igu_seg_id = IGU_SEG_ACCESS_NORM;
4876 bnx2x_zero_fp_sb(sc, fw_sb_id);
4878 if (!CHIP_IS_E1x(sc)) {
4879 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4880 sb_data_e2.common.state = SB_ENABLED;
4881 sb_data_e2.common.p_func.pf_id = SC_FUNC(sc);
4882 sb_data_e2.common.p_func.vf_id = vfid;
4883 sb_data_e2.common.p_func.vf_valid = vf_valid;
4884 sb_data_e2.common.p_func.vnic_id = SC_VN(sc);
4885 sb_data_e2.common.same_igu_sb_1b = TRUE;
4886 sb_data_e2.common.host_sb_addr.hi = U64_HI(busaddr);
4887 sb_data_e2.common.host_sb_addr.lo = U64_LO(busaddr);
4888 hc_sm_p = sb_data_e2.common.state_machine;
4889 sb_data_p = (uint32_t *) & sb_data_e2;
4890 data_size = (sizeof(struct hc_status_block_data_e2) /
4892 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
4894 memset(&sb_data_e1x, 0,
4895 sizeof(struct hc_status_block_data_e1x));
4896 sb_data_e1x.common.state = SB_ENABLED;
4897 sb_data_e1x.common.p_func.pf_id = SC_FUNC(sc);
4898 sb_data_e1x.common.p_func.vf_id = 0xff;
4899 sb_data_e1x.common.p_func.vf_valid = FALSE;
4900 sb_data_e1x.common.p_func.vnic_id = SC_VN(sc);
4901 sb_data_e1x.common.same_igu_sb_1b = TRUE;
4902 sb_data_e1x.common.host_sb_addr.hi = U64_HI(busaddr);
4903 sb_data_e1x.common.host_sb_addr.lo = U64_LO(busaddr);
4904 hc_sm_p = sb_data_e1x.common.state_machine;
4905 sb_data_p = (uint32_t *) & sb_data_e1x;
4906 data_size = (sizeof(struct hc_status_block_data_e1x) /
4908 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
4911 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], igu_sb_id, igu_seg_id);
4912 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], igu_sb_id, igu_seg_id);
4914 /* write indices to HW - PCI guarantees endianity of regpairs */
4915 bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4918 static uint8_t bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp)
4920 if (CHIP_IS_E1x(fp->sc)) {
4921 return fp->cl_id + SC_PORT(fp->sc) * ETH_MAX_RX_CLIENTS_E1H;
4928 bnx2x_rx_ustorm_prods_offset(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
4930 uint32_t offset = BAR_USTRORM_INTMEM;
4933 return PXP_VF_ADDR_USDM_QUEUES_START +
4934 (sc->acquire_resp.resc.hw_qid[fp->index] *
4935 sizeof(struct ustorm_queue_zone_data));
4936 } else if (!CHIP_IS_E1x(sc)) {
4937 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
4939 offset += USTORM_RX_PRODS_E1X_OFFSET(SC_PORT(sc), fp->cl_id);
4945 static void bnx2x_init_eth_fp(struct bnx2x_softc *sc, int idx)
4947 struct bnx2x_fastpath *fp = &sc->fp[idx];
4948 uint32_t cids[ECORE_MULTI_TX_COS] = { 0 };
4949 unsigned long q_type = 0;
4955 fp->igu_sb_id = (sc->igu_base_sb + idx + CNIC_SUPPORT(sc));
4956 fp->fw_sb_id = (sc->base_fw_ndsb + idx + CNIC_SUPPORT(sc));
4958 if (CHIP_IS_E1x(sc))
4959 fp->cl_id = SC_L_ID(sc) + idx;
4961 /* want client ID same as IGU SB ID for non-E1 */
4962 fp->cl_id = fp->igu_sb_id;
4963 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
4965 /* setup sb indices */
4966 if (!CHIP_IS_E1x(sc)) {
4967 fp->sb_index_values = fp->status_block.e2_sb->sb.index_values;
4968 fp->sb_running_index = fp->status_block.e2_sb->sb.running_index;
4970 fp->sb_index_values = fp->status_block.e1x_sb->sb.index_values;
4971 fp->sb_running_index =
4972 fp->status_block.e1x_sb->sb.running_index;
4976 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(sc, fp);
4978 fp->rx_cq_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS];
4980 for (cos = 0; cos < sc->max_cos; cos++) {
4983 fp->tx_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0];
4985 /* nothing more for a VF to do */
4990 bnx2x_init_sb(sc, fp->sb_dma.paddr, BNX2X_VF_ID_INVALID, FALSE,
4991 fp->fw_sb_id, fp->igu_sb_id);
4993 bnx2x_update_fp_sb_idx(fp);
4995 /* Configure Queue State object */
4996 bnx2x_set_bit(ECORE_Q_TYPE_HAS_RX, &q_type);
4997 bnx2x_set_bit(ECORE_Q_TYPE_HAS_TX, &q_type);
4999 ecore_init_queue_obj(sc,
5000 &sc->sp_objs[idx].q_obj,
5005 BNX2X_SP(sc, q_rdata),
5006 (rte_iova_t)BNX2X_SP_MAPPING(sc, q_rdata),
5009 /* configure classification DBs */
5010 ecore_init_mac_obj(sc,
5011 &sc->sp_objs[idx].mac_obj,
5015 BNX2X_SP(sc, mac_rdata),
5016 (rte_iova_t)BNX2X_SP_MAPPING(sc, mac_rdata),
5017 ECORE_FILTER_MAC_PENDING, &sc->sp_state,
5018 ECORE_OBJ_TYPE_RX_TX, &sc->macs_pool);
5022 bnx2x_update_rx_prod(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
5023 uint16_t rx_bd_prod, uint16_t rx_cq_prod)
5025 union ustorm_eth_rx_producers rx_prods;
5028 /* update producers */
5029 rx_prods.prod.bd_prod = rx_bd_prod;
5030 rx_prods.prod.cqe_prod = rx_cq_prod;
5031 rx_prods.prod.reserved = 0;
5034 * Make sure that the BD and SGE data is updated before updating the
5035 * producers since FW might read the BD/SGE right after the producer
5037 * This is only applicable for weak-ordered memory model archs such
5038 * as IA-64. The following barrier is also mandatory since FW will
5039 * assumes BDs must have buffers.
5043 for (i = 0; i < (sizeof(rx_prods) / 4); i++) {
5045 (fp->ustorm_rx_prods_offset + (i * 4)),
5046 rx_prods.raw_data[i]);
5049 wmb(); /* keep prod updates ordered */
5052 static void bnx2x_init_rx_rings(struct bnx2x_softc *sc)
5054 struct bnx2x_fastpath *fp;
5056 struct bnx2x_rx_queue *rxq;
5058 for (i = 0; i < sc->num_queues; i++) {
5060 rxq = sc->rx_queues[fp->index];
5062 PMD_RX_LOG(ERR, "RX queue is NULL");
5066 rxq->rx_bd_head = 0;
5067 rxq->rx_bd_tail = rxq->nb_rx_desc;
5068 rxq->rx_cq_head = 0;
5069 rxq->rx_cq_tail = TOTAL_RCQ_ENTRIES(rxq);
5070 *fp->rx_cq_cons_sb = 0;
5073 * Activate the BD ring...
5074 * Warning, this will generate an interrupt (to the TSTORM)
5075 * so this can only be done after the chip is initialized
5077 bnx2x_update_rx_prod(sc, fp, rxq->rx_bd_tail, rxq->rx_cq_tail);
5085 static void bnx2x_init_tx_ring_one(struct bnx2x_fastpath *fp)
5087 struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
5089 fp->tx_db.data.header.header = 1 << DOORBELL_HDR_DB_TYPE_SHIFT;
5090 fp->tx_db.data.zero_fill1 = 0;
5091 fp->tx_db.data.prod = 0;
5094 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
5098 txq->tx_pkt_tail = 0;
5099 txq->tx_pkt_head = 0;
5100 txq->tx_bd_tail = 0;
5101 txq->tx_bd_head = 0;
5104 static void bnx2x_init_tx_rings(struct bnx2x_softc *sc)
5108 for (i = 0; i < sc->num_queues; i++) {
5109 bnx2x_init_tx_ring_one(&sc->fp[i]);
5113 static void bnx2x_init_def_sb(struct bnx2x_softc *sc)
5115 struct host_sp_status_block *def_sb = sc->def_sb;
5116 rte_iova_t mapping = sc->def_sb_dma.paddr;
5117 int igu_sp_sb_index;
5119 int port = SC_PORT(sc);
5120 int func = SC_FUNC(sc);
5121 int reg_offset, reg_offset_en5;
5124 struct hc_sp_status_block_data sp_sb_data;
5126 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5128 if (CHIP_INT_MODE_IS_BC(sc)) {
5129 igu_sp_sb_index = DEF_SB_IGU_ID;
5130 igu_seg_id = HC_SEG_ACCESS_DEF;
5132 igu_sp_sb_index = sc->igu_dsb_id;
5133 igu_seg_id = IGU_SEG_ACCESS_DEF;
5137 section = ((uint64_t) mapping +
5138 offsetof(struct host_sp_status_block, atten_status_block));
5139 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5142 reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5143 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
5145 reg_offset_en5 = (port) ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5146 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0;
5148 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5149 /* take care of sig[0]..sig[4] */
5150 for (sindex = 0; sindex < 4; sindex++) {
5151 sc->attn_group[index].sig[sindex] =
5153 (reg_offset + (sindex * 0x4) +
5157 if (!CHIP_IS_E1x(sc)) {
5159 * enable5 is separate from the rest of the registers,
5160 * and the address skip is 4 and not 16 between the
5163 sc->attn_group[index].sig[4] =
5164 REG_RD(sc, (reg_offset_en5 + (0x4 * index)));
5166 sc->attn_group[index].sig[4] = 0;
5170 if (sc->devinfo.int_block == INT_BLOCK_HC) {
5172 port ? HC_REG_ATTN_MSG1_ADDR_L : HC_REG_ATTN_MSG0_ADDR_L;
5173 REG_WR(sc, reg_offset, U64_LO(section));
5174 REG_WR(sc, (reg_offset + 4), U64_HI(section));
5175 } else if (!CHIP_IS_E1x(sc)) {
5176 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5177 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5180 section = ((uint64_t) mapping +
5181 offsetof(struct host_sp_status_block, sp_sb));
5183 bnx2x_zero_sp_sb(sc);
5185 /* PCI guarantees endianity of regpair */
5186 sp_sb_data.state = SB_ENABLED;
5187 sp_sb_data.host_sb_addr.lo = U64_LO(section);
5188 sp_sb_data.host_sb_addr.hi = U64_HI(section);
5189 sp_sb_data.igu_sb_id = igu_sp_sb_index;
5190 sp_sb_data.igu_seg_id = igu_seg_id;
5191 sp_sb_data.p_func.pf_id = func;
5192 sp_sb_data.p_func.vnic_id = SC_VN(sc);
5193 sp_sb_data.p_func.vf_id = 0xff;
5195 bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
5197 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5200 static void bnx2x_init_sp_ring(struct bnx2x_softc *sc)
5202 atomic_store_rel_long(&sc->cq_spq_left, MAX_SPQ_PENDING);
5203 sc->spq_prod_idx = 0;
5205 &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_ETH_DEF_CONS];
5206 sc->spq_prod_bd = sc->spq;
5207 sc->spq_last_bd = (sc->spq_prod_bd + MAX_SP_DESC_CNT);
5210 static void bnx2x_init_eq_ring(struct bnx2x_softc *sc)
5212 union event_ring_elem *elem;
5215 for (i = 1; i <= NUM_EQ_PAGES; i++) {
5216 elem = &sc->eq[EQ_DESC_CNT_PAGE * i - 1];
5218 elem->next_page.addr.hi = htole32(U64_HI(sc->eq_dma.paddr +
5220 (i % NUM_EQ_PAGES)));
5221 elem->next_page.addr.lo = htole32(U64_LO(sc->eq_dma.paddr +
5223 (i % NUM_EQ_PAGES)));
5227 sc->eq_prod = NUM_EQ_DESC;
5228 sc->eq_cons_sb = &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_EQ_CONS];
5230 atomic_store_rel_long(&sc->eq_spq_left,
5231 (min((MAX_SP_DESC_CNT - MAX_SPQ_PENDING),
5235 static void bnx2x_init_internal_common(struct bnx2x_softc *sc)
5241 * In switch independent mode, the TSTORM needs to accept
5242 * packets that failed classification, since approximate match
5243 * mac addresses aren't written to NIG LLH.
5246 (BAR_TSTRORM_INTMEM +
5247 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 2);
5250 (BAR_TSTRORM_INTMEM +
5251 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 0);
5254 * Zero this manually as its initialization is currently missing
5257 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) {
5259 (BAR_USTRORM_INTMEM + USTORM_AGG_DATA_OFFSET + (i * 4)),
5263 if (!CHIP_IS_E1x(sc)) {
5264 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET),
5265 CHIP_INT_MODE_IS_BC(sc) ? HC_IGU_BC_MODE :
5270 static void bnx2x_init_internal(struct bnx2x_softc *sc, uint32_t load_code)
5272 switch (load_code) {
5273 case FW_MSG_CODE_DRV_LOAD_COMMON:
5274 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5275 bnx2x_init_internal_common(sc);
5278 case FW_MSG_CODE_DRV_LOAD_PORT:
5282 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5283 /* internal memory per function is initialized inside bnx2x_pf_init */
5287 PMD_DRV_LOG(NOTICE, sc, "Unknown load_code (0x%x) from MCP",
5294 storm_memset_func_cfg(struct bnx2x_softc *sc,
5295 struct tstorm_eth_function_common_config *tcfg,
5301 addr = (BAR_TSTRORM_INTMEM +
5302 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid));
5303 size = sizeof(struct tstorm_eth_function_common_config);
5304 ecore_storm_memset_struct(sc, addr, size, (uint32_t *) tcfg);
5307 static void bnx2x_func_init(struct bnx2x_softc *sc, struct bnx2x_func_init_params *p)
5309 struct tstorm_eth_function_common_config tcfg = { 0 };
5311 if (CHIP_IS_E1x(sc)) {
5312 storm_memset_func_cfg(sc, &tcfg, p->func_id);
5315 /* Enable the function in the FW */
5316 storm_memset_vf_to_pf(sc, p->func_id, p->pf_id);
5317 storm_memset_func_en(sc, p->func_id, 1);
5320 if (p->func_flgs & FUNC_FLG_SPQ) {
5321 storm_memset_spq_addr(sc, p->spq_map, p->func_id);
5323 (XSEM_REG_FAST_MEMORY +
5324 XSTORM_SPQ_PROD_OFFSET(p->func_id)), p->spq_prod);
5329 * Calculates the sum of vn_min_rates.
5330 * It's needed for further normalizing of the min_rates.
5332 * sum of vn_min_rates.
5334 * 0 - if all the min_rates are 0.
5335 * In the later case fainess algorithm should be deactivated.
5336 * If all min rates are not zero then those that are zeroes will be set to 1.
5338 static void bnx2x_calc_vn_min(struct bnx2x_softc *sc, struct cmng_init_input *input)
5341 uint32_t vn_min_rate;
5345 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5346 vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5347 vn_min_rate = (((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
5348 FUNC_MF_CFG_MIN_BW_SHIFT) * 100);
5350 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5351 /* skip hidden VNs */
5353 } else if (!vn_min_rate) {
5354 /* If min rate is zero - set it to 100 */
5355 vn_min_rate = DEF_MIN_RATE;
5360 input->vnic_min_rate[vn] = vn_min_rate;
5363 /* if ETS or all min rates are zeros - disable fairness */
5365 input->flags.cmng_enables &= ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5367 input->flags.cmng_enables |= CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5372 bnx2x_extract_max_cfg(__rte_unused struct bnx2x_softc *sc, uint32_t mf_cfg)
5374 uint16_t max_cfg = ((mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
5375 FUNC_MF_CFG_MAX_BW_SHIFT);
5378 PMD_DRV_LOG(DEBUG, sc,
5379 "Max BW configured to 0 - using 100 instead");
5387 bnx2x_calc_vn_max(struct bnx2x_softc *sc, int vn, struct cmng_init_input *input)
5389 uint16_t vn_max_rate;
5390 uint32_t vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5393 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5396 max_cfg = bnx2x_extract_max_cfg(sc, vn_cfg);
5399 /* max_cfg in percents of linkspeed */
5401 ((sc->link_vars.line_speed * max_cfg) / 100);
5402 } else { /* SD modes */
5403 /* max_cfg is absolute in 100Mb units */
5404 vn_max_rate = (max_cfg * 100);
5408 input->vnic_max_rate[vn] = vn_max_rate;
5412 bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg, uint8_t cmng_type)
5414 struct cmng_init_input input;
5417 memset(&input, 0, sizeof(struct cmng_init_input));
5419 input.port_rate = sc->link_vars.line_speed;
5421 if (cmng_type == CMNG_FNS_MINMAX) {
5422 /* read mf conf from shmem */
5424 bnx2x_read_mf_cfg(sc);
5427 /* get VN min rate and enable fairness if not 0 */
5428 bnx2x_calc_vn_min(sc, &input);
5430 /* get VN max rate */
5432 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5433 bnx2x_calc_vn_max(sc, vn, &input);
5437 /* always enable rate shaping and fairness */
5438 input.flags.cmng_enables |= CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
5440 ecore_init_cmng(&input, &sc->cmng);
5445 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc)
5447 if (CHIP_REV_IS_SLOW(sc)) {
5448 return CMNG_FNS_NONE;
5452 return CMNG_FNS_MINMAX;
5455 return CMNG_FNS_NONE;
5459 storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng, uint8_t port)
5466 addr = (BAR_XSTRORM_INTMEM + XSTORM_CMNG_PER_PORT_VARS_OFFSET(port));
5467 size = sizeof(struct cmng_struct_per_port);
5468 ecore_storm_memset_struct(sc, addr, size, (uint32_t *) & cmng->port);
5470 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5471 func = func_by_vn(sc, vn);
5473 addr = (BAR_XSTRORM_INTMEM +
5474 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func));
5475 size = sizeof(struct rate_shaping_vars_per_vn);
5476 ecore_storm_memset_struct(sc, addr, size,
5477 (uint32_t *) & cmng->
5478 vnic.vnic_max_rate[vn]);
5480 addr = (BAR_XSTRORM_INTMEM +
5481 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func));
5482 size = sizeof(struct fairness_vars_per_vn);
5483 ecore_storm_memset_struct(sc, addr, size,
5484 (uint32_t *) & cmng->
5485 vnic.vnic_min_rate[vn]);
5489 static void bnx2x_pf_init(struct bnx2x_softc *sc)
5491 struct bnx2x_func_init_params func_init;
5492 struct event_ring_data eq_data;
5495 memset(&eq_data, 0, sizeof(struct event_ring_data));
5496 memset(&func_init, 0, sizeof(struct bnx2x_func_init_params));
5498 if (!CHIP_IS_E1x(sc)) {
5499 /* reset IGU PF statistics: MSIX + ATTN */
5502 (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5503 (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5504 ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5508 (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5509 (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5510 (BNX2X_IGU_STAS_MSG_PF_CNT * 4) +
5511 ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5515 /* function setup flags */
5516 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
5518 func_init.func_flgs = flags;
5519 func_init.pf_id = SC_FUNC(sc);
5520 func_init.func_id = SC_FUNC(sc);
5521 func_init.spq_map = sc->spq_dma.paddr;
5522 func_init.spq_prod = sc->spq_prod_idx;
5524 bnx2x_func_init(sc, &func_init);
5526 memset(&sc->cmng, 0, sizeof(struct cmng_struct_per_port));
5529 * Congestion management values depend on the link rate.
5530 * There is no active link so initial link rate is set to 10Gbps.
5531 * When the link comes up the congestion management values are
5532 * re-calculated according to the actual link rate.
5534 sc->link_vars.line_speed = SPEED_10000;
5535 bnx2x_cmng_fns_init(sc, TRUE, bnx2x_get_cmng_fns_mode(sc));
5537 /* Only the PMF sets the HW */
5539 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
5542 /* init Event Queue - PCI bus guarantees correct endainity */
5543 eq_data.base_addr.hi = U64_HI(sc->eq_dma.paddr);
5544 eq_data.base_addr.lo = U64_LO(sc->eq_dma.paddr);
5545 eq_data.producer = sc->eq_prod;
5546 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
5547 eq_data.sb_id = DEF_SB_ID;
5548 storm_memset_eq_data(sc, &eq_data, SC_FUNC(sc));
5551 static void bnx2x_hc_int_enable(struct bnx2x_softc *sc)
5553 int port = SC_PORT(sc);
5554 uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5555 uint32_t val = REG_RD(sc, addr);
5556 uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5557 || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5558 uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5559 uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5562 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5563 HC_CONFIG_0_REG_INT_LINE_EN_0);
5564 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5565 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5567 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
5570 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
5571 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5572 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5573 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5575 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5576 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5577 HC_CONFIG_0_REG_INT_LINE_EN_0 |
5578 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5580 REG_WR(sc, addr, val);
5582 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
5585 REG_WR(sc, addr, val);
5587 /* ensure that HC_CONFIG is written before leading/trailing edge config */
5590 /* init leading/trailing edge */
5592 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5594 /* enable nig and gpio3 attention */
5601 REG_WR(sc, (HC_REG_TRAILING_EDGE_0 + port * 8), val);
5602 REG_WR(sc, (HC_REG_LEADING_EDGE_0 + port * 8), val);
5604 /* make sure that interrupts are indeed enabled from here on */
5608 static void bnx2x_igu_int_enable(struct bnx2x_softc *sc)
5611 uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5612 || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5613 uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5614 uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5616 val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5619 val &= ~(IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5620 val |= (IGU_PF_CONF_MSI_MSIX_EN | IGU_PF_CONF_ATTN_BIT_EN);
5622 val |= IGU_PF_CONF_SINGLE_ISR_EN;
5625 val &= ~IGU_PF_CONF_INT_LINE_EN;
5626 val |= (IGU_PF_CONF_MSI_MSIX_EN |
5627 IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5629 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
5630 val |= (IGU_PF_CONF_INT_LINE_EN |
5631 IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5634 /* clean previous status - need to configure igu prior to ack */
5635 if ((!msix) || single_msix) {
5636 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5640 val |= IGU_PF_CONF_FUNC_EN;
5642 PMD_DRV_LOG(DEBUG, sc, "write 0x%x to IGU mode %s",
5643 val, ((msix) ? "MSI-X" : ((msi) ? "MSI" : "INTx")));
5645 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5649 /* init leading/trailing edge */
5651 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5653 /* enable nig and gpio3 attention */
5660 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
5661 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
5663 /* make sure that interrupts are indeed enabled from here on */
5667 static void bnx2x_int_enable(struct bnx2x_softc *sc)
5669 if (sc->devinfo.int_block == INT_BLOCK_HC) {
5670 bnx2x_hc_int_enable(sc);
5672 bnx2x_igu_int_enable(sc);
5676 static void bnx2x_hc_int_disable(struct bnx2x_softc *sc)
5678 int port = SC_PORT(sc);
5679 uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5680 uint32_t val = REG_RD(sc, addr);
5682 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5683 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5684 HC_CONFIG_0_REG_INT_LINE_EN_0 | HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5685 /* flush all outstanding writes */
5688 REG_WR(sc, addr, val);
5689 if (REG_RD(sc, addr) != val) {
5690 PMD_DRV_LOG(ERR, sc, "proper val not read from HC IGU!");
5694 static void bnx2x_igu_int_disable(struct bnx2x_softc *sc)
5696 uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5698 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
5699 IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_ATTN_BIT_EN);
5701 PMD_DRV_LOG(DEBUG, sc, "write %x to IGU", val);
5703 /* flush all outstanding writes */
5706 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5707 if (REG_RD(sc, IGU_REG_PF_CONFIGURATION) != val) {
5708 PMD_DRV_LOG(ERR, sc, "proper val not read from IGU!");
5712 static void bnx2x_int_disable(struct bnx2x_softc *sc)
5714 if (sc->devinfo.int_block == INT_BLOCK_HC) {
5715 bnx2x_hc_int_disable(sc);
5717 bnx2x_igu_int_disable(sc);
5721 static void bnx2x_nic_init(struct bnx2x_softc *sc, int load_code)
5725 PMD_INIT_FUNC_TRACE(sc);
5727 for (i = 0; i < sc->num_queues; i++) {
5728 bnx2x_init_eth_fp(sc, i);
5731 rmb(); /* ensure status block indices were read */
5733 bnx2x_init_rx_rings(sc);
5734 bnx2x_init_tx_rings(sc);
5737 bnx2x_memset_stats(sc);
5741 /* initialize MOD_ABS interrupts */
5742 elink_init_mod_abs_int(sc, &sc->link_vars,
5743 sc->devinfo.chip_id,
5744 sc->devinfo.shmem_base,
5745 sc->devinfo.shmem2_base, SC_PORT(sc));
5747 bnx2x_init_def_sb(sc);
5748 bnx2x_update_dsb_idx(sc);
5749 bnx2x_init_sp_ring(sc);
5750 bnx2x_init_eq_ring(sc);
5751 bnx2x_init_internal(sc, load_code);
5753 bnx2x_stats_init(sc);
5755 /* flush all before enabling interrupts */
5758 bnx2x_int_enable(sc);
5760 /* check for SPIO5 */
5761 bnx2x_attn_int_deasserted0(sc,
5763 (MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
5765 AEU_INPUTS_ATTN_BITS_SPIO5);
5768 static void bnx2x_init_objs(struct bnx2x_softc *sc)
5770 /* mcast rules must be added to tx if tx switching is enabled */
5771 ecore_obj_type o_type;
5772 if (sc->flags & BNX2X_TX_SWITCHING)
5773 o_type = ECORE_OBJ_TYPE_RX_TX;
5775 o_type = ECORE_OBJ_TYPE_RX;
5777 /* RX_MODE controlling object */
5778 ecore_init_rx_mode_obj(sc, &sc->rx_mode_obj);
5780 /* multicast configuration controlling object */
5781 ecore_init_mcast_obj(sc,
5787 BNX2X_SP(sc, mcast_rdata),
5788 (rte_iova_t)BNX2X_SP_MAPPING(sc, mcast_rdata),
5789 ECORE_FILTER_MCAST_PENDING,
5790 &sc->sp_state, o_type);
5792 /* Setup CAM credit pools */
5793 ecore_init_mac_credit_pool(sc,
5796 CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5797 VNICS_PER_PATH(sc));
5799 ecore_init_vlan_credit_pool(sc,
5801 SC_ABS_FUNC(sc) >> 1,
5802 CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5803 VNICS_PER_PATH(sc));
5805 /* RSS configuration object */
5806 ecore_init_rss_config_obj(&sc->rss_conf_obj,
5811 BNX2X_SP(sc, rss_rdata),
5812 (rte_iova_t)BNX2X_SP_MAPPING(sc, rss_rdata),
5813 ECORE_FILTER_RSS_CONF_PENDING,
5814 &sc->sp_state, ECORE_OBJ_TYPE_RX);
5818 * Initialize the function. This must be called before sending CLIENT_SETUP
5819 * for the first client.
5821 static int bnx2x_func_start(struct bnx2x_softc *sc)
5823 struct ecore_func_state_params func_params = { NULL };
5824 struct ecore_func_start_params *start_params =
5825 &func_params.params.start;
5827 /* Prepare parameters for function state transitions */
5828 bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
5830 func_params.f_obj = &sc->func_obj;
5831 func_params.cmd = ECORE_F_CMD_START;
5833 /* Function parameters */
5834 start_params->mf_mode = sc->devinfo.mf_info.mf_mode;
5835 start_params->sd_vlan_tag = OVLAN(sc);
5837 if (CHIP_IS_E2(sc) || CHIP_IS_E3(sc)) {
5838 start_params->network_cos_mode = STATIC_COS;
5839 } else { /* CHIP_IS_E1X */
5840 start_params->network_cos_mode = FW_WRR;
5843 start_params->gre_tunnel_mode = 0;
5844 start_params->gre_tunnel_rss = 0;
5846 return ecore_func_state_change(sc, &func_params);
5849 static int bnx2x_set_power_state(struct bnx2x_softc *sc, uint8_t state)
5853 /* If there is no power capability, silently succeed */
5854 if (!(sc->devinfo.pcie_cap_flags & BNX2X_PM_CAPABLE_FLAG)) {
5855 PMD_DRV_LOG(INFO, sc, "No power capability");
5859 pci_read(sc, (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS), &pmcsr,
5865 (sc->devinfo.pcie_pm_cap_reg +
5867 ((pmcsr & ~PCIM_PSTAT_DMASK) | PCIM_PSTAT_PME));
5869 if (pmcsr & PCIM_PSTAT_DMASK) {
5870 /* delay required during transition out of D3hot */
5877 /* don't shut down the power for emulation and FPGA */
5878 if (CHIP_REV_IS_SLOW(sc)) {
5882 pmcsr &= ~PCIM_PSTAT_DMASK;
5883 pmcsr |= PCIM_PSTAT_D3;
5886 pmcsr |= PCIM_PSTAT_PMEENABLE;
5890 (sc->devinfo.pcie_pm_cap_reg +
5891 PCIR_POWER_STATUS), pmcsr);
5894 * No more memory access after this point until device is brought back
5900 PMD_DRV_LOG(NOTICE, sc, "Can't support PCI power state = %d",
5908 /* return true if succeeded to acquire the lock */
5909 static uint8_t bnx2x_trylock_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
5911 uint32_t lock_status;
5912 uint32_t resource_bit = (1 << resource);
5913 int func = SC_FUNC(sc);
5914 uint32_t hw_lock_control_reg;
5916 /* Validating that the resource is within range */
5917 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
5918 PMD_DRV_LOG(INFO, sc,
5919 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)",
5920 resource, HW_LOCK_MAX_RESOURCE_VALUE);
5925 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func * 8);
5927 hw_lock_control_reg =
5928 (MISC_REG_DRIVER_CONTROL_7 + (func - 6) * 8);
5931 /* try to acquire the lock */
5932 REG_WR(sc, hw_lock_control_reg + 4, resource_bit);
5933 lock_status = REG_RD(sc, hw_lock_control_reg);
5934 if (lock_status & resource_bit) {
5938 PMD_DRV_LOG(NOTICE, sc, "Failed to get a resource lock 0x%x", resource);
5944 * Get the recovery leader resource id according to the engine this function
5945 * belongs to. Currently only only 2 engines is supported.
5947 static int bnx2x_get_leader_lock_resource(struct bnx2x_softc *sc)
5950 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
5952 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
5956 /* try to acquire a leader lock for current engine */
5957 static uint8_t bnx2x_trylock_leader_lock(struct bnx2x_softc *sc)
5959 return bnx2x_trylock_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5962 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc)
5964 return bnx2x_release_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5967 /* close gates #2, #3 and #4 */
5968 static void bnx2x_set_234_gates(struct bnx2x_softc *sc, uint8_t close)
5972 /* gates #2 and #4a are closed/opened */
5974 REG_WR(sc, PXP_REG_HST_DISCARD_DOORBELLS, ! !close);
5976 REG_WR(sc, PXP_REG_HST_DISCARD_INTERNAL_WRITES, ! !close);
5979 if (CHIP_IS_E1x(sc)) {
5980 /* prevent interrupts from HC on both ports */
5981 val = REG_RD(sc, HC_REG_CONFIG_1);
5983 REG_WR(sc, HC_REG_CONFIG_1, (val & ~(uint32_t)
5984 HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5986 REG_WR(sc, HC_REG_CONFIG_1,
5987 (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5989 val = REG_RD(sc, HC_REG_CONFIG_0);
5991 REG_WR(sc, HC_REG_CONFIG_0, (val & ~(uint32_t)
5992 HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5994 REG_WR(sc, HC_REG_CONFIG_0,
5995 (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5998 /* Prevent incoming interrupts in IGU */
5999 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
6002 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
6004 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
6006 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
6008 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
6014 /* poll for pending writes bit, it should get cleared in no more than 1s */
6015 static int bnx2x_er_poll_igu_vq(struct bnx2x_softc *sc)
6017 uint32_t cnt = 1000;
6018 uint32_t pend_bits = 0;
6021 pend_bits = REG_RD(sc, IGU_REG_PENDING_BITS_STATUS);
6023 if (pend_bits == 0) {
6028 } while (cnt-- > 0);
6031 PMD_DRV_LOG(NOTICE, sc, "Still pending IGU requests bits=0x%08x!",
6039 #define SHARED_MF_CLP_MAGIC 0x80000000 /* 'magic' bit */
6041 static void bnx2x_clp_reset_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
6043 /* Do some magic... */
6044 uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
6045 *magic_val = val & SHARED_MF_CLP_MAGIC;
6046 MFCFG_WR(sc, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
6049 /* restore the value of the 'magic' bit */
6050 static void bnx2x_clp_reset_done(struct bnx2x_softc *sc, uint32_t magic_val)
6052 /* Restore the 'magic' bit value... */
6053 uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
6054 MFCFG_WR(sc, shared_mf_config.clp_mb,
6055 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
6058 /* prepare for MCP reset, takes care of CLP configurations */
6059 static void bnx2x_reset_mcp_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
6062 uint32_t validity_offset;
6064 /* set `magic' bit in order to save MF config */
6065 bnx2x_clp_reset_prep(sc, magic_val);
6067 /* get shmem offset */
6068 shmem = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
6070 offsetof(struct shmem_region, validity_map[SC_PORT(sc)]);
6072 /* Clear validity map flags */
6074 REG_WR(sc, shmem + validity_offset, 0);
6078 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
6079 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
6081 static void bnx2x_mcp_wait_one(struct bnx2x_softc *sc)
6083 /* special handling for emulation and FPGA (10 times longer) */
6084 if (CHIP_REV_IS_SLOW(sc)) {
6085 DELAY((MCP_ONE_TIMEOUT * 10) * 1000);
6087 DELAY((MCP_ONE_TIMEOUT) * 1000);
6091 /* initialize shmem_base and waits for validity signature to appear */
6092 static int bnx2x_init_shmem(struct bnx2x_softc *sc)
6098 sc->devinfo.shmem_base =
6099 sc->link_params.shmem_base =
6100 REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
6102 if (sc->devinfo.shmem_base) {
6103 val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
6104 if (val & SHR_MEM_VALIDITY_MB)
6108 bnx2x_mcp_wait_one(sc);
6110 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
6112 PMD_DRV_LOG(NOTICE, sc, "BAD MCP validity signature");
6117 static int bnx2x_reset_mcp_comp(struct bnx2x_softc *sc, uint32_t magic_val)
6119 int rc = bnx2x_init_shmem(sc);
6121 /* Restore the `magic' bit value */
6122 bnx2x_clp_reset_done(sc, magic_val);
6127 static void bnx2x_pxp_prep(struct bnx2x_softc *sc)
6129 REG_WR(sc, PXP2_REG_RD_START_INIT, 0);
6130 REG_WR(sc, PXP2_REG_RQ_RBC_DONE, 0);
6135 * Reset the whole chip except for:
6137 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by one reset bit)
6139 * - MISC (including AEU)
6143 static void bnx2x_process_kill_chip_reset(struct bnx2x_softc *sc, uint8_t global)
6145 uint32_t not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
6146 uint32_t global_bits2, stay_reset2;
6149 * Bits that have to be set in reset_mask2 if we want to reset 'global'
6150 * (per chip) blocks.
6153 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
6154 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
6157 * Don't reset the following blocks.
6158 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
6159 * reset, as in 4 port device they might still be owned
6160 * by the MCP (there is only one leader per path).
6163 MISC_REGISTERS_RESET_REG_1_RST_HC |
6164 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
6165 MISC_REGISTERS_RESET_REG_1_RST_PXP;
6168 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
6169 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
6170 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
6171 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
6172 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
6173 MISC_REGISTERS_RESET_REG_2_RST_GRC |
6174 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
6175 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
6176 MISC_REGISTERS_RESET_REG_2_RST_ATC |
6177 MISC_REGISTERS_RESET_REG_2_PGLC |
6178 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
6179 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
6180 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
6181 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
6182 MISC_REGISTERS_RESET_REG_2_UMAC0 | MISC_REGISTERS_RESET_REG_2_UMAC1;
6185 * Keep the following blocks in reset:
6186 * - all xxMACs are handled by the elink code.
6189 MISC_REGISTERS_RESET_REG_2_XMAC |
6190 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
6192 /* Full reset masks according to the chip */
6193 reset_mask1 = 0xffffffff;
6195 if (CHIP_IS_E1H(sc))
6196 reset_mask2 = 0x1ffff;
6197 else if (CHIP_IS_E2(sc))
6198 reset_mask2 = 0xfffff;
6199 else /* CHIP_IS_E3 */
6200 reset_mask2 = 0x3ffffff;
6202 /* Don't reset global blocks unless we need to */
6204 reset_mask2 &= ~global_bits2;
6207 * In case of attention in the QM, we need to reset PXP
6208 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
6209 * because otherwise QM reset would release 'close the gates' shortly
6210 * before resetting the PXP, then the PSWRQ would send a write
6211 * request to PGLUE. Then when PXP is reset, PGLUE would try to
6212 * read the payload data from PSWWR, but PSWWR would not
6213 * respond. The write queue in PGLUE would stuck, dmae commands
6214 * would not return. Therefore it's important to reset the second
6215 * reset register (containing the
6216 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
6217 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
6220 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
6221 reset_mask2 & (~not_reset_mask2));
6223 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6224 reset_mask1 & (~not_reset_mask1));
6229 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
6230 reset_mask2 & (~stay_reset2));
6235 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
6239 static int bnx2x_process_kill(struct bnx2x_softc *sc, uint8_t global)
6243 uint32_t sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
6244 uint32_t tags_63_32 = 0;
6246 /* Empty the Tetris buffer, wait for 1s */
6248 sr_cnt = REG_RD(sc, PXP2_REG_RD_SR_CNT);
6249 blk_cnt = REG_RD(sc, PXP2_REG_RD_BLK_CNT);
6250 port_is_idle_0 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_0);
6251 port_is_idle_1 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_1);
6252 pgl_exp_rom2 = REG_RD(sc, PXP2_REG_PGL_EXP_ROM2);
6253 if (CHIP_IS_E3(sc)) {
6254 tags_63_32 = REG_RD(sc, PGLUE_B_REG_TAGS_63_32);
6257 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
6258 ((port_is_idle_0 & 0x1) == 0x1) &&
6259 ((port_is_idle_1 & 0x1) == 0x1) &&
6260 (pgl_exp_rom2 == 0xffffffff) &&
6261 (!CHIP_IS_E3(sc) || (tags_63_32 == 0xffffffff)))
6264 } while (cnt-- > 0);
6267 PMD_DRV_LOG(NOTICE, sc,
6268 "ERROR: Tetris buffer didn't get empty or there "
6269 "are still outstanding read requests after 1s! "
6270 "sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, "
6271 "port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x",
6272 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
6279 /* Close gates #2, #3 and #4 */
6280 bnx2x_set_234_gates(sc, TRUE);
6282 /* Poll for IGU VQs for 57712 and newer chips */
6283 if (!CHIP_IS_E1x(sc) && bnx2x_er_poll_igu_vq(sc)) {
6287 /* clear "unprepared" bit */
6288 REG_WR(sc, MISC_REG_UNPREPARED, 0);
6291 /* Make sure all is written to the chip before the reset */
6295 * Wait for 1ms to empty GLUE and PCI-E core queues,
6296 * PSWHST, GRC and PSWRD Tetris buffer.
6300 /* Prepare to chip reset: */
6303 bnx2x_reset_mcp_prep(sc, &val);
6310 /* reset the chip */
6311 bnx2x_process_kill_chip_reset(sc, global);
6314 /* Recover after reset: */
6316 if (global && bnx2x_reset_mcp_comp(sc, val)) {
6320 /* Open the gates #2, #3 and #4 */
6321 bnx2x_set_234_gates(sc, FALSE);
6326 static int bnx2x_leader_reset(struct bnx2x_softc *sc)
6329 uint8_t global = bnx2x_reset_is_global(sc);
6333 * If not going to reset MCP, load "fake" driver to reset HW while
6334 * driver is owner of the HW.
6336 if (!global && !BNX2X_NOMCP(sc)) {
6337 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
6338 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
6340 PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
6342 goto exit_leader_reset;
6345 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
6346 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
6347 PMD_DRV_LOG(NOTICE, sc,
6348 "MCP unexpected response, aborting");
6350 goto exit_leader_reset2;
6353 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
6355 PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
6357 goto exit_leader_reset2;
6361 /* try to recover after the failure */
6362 if (bnx2x_process_kill(sc, global)) {
6363 PMD_DRV_LOG(NOTICE, sc, "Something bad occurred on engine %d!",
6366 goto exit_leader_reset2;
6370 * Clear the RESET_IN_PROGRESS and RESET_GLOBAL bits and update the driver
6373 bnx2x_set_reset_done(sc);
6375 bnx2x_clear_reset_global(sc);
6380 /* unload "fake driver" if it was loaded */
6381 if (!global &&!BNX2X_NOMCP(sc)) {
6382 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
6383 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
6389 bnx2x_release_leader_lock(sc);
6396 * prepare INIT transition, parameters configured:
6397 * - HC configuration
6398 * - Queue's CDU context
6401 bnx2x_pf_q_prep_init(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6402 struct ecore_queue_init_params *init_params)
6405 int cxt_index, cxt_offset;
6407 bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->rx.flags);
6408 bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->tx.flags);
6410 bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->rx.flags);
6411 bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->tx.flags);
6414 init_params->rx.hc_rate =
6415 sc->hc_rx_ticks ? (1000000 / sc->hc_rx_ticks) : 0;
6416 init_params->tx.hc_rate =
6417 sc->hc_tx_ticks ? (1000000 / sc->hc_tx_ticks) : 0;
6420 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = fp->fw_sb_id;
6422 /* CQ index among the SB indices */
6423 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6424 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
6426 /* set maximum number of COSs supported by this queue */
6427 init_params->max_cos = sc->max_cos;
6429 /* set the context pointers queue object */
6430 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
6431 cxt_index = fp->index / ILT_PAGE_CIDS;
6432 cxt_offset = fp->index - (cxt_index * ILT_PAGE_CIDS);
6433 init_params->cxts[cos] =
6434 &sc->context[cxt_index].vcxt[cxt_offset].eth;
6438 /* set flags that are common for the Tx-only and not normal connections */
6439 static unsigned long
6440 bnx2x_get_common_flags(struct bnx2x_softc *sc, uint8_t zero_stats)
6442 unsigned long flags = 0;
6444 /* PF driver will always initialize the Queue to an ACTIVE state */
6445 bnx2x_set_bit(ECORE_Q_FLG_ACTIVE, &flags);
6448 * tx only connections collect statistics (on the same index as the
6449 * parent connection). The statistics are zeroed when the parent
6450 * connection is initialized.
6453 bnx2x_set_bit(ECORE_Q_FLG_STATS, &flags);
6455 bnx2x_set_bit(ECORE_Q_FLG_ZERO_STATS, &flags);
6459 * tx only connections can support tx-switching, though their
6460 * CoS-ness doesn't survive the loopback
6462 if (sc->flags & BNX2X_TX_SWITCHING) {
6463 bnx2x_set_bit(ECORE_Q_FLG_TX_SWITCH, &flags);
6466 bnx2x_set_bit(ECORE_Q_FLG_PCSUM_ON_PKT, &flags);
6471 static unsigned long bnx2x_get_q_flags(struct bnx2x_softc *sc, uint8_t leading)
6473 unsigned long flags = 0;
6476 bnx2x_set_bit(ECORE_Q_FLG_OV, &flags);
6480 bnx2x_set_bit(ECORE_Q_FLG_LEADING_RSS, &flags);
6481 bnx2x_set_bit(ECORE_Q_FLG_MCAST, &flags);
6484 bnx2x_set_bit(ECORE_Q_FLG_VLAN, &flags);
6486 /* merge with common flags */
6487 return flags | bnx2x_get_common_flags(sc, TRUE);
6491 bnx2x_pf_q_prep_general(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6492 struct ecore_general_setup_params *gen_init, uint8_t cos)
6494 gen_init->stat_id = bnx2x_stats_id(fp);
6495 gen_init->spcl_id = fp->cl_id;
6496 gen_init->mtu = sc->mtu;
6497 gen_init->cos = cos;
6501 bnx2x_pf_rx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6502 struct rxq_pause_params *pause,
6503 struct ecore_rxq_setup_params *rxq_init)
6505 struct bnx2x_rx_queue *rxq;
6507 rxq = sc->rx_queues[fp->index];
6509 PMD_RX_LOG(ERR, "RX queue is NULL");
6513 pause->bd_th_lo = BD_TH_LO(sc);
6514 pause->bd_th_hi = BD_TH_HI(sc);
6516 pause->rcq_th_lo = RCQ_TH_LO(sc);
6517 pause->rcq_th_hi = RCQ_TH_HI(sc);
6519 /* validate rings have enough entries to cross high thresholds */
6520 if (sc->dropless_fc &&
6521 pause->bd_th_hi + FW_PREFETCH_CNT > sc->rx_ring_size) {
6522 PMD_DRV_LOG(WARNING, sc, "rx bd ring threshold limit");
6525 if (sc->dropless_fc &&
6526 pause->rcq_th_hi + FW_PREFETCH_CNT > USABLE_RCQ_ENTRIES(rxq)) {
6527 PMD_DRV_LOG(WARNING, sc, "rcq ring threshold limit");
6533 rxq_init->dscr_map = (rte_iova_t)rxq->rx_ring_phys_addr;
6534 rxq_init->rcq_map = (rte_iova_t)rxq->cq_ring_phys_addr;
6535 rxq_init->rcq_np_map = (rte_iova_t)(rxq->cq_ring_phys_addr +
6539 * This should be a maximum number of data bytes that may be
6540 * placed on the BD (not including paddings).
6542 rxq_init->buf_sz = (fp->rx_buf_size - IP_HEADER_ALIGNMENT_PADDING);
6544 rxq_init->cl_qzone_id = fp->cl_qzone_id;
6545 rxq_init->rss_engine_id = SC_FUNC(sc);
6546 rxq_init->mcast_engine_id = SC_FUNC(sc);
6548 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
6549 rxq_init->fw_sb_id = fp->fw_sb_id;
6551 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6554 * configure silent vlan removal
6555 * if multi function mode is afex, then mask default vlan
6557 if (IS_MF_AFEX(sc)) {
6558 rxq_init->silent_removal_value =
6559 sc->devinfo.mf_info.afex_def_vlan_tag;
6560 rxq_init->silent_removal_mask = EVL_VLID_MASK;
6565 bnx2x_pf_tx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6566 struct ecore_txq_setup_params *txq_init, uint8_t cos)
6568 struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
6571 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
6574 txq_init->dscr_map = (rte_iova_t)txq->tx_ring_phys_addr;
6575 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
6576 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
6577 txq_init->fw_sb_id = fp->fw_sb_id;
6580 * set the TSS leading client id for TX classfication to the
6581 * leading RSS client id
6583 txq_init->tss_leading_cl_id = BNX2X_FP(sc, 0, cl_id);
6587 * This function performs 2 steps in a queue state machine:
6592 bnx2x_setup_queue(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp, uint8_t leading)
6594 struct ecore_queue_state_params q_params = { NULL };
6595 struct ecore_queue_setup_params *setup_params = &q_params.params.setup;
6598 PMD_DRV_LOG(DEBUG, sc, "setting up queue %d", fp->index);
6600 bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6602 q_params.q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
6604 /* we want to wait for completion in this context */
6605 bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
6607 /* prepare the INIT parameters */
6608 bnx2x_pf_q_prep_init(sc, fp, &q_params.params.init);
6610 /* Set the command */
6611 q_params.cmd = ECORE_Q_CMD_INIT;
6613 /* Change the state to INIT */
6614 rc = ecore_queue_state_change(sc, &q_params);
6616 PMD_DRV_LOG(NOTICE, sc, "Queue(%d) INIT failed", fp->index);
6620 PMD_DRV_LOG(DEBUG, sc, "init complete");
6622 /* now move the Queue to the SETUP state */
6623 memset(setup_params, 0, sizeof(*setup_params));
6625 /* set Queue flags */
6626 setup_params->flags = bnx2x_get_q_flags(sc, leading);
6628 /* set general SETUP parameters */
6629 bnx2x_pf_q_prep_general(sc, fp, &setup_params->gen_params,
6630 FIRST_TX_COS_INDEX);
6632 bnx2x_pf_rx_q_prep(sc, fp,
6633 &setup_params->pause_params,
6634 &setup_params->rxq_params);
6636 bnx2x_pf_tx_q_prep(sc, fp, &setup_params->txq_params, FIRST_TX_COS_INDEX);
6638 /* Set the command */
6639 q_params.cmd = ECORE_Q_CMD_SETUP;
6641 /* change the state to SETUP */
6642 rc = ecore_queue_state_change(sc, &q_params);
6644 PMD_DRV_LOG(NOTICE, sc, "Queue(%d) SETUP failed", fp->index);
6651 static int bnx2x_setup_leading(struct bnx2x_softc *sc)
6654 return bnx2x_setup_queue(sc, &sc->fp[0], TRUE);
6656 return bnx2x_vf_setup_queue(sc, &sc->fp[0], TRUE);
6660 bnx2x_config_rss_pf(struct bnx2x_softc *sc, struct ecore_rss_config_obj *rss_obj,
6661 uint8_t config_hash)
6663 struct ecore_config_rss_params params = { NULL };
6667 * Although RSS is meaningless when there is a single HW queue we
6668 * still need it enabled in order to have HW Rx hash generated.
6671 params.rss_obj = rss_obj;
6673 bnx2x_set_bit(RAMROD_COMP_WAIT, ¶ms.ramrod_flags);
6675 bnx2x_set_bit(ECORE_RSS_MODE_REGULAR, ¶ms.rss_flags);
6677 /* RSS configuration */
6678 bnx2x_set_bit(ECORE_RSS_IPV4, ¶ms.rss_flags);
6679 bnx2x_set_bit(ECORE_RSS_IPV4_TCP, ¶ms.rss_flags);
6680 bnx2x_set_bit(ECORE_RSS_IPV6, ¶ms.rss_flags);
6681 bnx2x_set_bit(ECORE_RSS_IPV6_TCP, ¶ms.rss_flags);
6682 if (rss_obj->udp_rss_v4) {
6683 bnx2x_set_bit(ECORE_RSS_IPV4_UDP, ¶ms.rss_flags);
6685 if (rss_obj->udp_rss_v6) {
6686 bnx2x_set_bit(ECORE_RSS_IPV6_UDP, ¶ms.rss_flags);
6690 params.rss_result_mask = MULTI_MASK;
6692 rte_memcpy(params.ind_table, rss_obj->ind_table,
6693 sizeof(params.ind_table));
6697 for (i = 0; i < sizeof(params.rss_key) / 4; i++) {
6698 params.rss_key[i] = (uint32_t) rte_rand();
6701 bnx2x_set_bit(ECORE_RSS_SET_SRCH, ¶ms.rss_flags);
6705 return ecore_config_rss(sc, ¶ms);
6707 return bnx2x_vf_config_rss(sc, ¶ms);
6710 static int bnx2x_config_rss_eth(struct bnx2x_softc *sc, uint8_t config_hash)
6712 return bnx2x_config_rss_pf(sc, &sc->rss_conf_obj, config_hash);
6715 static int bnx2x_init_rss_pf(struct bnx2x_softc *sc)
6717 uint8_t num_eth_queues = BNX2X_NUM_ETH_QUEUES(sc);
6721 * Prepare the initial contents of the indirection table if
6724 for (i = 0; i < sizeof(sc->rss_conf_obj.ind_table); i++) {
6725 sc->rss_conf_obj.ind_table[i] =
6726 (sc->fp->cl_id + (i % num_eth_queues));
6730 sc->rss_conf_obj.udp_rss_v4 = sc->rss_conf_obj.udp_rss_v6 = 1;
6734 * For 57711 SEARCHER configuration (rss_keys) is
6735 * per-port, so if explicit configuration is needed, do it only
6738 * For 57712 and newer it's a per-function configuration.
6740 return bnx2x_config_rss_eth(sc, sc->port.pmf || !CHIP_IS_E1x(sc));
6744 bnx2x_set_mac_one(struct bnx2x_softc *sc, uint8_t * mac,
6745 struct ecore_vlan_mac_obj *obj, uint8_t set, int mac_type,
6746 unsigned long *ramrod_flags)
6748 struct ecore_vlan_mac_ramrod_params ramrod_param;
6751 memset(&ramrod_param, 0, sizeof(ramrod_param));
6753 /* fill in general parameters */
6754 ramrod_param.vlan_mac_obj = obj;
6755 ramrod_param.ramrod_flags = *ramrod_flags;
6757 /* fill a user request section if needed */
6758 if (!bnx2x_test_bit(RAMROD_CONT, ramrod_flags)) {
6759 rte_memcpy(ramrod_param.user_req.u.mac.mac, mac,
6762 bnx2x_set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
6764 /* Set the command: ADD or DEL */
6765 ramrod_param.user_req.cmd = (set) ? ECORE_VLAN_MAC_ADD :
6769 rc = ecore_config_vlan_mac(sc, &ramrod_param);
6771 if (rc == ECORE_EXISTS) {
6772 PMD_DRV_LOG(INFO, sc, "Failed to schedule ADD operations (EEXIST)");
6773 /* do not treat adding same MAC as error */
6775 } else if (rc < 0) {
6776 PMD_DRV_LOG(ERR, sc,
6777 "%s MAC failed (%d)", (set ? "Set" : "Delete"), rc);
6783 static int bnx2x_set_eth_mac(struct bnx2x_softc *sc, uint8_t set)
6785 unsigned long ramrod_flags = 0;
6787 PMD_DRV_LOG(DEBUG, sc, "Adding Ethernet MAC");
6789 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
6791 /* Eth MAC is set on RSS leading client (fp[0]) */
6792 return bnx2x_set_mac_one(sc, sc->link_params.mac_addr,
6793 &sc->sp_objs->mac_obj,
6794 set, ECORE_ETH_MAC, &ramrod_flags);
6797 static int bnx2x_get_cur_phy_idx(struct bnx2x_softc *sc)
6799 uint32_t sel_phy_idx = 0;
6801 if (sc->link_params.num_phys <= 1) {
6802 return ELINK_INT_PHY;
6805 if (sc->link_vars.link_up) {
6806 sel_phy_idx = ELINK_EXT_PHY1;
6807 /* In case link is SERDES, check if the ELINK_EXT_PHY2 is the one */
6808 if ((sc->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
6809 (sc->link_params.phy[ELINK_EXT_PHY2].supported &
6810 ELINK_SUPPORTED_FIBRE))
6811 sel_phy_idx = ELINK_EXT_PHY2;
6813 switch (elink_phy_selection(&sc->link_params)) {
6814 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6815 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
6816 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6817 sel_phy_idx = ELINK_EXT_PHY1;
6819 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
6820 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6821 sel_phy_idx = ELINK_EXT_PHY2;
6829 static int bnx2x_get_link_cfg_idx(struct bnx2x_softc *sc)
6831 uint32_t sel_phy_idx = bnx2x_get_cur_phy_idx(sc);
6834 * The selected activated PHY is always after swapping (in case PHY
6835 * swapping is enabled). So when swapping is enabled, we need to reverse
6839 if (sc->link_params.multi_phy_config & PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
6840 if (sel_phy_idx == ELINK_EXT_PHY1)
6841 sel_phy_idx = ELINK_EXT_PHY2;
6842 else if (sel_phy_idx == ELINK_EXT_PHY2)
6843 sel_phy_idx = ELINK_EXT_PHY1;
6846 return ELINK_LINK_CONFIG_IDX(sel_phy_idx);
6849 static void bnx2x_set_requested_fc(struct bnx2x_softc *sc)
6852 * Initialize link parameters structure variables
6853 * It is recommended to turn off RX FC for jumbo frames
6854 * for better performance
6856 if (CHIP_IS_E1x(sc) && (sc->mtu > 5000)) {
6857 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_TX;
6859 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_BOTH;
6863 static void bnx2x_calc_fc_adv(struct bnx2x_softc *sc)
6865 uint8_t cfg_idx = bnx2x_get_link_cfg_idx(sc);
6866 switch (sc->link_vars.ieee_fc &
6867 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
6868 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
6870 sc->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
6874 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
6875 sc->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
6879 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
6880 sc->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
6885 static uint16_t bnx2x_get_mf_speed(struct bnx2x_softc *sc)
6887 uint16_t line_speed = sc->link_vars.line_speed;
6889 uint16_t maxCfg = bnx2x_extract_max_cfg(sc,
6891 mf_info.mf_config[SC_VN
6894 /* calculate the current MAX line speed limit for the MF devices */
6896 line_speed = (line_speed * maxCfg) / 100;
6897 } else { /* SD mode */
6898 uint16_t vn_max_rate = maxCfg * 100;
6900 if (vn_max_rate < line_speed) {
6901 line_speed = vn_max_rate;
6910 bnx2x_fill_report_data(struct bnx2x_softc *sc, struct bnx2x_link_report_data *data)
6912 uint16_t line_speed = bnx2x_get_mf_speed(sc);
6914 memset(data, 0, sizeof(*data));
6916 /* fill the report data with the effective line speed */
6917 data->line_speed = line_speed;
6920 if (!sc->link_vars.link_up || (sc->flags & BNX2X_MF_FUNC_DIS)) {
6921 bnx2x_set_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6922 &data->link_report_flags);
6926 if (sc->link_vars.duplex == DUPLEX_FULL) {
6927 bnx2x_set_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6928 &data->link_report_flags);
6931 /* Rx Flow Control is ON */
6932 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_RX) {
6933 bnx2x_set_bit(BNX2X_LINK_REPORT_RX_FC_ON, &data->link_report_flags);
6936 /* Tx Flow Control is ON */
6937 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
6938 bnx2x_set_bit(BNX2X_LINK_REPORT_TX_FC_ON, &data->link_report_flags);
6942 /* report link status to OS, should be called under phy_lock */
6943 static void bnx2x_link_report_locked(struct bnx2x_softc *sc)
6945 struct bnx2x_link_report_data cur_data;
6949 bnx2x_read_mf_cfg(sc);
6952 /* Read the current link report info */
6953 bnx2x_fill_report_data(sc, &cur_data);
6955 /* Don't report link down or exactly the same link status twice */
6956 if (!memcmp(&cur_data, &sc->last_reported_link, sizeof(cur_data)) ||
6957 (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6958 &sc->last_reported_link.link_report_flags) &&
6959 bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6960 &cur_data.link_report_flags))) {
6964 ELINK_DEBUG_P2(sc, "Change in link status : cur_data = %lx, last_reported_link = %lx",
6965 cur_data.link_report_flags,
6966 sc->last_reported_link.link_report_flags);
6970 ELINK_DEBUG_P1(sc, "link status change count = %x", sc->link_cnt);
6971 /* report new link params and remember the state for the next time */
6972 rte_memcpy(&sc->last_reported_link, &cur_data, sizeof(cur_data));
6974 if (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6975 &cur_data.link_report_flags)) {
6976 ELINK_DEBUG_P0(sc, "NIC Link is Down");
6978 __rte_unused const char *duplex;
6979 __rte_unused const char *flow;
6981 if (bnx2x_test_and_clear_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6982 &cur_data.link_report_flags)) {
6984 ELINK_DEBUG_P0(sc, "link set to full duplex");
6987 ELINK_DEBUG_P0(sc, "link set to half duplex");
6991 * Handle the FC at the end so that only these flags would be
6992 * possibly set. This way we may easily check if there is no FC
6995 if (cur_data.link_report_flags) {
6996 if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6997 &cur_data.link_report_flags) &&
6998 bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6999 &cur_data.link_report_flags)) {
7000 flow = "ON - receive & transmit";
7001 } else if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
7002 &cur_data.link_report_flags) &&
7003 !bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
7004 &cur_data.link_report_flags)) {
7005 flow = "ON - receive";
7006 } else if (!bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
7007 &cur_data.link_report_flags) &&
7008 bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
7009 &cur_data.link_report_flags)) {
7010 flow = "ON - transmit";
7012 flow = "none"; /* possible? */
7018 PMD_DRV_LOG(INFO, sc,
7019 "NIC Link is Up, %d Mbps %s duplex, Flow control: %s",
7020 cur_data.line_speed, duplex, flow);
7025 bnx2x_link_report(struct bnx2x_softc *sc)
7027 bnx2x_acquire_phy_lock(sc);
7028 bnx2x_link_report_locked(sc);
7029 bnx2x_release_phy_lock(sc);
7032 void bnx2x_link_status_update(struct bnx2x_softc *sc)
7034 if (sc->state != BNX2X_STATE_OPEN) {
7038 if (IS_PF(sc) && !CHIP_REV_IS_SLOW(sc)) {
7039 elink_link_status_update(&sc->link_params, &sc->link_vars);
7041 sc->port.supported[0] |= (ELINK_SUPPORTED_10baseT_Half |
7042 ELINK_SUPPORTED_10baseT_Full |
7043 ELINK_SUPPORTED_100baseT_Half |
7044 ELINK_SUPPORTED_100baseT_Full |
7045 ELINK_SUPPORTED_1000baseT_Full |
7046 ELINK_SUPPORTED_2500baseX_Full |
7047 ELINK_SUPPORTED_10000baseT_Full |
7048 ELINK_SUPPORTED_TP |
7049 ELINK_SUPPORTED_FIBRE |
7050 ELINK_SUPPORTED_Autoneg |
7051 ELINK_SUPPORTED_Pause |
7052 ELINK_SUPPORTED_Asym_Pause);
7053 sc->port.advertising[0] = sc->port.supported[0];
7055 sc->link_params.sc = sc;
7056 sc->link_params.port = SC_PORT(sc);
7057 sc->link_params.req_duplex[0] = DUPLEX_FULL;
7058 sc->link_params.req_flow_ctrl[0] = ELINK_FLOW_CTRL_NONE;
7059 sc->link_params.req_line_speed[0] = SPEED_10000;
7060 sc->link_params.speed_cap_mask[0] = 0x7f0000;
7061 sc->link_params.switch_cfg = ELINK_SWITCH_CFG_10G;
7063 if (CHIP_REV_IS_FPGA(sc)) {
7064 sc->link_vars.mac_type = ELINK_MAC_TYPE_EMAC;
7065 sc->link_vars.line_speed = ELINK_SPEED_1000;
7066 sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
7067 LINK_STATUS_SPEED_AND_DUPLEX_1000TFD);
7069 sc->link_vars.mac_type = ELINK_MAC_TYPE_BMAC;
7070 sc->link_vars.line_speed = ELINK_SPEED_10000;
7071 sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
7072 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
7075 sc->link_vars.link_up = 1;
7077 sc->link_vars.duplex = DUPLEX_FULL;
7078 sc->link_vars.flow_ctrl = ELINK_FLOW_CTRL_NONE;
7082 NIG_REG_EGRESS_DRAIN0_MODE +
7083 sc->link_params.port * 4, 0);
7084 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7085 bnx2x_link_report(sc);
7090 if (sc->link_vars.link_up) {
7091 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7093 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
7095 bnx2x_link_report(sc);
7097 bnx2x_link_report_locked(sc);
7098 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7102 static int bnx2x_initial_phy_init(struct bnx2x_softc *sc, int load_mode)
7104 int rc, cfg_idx = bnx2x_get_link_cfg_idx(sc);
7105 uint16_t req_line_speed = sc->link_params.req_line_speed[cfg_idx];
7106 struct elink_params *lp = &sc->link_params;
7108 bnx2x_set_requested_fc(sc);
7110 bnx2x_acquire_phy_lock(sc);
7112 if (load_mode == LOAD_DIAG) {
7113 lp->loopback_mode = ELINK_LOOPBACK_XGXS;
7114 /* Prefer doing PHY loopback at 10G speed, if possible */
7115 if (lp->req_line_speed[cfg_idx] < ELINK_SPEED_10000) {
7116 if (lp->speed_cap_mask[cfg_idx] &
7117 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
7118 lp->req_line_speed[cfg_idx] = ELINK_SPEED_10000;
7120 lp->req_line_speed[cfg_idx] = ELINK_SPEED_1000;
7125 if (load_mode == LOAD_LOOPBACK_EXT) {
7126 lp->loopback_mode = ELINK_LOOPBACK_EXT;
7129 rc = elink_phy_init(&sc->link_params, &sc->link_vars);
7131 bnx2x_release_phy_lock(sc);
7133 bnx2x_calc_fc_adv(sc);
7135 if (sc->link_vars.link_up) {
7136 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7137 bnx2x_link_report(sc);
7140 sc->link_params.req_line_speed[cfg_idx] = req_line_speed;
7144 /* update flags in shmem */
7146 bnx2x_update_drv_flags(struct bnx2x_softc *sc, uint32_t flags, uint32_t set)
7150 if (SHMEM2_HAS(sc, drv_flags)) {
7151 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7152 drv_flags = SHMEM2_RD(sc, drv_flags);
7157 drv_flags &= ~flags;
7160 SHMEM2_WR(sc, drv_flags, drv_flags);
7162 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7166 /* periodic timer callout routine, only runs when the interface is up */
7167 void bnx2x_periodic_callout(struct bnx2x_softc *sc)
7169 if ((sc->state != BNX2X_STATE_OPEN) ||
7170 (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_STOP)) {
7171 PMD_DRV_LOG(DEBUG, sc, "periodic callout exit (state=0x%x)",
7175 if (!CHIP_REV_IS_SLOW(sc)) {
7177 * This barrier is needed to ensure the ordering between the writing
7178 * to the sc->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
7183 bnx2x_acquire_phy_lock(sc);
7184 elink_period_func(&sc->link_params, &sc->link_vars);
7185 bnx2x_release_phy_lock(sc);
7189 if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7190 int mb_idx = SC_FW_MB_IDX(sc);
7194 ++sc->fw_drv_pulse_wr_seq;
7195 sc->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
7197 drv_pulse = sc->fw_drv_pulse_wr_seq;
7198 bnx2x_drv_pulse(sc);
7200 mcp_pulse = (SHMEM_RD(sc, func_mb[mb_idx].mcp_pulse_mb) &
7201 MCP_PULSE_SEQ_MASK);
7204 * The delta between driver pulse and mcp response should
7205 * be 1 (before mcp response) or 0 (after mcp response).
7207 if ((drv_pulse != mcp_pulse) &&
7208 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
7209 /* someone lost a heartbeat... */
7210 PMD_DRV_LOG(ERR, sc,
7211 "drv_pulse (0x%x) != mcp_pulse (0x%x)",
7212 drv_pulse, mcp_pulse);
7218 /* start the controller */
7219 static __rte_noinline
7220 int bnx2x_nic_load(struct bnx2x_softc *sc)
7223 uint32_t load_code = 0;
7226 PMD_INIT_FUNC_TRACE(sc);
7228 sc->state = BNX2X_STATE_OPENING_WAITING_LOAD;
7231 /* must be called before memory allocation and HW init */
7232 bnx2x_ilt_set_info(sc);
7235 bnx2x_set_fp_rx_buf_size(sc);
7238 if (bnx2x_alloc_mem(sc) != 0) {
7239 sc->state = BNX2X_STATE_CLOSED;
7241 goto bnx2x_nic_load_error0;
7245 if (bnx2x_alloc_fw_stats_mem(sc) != 0) {
7246 sc->state = BNX2X_STATE_CLOSED;
7248 goto bnx2x_nic_load_error0;
7252 rc = bnx2x_vf_init(sc);
7254 sc->state = BNX2X_STATE_ERROR;
7255 goto bnx2x_nic_load_error0;
7260 /* set pf load just before approaching the MCP */
7261 bnx2x_set_pf_load(sc);
7263 /* if MCP exists send load request and analyze response */
7264 if (!BNX2X_NOMCP(sc)) {
7265 /* attempt to load pf */
7266 if (bnx2x_nic_load_request(sc, &load_code) != 0) {
7267 sc->state = BNX2X_STATE_CLOSED;
7269 goto bnx2x_nic_load_error1;
7272 /* what did the MCP say? */
7273 if (bnx2x_nic_load_analyze_req(sc, load_code) != 0) {
7274 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7275 sc->state = BNX2X_STATE_CLOSED;
7277 goto bnx2x_nic_load_error2;
7280 PMD_DRV_LOG(INFO, sc, "Device has no MCP!");
7281 load_code = bnx2x_nic_load_no_mcp(sc);
7284 /* mark PMF if applicable */
7285 bnx2x_nic_load_pmf(sc, load_code);
7287 /* Init Function state controlling object */
7288 bnx2x_init_func_obj(sc);
7291 if (bnx2x_init_hw(sc, load_code) != 0) {
7292 PMD_DRV_LOG(NOTICE, sc, "HW init failed");
7293 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7294 sc->state = BNX2X_STATE_CLOSED;
7296 goto bnx2x_nic_load_error2;
7300 bnx2x_nic_init(sc, load_code);
7302 /* Init per-function objects */
7304 bnx2x_init_objs(sc);
7306 /* set AFEX default VLAN tag to an invalid value */
7307 sc->devinfo.mf_info.afex_def_vlan_tag = -1;
7309 sc->state = BNX2X_STATE_OPENING_WAITING_PORT;
7310 rc = bnx2x_func_start(sc);
7312 PMD_DRV_LOG(NOTICE, sc, "Function start failed!");
7313 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7314 sc->state = BNX2X_STATE_ERROR;
7315 goto bnx2x_nic_load_error3;
7318 /* send LOAD_DONE command to MCP */
7319 if (!BNX2X_NOMCP(sc)) {
7321 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7323 PMD_DRV_LOG(NOTICE, sc,
7324 "MCP response failure, aborting");
7325 sc->state = BNX2X_STATE_ERROR;
7327 goto bnx2x_nic_load_error3;
7332 rc = bnx2x_setup_leading(sc);
7334 PMD_DRV_LOG(NOTICE, sc, "Setup leading failed!");
7335 sc->state = BNX2X_STATE_ERROR;
7336 goto bnx2x_nic_load_error3;
7339 FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, i) {
7341 rc = bnx2x_setup_queue(sc, &sc->fp[i], FALSE);
7342 else /* IS_VF(sc) */
7343 rc = bnx2x_vf_setup_queue(sc, &sc->fp[i], FALSE);
7346 PMD_DRV_LOG(NOTICE, sc, "Queue(%d) setup failed", i);
7347 sc->state = BNX2X_STATE_ERROR;
7348 goto bnx2x_nic_load_error3;
7352 rc = bnx2x_init_rss_pf(sc);
7354 PMD_DRV_LOG(NOTICE, sc, "PF RSS init failed");
7355 sc->state = BNX2X_STATE_ERROR;
7356 goto bnx2x_nic_load_error3;
7359 /* now when Clients are configured we are ready to work */
7360 sc->state = BNX2X_STATE_OPEN;
7362 /* Configure a ucast MAC */
7364 rc = bnx2x_set_eth_mac(sc, TRUE);
7365 } else { /* IS_VF(sc) */
7366 rc = bnx2x_vf_set_mac(sc, TRUE);
7370 PMD_DRV_LOG(NOTICE, sc, "Setting Ethernet MAC failed");
7371 sc->state = BNX2X_STATE_ERROR;
7372 goto bnx2x_nic_load_error3;
7376 rc = bnx2x_initial_phy_init(sc, LOAD_OPEN);
7378 sc->state = BNX2X_STATE_ERROR;
7379 goto bnx2x_nic_load_error3;
7383 sc->link_params.feature_config_flags &=
7384 ~ELINK_FEATURE_CONFIG_BOOT_FROM_SAN;
7387 switch (LOAD_OPEN) {
7393 case LOAD_LOOPBACK_EXT:
7394 sc->state = BNX2X_STATE_DIAG;
7402 bnx2x_update_drv_flags(sc, 1 << DRV_FLAGS_PORT_MASK, 0);
7404 bnx2x_link_status_update(sc);
7407 if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
7408 /* mark driver is loaded in shmem2 */
7409 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
7410 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
7412 DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED |
7413 DRV_FLAGS_CAPABILITIES_LOADED_L2));
7416 /* start fast path */
7417 /* Initialize Rx filter */
7418 bnx2x_set_rx_mode(sc);
7420 /* wait for all pending SP commands to complete */
7421 if (IS_PF(sc) && !bnx2x_wait_sp_comp(sc, ~0x0UL)) {
7422 PMD_DRV_LOG(NOTICE, sc, "Timeout waiting for all SPs to complete!");
7423 bnx2x_periodic_stop(sc);
7424 bnx2x_nic_unload(sc, UNLOAD_CLOSE, FALSE);
7428 PMD_DRV_LOG(DEBUG, sc, "NIC successfully loaded");
7432 bnx2x_nic_load_error3:
7435 bnx2x_int_disable_sync(sc, 1);
7437 /* clean out queued objects */
7438 bnx2x_squeeze_objects(sc);
7441 bnx2x_nic_load_error2:
7443 if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7444 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
7445 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
7450 bnx2x_nic_load_error1:
7452 /* clear pf_load status, as it was already set */
7454 bnx2x_clear_pf_load(sc);
7457 bnx2x_nic_load_error0:
7459 bnx2x_free_fw_stats_mem(sc);
7466 * Handles controller initialization.
7468 int bnx2x_init(struct bnx2x_softc *sc)
7470 int other_engine = SC_PATH(sc) ? 0 : 1;
7471 uint8_t other_load_status, load_status;
7472 uint8_t global = FALSE;
7475 /* Check if the driver is still running and bail out if it is. */
7476 if (sc->state != BNX2X_STATE_CLOSED) {
7477 PMD_DRV_LOG(DEBUG, sc, "Init called while driver is running!");
7479 goto bnx2x_init_done;
7482 bnx2x_set_power_state(sc, PCI_PM_D0);
7485 * If parity occurred during the unload, then attentions and/or
7486 * RECOVERY_IN_PROGRESS may still be set. If so we want the first function
7487 * loaded on the current engine to complete the recovery. Parity recovery
7488 * is only relevant for PF driver.
7491 other_load_status = bnx2x_get_load_status(sc, other_engine);
7492 load_status = bnx2x_get_load_status(sc, SC_PATH(sc));
7494 if (!bnx2x_reset_is_done(sc, SC_PATH(sc)) ||
7495 bnx2x_chk_parity_attn(sc, &global, TRUE)) {
7498 * If there are attentions and they are in global blocks, set
7499 * the GLOBAL_RESET bit regardless whether it will be this
7500 * function that will complete the recovery or not.
7503 bnx2x_set_reset_global(sc);
7507 * Only the first function on the current engine should try
7508 * to recover in open. In case of attentions in global blocks
7509 * only the first in the chip should try to recover.
7512 && (!global ||!other_load_status))
7513 && bnx2x_trylock_leader_lock(sc)
7514 && !bnx2x_leader_reset(sc)) {
7515 PMD_DRV_LOG(INFO, sc,
7516 "Recovered during init");
7520 /* recovery has failed... */
7521 bnx2x_set_power_state(sc, PCI_PM_D3hot);
7523 sc->recovery_state = BNX2X_RECOVERY_FAILED;
7525 PMD_DRV_LOG(NOTICE, sc,
7526 "Recovery flow hasn't properly "
7527 "completed yet, try again later. "
7528 "If you still see this message after a "
7529 "few retries then power cycle is required.");
7532 goto bnx2x_init_done;
7537 sc->recovery_state = BNX2X_RECOVERY_DONE;
7539 rc = bnx2x_nic_load(sc);
7544 PMD_DRV_LOG(NOTICE, sc, "Initialization failed, "
7545 "stack notified driver is NOT running!");
7551 static void bnx2x_get_function_num(struct bnx2x_softc *sc)
7556 * Read the ME register to get the function number. The ME register
7557 * holds the relative-function number and absolute-function number. The
7558 * absolute-function number appears only in E2 and above. Before that
7559 * these bits always contained zero, therefore we cannot blindly use them.
7562 val = REG_RD(sc, BAR_ME_REGISTER);
7565 (uint8_t) ((val & ME_REG_PF_NUM) >> ME_REG_PF_NUM_SHIFT);
7567 (uint8_t) ((val & ME_REG_ABS_PF_NUM) >> ME_REG_ABS_PF_NUM_SHIFT) &
7570 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7571 sc->pfunc_abs = ((sc->pfunc_rel << 1) | sc->path_id);
7573 sc->pfunc_abs = (sc->pfunc_rel | sc->path_id);
7576 PMD_DRV_LOG(DEBUG, sc,
7577 "Relative function %d, Absolute function %d, Path %d",
7578 sc->pfunc_rel, sc->pfunc_abs, sc->path_id);
7581 static uint32_t bnx2x_get_shmem_mf_cfg_base(struct bnx2x_softc *sc)
7583 uint32_t shmem2_size;
7585 uint32_t mf_cfg_offset_value;
7588 offset = (SHMEM_ADDR(sc, func_mb) +
7589 (MAX_FUNC_NUM * sizeof(struct drv_func_mb)));
7592 if (sc->devinfo.shmem2_base != 0) {
7593 shmem2_size = SHMEM2_RD(sc, size);
7594 if (shmem2_size > offsetof(struct shmem2_region, mf_cfg_addr)) {
7595 mf_cfg_offset_value = SHMEM2_RD(sc, mf_cfg_addr);
7596 if (SHMEM_MF_CFG_ADDR_NONE != mf_cfg_offset_value) {
7597 offset = mf_cfg_offset_value;
7605 static uint32_t bnx2x_pcie_capability_read(struct bnx2x_softc *sc, int reg)
7608 struct bnx2x_pci_cap *caps;
7610 /* ensure PCIe capability is enabled */
7611 caps = pci_find_cap(sc, PCIY_EXPRESS, BNX2X_PCI_CAP);
7613 PMD_DRV_LOG(DEBUG, sc, "Found PCIe capability: "
7614 "id=0x%04X type=0x%04X addr=0x%08X",
7615 caps->id, caps->type, caps->addr);
7616 pci_read(sc, (caps->addr + reg), &ret, 2);
7620 PMD_DRV_LOG(WARNING, sc, "PCIe capability NOT FOUND!!!");
7625 static uint8_t bnx2x_is_pcie_pending(struct bnx2x_softc *sc)
7627 return bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_STA) &
7628 PCIM_EXP_STA_TRANSACTION_PND;
7632 * Walk the PCI capabiites list for the device to find what features are
7633 * supported. These capabilites may be enabled/disabled by firmware so it's
7634 * best to walk the list rather than make assumptions.
7636 static void bnx2x_probe_pci_caps(struct bnx2x_softc *sc)
7638 PMD_INIT_FUNC_TRACE(sc);
7640 struct bnx2x_pci_cap *caps;
7641 uint16_t link_status;
7644 /* check if PCI Power Management is enabled */
7645 caps = pci_find_cap(sc, PCIY_PMG, BNX2X_PCI_CAP);
7647 PMD_DRV_LOG(DEBUG, sc, "Found PM capability: "
7648 "id=0x%04X type=0x%04X addr=0x%08X",
7649 caps->id, caps->type, caps->addr);
7651 sc->devinfo.pcie_cap_flags |= BNX2X_PM_CAPABLE_FLAG;
7652 sc->devinfo.pcie_pm_cap_reg = caps->addr;
7655 link_status = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_LINK_STA);
7657 sc->devinfo.pcie_link_speed = (link_status & PCIM_LINK_STA_SPEED);
7658 sc->devinfo.pcie_link_width =
7659 ((link_status & PCIM_LINK_STA_WIDTH) >> 4);
7661 PMD_DRV_LOG(DEBUG, sc, "PCIe link speed=%d width=%d",
7662 sc->devinfo.pcie_link_speed, sc->devinfo.pcie_link_width);
7664 sc->devinfo.pcie_cap_flags |= BNX2X_PCIE_CAPABLE_FLAG;
7666 /* check if MSI capability is enabled */
7667 caps = pci_find_cap(sc, PCIY_MSI, BNX2X_PCI_CAP);
7669 PMD_DRV_LOG(DEBUG, sc, "Found MSI capability at 0x%04x", reg);
7671 sc->devinfo.pcie_cap_flags |= BNX2X_MSI_CAPABLE_FLAG;
7672 sc->devinfo.pcie_msi_cap_reg = caps->addr;
7675 /* check if MSI-X capability is enabled */
7676 caps = pci_find_cap(sc, PCIY_MSIX, BNX2X_PCI_CAP);
7678 PMD_DRV_LOG(DEBUG, sc, "Found MSI-X capability at 0x%04x", reg);
7680 sc->devinfo.pcie_cap_flags |= BNX2X_MSIX_CAPABLE_FLAG;
7681 sc->devinfo.pcie_msix_cap_reg = caps->addr;
7685 static int bnx2x_get_shmem_mf_cfg_info_sd(struct bnx2x_softc *sc)
7687 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7690 /* get the outer vlan if we're in switch-dependent mode */
7692 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7693 mf_info->ext_id = (uint16_t) val;
7695 mf_info->multi_vnics_mode = 1;
7697 if (!VALID_OVLAN(mf_info->ext_id)) {
7698 PMD_DRV_LOG(NOTICE, sc, "Invalid VLAN (%d)", mf_info->ext_id);
7702 /* get the capabilities */
7703 if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK) ==
7704 FUNC_MF_CFG_PROTOCOL_ISCSI) {
7705 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ISCSI;
7706 } else if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK)
7707 == FUNC_MF_CFG_PROTOCOL_FCOE) {
7708 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_FCOE;
7710 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ETHERNET;
7713 mf_info->vnics_per_port =
7714 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7719 static uint32_t bnx2x_get_shmem_ext_proto_support_flags(struct bnx2x_softc *sc)
7721 uint32_t retval = 0;
7724 val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7726 if (val & MACP_FUNC_CFG_FLAGS_ENABLED) {
7727 if (val & MACP_FUNC_CFG_FLAGS_ETHERNET) {
7728 retval |= MF_PROTO_SUPPORT_ETHERNET;
7730 if (val & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
7731 retval |= MF_PROTO_SUPPORT_ISCSI;
7733 if (val & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
7734 retval |= MF_PROTO_SUPPORT_FCOE;
7741 static int bnx2x_get_shmem_mf_cfg_info_si(struct bnx2x_softc *sc)
7743 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7747 * There is no outer vlan if we're in switch-independent mode.
7748 * If the mac is valid then assume multi-function.
7751 val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7753 mf_info->multi_vnics_mode = ((val & MACP_FUNC_CFG_FLAGS_MASK) != 0);
7755 mf_info->mf_protos_supported =
7756 bnx2x_get_shmem_ext_proto_support_flags(sc);
7758 mf_info->vnics_per_port =
7759 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7764 static int bnx2x_get_shmem_mf_cfg_info_niv(struct bnx2x_softc *sc)
7766 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7768 uint32_t func_config;
7769 uint32_t niv_config;
7771 mf_info->multi_vnics_mode = 1;
7773 e1hov_tag = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7774 func_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7775 niv_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].afex_config);
7778 (uint16_t) ((e1hov_tag & FUNC_MF_CFG_E1HOV_TAG_MASK) >>
7779 FUNC_MF_CFG_E1HOV_TAG_SHIFT);
7781 mf_info->default_vlan =
7782 (uint16_t) ((e1hov_tag & FUNC_MF_CFG_AFEX_VLAN_MASK) >>
7783 FUNC_MF_CFG_AFEX_VLAN_SHIFT);
7785 mf_info->niv_allowed_priorities =
7786 (uint8_t) ((niv_config & FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
7787 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT);
7789 mf_info->niv_default_cos =
7790 (uint8_t) ((func_config & FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
7791 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT);
7793 mf_info->afex_vlan_mode =
7794 ((niv_config & FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
7795 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT);
7797 mf_info->niv_mba_enabled =
7798 ((niv_config & FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK) >>
7799 FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT);
7801 mf_info->mf_protos_supported =
7802 bnx2x_get_shmem_ext_proto_support_flags(sc);
7804 mf_info->vnics_per_port =
7805 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7810 static int bnx2x_check_valid_mf_cfg(struct bnx2x_softc *sc)
7812 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7819 /* various MF mode sanity checks... */
7821 if (mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_HIDE) {
7822 PMD_DRV_LOG(NOTICE, sc,
7823 "Enumerated function %d is marked as hidden",
7828 if ((mf_info->vnics_per_port > 1) && !mf_info->multi_vnics_mode) {
7829 PMD_DRV_LOG(NOTICE, sc, "vnics_per_port=%d multi_vnics_mode=%d",
7830 mf_info->vnics_per_port, mf_info->multi_vnics_mode);
7834 if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7835 /* vnic id > 0 must have valid ovlan in switch-dependent mode */
7836 if ((SC_VN(sc) > 0) && !VALID_OVLAN(OVLAN(sc))) {
7837 PMD_DRV_LOG(NOTICE, sc, "mf_mode=SD vnic_id=%d ovlan=%d",
7838 SC_VN(sc), OVLAN(sc));
7842 if (!VALID_OVLAN(OVLAN(sc)) && mf_info->multi_vnics_mode) {
7843 PMD_DRV_LOG(NOTICE, sc,
7844 "mf_mode=SD multi_vnics_mode=%d ovlan=%d",
7845 mf_info->multi_vnics_mode, OVLAN(sc));
7850 * Verify all functions are either MF or SF mode. If MF, make sure
7851 * sure that all non-hidden functions have a valid ovlan. If SF,
7852 * make sure that all non-hidden functions have an invalid ovlan.
7854 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7855 mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7856 ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7857 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE) &&
7858 (((mf_info->multi_vnics_mode)
7859 && !VALID_OVLAN(ovlan1))
7860 || ((!mf_info->multi_vnics_mode)
7861 && VALID_OVLAN(ovlan1)))) {
7862 PMD_DRV_LOG(NOTICE, sc,
7863 "mf_mode=SD function %d MF config "
7864 "mismatch, multi_vnics_mode=%d ovlan=%d",
7865 i, mf_info->multi_vnics_mode,
7871 /* Verify all funcs on the same port each have a different ovlan. */
7872 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7873 mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7874 ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7875 /* iterate from the next function on the port to the max func */
7876 for (j = i + 2; j < MAX_FUNC_NUM; j += 2) {
7878 MFCFG_RD(sc, func_mf_config[j].config);
7880 MFCFG_RD(sc, func_mf_config[j].e1hov_tag);
7881 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE)
7882 && VALID_OVLAN(ovlan1)
7883 && !(mf_cfg2 & FUNC_MF_CFG_FUNC_HIDE)
7884 && VALID_OVLAN(ovlan2)
7885 && (ovlan1 == ovlan2)) {
7886 PMD_DRV_LOG(NOTICE, sc,
7887 "mf_mode=SD functions %d and %d "
7888 "have the same ovlan (%d)",
7895 /* MULTI_FUNCTION_SD */
7899 static int bnx2x_get_mf_cfg_info(struct bnx2x_softc *sc)
7901 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7902 uint32_t val, mac_upper;
7905 /* initialize mf_info defaults */
7906 mf_info->vnics_per_port = 1;
7907 mf_info->multi_vnics_mode = FALSE;
7908 mf_info->path_has_ovlan = FALSE;
7909 mf_info->mf_mode = SINGLE_FUNCTION;
7911 if (!CHIP_IS_MF_CAP(sc)) {
7915 if (sc->devinfo.mf_cfg_base == SHMEM_MF_CFG_ADDR_NONE) {
7916 PMD_DRV_LOG(NOTICE, sc, "Invalid mf_cfg_base!");
7920 /* get the MF mode (switch dependent / independent / single-function) */
7922 val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
7924 switch (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK) {
7925 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
7928 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7930 /* check for legal upper mac bytes */
7931 if (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT) {
7932 mf_info->mf_mode = MULTI_FUNCTION_SI;
7934 PMD_DRV_LOG(NOTICE, sc,
7935 "Invalid config for Switch Independent mode");
7940 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
7941 case SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4:
7943 /* get outer vlan configuration */
7944 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7946 if ((val & FUNC_MF_CFG_E1HOV_TAG_MASK) !=
7947 FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
7948 mf_info->mf_mode = MULTI_FUNCTION_SD;
7950 PMD_DRV_LOG(NOTICE, sc,
7951 "Invalid config for Switch Dependent mode");
7956 case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
7958 /* not in MF mode, vnics_per_port=1 and multi_vnics_mode=FALSE */
7961 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
7964 * Mark MF mode as NIV if MCP version includes NPAR-SD support
7965 * and the MAC address is valid.
7968 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7970 if ((SHMEM2_HAS(sc, afex_driver_support)) &&
7971 (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT)) {
7972 mf_info->mf_mode = MULTI_FUNCTION_AFEX;
7974 PMD_DRV_LOG(NOTICE, sc, "Invalid config for AFEX mode");
7981 PMD_DRV_LOG(NOTICE, sc, "Unknown MF mode (0x%08x)",
7982 (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK));
7987 /* set path mf_mode (which could be different than function mf_mode) */
7988 if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7989 mf_info->path_has_ovlan = TRUE;
7990 } else if (mf_info->mf_mode == SINGLE_FUNCTION) {
7992 * Decide on path multi vnics mode. If we're not in MF mode and in
7993 * 4-port mode, this is good enough to check vnic-0 of the other port
7996 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7997 uint8_t other_port = !(PORT_ID(sc) & 1);
7998 uint8_t abs_func_other_port =
7999 (SC_PATH(sc) + (2 * other_port));
8004 [abs_func_other_port].e1hov_tag);
8006 mf_info->path_has_ovlan = VALID_OVLAN((uint16_t) val);
8010 if (mf_info->mf_mode == SINGLE_FUNCTION) {
8011 /* invalid MF config */
8012 if (SC_VN(sc) >= 1) {
8013 PMD_DRV_LOG(NOTICE, sc, "VNIC ID >= 1 in SF mode");
8020 /* get the MF configuration */
8021 mf_info->mf_config[SC_VN(sc)] =
8022 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
8024 switch (mf_info->mf_mode) {
8025 case MULTI_FUNCTION_SD:
8027 bnx2x_get_shmem_mf_cfg_info_sd(sc);
8030 case MULTI_FUNCTION_SI:
8032 bnx2x_get_shmem_mf_cfg_info_si(sc);
8035 case MULTI_FUNCTION_AFEX:
8037 bnx2x_get_shmem_mf_cfg_info_niv(sc);
8042 PMD_DRV_LOG(NOTICE, sc, "Get MF config failed (mf_mode=0x%08x)",
8047 /* get the congestion management parameters */
8050 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
8051 /* get min/max bw */
8052 val = MFCFG_RD(sc, func_mf_config[i].config);
8053 mf_info->min_bw[vnic] =
8054 ((val & FUNC_MF_CFG_MIN_BW_MASK) >>
8055 FUNC_MF_CFG_MIN_BW_SHIFT);
8056 mf_info->max_bw[vnic] =
8057 ((val & FUNC_MF_CFG_MAX_BW_MASK) >>
8058 FUNC_MF_CFG_MAX_BW_SHIFT);
8062 return bnx2x_check_valid_mf_cfg(sc);
8065 static int bnx2x_get_shmem_info(struct bnx2x_softc *sc)
8068 uint32_t mac_hi, mac_lo, val;
8070 PMD_INIT_FUNC_TRACE(sc);
8073 mac_hi = mac_lo = 0;
8075 sc->link_params.sc = sc;
8076 sc->link_params.port = port;
8078 /* get the hardware config info */
8079 sc->devinfo.hw_config = SHMEM_RD(sc, dev_info.shared_hw_config.config);
8080 sc->devinfo.hw_config2 =
8081 SHMEM_RD(sc, dev_info.shared_hw_config.config2);
8083 sc->link_params.hw_led_mode =
8084 ((sc->devinfo.hw_config & SHARED_HW_CFG_LED_MODE_MASK) >>
8085 SHARED_HW_CFG_LED_MODE_SHIFT);
8087 /* get the port feature config */
8089 SHMEM_RD(sc, dev_info.port_feature_config[port].config);
8091 /* get the link params */
8092 sc->link_params.speed_cap_mask[ELINK_INT_PHY] =
8093 SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask)
8094 & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
8095 sc->link_params.speed_cap_mask[ELINK_EXT_PHY1] =
8096 SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask2)
8097 & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
8099 /* get the lane config */
8100 sc->link_params.lane_config =
8101 SHMEM_RD(sc, dev_info.port_hw_config[port].lane_config);
8103 /* get the link config */
8104 val = SHMEM_RD(sc, dev_info.port_feature_config[port].link_config);
8105 sc->port.link_config[ELINK_INT_PHY] = val;
8106 sc->link_params.switch_cfg = (val & PORT_FEATURE_CONNECTED_SWITCH_MASK);
8107 sc->port.link_config[ELINK_EXT_PHY1] =
8108 SHMEM_RD(sc, dev_info.port_feature_config[port].link_config2);
8110 /* get the override preemphasis flag and enable it or turn it off */
8111 val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
8112 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) {
8113 sc->link_params.feature_config_flags |=
8114 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8116 sc->link_params.feature_config_flags &=
8117 ~ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8120 val = sc->devinfo.bc_ver >> 8;
8121 if (val < BNX2X_BC_VER) {
8122 /* for now only warn later we might need to enforce this */
8123 PMD_DRV_LOG(NOTICE, sc, "This driver needs bc_ver %X but found %X, please upgrade BC\n",
8126 sc->link_params.feature_config_flags |=
8127 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
8128 ELINK_FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY :
8131 sc->link_params.feature_config_flags |=
8132 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
8133 ELINK_FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
8134 sc->link_params.feature_config_flags |=
8135 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
8136 ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
8137 sc->link_params.feature_config_flags |=
8138 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
8139 ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
8141 /* get the initial value of the link params */
8142 sc->link_params.multi_phy_config =
8143 SHMEM_RD(sc, dev_info.port_hw_config[port].multi_phy_config);
8145 /* get external phy info */
8146 sc->port.ext_phy_config =
8147 SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
8149 /* get the multifunction configuration */
8150 bnx2x_get_mf_cfg_info(sc);
8152 /* get the mac address */
8155 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
8157 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_lower);
8159 mac_hi = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_upper);
8160 mac_lo = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_lower);
8163 if ((mac_lo == 0) && (mac_hi == 0)) {
8164 *sc->mac_addr_str = 0;
8165 PMD_DRV_LOG(NOTICE, sc, "No Ethernet address programmed!");
8167 sc->link_params.mac_addr[0] = (uint8_t) (mac_hi >> 8);
8168 sc->link_params.mac_addr[1] = (uint8_t) (mac_hi);
8169 sc->link_params.mac_addr[2] = (uint8_t) (mac_lo >> 24);
8170 sc->link_params.mac_addr[3] = (uint8_t) (mac_lo >> 16);
8171 sc->link_params.mac_addr[4] = (uint8_t) (mac_lo >> 8);
8172 sc->link_params.mac_addr[5] = (uint8_t) (mac_lo);
8173 snprintf(sc->mac_addr_str, sizeof(sc->mac_addr_str),
8174 "%02x:%02x:%02x:%02x:%02x:%02x",
8175 sc->link_params.mac_addr[0],
8176 sc->link_params.mac_addr[1],
8177 sc->link_params.mac_addr[2],
8178 sc->link_params.mac_addr[3],
8179 sc->link_params.mac_addr[4],
8180 sc->link_params.mac_addr[5]);
8181 PMD_DRV_LOG(DEBUG, sc,
8182 "Ethernet address: %s", sc->mac_addr_str);
8188 static void bnx2x_media_detect(struct bnx2x_softc *sc)
8190 uint32_t phy_idx = bnx2x_get_cur_phy_idx(sc);
8191 switch (sc->link_params.phy[phy_idx].media_type) {
8192 case ELINK_ETH_PHY_SFPP_10G_FIBER:
8193 case ELINK_ETH_PHY_SFP_1G_FIBER:
8194 case ELINK_ETH_PHY_XFP_FIBER:
8195 case ELINK_ETH_PHY_KR:
8196 case ELINK_ETH_PHY_CX4:
8197 PMD_DRV_LOG(INFO, sc, "Found 10GBase-CX4 media.");
8198 sc->media = IFM_10G_CX4;
8200 case ELINK_ETH_PHY_DA_TWINAX:
8201 PMD_DRV_LOG(INFO, sc, "Found 10Gb Twinax media.");
8202 sc->media = IFM_10G_TWINAX;
8204 case ELINK_ETH_PHY_BASE_T:
8205 PMD_DRV_LOG(INFO, sc, "Found 10GBase-T media.");
8206 sc->media = IFM_10G_T;
8208 case ELINK_ETH_PHY_NOT_PRESENT:
8209 PMD_DRV_LOG(INFO, sc, "Media not present.");
8212 case ELINK_ETH_PHY_UNSPECIFIED:
8214 PMD_DRV_LOG(INFO, sc, "Unknown media!");
8220 #define GET_FIELD(value, fname) \
8221 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
8222 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
8223 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
8225 static int bnx2x_get_igu_cam_info(struct bnx2x_softc *sc)
8227 int pfid = SC_FUNC(sc);
8230 uint8_t fid, igu_sb_cnt = 0;
8232 sc->igu_base_sb = 0xff;
8234 if (CHIP_INT_MODE_IS_BC(sc)) {
8236 igu_sb_cnt = sc->igu_sb_cnt;
8237 sc->igu_base_sb = ((CHIP_IS_MODE_4_PORT(sc) ? pfid : vn) *
8239 sc->igu_dsb_id = (E1HVN_MAX * FP_SB_MAX_E1x +
8240 (CHIP_IS_MODE_4_PORT(sc) ? pfid : vn));
8244 /* IGU in normal mode - read CAM */
8246 igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; igu_sb_id++) {
8247 val = REG_RD(sc, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
8248 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) {
8252 if (fid & IGU_FID_ENCODE_IS_PF) {
8253 if ((fid & IGU_FID_PF_NUM_MASK) != pfid) {
8256 if (IGU_VEC(val) == 0) {
8257 /* default status block */
8258 sc->igu_dsb_id = igu_sb_id;
8260 if (sc->igu_base_sb == 0xff) {
8261 sc->igu_base_sb = igu_sb_id;
8269 * Due to new PF resource allocation by MFW T7.4 and above, it's optional
8270 * that number of CAM entries will not be equal to the value advertised in
8271 * PCI. Driver should use the minimal value of both as the actual status
8274 sc->igu_sb_cnt = min(sc->igu_sb_cnt, igu_sb_cnt);
8276 if (igu_sb_cnt == 0) {
8277 PMD_DRV_LOG(ERR, sc, "CAM configuration error");
8285 * Gather various information from the device config space, the device itself,
8286 * shmem, and the user input.
8288 static int bnx2x_get_device_info(struct bnx2x_softc *sc)
8293 /* get the chip revision (chip metal comes from pci config space) */
8294 sc->devinfo.chip_id = sc->link_params.chip_id =
8295 (((REG_RD(sc, MISC_REG_CHIP_NUM) & 0xffff) << 16) |
8296 ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12) |
8297 (((REG_RD(sc, PCICFG_OFFSET + PCI_ID_VAL3) >> 24) & 0xf) << 4) |
8298 ((REG_RD(sc, MISC_REG_BOND_ID) & 0xf) << 0));
8300 /* force 57811 according to MISC register */
8301 if (REG_RD(sc, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
8302 if (CHIP_IS_57810(sc)) {
8303 sc->devinfo.chip_id = ((CHIP_NUM_57811 << 16) |
8305 devinfo.chip_id & 0x0000ffff));
8306 } else if (CHIP_IS_57810_MF(sc)) {
8307 sc->devinfo.chip_id = ((CHIP_NUM_57811_MF << 16) |
8309 devinfo.chip_id & 0x0000ffff));
8311 sc->devinfo.chip_id |= 0x1;
8314 PMD_DRV_LOG(DEBUG, sc,
8315 "chip_id=0x%08x (num=0x%04x rev=0x%01x metal=0x%02x bond=0x%01x)",
8316 sc->devinfo.chip_id,
8317 ((sc->devinfo.chip_id >> 16) & 0xffff),
8318 ((sc->devinfo.chip_id >> 12) & 0xf),
8319 ((sc->devinfo.chip_id >> 4) & 0xff),
8320 ((sc->devinfo.chip_id >> 0) & 0xf));
8322 val = (REG_RD(sc, 0x2874) & 0x55);
8323 if ((sc->devinfo.chip_id & 0x1) || (CHIP_IS_E1H(sc) && (val == 0x55))) {
8324 sc->flags |= BNX2X_ONE_PORT_FLAG;
8325 PMD_DRV_LOG(DEBUG, sc, "single port device");
8328 /* set the doorbell size */
8329 sc->doorbell_size = (1 << BNX2X_DB_SHIFT);
8331 /* determine whether the device is in 2 port or 4 port mode */
8332 sc->devinfo.chip_port_mode = CHIP_PORT_MODE_NONE; /* E1h */
8333 if (CHIP_IS_E2E3(sc)) {
8335 * Read port4mode_en_ovwr[0]:
8336 * If 1, four port mode is in port4mode_en_ovwr[1].
8337 * If 0, four port mode is in port4mode_en[0].
8339 val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);
8341 val = ((val >> 1) & 1);
8343 val = REG_RD(sc, MISC_REG_PORT4MODE_EN);
8346 sc->devinfo.chip_port_mode =
8347 (val) ? CHIP_4_PORT_MODE : CHIP_2_PORT_MODE;
8349 PMD_DRV_LOG(DEBUG, sc, "Port mode = %s", (val) ? "4" : "2");
8352 /* get the function and path info for the device */
8353 bnx2x_get_function_num(sc);
8355 /* get the shared memory base address */
8356 sc->devinfo.shmem_base =
8357 sc->link_params.shmem_base = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
8358 sc->devinfo.shmem2_base =
8359 REG_RD(sc, (SC_PATH(sc) ? MISC_REG_GENERIC_CR_1 :
8360 MISC_REG_GENERIC_CR_0));
8362 if (!sc->devinfo.shmem_base) {
8363 /* this should ONLY prevent upcoming shmem reads */
8364 PMD_DRV_LOG(INFO, sc, "MCP not active");
8365 sc->flags |= BNX2X_NO_MCP_FLAG;
8369 /* make sure the shared memory contents are valid */
8370 val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
8371 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) !=
8372 (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) {
8373 PMD_DRV_LOG(NOTICE, sc, "Invalid SHMEM validity signature: 0x%08x",
8378 /* get the bootcode version */
8379 sc->devinfo.bc_ver = SHMEM_RD(sc, dev_info.bc_rev);
8380 snprintf(sc->devinfo.bc_ver_str,
8381 sizeof(sc->devinfo.bc_ver_str),
8383 ((sc->devinfo.bc_ver >> 24) & 0xff),
8384 ((sc->devinfo.bc_ver >> 16) & 0xff),
8385 ((sc->devinfo.bc_ver >> 8) & 0xff));
8386 PMD_DRV_LOG(DEBUG, sc, "Bootcode version: %s", sc->devinfo.bc_ver_str);
8388 /* get the bootcode shmem address */
8389 sc->devinfo.mf_cfg_base = bnx2x_get_shmem_mf_cfg_base(sc);
8391 /* clean indirect addresses as they're not used */
8392 pci_write_long(sc, PCICFG_GRC_ADDRESS, 0);
8394 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F0, 0);
8395 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F0, 0);
8396 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F0, 0);
8397 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F0, 0);
8398 if (CHIP_IS_E1x(sc)) {
8399 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F1, 0);
8400 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F1, 0);
8401 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F1, 0);
8402 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F1, 0);
8406 /* get the nvram size */
8407 val = REG_RD(sc, MCP_REG_MCPR_NVM_CFG4);
8408 sc->devinfo.flash_size =
8409 (NVRAM_1MB_SIZE << (val & MCPR_NVM_CFG4_FLASH_SIZE));
8411 bnx2x_set_power_state(sc, PCI_PM_D0);
8412 /* get various configuration parameters from shmem */
8413 bnx2x_get_shmem_info(sc);
8415 /* initialize IGU parameters */
8416 if (CHIP_IS_E1x(sc)) {
8417 sc->devinfo.int_block = INT_BLOCK_HC;
8418 sc->igu_dsb_id = DEF_SB_IGU_ID;
8419 sc->igu_base_sb = 0;
8421 sc->devinfo.int_block = INT_BLOCK_IGU;
8423 /* do not allow device reset during IGU info preocessing */
8424 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8426 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
8428 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8431 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
8432 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION, val);
8433 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x7f);
8435 while (tout && REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8440 if (REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8441 PMD_DRV_LOG(NOTICE, sc,
8442 "FORCING IGU Normal Mode failed!!!");
8443 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8448 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8449 PMD_DRV_LOG(DEBUG, sc, "IGU Backward Compatible Mode");
8450 sc->devinfo.int_block |= INT_BLOCK_MODE_BW_COMP;
8452 PMD_DRV_LOG(DEBUG, sc, "IGU Normal Mode");
8455 rc = bnx2x_get_igu_cam_info(sc);
8457 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8465 * Get base FW non-default (fast path) status block ID. This value is
8466 * used to initialize the fw_sb_id saved on the fp/queue structure to
8467 * determine the id used by the FW.
8469 if (CHIP_IS_E1x(sc)) {
8471 ((SC_PORT(sc) * FP_SB_MAX_E1x) + SC_L_ID(sc));
8474 * 57712+ - We currently use one FW SB per IGU SB (Rx and Tx of
8475 * the same queue are indicated on the same IGU SB). So we prefer
8476 * FW and IGU SBs to be the same value.
8478 sc->base_fw_ndsb = sc->igu_base_sb;
8481 elink_phy_probe(&sc->link_params);
8487 bnx2x_link_settings_supported(struct bnx2x_softc *sc, uint32_t switch_cfg)
8489 uint32_t cfg_size = 0;
8491 uint8_t port = SC_PORT(sc);
8493 /* aggregation of supported attributes of all external phys */
8494 sc->port.supported[0] = 0;
8495 sc->port.supported[1] = 0;
8497 switch (sc->link_params.num_phys) {
8499 sc->port.supported[0] =
8500 sc->link_params.phy[ELINK_INT_PHY].supported;
8504 sc->port.supported[0] =
8505 sc->link_params.phy[ELINK_EXT_PHY1].supported;
8509 if (sc->link_params.multi_phy_config &
8510 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
8511 sc->port.supported[1] =
8512 sc->link_params.phy[ELINK_EXT_PHY1].supported;
8513 sc->port.supported[0] =
8514 sc->link_params.phy[ELINK_EXT_PHY2].supported;
8516 sc->port.supported[0] =
8517 sc->link_params.phy[ELINK_EXT_PHY1].supported;
8518 sc->port.supported[1] =
8519 sc->link_params.phy[ELINK_EXT_PHY2].supported;
8525 if (!(sc->port.supported[0] || sc->port.supported[1])) {
8526 PMD_DRV_LOG(ERR, sc,
8527 "Invalid phy config in NVRAM (PHY1=0x%08x PHY2=0x%08x)",
8529 dev_info.port_hw_config
8530 [port].external_phy_config),
8532 dev_info.port_hw_config
8533 [port].external_phy_config2));
8538 sc->port.phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR);
8540 switch (switch_cfg) {
8541 case ELINK_SWITCH_CFG_1G:
8544 NIG_REG_SERDES0_CTRL_PHY_ADDR + port * 0x10);
8546 case ELINK_SWITCH_CFG_10G:
8549 NIG_REG_XGXS0_CTRL_PHY_ADDR + port * 0x18);
8552 PMD_DRV_LOG(ERR, sc,
8553 "Invalid switch config in"
8554 "link_config=0x%08x",
8555 sc->port.link_config[0]);
8560 PMD_DRV_LOG(INFO, sc, "PHY addr 0x%08x", sc->port.phy_addr);
8562 /* mask what we support according to speed_cap_mask per configuration */
8563 for (idx = 0; idx < cfg_size; idx++) {
8564 if (!(sc->link_params.speed_cap_mask[idx] &
8565 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) {
8566 sc->port.supported[idx] &=
8567 ~ELINK_SUPPORTED_10baseT_Half;
8570 if (!(sc->link_params.speed_cap_mask[idx] &
8571 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) {
8572 sc->port.supported[idx] &=
8573 ~ELINK_SUPPORTED_10baseT_Full;
8576 if (!(sc->link_params.speed_cap_mask[idx] &
8577 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) {
8578 sc->port.supported[idx] &=
8579 ~ELINK_SUPPORTED_100baseT_Half;
8582 if (!(sc->link_params.speed_cap_mask[idx] &
8583 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) {
8584 sc->port.supported[idx] &=
8585 ~ELINK_SUPPORTED_100baseT_Full;
8588 if (!(sc->link_params.speed_cap_mask[idx] &
8589 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) {
8590 sc->port.supported[idx] &=
8591 ~ELINK_SUPPORTED_1000baseT_Full;
8594 if (!(sc->link_params.speed_cap_mask[idx] &
8595 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) {
8596 sc->port.supported[idx] &=
8597 ~ELINK_SUPPORTED_2500baseX_Full;
8600 if (!(sc->link_params.speed_cap_mask[idx] &
8601 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8602 sc->port.supported[idx] &=
8603 ~ELINK_SUPPORTED_10000baseT_Full;
8606 if (!(sc->link_params.speed_cap_mask[idx] &
8607 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) {
8608 sc->port.supported[idx] &=
8609 ~ELINK_SUPPORTED_20000baseKR2_Full;
8613 PMD_DRV_LOG(INFO, sc, "PHY supported 0=0x%08x 1=0x%08x",
8614 sc->port.supported[0], sc->port.supported[1]);
8617 static void bnx2x_link_settings_requested(struct bnx2x_softc *sc)
8619 uint32_t link_config;
8621 uint32_t cfg_size = 0;
8623 sc->port.advertising[0] = 0;
8624 sc->port.advertising[1] = 0;
8626 switch (sc->link_params.num_phys) {
8636 for (idx = 0; idx < cfg_size; idx++) {
8637 sc->link_params.req_duplex[idx] = DUPLEX_FULL;
8638 link_config = sc->port.link_config[idx];
8640 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
8641 case PORT_FEATURE_LINK_SPEED_AUTO:
8642 if (sc->port.supported[idx] & ELINK_SUPPORTED_Autoneg) {
8643 sc->link_params.req_line_speed[idx] =
8644 ELINK_SPEED_AUTO_NEG;
8645 sc->port.advertising[idx] |=
8646 sc->port.supported[idx];
8647 if (sc->link_params.phy[ELINK_EXT_PHY1].type ==
8648 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833)
8649 sc->port.advertising[idx] |=
8650 (ELINK_SUPPORTED_100baseT_Half |
8651 ELINK_SUPPORTED_100baseT_Full);
8653 /* force 10G, no AN */
8654 sc->link_params.req_line_speed[idx] =
8656 sc->port.advertising[idx] |=
8657 (ADVERTISED_10000baseT_Full |
8663 case PORT_FEATURE_LINK_SPEED_10M_FULL:
8665 port.supported[idx] & ELINK_SUPPORTED_10baseT_Full)
8667 sc->link_params.req_line_speed[idx] =
8669 sc->port.advertising[idx] |=
8670 (ADVERTISED_10baseT_Full | ADVERTISED_TP);
8672 PMD_DRV_LOG(ERR, sc,
8673 "Invalid NVRAM config link_config=0x%08x "
8674 "speed_cap_mask=0x%08x",
8677 link_params.speed_cap_mask[idx]);
8682 case PORT_FEATURE_LINK_SPEED_10M_HALF:
8684 port.supported[idx] & ELINK_SUPPORTED_10baseT_Half)
8686 sc->link_params.req_line_speed[idx] =
8688 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8689 sc->port.advertising[idx] |=
8690 (ADVERTISED_10baseT_Half | ADVERTISED_TP);
8692 PMD_DRV_LOG(ERR, sc,
8693 "Invalid NVRAM config link_config=0x%08x "
8694 "speed_cap_mask=0x%08x",
8697 link_params.speed_cap_mask[idx]);
8702 case PORT_FEATURE_LINK_SPEED_100M_FULL:
8704 port.supported[idx] & ELINK_SUPPORTED_100baseT_Full)
8706 sc->link_params.req_line_speed[idx] =
8708 sc->port.advertising[idx] |=
8709 (ADVERTISED_100baseT_Full | ADVERTISED_TP);
8711 PMD_DRV_LOG(ERR, sc,
8712 "Invalid NVRAM config link_config=0x%08x "
8713 "speed_cap_mask=0x%08x",
8716 link_params.speed_cap_mask[idx]);
8721 case PORT_FEATURE_LINK_SPEED_100M_HALF:
8723 port.supported[idx] & ELINK_SUPPORTED_100baseT_Half)
8725 sc->link_params.req_line_speed[idx] =
8727 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8728 sc->port.advertising[idx] |=
8729 (ADVERTISED_100baseT_Half | ADVERTISED_TP);
8731 PMD_DRV_LOG(ERR, sc,
8732 "Invalid NVRAM config link_config=0x%08x "
8733 "speed_cap_mask=0x%08x",
8736 link_params.speed_cap_mask[idx]);
8741 case PORT_FEATURE_LINK_SPEED_1G:
8742 if (sc->port.supported[idx] &
8743 ELINK_SUPPORTED_1000baseT_Full) {
8744 sc->link_params.req_line_speed[idx] =
8746 sc->port.advertising[idx] |=
8747 (ADVERTISED_1000baseT_Full | ADVERTISED_TP);
8749 PMD_DRV_LOG(ERR, sc,
8750 "Invalid NVRAM config link_config=0x%08x "
8751 "speed_cap_mask=0x%08x",
8754 link_params.speed_cap_mask[idx]);
8759 case PORT_FEATURE_LINK_SPEED_2_5G:
8760 if (sc->port.supported[idx] &
8761 ELINK_SUPPORTED_2500baseX_Full) {
8762 sc->link_params.req_line_speed[idx] =
8764 sc->port.advertising[idx] |=
8765 (ADVERTISED_2500baseX_Full | ADVERTISED_TP);
8767 PMD_DRV_LOG(ERR, sc,
8768 "Invalid NVRAM config link_config=0x%08x "
8769 "speed_cap_mask=0x%08x",
8772 link_params.speed_cap_mask[idx]);
8777 case PORT_FEATURE_LINK_SPEED_10G_CX4:
8778 if (sc->port.supported[idx] &
8779 ELINK_SUPPORTED_10000baseT_Full) {
8780 sc->link_params.req_line_speed[idx] =
8782 sc->port.advertising[idx] |=
8783 (ADVERTISED_10000baseT_Full |
8786 PMD_DRV_LOG(ERR, sc,
8787 "Invalid NVRAM config link_config=0x%08x "
8788 "speed_cap_mask=0x%08x",
8791 link_params.speed_cap_mask[idx]);
8796 case PORT_FEATURE_LINK_SPEED_20G:
8797 sc->link_params.req_line_speed[idx] = ELINK_SPEED_20000;
8801 PMD_DRV_LOG(ERR, sc,
8802 "Invalid NVRAM config link_config=0x%08x "
8803 "speed_cap_mask=0x%08x", link_config,
8804 sc->link_params.speed_cap_mask[idx]);
8805 sc->link_params.req_line_speed[idx] =
8806 ELINK_SPEED_AUTO_NEG;
8807 sc->port.advertising[idx] = sc->port.supported[idx];
8811 sc->link_params.req_flow_ctrl[idx] =
8812 (link_config & PORT_FEATURE_FLOW_CONTROL_MASK);
8814 if (sc->link_params.req_flow_ctrl[idx] == ELINK_FLOW_CTRL_AUTO) {
8817 port.supported[idx] & ELINK_SUPPORTED_Autoneg)) {
8818 sc->link_params.req_flow_ctrl[idx] =
8819 ELINK_FLOW_CTRL_NONE;
8821 bnx2x_set_requested_fc(sc);
8827 static void bnx2x_get_phy_info(struct bnx2x_softc *sc)
8829 uint8_t port = SC_PORT(sc);
8832 PMD_INIT_FUNC_TRACE(sc);
8834 /* shmem data already read in bnx2x_get_shmem_info() */
8836 bnx2x_link_settings_supported(sc, sc->link_params.switch_cfg);
8837 bnx2x_link_settings_requested(sc);
8839 /* configure link feature according to nvram value */
8841 (((SHMEM_RD(sc, dev_info.port_feature_config[port].eee_power_mode))
8842 & PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
8843 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
8844 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
8845 sc->link_params.eee_mode = (ELINK_EEE_MODE_ADV_LPI |
8846 ELINK_EEE_MODE_ENABLE_LPI |
8847 ELINK_EEE_MODE_OUTPUT_TIME);
8849 sc->link_params.eee_mode = 0;
8852 /* get the media type */
8853 bnx2x_media_detect(sc);
8856 static void bnx2x_set_modes_bitmap(struct bnx2x_softc *sc)
8858 uint32_t flags = MODE_ASIC | MODE_PORT2;
8860 if (CHIP_IS_E2(sc)) {
8862 } else if (CHIP_IS_E3(sc)) {
8864 if (CHIP_REV(sc) == CHIP_REV_Ax) {
8865 flags |= MODE_E3_A0;
8866 } else { /*if (CHIP_REV(sc) == CHIP_REV_Bx) */
8868 flags |= MODE_E3_B0 | MODE_COS3;
8874 switch (sc->devinfo.mf_info.mf_mode) {
8875 case MULTI_FUNCTION_SD:
8876 flags |= MODE_MF_SD;
8878 case MULTI_FUNCTION_SI:
8879 flags |= MODE_MF_SI;
8881 case MULTI_FUNCTION_AFEX:
8882 flags |= MODE_MF_AFEX;
8889 #if defined(__LITTLE_ENDIAN)
8890 flags |= MODE_LITTLE_ENDIAN;
8891 #else /* __BIG_ENDIAN */
8892 flags |= MODE_BIG_ENDIAN;
8895 INIT_MODE_FLAGS(sc) = flags;
8898 int bnx2x_alloc_hsi_mem(struct bnx2x_softc *sc)
8900 struct bnx2x_fastpath *fp;
8905 /************************/
8906 /* DEFAULT STATUS BLOCK */
8907 /************************/
8909 if (bnx2x_dma_alloc(sc, sizeof(struct host_sp_status_block),
8910 &sc->def_sb_dma, "def_sb",
8911 RTE_CACHE_LINE_SIZE) != 0) {
8916 (struct host_sp_status_block *)sc->def_sb_dma.vaddr;
8921 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8922 &sc->eq_dma, "ev_queue",
8923 RTE_CACHE_LINE_SIZE) != 0) {
8928 sc->eq = (union event_ring_elem *)sc->eq_dma.vaddr;
8934 if (bnx2x_dma_alloc(sc, sizeof(struct bnx2x_slowpath),
8936 RTE_CACHE_LINE_SIZE) != 0) {
8942 sc->sp = (struct bnx2x_slowpath *)sc->sp_dma.vaddr;
8944 /*******************/
8945 /* SLOW PATH QUEUE */
8946 /*******************/
8948 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8949 &sc->spq_dma, "sp_queue",
8950 RTE_CACHE_LINE_SIZE) != 0) {
8957 sc->spq = (struct eth_spe *)sc->spq_dma.vaddr;
8959 /***************************/
8960 /* FW DECOMPRESSION BUFFER */
8961 /***************************/
8963 if (bnx2x_dma_alloc(sc, FW_BUF_SIZE, &sc->gz_buf_dma,
8964 "fw_buf", RTE_CACHE_LINE_SIZE) != 0) {
8972 sc->gz_buf = (void *)sc->gz_buf_dma.vaddr;
8979 /* allocate DMA memory for each fastpath structure */
8980 for (i = 0; i < sc->num_queues; i++) {
8985 /*******************/
8986 /* FP STATUS BLOCK */
8987 /*******************/
8989 snprintf(buf, sizeof(buf), "fp_%d_sb", i);
8990 if (bnx2x_dma_alloc(sc, sizeof(union bnx2x_host_hc_status_block),
8991 &fp->sb_dma, buf, RTE_CACHE_LINE_SIZE) != 0) {
8992 PMD_DRV_LOG(NOTICE, sc, "Failed to alloc %s", buf);
8995 if (CHIP_IS_E2E3(sc)) {
8996 fp->status_block.e2_sb =
8997 (struct host_hc_status_block_e2 *)
9000 fp->status_block.e1x_sb =
9001 (struct host_hc_status_block_e1x *)
9010 void bnx2x_free_hsi_mem(struct bnx2x_softc *sc)
9012 struct bnx2x_fastpath *fp;
9015 for (i = 0; i < sc->num_queues; i++) {
9018 /*******************/
9019 /* FP STATUS BLOCK */
9020 /*******************/
9022 memset(&fp->status_block, 0, sizeof(fp->status_block));
9023 bnx2x_dma_free(&fp->sb_dma);
9026 /***************************/
9027 /* FW DECOMPRESSION BUFFER */
9028 /***************************/
9030 bnx2x_dma_free(&sc->gz_buf_dma);
9033 /*******************/
9034 /* SLOW PATH QUEUE */
9035 /*******************/
9037 bnx2x_dma_free(&sc->spq_dma);
9044 bnx2x_dma_free(&sc->sp_dma);
9051 bnx2x_dma_free(&sc->eq_dma);
9054 /************************/
9055 /* DEFAULT STATUS BLOCK */
9056 /************************/
9058 bnx2x_dma_free(&sc->def_sb_dma);
9064 * Previous driver DMAE transaction may have occurred when pre-boot stage
9065 * ended and boot began. This would invalidate the addresses of the
9066 * transaction, resulting in was-error bit set in the PCI causing all
9067 * hw-to-host PCIe transactions to timeout. If this happened we want to clear
9068 * the interrupt which detected this from the pglueb and the was-done bit
9070 static void bnx2x_prev_interrupted_dmae(struct bnx2x_softc *sc)
9074 if (!CHIP_IS_E1x(sc)) {
9075 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS);
9076 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
9077 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
9083 static int bnx2x_prev_mcp_done(struct bnx2x_softc *sc)
9085 uint32_t rc = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE,
9086 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
9088 PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
9095 static struct bnx2x_prev_list_node *bnx2x_prev_path_get_entry(struct bnx2x_softc *sc)
9097 struct bnx2x_prev_list_node *tmp;
9099 LIST_FOREACH(tmp, &bnx2x_prev_list, node) {
9100 if ((sc->pcie_bus == tmp->bus) &&
9101 (sc->pcie_device == tmp->slot) &&
9102 (SC_PATH(sc) == tmp->path)) {
9110 static uint8_t bnx2x_prev_is_path_marked(struct bnx2x_softc *sc)
9112 struct bnx2x_prev_list_node *tmp;
9115 rte_spinlock_lock(&bnx2x_prev_mtx);
9117 tmp = bnx2x_prev_path_get_entry(sc);
9120 PMD_DRV_LOG(DEBUG, sc,
9121 "Path %d/%d/%d was marked by AER",
9122 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9125 PMD_DRV_LOG(DEBUG, sc,
9126 "Path %d/%d/%d was already cleaned from previous drivers",
9127 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9131 rte_spinlock_unlock(&bnx2x_prev_mtx);
9136 static int bnx2x_prev_mark_path(struct bnx2x_softc *sc, uint8_t after_undi)
9138 struct bnx2x_prev_list_node *tmp;
9140 rte_spinlock_lock(&bnx2x_prev_mtx);
9142 /* Check whether the entry for this path already exists */
9143 tmp = bnx2x_prev_path_get_entry(sc);
9146 PMD_DRV_LOG(DEBUG, sc,
9147 "Re-marking AER in path %d/%d/%d",
9148 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9150 PMD_DRV_LOG(DEBUG, sc,
9151 "Removing AER indication from path %d/%d/%d",
9152 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9156 rte_spinlock_unlock(&bnx2x_prev_mtx);
9160 rte_spinlock_unlock(&bnx2x_prev_mtx);
9162 /* Create an entry for this path and add it */
9163 tmp = rte_malloc("", sizeof(struct bnx2x_prev_list_node),
9164 RTE_CACHE_LINE_SIZE);
9166 PMD_DRV_LOG(NOTICE, sc, "Failed to allocate 'bnx2x_prev_list_node'");
9170 tmp->bus = sc->pcie_bus;
9171 tmp->slot = sc->pcie_device;
9172 tmp->path = SC_PATH(sc);
9174 tmp->undi = after_undi ? (1 << SC_PORT(sc)) : 0;
9176 rte_spinlock_lock(&bnx2x_prev_mtx);
9178 LIST_INSERT_HEAD(&bnx2x_prev_list, tmp, node);
9180 rte_spinlock_unlock(&bnx2x_prev_mtx);
9185 static int bnx2x_do_flr(struct bnx2x_softc *sc)
9189 /* only E2 and onwards support FLR */
9190 if (CHIP_IS_E1x(sc)) {
9191 PMD_DRV_LOG(WARNING, sc, "FLR not supported in E1H");
9195 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9196 if (sc->devinfo.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9197 PMD_DRV_LOG(WARNING, sc,
9198 "FLR not supported by BC_VER: 0x%08x",
9199 sc->devinfo.bc_ver);
9203 /* Wait for Transaction Pending bit clean */
9204 for (i = 0; i < 4; i++) {
9206 DELAY(((1 << (i - 1)) * 100) * 1000);
9209 if (!bnx2x_is_pcie_pending(sc)) {
9214 PMD_DRV_LOG(NOTICE, sc, "PCIE transaction is not cleared, "
9215 "proceeding with reset anyway");
9218 bnx2x_fw_command(sc, DRV_MSG_CODE_INITIATE_FLR, 0);
9223 struct bnx2x_mac_vals {
9231 uint32_t bmac_val[2];
9235 bnx2x_prev_unload_close_mac(struct bnx2x_softc *sc, struct bnx2x_mac_vals *vals)
9237 uint32_t val, base_addr, offset, mask, reset_reg;
9238 uint8_t mac_stopped = FALSE;
9239 uint8_t port = SC_PORT(sc);
9240 uint32_t wb_data[2];
9242 /* reset addresses as they also mark which values were changed */
9243 vals->bmac_addr = 0;
9244 vals->umac_addr = 0;
9245 vals->xmac_addr = 0;
9246 vals->emac_addr = 0;
9248 reset_reg = REG_RD(sc, MISC_REG_RESET_REG_2);
9250 if (!CHIP_IS_E3(sc)) {
9251 val = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9252 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9253 if ((mask & reset_reg) && val) {
9254 base_addr = SC_PORT(sc) ? NIG_REG_INGRESS_BMAC1_MEM
9255 : NIG_REG_INGRESS_BMAC0_MEM;
9256 offset = CHIP_IS_E2(sc) ? BIGMAC2_REGISTER_BMAC_CONTROL
9257 : BIGMAC_REGISTER_BMAC_CONTROL;
9260 * use rd/wr since we cannot use dmae. This is safe
9261 * since MCP won't access the bus due to the request
9262 * to unload, and no function on the path can be
9263 * loaded at this time.
9265 wb_data[0] = REG_RD(sc, base_addr + offset);
9266 wb_data[1] = REG_RD(sc, base_addr + offset + 0x4);
9267 vals->bmac_addr = base_addr + offset;
9268 vals->bmac_val[0] = wb_data[0];
9269 vals->bmac_val[1] = wb_data[1];
9270 wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE;
9271 REG_WR(sc, vals->bmac_addr, wb_data[0]);
9272 REG_WR(sc, vals->bmac_addr + 0x4, wb_data[1]);
9275 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + SC_PORT(sc) * 4;
9276 vals->emac_val = REG_RD(sc, vals->emac_addr);
9277 REG_WR(sc, vals->emac_addr, 0);
9280 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9281 base_addr = SC_PORT(sc) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9282 val = REG_RD(sc, base_addr + XMAC_REG_PFC_CTRL_HI);
9283 REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9285 REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9287 vals->xmac_addr = base_addr + XMAC_REG_CTRL;
9288 vals->xmac_val = REG_RD(sc, vals->xmac_addr);
9289 REG_WR(sc, vals->xmac_addr, 0);
9293 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9294 if (mask & reset_reg) {
9295 base_addr = SC_PORT(sc) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9296 vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
9297 vals->umac_val = REG_RD(sc, vals->umac_addr);
9298 REG_WR(sc, vals->umac_addr, 0);
9308 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9309 #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
9310 #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
9311 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
9314 bnx2x_prev_unload_undi_inc(struct bnx2x_softc *sc, uint8_t port, uint8_t inc)
9317 uint32_t tmp_reg = REG_RD(sc, BNX2X_PREV_UNDI_PROD_ADDR(port));
9319 rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9320 bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9322 tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9323 REG_WR(sc, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9326 static int bnx2x_prev_unload_common(struct bnx2x_softc *sc)
9328 uint32_t reset_reg, tmp_reg = 0, rc;
9329 uint8_t prev_undi = FALSE;
9330 struct bnx2x_mac_vals mac_vals;
9331 uint32_t timer_count = 1000;
9335 * It is possible a previous function received 'common' answer,
9336 * but hasn't loaded yet, therefore creating a scenario of
9337 * multiple functions receiving 'common' on the same path.
9339 memset(&mac_vals, 0, sizeof(mac_vals));
9341 if (bnx2x_prev_is_path_marked(sc)) {
9342 return bnx2x_prev_mcp_done(sc);
9345 reset_reg = REG_RD(sc, MISC_REG_RESET_REG_1);
9347 /* Reset should be performed after BRB is emptied */
9348 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
9349 /* Close the MAC Rx to prevent BRB from filling up */
9350 bnx2x_prev_unload_close_mac(sc, &mac_vals);
9352 /* close LLH filters towards the BRB */
9353 elink_set_rx_filter(&sc->link_params, 0);
9356 * Check if the UNDI driver was previously loaded.
9357 * UNDI driver initializes CID offset for normal bell to 0x7
9359 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
9360 tmp_reg = REG_RD(sc, DORQ_REG_NORM_CID_OFST);
9361 if (tmp_reg == 0x7) {
9362 PMD_DRV_LOG(DEBUG, sc, "UNDI previously loaded");
9364 /* clear the UNDI indication */
9365 REG_WR(sc, DORQ_REG_NORM_CID_OFST, 0);
9366 /* clear possible idle check errors */
9367 REG_RD(sc, NIG_REG_NIG_INT_STS_CLR_0);
9371 /* wait until BRB is empty */
9372 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9373 while (timer_count) {
9376 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9381 PMD_DRV_LOG(DEBUG, sc, "BRB still has 0x%08x", tmp_reg);
9383 /* reset timer as long as BRB actually gets emptied */
9384 if (prev_brb > tmp_reg) {
9390 /* If UNDI resides in memory, manually increment it */
9392 bnx2x_prev_unload_undi_inc(sc, SC_PORT(sc), 1);
9399 PMD_DRV_LOG(NOTICE, sc, "Failed to empty BRB");
9403 /* No packets are in the pipeline, path is ready for reset */
9404 bnx2x_reset_common(sc);
9406 if (mac_vals.xmac_addr) {
9407 REG_WR(sc, mac_vals.xmac_addr, mac_vals.xmac_val);
9409 if (mac_vals.umac_addr) {
9410 REG_WR(sc, mac_vals.umac_addr, mac_vals.umac_val);
9412 if (mac_vals.emac_addr) {
9413 REG_WR(sc, mac_vals.emac_addr, mac_vals.emac_val);
9415 if (mac_vals.bmac_addr) {
9416 REG_WR(sc, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
9417 REG_WR(sc, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
9420 rc = bnx2x_prev_mark_path(sc, prev_undi);
9422 bnx2x_prev_mcp_done(sc);
9426 return bnx2x_prev_mcp_done(sc);
9429 static int bnx2x_prev_unload_uncommon(struct bnx2x_softc *sc)
9433 /* Test if previous unload process was already finished for this path */
9434 if (bnx2x_prev_is_path_marked(sc)) {
9435 return bnx2x_prev_mcp_done(sc);
9439 * If function has FLR capabilities, and existing FW version matches
9440 * the one required, then FLR will be sufficient to clean any residue
9441 * left by previous driver
9443 rc = bnx2x_nic_load_analyze_req(sc, FW_MSG_CODE_DRV_LOAD_FUNCTION);
9445 /* fw version is good */
9446 rc = bnx2x_do_flr(sc);
9450 /* FLR was performed */
9454 PMD_DRV_LOG(INFO, sc, "Could not FLR");
9456 /* Close the MCP request, return failure */
9457 rc = bnx2x_prev_mcp_done(sc);
9459 rc = BNX2X_PREV_WAIT_NEEDED;
9465 static int bnx2x_prev_unload(struct bnx2x_softc *sc)
9467 int time_counter = 10;
9468 uint32_t fw, hw_lock_reg, hw_lock_val;
9471 PMD_INIT_FUNC_TRACE(sc);
9474 * Clear HW from errors which may have resulted from an interrupted
9477 bnx2x_prev_interrupted_dmae(sc);
9479 /* Release previously held locks */
9480 hw_lock_reg = (SC_FUNC(sc) <= 5) ?
9481 (MISC_REG_DRIVER_CONTROL_1 + SC_FUNC(sc) * 8) :
9482 (MISC_REG_DRIVER_CONTROL_7 + (SC_FUNC(sc) - 6) * 8);
9484 hw_lock_val = (REG_RD(sc, hw_lock_reg));
9486 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
9487 PMD_DRV_LOG(DEBUG, sc, "Releasing previously held NVRAM lock\n");
9488 REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
9489 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << SC_PORT(sc)));
9491 PMD_DRV_LOG(DEBUG, sc, "Releasing previously held HW lock\n");
9492 REG_WR(sc, hw_lock_reg, 0xffffffff);
9495 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(sc, MCP_REG_MCPR_ACCESS_LOCK)) {
9496 PMD_DRV_LOG(DEBUG, sc, "Releasing previously held ALR\n");
9497 REG_WR(sc, MCP_REG_MCPR_ACCESS_LOCK, 0);
9501 /* Lock MCP using an unload request */
9502 fw = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
9504 PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
9509 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
9510 rc = bnx2x_prev_unload_common(sc);
9514 /* non-common reply from MCP might require looping */
9515 rc = bnx2x_prev_unload_uncommon(sc);
9516 if (rc != BNX2X_PREV_WAIT_NEEDED) {
9521 } while (--time_counter);
9523 if (!time_counter || rc) {
9524 PMD_DRV_LOG(NOTICE, sc, "Failed to unload previous driver!");
9532 bnx2x_dcbx_set_state(struct bnx2x_softc *sc, uint8_t dcb_on, uint32_t dcbx_enabled)
9534 if (!CHIP_IS_E1x(sc)) {
9535 sc->dcb_state = dcb_on;
9536 sc->dcbx_enabled = dcbx_enabled;
9538 sc->dcb_state = FALSE;
9539 sc->dcbx_enabled = BNX2X_DCBX_ENABLED_INVALID;
9541 PMD_DRV_LOG(DEBUG, sc,
9542 "DCB state [%s:%s]",
9543 dcb_on ? "ON" : "OFF",
9544 (dcbx_enabled == BNX2X_DCBX_ENABLED_OFF) ? "user-mode" :
9546 BNX2X_DCBX_ENABLED_ON_NEG_OFF) ? "on-chip static"
9548 BNX2X_DCBX_ENABLED_ON_NEG_ON) ?
9549 "on-chip with negotiation" : "invalid");
9552 static int bnx2x_set_qm_cid_count(struct bnx2x_softc *sc)
9554 int cid_count = BNX2X_L2_MAX_CID(sc);
9556 if (CNIC_SUPPORT(sc)) {
9557 cid_count += CNIC_CID_MAX;
9560 return roundup(cid_count, QM_CID_ROUND);
9563 static void bnx2x_init_multi_cos(struct bnx2x_softc *sc)
9567 uint32_t pri_map = 0;
9569 for (pri = 0; pri < BNX2X_MAX_PRIORITY; pri++) {
9570 cos = ((pri_map & (0xf << (pri * 4))) >> (pri * 4));
9571 if (cos < sc->max_cos) {
9572 sc->prio_to_cos[pri] = cos;
9574 PMD_DRV_LOG(WARNING, sc,
9575 "Invalid COS %d for priority %d "
9576 "(max COS is %d), setting to 0", cos, pri,
9578 sc->prio_to_cos[pri] = 0;
9583 static int bnx2x_pci_get_caps(struct bnx2x_softc *sc)
9590 struct bnx2x_pci_cap *cap;
9592 cap = sc->pci_caps = rte_zmalloc("caps", sizeof(struct bnx2x_pci_cap),
9593 RTE_CACHE_LINE_SIZE);
9595 PMD_DRV_LOG(NOTICE, sc, "Failed to allocate memory");
9600 pci_read(sc, PCI_STATUS, &status, 2);
9601 if (!(status & PCI_STATUS_CAP_LIST)) {
9603 pci_read(sc, PCIR_STATUS, &status, 2);
9604 if (!(status & PCIM_STATUS_CAPPRESENT)) {
9606 PMD_DRV_LOG(NOTICE, sc, "PCIe capability reading failed");
9611 pci_read(sc, PCI_CAPABILITY_LIST, &pci_cap.next, 1);
9613 pci_read(sc, PCIR_CAP_PTR, &pci_cap.next, 1);
9615 while (pci_cap.next) {
9616 cap->addr = pci_cap.next & ~3;
9617 pci_read(sc, pci_cap.next & ~3, &pci_cap, 2);
9618 if (pci_cap.id == 0xff)
9620 cap->id = pci_cap.id;
9621 cap->type = BNX2X_PCI_CAP;
9622 cap->next = rte_zmalloc("pci_cap",
9623 sizeof(struct bnx2x_pci_cap),
9624 RTE_CACHE_LINE_SIZE);
9626 PMD_DRV_LOG(NOTICE, sc, "Failed to allocate memory");
9635 static void bnx2x_init_rte(struct bnx2x_softc *sc)
9638 sc->max_tx_queues = min(BNX2X_VF_MAX_QUEUES_PER_VF,
9640 sc->max_rx_queues = min(BNX2X_VF_MAX_QUEUES_PER_VF,
9643 sc->max_rx_queues = BNX2X_MAX_RSS_COUNT(sc);
9644 sc->max_tx_queues = sc->max_rx_queues;
9648 #define FW_HEADER_LEN 104
9649 #define FW_NAME_57711 "/lib/firmware/bnx2x/bnx2x-e1h-7.2.51.0.fw"
9650 #define FW_NAME_57810 "/lib/firmware/bnx2x/bnx2x-e2-7.2.51.0.fw"
9652 void bnx2x_load_firmware(struct bnx2x_softc *sc)
9658 fwname = sc->devinfo.device_id == CHIP_NUM_57711
9659 ? FW_NAME_57711 : FW_NAME_57810;
9660 f = open(fwname, O_RDONLY);
9662 PMD_DRV_LOG(NOTICE, sc, "Can't open firmware file");
9666 if (fstat(f, &st) < 0) {
9667 PMD_DRV_LOG(NOTICE, sc, "Can't stat firmware file");
9672 sc->firmware = rte_zmalloc("bnx2x_fw", st.st_size, RTE_CACHE_LINE_SIZE);
9673 if (!sc->firmware) {
9674 PMD_DRV_LOG(NOTICE, sc, "Can't allocate memory for firmware");
9679 if (read(f, sc->firmware, st.st_size) != st.st_size) {
9680 PMD_DRV_LOG(NOTICE, sc, "Can't read firmware data");
9686 sc->fw_len = st.st_size;
9687 if (sc->fw_len < FW_HEADER_LEN) {
9688 PMD_DRV_LOG(NOTICE, sc,
9689 "Invalid fw size: %" PRIu64, sc->fw_len);
9692 PMD_DRV_LOG(DEBUG, sc, "fw_len = %" PRIu64, sc->fw_len);
9696 bnx2x_data_to_init_ops(uint8_t * data, struct raw_op *dst, uint32_t len)
9698 uint32_t *src = (uint32_t *) data;
9701 for (i = 0, j = 0; i < len / 8; ++i, j += 2) {
9702 tmp = rte_be_to_cpu_32(src[j]);
9703 dst[i].op = (tmp >> 24) & 0xFF;
9704 dst[i].offset = tmp & 0xFFFFFF;
9705 dst[i].raw_data = rte_be_to_cpu_32(src[j + 1]);
9710 bnx2x_data_to_init_offsets(uint8_t * data, uint16_t * dst, uint32_t len)
9712 uint16_t *src = (uint16_t *) data;
9715 for (i = 0; i < len / 2; ++i)
9716 dst[i] = rte_be_to_cpu_16(src[i]);
9719 static void bnx2x_data_to_init_data(uint8_t * data, uint32_t * dst, uint32_t len)
9721 uint32_t *src = (uint32_t *) data;
9724 for (i = 0; i < len / 4; ++i)
9725 dst[i] = rte_be_to_cpu_32(src[i]);
9728 static void bnx2x_data_to_iro_array(uint8_t * data, struct iro *dst, uint32_t len)
9730 uint32_t *src = (uint32_t *) data;
9733 for (i = 0, j = 0; i < len / sizeof(struct iro); ++i, ++j) {
9734 dst[i].base = rte_be_to_cpu_32(src[j++]);
9735 tmp = rte_be_to_cpu_32(src[j]);
9736 dst[i].m1 = (tmp >> 16) & 0xFFFF;
9737 dst[i].m2 = tmp & 0xFFFF;
9739 tmp = rte_be_to_cpu_32(src[j]);
9740 dst[i].m3 = (tmp >> 16) & 0xFFFF;
9741 dst[i].size = tmp & 0xFFFF;
9746 * Device attach function.
9748 * Allocates device resources, performs secondary chip identification, and
9749 * initializes driver instance variables. This function is called from driver
9750 * load after a successful probe.
9753 * 0 = Success, >0 = Failure
9755 int bnx2x_attach(struct bnx2x_softc *sc)
9759 PMD_DRV_LOG(DEBUG, sc, "Starting attach...");
9761 rc = bnx2x_pci_get_caps(sc);
9763 PMD_DRV_LOG(NOTICE, sc, "PCIe caps reading was failed");
9767 sc->state = BNX2X_STATE_CLOSED;
9769 pci_write_long(sc, PCICFG_GRC_ADDRESS, PCICFG_VENDOR_ID_OFFSET);
9771 sc->igu_base_addr = IS_VF(sc) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
9773 /* get PCI capabilites */
9774 bnx2x_probe_pci_caps(sc);
9776 if (sc->devinfo.pcie_msix_cap_reg != 0) {
9779 (sc->devinfo.pcie_msix_cap_reg + PCIR_MSIX_CTRL), &val,
9781 sc->igu_sb_cnt = (val & PCIM_MSIXCTRL_TABLE_SIZE) + 1;
9786 /* Init RTE stuff */
9790 /* Enable internal target-read (in case we are probed after PF
9791 * FLR). Must be done prior to any BAR read access. Only for
9794 if (!CHIP_IS_E1x(sc)) {
9795 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ,
9800 /* get device info and set params */
9801 if (bnx2x_get_device_info(sc) != 0) {
9802 PMD_DRV_LOG(NOTICE, sc, "getting device info");
9806 /* get phy settings from shmem and 'and' against admin settings */
9807 bnx2x_get_phy_info(sc);
9809 /* Left mac of VF unfilled, PF should set it for VF */
9810 memset(sc->link_params.mac_addr, 0, RTE_ETHER_ADDR_LEN);
9815 /* set the default MTU (changed via ifconfig) */
9816 sc->mtu = RTE_ETHER_MTU;
9818 bnx2x_set_modes_bitmap(sc);
9820 /* need to reset chip if UNDI was active */
9821 if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
9824 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
9825 DRV_MSG_SEQ_NUMBER_MASK);
9826 PMD_DRV_LOG(DEBUG, sc, "prev unload fw_seq 0x%04x",
9828 bnx2x_prev_unload(sc);
9831 bnx2x_dcbx_set_state(sc, FALSE, BNX2X_DCBX_ENABLED_OFF);
9833 /* calculate qm_cid_count */
9834 sc->qm_cid_count = bnx2x_set_qm_cid_count(sc);
9837 bnx2x_init_multi_cos(sc);
9843 bnx2x_igu_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t segment,
9844 uint16_t index, uint8_t op, uint8_t update)
9846 uint32_t igu_addr = sc->igu_base_addr;
9847 igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
9848 bnx2x_igu_ack_sb_gen(sc, segment, index, op, update, igu_addr);
9852 bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t storm,
9853 uint16_t index, uint8_t op, uint8_t update)
9855 if (unlikely(sc->devinfo.int_block == INT_BLOCK_HC))
9856 bnx2x_hc_ack_sb(sc, igu_sb_id, storm, index, op, update);
9859 if (CHIP_INT_MODE_IS_BC(sc)) {
9861 } else if (igu_sb_id != sc->igu_dsb_id) {
9862 segment = IGU_SEG_ACCESS_DEF;
9863 } else if (storm == ATTENTION_ID) {
9864 segment = IGU_SEG_ACCESS_ATTN;
9866 segment = IGU_SEG_ACCESS_DEF;
9868 bnx2x_igu_ack_sb(sc, igu_sb_id, segment, index, op, update);
9873 bnx2x_igu_clear_sb_gen(struct bnx2x_softc *sc, uint8_t func, uint8_t idu_sb_id,
9876 uint32_t data, ctl, cnt = 100;
9877 uint32_t igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
9878 uint32_t igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
9879 uint32_t igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP +
9880 (idu_sb_id / 32) * 4;
9881 uint32_t sb_bit = 1 << (idu_sb_id % 32);
9882 uint32_t func_encode = func |
9883 (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
9884 uint32_t addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
9886 /* Not supported in BC mode */
9887 if (CHIP_INT_MODE_IS_BC(sc)) {
9891 data = ((IGU_USE_REGISTER_cstorm_type_0_sb_cleanup <<
9892 IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
9893 IGU_REGULAR_CLEANUP_SET | IGU_REGULAR_BCLEANUP);
9895 ctl = ((addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT) |
9896 (func_encode << IGU_CTRL_REG_FID_SHIFT) |
9897 (IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT));
9899 REG_WR(sc, igu_addr_data, data);
9903 PMD_DRV_LOG(DEBUG, sc, "write 0x%08x to IGU(via GRC) addr 0x%x",
9905 REG_WR(sc, igu_addr_ctl, ctl);
9909 /* wait for clean up to finish */
9910 while (!(REG_RD(sc, igu_addr_ack) & sb_bit) && --cnt) {
9914 if (!(REG_RD(sc, igu_addr_ack) & sb_bit)) {
9915 PMD_DRV_LOG(DEBUG, sc,
9916 "Unable to finish IGU cleanup: "
9917 "idu_sb_id %d offset %d bit %d (cnt %d)",
9918 idu_sb_id, idu_sb_id / 32, idu_sb_id % 32, cnt);
9922 static void bnx2x_igu_clear_sb(struct bnx2x_softc *sc, uint8_t idu_sb_id)
9924 bnx2x_igu_clear_sb_gen(sc, SC_FUNC(sc), idu_sb_id, TRUE /*PF*/);
9927 /*******************/
9928 /* ECORE CALLBACKS */
9929 /*******************/
9931 static void bnx2x_reset_common(struct bnx2x_softc *sc)
9933 uint32_t val = 0x1400;
9935 PMD_INIT_FUNC_TRACE(sc);
9938 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR),
9941 if (CHIP_IS_E3(sc)) {
9942 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
9943 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
9946 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR), val);
9949 static void bnx2x_common_init_phy(struct bnx2x_softc *sc)
9951 uint32_t shmem_base[2];
9952 uint32_t shmem2_base[2];
9954 /* Avoid common init in case MFW supports LFA */
9955 if (SHMEM2_RD(sc, size) >
9956 (uint32_t) offsetof(struct shmem2_region,
9957 lfa_host_addr[SC_PORT(sc)])) {
9961 shmem_base[0] = sc->devinfo.shmem_base;
9962 shmem2_base[0] = sc->devinfo.shmem2_base;
9964 if (!CHIP_IS_E1x(sc)) {
9965 shmem_base[1] = SHMEM2_RD(sc, other_shmem_base_addr);
9966 shmem2_base[1] = SHMEM2_RD(sc, other_shmem2_base_addr);
9969 bnx2x_acquire_phy_lock(sc);
9970 elink_common_init_phy(sc, shmem_base, shmem2_base,
9971 sc->devinfo.chip_id, 0);
9972 bnx2x_release_phy_lock(sc);
9975 static void bnx2x_pf_disable(struct bnx2x_softc *sc)
9977 uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
9979 val &= ~IGU_PF_CONF_FUNC_EN;
9981 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
9982 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
9983 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 0);
9986 static void bnx2x_init_pxp(struct bnx2x_softc *sc)
9989 int r_order, w_order;
9991 devctl = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_CTL);
9993 w_order = ((devctl & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5);
9994 r_order = ((devctl & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12);
9996 ecore_init_pxp_arb(sc, r_order, w_order);
9999 static uint32_t bnx2x_get_pretend_reg(struct bnx2x_softc *sc)
10001 uint32_t base = PXP2_REG_PGL_PRETEND_FUNC_F0;
10002 uint32_t stride = (PXP2_REG_PGL_PRETEND_FUNC_F1 - base);
10003 return base + (SC_ABS_FUNC(sc)) * stride;
10007 * Called only on E1H or E2.
10008 * When pretending to be PF, the pretend value is the function number 0..7.
10009 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
10012 static int bnx2x_pretend_func(struct bnx2x_softc *sc, uint16_t pretend_func_val)
10014 uint32_t pretend_reg;
10016 if (CHIP_IS_E1H(sc) && (pretend_func_val > E1H_FUNC_MAX))
10019 /* get my own pretend register */
10020 pretend_reg = bnx2x_get_pretend_reg(sc);
10021 REG_WR(sc, pretend_reg, pretend_func_val);
10022 REG_RD(sc, pretend_reg);
10026 static void bnx2x_setup_fan_failure_detection(struct bnx2x_softc *sc)
10033 val = (SHMEM_RD(sc, dev_info.shared_hw_config.config2) &
10034 SHARED_HW_CFG_FAN_FAILURE_MASK);
10036 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) {
10040 * The fan failure mechanism is usually related to the PHY type since
10041 * the power consumption of the board is affected by the PHY. Currently,
10042 * fan is required for most designs with SFX7101, BNX2X8727 and BNX2X8481.
10044 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) {
10045 for (port = PORT_0; port < PORT_MAX; port++) {
10046 is_required |= elink_fan_failure_det_req(sc,
10048 devinfo.shmem_base,
10050 devinfo.shmem2_base,
10055 if (is_required == 0) {
10059 /* Fan failure is indicated by SPIO 5 */
10060 bnx2x_set_spio(sc, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
10062 /* set to active low mode */
10063 val = REG_RD(sc, MISC_REG_SPIO_INT);
10064 val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
10065 REG_WR(sc, MISC_REG_SPIO_INT, val);
10067 /* enable interrupt to signal the IGU */
10068 val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
10069 val |= MISC_SPIO_SPIO5;
10070 REG_WR(sc, MISC_REG_SPIO_EVENT_EN, val);
10073 static void bnx2x_enable_blocks_attention(struct bnx2x_softc *sc)
10077 REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0);
10078 if (!CHIP_IS_E1x(sc)) {
10079 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0x40);
10081 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0);
10083 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
10084 REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
10086 * mask read length error interrupts in brb for parser
10087 * (parsing unit and 'checksum and crc' unit)
10088 * these errors are legal (PU reads fixed length and CAC can cause
10089 * read length error on truncated packets)
10091 REG_WR(sc, BRB1_REG_BRB1_INT_MASK, 0xFC00);
10092 REG_WR(sc, QM_REG_QM_INT_MASK, 0);
10093 REG_WR(sc, TM_REG_TM_INT_MASK, 0);
10094 REG_WR(sc, XSDM_REG_XSDM_INT_MASK_0, 0);
10095 REG_WR(sc, XSDM_REG_XSDM_INT_MASK_1, 0);
10096 REG_WR(sc, XCM_REG_XCM_INT_MASK, 0);
10097 /* REG_WR(sc, XSEM_REG_XSEM_INT_MASK_0, 0); */
10098 /* REG_WR(sc, XSEM_REG_XSEM_INT_MASK_1, 0); */
10099 REG_WR(sc, USDM_REG_USDM_INT_MASK_0, 0);
10100 REG_WR(sc, USDM_REG_USDM_INT_MASK_1, 0);
10101 REG_WR(sc, UCM_REG_UCM_INT_MASK, 0);
10102 /* REG_WR(sc, USEM_REG_USEM_INT_MASK_0, 0); */
10103 /* REG_WR(sc, USEM_REG_USEM_INT_MASK_1, 0); */
10104 REG_WR(sc, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
10105 REG_WR(sc, CSDM_REG_CSDM_INT_MASK_0, 0);
10106 REG_WR(sc, CSDM_REG_CSDM_INT_MASK_1, 0);
10107 REG_WR(sc, CCM_REG_CCM_INT_MASK, 0);
10108 /* REG_WR(sc, CSEM_REG_CSEM_INT_MASK_0, 0); */
10109 /* REG_WR(sc, CSEM_REG_CSEM_INT_MASK_1, 0); */
10111 val = (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
10112 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
10113 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN);
10114 if (!CHIP_IS_E1x(sc)) {
10115 val |= (PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
10116 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED);
10118 REG_WR(sc, PXP2_REG_PXP2_INT_MASK_0, val);
10120 REG_WR(sc, TSDM_REG_TSDM_INT_MASK_0, 0);
10121 REG_WR(sc, TSDM_REG_TSDM_INT_MASK_1, 0);
10122 REG_WR(sc, TCM_REG_TCM_INT_MASK, 0);
10123 /* REG_WR(sc, TSEM_REG_TSEM_INT_MASK_0, 0); */
10125 if (!CHIP_IS_E1x(sc)) {
10126 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
10127 REG_WR(sc, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
10130 REG_WR(sc, CDU_REG_CDU_INT_MASK, 0);
10131 REG_WR(sc, DMAE_REG_DMAE_INT_MASK, 0);
10132 /* REG_WR(sc, MISC_REG_MISC_INT_MASK, 0); */
10133 REG_WR(sc, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
10137 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
10139 * @sc: driver handle
10141 static int bnx2x_init_hw_common(struct bnx2x_softc *sc)
10143 uint8_t abs_func_id;
10146 PMD_DRV_LOG(DEBUG, sc,
10147 "starting common init for func %d", SC_ABS_FUNC(sc));
10150 * take the RESET lock to protect undi_unload flow from accessing
10151 * registers while we are resetting the chip
10153 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10155 bnx2x_reset_common(sc);
10157 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET), 0xffffffff);
10160 if (CHIP_IS_E3(sc)) {
10161 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
10162 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
10165 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET), val);
10167 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10169 ecore_init_block(sc, BLOCK_MISC, PHASE_COMMON);
10171 if (!CHIP_IS_E1x(sc)) {
10173 * 4-port mode or 2-port mode we need to turn off master-enable for
10174 * everyone. After that we turn it back on for self. So, we disregard
10175 * multi-function, and always disable all functions on the given path,
10176 * this means 0,2,4,6 for path 0 and 1,3,5,7 for path 1
10178 for (abs_func_id = SC_PATH(sc);
10179 abs_func_id < (E2_FUNC_MAX * 2); abs_func_id += 2) {
10180 if (abs_func_id == SC_ABS_FUNC(sc)) {
10182 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
10187 bnx2x_pretend_func(sc, abs_func_id);
10189 /* clear pf enable */
10190 bnx2x_pf_disable(sc);
10192 bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10196 ecore_init_block(sc, BLOCK_PXP, PHASE_COMMON);
10198 ecore_init_block(sc, BLOCK_PXP2, PHASE_COMMON);
10199 bnx2x_init_pxp(sc);
10201 #ifdef __BIG_ENDIAN
10202 REG_WR(sc, PXP2_REG_RQ_QM_ENDIAN_M, 1);
10203 REG_WR(sc, PXP2_REG_RQ_TM_ENDIAN_M, 1);
10204 REG_WR(sc, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
10205 REG_WR(sc, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
10206 REG_WR(sc, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
10207 /* make sure this value is 0 */
10208 REG_WR(sc, PXP2_REG_RQ_HC_ENDIAN_M, 0);
10210 //REG_WR(sc, PXP2_REG_RD_PBF_SWAP_MODE, 1);
10211 REG_WR(sc, PXP2_REG_RD_QM_SWAP_MODE, 1);
10212 REG_WR(sc, PXP2_REG_RD_TM_SWAP_MODE, 1);
10213 REG_WR(sc, PXP2_REG_RD_SRC_SWAP_MODE, 1);
10214 REG_WR(sc, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
10217 ecore_ilt_init_page_size(sc, INITOP_SET);
10219 if (CHIP_REV_IS_FPGA(sc) && CHIP_IS_E1H(sc)) {
10220 REG_WR(sc, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
10223 /* let the HW do it's magic... */
10226 /* finish PXP init */
10228 val = REG_RD(sc, PXP2_REG_RQ_CFG_DONE);
10230 PMD_DRV_LOG(NOTICE, sc, "PXP2 CFG failed");
10233 val = REG_RD(sc, PXP2_REG_RD_INIT_DONE);
10235 PMD_DRV_LOG(NOTICE, sc, "PXP2 RD_INIT failed");
10240 * Timer bug workaround for E2 only. We need to set the entire ILT to have
10241 * entries with value "0" and valid bit on. This needs to be done by the
10242 * first PF that is loaded in a path (i.e. common phase)
10244 if (!CHIP_IS_E1x(sc)) {
10246 * In E2 there is a bug in the timers block that can cause function 6 / 7
10247 * (i.e. vnic3) to start even if it is marked as "scan-off".
10248 * This occurs when a different function (func2,3) is being marked
10249 * as "scan-off". Real-life scenario for example: if a driver is being
10250 * load-unloaded while func6,7 are down. This will cause the timer to access
10251 * the ilt, translate to a logical address and send a request to read/write.
10252 * Since the ilt for the function that is down is not valid, this will cause
10253 * a translation error which is unrecoverable.
10254 * The Workaround is intended to make sure that when this happens nothing
10255 * fatal will occur. The workaround:
10256 * 1. First PF driver which loads on a path will:
10257 * a. After taking the chip out of reset, by using pretend,
10258 * it will write "0" to the following registers of
10260 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10261 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
10262 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
10263 * And for itself it will write '1' to
10264 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
10265 * dmae-operations (writing to pram for example.)
10266 * note: can be done for only function 6,7 but cleaner this
10268 * b. Write zero+valid to the entire ILT.
10269 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
10270 * VNIC3 (of that port). The range allocated will be the
10271 * entire ILT. This is needed to prevent ILT range error.
10272 * 2. Any PF driver load flow:
10273 * a. ILT update with the physical addresses of the allocated
10275 * b. Wait 20msec. - note that this timeout is needed to make
10276 * sure there are no requests in one of the PXP internal
10277 * queues with "old" ILT addresses.
10278 * c. PF enable in the PGLC.
10279 * d. Clear the was_error of the PF in the PGLC. (could have
10280 * occurred while driver was down)
10281 * e. PF enable in the CFC (WEAK + STRONG)
10282 * f. Timers scan enable
10283 * 3. PF driver unload flow:
10284 * a. Clear the Timers scan_en.
10285 * b. Polling for scan_on=0 for that PF.
10286 * c. Clear the PF enable bit in the PXP.
10287 * d. Clear the PF enable in the CFC (WEAK + STRONG)
10288 * e. Write zero+valid to all ILT entries (The valid bit must
10290 * f. If this is VNIC 3 of a port then also init
10291 * first_timers_ilt_entry to zero and last_timers_ilt_entry
10292 * to the last enrty in the ILT.
10295 * Currently the PF error in the PGLC is non recoverable.
10296 * In the future the there will be a recovery routine for this error.
10297 * Currently attention is masked.
10298 * Having an MCP lock on the load/unload process does not guarantee that
10299 * there is no Timer disable during Func6/7 enable. This is because the
10300 * Timers scan is currently being cleared by the MCP on FLR.
10301 * Step 2.d can be done only for PF6/7 and the driver can also check if
10302 * there is error before clearing it. But the flow above is simpler and
10304 * All ILT entries are written by zero+valid and not just PF6/7
10305 * ILT entries since in the future the ILT entries allocation for
10306 * PF-s might be dynamic.
10308 struct ilt_client_info ilt_cli;
10309 struct ecore_ilt ilt;
10311 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
10312 memset(&ilt, 0, sizeof(struct ecore_ilt));
10314 /* initialize dummy TM client */
10316 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
10317 ilt_cli.client_num = ILT_CLIENT_TM;
10320 * Step 1: set zeroes to all ilt page entries with valid bit on
10321 * Step 2: set the timers first/last ilt entry to point
10322 * to the entire range to prevent ILT range error for 3rd/4th
10323 * vnic (this code assumes existence of the vnic)
10325 * both steps performed by call to ecore_ilt_client_init_op()
10326 * with dummy TM client
10328 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
10329 * and his brother are split registers
10332 bnx2x_pretend_func(sc, (SC_PATH(sc) + 6));
10333 ecore_ilt_client_init_op_ilt(sc, &ilt, &ilt_cli, INITOP_CLEAR);
10334 bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10336 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
10337 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
10338 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
10341 REG_WR(sc, PXP2_REG_RQ_DISABLE_INPUTS, 0);
10342 REG_WR(sc, PXP2_REG_RD_DISABLE_INPUTS, 0);
10344 if (!CHIP_IS_E1x(sc)) {
10347 ecore_init_block(sc, BLOCK_PGLUE_B, PHASE_COMMON);
10348 ecore_init_block(sc, BLOCK_ATC, PHASE_COMMON);
10350 /* let the HW do it's magic... */
10353 val = REG_RD(sc, ATC_REG_ATC_INIT_DONE);
10354 } while (factor-- && (val != 1));
10357 PMD_DRV_LOG(NOTICE, sc, "ATC_INIT failed");
10362 ecore_init_block(sc, BLOCK_DMAE, PHASE_COMMON);
10364 /* clean the DMAE memory */
10365 sc->dmae_ready = 1;
10366 ecore_init_fill(sc, TSEM_REG_PRAM, 0, 8);
10368 ecore_init_block(sc, BLOCK_TCM, PHASE_COMMON);
10370 ecore_init_block(sc, BLOCK_UCM, PHASE_COMMON);
10372 ecore_init_block(sc, BLOCK_CCM, PHASE_COMMON);
10374 ecore_init_block(sc, BLOCK_XCM, PHASE_COMMON);
10376 bnx2x_read_dmae(sc, XSEM_REG_PASSIVE_BUFFER, 3);
10377 bnx2x_read_dmae(sc, CSEM_REG_PASSIVE_BUFFER, 3);
10378 bnx2x_read_dmae(sc, TSEM_REG_PASSIVE_BUFFER, 3);
10379 bnx2x_read_dmae(sc, USEM_REG_PASSIVE_BUFFER, 3);
10381 ecore_init_block(sc, BLOCK_QM, PHASE_COMMON);
10383 /* QM queues pointers table */
10384 ecore_qm_init_ptr_table(sc, sc->qm_cid_count, INITOP_SET);
10386 /* soft reset pulse */
10387 REG_WR(sc, QM_REG_SOFT_RESET, 1);
10388 REG_WR(sc, QM_REG_SOFT_RESET, 0);
10390 if (CNIC_SUPPORT(sc))
10391 ecore_init_block(sc, BLOCK_TM, PHASE_COMMON);
10393 ecore_init_block(sc, BLOCK_DORQ, PHASE_COMMON);
10394 REG_WR(sc, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
10396 if (!CHIP_REV_IS_SLOW(sc)) {
10397 /* enable hw interrupt from doorbell Q */
10398 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
10401 ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON);
10403 ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON);
10404 REG_WR(sc, PRS_REG_A_PRSU_20, 0xf);
10405 REG_WR(sc, PRS_REG_E1HOV_MODE, sc->devinfo.mf_info.path_has_ovlan);
10407 if (!CHIP_IS_E1x(sc) && !CHIP_IS_E3B0(sc)) {
10408 if (IS_MF_AFEX(sc)) {
10410 * configure that AFEX and VLAN headers must be
10411 * received in AFEX mode
10413 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC, 0xE);
10414 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS, 0xA);
10415 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
10416 REG_WR(sc, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
10417 REG_WR(sc, PRS_REG_TAG_LEN_0, 0x4);
10420 * Bit-map indicating which L2 hdrs may appear
10421 * after the basic Ethernet header
10423 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC,
10424 sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10428 ecore_init_block(sc, BLOCK_TSDM, PHASE_COMMON);
10429 ecore_init_block(sc, BLOCK_CSDM, PHASE_COMMON);
10430 ecore_init_block(sc, BLOCK_USDM, PHASE_COMMON);
10431 ecore_init_block(sc, BLOCK_XSDM, PHASE_COMMON);
10433 if (!CHIP_IS_E1x(sc)) {
10434 /* reset VFC memories */
10435 REG_WR(sc, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10436 VFC_MEMORIES_RST_REG_CAM_RST |
10437 VFC_MEMORIES_RST_REG_RAM_RST);
10438 REG_WR(sc, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10439 VFC_MEMORIES_RST_REG_CAM_RST |
10440 VFC_MEMORIES_RST_REG_RAM_RST);
10445 ecore_init_block(sc, BLOCK_TSEM, PHASE_COMMON);
10446 ecore_init_block(sc, BLOCK_USEM, PHASE_COMMON);
10447 ecore_init_block(sc, BLOCK_CSEM, PHASE_COMMON);
10448 ecore_init_block(sc, BLOCK_XSEM, PHASE_COMMON);
10450 /* sync semi rtc */
10451 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x80000000);
10452 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x80000000);
10454 ecore_init_block(sc, BLOCK_UPB, PHASE_COMMON);
10455 ecore_init_block(sc, BLOCK_XPB, PHASE_COMMON);
10456 ecore_init_block(sc, BLOCK_PBF, PHASE_COMMON);
10458 if (!CHIP_IS_E1x(sc)) {
10459 if (IS_MF_AFEX(sc)) {
10461 * configure that AFEX and VLAN headers must be
10462 * sent in AFEX mode
10464 REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC, 0xE);
10465 REG_WR(sc, PBF_REG_MUST_HAVE_HDRS, 0xA);
10466 REG_WR(sc, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
10467 REG_WR(sc, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
10468 REG_WR(sc, PBF_REG_TAG_LEN_0, 0x4);
10470 REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC,
10471 sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10475 REG_WR(sc, SRC_REG_SOFT_RST, 1);
10477 ecore_init_block(sc, BLOCK_SRC, PHASE_COMMON);
10479 if (CNIC_SUPPORT(sc)) {
10480 REG_WR(sc, SRC_REG_KEYSEARCH_0, 0x63285672);
10481 REG_WR(sc, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
10482 REG_WR(sc, SRC_REG_KEYSEARCH_2, 0x223aef9b);
10483 REG_WR(sc, SRC_REG_KEYSEARCH_3, 0x26001e3a);
10484 REG_WR(sc, SRC_REG_KEYSEARCH_4, 0x7ae91116);
10485 REG_WR(sc, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
10486 REG_WR(sc, SRC_REG_KEYSEARCH_6, 0x298d8adf);
10487 REG_WR(sc, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
10488 REG_WR(sc, SRC_REG_KEYSEARCH_8, 0x1830f82f);
10489 REG_WR(sc, SRC_REG_KEYSEARCH_9, 0x01e46be7);
10491 REG_WR(sc, SRC_REG_SOFT_RST, 0);
10493 if (sizeof(union cdu_context) != 1024) {
10494 /* we currently assume that a context is 1024 bytes */
10495 PMD_DRV_LOG(NOTICE, sc,
10496 "please adjust the size of cdu_context(%ld)",
10497 (long)sizeof(union cdu_context));
10500 ecore_init_block(sc, BLOCK_CDU, PHASE_COMMON);
10501 val = (4 << 24) + (0 << 12) + 1024;
10502 REG_WR(sc, CDU_REG_CDU_GLOBAL_PARAMS, val);
10504 ecore_init_block(sc, BLOCK_CFC, PHASE_COMMON);
10506 REG_WR(sc, CFC_REG_INIT_REG, 0x7FF);
10507 /* enable context validation interrupt from CFC */
10508 REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
10510 /* set the thresholds to prevent CFC/CDU race */
10511 REG_WR(sc, CFC_REG_DEBUG0, 0x20020000);
10512 ecore_init_block(sc, BLOCK_HC, PHASE_COMMON);
10514 if (!CHIP_IS_E1x(sc) && BNX2X_NOMCP(sc)) {
10515 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x36);
10518 ecore_init_block(sc, BLOCK_IGU, PHASE_COMMON);
10519 ecore_init_block(sc, BLOCK_MISC_AEU, PHASE_COMMON);
10521 /* Reset PCIE errors for debug */
10522 REG_WR(sc, 0x2814, 0xffffffff);
10523 REG_WR(sc, 0x3820, 0xffffffff);
10525 if (!CHIP_IS_E1x(sc)) {
10526 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
10527 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
10528 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
10529 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
10530 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
10531 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
10532 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
10533 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
10534 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
10535 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
10536 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
10539 ecore_init_block(sc, BLOCK_NIG, PHASE_COMMON);
10541 /* in E3 this done in per-port section */
10542 if (!CHIP_IS_E3(sc))
10543 REG_WR(sc, NIG_REG_LLH_MF_MODE, IS_MF(sc));
10545 if (CHIP_IS_E1H(sc)) {
10546 /* not applicable for E2 (and above ...) */
10547 REG_WR(sc, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(sc));
10550 if (CHIP_REV_IS_SLOW(sc)) {
10554 /* finish CFC init */
10555 val = reg_poll(sc, CFC_REG_LL_INIT_DONE, 1, 100, 10);
10557 PMD_DRV_LOG(NOTICE, sc, "CFC LL_INIT failed");
10560 val = reg_poll(sc, CFC_REG_AC_INIT_DONE, 1, 100, 10);
10562 PMD_DRV_LOG(NOTICE, sc, "CFC AC_INIT failed");
10565 val = reg_poll(sc, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
10567 PMD_DRV_LOG(NOTICE, sc, "CFC CAM_INIT failed");
10570 REG_WR(sc, CFC_REG_DEBUG0, 0);
10572 bnx2x_setup_fan_failure_detection(sc);
10574 /* clear PXP2 attentions */
10575 REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
10577 bnx2x_enable_blocks_attention(sc);
10579 if (!CHIP_REV_IS_SLOW(sc)) {
10580 ecore_enable_blocks_parity(sc);
10583 if (!BNX2X_NOMCP(sc)) {
10584 if (CHIP_IS_E1x(sc)) {
10585 bnx2x_common_init_phy(sc);
10593 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
10595 * @sc: driver handle
10597 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc)
10599 int rc = bnx2x_init_hw_common(sc);
10605 /* In E2 2-PORT mode, same ext phy is used for the two paths */
10606 if (!BNX2X_NOMCP(sc)) {
10607 bnx2x_common_init_phy(sc);
10613 static int bnx2x_init_hw_port(struct bnx2x_softc *sc)
10615 int port = SC_PORT(sc);
10616 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
10617 uint32_t low, high;
10620 PMD_DRV_LOG(DEBUG, sc, "starting port init for port %d", port);
10622 REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
10624 ecore_init_block(sc, BLOCK_MISC, init_phase);
10625 ecore_init_block(sc, BLOCK_PXP, init_phase);
10626 ecore_init_block(sc, BLOCK_PXP2, init_phase);
10629 * Timers bug workaround: disables the pf_master bit in pglue at
10630 * common phase, we need to enable it here before any dmae access are
10631 * attempted. Therefore we manually added the enable-master to the
10632 * port phase (it also happens in the function phase)
10634 if (!CHIP_IS_E1x(sc)) {
10635 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
10638 ecore_init_block(sc, BLOCK_ATC, init_phase);
10639 ecore_init_block(sc, BLOCK_DMAE, init_phase);
10640 ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
10641 ecore_init_block(sc, BLOCK_QM, init_phase);
10643 ecore_init_block(sc, BLOCK_TCM, init_phase);
10644 ecore_init_block(sc, BLOCK_UCM, init_phase);
10645 ecore_init_block(sc, BLOCK_CCM, init_phase);
10646 ecore_init_block(sc, BLOCK_XCM, init_phase);
10648 /* QM cid (connection) count */
10649 ecore_qm_init_cid_count(sc, sc->qm_cid_count, INITOP_SET);
10651 if (CNIC_SUPPORT(sc)) {
10652 ecore_init_block(sc, BLOCK_TM, init_phase);
10653 REG_WR(sc, TM_REG_LIN0_SCAN_TIME + port * 4, 20);
10654 REG_WR(sc, TM_REG_LIN0_MAX_ACTIVE_CID + port * 4, 31);
10657 ecore_init_block(sc, BLOCK_DORQ, init_phase);
10659 ecore_init_block(sc, BLOCK_BRB1, init_phase);
10661 if (CHIP_IS_E1H(sc)) {
10663 low = (BNX2X_ONE_PORT(sc) ? 160 : 246);
10664 } else if (sc->mtu > 4096) {
10665 if (BNX2X_ONE_PORT(sc)) {
10669 /* (24*1024 + val*4)/256 */
10670 low = (96 + (val / 64) + ((val % 64) ? 1 : 0));
10673 low = (BNX2X_ONE_PORT(sc) ? 80 : 160);
10675 high = (low + 56); /* 14*1024/256 */
10676 REG_WR(sc, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port * 4, low);
10677 REG_WR(sc, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port * 4, high);
10680 if (CHIP_IS_MODE_4_PORT(sc)) {
10681 REG_WR(sc, SC_PORT(sc) ?
10682 BRB1_REG_MAC_GUARANTIED_1 :
10683 BRB1_REG_MAC_GUARANTIED_0, 40);
10686 ecore_init_block(sc, BLOCK_PRS, init_phase);
10687 if (CHIP_IS_E3B0(sc)) {
10688 if (IS_MF_AFEX(sc)) {
10689 /* configure headers for AFEX mode */
10691 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_1,
10693 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_1,
10695 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_1, 0xA);
10697 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10699 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_0,
10701 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
10704 /* Ovlan exists only if we are in multi-function +
10705 * switch-dependent mode, in switch-independent there
10706 * is no ovlan headers
10708 REG_WR(sc, SC_PORT(sc) ?
10709 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
10710 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10711 (sc->devinfo.mf_info.path_has_ovlan ? 7 : 6));
10715 ecore_init_block(sc, BLOCK_TSDM, init_phase);
10716 ecore_init_block(sc, BLOCK_CSDM, init_phase);
10717 ecore_init_block(sc, BLOCK_USDM, init_phase);
10718 ecore_init_block(sc, BLOCK_XSDM, init_phase);
10720 ecore_init_block(sc, BLOCK_TSEM, init_phase);
10721 ecore_init_block(sc, BLOCK_USEM, init_phase);
10722 ecore_init_block(sc, BLOCK_CSEM, init_phase);
10723 ecore_init_block(sc, BLOCK_XSEM, init_phase);
10725 ecore_init_block(sc, BLOCK_UPB, init_phase);
10726 ecore_init_block(sc, BLOCK_XPB, init_phase);
10728 ecore_init_block(sc, BLOCK_PBF, init_phase);
10730 if (CHIP_IS_E1x(sc)) {
10731 /* configure PBF to work without PAUSE mtu 9000 */
10732 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 0);
10734 /* update threshold */
10735 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, (9040 / 16));
10736 /* update init credit */
10737 REG_WR(sc, PBF_REG_P0_INIT_CRD + port * 4,
10738 (9040 / 16) + 553 - 22);
10740 /* probe changes */
10741 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 1);
10743 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0);
10746 if (CNIC_SUPPORT(sc)) {
10747 ecore_init_block(sc, BLOCK_SRC, init_phase);
10750 ecore_init_block(sc, BLOCK_CDU, init_phase);
10751 ecore_init_block(sc, BLOCK_CFC, init_phase);
10752 ecore_init_block(sc, BLOCK_HC, init_phase);
10753 ecore_init_block(sc, BLOCK_IGU, init_phase);
10754 ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
10755 /* init aeu_mask_attn_func_0/1:
10756 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
10757 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
10758 * bits 4-7 are used for "per vn group attention" */
10759 val = IS_MF(sc) ? 0xF7 : 0x7;
10761 REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, val);
10763 ecore_init_block(sc, BLOCK_NIG, init_phase);
10765 if (!CHIP_IS_E1x(sc)) {
10766 /* Bit-map indicating which L2 hdrs may appear after the
10767 * basic Ethernet header
10769 if (IS_MF_AFEX(sc)) {
10770 REG_WR(sc, SC_PORT(sc) ?
10771 NIG_REG_P1_HDRS_AFTER_BASIC :
10772 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
10774 REG_WR(sc, SC_PORT(sc) ?
10775 NIG_REG_P1_HDRS_AFTER_BASIC :
10776 NIG_REG_P0_HDRS_AFTER_BASIC,
10777 IS_MF_SD(sc) ? 7 : 6);
10780 if (CHIP_IS_E3(sc)) {
10781 REG_WR(sc, SC_PORT(sc) ?
10782 NIG_REG_LLH1_MF_MODE :
10783 NIG_REG_LLH_MF_MODE, IS_MF(sc));
10786 if (!CHIP_IS_E3(sc)) {
10787 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1);
10790 /* 0x2 disable mf_ov, 0x1 enable */
10791 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port * 4,
10792 (IS_MF_SD(sc) ? 0x1 : 0x2));
10794 if (!CHIP_IS_E1x(sc)) {
10796 switch (sc->devinfo.mf_info.mf_mode) {
10797 case MULTI_FUNCTION_SD:
10800 case MULTI_FUNCTION_SI:
10801 case MULTI_FUNCTION_AFEX:
10806 REG_WR(sc, (SC_PORT(sc) ? NIG_REG_LLH1_CLS_TYPE :
10807 NIG_REG_LLH0_CLS_TYPE), val);
10809 REG_WR(sc, NIG_REG_LLFC_ENABLE_0 + port * 4, 0);
10810 REG_WR(sc, NIG_REG_LLFC_OUT_EN_0 + port * 4, 0);
10811 REG_WR(sc, NIG_REG_PAUSE_ENABLE_0 + port * 4, 1);
10813 /* If SPIO5 is set to generate interrupts, enable it for this port */
10814 val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
10815 if (val & MISC_SPIO_SPIO5) {
10816 uint32_t reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
10817 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
10818 val = REG_RD(sc, reg_addr);
10819 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
10820 REG_WR(sc, reg_addr, val);
10827 bnx2x_flr_clnup_reg_poll(struct bnx2x_softc *sc, uint32_t reg,
10828 uint32_t expected, uint32_t poll_count)
10830 uint32_t cur_cnt = poll_count;
10833 while ((val = REG_RD(sc, reg)) != expected && cur_cnt--) {
10834 DELAY(FLR_WAIT_INTERVAL);
10841 bnx2x_flr_clnup_poll_hw_counter(struct bnx2x_softc *sc, uint32_t reg,
10842 __rte_unused const char *msg, uint32_t poll_cnt)
10844 uint32_t val = bnx2x_flr_clnup_reg_poll(sc, reg, 0, poll_cnt);
10847 PMD_DRV_LOG(NOTICE, sc, "%s usage count=%d", msg, val);
10854 /* Common routines with VF FLR cleanup */
10855 static uint32_t bnx2x_flr_clnup_poll_count(struct bnx2x_softc *sc)
10857 /* adjust polling timeout */
10858 if (CHIP_REV_IS_EMUL(sc)) {
10859 return FLR_POLL_CNT * 2000;
10862 if (CHIP_REV_IS_FPGA(sc)) {
10863 return FLR_POLL_CNT * 120;
10866 return FLR_POLL_CNT;
10869 static int bnx2x_poll_hw_usage_counters(struct bnx2x_softc *sc, uint32_t poll_cnt)
10871 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
10872 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10873 CFC_REG_NUM_LCIDS_INSIDE_PF,
10874 "CFC PF usage counter timed out",
10879 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
10880 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10881 DORQ_REG_PF_USAGE_CNT,
10882 "DQ PF usage counter timed out",
10887 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
10888 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10889 QM_REG_PF_USG_CNT_0 + 4 * SC_FUNC(sc),
10890 "QM PF usage counter timed out",
10895 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
10896 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10897 TM_REG_LIN0_VNIC_UC + 4 * SC_PORT(sc),
10898 "Timers VNIC usage counter timed out",
10903 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10904 TM_REG_LIN0_NUM_SCANS +
10906 "Timers NUM_SCANS usage counter timed out",
10911 /* Wait DMAE PF usage counter to zero */
10912 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10913 dmae_reg_go_c[INIT_DMAE_C(sc)],
10914 "DMAE dommand register timed out",
10922 #define OP_GEN_PARAM(param) \
10923 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
10924 #define OP_GEN_TYPE(type) \
10925 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
10926 #define OP_GEN_AGG_VECT(index) \
10927 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
10930 bnx2x_send_final_clnup(struct bnx2x_softc *sc, uint8_t clnup_func,
10933 uint32_t op_gen_command = 0;
10934 uint32_t comp_addr = (BAR_CSTRORM_INTMEM +
10935 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func));
10938 if (REG_RD(sc, comp_addr)) {
10939 PMD_DRV_LOG(NOTICE, sc,
10940 "Cleanup complete was not 0 before sending");
10944 op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
10945 op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
10946 op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
10947 op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
10949 REG_WR(sc, XSDM_REG_OPERATION_GEN, op_gen_command);
10951 if (bnx2x_flr_clnup_reg_poll(sc, comp_addr, 1, poll_cnt) != 1) {
10952 PMD_DRV_LOG(NOTICE, sc, "FW final cleanup did not succeed");
10953 PMD_DRV_LOG(DEBUG, sc, "At timeout completion address contained %x",
10954 (REG_RD(sc, comp_addr)));
10955 rte_panic("FLR cleanup failed");
10959 /* Zero completion for nxt FLR */
10960 REG_WR(sc, comp_addr, 0);
10966 bnx2x_pbf_pN_buf_flushed(struct bnx2x_softc *sc, struct pbf_pN_buf_regs *regs,
10967 uint32_t poll_count)
10969 uint32_t init_crd, crd, crd_start, crd_freed, crd_freed_start;
10970 uint32_t cur_cnt = poll_count;
10972 crd_freed = crd_freed_start = REG_RD(sc, regs->crd_freed);
10973 crd = crd_start = REG_RD(sc, regs->crd);
10974 init_crd = REG_RD(sc, regs->init_crd);
10976 while ((crd != init_crd) &&
10977 ((uint32_t) ((int32_t) crd_freed - (int32_t) crd_freed_start) <
10978 (init_crd - crd_start))) {
10980 DELAY(FLR_WAIT_INTERVAL);
10981 crd = REG_RD(sc, regs->crd);
10982 crd_freed = REG_RD(sc, regs->crd_freed);
10990 bnx2x_pbf_pN_cmd_flushed(struct bnx2x_softc *sc, struct pbf_pN_cmd_regs *regs,
10991 uint32_t poll_count)
10993 uint32_t occup, to_free, freed, freed_start;
10994 uint32_t cur_cnt = poll_count;
10996 occup = to_free = REG_RD(sc, regs->lines_occup);
10997 freed = freed_start = REG_RD(sc, regs->lines_freed);
11000 ((uint32_t) ((int32_t) freed - (int32_t) freed_start) <
11003 DELAY(FLR_WAIT_INTERVAL);
11004 occup = REG_RD(sc, regs->lines_occup);
11005 freed = REG_RD(sc, regs->lines_freed);
11012 static void bnx2x_tx_hw_flushed(struct bnx2x_softc *sc, uint32_t poll_count)
11014 struct pbf_pN_cmd_regs cmd_regs[] = {
11015 {0, (CHIP_IS_E3B0(sc)) ?
11016 PBF_REG_TQ_OCCUPANCY_Q0 : PBF_REG_P0_TQ_OCCUPANCY,
11017 (CHIP_IS_E3B0(sc)) ?
11018 PBF_REG_TQ_LINES_FREED_CNT_Q0 : PBF_REG_P0_TQ_LINES_FREED_CNT},
11019 {1, (CHIP_IS_E3B0(sc)) ?
11020 PBF_REG_TQ_OCCUPANCY_Q1 : PBF_REG_P1_TQ_OCCUPANCY,
11021 (CHIP_IS_E3B0(sc)) ?
11022 PBF_REG_TQ_LINES_FREED_CNT_Q1 : PBF_REG_P1_TQ_LINES_FREED_CNT},
11023 {4, (CHIP_IS_E3B0(sc)) ?
11024 PBF_REG_TQ_OCCUPANCY_LB_Q : PBF_REG_P4_TQ_OCCUPANCY,
11025 (CHIP_IS_E3B0(sc)) ?
11026 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
11027 PBF_REG_P4_TQ_LINES_FREED_CNT}
11030 struct pbf_pN_buf_regs buf_regs[] = {
11031 {0, (CHIP_IS_E3B0(sc)) ?
11032 PBF_REG_INIT_CRD_Q0 : PBF_REG_P0_INIT_CRD,
11033 (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q0 : PBF_REG_P0_CREDIT,
11034 (CHIP_IS_E3B0(sc)) ?
11035 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
11036 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
11037 {1, (CHIP_IS_E3B0(sc)) ?
11038 PBF_REG_INIT_CRD_Q1 : PBF_REG_P1_INIT_CRD,
11039 (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q1 : PBF_REG_P1_CREDIT,
11040 (CHIP_IS_E3B0(sc)) ?
11041 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
11042 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
11043 {4, (CHIP_IS_E3B0(sc)) ?
11044 PBF_REG_INIT_CRD_LB_Q : PBF_REG_P4_INIT_CRD,
11045 (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_LB_Q : PBF_REG_P4_CREDIT,
11046 (CHIP_IS_E3B0(sc)) ?
11047 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
11048 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
11053 /* Verify the command queues are flushed P0, P1, P4 */
11054 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) {
11055 bnx2x_pbf_pN_cmd_flushed(sc, &cmd_regs[i], poll_count);
11058 /* Verify the transmission buffers are flushed P0, P1, P4 */
11059 for (i = 0; i < ARRAY_SIZE(buf_regs); i++) {
11060 bnx2x_pbf_pN_buf_flushed(sc, &buf_regs[i], poll_count);
11064 static void bnx2x_hw_enable_status(struct bnx2x_softc *sc)
11066 __rte_unused uint32_t val;
11068 val = REG_RD(sc, CFC_REG_WEAK_ENABLE_PF);
11069 PMD_DRV_LOG(DEBUG, sc, "CFC_REG_WEAK_ENABLE_PF is 0x%x", val);
11071 val = REG_RD(sc, PBF_REG_DISABLE_PF);
11072 PMD_DRV_LOG(DEBUG, sc, "PBF_REG_DISABLE_PF is 0x%x", val);
11074 val = REG_RD(sc, IGU_REG_PCI_PF_MSI_EN);
11075 PMD_DRV_LOG(DEBUG, sc, "IGU_REG_PCI_PF_MSI_EN is 0x%x", val);
11077 val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_EN);
11078 PMD_DRV_LOG(DEBUG, sc, "IGU_REG_PCI_PF_MSIX_EN is 0x%x", val);
11080 val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
11081 PMD_DRV_LOG(DEBUG, sc, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x", val);
11083 val = REG_RD(sc, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
11084 PMD_DRV_LOG(DEBUG, sc,
11085 "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x", val);
11087 val = REG_RD(sc, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
11088 PMD_DRV_LOG(DEBUG, sc,
11089 "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x", val);
11091 val = REG_RD(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
11092 PMD_DRV_LOG(DEBUG, sc, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x",
11097 * bnx2x_pf_flr_clnup
11098 * a. re-enable target read on the PF
11099 * b. poll cfc per function usgae counter
11100 * c. poll the qm perfunction usage counter
11101 * d. poll the tm per function usage counter
11102 * e. poll the tm per function scan-done indication
11103 * f. clear the dmae channel associated wit hthe PF
11104 * g. zero the igu 'trailing edge' and 'leading edge' regs (attentions)
11105 * h. call the common flr cleanup code with -1 (pf indication)
11107 static int bnx2x_pf_flr_clnup(struct bnx2x_softc *sc)
11109 uint32_t poll_cnt = bnx2x_flr_clnup_poll_count(sc);
11111 /* Re-enable PF target read access */
11112 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
11114 /* Poll HW usage counters */
11115 if (bnx2x_poll_hw_usage_counters(sc, poll_cnt)) {
11119 /* Zero the igu 'trailing edge' and 'leading edge' */
11121 /* Send the FW cleanup command */
11122 if (bnx2x_send_final_clnup(sc, (uint8_t) SC_FUNC(sc), poll_cnt)) {
11128 /* Verify TX hw is flushed */
11129 bnx2x_tx_hw_flushed(sc, poll_cnt);
11131 /* Wait 100ms (not adjusted according to platform) */
11134 /* Verify no pending pci transactions */
11135 if (bnx2x_is_pcie_pending(sc)) {
11136 PMD_DRV_LOG(NOTICE, sc, "PCIE Transactions still pending");
11140 bnx2x_hw_enable_status(sc);
11143 * Master enable - Due to WB DMAE writes performed before this
11144 * register is re-initialized as part of the regular function init
11146 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11151 static int bnx2x_init_hw_func(struct bnx2x_softc *sc)
11153 int port = SC_PORT(sc);
11154 int func = SC_FUNC(sc);
11155 int init_phase = PHASE_PF0 + func;
11156 struct ecore_ilt *ilt = sc->ilt;
11157 uint16_t cdu_ilt_start;
11158 uint32_t addr, val;
11159 uint32_t main_mem_base, main_mem_size, main_mem_prty_clr;
11160 int main_mem_width, rc;
11163 PMD_DRV_LOG(DEBUG, sc, "starting func init for func %d", func);
11166 if (!CHIP_IS_E1x(sc)) {
11167 rc = bnx2x_pf_flr_clnup(sc);
11169 PMD_DRV_LOG(NOTICE, sc, "FLR cleanup failed!");
11174 /* set MSI reconfigure capability */
11175 if (sc->devinfo.int_block == INT_BLOCK_HC) {
11176 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
11177 val = REG_RD(sc, addr);
11178 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
11179 REG_WR(sc, addr, val);
11182 ecore_init_block(sc, BLOCK_PXP, init_phase);
11183 ecore_init_block(sc, BLOCK_PXP2, init_phase);
11186 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
11188 for (i = 0; i < L2_ILT_LINES(sc); i++) {
11189 ilt->lines[cdu_ilt_start + i].page = sc->context[i].vcxt;
11190 ilt->lines[cdu_ilt_start + i].page_mapping =
11191 (rte_iova_t)sc->context[i].vcxt_dma.paddr;
11192 ilt->lines[cdu_ilt_start + i].size = sc->context[i].size;
11194 ecore_ilt_init_op(sc, INITOP_SET);
11196 REG_WR(sc, PRS_REG_NIC_MODE, 1);
11198 if (!CHIP_IS_E1x(sc)) {
11199 uint32_t pf_conf = IGU_PF_CONF_FUNC_EN;
11201 /* Turn on a single ISR mode in IGU if driver is going to use
11204 if ((sc->interrupt_mode != INTR_MODE_MSIX)
11205 || (sc->interrupt_mode != INTR_MODE_SINGLE_MSIX)) {
11206 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
11210 * Timers workaround bug: function init part.
11211 * Need to wait 20msec after initializing ILT,
11212 * needed to make sure there are no requests in
11213 * one of the PXP internal queues with "old" ILT addresses
11218 * Master enable - Due to WB DMAE writes performed before this
11219 * register is re-initialized as part of the regular function
11222 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11223 /* Enable the function in IGU */
11224 REG_WR(sc, IGU_REG_PF_CONFIGURATION, pf_conf);
11227 sc->dmae_ready = 1;
11229 ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
11231 if (!CHIP_IS_E1x(sc))
11232 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
11234 ecore_init_block(sc, BLOCK_ATC, init_phase);
11235 ecore_init_block(sc, BLOCK_DMAE, init_phase);
11236 ecore_init_block(sc, BLOCK_NIG, init_phase);
11237 ecore_init_block(sc, BLOCK_SRC, init_phase);
11238 ecore_init_block(sc, BLOCK_MISC, init_phase);
11239 ecore_init_block(sc, BLOCK_TCM, init_phase);
11240 ecore_init_block(sc, BLOCK_UCM, init_phase);
11241 ecore_init_block(sc, BLOCK_CCM, init_phase);
11242 ecore_init_block(sc, BLOCK_XCM, init_phase);
11243 ecore_init_block(sc, BLOCK_TSEM, init_phase);
11244 ecore_init_block(sc, BLOCK_USEM, init_phase);
11245 ecore_init_block(sc, BLOCK_CSEM, init_phase);
11246 ecore_init_block(sc, BLOCK_XSEM, init_phase);
11248 if (!CHIP_IS_E1x(sc))
11249 REG_WR(sc, QM_REG_PF_EN, 1);
11251 if (!CHIP_IS_E1x(sc)) {
11252 REG_WR(sc, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11253 REG_WR(sc, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11254 REG_WR(sc, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11255 REG_WR(sc, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11257 ecore_init_block(sc, BLOCK_QM, init_phase);
11259 ecore_init_block(sc, BLOCK_TM, init_phase);
11260 ecore_init_block(sc, BLOCK_DORQ, init_phase);
11262 ecore_init_block(sc, BLOCK_BRB1, init_phase);
11263 ecore_init_block(sc, BLOCK_PRS, init_phase);
11264 ecore_init_block(sc, BLOCK_TSDM, init_phase);
11265 ecore_init_block(sc, BLOCK_CSDM, init_phase);
11266 ecore_init_block(sc, BLOCK_USDM, init_phase);
11267 ecore_init_block(sc, BLOCK_XSDM, init_phase);
11268 ecore_init_block(sc, BLOCK_UPB, init_phase);
11269 ecore_init_block(sc, BLOCK_XPB, init_phase);
11270 ecore_init_block(sc, BLOCK_PBF, init_phase);
11271 if (!CHIP_IS_E1x(sc))
11272 REG_WR(sc, PBF_REG_DISABLE_PF, 0);
11274 ecore_init_block(sc, BLOCK_CDU, init_phase);
11276 ecore_init_block(sc, BLOCK_CFC, init_phase);
11278 if (!CHIP_IS_E1x(sc))
11279 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 1);
11282 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
11283 REG_WR(sc, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8, OVLAN(sc));
11286 ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
11288 /* HC init per function */
11289 if (sc->devinfo.int_block == INT_BLOCK_HC) {
11290 if (CHIP_IS_E1H(sc)) {
11291 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11293 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11294 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11296 ecore_init_block(sc, BLOCK_HC, init_phase);
11299 uint32_t num_segs, sb_idx, prod_offset;
11301 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11303 if (!CHIP_IS_E1x(sc)) {
11304 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11305 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11308 ecore_init_block(sc, BLOCK_IGU, init_phase);
11310 if (!CHIP_IS_E1x(sc)) {
11314 * E2 mode: address 0-135 match to the mapping memory;
11315 * 136 - PF0 default prod; 137 - PF1 default prod;
11316 * 138 - PF2 default prod; 139 - PF3 default prod;
11317 * 140 - PF0 attn prod; 141 - PF1 attn prod;
11318 * 142 - PF2 attn prod; 143 - PF3 attn prod;
11319 * 144-147 reserved.
11321 * E1.5 mode - In backward compatible mode;
11322 * for non default SB; each even line in the memory
11323 * holds the U producer and each odd line hold
11324 * the C producer. The first 128 producers are for
11325 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
11326 * producers are for the DSB for each PF.
11327 * Each PF has five segments: (the order inside each
11328 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
11329 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
11330 * 144-147 attn prods;
11332 /* non-default-status-blocks */
11333 num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11334 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
11335 for (sb_idx = 0; sb_idx < sc->igu_sb_cnt; sb_idx++) {
11336 prod_offset = (sc->igu_base_sb + sb_idx) *
11339 for (i = 0; i < num_segs; i++) {
11340 addr = IGU_REG_PROD_CONS_MEMORY +
11341 (prod_offset + i) * 4;
11342 REG_WR(sc, addr, 0);
11344 /* send consumer update with value 0 */
11345 bnx2x_ack_sb(sc, sc->igu_base_sb + sb_idx,
11346 USTORM_ID, 0, IGU_INT_NOP, 1);
11347 bnx2x_igu_clear_sb(sc, sc->igu_base_sb + sb_idx);
11350 /* default-status-blocks */
11351 num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11352 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
11354 if (CHIP_IS_MODE_4_PORT(sc))
11355 dsb_idx = SC_FUNC(sc);
11357 dsb_idx = SC_VN(sc);
11359 prod_offset = (CHIP_INT_MODE_IS_BC(sc) ?
11360 IGU_BC_BASE_DSB_PROD + dsb_idx :
11361 IGU_NORM_BASE_DSB_PROD + dsb_idx);
11364 * igu prods come in chunks of E1HVN_MAX (4) -
11365 * does not matters what is the current chip mode
11367 for (i = 0; i < (num_segs * E1HVN_MAX); i += E1HVN_MAX) {
11368 addr = IGU_REG_PROD_CONS_MEMORY +
11369 (prod_offset + i) * 4;
11370 REG_WR(sc, addr, 0);
11372 /* send consumer update with 0 */
11373 if (CHIP_INT_MODE_IS_BC(sc)) {
11374 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11375 USTORM_ID, 0, IGU_INT_NOP, 1);
11376 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11377 CSTORM_ID, 0, IGU_INT_NOP, 1);
11378 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11379 XSTORM_ID, 0, IGU_INT_NOP, 1);
11380 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11381 TSTORM_ID, 0, IGU_INT_NOP, 1);
11382 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11383 ATTENTION_ID, 0, IGU_INT_NOP, 1);
11385 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11386 USTORM_ID, 0, IGU_INT_NOP, 1);
11387 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11388 ATTENTION_ID, 0, IGU_INT_NOP, 1);
11390 bnx2x_igu_clear_sb(sc, sc->igu_dsb_id);
11392 /* !!! these should become driver const once
11393 rf-tool supports split-68 const */
11394 REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
11395 REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
11396 REG_WR(sc, IGU_REG_SB_MASK_LSB, 0);
11397 REG_WR(sc, IGU_REG_SB_MASK_MSB, 0);
11398 REG_WR(sc, IGU_REG_PBA_STATUS_LSB, 0);
11399 REG_WR(sc, IGU_REG_PBA_STATUS_MSB, 0);
11403 /* Reset PCIE errors for debug */
11404 REG_WR(sc, 0x2114, 0xffffffff);
11405 REG_WR(sc, 0x2120, 0xffffffff);
11407 if (CHIP_IS_E1x(sc)) {
11408 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords */
11409 main_mem_base = HC_REG_MAIN_MEMORY +
11410 SC_PORT(sc) * (main_mem_size * 4);
11411 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
11412 main_mem_width = 8;
11414 val = REG_RD(sc, main_mem_prty_clr);
11416 PMD_DRV_LOG(DEBUG, sc,
11417 "Parity errors in HC block during function init (0x%x)!",
11421 /* Clear "false" parity errors in MSI-X table */
11422 for (i = main_mem_base;
11423 i < main_mem_base + main_mem_size * 4;
11424 i += main_mem_width) {
11425 bnx2x_read_dmae(sc, i, main_mem_width / 4);
11426 bnx2x_write_dmae(sc, BNX2X_SP_MAPPING(sc, wb_data),
11427 i, main_mem_width / 4);
11429 /* Clear HC parity attention */
11430 REG_RD(sc, main_mem_prty_clr);
11433 /* Enable STORMs SP logging */
11434 REG_WR8(sc, BAR_USTRORM_INTMEM +
11435 USTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11436 REG_WR8(sc, BAR_TSTRORM_INTMEM +
11437 TSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11438 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11439 CSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11440 REG_WR8(sc, BAR_XSTRORM_INTMEM +
11441 XSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11443 elink_phy_probe(&sc->link_params);
11448 static void bnx2x_link_reset(struct bnx2x_softc *sc)
11450 if (!BNX2X_NOMCP(sc)) {
11451 bnx2x_acquire_phy_lock(sc);
11452 elink_lfa_reset(&sc->link_params, &sc->link_vars);
11453 bnx2x_release_phy_lock(sc);
11455 if (!CHIP_REV_IS_SLOW(sc)) {
11456 PMD_DRV_LOG(WARNING, sc,
11457 "Bootcode is missing - cannot reset link");
11462 static void bnx2x_reset_port(struct bnx2x_softc *sc)
11464 int port = SC_PORT(sc);
11467 /* reset physical Link */
11468 bnx2x_link_reset(sc);
11470 REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
11472 /* Do not rcv packets to BRB */
11473 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + port * 4, 0x0);
11474 /* Do not direct rcv packets that are not for MCP to the BRB */
11475 REG_WR(sc, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
11476 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
11478 /* Configure AEU */
11479 REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, 0);
11483 /* Check for BRB port occupancy */
11484 val = REG_RD(sc, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port * 4);
11486 PMD_DRV_LOG(DEBUG, sc,
11487 "BRB1 is not empty, %d blocks are occupied", val);
11491 static void bnx2x_ilt_wr(struct bnx2x_softc *sc, uint32_t index, rte_iova_t addr)
11494 uint32_t wb_write[2];
11496 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index * 8;
11498 wb_write[0] = ONCHIP_ADDR1(addr);
11499 wb_write[1] = ONCHIP_ADDR2(addr);
11500 REG_WR_DMAE(sc, reg, wb_write, 2);
11503 static void bnx2x_clear_func_ilt(struct bnx2x_softc *sc, uint32_t func)
11505 uint32_t i, base = FUNC_ILT_BASE(func);
11506 for (i = base; i < base + ILT_PER_FUNC; i++) {
11507 bnx2x_ilt_wr(sc, i, 0);
11511 static void bnx2x_reset_func(struct bnx2x_softc *sc)
11513 struct bnx2x_fastpath *fp;
11514 int port = SC_PORT(sc);
11515 int func = SC_FUNC(sc);
11518 /* Disable the function in the FW */
11519 REG_WR8(sc, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
11520 REG_WR8(sc, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
11521 REG_WR8(sc, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
11522 REG_WR8(sc, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
11525 FOR_EACH_ETH_QUEUE(sc, i) {
11527 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11528 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
11533 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11534 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), SB_DISABLED);
11536 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) {
11537 REG_WR(sc, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
11541 /* Configure IGU */
11542 if (sc->devinfo.int_block == INT_BLOCK_HC) {
11543 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11544 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11546 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11547 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11550 if (CNIC_LOADED(sc)) {
11551 /* Disable Timer scan */
11552 REG_WR(sc, TM_REG_EN_LINEAR0_TIMER + port * 4, 0);
11554 * Wait for at least 10ms and up to 2 second for the timers
11557 for (i = 0; i < 200; i++) {
11559 if (!REG_RD(sc, TM_REG_LIN0_SCAN_ON + port * 4))
11565 bnx2x_clear_func_ilt(sc, func);
11568 * Timers workaround bug for E2: if this is vnic-3,
11569 * we need to set the entire ilt range for this timers.
11571 if (!CHIP_IS_E1x(sc) && SC_VN(sc) == 3) {
11572 struct ilt_client_info ilt_cli;
11573 /* use dummy TM client */
11574 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
11576 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
11577 ilt_cli.client_num = ILT_CLIENT_TM;
11579 ecore_ilt_boundry_init_op(sc, &ilt_cli, 0);
11582 /* this assumes that reset_port() called before reset_func() */
11583 if (!CHIP_IS_E1x(sc)) {
11584 bnx2x_pf_disable(sc);
11587 sc->dmae_ready = 0;
11590 static void bnx2x_release_firmware(struct bnx2x_softc *sc)
11592 rte_free(sc->init_ops);
11593 rte_free(sc->init_ops_offsets);
11594 rte_free(sc->init_data);
11595 rte_free(sc->iro_array);
11598 static int bnx2x_init_firmware(struct bnx2x_softc *sc)
11601 uint8_t *p = sc->firmware;
11604 for (i = 0; i < 24; ++i)
11605 off[i] = rte_be_to_cpu_32(*((uint32_t *) sc->firmware + i));
11608 sc->init_ops = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11611 bnx2x_data_to_init_ops(p + off[1], sc->init_ops, len);
11614 sc->init_ops_offsets = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11615 if (!sc->init_ops_offsets)
11617 bnx2x_data_to_init_offsets(p + off[3], sc->init_ops_offsets, len);
11620 sc->init_data = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11621 if (!sc->init_data)
11623 bnx2x_data_to_init_data(p + off[5], sc->init_data, len);
11625 sc->tsem_int_table_data = p + off[7];
11626 sc->tsem_pram_data = p + off[9];
11627 sc->usem_int_table_data = p + off[11];
11628 sc->usem_pram_data = p + off[13];
11629 sc->csem_int_table_data = p + off[15];
11630 sc->csem_pram_data = p + off[17];
11631 sc->xsem_int_table_data = p + off[19];
11632 sc->xsem_pram_data = p + off[21];
11635 sc->iro_array = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11636 if (!sc->iro_array)
11638 bnx2x_data_to_iro_array(p + off[23], sc->iro_array, len);
11643 bnx2x_release_firmware(sc);
11647 static int cut_gzip_prefix(const uint8_t * zbuf, int len)
11649 #define MIN_PREFIX_SIZE (10)
11651 int n = MIN_PREFIX_SIZE;
11654 if (!(zbuf[0] == 0x1f && zbuf[1] == 0x8b && zbuf[2] == Z_DEFLATED) ||
11655 len <= MIN_PREFIX_SIZE) {
11659 /* optional extra fields are present */
11660 if (zbuf[3] & 0x4) {
11667 /* file name is present */
11668 if (zbuf[3] & 0x8) {
11669 while ((zbuf[n++] != 0) && (n < len)) ;
11675 static int ecore_gunzip(struct bnx2x_softc *sc, const uint8_t * zbuf, int len)
11678 int data_begin = cut_gzip_prefix(zbuf, len);
11680 PMD_DRV_LOG(DEBUG, sc, "ecore_gunzip %d", len);
11682 if (data_begin <= 0) {
11683 PMD_DRV_LOG(NOTICE, sc, "bad gzip prefix");
11687 memset(&zlib_stream, 0, sizeof(zlib_stream));
11688 zlib_stream.next_in = zbuf + data_begin;
11689 zlib_stream.avail_in = len - data_begin;
11690 zlib_stream.next_out = sc->gz_buf;
11691 zlib_stream.avail_out = FW_BUF_SIZE;
11693 ret = inflateInit2(&zlib_stream, -MAX_WBITS);
11695 PMD_DRV_LOG(NOTICE, sc, "zlib inflateInit2 error");
11699 ret = inflate(&zlib_stream, Z_FINISH);
11700 if ((ret != Z_STREAM_END) && (ret != Z_OK)) {
11701 PMD_DRV_LOG(NOTICE, sc, "zlib inflate error: %d %s", ret,
11705 sc->gz_outlen = zlib_stream.total_out;
11706 if (sc->gz_outlen & 0x3) {
11707 PMD_DRV_LOG(NOTICE, sc, "firmware is not aligned. gz_outlen == %d",
11710 sc->gz_outlen >>= 2;
11712 inflateEnd(&zlib_stream);
11714 if (ret == Z_STREAM_END)
11721 ecore_write_dmae_phys_len(struct bnx2x_softc *sc, rte_iova_t phys_addr,
11722 uint32_t addr, uint32_t len)
11724 bnx2x_write_dmae_phys_len(sc, phys_addr, addr, len);
11728 ecore_storm_memset_struct(struct bnx2x_softc *sc, uint32_t addr, size_t size,
11732 for (i = 0; i < size / 4; i++) {
11733 REG_WR(sc, addr + (i * 4), data[i]);
11737 static const char *get_ext_phy_type(uint32_t ext_phy_type)
11739 uint32_t phy_type_idx = ext_phy_type >> 8;
11740 static const char *types[] =
11741 { "DIRECT", "BNX2X-8071", "BNX2X-8072", "BNX2X-8073",
11742 "BNX2X-8705", "BNX2X-8706", "BNX2X-8726", "BNX2X-8481", "SFX-7101",
11744 "BNX2X-8727-NOC", "BNX2X-84823", "NOT_CONN", "FAILURE"
11747 if (phy_type_idx < 12)
11748 return types[phy_type_idx];
11749 else if (PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN == ext_phy_type)
11755 static const char *get_state(uint32_t state)
11757 uint32_t state_idx = state >> 12;
11758 static const char *states[] = { "CLOSED", "OPENING_WAIT4_LOAD",
11759 "OPENING_WAIT4_PORT", "OPEN", "CLOSING_WAIT4_HALT",
11760 "CLOSING_WAIT4_DELETE", "CLOSING_WAIT4_UNLOAD",
11761 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
11762 "UNKNOWN", "DISABLED", "DIAG", "ERROR", "UNDEFINED"
11765 if (state_idx <= 0xF)
11766 return states[state_idx];
11768 return states[0x10];
11771 static const char *get_recovery_state(uint32_t state)
11773 static const char *states[] = { "NONE", "DONE", "INIT",
11774 "WAIT", "FAILED", "NIC_LOADING"
11776 return states[state];
11779 static const char *get_rx_mode(uint32_t mode)
11781 static const char *modes[] = { "NONE", "NORMAL", "ALLMULTI",
11782 "PROMISC", "MAX_MULTICAST", "ERROR"
11786 return modes[mode];
11787 else if (BNX2X_MAX_MULTICAST == mode)
11793 #define BNX2X_INFO_STR_MAX 256
11794 static const char *get_bnx2x_flags(uint32_t flags)
11797 static const char *flag[] = { "ONE_PORT ", "NO_ISCSI ",
11798 "NO_FCOE ", "NO_WOL ", "USING_DAC ", "USING_MSIX ",
11799 "USING_MSI ", "DISABLE_MSI ", "UNKNOWN ", "NO_MCP ",
11800 "SAFC_TX_FLAG ", "MF_FUNC_DIS ", "TX_SWITCHING "
11802 static char flag_str[BNX2X_INFO_STR_MAX];
11803 memset(flag_str, 0, BNX2X_INFO_STR_MAX);
11805 for (i = 0; i < 5; i++)
11806 if (flags & (1 << i)) {
11807 strlcat(flag_str, flag[i], sizeof(flag_str));
11811 static char unknown[BNX2X_INFO_STR_MAX];
11812 snprintf(unknown, 32, "Unknown flag mask %x", flags);
11813 strlcat(flag_str, unknown, sizeof(flag_str));
11818 /* Prints useful adapter info. */
11819 void bnx2x_print_adapter_info(struct bnx2x_softc *sc)
11823 PMD_DRV_LOG(INFO, sc, "========================================");
11824 /* DPDK and Driver versions */
11825 PMD_DRV_LOG(INFO, sc, "%12s : %s", "DPDK",
11827 PMD_DRV_LOG(INFO, sc, "%12s : %s", "Driver",
11828 bnx2x_pmd_version());
11829 /* Firmware versions. */
11830 PMD_DRV_LOG(INFO, sc, "%12s : %d.%d.%d",
11832 BNX2X_5710_FW_MAJOR_VERSION,
11833 BNX2X_5710_FW_MINOR_VERSION,
11834 BNX2X_5710_FW_REVISION_VERSION);
11835 PMD_DRV_LOG(INFO, sc, "%12s : %s",
11836 "Bootcode", sc->devinfo.bc_ver_str);
11837 /* Hardware chip info. */
11838 PMD_DRV_LOG(INFO, sc, "%12s : %#08x", "ASIC", sc->devinfo.chip_id);
11839 PMD_DRV_LOG(INFO, sc, "%12s : %c%d", "Rev", (CHIP_REV(sc) >> 12) + 'A',
11840 (CHIP_METAL(sc) >> 4));
11841 /* Bus PCIe info. */
11842 PMD_DRV_LOG(INFO, sc, "%12s : 0x%x", "Vendor Id",
11843 sc->devinfo.vendor_id);
11844 PMD_DRV_LOG(INFO, sc, "%12s : 0x%x", "Device Id",
11845 sc->devinfo.device_id);
11846 PMD_DRV_LOG(INFO, sc, "%12s : width x%d, ", "Bus PCIe",
11847 sc->devinfo.pcie_link_width);
11848 switch (sc->devinfo.pcie_link_speed) {
11850 PMD_DRV_LOG(INFO, sc, "%23s", "2.5 Gbps");
11853 PMD_DRV_LOG(INFO, sc, "%21s", "5 Gbps");
11856 PMD_DRV_LOG(INFO, sc, "%21s", "8 Gbps");
11859 PMD_DRV_LOG(INFO, sc, "%33s", "Unknown link speed");
11861 /* Device features. */
11862 PMD_DRV_LOG(INFO, sc, "%12s : ", "Flags");
11863 /* Miscellaneous flags. */
11864 if (sc->devinfo.pcie_cap_flags & BNX2X_MSI_CAPABLE_FLAG) {
11865 PMD_DRV_LOG(INFO, sc, "%18s", "MSI");
11868 if (sc->devinfo.pcie_cap_flags & BNX2X_MSIX_CAPABLE_FLAG) {
11870 PMD_DRV_LOG(INFO, sc, "|");
11871 PMD_DRV_LOG(INFO, sc, "%20s", "MSI-X");
11874 PMD_DRV_LOG(INFO, sc, "%12s : %s", "OVLAN", (OVLAN(sc) ? "YES" : "NO"));
11875 PMD_DRV_LOG(INFO, sc, "%12s : %s", "MF", (IS_MF(sc) ? "YES" : "NO"));
11876 PMD_DRV_LOG(INFO, sc, "========================================");
11879 /* Prints useful device info. */
11880 void bnx2x_print_device_info(struct bnx2x_softc *sc)
11882 __rte_unused uint32_t ext_phy_type;
11883 uint32_t offset, reg_val;
11885 PMD_INIT_FUNC_TRACE(sc);
11886 offset = offsetof(struct shmem_region,
11887 dev_info.port_hw_config[0].external_phy_config);
11888 reg_val = REG_RD(sc, sc->devinfo.shmem_base + offset);
11889 if (sc->link_vars.phy_flags & PHY_XGXS_FLAG)
11890 ext_phy_type = ELINK_XGXS_EXT_PHY_TYPE(reg_val);
11892 ext_phy_type = ELINK_SERDES_EXT_PHY_TYPE(reg_val);
11894 /* Device features. */
11895 PMD_DRV_LOG(INFO, sc, "%12s : %u", "Bnx2x Func", sc->pcie_func);
11896 PMD_DRV_LOG(INFO, sc,
11897 "%12s : %s", "Bnx2x Flags", get_bnx2x_flags(sc->flags));
11898 PMD_DRV_LOG(INFO, sc, "%12s : %s", "DMAE Is",
11899 (sc->dmae_ready ? "Ready" : "Not Ready"));
11900 PMD_DRV_LOG(INFO, sc, "%12s : %u", "MTU", sc->mtu);
11901 PMD_DRV_LOG(INFO, sc,
11902 "%12s : %s", "PHY Type", get_ext_phy_type(ext_phy_type));
11903 PMD_DRV_LOG(INFO, sc, "%12s : %x:%x:%x:%x:%x:%x", "MAC Addr",
11904 sc->link_params.mac_addr[0],
11905 sc->link_params.mac_addr[1],
11906 sc->link_params.mac_addr[2],
11907 sc->link_params.mac_addr[3],
11908 sc->link_params.mac_addr[4],
11909 sc->link_params.mac_addr[5]);
11910 PMD_DRV_LOG(INFO, sc, "%12s : %s", "RX Mode", get_rx_mode(sc->rx_mode));
11911 PMD_DRV_LOG(INFO, sc, "%12s : %s", "State", get_state(sc->state));
11912 if (sc->recovery_state)
11913 PMD_DRV_LOG(INFO, sc, "%12s : %s", "Recovery",
11914 get_recovery_state(sc->recovery_state));
11917 switch (sc->sp->rss_rdata.rss_mode) {
11918 case ETH_RSS_MODE_DISABLED:
11919 PMD_DRV_LOG(INFO, sc, "%12s : %s", "Queues", "RSS mode - None");
11921 case ETH_RSS_MODE_REGULAR:
11922 PMD_DRV_LOG(INFO, sc, "%12s : %s,", "Queues", "RSS mode - Regular");
11923 PMD_DRV_LOG(INFO, sc, "%16d", sc->num_queues);
11926 PMD_DRV_LOG(INFO, sc, "%12s : %s", "Queues", "RSS mode - Unknown");
11930 PMD_DRV_LOG(INFO, sc, "%12s : CQ = %lx, EQ = %lx", "SPQ Left",
11931 sc->cq_spq_left, sc->eq_spq_left);
11933 PMD_DRV_LOG(INFO, sc,
11934 "%12s : %x", "Switch", sc->link_params.switch_cfg);
11935 PMD_DRV_LOG(INFO, sc, "pcie_bus=%d, pcie_device=%d",
11936 sc->pcie_bus, sc->pcie_device);
11937 PMD_DRV_LOG(INFO, sc, "bar0.addr=%p, bar1.addr=%p",
11938 sc->bar[BAR0].base_addr, sc->bar[BAR1].base_addr);
11939 PMD_DRV_LOG(INFO, sc, "port=%d, path=%d, vnic=%d, func=%d",
11940 PORT_ID(sc), PATH_ID(sc), VNIC_ID(sc), FUNC_ID(sc));