1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2007-2013 Broadcom Corporation.
4 * Eric Davis <edavis@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
6 * Gary Zambrano <zambrano@broadcom.com>
8 * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
9 * Copyright (c) 2015-2018 Cavium Inc.
10 * All rights reserved.
14 #define BNX2X_DRIVER_VERSION "1.78.18"
17 #include "bnx2x_vfpf.h"
19 #include "ecore_init.h"
20 #include "ecore_init_ops.h"
22 #include "rte_version.h"
24 #include <sys/types.h>
28 #include <rte_bitops.h>
29 #include <rte_string_fns.h>
31 #define BNX2X_PMD_VER_PREFIX "BNX2X PMD"
32 #define BNX2X_PMD_VERSION_MAJOR 1
33 #define BNX2X_PMD_VERSION_MINOR 1
34 #define BNX2X_PMD_VERSION_REVISION 0
35 #define BNX2X_PMD_VERSION_PATCH 1
37 static inline const char *
38 bnx2x_pmd_version(void)
40 static char version[32];
42 snprintf(version, sizeof(version), "%s %s_%d.%d.%d.%d",
45 BNX2X_PMD_VERSION_MAJOR,
46 BNX2X_PMD_VERSION_MINOR,
47 BNX2X_PMD_VERSION_REVISION,
48 BNX2X_PMD_VERSION_PATCH);
53 static z_stream zlib_stream;
55 #define EVL_VLID_MASK 0x0FFF
57 #define BNX2X_DEF_SB_ATT_IDX 0x0001
58 #define BNX2X_DEF_SB_IDX 0x0002
61 * FLR Support - bnx2x_pf_flr_clnup() is called during nic_load in the per
62 * function HW initialization.
64 #define FLR_WAIT_USEC 10000 /* 10 msecs */
65 #define FLR_WAIT_INTERVAL 50 /* usecs */
66 #define FLR_POLL_CNT (FLR_WAIT_USEC / FLR_WAIT_INTERVAL) /* 200 */
68 struct pbf_pN_buf_regs {
75 struct pbf_pN_cmd_regs {
81 /* resources needed for unloading a previously loaded device */
83 #define BNX2X_PREV_WAIT_NEEDED 1
84 rte_spinlock_t bnx2x_prev_mtx;
85 struct bnx2x_prev_list_node {
86 LIST_ENTRY(bnx2x_prev_list_node) node;
94 static LIST_HEAD(, bnx2x_prev_list_node) bnx2x_prev_list
95 = LIST_HEAD_INITIALIZER(bnx2x_prev_list);
97 static int load_count[2][3] = { { 0 } };
98 /* per-path: 0-common, 1-port0, 2-port1 */
100 static void bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg,
102 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc);
103 static void storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng,
105 static void bnx2x_set_reset_global(struct bnx2x_softc *sc);
106 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc);
107 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine);
108 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc);
109 static uint8_t bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global,
111 static void bnx2x_int_disable(struct bnx2x_softc *sc);
112 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc);
113 static void bnx2x_pf_disable(struct bnx2x_softc *sc);
114 static void bnx2x_update_rx_prod(struct bnx2x_softc *sc,
115 struct bnx2x_fastpath *fp,
116 uint16_t rx_bd_prod, uint16_t rx_cq_prod);
117 static void bnx2x_link_report_locked(struct bnx2x_softc *sc);
118 static void bnx2x_link_report(struct bnx2x_softc *sc);
119 void bnx2x_link_status_update(struct bnx2x_softc *sc);
120 static int bnx2x_alloc_mem(struct bnx2x_softc *sc);
121 static void bnx2x_free_mem(struct bnx2x_softc *sc);
122 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc);
123 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc);
124 static __rte_noinline
125 int bnx2x_nic_load(struct bnx2x_softc *sc);
127 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc);
128 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp);
129 static void bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id,
130 uint8_t storm, uint16_t index, uint8_t op,
133 int bnx2x_cmpxchg(volatile int *addr, int old, int new)
135 return __sync_val_compare_and_swap(addr, old, new);
139 bnx2x_dma_alloc(struct bnx2x_softc *sc, size_t size, struct bnx2x_dma *dma,
140 const char *msg, uint32_t align)
142 char mz_name[RTE_MEMZONE_NAMESIZE];
143 const struct rte_memzone *z;
147 snprintf(mz_name, sizeof(mz_name), "bnx2x%d_%s_%" PRIx64, SC_ABS_FUNC(sc), msg,
148 rte_get_timer_cycles());
150 snprintf(mz_name, sizeof(mz_name), "bnx2x%d_%s_%" PRIx64, sc->pcie_device, msg,
151 rte_get_timer_cycles());
153 /* Caller must take care that strlen(mz_name) < RTE_MEMZONE_NAMESIZE */
154 z = rte_memzone_reserve_aligned(mz_name, (uint64_t)size,
156 RTE_MEMZONE_IOVA_CONTIG, align);
158 PMD_DRV_LOG(ERR, sc, "DMA alloc failed for %s", msg);
161 dma->paddr = (uint64_t) z->iova;
162 dma->vaddr = z->addr;
163 dma->mzone = (const void *)z;
165 PMD_DRV_LOG(DEBUG, sc,
166 "%s: virt=%p phys=%" PRIx64, msg, dma->vaddr, dma->paddr);
171 void bnx2x_dma_free(struct bnx2x_dma *dma)
173 if (dma->mzone == NULL)
176 rte_memzone_free((const struct rte_memzone *)dma->mzone);
184 static int bnx2x_acquire_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
186 uint32_t lock_status;
187 uint32_t resource_bit = (1 << resource);
188 int func = SC_FUNC(sc);
189 uint32_t hw_lock_control_reg;
192 #ifndef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
194 PMD_INIT_FUNC_TRACE(sc);
196 PMD_INIT_FUNC_TRACE(sc);
199 /* validate the resource is within range */
200 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
201 PMD_DRV_LOG(NOTICE, sc,
202 "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
208 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
210 hw_lock_control_reg =
211 (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
214 /* validate the resource is not already taken */
215 lock_status = REG_RD(sc, hw_lock_control_reg);
216 if (lock_status & resource_bit) {
217 PMD_DRV_LOG(NOTICE, sc,
218 "resource in use (status 0x%x bit 0x%x)",
219 lock_status, resource_bit);
223 /* try every 5ms for 5 seconds */
224 for (cnt = 0; cnt < 1000; cnt++) {
225 REG_WR(sc, (hw_lock_control_reg + 4), resource_bit);
226 lock_status = REG_RD(sc, hw_lock_control_reg);
227 if (lock_status & resource_bit) {
233 PMD_DRV_LOG(NOTICE, sc, "Resource 0x%x resource_bit 0x%x lock timeout!",
234 resource, resource_bit);
238 static int bnx2x_release_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
240 uint32_t lock_status;
241 uint32_t resource_bit = (1 << resource);
242 int func = SC_FUNC(sc);
243 uint32_t hw_lock_control_reg;
245 #ifndef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
247 PMD_INIT_FUNC_TRACE(sc);
249 PMD_INIT_FUNC_TRACE(sc);
252 /* validate the resource is within range */
253 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
254 PMD_DRV_LOG(NOTICE, sc,
255 "(resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE)"
256 " resource_bit 0x%x", resource, resource_bit);
261 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
263 hw_lock_control_reg =
264 (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
267 /* validate the resource is currently taken */
268 lock_status = REG_RD(sc, hw_lock_control_reg);
269 if (!(lock_status & resource_bit)) {
270 PMD_DRV_LOG(NOTICE, sc,
271 "resource not in use (status 0x%x bit 0x%x)",
272 lock_status, resource_bit);
276 REG_WR(sc, hw_lock_control_reg, resource_bit);
280 static void bnx2x_acquire_phy_lock(struct bnx2x_softc *sc)
283 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_MDIO);
286 static void bnx2x_release_phy_lock(struct bnx2x_softc *sc)
288 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_MDIO);
289 BNX2X_PHY_UNLOCK(sc);
292 /* copy command into DMAE command memory and set DMAE command Go */
293 void bnx2x_post_dmae(struct bnx2x_softc *sc, struct dmae_command *dmae, int idx)
298 cmd_offset = (DMAE_REG_CMD_MEM + (sizeof(struct dmae_command) * idx));
299 for (i = 0; i < ((sizeof(struct dmae_command) / 4)); i++) {
300 REG_WR(sc, (cmd_offset + (i * 4)), *(((uint32_t *) dmae) + i));
303 REG_WR(sc, dmae_reg_go_c[idx], 1);
306 uint32_t bnx2x_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type)
308 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
309 DMAE_COMMAND_C_TYPE_ENABLE);
312 uint32_t bnx2x_dmae_opcode_clr_src_reset(uint32_t opcode)
314 return opcode & ~DMAE_COMMAND_SRC_RESET;
318 bnx2x_dmae_opcode(struct bnx2x_softc * sc, uint8_t src_type, uint8_t dst_type,
319 uint8_t with_comp, uint8_t comp_type)
323 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
324 (dst_type << DMAE_COMMAND_DST_SHIFT));
326 opcode |= (DMAE_COMMAND_SRC_RESET | DMAE_COMMAND_DST_RESET);
328 opcode |= (SC_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
330 opcode |= ((SC_VN(sc) << DMAE_COMMAND_E1HVN_SHIFT) |
331 (SC_VN(sc) << DMAE_COMMAND_DST_VN_SHIFT));
333 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
336 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
338 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
342 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
349 bnx2x_prep_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae,
350 uint8_t src_type, uint8_t dst_type)
352 memset(dmae, 0, sizeof(struct dmae_command));
355 dmae->opcode = bnx2x_dmae_opcode(sc, src_type, dst_type,
356 TRUE, DMAE_COMP_PCI);
358 /* fill in the completion parameters */
359 dmae->comp_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_comp));
360 dmae->comp_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_comp));
361 dmae->comp_val = DMAE_COMP_VAL;
364 /* issue a DMAE command over the init channel and wait for completion */
366 bnx2x_issue_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae)
368 uint32_t *wb_comp = BNX2X_SP(sc, wb_comp);
369 int timeout = CHIP_REV_IS_SLOW(sc) ? 400000 : 4000;
371 /* reset completion */
374 /* post the command on the channel used for initializations */
375 bnx2x_post_dmae(sc, dmae, INIT_DMAE_C(sc));
377 /* wait for completion */
380 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
382 (sc->recovery_state != BNX2X_RECOVERY_DONE &&
383 sc->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
384 PMD_DRV_LOG(INFO, sc, "DMAE timeout!");
392 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
393 PMD_DRV_LOG(INFO, sc, "DMAE PCI error!");
394 return DMAE_PCI_ERROR;
400 void bnx2x_read_dmae(struct bnx2x_softc *sc, uint32_t src_addr, uint32_t len32)
402 struct dmae_command dmae;
407 if (!sc->dmae_ready) {
408 data = BNX2X_SP(sc, wb_data[0]);
410 for (i = 0; i < len32; i++) {
411 data[i] = REG_RD(sc, (src_addr + (i * 4)));
417 /* set opcode and fixed command fields */
418 bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
420 /* fill in addresses and len */
421 dmae.src_addr_lo = (src_addr >> 2); /* GRC addr has dword resolution */
422 dmae.src_addr_hi = 0;
423 dmae.dst_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_data));
424 dmae.dst_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_data));
427 /* issue the command and wait for completion */
428 if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
429 rte_panic("DMAE failed (%d)", rc);
434 bnx2x_write_dmae(struct bnx2x_softc *sc, rte_iova_t dma_addr, uint32_t dst_addr,
437 struct dmae_command dmae;
440 if (!sc->dmae_ready) {
441 ecore_init_str_wr(sc, dst_addr, BNX2X_SP(sc, wb_data[0]), len32);
445 /* set opcode and fixed command fields */
446 bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
448 /* fill in addresses and len */
449 dmae.src_addr_lo = U64_LO(dma_addr);
450 dmae.src_addr_hi = U64_HI(dma_addr);
451 dmae.dst_addr_lo = (dst_addr >> 2); /* GRC addr has dword resolution */
452 dmae.dst_addr_hi = 0;
455 /* issue the command and wait for completion */
456 if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
457 rte_panic("DMAE failed (%d)", rc);
462 bnx2x_write_dmae_phys_len(struct bnx2x_softc *sc, rte_iova_t phys_addr,
463 uint32_t addr, uint32_t len)
465 uint32_t dmae_wr_max = DMAE_LEN32_WR_MAX(sc);
468 while (len > dmae_wr_max) {
469 bnx2x_write_dmae(sc, (phys_addr + offset), /* src DMA address */
470 (addr + offset), /* dst GRC address */
472 offset += (dmae_wr_max * 4);
476 bnx2x_write_dmae(sc, (phys_addr + offset), /* src DMA address */
477 (addr + offset), /* dst GRC address */
482 bnx2x_set_ctx_validation(struct bnx2x_softc *sc, struct eth_context *cxt,
485 /* ustorm cxt validation */
486 cxt->ustorm_ag_context.cdu_usage =
487 CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
488 CDU_REGION_NUMBER_UCM_AG,
489 ETH_CONNECTION_TYPE);
490 /* xcontext validation */
491 cxt->xstorm_ag_context.cdu_reserved =
492 CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
493 CDU_REGION_NUMBER_XCM_AG,
494 ETH_CONNECTION_TYPE);
498 bnx2x_storm_memset_hc_timeout(struct bnx2x_softc *sc, uint8_t fw_sb_id,
499 uint8_t sb_index, uint8_t ticks)
502 (BAR_CSTRORM_INTMEM +
503 CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(fw_sb_id, sb_index));
505 REG_WR8(sc, addr, ticks);
509 bnx2x_storm_memset_hc_disable(struct bnx2x_softc *sc, uint16_t fw_sb_id,
510 uint8_t sb_index, uint8_t disable)
512 uint32_t enable_flag =
513 (disable) ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
515 (BAR_CSTRORM_INTMEM +
516 CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(fw_sb_id, sb_index));
520 flags = REG_RD8(sc, addr);
521 flags &= ~HC_INDEX_DATA_HC_ENABLED;
522 flags |= enable_flag;
523 REG_WR8(sc, addr, flags);
527 bnx2x_update_coalesce_sb_index(struct bnx2x_softc *sc, uint8_t fw_sb_id,
528 uint8_t sb_index, uint8_t disable, uint16_t usec)
530 uint8_t ticks = (usec / 4);
532 bnx2x_storm_memset_hc_timeout(sc, fw_sb_id, sb_index, ticks);
534 disable = (disable) ? 1 : ((usec) ? 0 : 1);
535 bnx2x_storm_memset_hc_disable(sc, fw_sb_id, sb_index, disable);
538 uint32_t elink_cb_reg_read(struct bnx2x_softc *sc, uint32_t reg_addr)
540 return REG_RD(sc, reg_addr);
543 void elink_cb_reg_write(struct bnx2x_softc *sc, uint32_t reg_addr, uint32_t val)
545 REG_WR(sc, reg_addr, val);
549 elink_cb_event_log(__rte_unused struct bnx2x_softc *sc,
550 __rte_unused const elink_log_id_t elink_log_id, ...)
552 PMD_DRV_LOG(DEBUG, sc, "ELINK EVENT LOG (%d)", elink_log_id);
555 static int bnx2x_set_spio(struct bnx2x_softc *sc, int spio, uint32_t mode)
559 /* Only 2 SPIOs are configurable */
560 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
561 PMD_DRV_LOG(NOTICE, sc, "Invalid SPIO 0x%x", spio);
565 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
567 /* read SPIO and mask except the float bits */
568 spio_reg = (REG_RD(sc, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
571 case MISC_SPIO_OUTPUT_LOW:
572 /* clear FLOAT and set CLR */
573 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
574 spio_reg |= (spio << MISC_SPIO_CLR_POS);
577 case MISC_SPIO_OUTPUT_HIGH:
578 /* clear FLOAT and set SET */
579 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
580 spio_reg |= (spio << MISC_SPIO_SET_POS);
583 case MISC_SPIO_INPUT_HI_Z:
585 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
592 REG_WR(sc, MISC_REG_SPIO, spio_reg);
593 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
598 static int bnx2x_gpio_read(struct bnx2x_softc *sc, int gpio_num, uint8_t port)
600 /* The GPIO should be swapped if swap register is set and active */
601 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
602 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
603 int gpio_shift = gpio_num;
605 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
607 uint32_t gpio_mask = (1 << gpio_shift);
610 if (gpio_num > MISC_REGISTERS_GPIO_3) {
611 PMD_DRV_LOG(NOTICE, sc, "Invalid GPIO %d", gpio_num);
615 /* read GPIO value */
616 gpio_reg = REG_RD(sc, MISC_REG_GPIO);
618 /* get the requested pin value */
619 return ((gpio_reg & gpio_mask) == gpio_mask) ? 1 : 0;
623 bnx2x_gpio_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode, uint8_t port)
625 /* The GPIO should be swapped if swap register is set and active */
626 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
627 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
628 int gpio_shift = gpio_num;
630 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
632 uint32_t gpio_mask = (1 << gpio_shift);
635 if (gpio_num > MISC_REGISTERS_GPIO_3) {
636 PMD_DRV_LOG(NOTICE, sc, "Invalid GPIO %d", gpio_num);
640 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
642 /* read GPIO and mask except the float bits */
643 gpio_reg = (REG_RD(sc, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
646 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
647 /* clear FLOAT and set CLR */
648 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
649 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
652 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
653 /* clear FLOAT and set SET */
654 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
655 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
658 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
660 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
667 REG_WR(sc, MISC_REG_GPIO, gpio_reg);
668 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
674 bnx2x_gpio_mult_write(struct bnx2x_softc *sc, uint8_t pins, uint32_t mode)
678 /* any port swapping should be handled by caller */
680 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
682 /* read GPIO and mask except the float bits */
683 gpio_reg = REG_RD(sc, MISC_REG_GPIO);
684 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
685 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
686 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
689 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
691 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
694 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
696 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
699 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
701 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
705 PMD_DRV_LOG(NOTICE, sc,
706 "Invalid GPIO mode assignment %d", mode);
707 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
711 REG_WR(sc, MISC_REG_GPIO, gpio_reg);
712 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
718 bnx2x_gpio_int_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode,
721 /* The GPIO should be swapped if swap register is set and active */
722 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
723 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
724 int gpio_shift = gpio_num;
726 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
728 uint32_t gpio_mask = (1 << gpio_shift);
731 if (gpio_num > MISC_REGISTERS_GPIO_3) {
732 PMD_DRV_LOG(NOTICE, sc, "Invalid GPIO %d", gpio_num);
736 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
739 gpio_reg = REG_RD(sc, MISC_REG_GPIO_INT);
742 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
743 /* clear SET and set CLR */
744 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
745 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
748 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
749 /* clear CLR and set SET */
750 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
751 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
758 REG_WR(sc, MISC_REG_GPIO_INT, gpio_reg);
759 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
765 elink_cb_gpio_read(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t port)
767 return bnx2x_gpio_read(sc, gpio_num, port);
770 uint8_t elink_cb_gpio_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode, /* 0=low 1=high */
773 return bnx2x_gpio_write(sc, gpio_num, mode, port);
777 elink_cb_gpio_mult_write(struct bnx2x_softc * sc, uint8_t pins,
778 uint8_t mode /* 0=low 1=high */ )
780 return bnx2x_gpio_mult_write(sc, pins, mode);
783 uint8_t elink_cb_gpio_int_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode, /* 0=low 1=high */
786 return bnx2x_gpio_int_write(sc, gpio_num, mode, port);
789 void elink_cb_notify_link_changed(struct bnx2x_softc *sc)
791 REG_WR(sc, (MISC_REG_AEU_GENERAL_ATTN_12 +
792 (SC_FUNC(sc) * sizeof(uint32_t))), 1);
795 /* send the MCP a request, block until there is a reply */
797 elink_cb_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
799 int mb_idx = SC_FW_MB_IDX(sc);
803 uint8_t delay = CHIP_REV_IS_SLOW(sc) ? 100 : 10;
806 SHMEM_WR(sc, func_mb[mb_idx].drv_mb_param, param);
807 SHMEM_WR(sc, func_mb[mb_idx].drv_mb_header, (command | seq));
809 PMD_DRV_LOG(DEBUG, sc,
810 "wrote command 0x%08x to FW MB param 0x%08x",
811 (command | seq), param);
813 /* Let the FW do it's magic. GIve it up to 5 seconds... */
816 rc = SHMEM_RD(sc, func_mb[mb_idx].fw_mb_header);
817 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
819 /* is this a reply to our command? */
820 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) {
821 rc &= FW_MSG_CODE_MASK;
824 PMD_DRV_LOG(NOTICE, sc, "FW failed to respond!");
832 bnx2x_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
834 return elink_cb_fw_command(sc, command, param);
838 __storm_memset_dma_mapping(struct bnx2x_softc *sc, uint32_t addr,
841 REG_WR(sc, addr, U64_LO(mapping));
842 REG_WR(sc, (addr + 4), U64_HI(mapping));
846 storm_memset_spq_addr(struct bnx2x_softc *sc, rte_iova_t mapping,
849 uint32_t addr = (XSEM_REG_FAST_MEMORY +
850 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid));
851 __storm_memset_dma_mapping(sc, addr, mapping);
855 storm_memset_vf_to_pf(struct bnx2x_softc *sc, uint16_t abs_fid, uint16_t pf_id)
857 REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid)),
859 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid)),
861 REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid)),
863 REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid)),
868 storm_memset_func_en(struct bnx2x_softc *sc, uint16_t abs_fid, uint8_t enable)
870 REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid)),
872 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid)),
874 REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid)),
876 REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid)),
881 storm_memset_eq_data(struct bnx2x_softc *sc, struct event_ring_data *eq_data,
887 addr = (BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid));
888 size = sizeof(struct event_ring_data);
889 ecore_storm_memset_struct(sc, addr, size, (uint32_t *) eq_data);
893 storm_memset_eq_prod(struct bnx2x_softc *sc, uint16_t eq_prod, uint16_t pfid)
895 uint32_t addr = (BAR_CSTRORM_INTMEM +
896 CSTORM_EVENT_RING_PROD_OFFSET(pfid));
897 REG_WR16(sc, addr, eq_prod);
901 * Post a slowpath command.
903 * A slowpath command is used to propagate a configuration change through
904 * the controller in a controlled manner, allowing each STORM processor and
905 * other H/W blocks to phase in the change. The commands sent on the
906 * slowpath are referred to as ramrods. Depending on the ramrod used the
907 * completion of the ramrod will occur in different ways. Here's a
908 * breakdown of ramrods and how they complete:
910 * RAMROD_CMD_ID_ETH_PORT_SETUP
911 * Used to setup the leading connection on a port. Completes on the
912 * Receive Completion Queue (RCQ) of that port (typically fp[0]).
914 * RAMROD_CMD_ID_ETH_CLIENT_SETUP
915 * Used to setup an additional connection on a port. Completes on the
916 * RCQ of the multi-queue/RSS connection being initialized.
918 * RAMROD_CMD_ID_ETH_STAT_QUERY
919 * Used to force the storm processors to update the statistics database
920 * in host memory. This ramrod is send on the leading connection CID and
921 * completes as an index increment of the CSTORM on the default status
924 * RAMROD_CMD_ID_ETH_UPDATE
925 * Used to update the state of the leading connection, usually to udpate
926 * the RSS indirection table. Completes on the RCQ of the leading
927 * connection. (Not currently used under FreeBSD until OS support becomes
930 * RAMROD_CMD_ID_ETH_HALT
931 * Used when tearing down a connection prior to driver unload. Completes
932 * on the RCQ of the multi-queue/RSS connection being torn down. Don't
933 * use this on the leading connection.
935 * RAMROD_CMD_ID_ETH_SET_MAC
936 * Sets the Unicast/Broadcast/Multicast used by the port. Completes on
937 * the RCQ of the leading connection.
939 * RAMROD_CMD_ID_ETH_CFC_DEL
940 * Used when tearing down a conneciton prior to driver unload. Completes
941 * on the RCQ of the leading connection (since the current connection
942 * has been completely removed from controller memory).
944 * RAMROD_CMD_ID_ETH_PORT_DEL
945 * Used to tear down the leading connection prior to driver unload,
946 * typically fp[0]. Completes as an index increment of the CSTORM on the
947 * default status block.
949 * RAMROD_CMD_ID_ETH_FORWARD_SETUP
950 * Used for connection offload. Completes on the RCQ of the multi-queue
951 * RSS connection that is being offloaded. (Not currently used under
954 * There can only be one command pending per function.
957 * 0 = Success, !0 = Failure.
960 /* must be called under the spq lock */
961 static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x_softc *sc)
963 struct eth_spe *next_spe = sc->spq_prod_bd;
965 if (sc->spq_prod_bd == sc->spq_last_bd) {
966 /* wrap back to the first eth_spq */
967 sc->spq_prod_bd = sc->spq;
968 sc->spq_prod_idx = 0;
977 /* must be called under the spq lock */
978 static void bnx2x_sp_prod_update(struct bnx2x_softc *sc)
980 int func = SC_FUNC(sc);
983 * Make sure that BD data is updated before writing the producer.
984 * BD data is written to the memory, the producer is read from the
985 * memory, thus we need a full memory barrier to ensure the ordering.
989 REG_WR16(sc, (BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func)),
996 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
998 * @cmd: command to check
999 * @cmd_type: command type
1001 static int bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
1003 if ((cmd_type == NONE_CONNECTION_TYPE) ||
1004 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
1005 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
1006 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
1007 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
1008 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
1009 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) {
1017 * bnx2x_sp_post - place a single command on an SP ring
1019 * @sc: driver handle
1020 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
1021 * @cid: SW CID the command is related to
1022 * @data_hi: command private data address (high 32 bits)
1023 * @data_lo: command private data address (low 32 bits)
1024 * @cmd_type: command type (e.g. NONE, ETH)
1026 * SP data is handled as if it's always an address pair, thus data fields are
1027 * not swapped to little endian in upper functions. Instead this function swaps
1028 * data as if it's two uint32 fields.
1031 bnx2x_sp_post(struct bnx2x_softc *sc, int command, int cid, uint32_t data_hi,
1032 uint32_t data_lo, int cmd_type)
1034 struct eth_spe *spe;
1038 common = bnx2x_is_contextless_ramrod(command, cmd_type);
1041 if (!atomic_load_acq_long(&sc->eq_spq_left)) {
1042 PMD_DRV_LOG(INFO, sc, "EQ ring is full!");
1046 if (!atomic_load_acq_long(&sc->cq_spq_left)) {
1047 PMD_DRV_LOG(INFO, sc, "SPQ ring is full!");
1052 spe = bnx2x_sp_get_next(sc);
1054 /* CID needs port number to be encoded int it */
1055 spe->hdr.conn_and_cmd_data =
1056 htole32((command << SPE_HDR_CMD_ID_SHIFT) | HW_CID(sc, cid));
1058 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
1060 /* TBD: Check if it works for VFs */
1061 type |= ((SC_FUNC(sc) << SPE_HDR_FUNCTION_ID_SHIFT) &
1062 SPE_HDR_FUNCTION_ID);
1064 spe->hdr.type = htole16(type);
1066 spe->data.update_data_addr.hi = htole32(data_hi);
1067 spe->data.update_data_addr.lo = htole32(data_lo);
1070 * It's ok if the actual decrement is issued towards the memory
1071 * somewhere between the lock and unlock. Thus no more explict
1072 * memory barrier is needed.
1075 atomic_subtract_acq_long(&sc->eq_spq_left, 1);
1077 atomic_subtract_acq_long(&sc->cq_spq_left, 1);
1080 PMD_DRV_LOG(DEBUG, sc,
1081 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x"
1082 "data (%x:%x) type(0x%x) left (CQ, EQ) (%lx,%lx)",
1084 (uint32_t) U64_HI(sc->spq_dma.paddr),
1085 (uint32_t) (U64_LO(sc->spq_dma.paddr) +
1086 (uint8_t *) sc->spq_prod_bd -
1087 (uint8_t *) sc->spq), command, common,
1088 HW_CID(sc, cid), data_hi, data_lo, type,
1089 atomic_load_acq_long(&sc->cq_spq_left),
1090 atomic_load_acq_long(&sc->eq_spq_left));
1092 /* RAMROD completion is processed in bnx2x_intr_legacy()
1093 * which can run from different contexts.
1094 * Ask bnx2x_intr_intr() to process RAMROD
1095 * completion whenever it gets scheduled.
1097 rte_atomic32_set(&sc->scan_fp, 1);
1098 bnx2x_sp_prod_update(sc);
1103 static void bnx2x_drv_pulse(struct bnx2x_softc *sc)
1105 SHMEM_WR(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb,
1106 sc->fw_drv_pulse_wr_seq);
1109 static int bnx2x_tx_queue_has_work(const struct bnx2x_fastpath *fp)
1112 struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1114 if (unlikely(!txq)) {
1115 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1119 mb(); /* status block fields can change */
1120 hw_cons = le16toh(*fp->tx_cons_sb);
1121 return hw_cons != txq->tx_pkt_head;
1124 static uint8_t bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
1126 /* expand this for multi-cos if ever supported */
1127 return bnx2x_tx_queue_has_work(fp);
1130 static int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
1132 uint16_t rx_cq_cons_sb;
1133 struct bnx2x_rx_queue *rxq;
1134 rxq = fp->sc->rx_queues[fp->index];
1135 if (unlikely(!rxq)) {
1136 PMD_RX_LOG(ERR, "ERROR: RX queue is NULL");
1140 mb(); /* status block fields can change */
1141 rx_cq_cons_sb = le16toh(*fp->rx_cq_cons_sb);
1142 if (unlikely((rx_cq_cons_sb & MAX_RCQ_ENTRIES(rxq)) ==
1143 MAX_RCQ_ENTRIES(rxq)))
1146 PMD_RX_LOG(DEBUG, "hw CQ cons = %d, sw CQ cons = %d",
1147 rx_cq_cons_sb, rxq->rx_cq_head);
1149 return rxq->rx_cq_head != rx_cq_cons_sb;
1153 bnx2x_sp_event(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
1154 union eth_rx_cqe *rr_cqe)
1156 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1157 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1158 enum ecore_queue_cmd drv_cmd = ECORE_Q_CMD_MAX;
1159 struct ecore_queue_sp_obj *q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
1161 PMD_DRV_LOG(DEBUG, sc,
1162 "fp=%d cid=%d got ramrod #%d state is %x type is %d",
1163 fp->index, cid, command, sc->state,
1164 rr_cqe->ramrod_cqe.ramrod_type);
1167 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1168 PMD_DRV_LOG(DEBUG, sc, "got UPDATE ramrod. CID %d", cid);
1169 drv_cmd = ECORE_Q_CMD_UPDATE;
1172 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1173 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] setup ramrod", cid);
1174 drv_cmd = ECORE_Q_CMD_SETUP;
1177 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1178 PMD_DRV_LOG(DEBUG, sc,
1179 "got MULTI[%d] tx-only setup ramrod", cid);
1180 drv_cmd = ECORE_Q_CMD_SETUP_TX_ONLY;
1183 case (RAMROD_CMD_ID_ETH_HALT):
1184 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] halt ramrod", cid);
1185 drv_cmd = ECORE_Q_CMD_HALT;
1188 case (RAMROD_CMD_ID_ETH_TERMINATE):
1189 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] teminate ramrod", cid);
1190 drv_cmd = ECORE_Q_CMD_TERMINATE;
1193 case (RAMROD_CMD_ID_ETH_EMPTY):
1194 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] empty ramrod", cid);
1195 drv_cmd = ECORE_Q_CMD_EMPTY;
1199 PMD_DRV_LOG(DEBUG, sc,
1200 "ERROR: unexpected MC reply (%d)"
1201 "on fp[%d]", command, fp->index);
1205 if ((drv_cmd != ECORE_Q_CMD_MAX) &&
1206 q_obj->complete_cmd(sc, q_obj, drv_cmd)) {
1208 * q_obj->complete_cmd() failure means that this was
1209 * an unexpected completion.
1211 * In this case we don't want to increase the sc->spq_left
1212 * because apparently we haven't sent this command the first
1215 // rte_panic("Unexpected SP completion");
1219 atomic_add_acq_long(&sc->cq_spq_left, 1);
1221 PMD_DRV_LOG(DEBUG, sc, "sc->cq_spq_left 0x%lx",
1222 atomic_load_acq_long(&sc->cq_spq_left));
1225 static uint8_t bnx2x_rxeof(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
1227 struct bnx2x_rx_queue *rxq;
1228 uint16_t bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
1229 uint16_t hw_cq_cons, sw_cq_cons, sw_cq_prod;
1231 rte_spinlock_lock(&(fp)->rx_mtx);
1233 rxq = sc->rx_queues[fp->index];
1235 PMD_RX_LOG(ERR, "RX queue %d is NULL", fp->index);
1236 rte_spinlock_unlock(&(fp)->rx_mtx);
1240 /* CQ "next element" is of the size of the regular element */
1241 hw_cq_cons = le16toh(*fp->rx_cq_cons_sb);
1242 if (unlikely((hw_cq_cons & USABLE_RCQ_ENTRIES_PER_PAGE) ==
1243 USABLE_RCQ_ENTRIES_PER_PAGE)) {
1247 bd_cons = rxq->rx_bd_head;
1248 bd_prod = rxq->rx_bd_tail;
1249 bd_prod_fw = bd_prod;
1250 sw_cq_cons = rxq->rx_cq_head;
1251 sw_cq_prod = rxq->rx_cq_tail;
1254 * Memory barrier necessary as speculative reads of the rx
1255 * buffer can be ahead of the index in the status block
1259 while (sw_cq_cons != hw_cq_cons) {
1260 union eth_rx_cqe *cqe;
1261 struct eth_fast_path_rx_cqe *cqe_fp;
1262 uint8_t cqe_fp_flags;
1263 enum eth_rx_cqe_type cqe_fp_type;
1265 comp_ring_cons = RCQ_ENTRY(sw_cq_cons, rxq);
1266 bd_prod = RX_BD(bd_prod, rxq);
1267 bd_cons = RX_BD(bd_cons, rxq);
1269 cqe = &rxq->cq_ring[comp_ring_cons];
1270 cqe_fp = &cqe->fast_path_cqe;
1271 cqe_fp_flags = cqe_fp->type_error_flags;
1272 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
1274 /* is this a slowpath msg? */
1275 if (CQE_TYPE_SLOW(cqe_fp_type)) {
1276 bnx2x_sp_event(sc, fp, cqe);
1280 /* is this an error packet? */
1281 if (unlikely(cqe_fp_flags &
1282 ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG)) {
1283 PMD_RX_LOG(DEBUG, "flags 0x%x rx packet %u",
1284 cqe_fp_flags, sw_cq_cons);
1288 PMD_RX_LOG(DEBUG, "Dropping fastpath called from attn poller!");
1291 bd_cons = NEXT_RX_BD(bd_cons);
1292 bd_prod = NEXT_RX_BD(bd_prod);
1293 bd_prod_fw = NEXT_RX_BD(bd_prod_fw);
1296 sw_cq_prod = NEXT_RCQ_IDX(sw_cq_prod);
1297 sw_cq_cons = NEXT_RCQ_IDX(sw_cq_cons);
1299 } /* while work to do */
1301 rxq->rx_bd_head = bd_cons;
1302 rxq->rx_bd_tail = bd_prod_fw;
1303 rxq->rx_cq_head = sw_cq_cons;
1304 rxq->rx_cq_tail = sw_cq_prod;
1306 PMD_RX_LOG(DEBUG, "BD prod = %d, sw CQ prod = %d",
1307 bd_prod_fw, sw_cq_prod);
1309 /* Update producers */
1310 bnx2x_update_rx_prod(sc, fp, bd_prod_fw, sw_cq_prod);
1312 rte_spinlock_unlock(&(fp)->rx_mtx);
1314 return sw_cq_cons != hw_cq_cons;
1318 bnx2x_free_tx_pkt(__rte_unused struct bnx2x_fastpath *fp, struct bnx2x_tx_queue *txq,
1319 uint16_t pkt_idx, uint16_t bd_idx)
1321 struct eth_tx_start_bd *tx_start_bd =
1322 &txq->tx_ring[TX_BD(bd_idx, txq)].start_bd;
1323 uint16_t nbd = rte_le_to_cpu_16(tx_start_bd->nbd);
1324 struct rte_mbuf *tx_mbuf = txq->sw_ring[TX_BD(pkt_idx, txq)];
1326 if (likely(tx_mbuf != NULL)) {
1327 rte_pktmbuf_free_seg(tx_mbuf);
1329 PMD_RX_LOG(ERR, "fp[%02d] lost mbuf %lu",
1330 fp->index, (unsigned long)TX_BD(pkt_idx, txq));
1333 txq->sw_ring[TX_BD(pkt_idx, txq)] = NULL;
1334 txq->nb_tx_avail += nbd;
1337 bd_idx = NEXT_TX_BD(bd_idx);
1342 /* processes transmit completions */
1343 uint8_t bnx2x_txeof(__rte_unused struct bnx2x_softc * sc, struct bnx2x_fastpath * fp)
1345 uint16_t bd_cons, hw_cons, sw_cons;
1346 __rte_unused uint16_t tx_bd_avail;
1348 struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1350 if (unlikely(!txq)) {
1351 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1355 bd_cons = txq->tx_bd_head;
1356 hw_cons = rte_le_to_cpu_16(*fp->tx_cons_sb);
1357 sw_cons = txq->tx_pkt_head;
1359 while (sw_cons != hw_cons) {
1360 bd_cons = bnx2x_free_tx_pkt(fp, txq, sw_cons, bd_cons);
1364 txq->tx_pkt_head = sw_cons;
1365 txq->tx_bd_head = bd_cons;
1367 tx_bd_avail = txq->nb_tx_avail;
1369 PMD_TX_LOG(DEBUG, "fp[%02d] avail=%u cons_sb=%u, "
1370 "pkt_head=%u pkt_tail=%u bd_head=%u bd_tail=%u",
1371 fp->index, tx_bd_avail, hw_cons,
1372 txq->tx_pkt_head, txq->tx_pkt_tail,
1373 txq->tx_bd_head, txq->tx_bd_tail);
1377 static void bnx2x_drain_tx_queues(struct bnx2x_softc *sc)
1379 struct bnx2x_fastpath *fp;
1382 /* wait until all TX fastpath tasks have completed */
1383 for (i = 0; i < sc->num_queues; i++) {
1388 while (bnx2x_has_tx_work(fp)) {
1389 bnx2x_txeof(sc, fp);
1393 "Timeout waiting for fp[%d] "
1394 "transmits to complete!", i);
1395 rte_panic("tx drain failure");
1409 bnx2x_del_all_macs(struct bnx2x_softc *sc, struct ecore_vlan_mac_obj *mac_obj,
1410 int mac_type, uint8_t wait_for_comp)
1412 uint32_t ramrod_flags = 0, vlan_mac_flags = 0;
1415 /* wait for completion of requested */
1416 if (wait_for_comp) {
1417 rte_bit_relaxed_set32(RAMROD_COMP_WAIT, &ramrod_flags);
1420 /* Set the mac type of addresses we want to clear */
1421 rte_bit_relaxed_set32(mac_type, &vlan_mac_flags);
1423 rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1425 PMD_DRV_LOG(ERR, sc, "Failed to delete MACs (%d)", rc);
1431 bnx2x_fill_accept_flags(struct bnx2x_softc *sc, uint32_t rx_mode,
1432 uint32_t *rx_accept_flags, uint32_t *tx_accept_flags)
1434 /* Clear the flags first */
1435 *rx_accept_flags = 0;
1436 *tx_accept_flags = 0;
1439 case BNX2X_RX_MODE_NONE:
1441 * 'drop all' supersedes any accept flags that may have been
1442 * passed to the function.
1446 case BNX2X_RX_MODE_NORMAL:
1447 rte_bit_relaxed_set32(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1448 rte_bit_relaxed_set32(ECORE_ACCEPT_MULTICAST, rx_accept_flags);
1449 rte_bit_relaxed_set32(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1451 /* internal switching mode */
1452 rte_bit_relaxed_set32(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1453 rte_bit_relaxed_set32(ECORE_ACCEPT_MULTICAST, tx_accept_flags);
1454 rte_bit_relaxed_set32(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1458 case BNX2X_RX_MODE_ALLMULTI:
1459 rte_bit_relaxed_set32(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1460 rte_bit_relaxed_set32(ECORE_ACCEPT_ALL_MULTICAST,
1462 rte_bit_relaxed_set32(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1464 /* internal switching mode */
1465 rte_bit_relaxed_set32(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1466 rte_bit_relaxed_set32(ECORE_ACCEPT_ALL_MULTICAST,
1468 rte_bit_relaxed_set32(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1472 case BNX2X_RX_MODE_ALLMULTI_PROMISC:
1473 case BNX2X_RX_MODE_PROMISC:
1475 * According to deffinition of SI mode, iface in promisc mode
1476 * should receive matched and unmatched (in resolution of port)
1479 rte_bit_relaxed_set32(ECORE_ACCEPT_UNMATCHED, rx_accept_flags);
1480 rte_bit_relaxed_set32(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1481 rte_bit_relaxed_set32(ECORE_ACCEPT_ALL_MULTICAST,
1483 rte_bit_relaxed_set32(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1485 /* internal switching mode */
1486 rte_bit_relaxed_set32(ECORE_ACCEPT_ALL_MULTICAST,
1488 rte_bit_relaxed_set32(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1491 rte_bit_relaxed_set32(ECORE_ACCEPT_ALL_UNICAST,
1494 rte_bit_relaxed_set32(ECORE_ACCEPT_UNICAST,
1501 PMD_RX_LOG(ERR, "Unknown rx_mode (%d)", rx_mode);
1505 /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
1506 if (rx_mode != BNX2X_RX_MODE_NONE) {
1507 rte_bit_relaxed_set32(ECORE_ACCEPT_ANY_VLAN, rx_accept_flags);
1508 rte_bit_relaxed_set32(ECORE_ACCEPT_ANY_VLAN, tx_accept_flags);
1515 bnx2x_set_q_rx_mode(struct bnx2x_softc *sc, uint8_t cl_id,
1516 unsigned long rx_mode_flags,
1517 unsigned long rx_accept_flags,
1518 unsigned long tx_accept_flags, unsigned long ramrod_flags)
1520 struct ecore_rx_mode_ramrod_params ramrod_param;
1523 memset(&ramrod_param, 0, sizeof(ramrod_param));
1525 /* Prepare ramrod parameters */
1526 ramrod_param.cid = 0;
1527 ramrod_param.cl_id = cl_id;
1528 ramrod_param.rx_mode_obj = &sc->rx_mode_obj;
1529 ramrod_param.func_id = SC_FUNC(sc);
1531 ramrod_param.pstate = &sc->sp_state;
1532 ramrod_param.state = ECORE_FILTER_RX_MODE_PENDING;
1534 ramrod_param.rdata = BNX2X_SP(sc, rx_mode_rdata);
1535 ramrod_param.rdata_mapping =
1536 (rte_iova_t)BNX2X_SP_MAPPING(sc, rx_mode_rdata),
1537 rte_bit_relaxed_set32(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
1539 ramrod_param.ramrod_flags = ramrod_flags;
1540 ramrod_param.rx_mode_flags = rx_mode_flags;
1542 ramrod_param.rx_accept_flags = rx_accept_flags;
1543 ramrod_param.tx_accept_flags = tx_accept_flags;
1545 rc = ecore_config_rx_mode(sc, &ramrod_param);
1547 PMD_RX_LOG(ERR, "Set rx_mode %d failed", sc->rx_mode);
1554 int bnx2x_set_storm_rx_mode(struct bnx2x_softc *sc)
1556 uint32_t rx_mode_flags = 0, ramrod_flags = 0;
1557 uint32_t rx_accept_flags = 0, tx_accept_flags = 0;
1560 rc = bnx2x_fill_accept_flags(sc, sc->rx_mode, &rx_accept_flags,
1566 rte_bit_relaxed_set32(RAMROD_RX, &ramrod_flags);
1567 rte_bit_relaxed_set32(RAMROD_TX, &ramrod_flags);
1568 rte_bit_relaxed_set32(RAMROD_COMP_WAIT, &ramrod_flags);
1570 return bnx2x_set_q_rx_mode(sc, sc->fp[0].cl_id, rx_mode_flags,
1571 rx_accept_flags, tx_accept_flags,
1575 /* returns the "mcp load_code" according to global load_count array */
1576 static int bnx2x_nic_load_no_mcp(struct bnx2x_softc *sc)
1578 int path = SC_PATH(sc);
1579 int port = SC_PORT(sc);
1581 PMD_DRV_LOG(INFO, sc, "NO MCP - load counts[%d] %d, %d, %d",
1582 path, load_count[path][0], load_count[path][1],
1583 load_count[path][2]);
1585 load_count[path][0]++;
1586 load_count[path][1 + port]++;
1587 PMD_DRV_LOG(INFO, sc, "NO MCP - new load counts[%d] %d, %d, %d",
1588 path, load_count[path][0], load_count[path][1],
1589 load_count[path][2]);
1590 if (load_count[path][0] == 1)
1591 return FW_MSG_CODE_DRV_LOAD_COMMON;
1592 else if (load_count[path][1 + port] == 1)
1593 return FW_MSG_CODE_DRV_LOAD_PORT;
1595 return FW_MSG_CODE_DRV_LOAD_FUNCTION;
1598 /* returns the "mcp load_code" according to global load_count array */
1599 static int bnx2x_nic_unload_no_mcp(struct bnx2x_softc *sc)
1601 int port = SC_PORT(sc);
1602 int path = SC_PATH(sc);
1604 PMD_DRV_LOG(INFO, sc, "NO MCP - load counts[%d] %d, %d, %d",
1605 path, load_count[path][0], load_count[path][1],
1606 load_count[path][2]);
1607 load_count[path][0]--;
1608 load_count[path][1 + port]--;
1609 PMD_DRV_LOG(INFO, sc, "NO MCP - new load counts[%d] %d, %d, %d",
1610 path, load_count[path][0], load_count[path][1],
1611 load_count[path][2]);
1612 if (load_count[path][0] == 0) {
1613 return FW_MSG_CODE_DRV_UNLOAD_COMMON;
1614 } else if (load_count[path][1 + port] == 0) {
1615 return FW_MSG_CODE_DRV_UNLOAD_PORT;
1617 return FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
1621 /* request unload mode from the MCP: COMMON, PORT or FUNCTION */
1622 static uint32_t bnx2x_send_unload_req(struct bnx2x_softc *sc, int unload_mode)
1624 uint32_t reset_code = 0;
1626 /* Select the UNLOAD request mode */
1627 if (unload_mode == UNLOAD_NORMAL) {
1628 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1630 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1633 /* Send the request to the MCP */
1634 if (!BNX2X_NOMCP(sc)) {
1635 reset_code = bnx2x_fw_command(sc, reset_code, 0);
1637 reset_code = bnx2x_nic_unload_no_mcp(sc);
1643 /* send UNLOAD_DONE command to the MCP */
1644 static void bnx2x_send_unload_done(struct bnx2x_softc *sc, uint8_t keep_link)
1646 uint32_t reset_param =
1647 keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
1649 /* Report UNLOAD_DONE to MCP */
1650 if (!BNX2X_NOMCP(sc)) {
1651 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
1655 static int bnx2x_func_wait_started(struct bnx2x_softc *sc)
1659 if (!sc->port.pmf) {
1664 * (assumption: No Attention from MCP at this stage)
1665 * PMF probably in the middle of TX disable/enable transaction
1666 * 1. Sync IRS for default SB
1667 * 2. Sync SP queue - this guarantees us that attention handling started
1668 * 3. Wait, that TX disable/enable transaction completes
1670 * 1+2 guarantee that if DCBX attention was scheduled it already changed
1671 * pending bit of transaction from STARTED-->TX_STOPPED, if we already
1672 * received completion for the transaction the state is TX_STOPPED.
1673 * State will return to STARTED after completion of TX_STOPPED-->STARTED
1677 while (ecore_func_get_state(sc, &sc->func_obj) !=
1678 ECORE_F_STATE_STARTED && tout--) {
1682 if (ecore_func_get_state(sc, &sc->func_obj) != ECORE_F_STATE_STARTED) {
1684 * Failed to complete the transaction in a "good way"
1685 * Force both transactions with CLR bit.
1687 struct ecore_func_state_params func_params = { NULL };
1689 PMD_DRV_LOG(NOTICE, sc, "Unexpected function state! "
1690 "Forcing STARTED-->TX_STOPPED-->STARTED");
1692 func_params.f_obj = &sc->func_obj;
1693 rte_bit_relaxed_set32(RAMROD_DRV_CLR_ONLY,
1694 &func_params.ramrod_flags);
1696 /* STARTED-->TX_STOPPED */
1697 func_params.cmd = ECORE_F_CMD_TX_STOP;
1698 ecore_func_state_change(sc, &func_params);
1700 /* TX_STOPPED-->STARTED */
1701 func_params.cmd = ECORE_F_CMD_TX_START;
1702 return ecore_func_state_change(sc, &func_params);
1708 static int bnx2x_stop_queue(struct bnx2x_softc *sc, int index)
1710 struct bnx2x_fastpath *fp = &sc->fp[index];
1711 struct ecore_queue_state_params q_params = { NULL };
1714 PMD_DRV_LOG(DEBUG, sc, "stopping queue %d cid %d", index, fp->index);
1716 q_params.q_obj = &sc->sp_objs[fp->index].q_obj;
1717 /* We want to wait for completion in this context */
1718 rte_bit_relaxed_set32(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
1720 /* Stop the primary connection: */
1722 /* ...halt the connection */
1723 q_params.cmd = ECORE_Q_CMD_HALT;
1724 rc = ecore_queue_state_change(sc, &q_params);
1729 /* ...terminate the connection */
1730 q_params.cmd = ECORE_Q_CMD_TERMINATE;
1731 memset(&q_params.params.terminate, 0,
1732 sizeof(q_params.params.terminate));
1733 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
1734 rc = ecore_queue_state_change(sc, &q_params);
1739 /* ...delete cfc entry */
1740 q_params.cmd = ECORE_Q_CMD_CFC_DEL;
1741 memset(&q_params.params.cfc_del, 0, sizeof(q_params.params.cfc_del));
1742 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
1743 return ecore_queue_state_change(sc, &q_params);
1746 /* wait for the outstanding SP commands */
1747 static uint8_t bnx2x_wait_sp_comp(struct bnx2x_softc *sc, uint32_t mask)
1750 int tout = 5000; /* wait for 5 secs tops */
1754 if (!(atomic_load_acq_int(&sc->sp_state) & mask))
1762 tmp = atomic_load_acq_int(&sc->sp_state);
1764 PMD_DRV_LOG(INFO, sc, "Filtering completion timed out: "
1765 "sp_state 0x%x, mask 0x%x", tmp, mask);
1772 static int bnx2x_func_stop(struct bnx2x_softc *sc)
1774 struct ecore_func_state_params func_params = { NULL };
1777 /* prepare parameters for function state transitions */
1778 rte_bit_relaxed_set32(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1779 func_params.f_obj = &sc->func_obj;
1780 func_params.cmd = ECORE_F_CMD_STOP;
1783 * Try to stop the function the 'good way'. If it fails (in case
1784 * of a parity error during bnx2x_chip_cleanup()) and we are
1785 * not in a debug mode, perform a state transaction in order to
1786 * enable further HW_RESET transaction.
1788 rc = ecore_func_state_change(sc, &func_params);
1790 PMD_DRV_LOG(NOTICE, sc, "FUNC_STOP ramrod failed. "
1791 "Running a dry transaction");
1792 rte_bit_relaxed_set32(RAMROD_DRV_CLR_ONLY,
1793 &func_params.ramrod_flags);
1794 return ecore_func_state_change(sc, &func_params);
1800 static int bnx2x_reset_hw(struct bnx2x_softc *sc, uint32_t load_code)
1802 struct ecore_func_state_params func_params = { NULL };
1804 /* Prepare parameters for function state transitions */
1805 rte_bit_relaxed_set32(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1807 func_params.f_obj = &sc->func_obj;
1808 func_params.cmd = ECORE_F_CMD_HW_RESET;
1810 func_params.params.hw_init.load_phase = load_code;
1812 return ecore_func_state_change(sc, &func_params);
1815 static void bnx2x_int_disable_sync(struct bnx2x_softc *sc, int disable_hw)
1818 /* prevent the HW from sending interrupts */
1819 bnx2x_int_disable(sc);
1824 bnx2x_chip_cleanup(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1826 int port = SC_PORT(sc);
1827 struct ecore_mcast_ramrod_params rparam = { NULL };
1828 uint32_t reset_code;
1831 bnx2x_drain_tx_queues(sc);
1833 /* give HW time to discard old tx messages */
1836 /* Clean all ETH MACs */
1837 rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_ETH_MAC,
1840 PMD_DRV_LOG(NOTICE, sc,
1841 "Failed to delete all ETH MACs (%d)", rc);
1844 /* Clean up UC list */
1845 rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_UC_LIST_MAC,
1848 PMD_DRV_LOG(NOTICE, sc,
1849 "Failed to delete UC MACs list (%d)", rc);
1853 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
1855 /* Set "drop all" to stop Rx */
1858 * We need to take the if_maddr_lock() here in order to prevent
1859 * a race between the completion code and this code.
1862 if (rte_bit_relaxed_get32(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state))
1863 rte_bit_relaxed_set32(ECORE_FILTER_RX_MODE_SCHED,
1866 bnx2x_set_storm_rx_mode(sc);
1868 /* Clean up multicast configuration */
1869 rparam.mcast_obj = &sc->mcast_obj;
1870 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1872 PMD_DRV_LOG(NOTICE, sc,
1873 "Failed to send DEL MCAST command (%d)", rc);
1877 * Send the UNLOAD_REQUEST to the MCP. This will return if
1878 * this function should perform FUNCTION, PORT, or COMMON HW
1881 reset_code = bnx2x_send_unload_req(sc, unload_mode);
1884 * (assumption: No Attention from MCP at this stage)
1885 * PMF probably in the middle of TX disable/enable transaction
1887 rc = bnx2x_func_wait_started(sc);
1889 PMD_DRV_LOG(NOTICE, sc, "bnx2x_func_wait_started failed");
1893 * Close multi and leading connections
1894 * Completions for ramrods are collected in a synchronous way
1896 for (i = 0; i < sc->num_queues; i++) {
1897 if (bnx2x_stop_queue(sc, i)) {
1903 * If SP settings didn't get completed so far - something
1904 * very wrong has happen.
1906 if (!bnx2x_wait_sp_comp(sc, ~0x0U))
1907 PMD_DRV_LOG(NOTICE, sc, "Common slow path ramrods got stuck!");
1911 rc = bnx2x_func_stop(sc);
1913 PMD_DRV_LOG(NOTICE, sc, "Function stop failed!");
1916 /* disable HW interrupts */
1917 bnx2x_int_disable_sync(sc, TRUE);
1919 /* Reset the chip */
1920 rc = bnx2x_reset_hw(sc, reset_code);
1922 PMD_DRV_LOG(NOTICE, sc, "Hardware reset failed");
1925 /* Report UNLOAD_DONE to MCP */
1926 bnx2x_send_unload_done(sc, keep_link);
1929 static void bnx2x_disable_close_the_gate(struct bnx2x_softc *sc)
1933 PMD_DRV_LOG(DEBUG, sc, "Disabling 'close the gates'");
1935 val = REG_RD(sc, MISC_REG_AEU_GENERAL_MASK);
1936 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
1937 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
1938 REG_WR(sc, MISC_REG_AEU_GENERAL_MASK, val);
1942 * Cleans the object that have internal lists without sending
1943 * ramrods. Should be run when interrutps are disabled.
1945 static void bnx2x_squeeze_objects(struct bnx2x_softc *sc)
1947 uint32_t ramrod_flags = 0, vlan_mac_flags = 0;
1948 struct ecore_mcast_ramrod_params rparam = { NULL };
1949 struct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj;
1952 /* Cleanup MACs' object first... */
1954 /* Wait for completion of requested */
1955 rte_bit_relaxed_set32(RAMROD_COMP_WAIT, &ramrod_flags);
1956 /* Perform a dry cleanup */
1957 rte_bit_relaxed_set32(RAMROD_DRV_CLR_ONLY, &ramrod_flags);
1959 /* Clean ETH primary MAC */
1960 rte_bit_relaxed_set32(ECORE_ETH_MAC, &vlan_mac_flags);
1961 rc = mac_obj->delete_all(sc, &sc->sp_objs->mac_obj, &vlan_mac_flags,
1964 PMD_DRV_LOG(NOTICE, sc, "Failed to clean ETH MACs (%d)", rc);
1967 /* Cleanup UC list */
1969 rte_bit_relaxed_set32(ECORE_UC_LIST_MAC, &vlan_mac_flags);
1970 rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1972 PMD_DRV_LOG(NOTICE, sc,
1973 "Failed to clean UC list MACs (%d)", rc);
1976 /* Now clean mcast object... */
1978 rparam.mcast_obj = &sc->mcast_obj;
1979 rte_bit_relaxed_set32(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags);
1981 /* Add a DEL command... */
1982 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1984 PMD_DRV_LOG(NOTICE, sc,
1985 "Failed to send DEL MCAST command (%d)", rc);
1988 /* now wait until all pending commands are cleared */
1990 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
1993 PMD_DRV_LOG(NOTICE, sc,
1994 "Failed to clean MCAST object (%d)", rc);
1998 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
2002 /* stop the controller */
2005 bnx2x_nic_unload(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
2007 uint8_t global = FALSE;
2010 PMD_INIT_FUNC_TRACE(sc);
2012 PMD_DRV_LOG(DEBUG, sc, "Starting NIC unload...");
2014 /* mark driver as unloaded in shmem2 */
2015 if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
2016 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
2017 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
2018 val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
2021 if (IS_PF(sc) && sc->recovery_state != BNX2X_RECOVERY_DONE &&
2022 (sc->state == BNX2X_STATE_CLOSED || sc->state == BNX2X_STATE_ERROR)) {
2024 * We can get here if the driver has been unloaded
2025 * during parity error recovery and is either waiting for a
2026 * leader to complete or for other functions to unload and
2027 * then ifconfig down has been issued. In this case we want to
2028 * unload and let other functions to complete a recovery
2031 sc->recovery_state = BNX2X_RECOVERY_DONE;
2033 bnx2x_release_leader_lock(sc);
2036 PMD_DRV_LOG(NOTICE, sc, "Can't unload in closed or error state");
2041 * Nothing to do during unload if previous bnx2x_nic_load()
2042 * did not completed successfully - all resourses are released.
2044 if ((sc->state == BNX2X_STATE_CLOSED) || (sc->state == BNX2X_STATE_ERROR)) {
2048 sc->state = BNX2X_STATE_CLOSING_WAITING_HALT;
2051 sc->rx_mode = BNX2X_RX_MODE_NONE;
2052 bnx2x_set_rx_mode(sc);
2056 /* set ALWAYS_ALIVE bit in shmem */
2057 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2059 bnx2x_drv_pulse(sc);
2061 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2062 bnx2x_save_statistics(sc);
2065 /* wait till consumers catch up with producers in all queues */
2066 bnx2x_drain_tx_queues(sc);
2068 /* if VF indicate to PF this function is going down (PF will delete sp
2069 * elements and clear initializations
2072 bnx2x_vf_unload(sc);
2073 } else if (unload_mode != UNLOAD_RECOVERY) {
2074 /* if this is a normal/close unload need to clean up chip */
2075 bnx2x_chip_cleanup(sc, unload_mode, keep_link);
2077 /* Send the UNLOAD_REQUEST to the MCP */
2078 bnx2x_send_unload_req(sc, unload_mode);
2081 * Prevent transactions to host from the functions on the
2082 * engine that doesn't reset global blocks in case of global
2083 * attention once gloabl blocks are reset and gates are opened
2084 * (the engine which leader will perform the recovery
2087 if (!CHIP_IS_E1x(sc)) {
2088 bnx2x_pf_disable(sc);
2091 /* disable HW interrupts */
2092 bnx2x_int_disable_sync(sc, TRUE);
2094 /* Report UNLOAD_DONE to MCP */
2095 bnx2x_send_unload_done(sc, FALSE);
2099 * At this stage no more interrupts will arrive so we may safely clean
2100 * the queue'able objects here in case they failed to get cleaned so far.
2103 bnx2x_squeeze_objects(sc);
2106 /* There should be no more pending SP commands at this stage */
2115 /* free the host hardware/software hsi structures */
2116 bnx2x_free_hsi_mem(sc);
2118 bnx2x_free_fw_stats_mem(sc);
2120 sc->state = BNX2X_STATE_CLOSED;
2123 * Check if there are pending parity attentions. If there are - set
2124 * RECOVERY_IN_PROGRESS.
2126 if (IS_PF(sc) && bnx2x_chk_parity_attn(sc, &global, FALSE)) {
2127 bnx2x_set_reset_in_progress(sc);
2129 /* Set RESET_IS_GLOBAL if needed */
2131 bnx2x_set_reset_global(sc);
2136 * The last driver must disable a "close the gate" if there is no
2137 * parity attention or "process kill" pending.
2139 if (IS_PF(sc) && !bnx2x_clear_pf_load(sc) &&
2140 bnx2x_reset_is_done(sc, SC_PATH(sc))) {
2141 bnx2x_disable_close_the_gate(sc);
2144 PMD_DRV_LOG(DEBUG, sc, "Ended NIC unload");
2150 * Encapsulte an mbuf cluster into the tx bd chain and makes the memory
2151 * visible to the controller.
2153 * If an mbuf is submitted to this routine and cannot be given to the
2154 * controller (e.g. it has too many fragments) then the function may free
2155 * the mbuf and return to the caller.
2158 * int: Number of TX BDs used for the mbuf
2160 * Note the side effect that an mbuf may be freed if it causes a problem.
2162 int bnx2x_tx_encap(struct bnx2x_tx_queue *txq, struct rte_mbuf *m0)
2164 struct eth_tx_start_bd *tx_start_bd;
2165 uint16_t bd_prod, pkt_prod;
2166 struct bnx2x_softc *sc;
2170 bd_prod = txq->tx_bd_tail;
2171 pkt_prod = txq->tx_pkt_tail;
2173 txq->sw_ring[TX_BD(pkt_prod, txq)] = m0;
2175 tx_start_bd = &txq->tx_ring[TX_BD(bd_prod, txq)].start_bd;
2177 tx_start_bd->addr_lo =
2178 rte_cpu_to_le_32(U64_LO(rte_mbuf_data_iova(m0)));
2179 tx_start_bd->addr_hi =
2180 rte_cpu_to_le_32(U64_HI(rte_mbuf_data_iova(m0)));
2181 tx_start_bd->nbytes = rte_cpu_to_le_16(m0->data_len);
2182 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2183 tx_start_bd->general_data =
2184 (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
2186 tx_start_bd->nbd = rte_cpu_to_le_16(2);
2188 if (m0->ol_flags & PKT_TX_VLAN_PKT) {
2189 tx_start_bd->vlan_or_ethertype =
2190 rte_cpu_to_le_16(m0->vlan_tci);
2191 tx_start_bd->bd_flags.as_bitfield |=
2192 (X_ETH_OUTBAND_VLAN <<
2193 ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT);
2196 tx_start_bd->vlan_or_ethertype =
2197 rte_cpu_to_le_16(pkt_prod);
2199 /* when transmitting in a vf, start bd
2200 * must hold the ethertype for fw to enforce it
2202 struct rte_ether_hdr *eh =
2203 rte_pktmbuf_mtod(m0, struct rte_ether_hdr *);
2205 /* Still need to consider inband vlan for enforced */
2206 if (eh->ether_type ==
2207 rte_cpu_to_be_16(RTE_ETHER_TYPE_VLAN)) {
2208 struct rte_vlan_hdr *vh =
2209 (struct rte_vlan_hdr *)(eh + 1);
2210 tx_start_bd->bd_flags.as_bitfield |=
2211 (X_ETH_INBAND_VLAN <<
2212 ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT);
2213 tx_start_bd->vlan_or_ethertype =
2214 rte_cpu_to_le_16(ntohs(vh->vlan_tci));
2216 tx_start_bd->vlan_or_ethertype =
2218 (rte_be_to_cpu_16(eh->ether_type)));
2223 bd_prod = NEXT_TX_BD(bd_prod);
2225 struct eth_tx_parse_bd_e2 *tx_parse_bd;
2226 const struct rte_ether_hdr *eh =
2227 rte_pktmbuf_mtod(m0, struct rte_ether_hdr *);
2228 uint8_t mac_type = UNICAST_ADDRESS;
2231 &txq->tx_ring[TX_BD(bd_prod, txq)].parse_bd_e2;
2232 if (rte_is_multicast_ether_addr(&eh->d_addr)) {
2233 if (rte_is_broadcast_ether_addr(&eh->d_addr))
2234 mac_type = BROADCAST_ADDRESS;
2236 mac_type = MULTICAST_ADDRESS;
2238 tx_parse_bd->parsing_data =
2239 (mac_type << ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT);
2241 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_hi,
2242 &eh->d_addr.addr_bytes[0], 2);
2243 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_mid,
2244 &eh->d_addr.addr_bytes[2], 2);
2245 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_lo,
2246 &eh->d_addr.addr_bytes[4], 2);
2247 rte_memcpy(&tx_parse_bd->data.mac_addr.src_hi,
2248 &eh->s_addr.addr_bytes[0], 2);
2249 rte_memcpy(&tx_parse_bd->data.mac_addr.src_mid,
2250 &eh->s_addr.addr_bytes[2], 2);
2251 rte_memcpy(&tx_parse_bd->data.mac_addr.src_lo,
2252 &eh->s_addr.addr_bytes[4], 2);
2254 tx_parse_bd->data.mac_addr.dst_hi =
2255 rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_hi);
2256 tx_parse_bd->data.mac_addr.dst_mid =
2257 rte_cpu_to_be_16(tx_parse_bd->data.
2259 tx_parse_bd->data.mac_addr.dst_lo =
2260 rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_lo);
2261 tx_parse_bd->data.mac_addr.src_hi =
2262 rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_hi);
2263 tx_parse_bd->data.mac_addr.src_mid =
2264 rte_cpu_to_be_16(tx_parse_bd->data.
2266 tx_parse_bd->data.mac_addr.src_lo =
2267 rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_lo);
2270 "PBD dst %x %x %x src %x %x %x p_data %x",
2271 tx_parse_bd->data.mac_addr.dst_hi,
2272 tx_parse_bd->data.mac_addr.dst_mid,
2273 tx_parse_bd->data.mac_addr.dst_lo,
2274 tx_parse_bd->data.mac_addr.src_hi,
2275 tx_parse_bd->data.mac_addr.src_mid,
2276 tx_parse_bd->data.mac_addr.src_lo,
2277 tx_parse_bd->parsing_data);
2281 "start bd: nbytes %d flags %x vlan %x",
2282 tx_start_bd->nbytes,
2283 tx_start_bd->bd_flags.as_bitfield,
2284 tx_start_bd->vlan_or_ethertype);
2286 bd_prod = NEXT_TX_BD(bd_prod);
2289 if (TX_IDX(bd_prod) < 2)
2292 txq->nb_tx_avail -= 2;
2293 txq->tx_bd_tail = bd_prod;
2294 txq->tx_pkt_tail = pkt_prod;
2299 static uint16_t bnx2x_cid_ilt_lines(struct bnx2x_softc *sc)
2301 return L2_ILT_LINES(sc);
2304 static void bnx2x_ilt_set_info(struct bnx2x_softc *sc)
2306 struct ilt_client_info *ilt_client;
2307 struct ecore_ilt *ilt = sc->ilt;
2310 PMD_INIT_FUNC_TRACE(sc);
2312 ilt->start_line = FUNC_ILT_BASE(SC_FUNC(sc));
2315 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
2316 ilt_client->client_num = ILT_CLIENT_CDU;
2317 ilt_client->page_size = CDU_ILT_PAGE_SZ;
2318 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
2319 ilt_client->start = line;
2320 line += bnx2x_cid_ilt_lines(sc);
2322 if (CNIC_SUPPORT(sc)) {
2323 line += CNIC_ILT_LINES;
2326 ilt_client->end = (line - 1);
2329 if (QM_INIT(sc->qm_cid_count)) {
2330 ilt_client = &ilt->clients[ILT_CLIENT_QM];
2331 ilt_client->client_num = ILT_CLIENT_QM;
2332 ilt_client->page_size = QM_ILT_PAGE_SZ;
2333 ilt_client->flags = 0;
2334 ilt_client->start = line;
2336 /* 4 bytes for each cid */
2337 line += DIV_ROUND_UP(sc->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
2340 ilt_client->end = (line - 1);
2343 if (CNIC_SUPPORT(sc)) {
2345 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
2346 ilt_client->client_num = ILT_CLIENT_SRC;
2347 ilt_client->page_size = SRC_ILT_PAGE_SZ;
2348 ilt_client->flags = 0;
2349 ilt_client->start = line;
2350 line += SRC_ILT_LINES;
2351 ilt_client->end = (line - 1);
2354 ilt_client = &ilt->clients[ILT_CLIENT_TM];
2355 ilt_client->client_num = ILT_CLIENT_TM;
2356 ilt_client->page_size = TM_ILT_PAGE_SZ;
2357 ilt_client->flags = 0;
2358 ilt_client->start = line;
2359 line += TM_ILT_LINES;
2360 ilt_client->end = (line - 1);
2363 assert((line <= ILT_MAX_LINES));
2366 static void bnx2x_set_fp_rx_buf_size(struct bnx2x_softc *sc)
2370 for (i = 0; i < sc->num_queues; i++) {
2371 /* get the Rx buffer size for RX frames */
2372 sc->fp[i].rx_buf_size =
2373 (IP_HEADER_ALIGNMENT_PADDING + ETH_OVERHEAD + sc->mtu);
2377 int bnx2x_alloc_ilt_mem(struct bnx2x_softc *sc)
2380 sc->ilt = rte_malloc("", sizeof(struct ecore_ilt), RTE_CACHE_LINE_SIZE);
2382 return sc->ilt == NULL;
2385 static int bnx2x_alloc_ilt_lines_mem(struct bnx2x_softc *sc)
2387 sc->ilt->lines = rte_calloc("",
2388 sizeof(struct ilt_line), ILT_MAX_LINES,
2389 RTE_CACHE_LINE_SIZE);
2390 return sc->ilt->lines == NULL;
2393 void bnx2x_free_ilt_mem(struct bnx2x_softc *sc)
2399 static void bnx2x_free_ilt_lines_mem(struct bnx2x_softc *sc)
2401 if (sc->ilt->lines != NULL) {
2402 rte_free(sc->ilt->lines);
2403 sc->ilt->lines = NULL;
2407 static void bnx2x_free_mem(struct bnx2x_softc *sc)
2411 for (i = 0; i < L2_ILT_LINES(sc); i++) {
2412 sc->context[i].vcxt = NULL;
2413 sc->context[i].size = 0;
2416 ecore_ilt_mem_op(sc, ILT_MEMOP_FREE);
2418 bnx2x_free_ilt_lines_mem(sc);
2421 static int bnx2x_alloc_mem(struct bnx2x_softc *sc)
2426 char cdu_name[RTE_MEMZONE_NAMESIZE];
2429 * Allocate memory for CDU context:
2430 * This memory is allocated separately and not in the generic ILT
2431 * functions because CDU differs in few aspects:
2432 * 1. There can be multiple entities allocating memory for context -
2433 * regular L2, CNIC, and SRIOV drivers. Each separately controls
2434 * its own ILT lines.
2435 * 2. Since CDU page-size is not a single 4KB page (which is the case
2436 * for the other ILT clients), to be efficient we want to support
2437 * allocation of sub-page-size in the last entry.
2438 * 3. Context pointers are used by the driver to pass to FW / update
2439 * the context (for the other ILT clients the pointers are used just to
2440 * free the memory during unload).
2442 context_size = (sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(sc));
2443 for (i = 0, allocated = 0; allocated < context_size; i++) {
2444 sc->context[i].size = min(CDU_ILT_PAGE_SZ,
2445 (context_size - allocated));
2447 snprintf(cdu_name, sizeof(cdu_name), "cdu_%d", i);
2448 if (bnx2x_dma_alloc(sc, sc->context[i].size,
2449 &sc->context[i].vcxt_dma,
2450 cdu_name, BNX2X_PAGE_SIZE) != 0) {
2455 sc->context[i].vcxt =
2456 (union cdu_context *)sc->context[i].vcxt_dma.vaddr;
2458 allocated += sc->context[i].size;
2461 bnx2x_alloc_ilt_lines_mem(sc);
2463 if (ecore_ilt_mem_op(sc, ILT_MEMOP_ALLOC)) {
2464 PMD_DRV_LOG(NOTICE, sc, "ecore_ilt_mem_op ILT_MEMOP_ALLOC failed");
2472 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc)
2474 bnx2x_dma_free(&sc->fw_stats_dma);
2475 sc->fw_stats_num = 0;
2477 sc->fw_stats_req_size = 0;
2478 sc->fw_stats_req = NULL;
2479 sc->fw_stats_req_mapping = 0;
2481 sc->fw_stats_data_size = 0;
2482 sc->fw_stats_data = NULL;
2483 sc->fw_stats_data_mapping = 0;
2486 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc)
2488 uint8_t num_queue_stats;
2489 int num_groups, vf_headroom = 0;
2491 /* number of queues for statistics is number of eth queues */
2492 num_queue_stats = BNX2X_NUM_ETH_QUEUES(sc);
2495 * Total number of FW statistics requests =
2496 * 1 for port stats + 1 for PF stats + num of queues
2498 sc->fw_stats_num = (2 + num_queue_stats);
2501 * Request is built from stats_query_header and an array of
2502 * stats_query_cmd_group each of which contains STATS_QUERY_CMD_COUNT
2503 * rules. The real number or requests is configured in the
2504 * stats_query_header.
2506 num_groups = (sc->fw_stats_num + vf_headroom) / STATS_QUERY_CMD_COUNT;
2507 if ((sc->fw_stats_num + vf_headroom) % STATS_QUERY_CMD_COUNT)
2510 sc->fw_stats_req_size =
2511 (sizeof(struct stats_query_header) +
2512 (num_groups * sizeof(struct stats_query_cmd_group)));
2515 * Data for statistics requests + stats_counter.
2516 * stats_counter holds per-STORM counters that are incremented when
2517 * STORM has finished with the current request. Memory for FCoE
2518 * offloaded statistics are counted anyway, even if they will not be sent.
2519 * VF stats are not accounted for here as the data of VF stats is stored
2520 * in memory allocated by the VF, not here.
2522 sc->fw_stats_data_size =
2523 (sizeof(struct stats_counter) +
2524 sizeof(struct per_port_stats) + sizeof(struct per_pf_stats) +
2525 /* sizeof(struct fcoe_statistics_params) + */
2526 (sizeof(struct per_queue_stats) * num_queue_stats));
2528 if (bnx2x_dma_alloc(sc, (sc->fw_stats_req_size + sc->fw_stats_data_size),
2529 &sc->fw_stats_dma, "fw_stats",
2530 RTE_CACHE_LINE_SIZE) != 0) {
2531 bnx2x_free_fw_stats_mem(sc);
2535 /* set up the shortcuts */
2537 sc->fw_stats_req = (struct bnx2x_fw_stats_req *)sc->fw_stats_dma.vaddr;
2538 sc->fw_stats_req_mapping = sc->fw_stats_dma.paddr;
2541 (struct bnx2x_fw_stats_data *)((uint8_t *) sc->fw_stats_dma.vaddr +
2542 sc->fw_stats_req_size);
2543 sc->fw_stats_data_mapping = (sc->fw_stats_dma.paddr +
2544 sc->fw_stats_req_size);
2551 * 0-7 - Engine0 load counter.
2552 * 8-15 - Engine1 load counter.
2553 * 16 - Engine0 RESET_IN_PROGRESS bit.
2554 * 17 - Engine1 RESET_IN_PROGRESS bit.
2555 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active
2556 * function on the engine
2557 * 19 - Engine1 ONE_IS_LOADED.
2558 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
2559 * leader to complete (check for both RESET_IN_PROGRESS bits and not
2560 * for just the one belonging to its engine).
2562 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
2563 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
2564 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
2565 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
2566 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
2567 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
2568 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
2569 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
2571 /* set the GLOBAL_RESET bit, should be run under rtnl lock */
2572 static void bnx2x_set_reset_global(struct bnx2x_softc *sc)
2575 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2576 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2577 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
2578 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2581 /* clear the GLOBAL_RESET bit, should be run under rtnl lock */
2582 static void bnx2x_clear_reset_global(struct bnx2x_softc *sc)
2585 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2586 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2587 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
2588 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2591 /* checks the GLOBAL_RESET bit, should be run under rtnl lock */
2592 static uint8_t bnx2x_reset_is_global(struct bnx2x_softc *sc)
2594 return REG_RD(sc, BNX2X_RECOVERY_GLOB_REG) & BNX2X_GLOBAL_RESET_BIT;
2597 /* clear RESET_IN_PROGRESS bit for the engine, should be run under rtnl lock */
2598 static void bnx2x_set_reset_done(struct bnx2x_softc *sc)
2601 uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2602 BNX2X_PATH0_RST_IN_PROG_BIT;
2604 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2606 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2609 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2611 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2614 /* set RESET_IN_PROGRESS for the engine, should be run under rtnl lock */
2615 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc)
2618 uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2619 BNX2X_PATH0_RST_IN_PROG_BIT;
2621 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2623 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2626 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2628 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2631 /* check RESET_IN_PROGRESS bit for an engine, should be run under rtnl lock */
2632 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine)
2634 uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2635 uint32_t bit = engine ? BNX2X_PATH1_RST_IN_PROG_BIT :
2636 BNX2X_PATH0_RST_IN_PROG_BIT;
2638 /* return false if bit is set */
2639 return (val & bit) ? FALSE : TRUE;
2642 /* get the load status for an engine, should be run under rtnl lock */
2643 static uint8_t bnx2x_get_load_status(struct bnx2x_softc *sc, int engine)
2645 uint32_t mask = engine ? BNX2X_PATH1_LOAD_CNT_MASK :
2646 BNX2X_PATH0_LOAD_CNT_MASK;
2647 uint32_t shift = engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2648 BNX2X_PATH0_LOAD_CNT_SHIFT;
2649 uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2651 val = ((val & mask) >> shift);
2656 /* set pf load mark */
2657 static void bnx2x_set_pf_load(struct bnx2x_softc *sc)
2661 uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2662 BNX2X_PATH0_LOAD_CNT_MASK;
2663 uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2664 BNX2X_PATH0_LOAD_CNT_SHIFT;
2666 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2668 PMD_INIT_FUNC_TRACE(sc);
2670 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2672 /* get the current counter value */
2673 val1 = ((val & mask) >> shift);
2675 /* set bit of this PF */
2676 val1 |= (1 << SC_ABS_FUNC(sc));
2678 /* clear the old value */
2681 /* set the new one */
2682 val |= ((val1 << shift) & mask);
2684 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2686 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2689 /* clear pf load mark */
2690 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc)
2693 uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2694 BNX2X_PATH0_LOAD_CNT_MASK;
2695 uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2696 BNX2X_PATH0_LOAD_CNT_SHIFT;
2698 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2699 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2701 /* get the current counter value */
2702 val1 = (val & mask) >> shift;
2704 /* clear bit of that PF */
2705 val1 &= ~(1 << SC_ABS_FUNC(sc));
2707 /* clear the old value */
2710 /* set the new one */
2711 val |= ((val1 << shift) & mask);
2713 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2714 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2718 /* send load requrest to mcp and analyze response */
2719 static int bnx2x_nic_load_request(struct bnx2x_softc *sc, uint32_t * load_code)
2721 PMD_INIT_FUNC_TRACE(sc);
2725 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
2726 DRV_MSG_SEQ_NUMBER_MASK);
2728 PMD_DRV_LOG(DEBUG, sc, "initial fw_seq 0x%04x", sc->fw_seq);
2731 /* get the current FW pulse sequence */
2732 sc->fw_drv_pulse_wr_seq =
2733 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb) &
2734 DRV_PULSE_SEQ_MASK);
2736 /* set ALWAYS_ALIVE bit in shmem */
2737 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2738 bnx2x_drv_pulse(sc);
2742 (*load_code) = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
2743 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
2745 /* if the MCP fails to respond we must abort */
2746 if (!(*load_code)) {
2747 PMD_DRV_LOG(NOTICE, sc, "MCP response failure!");
2751 /* if MCP refused then must abort */
2752 if ((*load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED) {
2753 PMD_DRV_LOG(NOTICE, sc, "MCP refused load request");
2761 * Check whether another PF has already loaded FW to chip. In virtualized
2762 * environments a pf from anoth VM may have already initialized the device
2763 * including loading FW.
2765 static int bnx2x_nic_load_analyze_req(struct bnx2x_softc *sc, uint32_t load_code)
2767 uint32_t my_fw, loaded_fw;
2769 /* is another pf loaded on this engine? */
2770 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
2771 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
2772 /* build my FW version dword */
2773 my_fw = (BNX2X_5710_FW_MAJOR_VERSION +
2774 (BNX2X_5710_FW_MINOR_VERSION << 8) +
2775 (BNX2X_5710_FW_REVISION_VERSION << 16) +
2776 (BNX2X_5710_FW_ENGINEERING_VERSION << 24));
2778 /* read loaded FW from chip */
2779 loaded_fw = REG_RD(sc, XSEM_REG_PRAM);
2780 PMD_DRV_LOG(DEBUG, sc, "loaded FW 0x%08x / my FW 0x%08x",
2783 /* abort nic load if version mismatch */
2784 if (my_fw != loaded_fw) {
2785 PMD_DRV_LOG(NOTICE, sc,
2786 "FW 0x%08x already loaded (mine is 0x%08x)",
2795 /* mark PMF if applicable */
2796 static void bnx2x_nic_load_pmf(struct bnx2x_softc *sc, uint32_t load_code)
2798 uint32_t ncsi_oem_data_addr;
2800 PMD_INIT_FUNC_TRACE(sc);
2802 if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
2803 (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
2804 (load_code == FW_MSG_CODE_DRV_LOAD_PORT)) {
2806 * Barrier here for ordering between the writing to sc->port.pmf here
2807 * and reading it from the periodic task.
2815 PMD_DRV_LOG(DEBUG, sc, "pmf %d", sc->port.pmf);
2817 if (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) {
2818 if (SHMEM2_HAS(sc, ncsi_oem_data_addr)) {
2819 ncsi_oem_data_addr = SHMEM2_RD(sc, ncsi_oem_data_addr);
2820 if (ncsi_oem_data_addr) {
2822 (ncsi_oem_data_addr +
2823 offsetof(struct glob_ncsi_oem_data,
2824 driver_version)), 0);
2830 static void bnx2x_read_mf_cfg(struct bnx2x_softc *sc)
2832 int n = (CHIP_IS_MODE_4_PORT(sc) ? 2 : 1);
2836 if (BNX2X_NOMCP(sc)) {
2837 return; /* what should be the default bvalue in this case */
2841 * The formula for computing the absolute function number is...
2842 * For 2 port configuration (4 functions per port):
2843 * abs_func = 2 * vn + SC_PORT + SC_PATH
2844 * For 4 port configuration (2 functions per port):
2845 * abs_func = 4 * vn + 2 * SC_PORT + SC_PATH
2847 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
2848 abs_func = (n * (2 * vn + SC_PORT(sc)) + SC_PATH(sc));
2849 if (abs_func >= E1H_FUNC_MAX) {
2852 sc->devinfo.mf_info.mf_config[vn] =
2853 MFCFG_RD(sc, func_mf_config[abs_func].config);
2856 if (sc->devinfo.mf_info.mf_config[SC_VN(sc)] &
2857 FUNC_MF_CFG_FUNC_DISABLED) {
2858 PMD_DRV_LOG(DEBUG, sc, "mf_cfg function disabled");
2859 sc->flags |= BNX2X_MF_FUNC_DIS;
2861 PMD_DRV_LOG(DEBUG, sc, "mf_cfg function enabled");
2862 sc->flags &= ~BNX2X_MF_FUNC_DIS;
2866 /* acquire split MCP access lock register */
2867 static int bnx2x_acquire_alr(struct bnx2x_softc *sc)
2871 for (j = 0; j < 1000; j++) {
2873 REG_WR(sc, GRCBASE_MCP + 0x9c, val);
2874 val = REG_RD(sc, GRCBASE_MCP + 0x9c);
2875 if (val & (1L << 31))
2881 if (!(val & (1L << 31))) {
2882 PMD_DRV_LOG(NOTICE, sc, "Cannot acquire MCP access lock register");
2889 /* release split MCP access lock register */
2890 static void bnx2x_release_alr(struct bnx2x_softc *sc)
2892 REG_WR(sc, GRCBASE_MCP + 0x9c, 0);
2895 static void bnx2x_fan_failure(struct bnx2x_softc *sc)
2897 int port = SC_PORT(sc);
2898 uint32_t ext_phy_config;
2900 /* mark the failure */
2902 SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
2904 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2905 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
2906 SHMEM_WR(sc, dev_info.port_hw_config[port].external_phy_config,
2909 /* log the failure */
2910 PMD_DRV_LOG(INFO, sc,
2911 "Fan Failure has caused the driver to shutdown "
2912 "the card to prevent permanent damage. "
2913 "Please contact OEM Support for assistance");
2915 rte_panic("Schedule task to handle fan failure");
2918 /* this function is called upon a link interrupt */
2919 static void bnx2x_link_attn(struct bnx2x_softc *sc)
2921 uint32_t pause_enabled = 0;
2922 struct host_port_stats *pstats;
2925 /* Make sure that we are synced with the current statistics */
2926 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2928 elink_link_update(&sc->link_params, &sc->link_vars);
2930 if (sc->link_vars.link_up) {
2932 /* dropless flow control */
2933 if (sc->dropless_fc) {
2936 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
2941 (BAR_USTRORM_INTMEM +
2942 USTORM_ETH_PAUSE_ENABLED_OFFSET(SC_PORT(sc))),
2946 if (sc->link_vars.mac_type != ELINK_MAC_TYPE_EMAC) {
2947 pstats = BNX2X_SP(sc, port_stats);
2948 /* reset old mac stats */
2949 memset(&(pstats->mac_stx[0]), 0,
2950 sizeof(struct mac_stx));
2953 if (sc->state == BNX2X_STATE_OPEN) {
2954 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
2958 if (sc->link_vars.link_up && sc->link_vars.line_speed) {
2959 cmng_fns = bnx2x_get_cmng_fns_mode(sc);
2961 if (cmng_fns != CMNG_FNS_NONE) {
2962 bnx2x_cmng_fns_init(sc, FALSE, cmng_fns);
2963 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
2967 bnx2x_link_report_locked(sc);
2970 bnx2x_link_sync_notify(sc);
2974 static void bnx2x_attn_int_asserted(struct bnx2x_softc *sc, uint32_t asserted)
2976 int port = SC_PORT(sc);
2977 uint32_t aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2978 MISC_REG_AEU_MASK_ATTN_FUNC_0;
2979 uint32_t nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2980 NIG_REG_MASK_INTERRUPT_PORT0;
2982 uint32_t nig_mask = 0;
2987 if (sc->attn_state & asserted) {
2988 PMD_DRV_LOG(ERR, sc, "IGU ERROR attn=0x%08x", asserted);
2991 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2993 aeu_mask = REG_RD(sc, aeu_addr);
2995 aeu_mask &= ~(asserted & 0x3ff);
2997 REG_WR(sc, aeu_addr, aeu_mask);
2999 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3001 sc->attn_state |= asserted;
3003 if (asserted & ATTN_HARD_WIRED_MASK) {
3004 if (asserted & ATTN_NIG_FOR_FUNC) {
3006 bnx2x_acquire_phy_lock(sc);
3007 /* save nig interrupt mask */
3008 nig_mask = REG_RD(sc, nig_int_mask_addr);
3010 /* If nig_mask is not set, no need to call the update function */
3012 REG_WR(sc, nig_int_mask_addr, 0);
3014 bnx2x_link_attn(sc);
3017 /* handle unicore attn? */
3020 if (asserted & ATTN_SW_TIMER_4_FUNC) {
3021 PMD_DRV_LOG(DEBUG, sc, "ATTN_SW_TIMER_4_FUNC!");
3024 if (asserted & GPIO_2_FUNC) {
3025 PMD_DRV_LOG(DEBUG, sc, "GPIO_2_FUNC!");
3028 if (asserted & GPIO_3_FUNC) {
3029 PMD_DRV_LOG(DEBUG, sc, "GPIO_3_FUNC!");
3032 if (asserted & GPIO_4_FUNC) {
3033 PMD_DRV_LOG(DEBUG, sc, "GPIO_4_FUNC!");
3037 if (asserted & ATTN_GENERAL_ATTN_1) {
3038 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_1!");
3039 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3041 if (asserted & ATTN_GENERAL_ATTN_2) {
3042 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_2!");
3043 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3045 if (asserted & ATTN_GENERAL_ATTN_3) {
3046 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_3!");
3047 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3050 if (asserted & ATTN_GENERAL_ATTN_4) {
3051 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_4!");
3052 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3054 if (asserted & ATTN_GENERAL_ATTN_5) {
3055 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_5!");
3056 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3058 if (asserted & ATTN_GENERAL_ATTN_6) {
3059 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_6!");
3060 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3065 if (sc->devinfo.int_block == INT_BLOCK_HC) {
3067 (HC_REG_COMMAND_REG + port * 32 +
3068 COMMAND_REG_ATTN_BITS_SET);
3070 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER * 8);
3073 PMD_DRV_LOG(DEBUG, sc, "about to mask 0x%08x at %s addr 0x%08x",
3075 (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
3077 REG_WR(sc, reg_addr, asserted);
3079 /* now set back the mask */
3080 if (asserted & ATTN_NIG_FOR_FUNC) {
3082 * Verify that IGU ack through BAR was written before restoring
3083 * NIG mask. This loop should exit after 2-3 iterations max.
3085 if (sc->devinfo.int_block != INT_BLOCK_HC) {
3090 REG_RD(sc, IGU_REG_ATTENTION_ACK_BITS);
3091 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0)
3092 && (++cnt < MAX_IGU_ATTN_ACK_TO));
3095 PMD_DRV_LOG(ERR, sc,
3096 "Failed to verify IGU ack on time");
3102 REG_WR(sc, nig_int_mask_addr, nig_mask);
3104 bnx2x_release_phy_lock(sc);
3109 bnx2x_print_next_block(__rte_unused struct bnx2x_softc *sc, __rte_unused int idx,
3110 __rte_unused const char *blk)
3112 PMD_DRV_LOG(INFO, sc, "%s%s", idx ? ", " : "", blk);
3116 bnx2x_check_blocks_with_parity0(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3119 uint32_t cur_bit = 0;
3122 for (i = 0; sig; i++) {
3123 cur_bit = ((uint32_t) 0x1 << i);
3124 if (sig & cur_bit) {
3126 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3128 bnx2x_print_next_block(sc, par_num++,
3131 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3133 bnx2x_print_next_block(sc, par_num++,
3136 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3138 bnx2x_print_next_block(sc, par_num++,
3141 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3143 bnx2x_print_next_block(sc, par_num++,
3146 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3148 bnx2x_print_next_block(sc, par_num++,
3151 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3153 bnx2x_print_next_block(sc, par_num++,
3156 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3158 bnx2x_print_next_block(sc, par_num++,
3172 bnx2x_check_blocks_with_parity1(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3173 uint8_t * global, uint8_t print)
3176 uint32_t cur_bit = 0;
3177 for (i = 0; sig; i++) {
3178 cur_bit = ((uint32_t) 0x1 << i);
3179 if (sig & cur_bit) {
3181 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3183 bnx2x_print_next_block(sc, par_num++,
3186 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3188 bnx2x_print_next_block(sc, par_num++,
3191 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3193 bnx2x_print_next_block(sc, par_num++,
3196 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3198 bnx2x_print_next_block(sc, par_num++,
3201 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
3203 bnx2x_print_next_block(sc, par_num++,
3206 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3208 bnx2x_print_next_block(sc, par_num++,
3211 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3213 bnx2x_print_next_block(sc, par_num++,
3216 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
3218 bnx2x_print_next_block(sc, par_num++,
3221 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3223 bnx2x_print_next_block(sc, par_num++,
3227 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3229 bnx2x_print_next_block(sc, par_num++,
3232 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3234 bnx2x_print_next_block(sc, par_num++,
3237 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
3239 bnx2x_print_next_block(sc, par_num++,
3242 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3244 bnx2x_print_next_block(sc, par_num++,
3247 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3249 bnx2x_print_next_block(sc, par_num++,
3252 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3254 bnx2x_print_next_block(sc, par_num++,
3257 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
3259 bnx2x_print_next_block(sc, par_num++,
3273 bnx2x_check_blocks_with_parity2(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3276 uint32_t cur_bit = 0;
3279 for (i = 0; sig; i++) {
3280 cur_bit = ((uint32_t) 0x1 << i);
3281 if (sig & cur_bit) {
3283 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3285 bnx2x_print_next_block(sc, par_num++,
3288 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3290 bnx2x_print_next_block(sc, par_num++,
3293 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3295 bnx2x_print_next_block(sc, par_num++,
3296 "PXPPCICLOCKCLIENT");
3298 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3300 bnx2x_print_next_block(sc, par_num++,
3303 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3305 bnx2x_print_next_block(sc, par_num++,
3308 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
3310 bnx2x_print_next_block(sc, par_num++,
3313 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3315 bnx2x_print_next_block(sc, par_num++,
3318 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3320 bnx2x_print_next_block(sc, par_num++,
3334 bnx2x_check_blocks_with_parity3(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3335 uint8_t * global, uint8_t print)
3337 uint32_t cur_bit = 0;
3340 for (i = 0; sig; i++) {
3341 cur_bit = ((uint32_t) 0x1 << i);
3342 if (sig & cur_bit) {
3344 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3346 bnx2x_print_next_block(sc, par_num++,
3350 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3352 bnx2x_print_next_block(sc, par_num++,
3356 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3358 bnx2x_print_next_block(sc, par_num++,
3362 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3364 bnx2x_print_next_block(sc, par_num++,
3379 bnx2x_check_blocks_with_parity4(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3382 uint32_t cur_bit = 0;
3385 for (i = 0; sig; i++) {
3386 cur_bit = ((uint32_t) 0x1 << i);
3387 if (sig & cur_bit) {
3389 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
3391 bnx2x_print_next_block(sc, par_num++,
3394 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
3396 bnx2x_print_next_block(sc, par_num++,
3410 bnx2x_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print,
3415 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
3416 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
3417 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
3418 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
3419 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
3420 PMD_DRV_LOG(ERR, sc,
3421 "Parity error: HW block parity attention:"
3422 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x",
3423 (uint32_t) (sig[0] & HW_PRTY_ASSERT_SET_0),
3424 (uint32_t) (sig[1] & HW_PRTY_ASSERT_SET_1),
3425 (uint32_t) (sig[2] & HW_PRTY_ASSERT_SET_2),
3426 (uint32_t) (sig[3] & HW_PRTY_ASSERT_SET_3),
3427 (uint32_t) (sig[4] & HW_PRTY_ASSERT_SET_4));
3430 PMD_DRV_LOG(INFO, sc, "Parity errors detected in blocks: ");
3433 bnx2x_check_blocks_with_parity0(sc, sig[0] &
3434 HW_PRTY_ASSERT_SET_0,
3437 bnx2x_check_blocks_with_parity1(sc, sig[1] &
3438 HW_PRTY_ASSERT_SET_1,
3439 par_num, global, print);
3441 bnx2x_check_blocks_with_parity2(sc, sig[2] &
3442 HW_PRTY_ASSERT_SET_2,
3445 bnx2x_check_blocks_with_parity3(sc, sig[3] &
3446 HW_PRTY_ASSERT_SET_3,
3447 par_num, global, print);
3449 bnx2x_check_blocks_with_parity4(sc, sig[4] &
3450 HW_PRTY_ASSERT_SET_4,
3454 PMD_DRV_LOG(INFO, sc, "");
3463 bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print)
3465 struct attn_route attn = { {0} };
3466 int port = SC_PORT(sc);
3468 attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
3469 attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
3470 attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
3471 attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
3473 if (!CHIP_IS_E1x(sc))
3475 REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
3477 return bnx2x_parity_attn(sc, global, print, attn.sig);
3480 static void bnx2x_attn_int_deasserted4(struct bnx2x_softc *sc, uint32_t attn)
3484 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
3485 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
3486 PMD_DRV_LOG(INFO, sc, "ERROR: PGLUE hw attention 0x%08x", val);
3487 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
3488 PMD_DRV_LOG(INFO, sc,
3489 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR");
3490 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
3491 PMD_DRV_LOG(INFO, sc,
3492 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR");
3493 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
3494 PMD_DRV_LOG(INFO, sc,
3495 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN");
3496 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
3497 PMD_DRV_LOG(INFO, sc,
3498 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN");
3500 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
3501 PMD_DRV_LOG(INFO, sc,
3502 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN");
3504 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
3505 PMD_DRV_LOG(INFO, sc,
3506 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN");
3507 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
3508 PMD_DRV_LOG(INFO, sc,
3509 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN");
3510 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
3511 PMD_DRV_LOG(INFO, sc,
3512 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN");
3513 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
3514 PMD_DRV_LOG(INFO, sc,
3515 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW");
3518 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
3519 val = REG_RD(sc, ATC_REG_ATC_INT_STS_CLR);
3520 PMD_DRV_LOG(INFO, sc, "ERROR: ATC hw attention 0x%08x", val);
3521 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
3522 PMD_DRV_LOG(INFO, sc,
3523 "ERROR: ATC_ATC_INT_STS_REG_ADDRESS_ERROR");
3524 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
3525 PMD_DRV_LOG(INFO, sc,
3526 "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND");
3527 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
3528 PMD_DRV_LOG(INFO, sc,
3529 "ERROR: ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS");
3530 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
3531 PMD_DRV_LOG(INFO, sc,
3532 "ERROR: ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT");
3533 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
3534 PMD_DRV_LOG(INFO, sc,
3535 "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR");
3536 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
3537 PMD_DRV_LOG(INFO, sc,
3538 "ERROR: ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU");
3541 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3542 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
3543 PMD_DRV_LOG(INFO, sc,
3544 "ERROR: FATAL parity attention set4 0x%08x",
3546 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
3548 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
3552 static void bnx2x_e1h_disable(struct bnx2x_softc *sc)
3554 int port = SC_PORT(sc);
3556 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
3559 static void bnx2x_e1h_enable(struct bnx2x_softc *sc)
3561 int port = SC_PORT(sc);
3563 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3567 * called due to MCP event (on pmf):
3568 * reread new bandwidth configuration
3570 * notify others function about the change
3572 static void bnx2x_config_mf_bw(struct bnx2x_softc *sc)
3574 if (sc->link_vars.link_up) {
3575 bnx2x_cmng_fns_init(sc, TRUE, CMNG_FNS_MINMAX);
3576 bnx2x_link_sync_notify(sc);
3579 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
3582 static void bnx2x_set_mf_bw(struct bnx2x_softc *sc)
3584 bnx2x_config_mf_bw(sc);
3585 bnx2x_fw_command(sc, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3588 static void bnx2x_handle_eee_event(struct bnx2x_softc *sc)
3590 bnx2x_fw_command(sc, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3593 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3595 static void bnx2x_drv_info_ether_stat(struct bnx2x_softc *sc)
3597 struct eth_stats_info *ether_stat = &sc->sp->drv_info_to_mcp.ether_stat;
3599 strncpy(ether_stat->version, BNX2X_DRIVER_VERSION,
3600 ETH_STAT_INFO_VERSION_LEN);
3602 sc->sp_objs[0].mac_obj.get_n_elements(sc, &sc->sp_objs[0].mac_obj,
3603 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3604 ether_stat->mac_local + MAC_PAD,
3607 ether_stat->mtu_size = sc->mtu;
3609 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3610 ether_stat->promiscuous_mode = 0; // (flags & PROMISC) ? 1 : 0;
3612 ether_stat->txq_size = sc->tx_ring_size;
3613 ether_stat->rxq_size = sc->rx_ring_size;
3616 static void bnx2x_handle_drv_info_req(struct bnx2x_softc *sc)
3618 enum drv_info_opcode op_code;
3619 uint32_t drv_info_ctl = SHMEM2_RD(sc, drv_info_control);
3621 /* if drv_info version supported by MFW doesn't match - send NACK */
3622 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3623 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3627 op_code = ((drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3628 DRV_INFO_CONTROL_OP_CODE_SHIFT);
3630 memset(&sc->sp->drv_info_to_mcp, 0, sizeof(union drv_info_to_mcp));
3633 case ETH_STATS_OPCODE:
3634 bnx2x_drv_info_ether_stat(sc);
3636 case FCOE_STATS_OPCODE:
3637 case ISCSI_STATS_OPCODE:
3639 /* if op code isn't supported - send NACK */
3640 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3645 * If we got drv_info attn from MFW then these fields are defined in
3648 SHMEM2_WR(sc, drv_info_host_addr_lo,
3649 U64_LO(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3650 SHMEM2_WR(sc, drv_info_host_addr_hi,
3651 U64_HI(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3653 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3656 static void bnx2x_dcc_event(struct bnx2x_softc *sc, uint32_t dcc_event)
3658 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3660 * This is the only place besides the function initialization
3661 * where the sc->flags can change so it is done without any
3665 mf_info.mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_DISABLED) {
3666 PMD_DRV_LOG(DEBUG, sc, "mf_cfg function disabled");
3667 sc->flags |= BNX2X_MF_FUNC_DIS;
3668 bnx2x_e1h_disable(sc);
3670 PMD_DRV_LOG(DEBUG, sc, "mf_cfg function enabled");
3671 sc->flags &= ~BNX2X_MF_FUNC_DIS;
3672 bnx2x_e1h_enable(sc);
3674 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3677 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3678 bnx2x_config_mf_bw(sc);
3679 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3682 /* Report results to MCP */
3684 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_FAILURE, 0);
3686 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_OK, 0);
3689 static void bnx2x_pmf_update(struct bnx2x_softc *sc)
3691 int port = SC_PORT(sc);
3697 * We need the mb() to ensure the ordering between the writing to
3698 * sc->port.pmf here and reading it from the bnx2x_periodic_task().
3702 /* enable nig attention */
3703 val = (0xff0f | (1 << (SC_VN(sc) + 4)));
3704 if (sc->devinfo.int_block == INT_BLOCK_HC) {
3705 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, val);
3706 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, val);
3707 } else if (!CHIP_IS_E1x(sc)) {
3708 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
3709 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
3712 bnx2x_stats_handle(sc, STATS_EVENT_PMF);
3715 static int bnx2x_mc_assert(struct bnx2x_softc *sc)
3719 __rte_unused uint32_t row0, row1, row2, row3;
3723 REG_RD8(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_INDEX_OFFSET);
3725 PMD_DRV_LOG(ERR, sc, "XSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3727 /* print the asserts */
3728 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3732 BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i));
3735 BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3739 BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3743 BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3746 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3747 PMD_DRV_LOG(ERR, sc,
3748 "XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3749 i, row3, row2, row1, row0);
3758 REG_RD8(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_INDEX_OFFSET);
3760 PMD_DRV_LOG(ERR, sc, "TSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3763 /* print the asserts */
3764 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3768 BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i));
3771 BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3775 BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3779 BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3782 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3783 PMD_DRV_LOG(ERR, sc,
3784 "TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3785 i, row3, row2, row1, row0);
3794 REG_RD8(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_INDEX_OFFSET);
3796 PMD_DRV_LOG(ERR, sc, "CSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3799 /* print the asserts */
3800 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3804 BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i));
3807 BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3811 BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3815 BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3818 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3819 PMD_DRV_LOG(ERR, sc,
3820 "CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3821 i, row3, row2, row1, row0);
3830 REG_RD8(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_INDEX_OFFSET);
3832 PMD_DRV_LOG(ERR, sc, "USTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3835 /* print the asserts */
3836 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3840 BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i));
3843 BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3847 BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3851 BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3854 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3855 PMD_DRV_LOG(ERR, sc,
3856 "USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3857 i, row3, row2, row1, row0);
3867 static void bnx2x_attn_int_deasserted3(struct bnx2x_softc *sc, uint32_t attn)
3869 int func = SC_FUNC(sc);
3872 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3874 if (attn & BNX2X_PMF_LINK_ASSERT(sc)) {
3876 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
3877 bnx2x_read_mf_cfg(sc);
3878 sc->devinfo.mf_info.mf_config[SC_VN(sc)] =
3880 func_mf_config[SC_ABS_FUNC(sc)].config);
3882 SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_status);
3884 if (val & DRV_STATUS_DCC_EVENT_MASK)
3887 DRV_STATUS_DCC_EVENT_MASK));
3889 if (val & DRV_STATUS_SET_MF_BW)
3890 bnx2x_set_mf_bw(sc);
3892 if (val & DRV_STATUS_DRV_INFO_REQ)
3893 bnx2x_handle_drv_info_req(sc);
3895 if ((sc->port.pmf == 0) && (val & DRV_STATUS_PMF))
3896 bnx2x_pmf_update(sc);
3898 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
3899 bnx2x_handle_eee_event(sc);
3901 if (sc->link_vars.periodic_flags &
3902 ELINK_PERIODIC_FLAGS_LINK_EVENT) {
3903 /* sync with link */
3904 bnx2x_acquire_phy_lock(sc);
3905 sc->link_vars.periodic_flags &=
3906 ~ELINK_PERIODIC_FLAGS_LINK_EVENT;
3907 bnx2x_release_phy_lock(sc);
3909 bnx2x_link_sync_notify(sc);
3911 bnx2x_link_report(sc);
3915 * Always call it here: bnx2x_link_report() will
3916 * prevent the link indication duplication.
3918 bnx2x_link_status_update(sc);
3920 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3922 PMD_DRV_LOG(ERR, sc, "MC assert!");
3923 bnx2x_mc_assert(sc);
3924 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3925 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3926 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3927 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3928 rte_panic("MC assert!");
3930 } else if (attn & BNX2X_MCP_ASSERT) {
3932 PMD_DRV_LOG(ERR, sc, "MCP assert!");
3933 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3936 PMD_DRV_LOG(ERR, sc,
3937 "Unknown HW assert! (attn 0x%08x)", attn);
3941 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3942 PMD_DRV_LOG(ERR, sc, "LATCHED attention 0x%08x (masked)", attn);
3943 if (attn & BNX2X_GRC_TIMEOUT) {
3944 val = REG_RD(sc, MISC_REG_GRC_TIMEOUT_ATTN);
3945 PMD_DRV_LOG(ERR, sc, "GRC time-out 0x%08x", val);
3947 if (attn & BNX2X_GRC_RSV) {
3948 val = REG_RD(sc, MISC_REG_GRC_RSV_ATTN);
3949 PMD_DRV_LOG(ERR, sc, "GRC reserved 0x%08x", val);
3951 REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3955 static void bnx2x_attn_int_deasserted2(struct bnx2x_softc *sc, uint32_t attn)
3957 int port = SC_PORT(sc);
3959 uint32_t val0, mask0, val1, mask1;
3962 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3963 val = REG_RD(sc, CFC_REG_CFC_INT_STS_CLR);
3964 PMD_DRV_LOG(ERR, sc, "CFC hw attention 0x%08x", val);
3965 /* CFC error attention */
3967 PMD_DRV_LOG(ERR, sc, "FATAL error from CFC");
3971 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3972 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_0);
3973 PMD_DRV_LOG(ERR, sc, "PXP hw attention-0 0x%08x", val);
3974 /* RQ_USDMDP_FIFO_OVERFLOW */
3975 if (val & 0x18000) {
3976 PMD_DRV_LOG(ERR, sc, "FATAL error from PXP");
3979 if (!CHIP_IS_E1x(sc)) {
3980 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_1);
3981 PMD_DRV_LOG(ERR, sc, "PXP hw attention-1 0x%08x", val);
3984 #define PXP2_EOP_ERROR_BIT PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR
3985 #define AEU_PXP2_HW_INT_BIT AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT
3987 if (attn & AEU_PXP2_HW_INT_BIT) {
3988 /* CQ47854 workaround do not panic on
3989 * PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3991 if (!CHIP_IS_E1x(sc)) {
3992 mask0 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_0);
3993 val1 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_1);
3994 mask1 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_1);
3995 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_0);
3997 * If the only PXP2_EOP_ERROR_BIT is set in
3998 * STS0 and STS1 - clear it
4000 * probably we lose additional attentions between
4001 * STS0 and STS_CLR0, in this case user will not
4002 * be notified about them
4004 if (val0 & mask0 & PXP2_EOP_ERROR_BIT &&
4006 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
4008 /* print the register, since no one can restore it */
4009 PMD_DRV_LOG(ERR, sc,
4010 "PXP2_REG_PXP2_INT_STS_CLR_0 0x%08x", val0);
4013 * if PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
4016 if (val0 & PXP2_EOP_ERROR_BIT) {
4017 PMD_DRV_LOG(ERR, sc, "PXP2_WR_PGLUE_EOP_ERROR");
4020 * if only PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR is
4021 * set then clear attention from PXP2 block without panic
4023 if (((val0 & mask0) == PXP2_EOP_ERROR_BIT) &&
4024 ((val1 & mask1) == 0))
4025 attn &= ~AEU_PXP2_HW_INT_BIT;
4030 if (attn & HW_INTERRUT_ASSERT_SET_2) {
4031 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
4032 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
4034 val = REG_RD(sc, reg_offset);
4035 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
4036 REG_WR(sc, reg_offset, val);
4038 PMD_DRV_LOG(ERR, sc,
4039 "FATAL HW block attention set2 0x%x",
4040 (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_2));
4041 rte_panic("HW block attention set2");
4045 static void bnx2x_attn_int_deasserted1(struct bnx2x_softc *sc, uint32_t attn)
4047 int port = SC_PORT(sc);
4051 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
4052 val = REG_RD(sc, DORQ_REG_DORQ_INT_STS_CLR);
4053 PMD_DRV_LOG(ERR, sc, "DB hw attention 0x%08x", val);
4054 /* DORQ discard attention */
4056 PMD_DRV_LOG(ERR, sc, "FATAL error from DORQ");
4060 if (attn & HW_INTERRUT_ASSERT_SET_1) {
4061 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4062 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4064 val = REG_RD(sc, reg_offset);
4065 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4066 REG_WR(sc, reg_offset, val);
4068 PMD_DRV_LOG(ERR, sc,
4069 "FATAL HW block attention set1 0x%08x",
4070 (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_1));
4071 rte_panic("HW block attention set1");
4075 static void bnx2x_attn_int_deasserted0(struct bnx2x_softc *sc, uint32_t attn)
4077 int port = SC_PORT(sc);
4081 reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4082 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
4084 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4085 val = REG_RD(sc, reg_offset);
4086 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4087 REG_WR(sc, reg_offset, val);
4089 PMD_DRV_LOG(WARNING, sc, "SPIO5 hw attention");
4091 /* Fan failure attention */
4092 elink_hw_reset_phy(&sc->link_params);
4093 bnx2x_fan_failure(sc);
4096 if ((attn & sc->link_vars.aeu_int_mask) && sc->port.pmf) {
4097 bnx2x_acquire_phy_lock(sc);
4098 elink_handle_module_detect_int(&sc->link_params);
4099 bnx2x_release_phy_lock(sc);
4102 if (attn & HW_INTERRUT_ASSERT_SET_0) {
4103 val = REG_RD(sc, reg_offset);
4104 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4105 REG_WR(sc, reg_offset, val);
4107 rte_panic("FATAL HW block attention set0 0x%lx",
4108 (attn & (unsigned long)HW_INTERRUT_ASSERT_SET_0));
4112 static void bnx2x_attn_int_deasserted(struct bnx2x_softc *sc, uint32_t deasserted)
4114 struct attn_route attn;
4115 struct attn_route *group_mask;
4116 int port = SC_PORT(sc);
4121 uint8_t global = FALSE;
4124 * Need to take HW lock because MCP or other port might also
4125 * try to handle this event.
4127 bnx2x_acquire_alr(sc);
4129 if (bnx2x_chk_parity_attn(sc, &global, TRUE)) {
4130 sc->recovery_state = BNX2X_RECOVERY_INIT;
4132 /* disable HW interrupts */
4133 bnx2x_int_disable(sc);
4134 bnx2x_release_alr(sc);
4138 attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
4139 attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
4140 attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
4141 attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
4142 if (!CHIP_IS_E1x(sc)) {
4144 REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
4149 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4150 if (deasserted & (1 << index)) {
4151 group_mask = &sc->attn_group[index];
4153 bnx2x_attn_int_deasserted4(sc,
4155 sig[4] & group_mask->sig[4]);
4156 bnx2x_attn_int_deasserted3(sc,
4158 sig[3] & group_mask->sig[3]);
4159 bnx2x_attn_int_deasserted1(sc,
4161 sig[1] & group_mask->sig[1]);
4162 bnx2x_attn_int_deasserted2(sc,
4164 sig[2] & group_mask->sig[2]);
4165 bnx2x_attn_int_deasserted0(sc,
4167 sig[0] & group_mask->sig[0]);
4171 bnx2x_release_alr(sc);
4173 if (sc->devinfo.int_block == INT_BLOCK_HC) {
4174 reg_addr = (HC_REG_COMMAND_REG + port * 32 +
4175 COMMAND_REG_ATTN_BITS_CLR);
4177 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER * 8);
4181 PMD_DRV_LOG(DEBUG, sc,
4182 "about to mask 0x%08x at %s addr 0x%08x", val,
4183 (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
4185 REG_WR(sc, reg_addr, val);
4187 if (~sc->attn_state & deasserted) {
4188 PMD_DRV_LOG(ERR, sc, "IGU error");
4191 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4192 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4194 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4196 aeu_mask = REG_RD(sc, reg_addr);
4198 aeu_mask |= (deasserted & 0x3ff);
4200 REG_WR(sc, reg_addr, aeu_mask);
4201 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4203 sc->attn_state &= ~deasserted;
4206 static void bnx2x_attn_int(struct bnx2x_softc *sc)
4208 /* read local copy of bits */
4209 uint32_t attn_bits = le32toh(sc->def_sb->atten_status_block.attn_bits);
4211 le32toh(sc->def_sb->atten_status_block.attn_bits_ack);
4212 uint32_t attn_state = sc->attn_state;
4214 /* look for changed bits */
4215 uint32_t asserted = attn_bits & ~attn_ack & ~attn_state;
4216 uint32_t deasserted = ~attn_bits & attn_ack & attn_state;
4218 PMD_DRV_LOG(DEBUG, sc,
4219 "attn_bits 0x%08x attn_ack 0x%08x asserted 0x%08x deasserted 0x%08x",
4220 attn_bits, attn_ack, asserted, deasserted);
4222 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) {
4223 PMD_DRV_LOG(ERR, sc, "BAD attention state");
4226 /* handle bits that were raised */
4228 bnx2x_attn_int_asserted(sc, asserted);
4232 bnx2x_attn_int_deasserted(sc, deasserted);
4236 static uint16_t bnx2x_update_dsb_idx(struct bnx2x_softc *sc)
4238 struct host_sp_status_block *def_sb = sc->def_sb;
4244 mb(); /* status block is written to by the chip */
4246 if (sc->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
4247 sc->def_att_idx = def_sb->atten_status_block.attn_bits_index;
4248 rc |= BNX2X_DEF_SB_ATT_IDX;
4251 if (sc->def_idx != def_sb->sp_sb.running_index) {
4252 sc->def_idx = def_sb->sp_sb.running_index;
4253 rc |= BNX2X_DEF_SB_IDX;
4261 static struct ecore_queue_sp_obj *bnx2x_cid_to_q_obj(struct bnx2x_softc *sc,
4264 return &sc->sp_objs[CID_TO_FP(cid, sc)].q_obj;
4267 static void bnx2x_handle_mcast_eqe(struct bnx2x_softc *sc)
4269 struct ecore_mcast_ramrod_params rparam;
4272 memset(&rparam, 0, sizeof(rparam));
4274 rparam.mcast_obj = &sc->mcast_obj;
4276 /* clear pending state for the last command */
4277 sc->mcast_obj.raw.clear_pending(&sc->mcast_obj.raw);
4279 /* if there are pending mcast commands - send them */
4280 if (sc->mcast_obj.check_pending(&sc->mcast_obj)) {
4281 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
4283 PMD_DRV_LOG(INFO, sc,
4284 "Failed to send pending mcast commands (%d)",
4291 bnx2x_handle_classification_eqe(struct bnx2x_softc *sc, union event_ring_elem *elem)
4293 uint32_t ramrod_flags = 0;
4295 uint32_t cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4296 struct ecore_vlan_mac_obj *vlan_mac_obj;
4298 /* always push next commands out, don't wait here */
4299 rte_bit_relaxed_set32(RAMROD_CONT, &ramrod_flags);
4301 switch (le32toh(elem->message.data.eth_event.echo) >> BNX2X_SWCID_SHIFT) {
4302 case ECORE_FILTER_MAC_PENDING:
4303 PMD_DRV_LOG(DEBUG, sc, "Got SETUP_MAC completions");
4304 vlan_mac_obj = &sc->sp_objs[cid].mac_obj;
4307 case ECORE_FILTER_MCAST_PENDING:
4308 PMD_DRV_LOG(DEBUG, sc, "Got SETUP_MCAST completions");
4309 bnx2x_handle_mcast_eqe(sc);
4313 PMD_DRV_LOG(NOTICE, sc, "Unsupported classification command: %d",
4314 elem->message.data.eth_event.echo);
4318 rc = vlan_mac_obj->complete(sc, vlan_mac_obj, elem, &ramrod_flags);
4321 PMD_DRV_LOG(NOTICE, sc,
4322 "Failed to schedule new commands (%d)", rc);
4323 } else if (rc > 0) {
4324 PMD_DRV_LOG(DEBUG, sc, "Scheduled next pending commands...");
4328 static void bnx2x_handle_rx_mode_eqe(struct bnx2x_softc *sc)
4330 rte_bit_relaxed_clear32(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
4332 /* send rx_mode command again if was requested */
4333 if (rte_bit_relaxed_test_and_clear32(ECORE_FILTER_RX_MODE_SCHED,
4335 bnx2x_set_storm_rx_mode(sc);
4338 static void bnx2x_update_eq_prod(struct bnx2x_softc *sc, uint16_t prod)
4340 storm_memset_eq_prod(sc, prod, SC_FUNC(sc));
4341 wmb(); /* keep prod updates ordered */
4344 static void bnx2x_eq_int(struct bnx2x_softc *sc)
4346 uint16_t hw_cons, sw_cons, sw_prod;
4347 union event_ring_elem *elem;
4352 struct ecore_queue_sp_obj *q_obj;
4353 struct ecore_func_sp_obj *f_obj = &sc->func_obj;
4354 struct ecore_raw_obj *rss_raw = &sc->rss_conf_obj.raw;
4356 hw_cons = le16toh(*sc->eq_cons_sb);
4359 * The hw_cons range is 1-255, 257 - the sw_cons range is 0-254, 256.
4360 * when we get to the next-page we need to adjust so the loop
4361 * condition below will be met. The next element is the size of a
4362 * regular element and hence incrementing by 1
4364 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) {
4369 * This function may never run in parallel with itself for a
4370 * specific sc and no need for a read memory barrier here.
4372 sw_cons = sc->eq_cons;
4373 sw_prod = sc->eq_prod;
4377 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4379 elem = &sc->eq[EQ_DESC(sw_cons)];
4381 /* elem CID originates from FW, actually LE */
4382 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4383 opcode = elem->message.opcode;
4385 /* handle eq element */
4387 case EVENT_RING_OPCODE_STAT_QUERY:
4388 PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "got statistics completion event %d",
4390 /* nothing to do with stats comp */
4393 case EVENT_RING_OPCODE_CFC_DEL:
4394 /* handle according to cid range */
4395 /* we may want to verify here that the sc state is HALTING */
4396 PMD_DRV_LOG(DEBUG, sc, "got delete ramrod for MULTI[%d]",
4398 q_obj = bnx2x_cid_to_q_obj(sc, cid);
4399 if (q_obj->complete_cmd(sc, q_obj, ECORE_Q_CMD_CFC_DEL)) {
4404 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4405 PMD_DRV_LOG(DEBUG, sc, "got STOP TRAFFIC");
4406 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_STOP)) {
4411 case EVENT_RING_OPCODE_START_TRAFFIC:
4412 PMD_DRV_LOG(DEBUG, sc, "got START TRAFFIC");
4413 if (f_obj->complete_cmd
4414 (sc, f_obj, ECORE_F_CMD_TX_START)) {
4419 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
4420 echo = elem->message.data.function_update_event.echo;
4421 if (echo == SWITCH_UPDATE) {
4422 PMD_DRV_LOG(DEBUG, sc,
4423 "got FUNC_SWITCH_UPDATE ramrod");
4424 if (f_obj->complete_cmd(sc, f_obj,
4425 ECORE_F_CMD_SWITCH_UPDATE))
4430 PMD_DRV_LOG(DEBUG, sc,
4431 "AFEX: ramrod completed FUNCTION_UPDATE");
4432 f_obj->complete_cmd(sc, f_obj,
4433 ECORE_F_CMD_AFEX_UPDATE);
4437 case EVENT_RING_OPCODE_FORWARD_SETUP:
4438 q_obj = &bnx2x_fwd_sp_obj(sc, q_obj);
4439 if (q_obj->complete_cmd(sc, q_obj,
4440 ECORE_Q_CMD_SETUP_TX_ONLY)) {
4445 case EVENT_RING_OPCODE_FUNCTION_START:
4446 PMD_DRV_LOG(DEBUG, sc, "got FUNC_START ramrod");
4447 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_START)) {
4452 case EVENT_RING_OPCODE_FUNCTION_STOP:
4453 PMD_DRV_LOG(DEBUG, sc, "got FUNC_STOP ramrod");
4454 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_STOP)) {
4460 switch (opcode | sc->state) {
4461 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPEN):
4462 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPENING_WAITING_PORT):
4464 elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4465 PMD_DRV_LOG(DEBUG, sc, "got RSS_UPDATE ramrod. CID %d",
4467 rss_raw->clear_pending(rss_raw);
4470 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4471 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4472 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_CLOSING_WAITING_HALT):
4473 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_OPEN):
4474 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_DIAG):
4475 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4476 PMD_DRV_LOG(DEBUG, sc,
4477 "got (un)set mac ramrod");
4478 bnx2x_handle_classification_eqe(sc, elem);
4481 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_OPEN):
4482 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_DIAG):
4483 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4484 PMD_DRV_LOG(DEBUG, sc,
4485 "got mcast ramrod");
4486 bnx2x_handle_mcast_eqe(sc);
4489 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_OPEN):
4490 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_DIAG):
4491 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4492 PMD_DRV_LOG(DEBUG, sc,
4493 "got rx_mode ramrod");
4494 bnx2x_handle_rx_mode_eqe(sc);
4498 /* unknown event log error and continue */
4499 PMD_DRV_LOG(INFO, sc, "Unknown EQ event %d, sc->state 0x%x",
4500 elem->message.opcode, sc->state);
4508 atomic_add_acq_long(&sc->eq_spq_left, spqe_cnt);
4510 sc->eq_cons = sw_cons;
4511 sc->eq_prod = sw_prod;
4513 /* make sure that above mem writes were issued towards the memory */
4516 /* update producer */
4517 bnx2x_update_eq_prod(sc, sc->eq_prod);
4520 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc)
4525 PMD_DRV_LOG(DEBUG, sc, "---> SP TASK <---");
4527 /* what work needs to be performed? */
4528 status = bnx2x_update_dsb_idx(sc);
4530 PMD_DRV_LOG(DEBUG, sc, "dsb status 0x%04x", status);
4533 if (status & BNX2X_DEF_SB_ATT_IDX) {
4534 PMD_DRV_LOG(DEBUG, sc, "---> ATTN INTR <---");
4536 status &= ~BNX2X_DEF_SB_ATT_IDX;
4540 /* SP events: STAT_QUERY and others */
4541 if (status & BNX2X_DEF_SB_IDX) {
4542 /* handle EQ completions */
4543 PMD_DRV_LOG(DEBUG, sc, "---> EQ INTR <---");
4545 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
4546 le16toh(sc->def_idx), IGU_INT_NOP, 1);
4547 status &= ~BNX2X_DEF_SB_IDX;
4550 /* if status is non zero then something went wrong */
4551 if (unlikely(status)) {
4552 PMD_DRV_LOG(INFO, sc,
4553 "Got an unknown SP interrupt! (0x%04x)", status);
4556 /* ack status block only if something was actually handled */
4557 bnx2x_ack_sb(sc, sc->igu_dsb_id, ATTENTION_ID,
4558 le16toh(sc->def_att_idx), IGU_INT_ENABLE, 1);
4563 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp)
4565 struct bnx2x_softc *sc = fp->sc;
4566 uint8_t more_rx = FALSE;
4568 /* Make sure FP is initialized */
4569 if (!fp->sb_running_index)
4572 PMD_DEBUG_PERIODIC_LOG(DEBUG, sc,
4573 "---> FP TASK QUEUE (%d) <--", fp->index);
4575 /* update the fastpath index */
4576 bnx2x_update_fp_sb_idx(fp);
4578 if (rte_atomic32_read(&sc->scan_fp) == 1) {
4579 if (bnx2x_has_rx_work(fp)) {
4580 more_rx = bnx2x_rxeof(sc, fp);
4584 /* still more work to do */
4585 bnx2x_handle_fp_tq(fp);
4588 /* We have completed slow path completion, clear the flag */
4589 rte_atomic32_set(&sc->scan_fp, 0);
4592 bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
4593 le16toh(fp->fp_hc_idx), IGU_INT_ENABLE, 1);
4597 * Legacy interrupt entry point.
4599 * Verifies that the controller generated the interrupt and
4600 * then calls a separate routine to handle the various
4601 * interrupt causes: link, RX, and TX.
4603 int bnx2x_intr_legacy(struct bnx2x_softc *sc)
4605 struct bnx2x_fastpath *fp;
4606 uint32_t status, mask;
4610 * 0 for ustorm, 1 for cstorm
4611 * the bits returned from ack_int() are 0-15
4612 * bit 0 = attention status block
4613 * bit 1 = fast path status block
4614 * a mask of 0x2 or more = tx/rx event
4615 * a mask of 1 = slow path event
4618 status = bnx2x_ack_int(sc);
4620 /* the interrupt is not for us */
4621 if (unlikely(status == 0)) {
4625 PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "Interrupt status 0x%04x", status);
4626 //bnx2x_dump_status_block(sc);
4628 FOR_EACH_ETH_QUEUE(sc, i) {
4630 mask = (0x2 << (fp->index + CNIC_SUPPORT(sc)));
4631 if (status & mask) {
4632 /* acknowledge and disable further fastpath interrupts */
4633 bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
4634 0, IGU_INT_DISABLE, 0);
4635 bnx2x_handle_fp_tq(fp);
4640 if (unlikely(status & 0x1)) {
4641 /* acknowledge and disable further slowpath interrupts */
4642 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
4643 0, IGU_INT_DISABLE, 0);
4644 rc = bnx2x_handle_sp_tq(sc);
4648 if (unlikely(status)) {
4649 PMD_DRV_LOG(WARNING, sc,
4650 "Unexpected fastpath status (0x%08x)!", status);
4656 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc);
4657 static int bnx2x_init_hw_common(struct bnx2x_softc *sc);
4658 static int bnx2x_init_hw_port(struct bnx2x_softc *sc);
4659 static int bnx2x_init_hw_func(struct bnx2x_softc *sc);
4660 static void bnx2x_reset_common(struct bnx2x_softc *sc);
4661 static void bnx2x_reset_port(struct bnx2x_softc *sc);
4662 static void bnx2x_reset_func(struct bnx2x_softc *sc);
4663 static int bnx2x_init_firmware(struct bnx2x_softc *sc);
4664 static void bnx2x_release_firmware(struct bnx2x_softc *sc);
4667 ecore_func_sp_drv_ops bnx2x_func_sp_drv = {
4668 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
4669 .init_hw_cmn = bnx2x_init_hw_common,
4670 .init_hw_port = bnx2x_init_hw_port,
4671 .init_hw_func = bnx2x_init_hw_func,
4673 .reset_hw_cmn = bnx2x_reset_common,
4674 .reset_hw_port = bnx2x_reset_port,
4675 .reset_hw_func = bnx2x_reset_func,
4677 .init_fw = bnx2x_init_firmware,
4678 .release_fw = bnx2x_release_firmware,
4681 static void bnx2x_init_func_obj(struct bnx2x_softc *sc)
4685 PMD_INIT_FUNC_TRACE(sc);
4687 ecore_init_func_obj(sc,
4689 BNX2X_SP(sc, func_rdata),
4690 (rte_iova_t)BNX2X_SP_MAPPING(sc, func_rdata),
4691 BNX2X_SP(sc, func_afex_rdata),
4692 (rte_iova_t)BNX2X_SP_MAPPING(sc, func_afex_rdata),
4693 &bnx2x_func_sp_drv);
4696 static int bnx2x_init_hw(struct bnx2x_softc *sc, uint32_t load_code)
4698 struct ecore_func_state_params func_params = { NULL };
4701 PMD_INIT_FUNC_TRACE(sc);
4703 /* prepare the parameters for function state transitions */
4704 rte_bit_relaxed_set32(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
4706 func_params.f_obj = &sc->func_obj;
4707 func_params.cmd = ECORE_F_CMD_HW_INIT;
4709 func_params.params.hw_init.load_phase = load_code;
4712 * Via a plethora of function pointers, we will eventually reach
4713 * bnx2x_init_hw_common(), bnx2x_init_hw_port(), or bnx2x_init_hw_func().
4715 rc = ecore_func_state_change(sc, &func_params);
4721 bnx2x_fill(struct bnx2x_softc *sc, uint32_t addr, int fill, uint32_t len)
4725 if (!(len % 4) && !(addr % 4)) {
4726 for (i = 0; i < len; i += 4) {
4727 REG_WR(sc, (addr + i), fill);
4730 for (i = 0; i < len; i++) {
4731 REG_WR8(sc, (addr + i), fill);
4736 /* writes FP SP data to FW - data_size in dwords */
4738 bnx2x_wr_fp_sb_data(struct bnx2x_softc *sc, int fw_sb_id, uint32_t * sb_data_p,
4743 for (index = 0; index < data_size; index++) {
4745 (BAR_CSTRORM_INTMEM +
4746 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
4747 (sizeof(uint32_t) * index)), *(sb_data_p + index));
4751 static void bnx2x_zero_fp_sb(struct bnx2x_softc *sc, int fw_sb_id)
4753 struct hc_status_block_data_e2 sb_data_e2;
4754 struct hc_status_block_data_e1x sb_data_e1x;
4755 uint32_t *sb_data_p;
4756 uint32_t data_size = 0;
4758 if (!CHIP_IS_E1x(sc)) {
4759 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4760 sb_data_e2.common.state = SB_DISABLED;
4761 sb_data_e2.common.p_func.vf_valid = FALSE;
4762 sb_data_p = (uint32_t *) & sb_data_e2;
4763 data_size = (sizeof(struct hc_status_block_data_e2) /
4766 memset(&sb_data_e1x, 0,
4767 sizeof(struct hc_status_block_data_e1x));
4768 sb_data_e1x.common.state = SB_DISABLED;
4769 sb_data_e1x.common.p_func.vf_valid = FALSE;
4770 sb_data_p = (uint32_t *) & sb_data_e1x;
4771 data_size = (sizeof(struct hc_status_block_data_e1x) /
4775 bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4778 (BAR_CSTRORM_INTMEM + CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id)), 0,
4779 CSTORM_STATUS_BLOCK_SIZE);
4780 bnx2x_fill(sc, (BAR_CSTRORM_INTMEM + CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id)),
4781 0, CSTORM_SYNC_BLOCK_SIZE);
4785 bnx2x_wr_sp_sb_data(struct bnx2x_softc *sc,
4786 struct hc_sp_status_block_data *sp_sb_data)
4791 i < (sizeof(struct hc_sp_status_block_data) / sizeof(uint32_t));
4794 (BAR_CSTRORM_INTMEM +
4795 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(SC_FUNC(sc)) +
4796 (i * sizeof(uint32_t))),
4797 *((uint32_t *) sp_sb_data + i));
4801 static void bnx2x_zero_sp_sb(struct bnx2x_softc *sc)
4803 struct hc_sp_status_block_data sp_sb_data;
4805 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4807 sp_sb_data.state = SB_DISABLED;
4808 sp_sb_data.p_func.vf_valid = FALSE;
4810 bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
4813 (BAR_CSTRORM_INTMEM +
4814 CSTORM_SP_STATUS_BLOCK_OFFSET(SC_FUNC(sc))),
4815 0, CSTORM_SP_STATUS_BLOCK_SIZE);
4817 (BAR_CSTRORM_INTMEM +
4818 CSTORM_SP_SYNC_BLOCK_OFFSET(SC_FUNC(sc))),
4819 0, CSTORM_SP_SYNC_BLOCK_SIZE);
4823 bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, int igu_sb_id,
4826 hc_sm->igu_sb_id = igu_sb_id;
4827 hc_sm->igu_seg_id = igu_seg_id;
4828 hc_sm->timer_value = 0xFF;
4829 hc_sm->time_to_expire = 0xFFFFFFFF;
4832 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
4834 /* zero out state machine indices */
4837 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4840 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4841 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
4842 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
4843 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
4848 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
4849 (SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4852 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
4853 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4854 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
4855 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4856 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
4857 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4858 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
4859 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4863 bnx2x_init_sb(struct bnx2x_softc *sc, rte_iova_t busaddr, int vfid,
4864 uint8_t vf_valid, int fw_sb_id, int igu_sb_id)
4866 struct hc_status_block_data_e2 sb_data_e2;
4867 struct hc_status_block_data_e1x sb_data_e1x;
4868 struct hc_status_block_sm *hc_sm_p;
4869 uint32_t *sb_data_p;
4873 if (CHIP_INT_MODE_IS_BC(sc)) {
4874 igu_seg_id = HC_SEG_ACCESS_NORM;
4876 igu_seg_id = IGU_SEG_ACCESS_NORM;
4879 bnx2x_zero_fp_sb(sc, fw_sb_id);
4881 if (!CHIP_IS_E1x(sc)) {
4882 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4883 sb_data_e2.common.state = SB_ENABLED;
4884 sb_data_e2.common.p_func.pf_id = SC_FUNC(sc);
4885 sb_data_e2.common.p_func.vf_id = vfid;
4886 sb_data_e2.common.p_func.vf_valid = vf_valid;
4887 sb_data_e2.common.p_func.vnic_id = SC_VN(sc);
4888 sb_data_e2.common.same_igu_sb_1b = TRUE;
4889 sb_data_e2.common.host_sb_addr.hi = U64_HI(busaddr);
4890 sb_data_e2.common.host_sb_addr.lo = U64_LO(busaddr);
4891 hc_sm_p = sb_data_e2.common.state_machine;
4892 sb_data_p = (uint32_t *) & sb_data_e2;
4893 data_size = (sizeof(struct hc_status_block_data_e2) /
4895 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
4897 memset(&sb_data_e1x, 0,
4898 sizeof(struct hc_status_block_data_e1x));
4899 sb_data_e1x.common.state = SB_ENABLED;
4900 sb_data_e1x.common.p_func.pf_id = SC_FUNC(sc);
4901 sb_data_e1x.common.p_func.vf_id = 0xff;
4902 sb_data_e1x.common.p_func.vf_valid = FALSE;
4903 sb_data_e1x.common.p_func.vnic_id = SC_VN(sc);
4904 sb_data_e1x.common.same_igu_sb_1b = TRUE;
4905 sb_data_e1x.common.host_sb_addr.hi = U64_HI(busaddr);
4906 sb_data_e1x.common.host_sb_addr.lo = U64_LO(busaddr);
4907 hc_sm_p = sb_data_e1x.common.state_machine;
4908 sb_data_p = (uint32_t *) & sb_data_e1x;
4909 data_size = (sizeof(struct hc_status_block_data_e1x) /
4911 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
4914 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], igu_sb_id, igu_seg_id);
4915 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], igu_sb_id, igu_seg_id);
4917 /* write indices to HW - PCI guarantees endianity of regpairs */
4918 bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4921 static uint8_t bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp)
4923 if (CHIP_IS_E1x(fp->sc)) {
4924 return fp->cl_id + SC_PORT(fp->sc) * ETH_MAX_RX_CLIENTS_E1H;
4931 bnx2x_rx_ustorm_prods_offset(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
4933 uint32_t offset = BAR_USTRORM_INTMEM;
4936 return PXP_VF_ADDR_USDM_QUEUES_START +
4937 (sc->acquire_resp.resc.hw_qid[fp->index] *
4938 sizeof(struct ustorm_queue_zone_data));
4939 } else if (!CHIP_IS_E1x(sc)) {
4940 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
4942 offset += USTORM_RX_PRODS_E1X_OFFSET(SC_PORT(sc), fp->cl_id);
4948 static void bnx2x_init_eth_fp(struct bnx2x_softc *sc, int idx)
4950 struct bnx2x_fastpath *fp = &sc->fp[idx];
4951 uint32_t cids[ECORE_MULTI_TX_COS] = { 0 };
4952 uint32_t q_type = 0;
4958 fp->igu_sb_id = (sc->igu_base_sb + idx + CNIC_SUPPORT(sc));
4959 fp->fw_sb_id = (sc->base_fw_ndsb + idx + CNIC_SUPPORT(sc));
4961 if (CHIP_IS_E1x(sc))
4962 fp->cl_id = SC_L_ID(sc) + idx;
4964 /* want client ID same as IGU SB ID for non-E1 */
4965 fp->cl_id = fp->igu_sb_id;
4966 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
4968 /* setup sb indices */
4969 if (!CHIP_IS_E1x(sc)) {
4970 fp->sb_index_values = fp->status_block.e2_sb->sb.index_values;
4971 fp->sb_running_index = fp->status_block.e2_sb->sb.running_index;
4973 fp->sb_index_values = fp->status_block.e1x_sb->sb.index_values;
4974 fp->sb_running_index =
4975 fp->status_block.e1x_sb->sb.running_index;
4979 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(sc, fp);
4981 fp->rx_cq_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS];
4983 for (cos = 0; cos < sc->max_cos; cos++) {
4986 fp->tx_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0];
4988 /* nothing more for a VF to do */
4993 bnx2x_init_sb(sc, fp->sb_dma.paddr, BNX2X_VF_ID_INVALID, FALSE,
4994 fp->fw_sb_id, fp->igu_sb_id);
4996 bnx2x_update_fp_sb_idx(fp);
4998 /* Configure Queue State object */
4999 rte_bit_relaxed_set32(ECORE_Q_TYPE_HAS_RX, &q_type);
5000 rte_bit_relaxed_set32(ECORE_Q_TYPE_HAS_TX, &q_type);
5002 ecore_init_queue_obj(sc,
5003 &sc->sp_objs[idx].q_obj,
5008 BNX2X_SP(sc, q_rdata),
5009 (rte_iova_t)BNX2X_SP_MAPPING(sc, q_rdata),
5012 /* configure classification DBs */
5013 ecore_init_mac_obj(sc,
5014 &sc->sp_objs[idx].mac_obj,
5018 BNX2X_SP(sc, mac_rdata),
5019 (rte_iova_t)BNX2X_SP_MAPPING(sc, mac_rdata),
5020 ECORE_FILTER_MAC_PENDING, &sc->sp_state,
5021 ECORE_OBJ_TYPE_RX_TX, &sc->macs_pool);
5025 bnx2x_update_rx_prod(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
5026 uint16_t rx_bd_prod, uint16_t rx_cq_prod)
5028 struct ustorm_eth_rx_producers rx_prods;
5031 memset(&rx_prods, 0, sizeof(rx_prods));
5033 /* update producers */
5034 rx_prods.bd_prod = rx_bd_prod;
5035 rx_prods.cqe_prod = rx_cq_prod;
5038 * Make sure that the BD and SGE data is updated before updating the
5039 * producers since FW might read the BD/SGE right after the producer
5041 * This is only applicable for weak-ordered memory model archs such
5042 * as IA-64. The following barrier is also mandatory since FW will
5043 * assumes BDs must have buffers.
5047 for (i = 0; i < (sizeof(rx_prods) / 4); i++) {
5048 REG_WR(sc, (fp->ustorm_rx_prods_offset + (i * 4)),
5049 ((uint32_t *)&rx_prods)[i]);
5052 wmb(); /* keep prod updates ordered */
5055 static void bnx2x_init_rx_rings(struct bnx2x_softc *sc)
5057 struct bnx2x_fastpath *fp;
5059 struct bnx2x_rx_queue *rxq;
5061 for (i = 0; i < sc->num_queues; i++) {
5063 rxq = sc->rx_queues[fp->index];
5065 PMD_RX_LOG(ERR, "RX queue is NULL");
5069 rxq->rx_bd_head = 0;
5070 rxq->rx_bd_tail = rxq->nb_rx_desc;
5071 rxq->rx_cq_head = 0;
5072 rxq->rx_cq_tail = TOTAL_RCQ_ENTRIES(rxq);
5073 *fp->rx_cq_cons_sb = 0;
5076 * Activate the BD ring...
5077 * Warning, this will generate an interrupt (to the TSTORM)
5078 * so this can only be done after the chip is initialized
5080 bnx2x_update_rx_prod(sc, fp, rxq->rx_bd_tail, rxq->rx_cq_tail);
5088 static void bnx2x_init_tx_ring_one(struct bnx2x_fastpath *fp)
5090 struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
5092 fp->tx_db.data.header.header = 1 << DOORBELL_HDR_DB_TYPE_SHIFT;
5093 fp->tx_db.data.zero_fill1 = 0;
5094 fp->tx_db.data.prod = 0;
5097 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
5101 txq->tx_pkt_tail = 0;
5102 txq->tx_pkt_head = 0;
5103 txq->tx_bd_tail = 0;
5104 txq->tx_bd_head = 0;
5107 static void bnx2x_init_tx_rings(struct bnx2x_softc *sc)
5111 for (i = 0; i < sc->num_queues; i++) {
5112 bnx2x_init_tx_ring_one(&sc->fp[i]);
5116 static void bnx2x_init_def_sb(struct bnx2x_softc *sc)
5118 struct host_sp_status_block *def_sb = sc->def_sb;
5119 rte_iova_t mapping = sc->def_sb_dma.paddr;
5120 int igu_sp_sb_index;
5122 int port = SC_PORT(sc);
5123 int func = SC_FUNC(sc);
5124 int reg_offset, reg_offset_en5;
5127 struct hc_sp_status_block_data sp_sb_data;
5129 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5131 if (CHIP_INT_MODE_IS_BC(sc)) {
5132 igu_sp_sb_index = DEF_SB_IGU_ID;
5133 igu_seg_id = HC_SEG_ACCESS_DEF;
5135 igu_sp_sb_index = sc->igu_dsb_id;
5136 igu_seg_id = IGU_SEG_ACCESS_DEF;
5140 section = ((uint64_t) mapping +
5141 offsetof(struct host_sp_status_block, atten_status_block));
5142 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5145 reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5146 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
5148 reg_offset_en5 = (port) ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5149 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0;
5151 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5152 /* take care of sig[0]..sig[4] */
5153 for (sindex = 0; sindex < 4; sindex++) {
5154 sc->attn_group[index].sig[sindex] =
5156 (reg_offset + (sindex * 0x4) +
5160 if (!CHIP_IS_E1x(sc)) {
5162 * enable5 is separate from the rest of the registers,
5163 * and the address skip is 4 and not 16 between the
5166 sc->attn_group[index].sig[4] =
5167 REG_RD(sc, (reg_offset_en5 + (0x4 * index)));
5169 sc->attn_group[index].sig[4] = 0;
5173 if (sc->devinfo.int_block == INT_BLOCK_HC) {
5175 port ? HC_REG_ATTN_MSG1_ADDR_L : HC_REG_ATTN_MSG0_ADDR_L;
5176 REG_WR(sc, reg_offset, U64_LO(section));
5177 REG_WR(sc, (reg_offset + 4), U64_HI(section));
5178 } else if (!CHIP_IS_E1x(sc)) {
5179 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5180 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5183 section = ((uint64_t) mapping +
5184 offsetof(struct host_sp_status_block, sp_sb));
5186 bnx2x_zero_sp_sb(sc);
5188 /* PCI guarantees endianity of regpair */
5189 sp_sb_data.state = SB_ENABLED;
5190 sp_sb_data.host_sb_addr.lo = U64_LO(section);
5191 sp_sb_data.host_sb_addr.hi = U64_HI(section);
5192 sp_sb_data.igu_sb_id = igu_sp_sb_index;
5193 sp_sb_data.igu_seg_id = igu_seg_id;
5194 sp_sb_data.p_func.pf_id = func;
5195 sp_sb_data.p_func.vnic_id = SC_VN(sc);
5196 sp_sb_data.p_func.vf_id = 0xff;
5198 bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
5200 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5203 static void bnx2x_init_sp_ring(struct bnx2x_softc *sc)
5205 atomic_store_rel_long(&sc->cq_spq_left, MAX_SPQ_PENDING);
5206 sc->spq_prod_idx = 0;
5208 &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_ETH_DEF_CONS];
5209 sc->spq_prod_bd = sc->spq;
5210 sc->spq_last_bd = (sc->spq_prod_bd + MAX_SP_DESC_CNT);
5213 static void bnx2x_init_eq_ring(struct bnx2x_softc *sc)
5215 union event_ring_elem *elem;
5218 for (i = 1; i <= NUM_EQ_PAGES; i++) {
5219 elem = &sc->eq[EQ_DESC_CNT_PAGE * i - 1];
5221 elem->next_page.addr.hi = htole32(U64_HI(sc->eq_dma.paddr +
5223 (i % NUM_EQ_PAGES)));
5224 elem->next_page.addr.lo = htole32(U64_LO(sc->eq_dma.paddr +
5226 (i % NUM_EQ_PAGES)));
5230 sc->eq_prod = NUM_EQ_DESC;
5231 sc->eq_cons_sb = &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_EQ_CONS];
5233 atomic_store_rel_long(&sc->eq_spq_left,
5234 (min((MAX_SP_DESC_CNT - MAX_SPQ_PENDING),
5238 static void bnx2x_init_internal_common(struct bnx2x_softc *sc)
5243 * Zero this manually as its initialization is currently missing
5246 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) {
5248 (BAR_USTRORM_INTMEM + USTORM_AGG_DATA_OFFSET + (i * 4)),
5252 if (!CHIP_IS_E1x(sc)) {
5253 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET),
5254 CHIP_INT_MODE_IS_BC(sc) ? HC_IGU_BC_MODE :
5259 static void bnx2x_init_internal(struct bnx2x_softc *sc, uint32_t load_code)
5261 switch (load_code) {
5262 case FW_MSG_CODE_DRV_LOAD_COMMON:
5263 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5264 bnx2x_init_internal_common(sc);
5267 case FW_MSG_CODE_DRV_LOAD_PORT:
5271 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5272 /* internal memory per function is initialized inside bnx2x_pf_init */
5276 PMD_DRV_LOG(NOTICE, sc, "Unknown load_code (0x%x) from MCP",
5283 storm_memset_func_cfg(struct bnx2x_softc *sc,
5284 struct tstorm_eth_function_common_config *tcfg,
5290 addr = (BAR_TSTRORM_INTMEM +
5291 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid));
5292 size = sizeof(struct tstorm_eth_function_common_config);
5293 ecore_storm_memset_struct(sc, addr, size, (uint32_t *) tcfg);
5296 static void bnx2x_func_init(struct bnx2x_softc *sc, struct bnx2x_func_init_params *p)
5298 struct tstorm_eth_function_common_config tcfg = { 0 };
5300 if (CHIP_IS_E1x(sc)) {
5301 storm_memset_func_cfg(sc, &tcfg, p->func_id);
5304 /* Enable the function in the FW */
5305 storm_memset_vf_to_pf(sc, p->func_id, p->pf_id);
5306 storm_memset_func_en(sc, p->func_id, 1);
5309 if (p->func_flgs & FUNC_FLG_SPQ) {
5310 storm_memset_spq_addr(sc, p->spq_map, p->func_id);
5312 (XSEM_REG_FAST_MEMORY +
5313 XSTORM_SPQ_PROD_OFFSET(p->func_id)), p->spq_prod);
5318 * Calculates the sum of vn_min_rates.
5319 * It's needed for further normalizing of the min_rates.
5321 * sum of vn_min_rates.
5323 * 0 - if all the min_rates are 0.
5324 * In the later case fainess algorithm should be deactivated.
5325 * If all min rates are not zero then those that are zeroes will be set to 1.
5327 static void bnx2x_calc_vn_min(struct bnx2x_softc *sc, struct cmng_init_input *input)
5330 uint32_t vn_min_rate;
5334 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5335 vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5336 vn_min_rate = (((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
5337 FUNC_MF_CFG_MIN_BW_SHIFT) * 100);
5339 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5340 /* skip hidden VNs */
5342 } else if (!vn_min_rate) {
5343 /* If min rate is zero - set it to 100 */
5344 vn_min_rate = DEF_MIN_RATE;
5349 input->vnic_min_rate[vn] = vn_min_rate;
5352 /* if ETS or all min rates are zeros - disable fairness */
5354 input->flags.cmng_enables &= ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5356 input->flags.cmng_enables |= CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5361 bnx2x_extract_max_cfg(__rte_unused struct bnx2x_softc *sc, uint32_t mf_cfg)
5363 uint16_t max_cfg = ((mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
5364 FUNC_MF_CFG_MAX_BW_SHIFT);
5367 PMD_DRV_LOG(DEBUG, sc,
5368 "Max BW configured to 0 - using 100 instead");
5376 bnx2x_calc_vn_max(struct bnx2x_softc *sc, int vn, struct cmng_init_input *input)
5378 uint16_t vn_max_rate;
5379 uint32_t vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5382 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5385 max_cfg = bnx2x_extract_max_cfg(sc, vn_cfg);
5388 /* max_cfg in percents of linkspeed */
5390 ((sc->link_vars.line_speed * max_cfg) / 100);
5391 } else { /* SD modes */
5392 /* max_cfg is absolute in 100Mb units */
5393 vn_max_rate = (max_cfg * 100);
5397 input->vnic_max_rate[vn] = vn_max_rate;
5401 bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg, uint8_t cmng_type)
5403 struct cmng_init_input input;
5406 memset(&input, 0, sizeof(struct cmng_init_input));
5408 input.port_rate = sc->link_vars.line_speed;
5410 if (cmng_type == CMNG_FNS_MINMAX) {
5411 /* read mf conf from shmem */
5413 bnx2x_read_mf_cfg(sc);
5416 /* get VN min rate and enable fairness if not 0 */
5417 bnx2x_calc_vn_min(sc, &input);
5419 /* get VN max rate */
5421 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5422 bnx2x_calc_vn_max(sc, vn, &input);
5426 /* always enable rate shaping and fairness */
5427 input.flags.cmng_enables |= CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
5429 ecore_init_cmng(&input, &sc->cmng);
5434 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc)
5436 if (CHIP_REV_IS_SLOW(sc)) {
5437 return CMNG_FNS_NONE;
5441 return CMNG_FNS_MINMAX;
5444 return CMNG_FNS_NONE;
5448 storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng, uint8_t port)
5455 addr = (BAR_XSTRORM_INTMEM + XSTORM_CMNG_PER_PORT_VARS_OFFSET(port));
5456 size = sizeof(struct cmng_struct_per_port);
5457 ecore_storm_memset_struct(sc, addr, size, (uint32_t *) & cmng->port);
5459 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5460 func = func_by_vn(sc, vn);
5462 addr = (BAR_XSTRORM_INTMEM +
5463 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func));
5464 size = sizeof(struct rate_shaping_vars_per_vn);
5465 ecore_storm_memset_struct(sc, addr, size,
5466 (uint32_t *) & cmng->
5467 vnic.vnic_max_rate[vn]);
5469 addr = (BAR_XSTRORM_INTMEM +
5470 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func));
5471 size = sizeof(struct fairness_vars_per_vn);
5472 ecore_storm_memset_struct(sc, addr, size,
5473 (uint32_t *) & cmng->
5474 vnic.vnic_min_rate[vn]);
5478 static void bnx2x_pf_init(struct bnx2x_softc *sc)
5480 struct bnx2x_func_init_params func_init;
5481 struct event_ring_data eq_data;
5484 memset(&eq_data, 0, sizeof(struct event_ring_data));
5485 memset(&func_init, 0, sizeof(struct bnx2x_func_init_params));
5487 if (!CHIP_IS_E1x(sc)) {
5488 /* reset IGU PF statistics: MSIX + ATTN */
5491 (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5492 (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5493 ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5497 (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5498 (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5499 (BNX2X_IGU_STAS_MSG_PF_CNT * 4) +
5500 ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5504 /* function setup flags */
5505 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
5507 func_init.func_flgs = flags;
5508 func_init.pf_id = SC_FUNC(sc);
5509 func_init.func_id = SC_FUNC(sc);
5510 func_init.spq_map = sc->spq_dma.paddr;
5511 func_init.spq_prod = sc->spq_prod_idx;
5513 bnx2x_func_init(sc, &func_init);
5515 memset(&sc->cmng, 0, sizeof(struct cmng_struct_per_port));
5518 * Congestion management values depend on the link rate.
5519 * There is no active link so initial link rate is set to 10Gbps.
5520 * When the link comes up the congestion management values are
5521 * re-calculated according to the actual link rate.
5523 sc->link_vars.line_speed = SPEED_10000;
5524 bnx2x_cmng_fns_init(sc, TRUE, bnx2x_get_cmng_fns_mode(sc));
5526 /* Only the PMF sets the HW */
5528 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
5531 /* init Event Queue - PCI bus guarantees correct endainity */
5532 eq_data.base_addr.hi = U64_HI(sc->eq_dma.paddr);
5533 eq_data.base_addr.lo = U64_LO(sc->eq_dma.paddr);
5534 eq_data.producer = sc->eq_prod;
5535 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
5536 eq_data.sb_id = DEF_SB_ID;
5537 storm_memset_eq_data(sc, &eq_data, SC_FUNC(sc));
5540 static void bnx2x_hc_int_enable(struct bnx2x_softc *sc)
5542 int port = SC_PORT(sc);
5543 uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5544 uint32_t val = REG_RD(sc, addr);
5545 uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5546 || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5547 uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5548 uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5551 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5552 HC_CONFIG_0_REG_INT_LINE_EN_0);
5553 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5554 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5556 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
5559 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
5560 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5561 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5562 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5564 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5565 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5566 HC_CONFIG_0_REG_INT_LINE_EN_0 |
5567 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5569 REG_WR(sc, addr, val);
5571 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
5574 REG_WR(sc, addr, val);
5576 /* ensure that HC_CONFIG is written before leading/trailing edge config */
5579 /* init leading/trailing edge */
5581 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5583 /* enable nig and gpio3 attention */
5590 REG_WR(sc, (HC_REG_TRAILING_EDGE_0 + port * 8), val);
5591 REG_WR(sc, (HC_REG_LEADING_EDGE_0 + port * 8), val);
5593 /* make sure that interrupts are indeed enabled from here on */
5597 static void bnx2x_igu_int_enable(struct bnx2x_softc *sc)
5600 uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5601 || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5602 uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5603 uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5605 val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5608 val &= ~(IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5609 val |= (IGU_PF_CONF_MSI_MSIX_EN | IGU_PF_CONF_ATTN_BIT_EN);
5611 val |= IGU_PF_CONF_SINGLE_ISR_EN;
5614 val &= ~IGU_PF_CONF_INT_LINE_EN;
5615 val |= (IGU_PF_CONF_MSI_MSIX_EN |
5616 IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5618 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
5619 val |= (IGU_PF_CONF_INT_LINE_EN |
5620 IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5623 /* clean previous status - need to configure igu prior to ack */
5624 if ((!msix) || single_msix) {
5625 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5629 val |= IGU_PF_CONF_FUNC_EN;
5631 PMD_DRV_LOG(DEBUG, sc, "write 0x%x to IGU mode %s",
5632 val, ((msix) ? "MSI-X" : ((msi) ? "MSI" : "INTx")));
5634 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5638 /* init leading/trailing edge */
5640 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5642 /* enable nig and gpio3 attention */
5649 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
5650 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
5652 /* make sure that interrupts are indeed enabled from here on */
5656 static void bnx2x_int_enable(struct bnx2x_softc *sc)
5658 if (sc->devinfo.int_block == INT_BLOCK_HC) {
5659 bnx2x_hc_int_enable(sc);
5661 bnx2x_igu_int_enable(sc);
5665 static void bnx2x_hc_int_disable(struct bnx2x_softc *sc)
5667 int port = SC_PORT(sc);
5668 uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5669 uint32_t val = REG_RD(sc, addr);
5671 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5672 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5673 HC_CONFIG_0_REG_INT_LINE_EN_0 | HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5674 /* flush all outstanding writes */
5677 REG_WR(sc, addr, val);
5678 if (REG_RD(sc, addr) != val) {
5679 PMD_DRV_LOG(ERR, sc, "proper val not read from HC IGU!");
5683 static void bnx2x_igu_int_disable(struct bnx2x_softc *sc)
5685 uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5687 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
5688 IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_ATTN_BIT_EN);
5690 PMD_DRV_LOG(DEBUG, sc, "write %x to IGU", val);
5692 /* flush all outstanding writes */
5695 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5696 if (REG_RD(sc, IGU_REG_PF_CONFIGURATION) != val) {
5697 PMD_DRV_LOG(ERR, sc, "proper val not read from IGU!");
5701 static void bnx2x_int_disable(struct bnx2x_softc *sc)
5703 if (sc->devinfo.int_block == INT_BLOCK_HC) {
5704 bnx2x_hc_int_disable(sc);
5706 bnx2x_igu_int_disable(sc);
5710 static void bnx2x_nic_init(struct bnx2x_softc *sc, int load_code)
5714 PMD_INIT_FUNC_TRACE(sc);
5716 for (i = 0; i < sc->num_queues; i++) {
5717 bnx2x_init_eth_fp(sc, i);
5720 rmb(); /* ensure status block indices were read */
5722 bnx2x_init_rx_rings(sc);
5723 bnx2x_init_tx_rings(sc);
5726 bnx2x_memset_stats(sc);
5730 /* initialize MOD_ABS interrupts */
5731 elink_init_mod_abs_int(sc, &sc->link_vars,
5732 sc->devinfo.chip_id,
5733 sc->devinfo.shmem_base,
5734 sc->devinfo.shmem2_base, SC_PORT(sc));
5736 bnx2x_init_def_sb(sc);
5737 bnx2x_update_dsb_idx(sc);
5738 bnx2x_init_sp_ring(sc);
5739 bnx2x_init_eq_ring(sc);
5740 bnx2x_init_internal(sc, load_code);
5742 bnx2x_stats_init(sc);
5744 /* flush all before enabling interrupts */
5747 bnx2x_int_enable(sc);
5749 /* check for SPIO5 */
5750 bnx2x_attn_int_deasserted0(sc,
5752 (MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
5754 AEU_INPUTS_ATTN_BITS_SPIO5);
5757 static void bnx2x_init_objs(struct bnx2x_softc *sc)
5759 /* mcast rules must be added to tx if tx switching is enabled */
5760 ecore_obj_type o_type;
5761 if (sc->flags & BNX2X_TX_SWITCHING)
5762 o_type = ECORE_OBJ_TYPE_RX_TX;
5764 o_type = ECORE_OBJ_TYPE_RX;
5766 /* RX_MODE controlling object */
5767 ecore_init_rx_mode_obj(sc, &sc->rx_mode_obj);
5769 /* multicast configuration controlling object */
5770 ecore_init_mcast_obj(sc,
5776 BNX2X_SP(sc, mcast_rdata),
5777 (rte_iova_t)BNX2X_SP_MAPPING(sc, mcast_rdata),
5778 ECORE_FILTER_MCAST_PENDING,
5779 &sc->sp_state, o_type);
5781 /* Setup CAM credit pools */
5782 ecore_init_mac_credit_pool(sc,
5785 CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5786 VNICS_PER_PATH(sc));
5788 ecore_init_vlan_credit_pool(sc,
5790 SC_ABS_FUNC(sc) >> 1,
5791 CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5792 VNICS_PER_PATH(sc));
5794 /* RSS configuration object */
5795 ecore_init_rss_config_obj(sc, &sc->rss_conf_obj, sc->fp->cl_id,
5796 sc->fp->index, SC_FUNC(sc), SC_FUNC(sc),
5797 BNX2X_SP(sc, rss_rdata),
5798 (rte_iova_t)BNX2X_SP_MAPPING(sc, rss_rdata),
5799 ECORE_FILTER_RSS_CONF_PENDING, &sc->sp_state,
5804 * Initialize the function. This must be called before sending CLIENT_SETUP
5805 * for the first client.
5807 static int bnx2x_func_start(struct bnx2x_softc *sc)
5809 struct ecore_func_state_params func_params = { NULL };
5810 struct ecore_func_start_params *start_params =
5811 &func_params.params.start;
5813 /* Prepare parameters for function state transitions */
5814 rte_bit_relaxed_set32(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
5816 func_params.f_obj = &sc->func_obj;
5817 func_params.cmd = ECORE_F_CMD_START;
5819 /* Function parameters */
5820 start_params->mf_mode = sc->devinfo.mf_info.mf_mode;
5821 start_params->sd_vlan_tag = OVLAN(sc);
5823 if (CHIP_IS_E2(sc) || CHIP_IS_E3(sc)) {
5824 start_params->network_cos_mode = STATIC_COS;
5825 } else { /* CHIP_IS_E1X */
5826 start_params->network_cos_mode = FW_WRR;
5829 return ecore_func_state_change(sc, &func_params);
5832 static int bnx2x_set_power_state(struct bnx2x_softc *sc, uint8_t state)
5836 /* If there is no power capability, silently succeed */
5837 if (!(sc->devinfo.pcie_cap_flags & BNX2X_PM_CAPABLE_FLAG)) {
5838 PMD_DRV_LOG(INFO, sc, "No power capability");
5842 pci_read(sc, (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS), &pmcsr,
5848 (sc->devinfo.pcie_pm_cap_reg +
5850 ((pmcsr & ~PCIM_PSTAT_DMASK) | PCIM_PSTAT_PME));
5852 if (pmcsr & PCIM_PSTAT_DMASK) {
5853 /* delay required during transition out of D3hot */
5860 /* don't shut down the power for emulation and FPGA */
5861 if (CHIP_REV_IS_SLOW(sc)) {
5865 pmcsr &= ~PCIM_PSTAT_DMASK;
5866 pmcsr |= PCIM_PSTAT_D3;
5869 pmcsr |= PCIM_PSTAT_PMEENABLE;
5873 (sc->devinfo.pcie_pm_cap_reg +
5874 PCIR_POWER_STATUS), pmcsr);
5877 * No more memory access after this point until device is brought back
5883 PMD_DRV_LOG(NOTICE, sc, "Can't support PCI power state = %d",
5891 /* return true if succeeded to acquire the lock */
5892 static uint8_t bnx2x_trylock_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
5894 uint32_t lock_status;
5895 uint32_t resource_bit = (1 << resource);
5896 int func = SC_FUNC(sc);
5897 uint32_t hw_lock_control_reg;
5899 /* Validating that the resource is within range */
5900 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
5901 PMD_DRV_LOG(INFO, sc,
5902 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)",
5903 resource, HW_LOCK_MAX_RESOURCE_VALUE);
5908 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func * 8);
5910 hw_lock_control_reg =
5911 (MISC_REG_DRIVER_CONTROL_7 + (func - 6) * 8);
5914 /* try to acquire the lock */
5915 REG_WR(sc, hw_lock_control_reg + 4, resource_bit);
5916 lock_status = REG_RD(sc, hw_lock_control_reg);
5917 if (lock_status & resource_bit) {
5921 PMD_DRV_LOG(NOTICE, sc, "Failed to get a resource lock 0x%x", resource);
5927 * Get the recovery leader resource id according to the engine this function
5928 * belongs to. Currently only only 2 engines is supported.
5930 static int bnx2x_get_leader_lock_resource(struct bnx2x_softc *sc)
5933 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
5935 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
5939 /* try to acquire a leader lock for current engine */
5940 static uint8_t bnx2x_trylock_leader_lock(struct bnx2x_softc *sc)
5942 return bnx2x_trylock_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5945 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc)
5947 return bnx2x_release_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5950 /* close gates #2, #3 and #4 */
5951 static void bnx2x_set_234_gates(struct bnx2x_softc *sc, uint8_t close)
5955 /* gates #2 and #4a are closed/opened */
5957 REG_WR(sc, PXP_REG_HST_DISCARD_DOORBELLS, ! !close);
5959 REG_WR(sc, PXP_REG_HST_DISCARD_INTERNAL_WRITES, ! !close);
5962 if (CHIP_IS_E1x(sc)) {
5963 /* prevent interrupts from HC on both ports */
5964 val = REG_RD(sc, HC_REG_CONFIG_1);
5966 REG_WR(sc, HC_REG_CONFIG_1, (val & ~(uint32_t)
5967 HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5969 REG_WR(sc, HC_REG_CONFIG_1,
5970 (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5972 val = REG_RD(sc, HC_REG_CONFIG_0);
5974 REG_WR(sc, HC_REG_CONFIG_0, (val & ~(uint32_t)
5975 HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5977 REG_WR(sc, HC_REG_CONFIG_0,
5978 (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5981 /* Prevent incoming interrupts in IGU */
5982 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
5985 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5987 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5989 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5991 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5997 /* poll for pending writes bit, it should get cleared in no more than 1s */
5998 static int bnx2x_er_poll_igu_vq(struct bnx2x_softc *sc)
6000 uint32_t cnt = 1000;
6001 uint32_t pend_bits = 0;
6004 pend_bits = REG_RD(sc, IGU_REG_PENDING_BITS_STATUS);
6006 if (pend_bits == 0) {
6011 } while (cnt-- > 0);
6014 PMD_DRV_LOG(NOTICE, sc, "Still pending IGU requests bits=0x%08x!",
6022 #define SHARED_MF_CLP_MAGIC 0x80000000 /* 'magic' bit */
6024 static void bnx2x_clp_reset_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
6026 /* Do some magic... */
6027 uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
6028 *magic_val = val & SHARED_MF_CLP_MAGIC;
6029 MFCFG_WR(sc, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
6032 /* restore the value of the 'magic' bit */
6033 static void bnx2x_clp_reset_done(struct bnx2x_softc *sc, uint32_t magic_val)
6035 /* Restore the 'magic' bit value... */
6036 uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
6037 MFCFG_WR(sc, shared_mf_config.clp_mb,
6038 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
6041 /* prepare for MCP reset, takes care of CLP configurations */
6042 static void bnx2x_reset_mcp_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
6045 uint32_t validity_offset;
6047 /* set `magic' bit in order to save MF config */
6048 bnx2x_clp_reset_prep(sc, magic_val);
6050 /* get shmem offset */
6051 shmem = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
6053 offsetof(struct shmem_region, validity_map[SC_PORT(sc)]);
6055 /* Clear validity map flags */
6057 REG_WR(sc, shmem + validity_offset, 0);
6061 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
6062 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
6064 static void bnx2x_mcp_wait_one(struct bnx2x_softc *sc)
6066 /* special handling for emulation and FPGA (10 times longer) */
6067 if (CHIP_REV_IS_SLOW(sc)) {
6068 DELAY((MCP_ONE_TIMEOUT * 10) * 1000);
6070 DELAY((MCP_ONE_TIMEOUT) * 1000);
6074 /* initialize shmem_base and waits for validity signature to appear */
6075 static int bnx2x_init_shmem(struct bnx2x_softc *sc)
6081 sc->devinfo.shmem_base =
6082 sc->link_params.shmem_base =
6083 REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
6085 if (sc->devinfo.shmem_base) {
6086 val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
6087 if (val & SHR_MEM_VALIDITY_MB)
6091 bnx2x_mcp_wait_one(sc);
6093 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
6095 PMD_DRV_LOG(NOTICE, sc, "BAD MCP validity signature");
6100 static int bnx2x_reset_mcp_comp(struct bnx2x_softc *sc, uint32_t magic_val)
6102 int rc = bnx2x_init_shmem(sc);
6104 /* Restore the `magic' bit value */
6105 bnx2x_clp_reset_done(sc, magic_val);
6110 static void bnx2x_pxp_prep(struct bnx2x_softc *sc)
6112 REG_WR(sc, PXP2_REG_RD_START_INIT, 0);
6113 REG_WR(sc, PXP2_REG_RQ_RBC_DONE, 0);
6118 * Reset the whole chip except for:
6120 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by one reset bit)
6122 * - MISC (including AEU)
6126 static void bnx2x_process_kill_chip_reset(struct bnx2x_softc *sc, uint8_t global)
6128 uint32_t not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
6129 uint32_t global_bits2, stay_reset2;
6132 * Bits that have to be set in reset_mask2 if we want to reset 'global'
6133 * (per chip) blocks.
6136 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
6137 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
6140 * Don't reset the following blocks.
6141 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
6142 * reset, as in 4 port device they might still be owned
6143 * by the MCP (there is only one leader per path).
6146 MISC_REGISTERS_RESET_REG_1_RST_HC |
6147 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
6148 MISC_REGISTERS_RESET_REG_1_RST_PXP;
6151 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
6152 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
6153 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
6154 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
6155 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
6156 MISC_REGISTERS_RESET_REG_2_RST_GRC |
6157 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
6158 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
6159 MISC_REGISTERS_RESET_REG_2_RST_ATC |
6160 MISC_REGISTERS_RESET_REG_2_PGLC |
6161 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
6162 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
6163 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
6164 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
6165 MISC_REGISTERS_RESET_REG_2_UMAC0 | MISC_REGISTERS_RESET_REG_2_UMAC1;
6168 * Keep the following blocks in reset:
6169 * - all xxMACs are handled by the elink code.
6172 MISC_REGISTERS_RESET_REG_2_XMAC |
6173 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
6175 /* Full reset masks according to the chip */
6176 reset_mask1 = 0xffffffff;
6178 if (CHIP_IS_E1H(sc))
6179 reset_mask2 = 0x1ffff;
6180 else if (CHIP_IS_E2(sc))
6181 reset_mask2 = 0xfffff;
6182 else /* CHIP_IS_E3 */
6183 reset_mask2 = 0x3ffffff;
6185 /* Don't reset global blocks unless we need to */
6187 reset_mask2 &= ~global_bits2;
6190 * In case of attention in the QM, we need to reset PXP
6191 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
6192 * because otherwise QM reset would release 'close the gates' shortly
6193 * before resetting the PXP, then the PSWRQ would send a write
6194 * request to PGLUE. Then when PXP is reset, PGLUE would try to
6195 * read the payload data from PSWWR, but PSWWR would not
6196 * respond. The write queue in PGLUE would stuck, dmae commands
6197 * would not return. Therefore it's important to reset the second
6198 * reset register (containing the
6199 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
6200 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
6203 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
6204 reset_mask2 & (~not_reset_mask2));
6206 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6207 reset_mask1 & (~not_reset_mask1));
6212 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
6213 reset_mask2 & (~stay_reset2));
6218 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
6222 static int bnx2x_process_kill(struct bnx2x_softc *sc, uint8_t global)
6226 uint32_t sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
6227 uint32_t tags_63_32 = 0;
6229 /* Empty the Tetris buffer, wait for 1s */
6231 sr_cnt = REG_RD(sc, PXP2_REG_RD_SR_CNT);
6232 blk_cnt = REG_RD(sc, PXP2_REG_RD_BLK_CNT);
6233 port_is_idle_0 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_0);
6234 port_is_idle_1 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_1);
6235 pgl_exp_rom2 = REG_RD(sc, PXP2_REG_PGL_EXP_ROM2);
6236 if (CHIP_IS_E3(sc)) {
6237 tags_63_32 = REG_RD(sc, PGLUE_B_REG_TAGS_63_32);
6240 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
6241 ((port_is_idle_0 & 0x1) == 0x1) &&
6242 ((port_is_idle_1 & 0x1) == 0x1) &&
6243 (pgl_exp_rom2 == 0xffffffff) &&
6244 (!CHIP_IS_E3(sc) || (tags_63_32 == 0xffffffff)))
6247 } while (cnt-- > 0);
6250 PMD_DRV_LOG(NOTICE, sc,
6251 "ERROR: Tetris buffer didn't get empty or there "
6252 "are still outstanding read requests after 1s! "
6253 "sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, "
6254 "port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x",
6255 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
6262 /* Close gates #2, #3 and #4 */
6263 bnx2x_set_234_gates(sc, TRUE);
6265 /* Poll for IGU VQs for 57712 and newer chips */
6266 if (!CHIP_IS_E1x(sc) && bnx2x_er_poll_igu_vq(sc)) {
6270 /* clear "unprepared" bit */
6271 REG_WR(sc, MISC_REG_UNPREPARED, 0);
6274 /* Make sure all is written to the chip before the reset */
6278 * Wait for 1ms to empty GLUE and PCI-E core queues,
6279 * PSWHST, GRC and PSWRD Tetris buffer.
6283 /* Prepare to chip reset: */
6286 bnx2x_reset_mcp_prep(sc, &val);
6293 /* reset the chip */
6294 bnx2x_process_kill_chip_reset(sc, global);
6297 /* Recover after reset: */
6299 if (global && bnx2x_reset_mcp_comp(sc, val)) {
6303 /* Open the gates #2, #3 and #4 */
6304 bnx2x_set_234_gates(sc, FALSE);
6309 static int bnx2x_leader_reset(struct bnx2x_softc *sc)
6312 uint8_t global = bnx2x_reset_is_global(sc);
6316 * If not going to reset MCP, load "fake" driver to reset HW while
6317 * driver is owner of the HW.
6319 if (!global && !BNX2X_NOMCP(sc)) {
6320 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
6321 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
6323 PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
6325 goto exit_leader_reset;
6328 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
6329 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
6330 PMD_DRV_LOG(NOTICE, sc,
6331 "MCP unexpected response, aborting");
6333 goto exit_leader_reset2;
6336 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
6338 PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
6340 goto exit_leader_reset2;
6344 /* try to recover after the failure */
6345 if (bnx2x_process_kill(sc, global)) {
6346 PMD_DRV_LOG(NOTICE, sc, "Something bad occurred on engine %d!",
6349 goto exit_leader_reset2;
6353 * Clear the RESET_IN_PROGRESS and RESET_GLOBAL bits and update the driver
6356 bnx2x_set_reset_done(sc);
6358 bnx2x_clear_reset_global(sc);
6363 /* unload "fake driver" if it was loaded */
6364 if (!global &&!BNX2X_NOMCP(sc)) {
6365 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
6366 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
6372 bnx2x_release_leader_lock(sc);
6379 * prepare INIT transition, parameters configured:
6380 * - HC configuration
6381 * - Queue's CDU context
6384 bnx2x_pf_q_prep_init(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6385 struct ecore_queue_init_params *init_params)
6388 int cxt_index, cxt_offset;
6390 rte_bit_relaxed_set32(ECORE_Q_FLG_HC, &init_params->rx.flags);
6391 rte_bit_relaxed_set32(ECORE_Q_FLG_HC, &init_params->tx.flags);
6393 rte_bit_relaxed_set32(ECORE_Q_FLG_HC_EN, &init_params->rx.flags);
6394 rte_bit_relaxed_set32(ECORE_Q_FLG_HC_EN, &init_params->tx.flags);
6397 init_params->rx.hc_rate =
6398 sc->hc_rx_ticks ? (1000000 / sc->hc_rx_ticks) : 0;
6399 init_params->tx.hc_rate =
6400 sc->hc_tx_ticks ? (1000000 / sc->hc_tx_ticks) : 0;
6403 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = fp->fw_sb_id;
6405 /* CQ index among the SB indices */
6406 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6407 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
6409 /* set maximum number of COSs supported by this queue */
6410 init_params->max_cos = sc->max_cos;
6412 /* set the context pointers queue object */
6413 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
6414 cxt_index = fp->index / ILT_PAGE_CIDS;
6415 cxt_offset = fp->index - (cxt_index * ILT_PAGE_CIDS);
6416 init_params->cxts[cos] =
6417 &sc->context[cxt_index].vcxt[cxt_offset].eth;
6421 /* set flags that are common for the Tx-only and not normal connections */
6422 static unsigned long
6423 bnx2x_get_common_flags(struct bnx2x_softc *sc, uint8_t zero_stats)
6427 /* PF driver will always initialize the Queue to an ACTIVE state */
6428 rte_bit_relaxed_set32(ECORE_Q_FLG_ACTIVE, &flags);
6431 * tx only connections collect statistics (on the same index as the
6432 * parent connection). The statistics are zeroed when the parent
6433 * connection is initialized.
6436 rte_bit_relaxed_set32(ECORE_Q_FLG_STATS, &flags);
6438 rte_bit_relaxed_set32(ECORE_Q_FLG_ZERO_STATS, &flags);
6442 * tx only connections can support tx-switching, though their
6443 * CoS-ness doesn't survive the loopback
6445 if (sc->flags & BNX2X_TX_SWITCHING) {
6446 rte_bit_relaxed_set32(ECORE_Q_FLG_TX_SWITCH, &flags);
6449 rte_bit_relaxed_set32(ECORE_Q_FLG_PCSUM_ON_PKT, &flags);
6454 static unsigned long bnx2x_get_q_flags(struct bnx2x_softc *sc, uint8_t leading)
6459 rte_bit_relaxed_set32(ECORE_Q_FLG_OV, &flags);
6463 rte_bit_relaxed_set32(ECORE_Q_FLG_LEADING_RSS, &flags);
6464 rte_bit_relaxed_set32(ECORE_Q_FLG_MCAST, &flags);
6467 rte_bit_relaxed_set32(ECORE_Q_FLG_VLAN, &flags);
6469 /* merge with common flags */
6470 return flags | bnx2x_get_common_flags(sc, TRUE);
6474 bnx2x_pf_q_prep_general(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6475 struct ecore_general_setup_params *gen_init, uint8_t cos)
6477 gen_init->stat_id = bnx2x_stats_id(fp);
6478 gen_init->spcl_id = fp->cl_id;
6479 gen_init->mtu = sc->mtu;
6480 gen_init->cos = cos;
6484 bnx2x_pf_rx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6485 struct rxq_pause_params *pause,
6486 struct ecore_rxq_setup_params *rxq_init)
6488 struct bnx2x_rx_queue *rxq;
6490 rxq = sc->rx_queues[fp->index];
6492 PMD_RX_LOG(ERR, "RX queue is NULL");
6496 pause->bd_th_lo = BD_TH_LO(sc);
6497 pause->bd_th_hi = BD_TH_HI(sc);
6499 pause->rcq_th_lo = RCQ_TH_LO(sc);
6500 pause->rcq_th_hi = RCQ_TH_HI(sc);
6502 /* validate rings have enough entries to cross high thresholds */
6503 if (sc->dropless_fc &&
6504 pause->bd_th_hi + FW_PREFETCH_CNT > sc->rx_ring_size) {
6505 PMD_DRV_LOG(WARNING, sc, "rx bd ring threshold limit");
6508 if (sc->dropless_fc &&
6509 pause->rcq_th_hi + FW_PREFETCH_CNT > USABLE_RCQ_ENTRIES(rxq)) {
6510 PMD_DRV_LOG(WARNING, sc, "rcq ring threshold limit");
6516 rxq_init->dscr_map = (rte_iova_t)rxq->rx_ring_phys_addr;
6517 rxq_init->rcq_map = (rte_iova_t)rxq->cq_ring_phys_addr;
6518 rxq_init->rcq_np_map = (rte_iova_t)(rxq->cq_ring_phys_addr +
6522 * This should be a maximum number of data bytes that may be
6523 * placed on the BD (not including paddings).
6525 rxq_init->buf_sz = (fp->rx_buf_size - IP_HEADER_ALIGNMENT_PADDING);
6527 rxq_init->cl_qzone_id = fp->cl_qzone_id;
6528 rxq_init->rss_engine_id = SC_FUNC(sc);
6529 rxq_init->mcast_engine_id = SC_FUNC(sc);
6531 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
6532 rxq_init->fw_sb_id = fp->fw_sb_id;
6534 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6537 * configure silent vlan removal
6538 * if multi function mode is afex, then mask default vlan
6540 if (IS_MF_AFEX(sc)) {
6541 rxq_init->silent_removal_value =
6542 sc->devinfo.mf_info.afex_def_vlan_tag;
6543 rxq_init->silent_removal_mask = EVL_VLID_MASK;
6548 bnx2x_pf_tx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6549 struct ecore_txq_setup_params *txq_init, uint8_t cos)
6551 struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
6554 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
6557 txq_init->dscr_map = (rte_iova_t)txq->tx_ring_phys_addr;
6558 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
6559 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
6560 txq_init->fw_sb_id = fp->fw_sb_id;
6563 * set the TSS leading client id for TX classfication to the
6564 * leading RSS client id
6566 txq_init->tss_leading_cl_id = BNX2X_FP(sc, 0, cl_id);
6570 * This function performs 2 steps in a queue state machine:
6575 bnx2x_setup_queue(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp, uint8_t leading)
6577 struct ecore_queue_state_params q_params = { NULL };
6578 struct ecore_queue_setup_params *setup_params = &q_params.params.setup;
6581 PMD_DRV_LOG(DEBUG, sc, "setting up queue %d", fp->index);
6583 bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6585 q_params.q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
6587 /* we want to wait for completion in this context */
6588 rte_bit_relaxed_set32(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
6590 /* prepare the INIT parameters */
6591 bnx2x_pf_q_prep_init(sc, fp, &q_params.params.init);
6593 /* Set the command */
6594 q_params.cmd = ECORE_Q_CMD_INIT;
6596 /* Change the state to INIT */
6597 rc = ecore_queue_state_change(sc, &q_params);
6599 PMD_DRV_LOG(NOTICE, sc, "Queue(%d) INIT failed", fp->index);
6603 PMD_DRV_LOG(DEBUG, sc, "init complete");
6605 /* now move the Queue to the SETUP state */
6606 memset(setup_params, 0, sizeof(*setup_params));
6608 /* set Queue flags */
6609 setup_params->flags = bnx2x_get_q_flags(sc, leading);
6611 /* set general SETUP parameters */
6612 bnx2x_pf_q_prep_general(sc, fp, &setup_params->gen_params,
6613 FIRST_TX_COS_INDEX);
6615 bnx2x_pf_rx_q_prep(sc, fp,
6616 &setup_params->pause_params,
6617 &setup_params->rxq_params);
6619 bnx2x_pf_tx_q_prep(sc, fp, &setup_params->txq_params, FIRST_TX_COS_INDEX);
6621 /* Set the command */
6622 q_params.cmd = ECORE_Q_CMD_SETUP;
6624 /* change the state to SETUP */
6625 rc = ecore_queue_state_change(sc, &q_params);
6627 PMD_DRV_LOG(NOTICE, sc, "Queue(%d) SETUP failed", fp->index);
6634 static int bnx2x_setup_leading(struct bnx2x_softc *sc)
6637 return bnx2x_setup_queue(sc, &sc->fp[0], TRUE);
6639 return bnx2x_vf_setup_queue(sc, &sc->fp[0], TRUE);
6643 bnx2x_config_rss_pf(struct bnx2x_softc *sc, struct ecore_rss_config_obj *rss_obj,
6644 uint8_t config_hash)
6646 struct ecore_config_rss_params params = { NULL };
6650 * Although RSS is meaningless when there is a single HW queue we
6651 * still need it enabled in order to have HW Rx hash generated.
6654 params.rss_obj = rss_obj;
6656 rte_bit_relaxed_set32(RAMROD_COMP_WAIT, ¶ms.ramrod_flags);
6658 rte_bit_relaxed_set32(ECORE_RSS_MODE_REGULAR, ¶ms.rss_flags);
6660 /* RSS configuration */
6661 rte_bit_relaxed_set32(ECORE_RSS_IPV4, ¶ms.rss_flags);
6662 rte_bit_relaxed_set32(ECORE_RSS_IPV4_TCP, ¶ms.rss_flags);
6663 rte_bit_relaxed_set32(ECORE_RSS_IPV6, ¶ms.rss_flags);
6664 rte_bit_relaxed_set32(ECORE_RSS_IPV6_TCP, ¶ms.rss_flags);
6665 if (rss_obj->udp_rss_v4) {
6666 rte_bit_relaxed_set32(ECORE_RSS_IPV4_UDP, ¶ms.rss_flags);
6668 if (rss_obj->udp_rss_v6) {
6669 rte_bit_relaxed_set32(ECORE_RSS_IPV6_UDP, ¶ms.rss_flags);
6673 params.rss_result_mask = MULTI_MASK;
6675 rte_memcpy(params.ind_table, rss_obj->ind_table,
6676 sizeof(params.ind_table));
6680 for (i = 0; i < sizeof(params.rss_key) / 4; i++) {
6681 params.rss_key[i] = (uint32_t) rte_rand();
6684 rte_bit_relaxed_set32(ECORE_RSS_SET_SRCH, ¶ms.rss_flags);
6688 return ecore_config_rss(sc, ¶ms);
6690 return bnx2x_vf_config_rss(sc, ¶ms);
6693 static int bnx2x_config_rss_eth(struct bnx2x_softc *sc, uint8_t config_hash)
6695 return bnx2x_config_rss_pf(sc, &sc->rss_conf_obj, config_hash);
6698 static int bnx2x_init_rss_pf(struct bnx2x_softc *sc)
6700 uint8_t num_eth_queues = BNX2X_NUM_ETH_QUEUES(sc);
6704 * Prepare the initial contents of the indirection table if
6707 for (i = 0; i < sizeof(sc->rss_conf_obj.ind_table); i++) {
6708 sc->rss_conf_obj.ind_table[i] =
6709 (sc->fp->cl_id + (i % num_eth_queues));
6713 sc->rss_conf_obj.udp_rss_v4 = sc->rss_conf_obj.udp_rss_v6 = 1;
6717 * For 57711 SEARCHER configuration (rss_keys) is
6718 * per-port, so if explicit configuration is needed, do it only
6721 * For 57712 and newer it's a per-function configuration.
6723 return bnx2x_config_rss_eth(sc, sc->port.pmf || !CHIP_IS_E1x(sc));
6727 bnx2x_set_mac_one(struct bnx2x_softc *sc, uint8_t * mac,
6728 struct ecore_vlan_mac_obj *obj, uint8_t set, int mac_type,
6729 uint32_t *ramrod_flags)
6731 struct ecore_vlan_mac_ramrod_params ramrod_param;
6734 memset(&ramrod_param, 0, sizeof(ramrod_param));
6736 /* fill in general parameters */
6737 ramrod_param.vlan_mac_obj = obj;
6738 ramrod_param.ramrod_flags = *ramrod_flags;
6740 /* fill a user request section if needed */
6741 if (!rte_bit_relaxed_get32(RAMROD_CONT, ramrod_flags)) {
6742 rte_memcpy(ramrod_param.user_req.u.mac.mac, mac,
6745 rte_bit_relaxed_set32(mac_type,
6746 &ramrod_param.user_req.vlan_mac_flags);
6748 /* Set the command: ADD or DEL */
6749 ramrod_param.user_req.cmd = (set) ? ECORE_VLAN_MAC_ADD :
6753 rc = ecore_config_vlan_mac(sc, &ramrod_param);
6755 if (rc == ECORE_EXISTS) {
6756 PMD_DRV_LOG(INFO, sc, "Failed to schedule ADD operations (EEXIST)");
6757 /* do not treat adding same MAC as error */
6759 } else if (rc < 0) {
6760 PMD_DRV_LOG(ERR, sc,
6761 "%s MAC failed (%d)", (set ? "Set" : "Delete"), rc);
6767 static int bnx2x_set_eth_mac(struct bnx2x_softc *sc, uint8_t set)
6769 uint32_t ramrod_flags = 0;
6771 PMD_DRV_LOG(DEBUG, sc, "Adding Ethernet MAC");
6773 rte_bit_relaxed_set32(RAMROD_COMP_WAIT, &ramrod_flags);
6775 /* Eth MAC is set on RSS leading client (fp[0]) */
6776 return bnx2x_set_mac_one(sc, sc->link_params.mac_addr,
6777 &sc->sp_objs->mac_obj,
6778 set, ECORE_ETH_MAC, &ramrod_flags);
6781 static int bnx2x_get_cur_phy_idx(struct bnx2x_softc *sc)
6783 uint32_t sel_phy_idx = 0;
6785 if (sc->link_params.num_phys <= 1) {
6786 return ELINK_INT_PHY;
6789 if (sc->link_vars.link_up) {
6790 sel_phy_idx = ELINK_EXT_PHY1;
6791 /* In case link is SERDES, check if the ELINK_EXT_PHY2 is the one */
6792 if ((sc->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
6793 (sc->link_params.phy[ELINK_EXT_PHY2].supported &
6794 ELINK_SUPPORTED_FIBRE))
6795 sel_phy_idx = ELINK_EXT_PHY2;
6797 switch (elink_phy_selection(&sc->link_params)) {
6798 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6799 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
6800 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6801 sel_phy_idx = ELINK_EXT_PHY1;
6803 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
6804 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6805 sel_phy_idx = ELINK_EXT_PHY2;
6813 static int bnx2x_get_link_cfg_idx(struct bnx2x_softc *sc)
6815 uint32_t sel_phy_idx = bnx2x_get_cur_phy_idx(sc);
6818 * The selected activated PHY is always after swapping (in case PHY
6819 * swapping is enabled). So when swapping is enabled, we need to reverse
6823 if (sc->link_params.multi_phy_config & PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
6824 if (sel_phy_idx == ELINK_EXT_PHY1)
6825 sel_phy_idx = ELINK_EXT_PHY2;
6826 else if (sel_phy_idx == ELINK_EXT_PHY2)
6827 sel_phy_idx = ELINK_EXT_PHY1;
6830 return ELINK_LINK_CONFIG_IDX(sel_phy_idx);
6833 static void bnx2x_set_requested_fc(struct bnx2x_softc *sc)
6836 * Initialize link parameters structure variables
6837 * It is recommended to turn off RX FC for jumbo frames
6838 * for better performance
6840 if (CHIP_IS_E1x(sc) && (sc->mtu > 5000)) {
6841 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_TX;
6843 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_BOTH;
6847 static void bnx2x_calc_fc_adv(struct bnx2x_softc *sc)
6849 uint8_t cfg_idx = bnx2x_get_link_cfg_idx(sc);
6850 switch (sc->link_vars.ieee_fc &
6851 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
6852 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
6854 sc->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
6858 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
6859 sc->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
6863 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
6864 sc->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
6869 static uint16_t bnx2x_get_mf_speed(struct bnx2x_softc *sc)
6871 uint16_t line_speed = sc->link_vars.line_speed;
6873 uint16_t maxCfg = bnx2x_extract_max_cfg(sc,
6875 mf_info.mf_config[SC_VN
6878 /* calculate the current MAX line speed limit for the MF devices */
6880 line_speed = (line_speed * maxCfg) / 100;
6881 } else { /* SD mode */
6882 uint16_t vn_max_rate = maxCfg * 100;
6884 if (vn_max_rate < line_speed) {
6885 line_speed = vn_max_rate;
6894 bnx2x_fill_report_data(struct bnx2x_softc *sc, struct bnx2x_link_report_data *data)
6896 uint16_t line_speed = bnx2x_get_mf_speed(sc);
6898 memset(data, 0, sizeof(*data));
6900 /* fill the report data with the effective line speed */
6901 data->line_speed = line_speed;
6904 if (!sc->link_vars.link_up || (sc->flags & BNX2X_MF_FUNC_DIS)) {
6905 rte_bit_relaxed_set32(BNX2X_LINK_REPORT_LINK_DOWN,
6906 &data->link_report_flags);
6910 if (sc->link_vars.duplex == DUPLEX_FULL) {
6911 rte_bit_relaxed_set32(BNX2X_LINK_REPORT_FULL_DUPLEX,
6912 &data->link_report_flags);
6915 /* Rx Flow Control is ON */
6916 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_RX) {
6917 rte_bit_relaxed_set32(BNX2X_LINK_REPORT_RX_FC_ON,
6918 &data->link_report_flags);
6921 /* Tx Flow Control is ON */
6922 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
6923 rte_bit_relaxed_set32(BNX2X_LINK_REPORT_TX_FC_ON,
6924 &data->link_report_flags);
6928 /* report link status to OS, should be called under phy_lock */
6929 static void bnx2x_link_report_locked(struct bnx2x_softc *sc)
6931 struct bnx2x_link_report_data cur_data;
6935 bnx2x_read_mf_cfg(sc);
6938 /* Read the current link report info */
6939 bnx2x_fill_report_data(sc, &cur_data);
6941 /* Don't report link down or exactly the same link status twice */
6942 if (!memcmp(&cur_data, &sc->last_reported_link, sizeof(cur_data)) ||
6943 (rte_bit_relaxed_get32(BNX2X_LINK_REPORT_LINK_DOWN,
6944 &sc->last_reported_link.link_report_flags) &&
6945 rte_bit_relaxed_get32(BNX2X_LINK_REPORT_LINK_DOWN,
6946 &cur_data.link_report_flags))) {
6950 ELINK_DEBUG_P2(sc, "Change in link status : cur_data = %x, last_reported_link = %x",
6951 cur_data.link_report_flags,
6952 sc->last_reported_link.link_report_flags);
6956 ELINK_DEBUG_P1(sc, "link status change count = %x", sc->link_cnt);
6957 /* report new link params and remember the state for the next time */
6958 rte_memcpy(&sc->last_reported_link, &cur_data, sizeof(cur_data));
6960 if (rte_bit_relaxed_get32(BNX2X_LINK_REPORT_LINK_DOWN,
6961 &cur_data.link_report_flags)) {
6962 ELINK_DEBUG_P0(sc, "NIC Link is Down");
6964 __rte_unused const char *duplex;
6965 __rte_unused const char *flow;
6967 if (rte_bit_relaxed_test_and_clear32
6968 (BNX2X_LINK_REPORT_FULL_DUPLEX,
6969 &cur_data.link_report_flags)) {
6971 ELINK_DEBUG_P0(sc, "link set to full duplex");
6974 ELINK_DEBUG_P0(sc, "link set to half duplex");
6978 * Handle the FC at the end so that only these flags would be
6979 * possibly set. This way we may easily check if there is no FC
6982 if (cur_data.link_report_flags) {
6983 if (rte_bit_relaxed_get32
6984 (BNX2X_LINK_REPORT_RX_FC_ON,
6985 &cur_data.link_report_flags) &&
6986 rte_bit_relaxed_get32(BNX2X_LINK_REPORT_TX_FC_ON,
6987 &cur_data.link_report_flags)) {
6988 flow = "ON - receive & transmit";
6989 } else if (rte_bit_relaxed_get32
6990 (BNX2X_LINK_REPORT_RX_FC_ON,
6991 &cur_data.link_report_flags) &&
6992 !rte_bit_relaxed_get32
6993 (BNX2X_LINK_REPORT_TX_FC_ON,
6994 &cur_data.link_report_flags)) {
6995 flow = "ON - receive";
6996 } else if (!rte_bit_relaxed_get32
6997 (BNX2X_LINK_REPORT_RX_FC_ON,
6998 &cur_data.link_report_flags) &&
6999 rte_bit_relaxed_get32
7000 (BNX2X_LINK_REPORT_TX_FC_ON,
7001 &cur_data.link_report_flags)) {
7002 flow = "ON - transmit";
7004 flow = "none"; /* possible? */
7010 PMD_DRV_LOG(INFO, sc,
7011 "NIC Link is Up, %d Mbps %s duplex, Flow control: %s",
7012 cur_data.line_speed, duplex, flow);
7017 bnx2x_link_report(struct bnx2x_softc *sc)
7019 bnx2x_acquire_phy_lock(sc);
7020 bnx2x_link_report_locked(sc);
7021 bnx2x_release_phy_lock(sc);
7024 void bnx2x_link_status_update(struct bnx2x_softc *sc)
7026 if (sc->state != BNX2X_STATE_OPEN) {
7030 if (IS_PF(sc) && !CHIP_REV_IS_SLOW(sc)) {
7031 elink_link_status_update(&sc->link_params, &sc->link_vars);
7033 sc->port.supported[0] |= (ELINK_SUPPORTED_10baseT_Half |
7034 ELINK_SUPPORTED_10baseT_Full |
7035 ELINK_SUPPORTED_100baseT_Half |
7036 ELINK_SUPPORTED_100baseT_Full |
7037 ELINK_SUPPORTED_1000baseT_Full |
7038 ELINK_SUPPORTED_2500baseX_Full |
7039 ELINK_SUPPORTED_10000baseT_Full |
7040 ELINK_SUPPORTED_TP |
7041 ELINK_SUPPORTED_FIBRE |
7042 ELINK_SUPPORTED_Autoneg |
7043 ELINK_SUPPORTED_Pause |
7044 ELINK_SUPPORTED_Asym_Pause);
7045 sc->port.advertising[0] = sc->port.supported[0];
7047 sc->link_params.sc = sc;
7048 sc->link_params.port = SC_PORT(sc);
7049 sc->link_params.req_duplex[0] = DUPLEX_FULL;
7050 sc->link_params.req_flow_ctrl[0] = ELINK_FLOW_CTRL_NONE;
7051 sc->link_params.req_line_speed[0] = SPEED_10000;
7052 sc->link_params.speed_cap_mask[0] = 0x7f0000;
7053 sc->link_params.switch_cfg = ELINK_SWITCH_CFG_10G;
7055 if (CHIP_REV_IS_FPGA(sc)) {
7056 sc->link_vars.mac_type = ELINK_MAC_TYPE_EMAC;
7057 sc->link_vars.line_speed = ELINK_SPEED_1000;
7058 sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
7059 LINK_STATUS_SPEED_AND_DUPLEX_1000TFD);
7061 sc->link_vars.mac_type = ELINK_MAC_TYPE_BMAC;
7062 sc->link_vars.line_speed = ELINK_SPEED_10000;
7063 sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
7064 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
7067 sc->link_vars.link_up = 1;
7069 sc->link_vars.duplex = DUPLEX_FULL;
7070 sc->link_vars.flow_ctrl = ELINK_FLOW_CTRL_NONE;
7074 NIG_REG_EGRESS_DRAIN0_MODE +
7075 sc->link_params.port * 4, 0);
7076 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7077 bnx2x_link_report(sc);
7082 if (sc->link_vars.link_up) {
7083 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7085 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
7087 bnx2x_link_report(sc);
7089 bnx2x_link_report_locked(sc);
7090 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7094 static int bnx2x_initial_phy_init(struct bnx2x_softc *sc, int load_mode)
7096 int rc, cfg_idx = bnx2x_get_link_cfg_idx(sc);
7097 uint16_t req_line_speed = sc->link_params.req_line_speed[cfg_idx];
7098 struct elink_params *lp = &sc->link_params;
7100 bnx2x_set_requested_fc(sc);
7102 bnx2x_acquire_phy_lock(sc);
7104 if (load_mode == LOAD_DIAG) {
7105 lp->loopback_mode = ELINK_LOOPBACK_XGXS;
7106 /* Prefer doing PHY loopback at 10G speed, if possible */
7107 if (lp->req_line_speed[cfg_idx] < ELINK_SPEED_10000) {
7108 if (lp->speed_cap_mask[cfg_idx] &
7109 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
7110 lp->req_line_speed[cfg_idx] = ELINK_SPEED_10000;
7112 lp->req_line_speed[cfg_idx] = ELINK_SPEED_1000;
7117 if (load_mode == LOAD_LOOPBACK_EXT) {
7118 lp->loopback_mode = ELINK_LOOPBACK_EXT;
7121 rc = elink_phy_init(&sc->link_params, &sc->link_vars);
7123 bnx2x_release_phy_lock(sc);
7125 bnx2x_calc_fc_adv(sc);
7127 if (sc->link_vars.link_up) {
7128 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7129 bnx2x_link_report(sc);
7132 sc->link_params.req_line_speed[cfg_idx] = req_line_speed;
7136 /* update flags in shmem */
7138 bnx2x_update_drv_flags(struct bnx2x_softc *sc, uint32_t flags, uint32_t set)
7142 if (SHMEM2_HAS(sc, drv_flags)) {
7143 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7144 drv_flags = SHMEM2_RD(sc, drv_flags);
7149 drv_flags &= ~flags;
7152 SHMEM2_WR(sc, drv_flags, drv_flags);
7154 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7158 /* periodic timer callout routine, only runs when the interface is up */
7159 void bnx2x_periodic_callout(struct bnx2x_softc *sc)
7161 if ((sc->state != BNX2X_STATE_OPEN) ||
7162 (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_STOP)) {
7163 PMD_DRV_LOG(DEBUG, sc, "periodic callout exit (state=0x%x)",
7167 if (!CHIP_REV_IS_SLOW(sc)) {
7169 * This barrier is needed to ensure the ordering between the writing
7170 * to the sc->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
7175 bnx2x_acquire_phy_lock(sc);
7176 elink_period_func(&sc->link_params, &sc->link_vars);
7177 bnx2x_release_phy_lock(sc);
7181 if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7182 int mb_idx = SC_FW_MB_IDX(sc);
7186 ++sc->fw_drv_pulse_wr_seq;
7187 sc->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
7189 drv_pulse = sc->fw_drv_pulse_wr_seq;
7190 bnx2x_drv_pulse(sc);
7192 mcp_pulse = (SHMEM_RD(sc, func_mb[mb_idx].mcp_pulse_mb) &
7193 MCP_PULSE_SEQ_MASK);
7196 * The delta between driver pulse and mcp response should
7197 * be 1 (before mcp response) or 0 (after mcp response).
7199 if ((drv_pulse != mcp_pulse) &&
7200 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
7201 /* someone lost a heartbeat... */
7202 PMD_DRV_LOG(ERR, sc,
7203 "drv_pulse (0x%x) != mcp_pulse (0x%x)",
7204 drv_pulse, mcp_pulse);
7210 /* start the controller */
7211 static __rte_noinline
7212 int bnx2x_nic_load(struct bnx2x_softc *sc)
7215 uint32_t load_code = 0;
7218 PMD_INIT_FUNC_TRACE(sc);
7220 sc->state = BNX2X_STATE_OPENING_WAITING_LOAD;
7223 /* must be called before memory allocation and HW init */
7224 bnx2x_ilt_set_info(sc);
7227 bnx2x_set_fp_rx_buf_size(sc);
7230 if (bnx2x_alloc_mem(sc) != 0) {
7231 sc->state = BNX2X_STATE_CLOSED;
7233 goto bnx2x_nic_load_error0;
7237 /* allocate the host hardware/software hsi structures */
7238 if (bnx2x_alloc_hsi_mem(sc) != 0) {
7239 PMD_DRV_LOG(ERR, sc, "bnx2x_alloc_hsi_mem was failed");
7240 sc->state = BNX2X_STATE_CLOSED;
7242 goto bnx2x_nic_load_error0;
7245 if (bnx2x_alloc_fw_stats_mem(sc) != 0) {
7246 sc->state = BNX2X_STATE_CLOSED;
7248 goto bnx2x_nic_load_error0;
7252 rc = bnx2x_vf_init(sc);
7254 sc->state = BNX2X_STATE_ERROR;
7255 goto bnx2x_nic_load_error0;
7260 /* set pf load just before approaching the MCP */
7261 bnx2x_set_pf_load(sc);
7263 /* if MCP exists send load request and analyze response */
7264 if (!BNX2X_NOMCP(sc)) {
7265 /* attempt to load pf */
7266 if (bnx2x_nic_load_request(sc, &load_code) != 0) {
7267 sc->state = BNX2X_STATE_CLOSED;
7269 goto bnx2x_nic_load_error1;
7272 /* what did the MCP say? */
7273 if (bnx2x_nic_load_analyze_req(sc, load_code) != 0) {
7274 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7275 sc->state = BNX2X_STATE_CLOSED;
7277 goto bnx2x_nic_load_error2;
7280 PMD_DRV_LOG(INFO, sc, "Device has no MCP!");
7281 load_code = bnx2x_nic_load_no_mcp(sc);
7284 /* mark PMF if applicable */
7285 bnx2x_nic_load_pmf(sc, load_code);
7287 /* Init Function state controlling object */
7288 bnx2x_init_func_obj(sc);
7291 if (bnx2x_init_hw(sc, load_code) != 0) {
7292 PMD_DRV_LOG(NOTICE, sc, "HW init failed");
7293 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7294 sc->state = BNX2X_STATE_CLOSED;
7296 goto bnx2x_nic_load_error2;
7300 bnx2x_nic_init(sc, load_code);
7302 /* Init per-function objects */
7304 bnx2x_init_objs(sc);
7306 /* set AFEX default VLAN tag to an invalid value */
7307 sc->devinfo.mf_info.afex_def_vlan_tag = -1;
7309 sc->state = BNX2X_STATE_OPENING_WAITING_PORT;
7310 rc = bnx2x_func_start(sc);
7312 PMD_DRV_LOG(NOTICE, sc, "Function start failed!");
7313 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7314 sc->state = BNX2X_STATE_ERROR;
7315 goto bnx2x_nic_load_error3;
7318 /* send LOAD_DONE command to MCP */
7319 if (!BNX2X_NOMCP(sc)) {
7321 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7323 PMD_DRV_LOG(NOTICE, sc,
7324 "MCP response failure, aborting");
7325 sc->state = BNX2X_STATE_ERROR;
7327 goto bnx2x_nic_load_error3;
7332 rc = bnx2x_setup_leading(sc);
7334 PMD_DRV_LOG(NOTICE, sc, "Setup leading failed!");
7335 sc->state = BNX2X_STATE_ERROR;
7336 goto bnx2x_nic_load_error3;
7339 FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, i) {
7341 rc = bnx2x_setup_queue(sc, &sc->fp[i], FALSE);
7342 else /* IS_VF(sc) */
7343 rc = bnx2x_vf_setup_queue(sc, &sc->fp[i], FALSE);
7346 PMD_DRV_LOG(NOTICE, sc, "Queue(%d) setup failed", i);
7347 sc->state = BNX2X_STATE_ERROR;
7348 goto bnx2x_nic_load_error3;
7352 rc = bnx2x_init_rss_pf(sc);
7354 PMD_DRV_LOG(NOTICE, sc, "PF RSS init failed");
7355 sc->state = BNX2X_STATE_ERROR;
7356 goto bnx2x_nic_load_error3;
7359 /* now when Clients are configured we are ready to work */
7360 sc->state = BNX2X_STATE_OPEN;
7362 /* Configure a ucast MAC */
7364 rc = bnx2x_set_eth_mac(sc, TRUE);
7365 } else { /* IS_VF(sc) */
7366 rc = bnx2x_vf_set_mac(sc, TRUE);
7370 PMD_DRV_LOG(NOTICE, sc, "Setting Ethernet MAC failed");
7371 sc->state = BNX2X_STATE_ERROR;
7372 goto bnx2x_nic_load_error3;
7376 rc = bnx2x_initial_phy_init(sc, LOAD_OPEN);
7378 sc->state = BNX2X_STATE_ERROR;
7379 goto bnx2x_nic_load_error3;
7383 sc->link_params.feature_config_flags &=
7384 ~ELINK_FEATURE_CONFIG_BOOT_FROM_SAN;
7387 switch (LOAD_OPEN) {
7393 case LOAD_LOOPBACK_EXT:
7394 sc->state = BNX2X_STATE_DIAG;
7402 bnx2x_update_drv_flags(sc, 1 << DRV_FLAGS_PORT_MASK, 0);
7404 bnx2x_link_status_update(sc);
7407 if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
7408 /* mark driver is loaded in shmem2 */
7409 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
7410 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
7412 DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED |
7413 DRV_FLAGS_CAPABILITIES_LOADED_L2));
7416 /* start fast path */
7417 /* Initialize Rx filter */
7418 bnx2x_set_rx_mode(sc);
7420 /* wait for all pending SP commands to complete */
7421 if (IS_PF(sc) && !bnx2x_wait_sp_comp(sc, ~0x0U)) {
7422 PMD_DRV_LOG(NOTICE, sc, "Timeout waiting for all SPs to complete!");
7423 bnx2x_periodic_stop(sc);
7424 bnx2x_nic_unload(sc, UNLOAD_CLOSE, FALSE);
7428 PMD_DRV_LOG(DEBUG, sc, "NIC successfully loaded");
7432 bnx2x_nic_load_error3:
7435 bnx2x_int_disable_sync(sc, 1);
7437 /* clean out queued objects */
7438 bnx2x_squeeze_objects(sc);
7441 bnx2x_nic_load_error2:
7443 if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7444 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
7445 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
7450 bnx2x_nic_load_error1:
7452 /* clear pf_load status, as it was already set */
7454 bnx2x_clear_pf_load(sc);
7457 bnx2x_nic_load_error0:
7459 bnx2x_free_fw_stats_mem(sc);
7460 bnx2x_free_hsi_mem(sc);
7467 * Handles controller initialization.
7469 int bnx2x_init(struct bnx2x_softc *sc)
7471 int other_engine = SC_PATH(sc) ? 0 : 1;
7472 uint8_t other_load_status, load_status;
7473 uint8_t global = FALSE;
7476 /* Check if the driver is still running and bail out if it is. */
7477 if (sc->state != BNX2X_STATE_CLOSED) {
7478 PMD_DRV_LOG(DEBUG, sc, "Init called while driver is running!");
7480 goto bnx2x_init_done;
7483 bnx2x_set_power_state(sc, PCI_PM_D0);
7486 * If parity occurred during the unload, then attentions and/or
7487 * RECOVERY_IN_PROGRESS may still be set. If so we want the first function
7488 * loaded on the current engine to complete the recovery. Parity recovery
7489 * is only relevant for PF driver.
7492 other_load_status = bnx2x_get_load_status(sc, other_engine);
7493 load_status = bnx2x_get_load_status(sc, SC_PATH(sc));
7495 if (!bnx2x_reset_is_done(sc, SC_PATH(sc)) ||
7496 bnx2x_chk_parity_attn(sc, &global, TRUE)) {
7499 * If there are attentions and they are in global blocks, set
7500 * the GLOBAL_RESET bit regardless whether it will be this
7501 * function that will complete the recovery or not.
7504 bnx2x_set_reset_global(sc);
7508 * Only the first function on the current engine should try
7509 * to recover in open. In case of attentions in global blocks
7510 * only the first in the chip should try to recover.
7513 && (!global ||!other_load_status))
7514 && bnx2x_trylock_leader_lock(sc)
7515 && !bnx2x_leader_reset(sc)) {
7516 PMD_DRV_LOG(INFO, sc,
7517 "Recovered during init");
7521 /* recovery has failed... */
7522 bnx2x_set_power_state(sc, PCI_PM_D3hot);
7524 sc->recovery_state = BNX2X_RECOVERY_FAILED;
7526 PMD_DRV_LOG(NOTICE, sc,
7527 "Recovery flow hasn't properly "
7528 "completed yet, try again later. "
7529 "If you still see this message after a "
7530 "few retries then power cycle is required.");
7533 goto bnx2x_init_done;
7538 sc->recovery_state = BNX2X_RECOVERY_DONE;
7540 rc = bnx2x_nic_load(sc);
7545 PMD_DRV_LOG(NOTICE, sc, "Initialization failed, "
7546 "stack notified driver is NOT running!");
7552 static void bnx2x_get_function_num(struct bnx2x_softc *sc)
7557 * Read the ME register to get the function number. The ME register
7558 * holds the relative-function number and absolute-function number. The
7559 * absolute-function number appears only in E2 and above. Before that
7560 * these bits always contained zero, therefore we cannot blindly use them.
7563 val = REG_RD(sc, BAR_ME_REGISTER);
7566 (uint8_t) ((val & ME_REG_PF_NUM) >> ME_REG_PF_NUM_SHIFT);
7568 (uint8_t) ((val & ME_REG_ABS_PF_NUM) >> ME_REG_ABS_PF_NUM_SHIFT) &
7571 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7572 sc->pfunc_abs = ((sc->pfunc_rel << 1) | sc->path_id);
7574 sc->pfunc_abs = (sc->pfunc_rel | sc->path_id);
7577 PMD_DRV_LOG(DEBUG, sc,
7578 "Relative function %d, Absolute function %d, Path %d",
7579 sc->pfunc_rel, sc->pfunc_abs, sc->path_id);
7582 static uint32_t bnx2x_get_shmem_mf_cfg_base(struct bnx2x_softc *sc)
7584 uint32_t shmem2_size;
7586 uint32_t mf_cfg_offset_value;
7589 offset = (SHMEM_ADDR(sc, func_mb) +
7590 (MAX_FUNC_NUM * sizeof(struct drv_func_mb)));
7593 if (sc->devinfo.shmem2_base != 0) {
7594 shmem2_size = SHMEM2_RD(sc, size);
7595 if (shmem2_size > offsetof(struct shmem2_region, mf_cfg_addr)) {
7596 mf_cfg_offset_value = SHMEM2_RD(sc, mf_cfg_addr);
7597 if (SHMEM_MF_CFG_ADDR_NONE != mf_cfg_offset_value) {
7598 offset = mf_cfg_offset_value;
7606 static uint32_t bnx2x_pcie_capability_read(struct bnx2x_softc *sc, int reg)
7609 struct bnx2x_pci_cap *caps;
7611 /* ensure PCIe capability is enabled */
7612 caps = pci_find_cap(sc, PCIY_EXPRESS, BNX2X_PCI_CAP);
7614 PMD_DRV_LOG(DEBUG, sc, "Found PCIe capability: "
7615 "id=0x%04X type=0x%04X addr=0x%08X",
7616 caps->id, caps->type, caps->addr);
7617 pci_read(sc, (caps->addr + reg), &ret, 2);
7621 PMD_DRV_LOG(WARNING, sc, "PCIe capability NOT FOUND!!!");
7626 static uint8_t bnx2x_is_pcie_pending(struct bnx2x_softc *sc)
7628 return bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_STA) &
7629 PCIM_EXP_STA_TRANSACTION_PND;
7633 * Walk the PCI capabiites list for the device to find what features are
7634 * supported. These capabilites may be enabled/disabled by firmware so it's
7635 * best to walk the list rather than make assumptions.
7637 static void bnx2x_probe_pci_caps(struct bnx2x_softc *sc)
7639 PMD_INIT_FUNC_TRACE(sc);
7641 struct bnx2x_pci_cap *caps;
7642 uint16_t link_status;
7645 /* check if PCI Power Management is enabled */
7646 caps = pci_find_cap(sc, PCIY_PMG, BNX2X_PCI_CAP);
7648 PMD_DRV_LOG(DEBUG, sc, "Found PM capability: "
7649 "id=0x%04X type=0x%04X addr=0x%08X",
7650 caps->id, caps->type, caps->addr);
7652 sc->devinfo.pcie_cap_flags |= BNX2X_PM_CAPABLE_FLAG;
7653 sc->devinfo.pcie_pm_cap_reg = caps->addr;
7656 link_status = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_LINK_STA);
7658 sc->devinfo.pcie_link_speed = (link_status & PCIM_LINK_STA_SPEED);
7659 sc->devinfo.pcie_link_width =
7660 ((link_status & PCIM_LINK_STA_WIDTH) >> 4);
7662 PMD_DRV_LOG(DEBUG, sc, "PCIe link speed=%d width=%d",
7663 sc->devinfo.pcie_link_speed, sc->devinfo.pcie_link_width);
7665 sc->devinfo.pcie_cap_flags |= BNX2X_PCIE_CAPABLE_FLAG;
7667 /* check if MSI capability is enabled */
7668 caps = pci_find_cap(sc, PCIY_MSI, BNX2X_PCI_CAP);
7670 PMD_DRV_LOG(DEBUG, sc, "Found MSI capability at 0x%04x", reg);
7672 sc->devinfo.pcie_cap_flags |= BNX2X_MSI_CAPABLE_FLAG;
7673 sc->devinfo.pcie_msi_cap_reg = caps->addr;
7676 /* check if MSI-X capability is enabled */
7677 caps = pci_find_cap(sc, PCIY_MSIX, BNX2X_PCI_CAP);
7679 PMD_DRV_LOG(DEBUG, sc, "Found MSI-X capability at 0x%04x", reg);
7681 sc->devinfo.pcie_cap_flags |= BNX2X_MSIX_CAPABLE_FLAG;
7682 sc->devinfo.pcie_msix_cap_reg = caps->addr;
7686 static int bnx2x_get_shmem_mf_cfg_info_sd(struct bnx2x_softc *sc)
7688 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7691 /* get the outer vlan if we're in switch-dependent mode */
7693 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7694 mf_info->ext_id = (uint16_t) val;
7696 mf_info->multi_vnics_mode = 1;
7698 if (!VALID_OVLAN(mf_info->ext_id)) {
7699 PMD_DRV_LOG(NOTICE, sc, "Invalid VLAN (%d)", mf_info->ext_id);
7703 /* get the capabilities */
7704 if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK) ==
7705 FUNC_MF_CFG_PROTOCOL_ISCSI) {
7706 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ISCSI;
7707 } else if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK)
7708 == FUNC_MF_CFG_PROTOCOL_FCOE) {
7709 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_FCOE;
7711 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ETHERNET;
7714 mf_info->vnics_per_port =
7715 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7720 static uint32_t bnx2x_get_shmem_ext_proto_support_flags(struct bnx2x_softc *sc)
7722 uint32_t retval = 0;
7725 val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7727 if (val & MACP_FUNC_CFG_FLAGS_ENABLED) {
7728 if (val & MACP_FUNC_CFG_FLAGS_ETHERNET) {
7729 retval |= MF_PROTO_SUPPORT_ETHERNET;
7731 if (val & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
7732 retval |= MF_PROTO_SUPPORT_ISCSI;
7734 if (val & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
7735 retval |= MF_PROTO_SUPPORT_FCOE;
7742 static int bnx2x_get_shmem_mf_cfg_info_si(struct bnx2x_softc *sc)
7744 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7748 * There is no outer vlan if we're in switch-independent mode.
7749 * If the mac is valid then assume multi-function.
7752 val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7754 mf_info->multi_vnics_mode = ((val & MACP_FUNC_CFG_FLAGS_MASK) != 0);
7756 mf_info->mf_protos_supported =
7757 bnx2x_get_shmem_ext_proto_support_flags(sc);
7759 mf_info->vnics_per_port =
7760 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7765 static int bnx2x_get_shmem_mf_cfg_info_niv(struct bnx2x_softc *sc)
7767 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7769 uint32_t func_config;
7770 uint32_t niv_config;
7772 mf_info->multi_vnics_mode = 1;
7774 e1hov_tag = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7775 func_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7776 niv_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].afex_config);
7779 (uint16_t) ((e1hov_tag & FUNC_MF_CFG_E1HOV_TAG_MASK) >>
7780 FUNC_MF_CFG_E1HOV_TAG_SHIFT);
7782 mf_info->default_vlan =
7783 (uint16_t) ((e1hov_tag & FUNC_MF_CFG_AFEX_VLAN_MASK) >>
7784 FUNC_MF_CFG_AFEX_VLAN_SHIFT);
7786 mf_info->niv_allowed_priorities =
7787 (uint8_t) ((niv_config & FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
7788 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT);
7790 mf_info->niv_default_cos =
7791 (uint8_t) ((func_config & FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
7792 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT);
7794 mf_info->afex_vlan_mode =
7795 ((niv_config & FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
7796 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT);
7798 mf_info->niv_mba_enabled =
7799 ((niv_config & FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK) >>
7800 FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT);
7802 mf_info->mf_protos_supported =
7803 bnx2x_get_shmem_ext_proto_support_flags(sc);
7805 mf_info->vnics_per_port =
7806 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7811 static int bnx2x_check_valid_mf_cfg(struct bnx2x_softc *sc)
7813 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7820 /* various MF mode sanity checks... */
7822 if (mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_HIDE) {
7823 PMD_DRV_LOG(NOTICE, sc,
7824 "Enumerated function %d is marked as hidden",
7829 if ((mf_info->vnics_per_port > 1) && !mf_info->multi_vnics_mode) {
7830 PMD_DRV_LOG(NOTICE, sc, "vnics_per_port=%d multi_vnics_mode=%d",
7831 mf_info->vnics_per_port, mf_info->multi_vnics_mode);
7835 if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7836 /* vnic id > 0 must have valid ovlan in switch-dependent mode */
7837 if ((SC_VN(sc) > 0) && !VALID_OVLAN(OVLAN(sc))) {
7838 PMD_DRV_LOG(NOTICE, sc, "mf_mode=SD vnic_id=%d ovlan=%d",
7839 SC_VN(sc), OVLAN(sc));
7843 if (!VALID_OVLAN(OVLAN(sc)) && mf_info->multi_vnics_mode) {
7844 PMD_DRV_LOG(NOTICE, sc,
7845 "mf_mode=SD multi_vnics_mode=%d ovlan=%d",
7846 mf_info->multi_vnics_mode, OVLAN(sc));
7851 * Verify all functions are either MF or SF mode. If MF, make sure
7852 * sure that all non-hidden functions have a valid ovlan. If SF,
7853 * make sure that all non-hidden functions have an invalid ovlan.
7855 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7856 mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7857 ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7858 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE) &&
7859 (((mf_info->multi_vnics_mode)
7860 && !VALID_OVLAN(ovlan1))
7861 || ((!mf_info->multi_vnics_mode)
7862 && VALID_OVLAN(ovlan1)))) {
7863 PMD_DRV_LOG(NOTICE, sc,
7864 "mf_mode=SD function %d MF config "
7865 "mismatch, multi_vnics_mode=%d ovlan=%d",
7866 i, mf_info->multi_vnics_mode,
7872 /* Verify all funcs on the same port each have a different ovlan. */
7873 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7874 mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7875 ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7876 /* iterate from the next function on the port to the max func */
7877 for (j = i + 2; j < MAX_FUNC_NUM; j += 2) {
7879 MFCFG_RD(sc, func_mf_config[j].config);
7881 MFCFG_RD(sc, func_mf_config[j].e1hov_tag);
7882 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE)
7883 && VALID_OVLAN(ovlan1)
7884 && !(mf_cfg2 & FUNC_MF_CFG_FUNC_HIDE)
7885 && VALID_OVLAN(ovlan2)
7886 && (ovlan1 == ovlan2)) {
7887 PMD_DRV_LOG(NOTICE, sc,
7888 "mf_mode=SD functions %d and %d "
7889 "have the same ovlan (%d)",
7896 /* MULTI_FUNCTION_SD */
7900 static int bnx2x_get_mf_cfg_info(struct bnx2x_softc *sc)
7902 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7903 uint32_t val, mac_upper;
7906 /* initialize mf_info defaults */
7907 mf_info->vnics_per_port = 1;
7908 mf_info->multi_vnics_mode = FALSE;
7909 mf_info->path_has_ovlan = FALSE;
7910 mf_info->mf_mode = SINGLE_FUNCTION;
7912 if (!CHIP_IS_MF_CAP(sc)) {
7916 if (sc->devinfo.mf_cfg_base == SHMEM_MF_CFG_ADDR_NONE) {
7917 PMD_DRV_LOG(NOTICE, sc, "Invalid mf_cfg_base!");
7921 /* get the MF mode (switch dependent / independent / single-function) */
7923 val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
7925 switch (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK) {
7926 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
7929 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7931 /* check for legal upper mac bytes */
7932 if (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT) {
7933 mf_info->mf_mode = MULTI_FUNCTION_SI;
7935 PMD_DRV_LOG(NOTICE, sc,
7936 "Invalid config for Switch Independent mode");
7941 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
7942 case SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4:
7944 /* get outer vlan configuration */
7945 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7947 if ((val & FUNC_MF_CFG_E1HOV_TAG_MASK) !=
7948 FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
7949 mf_info->mf_mode = MULTI_FUNCTION_SD;
7951 PMD_DRV_LOG(NOTICE, sc,
7952 "Invalid config for Switch Dependent mode");
7957 case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
7959 /* not in MF mode, vnics_per_port=1 and multi_vnics_mode=FALSE */
7962 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
7965 * Mark MF mode as NIV if MCP version includes NPAR-SD support
7966 * and the MAC address is valid.
7969 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7971 if ((SHMEM2_HAS(sc, afex_driver_support)) &&
7972 (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT)) {
7973 mf_info->mf_mode = MULTI_FUNCTION_AFEX;
7975 PMD_DRV_LOG(NOTICE, sc, "Invalid config for AFEX mode");
7982 PMD_DRV_LOG(NOTICE, sc, "Unknown MF mode (0x%08x)",
7983 (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK));
7988 /* set path mf_mode (which could be different than function mf_mode) */
7989 if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7990 mf_info->path_has_ovlan = TRUE;
7991 } else if (mf_info->mf_mode == SINGLE_FUNCTION) {
7993 * Decide on path multi vnics mode. If we're not in MF mode and in
7994 * 4-port mode, this is good enough to check vnic-0 of the other port
7997 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7998 uint8_t other_port = !(PORT_ID(sc) & 1);
7999 uint8_t abs_func_other_port =
8000 (SC_PATH(sc) + (2 * other_port));
8005 [abs_func_other_port].e1hov_tag);
8007 mf_info->path_has_ovlan = VALID_OVLAN((uint16_t) val);
8011 if (mf_info->mf_mode == SINGLE_FUNCTION) {
8012 /* invalid MF config */
8013 if (SC_VN(sc) >= 1) {
8014 PMD_DRV_LOG(NOTICE, sc, "VNIC ID >= 1 in SF mode");
8021 /* get the MF configuration */
8022 mf_info->mf_config[SC_VN(sc)] =
8023 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
8025 switch (mf_info->mf_mode) {
8026 case MULTI_FUNCTION_SD:
8028 bnx2x_get_shmem_mf_cfg_info_sd(sc);
8031 case MULTI_FUNCTION_SI:
8033 bnx2x_get_shmem_mf_cfg_info_si(sc);
8036 case MULTI_FUNCTION_AFEX:
8038 bnx2x_get_shmem_mf_cfg_info_niv(sc);
8043 PMD_DRV_LOG(NOTICE, sc, "Get MF config failed (mf_mode=0x%08x)",
8048 /* get the congestion management parameters */
8051 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
8052 /* get min/max bw */
8053 val = MFCFG_RD(sc, func_mf_config[i].config);
8054 mf_info->min_bw[vnic] =
8055 ((val & FUNC_MF_CFG_MIN_BW_MASK) >>
8056 FUNC_MF_CFG_MIN_BW_SHIFT);
8057 mf_info->max_bw[vnic] =
8058 ((val & FUNC_MF_CFG_MAX_BW_MASK) >>
8059 FUNC_MF_CFG_MAX_BW_SHIFT);
8063 return bnx2x_check_valid_mf_cfg(sc);
8066 static int bnx2x_get_shmem_info(struct bnx2x_softc *sc)
8069 uint32_t mac_hi, mac_lo, val;
8071 PMD_INIT_FUNC_TRACE(sc);
8074 mac_hi = mac_lo = 0;
8076 sc->link_params.sc = sc;
8077 sc->link_params.port = port;
8079 /* get the hardware config info */
8080 sc->devinfo.hw_config = SHMEM_RD(sc, dev_info.shared_hw_config.config);
8081 sc->devinfo.hw_config2 =
8082 SHMEM_RD(sc, dev_info.shared_hw_config.config2);
8084 sc->link_params.hw_led_mode =
8085 ((sc->devinfo.hw_config & SHARED_HW_CFG_LED_MODE_MASK) >>
8086 SHARED_HW_CFG_LED_MODE_SHIFT);
8088 /* get the port feature config */
8090 SHMEM_RD(sc, dev_info.port_feature_config[port].config);
8092 /* get the link params */
8093 sc->link_params.speed_cap_mask[ELINK_INT_PHY] =
8094 SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask)
8095 & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
8096 sc->link_params.speed_cap_mask[ELINK_EXT_PHY1] =
8097 SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask2)
8098 & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
8100 /* get the lane config */
8101 sc->link_params.lane_config =
8102 SHMEM_RD(sc, dev_info.port_hw_config[port].lane_config);
8104 /* get the link config */
8105 val = SHMEM_RD(sc, dev_info.port_feature_config[port].link_config);
8106 sc->port.link_config[ELINK_INT_PHY] = val;
8107 sc->link_params.switch_cfg = (val & PORT_FEATURE_CONNECTED_SWITCH_MASK);
8108 sc->port.link_config[ELINK_EXT_PHY1] =
8109 SHMEM_RD(sc, dev_info.port_feature_config[port].link_config2);
8111 /* get the override preemphasis flag and enable it or turn it off */
8112 val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
8113 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) {
8114 sc->link_params.feature_config_flags |=
8115 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8117 sc->link_params.feature_config_flags &=
8118 ~ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8121 val = sc->devinfo.bc_ver >> 8;
8122 if (val < BNX2X_BC_VER) {
8123 /* for now only warn later we might need to enforce this */
8124 PMD_DRV_LOG(NOTICE, sc, "This driver needs bc_ver %X but found %X, please upgrade BC\n",
8127 sc->link_params.feature_config_flags |=
8128 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
8129 ELINK_FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY :
8132 sc->link_params.feature_config_flags |=
8133 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
8134 ELINK_FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
8135 sc->link_params.feature_config_flags |=
8136 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
8137 ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
8138 sc->link_params.feature_config_flags |=
8139 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
8140 ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
8142 /* get the initial value of the link params */
8143 sc->link_params.multi_phy_config =
8144 SHMEM_RD(sc, dev_info.port_hw_config[port].multi_phy_config);
8146 /* get external phy info */
8147 sc->port.ext_phy_config =
8148 SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
8150 /* get the multifunction configuration */
8151 bnx2x_get_mf_cfg_info(sc);
8153 /* get the mac address */
8156 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
8158 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_lower);
8160 mac_hi = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_upper);
8161 mac_lo = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_lower);
8164 if ((mac_lo == 0) && (mac_hi == 0)) {
8165 *sc->mac_addr_str = 0;
8166 PMD_DRV_LOG(NOTICE, sc, "No Ethernet address programmed!");
8168 sc->link_params.mac_addr[0] = (uint8_t) (mac_hi >> 8);
8169 sc->link_params.mac_addr[1] = (uint8_t) (mac_hi);
8170 sc->link_params.mac_addr[2] = (uint8_t) (mac_lo >> 24);
8171 sc->link_params.mac_addr[3] = (uint8_t) (mac_lo >> 16);
8172 sc->link_params.mac_addr[4] = (uint8_t) (mac_lo >> 8);
8173 sc->link_params.mac_addr[5] = (uint8_t) (mac_lo);
8174 snprintf(sc->mac_addr_str, sizeof(sc->mac_addr_str),
8175 "%02x:%02x:%02x:%02x:%02x:%02x",
8176 sc->link_params.mac_addr[0],
8177 sc->link_params.mac_addr[1],
8178 sc->link_params.mac_addr[2],
8179 sc->link_params.mac_addr[3],
8180 sc->link_params.mac_addr[4],
8181 sc->link_params.mac_addr[5]);
8182 PMD_DRV_LOG(DEBUG, sc,
8183 "Ethernet address: %s", sc->mac_addr_str);
8189 static void bnx2x_media_detect(struct bnx2x_softc *sc)
8191 uint32_t phy_idx = bnx2x_get_cur_phy_idx(sc);
8192 switch (sc->link_params.phy[phy_idx].media_type) {
8193 case ELINK_ETH_PHY_SFPP_10G_FIBER:
8194 case ELINK_ETH_PHY_SFP_1G_FIBER:
8195 case ELINK_ETH_PHY_XFP_FIBER:
8196 case ELINK_ETH_PHY_KR:
8197 case ELINK_ETH_PHY_CX4:
8198 PMD_DRV_LOG(INFO, sc, "Found 10GBase-CX4 media.");
8199 sc->media = IFM_10G_CX4;
8201 case ELINK_ETH_PHY_DA_TWINAX:
8202 PMD_DRV_LOG(INFO, sc, "Found 10Gb Twinax media.");
8203 sc->media = IFM_10G_TWINAX;
8205 case ELINK_ETH_PHY_BASE_T:
8206 PMD_DRV_LOG(INFO, sc, "Found 10GBase-T media.");
8207 sc->media = IFM_10G_T;
8209 case ELINK_ETH_PHY_NOT_PRESENT:
8210 PMD_DRV_LOG(INFO, sc, "Media not present.");
8213 case ELINK_ETH_PHY_UNSPECIFIED:
8215 PMD_DRV_LOG(INFO, sc, "Unknown media!");
8221 #define GET_FIELD(value, fname) \
8222 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
8223 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
8224 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
8226 static int bnx2x_get_igu_cam_info(struct bnx2x_softc *sc)
8228 int pfid = SC_FUNC(sc);
8231 uint8_t fid, igu_sb_cnt = 0;
8233 sc->igu_base_sb = 0xff;
8235 if (CHIP_INT_MODE_IS_BC(sc)) {
8237 igu_sb_cnt = sc->igu_sb_cnt;
8238 sc->igu_base_sb = ((CHIP_IS_MODE_4_PORT(sc) ? pfid : vn) *
8240 sc->igu_dsb_id = (E1HVN_MAX * FP_SB_MAX_E1x +
8241 (CHIP_IS_MODE_4_PORT(sc) ? pfid : vn));
8245 /* IGU in normal mode - read CAM */
8247 igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; igu_sb_id++) {
8248 val = REG_RD(sc, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
8249 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) {
8253 if (fid & IGU_FID_ENCODE_IS_PF) {
8254 if ((fid & IGU_FID_PF_NUM_MASK) != pfid) {
8257 if (IGU_VEC(val) == 0) {
8258 /* default status block */
8259 sc->igu_dsb_id = igu_sb_id;
8261 if (sc->igu_base_sb == 0xff) {
8262 sc->igu_base_sb = igu_sb_id;
8270 * Due to new PF resource allocation by MFW T7.4 and above, it's optional
8271 * that number of CAM entries will not be equal to the value advertised in
8272 * PCI. Driver should use the minimal value of both as the actual status
8275 sc->igu_sb_cnt = min(sc->igu_sb_cnt, igu_sb_cnt);
8277 if (igu_sb_cnt == 0) {
8278 PMD_DRV_LOG(ERR, sc, "CAM configuration error");
8286 * Gather various information from the device config space, the device itself,
8287 * shmem, and the user input.
8289 static int bnx2x_get_device_info(struct bnx2x_softc *sc)
8294 /* get the chip revision (chip metal comes from pci config space) */
8295 sc->devinfo.chip_id = sc->link_params.chip_id =
8296 (((REG_RD(sc, MISC_REG_CHIP_NUM) & 0xffff) << 16) |
8297 ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12) |
8298 (((REG_RD(sc, PCICFG_OFFSET + PCI_ID_VAL3) >> 24) & 0xf) << 4) |
8299 ((REG_RD(sc, MISC_REG_BOND_ID) & 0xf) << 0));
8301 /* force 57811 according to MISC register */
8302 if (REG_RD(sc, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
8303 if (CHIP_IS_57810(sc)) {
8304 sc->devinfo.chip_id = ((CHIP_NUM_57811 << 16) |
8306 devinfo.chip_id & 0x0000ffff));
8307 } else if (CHIP_IS_57810_MF(sc)) {
8308 sc->devinfo.chip_id = ((CHIP_NUM_57811_MF << 16) |
8310 devinfo.chip_id & 0x0000ffff));
8312 sc->devinfo.chip_id |= 0x1;
8315 PMD_DRV_LOG(DEBUG, sc,
8316 "chip_id=0x%08x (num=0x%04x rev=0x%01x metal=0x%02x bond=0x%01x)",
8317 sc->devinfo.chip_id,
8318 ((sc->devinfo.chip_id >> 16) & 0xffff),
8319 ((sc->devinfo.chip_id >> 12) & 0xf),
8320 ((sc->devinfo.chip_id >> 4) & 0xff),
8321 ((sc->devinfo.chip_id >> 0) & 0xf));
8323 val = (REG_RD(sc, 0x2874) & 0x55);
8324 if ((sc->devinfo.chip_id & 0x1) || (CHIP_IS_E1H(sc) && (val == 0x55))) {
8325 sc->flags |= BNX2X_ONE_PORT_FLAG;
8326 PMD_DRV_LOG(DEBUG, sc, "single port device");
8329 /* set the doorbell size */
8330 sc->doorbell_size = (1 << BNX2X_DB_SHIFT);
8332 /* determine whether the device is in 2 port or 4 port mode */
8333 sc->devinfo.chip_port_mode = CHIP_PORT_MODE_NONE; /* E1h */
8334 if (CHIP_IS_E2E3(sc)) {
8336 * Read port4mode_en_ovwr[0]:
8337 * If 1, four port mode is in port4mode_en_ovwr[1].
8338 * If 0, four port mode is in port4mode_en[0].
8340 val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);
8342 val = ((val >> 1) & 1);
8344 val = REG_RD(sc, MISC_REG_PORT4MODE_EN);
8347 sc->devinfo.chip_port_mode =
8348 (val) ? CHIP_4_PORT_MODE : CHIP_2_PORT_MODE;
8350 PMD_DRV_LOG(DEBUG, sc, "Port mode = %s", (val) ? "4" : "2");
8353 /* get the function and path info for the device */
8354 bnx2x_get_function_num(sc);
8356 /* get the shared memory base address */
8357 sc->devinfo.shmem_base =
8358 sc->link_params.shmem_base = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
8359 sc->devinfo.shmem2_base =
8360 REG_RD(sc, (SC_PATH(sc) ? MISC_REG_GENERIC_CR_1 :
8361 MISC_REG_GENERIC_CR_0));
8363 if (!sc->devinfo.shmem_base) {
8364 /* this should ONLY prevent upcoming shmem reads */
8365 PMD_DRV_LOG(INFO, sc, "MCP not active");
8366 sc->flags |= BNX2X_NO_MCP_FLAG;
8370 /* make sure the shared memory contents are valid */
8371 val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
8372 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) !=
8373 (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) {
8374 PMD_DRV_LOG(NOTICE, sc, "Invalid SHMEM validity signature: 0x%08x",
8379 /* get the bootcode version */
8380 sc->devinfo.bc_ver = SHMEM_RD(sc, dev_info.bc_rev);
8381 snprintf(sc->devinfo.bc_ver_str,
8382 sizeof(sc->devinfo.bc_ver_str),
8384 ((sc->devinfo.bc_ver >> 24) & 0xff),
8385 ((sc->devinfo.bc_ver >> 16) & 0xff),
8386 ((sc->devinfo.bc_ver >> 8) & 0xff));
8387 PMD_DRV_LOG(DEBUG, sc, "Bootcode version: %s", sc->devinfo.bc_ver_str);
8389 /* get the bootcode shmem address */
8390 sc->devinfo.mf_cfg_base = bnx2x_get_shmem_mf_cfg_base(sc);
8392 /* clean indirect addresses as they're not used */
8393 pci_write_long(sc, PCICFG_GRC_ADDRESS, 0);
8395 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F0, 0);
8396 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F0, 0);
8397 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F0, 0);
8398 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F0, 0);
8399 if (CHIP_IS_E1x(sc)) {
8400 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F1, 0);
8401 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F1, 0);
8402 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F1, 0);
8403 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F1, 0);
8407 /* get the nvram size */
8408 val = REG_RD(sc, MCP_REG_MCPR_NVM_CFG4);
8409 sc->devinfo.flash_size =
8410 (NVRAM_1MB_SIZE << (val & MCPR_NVM_CFG4_FLASH_SIZE));
8412 bnx2x_set_power_state(sc, PCI_PM_D0);
8413 /* get various configuration parameters from shmem */
8414 bnx2x_get_shmem_info(sc);
8416 /* initialize IGU parameters */
8417 if (CHIP_IS_E1x(sc)) {
8418 sc->devinfo.int_block = INT_BLOCK_HC;
8419 sc->igu_dsb_id = DEF_SB_IGU_ID;
8420 sc->igu_base_sb = 0;
8422 sc->devinfo.int_block = INT_BLOCK_IGU;
8424 /* do not allow device reset during IGU info preocessing */
8425 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8427 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
8429 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8432 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
8433 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION, val);
8434 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x7f);
8436 while (tout && REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8441 if (REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8442 PMD_DRV_LOG(NOTICE, sc,
8443 "FORCING IGU Normal Mode failed!!!");
8444 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8449 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8450 PMD_DRV_LOG(DEBUG, sc, "IGU Backward Compatible Mode");
8451 sc->devinfo.int_block |= INT_BLOCK_MODE_BW_COMP;
8453 PMD_DRV_LOG(DEBUG, sc, "IGU Normal Mode");
8456 rc = bnx2x_get_igu_cam_info(sc);
8458 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8466 * Get base FW non-default (fast path) status block ID. This value is
8467 * used to initialize the fw_sb_id saved on the fp/queue structure to
8468 * determine the id used by the FW.
8470 if (CHIP_IS_E1x(sc)) {
8472 ((SC_PORT(sc) * FP_SB_MAX_E1x) + SC_L_ID(sc));
8475 * 57712+ - We currently use one FW SB per IGU SB (Rx and Tx of
8476 * the same queue are indicated on the same IGU SB). So we prefer
8477 * FW and IGU SBs to be the same value.
8479 sc->base_fw_ndsb = sc->igu_base_sb;
8482 elink_phy_probe(&sc->link_params);
8488 bnx2x_link_settings_supported(struct bnx2x_softc *sc, uint32_t switch_cfg)
8490 uint32_t cfg_size = 0;
8492 uint8_t port = SC_PORT(sc);
8494 /* aggregation of supported attributes of all external phys */
8495 sc->port.supported[0] = 0;
8496 sc->port.supported[1] = 0;
8498 switch (sc->link_params.num_phys) {
8500 sc->port.supported[0] =
8501 sc->link_params.phy[ELINK_INT_PHY].supported;
8505 sc->port.supported[0] =
8506 sc->link_params.phy[ELINK_EXT_PHY1].supported;
8510 if (sc->link_params.multi_phy_config &
8511 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
8512 sc->port.supported[1] =
8513 sc->link_params.phy[ELINK_EXT_PHY1].supported;
8514 sc->port.supported[0] =
8515 sc->link_params.phy[ELINK_EXT_PHY2].supported;
8517 sc->port.supported[0] =
8518 sc->link_params.phy[ELINK_EXT_PHY1].supported;
8519 sc->port.supported[1] =
8520 sc->link_params.phy[ELINK_EXT_PHY2].supported;
8526 if (!(sc->port.supported[0] || sc->port.supported[1])) {
8527 PMD_DRV_LOG(ERR, sc,
8528 "Invalid phy config in NVRAM (PHY1=0x%08x PHY2=0x%08x)",
8530 dev_info.port_hw_config
8531 [port].external_phy_config),
8533 dev_info.port_hw_config
8534 [port].external_phy_config2));
8539 sc->port.phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR);
8541 switch (switch_cfg) {
8542 case ELINK_SWITCH_CFG_1G:
8545 NIG_REG_SERDES0_CTRL_PHY_ADDR + port * 0x10);
8547 case ELINK_SWITCH_CFG_10G:
8550 NIG_REG_XGXS0_CTRL_PHY_ADDR + port * 0x18);
8553 PMD_DRV_LOG(ERR, sc,
8554 "Invalid switch config in"
8555 "link_config=0x%08x",
8556 sc->port.link_config[0]);
8561 PMD_DRV_LOG(INFO, sc, "PHY addr 0x%08x", sc->port.phy_addr);
8563 /* mask what we support according to speed_cap_mask per configuration */
8564 for (idx = 0; idx < cfg_size; idx++) {
8565 if (!(sc->link_params.speed_cap_mask[idx] &
8566 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) {
8567 sc->port.supported[idx] &=
8568 ~ELINK_SUPPORTED_10baseT_Half;
8571 if (!(sc->link_params.speed_cap_mask[idx] &
8572 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) {
8573 sc->port.supported[idx] &=
8574 ~ELINK_SUPPORTED_10baseT_Full;
8577 if (!(sc->link_params.speed_cap_mask[idx] &
8578 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) {
8579 sc->port.supported[idx] &=
8580 ~ELINK_SUPPORTED_100baseT_Half;
8583 if (!(sc->link_params.speed_cap_mask[idx] &
8584 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) {
8585 sc->port.supported[idx] &=
8586 ~ELINK_SUPPORTED_100baseT_Full;
8589 if (!(sc->link_params.speed_cap_mask[idx] &
8590 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) {
8591 sc->port.supported[idx] &=
8592 ~ELINK_SUPPORTED_1000baseT_Full;
8595 if (!(sc->link_params.speed_cap_mask[idx] &
8596 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) {
8597 sc->port.supported[idx] &=
8598 ~ELINK_SUPPORTED_2500baseX_Full;
8601 if (!(sc->link_params.speed_cap_mask[idx] &
8602 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8603 sc->port.supported[idx] &=
8604 ~ELINK_SUPPORTED_10000baseT_Full;
8607 if (!(sc->link_params.speed_cap_mask[idx] &
8608 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) {
8609 sc->port.supported[idx] &=
8610 ~ELINK_SUPPORTED_20000baseKR2_Full;
8614 PMD_DRV_LOG(INFO, sc, "PHY supported 0=0x%08x 1=0x%08x",
8615 sc->port.supported[0], sc->port.supported[1]);
8618 static void bnx2x_link_settings_requested(struct bnx2x_softc *sc)
8620 uint32_t link_config;
8622 uint32_t cfg_size = 0;
8624 sc->port.advertising[0] = 0;
8625 sc->port.advertising[1] = 0;
8627 switch (sc->link_params.num_phys) {
8637 for (idx = 0; idx < cfg_size; idx++) {
8638 sc->link_params.req_duplex[idx] = DUPLEX_FULL;
8639 link_config = sc->port.link_config[idx];
8641 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
8642 case PORT_FEATURE_LINK_SPEED_AUTO:
8643 if (sc->port.supported[idx] & ELINK_SUPPORTED_Autoneg) {
8644 sc->link_params.req_line_speed[idx] =
8645 ELINK_SPEED_AUTO_NEG;
8646 sc->port.advertising[idx] |=
8647 sc->port.supported[idx];
8648 if (sc->link_params.phy[ELINK_EXT_PHY1].type ==
8649 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833)
8650 sc->port.advertising[idx] |=
8651 (ELINK_SUPPORTED_100baseT_Half |
8652 ELINK_SUPPORTED_100baseT_Full);
8654 /* force 10G, no AN */
8655 sc->link_params.req_line_speed[idx] =
8657 sc->port.advertising[idx] |=
8658 (ADVERTISED_10000baseT_Full |
8664 case PORT_FEATURE_LINK_SPEED_10M_FULL:
8666 port.supported[idx] & ELINK_SUPPORTED_10baseT_Full)
8668 sc->link_params.req_line_speed[idx] =
8670 sc->port.advertising[idx] |=
8671 (ADVERTISED_10baseT_Full | ADVERTISED_TP);
8673 PMD_DRV_LOG(ERR, sc,
8674 "Invalid NVRAM config link_config=0x%08x "
8675 "speed_cap_mask=0x%08x",
8678 link_params.speed_cap_mask[idx]);
8683 case PORT_FEATURE_LINK_SPEED_10M_HALF:
8685 port.supported[idx] & ELINK_SUPPORTED_10baseT_Half)
8687 sc->link_params.req_line_speed[idx] =
8689 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8690 sc->port.advertising[idx] |=
8691 (ADVERTISED_10baseT_Half | ADVERTISED_TP);
8693 PMD_DRV_LOG(ERR, sc,
8694 "Invalid NVRAM config link_config=0x%08x "
8695 "speed_cap_mask=0x%08x",
8698 link_params.speed_cap_mask[idx]);
8703 case PORT_FEATURE_LINK_SPEED_100M_FULL:
8705 port.supported[idx] & ELINK_SUPPORTED_100baseT_Full)
8707 sc->link_params.req_line_speed[idx] =
8709 sc->port.advertising[idx] |=
8710 (ADVERTISED_100baseT_Full | ADVERTISED_TP);
8712 PMD_DRV_LOG(ERR, sc,
8713 "Invalid NVRAM config link_config=0x%08x "
8714 "speed_cap_mask=0x%08x",
8717 link_params.speed_cap_mask[idx]);
8722 case PORT_FEATURE_LINK_SPEED_100M_HALF:
8724 port.supported[idx] & ELINK_SUPPORTED_100baseT_Half)
8726 sc->link_params.req_line_speed[idx] =
8728 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8729 sc->port.advertising[idx] |=
8730 (ADVERTISED_100baseT_Half | ADVERTISED_TP);
8732 PMD_DRV_LOG(ERR, sc,
8733 "Invalid NVRAM config link_config=0x%08x "
8734 "speed_cap_mask=0x%08x",
8737 link_params.speed_cap_mask[idx]);
8742 case PORT_FEATURE_LINK_SPEED_1G:
8743 if (sc->port.supported[idx] &
8744 ELINK_SUPPORTED_1000baseT_Full) {
8745 sc->link_params.req_line_speed[idx] =
8747 sc->port.advertising[idx] |=
8748 (ADVERTISED_1000baseT_Full | ADVERTISED_TP);
8750 PMD_DRV_LOG(ERR, sc,
8751 "Invalid NVRAM config link_config=0x%08x "
8752 "speed_cap_mask=0x%08x",
8755 link_params.speed_cap_mask[idx]);
8760 case PORT_FEATURE_LINK_SPEED_2_5G:
8761 if (sc->port.supported[idx] &
8762 ELINK_SUPPORTED_2500baseX_Full) {
8763 sc->link_params.req_line_speed[idx] =
8765 sc->port.advertising[idx] |=
8766 (ADVERTISED_2500baseX_Full | ADVERTISED_TP);
8768 PMD_DRV_LOG(ERR, sc,
8769 "Invalid NVRAM config link_config=0x%08x "
8770 "speed_cap_mask=0x%08x",
8773 link_params.speed_cap_mask[idx]);
8778 case PORT_FEATURE_LINK_SPEED_10G_CX4:
8779 if (sc->port.supported[idx] &
8780 ELINK_SUPPORTED_10000baseT_Full) {
8781 sc->link_params.req_line_speed[idx] =
8783 sc->port.advertising[idx] |=
8784 (ADVERTISED_10000baseT_Full |
8787 PMD_DRV_LOG(ERR, sc,
8788 "Invalid NVRAM config link_config=0x%08x "
8789 "speed_cap_mask=0x%08x",
8792 link_params.speed_cap_mask[idx]);
8797 case PORT_FEATURE_LINK_SPEED_20G:
8798 sc->link_params.req_line_speed[idx] = ELINK_SPEED_20000;
8802 PMD_DRV_LOG(ERR, sc,
8803 "Invalid NVRAM config link_config=0x%08x "
8804 "speed_cap_mask=0x%08x", link_config,
8805 sc->link_params.speed_cap_mask[idx]);
8806 sc->link_params.req_line_speed[idx] =
8807 ELINK_SPEED_AUTO_NEG;
8808 sc->port.advertising[idx] = sc->port.supported[idx];
8812 sc->link_params.req_flow_ctrl[idx] =
8813 (link_config & PORT_FEATURE_FLOW_CONTROL_MASK);
8815 if (sc->link_params.req_flow_ctrl[idx] == ELINK_FLOW_CTRL_AUTO) {
8818 port.supported[idx] & ELINK_SUPPORTED_Autoneg)) {
8819 sc->link_params.req_flow_ctrl[idx] =
8820 ELINK_FLOW_CTRL_NONE;
8822 bnx2x_set_requested_fc(sc);
8828 static void bnx2x_get_phy_info(struct bnx2x_softc *sc)
8830 uint8_t port = SC_PORT(sc);
8833 PMD_INIT_FUNC_TRACE(sc);
8835 /* shmem data already read in bnx2x_get_shmem_info() */
8837 bnx2x_link_settings_supported(sc, sc->link_params.switch_cfg);
8838 bnx2x_link_settings_requested(sc);
8840 /* configure link feature according to nvram value */
8842 (((SHMEM_RD(sc, dev_info.port_feature_config[port].eee_power_mode))
8843 & PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
8844 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
8845 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
8846 sc->link_params.eee_mode = (ELINK_EEE_MODE_ADV_LPI |
8847 ELINK_EEE_MODE_ENABLE_LPI |
8848 ELINK_EEE_MODE_OUTPUT_TIME);
8850 sc->link_params.eee_mode = 0;
8853 /* get the media type */
8854 bnx2x_media_detect(sc);
8857 static void bnx2x_set_modes_bitmap(struct bnx2x_softc *sc)
8859 uint32_t flags = MODE_ASIC | MODE_PORT2;
8861 if (CHIP_IS_E2(sc)) {
8863 } else if (CHIP_IS_E3(sc)) {
8865 if (CHIP_REV(sc) == CHIP_REV_Ax) {
8866 flags |= MODE_E3_A0;
8867 } else { /*if (CHIP_REV(sc) == CHIP_REV_Bx) */
8869 flags |= MODE_E3_B0 | MODE_COS3;
8875 switch (sc->devinfo.mf_info.mf_mode) {
8876 case MULTI_FUNCTION_SD:
8877 flags |= MODE_MF_SD;
8879 case MULTI_FUNCTION_SI:
8880 flags |= MODE_MF_SI;
8882 case MULTI_FUNCTION_AFEX:
8883 flags |= MODE_MF_AFEX;
8890 #if defined(__LITTLE_ENDIAN)
8891 flags |= MODE_LITTLE_ENDIAN;
8892 #else /* __BIG_ENDIAN */
8893 flags |= MODE_BIG_ENDIAN;
8896 INIT_MODE_FLAGS(sc) = flags;
8899 int bnx2x_alloc_hsi_mem(struct bnx2x_softc *sc)
8901 struct bnx2x_fastpath *fp;
8906 /************************/
8907 /* DEFAULT STATUS BLOCK */
8908 /************************/
8910 if (bnx2x_dma_alloc(sc, sizeof(struct host_sp_status_block),
8911 &sc->def_sb_dma, "def_sb",
8912 RTE_CACHE_LINE_SIZE) != 0) {
8917 (struct host_sp_status_block *)sc->def_sb_dma.vaddr;
8922 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8923 &sc->eq_dma, "ev_queue",
8924 RTE_CACHE_LINE_SIZE) != 0) {
8929 sc->eq = (union event_ring_elem *)sc->eq_dma.vaddr;
8935 if (bnx2x_dma_alloc(sc, sizeof(struct bnx2x_slowpath),
8937 RTE_CACHE_LINE_SIZE) != 0) {
8943 sc->sp = (struct bnx2x_slowpath *)sc->sp_dma.vaddr;
8945 /*******************/
8946 /* SLOW PATH QUEUE */
8947 /*******************/
8949 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8950 &sc->spq_dma, "sp_queue",
8951 RTE_CACHE_LINE_SIZE) != 0) {
8958 sc->spq = (struct eth_spe *)sc->spq_dma.vaddr;
8960 /***************************/
8961 /* FW DECOMPRESSION BUFFER */
8962 /***************************/
8964 if (bnx2x_dma_alloc(sc, FW_BUF_SIZE, &sc->gz_buf_dma,
8965 "fw_buf", RTE_CACHE_LINE_SIZE) != 0) {
8973 sc->gz_buf = (void *)sc->gz_buf_dma.vaddr;
8980 /* allocate DMA memory for each fastpath structure */
8981 for (i = 0; i < sc->num_queues; i++) {
8986 /*******************/
8987 /* FP STATUS BLOCK */
8988 /*******************/
8990 snprintf(buf, sizeof(buf), "fp_%d_sb", i);
8991 if (bnx2x_dma_alloc(sc, sizeof(union bnx2x_host_hc_status_block),
8992 &fp->sb_dma, buf, RTE_CACHE_LINE_SIZE) != 0) {
8993 PMD_DRV_LOG(NOTICE, sc, "Failed to alloc %s", buf);
8996 if (CHIP_IS_E2E3(sc)) {
8997 fp->status_block.e2_sb =
8998 (struct host_hc_status_block_e2 *)
9001 fp->status_block.e1x_sb =
9002 (struct host_hc_status_block_e1x *)
9011 void bnx2x_free_hsi_mem(struct bnx2x_softc *sc)
9013 struct bnx2x_fastpath *fp;
9016 for (i = 0; i < sc->num_queues; i++) {
9019 /*******************/
9020 /* FP STATUS BLOCK */
9021 /*******************/
9023 memset(&fp->status_block, 0, sizeof(fp->status_block));
9024 bnx2x_dma_free(&fp->sb_dma);
9028 /***************************/
9029 /* FW DECOMPRESSION BUFFER */
9030 /***************************/
9032 bnx2x_dma_free(&sc->gz_buf_dma);
9035 /*******************/
9036 /* SLOW PATH QUEUE */
9037 /*******************/
9039 bnx2x_dma_free(&sc->spq_dma);
9046 bnx2x_dma_free(&sc->sp_dma);
9053 bnx2x_dma_free(&sc->eq_dma);
9056 /************************/
9057 /* DEFAULT STATUS BLOCK */
9058 /************************/
9060 bnx2x_dma_free(&sc->def_sb_dma);
9066 * Previous driver DMAE transaction may have occurred when pre-boot stage
9067 * ended and boot began. This would invalidate the addresses of the
9068 * transaction, resulting in was-error bit set in the PCI causing all
9069 * hw-to-host PCIe transactions to timeout. If this happened we want to clear
9070 * the interrupt which detected this from the pglueb and the was-done bit
9072 static void bnx2x_prev_interrupted_dmae(struct bnx2x_softc *sc)
9076 if (!CHIP_IS_E1x(sc)) {
9077 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS);
9078 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
9079 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
9085 static int bnx2x_prev_mcp_done(struct bnx2x_softc *sc)
9087 uint32_t rc = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE,
9088 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
9090 PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
9097 static struct bnx2x_prev_list_node *bnx2x_prev_path_get_entry(struct bnx2x_softc *sc)
9099 struct bnx2x_prev_list_node *tmp;
9101 LIST_FOREACH(tmp, &bnx2x_prev_list, node) {
9102 if ((sc->pcie_bus == tmp->bus) &&
9103 (sc->pcie_device == tmp->slot) &&
9104 (SC_PATH(sc) == tmp->path)) {
9112 static uint8_t bnx2x_prev_is_path_marked(struct bnx2x_softc *sc)
9114 struct bnx2x_prev_list_node *tmp;
9117 rte_spinlock_lock(&bnx2x_prev_mtx);
9119 tmp = bnx2x_prev_path_get_entry(sc);
9122 PMD_DRV_LOG(DEBUG, sc,
9123 "Path %d/%d/%d was marked by AER",
9124 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9127 PMD_DRV_LOG(DEBUG, sc,
9128 "Path %d/%d/%d was already cleaned from previous drivers",
9129 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9133 rte_spinlock_unlock(&bnx2x_prev_mtx);
9138 static int bnx2x_prev_mark_path(struct bnx2x_softc *sc, uint8_t after_undi)
9140 struct bnx2x_prev_list_node *tmp;
9142 rte_spinlock_lock(&bnx2x_prev_mtx);
9144 /* Check whether the entry for this path already exists */
9145 tmp = bnx2x_prev_path_get_entry(sc);
9148 PMD_DRV_LOG(DEBUG, sc,
9149 "Re-marking AER in path %d/%d/%d",
9150 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9152 PMD_DRV_LOG(DEBUG, sc,
9153 "Removing AER indication from path %d/%d/%d",
9154 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9158 rte_spinlock_unlock(&bnx2x_prev_mtx);
9162 rte_spinlock_unlock(&bnx2x_prev_mtx);
9164 /* Create an entry for this path and add it */
9165 tmp = rte_malloc("", sizeof(struct bnx2x_prev_list_node),
9166 RTE_CACHE_LINE_SIZE);
9168 PMD_DRV_LOG(NOTICE, sc, "Failed to allocate 'bnx2x_prev_list_node'");
9172 tmp->bus = sc->pcie_bus;
9173 tmp->slot = sc->pcie_device;
9174 tmp->path = SC_PATH(sc);
9176 tmp->undi = after_undi ? (1 << SC_PORT(sc)) : 0;
9178 rte_spinlock_lock(&bnx2x_prev_mtx);
9180 LIST_INSERT_HEAD(&bnx2x_prev_list, tmp, node);
9182 rte_spinlock_unlock(&bnx2x_prev_mtx);
9187 static int bnx2x_do_flr(struct bnx2x_softc *sc)
9191 /* only E2 and onwards support FLR */
9192 if (CHIP_IS_E1x(sc)) {
9193 PMD_DRV_LOG(WARNING, sc, "FLR not supported in E1H");
9197 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9198 if (sc->devinfo.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9199 PMD_DRV_LOG(WARNING, sc,
9200 "FLR not supported by BC_VER: 0x%08x",
9201 sc->devinfo.bc_ver);
9205 /* Wait for Transaction Pending bit clean */
9206 for (i = 0; i < 4; i++) {
9208 DELAY(((1 << (i - 1)) * 100) * 1000);
9211 if (!bnx2x_is_pcie_pending(sc)) {
9216 PMD_DRV_LOG(NOTICE, sc, "PCIE transaction is not cleared, "
9217 "proceeding with reset anyway");
9220 bnx2x_fw_command(sc, DRV_MSG_CODE_INITIATE_FLR, 0);
9225 struct bnx2x_mac_vals {
9233 uint32_t bmac_val[2];
9237 bnx2x_prev_unload_close_mac(struct bnx2x_softc *sc, struct bnx2x_mac_vals *vals)
9239 uint32_t val, base_addr, offset, mask, reset_reg;
9240 uint8_t mac_stopped = FALSE;
9241 uint8_t port = SC_PORT(sc);
9242 uint32_t wb_data[2];
9244 /* reset addresses as they also mark which values were changed */
9245 vals->bmac_addr = 0;
9246 vals->umac_addr = 0;
9247 vals->xmac_addr = 0;
9248 vals->emac_addr = 0;
9250 reset_reg = REG_RD(sc, MISC_REG_RESET_REG_2);
9252 if (!CHIP_IS_E3(sc)) {
9253 val = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9254 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9255 if ((mask & reset_reg) && val) {
9256 base_addr = SC_PORT(sc) ? NIG_REG_INGRESS_BMAC1_MEM
9257 : NIG_REG_INGRESS_BMAC0_MEM;
9258 offset = CHIP_IS_E2(sc) ? BIGMAC2_REGISTER_BMAC_CONTROL
9259 : BIGMAC_REGISTER_BMAC_CONTROL;
9262 * use rd/wr since we cannot use dmae. This is safe
9263 * since MCP won't access the bus due to the request
9264 * to unload, and no function on the path can be
9265 * loaded at this time.
9267 wb_data[0] = REG_RD(sc, base_addr + offset);
9268 wb_data[1] = REG_RD(sc, base_addr + offset + 0x4);
9269 vals->bmac_addr = base_addr + offset;
9270 vals->bmac_val[0] = wb_data[0];
9271 vals->bmac_val[1] = wb_data[1];
9272 wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE;
9273 REG_WR(sc, vals->bmac_addr, wb_data[0]);
9274 REG_WR(sc, vals->bmac_addr + 0x4, wb_data[1]);
9277 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + SC_PORT(sc) * 4;
9278 vals->emac_val = REG_RD(sc, vals->emac_addr);
9279 REG_WR(sc, vals->emac_addr, 0);
9282 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9283 base_addr = SC_PORT(sc) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9284 val = REG_RD(sc, base_addr + XMAC_REG_PFC_CTRL_HI);
9285 REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9287 REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9289 vals->xmac_addr = base_addr + XMAC_REG_CTRL;
9290 vals->xmac_val = REG_RD(sc, vals->xmac_addr);
9291 REG_WR(sc, vals->xmac_addr, 0);
9295 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9296 if (mask & reset_reg) {
9297 base_addr = SC_PORT(sc) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9298 vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
9299 vals->umac_val = REG_RD(sc, vals->umac_addr);
9300 REG_WR(sc, vals->umac_addr, 0);
9310 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9311 #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
9312 #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
9313 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
9316 bnx2x_prev_unload_undi_inc(struct bnx2x_softc *sc, uint8_t port, uint8_t inc)
9319 uint32_t tmp_reg = REG_RD(sc, BNX2X_PREV_UNDI_PROD_ADDR(port));
9321 rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9322 bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9324 tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9325 REG_WR(sc, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9328 static int bnx2x_prev_unload_common(struct bnx2x_softc *sc)
9330 uint32_t reset_reg, tmp_reg = 0, rc;
9331 uint8_t prev_undi = FALSE;
9332 struct bnx2x_mac_vals mac_vals;
9333 uint32_t timer_count = 1000;
9337 * It is possible a previous function received 'common' answer,
9338 * but hasn't loaded yet, therefore creating a scenario of
9339 * multiple functions receiving 'common' on the same path.
9341 memset(&mac_vals, 0, sizeof(mac_vals));
9343 if (bnx2x_prev_is_path_marked(sc)) {
9344 return bnx2x_prev_mcp_done(sc);
9347 reset_reg = REG_RD(sc, MISC_REG_RESET_REG_1);
9349 /* Reset should be performed after BRB is emptied */
9350 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
9351 /* Close the MAC Rx to prevent BRB from filling up */
9352 bnx2x_prev_unload_close_mac(sc, &mac_vals);
9354 /* close LLH filters towards the BRB */
9355 elink_set_rx_filter(&sc->link_params, 0);
9358 * Check if the UNDI driver was previously loaded.
9359 * UNDI driver initializes CID offset for normal bell to 0x7
9361 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
9362 tmp_reg = REG_RD(sc, DORQ_REG_NORM_CID_OFST);
9363 if (tmp_reg == 0x7) {
9364 PMD_DRV_LOG(DEBUG, sc, "UNDI previously loaded");
9366 /* clear the UNDI indication */
9367 REG_WR(sc, DORQ_REG_NORM_CID_OFST, 0);
9368 /* clear possible idle check errors */
9369 REG_RD(sc, NIG_REG_NIG_INT_STS_CLR_0);
9373 /* wait until BRB is empty */
9374 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9375 while (timer_count) {
9378 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9383 PMD_DRV_LOG(DEBUG, sc, "BRB still has 0x%08x", tmp_reg);
9385 /* reset timer as long as BRB actually gets emptied */
9386 if (prev_brb > tmp_reg) {
9392 /* If UNDI resides in memory, manually increment it */
9394 bnx2x_prev_unload_undi_inc(sc, SC_PORT(sc), 1);
9401 PMD_DRV_LOG(NOTICE, sc, "Failed to empty BRB");
9405 /* No packets are in the pipeline, path is ready for reset */
9406 bnx2x_reset_common(sc);
9408 if (mac_vals.xmac_addr) {
9409 REG_WR(sc, mac_vals.xmac_addr, mac_vals.xmac_val);
9411 if (mac_vals.umac_addr) {
9412 REG_WR(sc, mac_vals.umac_addr, mac_vals.umac_val);
9414 if (mac_vals.emac_addr) {
9415 REG_WR(sc, mac_vals.emac_addr, mac_vals.emac_val);
9417 if (mac_vals.bmac_addr) {
9418 REG_WR(sc, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
9419 REG_WR(sc, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
9422 rc = bnx2x_prev_mark_path(sc, prev_undi);
9424 bnx2x_prev_mcp_done(sc);
9428 return bnx2x_prev_mcp_done(sc);
9431 static int bnx2x_prev_unload_uncommon(struct bnx2x_softc *sc)
9435 /* Test if previous unload process was already finished for this path */
9436 if (bnx2x_prev_is_path_marked(sc)) {
9437 return bnx2x_prev_mcp_done(sc);
9441 * If function has FLR capabilities, and existing FW version matches
9442 * the one required, then FLR will be sufficient to clean any residue
9443 * left by previous driver
9445 rc = bnx2x_nic_load_analyze_req(sc, FW_MSG_CODE_DRV_LOAD_FUNCTION);
9447 /* fw version is good */
9448 rc = bnx2x_do_flr(sc);
9452 /* FLR was performed */
9456 PMD_DRV_LOG(INFO, sc, "Could not FLR");
9458 /* Close the MCP request, return failure */
9459 rc = bnx2x_prev_mcp_done(sc);
9461 rc = BNX2X_PREV_WAIT_NEEDED;
9467 static int bnx2x_prev_unload(struct bnx2x_softc *sc)
9469 int time_counter = 10;
9470 uint32_t fw, hw_lock_reg, hw_lock_val;
9473 PMD_INIT_FUNC_TRACE(sc);
9476 * Clear HW from errors which may have resulted from an interrupted
9479 bnx2x_prev_interrupted_dmae(sc);
9481 /* Release previously held locks */
9482 hw_lock_reg = (SC_FUNC(sc) <= 5) ?
9483 (MISC_REG_DRIVER_CONTROL_1 + SC_FUNC(sc) * 8) :
9484 (MISC_REG_DRIVER_CONTROL_7 + (SC_FUNC(sc) - 6) * 8);
9486 hw_lock_val = (REG_RD(sc, hw_lock_reg));
9488 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
9489 PMD_DRV_LOG(DEBUG, sc, "Releasing previously held NVRAM lock\n");
9490 REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
9491 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << SC_PORT(sc)));
9493 PMD_DRV_LOG(DEBUG, sc, "Releasing previously held HW lock\n");
9494 REG_WR(sc, hw_lock_reg, 0xffffffff);
9497 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(sc, MCP_REG_MCPR_ACCESS_LOCK)) {
9498 PMD_DRV_LOG(DEBUG, sc, "Releasing previously held ALR\n");
9499 REG_WR(sc, MCP_REG_MCPR_ACCESS_LOCK, 0);
9503 /* Lock MCP using an unload request */
9504 fw = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
9506 PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
9511 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
9512 rc = bnx2x_prev_unload_common(sc);
9516 /* non-common reply from MCP might require looping */
9517 rc = bnx2x_prev_unload_uncommon(sc);
9518 if (rc != BNX2X_PREV_WAIT_NEEDED) {
9523 } while (--time_counter);
9525 if (!time_counter || rc) {
9526 PMD_DRV_LOG(NOTICE, sc, "Failed to unload previous driver!");
9534 bnx2x_dcbx_set_state(struct bnx2x_softc *sc, uint8_t dcb_on, uint32_t dcbx_enabled)
9536 if (!CHIP_IS_E1x(sc)) {
9537 sc->dcb_state = dcb_on;
9538 sc->dcbx_enabled = dcbx_enabled;
9540 sc->dcb_state = FALSE;
9541 sc->dcbx_enabled = BNX2X_DCBX_ENABLED_INVALID;
9543 PMD_DRV_LOG(DEBUG, sc,
9544 "DCB state [%s:%s]",
9545 dcb_on ? "ON" : "OFF",
9546 (dcbx_enabled == BNX2X_DCBX_ENABLED_OFF) ? "user-mode" :
9548 BNX2X_DCBX_ENABLED_ON_NEG_OFF) ? "on-chip static"
9550 BNX2X_DCBX_ENABLED_ON_NEG_ON) ?
9551 "on-chip with negotiation" : "invalid");
9554 static int bnx2x_set_qm_cid_count(struct bnx2x_softc *sc)
9556 int cid_count = BNX2X_L2_MAX_CID(sc);
9558 if (CNIC_SUPPORT(sc)) {
9559 cid_count += CNIC_CID_MAX;
9562 return roundup(cid_count, QM_CID_ROUND);
9565 static void bnx2x_init_multi_cos(struct bnx2x_softc *sc)
9569 uint32_t pri_map = 0;
9571 for (pri = 0; pri < BNX2X_MAX_PRIORITY; pri++) {
9572 cos = ((pri_map & (0xf << (pri * 4))) >> (pri * 4));
9573 if (cos < sc->max_cos) {
9574 sc->prio_to_cos[pri] = cos;
9576 PMD_DRV_LOG(WARNING, sc,
9577 "Invalid COS %d for priority %d "
9578 "(max COS is %d), setting to 0", cos, pri,
9580 sc->prio_to_cos[pri] = 0;
9585 static int bnx2x_pci_get_caps(struct bnx2x_softc *sc)
9592 struct bnx2x_pci_cap *cap;
9594 cap = sc->pci_caps = rte_zmalloc("caps", sizeof(struct bnx2x_pci_cap),
9595 RTE_CACHE_LINE_SIZE);
9597 PMD_DRV_LOG(NOTICE, sc, "Failed to allocate memory");
9601 #ifndef RTE_EXEC_ENV_FREEBSD
9602 pci_read(sc, PCI_STATUS, &status, 2);
9603 if (!(status & PCI_STATUS_CAP_LIST)) {
9605 pci_read(sc, PCIR_STATUS, &status, 2);
9606 if (!(status & PCIM_STATUS_CAPPRESENT)) {
9608 PMD_DRV_LOG(NOTICE, sc, "PCIe capability reading failed");
9612 #ifndef RTE_EXEC_ENV_FREEBSD
9613 pci_read(sc, PCI_CAPABILITY_LIST, &pci_cap.next, 1);
9615 pci_read(sc, PCIR_CAP_PTR, &pci_cap.next, 1);
9617 while (pci_cap.next) {
9618 cap->addr = pci_cap.next & ~3;
9619 pci_read(sc, pci_cap.next & ~3, &pci_cap, 2);
9620 if (pci_cap.id == 0xff)
9622 cap->id = pci_cap.id;
9623 cap->type = BNX2X_PCI_CAP;
9624 cap->next = rte_zmalloc("pci_cap",
9625 sizeof(struct bnx2x_pci_cap),
9626 RTE_CACHE_LINE_SIZE);
9628 PMD_DRV_LOG(NOTICE, sc, "Failed to allocate memory");
9637 static void bnx2x_init_rte(struct bnx2x_softc *sc)
9640 sc->max_tx_queues = min(BNX2X_VF_MAX_QUEUES_PER_VF,
9642 sc->max_rx_queues = min(BNX2X_VF_MAX_QUEUES_PER_VF,
9645 sc->max_rx_queues = BNX2X_MAX_RSS_COUNT(sc);
9646 sc->max_tx_queues = sc->max_rx_queues;
9650 #define FW_HEADER_LEN 104
9651 #define FW_NAME_57711 "/lib/firmware/bnx2x/bnx2x-e1h-7.13.11.0.fw"
9652 #define FW_NAME_57810 "/lib/firmware/bnx2x/bnx2x-e2-7.13.11.0.fw"
9654 void bnx2x_load_firmware(struct bnx2x_softc *sc)
9660 fwname = sc->devinfo.device_id == CHIP_NUM_57711
9661 ? FW_NAME_57711 : FW_NAME_57810;
9662 f = open(fwname, O_RDONLY);
9664 PMD_DRV_LOG(NOTICE, sc, "Can't open firmware file");
9668 if (fstat(f, &st) < 0) {
9669 PMD_DRV_LOG(NOTICE, sc, "Can't stat firmware file");
9674 sc->firmware = rte_zmalloc("bnx2x_fw", st.st_size, RTE_CACHE_LINE_SIZE);
9675 if (!sc->firmware) {
9676 PMD_DRV_LOG(NOTICE, sc, "Can't allocate memory for firmware");
9681 if (read(f, sc->firmware, st.st_size) != st.st_size) {
9682 PMD_DRV_LOG(NOTICE, sc, "Can't read firmware data");
9688 sc->fw_len = st.st_size;
9689 if (sc->fw_len < FW_HEADER_LEN) {
9690 PMD_DRV_LOG(NOTICE, sc,
9691 "Invalid fw size: %" PRIu64, sc->fw_len);
9694 PMD_DRV_LOG(DEBUG, sc, "fw_len = %" PRIu64, sc->fw_len);
9698 bnx2x_data_to_init_ops(uint8_t * data, struct raw_op *dst, uint32_t len)
9700 uint32_t *src = (uint32_t *) data;
9703 for (i = 0, j = 0; i < len / 8; ++i, j += 2) {
9704 tmp = rte_be_to_cpu_32(src[j]);
9705 dst[i].op = (tmp >> 24) & 0xFF;
9706 dst[i].offset = tmp & 0xFFFFFF;
9707 dst[i].raw_data = rte_be_to_cpu_32(src[j + 1]);
9712 bnx2x_data_to_init_offsets(uint8_t * data, uint16_t * dst, uint32_t len)
9714 uint16_t *src = (uint16_t *) data;
9717 for (i = 0; i < len / 2; ++i)
9718 dst[i] = rte_be_to_cpu_16(src[i]);
9721 static void bnx2x_data_to_init_data(uint8_t * data, uint32_t * dst, uint32_t len)
9723 uint32_t *src = (uint32_t *) data;
9726 for (i = 0; i < len / 4; ++i)
9727 dst[i] = rte_be_to_cpu_32(src[i]);
9730 static void bnx2x_data_to_iro_array(uint8_t * data, struct iro *dst, uint32_t len)
9732 uint32_t *src = (uint32_t *) data;
9735 for (i = 0, j = 0; i < len / sizeof(struct iro); ++i, ++j) {
9736 dst[i].base = rte_be_to_cpu_32(src[j++]);
9737 tmp = rte_be_to_cpu_32(src[j]);
9738 dst[i].m1 = (tmp >> 16) & 0xFFFF;
9739 dst[i].m2 = tmp & 0xFFFF;
9741 tmp = rte_be_to_cpu_32(src[j]);
9742 dst[i].m3 = (tmp >> 16) & 0xFFFF;
9743 dst[i].size = tmp & 0xFFFF;
9748 * Device attach function.
9750 * Allocates device resources, performs secondary chip identification, and
9751 * initializes driver instance variables. This function is called from driver
9752 * load after a successful probe.
9755 * 0 = Success, >0 = Failure
9757 int bnx2x_attach(struct bnx2x_softc *sc)
9761 PMD_DRV_LOG(DEBUG, sc, "Starting attach...");
9763 rc = bnx2x_pci_get_caps(sc);
9765 PMD_DRV_LOG(NOTICE, sc, "PCIe caps reading was failed");
9769 sc->state = BNX2X_STATE_CLOSED;
9771 pci_write_long(sc, PCICFG_GRC_ADDRESS, PCICFG_VENDOR_ID_OFFSET);
9773 sc->igu_base_addr = IS_VF(sc) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
9775 /* get PCI capabilites */
9776 bnx2x_probe_pci_caps(sc);
9778 if (sc->devinfo.pcie_msix_cap_reg != 0) {
9781 (sc->devinfo.pcie_msix_cap_reg + PCIR_MSIX_CTRL), &val,
9783 sc->igu_sb_cnt = (val & PCIM_MSIXCTRL_TABLE_SIZE) + 1;
9788 /* Init RTE stuff */
9792 /* Enable internal target-read (in case we are probed after PF
9793 * FLR). Must be done prior to any BAR read access. Only for
9796 if (!CHIP_IS_E1x(sc)) {
9797 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ,
9802 /* get device info and set params */
9803 if (bnx2x_get_device_info(sc) != 0) {
9804 PMD_DRV_LOG(NOTICE, sc, "getting device info");
9808 /* get phy settings from shmem and 'and' against admin settings */
9809 bnx2x_get_phy_info(sc);
9811 /* Left mac of VF unfilled, PF should set it for VF */
9812 memset(sc->link_params.mac_addr, 0, RTE_ETHER_ADDR_LEN);
9817 /* set the default MTU (changed via ifconfig) */
9818 sc->mtu = RTE_ETHER_MTU;
9820 bnx2x_set_modes_bitmap(sc);
9822 /* need to reset chip if UNDI was active */
9823 if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
9826 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
9827 DRV_MSG_SEQ_NUMBER_MASK);
9828 PMD_DRV_LOG(DEBUG, sc, "prev unload fw_seq 0x%04x",
9830 bnx2x_prev_unload(sc);
9833 bnx2x_dcbx_set_state(sc, FALSE, BNX2X_DCBX_ENABLED_OFF);
9835 /* calculate qm_cid_count */
9836 sc->qm_cid_count = bnx2x_set_qm_cid_count(sc);
9839 bnx2x_init_multi_cos(sc);
9845 bnx2x_igu_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t segment,
9846 uint16_t index, uint8_t op, uint8_t update)
9848 uint32_t igu_addr = sc->igu_base_addr;
9849 igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
9850 bnx2x_igu_ack_sb_gen(sc, segment, index, op, update, igu_addr);
9854 bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t storm,
9855 uint16_t index, uint8_t op, uint8_t update)
9857 if (unlikely(sc->devinfo.int_block == INT_BLOCK_HC))
9858 bnx2x_hc_ack_sb(sc, igu_sb_id, storm, index, op, update);
9861 if (CHIP_INT_MODE_IS_BC(sc)) {
9863 } else if (igu_sb_id != sc->igu_dsb_id) {
9864 segment = IGU_SEG_ACCESS_DEF;
9865 } else if (storm == ATTENTION_ID) {
9866 segment = IGU_SEG_ACCESS_ATTN;
9868 segment = IGU_SEG_ACCESS_DEF;
9870 bnx2x_igu_ack_sb(sc, igu_sb_id, segment, index, op, update);
9875 bnx2x_igu_clear_sb_gen(struct bnx2x_softc *sc, uint8_t func, uint8_t idu_sb_id,
9878 uint32_t data, ctl, cnt = 100;
9879 uint32_t igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
9880 uint32_t igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
9881 uint32_t igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP +
9882 (idu_sb_id / 32) * 4;
9883 uint32_t sb_bit = 1 << (idu_sb_id % 32);
9884 uint32_t func_encode = func |
9885 (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
9886 uint32_t addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
9888 /* Not supported in BC mode */
9889 if (CHIP_INT_MODE_IS_BC(sc)) {
9893 data = ((IGU_USE_REGISTER_cstorm_type_0_sb_cleanup <<
9894 IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
9895 IGU_REGULAR_CLEANUP_SET | IGU_REGULAR_BCLEANUP);
9897 ctl = ((addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT) |
9898 (func_encode << IGU_CTRL_REG_FID_SHIFT) |
9899 (IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT));
9901 REG_WR(sc, igu_addr_data, data);
9905 PMD_DRV_LOG(DEBUG, sc, "write 0x%08x to IGU(via GRC) addr 0x%x",
9907 REG_WR(sc, igu_addr_ctl, ctl);
9911 /* wait for clean up to finish */
9912 while (!(REG_RD(sc, igu_addr_ack) & sb_bit) && --cnt) {
9916 if (!(REG_RD(sc, igu_addr_ack) & sb_bit)) {
9917 PMD_DRV_LOG(DEBUG, sc,
9918 "Unable to finish IGU cleanup: "
9919 "idu_sb_id %d offset %d bit %d (cnt %d)",
9920 idu_sb_id, idu_sb_id / 32, idu_sb_id % 32, cnt);
9924 static void bnx2x_igu_clear_sb(struct bnx2x_softc *sc, uint8_t idu_sb_id)
9926 bnx2x_igu_clear_sb_gen(sc, SC_FUNC(sc), idu_sb_id, TRUE /*PF*/);
9929 /*******************/
9930 /* ECORE CALLBACKS */
9931 /*******************/
9933 static void bnx2x_reset_common(struct bnx2x_softc *sc)
9935 uint32_t val = 0x1400;
9937 PMD_INIT_FUNC_TRACE(sc);
9940 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR),
9943 if (CHIP_IS_E3(sc)) {
9944 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
9945 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
9948 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR), val);
9951 static void bnx2x_common_init_phy(struct bnx2x_softc *sc)
9953 uint32_t shmem_base[2];
9954 uint32_t shmem2_base[2];
9956 /* Avoid common init in case MFW supports LFA */
9957 if (SHMEM2_RD(sc, size) >
9958 (uint32_t) offsetof(struct shmem2_region,
9959 lfa_host_addr[SC_PORT(sc)])) {
9963 shmem_base[0] = sc->devinfo.shmem_base;
9964 shmem2_base[0] = sc->devinfo.shmem2_base;
9966 if (!CHIP_IS_E1x(sc)) {
9967 shmem_base[1] = SHMEM2_RD(sc, other_shmem_base_addr);
9968 shmem2_base[1] = SHMEM2_RD(sc, other_shmem2_base_addr);
9971 bnx2x_acquire_phy_lock(sc);
9972 elink_common_init_phy(sc, shmem_base, shmem2_base,
9973 sc->devinfo.chip_id, 0);
9974 bnx2x_release_phy_lock(sc);
9977 static void bnx2x_pf_disable(struct bnx2x_softc *sc)
9979 uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
9981 val &= ~IGU_PF_CONF_FUNC_EN;
9983 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
9984 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
9985 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 0);
9988 static void bnx2x_init_pxp(struct bnx2x_softc *sc)
9991 int r_order, w_order;
9993 devctl = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_CTL);
9995 w_order = ((devctl & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5);
9996 r_order = ((devctl & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12);
9998 ecore_init_pxp_arb(sc, r_order, w_order);
10001 static uint32_t bnx2x_get_pretend_reg(struct bnx2x_softc *sc)
10003 uint32_t base = PXP2_REG_PGL_PRETEND_FUNC_F0;
10004 uint32_t stride = (PXP2_REG_PGL_PRETEND_FUNC_F1 - base);
10005 return base + (SC_ABS_FUNC(sc)) * stride;
10009 * Called only on E1H or E2.
10010 * When pretending to be PF, the pretend value is the function number 0..7.
10011 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
10014 static int bnx2x_pretend_func(struct bnx2x_softc *sc, uint16_t pretend_func_val)
10016 uint32_t pretend_reg;
10018 if (CHIP_IS_E1H(sc) && (pretend_func_val > E1H_FUNC_MAX))
10021 /* get my own pretend register */
10022 pretend_reg = bnx2x_get_pretend_reg(sc);
10023 REG_WR(sc, pretend_reg, pretend_func_val);
10024 REG_RD(sc, pretend_reg);
10028 static void bnx2x_setup_fan_failure_detection(struct bnx2x_softc *sc)
10035 val = (SHMEM_RD(sc, dev_info.shared_hw_config.config2) &
10036 SHARED_HW_CFG_FAN_FAILURE_MASK);
10038 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) {
10042 * The fan failure mechanism is usually related to the PHY type since
10043 * the power consumption of the board is affected by the PHY. Currently,
10044 * fan is required for most designs with SFX7101, BNX2X8727 and BNX2X8481.
10046 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) {
10047 for (port = PORT_0; port < PORT_MAX; port++) {
10048 is_required |= elink_fan_failure_det_req(sc,
10050 devinfo.shmem_base,
10052 devinfo.shmem2_base,
10057 if (is_required == 0) {
10061 /* Fan failure is indicated by SPIO 5 */
10062 bnx2x_set_spio(sc, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
10064 /* set to active low mode */
10065 val = REG_RD(sc, MISC_REG_SPIO_INT);
10066 val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
10067 REG_WR(sc, MISC_REG_SPIO_INT, val);
10069 /* enable interrupt to signal the IGU */
10070 val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
10071 val |= MISC_SPIO_SPIO5;
10072 REG_WR(sc, MISC_REG_SPIO_EVENT_EN, val);
10075 static void bnx2x_enable_blocks_attention(struct bnx2x_softc *sc)
10079 REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0);
10080 if (!CHIP_IS_E1x(sc)) {
10081 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0x40);
10083 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0);
10085 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
10086 REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
10088 * mask read length error interrupts in brb for parser
10089 * (parsing unit and 'checksum and crc' unit)
10090 * these errors are legal (PU reads fixed length and CAC can cause
10091 * read length error on truncated packets)
10093 REG_WR(sc, BRB1_REG_BRB1_INT_MASK, 0xFC00);
10094 REG_WR(sc, QM_REG_QM_INT_MASK, 0);
10095 REG_WR(sc, TM_REG_TM_INT_MASK, 0);
10096 REG_WR(sc, XSDM_REG_XSDM_INT_MASK_0, 0);
10097 REG_WR(sc, XSDM_REG_XSDM_INT_MASK_1, 0);
10098 REG_WR(sc, XCM_REG_XCM_INT_MASK, 0);
10099 /* REG_WR(sc, XSEM_REG_XSEM_INT_MASK_0, 0); */
10100 /* REG_WR(sc, XSEM_REG_XSEM_INT_MASK_1, 0); */
10101 REG_WR(sc, USDM_REG_USDM_INT_MASK_0, 0);
10102 REG_WR(sc, USDM_REG_USDM_INT_MASK_1, 0);
10103 REG_WR(sc, UCM_REG_UCM_INT_MASK, 0);
10104 /* REG_WR(sc, USEM_REG_USEM_INT_MASK_0, 0); */
10105 /* REG_WR(sc, USEM_REG_USEM_INT_MASK_1, 0); */
10106 REG_WR(sc, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
10107 REG_WR(sc, CSDM_REG_CSDM_INT_MASK_0, 0);
10108 REG_WR(sc, CSDM_REG_CSDM_INT_MASK_1, 0);
10109 REG_WR(sc, CCM_REG_CCM_INT_MASK, 0);
10110 /* REG_WR(sc, CSEM_REG_CSEM_INT_MASK_0, 0); */
10111 /* REG_WR(sc, CSEM_REG_CSEM_INT_MASK_1, 0); */
10113 val = (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
10114 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
10115 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN);
10116 if (!CHIP_IS_E1x(sc)) {
10117 val |= (PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
10118 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED);
10120 REG_WR(sc, PXP2_REG_PXP2_INT_MASK_0, val);
10122 REG_WR(sc, TSDM_REG_TSDM_INT_MASK_0, 0);
10123 REG_WR(sc, TSDM_REG_TSDM_INT_MASK_1, 0);
10124 REG_WR(sc, TCM_REG_TCM_INT_MASK, 0);
10125 /* REG_WR(sc, TSEM_REG_TSEM_INT_MASK_0, 0); */
10127 if (!CHIP_IS_E1x(sc)) {
10128 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
10129 REG_WR(sc, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
10132 REG_WR(sc, CDU_REG_CDU_INT_MASK, 0);
10133 REG_WR(sc, DMAE_REG_DMAE_INT_MASK, 0);
10134 /* REG_WR(sc, MISC_REG_MISC_INT_MASK, 0); */
10135 REG_WR(sc, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
10139 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
10141 * @sc: driver handle
10143 static int bnx2x_init_hw_common(struct bnx2x_softc *sc)
10145 uint8_t abs_func_id;
10148 PMD_DRV_LOG(DEBUG, sc,
10149 "starting common init for func %d", SC_ABS_FUNC(sc));
10152 * take the RESET lock to protect undi_unload flow from accessing
10153 * registers while we are resetting the chip
10155 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10157 bnx2x_reset_common(sc);
10159 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET), 0xffffffff);
10162 if (CHIP_IS_E3(sc)) {
10163 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
10164 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
10167 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET), val);
10169 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10171 ecore_init_block(sc, BLOCK_MISC, PHASE_COMMON);
10173 if (!CHIP_IS_E1x(sc)) {
10175 * 4-port mode or 2-port mode we need to turn off master-enable for
10176 * everyone. After that we turn it back on for self. So, we disregard
10177 * multi-function, and always disable all functions on the given path,
10178 * this means 0,2,4,6 for path 0 and 1,3,5,7 for path 1
10180 for (abs_func_id = SC_PATH(sc);
10181 abs_func_id < (E2_FUNC_MAX * 2); abs_func_id += 2) {
10182 if (abs_func_id == SC_ABS_FUNC(sc)) {
10184 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
10189 bnx2x_pretend_func(sc, abs_func_id);
10191 /* clear pf enable */
10192 bnx2x_pf_disable(sc);
10194 bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10198 ecore_init_block(sc, BLOCK_PXP, PHASE_COMMON);
10200 ecore_init_block(sc, BLOCK_PXP2, PHASE_COMMON);
10201 bnx2x_init_pxp(sc);
10203 #ifdef __BIG_ENDIAN
10204 REG_WR(sc, PXP2_REG_RQ_QM_ENDIAN_M, 1);
10205 REG_WR(sc, PXP2_REG_RQ_TM_ENDIAN_M, 1);
10206 REG_WR(sc, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
10207 REG_WR(sc, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
10208 REG_WR(sc, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
10209 /* make sure this value is 0 */
10210 REG_WR(sc, PXP2_REG_RQ_HC_ENDIAN_M, 0);
10212 //REG_WR(sc, PXP2_REG_RD_PBF_SWAP_MODE, 1);
10213 REG_WR(sc, PXP2_REG_RD_QM_SWAP_MODE, 1);
10214 REG_WR(sc, PXP2_REG_RD_TM_SWAP_MODE, 1);
10215 REG_WR(sc, PXP2_REG_RD_SRC_SWAP_MODE, 1);
10216 REG_WR(sc, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
10219 ecore_ilt_init_page_size(sc, INITOP_SET);
10221 if (CHIP_REV_IS_FPGA(sc) && CHIP_IS_E1H(sc)) {
10222 REG_WR(sc, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
10225 /* let the HW do it's magic... */
10228 /* finish PXP init */
10230 val = REG_RD(sc, PXP2_REG_RQ_CFG_DONE);
10232 PMD_DRV_LOG(NOTICE, sc, "PXP2 CFG failed");
10235 val = REG_RD(sc, PXP2_REG_RD_INIT_DONE);
10237 PMD_DRV_LOG(NOTICE, sc, "PXP2 RD_INIT failed");
10242 * Timer bug workaround for E2 only. We need to set the entire ILT to have
10243 * entries with value "0" and valid bit on. This needs to be done by the
10244 * first PF that is loaded in a path (i.e. common phase)
10246 if (!CHIP_IS_E1x(sc)) {
10248 * In E2 there is a bug in the timers block that can cause function 6 / 7
10249 * (i.e. vnic3) to start even if it is marked as "scan-off".
10250 * This occurs when a different function (func2,3) is being marked
10251 * as "scan-off". Real-life scenario for example: if a driver is being
10252 * load-unloaded while func6,7 are down. This will cause the timer to access
10253 * the ilt, translate to a logical address and send a request to read/write.
10254 * Since the ilt for the function that is down is not valid, this will cause
10255 * a translation error which is unrecoverable.
10256 * The Workaround is intended to make sure that when this happens nothing
10257 * fatal will occur. The workaround:
10258 * 1. First PF driver which loads on a path will:
10259 * a. After taking the chip out of reset, by using pretend,
10260 * it will write "0" to the following registers of
10262 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10263 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
10264 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
10265 * And for itself it will write '1' to
10266 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
10267 * dmae-operations (writing to pram for example.)
10268 * note: can be done for only function 6,7 but cleaner this
10270 * b. Write zero+valid to the entire ILT.
10271 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
10272 * VNIC3 (of that port). The range allocated will be the
10273 * entire ILT. This is needed to prevent ILT range error.
10274 * 2. Any PF driver load flow:
10275 * a. ILT update with the physical addresses of the allocated
10277 * b. Wait 20msec. - note that this timeout is needed to make
10278 * sure there are no requests in one of the PXP internal
10279 * queues with "old" ILT addresses.
10280 * c. PF enable in the PGLC.
10281 * d. Clear the was_error of the PF in the PGLC. (could have
10282 * occurred while driver was down)
10283 * e. PF enable in the CFC (WEAK + STRONG)
10284 * f. Timers scan enable
10285 * 3. PF driver unload flow:
10286 * a. Clear the Timers scan_en.
10287 * b. Polling for scan_on=0 for that PF.
10288 * c. Clear the PF enable bit in the PXP.
10289 * d. Clear the PF enable in the CFC (WEAK + STRONG)
10290 * e. Write zero+valid to all ILT entries (The valid bit must
10292 * f. If this is VNIC 3 of a port then also init
10293 * first_timers_ilt_entry to zero and last_timers_ilt_entry
10294 * to the last enrty in the ILT.
10297 * Currently the PF error in the PGLC is non recoverable.
10298 * In the future the there will be a recovery routine for this error.
10299 * Currently attention is masked.
10300 * Having an MCP lock on the load/unload process does not guarantee that
10301 * there is no Timer disable during Func6/7 enable. This is because the
10302 * Timers scan is currently being cleared by the MCP on FLR.
10303 * Step 2.d can be done only for PF6/7 and the driver can also check if
10304 * there is error before clearing it. But the flow above is simpler and
10306 * All ILT entries are written by zero+valid and not just PF6/7
10307 * ILT entries since in the future the ILT entries allocation for
10308 * PF-s might be dynamic.
10310 struct ilt_client_info ilt_cli;
10311 struct ecore_ilt ilt;
10313 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
10314 memset(&ilt, 0, sizeof(struct ecore_ilt));
10316 /* initialize dummy TM client */
10318 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
10319 ilt_cli.client_num = ILT_CLIENT_TM;
10322 * Step 1: set zeroes to all ilt page entries with valid bit on
10323 * Step 2: set the timers first/last ilt entry to point
10324 * to the entire range to prevent ILT range error for 3rd/4th
10325 * vnic (this code assumes existence of the vnic)
10327 * both steps performed by call to ecore_ilt_client_init_op()
10328 * with dummy TM client
10330 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
10331 * and his brother are split registers
10334 bnx2x_pretend_func(sc, (SC_PATH(sc) + 6));
10335 ecore_ilt_client_init_op_ilt(sc, &ilt, &ilt_cli, INITOP_CLEAR);
10336 bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10338 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
10339 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
10340 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
10343 REG_WR(sc, PXP2_REG_RQ_DISABLE_INPUTS, 0);
10344 REG_WR(sc, PXP2_REG_RD_DISABLE_INPUTS, 0);
10346 if (!CHIP_IS_E1x(sc)) {
10349 ecore_init_block(sc, BLOCK_PGLUE_B, PHASE_COMMON);
10350 ecore_init_block(sc, BLOCK_ATC, PHASE_COMMON);
10352 /* let the HW do it's magic... */
10355 val = REG_RD(sc, ATC_REG_ATC_INIT_DONE);
10356 } while (factor-- && (val != 1));
10359 PMD_DRV_LOG(NOTICE, sc, "ATC_INIT failed");
10364 ecore_init_block(sc, BLOCK_DMAE, PHASE_COMMON);
10366 /* clean the DMAE memory */
10367 sc->dmae_ready = 1;
10368 ecore_init_fill(sc, TSEM_REG_PRAM, 0, 8, 1);
10370 ecore_init_block(sc, BLOCK_TCM, PHASE_COMMON);
10372 ecore_init_block(sc, BLOCK_UCM, PHASE_COMMON);
10374 ecore_init_block(sc, BLOCK_CCM, PHASE_COMMON);
10376 ecore_init_block(sc, BLOCK_XCM, PHASE_COMMON);
10378 bnx2x_read_dmae(sc, XSEM_REG_PASSIVE_BUFFER, 3);
10379 bnx2x_read_dmae(sc, CSEM_REG_PASSIVE_BUFFER, 3);
10380 bnx2x_read_dmae(sc, TSEM_REG_PASSIVE_BUFFER, 3);
10381 bnx2x_read_dmae(sc, USEM_REG_PASSIVE_BUFFER, 3);
10383 ecore_init_block(sc, BLOCK_QM, PHASE_COMMON);
10385 /* QM queues pointers table */
10386 ecore_qm_init_ptr_table(sc, sc->qm_cid_count, INITOP_SET);
10388 /* soft reset pulse */
10389 REG_WR(sc, QM_REG_SOFT_RESET, 1);
10390 REG_WR(sc, QM_REG_SOFT_RESET, 0);
10392 if (CNIC_SUPPORT(sc))
10393 ecore_init_block(sc, BLOCK_TM, PHASE_COMMON);
10395 ecore_init_block(sc, BLOCK_DORQ, PHASE_COMMON);
10397 if (!CHIP_REV_IS_SLOW(sc)) {
10398 /* enable hw interrupt from doorbell Q */
10399 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
10402 ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON);
10404 ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON);
10405 REG_WR(sc, PRS_REG_A_PRSU_20, 0xf);
10406 REG_WR(sc, PRS_REG_E1HOV_MODE, sc->devinfo.mf_info.path_has_ovlan);
10408 if (!CHIP_IS_E1x(sc) && !CHIP_IS_E3B0(sc)) {
10409 if (IS_MF_AFEX(sc)) {
10411 * configure that AFEX and VLAN headers must be
10412 * received in AFEX mode
10414 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC, 0xE);
10415 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS, 0xA);
10416 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
10417 REG_WR(sc, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
10418 REG_WR(sc, PRS_REG_TAG_LEN_0, 0x4);
10421 * Bit-map indicating which L2 hdrs may appear
10422 * after the basic Ethernet header
10424 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC,
10425 sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10429 ecore_init_block(sc, BLOCK_TSDM, PHASE_COMMON);
10430 ecore_init_block(sc, BLOCK_CSDM, PHASE_COMMON);
10431 ecore_init_block(sc, BLOCK_USDM, PHASE_COMMON);
10432 ecore_init_block(sc, BLOCK_XSDM, PHASE_COMMON);
10434 if (!CHIP_IS_E1x(sc)) {
10435 /* reset VFC memories */
10436 REG_WR(sc, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10437 VFC_MEMORIES_RST_REG_CAM_RST |
10438 VFC_MEMORIES_RST_REG_RAM_RST);
10439 REG_WR(sc, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10440 VFC_MEMORIES_RST_REG_CAM_RST |
10441 VFC_MEMORIES_RST_REG_RAM_RST);
10446 ecore_init_block(sc, BLOCK_TSEM, PHASE_COMMON);
10447 ecore_init_block(sc, BLOCK_USEM, PHASE_COMMON);
10448 ecore_init_block(sc, BLOCK_CSEM, PHASE_COMMON);
10449 ecore_init_block(sc, BLOCK_XSEM, PHASE_COMMON);
10451 /* sync semi rtc */
10452 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x80000000);
10453 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x80000000);
10455 ecore_init_block(sc, BLOCK_UPB, PHASE_COMMON);
10456 ecore_init_block(sc, BLOCK_XPB, PHASE_COMMON);
10457 ecore_init_block(sc, BLOCK_PBF, PHASE_COMMON);
10459 if (!CHIP_IS_E1x(sc)) {
10460 if (IS_MF_AFEX(sc)) {
10462 * configure that AFEX and VLAN headers must be
10463 * sent in AFEX mode
10465 REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC, 0xE);
10466 REG_WR(sc, PBF_REG_MUST_HAVE_HDRS, 0xA);
10467 REG_WR(sc, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
10468 REG_WR(sc, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
10469 REG_WR(sc, PBF_REG_TAG_LEN_0, 0x4);
10471 REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC,
10472 sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10476 REG_WR(sc, SRC_REG_SOFT_RST, 1);
10478 ecore_init_block(sc, BLOCK_SRC, PHASE_COMMON);
10480 if (CNIC_SUPPORT(sc)) {
10481 REG_WR(sc, SRC_REG_KEYSEARCH_0, 0x63285672);
10482 REG_WR(sc, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
10483 REG_WR(sc, SRC_REG_KEYSEARCH_2, 0x223aef9b);
10484 REG_WR(sc, SRC_REG_KEYSEARCH_3, 0x26001e3a);
10485 REG_WR(sc, SRC_REG_KEYSEARCH_4, 0x7ae91116);
10486 REG_WR(sc, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
10487 REG_WR(sc, SRC_REG_KEYSEARCH_6, 0x298d8adf);
10488 REG_WR(sc, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
10489 REG_WR(sc, SRC_REG_KEYSEARCH_8, 0x1830f82f);
10490 REG_WR(sc, SRC_REG_KEYSEARCH_9, 0x01e46be7);
10492 REG_WR(sc, SRC_REG_SOFT_RST, 0);
10494 if (sizeof(union cdu_context) != 1024) {
10495 /* we currently assume that a context is 1024 bytes */
10496 PMD_DRV_LOG(NOTICE, sc,
10497 "please adjust the size of cdu_context(%ld)",
10498 (long)sizeof(union cdu_context));
10501 ecore_init_block(sc, BLOCK_CDU, PHASE_COMMON);
10502 val = (4 << 24) + (0 << 12) + 1024;
10503 REG_WR(sc, CDU_REG_CDU_GLOBAL_PARAMS, val);
10505 ecore_init_block(sc, BLOCK_CFC, PHASE_COMMON);
10507 REG_WR(sc, CFC_REG_INIT_REG, 0x7FF);
10508 /* enable context validation interrupt from CFC */
10509 REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
10511 /* set the thresholds to prevent CFC/CDU race */
10512 REG_WR(sc, CFC_REG_DEBUG0, 0x20020000);
10513 ecore_init_block(sc, BLOCK_HC, PHASE_COMMON);
10515 if (!CHIP_IS_E1x(sc) && BNX2X_NOMCP(sc)) {
10516 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x36);
10519 ecore_init_block(sc, BLOCK_IGU, PHASE_COMMON);
10520 ecore_init_block(sc, BLOCK_MISC_AEU, PHASE_COMMON);
10522 /* Reset PCIE errors for debug */
10523 REG_WR(sc, 0x2814, 0xffffffff);
10524 REG_WR(sc, 0x3820, 0xffffffff);
10526 if (!CHIP_IS_E1x(sc)) {
10527 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
10528 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
10529 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
10530 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
10531 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
10532 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
10533 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
10534 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
10535 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
10536 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
10537 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
10540 ecore_init_block(sc, BLOCK_NIG, PHASE_COMMON);
10542 /* in E3 this done in per-port section */
10543 if (!CHIP_IS_E3(sc))
10544 REG_WR(sc, NIG_REG_LLH_MF_MODE, IS_MF(sc));
10546 if (CHIP_IS_E1H(sc)) {
10547 /* not applicable for E2 (and above ...) */
10548 REG_WR(sc, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(sc));
10551 if (CHIP_REV_IS_SLOW(sc)) {
10555 /* finish CFC init */
10556 val = reg_poll(sc, CFC_REG_LL_INIT_DONE, 1, 100, 10);
10558 PMD_DRV_LOG(NOTICE, sc, "CFC LL_INIT failed");
10561 val = reg_poll(sc, CFC_REG_AC_INIT_DONE, 1, 100, 10);
10563 PMD_DRV_LOG(NOTICE, sc, "CFC AC_INIT failed");
10566 val = reg_poll(sc, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
10568 PMD_DRV_LOG(NOTICE, sc, "CFC CAM_INIT failed");
10571 REG_WR(sc, CFC_REG_DEBUG0, 0);
10573 bnx2x_setup_fan_failure_detection(sc);
10575 /* clear PXP2 attentions */
10576 REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
10578 bnx2x_enable_blocks_attention(sc);
10580 if (!CHIP_REV_IS_SLOW(sc)) {
10581 ecore_enable_blocks_parity(sc);
10584 if (!BNX2X_NOMCP(sc)) {
10585 if (CHIP_IS_E1x(sc)) {
10586 bnx2x_common_init_phy(sc);
10594 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
10596 * @sc: driver handle
10598 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc)
10600 int rc = bnx2x_init_hw_common(sc);
10606 /* In E2 2-PORT mode, same ext phy is used for the two paths */
10607 if (!BNX2X_NOMCP(sc)) {
10608 bnx2x_common_init_phy(sc);
10614 static int bnx2x_init_hw_port(struct bnx2x_softc *sc)
10616 int port = SC_PORT(sc);
10617 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
10618 uint32_t low, high;
10621 PMD_DRV_LOG(DEBUG, sc, "starting port init for port %d", port);
10623 REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
10625 ecore_init_block(sc, BLOCK_MISC, init_phase);
10626 ecore_init_block(sc, BLOCK_PXP, init_phase);
10627 ecore_init_block(sc, BLOCK_PXP2, init_phase);
10630 * Timers bug workaround: disables the pf_master bit in pglue at
10631 * common phase, we need to enable it here before any dmae access are
10632 * attempted. Therefore we manually added the enable-master to the
10633 * port phase (it also happens in the function phase)
10635 if (!CHIP_IS_E1x(sc)) {
10636 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
10639 ecore_init_block(sc, BLOCK_ATC, init_phase);
10640 ecore_init_block(sc, BLOCK_DMAE, init_phase);
10641 ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
10642 ecore_init_block(sc, BLOCK_QM, init_phase);
10644 ecore_init_block(sc, BLOCK_TCM, init_phase);
10645 ecore_init_block(sc, BLOCK_UCM, init_phase);
10646 ecore_init_block(sc, BLOCK_CCM, init_phase);
10647 ecore_init_block(sc, BLOCK_XCM, init_phase);
10649 /* QM cid (connection) count */
10650 ecore_qm_init_cid_count(sc, sc->qm_cid_count, INITOP_SET);
10652 if (CNIC_SUPPORT(sc)) {
10653 ecore_init_block(sc, BLOCK_TM, init_phase);
10654 REG_WR(sc, TM_REG_LIN0_SCAN_TIME + port * 4, 20);
10655 REG_WR(sc, TM_REG_LIN0_MAX_ACTIVE_CID + port * 4, 31);
10658 ecore_init_block(sc, BLOCK_DORQ, init_phase);
10660 ecore_init_block(sc, BLOCK_BRB1, init_phase);
10662 if (CHIP_IS_E1H(sc)) {
10664 low = (BNX2X_ONE_PORT(sc) ? 160 : 246);
10665 } else if (sc->mtu > 4096) {
10666 if (BNX2X_ONE_PORT(sc)) {
10670 /* (24*1024 + val*4)/256 */
10671 low = (96 + (val / 64) + ((val % 64) ? 1 : 0));
10674 low = (BNX2X_ONE_PORT(sc) ? 80 : 160);
10676 high = (low + 56); /* 14*1024/256 */
10677 REG_WR(sc, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port * 4, low);
10678 REG_WR(sc, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port * 4, high);
10681 if (CHIP_IS_MODE_4_PORT(sc)) {
10682 REG_WR(sc, SC_PORT(sc) ?
10683 BRB1_REG_MAC_GUARANTIED_1 :
10684 BRB1_REG_MAC_GUARANTIED_0, 40);
10687 ecore_init_block(sc, BLOCK_PRS, init_phase);
10688 if (CHIP_IS_E3B0(sc)) {
10689 if (IS_MF_AFEX(sc)) {
10690 /* configure headers for AFEX mode */
10692 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_1,
10694 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_1,
10696 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_1, 0xA);
10698 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10700 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_0,
10702 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
10705 /* Ovlan exists only if we are in multi-function +
10706 * switch-dependent mode, in switch-independent there
10707 * is no ovlan headers
10709 REG_WR(sc, SC_PORT(sc) ?
10710 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
10711 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10712 (sc->devinfo.mf_info.path_has_ovlan ? 7 : 6));
10716 ecore_init_block(sc, BLOCK_TSDM, init_phase);
10717 ecore_init_block(sc, BLOCK_CSDM, init_phase);
10718 ecore_init_block(sc, BLOCK_USDM, init_phase);
10719 ecore_init_block(sc, BLOCK_XSDM, init_phase);
10721 ecore_init_block(sc, BLOCK_TSEM, init_phase);
10722 ecore_init_block(sc, BLOCK_USEM, init_phase);
10723 ecore_init_block(sc, BLOCK_CSEM, init_phase);
10724 ecore_init_block(sc, BLOCK_XSEM, init_phase);
10726 ecore_init_block(sc, BLOCK_UPB, init_phase);
10727 ecore_init_block(sc, BLOCK_XPB, init_phase);
10729 ecore_init_block(sc, BLOCK_PBF, init_phase);
10731 if (CHIP_IS_E1x(sc)) {
10732 /* configure PBF to work without PAUSE mtu 9000 */
10733 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 0);
10735 /* update threshold */
10736 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, (9040 / 16));
10737 /* update init credit */
10738 REG_WR(sc, PBF_REG_P0_INIT_CRD + port * 4,
10739 (9040 / 16) + 553 - 22);
10741 /* probe changes */
10742 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 1);
10744 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0);
10747 if (CNIC_SUPPORT(sc)) {
10748 ecore_init_block(sc, BLOCK_SRC, init_phase);
10751 ecore_init_block(sc, BLOCK_CDU, init_phase);
10752 ecore_init_block(sc, BLOCK_CFC, init_phase);
10753 ecore_init_block(sc, BLOCK_HC, init_phase);
10754 ecore_init_block(sc, BLOCK_IGU, init_phase);
10755 ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
10756 /* init aeu_mask_attn_func_0/1:
10757 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
10758 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
10759 * bits 4-7 are used for "per vn group attention" */
10760 val = IS_MF(sc) ? 0xF7 : 0x7;
10762 REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, val);
10764 ecore_init_block(sc, BLOCK_NIG, init_phase);
10766 if (!CHIP_IS_E1x(sc)) {
10767 /* Bit-map indicating which L2 hdrs may appear after the
10768 * basic Ethernet header
10770 if (IS_MF_AFEX(sc)) {
10771 REG_WR(sc, SC_PORT(sc) ?
10772 NIG_REG_P1_HDRS_AFTER_BASIC :
10773 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
10775 REG_WR(sc, SC_PORT(sc) ?
10776 NIG_REG_P1_HDRS_AFTER_BASIC :
10777 NIG_REG_P0_HDRS_AFTER_BASIC,
10778 IS_MF_SD(sc) ? 7 : 6);
10781 if (CHIP_IS_E3(sc)) {
10782 REG_WR(sc, SC_PORT(sc) ?
10783 NIG_REG_LLH1_MF_MODE :
10784 NIG_REG_LLH_MF_MODE, IS_MF(sc));
10787 if (!CHIP_IS_E3(sc)) {
10788 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1);
10791 /* 0x2 disable mf_ov, 0x1 enable */
10792 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port * 4,
10793 (IS_MF_SD(sc) ? 0x1 : 0x2));
10795 if (!CHIP_IS_E1x(sc)) {
10797 switch (sc->devinfo.mf_info.mf_mode) {
10798 case MULTI_FUNCTION_SD:
10801 case MULTI_FUNCTION_SI:
10802 case MULTI_FUNCTION_AFEX:
10807 REG_WR(sc, (SC_PORT(sc) ? NIG_REG_LLH1_CLS_TYPE :
10808 NIG_REG_LLH0_CLS_TYPE), val);
10810 REG_WR(sc, NIG_REG_LLFC_ENABLE_0 + port * 4, 0);
10811 REG_WR(sc, NIG_REG_LLFC_OUT_EN_0 + port * 4, 0);
10812 REG_WR(sc, NIG_REG_PAUSE_ENABLE_0 + port * 4, 1);
10814 /* If SPIO5 is set to generate interrupts, enable it for this port */
10815 val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
10816 if (val & MISC_SPIO_SPIO5) {
10817 uint32_t reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
10818 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
10819 val = REG_RD(sc, reg_addr);
10820 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
10821 REG_WR(sc, reg_addr, val);
10828 bnx2x_flr_clnup_reg_poll(struct bnx2x_softc *sc, uint32_t reg,
10829 uint32_t expected, uint32_t poll_count)
10831 uint32_t cur_cnt = poll_count;
10834 while ((val = REG_RD(sc, reg)) != expected && cur_cnt--) {
10835 DELAY(FLR_WAIT_INTERVAL);
10842 bnx2x_flr_clnup_poll_hw_counter(struct bnx2x_softc *sc, uint32_t reg,
10843 __rte_unused const char *msg, uint32_t poll_cnt)
10845 uint32_t val = bnx2x_flr_clnup_reg_poll(sc, reg, 0, poll_cnt);
10848 PMD_DRV_LOG(NOTICE, sc, "%s usage count=%d", msg, val);
10855 /* Common routines with VF FLR cleanup */
10856 static uint32_t bnx2x_flr_clnup_poll_count(struct bnx2x_softc *sc)
10858 /* adjust polling timeout */
10859 if (CHIP_REV_IS_EMUL(sc)) {
10860 return FLR_POLL_CNT * 2000;
10863 if (CHIP_REV_IS_FPGA(sc)) {
10864 return FLR_POLL_CNT * 120;
10867 return FLR_POLL_CNT;
10870 static int bnx2x_poll_hw_usage_counters(struct bnx2x_softc *sc, uint32_t poll_cnt)
10872 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
10873 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10874 CFC_REG_NUM_LCIDS_INSIDE_PF,
10875 "CFC PF usage counter timed out",
10880 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
10881 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10882 DORQ_REG_PF_USAGE_CNT,
10883 "DQ PF usage counter timed out",
10888 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
10889 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10890 QM_REG_PF_USG_CNT_0 + 4 * SC_FUNC(sc),
10891 "QM PF usage counter timed out",
10896 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
10897 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10898 TM_REG_LIN0_VNIC_UC + 4 * SC_PORT(sc),
10899 "Timers VNIC usage counter timed out",
10904 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10905 TM_REG_LIN0_NUM_SCANS +
10907 "Timers NUM_SCANS usage counter timed out",
10912 /* Wait DMAE PF usage counter to zero */
10913 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10914 dmae_reg_go_c[INIT_DMAE_C(sc)],
10915 "DMAE dommand register timed out",
10923 #define OP_GEN_PARAM(param) \
10924 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
10925 #define OP_GEN_TYPE(type) \
10926 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
10927 #define OP_GEN_AGG_VECT(index) \
10928 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
10931 bnx2x_send_final_clnup(struct bnx2x_softc *sc, uint8_t clnup_func,
10934 uint32_t op_gen_command = 0;
10935 uint32_t comp_addr = (BAR_CSTRORM_INTMEM +
10936 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func));
10939 if (REG_RD(sc, comp_addr)) {
10940 PMD_DRV_LOG(NOTICE, sc,
10941 "Cleanup complete was not 0 before sending");
10945 op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
10946 op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
10947 op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
10948 op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
10950 REG_WR(sc, XSDM_REG_OPERATION_GEN, op_gen_command);
10952 if (bnx2x_flr_clnup_reg_poll(sc, comp_addr, 1, poll_cnt) != 1) {
10953 PMD_DRV_LOG(NOTICE, sc, "FW final cleanup did not succeed");
10954 PMD_DRV_LOG(DEBUG, sc, "At timeout completion address contained %x",
10955 (REG_RD(sc, comp_addr)));
10956 rte_panic("FLR cleanup failed");
10960 /* Zero completion for nxt FLR */
10961 REG_WR(sc, comp_addr, 0);
10967 bnx2x_pbf_pN_buf_flushed(struct bnx2x_softc *sc, struct pbf_pN_buf_regs *regs,
10968 uint32_t poll_count)
10970 uint32_t init_crd, crd, crd_start, crd_freed, crd_freed_start;
10971 uint32_t cur_cnt = poll_count;
10973 crd_freed = crd_freed_start = REG_RD(sc, regs->crd_freed);
10974 crd = crd_start = REG_RD(sc, regs->crd);
10975 init_crd = REG_RD(sc, regs->init_crd);
10977 while ((crd != init_crd) &&
10978 ((uint32_t) ((int32_t) crd_freed - (int32_t) crd_freed_start) <
10979 (init_crd - crd_start))) {
10981 DELAY(FLR_WAIT_INTERVAL);
10982 crd = REG_RD(sc, regs->crd);
10983 crd_freed = REG_RD(sc, regs->crd_freed);
10991 bnx2x_pbf_pN_cmd_flushed(struct bnx2x_softc *sc, struct pbf_pN_cmd_regs *regs,
10992 uint32_t poll_count)
10994 uint32_t occup, to_free, freed, freed_start;
10995 uint32_t cur_cnt = poll_count;
10997 occup = to_free = REG_RD(sc, regs->lines_occup);
10998 freed = freed_start = REG_RD(sc, regs->lines_freed);
11001 ((uint32_t) ((int32_t) freed - (int32_t) freed_start) <
11004 DELAY(FLR_WAIT_INTERVAL);
11005 occup = REG_RD(sc, regs->lines_occup);
11006 freed = REG_RD(sc, regs->lines_freed);
11013 static void bnx2x_tx_hw_flushed(struct bnx2x_softc *sc, uint32_t poll_count)
11015 struct pbf_pN_cmd_regs cmd_regs[] = {
11016 {0, (CHIP_IS_E3B0(sc)) ?
11017 PBF_REG_TQ_OCCUPANCY_Q0 : PBF_REG_P0_TQ_OCCUPANCY,
11018 (CHIP_IS_E3B0(sc)) ?
11019 PBF_REG_TQ_LINES_FREED_CNT_Q0 : PBF_REG_P0_TQ_LINES_FREED_CNT},
11020 {1, (CHIP_IS_E3B0(sc)) ?
11021 PBF_REG_TQ_OCCUPANCY_Q1 : PBF_REG_P1_TQ_OCCUPANCY,
11022 (CHIP_IS_E3B0(sc)) ?
11023 PBF_REG_TQ_LINES_FREED_CNT_Q1 : PBF_REG_P1_TQ_LINES_FREED_CNT},
11024 {4, (CHIP_IS_E3B0(sc)) ?
11025 PBF_REG_TQ_OCCUPANCY_LB_Q : PBF_REG_P4_TQ_OCCUPANCY,
11026 (CHIP_IS_E3B0(sc)) ?
11027 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
11028 PBF_REG_P4_TQ_LINES_FREED_CNT}
11031 struct pbf_pN_buf_regs buf_regs[] = {
11032 {0, (CHIP_IS_E3B0(sc)) ?
11033 PBF_REG_INIT_CRD_Q0 : PBF_REG_P0_INIT_CRD,
11034 (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q0 : PBF_REG_P0_CREDIT,
11035 (CHIP_IS_E3B0(sc)) ?
11036 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
11037 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
11038 {1, (CHIP_IS_E3B0(sc)) ?
11039 PBF_REG_INIT_CRD_Q1 : PBF_REG_P1_INIT_CRD,
11040 (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q1 : PBF_REG_P1_CREDIT,
11041 (CHIP_IS_E3B0(sc)) ?
11042 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
11043 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
11044 {4, (CHIP_IS_E3B0(sc)) ?
11045 PBF_REG_INIT_CRD_LB_Q : PBF_REG_P4_INIT_CRD,
11046 (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_LB_Q : PBF_REG_P4_CREDIT,
11047 (CHIP_IS_E3B0(sc)) ?
11048 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
11049 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
11054 /* Verify the command queues are flushed P0, P1, P4 */
11055 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) {
11056 bnx2x_pbf_pN_cmd_flushed(sc, &cmd_regs[i], poll_count);
11059 /* Verify the transmission buffers are flushed P0, P1, P4 */
11060 for (i = 0; i < ARRAY_SIZE(buf_regs); i++) {
11061 bnx2x_pbf_pN_buf_flushed(sc, &buf_regs[i], poll_count);
11065 static void bnx2x_hw_enable_status(struct bnx2x_softc *sc)
11067 __rte_unused uint32_t val;
11069 val = REG_RD(sc, CFC_REG_WEAK_ENABLE_PF);
11070 PMD_DRV_LOG(DEBUG, sc, "CFC_REG_WEAK_ENABLE_PF is 0x%x", val);
11072 val = REG_RD(sc, PBF_REG_DISABLE_PF);
11073 PMD_DRV_LOG(DEBUG, sc, "PBF_REG_DISABLE_PF is 0x%x", val);
11075 val = REG_RD(sc, IGU_REG_PCI_PF_MSI_EN);
11076 PMD_DRV_LOG(DEBUG, sc, "IGU_REG_PCI_PF_MSI_EN is 0x%x", val);
11078 val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_EN);
11079 PMD_DRV_LOG(DEBUG, sc, "IGU_REG_PCI_PF_MSIX_EN is 0x%x", val);
11081 val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
11082 PMD_DRV_LOG(DEBUG, sc, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x", val);
11084 val = REG_RD(sc, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
11085 PMD_DRV_LOG(DEBUG, sc,
11086 "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x", val);
11088 val = REG_RD(sc, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
11089 PMD_DRV_LOG(DEBUG, sc,
11090 "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x", val);
11092 val = REG_RD(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
11093 PMD_DRV_LOG(DEBUG, sc, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x",
11098 * bnx2x_pf_flr_clnup
11099 * a. re-enable target read on the PF
11100 * b. poll cfc per function usgae counter
11101 * c. poll the qm perfunction usage counter
11102 * d. poll the tm per function usage counter
11103 * e. poll the tm per function scan-done indication
11104 * f. clear the dmae channel associated wit hthe PF
11105 * g. zero the igu 'trailing edge' and 'leading edge' regs (attentions)
11106 * h. call the common flr cleanup code with -1 (pf indication)
11108 static int bnx2x_pf_flr_clnup(struct bnx2x_softc *sc)
11110 uint32_t poll_cnt = bnx2x_flr_clnup_poll_count(sc);
11112 /* Re-enable PF target read access */
11113 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
11115 /* Poll HW usage counters */
11116 if (bnx2x_poll_hw_usage_counters(sc, poll_cnt)) {
11120 /* Zero the igu 'trailing edge' and 'leading edge' */
11122 /* Send the FW cleanup command */
11123 if (bnx2x_send_final_clnup(sc, (uint8_t) SC_FUNC(sc), poll_cnt)) {
11129 /* Verify TX hw is flushed */
11130 bnx2x_tx_hw_flushed(sc, poll_cnt);
11132 /* Wait 100ms (not adjusted according to platform) */
11135 /* Verify no pending pci transactions */
11136 if (bnx2x_is_pcie_pending(sc)) {
11137 PMD_DRV_LOG(NOTICE, sc, "PCIE Transactions still pending");
11141 bnx2x_hw_enable_status(sc);
11144 * Master enable - Due to WB DMAE writes performed before this
11145 * register is re-initialized as part of the regular function init
11147 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11152 static int bnx2x_init_hw_func(struct bnx2x_softc *sc)
11154 int port = SC_PORT(sc);
11155 int func = SC_FUNC(sc);
11156 int init_phase = PHASE_PF0 + func;
11157 struct ecore_ilt *ilt = sc->ilt;
11158 uint16_t cdu_ilt_start;
11159 uint32_t addr, val;
11160 uint32_t main_mem_base, main_mem_size, main_mem_prty_clr;
11161 int main_mem_width, rc;
11164 PMD_DRV_LOG(DEBUG, sc, "starting func init for func %d", func);
11167 if (!CHIP_IS_E1x(sc)) {
11168 rc = bnx2x_pf_flr_clnup(sc);
11170 PMD_DRV_LOG(NOTICE, sc, "FLR cleanup failed!");
11175 /* set MSI reconfigure capability */
11176 if (sc->devinfo.int_block == INT_BLOCK_HC) {
11177 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
11178 val = REG_RD(sc, addr);
11179 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
11180 REG_WR(sc, addr, val);
11183 ecore_init_block(sc, BLOCK_PXP, init_phase);
11184 ecore_init_block(sc, BLOCK_PXP2, init_phase);
11187 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
11189 for (i = 0; i < L2_ILT_LINES(sc); i++) {
11190 ilt->lines[cdu_ilt_start + i].page = sc->context[i].vcxt;
11191 ilt->lines[cdu_ilt_start + i].page_mapping =
11192 (rte_iova_t)sc->context[i].vcxt_dma.paddr;
11193 ilt->lines[cdu_ilt_start + i].size = sc->context[i].size;
11195 ecore_ilt_init_op(sc, INITOP_SET);
11197 REG_WR(sc, PRS_REG_NIC_MODE, 1);
11199 if (!CHIP_IS_E1x(sc)) {
11200 uint32_t pf_conf = IGU_PF_CONF_FUNC_EN;
11202 /* Turn on a single ISR mode in IGU if driver is going to use
11205 if ((sc->interrupt_mode != INTR_MODE_MSIX)
11206 || (sc->interrupt_mode != INTR_MODE_SINGLE_MSIX)) {
11207 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
11211 * Timers workaround bug: function init part.
11212 * Need to wait 20msec after initializing ILT,
11213 * needed to make sure there are no requests in
11214 * one of the PXP internal queues with "old" ILT addresses
11219 * Master enable - Due to WB DMAE writes performed before this
11220 * register is re-initialized as part of the regular function
11223 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11224 /* Enable the function in IGU */
11225 REG_WR(sc, IGU_REG_PF_CONFIGURATION, pf_conf);
11228 sc->dmae_ready = 1;
11230 ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
11232 if (!CHIP_IS_E1x(sc))
11233 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
11235 ecore_init_block(sc, BLOCK_ATC, init_phase);
11236 ecore_init_block(sc, BLOCK_DMAE, init_phase);
11237 ecore_init_block(sc, BLOCK_NIG, init_phase);
11238 ecore_init_block(sc, BLOCK_SRC, init_phase);
11239 ecore_init_block(sc, BLOCK_MISC, init_phase);
11240 ecore_init_block(sc, BLOCK_TCM, init_phase);
11241 ecore_init_block(sc, BLOCK_UCM, init_phase);
11242 ecore_init_block(sc, BLOCK_CCM, init_phase);
11243 ecore_init_block(sc, BLOCK_XCM, init_phase);
11244 ecore_init_block(sc, BLOCK_TSEM, init_phase);
11245 ecore_init_block(sc, BLOCK_USEM, init_phase);
11246 ecore_init_block(sc, BLOCK_CSEM, init_phase);
11247 ecore_init_block(sc, BLOCK_XSEM, init_phase);
11249 if (!CHIP_IS_E1x(sc))
11250 REG_WR(sc, QM_REG_PF_EN, 1);
11252 if (!CHIP_IS_E1x(sc)) {
11253 REG_WR(sc, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11254 REG_WR(sc, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11255 REG_WR(sc, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11256 REG_WR(sc, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11258 ecore_init_block(sc, BLOCK_QM, init_phase);
11260 ecore_init_block(sc, BLOCK_TM, init_phase);
11261 ecore_init_block(sc, BLOCK_DORQ, init_phase);
11263 ecore_init_block(sc, BLOCK_BRB1, init_phase);
11264 ecore_init_block(sc, BLOCK_PRS, init_phase);
11265 ecore_init_block(sc, BLOCK_TSDM, init_phase);
11266 ecore_init_block(sc, BLOCK_CSDM, init_phase);
11267 ecore_init_block(sc, BLOCK_USDM, init_phase);
11268 ecore_init_block(sc, BLOCK_XSDM, init_phase);
11269 ecore_init_block(sc, BLOCK_UPB, init_phase);
11270 ecore_init_block(sc, BLOCK_XPB, init_phase);
11271 ecore_init_block(sc, BLOCK_PBF, init_phase);
11272 if (!CHIP_IS_E1x(sc))
11273 REG_WR(sc, PBF_REG_DISABLE_PF, 0);
11275 ecore_init_block(sc, BLOCK_CDU, init_phase);
11277 ecore_init_block(sc, BLOCK_CFC, init_phase);
11279 if (!CHIP_IS_E1x(sc))
11280 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 1);
11283 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
11284 REG_WR(sc, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8, OVLAN(sc));
11287 ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
11289 /* HC init per function */
11290 if (sc->devinfo.int_block == INT_BLOCK_HC) {
11291 if (CHIP_IS_E1H(sc)) {
11292 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11294 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11295 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11297 ecore_init_block(sc, BLOCK_HC, init_phase);
11300 uint32_t num_segs, sb_idx, prod_offset;
11302 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11304 if (!CHIP_IS_E1x(sc)) {
11305 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11306 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11309 ecore_init_block(sc, BLOCK_IGU, init_phase);
11311 if (!CHIP_IS_E1x(sc)) {
11315 * E2 mode: address 0-135 match to the mapping memory;
11316 * 136 - PF0 default prod; 137 - PF1 default prod;
11317 * 138 - PF2 default prod; 139 - PF3 default prod;
11318 * 140 - PF0 attn prod; 141 - PF1 attn prod;
11319 * 142 - PF2 attn prod; 143 - PF3 attn prod;
11320 * 144-147 reserved.
11322 * E1.5 mode - In backward compatible mode;
11323 * for non default SB; each even line in the memory
11324 * holds the U producer and each odd line hold
11325 * the C producer. The first 128 producers are for
11326 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
11327 * producers are for the DSB for each PF.
11328 * Each PF has five segments: (the order inside each
11329 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
11330 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
11331 * 144-147 attn prods;
11333 /* non-default-status-blocks */
11334 num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11335 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
11336 for (sb_idx = 0; sb_idx < sc->igu_sb_cnt; sb_idx++) {
11337 prod_offset = (sc->igu_base_sb + sb_idx) *
11340 for (i = 0; i < num_segs; i++) {
11341 addr = IGU_REG_PROD_CONS_MEMORY +
11342 (prod_offset + i) * 4;
11343 REG_WR(sc, addr, 0);
11345 /* send consumer update with value 0 */
11346 bnx2x_ack_sb(sc, sc->igu_base_sb + sb_idx,
11347 USTORM_ID, 0, IGU_INT_NOP, 1);
11348 bnx2x_igu_clear_sb(sc, sc->igu_base_sb + sb_idx);
11351 /* default-status-blocks */
11352 num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11353 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
11355 if (CHIP_IS_MODE_4_PORT(sc))
11356 dsb_idx = SC_FUNC(sc);
11358 dsb_idx = SC_VN(sc);
11360 prod_offset = (CHIP_INT_MODE_IS_BC(sc) ?
11361 IGU_BC_BASE_DSB_PROD + dsb_idx :
11362 IGU_NORM_BASE_DSB_PROD + dsb_idx);
11365 * igu prods come in chunks of E1HVN_MAX (4) -
11366 * does not matters what is the current chip mode
11368 for (i = 0; i < (num_segs * E1HVN_MAX); i += E1HVN_MAX) {
11369 addr = IGU_REG_PROD_CONS_MEMORY +
11370 (prod_offset + i) * 4;
11371 REG_WR(sc, addr, 0);
11373 /* send consumer update with 0 */
11374 if (CHIP_INT_MODE_IS_BC(sc)) {
11375 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11376 USTORM_ID, 0, IGU_INT_NOP, 1);
11377 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11378 CSTORM_ID, 0, IGU_INT_NOP, 1);
11379 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11380 XSTORM_ID, 0, IGU_INT_NOP, 1);
11381 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11382 TSTORM_ID, 0, IGU_INT_NOP, 1);
11383 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11384 ATTENTION_ID, 0, IGU_INT_NOP, 1);
11386 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11387 USTORM_ID, 0, IGU_INT_NOP, 1);
11388 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11389 ATTENTION_ID, 0, IGU_INT_NOP, 1);
11391 bnx2x_igu_clear_sb(sc, sc->igu_dsb_id);
11393 /* !!! these should become driver const once
11394 rf-tool supports split-68 const */
11395 REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
11396 REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
11397 REG_WR(sc, IGU_REG_SB_MASK_LSB, 0);
11398 REG_WR(sc, IGU_REG_SB_MASK_MSB, 0);
11399 REG_WR(sc, IGU_REG_PBA_STATUS_LSB, 0);
11400 REG_WR(sc, IGU_REG_PBA_STATUS_MSB, 0);
11404 /* Reset PCIE errors for debug */
11405 REG_WR(sc, 0x2114, 0xffffffff);
11406 REG_WR(sc, 0x2120, 0xffffffff);
11408 if (CHIP_IS_E1x(sc)) {
11409 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords */
11410 main_mem_base = HC_REG_MAIN_MEMORY +
11411 SC_PORT(sc) * (main_mem_size * 4);
11412 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
11413 main_mem_width = 8;
11415 val = REG_RD(sc, main_mem_prty_clr);
11417 PMD_DRV_LOG(DEBUG, sc,
11418 "Parity errors in HC block during function init (0x%x)!",
11422 /* Clear "false" parity errors in MSI-X table */
11423 for (i = main_mem_base;
11424 i < main_mem_base + main_mem_size * 4;
11425 i += main_mem_width) {
11426 bnx2x_read_dmae(sc, i, main_mem_width / 4);
11427 bnx2x_write_dmae(sc, BNX2X_SP_MAPPING(sc, wb_data),
11428 i, main_mem_width / 4);
11430 /* Clear HC parity attention */
11431 REG_RD(sc, main_mem_prty_clr);
11434 /* Enable STORMs SP logging */
11435 REG_WR8(sc, BAR_USTRORM_INTMEM +
11436 USTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11437 REG_WR8(sc, BAR_TSTRORM_INTMEM +
11438 TSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11439 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11440 CSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11441 REG_WR8(sc, BAR_XSTRORM_INTMEM +
11442 XSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11444 elink_phy_probe(&sc->link_params);
11449 static void bnx2x_link_reset(struct bnx2x_softc *sc)
11451 if (!BNX2X_NOMCP(sc)) {
11452 bnx2x_acquire_phy_lock(sc);
11453 elink_lfa_reset(&sc->link_params, &sc->link_vars);
11454 bnx2x_release_phy_lock(sc);
11456 if (!CHIP_REV_IS_SLOW(sc)) {
11457 PMD_DRV_LOG(WARNING, sc,
11458 "Bootcode is missing - cannot reset link");
11463 static void bnx2x_reset_port(struct bnx2x_softc *sc)
11465 int port = SC_PORT(sc);
11468 /* reset physical Link */
11469 bnx2x_link_reset(sc);
11471 REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
11473 /* Do not rcv packets to BRB */
11474 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + port * 4, 0x0);
11475 /* Do not direct rcv packets that are not for MCP to the BRB */
11476 REG_WR(sc, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
11477 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
11479 /* Configure AEU */
11480 REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, 0);
11484 /* Check for BRB port occupancy */
11485 val = REG_RD(sc, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port * 4);
11487 PMD_DRV_LOG(DEBUG, sc,
11488 "BRB1 is not empty, %d blocks are occupied", val);
11492 static void bnx2x_ilt_wr(struct bnx2x_softc *sc, uint32_t index, rte_iova_t addr)
11495 uint32_t wb_write[2];
11497 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index * 8;
11499 wb_write[0] = ONCHIP_ADDR1(addr);
11500 wb_write[1] = ONCHIP_ADDR2(addr);
11501 REG_WR_DMAE(sc, reg, wb_write, 2);
11504 static void bnx2x_clear_func_ilt(struct bnx2x_softc *sc, uint32_t func)
11506 uint32_t i, base = FUNC_ILT_BASE(func);
11507 for (i = base; i < base + ILT_PER_FUNC; i++) {
11508 bnx2x_ilt_wr(sc, i, 0);
11512 static void bnx2x_reset_func(struct bnx2x_softc *sc)
11514 struct bnx2x_fastpath *fp;
11515 int port = SC_PORT(sc);
11516 int func = SC_FUNC(sc);
11519 /* Disable the function in the FW */
11520 REG_WR8(sc, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
11521 REG_WR8(sc, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
11522 REG_WR8(sc, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
11523 REG_WR8(sc, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
11526 FOR_EACH_ETH_QUEUE(sc, i) {
11528 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11529 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
11534 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11535 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), SB_DISABLED);
11537 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) {
11538 REG_WR(sc, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
11542 /* Configure IGU */
11543 if (sc->devinfo.int_block == INT_BLOCK_HC) {
11544 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11545 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11547 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11548 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11551 if (CNIC_LOADED(sc)) {
11552 /* Disable Timer scan */
11553 REG_WR(sc, TM_REG_EN_LINEAR0_TIMER + port * 4, 0);
11555 * Wait for at least 10ms and up to 2 second for the timers
11558 for (i = 0; i < 200; i++) {
11560 if (!REG_RD(sc, TM_REG_LIN0_SCAN_ON + port * 4))
11566 bnx2x_clear_func_ilt(sc, func);
11569 * Timers workaround bug for E2: if this is vnic-3,
11570 * we need to set the entire ilt range for this timers.
11572 if (!CHIP_IS_E1x(sc) && SC_VN(sc) == 3) {
11573 struct ilt_client_info ilt_cli;
11574 /* use dummy TM client */
11575 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
11577 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
11578 ilt_cli.client_num = ILT_CLIENT_TM;
11580 ecore_ilt_boundary_init_op(sc, &ilt_cli, 0, INITOP_CLEAR);
11583 /* this assumes that reset_port() called before reset_func() */
11584 if (!CHIP_IS_E1x(sc)) {
11585 bnx2x_pf_disable(sc);
11588 sc->dmae_ready = 0;
11591 static void bnx2x_release_firmware(struct bnx2x_softc *sc)
11593 rte_free(sc->init_ops);
11594 rte_free(sc->init_ops_offsets);
11595 rte_free(sc->init_data);
11596 rte_free(sc->iro_array);
11599 static int bnx2x_init_firmware(struct bnx2x_softc *sc)
11602 uint8_t *p = sc->firmware;
11605 for (i = 0; i < 24; ++i)
11606 off[i] = rte_be_to_cpu_32(*((uint32_t *) sc->firmware + i));
11609 sc->init_ops = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11612 bnx2x_data_to_init_ops(p + off[1], sc->init_ops, len);
11615 sc->init_ops_offsets = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11616 if (!sc->init_ops_offsets)
11618 bnx2x_data_to_init_offsets(p + off[3], sc->init_ops_offsets, len);
11621 sc->init_data = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11622 if (!sc->init_data)
11624 bnx2x_data_to_init_data(p + off[5], sc->init_data, len);
11626 sc->tsem_int_table_data = p + off[7];
11627 sc->tsem_pram_data = p + off[9];
11628 sc->usem_int_table_data = p + off[11];
11629 sc->usem_pram_data = p + off[13];
11630 sc->csem_int_table_data = p + off[15];
11631 sc->csem_pram_data = p + off[17];
11632 sc->xsem_int_table_data = p + off[19];
11633 sc->xsem_pram_data = p + off[21];
11636 sc->iro_array = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11637 if (!sc->iro_array)
11639 bnx2x_data_to_iro_array(p + off[23], sc->iro_array, len);
11644 bnx2x_release_firmware(sc);
11648 static int cut_gzip_prefix(const uint8_t * zbuf, int len)
11650 #define MIN_PREFIX_SIZE (10)
11652 int n = MIN_PREFIX_SIZE;
11655 if (!(zbuf[0] == 0x1f && zbuf[1] == 0x8b && zbuf[2] == Z_DEFLATED) ||
11656 len <= MIN_PREFIX_SIZE) {
11660 /* optional extra fields are present */
11661 if (zbuf[3] & 0x4) {
11668 /* file name is present */
11669 if (zbuf[3] & 0x8) {
11670 while ((zbuf[n++] != 0) && (n < len)) ;
11676 static int ecore_gunzip(struct bnx2x_softc *sc, const uint8_t * zbuf, int len)
11679 int data_begin = cut_gzip_prefix(zbuf, len);
11681 PMD_DRV_LOG(DEBUG, sc, "ecore_gunzip %d", len);
11683 if (data_begin <= 0) {
11684 PMD_DRV_LOG(NOTICE, sc, "bad gzip prefix");
11688 memset(&zlib_stream, 0, sizeof(zlib_stream));
11689 zlib_stream.next_in = zbuf + data_begin;
11690 zlib_stream.avail_in = len - data_begin;
11691 zlib_stream.next_out = sc->gz_buf;
11692 zlib_stream.avail_out = FW_BUF_SIZE;
11694 ret = inflateInit2(&zlib_stream, -MAX_WBITS);
11696 PMD_DRV_LOG(NOTICE, sc, "zlib inflateInit2 error");
11700 ret = inflate(&zlib_stream, Z_FINISH);
11701 if ((ret != Z_STREAM_END) && (ret != Z_OK)) {
11702 PMD_DRV_LOG(NOTICE, sc, "zlib inflate error: %d %s", ret,
11706 sc->gz_outlen = zlib_stream.total_out;
11707 if (sc->gz_outlen & 0x3) {
11708 PMD_DRV_LOG(NOTICE, sc, "firmware is not aligned. gz_outlen == %d",
11711 sc->gz_outlen >>= 2;
11713 inflateEnd(&zlib_stream);
11715 if (ret == Z_STREAM_END)
11722 ecore_write_dmae_phys_len(struct bnx2x_softc *sc, rte_iova_t phys_addr,
11723 uint32_t addr, uint32_t len)
11725 bnx2x_write_dmae_phys_len(sc, phys_addr, addr, len);
11729 ecore_storm_memset_struct(struct bnx2x_softc *sc, uint32_t addr, size_t size,
11733 for (i = 0; i < size / 4; i++) {
11734 REG_WR(sc, addr + (i * 4), data[i]);
11738 static const char *get_ext_phy_type(uint32_t ext_phy_type)
11740 uint32_t phy_type_idx = ext_phy_type >> 8;
11741 static const char *types[] =
11742 { "DIRECT", "BNX2X-8071", "BNX2X-8072", "BNX2X-8073",
11743 "BNX2X-8705", "BNX2X-8706", "BNX2X-8726", "BNX2X-8481", "SFX-7101",
11745 "BNX2X-8727-NOC", "BNX2X-84823", "NOT_CONN", "FAILURE"
11748 if (phy_type_idx < 12)
11749 return types[phy_type_idx];
11750 else if (PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN == ext_phy_type)
11756 static const char *get_state(uint32_t state)
11758 uint32_t state_idx = state >> 12;
11759 static const char *states[] = { "CLOSED", "OPENING_WAIT4_LOAD",
11760 "OPENING_WAIT4_PORT", "OPEN", "CLOSING_WAIT4_HALT",
11761 "CLOSING_WAIT4_DELETE", "CLOSING_WAIT4_UNLOAD",
11762 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
11763 "UNKNOWN", "DISABLED", "DIAG", "ERROR", "UNDEFINED"
11766 if (state_idx <= 0xF)
11767 return states[state_idx];
11769 return states[0x10];
11772 static const char *get_recovery_state(uint32_t state)
11774 static const char *states[] = { "NONE", "DONE", "INIT",
11775 "WAIT", "FAILED", "NIC_LOADING"
11777 return states[state];
11780 static const char *get_rx_mode(uint32_t mode)
11782 static const char *modes[] = { "NONE", "NORMAL", "ALLMULTI",
11783 "PROMISC", "MAX_MULTICAST", "ERROR"
11787 return modes[mode];
11788 else if (BNX2X_MAX_MULTICAST == mode)
11794 #define BNX2X_INFO_STR_MAX 256
11795 static const char *get_bnx2x_flags(uint32_t flags)
11798 static const char *flag[] = { "ONE_PORT ", "NO_ISCSI ",
11799 "NO_FCOE ", "NO_WOL ", "USING_DAC ", "USING_MSIX ",
11800 "USING_MSI ", "DISABLE_MSI ", "UNKNOWN ", "NO_MCP ",
11801 "SAFC_TX_FLAG ", "MF_FUNC_DIS ", "TX_SWITCHING "
11803 static char flag_str[BNX2X_INFO_STR_MAX];
11804 memset(flag_str, 0, BNX2X_INFO_STR_MAX);
11806 for (i = 0; i < 5; i++)
11807 if (flags & (1 << i)) {
11808 strlcat(flag_str, flag[i], sizeof(flag_str));
11812 static char unknown[BNX2X_INFO_STR_MAX];
11813 snprintf(unknown, 32, "Unknown flag mask %x", flags);
11814 strlcat(flag_str, unknown, sizeof(flag_str));
11819 /* Prints useful adapter info. */
11820 void bnx2x_print_adapter_info(struct bnx2x_softc *sc)
11824 PMD_DRV_LOG(INFO, sc, "========================================");
11825 /* DPDK and Driver versions */
11826 PMD_DRV_LOG(INFO, sc, "%12s : %s", "DPDK",
11828 PMD_DRV_LOG(INFO, sc, "%12s : %s", "Driver",
11829 bnx2x_pmd_version());
11830 /* Firmware versions. */
11831 PMD_DRV_LOG(INFO, sc, "%12s : %d.%d.%d",
11833 BNX2X_5710_FW_MAJOR_VERSION,
11834 BNX2X_5710_FW_MINOR_VERSION,
11835 BNX2X_5710_FW_REVISION_VERSION);
11836 PMD_DRV_LOG(INFO, sc, "%12s : %s",
11837 "Bootcode", sc->devinfo.bc_ver_str);
11838 /* Hardware chip info. */
11839 PMD_DRV_LOG(INFO, sc, "%12s : %#08x", "ASIC", sc->devinfo.chip_id);
11840 PMD_DRV_LOG(INFO, sc, "%12s : %c%d", "Rev", (CHIP_REV(sc) >> 12) + 'A',
11841 (CHIP_METAL(sc) >> 4));
11842 /* Bus PCIe info. */
11843 PMD_DRV_LOG(INFO, sc, "%12s : 0x%x", "Vendor Id",
11844 sc->devinfo.vendor_id);
11845 PMD_DRV_LOG(INFO, sc, "%12s : 0x%x", "Device Id",
11846 sc->devinfo.device_id);
11847 PMD_DRV_LOG(INFO, sc, "%12s : width x%d, ", "Bus PCIe",
11848 sc->devinfo.pcie_link_width);
11849 switch (sc->devinfo.pcie_link_speed) {
11851 PMD_DRV_LOG(INFO, sc, "%23s", "2.5 Gbps");
11854 PMD_DRV_LOG(INFO, sc, "%21s", "5 Gbps");
11857 PMD_DRV_LOG(INFO, sc, "%21s", "8 Gbps");
11860 PMD_DRV_LOG(INFO, sc, "%33s", "Unknown link speed");
11862 /* Device features. */
11863 PMD_DRV_LOG(INFO, sc, "%12s : ", "Flags");
11864 /* Miscellaneous flags. */
11865 if (sc->devinfo.pcie_cap_flags & BNX2X_MSI_CAPABLE_FLAG) {
11866 PMD_DRV_LOG(INFO, sc, "%18s", "MSI");
11869 if (sc->devinfo.pcie_cap_flags & BNX2X_MSIX_CAPABLE_FLAG) {
11871 PMD_DRV_LOG(INFO, sc, "|");
11872 PMD_DRV_LOG(INFO, sc, "%20s", "MSI-X");
11875 PMD_DRV_LOG(INFO, sc, "%12s : %s", "OVLAN", (OVLAN(sc) ? "YES" : "NO"));
11876 PMD_DRV_LOG(INFO, sc, "%12s : %s", "MF", (IS_MF(sc) ? "YES" : "NO"));
11877 PMD_DRV_LOG(INFO, sc, "========================================");
11880 /* Prints useful device info. */
11881 void bnx2x_print_device_info(struct bnx2x_softc *sc)
11883 __rte_unused uint32_t ext_phy_type;
11884 uint32_t offset, reg_val;
11886 PMD_INIT_FUNC_TRACE(sc);
11887 offset = offsetof(struct shmem_region,
11888 dev_info.port_hw_config[0].external_phy_config);
11889 reg_val = REG_RD(sc, sc->devinfo.shmem_base + offset);
11890 if (sc->link_vars.phy_flags & PHY_XGXS_FLAG)
11891 ext_phy_type = ELINK_XGXS_EXT_PHY_TYPE(reg_val);
11893 ext_phy_type = ELINK_SERDES_EXT_PHY_TYPE(reg_val);
11895 /* Device features. */
11896 PMD_DRV_LOG(INFO, sc, "%12s : %u", "Bnx2x Func", sc->pcie_func);
11897 PMD_DRV_LOG(INFO, sc,
11898 "%12s : %s", "Bnx2x Flags", get_bnx2x_flags(sc->flags));
11899 PMD_DRV_LOG(INFO, sc, "%12s : %s", "DMAE Is",
11900 (sc->dmae_ready ? "Ready" : "Not Ready"));
11901 PMD_DRV_LOG(INFO, sc, "%12s : %u", "MTU", sc->mtu);
11902 PMD_DRV_LOG(INFO, sc,
11903 "%12s : %s", "PHY Type", get_ext_phy_type(ext_phy_type));
11904 PMD_DRV_LOG(INFO, sc, "%12s : %x:%x:%x:%x:%x:%x", "MAC Addr",
11905 sc->link_params.mac_addr[0],
11906 sc->link_params.mac_addr[1],
11907 sc->link_params.mac_addr[2],
11908 sc->link_params.mac_addr[3],
11909 sc->link_params.mac_addr[4],
11910 sc->link_params.mac_addr[5]);
11911 PMD_DRV_LOG(INFO, sc, "%12s : %s", "RX Mode", get_rx_mode(sc->rx_mode));
11912 PMD_DRV_LOG(INFO, sc, "%12s : %s", "State", get_state(sc->state));
11913 if (sc->recovery_state)
11914 PMD_DRV_LOG(INFO, sc, "%12s : %s", "Recovery",
11915 get_recovery_state(sc->recovery_state));
11918 switch (sc->sp->rss_rdata.rss_mode) {
11919 case ETH_RSS_MODE_DISABLED:
11920 PMD_DRV_LOG(INFO, sc, "%12s : %s", "Queues", "RSS mode - None");
11922 case ETH_RSS_MODE_REGULAR:
11923 PMD_DRV_LOG(INFO, sc, "%12s : %s,", "Queues", "RSS mode - Regular");
11924 PMD_DRV_LOG(INFO, sc, "%16d", sc->num_queues);
11927 PMD_DRV_LOG(INFO, sc, "%12s : %s", "Queues", "RSS mode - Unknown");
11931 PMD_DRV_LOG(INFO, sc, "%12s : CQ = %lx, EQ = %lx", "SPQ Left",
11932 sc->cq_spq_left, sc->eq_spq_left);
11934 PMD_DRV_LOG(INFO, sc,
11935 "%12s : %x", "Switch", sc->link_params.switch_cfg);
11936 PMD_DRV_LOG(INFO, sc, "pcie_bus=%d, pcie_device=%d",
11937 sc->pcie_bus, sc->pcie_device);
11938 PMD_DRV_LOG(INFO, sc, "bar0.addr=%p, bar1.addr=%p",
11939 sc->bar[BAR0].base_addr, sc->bar[BAR1].base_addr);
11940 PMD_DRV_LOG(INFO, sc, "port=%d, path=%d, vnic=%d, func=%d",
11941 PORT_ID(sc), PATH_ID(sc), VNIC_ID(sc), FUNC_ID(sc));