2 * Copyright (c) 2007-2013 Broadcom Corporation.
4 * Eric Davis <edavis@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
6 * Gary Zambrano <zambrano@broadcom.com>
8 * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
9 * Copyright (c) 2015-2018 Cavium Inc.
10 * All rights reserved.
13 * See LICENSE.bnx2x_pmd for copyright and licensing details.
16 #define BNX2X_DRIVER_VERSION "1.78.18"
19 #include "bnx2x_vfpf.h"
21 #include "ecore_init.h"
22 #include "ecore_init_ops.h"
24 #include "rte_version.h"
26 #include <sys/types.h>
31 #define BNX2X_PMD_VER_PREFIX "BNX2X PMD"
32 #define BNX2X_PMD_VERSION_MAJOR 1
33 #define BNX2X_PMD_VERSION_MINOR 0
34 #define BNX2X_PMD_VERSION_REVISION 5
35 #define BNX2X_PMD_VERSION_PATCH 1
37 static inline const char *
38 bnx2x_pmd_version(void)
40 static char version[32];
42 snprintf(version, sizeof(version), "%s %s_%d.%d.%d.%d",
45 BNX2X_PMD_VERSION_MAJOR,
46 BNX2X_PMD_VERSION_MINOR,
47 BNX2X_PMD_VERSION_REVISION,
48 BNX2X_PMD_VERSION_PATCH);
53 static z_stream zlib_stream;
55 #define EVL_VLID_MASK 0x0FFF
57 #define BNX2X_DEF_SB_ATT_IDX 0x0001
58 #define BNX2X_DEF_SB_IDX 0x0002
61 * FLR Support - bnx2x_pf_flr_clnup() is called during nic_load in the per
62 * function HW initialization.
64 #define FLR_WAIT_USEC 10000 /* 10 msecs */
65 #define FLR_WAIT_INTERVAL 50 /* usecs */
66 #define FLR_POLL_CNT (FLR_WAIT_USEC / FLR_WAIT_INTERVAL) /* 200 */
68 struct pbf_pN_buf_regs {
75 struct pbf_pN_cmd_regs {
81 /* resources needed for unloading a previously loaded device */
83 #define BNX2X_PREV_WAIT_NEEDED 1
84 rte_spinlock_t bnx2x_prev_mtx;
85 struct bnx2x_prev_list_node {
86 LIST_ENTRY(bnx2x_prev_list_node) node;
94 static LIST_HEAD(, bnx2x_prev_list_node) bnx2x_prev_list
95 = LIST_HEAD_INITIALIZER(bnx2x_prev_list);
97 static int load_count[2][3] = { { 0 } };
98 /* per-path: 0-common, 1-port0, 2-port1 */
100 static void bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg,
102 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc);
103 static void storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng,
105 static void bnx2x_set_reset_global(struct bnx2x_softc *sc);
106 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc);
107 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine);
108 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc);
109 static uint8_t bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global,
111 static void bnx2x_int_disable(struct bnx2x_softc *sc);
112 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc);
113 static void bnx2x_pf_disable(struct bnx2x_softc *sc);
114 static void bnx2x_update_rx_prod(struct bnx2x_softc *sc,
115 struct bnx2x_fastpath *fp,
116 uint16_t rx_bd_prod, uint16_t rx_cq_prod);
117 static void bnx2x_link_report(struct bnx2x_softc *sc);
118 void bnx2x_link_status_update(struct bnx2x_softc *sc);
119 static int bnx2x_alloc_mem(struct bnx2x_softc *sc);
120 static void bnx2x_free_mem(struct bnx2x_softc *sc);
121 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc);
122 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc);
123 static __rte_noinline
124 int bnx2x_nic_load(struct bnx2x_softc *sc);
126 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc);
127 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp, int scan_fp);
128 static void bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id,
129 uint8_t storm, uint16_t index, uint8_t op,
132 int bnx2x_test_bit(int nr, volatile unsigned long *addr)
137 res = ((*addr) & (1UL << nr)) != 0;
142 void bnx2x_set_bit(unsigned int nr, volatile unsigned long *addr)
144 __sync_fetch_and_or(addr, (1UL << nr));
147 void bnx2x_clear_bit(int nr, volatile unsigned long *addr)
149 __sync_fetch_and_and(addr, ~(1UL << nr));
152 int bnx2x_test_and_clear_bit(int nr, volatile unsigned long *addr)
154 unsigned long mask = (1UL << nr);
155 return __sync_fetch_and_and(addr, ~mask) & mask;
158 int bnx2x_cmpxchg(volatile int *addr, int old, int new)
160 return __sync_val_compare_and_swap(addr, old, new);
164 bnx2x_dma_alloc(struct bnx2x_softc *sc, size_t size, struct bnx2x_dma *dma,
165 const char *msg, uint32_t align)
167 char mz_name[RTE_MEMZONE_NAMESIZE];
168 const struct rte_memzone *z;
172 snprintf(mz_name, sizeof(mz_name), "bnx2x%d_%s_%" PRIx64, SC_ABS_FUNC(sc), msg,
173 rte_get_timer_cycles());
175 snprintf(mz_name, sizeof(mz_name), "bnx2x%d_%s_%" PRIx64, sc->pcie_device, msg,
176 rte_get_timer_cycles());
178 /* Caller must take care that strlen(mz_name) < RTE_MEMZONE_NAMESIZE */
179 z = rte_memzone_reserve_aligned(mz_name, (uint64_t)size,
181 RTE_MEMZONE_IOVA_CONTIG, align);
183 PMD_DRV_LOG(ERR, "DMA alloc failed for %s", msg);
186 dma->paddr = (uint64_t) z->iova;
187 dma->vaddr = z->addr;
189 PMD_DRV_LOG(DEBUG, "%s: virt=%p phys=%" PRIx64, msg, dma->vaddr, dma->paddr);
194 static int bnx2x_acquire_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
196 uint32_t lock_status;
197 uint32_t resource_bit = (1 << resource);
198 int func = SC_FUNC(sc);
199 uint32_t hw_lock_control_reg;
202 PMD_INIT_FUNC_TRACE();
204 /* validate the resource is within range */
205 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
207 "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
213 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
215 hw_lock_control_reg =
216 (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
219 /* validate the resource is not already taken */
220 lock_status = REG_RD(sc, hw_lock_control_reg);
221 if (lock_status & resource_bit) {
223 "resource in use (status 0x%x bit 0x%x)",
224 lock_status, resource_bit);
228 /* try every 5ms for 5 seconds */
229 for (cnt = 0; cnt < 1000; cnt++) {
230 REG_WR(sc, (hw_lock_control_reg + 4), resource_bit);
231 lock_status = REG_RD(sc, hw_lock_control_reg);
232 if (lock_status & resource_bit) {
238 PMD_DRV_LOG(NOTICE, "Resource lock timeout!");
242 static int bnx2x_release_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
244 uint32_t lock_status;
245 uint32_t resource_bit = (1 << resource);
246 int func = SC_FUNC(sc);
247 uint32_t hw_lock_control_reg;
249 PMD_INIT_FUNC_TRACE();
251 /* validate the resource is within range */
252 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
254 "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
260 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
262 hw_lock_control_reg =
263 (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
266 /* validate the resource is currently taken */
267 lock_status = REG_RD(sc, hw_lock_control_reg);
268 if (!(lock_status & resource_bit)) {
270 "resource not in use (status 0x%x bit 0x%x)",
271 lock_status, resource_bit);
275 REG_WR(sc, hw_lock_control_reg, resource_bit);
279 /* copy command into DMAE command memory and set DMAE command Go */
280 void bnx2x_post_dmae(struct bnx2x_softc *sc, struct dmae_command *dmae, int idx)
285 cmd_offset = (DMAE_REG_CMD_MEM + (sizeof(struct dmae_command) * idx));
286 for (i = 0; i < ((sizeof(struct dmae_command) / 4)); i++) {
287 REG_WR(sc, (cmd_offset + (i * 4)), *(((uint32_t *) dmae) + i));
290 REG_WR(sc, dmae_reg_go_c[idx], 1);
293 uint32_t bnx2x_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type)
295 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
296 DMAE_COMMAND_C_TYPE_ENABLE);
299 uint32_t bnx2x_dmae_opcode_clr_src_reset(uint32_t opcode)
301 return opcode & ~DMAE_COMMAND_SRC_RESET;
305 bnx2x_dmae_opcode(struct bnx2x_softc * sc, uint8_t src_type, uint8_t dst_type,
306 uint8_t with_comp, uint8_t comp_type)
310 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
311 (dst_type << DMAE_COMMAND_DST_SHIFT));
313 opcode |= (DMAE_COMMAND_SRC_RESET | DMAE_COMMAND_DST_RESET);
315 opcode |= (SC_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
317 opcode |= ((SC_VN(sc) << DMAE_COMMAND_E1HVN_SHIFT) |
318 (SC_VN(sc) << DMAE_COMMAND_DST_VN_SHIFT));
320 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
323 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
325 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
329 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
336 bnx2x_prep_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae,
337 uint8_t src_type, uint8_t dst_type)
339 memset(dmae, 0, sizeof(struct dmae_command));
342 dmae->opcode = bnx2x_dmae_opcode(sc, src_type, dst_type,
343 TRUE, DMAE_COMP_PCI);
345 /* fill in the completion parameters */
346 dmae->comp_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_comp));
347 dmae->comp_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_comp));
348 dmae->comp_val = DMAE_COMP_VAL;
351 /* issue a DMAE command over the init channel and wait for completion */
353 bnx2x_issue_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae)
355 uint32_t *wb_comp = BNX2X_SP(sc, wb_comp);
356 int timeout = CHIP_REV_IS_SLOW(sc) ? 400000 : 4000;
358 /* reset completion */
361 /* post the command on the channel used for initializations */
362 bnx2x_post_dmae(sc, dmae, INIT_DMAE_C(sc));
364 /* wait for completion */
367 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
369 (sc->recovery_state != BNX2X_RECOVERY_DONE &&
370 sc->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
371 PMD_DRV_LOG(INFO, "DMAE timeout!");
379 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
380 PMD_DRV_LOG(INFO, "DMAE PCI error!");
381 return DMAE_PCI_ERROR;
387 void bnx2x_read_dmae(struct bnx2x_softc *sc, uint32_t src_addr, uint32_t len32)
389 struct dmae_command dmae;
394 if (!sc->dmae_ready) {
395 data = BNX2X_SP(sc, wb_data[0]);
397 for (i = 0; i < len32; i++) {
398 data[i] = REG_RD(sc, (src_addr + (i * 4)));
404 /* set opcode and fixed command fields */
405 bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
407 /* fill in addresses and len */
408 dmae.src_addr_lo = (src_addr >> 2); /* GRC addr has dword resolution */
409 dmae.src_addr_hi = 0;
410 dmae.dst_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_data));
411 dmae.dst_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_data));
414 /* issue the command and wait for completion */
415 if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
416 rte_panic("DMAE failed (%d)", rc);
421 bnx2x_write_dmae(struct bnx2x_softc *sc, rte_iova_t dma_addr, uint32_t dst_addr,
424 struct dmae_command dmae;
427 if (!sc->dmae_ready) {
428 ecore_init_str_wr(sc, dst_addr, BNX2X_SP(sc, wb_data[0]), len32);
432 /* set opcode and fixed command fields */
433 bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
435 /* fill in addresses and len */
436 dmae.src_addr_lo = U64_LO(dma_addr);
437 dmae.src_addr_hi = U64_HI(dma_addr);
438 dmae.dst_addr_lo = (dst_addr >> 2); /* GRC addr has dword resolution */
439 dmae.dst_addr_hi = 0;
442 /* issue the command and wait for completion */
443 if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
444 rte_panic("DMAE failed (%d)", rc);
449 bnx2x_write_dmae_phys_len(struct bnx2x_softc *sc, rte_iova_t phys_addr,
450 uint32_t addr, uint32_t len)
452 uint32_t dmae_wr_max = DMAE_LEN32_WR_MAX(sc);
455 while (len > dmae_wr_max) {
456 bnx2x_write_dmae(sc, (phys_addr + offset), /* src DMA address */
457 (addr + offset), /* dst GRC address */
459 offset += (dmae_wr_max * 4);
463 bnx2x_write_dmae(sc, (phys_addr + offset), /* src DMA address */
464 (addr + offset), /* dst GRC address */
469 bnx2x_set_ctx_validation(struct bnx2x_softc *sc, struct eth_context *cxt,
472 /* ustorm cxt validation */
473 cxt->ustorm_ag_context.cdu_usage =
474 CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
475 CDU_REGION_NUMBER_UCM_AG,
476 ETH_CONNECTION_TYPE);
477 /* xcontext validation */
478 cxt->xstorm_ag_context.cdu_reserved =
479 CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
480 CDU_REGION_NUMBER_XCM_AG,
481 ETH_CONNECTION_TYPE);
485 bnx2x_storm_memset_hc_timeout(struct bnx2x_softc *sc, uint8_t fw_sb_id,
486 uint8_t sb_index, uint8_t ticks)
489 (BAR_CSTRORM_INTMEM +
490 CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(fw_sb_id, sb_index));
492 REG_WR8(sc, addr, ticks);
496 bnx2x_storm_memset_hc_disable(struct bnx2x_softc *sc, uint16_t fw_sb_id,
497 uint8_t sb_index, uint8_t disable)
499 uint32_t enable_flag =
500 (disable) ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
502 (BAR_CSTRORM_INTMEM +
503 CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(fw_sb_id, sb_index));
507 flags = REG_RD8(sc, addr);
508 flags &= ~HC_INDEX_DATA_HC_ENABLED;
509 flags |= enable_flag;
510 REG_WR8(sc, addr, flags);
514 bnx2x_update_coalesce_sb_index(struct bnx2x_softc *sc, uint8_t fw_sb_id,
515 uint8_t sb_index, uint8_t disable, uint16_t usec)
517 uint8_t ticks = (usec / 4);
519 bnx2x_storm_memset_hc_timeout(sc, fw_sb_id, sb_index, ticks);
521 disable = (disable) ? 1 : ((usec) ? 0 : 1);
522 bnx2x_storm_memset_hc_disable(sc, fw_sb_id, sb_index, disable);
525 uint32_t elink_cb_reg_read(struct bnx2x_softc *sc, uint32_t reg_addr)
527 return REG_RD(sc, reg_addr);
530 void elink_cb_reg_write(struct bnx2x_softc *sc, uint32_t reg_addr, uint32_t val)
532 REG_WR(sc, reg_addr, val);
536 elink_cb_event_log(__rte_unused struct bnx2x_softc *sc,
537 __rte_unused const elink_log_id_t elink_log_id, ...)
539 PMD_DRV_LOG(DEBUG, "ELINK EVENT LOG (%d)", elink_log_id);
542 static int bnx2x_set_spio(struct bnx2x_softc *sc, int spio, uint32_t mode)
546 /* Only 2 SPIOs are configurable */
547 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
548 PMD_DRV_LOG(NOTICE, "Invalid SPIO 0x%x", spio);
552 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
554 /* read SPIO and mask except the float bits */
555 spio_reg = (REG_RD(sc, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
558 case MISC_SPIO_OUTPUT_LOW:
559 /* clear FLOAT and set CLR */
560 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
561 spio_reg |= (spio << MISC_SPIO_CLR_POS);
564 case MISC_SPIO_OUTPUT_HIGH:
565 /* clear FLOAT and set SET */
566 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
567 spio_reg |= (spio << MISC_SPIO_SET_POS);
570 case MISC_SPIO_INPUT_HI_Z:
572 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
579 REG_WR(sc, MISC_REG_SPIO, spio_reg);
580 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
585 static int bnx2x_gpio_read(struct bnx2x_softc *sc, int gpio_num, uint8_t port)
587 /* The GPIO should be swapped if swap register is set and active */
588 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
589 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
590 int gpio_shift = gpio_num;
592 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
594 uint32_t gpio_mask = (1 << gpio_shift);
597 if (gpio_num > MISC_REGISTERS_GPIO_3) {
598 PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
602 /* read GPIO value */
603 gpio_reg = REG_RD(sc, MISC_REG_GPIO);
605 /* get the requested pin value */
606 return ((gpio_reg & gpio_mask) == gpio_mask) ? 1 : 0;
610 bnx2x_gpio_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode, uint8_t port)
612 /* The GPIO should be swapped if swap register is set and active */
613 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
614 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
615 int gpio_shift = gpio_num;
617 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
619 uint32_t gpio_mask = (1 << gpio_shift);
622 if (gpio_num > MISC_REGISTERS_GPIO_3) {
623 PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
627 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
629 /* read GPIO and mask except the float bits */
630 gpio_reg = (REG_RD(sc, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
633 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
634 /* clear FLOAT and set CLR */
635 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
636 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
639 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
640 /* clear FLOAT and set SET */
641 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
642 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
645 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
647 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
654 REG_WR(sc, MISC_REG_GPIO, gpio_reg);
655 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
661 bnx2x_gpio_mult_write(struct bnx2x_softc *sc, uint8_t pins, uint32_t mode)
665 /* any port swapping should be handled by caller */
667 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
669 /* read GPIO and mask except the float bits */
670 gpio_reg = REG_RD(sc, MISC_REG_GPIO);
671 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
672 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
673 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
676 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
678 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
681 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
683 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
686 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
688 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
692 PMD_DRV_LOG(NOTICE, "Invalid GPIO mode assignment %d", mode);
693 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
697 REG_WR(sc, MISC_REG_GPIO, gpio_reg);
698 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
704 bnx2x_gpio_int_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode,
707 /* The GPIO should be swapped if swap register is set and active */
708 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
709 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
710 int gpio_shift = gpio_num;
712 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
714 uint32_t gpio_mask = (1 << gpio_shift);
717 if (gpio_num > MISC_REGISTERS_GPIO_3) {
718 PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
722 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
725 gpio_reg = REG_RD(sc, MISC_REG_GPIO_INT);
728 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
729 /* clear SET and set CLR */
730 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
731 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
734 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
735 /* clear CLR and set SET */
736 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
737 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
744 REG_WR(sc, MISC_REG_GPIO_INT, gpio_reg);
745 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
751 elink_cb_gpio_read(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t port)
753 return bnx2x_gpio_read(sc, gpio_num, port);
756 uint8_t elink_cb_gpio_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode, /* 0=low 1=high */
759 return bnx2x_gpio_write(sc, gpio_num, mode, port);
763 elink_cb_gpio_mult_write(struct bnx2x_softc * sc, uint8_t pins,
764 uint8_t mode /* 0=low 1=high */ )
766 return bnx2x_gpio_mult_write(sc, pins, mode);
769 uint8_t elink_cb_gpio_int_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode, /* 0=low 1=high */
772 return bnx2x_gpio_int_write(sc, gpio_num, mode, port);
775 void elink_cb_notify_link_changed(struct bnx2x_softc *sc)
777 REG_WR(sc, (MISC_REG_AEU_GENERAL_ATTN_12 +
778 (SC_FUNC(sc) * sizeof(uint32_t))), 1);
781 /* send the MCP a request, block until there is a reply */
783 elink_cb_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
785 int mb_idx = SC_FW_MB_IDX(sc);
789 uint8_t delay = CHIP_REV_IS_SLOW(sc) ? 100 : 10;
792 SHMEM_WR(sc, func_mb[mb_idx].drv_mb_param, param);
793 SHMEM_WR(sc, func_mb[mb_idx].drv_mb_header, (command | seq));
796 "wrote command 0x%08x to FW MB param 0x%08x",
797 (command | seq), param);
799 /* Let the FW do it's magic. GIve it up to 5 seconds... */
802 rc = SHMEM_RD(sc, func_mb[mb_idx].fw_mb_header);
803 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
805 /* is this a reply to our command? */
806 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) {
807 rc &= FW_MSG_CODE_MASK;
810 PMD_DRV_LOG(NOTICE, "FW failed to respond!");
818 bnx2x_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
820 return elink_cb_fw_command(sc, command, param);
824 __storm_memset_dma_mapping(struct bnx2x_softc *sc, uint32_t addr,
827 REG_WR(sc, addr, U64_LO(mapping));
828 REG_WR(sc, (addr + 4), U64_HI(mapping));
832 storm_memset_spq_addr(struct bnx2x_softc *sc, rte_iova_t mapping,
835 uint32_t addr = (XSEM_REG_FAST_MEMORY +
836 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid));
837 __storm_memset_dma_mapping(sc, addr, mapping);
841 storm_memset_vf_to_pf(struct bnx2x_softc *sc, uint16_t abs_fid, uint16_t pf_id)
843 REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid)),
845 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid)),
847 REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid)),
849 REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid)),
854 storm_memset_func_en(struct bnx2x_softc *sc, uint16_t abs_fid, uint8_t enable)
856 REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid)),
858 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid)),
860 REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid)),
862 REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid)),
867 storm_memset_eq_data(struct bnx2x_softc *sc, struct event_ring_data *eq_data,
873 addr = (BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid));
874 size = sizeof(struct event_ring_data);
875 ecore_storm_memset_struct(sc, addr, size, (uint32_t *) eq_data);
879 storm_memset_eq_prod(struct bnx2x_softc *sc, uint16_t eq_prod, uint16_t pfid)
881 uint32_t addr = (BAR_CSTRORM_INTMEM +
882 CSTORM_EVENT_RING_PROD_OFFSET(pfid));
883 REG_WR16(sc, addr, eq_prod);
887 * Post a slowpath command.
889 * A slowpath command is used to propagate a configuration change through
890 * the controller in a controlled manner, allowing each STORM processor and
891 * other H/W blocks to phase in the change. The commands sent on the
892 * slowpath are referred to as ramrods. Depending on the ramrod used the
893 * completion of the ramrod will occur in different ways. Here's a
894 * breakdown of ramrods and how they complete:
896 * RAMROD_CMD_ID_ETH_PORT_SETUP
897 * Used to setup the leading connection on a port. Completes on the
898 * Receive Completion Queue (RCQ) of that port (typically fp[0]).
900 * RAMROD_CMD_ID_ETH_CLIENT_SETUP
901 * Used to setup an additional connection on a port. Completes on the
902 * RCQ of the multi-queue/RSS connection being initialized.
904 * RAMROD_CMD_ID_ETH_STAT_QUERY
905 * Used to force the storm processors to update the statistics database
906 * in host memory. This ramrod is send on the leading connection CID and
907 * completes as an index increment of the CSTORM on the default status
910 * RAMROD_CMD_ID_ETH_UPDATE
911 * Used to update the state of the leading connection, usually to udpate
912 * the RSS indirection table. Completes on the RCQ of the leading
913 * connection. (Not currently used under FreeBSD until OS support becomes
916 * RAMROD_CMD_ID_ETH_HALT
917 * Used when tearing down a connection prior to driver unload. Completes
918 * on the RCQ of the multi-queue/RSS connection being torn down. Don't
919 * use this on the leading connection.
921 * RAMROD_CMD_ID_ETH_SET_MAC
922 * Sets the Unicast/Broadcast/Multicast used by the port. Completes on
923 * the RCQ of the leading connection.
925 * RAMROD_CMD_ID_ETH_CFC_DEL
926 * Used when tearing down a conneciton prior to driver unload. Completes
927 * on the RCQ of the leading connection (since the current connection
928 * has been completely removed from controller memory).
930 * RAMROD_CMD_ID_ETH_PORT_DEL
931 * Used to tear down the leading connection prior to driver unload,
932 * typically fp[0]. Completes as an index increment of the CSTORM on the
933 * default status block.
935 * RAMROD_CMD_ID_ETH_FORWARD_SETUP
936 * Used for connection offload. Completes on the RCQ of the multi-queue
937 * RSS connection that is being offloaded. (Not currently used under
940 * There can only be one command pending per function.
943 * 0 = Success, !0 = Failure.
946 /* must be called under the spq lock */
947 static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x_softc *sc)
949 struct eth_spe *next_spe = sc->spq_prod_bd;
951 if (sc->spq_prod_bd == sc->spq_last_bd) {
952 /* wrap back to the first eth_spq */
953 sc->spq_prod_bd = sc->spq;
954 sc->spq_prod_idx = 0;
963 /* must be called under the spq lock */
964 static void bnx2x_sp_prod_update(struct bnx2x_softc *sc)
966 int func = SC_FUNC(sc);
969 * Make sure that BD data is updated before writing the producer.
970 * BD data is written to the memory, the producer is read from the
971 * memory, thus we need a full memory barrier to ensure the ordering.
975 REG_WR16(sc, (BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func)),
982 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
984 * @cmd: command to check
985 * @cmd_type: command type
987 static int bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
989 if ((cmd_type == NONE_CONNECTION_TYPE) ||
990 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
991 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
992 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
993 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
994 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
995 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) {
1003 * bnx2x_sp_post - place a single command on an SP ring
1005 * @sc: driver handle
1006 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
1007 * @cid: SW CID the command is related to
1008 * @data_hi: command private data address (high 32 bits)
1009 * @data_lo: command private data address (low 32 bits)
1010 * @cmd_type: command type (e.g. NONE, ETH)
1012 * SP data is handled as if it's always an address pair, thus data fields are
1013 * not swapped to little endian in upper functions. Instead this function swaps
1014 * data as if it's two uint32 fields.
1017 bnx2x_sp_post(struct bnx2x_softc *sc, int command, int cid, uint32_t data_hi,
1018 uint32_t data_lo, int cmd_type)
1020 struct eth_spe *spe;
1024 common = bnx2x_is_contextless_ramrod(command, cmd_type);
1027 if (!atomic_load_acq_long(&sc->eq_spq_left)) {
1028 PMD_DRV_LOG(INFO, "EQ ring is full!");
1032 if (!atomic_load_acq_long(&sc->cq_spq_left)) {
1033 PMD_DRV_LOG(INFO, "SPQ ring is full!");
1038 spe = bnx2x_sp_get_next(sc);
1040 /* CID needs port number to be encoded int it */
1041 spe->hdr.conn_and_cmd_data =
1042 htole32((command << SPE_HDR_CMD_ID_SHIFT) | HW_CID(sc, cid));
1044 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
1046 /* TBD: Check if it works for VFs */
1047 type |= ((SC_FUNC(sc) << SPE_HDR_FUNCTION_ID_SHIFT) &
1048 SPE_HDR_FUNCTION_ID);
1050 spe->hdr.type = htole16(type);
1052 spe->data.update_data_addr.hi = htole32(data_hi);
1053 spe->data.update_data_addr.lo = htole32(data_lo);
1056 * It's ok if the actual decrement is issued towards the memory
1057 * somewhere between the lock and unlock. Thus no more explict
1058 * memory barrier is needed.
1061 atomic_subtract_acq_long(&sc->eq_spq_left, 1);
1063 atomic_subtract_acq_long(&sc->cq_spq_left, 1);
1067 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x"
1068 "data (%x:%x) type(0x%x) left (CQ, EQ) (%lx,%lx)",
1070 (uint32_t) U64_HI(sc->spq_dma.paddr),
1071 (uint32_t) (U64_LO(sc->spq_dma.paddr) +
1072 (uint8_t *) sc->spq_prod_bd -
1073 (uint8_t *) sc->spq), command, common,
1074 HW_CID(sc, cid), data_hi, data_lo, type,
1075 atomic_load_acq_long(&sc->cq_spq_left),
1076 atomic_load_acq_long(&sc->eq_spq_left));
1078 bnx2x_sp_prod_update(sc);
1083 static void bnx2x_drv_pulse(struct bnx2x_softc *sc)
1085 SHMEM_WR(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb,
1086 sc->fw_drv_pulse_wr_seq);
1089 static int bnx2x_tx_queue_has_work(const struct bnx2x_fastpath *fp)
1092 struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1094 if (unlikely(!txq)) {
1095 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1099 mb(); /* status block fields can change */
1100 hw_cons = le16toh(*fp->tx_cons_sb);
1101 return hw_cons != txq->tx_pkt_head;
1104 static uint8_t bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
1106 /* expand this for multi-cos if ever supported */
1107 return bnx2x_tx_queue_has_work(fp);
1110 static int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
1112 uint16_t rx_cq_cons_sb;
1113 struct bnx2x_rx_queue *rxq;
1114 rxq = fp->sc->rx_queues[fp->index];
1115 if (unlikely(!rxq)) {
1116 PMD_RX_LOG(ERR, "ERROR: RX queue is NULL");
1120 mb(); /* status block fields can change */
1121 rx_cq_cons_sb = le16toh(*fp->rx_cq_cons_sb);
1122 if (unlikely((rx_cq_cons_sb & MAX_RCQ_ENTRIES(rxq)) ==
1123 MAX_RCQ_ENTRIES(rxq)))
1125 return rxq->rx_cq_head != rx_cq_cons_sb;
1129 bnx2x_sp_event(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
1130 union eth_rx_cqe *rr_cqe)
1132 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1133 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1134 enum ecore_queue_cmd drv_cmd = ECORE_Q_CMD_MAX;
1135 struct ecore_queue_sp_obj *q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
1138 "fp=%d cid=%d got ramrod #%d state is %x type is %d",
1139 fp->index, cid, command, sc->state,
1140 rr_cqe->ramrod_cqe.ramrod_type);
1143 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1144 PMD_DRV_LOG(DEBUG, "got UPDATE ramrod. CID %d", cid);
1145 drv_cmd = ECORE_Q_CMD_UPDATE;
1148 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1149 PMD_DRV_LOG(DEBUG, "got MULTI[%d] setup ramrod", cid);
1150 drv_cmd = ECORE_Q_CMD_SETUP;
1153 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1154 PMD_DRV_LOG(DEBUG, "got MULTI[%d] tx-only setup ramrod", cid);
1155 drv_cmd = ECORE_Q_CMD_SETUP_TX_ONLY;
1158 case (RAMROD_CMD_ID_ETH_HALT):
1159 PMD_DRV_LOG(DEBUG, "got MULTI[%d] halt ramrod", cid);
1160 drv_cmd = ECORE_Q_CMD_HALT;
1163 case (RAMROD_CMD_ID_ETH_TERMINATE):
1164 PMD_DRV_LOG(DEBUG, "got MULTI[%d] teminate ramrod", cid);
1165 drv_cmd = ECORE_Q_CMD_TERMINATE;
1168 case (RAMROD_CMD_ID_ETH_EMPTY):
1169 PMD_DRV_LOG(DEBUG, "got MULTI[%d] empty ramrod", cid);
1170 drv_cmd = ECORE_Q_CMD_EMPTY;
1175 "ERROR: unexpected MC reply (%d)"
1176 "on fp[%d]", command, fp->index);
1180 if ((drv_cmd != ECORE_Q_CMD_MAX) &&
1181 q_obj->complete_cmd(sc, q_obj, drv_cmd)) {
1183 * q_obj->complete_cmd() failure means that this was
1184 * an unexpected completion.
1186 * In this case we don't want to increase the sc->spq_left
1187 * because apparently we haven't sent this command the first
1190 // rte_panic("Unexpected SP completion");
1194 atomic_add_acq_long(&sc->cq_spq_left, 1);
1196 PMD_DRV_LOG(DEBUG, "sc->cq_spq_left 0x%lx",
1197 atomic_load_acq_long(&sc->cq_spq_left));
1200 static uint8_t bnx2x_rxeof(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
1202 struct bnx2x_rx_queue *rxq;
1203 uint16_t bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
1204 uint16_t hw_cq_cons, sw_cq_cons, sw_cq_prod;
1206 rxq = sc->rx_queues[fp->index];
1208 PMD_RX_LOG(ERR, "RX queue %d is NULL", fp->index);
1212 /* CQ "next element" is of the size of the regular element */
1213 hw_cq_cons = le16toh(*fp->rx_cq_cons_sb);
1214 if (unlikely((hw_cq_cons & USABLE_RCQ_ENTRIES_PER_PAGE) ==
1215 USABLE_RCQ_ENTRIES_PER_PAGE)) {
1219 bd_cons = rxq->rx_bd_head;
1220 bd_prod = rxq->rx_bd_tail;
1221 bd_prod_fw = bd_prod;
1222 sw_cq_cons = rxq->rx_cq_head;
1223 sw_cq_prod = rxq->rx_cq_tail;
1226 * Memory barrier necessary as speculative reads of the rx
1227 * buffer can be ahead of the index in the status block
1231 while (sw_cq_cons != hw_cq_cons) {
1232 union eth_rx_cqe *cqe;
1233 struct eth_fast_path_rx_cqe *cqe_fp;
1234 uint8_t cqe_fp_flags;
1235 enum eth_rx_cqe_type cqe_fp_type;
1237 comp_ring_cons = RCQ_ENTRY(sw_cq_cons, rxq);
1238 bd_prod = RX_BD(bd_prod, rxq);
1239 bd_cons = RX_BD(bd_cons, rxq);
1241 cqe = &rxq->cq_ring[comp_ring_cons];
1242 cqe_fp = &cqe->fast_path_cqe;
1243 cqe_fp_flags = cqe_fp->type_error_flags;
1244 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
1246 /* is this a slowpath msg? */
1247 if (CQE_TYPE_SLOW(cqe_fp_type)) {
1248 bnx2x_sp_event(sc, fp, cqe);
1252 /* is this an error packet? */
1253 if (unlikely(cqe_fp_flags &
1254 ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG)) {
1255 PMD_RX_LOG(DEBUG, "flags 0x%x rx packet %u",
1256 cqe_fp_flags, sw_cq_cons);
1260 PMD_RX_LOG(DEBUG, "Dropping fastpath called from attn poller!");
1263 bd_cons = NEXT_RX_BD(bd_cons);
1264 bd_prod = NEXT_RX_BD(bd_prod);
1265 bd_prod_fw = NEXT_RX_BD(bd_prod_fw);
1268 sw_cq_prod = NEXT_RCQ_IDX(sw_cq_prod);
1269 sw_cq_cons = NEXT_RCQ_IDX(sw_cq_cons);
1271 } /* while work to do */
1273 rxq->rx_bd_head = bd_cons;
1274 rxq->rx_bd_tail = bd_prod_fw;
1275 rxq->rx_cq_head = sw_cq_cons;
1276 rxq->rx_cq_tail = sw_cq_prod;
1278 /* Update producers */
1279 bnx2x_update_rx_prod(sc, fp, bd_prod_fw, sw_cq_prod);
1281 return sw_cq_cons != hw_cq_cons;
1285 bnx2x_free_tx_pkt(__rte_unused struct bnx2x_fastpath *fp, struct bnx2x_tx_queue *txq,
1286 uint16_t pkt_idx, uint16_t bd_idx)
1288 struct eth_tx_start_bd *tx_start_bd =
1289 &txq->tx_ring[TX_BD(bd_idx, txq)].start_bd;
1290 uint16_t nbd = rte_le_to_cpu_16(tx_start_bd->nbd);
1291 struct rte_mbuf *tx_mbuf = txq->sw_ring[TX_BD(pkt_idx, txq)];
1293 if (likely(tx_mbuf != NULL)) {
1294 rte_pktmbuf_free_seg(tx_mbuf);
1296 PMD_RX_LOG(ERR, "fp[%02d] lost mbuf %lu",
1297 fp->index, (unsigned long)TX_BD(pkt_idx, txq));
1300 txq->sw_ring[TX_BD(pkt_idx, txq)] = NULL;
1301 txq->nb_tx_avail += nbd;
1304 bd_idx = NEXT_TX_BD(bd_idx);
1309 /* processes transmit completions */
1310 uint8_t bnx2x_txeof(__rte_unused struct bnx2x_softc * sc, struct bnx2x_fastpath * fp)
1312 uint16_t bd_cons, hw_cons, sw_cons;
1313 __rte_unused uint16_t tx_bd_avail;
1315 struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1317 if (unlikely(!txq)) {
1318 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1322 bd_cons = txq->tx_bd_head;
1323 hw_cons = rte_le_to_cpu_16(*fp->tx_cons_sb);
1324 sw_cons = txq->tx_pkt_head;
1326 while (sw_cons != hw_cons) {
1327 bd_cons = bnx2x_free_tx_pkt(fp, txq, sw_cons, bd_cons);
1331 txq->tx_pkt_head = sw_cons;
1332 txq->tx_bd_head = bd_cons;
1334 tx_bd_avail = txq->nb_tx_avail;
1336 PMD_TX_LOG(DEBUG, "fp[%02d] avail=%u cons_sb=%u, "
1337 "pkt_head=%u pkt_tail=%u bd_head=%u bd_tail=%u",
1338 fp->index, tx_bd_avail, hw_cons,
1339 txq->tx_pkt_head, txq->tx_pkt_tail,
1340 txq->tx_bd_head, txq->tx_bd_tail);
1344 static void bnx2x_drain_tx_queues(struct bnx2x_softc *sc)
1346 struct bnx2x_fastpath *fp;
1349 /* wait until all TX fastpath tasks have completed */
1350 for (i = 0; i < sc->num_queues; i++) {
1355 while (bnx2x_has_tx_work(fp)) {
1356 bnx2x_txeof(sc, fp);
1360 "Timeout waiting for fp[%d] "
1361 "transmits to complete!", i);
1362 rte_panic("tx drain failure");
1376 bnx2x_del_all_macs(struct bnx2x_softc *sc, struct ecore_vlan_mac_obj *mac_obj,
1377 int mac_type, uint8_t wait_for_comp)
1379 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1382 /* wait for completion of requested */
1383 if (wait_for_comp) {
1384 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1387 /* Set the mac type of addresses we want to clear */
1388 bnx2x_set_bit(mac_type, &vlan_mac_flags);
1390 rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1392 PMD_DRV_LOG(ERR, "Failed to delete MACs (%d)", rc);
1398 bnx2x_fill_accept_flags(struct bnx2x_softc *sc, uint32_t rx_mode,
1399 unsigned long *rx_accept_flags,
1400 unsigned long *tx_accept_flags)
1402 /* Clear the flags first */
1403 *rx_accept_flags = 0;
1404 *tx_accept_flags = 0;
1407 case BNX2X_RX_MODE_NONE:
1409 * 'drop all' supersedes any accept flags that may have been
1410 * passed to the function.
1414 case BNX2X_RX_MODE_NORMAL:
1415 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1416 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, rx_accept_flags);
1417 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1419 /* internal switching mode */
1420 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1421 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, tx_accept_flags);
1422 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1426 case BNX2X_RX_MODE_ALLMULTI:
1427 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1428 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1429 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1431 /* internal switching mode */
1432 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1433 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1434 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1438 case BNX2X_RX_MODE_ALLMULTI_PROMISC:
1439 case BNX2X_RX_MODE_PROMISC:
1441 * According to deffinition of SI mode, iface in promisc mode
1442 * should receive matched and unmatched (in resolution of port)
1445 bnx2x_set_bit(ECORE_ACCEPT_UNMATCHED, rx_accept_flags);
1446 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1447 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1448 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1450 /* internal switching mode */
1451 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1452 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1455 bnx2x_set_bit(ECORE_ACCEPT_ALL_UNICAST, tx_accept_flags);
1457 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1463 PMD_RX_LOG(ERR, "Unknown rx_mode (%d)", rx_mode);
1467 /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
1468 if (rx_mode != BNX2X_RX_MODE_NONE) {
1469 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, rx_accept_flags);
1470 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, tx_accept_flags);
1477 bnx2x_set_q_rx_mode(struct bnx2x_softc *sc, uint8_t cl_id,
1478 unsigned long rx_mode_flags,
1479 unsigned long rx_accept_flags,
1480 unsigned long tx_accept_flags, unsigned long ramrod_flags)
1482 struct ecore_rx_mode_ramrod_params ramrod_param;
1485 memset(&ramrod_param, 0, sizeof(ramrod_param));
1487 /* Prepare ramrod parameters */
1488 ramrod_param.cid = 0;
1489 ramrod_param.cl_id = cl_id;
1490 ramrod_param.rx_mode_obj = &sc->rx_mode_obj;
1491 ramrod_param.func_id = SC_FUNC(sc);
1493 ramrod_param.pstate = &sc->sp_state;
1494 ramrod_param.state = ECORE_FILTER_RX_MODE_PENDING;
1496 ramrod_param.rdata = BNX2X_SP(sc, rx_mode_rdata);
1497 ramrod_param.rdata_mapping =
1498 (rte_iova_t)BNX2X_SP_MAPPING(sc, rx_mode_rdata),
1499 bnx2x_set_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
1501 ramrod_param.ramrod_flags = ramrod_flags;
1502 ramrod_param.rx_mode_flags = rx_mode_flags;
1504 ramrod_param.rx_accept_flags = rx_accept_flags;
1505 ramrod_param.tx_accept_flags = tx_accept_flags;
1507 rc = ecore_config_rx_mode(sc, &ramrod_param);
1509 PMD_RX_LOG(ERR, "Set rx_mode %d failed", sc->rx_mode);
1516 int bnx2x_set_storm_rx_mode(struct bnx2x_softc *sc)
1518 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
1519 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
1522 rc = bnx2x_fill_accept_flags(sc, sc->rx_mode, &rx_accept_flags,
1528 bnx2x_set_bit(RAMROD_RX, &ramrod_flags);
1529 bnx2x_set_bit(RAMROD_TX, &ramrod_flags);
1530 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1532 return bnx2x_set_q_rx_mode(sc, sc->fp[0].cl_id, rx_mode_flags,
1533 rx_accept_flags, tx_accept_flags,
1537 /* returns the "mcp load_code" according to global load_count array */
1538 static int bnx2x_nic_load_no_mcp(struct bnx2x_softc *sc)
1540 int path = SC_PATH(sc);
1541 int port = SC_PORT(sc);
1543 PMD_DRV_LOG(INFO, "NO MCP - load counts[%d] %d, %d, %d",
1544 path, load_count[path][0], load_count[path][1],
1545 load_count[path][2]);
1547 load_count[path][0]++;
1548 load_count[path][1 + port]++;
1549 PMD_DRV_LOG(INFO, "NO MCP - new load counts[%d] %d, %d, %d",
1550 path, load_count[path][0], load_count[path][1],
1551 load_count[path][2]);
1552 if (load_count[path][0] == 1)
1553 return FW_MSG_CODE_DRV_LOAD_COMMON;
1554 else if (load_count[path][1 + port] == 1)
1555 return FW_MSG_CODE_DRV_LOAD_PORT;
1557 return FW_MSG_CODE_DRV_LOAD_FUNCTION;
1560 /* returns the "mcp load_code" according to global load_count array */
1561 static int bnx2x_nic_unload_no_mcp(struct bnx2x_softc *sc)
1563 int port = SC_PORT(sc);
1564 int path = SC_PATH(sc);
1566 PMD_DRV_LOG(INFO, "NO MCP - load counts[%d] %d, %d, %d",
1567 path, load_count[path][0], load_count[path][1],
1568 load_count[path][2]);
1569 load_count[path][0]--;
1570 load_count[path][1 + port]--;
1571 PMD_DRV_LOG(INFO, "NO MCP - new load counts[%d] %d, %d, %d",
1572 path, load_count[path][0], load_count[path][1],
1573 load_count[path][2]);
1574 if (load_count[path][0] == 0) {
1575 return FW_MSG_CODE_DRV_UNLOAD_COMMON;
1576 } else if (load_count[path][1 + port] == 0) {
1577 return FW_MSG_CODE_DRV_UNLOAD_PORT;
1579 return FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
1583 /* request unload mode from the MCP: COMMON, PORT or FUNCTION */
1584 static uint32_t bnx2x_send_unload_req(struct bnx2x_softc *sc, int unload_mode)
1586 uint32_t reset_code = 0;
1588 /* Select the UNLOAD request mode */
1589 if (unload_mode == UNLOAD_NORMAL) {
1590 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1592 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1595 /* Send the request to the MCP */
1596 if (!BNX2X_NOMCP(sc)) {
1597 reset_code = bnx2x_fw_command(sc, reset_code, 0);
1599 reset_code = bnx2x_nic_unload_no_mcp(sc);
1605 /* send UNLOAD_DONE command to the MCP */
1606 static void bnx2x_send_unload_done(struct bnx2x_softc *sc, uint8_t keep_link)
1608 uint32_t reset_param =
1609 keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
1611 /* Report UNLOAD_DONE to MCP */
1612 if (!BNX2X_NOMCP(sc)) {
1613 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
1617 static int bnx2x_func_wait_started(struct bnx2x_softc *sc)
1621 if (!sc->port.pmf) {
1626 * (assumption: No Attention from MCP at this stage)
1627 * PMF probably in the middle of TX disable/enable transaction
1628 * 1. Sync IRS for default SB
1629 * 2. Sync SP queue - this guarantees us that attention handling started
1630 * 3. Wait, that TX disable/enable transaction completes
1632 * 1+2 guarantee that if DCBX attention was scheduled it already changed
1633 * pending bit of transaction from STARTED-->TX_STOPPED, if we already
1634 * received completion for the transaction the state is TX_STOPPED.
1635 * State will return to STARTED after completion of TX_STOPPED-->STARTED
1639 while (ecore_func_get_state(sc, &sc->func_obj) !=
1640 ECORE_F_STATE_STARTED && tout--) {
1644 if (ecore_func_get_state(sc, &sc->func_obj) != ECORE_F_STATE_STARTED) {
1646 * Failed to complete the transaction in a "good way"
1647 * Force both transactions with CLR bit.
1649 struct ecore_func_state_params func_params = { NULL };
1651 PMD_DRV_LOG(NOTICE, "Unexpected function state! "
1652 "Forcing STARTED-->TX_STOPPED-->STARTED");
1654 func_params.f_obj = &sc->func_obj;
1655 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1657 /* STARTED-->TX_STOPPED */
1658 func_params.cmd = ECORE_F_CMD_TX_STOP;
1659 ecore_func_state_change(sc, &func_params);
1661 /* TX_STOPPED-->STARTED */
1662 func_params.cmd = ECORE_F_CMD_TX_START;
1663 return ecore_func_state_change(sc, &func_params);
1669 static int bnx2x_stop_queue(struct bnx2x_softc *sc, int index)
1671 struct bnx2x_fastpath *fp = &sc->fp[index];
1672 struct ecore_queue_state_params q_params = { NULL };
1675 PMD_DRV_LOG(DEBUG, "stopping queue %d cid %d", index, fp->index);
1677 q_params.q_obj = &sc->sp_objs[fp->index].q_obj;
1678 /* We want to wait for completion in this context */
1679 bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
1681 /* Stop the primary connection: */
1683 /* ...halt the connection */
1684 q_params.cmd = ECORE_Q_CMD_HALT;
1685 rc = ecore_queue_state_change(sc, &q_params);
1690 /* ...terminate the connection */
1691 q_params.cmd = ECORE_Q_CMD_TERMINATE;
1692 memset(&q_params.params.terminate, 0,
1693 sizeof(q_params.params.terminate));
1694 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
1695 rc = ecore_queue_state_change(sc, &q_params);
1700 /* ...delete cfc entry */
1701 q_params.cmd = ECORE_Q_CMD_CFC_DEL;
1702 memset(&q_params.params.cfc_del, 0, sizeof(q_params.params.cfc_del));
1703 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
1704 return ecore_queue_state_change(sc, &q_params);
1707 /* wait for the outstanding SP commands */
1708 static uint8_t bnx2x_wait_sp_comp(struct bnx2x_softc *sc, unsigned long mask)
1711 int tout = 5000; /* wait for 5 secs tops */
1715 if (!(atomic_load_acq_long(&sc->sp_state) & mask)) {
1724 tmp = atomic_load_acq_long(&sc->sp_state);
1726 PMD_DRV_LOG(INFO, "Filtering completion timed out: "
1727 "sp_state 0x%lx, mask 0x%lx", tmp, mask);
1734 static int bnx2x_func_stop(struct bnx2x_softc *sc)
1736 struct ecore_func_state_params func_params = { NULL };
1739 /* prepare parameters for function state transitions */
1740 bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1741 func_params.f_obj = &sc->func_obj;
1742 func_params.cmd = ECORE_F_CMD_STOP;
1745 * Try to stop the function the 'good way'. If it fails (in case
1746 * of a parity error during bnx2x_chip_cleanup()) and we are
1747 * not in a debug mode, perform a state transaction in order to
1748 * enable further HW_RESET transaction.
1750 rc = ecore_func_state_change(sc, &func_params);
1752 PMD_DRV_LOG(NOTICE, "FUNC_STOP ramrod failed. "
1753 "Running a dry transaction");
1754 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1755 return ecore_func_state_change(sc, &func_params);
1761 static int bnx2x_reset_hw(struct bnx2x_softc *sc, uint32_t load_code)
1763 struct ecore_func_state_params func_params = { NULL };
1765 /* Prepare parameters for function state transitions */
1766 bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1768 func_params.f_obj = &sc->func_obj;
1769 func_params.cmd = ECORE_F_CMD_HW_RESET;
1771 func_params.params.hw_init.load_phase = load_code;
1773 return ecore_func_state_change(sc, &func_params);
1776 static void bnx2x_int_disable_sync(struct bnx2x_softc *sc, int disable_hw)
1779 /* prevent the HW from sending interrupts */
1780 bnx2x_int_disable(sc);
1785 bnx2x_chip_cleanup(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1787 int port = SC_PORT(sc);
1788 struct ecore_mcast_ramrod_params rparam = { NULL };
1789 uint32_t reset_code;
1792 bnx2x_drain_tx_queues(sc);
1794 /* give HW time to discard old tx messages */
1797 /* Clean all ETH MACs */
1798 rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_ETH_MAC,
1801 PMD_DRV_LOG(NOTICE, "Failed to delete all ETH MACs (%d)", rc);
1804 /* Clean up UC list */
1805 rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_UC_LIST_MAC,
1808 PMD_DRV_LOG(NOTICE, "Failed to delete UC MACs list (%d)", rc);
1812 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
1814 /* Set "drop all" to stop Rx */
1817 * We need to take the if_maddr_lock() here in order to prevent
1818 * a race between the completion code and this code.
1821 if (bnx2x_test_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) {
1822 bnx2x_set_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state);
1824 bnx2x_set_storm_rx_mode(sc);
1827 /* Clean up multicast configuration */
1828 rparam.mcast_obj = &sc->mcast_obj;
1829 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1832 "Failed to send DEL MCAST command (%d)", rc);
1836 * Send the UNLOAD_REQUEST to the MCP. This will return if
1837 * this function should perform FUNCTION, PORT, or COMMON HW
1840 reset_code = bnx2x_send_unload_req(sc, unload_mode);
1843 * (assumption: No Attention from MCP at this stage)
1844 * PMF probably in the middle of TX disable/enable transaction
1846 rc = bnx2x_func_wait_started(sc);
1848 PMD_DRV_LOG(NOTICE, "bnx2x_func_wait_started failed");
1852 * Close multi and leading connections
1853 * Completions for ramrods are collected in a synchronous way
1855 for (i = 0; i < sc->num_queues; i++) {
1856 if (bnx2x_stop_queue(sc, i)) {
1862 * If SP settings didn't get completed so far - something
1863 * very wrong has happen.
1865 if (!bnx2x_wait_sp_comp(sc, ~0x0UL)) {
1866 PMD_DRV_LOG(NOTICE, "Common slow path ramrods got stuck!");
1871 rc = bnx2x_func_stop(sc);
1873 PMD_DRV_LOG(NOTICE, "Function stop failed!");
1876 /* disable HW interrupts */
1877 bnx2x_int_disable_sync(sc, TRUE);
1879 /* Reset the chip */
1880 rc = bnx2x_reset_hw(sc, reset_code);
1882 PMD_DRV_LOG(NOTICE, "Hardware reset failed");
1885 /* Report UNLOAD_DONE to MCP */
1886 bnx2x_send_unload_done(sc, keep_link);
1889 static void bnx2x_disable_close_the_gate(struct bnx2x_softc *sc)
1893 PMD_DRV_LOG(DEBUG, "Disabling 'close the gates'");
1895 val = REG_RD(sc, MISC_REG_AEU_GENERAL_MASK);
1896 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
1897 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
1898 REG_WR(sc, MISC_REG_AEU_GENERAL_MASK, val);
1902 * Cleans the object that have internal lists without sending
1903 * ramrods. Should be run when interrutps are disabled.
1905 static void bnx2x_squeeze_objects(struct bnx2x_softc *sc)
1907 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1908 struct ecore_mcast_ramrod_params rparam = { NULL };
1909 struct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj;
1912 /* Cleanup MACs' object first... */
1914 /* Wait for completion of requested */
1915 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1916 /* Perform a dry cleanup */
1917 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &ramrod_flags);
1919 /* Clean ETH primary MAC */
1920 bnx2x_set_bit(ECORE_ETH_MAC, &vlan_mac_flags);
1921 rc = mac_obj->delete_all(sc, &sc->sp_objs->mac_obj, &vlan_mac_flags,
1924 PMD_DRV_LOG(NOTICE, "Failed to clean ETH MACs (%d)", rc);
1927 /* Cleanup UC list */
1929 bnx2x_set_bit(ECORE_UC_LIST_MAC, &vlan_mac_flags);
1930 rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1932 PMD_DRV_LOG(NOTICE, "Failed to clean UC list MACs (%d)", rc);
1935 /* Now clean mcast object... */
1937 rparam.mcast_obj = &sc->mcast_obj;
1938 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags);
1940 /* Add a DEL command... */
1941 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1944 "Failed to send DEL MCAST command (%d)", rc);
1947 /* now wait until all pending commands are cleared */
1949 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
1953 "Failed to clean MCAST object (%d)", rc);
1957 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
1961 /* stop the controller */
1964 bnx2x_nic_unload(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1966 uint8_t global = FALSE;
1969 PMD_DRV_LOG(DEBUG, "Starting NIC unload...");
1971 /* mark driver as unloaded in shmem2 */
1972 if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
1973 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
1974 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
1975 val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
1978 if (IS_PF(sc) && sc->recovery_state != BNX2X_RECOVERY_DONE &&
1979 (sc->state == BNX2X_STATE_CLOSED || sc->state == BNX2X_STATE_ERROR)) {
1981 * We can get here if the driver has been unloaded
1982 * during parity error recovery and is either waiting for a
1983 * leader to complete or for other functions to unload and
1984 * then ifconfig down has been issued. In this case we want to
1985 * unload and let other functions to complete a recovery
1988 sc->recovery_state = BNX2X_RECOVERY_DONE;
1990 bnx2x_release_leader_lock(sc);
1993 PMD_DRV_LOG(NOTICE, "Can't unload in closed or error state");
1998 * Nothing to do during unload if previous bnx2x_nic_load()
1999 * did not completed successfully - all resourses are released.
2001 if ((sc->state == BNX2X_STATE_CLOSED) || (sc->state == BNX2X_STATE_ERROR)) {
2005 sc->state = BNX2X_STATE_CLOSING_WAITING_HALT;
2008 sc->rx_mode = BNX2X_RX_MODE_NONE;
2009 bnx2x_set_rx_mode(sc);
2013 /* set ALWAYS_ALIVE bit in shmem */
2014 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2016 bnx2x_drv_pulse(sc);
2018 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2019 bnx2x_save_statistics(sc);
2022 /* wait till consumers catch up with producers in all queues */
2023 bnx2x_drain_tx_queues(sc);
2025 /* if VF indicate to PF this function is going down (PF will delete sp
2026 * elements and clear initializations
2029 bnx2x_vf_unload(sc);
2030 } else if (unload_mode != UNLOAD_RECOVERY) {
2031 /* if this is a normal/close unload need to clean up chip */
2032 bnx2x_chip_cleanup(sc, unload_mode, keep_link);
2034 /* Send the UNLOAD_REQUEST to the MCP */
2035 bnx2x_send_unload_req(sc, unload_mode);
2038 * Prevent transactions to host from the functions on the
2039 * engine that doesn't reset global blocks in case of global
2040 * attention once gloabl blocks are reset and gates are opened
2041 * (the engine which leader will perform the recovery
2044 if (!CHIP_IS_E1x(sc)) {
2045 bnx2x_pf_disable(sc);
2048 /* disable HW interrupts */
2049 bnx2x_int_disable_sync(sc, TRUE);
2051 /* Report UNLOAD_DONE to MCP */
2052 bnx2x_send_unload_done(sc, FALSE);
2056 * At this stage no more interrupts will arrive so we may safely clean
2057 * the queue'able objects here in case they failed to get cleaned so far.
2060 bnx2x_squeeze_objects(sc);
2063 /* There should be no more pending SP commands at this stage */
2072 bnx2x_free_fw_stats_mem(sc);
2074 sc->state = BNX2X_STATE_CLOSED;
2077 * Check if there are pending parity attentions. If there are - set
2078 * RECOVERY_IN_PROGRESS.
2080 if (IS_PF(sc) && bnx2x_chk_parity_attn(sc, &global, FALSE)) {
2081 bnx2x_set_reset_in_progress(sc);
2083 /* Set RESET_IS_GLOBAL if needed */
2085 bnx2x_set_reset_global(sc);
2090 * The last driver must disable a "close the gate" if there is no
2091 * parity attention or "process kill" pending.
2093 if (IS_PF(sc) && !bnx2x_clear_pf_load(sc) &&
2094 bnx2x_reset_is_done(sc, SC_PATH(sc))) {
2095 bnx2x_disable_close_the_gate(sc);
2098 PMD_DRV_LOG(DEBUG, "Ended NIC unload");
2104 * Encapsulte an mbuf cluster into the tx bd chain and makes the memory
2105 * visible to the controller.
2107 * If an mbuf is submitted to this routine and cannot be given to the
2108 * controller (e.g. it has too many fragments) then the function may free
2109 * the mbuf and return to the caller.
2112 * int: Number of TX BDs used for the mbuf
2114 * Note the side effect that an mbuf may be freed if it causes a problem.
2116 int bnx2x_tx_encap(struct bnx2x_tx_queue *txq, struct rte_mbuf *m0)
2118 struct eth_tx_start_bd *tx_start_bd;
2119 uint16_t bd_prod, pkt_prod;
2120 struct bnx2x_softc *sc;
2124 bd_prod = txq->tx_bd_tail;
2125 pkt_prod = txq->tx_pkt_tail;
2127 txq->sw_ring[TX_BD(pkt_prod, txq)] = m0;
2129 tx_start_bd = &txq->tx_ring[TX_BD(bd_prod, txq)].start_bd;
2132 rte_cpu_to_le_64(rte_mbuf_data_iova(m0));
2133 tx_start_bd->nbytes = rte_cpu_to_le_16(m0->data_len);
2134 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2135 tx_start_bd->general_data =
2136 (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
2138 tx_start_bd->nbd = rte_cpu_to_le_16(2);
2140 if (m0->ol_flags & PKT_TX_VLAN_PKT) {
2141 tx_start_bd->vlan_or_ethertype =
2142 rte_cpu_to_le_16(m0->vlan_tci);
2143 tx_start_bd->bd_flags.as_bitfield |=
2144 (X_ETH_OUTBAND_VLAN <<
2145 ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT);
2148 tx_start_bd->vlan_or_ethertype =
2149 rte_cpu_to_le_16(pkt_prod);
2151 struct ether_hdr *eh =
2152 rte_pktmbuf_mtod(m0, struct ether_hdr *);
2154 tx_start_bd->vlan_or_ethertype =
2155 rte_cpu_to_le_16(rte_be_to_cpu_16(eh->ether_type));
2159 bd_prod = NEXT_TX_BD(bd_prod);
2161 struct eth_tx_parse_bd_e2 *tx_parse_bd;
2162 const struct ether_hdr *eh =
2163 rte_pktmbuf_mtod(m0, struct ether_hdr *);
2164 uint8_t mac_type = UNICAST_ADDRESS;
2167 &txq->tx_ring[TX_BD(bd_prod, txq)].parse_bd_e2;
2168 if (is_multicast_ether_addr(&eh->d_addr)) {
2169 if (is_broadcast_ether_addr(&eh->d_addr))
2170 mac_type = BROADCAST_ADDRESS;
2172 mac_type = MULTICAST_ADDRESS;
2174 tx_parse_bd->parsing_data =
2175 (mac_type << ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT);
2177 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_hi,
2178 &eh->d_addr.addr_bytes[0], 2);
2179 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_mid,
2180 &eh->d_addr.addr_bytes[2], 2);
2181 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_lo,
2182 &eh->d_addr.addr_bytes[4], 2);
2183 rte_memcpy(&tx_parse_bd->data.mac_addr.src_hi,
2184 &eh->s_addr.addr_bytes[0], 2);
2185 rte_memcpy(&tx_parse_bd->data.mac_addr.src_mid,
2186 &eh->s_addr.addr_bytes[2], 2);
2187 rte_memcpy(&tx_parse_bd->data.mac_addr.src_lo,
2188 &eh->s_addr.addr_bytes[4], 2);
2190 tx_parse_bd->data.mac_addr.dst_hi =
2191 rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_hi);
2192 tx_parse_bd->data.mac_addr.dst_mid =
2193 rte_cpu_to_be_16(tx_parse_bd->data.
2195 tx_parse_bd->data.mac_addr.dst_lo =
2196 rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_lo);
2197 tx_parse_bd->data.mac_addr.src_hi =
2198 rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_hi);
2199 tx_parse_bd->data.mac_addr.src_mid =
2200 rte_cpu_to_be_16(tx_parse_bd->data.
2202 tx_parse_bd->data.mac_addr.src_lo =
2203 rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_lo);
2206 "PBD dst %x %x %x src %x %x %x p_data %x",
2207 tx_parse_bd->data.mac_addr.dst_hi,
2208 tx_parse_bd->data.mac_addr.dst_mid,
2209 tx_parse_bd->data.mac_addr.dst_lo,
2210 tx_parse_bd->data.mac_addr.src_hi,
2211 tx_parse_bd->data.mac_addr.src_mid,
2212 tx_parse_bd->data.mac_addr.src_lo,
2213 tx_parse_bd->parsing_data);
2217 "start bd: nbytes %d flags %x vlan %x",
2218 tx_start_bd->nbytes,
2219 tx_start_bd->bd_flags.as_bitfield,
2220 tx_start_bd->vlan_or_ethertype);
2222 bd_prod = NEXT_TX_BD(bd_prod);
2225 if (TX_IDX(bd_prod) < 2)
2228 txq->nb_tx_avail -= 2;
2229 txq->tx_bd_tail = bd_prod;
2230 txq->tx_pkt_tail = pkt_prod;
2235 static uint16_t bnx2x_cid_ilt_lines(struct bnx2x_softc *sc)
2237 return L2_ILT_LINES(sc);
2240 static void bnx2x_ilt_set_info(struct bnx2x_softc *sc)
2242 struct ilt_client_info *ilt_client;
2243 struct ecore_ilt *ilt = sc->ilt;
2246 PMD_INIT_FUNC_TRACE();
2248 ilt->start_line = FUNC_ILT_BASE(SC_FUNC(sc));
2251 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
2252 ilt_client->client_num = ILT_CLIENT_CDU;
2253 ilt_client->page_size = CDU_ILT_PAGE_SZ;
2254 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
2255 ilt_client->start = line;
2256 line += bnx2x_cid_ilt_lines(sc);
2258 if (CNIC_SUPPORT(sc)) {
2259 line += CNIC_ILT_LINES;
2262 ilt_client->end = (line - 1);
2265 if (QM_INIT(sc->qm_cid_count)) {
2266 ilt_client = &ilt->clients[ILT_CLIENT_QM];
2267 ilt_client->client_num = ILT_CLIENT_QM;
2268 ilt_client->page_size = QM_ILT_PAGE_SZ;
2269 ilt_client->flags = 0;
2270 ilt_client->start = line;
2272 /* 4 bytes for each cid */
2273 line += DIV_ROUND_UP(sc->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
2276 ilt_client->end = (line - 1);
2279 if (CNIC_SUPPORT(sc)) {
2281 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
2282 ilt_client->client_num = ILT_CLIENT_SRC;
2283 ilt_client->page_size = SRC_ILT_PAGE_SZ;
2284 ilt_client->flags = 0;
2285 ilt_client->start = line;
2286 line += SRC_ILT_LINES;
2287 ilt_client->end = (line - 1);
2290 ilt_client = &ilt->clients[ILT_CLIENT_TM];
2291 ilt_client->client_num = ILT_CLIENT_TM;
2292 ilt_client->page_size = TM_ILT_PAGE_SZ;
2293 ilt_client->flags = 0;
2294 ilt_client->start = line;
2295 line += TM_ILT_LINES;
2296 ilt_client->end = (line - 1);
2299 assert((line <= ILT_MAX_LINES));
2302 static void bnx2x_set_fp_rx_buf_size(struct bnx2x_softc *sc)
2306 for (i = 0; i < sc->num_queues; i++) {
2307 /* get the Rx buffer size for RX frames */
2308 sc->fp[i].rx_buf_size =
2309 (IP_HEADER_ALIGNMENT_PADDING + ETH_OVERHEAD + sc->mtu);
2313 int bnx2x_alloc_ilt_mem(struct bnx2x_softc *sc)
2316 sc->ilt = rte_malloc("", sizeof(struct ecore_ilt), RTE_CACHE_LINE_SIZE);
2318 return sc->ilt == NULL;
2321 static int bnx2x_alloc_ilt_lines_mem(struct bnx2x_softc *sc)
2323 sc->ilt->lines = rte_calloc("",
2324 sizeof(struct ilt_line), ILT_MAX_LINES,
2325 RTE_CACHE_LINE_SIZE);
2326 return sc->ilt->lines == NULL;
2329 void bnx2x_free_ilt_mem(struct bnx2x_softc *sc)
2335 static void bnx2x_free_ilt_lines_mem(struct bnx2x_softc *sc)
2337 if (sc->ilt->lines != NULL) {
2338 rte_free(sc->ilt->lines);
2339 sc->ilt->lines = NULL;
2343 static void bnx2x_free_mem(struct bnx2x_softc *sc)
2347 for (i = 0; i < L2_ILT_LINES(sc); i++) {
2348 sc->context[i].vcxt = NULL;
2349 sc->context[i].size = 0;
2352 ecore_ilt_mem_op(sc, ILT_MEMOP_FREE);
2354 bnx2x_free_ilt_lines_mem(sc);
2357 static int bnx2x_alloc_mem(struct bnx2x_softc *sc)
2362 char cdu_name[RTE_MEMZONE_NAMESIZE];
2365 * Allocate memory for CDU context:
2366 * This memory is allocated separately and not in the generic ILT
2367 * functions because CDU differs in few aspects:
2368 * 1. There can be multiple entities allocating memory for context -
2369 * regular L2, CNIC, and SRIOV drivers. Each separately controls
2370 * its own ILT lines.
2371 * 2. Since CDU page-size is not a single 4KB page (which is the case
2372 * for the other ILT clients), to be efficient we want to support
2373 * allocation of sub-page-size in the last entry.
2374 * 3. Context pointers are used by the driver to pass to FW / update
2375 * the context (for the other ILT clients the pointers are used just to
2376 * free the memory during unload).
2378 context_size = (sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(sc));
2379 for (i = 0, allocated = 0; allocated < context_size; i++) {
2380 sc->context[i].size = min(CDU_ILT_PAGE_SZ,
2381 (context_size - allocated));
2383 snprintf(cdu_name, sizeof(cdu_name), "cdu_%d", i);
2384 if (bnx2x_dma_alloc(sc, sc->context[i].size,
2385 &sc->context[i].vcxt_dma,
2386 cdu_name, BNX2X_PAGE_SIZE) != 0) {
2391 sc->context[i].vcxt =
2392 (union cdu_context *)sc->context[i].vcxt_dma.vaddr;
2394 allocated += sc->context[i].size;
2397 bnx2x_alloc_ilt_lines_mem(sc);
2399 if (ecore_ilt_mem_op(sc, ILT_MEMOP_ALLOC)) {
2400 PMD_DRV_LOG(NOTICE, "ecore_ilt_mem_op ILT_MEMOP_ALLOC failed");
2408 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc)
2410 sc->fw_stats_num = 0;
2412 sc->fw_stats_req_size = 0;
2413 sc->fw_stats_req = NULL;
2414 sc->fw_stats_req_mapping = 0;
2416 sc->fw_stats_data_size = 0;
2417 sc->fw_stats_data = NULL;
2418 sc->fw_stats_data_mapping = 0;
2421 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc)
2423 uint8_t num_queue_stats;
2424 int num_groups, vf_headroom = 0;
2426 /* number of queues for statistics is number of eth queues */
2427 num_queue_stats = BNX2X_NUM_ETH_QUEUES(sc);
2430 * Total number of FW statistics requests =
2431 * 1 for port stats + 1 for PF stats + num of queues
2433 sc->fw_stats_num = (2 + num_queue_stats);
2436 * Request is built from stats_query_header and an array of
2437 * stats_query_cmd_group each of which contains STATS_QUERY_CMD_COUNT
2438 * rules. The real number or requests is configured in the
2439 * stats_query_header.
2441 num_groups = (sc->fw_stats_num + vf_headroom) / STATS_QUERY_CMD_COUNT;
2442 if ((sc->fw_stats_num + vf_headroom) % STATS_QUERY_CMD_COUNT)
2445 sc->fw_stats_req_size =
2446 (sizeof(struct stats_query_header) +
2447 (num_groups * sizeof(struct stats_query_cmd_group)));
2450 * Data for statistics requests + stats_counter.
2451 * stats_counter holds per-STORM counters that are incremented when
2452 * STORM has finished with the current request. Memory for FCoE
2453 * offloaded statistics are counted anyway, even if they will not be sent.
2454 * VF stats are not accounted for here as the data of VF stats is stored
2455 * in memory allocated by the VF, not here.
2457 sc->fw_stats_data_size =
2458 (sizeof(struct stats_counter) +
2459 sizeof(struct per_port_stats) + sizeof(struct per_pf_stats) +
2460 /* sizeof(struct fcoe_statistics_params) + */
2461 (sizeof(struct per_queue_stats) * num_queue_stats));
2463 if (bnx2x_dma_alloc(sc, (sc->fw_stats_req_size + sc->fw_stats_data_size),
2464 &sc->fw_stats_dma, "fw_stats",
2465 RTE_CACHE_LINE_SIZE) != 0) {
2466 bnx2x_free_fw_stats_mem(sc);
2470 /* set up the shortcuts */
2472 sc->fw_stats_req = (struct bnx2x_fw_stats_req *)sc->fw_stats_dma.vaddr;
2473 sc->fw_stats_req_mapping = sc->fw_stats_dma.paddr;
2476 (struct bnx2x_fw_stats_data *)((uint8_t *) sc->fw_stats_dma.vaddr +
2477 sc->fw_stats_req_size);
2478 sc->fw_stats_data_mapping = (sc->fw_stats_dma.paddr +
2479 sc->fw_stats_req_size);
2486 * 0-7 - Engine0 load counter.
2487 * 8-15 - Engine1 load counter.
2488 * 16 - Engine0 RESET_IN_PROGRESS bit.
2489 * 17 - Engine1 RESET_IN_PROGRESS bit.
2490 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active
2491 * function on the engine
2492 * 19 - Engine1 ONE_IS_LOADED.
2493 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
2494 * leader to complete (check for both RESET_IN_PROGRESS bits and not
2495 * for just the one belonging to its engine).
2497 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
2498 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
2499 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
2500 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
2501 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
2502 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
2503 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
2504 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
2506 /* set the GLOBAL_RESET bit, should be run under rtnl lock */
2507 static void bnx2x_set_reset_global(struct bnx2x_softc *sc)
2510 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2511 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2512 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
2513 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2516 /* clear the GLOBAL_RESET bit, should be run under rtnl lock */
2517 static void bnx2x_clear_reset_global(struct bnx2x_softc *sc)
2520 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2521 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2522 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
2523 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2526 /* checks the GLOBAL_RESET bit, should be run under rtnl lock */
2527 static uint8_t bnx2x_reset_is_global(struct bnx2x_softc *sc)
2529 return REG_RD(sc, BNX2X_RECOVERY_GLOB_REG) & BNX2X_GLOBAL_RESET_BIT;
2532 /* clear RESET_IN_PROGRESS bit for the engine, should be run under rtnl lock */
2533 static void bnx2x_set_reset_done(struct bnx2x_softc *sc)
2536 uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2537 BNX2X_PATH0_RST_IN_PROG_BIT;
2539 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2541 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2544 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2546 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2549 /* set RESET_IN_PROGRESS for the engine, should be run under rtnl lock */
2550 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc)
2553 uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2554 BNX2X_PATH0_RST_IN_PROG_BIT;
2556 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2558 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2561 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2563 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2566 /* check RESET_IN_PROGRESS bit for an engine, should be run under rtnl lock */
2567 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine)
2569 uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2570 uint32_t bit = engine ? BNX2X_PATH1_RST_IN_PROG_BIT :
2571 BNX2X_PATH0_RST_IN_PROG_BIT;
2573 /* return false if bit is set */
2574 return (val & bit) ? FALSE : TRUE;
2577 /* get the load status for an engine, should be run under rtnl lock */
2578 static uint8_t bnx2x_get_load_status(struct bnx2x_softc *sc, int engine)
2580 uint32_t mask = engine ? BNX2X_PATH1_LOAD_CNT_MASK :
2581 BNX2X_PATH0_LOAD_CNT_MASK;
2582 uint32_t shift = engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2583 BNX2X_PATH0_LOAD_CNT_SHIFT;
2584 uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2586 val = ((val & mask) >> shift);
2591 /* set pf load mark */
2592 static void bnx2x_set_pf_load(struct bnx2x_softc *sc)
2596 uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2597 BNX2X_PATH0_LOAD_CNT_MASK;
2598 uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2599 BNX2X_PATH0_LOAD_CNT_SHIFT;
2601 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2603 PMD_INIT_FUNC_TRACE();
2605 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2607 /* get the current counter value */
2608 val1 = ((val & mask) >> shift);
2610 /* set bit of this PF */
2611 val1 |= (1 << SC_ABS_FUNC(sc));
2613 /* clear the old value */
2616 /* set the new one */
2617 val |= ((val1 << shift) & mask);
2619 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2621 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2624 /* clear pf load mark */
2625 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc)
2628 uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2629 BNX2X_PATH0_LOAD_CNT_MASK;
2630 uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2631 BNX2X_PATH0_LOAD_CNT_SHIFT;
2633 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2634 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2636 /* get the current counter value */
2637 val1 = (val & mask) >> shift;
2639 /* clear bit of that PF */
2640 val1 &= ~(1 << SC_ABS_FUNC(sc));
2642 /* clear the old value */
2645 /* set the new one */
2646 val |= ((val1 << shift) & mask);
2648 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2649 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2653 /* send load requrest to mcp and analyze response */
2654 static int bnx2x_nic_load_request(struct bnx2x_softc *sc, uint32_t * load_code)
2656 PMD_INIT_FUNC_TRACE();
2660 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
2661 DRV_MSG_SEQ_NUMBER_MASK);
2663 PMD_DRV_LOG(DEBUG, "initial fw_seq 0x%04x", sc->fw_seq);
2666 /* get the current FW pulse sequence */
2667 sc->fw_drv_pulse_wr_seq =
2668 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb) &
2669 DRV_PULSE_SEQ_MASK);
2671 /* set ALWAYS_ALIVE bit in shmem */
2672 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2673 bnx2x_drv_pulse(sc);
2677 (*load_code) = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
2678 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
2680 /* if the MCP fails to respond we must abort */
2681 if (!(*load_code)) {
2682 PMD_DRV_LOG(NOTICE, "MCP response failure!");
2686 /* if MCP refused then must abort */
2687 if ((*load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED) {
2688 PMD_DRV_LOG(NOTICE, "MCP refused load request");
2696 * Check whether another PF has already loaded FW to chip. In virtualized
2697 * environments a pf from anoth VM may have already initialized the device
2698 * including loading FW.
2700 static int bnx2x_nic_load_analyze_req(struct bnx2x_softc *sc, uint32_t load_code)
2702 uint32_t my_fw, loaded_fw;
2704 /* is another pf loaded on this engine? */
2705 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
2706 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
2707 /* build my FW version dword */
2708 my_fw = (BNX2X_5710_FW_MAJOR_VERSION +
2709 (BNX2X_5710_FW_MINOR_VERSION << 8) +
2710 (BNX2X_5710_FW_REVISION_VERSION << 16) +
2711 (BNX2X_5710_FW_ENGINEERING_VERSION << 24));
2713 /* read loaded FW from chip */
2714 loaded_fw = REG_RD(sc, XSEM_REG_PRAM);
2715 PMD_DRV_LOG(DEBUG, "loaded FW 0x%08x / my FW 0x%08x",
2718 /* abort nic load if version mismatch */
2719 if (my_fw != loaded_fw) {
2721 "FW 0x%08x already loaded (mine is 0x%08x)",
2730 /* mark PMF if applicable */
2731 static void bnx2x_nic_load_pmf(struct bnx2x_softc *sc, uint32_t load_code)
2733 uint32_t ncsi_oem_data_addr;
2735 PMD_INIT_FUNC_TRACE();
2737 if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
2738 (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
2739 (load_code == FW_MSG_CODE_DRV_LOAD_PORT)) {
2741 * Barrier here for ordering between the writing to sc->port.pmf here
2742 * and reading it from the periodic task.
2750 PMD_DRV_LOG(DEBUG, "pmf %d", sc->port.pmf);
2752 if (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) {
2753 if (SHMEM2_HAS(sc, ncsi_oem_data_addr)) {
2754 ncsi_oem_data_addr = SHMEM2_RD(sc, ncsi_oem_data_addr);
2755 if (ncsi_oem_data_addr) {
2757 (ncsi_oem_data_addr +
2758 offsetof(struct glob_ncsi_oem_data,
2759 driver_version)), 0);
2765 static void bnx2x_read_mf_cfg(struct bnx2x_softc *sc)
2767 int n = (CHIP_IS_MODE_4_PORT(sc) ? 2 : 1);
2771 if (BNX2X_NOMCP(sc)) {
2772 return; /* what should be the default bvalue in this case */
2776 * The formula for computing the absolute function number is...
2777 * For 2 port configuration (4 functions per port):
2778 * abs_func = 2 * vn + SC_PORT + SC_PATH
2779 * For 4 port configuration (2 functions per port):
2780 * abs_func = 4 * vn + 2 * SC_PORT + SC_PATH
2782 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
2783 abs_func = (n * (2 * vn + SC_PORT(sc)) + SC_PATH(sc));
2784 if (abs_func >= E1H_FUNC_MAX) {
2787 sc->devinfo.mf_info.mf_config[vn] =
2788 MFCFG_RD(sc, func_mf_config[abs_func].config);
2791 if (sc->devinfo.mf_info.mf_config[SC_VN(sc)] &
2792 FUNC_MF_CFG_FUNC_DISABLED) {
2793 PMD_DRV_LOG(DEBUG, "mf_cfg function disabled");
2794 sc->flags |= BNX2X_MF_FUNC_DIS;
2796 PMD_DRV_LOG(DEBUG, "mf_cfg function enabled");
2797 sc->flags &= ~BNX2X_MF_FUNC_DIS;
2801 /* acquire split MCP access lock register */
2802 static int bnx2x_acquire_alr(struct bnx2x_softc *sc)
2806 for (j = 0; j < 1000; j++) {
2808 REG_WR(sc, GRCBASE_MCP + 0x9c, val);
2809 val = REG_RD(sc, GRCBASE_MCP + 0x9c);
2810 if (val & (1L << 31))
2816 if (!(val & (1L << 31))) {
2817 PMD_DRV_LOG(NOTICE, "Cannot acquire MCP access lock register");
2824 /* release split MCP access lock register */
2825 static void bnx2x_release_alr(struct bnx2x_softc *sc)
2827 REG_WR(sc, GRCBASE_MCP + 0x9c, 0);
2830 static void bnx2x_fan_failure(struct bnx2x_softc *sc)
2832 int port = SC_PORT(sc);
2833 uint32_t ext_phy_config;
2835 /* mark the failure */
2837 SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
2839 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2840 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
2841 SHMEM_WR(sc, dev_info.port_hw_config[port].external_phy_config,
2844 /* log the failure */
2846 "Fan Failure has caused the driver to shutdown "
2847 "the card to prevent permanent damage. "
2848 "Please contact OEM Support for assistance");
2850 rte_panic("Schedule task to handle fan failure");
2853 /* this function is called upon a link interrupt */
2854 static void bnx2x_link_attn(struct bnx2x_softc *sc)
2856 uint32_t pause_enabled = 0;
2857 struct host_port_stats *pstats;
2860 /* Make sure that we are synced with the current statistics */
2861 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2863 elink_link_update(&sc->link_params, &sc->link_vars);
2865 if (sc->link_vars.link_up) {
2867 /* dropless flow control */
2868 if (sc->dropless_fc) {
2871 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
2876 (BAR_USTRORM_INTMEM +
2877 USTORM_ETH_PAUSE_ENABLED_OFFSET(SC_PORT(sc))),
2881 if (sc->link_vars.mac_type != ELINK_MAC_TYPE_EMAC) {
2882 pstats = BNX2X_SP(sc, port_stats);
2883 /* reset old mac stats */
2884 memset(&(pstats->mac_stx[0]), 0,
2885 sizeof(struct mac_stx));
2888 if (sc->state == BNX2X_STATE_OPEN) {
2889 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
2893 if (sc->link_vars.link_up && sc->link_vars.line_speed) {
2894 cmng_fns = bnx2x_get_cmng_fns_mode(sc);
2896 if (cmng_fns != CMNG_FNS_NONE) {
2897 bnx2x_cmng_fns_init(sc, FALSE, cmng_fns);
2898 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
2902 bnx2x_link_report(sc);
2905 bnx2x_link_sync_notify(sc);
2909 static void bnx2x_attn_int_asserted(struct bnx2x_softc *sc, uint32_t asserted)
2911 int port = SC_PORT(sc);
2912 uint32_t aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2913 MISC_REG_AEU_MASK_ATTN_FUNC_0;
2914 uint32_t nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2915 NIG_REG_MASK_INTERRUPT_PORT0;
2917 uint32_t nig_mask = 0;
2922 if (sc->attn_state & asserted) {
2923 PMD_DRV_LOG(ERR, "IGU ERROR attn=0x%08x", asserted);
2926 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2928 aeu_mask = REG_RD(sc, aeu_addr);
2930 aeu_mask &= ~(asserted & 0x3ff);
2932 REG_WR(sc, aeu_addr, aeu_mask);
2934 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2936 sc->attn_state |= asserted;
2938 if (asserted & ATTN_HARD_WIRED_MASK) {
2939 if (asserted & ATTN_NIG_FOR_FUNC) {
2941 /* save nig interrupt mask */
2942 nig_mask = REG_RD(sc, nig_int_mask_addr);
2944 /* If nig_mask is not set, no need to call the update function */
2946 REG_WR(sc, nig_int_mask_addr, 0);
2948 bnx2x_link_attn(sc);
2951 /* handle unicore attn? */
2954 if (asserted & ATTN_SW_TIMER_4_FUNC) {
2955 PMD_DRV_LOG(DEBUG, "ATTN_SW_TIMER_4_FUNC!");
2958 if (asserted & GPIO_2_FUNC) {
2959 PMD_DRV_LOG(DEBUG, "GPIO_2_FUNC!");
2962 if (asserted & GPIO_3_FUNC) {
2963 PMD_DRV_LOG(DEBUG, "GPIO_3_FUNC!");
2966 if (asserted & GPIO_4_FUNC) {
2967 PMD_DRV_LOG(DEBUG, "GPIO_4_FUNC!");
2971 if (asserted & ATTN_GENERAL_ATTN_1) {
2972 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_1!");
2973 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
2975 if (asserted & ATTN_GENERAL_ATTN_2) {
2976 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_2!");
2977 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
2979 if (asserted & ATTN_GENERAL_ATTN_3) {
2980 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_3!");
2981 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
2984 if (asserted & ATTN_GENERAL_ATTN_4) {
2985 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_4!");
2986 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
2988 if (asserted & ATTN_GENERAL_ATTN_5) {
2989 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_5!");
2990 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
2992 if (asserted & ATTN_GENERAL_ATTN_6) {
2993 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_6!");
2994 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
2999 if (sc->devinfo.int_block == INT_BLOCK_HC) {
3001 (HC_REG_COMMAND_REG + port * 32 +
3002 COMMAND_REG_ATTN_BITS_SET);
3004 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER * 8);
3007 PMD_DRV_LOG(DEBUG, "about to mask 0x%08x at %s addr 0x%08x",
3009 (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
3011 REG_WR(sc, reg_addr, asserted);
3013 /* now set back the mask */
3014 if (asserted & ATTN_NIG_FOR_FUNC) {
3016 * Verify that IGU ack through BAR was written before restoring
3017 * NIG mask. This loop should exit after 2-3 iterations max.
3019 if (sc->devinfo.int_block != INT_BLOCK_HC) {
3024 REG_RD(sc, IGU_REG_ATTENTION_ACK_BITS);
3025 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0)
3026 && (++cnt < MAX_IGU_ATTN_ACK_TO));
3030 "Failed to verify IGU ack on time");
3036 REG_WR(sc, nig_int_mask_addr, nig_mask);
3042 bnx2x_print_next_block(__rte_unused struct bnx2x_softc *sc, __rte_unused int idx,
3043 __rte_unused const char *blk)
3045 PMD_DRV_LOG(INFO, "%s%s", idx ? ", " : "", blk);
3049 bnx2x_check_blocks_with_parity0(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3052 uint32_t cur_bit = 0;
3055 for (i = 0; sig; i++) {
3056 cur_bit = ((uint32_t) 0x1 << i);
3057 if (sig & cur_bit) {
3059 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3061 bnx2x_print_next_block(sc, par_num++,
3064 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3066 bnx2x_print_next_block(sc, par_num++,
3069 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3071 bnx2x_print_next_block(sc, par_num++,
3074 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3076 bnx2x_print_next_block(sc, par_num++,
3079 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3081 bnx2x_print_next_block(sc, par_num++,
3084 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3086 bnx2x_print_next_block(sc, par_num++,
3089 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3091 bnx2x_print_next_block(sc, par_num++,
3105 bnx2x_check_blocks_with_parity1(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3106 uint8_t * global, uint8_t print)
3109 uint32_t cur_bit = 0;
3110 for (i = 0; sig; i++) {
3111 cur_bit = ((uint32_t) 0x1 << i);
3112 if (sig & cur_bit) {
3114 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3116 bnx2x_print_next_block(sc, par_num++,
3119 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3121 bnx2x_print_next_block(sc, par_num++,
3124 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3126 bnx2x_print_next_block(sc, par_num++,
3129 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3131 bnx2x_print_next_block(sc, par_num++,
3134 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
3136 bnx2x_print_next_block(sc, par_num++,
3139 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3141 bnx2x_print_next_block(sc, par_num++,
3144 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3146 bnx2x_print_next_block(sc, par_num++,
3149 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
3151 bnx2x_print_next_block(sc, par_num++,
3154 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3156 bnx2x_print_next_block(sc, par_num++,
3160 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3162 bnx2x_print_next_block(sc, par_num++,
3165 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3167 bnx2x_print_next_block(sc, par_num++,
3170 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
3172 bnx2x_print_next_block(sc, par_num++,
3175 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3177 bnx2x_print_next_block(sc, par_num++,
3180 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3182 bnx2x_print_next_block(sc, par_num++,
3185 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3187 bnx2x_print_next_block(sc, par_num++,
3190 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
3192 bnx2x_print_next_block(sc, par_num++,
3206 bnx2x_check_blocks_with_parity2(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3209 uint32_t cur_bit = 0;
3212 for (i = 0; sig; i++) {
3213 cur_bit = ((uint32_t) 0x1 << i);
3214 if (sig & cur_bit) {
3216 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3218 bnx2x_print_next_block(sc, par_num++,
3221 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3223 bnx2x_print_next_block(sc, par_num++,
3226 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3228 bnx2x_print_next_block(sc, par_num++,
3229 "PXPPCICLOCKCLIENT");
3231 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3233 bnx2x_print_next_block(sc, par_num++,
3236 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3238 bnx2x_print_next_block(sc, par_num++,
3241 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
3243 bnx2x_print_next_block(sc, par_num++,
3246 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3248 bnx2x_print_next_block(sc, par_num++,
3251 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3253 bnx2x_print_next_block(sc, par_num++,
3267 bnx2x_check_blocks_with_parity3(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3268 uint8_t * global, uint8_t print)
3270 uint32_t cur_bit = 0;
3273 for (i = 0; sig; i++) {
3274 cur_bit = ((uint32_t) 0x1 << i);
3275 if (sig & cur_bit) {
3277 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3279 bnx2x_print_next_block(sc, par_num++,
3283 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3285 bnx2x_print_next_block(sc, par_num++,
3289 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3291 bnx2x_print_next_block(sc, par_num++,
3295 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3297 bnx2x_print_next_block(sc, par_num++,
3312 bnx2x_check_blocks_with_parity4(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3315 uint32_t cur_bit = 0;
3318 for (i = 0; sig; i++) {
3319 cur_bit = ((uint32_t) 0x1 << i);
3320 if (sig & cur_bit) {
3322 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
3324 bnx2x_print_next_block(sc, par_num++,
3327 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
3329 bnx2x_print_next_block(sc, par_num++,
3343 bnx2x_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print,
3348 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
3349 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
3350 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
3351 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
3352 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
3354 "Parity error: HW block parity attention:"
3355 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x",
3356 (uint32_t) (sig[0] & HW_PRTY_ASSERT_SET_0),
3357 (uint32_t) (sig[1] & HW_PRTY_ASSERT_SET_1),
3358 (uint32_t) (sig[2] & HW_PRTY_ASSERT_SET_2),
3359 (uint32_t) (sig[3] & HW_PRTY_ASSERT_SET_3),
3360 (uint32_t) (sig[4] & HW_PRTY_ASSERT_SET_4));
3363 PMD_DRV_LOG(INFO, "Parity errors detected in blocks: ");
3366 bnx2x_check_blocks_with_parity0(sc, sig[0] &
3367 HW_PRTY_ASSERT_SET_0,
3370 bnx2x_check_blocks_with_parity1(sc, sig[1] &
3371 HW_PRTY_ASSERT_SET_1,
3372 par_num, global, print);
3374 bnx2x_check_blocks_with_parity2(sc, sig[2] &
3375 HW_PRTY_ASSERT_SET_2,
3378 bnx2x_check_blocks_with_parity3(sc, sig[3] &
3379 HW_PRTY_ASSERT_SET_3,
3380 par_num, global, print);
3382 bnx2x_check_blocks_with_parity4(sc, sig[4] &
3383 HW_PRTY_ASSERT_SET_4,
3387 PMD_DRV_LOG(INFO, "");
3396 bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print)
3398 struct attn_route attn = { {0} };
3399 int port = SC_PORT(sc);
3401 attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
3402 attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
3403 attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
3404 attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
3406 if (!CHIP_IS_E1x(sc))
3408 REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
3410 return bnx2x_parity_attn(sc, global, print, attn.sig);
3413 static void bnx2x_attn_int_deasserted4(struct bnx2x_softc *sc, uint32_t attn)
3417 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
3418 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
3419 PMD_DRV_LOG(INFO, "ERROR: PGLUE hw attention 0x%08x", val);
3420 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
3422 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR");
3423 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
3425 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR");
3426 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
3428 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN");
3429 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
3431 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN");
3433 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
3435 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN");
3437 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
3439 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN");
3440 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
3442 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN");
3443 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
3445 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN");
3446 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
3448 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW");
3451 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
3452 val = REG_RD(sc, ATC_REG_ATC_INT_STS_CLR);
3453 PMD_DRV_LOG(INFO, "ERROR: ATC hw attention 0x%08x", val);
3454 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
3456 "ERROR: ATC_ATC_INT_STS_REG_ADDRESS_ERROR");
3457 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
3459 "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND");
3460 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
3462 "ERROR: ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS");
3463 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
3465 "ERROR: ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT");
3466 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
3468 "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR");
3469 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
3471 "ERROR: ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU");
3474 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3475 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
3477 "ERROR: FATAL parity attention set4 0x%08x",
3479 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
3481 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
3485 static void bnx2x_e1h_disable(struct bnx2x_softc *sc)
3487 int port = SC_PORT(sc);
3489 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
3492 static void bnx2x_e1h_enable(struct bnx2x_softc *sc)
3494 int port = SC_PORT(sc);
3496 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3500 * called due to MCP event (on pmf):
3501 * reread new bandwidth configuration
3503 * notify others function about the change
3505 static void bnx2x_config_mf_bw(struct bnx2x_softc *sc)
3507 if (sc->link_vars.link_up) {
3508 bnx2x_cmng_fns_init(sc, TRUE, CMNG_FNS_MINMAX);
3509 bnx2x_link_sync_notify(sc);
3512 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
3515 static void bnx2x_set_mf_bw(struct bnx2x_softc *sc)
3517 bnx2x_config_mf_bw(sc);
3518 bnx2x_fw_command(sc, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3521 static void bnx2x_handle_eee_event(struct bnx2x_softc *sc)
3523 bnx2x_fw_command(sc, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3526 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3528 static void bnx2x_drv_info_ether_stat(struct bnx2x_softc *sc)
3530 struct eth_stats_info *ether_stat = &sc->sp->drv_info_to_mcp.ether_stat;
3532 strncpy(ether_stat->version, BNX2X_DRIVER_VERSION,
3533 ETH_STAT_INFO_VERSION_LEN);
3535 sc->sp_objs[0].mac_obj.get_n_elements(sc, &sc->sp_objs[0].mac_obj,
3536 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3537 ether_stat->mac_local + MAC_PAD,
3540 ether_stat->mtu_size = sc->mtu;
3542 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3543 ether_stat->promiscuous_mode = 0; // (flags & PROMISC) ? 1 : 0;
3545 ether_stat->txq_size = sc->tx_ring_size;
3546 ether_stat->rxq_size = sc->rx_ring_size;
3549 static void bnx2x_handle_drv_info_req(struct bnx2x_softc *sc)
3551 enum drv_info_opcode op_code;
3552 uint32_t drv_info_ctl = SHMEM2_RD(sc, drv_info_control);
3554 /* if drv_info version supported by MFW doesn't match - send NACK */
3555 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3556 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3560 op_code = ((drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3561 DRV_INFO_CONTROL_OP_CODE_SHIFT);
3563 memset(&sc->sp->drv_info_to_mcp, 0, sizeof(union drv_info_to_mcp));
3566 case ETH_STATS_OPCODE:
3567 bnx2x_drv_info_ether_stat(sc);
3569 case FCOE_STATS_OPCODE:
3570 case ISCSI_STATS_OPCODE:
3572 /* if op code isn't supported - send NACK */
3573 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3578 * If we got drv_info attn from MFW then these fields are defined in
3581 SHMEM2_WR(sc, drv_info_host_addr_lo,
3582 U64_LO(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3583 SHMEM2_WR(sc, drv_info_host_addr_hi,
3584 U64_HI(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3586 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3589 static void bnx2x_dcc_event(struct bnx2x_softc *sc, uint32_t dcc_event)
3591 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3593 * This is the only place besides the function initialization
3594 * where the sc->flags can change so it is done without any
3598 mf_info.mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_DISABLED) {
3599 PMD_DRV_LOG(DEBUG, "mf_cfg function disabled");
3600 sc->flags |= BNX2X_MF_FUNC_DIS;
3601 bnx2x_e1h_disable(sc);
3603 PMD_DRV_LOG(DEBUG, "mf_cfg function enabled");
3604 sc->flags &= ~BNX2X_MF_FUNC_DIS;
3605 bnx2x_e1h_enable(sc);
3607 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3610 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3611 bnx2x_config_mf_bw(sc);
3612 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3615 /* Report results to MCP */
3617 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_FAILURE, 0);
3619 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_OK, 0);
3622 static void bnx2x_pmf_update(struct bnx2x_softc *sc)
3624 int port = SC_PORT(sc);
3630 * We need the mb() to ensure the ordering between the writing to
3631 * sc->port.pmf here and reading it from the bnx2x_periodic_task().
3635 /* enable nig attention */
3636 val = (0xff0f | (1 << (SC_VN(sc) + 4)));
3637 if (sc->devinfo.int_block == INT_BLOCK_HC) {
3638 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, val);
3639 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, val);
3640 } else if (!CHIP_IS_E1x(sc)) {
3641 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
3642 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
3645 bnx2x_stats_handle(sc, STATS_EVENT_PMF);
3648 static int bnx2x_mc_assert(struct bnx2x_softc *sc)
3652 __rte_unused uint32_t row0, row1, row2, row3;
3656 REG_RD8(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_INDEX_OFFSET);
3658 PMD_DRV_LOG(ERR, "XSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3660 /* print the asserts */
3661 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3665 BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i));
3668 BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3672 BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3676 BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3679 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3681 "XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3682 i, row3, row2, row1, row0);
3691 REG_RD8(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_INDEX_OFFSET);
3693 PMD_DRV_LOG(ERR, "TSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3696 /* print the asserts */
3697 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3701 BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i));
3704 BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3708 BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3712 BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3715 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3717 "TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3718 i, row3, row2, row1, row0);
3727 REG_RD8(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_INDEX_OFFSET);
3729 PMD_DRV_LOG(ERR, "CSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3732 /* print the asserts */
3733 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3737 BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i));
3740 BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3744 BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3748 BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3751 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3753 "CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3754 i, row3, row2, row1, row0);
3763 REG_RD8(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_INDEX_OFFSET);
3765 PMD_DRV_LOG(ERR, "USTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3768 /* print the asserts */
3769 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3773 BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i));
3776 BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3780 BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3784 BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3787 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3789 "USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3790 i, row3, row2, row1, row0);
3800 static void bnx2x_attn_int_deasserted3(struct bnx2x_softc *sc, uint32_t attn)
3802 int func = SC_FUNC(sc);
3805 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3807 if (attn & BNX2X_PMF_LINK_ASSERT(sc)) {
3809 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
3810 bnx2x_read_mf_cfg(sc);
3811 sc->devinfo.mf_info.mf_config[SC_VN(sc)] =
3813 func_mf_config[SC_ABS_FUNC(sc)].config);
3815 SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_status);
3817 if (val & DRV_STATUS_DCC_EVENT_MASK)
3820 DRV_STATUS_DCC_EVENT_MASK));
3822 if (val & DRV_STATUS_SET_MF_BW)
3823 bnx2x_set_mf_bw(sc);
3825 if (val & DRV_STATUS_DRV_INFO_REQ)
3826 bnx2x_handle_drv_info_req(sc);
3828 if ((sc->port.pmf == 0) && (val & DRV_STATUS_PMF))
3829 bnx2x_pmf_update(sc);
3831 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
3832 bnx2x_handle_eee_event(sc);
3834 if (sc->link_vars.periodic_flags &
3835 ELINK_PERIODIC_FLAGS_LINK_EVENT) {
3836 /* sync with link */
3837 sc->link_vars.periodic_flags &=
3838 ~ELINK_PERIODIC_FLAGS_LINK_EVENT;
3840 bnx2x_link_sync_notify(sc);
3842 bnx2x_link_report(sc);
3846 * Always call it here: bnx2x_link_report() will
3847 * prevent the link indication duplication.
3849 bnx2x_link_status_update(sc);
3851 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3853 PMD_DRV_LOG(ERR, "MC assert!");
3854 bnx2x_mc_assert(sc);
3855 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3856 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3857 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3858 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3859 rte_panic("MC assert!");
3861 } else if (attn & BNX2X_MCP_ASSERT) {
3863 PMD_DRV_LOG(ERR, "MCP assert!");
3864 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3868 "Unknown HW assert! (attn 0x%08x)", attn);
3872 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3873 PMD_DRV_LOG(ERR, "LATCHED attention 0x%08x (masked)", attn);
3874 if (attn & BNX2X_GRC_TIMEOUT) {
3875 val = REG_RD(sc, MISC_REG_GRC_TIMEOUT_ATTN);
3876 PMD_DRV_LOG(ERR, "GRC time-out 0x%08x", val);
3878 if (attn & BNX2X_GRC_RSV) {
3879 val = REG_RD(sc, MISC_REG_GRC_RSV_ATTN);
3880 PMD_DRV_LOG(ERR, "GRC reserved 0x%08x", val);
3882 REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3886 static void bnx2x_attn_int_deasserted2(struct bnx2x_softc *sc, uint32_t attn)
3888 int port = SC_PORT(sc);
3890 uint32_t val0, mask0, val1, mask1;
3893 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3894 val = REG_RD(sc, CFC_REG_CFC_INT_STS_CLR);
3895 PMD_DRV_LOG(ERR, "CFC hw attention 0x%08x", val);
3896 /* CFC error attention */
3898 PMD_DRV_LOG(ERR, "FATAL error from CFC");
3902 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3903 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_0);
3904 PMD_DRV_LOG(ERR, "PXP hw attention-0 0x%08x", val);
3905 /* RQ_USDMDP_FIFO_OVERFLOW */
3906 if (val & 0x18000) {
3907 PMD_DRV_LOG(ERR, "FATAL error from PXP");
3910 if (!CHIP_IS_E1x(sc)) {
3911 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_1);
3912 PMD_DRV_LOG(ERR, "PXP hw attention-1 0x%08x", val);
3915 #define PXP2_EOP_ERROR_BIT PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR
3916 #define AEU_PXP2_HW_INT_BIT AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT
3918 if (attn & AEU_PXP2_HW_INT_BIT) {
3919 /* CQ47854 workaround do not panic on
3920 * PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3922 if (!CHIP_IS_E1x(sc)) {
3923 mask0 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_0);
3924 val1 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_1);
3925 mask1 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_1);
3926 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_0);
3928 * If the only PXP2_EOP_ERROR_BIT is set in
3929 * STS0 and STS1 - clear it
3931 * probably we lose additional attentions between
3932 * STS0 and STS_CLR0, in this case user will not
3933 * be notified about them
3935 if (val0 & mask0 & PXP2_EOP_ERROR_BIT &&
3937 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
3939 /* print the register, since no one can restore it */
3941 "PXP2_REG_PXP2_INT_STS_CLR_0 0x%08x", val0);
3944 * if PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3947 if (val0 & PXP2_EOP_ERROR_BIT) {
3948 PMD_DRV_LOG(ERR, "PXP2_WR_PGLUE_EOP_ERROR");
3951 * if only PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR is
3952 * set then clear attention from PXP2 block without panic
3954 if (((val0 & mask0) == PXP2_EOP_ERROR_BIT) &&
3955 ((val1 & mask1) == 0))
3956 attn &= ~AEU_PXP2_HW_INT_BIT;
3961 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3962 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3963 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3965 val = REG_RD(sc, reg_offset);
3966 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3967 REG_WR(sc, reg_offset, val);
3970 "FATAL HW block attention set2 0x%x",
3971 (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_2));
3972 rte_panic("HW block attention set2");
3976 static void bnx2x_attn_int_deasserted1(struct bnx2x_softc *sc, uint32_t attn)
3978 int port = SC_PORT(sc);
3982 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3983 val = REG_RD(sc, DORQ_REG_DORQ_INT_STS_CLR);
3984 PMD_DRV_LOG(ERR, "DB hw attention 0x%08x", val);
3985 /* DORQ discard attention */
3987 PMD_DRV_LOG(ERR, "FATAL error from DORQ");
3991 if (attn & HW_INTERRUT_ASSERT_SET_1) {
3992 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3993 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3995 val = REG_RD(sc, reg_offset);
3996 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3997 REG_WR(sc, reg_offset, val);
4000 "FATAL HW block attention set1 0x%08x",
4001 (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_1));
4002 rte_panic("HW block attention set1");
4006 static void bnx2x_attn_int_deasserted0(struct bnx2x_softc *sc, uint32_t attn)
4008 int port = SC_PORT(sc);
4012 reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4013 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
4015 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4016 val = REG_RD(sc, reg_offset);
4017 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4018 REG_WR(sc, reg_offset, val);
4020 PMD_DRV_LOG(WARNING, "SPIO5 hw attention");
4022 /* Fan failure attention */
4023 elink_hw_reset_phy(&sc->link_params);
4024 bnx2x_fan_failure(sc);
4027 if ((attn & sc->link_vars.aeu_int_mask) && sc->port.pmf) {
4028 elink_handle_module_detect_int(&sc->link_params);
4031 if (attn & HW_INTERRUT_ASSERT_SET_0) {
4032 val = REG_RD(sc, reg_offset);
4033 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4034 REG_WR(sc, reg_offset, val);
4036 rte_panic("FATAL HW block attention set0 0x%lx",
4037 (attn & HW_INTERRUT_ASSERT_SET_0));
4041 static void bnx2x_attn_int_deasserted(struct bnx2x_softc *sc, uint32_t deasserted)
4043 struct attn_route attn;
4044 struct attn_route *group_mask;
4045 int port = SC_PORT(sc);
4050 uint8_t global = FALSE;
4053 * Need to take HW lock because MCP or other port might also
4054 * try to handle this event.
4056 bnx2x_acquire_alr(sc);
4058 if (bnx2x_chk_parity_attn(sc, &global, TRUE)) {
4059 sc->recovery_state = BNX2X_RECOVERY_INIT;
4061 /* disable HW interrupts */
4062 bnx2x_int_disable(sc);
4063 bnx2x_release_alr(sc);
4067 attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
4068 attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
4069 attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
4070 attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
4071 if (!CHIP_IS_E1x(sc)) {
4073 REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
4078 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4079 if (deasserted & (1 << index)) {
4080 group_mask = &sc->attn_group[index];
4082 bnx2x_attn_int_deasserted4(sc,
4084 sig[4] & group_mask->sig[4]);
4085 bnx2x_attn_int_deasserted3(sc,
4087 sig[3] & group_mask->sig[3]);
4088 bnx2x_attn_int_deasserted1(sc,
4090 sig[1] & group_mask->sig[1]);
4091 bnx2x_attn_int_deasserted2(sc,
4093 sig[2] & group_mask->sig[2]);
4094 bnx2x_attn_int_deasserted0(sc,
4096 sig[0] & group_mask->sig[0]);
4100 bnx2x_release_alr(sc);
4102 if (sc->devinfo.int_block == INT_BLOCK_HC) {
4103 reg_addr = (HC_REG_COMMAND_REG + port * 32 +
4104 COMMAND_REG_ATTN_BITS_CLR);
4106 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER * 8);
4111 "about to mask 0x%08x at %s addr 0x%08x", val,
4112 (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
4114 REG_WR(sc, reg_addr, val);
4116 if (~sc->attn_state & deasserted) {
4117 PMD_DRV_LOG(ERR, "IGU error");
4120 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4121 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4123 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4125 aeu_mask = REG_RD(sc, reg_addr);
4127 aeu_mask |= (deasserted & 0x3ff);
4129 REG_WR(sc, reg_addr, aeu_mask);
4130 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4132 sc->attn_state &= ~deasserted;
4135 static void bnx2x_attn_int(struct bnx2x_softc *sc)
4137 /* read local copy of bits */
4138 uint32_t attn_bits = le32toh(sc->def_sb->atten_status_block.attn_bits);
4140 le32toh(sc->def_sb->atten_status_block.attn_bits_ack);
4141 uint32_t attn_state = sc->attn_state;
4143 /* look for changed bits */
4144 uint32_t asserted = attn_bits & ~attn_ack & ~attn_state;
4145 uint32_t deasserted = ~attn_bits & attn_ack & attn_state;
4148 "attn_bits 0x%08x attn_ack 0x%08x asserted 0x%08x deasserted 0x%08x",
4149 attn_bits, attn_ack, asserted, deasserted);
4151 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) {
4152 PMD_DRV_LOG(ERR, "BAD attention state");
4155 /* handle bits that were raised */
4157 bnx2x_attn_int_asserted(sc, asserted);
4161 bnx2x_attn_int_deasserted(sc, deasserted);
4165 static uint16_t bnx2x_update_dsb_idx(struct bnx2x_softc *sc)
4167 struct host_sp_status_block *def_sb = sc->def_sb;
4170 mb(); /* status block is written to by the chip */
4172 if (sc->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
4173 sc->def_att_idx = def_sb->atten_status_block.attn_bits_index;
4174 rc |= BNX2X_DEF_SB_ATT_IDX;
4177 if (sc->def_idx != def_sb->sp_sb.running_index) {
4178 sc->def_idx = def_sb->sp_sb.running_index;
4179 rc |= BNX2X_DEF_SB_IDX;
4187 static struct ecore_queue_sp_obj *bnx2x_cid_to_q_obj(struct bnx2x_softc *sc,
4190 return &sc->sp_objs[CID_TO_FP(cid, sc)].q_obj;
4193 static void bnx2x_handle_mcast_eqe(struct bnx2x_softc *sc)
4195 struct ecore_mcast_ramrod_params rparam;
4198 memset(&rparam, 0, sizeof(rparam));
4200 rparam.mcast_obj = &sc->mcast_obj;
4202 /* clear pending state for the last command */
4203 sc->mcast_obj.raw.clear_pending(&sc->mcast_obj.raw);
4205 /* if there are pending mcast commands - send them */
4206 if (sc->mcast_obj.check_pending(&sc->mcast_obj)) {
4207 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
4210 "Failed to send pending mcast commands (%d)",
4217 bnx2x_handle_classification_eqe(struct bnx2x_softc *sc, union event_ring_elem *elem)
4219 unsigned long ramrod_flags = 0;
4221 uint32_t cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4222 struct ecore_vlan_mac_obj *vlan_mac_obj;
4224 /* always push next commands out, don't wait here */
4225 bnx2x_set_bit(RAMROD_CONT, &ramrod_flags);
4227 switch (le32toh(elem->message.data.eth_event.echo) >> BNX2X_SWCID_SHIFT) {
4228 case ECORE_FILTER_MAC_PENDING:
4229 PMD_DRV_LOG(DEBUG, "Got SETUP_MAC completions");
4230 vlan_mac_obj = &sc->sp_objs[cid].mac_obj;
4233 case ECORE_FILTER_MCAST_PENDING:
4234 PMD_DRV_LOG(DEBUG, "Got SETUP_MCAST completions");
4235 bnx2x_handle_mcast_eqe(sc);
4239 PMD_DRV_LOG(NOTICE, "Unsupported classification command: %d",
4240 elem->message.data.eth_event.echo);
4244 rc = vlan_mac_obj->complete(sc, vlan_mac_obj, elem, &ramrod_flags);
4247 PMD_DRV_LOG(NOTICE, "Failed to schedule new commands (%d)", rc);
4248 } else if (rc > 0) {
4249 PMD_DRV_LOG(DEBUG, "Scheduled next pending commands...");
4253 static void bnx2x_handle_rx_mode_eqe(struct bnx2x_softc *sc)
4255 bnx2x_clear_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
4257 /* send rx_mode command again if was requested */
4258 if (bnx2x_test_and_clear_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state)) {
4259 bnx2x_set_storm_rx_mode(sc);
4263 static void bnx2x_update_eq_prod(struct bnx2x_softc *sc, uint16_t prod)
4265 storm_memset_eq_prod(sc, prod, SC_FUNC(sc));
4266 wmb(); /* keep prod updates ordered */
4269 static void bnx2x_eq_int(struct bnx2x_softc *sc)
4271 uint16_t hw_cons, sw_cons, sw_prod;
4272 union event_ring_elem *elem;
4277 struct ecore_queue_sp_obj *q_obj;
4278 struct ecore_func_sp_obj *f_obj = &sc->func_obj;
4279 struct ecore_raw_obj *rss_raw = &sc->rss_conf_obj.raw;
4281 hw_cons = le16toh(*sc->eq_cons_sb);
4284 * The hw_cons range is 1-255, 257 - the sw_cons range is 0-254, 256.
4285 * when we get to the next-page we need to adjust so the loop
4286 * condition below will be met. The next element is the size of a
4287 * regular element and hence incrementing by 1
4289 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) {
4294 * This function may never run in parallel with itself for a
4295 * specific sc and no need for a read memory barrier here.
4297 sw_cons = sc->eq_cons;
4298 sw_prod = sc->eq_prod;
4302 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4304 elem = &sc->eq[EQ_DESC(sw_cons)];
4306 /* elem CID originates from FW, actually LE */
4307 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4308 opcode = elem->message.opcode;
4310 /* handle eq element */
4312 case EVENT_RING_OPCODE_STAT_QUERY:
4313 PMD_DEBUG_PERIODIC_LOG(DEBUG, "got statistics completion event %d",
4315 /* nothing to do with stats comp */
4318 case EVENT_RING_OPCODE_CFC_DEL:
4319 /* handle according to cid range */
4320 /* we may want to verify here that the sc state is HALTING */
4321 PMD_DRV_LOG(DEBUG, "got delete ramrod for MULTI[%d]",
4323 q_obj = bnx2x_cid_to_q_obj(sc, cid);
4324 if (q_obj->complete_cmd(sc, q_obj, ECORE_Q_CMD_CFC_DEL)) {
4329 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4330 PMD_DRV_LOG(DEBUG, "got STOP TRAFFIC");
4331 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_STOP)) {
4336 case EVENT_RING_OPCODE_START_TRAFFIC:
4337 PMD_DRV_LOG(DEBUG, "got START TRAFFIC");
4338 if (f_obj->complete_cmd
4339 (sc, f_obj, ECORE_F_CMD_TX_START)) {
4344 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
4345 echo = elem->message.data.function_update_event.echo;
4346 if (echo == SWITCH_UPDATE) {
4348 "got FUNC_SWITCH_UPDATE ramrod");
4349 if (f_obj->complete_cmd(sc, f_obj,
4350 ECORE_F_CMD_SWITCH_UPDATE))
4356 "AFEX: ramrod completed FUNCTION_UPDATE");
4357 f_obj->complete_cmd(sc, f_obj,
4358 ECORE_F_CMD_AFEX_UPDATE);
4362 case EVENT_RING_OPCODE_FORWARD_SETUP:
4363 q_obj = &bnx2x_fwd_sp_obj(sc, q_obj);
4364 if (q_obj->complete_cmd(sc, q_obj,
4365 ECORE_Q_CMD_SETUP_TX_ONLY)) {
4370 case EVENT_RING_OPCODE_FUNCTION_START:
4371 PMD_DRV_LOG(DEBUG, "got FUNC_START ramrod");
4372 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_START)) {
4377 case EVENT_RING_OPCODE_FUNCTION_STOP:
4378 PMD_DRV_LOG(DEBUG, "got FUNC_STOP ramrod");
4379 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_STOP)) {
4385 switch (opcode | sc->state) {
4386 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPEN):
4387 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPENING_WAITING_PORT):
4389 elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4390 PMD_DRV_LOG(DEBUG, "got RSS_UPDATE ramrod. CID %d",
4392 rss_raw->clear_pending(rss_raw);
4395 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4396 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4397 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_CLOSING_WAITING_HALT):
4398 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_OPEN):
4399 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_DIAG):
4400 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4402 "got (un)set mac ramrod");
4403 bnx2x_handle_classification_eqe(sc, elem);
4406 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_OPEN):
4407 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_DIAG):
4408 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4410 "got mcast ramrod");
4411 bnx2x_handle_mcast_eqe(sc);
4414 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_OPEN):
4415 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_DIAG):
4416 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4418 "got rx_mode ramrod");
4419 bnx2x_handle_rx_mode_eqe(sc);
4423 /* unknown event log error and continue */
4424 PMD_DRV_LOG(INFO, "Unknown EQ event %d, sc->state 0x%x",
4425 elem->message.opcode, sc->state);
4433 atomic_add_acq_long(&sc->eq_spq_left, spqe_cnt);
4435 sc->eq_cons = sw_cons;
4436 sc->eq_prod = sw_prod;
4438 /* make sure that above mem writes were issued towards the memory */
4441 /* update producer */
4442 bnx2x_update_eq_prod(sc, sc->eq_prod);
4445 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc)
4450 /* what work needs to be performed? */
4451 status = bnx2x_update_dsb_idx(sc);
4454 if (status & BNX2X_DEF_SB_ATT_IDX) {
4455 PMD_DRV_LOG(DEBUG, "---> ATTN INTR <---");
4457 status &= ~BNX2X_DEF_SB_ATT_IDX;
4461 /* SP events: STAT_QUERY and others */
4462 if (status & BNX2X_DEF_SB_IDX) {
4463 /* handle EQ completions */
4464 PMD_DEBUG_PERIODIC_LOG(DEBUG, "---> EQ INTR <---");
4466 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
4467 le16toh(sc->def_idx), IGU_INT_NOP, 1);
4468 status &= ~BNX2X_DEF_SB_IDX;
4471 /* if status is non zero then something went wrong */
4472 if (unlikely(status)) {
4474 "Got an unknown SP interrupt! (0x%04x)", status);
4477 /* ack status block only if something was actually handled */
4478 bnx2x_ack_sb(sc, sc->igu_dsb_id, ATTENTION_ID,
4479 le16toh(sc->def_att_idx), IGU_INT_ENABLE, 1);
4484 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp, int scan_fp)
4486 struct bnx2x_softc *sc = fp->sc;
4487 uint8_t more_rx = FALSE;
4489 PMD_DRV_LOG(DEBUG, "---> FP TASK QUEUE (%d) <--", fp->index);
4491 /* update the fastpath index */
4492 bnx2x_update_fp_sb_idx(fp);
4495 if (bnx2x_has_rx_work(fp)) {
4496 more_rx = bnx2x_rxeof(sc, fp);
4500 /* still more work to do */
4501 bnx2x_handle_fp_tq(fp, scan_fp);
4506 bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
4507 le16toh(fp->fp_hc_idx), IGU_INT_ENABLE, 1);
4511 * Legacy interrupt entry point.
4513 * Verifies that the controller generated the interrupt and
4514 * then calls a separate routine to handle the various
4515 * interrupt causes: link, RX, and TX.
4517 int bnx2x_intr_legacy(struct bnx2x_softc *sc, int scan_fp)
4519 struct bnx2x_fastpath *fp;
4520 uint32_t status, mask;
4524 * 0 for ustorm, 1 for cstorm
4525 * the bits returned from ack_int() are 0-15
4526 * bit 0 = attention status block
4527 * bit 1 = fast path status block
4528 * a mask of 0x2 or more = tx/rx event
4529 * a mask of 1 = slow path event
4532 status = bnx2x_ack_int(sc);
4534 /* the interrupt is not for us */
4535 if (unlikely(status == 0)) {
4539 PMD_DEBUG_PERIODIC_LOG(DEBUG, "Interrupt status 0x%04x", status);
4540 //bnx2x_dump_status_block(sc);
4542 FOR_EACH_ETH_QUEUE(sc, i) {
4544 mask = (0x2 << (fp->index + CNIC_SUPPORT(sc)));
4545 if (status & mask) {
4546 bnx2x_handle_fp_tq(fp, scan_fp);
4551 if (unlikely(status & 0x1)) {
4552 rc = bnx2x_handle_sp_tq(sc);
4556 if (unlikely(status)) {
4557 PMD_DRV_LOG(WARNING,
4558 "Unexpected fastpath status (0x%08x)!", status);
4564 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc);
4565 static int bnx2x_init_hw_common(struct bnx2x_softc *sc);
4566 static int bnx2x_init_hw_port(struct bnx2x_softc *sc);
4567 static int bnx2x_init_hw_func(struct bnx2x_softc *sc);
4568 static void bnx2x_reset_common(struct bnx2x_softc *sc);
4569 static void bnx2x_reset_port(struct bnx2x_softc *sc);
4570 static void bnx2x_reset_func(struct bnx2x_softc *sc);
4571 static int bnx2x_init_firmware(struct bnx2x_softc *sc);
4572 static void bnx2x_release_firmware(struct bnx2x_softc *sc);
4575 ecore_func_sp_drv_ops bnx2x_func_sp_drv = {
4576 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
4577 .init_hw_cmn = bnx2x_init_hw_common,
4578 .init_hw_port = bnx2x_init_hw_port,
4579 .init_hw_func = bnx2x_init_hw_func,
4581 .reset_hw_cmn = bnx2x_reset_common,
4582 .reset_hw_port = bnx2x_reset_port,
4583 .reset_hw_func = bnx2x_reset_func,
4585 .init_fw = bnx2x_init_firmware,
4586 .release_fw = bnx2x_release_firmware,
4589 static void bnx2x_init_func_obj(struct bnx2x_softc *sc)
4593 PMD_INIT_FUNC_TRACE();
4595 ecore_init_func_obj(sc,
4597 BNX2X_SP(sc, func_rdata),
4598 (rte_iova_t)BNX2X_SP_MAPPING(sc, func_rdata),
4599 BNX2X_SP(sc, func_afex_rdata),
4600 (rte_iova_t)BNX2X_SP_MAPPING(sc, func_afex_rdata),
4601 &bnx2x_func_sp_drv);
4604 static int bnx2x_init_hw(struct bnx2x_softc *sc, uint32_t load_code)
4606 struct ecore_func_state_params func_params = { NULL };
4609 PMD_INIT_FUNC_TRACE();
4611 /* prepare the parameters for function state transitions */
4612 bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
4614 func_params.f_obj = &sc->func_obj;
4615 func_params.cmd = ECORE_F_CMD_HW_INIT;
4617 func_params.params.hw_init.load_phase = load_code;
4620 * Via a plethora of function pointers, we will eventually reach
4621 * bnx2x_init_hw_common(), bnx2x_init_hw_port(), or bnx2x_init_hw_func().
4623 rc = ecore_func_state_change(sc, &func_params);
4629 bnx2x_fill(struct bnx2x_softc *sc, uint32_t addr, int fill, uint32_t len)
4633 if (!(len % 4) && !(addr % 4)) {
4634 for (i = 0; i < len; i += 4) {
4635 REG_WR(sc, (addr + i), fill);
4638 for (i = 0; i < len; i++) {
4639 REG_WR8(sc, (addr + i), fill);
4644 /* writes FP SP data to FW - data_size in dwords */
4646 bnx2x_wr_fp_sb_data(struct bnx2x_softc *sc, int fw_sb_id, uint32_t * sb_data_p,
4651 for (index = 0; index < data_size; index++) {
4653 (BAR_CSTRORM_INTMEM +
4654 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
4655 (sizeof(uint32_t) * index)), *(sb_data_p + index));
4659 static void bnx2x_zero_fp_sb(struct bnx2x_softc *sc, int fw_sb_id)
4661 struct hc_status_block_data_e2 sb_data_e2;
4662 struct hc_status_block_data_e1x sb_data_e1x;
4663 uint32_t *sb_data_p;
4664 uint32_t data_size = 0;
4666 if (!CHIP_IS_E1x(sc)) {
4667 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4668 sb_data_e2.common.state = SB_DISABLED;
4669 sb_data_e2.common.p_func.vf_valid = FALSE;
4670 sb_data_p = (uint32_t *) & sb_data_e2;
4671 data_size = (sizeof(struct hc_status_block_data_e2) /
4674 memset(&sb_data_e1x, 0,
4675 sizeof(struct hc_status_block_data_e1x));
4676 sb_data_e1x.common.state = SB_DISABLED;
4677 sb_data_e1x.common.p_func.vf_valid = FALSE;
4678 sb_data_p = (uint32_t *) & sb_data_e1x;
4679 data_size = (sizeof(struct hc_status_block_data_e1x) /
4683 bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4686 (BAR_CSTRORM_INTMEM + CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id)), 0,
4687 CSTORM_STATUS_BLOCK_SIZE);
4688 bnx2x_fill(sc, (BAR_CSTRORM_INTMEM + CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id)),
4689 0, CSTORM_SYNC_BLOCK_SIZE);
4693 bnx2x_wr_sp_sb_data(struct bnx2x_softc *sc,
4694 struct hc_sp_status_block_data *sp_sb_data)
4699 i < (sizeof(struct hc_sp_status_block_data) / sizeof(uint32_t));
4702 (BAR_CSTRORM_INTMEM +
4703 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(SC_FUNC(sc)) +
4704 (i * sizeof(uint32_t))),
4705 *((uint32_t *) sp_sb_data + i));
4709 static void bnx2x_zero_sp_sb(struct bnx2x_softc *sc)
4711 struct hc_sp_status_block_data sp_sb_data;
4713 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4715 sp_sb_data.state = SB_DISABLED;
4716 sp_sb_data.p_func.vf_valid = FALSE;
4718 bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
4721 (BAR_CSTRORM_INTMEM +
4722 CSTORM_SP_STATUS_BLOCK_OFFSET(SC_FUNC(sc))),
4723 0, CSTORM_SP_STATUS_BLOCK_SIZE);
4725 (BAR_CSTRORM_INTMEM +
4726 CSTORM_SP_SYNC_BLOCK_OFFSET(SC_FUNC(sc))),
4727 0, CSTORM_SP_SYNC_BLOCK_SIZE);
4731 bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, int igu_sb_id,
4734 hc_sm->igu_sb_id = igu_sb_id;
4735 hc_sm->igu_seg_id = igu_seg_id;
4736 hc_sm->timer_value = 0xFF;
4737 hc_sm->time_to_expire = 0xFFFFFFFF;
4740 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
4742 /* zero out state machine indices */
4745 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4748 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4749 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
4750 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
4751 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
4756 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
4757 (SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4760 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
4761 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4762 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
4763 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4764 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
4765 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4766 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
4767 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4771 bnx2x_init_sb(struct bnx2x_softc *sc, rte_iova_t busaddr, int vfid,
4772 uint8_t vf_valid, int fw_sb_id, int igu_sb_id)
4774 struct hc_status_block_data_e2 sb_data_e2;
4775 struct hc_status_block_data_e1x sb_data_e1x;
4776 struct hc_status_block_sm *hc_sm_p;
4777 uint32_t *sb_data_p;
4781 if (CHIP_INT_MODE_IS_BC(sc)) {
4782 igu_seg_id = HC_SEG_ACCESS_NORM;
4784 igu_seg_id = IGU_SEG_ACCESS_NORM;
4787 bnx2x_zero_fp_sb(sc, fw_sb_id);
4789 if (!CHIP_IS_E1x(sc)) {
4790 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4791 sb_data_e2.common.state = SB_ENABLED;
4792 sb_data_e2.common.p_func.pf_id = SC_FUNC(sc);
4793 sb_data_e2.common.p_func.vf_id = vfid;
4794 sb_data_e2.common.p_func.vf_valid = vf_valid;
4795 sb_data_e2.common.p_func.vnic_id = SC_VN(sc);
4796 sb_data_e2.common.same_igu_sb_1b = TRUE;
4797 sb_data_e2.common.host_sb_addr.hi = U64_HI(busaddr);
4798 sb_data_e2.common.host_sb_addr.lo = U64_LO(busaddr);
4799 hc_sm_p = sb_data_e2.common.state_machine;
4800 sb_data_p = (uint32_t *) & sb_data_e2;
4801 data_size = (sizeof(struct hc_status_block_data_e2) /
4803 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
4805 memset(&sb_data_e1x, 0,
4806 sizeof(struct hc_status_block_data_e1x));
4807 sb_data_e1x.common.state = SB_ENABLED;
4808 sb_data_e1x.common.p_func.pf_id = SC_FUNC(sc);
4809 sb_data_e1x.common.p_func.vf_id = 0xff;
4810 sb_data_e1x.common.p_func.vf_valid = FALSE;
4811 sb_data_e1x.common.p_func.vnic_id = SC_VN(sc);
4812 sb_data_e1x.common.same_igu_sb_1b = TRUE;
4813 sb_data_e1x.common.host_sb_addr.hi = U64_HI(busaddr);
4814 sb_data_e1x.common.host_sb_addr.lo = U64_LO(busaddr);
4815 hc_sm_p = sb_data_e1x.common.state_machine;
4816 sb_data_p = (uint32_t *) & sb_data_e1x;
4817 data_size = (sizeof(struct hc_status_block_data_e1x) /
4819 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
4822 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], igu_sb_id, igu_seg_id);
4823 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], igu_sb_id, igu_seg_id);
4825 /* write indices to HW - PCI guarantees endianity of regpairs */
4826 bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4829 static uint8_t bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp)
4831 if (CHIP_IS_E1x(fp->sc)) {
4832 return fp->cl_id + SC_PORT(fp->sc) * ETH_MAX_RX_CLIENTS_E1H;
4839 bnx2x_rx_ustorm_prods_offset(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
4841 uint32_t offset = BAR_USTRORM_INTMEM;
4844 return PXP_VF_ADDR_USDM_QUEUES_START +
4845 (sc->acquire_resp.resc.hw_qid[fp->index] *
4846 sizeof(struct ustorm_queue_zone_data));
4847 } else if (!CHIP_IS_E1x(sc)) {
4848 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
4850 offset += USTORM_RX_PRODS_E1X_OFFSET(SC_PORT(sc), fp->cl_id);
4856 static void bnx2x_init_eth_fp(struct bnx2x_softc *sc, int idx)
4858 struct bnx2x_fastpath *fp = &sc->fp[idx];
4859 uint32_t cids[ECORE_MULTI_TX_COS] = { 0 };
4860 unsigned long q_type = 0;
4866 fp->igu_sb_id = (sc->igu_base_sb + idx + CNIC_SUPPORT(sc));
4867 fp->fw_sb_id = (sc->base_fw_ndsb + idx + CNIC_SUPPORT(sc));
4869 if (CHIP_IS_E1x(sc))
4870 fp->cl_id = SC_L_ID(sc) + idx;
4872 /* want client ID same as IGU SB ID for non-E1 */
4873 fp->cl_id = fp->igu_sb_id;
4874 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
4876 /* setup sb indices */
4877 if (!CHIP_IS_E1x(sc)) {
4878 fp->sb_index_values = fp->status_block.e2_sb->sb.index_values;
4879 fp->sb_running_index = fp->status_block.e2_sb->sb.running_index;
4881 fp->sb_index_values = fp->status_block.e1x_sb->sb.index_values;
4882 fp->sb_running_index =
4883 fp->status_block.e1x_sb->sb.running_index;
4887 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(sc, fp);
4889 fp->rx_cq_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS];
4891 for (cos = 0; cos < sc->max_cos; cos++) {
4894 fp->tx_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0];
4896 /* nothing more for a VF to do */
4901 bnx2x_init_sb(sc, fp->sb_dma.paddr, BNX2X_VF_ID_INVALID, FALSE,
4902 fp->fw_sb_id, fp->igu_sb_id);
4904 bnx2x_update_fp_sb_idx(fp);
4906 /* Configure Queue State object */
4907 bnx2x_set_bit(ECORE_Q_TYPE_HAS_RX, &q_type);
4908 bnx2x_set_bit(ECORE_Q_TYPE_HAS_TX, &q_type);
4910 ecore_init_queue_obj(sc,
4911 &sc->sp_objs[idx].q_obj,
4916 BNX2X_SP(sc, q_rdata),
4917 (rte_iova_t)BNX2X_SP_MAPPING(sc, q_rdata),
4920 /* configure classification DBs */
4921 ecore_init_mac_obj(sc,
4922 &sc->sp_objs[idx].mac_obj,
4926 BNX2X_SP(sc, mac_rdata),
4927 (rte_iova_t)BNX2X_SP_MAPPING(sc, mac_rdata),
4928 ECORE_FILTER_MAC_PENDING, &sc->sp_state,
4929 ECORE_OBJ_TYPE_RX_TX, &sc->macs_pool);
4933 bnx2x_update_rx_prod(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
4934 uint16_t rx_bd_prod, uint16_t rx_cq_prod)
4936 union ustorm_eth_rx_producers rx_prods;
4939 /* update producers */
4940 rx_prods.prod.bd_prod = rx_bd_prod;
4941 rx_prods.prod.cqe_prod = rx_cq_prod;
4942 rx_prods.prod.reserved = 0;
4945 * Make sure that the BD and SGE data is updated before updating the
4946 * producers since FW might read the BD/SGE right after the producer
4948 * This is only applicable for weak-ordered memory model archs such
4949 * as IA-64. The following barrier is also mandatory since FW will
4950 * assumes BDs must have buffers.
4954 for (i = 0; i < (sizeof(rx_prods) / 4); i++) {
4956 (fp->ustorm_rx_prods_offset + (i * 4)),
4957 rx_prods.raw_data[i]);
4960 wmb(); /* keep prod updates ordered */
4963 static void bnx2x_init_rx_rings(struct bnx2x_softc *sc)
4965 struct bnx2x_fastpath *fp;
4967 struct bnx2x_rx_queue *rxq;
4969 for (i = 0; i < sc->num_queues; i++) {
4971 rxq = sc->rx_queues[fp->index];
4973 PMD_RX_LOG(ERR, "RX queue is NULL");
4977 rxq->rx_bd_head = 0;
4978 rxq->rx_bd_tail = rxq->nb_rx_desc;
4979 rxq->rx_cq_head = 0;
4980 rxq->rx_cq_tail = TOTAL_RCQ_ENTRIES(rxq);
4981 *fp->rx_cq_cons_sb = 0;
4984 * Activate the BD ring...
4985 * Warning, this will generate an interrupt (to the TSTORM)
4986 * so this can only be done after the chip is initialized
4988 bnx2x_update_rx_prod(sc, fp, rxq->rx_bd_tail, rxq->rx_cq_tail);
4996 static void bnx2x_init_tx_ring_one(struct bnx2x_fastpath *fp)
4998 struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
5000 fp->tx_db.data.header.header = 1 << DOORBELL_HDR_DB_TYPE_SHIFT;
5001 fp->tx_db.data.zero_fill1 = 0;
5002 fp->tx_db.data.prod = 0;
5005 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
5009 txq->tx_pkt_tail = 0;
5010 txq->tx_pkt_head = 0;
5011 txq->tx_bd_tail = 0;
5012 txq->tx_bd_head = 0;
5015 static void bnx2x_init_tx_rings(struct bnx2x_softc *sc)
5019 for (i = 0; i < sc->num_queues; i++) {
5020 bnx2x_init_tx_ring_one(&sc->fp[i]);
5024 static void bnx2x_init_def_sb(struct bnx2x_softc *sc)
5026 struct host_sp_status_block *def_sb = sc->def_sb;
5027 rte_iova_t mapping = sc->def_sb_dma.paddr;
5028 int igu_sp_sb_index;
5030 int port = SC_PORT(sc);
5031 int func = SC_FUNC(sc);
5032 int reg_offset, reg_offset_en5;
5035 struct hc_sp_status_block_data sp_sb_data;
5037 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5039 if (CHIP_INT_MODE_IS_BC(sc)) {
5040 igu_sp_sb_index = DEF_SB_IGU_ID;
5041 igu_seg_id = HC_SEG_ACCESS_DEF;
5043 igu_sp_sb_index = sc->igu_dsb_id;
5044 igu_seg_id = IGU_SEG_ACCESS_DEF;
5048 section = ((uint64_t) mapping +
5049 offsetof(struct host_sp_status_block, atten_status_block));
5050 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5053 reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5054 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
5056 reg_offset_en5 = (port) ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5057 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0;
5059 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5060 /* take care of sig[0]..sig[4] */
5061 for (sindex = 0; sindex < 4; sindex++) {
5062 sc->attn_group[index].sig[sindex] =
5064 (reg_offset + (sindex * 0x4) +
5068 if (!CHIP_IS_E1x(sc)) {
5070 * enable5 is separate from the rest of the registers,
5071 * and the address skip is 4 and not 16 between the
5074 sc->attn_group[index].sig[4] =
5075 REG_RD(sc, (reg_offset_en5 + (0x4 * index)));
5077 sc->attn_group[index].sig[4] = 0;
5081 if (sc->devinfo.int_block == INT_BLOCK_HC) {
5083 port ? HC_REG_ATTN_MSG1_ADDR_L : HC_REG_ATTN_MSG0_ADDR_L;
5084 REG_WR(sc, reg_offset, U64_LO(section));
5085 REG_WR(sc, (reg_offset + 4), U64_HI(section));
5086 } else if (!CHIP_IS_E1x(sc)) {
5087 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5088 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5091 section = ((uint64_t) mapping +
5092 offsetof(struct host_sp_status_block, sp_sb));
5094 bnx2x_zero_sp_sb(sc);
5096 /* PCI guarantees endianity of regpair */
5097 sp_sb_data.state = SB_ENABLED;
5098 sp_sb_data.host_sb_addr.lo = U64_LO(section);
5099 sp_sb_data.host_sb_addr.hi = U64_HI(section);
5100 sp_sb_data.igu_sb_id = igu_sp_sb_index;
5101 sp_sb_data.igu_seg_id = igu_seg_id;
5102 sp_sb_data.p_func.pf_id = func;
5103 sp_sb_data.p_func.vnic_id = SC_VN(sc);
5104 sp_sb_data.p_func.vf_id = 0xff;
5106 bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
5108 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5111 static void bnx2x_init_sp_ring(struct bnx2x_softc *sc)
5113 atomic_store_rel_long(&sc->cq_spq_left, MAX_SPQ_PENDING);
5114 sc->spq_prod_idx = 0;
5116 &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_ETH_DEF_CONS];
5117 sc->spq_prod_bd = sc->spq;
5118 sc->spq_last_bd = (sc->spq_prod_bd + MAX_SP_DESC_CNT);
5121 static void bnx2x_init_eq_ring(struct bnx2x_softc *sc)
5123 union event_ring_elem *elem;
5126 for (i = 1; i <= NUM_EQ_PAGES; i++) {
5127 elem = &sc->eq[EQ_DESC_CNT_PAGE * i - 1];
5129 elem->next_page.addr.hi = htole32(U64_HI(sc->eq_dma.paddr +
5131 (i % NUM_EQ_PAGES)));
5132 elem->next_page.addr.lo = htole32(U64_LO(sc->eq_dma.paddr +
5134 (i % NUM_EQ_PAGES)));
5138 sc->eq_prod = NUM_EQ_DESC;
5139 sc->eq_cons_sb = &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_EQ_CONS];
5141 atomic_store_rel_long(&sc->eq_spq_left,
5142 (min((MAX_SP_DESC_CNT - MAX_SPQ_PENDING),
5146 static void bnx2x_init_internal_common(struct bnx2x_softc *sc)
5152 * In switch independent mode, the TSTORM needs to accept
5153 * packets that failed classification, since approximate match
5154 * mac addresses aren't written to NIG LLH.
5157 (BAR_TSTRORM_INTMEM +
5158 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 2);
5161 (BAR_TSTRORM_INTMEM +
5162 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 0);
5165 * Zero this manually as its initialization is currently missing
5168 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) {
5170 (BAR_USTRORM_INTMEM + USTORM_AGG_DATA_OFFSET + (i * 4)),
5174 if (!CHIP_IS_E1x(sc)) {
5175 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET),
5176 CHIP_INT_MODE_IS_BC(sc) ? HC_IGU_BC_MODE :
5181 static void bnx2x_init_internal(struct bnx2x_softc *sc, uint32_t load_code)
5183 switch (load_code) {
5184 case FW_MSG_CODE_DRV_LOAD_COMMON:
5185 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5186 bnx2x_init_internal_common(sc);
5189 case FW_MSG_CODE_DRV_LOAD_PORT:
5193 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5194 /* internal memory per function is initialized inside bnx2x_pf_init */
5198 PMD_DRV_LOG(NOTICE, "Unknown load_code (0x%x) from MCP",
5205 storm_memset_func_cfg(struct bnx2x_softc *sc,
5206 struct tstorm_eth_function_common_config *tcfg,
5212 addr = (BAR_TSTRORM_INTMEM +
5213 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid));
5214 size = sizeof(struct tstorm_eth_function_common_config);
5215 ecore_storm_memset_struct(sc, addr, size, (uint32_t *) tcfg);
5218 static void bnx2x_func_init(struct bnx2x_softc *sc, struct bnx2x_func_init_params *p)
5220 struct tstorm_eth_function_common_config tcfg = { 0 };
5222 if (CHIP_IS_E1x(sc)) {
5223 storm_memset_func_cfg(sc, &tcfg, p->func_id);
5226 /* Enable the function in the FW */
5227 storm_memset_vf_to_pf(sc, p->func_id, p->pf_id);
5228 storm_memset_func_en(sc, p->func_id, 1);
5231 if (p->func_flgs & FUNC_FLG_SPQ) {
5232 storm_memset_spq_addr(sc, p->spq_map, p->func_id);
5234 (XSEM_REG_FAST_MEMORY +
5235 XSTORM_SPQ_PROD_OFFSET(p->func_id)), p->spq_prod);
5240 * Calculates the sum of vn_min_rates.
5241 * It's needed for further normalizing of the min_rates.
5243 * sum of vn_min_rates.
5245 * 0 - if all the min_rates are 0.
5246 * In the later case fainess algorithm should be deactivated.
5247 * If all min rates are not zero then those that are zeroes will be set to 1.
5249 static void bnx2x_calc_vn_min(struct bnx2x_softc *sc, struct cmng_init_input *input)
5252 uint32_t vn_min_rate;
5256 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5257 vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5258 vn_min_rate = (((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
5259 FUNC_MF_CFG_MIN_BW_SHIFT) * 100);
5261 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5262 /* skip hidden VNs */
5264 } else if (!vn_min_rate) {
5265 /* If min rate is zero - set it to 100 */
5266 vn_min_rate = DEF_MIN_RATE;
5271 input->vnic_min_rate[vn] = vn_min_rate;
5274 /* if ETS or all min rates are zeros - disable fairness */
5276 input->flags.cmng_enables &= ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5278 input->flags.cmng_enables |= CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5283 bnx2x_extract_max_cfg(__rte_unused struct bnx2x_softc *sc, uint32_t mf_cfg)
5285 uint16_t max_cfg = ((mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
5286 FUNC_MF_CFG_MAX_BW_SHIFT);
5290 "Max BW configured to 0 - using 100 instead");
5298 bnx2x_calc_vn_max(struct bnx2x_softc *sc, int vn, struct cmng_init_input *input)
5300 uint16_t vn_max_rate;
5301 uint32_t vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5304 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5307 max_cfg = bnx2x_extract_max_cfg(sc, vn_cfg);
5310 /* max_cfg in percents of linkspeed */
5312 ((sc->link_vars.line_speed * max_cfg) / 100);
5313 } else { /* SD modes */
5314 /* max_cfg is absolute in 100Mb units */
5315 vn_max_rate = (max_cfg * 100);
5319 input->vnic_max_rate[vn] = vn_max_rate;
5323 bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg, uint8_t cmng_type)
5325 struct cmng_init_input input;
5328 memset(&input, 0, sizeof(struct cmng_init_input));
5330 input.port_rate = sc->link_vars.line_speed;
5332 if (cmng_type == CMNG_FNS_MINMAX) {
5333 /* read mf conf from shmem */
5335 bnx2x_read_mf_cfg(sc);
5338 /* get VN min rate and enable fairness if not 0 */
5339 bnx2x_calc_vn_min(sc, &input);
5341 /* get VN max rate */
5343 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5344 bnx2x_calc_vn_max(sc, vn, &input);
5348 /* always enable rate shaping and fairness */
5349 input.flags.cmng_enables |= CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
5351 ecore_init_cmng(&input, &sc->cmng);
5356 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc)
5358 if (CHIP_REV_IS_SLOW(sc)) {
5359 return CMNG_FNS_NONE;
5363 return CMNG_FNS_MINMAX;
5366 return CMNG_FNS_NONE;
5370 storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng, uint8_t port)
5377 addr = (BAR_XSTRORM_INTMEM + XSTORM_CMNG_PER_PORT_VARS_OFFSET(port));
5378 size = sizeof(struct cmng_struct_per_port);
5379 ecore_storm_memset_struct(sc, addr, size, (uint32_t *) & cmng->port);
5381 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5382 func = func_by_vn(sc, vn);
5384 addr = (BAR_XSTRORM_INTMEM +
5385 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func));
5386 size = sizeof(struct rate_shaping_vars_per_vn);
5387 ecore_storm_memset_struct(sc, addr, size,
5388 (uint32_t *) & cmng->
5389 vnic.vnic_max_rate[vn]);
5391 addr = (BAR_XSTRORM_INTMEM +
5392 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func));
5393 size = sizeof(struct fairness_vars_per_vn);
5394 ecore_storm_memset_struct(sc, addr, size,
5395 (uint32_t *) & cmng->
5396 vnic.vnic_min_rate[vn]);
5400 static void bnx2x_pf_init(struct bnx2x_softc *sc)
5402 struct bnx2x_func_init_params func_init;
5403 struct event_ring_data eq_data;
5406 memset(&eq_data, 0, sizeof(struct event_ring_data));
5407 memset(&func_init, 0, sizeof(struct bnx2x_func_init_params));
5409 if (!CHIP_IS_E1x(sc)) {
5410 /* reset IGU PF statistics: MSIX + ATTN */
5413 (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5414 (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5415 ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5419 (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5420 (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5421 (BNX2X_IGU_STAS_MSG_PF_CNT * 4) +
5422 ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5426 /* function setup flags */
5427 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
5429 func_init.func_flgs = flags;
5430 func_init.pf_id = SC_FUNC(sc);
5431 func_init.func_id = SC_FUNC(sc);
5432 func_init.spq_map = sc->spq_dma.paddr;
5433 func_init.spq_prod = sc->spq_prod_idx;
5435 bnx2x_func_init(sc, &func_init);
5437 memset(&sc->cmng, 0, sizeof(struct cmng_struct_per_port));
5440 * Congestion management values depend on the link rate.
5441 * There is no active link so initial link rate is set to 10Gbps.
5442 * When the link comes up the congestion management values are
5443 * re-calculated according to the actual link rate.
5445 sc->link_vars.line_speed = SPEED_10000;
5446 bnx2x_cmng_fns_init(sc, TRUE, bnx2x_get_cmng_fns_mode(sc));
5448 /* Only the PMF sets the HW */
5450 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
5453 /* init Event Queue - PCI bus guarantees correct endainity */
5454 eq_data.base_addr.hi = U64_HI(sc->eq_dma.paddr);
5455 eq_data.base_addr.lo = U64_LO(sc->eq_dma.paddr);
5456 eq_data.producer = sc->eq_prod;
5457 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
5458 eq_data.sb_id = DEF_SB_ID;
5459 storm_memset_eq_data(sc, &eq_data, SC_FUNC(sc));
5462 static void bnx2x_hc_int_enable(struct bnx2x_softc *sc)
5464 int port = SC_PORT(sc);
5465 uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5466 uint32_t val = REG_RD(sc, addr);
5467 uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5468 || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5469 uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5470 uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5473 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5474 HC_CONFIG_0_REG_INT_LINE_EN_0);
5475 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5476 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5478 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
5481 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
5482 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5483 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5484 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5486 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5487 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5488 HC_CONFIG_0_REG_INT_LINE_EN_0 |
5489 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5491 REG_WR(sc, addr, val);
5493 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
5496 REG_WR(sc, addr, val);
5498 /* ensure that HC_CONFIG is written before leading/trailing edge config */
5501 /* init leading/trailing edge */
5503 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5505 /* enable nig and gpio3 attention */
5512 REG_WR(sc, (HC_REG_TRAILING_EDGE_0 + port * 8), val);
5513 REG_WR(sc, (HC_REG_LEADING_EDGE_0 + port * 8), val);
5515 /* make sure that interrupts are indeed enabled from here on */
5519 static void bnx2x_igu_int_enable(struct bnx2x_softc *sc)
5522 uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5523 || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5524 uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5525 uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5527 val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5530 val &= ~(IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5531 val |= (IGU_PF_CONF_MSI_MSIX_EN | IGU_PF_CONF_ATTN_BIT_EN);
5533 val |= IGU_PF_CONF_SINGLE_ISR_EN;
5536 val &= ~IGU_PF_CONF_INT_LINE_EN;
5537 val |= (IGU_PF_CONF_MSI_MSIX_EN |
5538 IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5540 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
5541 val |= (IGU_PF_CONF_INT_LINE_EN |
5542 IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5545 /* clean previous status - need to configure igu prior to ack */
5546 if ((!msix) || single_msix) {
5547 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5551 val |= IGU_PF_CONF_FUNC_EN;
5553 PMD_DRV_LOG(DEBUG, "write 0x%x to IGU mode %s",
5554 val, ((msix) ? "MSI-X" : ((msi) ? "MSI" : "INTx")));
5556 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5560 /* init leading/trailing edge */
5562 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5564 /* enable nig and gpio3 attention */
5571 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
5572 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
5574 /* make sure that interrupts are indeed enabled from here on */
5578 static void bnx2x_int_enable(struct bnx2x_softc *sc)
5580 if (sc->devinfo.int_block == INT_BLOCK_HC) {
5581 bnx2x_hc_int_enable(sc);
5583 bnx2x_igu_int_enable(sc);
5587 static void bnx2x_hc_int_disable(struct bnx2x_softc *sc)
5589 int port = SC_PORT(sc);
5590 uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5591 uint32_t val = REG_RD(sc, addr);
5593 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5594 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5595 HC_CONFIG_0_REG_INT_LINE_EN_0 | HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5596 /* flush all outstanding writes */
5599 REG_WR(sc, addr, val);
5600 if (REG_RD(sc, addr) != val) {
5601 PMD_DRV_LOG(ERR, "proper val not read from HC IGU!");
5605 static void bnx2x_igu_int_disable(struct bnx2x_softc *sc)
5607 uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5609 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
5610 IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_ATTN_BIT_EN);
5612 PMD_DRV_LOG(DEBUG, "write %x to IGU", val);
5614 /* flush all outstanding writes */
5617 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5618 if (REG_RD(sc, IGU_REG_PF_CONFIGURATION) != val) {
5619 PMD_DRV_LOG(ERR, "proper val not read from IGU!");
5623 static void bnx2x_int_disable(struct bnx2x_softc *sc)
5625 if (sc->devinfo.int_block == INT_BLOCK_HC) {
5626 bnx2x_hc_int_disable(sc);
5628 bnx2x_igu_int_disable(sc);
5632 static void bnx2x_nic_init(struct bnx2x_softc *sc, int load_code)
5636 PMD_INIT_FUNC_TRACE();
5638 for (i = 0; i < sc->num_queues; i++) {
5639 bnx2x_init_eth_fp(sc, i);
5642 rmb(); /* ensure status block indices were read */
5644 bnx2x_init_rx_rings(sc);
5645 bnx2x_init_tx_rings(sc);
5648 bnx2x_memset_stats(sc);
5652 /* initialize MOD_ABS interrupts */
5653 elink_init_mod_abs_int(sc, &sc->link_vars,
5654 sc->devinfo.chip_id,
5655 sc->devinfo.shmem_base,
5656 sc->devinfo.shmem2_base, SC_PORT(sc));
5658 bnx2x_init_def_sb(sc);
5659 bnx2x_update_dsb_idx(sc);
5660 bnx2x_init_sp_ring(sc);
5661 bnx2x_init_eq_ring(sc);
5662 bnx2x_init_internal(sc, load_code);
5664 bnx2x_stats_init(sc);
5666 /* flush all before enabling interrupts */
5669 bnx2x_int_enable(sc);
5671 /* check for SPIO5 */
5672 bnx2x_attn_int_deasserted0(sc,
5674 (MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
5676 AEU_INPUTS_ATTN_BITS_SPIO5);
5679 static void bnx2x_init_objs(struct bnx2x_softc *sc)
5681 /* mcast rules must be added to tx if tx switching is enabled */
5682 ecore_obj_type o_type;
5683 if (sc->flags & BNX2X_TX_SWITCHING)
5684 o_type = ECORE_OBJ_TYPE_RX_TX;
5686 o_type = ECORE_OBJ_TYPE_RX;
5688 /* RX_MODE controlling object */
5689 ecore_init_rx_mode_obj(sc, &sc->rx_mode_obj);
5691 /* multicast configuration controlling object */
5692 ecore_init_mcast_obj(sc,
5698 BNX2X_SP(sc, mcast_rdata),
5699 (rte_iova_t)BNX2X_SP_MAPPING(sc, mcast_rdata),
5700 ECORE_FILTER_MCAST_PENDING,
5701 &sc->sp_state, o_type);
5703 /* Setup CAM credit pools */
5704 ecore_init_mac_credit_pool(sc,
5707 CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5708 VNICS_PER_PATH(sc));
5710 ecore_init_vlan_credit_pool(sc,
5712 SC_ABS_FUNC(sc) >> 1,
5713 CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5714 VNICS_PER_PATH(sc));
5716 /* RSS configuration object */
5717 ecore_init_rss_config_obj(&sc->rss_conf_obj,
5722 BNX2X_SP(sc, rss_rdata),
5723 (rte_iova_t)BNX2X_SP_MAPPING(sc, rss_rdata),
5724 ECORE_FILTER_RSS_CONF_PENDING,
5725 &sc->sp_state, ECORE_OBJ_TYPE_RX);
5729 * Initialize the function. This must be called before sending CLIENT_SETUP
5730 * for the first client.
5732 static int bnx2x_func_start(struct bnx2x_softc *sc)
5734 struct ecore_func_state_params func_params = { NULL };
5735 struct ecore_func_start_params *start_params =
5736 &func_params.params.start;
5738 /* Prepare parameters for function state transitions */
5739 bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
5741 func_params.f_obj = &sc->func_obj;
5742 func_params.cmd = ECORE_F_CMD_START;
5744 /* Function parameters */
5745 start_params->mf_mode = sc->devinfo.mf_info.mf_mode;
5746 start_params->sd_vlan_tag = OVLAN(sc);
5748 if (CHIP_IS_E2(sc) || CHIP_IS_E3(sc)) {
5749 start_params->network_cos_mode = STATIC_COS;
5750 } else { /* CHIP_IS_E1X */
5751 start_params->network_cos_mode = FW_WRR;
5754 start_params->gre_tunnel_mode = 0;
5755 start_params->gre_tunnel_rss = 0;
5757 return ecore_func_state_change(sc, &func_params);
5760 static int bnx2x_set_power_state(struct bnx2x_softc *sc, uint8_t state)
5764 /* If there is no power capability, silently succeed */
5765 if (!(sc->devinfo.pcie_cap_flags & BNX2X_PM_CAPABLE_FLAG)) {
5766 PMD_DRV_LOG(WARNING, "No power capability");
5770 pci_read(sc, (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS), &pmcsr,
5776 (sc->devinfo.pcie_pm_cap_reg +
5778 ((pmcsr & ~PCIM_PSTAT_DMASK) | PCIM_PSTAT_PME));
5780 if (pmcsr & PCIM_PSTAT_DMASK) {
5781 /* delay required during transition out of D3hot */
5788 /* don't shut down the power for emulation and FPGA */
5789 if (CHIP_REV_IS_SLOW(sc)) {
5793 pmcsr &= ~PCIM_PSTAT_DMASK;
5794 pmcsr |= PCIM_PSTAT_D3;
5797 pmcsr |= PCIM_PSTAT_PMEENABLE;
5801 (sc->devinfo.pcie_pm_cap_reg +
5802 PCIR_POWER_STATUS), pmcsr);
5805 * No more memory access after this point until device is brought back
5811 PMD_DRV_LOG(NOTICE, "Can't support PCI power state = %d",
5819 /* return true if succeeded to acquire the lock */
5820 static uint8_t bnx2x_trylock_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
5822 uint32_t lock_status;
5823 uint32_t resource_bit = (1 << resource);
5824 int func = SC_FUNC(sc);
5825 uint32_t hw_lock_control_reg;
5827 /* Validating that the resource is within range */
5828 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
5830 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)",
5831 resource, HW_LOCK_MAX_RESOURCE_VALUE);
5836 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func * 8);
5838 hw_lock_control_reg =
5839 (MISC_REG_DRIVER_CONTROL_7 + (func - 6) * 8);
5842 /* try to acquire the lock */
5843 REG_WR(sc, hw_lock_control_reg + 4, resource_bit);
5844 lock_status = REG_RD(sc, hw_lock_control_reg);
5845 if (lock_status & resource_bit) {
5849 PMD_DRV_LOG(NOTICE, "Failed to get a resource lock 0x%x", resource);
5855 * Get the recovery leader resource id according to the engine this function
5856 * belongs to. Currently only only 2 engines is supported.
5858 static int bnx2x_get_leader_lock_resource(struct bnx2x_softc *sc)
5861 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
5863 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
5867 /* try to acquire a leader lock for current engine */
5868 static uint8_t bnx2x_trylock_leader_lock(struct bnx2x_softc *sc)
5870 return bnx2x_trylock_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5873 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc)
5875 return bnx2x_release_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5878 /* close gates #2, #3 and #4 */
5879 static void bnx2x_set_234_gates(struct bnx2x_softc *sc, uint8_t close)
5883 /* gates #2 and #4a are closed/opened */
5885 REG_WR(sc, PXP_REG_HST_DISCARD_DOORBELLS, ! !close);
5887 REG_WR(sc, PXP_REG_HST_DISCARD_INTERNAL_WRITES, ! !close);
5890 if (CHIP_IS_E1x(sc)) {
5891 /* prevent interrupts from HC on both ports */
5892 val = REG_RD(sc, HC_REG_CONFIG_1);
5894 REG_WR(sc, HC_REG_CONFIG_1, (val & ~(uint32_t)
5895 HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5897 REG_WR(sc, HC_REG_CONFIG_1,
5898 (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5900 val = REG_RD(sc, HC_REG_CONFIG_0);
5902 REG_WR(sc, HC_REG_CONFIG_0, (val & ~(uint32_t)
5903 HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5905 REG_WR(sc, HC_REG_CONFIG_0,
5906 (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5909 /* Prevent incoming interrupts in IGU */
5910 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
5913 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5915 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5917 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5919 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5925 /* poll for pending writes bit, it should get cleared in no more than 1s */
5926 static int bnx2x_er_poll_igu_vq(struct bnx2x_softc *sc)
5928 uint32_t cnt = 1000;
5929 uint32_t pend_bits = 0;
5932 pend_bits = REG_RD(sc, IGU_REG_PENDING_BITS_STATUS);
5934 if (pend_bits == 0) {
5939 } while (cnt-- > 0);
5942 PMD_DRV_LOG(NOTICE, "Still pending IGU requests bits=0x%08x!",
5950 #define SHARED_MF_CLP_MAGIC 0x80000000 /* 'magic' bit */
5952 static void bnx2x_clp_reset_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
5954 /* Do some magic... */
5955 uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
5956 *magic_val = val & SHARED_MF_CLP_MAGIC;
5957 MFCFG_WR(sc, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
5960 /* restore the value of the 'magic' bit */
5961 static void bnx2x_clp_reset_done(struct bnx2x_softc *sc, uint32_t magic_val)
5963 /* Restore the 'magic' bit value... */
5964 uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
5965 MFCFG_WR(sc, shared_mf_config.clp_mb,
5966 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
5969 /* prepare for MCP reset, takes care of CLP configurations */
5970 static void bnx2x_reset_mcp_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
5973 uint32_t validity_offset;
5975 /* set `magic' bit in order to save MF config */
5976 bnx2x_clp_reset_prep(sc, magic_val);
5978 /* get shmem offset */
5979 shmem = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
5981 offsetof(struct shmem_region, validity_map[SC_PORT(sc)]);
5983 /* Clear validity map flags */
5985 REG_WR(sc, shmem + validity_offset, 0);
5989 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
5990 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
5992 static void bnx2x_mcp_wait_one(struct bnx2x_softc *sc)
5994 /* special handling for emulation and FPGA (10 times longer) */
5995 if (CHIP_REV_IS_SLOW(sc)) {
5996 DELAY((MCP_ONE_TIMEOUT * 10) * 1000);
5998 DELAY((MCP_ONE_TIMEOUT) * 1000);
6002 /* initialize shmem_base and waits for validity signature to appear */
6003 static int bnx2x_init_shmem(struct bnx2x_softc *sc)
6009 sc->devinfo.shmem_base =
6010 sc->link_params.shmem_base =
6011 REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
6013 if (sc->devinfo.shmem_base) {
6014 val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
6015 if (val & SHR_MEM_VALIDITY_MB)
6019 bnx2x_mcp_wait_one(sc);
6021 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
6023 PMD_DRV_LOG(NOTICE, "BAD MCP validity signature");
6028 static int bnx2x_reset_mcp_comp(struct bnx2x_softc *sc, uint32_t magic_val)
6030 int rc = bnx2x_init_shmem(sc);
6032 /* Restore the `magic' bit value */
6033 bnx2x_clp_reset_done(sc, magic_val);
6038 static void bnx2x_pxp_prep(struct bnx2x_softc *sc)
6040 REG_WR(sc, PXP2_REG_RD_START_INIT, 0);
6041 REG_WR(sc, PXP2_REG_RQ_RBC_DONE, 0);
6046 * Reset the whole chip except for:
6048 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by one reset bit)
6050 * - MISC (including AEU)
6054 static void bnx2x_process_kill_chip_reset(struct bnx2x_softc *sc, uint8_t global)
6056 uint32_t not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
6057 uint32_t global_bits2, stay_reset2;
6060 * Bits that have to be set in reset_mask2 if we want to reset 'global'
6061 * (per chip) blocks.
6064 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
6065 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
6068 * Don't reset the following blocks.
6069 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
6070 * reset, as in 4 port device they might still be owned
6071 * by the MCP (there is only one leader per path).
6074 MISC_REGISTERS_RESET_REG_1_RST_HC |
6075 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
6076 MISC_REGISTERS_RESET_REG_1_RST_PXP;
6079 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
6080 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
6081 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
6082 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
6083 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
6084 MISC_REGISTERS_RESET_REG_2_RST_GRC |
6085 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
6086 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
6087 MISC_REGISTERS_RESET_REG_2_RST_ATC |
6088 MISC_REGISTERS_RESET_REG_2_PGLC |
6089 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
6090 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
6091 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
6092 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
6093 MISC_REGISTERS_RESET_REG_2_UMAC0 | MISC_REGISTERS_RESET_REG_2_UMAC1;
6096 * Keep the following blocks in reset:
6097 * - all xxMACs are handled by the elink code.
6100 MISC_REGISTERS_RESET_REG_2_XMAC |
6101 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
6103 /* Full reset masks according to the chip */
6104 reset_mask1 = 0xffffffff;
6106 if (CHIP_IS_E1H(sc))
6107 reset_mask2 = 0x1ffff;
6108 else if (CHIP_IS_E2(sc))
6109 reset_mask2 = 0xfffff;
6110 else /* CHIP_IS_E3 */
6111 reset_mask2 = 0x3ffffff;
6113 /* Don't reset global blocks unless we need to */
6115 reset_mask2 &= ~global_bits2;
6118 * In case of attention in the QM, we need to reset PXP
6119 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
6120 * because otherwise QM reset would release 'close the gates' shortly
6121 * before resetting the PXP, then the PSWRQ would send a write
6122 * request to PGLUE. Then when PXP is reset, PGLUE would try to
6123 * read the payload data from PSWWR, but PSWWR would not
6124 * respond. The write queue in PGLUE would stuck, dmae commands
6125 * would not return. Therefore it's important to reset the second
6126 * reset register (containing the
6127 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
6128 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
6131 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
6132 reset_mask2 & (~not_reset_mask2));
6134 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6135 reset_mask1 & (~not_reset_mask1));
6140 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
6141 reset_mask2 & (~stay_reset2));
6146 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
6150 static int bnx2x_process_kill(struct bnx2x_softc *sc, uint8_t global)
6154 uint32_t sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
6155 uint32_t tags_63_32 = 0;
6157 /* Empty the Tetris buffer, wait for 1s */
6159 sr_cnt = REG_RD(sc, PXP2_REG_RD_SR_CNT);
6160 blk_cnt = REG_RD(sc, PXP2_REG_RD_BLK_CNT);
6161 port_is_idle_0 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_0);
6162 port_is_idle_1 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_1);
6163 pgl_exp_rom2 = REG_RD(sc, PXP2_REG_PGL_EXP_ROM2);
6164 if (CHIP_IS_E3(sc)) {
6165 tags_63_32 = REG_RD(sc, PGLUE_B_REG_TAGS_63_32);
6168 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
6169 ((port_is_idle_0 & 0x1) == 0x1) &&
6170 ((port_is_idle_1 & 0x1) == 0x1) &&
6171 (pgl_exp_rom2 == 0xffffffff) &&
6172 (!CHIP_IS_E3(sc) || (tags_63_32 == 0xffffffff)))
6175 } while (cnt-- > 0);
6179 "ERROR: Tetris buffer didn't get empty or there "
6180 "are still outstanding read requests after 1s! "
6181 "sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, "
6182 "port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x",
6183 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
6190 /* Close gates #2, #3 and #4 */
6191 bnx2x_set_234_gates(sc, TRUE);
6193 /* Poll for IGU VQs for 57712 and newer chips */
6194 if (!CHIP_IS_E1x(sc) && bnx2x_er_poll_igu_vq(sc)) {
6198 /* clear "unprepared" bit */
6199 REG_WR(sc, MISC_REG_UNPREPARED, 0);
6202 /* Make sure all is written to the chip before the reset */
6206 * Wait for 1ms to empty GLUE and PCI-E core queues,
6207 * PSWHST, GRC and PSWRD Tetris buffer.
6211 /* Prepare to chip reset: */
6214 bnx2x_reset_mcp_prep(sc, &val);
6221 /* reset the chip */
6222 bnx2x_process_kill_chip_reset(sc, global);
6225 /* Recover after reset: */
6227 if (global && bnx2x_reset_mcp_comp(sc, val)) {
6231 /* Open the gates #2, #3 and #4 */
6232 bnx2x_set_234_gates(sc, FALSE);
6237 static int bnx2x_leader_reset(struct bnx2x_softc *sc)
6240 uint8_t global = bnx2x_reset_is_global(sc);
6244 * If not going to reset MCP, load "fake" driver to reset HW while
6245 * driver is owner of the HW.
6247 if (!global && !BNX2X_NOMCP(sc)) {
6248 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
6249 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
6251 PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
6253 goto exit_leader_reset;
6256 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
6257 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
6259 "MCP unexpected response, aborting");
6261 goto exit_leader_reset2;
6264 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
6266 PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
6268 goto exit_leader_reset2;
6272 /* try to recover after the failure */
6273 if (bnx2x_process_kill(sc, global)) {
6274 PMD_DRV_LOG(NOTICE, "Something bad occurred on engine %d!",
6277 goto exit_leader_reset2;
6281 * Clear the RESET_IN_PROGRESS and RESET_GLOBAL bits and update the driver
6284 bnx2x_set_reset_done(sc);
6286 bnx2x_clear_reset_global(sc);
6291 /* unload "fake driver" if it was loaded */
6292 if (!global &&!BNX2X_NOMCP(sc)) {
6293 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
6294 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
6300 bnx2x_release_leader_lock(sc);
6307 * prepare INIT transition, parameters configured:
6308 * - HC configuration
6309 * - Queue's CDU context
6312 bnx2x_pf_q_prep_init(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6313 struct ecore_queue_init_params *init_params)
6316 int cxt_index, cxt_offset;
6318 bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->rx.flags);
6319 bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->tx.flags);
6321 bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->rx.flags);
6322 bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->tx.flags);
6325 init_params->rx.hc_rate =
6326 sc->hc_rx_ticks ? (1000000 / sc->hc_rx_ticks) : 0;
6327 init_params->tx.hc_rate =
6328 sc->hc_tx_ticks ? (1000000 / sc->hc_tx_ticks) : 0;
6331 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = fp->fw_sb_id;
6333 /* CQ index among the SB indices */
6334 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6335 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
6337 /* set maximum number of COSs supported by this queue */
6338 init_params->max_cos = sc->max_cos;
6340 /* set the context pointers queue object */
6341 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
6342 cxt_index = fp->index / ILT_PAGE_CIDS;
6343 cxt_offset = fp->index - (cxt_index * ILT_PAGE_CIDS);
6344 init_params->cxts[cos] =
6345 &sc->context[cxt_index].vcxt[cxt_offset].eth;
6349 /* set flags that are common for the Tx-only and not normal connections */
6350 static unsigned long
6351 bnx2x_get_common_flags(struct bnx2x_softc *sc, uint8_t zero_stats)
6353 unsigned long flags = 0;
6355 /* PF driver will always initialize the Queue to an ACTIVE state */
6356 bnx2x_set_bit(ECORE_Q_FLG_ACTIVE, &flags);
6359 * tx only connections collect statistics (on the same index as the
6360 * parent connection). The statistics are zeroed when the parent
6361 * connection is initialized.
6364 bnx2x_set_bit(ECORE_Q_FLG_STATS, &flags);
6366 bnx2x_set_bit(ECORE_Q_FLG_ZERO_STATS, &flags);
6370 * tx only connections can support tx-switching, though their
6371 * CoS-ness doesn't survive the loopback
6373 if (sc->flags & BNX2X_TX_SWITCHING) {
6374 bnx2x_set_bit(ECORE_Q_FLG_TX_SWITCH, &flags);
6377 bnx2x_set_bit(ECORE_Q_FLG_PCSUM_ON_PKT, &flags);
6382 static unsigned long bnx2x_get_q_flags(struct bnx2x_softc *sc, uint8_t leading)
6384 unsigned long flags = 0;
6387 bnx2x_set_bit(ECORE_Q_FLG_OV, &flags);
6391 bnx2x_set_bit(ECORE_Q_FLG_LEADING_RSS, &flags);
6392 bnx2x_set_bit(ECORE_Q_FLG_MCAST, &flags);
6395 bnx2x_set_bit(ECORE_Q_FLG_VLAN, &flags);
6397 /* merge with common flags */
6398 return flags | bnx2x_get_common_flags(sc, TRUE);
6402 bnx2x_pf_q_prep_general(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6403 struct ecore_general_setup_params *gen_init, uint8_t cos)
6405 gen_init->stat_id = bnx2x_stats_id(fp);
6406 gen_init->spcl_id = fp->cl_id;
6407 gen_init->mtu = sc->mtu;
6408 gen_init->cos = cos;
6412 bnx2x_pf_rx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6413 struct rxq_pause_params *pause,
6414 struct ecore_rxq_setup_params *rxq_init)
6416 struct bnx2x_rx_queue *rxq;
6418 rxq = sc->rx_queues[fp->index];
6420 PMD_RX_LOG(ERR, "RX queue is NULL");
6424 pause->bd_th_lo = BD_TH_LO(sc);
6425 pause->bd_th_hi = BD_TH_HI(sc);
6427 pause->rcq_th_lo = RCQ_TH_LO(sc);
6428 pause->rcq_th_hi = RCQ_TH_HI(sc);
6430 /* validate rings have enough entries to cross high thresholds */
6431 if (sc->dropless_fc &&
6432 pause->bd_th_hi + FW_PREFETCH_CNT > sc->rx_ring_size) {
6433 PMD_DRV_LOG(WARNING, "rx bd ring threshold limit");
6436 if (sc->dropless_fc &&
6437 pause->rcq_th_hi + FW_PREFETCH_CNT > USABLE_RCQ_ENTRIES(rxq)) {
6438 PMD_DRV_LOG(WARNING, "rcq ring threshold limit");
6444 rxq_init->dscr_map = (rte_iova_t)rxq->rx_ring_phys_addr;
6445 rxq_init->rcq_map = (rte_iova_t)rxq->cq_ring_phys_addr;
6446 rxq_init->rcq_np_map = (rte_iova_t)(rxq->cq_ring_phys_addr +
6450 * This should be a maximum number of data bytes that may be
6451 * placed on the BD (not including paddings).
6453 rxq_init->buf_sz = (fp->rx_buf_size - IP_HEADER_ALIGNMENT_PADDING);
6455 rxq_init->cl_qzone_id = fp->cl_qzone_id;
6456 rxq_init->rss_engine_id = SC_FUNC(sc);
6457 rxq_init->mcast_engine_id = SC_FUNC(sc);
6459 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
6460 rxq_init->fw_sb_id = fp->fw_sb_id;
6462 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6465 * configure silent vlan removal
6466 * if multi function mode is afex, then mask default vlan
6468 if (IS_MF_AFEX(sc)) {
6469 rxq_init->silent_removal_value =
6470 sc->devinfo.mf_info.afex_def_vlan_tag;
6471 rxq_init->silent_removal_mask = EVL_VLID_MASK;
6476 bnx2x_pf_tx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6477 struct ecore_txq_setup_params *txq_init, uint8_t cos)
6479 struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
6482 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
6485 txq_init->dscr_map = (rte_iova_t)txq->tx_ring_phys_addr;
6486 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
6487 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
6488 txq_init->fw_sb_id = fp->fw_sb_id;
6491 * set the TSS leading client id for TX classfication to the
6492 * leading RSS client id
6494 txq_init->tss_leading_cl_id = BNX2X_FP(sc, 0, cl_id);
6498 * This function performs 2 steps in a queue state machine:
6503 bnx2x_setup_queue(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp, uint8_t leading)
6505 struct ecore_queue_state_params q_params = { NULL };
6506 struct ecore_queue_setup_params *setup_params = &q_params.params.setup;
6509 PMD_DRV_LOG(DEBUG, "setting up queue %d", fp->index);
6511 bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6513 q_params.q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
6515 /* we want to wait for completion in this context */
6516 bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
6518 /* prepare the INIT parameters */
6519 bnx2x_pf_q_prep_init(sc, fp, &q_params.params.init);
6521 /* Set the command */
6522 q_params.cmd = ECORE_Q_CMD_INIT;
6524 /* Change the state to INIT */
6525 rc = ecore_queue_state_change(sc, &q_params);
6527 PMD_DRV_LOG(NOTICE, "Queue(%d) INIT failed", fp->index);
6531 PMD_DRV_LOG(DEBUG, "init complete");
6533 /* now move the Queue to the SETUP state */
6534 memset(setup_params, 0, sizeof(*setup_params));
6536 /* set Queue flags */
6537 setup_params->flags = bnx2x_get_q_flags(sc, leading);
6539 /* set general SETUP parameters */
6540 bnx2x_pf_q_prep_general(sc, fp, &setup_params->gen_params,
6541 FIRST_TX_COS_INDEX);
6543 bnx2x_pf_rx_q_prep(sc, fp,
6544 &setup_params->pause_params,
6545 &setup_params->rxq_params);
6547 bnx2x_pf_tx_q_prep(sc, fp, &setup_params->txq_params, FIRST_TX_COS_INDEX);
6549 /* Set the command */
6550 q_params.cmd = ECORE_Q_CMD_SETUP;
6552 /* change the state to SETUP */
6553 rc = ecore_queue_state_change(sc, &q_params);
6555 PMD_DRV_LOG(NOTICE, "Queue(%d) SETUP failed", fp->index);
6562 static int bnx2x_setup_leading(struct bnx2x_softc *sc)
6565 return bnx2x_setup_queue(sc, &sc->fp[0], TRUE);
6567 return bnx2x_vf_setup_queue(sc, &sc->fp[0], TRUE);
6571 bnx2x_config_rss_pf(struct bnx2x_softc *sc, struct ecore_rss_config_obj *rss_obj,
6572 uint8_t config_hash)
6574 struct ecore_config_rss_params params = { NULL };
6578 * Although RSS is meaningless when there is a single HW queue we
6579 * still need it enabled in order to have HW Rx hash generated.
6582 params.rss_obj = rss_obj;
6584 bnx2x_set_bit(RAMROD_COMP_WAIT, ¶ms.ramrod_flags);
6586 bnx2x_set_bit(ECORE_RSS_MODE_REGULAR, ¶ms.rss_flags);
6588 /* RSS configuration */
6589 bnx2x_set_bit(ECORE_RSS_IPV4, ¶ms.rss_flags);
6590 bnx2x_set_bit(ECORE_RSS_IPV4_TCP, ¶ms.rss_flags);
6591 bnx2x_set_bit(ECORE_RSS_IPV6, ¶ms.rss_flags);
6592 bnx2x_set_bit(ECORE_RSS_IPV6_TCP, ¶ms.rss_flags);
6593 if (rss_obj->udp_rss_v4) {
6594 bnx2x_set_bit(ECORE_RSS_IPV4_UDP, ¶ms.rss_flags);
6596 if (rss_obj->udp_rss_v6) {
6597 bnx2x_set_bit(ECORE_RSS_IPV6_UDP, ¶ms.rss_flags);
6601 params.rss_result_mask = MULTI_MASK;
6603 rte_memcpy(params.ind_table, rss_obj->ind_table,
6604 sizeof(params.ind_table));
6608 for (i = 0; i < sizeof(params.rss_key) / 4; i++) {
6609 params.rss_key[i] = (uint32_t) rte_rand();
6612 bnx2x_set_bit(ECORE_RSS_SET_SRCH, ¶ms.rss_flags);
6616 return ecore_config_rss(sc, ¶ms);
6618 return bnx2x_vf_config_rss(sc, ¶ms);
6621 static int bnx2x_config_rss_eth(struct bnx2x_softc *sc, uint8_t config_hash)
6623 return bnx2x_config_rss_pf(sc, &sc->rss_conf_obj, config_hash);
6626 static int bnx2x_init_rss_pf(struct bnx2x_softc *sc)
6628 uint8_t num_eth_queues = BNX2X_NUM_ETH_QUEUES(sc);
6632 * Prepare the initial contents of the indirection table if
6635 for (i = 0; i < sizeof(sc->rss_conf_obj.ind_table); i++) {
6636 sc->rss_conf_obj.ind_table[i] =
6637 (sc->fp->cl_id + (i % num_eth_queues));
6641 sc->rss_conf_obj.udp_rss_v4 = sc->rss_conf_obj.udp_rss_v6 = 1;
6645 * For 57711 SEARCHER configuration (rss_keys) is
6646 * per-port, so if explicit configuration is needed, do it only
6649 * For 57712 and newer it's a per-function configuration.
6651 return bnx2x_config_rss_eth(sc, sc->port.pmf || !CHIP_IS_E1x(sc));
6655 bnx2x_set_mac_one(struct bnx2x_softc *sc, uint8_t * mac,
6656 struct ecore_vlan_mac_obj *obj, uint8_t set, int mac_type,
6657 unsigned long *ramrod_flags)
6659 struct ecore_vlan_mac_ramrod_params ramrod_param;
6662 memset(&ramrod_param, 0, sizeof(ramrod_param));
6664 /* fill in general parameters */
6665 ramrod_param.vlan_mac_obj = obj;
6666 ramrod_param.ramrod_flags = *ramrod_flags;
6668 /* fill a user request section if needed */
6669 if (!bnx2x_test_bit(RAMROD_CONT, ramrod_flags)) {
6670 rte_memcpy(ramrod_param.user_req.u.mac.mac, mac,
6673 bnx2x_set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
6675 /* Set the command: ADD or DEL */
6676 ramrod_param.user_req.cmd = (set) ? ECORE_VLAN_MAC_ADD :
6680 rc = ecore_config_vlan_mac(sc, &ramrod_param);
6682 if (rc == ECORE_EXISTS) {
6683 PMD_DRV_LOG(INFO, "Failed to schedule ADD operations (EEXIST)");
6684 /* do not treat adding same MAC as error */
6686 } else if (rc < 0) {
6688 "%s MAC failed (%d)", (set ? "Set" : "Delete"), rc);
6694 static int bnx2x_set_eth_mac(struct bnx2x_softc *sc, uint8_t set)
6696 unsigned long ramrod_flags = 0;
6698 PMD_DRV_LOG(DEBUG, "Adding Ethernet MAC");
6700 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
6702 /* Eth MAC is set on RSS leading client (fp[0]) */
6703 return bnx2x_set_mac_one(sc, sc->link_params.mac_addr,
6704 &sc->sp_objs->mac_obj,
6705 set, ECORE_ETH_MAC, &ramrod_flags);
6708 static int bnx2x_get_cur_phy_idx(struct bnx2x_softc *sc)
6710 uint32_t sel_phy_idx = 0;
6712 if (sc->link_params.num_phys <= 1) {
6713 return ELINK_INT_PHY;
6716 if (sc->link_vars.link_up) {
6717 sel_phy_idx = ELINK_EXT_PHY1;
6718 /* In case link is SERDES, check if the ELINK_EXT_PHY2 is the one */
6719 if ((sc->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
6720 (sc->link_params.phy[ELINK_EXT_PHY2].supported &
6721 ELINK_SUPPORTED_FIBRE))
6722 sel_phy_idx = ELINK_EXT_PHY2;
6724 switch (elink_phy_selection(&sc->link_params)) {
6725 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6726 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
6727 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6728 sel_phy_idx = ELINK_EXT_PHY1;
6730 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
6731 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6732 sel_phy_idx = ELINK_EXT_PHY2;
6740 static int bnx2x_get_link_cfg_idx(struct bnx2x_softc *sc)
6742 uint32_t sel_phy_idx = bnx2x_get_cur_phy_idx(sc);
6745 * The selected activated PHY is always after swapping (in case PHY
6746 * swapping is enabled). So when swapping is enabled, we need to reverse
6750 if (sc->link_params.multi_phy_config & PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
6751 if (sel_phy_idx == ELINK_EXT_PHY1)
6752 sel_phy_idx = ELINK_EXT_PHY2;
6753 else if (sel_phy_idx == ELINK_EXT_PHY2)
6754 sel_phy_idx = ELINK_EXT_PHY1;
6757 return ELINK_LINK_CONFIG_IDX(sel_phy_idx);
6760 static void bnx2x_set_requested_fc(struct bnx2x_softc *sc)
6763 * Initialize link parameters structure variables
6764 * It is recommended to turn off RX FC for jumbo frames
6765 * for better performance
6767 if (CHIP_IS_E1x(sc) && (sc->mtu > 5000)) {
6768 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_TX;
6770 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_BOTH;
6774 static void bnx2x_calc_fc_adv(struct bnx2x_softc *sc)
6776 uint8_t cfg_idx = bnx2x_get_link_cfg_idx(sc);
6777 switch (sc->link_vars.ieee_fc &
6778 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
6779 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
6781 sc->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
6785 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
6786 sc->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
6790 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
6791 sc->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
6796 static uint16_t bnx2x_get_mf_speed(struct bnx2x_softc *sc)
6798 uint16_t line_speed = sc->link_vars.line_speed;
6800 uint16_t maxCfg = bnx2x_extract_max_cfg(sc,
6802 mf_info.mf_config[SC_VN
6805 /* calculate the current MAX line speed limit for the MF devices */
6807 line_speed = (line_speed * maxCfg) / 100;
6808 } else { /* SD mode */
6809 uint16_t vn_max_rate = maxCfg * 100;
6811 if (vn_max_rate < line_speed) {
6812 line_speed = vn_max_rate;
6821 bnx2x_fill_report_data(struct bnx2x_softc *sc, struct bnx2x_link_report_data *data)
6823 uint16_t line_speed = bnx2x_get_mf_speed(sc);
6825 memset(data, 0, sizeof(*data));
6827 /* fill the report data with the effective line speed */
6828 data->line_speed = line_speed;
6831 if (!sc->link_vars.link_up || (sc->flags & BNX2X_MF_FUNC_DIS)) {
6832 bnx2x_set_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6833 &data->link_report_flags);
6837 if (sc->link_vars.duplex == DUPLEX_FULL) {
6838 bnx2x_set_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6839 &data->link_report_flags);
6842 /* Rx Flow Control is ON */
6843 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_RX) {
6844 bnx2x_set_bit(BNX2X_LINK_REPORT_RX_FC_ON, &data->link_report_flags);
6847 /* Tx Flow Control is ON */
6848 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
6849 bnx2x_set_bit(BNX2X_LINK_REPORT_TX_FC_ON, &data->link_report_flags);
6853 /* report link status to OS, should be called under phy_lock */
6854 static void bnx2x_link_report(struct bnx2x_softc *sc)
6856 struct bnx2x_link_report_data cur_data;
6860 bnx2x_read_mf_cfg(sc);
6863 /* Read the current link report info */
6864 bnx2x_fill_report_data(sc, &cur_data);
6866 /* Don't report link down or exactly the same link status twice */
6867 if (!memcmp(&cur_data, &sc->last_reported_link, sizeof(cur_data)) ||
6868 (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6869 &sc->last_reported_link.link_report_flags) &&
6870 bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6871 &cur_data.link_report_flags))) {
6877 /* report new link params and remember the state for the next time */
6878 rte_memcpy(&sc->last_reported_link, &cur_data, sizeof(cur_data));
6880 if (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6881 &cur_data.link_report_flags)) {
6882 PMD_DRV_LOG(INFO, "NIC Link is Down");
6884 __rte_unused const char *duplex;
6885 __rte_unused const char *flow;
6887 if (bnx2x_test_and_clear_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6888 &cur_data.link_report_flags)) {
6895 * Handle the FC at the end so that only these flags would be
6896 * possibly set. This way we may easily check if there is no FC
6899 if (cur_data.link_report_flags) {
6900 if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6901 &cur_data.link_report_flags) &&
6902 bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6903 &cur_data.link_report_flags)) {
6904 flow = "ON - receive & transmit";
6905 } else if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6906 &cur_data.link_report_flags) &&
6907 !bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6908 &cur_data.link_report_flags)) {
6909 flow = "ON - receive";
6910 } else if (!bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6911 &cur_data.link_report_flags) &&
6912 bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6913 &cur_data.link_report_flags)) {
6914 flow = "ON - transmit";
6916 flow = "none"; /* possible? */
6923 "NIC Link is Up, %d Mbps %s duplex, Flow control: %s",
6924 cur_data.line_speed, duplex, flow);
6928 void bnx2x_link_status_update(struct bnx2x_softc *sc)
6930 if (sc->state != BNX2X_STATE_OPEN) {
6934 if (IS_PF(sc) && !CHIP_REV_IS_SLOW(sc)) {
6935 elink_link_status_update(&sc->link_params, &sc->link_vars);
6937 sc->port.supported[0] |= (ELINK_SUPPORTED_10baseT_Half |
6938 ELINK_SUPPORTED_10baseT_Full |
6939 ELINK_SUPPORTED_100baseT_Half |
6940 ELINK_SUPPORTED_100baseT_Full |
6941 ELINK_SUPPORTED_1000baseT_Full |
6942 ELINK_SUPPORTED_2500baseX_Full |
6943 ELINK_SUPPORTED_10000baseT_Full |
6944 ELINK_SUPPORTED_TP |
6945 ELINK_SUPPORTED_FIBRE |
6946 ELINK_SUPPORTED_Autoneg |
6947 ELINK_SUPPORTED_Pause |
6948 ELINK_SUPPORTED_Asym_Pause);
6949 sc->port.advertising[0] = sc->port.supported[0];
6951 sc->link_params.sc = sc;
6952 sc->link_params.port = SC_PORT(sc);
6953 sc->link_params.req_duplex[0] = DUPLEX_FULL;
6954 sc->link_params.req_flow_ctrl[0] = ELINK_FLOW_CTRL_NONE;
6955 sc->link_params.req_line_speed[0] = SPEED_10000;
6956 sc->link_params.speed_cap_mask[0] = 0x7f0000;
6957 sc->link_params.switch_cfg = ELINK_SWITCH_CFG_10G;
6959 if (CHIP_REV_IS_FPGA(sc)) {
6960 sc->link_vars.mac_type = ELINK_MAC_TYPE_EMAC;
6961 sc->link_vars.line_speed = ELINK_SPEED_1000;
6962 sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
6963 LINK_STATUS_SPEED_AND_DUPLEX_1000TFD);
6965 sc->link_vars.mac_type = ELINK_MAC_TYPE_BMAC;
6966 sc->link_vars.line_speed = ELINK_SPEED_10000;
6967 sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
6968 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
6971 sc->link_vars.link_up = 1;
6973 sc->link_vars.duplex = DUPLEX_FULL;
6974 sc->link_vars.flow_ctrl = ELINK_FLOW_CTRL_NONE;
6978 NIG_REG_EGRESS_DRAIN0_MODE +
6979 sc->link_params.port * 4, 0);
6980 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
6981 bnx2x_link_report(sc);
6986 if (sc->link_vars.link_up) {
6987 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
6989 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
6991 bnx2x_link_report(sc);
6993 bnx2x_link_report(sc);
6994 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
6998 static int bnx2x_initial_phy_init(struct bnx2x_softc *sc, int load_mode)
7000 int rc, cfg_idx = bnx2x_get_link_cfg_idx(sc);
7001 uint16_t req_line_speed = sc->link_params.req_line_speed[cfg_idx];
7002 struct elink_params *lp = &sc->link_params;
7004 bnx2x_set_requested_fc(sc);
7006 if (load_mode == LOAD_DIAG) {
7007 lp->loopback_mode = ELINK_LOOPBACK_XGXS;
7008 /* Prefer doing PHY loopback at 10G speed, if possible */
7009 if (lp->req_line_speed[cfg_idx] < ELINK_SPEED_10000) {
7010 if (lp->speed_cap_mask[cfg_idx] &
7011 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
7012 lp->req_line_speed[cfg_idx] = ELINK_SPEED_10000;
7014 lp->req_line_speed[cfg_idx] = ELINK_SPEED_1000;
7019 if (load_mode == LOAD_LOOPBACK_EXT) {
7020 lp->loopback_mode = ELINK_LOOPBACK_EXT;
7023 rc = elink_phy_init(&sc->link_params, &sc->link_vars);
7025 bnx2x_calc_fc_adv(sc);
7027 if (sc->link_vars.link_up) {
7028 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7029 bnx2x_link_report(sc);
7032 sc->link_params.req_line_speed[cfg_idx] = req_line_speed;
7036 /* update flags in shmem */
7038 bnx2x_update_drv_flags(struct bnx2x_softc *sc, uint32_t flags, uint32_t set)
7042 if (SHMEM2_HAS(sc, drv_flags)) {
7043 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7044 drv_flags = SHMEM2_RD(sc, drv_flags);
7049 drv_flags &= ~flags;
7052 SHMEM2_WR(sc, drv_flags, drv_flags);
7054 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7058 /* periodic timer callout routine, only runs when the interface is up */
7059 void bnx2x_periodic_callout(struct bnx2x_softc *sc)
7061 if ((sc->state != BNX2X_STATE_OPEN) ||
7062 (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_STOP)) {
7063 PMD_DRV_LOG(WARNING, "periodic callout exit (state=0x%x)",
7067 if (!CHIP_REV_IS_SLOW(sc)) {
7069 * This barrier is needed to ensure the ordering between the writing
7070 * to the sc->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
7075 elink_period_func(&sc->link_params, &sc->link_vars);
7079 if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7080 int mb_idx = SC_FW_MB_IDX(sc);
7084 ++sc->fw_drv_pulse_wr_seq;
7085 sc->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
7087 drv_pulse = sc->fw_drv_pulse_wr_seq;
7088 bnx2x_drv_pulse(sc);
7090 mcp_pulse = (SHMEM_RD(sc, func_mb[mb_idx].mcp_pulse_mb) &
7091 MCP_PULSE_SEQ_MASK);
7094 * The delta between driver pulse and mcp response should
7095 * be 1 (before mcp response) or 0 (after mcp response).
7097 if ((drv_pulse != mcp_pulse) &&
7098 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
7099 /* someone lost a heartbeat... */
7101 "drv_pulse (0x%x) != mcp_pulse (0x%x)",
7102 drv_pulse, mcp_pulse);
7108 /* start the controller */
7109 static __rte_noinline
7110 int bnx2x_nic_load(struct bnx2x_softc *sc)
7113 uint32_t load_code = 0;
7116 PMD_INIT_FUNC_TRACE();
7118 sc->state = BNX2X_STATE_OPENING_WAITING_LOAD;
7121 /* must be called before memory allocation and HW init */
7122 bnx2x_ilt_set_info(sc);
7125 bnx2x_set_fp_rx_buf_size(sc);
7128 if (bnx2x_alloc_mem(sc) != 0) {
7129 sc->state = BNX2X_STATE_CLOSED;
7131 goto bnx2x_nic_load_error0;
7135 if (bnx2x_alloc_fw_stats_mem(sc) != 0) {
7136 sc->state = BNX2X_STATE_CLOSED;
7138 goto bnx2x_nic_load_error0;
7142 rc = bnx2x_vf_init(sc);
7144 sc->state = BNX2X_STATE_ERROR;
7145 goto bnx2x_nic_load_error0;
7150 /* set pf load just before approaching the MCP */
7151 bnx2x_set_pf_load(sc);
7153 /* if MCP exists send load request and analyze response */
7154 if (!BNX2X_NOMCP(sc)) {
7155 /* attempt to load pf */
7156 if (bnx2x_nic_load_request(sc, &load_code) != 0) {
7157 sc->state = BNX2X_STATE_CLOSED;
7159 goto bnx2x_nic_load_error1;
7162 /* what did the MCP say? */
7163 if (bnx2x_nic_load_analyze_req(sc, load_code) != 0) {
7164 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7165 sc->state = BNX2X_STATE_CLOSED;
7167 goto bnx2x_nic_load_error2;
7170 PMD_DRV_LOG(INFO, "Device has no MCP!");
7171 load_code = bnx2x_nic_load_no_mcp(sc);
7174 /* mark PMF if applicable */
7175 bnx2x_nic_load_pmf(sc, load_code);
7177 /* Init Function state controlling object */
7178 bnx2x_init_func_obj(sc);
7181 if (bnx2x_init_hw(sc, load_code) != 0) {
7182 PMD_DRV_LOG(NOTICE, "HW init failed");
7183 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7184 sc->state = BNX2X_STATE_CLOSED;
7186 goto bnx2x_nic_load_error2;
7190 bnx2x_nic_init(sc, load_code);
7192 /* Init per-function objects */
7194 bnx2x_init_objs(sc);
7196 /* set AFEX default VLAN tag to an invalid value */
7197 sc->devinfo.mf_info.afex_def_vlan_tag = -1;
7199 sc->state = BNX2X_STATE_OPENING_WAITING_PORT;
7200 rc = bnx2x_func_start(sc);
7202 PMD_DRV_LOG(NOTICE, "Function start failed!");
7203 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7204 sc->state = BNX2X_STATE_ERROR;
7205 goto bnx2x_nic_load_error3;
7208 /* send LOAD_DONE command to MCP */
7209 if (!BNX2X_NOMCP(sc)) {
7211 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7214 "MCP response failure, aborting");
7215 sc->state = BNX2X_STATE_ERROR;
7217 goto bnx2x_nic_load_error3;
7222 rc = bnx2x_setup_leading(sc);
7224 PMD_DRV_LOG(NOTICE, "Setup leading failed!");
7225 sc->state = BNX2X_STATE_ERROR;
7226 goto bnx2x_nic_load_error3;
7229 FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, i) {
7231 rc = bnx2x_setup_queue(sc, &sc->fp[i], FALSE);
7232 else /* IS_VF(sc) */
7233 rc = bnx2x_vf_setup_queue(sc, &sc->fp[i], FALSE);
7236 PMD_DRV_LOG(NOTICE, "Queue(%d) setup failed", i);
7237 sc->state = BNX2X_STATE_ERROR;
7238 goto bnx2x_nic_load_error3;
7242 rc = bnx2x_init_rss_pf(sc);
7244 PMD_DRV_LOG(NOTICE, "PF RSS init failed");
7245 sc->state = BNX2X_STATE_ERROR;
7246 goto bnx2x_nic_load_error3;
7249 /* now when Clients are configured we are ready to work */
7250 sc->state = BNX2X_STATE_OPEN;
7252 /* Configure a ucast MAC */
7254 rc = bnx2x_set_eth_mac(sc, TRUE);
7255 } else { /* IS_VF(sc) */
7256 rc = bnx2x_vf_set_mac(sc, TRUE);
7260 PMD_DRV_LOG(NOTICE, "Setting Ethernet MAC failed");
7261 sc->state = BNX2X_STATE_ERROR;
7262 goto bnx2x_nic_load_error3;
7266 rc = bnx2x_initial_phy_init(sc, LOAD_OPEN);
7268 sc->state = BNX2X_STATE_ERROR;
7269 goto bnx2x_nic_load_error3;
7273 sc->link_params.feature_config_flags &=
7274 ~ELINK_FEATURE_CONFIG_BOOT_FROM_SAN;
7277 switch (LOAD_OPEN) {
7283 case LOAD_LOOPBACK_EXT:
7284 sc->state = BNX2X_STATE_DIAG;
7292 bnx2x_update_drv_flags(sc, 1 << DRV_FLAGS_PORT_MASK, 0);
7294 bnx2x_link_status_update(sc);
7297 if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
7298 /* mark driver is loaded in shmem2 */
7299 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
7300 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
7302 DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED |
7303 DRV_FLAGS_CAPABILITIES_LOADED_L2));
7306 /* start fast path */
7307 /* Initialize Rx filter */
7308 bnx2x_set_rx_mode(sc);
7310 /* wait for all pending SP commands to complete */
7311 if (IS_PF(sc) && !bnx2x_wait_sp_comp(sc, ~0x0UL)) {
7312 PMD_DRV_LOG(NOTICE, "Timeout waiting for all SPs to complete!");
7313 bnx2x_periodic_stop(sc);
7314 bnx2x_nic_unload(sc, UNLOAD_CLOSE, FALSE);
7318 PMD_DRV_LOG(DEBUG, "NIC successfully loaded");
7322 bnx2x_nic_load_error3:
7325 bnx2x_int_disable_sync(sc, 1);
7327 /* clean out queued objects */
7328 bnx2x_squeeze_objects(sc);
7331 bnx2x_nic_load_error2:
7333 if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7334 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
7335 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
7340 bnx2x_nic_load_error1:
7342 /* clear pf_load status, as it was already set */
7344 bnx2x_clear_pf_load(sc);
7347 bnx2x_nic_load_error0:
7349 bnx2x_free_fw_stats_mem(sc);
7356 * Handles controller initialization.
7358 int bnx2x_init(struct bnx2x_softc *sc)
7360 int other_engine = SC_PATH(sc) ? 0 : 1;
7361 uint8_t other_load_status, load_status;
7362 uint8_t global = FALSE;
7365 /* Check if the driver is still running and bail out if it is. */
7366 if (sc->state != BNX2X_STATE_CLOSED) {
7367 PMD_DRV_LOG(DEBUG, "Init called while driver is running!");
7369 goto bnx2x_init_done;
7372 bnx2x_set_power_state(sc, PCI_PM_D0);
7375 * If parity occurred during the unload, then attentions and/or
7376 * RECOVERY_IN_PROGRESS may still be set. If so we want the first function
7377 * loaded on the current engine to complete the recovery. Parity recovery
7378 * is only relevant for PF driver.
7381 other_load_status = bnx2x_get_load_status(sc, other_engine);
7382 load_status = bnx2x_get_load_status(sc, SC_PATH(sc));
7384 if (!bnx2x_reset_is_done(sc, SC_PATH(sc)) ||
7385 bnx2x_chk_parity_attn(sc, &global, TRUE)) {
7388 * If there are attentions and they are in global blocks, set
7389 * the GLOBAL_RESET bit regardless whether it will be this
7390 * function that will complete the recovery or not.
7393 bnx2x_set_reset_global(sc);
7397 * Only the first function on the current engine should try
7398 * to recover in open. In case of attentions in global blocks
7399 * only the first in the chip should try to recover.
7402 && (!global ||!other_load_status))
7403 && bnx2x_trylock_leader_lock(sc)
7404 && !bnx2x_leader_reset(sc)) {
7406 "Recovered during init");
7410 /* recovery has failed... */
7411 bnx2x_set_power_state(sc, PCI_PM_D3hot);
7413 sc->recovery_state = BNX2X_RECOVERY_FAILED;
7416 "Recovery flow hasn't properly "
7417 "completed yet, try again later. "
7418 "If you still see this message after a "
7419 "few retries then power cycle is required.");
7422 goto bnx2x_init_done;
7427 sc->recovery_state = BNX2X_RECOVERY_DONE;
7429 rc = bnx2x_nic_load(sc);
7434 PMD_DRV_LOG(NOTICE, "Initialization failed, "
7435 "stack notified driver is NOT running!");
7441 static void bnx2x_get_function_num(struct bnx2x_softc *sc)
7446 * Read the ME register to get the function number. The ME register
7447 * holds the relative-function number and absolute-function number. The
7448 * absolute-function number appears only in E2 and above. Before that
7449 * these bits always contained zero, therefore we cannot blindly use them.
7452 val = REG_RD(sc, BAR_ME_REGISTER);
7455 (uint8_t) ((val & ME_REG_PF_NUM) >> ME_REG_PF_NUM_SHIFT);
7457 (uint8_t) ((val & ME_REG_ABS_PF_NUM) >> ME_REG_ABS_PF_NUM_SHIFT) &
7460 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7461 sc->pfunc_abs = ((sc->pfunc_rel << 1) | sc->path_id);
7463 sc->pfunc_abs = (sc->pfunc_rel | sc->path_id);
7467 "Relative function %d, Absolute function %d, Path %d",
7468 sc->pfunc_rel, sc->pfunc_abs, sc->path_id);
7471 static uint32_t bnx2x_get_shmem_mf_cfg_base(struct bnx2x_softc *sc)
7473 uint32_t shmem2_size;
7475 uint32_t mf_cfg_offset_value;
7478 offset = (SHMEM_ADDR(sc, func_mb) +
7479 (MAX_FUNC_NUM * sizeof(struct drv_func_mb)));
7482 if (sc->devinfo.shmem2_base != 0) {
7483 shmem2_size = SHMEM2_RD(sc, size);
7484 if (shmem2_size > offsetof(struct shmem2_region, mf_cfg_addr)) {
7485 mf_cfg_offset_value = SHMEM2_RD(sc, mf_cfg_addr);
7486 if (SHMEM_MF_CFG_ADDR_NONE != mf_cfg_offset_value) {
7487 offset = mf_cfg_offset_value;
7495 static uint32_t bnx2x_pcie_capability_read(struct bnx2x_softc *sc, int reg)
7498 struct bnx2x_pci_cap *caps;
7500 /* ensure PCIe capability is enabled */
7501 caps = pci_find_cap(sc, PCIY_EXPRESS, BNX2X_PCI_CAP);
7503 PMD_DRV_LOG(DEBUG, "Found PCIe capability: "
7504 "id=0x%04X type=0x%04X addr=0x%08X",
7505 caps->id, caps->type, caps->addr);
7506 pci_read(sc, (caps->addr + reg), &ret, 2);
7510 PMD_DRV_LOG(WARNING, "PCIe capability NOT FOUND!!!");
7515 static uint8_t bnx2x_is_pcie_pending(struct bnx2x_softc *sc)
7517 return bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_STA) &
7518 PCIM_EXP_STA_TRANSACTION_PND;
7522 * Walk the PCI capabiites list for the device to find what features are
7523 * supported. These capabilites may be enabled/disabled by firmware so it's
7524 * best to walk the list rather than make assumptions.
7526 static void bnx2x_probe_pci_caps(struct bnx2x_softc *sc)
7528 PMD_INIT_FUNC_TRACE();
7530 struct bnx2x_pci_cap *caps;
7531 uint16_t link_status;
7534 /* check if PCI Power Management is enabled */
7535 caps = pci_find_cap(sc, PCIY_PMG, BNX2X_PCI_CAP);
7537 PMD_DRV_LOG(DEBUG, "Found PM capability: "
7538 "id=0x%04X type=0x%04X addr=0x%08X",
7539 caps->id, caps->type, caps->addr);
7541 sc->devinfo.pcie_cap_flags |= BNX2X_PM_CAPABLE_FLAG;
7542 sc->devinfo.pcie_pm_cap_reg = caps->addr;
7545 link_status = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_LINK_STA);
7547 sc->devinfo.pcie_link_speed = (link_status & PCIM_LINK_STA_SPEED);
7548 sc->devinfo.pcie_link_width =
7549 ((link_status & PCIM_LINK_STA_WIDTH) >> 4);
7551 PMD_DRV_LOG(DEBUG, "PCIe link speed=%d width=%d",
7552 sc->devinfo.pcie_link_speed, sc->devinfo.pcie_link_width);
7554 sc->devinfo.pcie_cap_flags |= BNX2X_PCIE_CAPABLE_FLAG;
7556 /* check if MSI capability is enabled */
7557 caps = pci_find_cap(sc, PCIY_MSI, BNX2X_PCI_CAP);
7559 PMD_DRV_LOG(DEBUG, "Found MSI capability at 0x%04x", reg);
7561 sc->devinfo.pcie_cap_flags |= BNX2X_MSI_CAPABLE_FLAG;
7562 sc->devinfo.pcie_msi_cap_reg = caps->addr;
7565 /* check if MSI-X capability is enabled */
7566 caps = pci_find_cap(sc, PCIY_MSIX, BNX2X_PCI_CAP);
7568 PMD_DRV_LOG(DEBUG, "Found MSI-X capability at 0x%04x", reg);
7570 sc->devinfo.pcie_cap_flags |= BNX2X_MSIX_CAPABLE_FLAG;
7571 sc->devinfo.pcie_msix_cap_reg = caps->addr;
7575 static int bnx2x_get_shmem_mf_cfg_info_sd(struct bnx2x_softc *sc)
7577 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7580 /* get the outer vlan if we're in switch-dependent mode */
7582 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7583 mf_info->ext_id = (uint16_t) val;
7585 mf_info->multi_vnics_mode = 1;
7587 if (!VALID_OVLAN(mf_info->ext_id)) {
7588 PMD_DRV_LOG(NOTICE, "Invalid VLAN (%d)", mf_info->ext_id);
7592 /* get the capabilities */
7593 if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK) ==
7594 FUNC_MF_CFG_PROTOCOL_ISCSI) {
7595 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ISCSI;
7596 } else if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK)
7597 == FUNC_MF_CFG_PROTOCOL_FCOE) {
7598 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_FCOE;
7600 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ETHERNET;
7603 mf_info->vnics_per_port =
7604 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7609 static uint32_t bnx2x_get_shmem_ext_proto_support_flags(struct bnx2x_softc *sc)
7611 uint32_t retval = 0;
7614 val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7616 if (val & MACP_FUNC_CFG_FLAGS_ENABLED) {
7617 if (val & MACP_FUNC_CFG_FLAGS_ETHERNET) {
7618 retval |= MF_PROTO_SUPPORT_ETHERNET;
7620 if (val & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
7621 retval |= MF_PROTO_SUPPORT_ISCSI;
7623 if (val & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
7624 retval |= MF_PROTO_SUPPORT_FCOE;
7631 static int bnx2x_get_shmem_mf_cfg_info_si(struct bnx2x_softc *sc)
7633 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7637 * There is no outer vlan if we're in switch-independent mode.
7638 * If the mac is valid then assume multi-function.
7641 val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7643 mf_info->multi_vnics_mode = ((val & MACP_FUNC_CFG_FLAGS_MASK) != 0);
7645 mf_info->mf_protos_supported =
7646 bnx2x_get_shmem_ext_proto_support_flags(sc);
7648 mf_info->vnics_per_port =
7649 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7654 static int bnx2x_get_shmem_mf_cfg_info_niv(struct bnx2x_softc *sc)
7656 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7658 uint32_t func_config;
7659 uint32_t niv_config;
7661 mf_info->multi_vnics_mode = 1;
7663 e1hov_tag = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7664 func_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7665 niv_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].afex_config);
7668 (uint16_t) ((e1hov_tag & FUNC_MF_CFG_E1HOV_TAG_MASK) >>
7669 FUNC_MF_CFG_E1HOV_TAG_SHIFT);
7671 mf_info->default_vlan =
7672 (uint16_t) ((e1hov_tag & FUNC_MF_CFG_AFEX_VLAN_MASK) >>
7673 FUNC_MF_CFG_AFEX_VLAN_SHIFT);
7675 mf_info->niv_allowed_priorities =
7676 (uint8_t) ((niv_config & FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
7677 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT);
7679 mf_info->niv_default_cos =
7680 (uint8_t) ((func_config & FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
7681 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT);
7683 mf_info->afex_vlan_mode =
7684 ((niv_config & FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
7685 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT);
7687 mf_info->niv_mba_enabled =
7688 ((niv_config & FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK) >>
7689 FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT);
7691 mf_info->mf_protos_supported =
7692 bnx2x_get_shmem_ext_proto_support_flags(sc);
7694 mf_info->vnics_per_port =
7695 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7700 static int bnx2x_check_valid_mf_cfg(struct bnx2x_softc *sc)
7702 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7709 /* various MF mode sanity checks... */
7711 if (mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_HIDE) {
7713 "Enumerated function %d is marked as hidden",
7718 if ((mf_info->vnics_per_port > 1) && !mf_info->multi_vnics_mode) {
7719 PMD_DRV_LOG(NOTICE, "vnics_per_port=%d multi_vnics_mode=%d",
7720 mf_info->vnics_per_port, mf_info->multi_vnics_mode);
7724 if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7725 /* vnic id > 0 must have valid ovlan in switch-dependent mode */
7726 if ((SC_VN(sc) > 0) && !VALID_OVLAN(OVLAN(sc))) {
7727 PMD_DRV_LOG(NOTICE, "mf_mode=SD vnic_id=%d ovlan=%d",
7728 SC_VN(sc), OVLAN(sc));
7732 if (!VALID_OVLAN(OVLAN(sc)) && mf_info->multi_vnics_mode) {
7734 "mf_mode=SD multi_vnics_mode=%d ovlan=%d",
7735 mf_info->multi_vnics_mode, OVLAN(sc));
7740 * Verify all functions are either MF or SF mode. If MF, make sure
7741 * sure that all non-hidden functions have a valid ovlan. If SF,
7742 * make sure that all non-hidden functions have an invalid ovlan.
7744 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7745 mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7746 ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7747 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE) &&
7748 (((mf_info->multi_vnics_mode)
7749 && !VALID_OVLAN(ovlan1))
7750 || ((!mf_info->multi_vnics_mode)
7751 && VALID_OVLAN(ovlan1)))) {
7753 "mf_mode=SD function %d MF config "
7754 "mismatch, multi_vnics_mode=%d ovlan=%d",
7755 i, mf_info->multi_vnics_mode,
7761 /* Verify all funcs on the same port each have a different ovlan. */
7762 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7763 mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7764 ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7765 /* iterate from the next function on the port to the max func */
7766 for (j = i + 2; j < MAX_FUNC_NUM; j += 2) {
7768 MFCFG_RD(sc, func_mf_config[j].config);
7770 MFCFG_RD(sc, func_mf_config[j].e1hov_tag);
7771 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE)
7772 && VALID_OVLAN(ovlan1)
7773 && !(mf_cfg2 & FUNC_MF_CFG_FUNC_HIDE)
7774 && VALID_OVLAN(ovlan2)
7775 && (ovlan1 == ovlan2)) {
7777 "mf_mode=SD functions %d and %d "
7778 "have the same ovlan (%d)",
7785 /* MULTI_FUNCTION_SD */
7789 static int bnx2x_get_mf_cfg_info(struct bnx2x_softc *sc)
7791 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7792 uint32_t val, mac_upper;
7795 /* initialize mf_info defaults */
7796 mf_info->vnics_per_port = 1;
7797 mf_info->multi_vnics_mode = FALSE;
7798 mf_info->path_has_ovlan = FALSE;
7799 mf_info->mf_mode = SINGLE_FUNCTION;
7801 if (!CHIP_IS_MF_CAP(sc)) {
7805 if (sc->devinfo.mf_cfg_base == SHMEM_MF_CFG_ADDR_NONE) {
7806 PMD_DRV_LOG(NOTICE, "Invalid mf_cfg_base!");
7810 /* get the MF mode (switch dependent / independent / single-function) */
7812 val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
7814 switch (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK) {
7815 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
7818 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7820 /* check for legal upper mac bytes */
7821 if (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT) {
7822 mf_info->mf_mode = MULTI_FUNCTION_SI;
7825 "Invalid config for Switch Independent mode");
7830 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
7831 case SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4:
7833 /* get outer vlan configuration */
7834 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7836 if ((val & FUNC_MF_CFG_E1HOV_TAG_MASK) !=
7837 FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
7838 mf_info->mf_mode = MULTI_FUNCTION_SD;
7841 "Invalid config for Switch Dependent mode");
7846 case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
7848 /* not in MF mode, vnics_per_port=1 and multi_vnics_mode=FALSE */
7851 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
7854 * Mark MF mode as NIV if MCP version includes NPAR-SD support
7855 * and the MAC address is valid.
7858 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7860 if ((SHMEM2_HAS(sc, afex_driver_support)) &&
7861 (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT)) {
7862 mf_info->mf_mode = MULTI_FUNCTION_AFEX;
7864 PMD_DRV_LOG(NOTICE, "Invalid config for AFEX mode");
7871 PMD_DRV_LOG(NOTICE, "Unknown MF mode (0x%08x)",
7872 (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK));
7877 /* set path mf_mode (which could be different than function mf_mode) */
7878 if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7879 mf_info->path_has_ovlan = TRUE;
7880 } else if (mf_info->mf_mode == SINGLE_FUNCTION) {
7882 * Decide on path multi vnics mode. If we're not in MF mode and in
7883 * 4-port mode, this is good enough to check vnic-0 of the other port
7886 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7887 uint8_t other_port = !(PORT_ID(sc) & 1);
7888 uint8_t abs_func_other_port =
7889 (SC_PATH(sc) + (2 * other_port));
7894 [abs_func_other_port].e1hov_tag);
7896 mf_info->path_has_ovlan = VALID_OVLAN((uint16_t) val);
7900 if (mf_info->mf_mode == SINGLE_FUNCTION) {
7901 /* invalid MF config */
7902 if (SC_VN(sc) >= 1) {
7903 PMD_DRV_LOG(NOTICE, "VNIC ID >= 1 in SF mode");
7910 /* get the MF configuration */
7911 mf_info->mf_config[SC_VN(sc)] =
7912 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7914 switch (mf_info->mf_mode) {
7915 case MULTI_FUNCTION_SD:
7917 bnx2x_get_shmem_mf_cfg_info_sd(sc);
7920 case MULTI_FUNCTION_SI:
7922 bnx2x_get_shmem_mf_cfg_info_si(sc);
7925 case MULTI_FUNCTION_AFEX:
7927 bnx2x_get_shmem_mf_cfg_info_niv(sc);
7932 PMD_DRV_LOG(NOTICE, "Get MF config failed (mf_mode=0x%08x)",
7937 /* get the congestion management parameters */
7940 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7941 /* get min/max bw */
7942 val = MFCFG_RD(sc, func_mf_config[i].config);
7943 mf_info->min_bw[vnic] =
7944 ((val & FUNC_MF_CFG_MIN_BW_MASK) >>
7945 FUNC_MF_CFG_MIN_BW_SHIFT);
7946 mf_info->max_bw[vnic] =
7947 ((val & FUNC_MF_CFG_MAX_BW_MASK) >>
7948 FUNC_MF_CFG_MAX_BW_SHIFT);
7952 return bnx2x_check_valid_mf_cfg(sc);
7955 static int bnx2x_get_shmem_info(struct bnx2x_softc *sc)
7958 uint32_t mac_hi, mac_lo, val;
7960 PMD_INIT_FUNC_TRACE();
7963 mac_hi = mac_lo = 0;
7965 sc->link_params.sc = sc;
7966 sc->link_params.port = port;
7968 /* get the hardware config info */
7969 sc->devinfo.hw_config = SHMEM_RD(sc, dev_info.shared_hw_config.config);
7970 sc->devinfo.hw_config2 =
7971 SHMEM_RD(sc, dev_info.shared_hw_config.config2);
7973 sc->link_params.hw_led_mode =
7974 ((sc->devinfo.hw_config & SHARED_HW_CFG_LED_MODE_MASK) >>
7975 SHARED_HW_CFG_LED_MODE_SHIFT);
7977 /* get the port feature config */
7979 SHMEM_RD(sc, dev_info.port_feature_config[port].config);
7981 /* get the link params */
7982 sc->link_params.speed_cap_mask[ELINK_INT_PHY] =
7983 SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask)
7984 & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
7985 sc->link_params.speed_cap_mask[ELINK_EXT_PHY1] =
7986 SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask2)
7987 & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
7989 /* get the lane config */
7990 sc->link_params.lane_config =
7991 SHMEM_RD(sc, dev_info.port_hw_config[port].lane_config);
7993 /* get the link config */
7994 val = SHMEM_RD(sc, dev_info.port_feature_config[port].link_config);
7995 sc->port.link_config[ELINK_INT_PHY] = val;
7996 sc->link_params.switch_cfg = (val & PORT_FEATURE_CONNECTED_SWITCH_MASK);
7997 sc->port.link_config[ELINK_EXT_PHY1] =
7998 SHMEM_RD(sc, dev_info.port_feature_config[port].link_config2);
8000 /* get the override preemphasis flag and enable it or turn it off */
8001 val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
8002 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) {
8003 sc->link_params.feature_config_flags |=
8004 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8006 sc->link_params.feature_config_flags &=
8007 ~ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8010 /* get the initial value of the link params */
8011 sc->link_params.multi_phy_config =
8012 SHMEM_RD(sc, dev_info.port_hw_config[port].multi_phy_config);
8014 /* get external phy info */
8015 sc->port.ext_phy_config =
8016 SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
8018 /* get the multifunction configuration */
8019 bnx2x_get_mf_cfg_info(sc);
8021 /* get the mac address */
8024 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
8026 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_lower);
8028 mac_hi = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_upper);
8029 mac_lo = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_lower);
8032 if ((mac_lo == 0) && (mac_hi == 0)) {
8033 *sc->mac_addr_str = 0;
8034 PMD_DRV_LOG(NOTICE, "No Ethernet address programmed!");
8036 sc->link_params.mac_addr[0] = (uint8_t) (mac_hi >> 8);
8037 sc->link_params.mac_addr[1] = (uint8_t) (mac_hi);
8038 sc->link_params.mac_addr[2] = (uint8_t) (mac_lo >> 24);
8039 sc->link_params.mac_addr[3] = (uint8_t) (mac_lo >> 16);
8040 sc->link_params.mac_addr[4] = (uint8_t) (mac_lo >> 8);
8041 sc->link_params.mac_addr[5] = (uint8_t) (mac_lo);
8042 snprintf(sc->mac_addr_str, sizeof(sc->mac_addr_str),
8043 "%02x:%02x:%02x:%02x:%02x:%02x",
8044 sc->link_params.mac_addr[0],
8045 sc->link_params.mac_addr[1],
8046 sc->link_params.mac_addr[2],
8047 sc->link_params.mac_addr[3],
8048 sc->link_params.mac_addr[4],
8049 sc->link_params.mac_addr[5]);
8050 PMD_DRV_LOG(DEBUG, "Ethernet address: %s", sc->mac_addr_str);
8056 static void bnx2x_media_detect(struct bnx2x_softc *sc)
8058 uint32_t phy_idx = bnx2x_get_cur_phy_idx(sc);
8059 switch (sc->link_params.phy[phy_idx].media_type) {
8060 case ELINK_ETH_PHY_SFPP_10G_FIBER:
8061 case ELINK_ETH_PHY_SFP_1G_FIBER:
8062 case ELINK_ETH_PHY_XFP_FIBER:
8063 case ELINK_ETH_PHY_KR:
8064 case ELINK_ETH_PHY_CX4:
8065 PMD_DRV_LOG(INFO, "Found 10GBase-CX4 media.");
8066 sc->media = IFM_10G_CX4;
8068 case ELINK_ETH_PHY_DA_TWINAX:
8069 PMD_DRV_LOG(INFO, "Found 10Gb Twinax media.");
8070 sc->media = IFM_10G_TWINAX;
8072 case ELINK_ETH_PHY_BASE_T:
8073 PMD_DRV_LOG(INFO, "Found 10GBase-T media.");
8074 sc->media = IFM_10G_T;
8076 case ELINK_ETH_PHY_NOT_PRESENT:
8077 PMD_DRV_LOG(INFO, "Media not present.");
8080 case ELINK_ETH_PHY_UNSPECIFIED:
8082 PMD_DRV_LOG(INFO, "Unknown media!");
8088 #define GET_FIELD(value, fname) \
8089 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
8090 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
8091 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
8093 static int bnx2x_get_igu_cam_info(struct bnx2x_softc *sc)
8095 int pfid = SC_FUNC(sc);
8098 uint8_t fid, igu_sb_cnt = 0;
8100 sc->igu_base_sb = 0xff;
8102 if (CHIP_INT_MODE_IS_BC(sc)) {
8104 igu_sb_cnt = sc->igu_sb_cnt;
8105 sc->igu_base_sb = ((CHIP_IS_MODE_4_PORT(sc) ? pfid : vn) *
8107 sc->igu_dsb_id = (E1HVN_MAX * FP_SB_MAX_E1x +
8108 (CHIP_IS_MODE_4_PORT(sc) ? pfid : vn));
8112 /* IGU in normal mode - read CAM */
8114 igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; igu_sb_id++) {
8115 val = REG_RD(sc, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
8116 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) {
8120 if (fid & IGU_FID_ENCODE_IS_PF) {
8121 if ((fid & IGU_FID_PF_NUM_MASK) != pfid) {
8124 if (IGU_VEC(val) == 0) {
8125 /* default status block */
8126 sc->igu_dsb_id = igu_sb_id;
8128 if (sc->igu_base_sb == 0xff) {
8129 sc->igu_base_sb = igu_sb_id;
8137 * Due to new PF resource allocation by MFW T7.4 and above, it's optional
8138 * that number of CAM entries will not be equal to the value advertised in
8139 * PCI. Driver should use the minimal value of both as the actual status
8142 sc->igu_sb_cnt = min(sc->igu_sb_cnt, igu_sb_cnt);
8144 if (igu_sb_cnt == 0) {
8145 PMD_DRV_LOG(ERR, "CAM configuration error");
8153 * Gather various information from the device config space, the device itself,
8154 * shmem, and the user input.
8156 static int bnx2x_get_device_info(struct bnx2x_softc *sc)
8161 /* get the chip revision (chip metal comes from pci config space) */
8162 sc->devinfo.chip_id = sc->link_params.chip_id =
8163 (((REG_RD(sc, MISC_REG_CHIP_NUM) & 0xffff) << 16) |
8164 ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12) |
8165 (((REG_RD(sc, PCICFG_OFFSET + PCI_ID_VAL3) >> 24) & 0xf) << 4) |
8166 ((REG_RD(sc, MISC_REG_BOND_ID) & 0xf) << 0));
8168 /* force 57811 according to MISC register */
8169 if (REG_RD(sc, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
8170 if (CHIP_IS_57810(sc)) {
8171 sc->devinfo.chip_id = ((CHIP_NUM_57811 << 16) |
8173 devinfo.chip_id & 0x0000ffff));
8174 } else if (CHIP_IS_57810_MF(sc)) {
8175 sc->devinfo.chip_id = ((CHIP_NUM_57811_MF << 16) |
8177 devinfo.chip_id & 0x0000ffff));
8179 sc->devinfo.chip_id |= 0x1;
8183 "chip_id=0x%08x (num=0x%04x rev=0x%01x metal=0x%02x bond=0x%01x)",
8184 sc->devinfo.chip_id,
8185 ((sc->devinfo.chip_id >> 16) & 0xffff),
8186 ((sc->devinfo.chip_id >> 12) & 0xf),
8187 ((sc->devinfo.chip_id >> 4) & 0xff),
8188 ((sc->devinfo.chip_id >> 0) & 0xf));
8190 val = (REG_RD(sc, 0x2874) & 0x55);
8191 if ((sc->devinfo.chip_id & 0x1) || (CHIP_IS_E1H(sc) && (val == 0x55))) {
8192 sc->flags |= BNX2X_ONE_PORT_FLAG;
8193 PMD_DRV_LOG(DEBUG, "single port device");
8196 /* set the doorbell size */
8197 sc->doorbell_size = (1 << BNX2X_DB_SHIFT);
8199 /* determine whether the device is in 2 port or 4 port mode */
8200 sc->devinfo.chip_port_mode = CHIP_PORT_MODE_NONE; /* E1h */
8201 if (CHIP_IS_E2E3(sc)) {
8203 * Read port4mode_en_ovwr[0]:
8204 * If 1, four port mode is in port4mode_en_ovwr[1].
8205 * If 0, four port mode is in port4mode_en[0].
8207 val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);
8209 val = ((val >> 1) & 1);
8211 val = REG_RD(sc, MISC_REG_PORT4MODE_EN);
8214 sc->devinfo.chip_port_mode =
8215 (val) ? CHIP_4_PORT_MODE : CHIP_2_PORT_MODE;
8217 PMD_DRV_LOG(DEBUG, "Port mode = %s", (val) ? "4" : "2");
8220 /* get the function and path info for the device */
8221 bnx2x_get_function_num(sc);
8223 /* get the shared memory base address */
8224 sc->devinfo.shmem_base =
8225 sc->link_params.shmem_base = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
8226 sc->devinfo.shmem2_base =
8227 REG_RD(sc, (SC_PATH(sc) ? MISC_REG_GENERIC_CR_1 :
8228 MISC_REG_GENERIC_CR_0));
8230 if (!sc->devinfo.shmem_base) {
8231 /* this should ONLY prevent upcoming shmem reads */
8232 PMD_DRV_LOG(INFO, "MCP not active");
8233 sc->flags |= BNX2X_NO_MCP_FLAG;
8237 /* make sure the shared memory contents are valid */
8238 val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
8239 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) !=
8240 (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) {
8241 PMD_DRV_LOG(NOTICE, "Invalid SHMEM validity signature: 0x%08x",
8246 /* get the bootcode version */
8247 sc->devinfo.bc_ver = SHMEM_RD(sc, dev_info.bc_rev);
8248 snprintf(sc->devinfo.bc_ver_str,
8249 sizeof(sc->devinfo.bc_ver_str),
8251 ((sc->devinfo.bc_ver >> 24) & 0xff),
8252 ((sc->devinfo.bc_ver >> 16) & 0xff),
8253 ((sc->devinfo.bc_ver >> 8) & 0xff));
8254 PMD_DRV_LOG(INFO, "Bootcode version: %s", sc->devinfo.bc_ver_str);
8256 /* get the bootcode shmem address */
8257 sc->devinfo.mf_cfg_base = bnx2x_get_shmem_mf_cfg_base(sc);
8259 /* clean indirect addresses as they're not used */
8260 pci_write_long(sc, PCICFG_GRC_ADDRESS, 0);
8262 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F0, 0);
8263 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F0, 0);
8264 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F0, 0);
8265 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F0, 0);
8266 if (CHIP_IS_E1x(sc)) {
8267 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F1, 0);
8268 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F1, 0);
8269 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F1, 0);
8270 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F1, 0);
8274 /* get the nvram size */
8275 val = REG_RD(sc, MCP_REG_MCPR_NVM_CFG4);
8276 sc->devinfo.flash_size =
8277 (NVRAM_1MB_SIZE << (val & MCPR_NVM_CFG4_FLASH_SIZE));
8279 bnx2x_set_power_state(sc, PCI_PM_D0);
8280 /* get various configuration parameters from shmem */
8281 bnx2x_get_shmem_info(sc);
8283 /* initialize IGU parameters */
8284 if (CHIP_IS_E1x(sc)) {
8285 sc->devinfo.int_block = INT_BLOCK_HC;
8286 sc->igu_dsb_id = DEF_SB_IGU_ID;
8287 sc->igu_base_sb = 0;
8289 sc->devinfo.int_block = INT_BLOCK_IGU;
8291 /* do not allow device reset during IGU info preocessing */
8292 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8294 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
8296 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8299 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
8300 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION, val);
8301 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x7f);
8303 while (tout && REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8308 if (REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8310 "FORCING IGU Normal Mode failed!!!");
8311 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8316 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8317 PMD_DRV_LOG(DEBUG, "IGU Backward Compatible Mode");
8318 sc->devinfo.int_block |= INT_BLOCK_MODE_BW_COMP;
8320 PMD_DRV_LOG(DEBUG, "IGU Normal Mode");
8323 rc = bnx2x_get_igu_cam_info(sc);
8325 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8333 * Get base FW non-default (fast path) status block ID. This value is
8334 * used to initialize the fw_sb_id saved on the fp/queue structure to
8335 * determine the id used by the FW.
8337 if (CHIP_IS_E1x(sc)) {
8339 ((SC_PORT(sc) * FP_SB_MAX_E1x) + SC_L_ID(sc));
8342 * 57712+ - We currently use one FW SB per IGU SB (Rx and Tx of
8343 * the same queue are indicated on the same IGU SB). So we prefer
8344 * FW and IGU SBs to be the same value.
8346 sc->base_fw_ndsb = sc->igu_base_sb;
8349 elink_phy_probe(&sc->link_params);
8355 bnx2x_link_settings_supported(struct bnx2x_softc *sc, uint32_t switch_cfg)
8357 uint32_t cfg_size = 0;
8359 uint8_t port = SC_PORT(sc);
8361 /* aggregation of supported attributes of all external phys */
8362 sc->port.supported[0] = 0;
8363 sc->port.supported[1] = 0;
8365 switch (sc->link_params.num_phys) {
8367 sc->port.supported[0] =
8368 sc->link_params.phy[ELINK_INT_PHY].supported;
8372 sc->port.supported[0] =
8373 sc->link_params.phy[ELINK_EXT_PHY1].supported;
8377 if (sc->link_params.multi_phy_config &
8378 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
8379 sc->port.supported[1] =
8380 sc->link_params.phy[ELINK_EXT_PHY1].supported;
8381 sc->port.supported[0] =
8382 sc->link_params.phy[ELINK_EXT_PHY2].supported;
8384 sc->port.supported[0] =
8385 sc->link_params.phy[ELINK_EXT_PHY1].supported;
8386 sc->port.supported[1] =
8387 sc->link_params.phy[ELINK_EXT_PHY2].supported;
8393 if (!(sc->port.supported[0] || sc->port.supported[1])) {
8395 "Invalid phy config in NVRAM (PHY1=0x%08x PHY2=0x%08x)",
8397 dev_info.port_hw_config
8398 [port].external_phy_config),
8400 dev_info.port_hw_config
8401 [port].external_phy_config2));
8406 sc->port.phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR);
8408 switch (switch_cfg) {
8409 case ELINK_SWITCH_CFG_1G:
8412 NIG_REG_SERDES0_CTRL_PHY_ADDR + port * 0x10);
8414 case ELINK_SWITCH_CFG_10G:
8417 NIG_REG_XGXS0_CTRL_PHY_ADDR + port * 0x18);
8421 "Invalid switch config in"
8422 "link_config=0x%08x",
8423 sc->port.link_config[0]);
8428 PMD_DRV_LOG(INFO, "PHY addr 0x%08x", sc->port.phy_addr);
8430 /* mask what we support according to speed_cap_mask per configuration */
8431 for (idx = 0; idx < cfg_size; idx++) {
8432 if (!(sc->link_params.speed_cap_mask[idx] &
8433 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) {
8434 sc->port.supported[idx] &=
8435 ~ELINK_SUPPORTED_10baseT_Half;
8438 if (!(sc->link_params.speed_cap_mask[idx] &
8439 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) {
8440 sc->port.supported[idx] &=
8441 ~ELINK_SUPPORTED_10baseT_Full;
8444 if (!(sc->link_params.speed_cap_mask[idx] &
8445 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) {
8446 sc->port.supported[idx] &=
8447 ~ELINK_SUPPORTED_100baseT_Half;
8450 if (!(sc->link_params.speed_cap_mask[idx] &
8451 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) {
8452 sc->port.supported[idx] &=
8453 ~ELINK_SUPPORTED_100baseT_Full;
8456 if (!(sc->link_params.speed_cap_mask[idx] &
8457 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) {
8458 sc->port.supported[idx] &=
8459 ~ELINK_SUPPORTED_1000baseT_Full;
8462 if (!(sc->link_params.speed_cap_mask[idx] &
8463 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) {
8464 sc->port.supported[idx] &=
8465 ~ELINK_SUPPORTED_2500baseX_Full;
8468 if (!(sc->link_params.speed_cap_mask[idx] &
8469 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8470 sc->port.supported[idx] &=
8471 ~ELINK_SUPPORTED_10000baseT_Full;
8474 if (!(sc->link_params.speed_cap_mask[idx] &
8475 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) {
8476 sc->port.supported[idx] &=
8477 ~ELINK_SUPPORTED_20000baseKR2_Full;
8481 PMD_DRV_LOG(INFO, "PHY supported 0=0x%08x 1=0x%08x",
8482 sc->port.supported[0], sc->port.supported[1]);
8485 static void bnx2x_link_settings_requested(struct bnx2x_softc *sc)
8487 uint32_t link_config;
8489 uint32_t cfg_size = 0;
8491 sc->port.advertising[0] = 0;
8492 sc->port.advertising[1] = 0;
8494 switch (sc->link_params.num_phys) {
8504 for (idx = 0; idx < cfg_size; idx++) {
8505 sc->link_params.req_duplex[idx] = DUPLEX_FULL;
8506 link_config = sc->port.link_config[idx];
8508 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
8509 case PORT_FEATURE_LINK_SPEED_AUTO:
8510 if (sc->port.supported[idx] & ELINK_SUPPORTED_Autoneg) {
8511 sc->link_params.req_line_speed[idx] =
8512 ELINK_SPEED_AUTO_NEG;
8513 sc->port.advertising[idx] |=
8514 sc->port.supported[idx];
8515 if (sc->link_params.phy[ELINK_EXT_PHY1].type ==
8516 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833)
8517 sc->port.advertising[idx] |=
8518 (ELINK_SUPPORTED_100baseT_Half |
8519 ELINK_SUPPORTED_100baseT_Full);
8521 /* force 10G, no AN */
8522 sc->link_params.req_line_speed[idx] =
8524 sc->port.advertising[idx] |=
8525 (ADVERTISED_10000baseT_Full |
8531 case PORT_FEATURE_LINK_SPEED_10M_FULL:
8533 port.supported[idx] & ELINK_SUPPORTED_10baseT_Full)
8535 sc->link_params.req_line_speed[idx] =
8537 sc->port.advertising[idx] |=
8538 (ADVERTISED_10baseT_Full | ADVERTISED_TP);
8541 "Invalid NVRAM config link_config=0x%08x "
8542 "speed_cap_mask=0x%08x",
8545 link_params.speed_cap_mask[idx]);
8550 case PORT_FEATURE_LINK_SPEED_10M_HALF:
8552 port.supported[idx] & ELINK_SUPPORTED_10baseT_Half)
8554 sc->link_params.req_line_speed[idx] =
8556 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8557 sc->port.advertising[idx] |=
8558 (ADVERTISED_10baseT_Half | ADVERTISED_TP);
8561 "Invalid NVRAM config link_config=0x%08x "
8562 "speed_cap_mask=0x%08x",
8565 link_params.speed_cap_mask[idx]);
8570 case PORT_FEATURE_LINK_SPEED_100M_FULL:
8572 port.supported[idx] & ELINK_SUPPORTED_100baseT_Full)
8574 sc->link_params.req_line_speed[idx] =
8576 sc->port.advertising[idx] |=
8577 (ADVERTISED_100baseT_Full | ADVERTISED_TP);
8580 "Invalid NVRAM config link_config=0x%08x "
8581 "speed_cap_mask=0x%08x",
8584 link_params.speed_cap_mask[idx]);
8589 case PORT_FEATURE_LINK_SPEED_100M_HALF:
8591 port.supported[idx] & ELINK_SUPPORTED_100baseT_Half)
8593 sc->link_params.req_line_speed[idx] =
8595 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8596 sc->port.advertising[idx] |=
8597 (ADVERTISED_100baseT_Half | ADVERTISED_TP);
8600 "Invalid NVRAM config link_config=0x%08x "
8601 "speed_cap_mask=0x%08x",
8604 link_params.speed_cap_mask[idx]);
8609 case PORT_FEATURE_LINK_SPEED_1G:
8610 if (sc->port.supported[idx] &
8611 ELINK_SUPPORTED_1000baseT_Full) {
8612 sc->link_params.req_line_speed[idx] =
8614 sc->port.advertising[idx] |=
8615 (ADVERTISED_1000baseT_Full | ADVERTISED_TP);
8618 "Invalid NVRAM config link_config=0x%08x "
8619 "speed_cap_mask=0x%08x",
8622 link_params.speed_cap_mask[idx]);
8627 case PORT_FEATURE_LINK_SPEED_2_5G:
8628 if (sc->port.supported[idx] &
8629 ELINK_SUPPORTED_2500baseX_Full) {
8630 sc->link_params.req_line_speed[idx] =
8632 sc->port.advertising[idx] |=
8633 (ADVERTISED_2500baseX_Full | ADVERTISED_TP);
8636 "Invalid NVRAM config link_config=0x%08x "
8637 "speed_cap_mask=0x%08x",
8640 link_params.speed_cap_mask[idx]);
8645 case PORT_FEATURE_LINK_SPEED_10G_CX4:
8646 if (sc->port.supported[idx] &
8647 ELINK_SUPPORTED_10000baseT_Full) {
8648 sc->link_params.req_line_speed[idx] =
8650 sc->port.advertising[idx] |=
8651 (ADVERTISED_10000baseT_Full |
8655 "Invalid NVRAM config link_config=0x%08x "
8656 "speed_cap_mask=0x%08x",
8659 link_params.speed_cap_mask[idx]);
8664 case PORT_FEATURE_LINK_SPEED_20G:
8665 sc->link_params.req_line_speed[idx] = ELINK_SPEED_20000;
8670 "Invalid NVRAM config link_config=0x%08x "
8671 "speed_cap_mask=0x%08x", link_config,
8672 sc->link_params.speed_cap_mask[idx]);
8673 sc->link_params.req_line_speed[idx] =
8674 ELINK_SPEED_AUTO_NEG;
8675 sc->port.advertising[idx] = sc->port.supported[idx];
8679 sc->link_params.req_flow_ctrl[idx] =
8680 (link_config & PORT_FEATURE_FLOW_CONTROL_MASK);
8682 if (sc->link_params.req_flow_ctrl[idx] == ELINK_FLOW_CTRL_AUTO) {
8685 port.supported[idx] & ELINK_SUPPORTED_Autoneg)) {
8686 sc->link_params.req_flow_ctrl[idx] =
8687 ELINK_FLOW_CTRL_NONE;
8689 bnx2x_set_requested_fc(sc);
8695 static void bnx2x_get_phy_info(struct bnx2x_softc *sc)
8697 uint8_t port = SC_PORT(sc);
8700 PMD_INIT_FUNC_TRACE();
8702 /* shmem data already read in bnx2x_get_shmem_info() */
8704 bnx2x_link_settings_supported(sc, sc->link_params.switch_cfg);
8705 bnx2x_link_settings_requested(sc);
8707 /* configure link feature according to nvram value */
8709 (((SHMEM_RD(sc, dev_info.port_feature_config[port].eee_power_mode))
8710 & PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
8711 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
8712 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
8713 sc->link_params.eee_mode = (ELINK_EEE_MODE_ADV_LPI |
8714 ELINK_EEE_MODE_ENABLE_LPI |
8715 ELINK_EEE_MODE_OUTPUT_TIME);
8717 sc->link_params.eee_mode = 0;
8720 /* get the media type */
8721 bnx2x_media_detect(sc);
8724 static void bnx2x_set_modes_bitmap(struct bnx2x_softc *sc)
8726 uint32_t flags = MODE_ASIC | MODE_PORT2;
8728 if (CHIP_IS_E2(sc)) {
8730 } else if (CHIP_IS_E3(sc)) {
8732 if (CHIP_REV(sc) == CHIP_REV_Ax) {
8733 flags |= MODE_E3_A0;
8734 } else { /*if (CHIP_REV(sc) == CHIP_REV_Bx) */
8736 flags |= MODE_E3_B0 | MODE_COS3;
8742 switch (sc->devinfo.mf_info.mf_mode) {
8743 case MULTI_FUNCTION_SD:
8744 flags |= MODE_MF_SD;
8746 case MULTI_FUNCTION_SI:
8747 flags |= MODE_MF_SI;
8749 case MULTI_FUNCTION_AFEX:
8750 flags |= MODE_MF_AFEX;
8757 #if defined(__LITTLE_ENDIAN)
8758 flags |= MODE_LITTLE_ENDIAN;
8759 #else /* __BIG_ENDIAN */
8760 flags |= MODE_BIG_ENDIAN;
8763 INIT_MODE_FLAGS(sc) = flags;
8766 int bnx2x_alloc_hsi_mem(struct bnx2x_softc *sc)
8768 struct bnx2x_fastpath *fp;
8773 /************************/
8774 /* DEFAULT STATUS BLOCK */
8775 /************************/
8777 if (bnx2x_dma_alloc(sc, sizeof(struct host_sp_status_block),
8778 &sc->def_sb_dma, "def_sb",
8779 RTE_CACHE_LINE_SIZE) != 0) {
8784 (struct host_sp_status_block *)sc->def_sb_dma.vaddr;
8789 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8790 &sc->eq_dma, "ev_queue",
8791 RTE_CACHE_LINE_SIZE) != 0) {
8796 sc->eq = (union event_ring_elem *)sc->eq_dma.vaddr;
8802 if (bnx2x_dma_alloc(sc, sizeof(struct bnx2x_slowpath),
8804 RTE_CACHE_LINE_SIZE) != 0) {
8810 sc->sp = (struct bnx2x_slowpath *)sc->sp_dma.vaddr;
8812 /*******************/
8813 /* SLOW PATH QUEUE */
8814 /*******************/
8816 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8817 &sc->spq_dma, "sp_queue",
8818 RTE_CACHE_LINE_SIZE) != 0) {
8825 sc->spq = (struct eth_spe *)sc->spq_dma.vaddr;
8827 /***************************/
8828 /* FW DECOMPRESSION BUFFER */
8829 /***************************/
8831 if (bnx2x_dma_alloc(sc, FW_BUF_SIZE, &sc->gz_buf_dma,
8832 "fw_buf", RTE_CACHE_LINE_SIZE) != 0) {
8840 sc->gz_buf = (void *)sc->gz_buf_dma.vaddr;
8847 /* allocate DMA memory for each fastpath structure */
8848 for (i = 0; i < sc->num_queues; i++) {
8853 /*******************/
8854 /* FP STATUS BLOCK */
8855 /*******************/
8857 snprintf(buf, sizeof(buf), "fp_%d_sb", i);
8858 if (bnx2x_dma_alloc(sc, sizeof(union bnx2x_host_hc_status_block),
8859 &fp->sb_dma, buf, RTE_CACHE_LINE_SIZE) != 0) {
8860 PMD_DRV_LOG(NOTICE, "Failed to alloc %s", buf);
8863 if (CHIP_IS_E2E3(sc)) {
8864 fp->status_block.e2_sb =
8865 (struct host_hc_status_block_e2 *)
8868 fp->status_block.e1x_sb =
8869 (struct host_hc_status_block_e1x *)
8878 void bnx2x_free_hsi_mem(struct bnx2x_softc *sc)
8880 struct bnx2x_fastpath *fp;
8883 for (i = 0; i < sc->num_queues; i++) {
8886 /*******************/
8887 /* FP STATUS BLOCK */
8888 /*******************/
8890 memset(&fp->status_block, 0, sizeof(fp->status_block));
8893 /***************************/
8894 /* FW DECOMPRESSION BUFFER */
8895 /***************************/
8899 /*******************/
8900 /* SLOW PATH QUEUE */
8901 /*******************/
8917 /************************/
8918 /* DEFAULT STATUS BLOCK */
8919 /************************/
8926 * Previous driver DMAE transaction may have occurred when pre-boot stage
8927 * ended and boot began. This would invalidate the addresses of the
8928 * transaction, resulting in was-error bit set in the PCI causing all
8929 * hw-to-host PCIe transactions to timeout. If this happened we want to clear
8930 * the interrupt which detected this from the pglueb and the was-done bit
8932 static void bnx2x_prev_interrupted_dmae(struct bnx2x_softc *sc)
8936 if (!CHIP_IS_E1x(sc)) {
8937 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS);
8938 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
8939 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
8945 static int bnx2x_prev_mcp_done(struct bnx2x_softc *sc)
8947 uint32_t rc = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE,
8948 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
8950 PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
8957 static struct bnx2x_prev_list_node *bnx2x_prev_path_get_entry(struct bnx2x_softc *sc)
8959 struct bnx2x_prev_list_node *tmp;
8961 LIST_FOREACH(tmp, &bnx2x_prev_list, node) {
8962 if ((sc->pcie_bus == tmp->bus) &&
8963 (sc->pcie_device == tmp->slot) &&
8964 (SC_PATH(sc) == tmp->path)) {
8972 static uint8_t bnx2x_prev_is_path_marked(struct bnx2x_softc *sc)
8974 struct bnx2x_prev_list_node *tmp;
8977 rte_spinlock_lock(&bnx2x_prev_mtx);
8979 tmp = bnx2x_prev_path_get_entry(sc);
8983 "Path %d/%d/%d was marked by AER",
8984 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
8988 "Path %d/%d/%d was already cleaned from previous drivers",
8989 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
8993 rte_spinlock_unlock(&bnx2x_prev_mtx);
8998 static int bnx2x_prev_mark_path(struct bnx2x_softc *sc, uint8_t after_undi)
9000 struct bnx2x_prev_list_node *tmp;
9002 rte_spinlock_lock(&bnx2x_prev_mtx);
9004 /* Check whether the entry for this path already exists */
9005 tmp = bnx2x_prev_path_get_entry(sc);
9009 "Re-marking AER in path %d/%d/%d",
9010 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9013 "Removing AER indication from path %d/%d/%d",
9014 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9018 rte_spinlock_unlock(&bnx2x_prev_mtx);
9022 rte_spinlock_unlock(&bnx2x_prev_mtx);
9024 /* Create an entry for this path and add it */
9025 tmp = rte_malloc("", sizeof(struct bnx2x_prev_list_node),
9026 RTE_CACHE_LINE_SIZE);
9028 PMD_DRV_LOG(NOTICE, "Failed to allocate 'bnx2x_prev_list_node'");
9032 tmp->bus = sc->pcie_bus;
9033 tmp->slot = sc->pcie_device;
9034 tmp->path = SC_PATH(sc);
9036 tmp->undi = after_undi ? (1 << SC_PORT(sc)) : 0;
9038 rte_spinlock_lock(&bnx2x_prev_mtx);
9040 LIST_INSERT_HEAD(&bnx2x_prev_list, tmp, node);
9042 rte_spinlock_unlock(&bnx2x_prev_mtx);
9047 static int bnx2x_do_flr(struct bnx2x_softc *sc)
9051 /* only E2 and onwards support FLR */
9052 if (CHIP_IS_E1x(sc)) {
9053 PMD_DRV_LOG(WARNING, "FLR not supported in E1H");
9057 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9058 if (sc->devinfo.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9059 PMD_DRV_LOG(WARNING,
9060 "FLR not supported by BC_VER: 0x%08x",
9061 sc->devinfo.bc_ver);
9065 /* Wait for Transaction Pending bit clean */
9066 for (i = 0; i < 4; i++) {
9068 DELAY(((1 << (i - 1)) * 100) * 1000);
9071 if (!bnx2x_is_pcie_pending(sc)) {
9076 PMD_DRV_LOG(NOTICE, "PCIE transaction is not cleared, "
9077 "proceeding with reset anyway");
9080 bnx2x_fw_command(sc, DRV_MSG_CODE_INITIATE_FLR, 0);
9085 struct bnx2x_mac_vals {
9093 uint32_t bmac_val[2];
9097 bnx2x_prev_unload_close_mac(struct bnx2x_softc *sc, struct bnx2x_mac_vals *vals)
9099 uint32_t val, base_addr, offset, mask, reset_reg;
9100 uint8_t mac_stopped = FALSE;
9101 uint8_t port = SC_PORT(sc);
9102 uint32_t wb_data[2];
9104 /* reset addresses as they also mark which values were changed */
9105 vals->bmac_addr = 0;
9106 vals->umac_addr = 0;
9107 vals->xmac_addr = 0;
9108 vals->emac_addr = 0;
9110 reset_reg = REG_RD(sc, MISC_REG_RESET_REG_2);
9112 if (!CHIP_IS_E3(sc)) {
9113 val = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9114 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9115 if ((mask & reset_reg) && val) {
9116 base_addr = SC_PORT(sc) ? NIG_REG_INGRESS_BMAC1_MEM
9117 : NIG_REG_INGRESS_BMAC0_MEM;
9118 offset = CHIP_IS_E2(sc) ? BIGMAC2_REGISTER_BMAC_CONTROL
9119 : BIGMAC_REGISTER_BMAC_CONTROL;
9122 * use rd/wr since we cannot use dmae. This is safe
9123 * since MCP won't access the bus due to the request
9124 * to unload, and no function on the path can be
9125 * loaded at this time.
9127 wb_data[0] = REG_RD(sc, base_addr + offset);
9128 wb_data[1] = REG_RD(sc, base_addr + offset + 0x4);
9129 vals->bmac_addr = base_addr + offset;
9130 vals->bmac_val[0] = wb_data[0];
9131 vals->bmac_val[1] = wb_data[1];
9132 wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE;
9133 REG_WR(sc, vals->bmac_addr, wb_data[0]);
9134 REG_WR(sc, vals->bmac_addr + 0x4, wb_data[1]);
9137 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + SC_PORT(sc) * 4;
9138 vals->emac_val = REG_RD(sc, vals->emac_addr);
9139 REG_WR(sc, vals->emac_addr, 0);
9142 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9143 base_addr = SC_PORT(sc) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9144 val = REG_RD(sc, base_addr + XMAC_REG_PFC_CTRL_HI);
9145 REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9147 REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9149 vals->xmac_addr = base_addr + XMAC_REG_CTRL;
9150 vals->xmac_val = REG_RD(sc, vals->xmac_addr);
9151 REG_WR(sc, vals->xmac_addr, 0);
9155 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9156 if (mask & reset_reg) {
9157 base_addr = SC_PORT(sc) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9158 vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
9159 vals->umac_val = REG_RD(sc, vals->umac_addr);
9160 REG_WR(sc, vals->umac_addr, 0);
9170 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9171 #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
9172 #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
9173 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
9176 bnx2x_prev_unload_undi_inc(struct bnx2x_softc *sc, uint8_t port, uint8_t inc)
9179 uint32_t tmp_reg = REG_RD(sc, BNX2X_PREV_UNDI_PROD_ADDR(port));
9181 rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9182 bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9184 tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9185 REG_WR(sc, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9188 static int bnx2x_prev_unload_common(struct bnx2x_softc *sc)
9190 uint32_t reset_reg, tmp_reg = 0, rc;
9191 uint8_t prev_undi = FALSE;
9192 struct bnx2x_mac_vals mac_vals;
9193 uint32_t timer_count = 1000;
9197 * It is possible a previous function received 'common' answer,
9198 * but hasn't loaded yet, therefore creating a scenario of
9199 * multiple functions receiving 'common' on the same path.
9201 memset(&mac_vals, 0, sizeof(mac_vals));
9203 if (bnx2x_prev_is_path_marked(sc)) {
9204 return bnx2x_prev_mcp_done(sc);
9207 reset_reg = REG_RD(sc, MISC_REG_RESET_REG_1);
9209 /* Reset should be performed after BRB is emptied */
9210 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
9211 /* Close the MAC Rx to prevent BRB from filling up */
9212 bnx2x_prev_unload_close_mac(sc, &mac_vals);
9214 /* close LLH filters towards the BRB */
9215 elink_set_rx_filter(&sc->link_params, 0);
9218 * Check if the UNDI driver was previously loaded.
9219 * UNDI driver initializes CID offset for normal bell to 0x7
9221 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
9222 tmp_reg = REG_RD(sc, DORQ_REG_NORM_CID_OFST);
9223 if (tmp_reg == 0x7) {
9224 PMD_DRV_LOG(DEBUG, "UNDI previously loaded");
9226 /* clear the UNDI indication */
9227 REG_WR(sc, DORQ_REG_NORM_CID_OFST, 0);
9228 /* clear possible idle check errors */
9229 REG_RD(sc, NIG_REG_NIG_INT_STS_CLR_0);
9233 /* wait until BRB is empty */
9234 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9235 while (timer_count) {
9238 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9243 PMD_DRV_LOG(DEBUG, "BRB still has 0x%08x", tmp_reg);
9245 /* reset timer as long as BRB actually gets emptied */
9246 if (prev_brb > tmp_reg) {
9252 /* If UNDI resides in memory, manually increment it */
9254 bnx2x_prev_unload_undi_inc(sc, SC_PORT(sc), 1);
9261 PMD_DRV_LOG(NOTICE, "Failed to empty BRB");
9265 /* No packets are in the pipeline, path is ready for reset */
9266 bnx2x_reset_common(sc);
9268 if (mac_vals.xmac_addr) {
9269 REG_WR(sc, mac_vals.xmac_addr, mac_vals.xmac_val);
9271 if (mac_vals.umac_addr) {
9272 REG_WR(sc, mac_vals.umac_addr, mac_vals.umac_val);
9274 if (mac_vals.emac_addr) {
9275 REG_WR(sc, mac_vals.emac_addr, mac_vals.emac_val);
9277 if (mac_vals.bmac_addr) {
9278 REG_WR(sc, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
9279 REG_WR(sc, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
9282 rc = bnx2x_prev_mark_path(sc, prev_undi);
9284 bnx2x_prev_mcp_done(sc);
9288 return bnx2x_prev_mcp_done(sc);
9291 static int bnx2x_prev_unload_uncommon(struct bnx2x_softc *sc)
9295 /* Test if previous unload process was already finished for this path */
9296 if (bnx2x_prev_is_path_marked(sc)) {
9297 return bnx2x_prev_mcp_done(sc);
9301 * If function has FLR capabilities, and existing FW version matches
9302 * the one required, then FLR will be sufficient to clean any residue
9303 * left by previous driver
9305 rc = bnx2x_nic_load_analyze_req(sc, FW_MSG_CODE_DRV_LOAD_FUNCTION);
9307 /* fw version is good */
9308 rc = bnx2x_do_flr(sc);
9312 /* FLR was performed */
9316 PMD_DRV_LOG(INFO, "Could not FLR");
9318 /* Close the MCP request, return failure */
9319 rc = bnx2x_prev_mcp_done(sc);
9321 rc = BNX2X_PREV_WAIT_NEEDED;
9327 static int bnx2x_prev_unload(struct bnx2x_softc *sc)
9329 int time_counter = 10;
9330 uint32_t fw, hw_lock_reg, hw_lock_val;
9334 * Clear HW from errors which may have resulted from an interrupted
9337 bnx2x_prev_interrupted_dmae(sc);
9339 /* Release previously held locks */
9340 if (SC_FUNC(sc) <= 5)
9341 hw_lock_reg = (MISC_REG_DRIVER_CONTROL_1 + SC_FUNC(sc) * 8);
9344 (MISC_REG_DRIVER_CONTROL_7 + (SC_FUNC(sc) - 6) * 8);
9346 hw_lock_val = (REG_RD(sc, hw_lock_reg));
9348 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
9349 REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
9350 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << SC_PORT(sc)));
9352 REG_WR(sc, hw_lock_reg, 0xffffffff);
9355 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(sc, MCP_REG_MCPR_ACCESS_LOCK)) {
9356 REG_WR(sc, MCP_REG_MCPR_ACCESS_LOCK, 0);
9360 /* Lock MCP using an unload request */
9361 fw = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
9363 PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
9368 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
9369 rc = bnx2x_prev_unload_common(sc);
9373 /* non-common reply from MCP might require looping */
9374 rc = bnx2x_prev_unload_uncommon(sc);
9375 if (rc != BNX2X_PREV_WAIT_NEEDED) {
9380 } while (--time_counter);
9382 if (!time_counter || rc) {
9383 PMD_DRV_LOG(NOTICE, "Failed to unload previous driver!");
9391 bnx2x_dcbx_set_state(struct bnx2x_softc *sc, uint8_t dcb_on, uint32_t dcbx_enabled)
9393 if (!CHIP_IS_E1x(sc)) {
9394 sc->dcb_state = dcb_on;
9395 sc->dcbx_enabled = dcbx_enabled;
9397 sc->dcb_state = FALSE;
9398 sc->dcbx_enabled = BNX2X_DCBX_ENABLED_INVALID;
9401 "DCB state [%s:%s]",
9402 dcb_on ? "ON" : "OFF",
9403 (dcbx_enabled == BNX2X_DCBX_ENABLED_OFF) ? "user-mode" :
9405 BNX2X_DCBX_ENABLED_ON_NEG_OFF) ? "on-chip static"
9407 BNX2X_DCBX_ENABLED_ON_NEG_ON) ?
9408 "on-chip with negotiation" : "invalid");
9411 static int bnx2x_set_qm_cid_count(struct bnx2x_softc *sc)
9413 int cid_count = BNX2X_L2_MAX_CID(sc);
9415 if (CNIC_SUPPORT(sc)) {
9416 cid_count += CNIC_CID_MAX;
9419 return roundup(cid_count, QM_CID_ROUND);
9422 static void bnx2x_init_multi_cos(struct bnx2x_softc *sc)
9426 uint32_t pri_map = 0;
9428 for (pri = 0; pri < BNX2X_MAX_PRIORITY; pri++) {
9429 cos = ((pri_map & (0xf << (pri * 4))) >> (pri * 4));
9430 if (cos < sc->max_cos) {
9431 sc->prio_to_cos[pri] = cos;
9433 PMD_DRV_LOG(WARNING,
9434 "Invalid COS %d for priority %d "
9435 "(max COS is %d), setting to 0", cos, pri,
9437 sc->prio_to_cos[pri] = 0;
9442 static int bnx2x_pci_get_caps(struct bnx2x_softc *sc)
9449 struct bnx2x_pci_cap *cap;
9451 cap = sc->pci_caps = rte_zmalloc("caps", sizeof(struct bnx2x_pci_cap),
9452 RTE_CACHE_LINE_SIZE);
9454 PMD_DRV_LOG(NOTICE, "Failed to allocate memory");
9459 pci_read(sc, PCI_STATUS, &status, 2);
9460 if (!(status & PCI_STATUS_CAP_LIST)) {
9462 pci_read(sc, PCIR_STATUS, &status, 2);
9463 if (!(status & PCIM_STATUS_CAPPRESENT)) {
9465 PMD_DRV_LOG(NOTICE, "PCIe capability reading failed");
9470 pci_read(sc, PCI_CAPABILITY_LIST, &pci_cap.next, 1);
9472 pci_read(sc, PCIR_CAP_PTR, &pci_cap.next, 1);
9474 while (pci_cap.next) {
9475 cap->addr = pci_cap.next & ~3;
9476 pci_read(sc, pci_cap.next & ~3, &pci_cap, 2);
9477 if (pci_cap.id == 0xff)
9479 cap->id = pci_cap.id;
9480 cap->type = BNX2X_PCI_CAP;
9481 cap->next = rte_zmalloc("pci_cap",
9482 sizeof(struct bnx2x_pci_cap),
9483 RTE_CACHE_LINE_SIZE);
9485 PMD_DRV_LOG(NOTICE, "Failed to allocate memory");
9494 static void bnx2x_init_rte(struct bnx2x_softc *sc)
9497 sc->max_tx_queues = min(BNX2X_VF_MAX_QUEUES_PER_VF,
9499 sc->max_rx_queues = min(BNX2X_VF_MAX_QUEUES_PER_VF,
9502 sc->max_rx_queues = BNX2X_MAX_RSS_COUNT(sc);
9503 sc->max_tx_queues = sc->max_rx_queues;
9507 #define FW_HEADER_LEN 104
9508 #define FW_NAME_57711 "/lib/firmware/bnx2x/bnx2x-e1h-7.2.51.0.fw"
9509 #define FW_NAME_57810 "/lib/firmware/bnx2x/bnx2x-e2-7.2.51.0.fw"
9511 void bnx2x_load_firmware(struct bnx2x_softc *sc)
9517 fwname = sc->devinfo.device_id == CHIP_NUM_57711
9518 ? FW_NAME_57711 : FW_NAME_57810;
9519 f = open(fwname, O_RDONLY);
9521 PMD_DRV_LOG(NOTICE, "Can't open firmware file");
9525 if (fstat(f, &st) < 0) {
9526 PMD_DRV_LOG(NOTICE, "Can't stat firmware file");
9531 sc->firmware = rte_zmalloc("bnx2x_fw", st.st_size, RTE_CACHE_LINE_SIZE);
9532 if (!sc->firmware) {
9533 PMD_DRV_LOG(NOTICE, "Can't allocate memory for firmware");
9538 if (read(f, sc->firmware, st.st_size) != st.st_size) {
9539 PMD_DRV_LOG(NOTICE, "Can't read firmware data");
9545 sc->fw_len = st.st_size;
9546 if (sc->fw_len < FW_HEADER_LEN) {
9547 PMD_DRV_LOG(NOTICE, "Invalid fw size: %" PRIu64, sc->fw_len);
9550 PMD_DRV_LOG(DEBUG, "fw_len = %" PRIu64, sc->fw_len);
9554 bnx2x_data_to_init_ops(uint8_t * data, struct raw_op *dst, uint32_t len)
9556 uint32_t *src = (uint32_t *) data;
9559 for (i = 0, j = 0; i < len / 8; ++i, j += 2) {
9560 tmp = rte_be_to_cpu_32(src[j]);
9561 dst[i].op = (tmp >> 24) & 0xFF;
9562 dst[i].offset = tmp & 0xFFFFFF;
9563 dst[i].raw_data = rte_be_to_cpu_32(src[j + 1]);
9568 bnx2x_data_to_init_offsets(uint8_t * data, uint16_t * dst, uint32_t len)
9570 uint16_t *src = (uint16_t *) data;
9573 for (i = 0; i < len / 2; ++i)
9574 dst[i] = rte_be_to_cpu_16(src[i]);
9577 static void bnx2x_data_to_init_data(uint8_t * data, uint32_t * dst, uint32_t len)
9579 uint32_t *src = (uint32_t *) data;
9582 for (i = 0; i < len / 4; ++i)
9583 dst[i] = rte_be_to_cpu_32(src[i]);
9586 static void bnx2x_data_to_iro_array(uint8_t * data, struct iro *dst, uint32_t len)
9588 uint32_t *src = (uint32_t *) data;
9591 for (i = 0, j = 0; i < len / sizeof(struct iro); ++i, ++j) {
9592 dst[i].base = rte_be_to_cpu_32(src[j++]);
9593 tmp = rte_be_to_cpu_32(src[j]);
9594 dst[i].m1 = (tmp >> 16) & 0xFFFF;
9595 dst[i].m2 = tmp & 0xFFFF;
9597 tmp = rte_be_to_cpu_32(src[j]);
9598 dst[i].m3 = (tmp >> 16) & 0xFFFF;
9599 dst[i].size = tmp & 0xFFFF;
9604 * Device attach function.
9606 * Allocates device resources, performs secondary chip identification, and
9607 * initializes driver instance variables. This function is called from driver
9608 * load after a successful probe.
9611 * 0 = Success, >0 = Failure
9613 int bnx2x_attach(struct bnx2x_softc *sc)
9617 PMD_DRV_LOG(DEBUG, "Starting attach...");
9619 rc = bnx2x_pci_get_caps(sc);
9621 PMD_DRV_LOG(NOTICE, "PCIe caps reading was failed");
9625 sc->state = BNX2X_STATE_CLOSED;
9627 pci_write_long(sc, PCICFG_GRC_ADDRESS, PCICFG_VENDOR_ID_OFFSET);
9629 sc->igu_base_addr = IS_VF(sc) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
9631 /* get PCI capabilites */
9632 bnx2x_probe_pci_caps(sc);
9634 if (sc->devinfo.pcie_msix_cap_reg != 0) {
9637 (sc->devinfo.pcie_msix_cap_reg + PCIR_MSIX_CTRL), &val,
9639 sc->igu_sb_cnt = (val & PCIM_MSIXCTRL_TABLE_SIZE) + 1;
9644 /* Init RTE stuff */
9648 /* Enable internal target-read (in case we are probed after PF
9649 * FLR). Must be done prior to any BAR read access. Only for
9652 if (!CHIP_IS_E1x(sc)) {
9653 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ,
9658 /* get device info and set params */
9659 if (bnx2x_get_device_info(sc) != 0) {
9660 PMD_DRV_LOG(NOTICE, "getting device info");
9664 /* get phy settings from shmem and 'and' against admin settings */
9665 bnx2x_get_phy_info(sc);
9667 /* Left mac of VF unfilled, PF should set it for VF */
9668 memset(sc->link_params.mac_addr, 0, ETHER_ADDR_LEN);
9673 /* set the default MTU (changed via ifconfig) */
9674 sc->mtu = ETHER_MTU;
9676 bnx2x_set_modes_bitmap(sc);
9678 /* need to reset chip if UNDI was active */
9679 if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
9682 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
9683 DRV_MSG_SEQ_NUMBER_MASK);
9684 bnx2x_prev_unload(sc);
9687 bnx2x_dcbx_set_state(sc, FALSE, BNX2X_DCBX_ENABLED_OFF);
9689 /* calculate qm_cid_count */
9690 sc->qm_cid_count = bnx2x_set_qm_cid_count(sc);
9693 bnx2x_init_multi_cos(sc);
9699 bnx2x_igu_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t segment,
9700 uint16_t index, uint8_t op, uint8_t update)
9702 uint32_t igu_addr = sc->igu_base_addr;
9703 igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
9704 bnx2x_igu_ack_sb_gen(sc, segment, index, op, update, igu_addr);
9708 bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t storm,
9709 uint16_t index, uint8_t op, uint8_t update)
9711 if (unlikely(sc->devinfo.int_block == INT_BLOCK_HC))
9712 bnx2x_hc_ack_sb(sc, igu_sb_id, storm, index, op, update);
9715 if (CHIP_INT_MODE_IS_BC(sc)) {
9717 } else if (igu_sb_id != sc->igu_dsb_id) {
9718 segment = IGU_SEG_ACCESS_DEF;
9719 } else if (storm == ATTENTION_ID) {
9720 segment = IGU_SEG_ACCESS_ATTN;
9722 segment = IGU_SEG_ACCESS_DEF;
9724 bnx2x_igu_ack_sb(sc, igu_sb_id, segment, index, op, update);
9729 bnx2x_igu_clear_sb_gen(struct bnx2x_softc *sc, uint8_t func, uint8_t idu_sb_id,
9732 uint32_t data, ctl, cnt = 100;
9733 uint32_t igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
9734 uint32_t igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
9735 uint32_t igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP +
9736 (idu_sb_id / 32) * 4;
9737 uint32_t sb_bit = 1 << (idu_sb_id % 32);
9738 uint32_t func_encode = func |
9739 (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
9740 uint32_t addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
9742 /* Not supported in BC mode */
9743 if (CHIP_INT_MODE_IS_BC(sc)) {
9747 data = ((IGU_USE_REGISTER_cstorm_type_0_sb_cleanup <<
9748 IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
9749 IGU_REGULAR_CLEANUP_SET | IGU_REGULAR_BCLEANUP);
9751 ctl = ((addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT) |
9752 (func_encode << IGU_CTRL_REG_FID_SHIFT) |
9753 (IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT));
9755 REG_WR(sc, igu_addr_data, data);
9759 PMD_DRV_LOG(DEBUG, "write 0x%08x to IGU(via GRC) addr 0x%x",
9761 REG_WR(sc, igu_addr_ctl, ctl);
9765 /* wait for clean up to finish */
9766 while (!(REG_RD(sc, igu_addr_ack) & sb_bit) && --cnt) {
9770 if (!(REG_RD(sc, igu_addr_ack) & sb_bit)) {
9772 "Unable to finish IGU cleanup: "
9773 "idu_sb_id %d offset %d bit %d (cnt %d)",
9774 idu_sb_id, idu_sb_id / 32, idu_sb_id % 32, cnt);
9778 static void bnx2x_igu_clear_sb(struct bnx2x_softc *sc, uint8_t idu_sb_id)
9780 bnx2x_igu_clear_sb_gen(sc, SC_FUNC(sc), idu_sb_id, TRUE /*PF*/);
9783 /*******************/
9784 /* ECORE CALLBACKS */
9785 /*******************/
9787 static void bnx2x_reset_common(struct bnx2x_softc *sc)
9789 uint32_t val = 0x1400;
9791 PMD_INIT_FUNC_TRACE();
9794 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR),
9797 if (CHIP_IS_E3(sc)) {
9798 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
9799 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
9802 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR), val);
9805 static void bnx2x_common_init_phy(struct bnx2x_softc *sc)
9807 uint32_t shmem_base[2];
9808 uint32_t shmem2_base[2];
9810 /* Avoid common init in case MFW supports LFA */
9811 if (SHMEM2_RD(sc, size) >
9812 (uint32_t) offsetof(struct shmem2_region,
9813 lfa_host_addr[SC_PORT(sc)])) {
9817 shmem_base[0] = sc->devinfo.shmem_base;
9818 shmem2_base[0] = sc->devinfo.shmem2_base;
9820 if (!CHIP_IS_E1x(sc)) {
9821 shmem_base[1] = SHMEM2_RD(sc, other_shmem_base_addr);
9822 shmem2_base[1] = SHMEM2_RD(sc, other_shmem2_base_addr);
9825 elink_common_init_phy(sc, shmem_base, shmem2_base,
9826 sc->devinfo.chip_id, 0);
9829 static void bnx2x_pf_disable(struct bnx2x_softc *sc)
9831 uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
9833 val &= ~IGU_PF_CONF_FUNC_EN;
9835 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
9836 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
9837 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 0);
9840 static void bnx2x_init_pxp(struct bnx2x_softc *sc)
9843 int r_order, w_order;
9845 devctl = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_CTL);
9847 w_order = ((devctl & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5);
9848 r_order = ((devctl & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12);
9850 ecore_init_pxp_arb(sc, r_order, w_order);
9853 static uint32_t bnx2x_get_pretend_reg(struct bnx2x_softc *sc)
9855 uint32_t base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9856 uint32_t stride = (PXP2_REG_PGL_PRETEND_FUNC_F1 - base);
9857 return base + (SC_ABS_FUNC(sc)) * stride;
9861 * Called only on E1H or E2.
9862 * When pretending to be PF, the pretend value is the function number 0..7.
9863 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
9866 static int bnx2x_pretend_func(struct bnx2x_softc *sc, uint16_t pretend_func_val)
9868 uint32_t pretend_reg;
9870 if (CHIP_IS_E1H(sc) && (pretend_func_val > E1H_FUNC_MAX))
9873 /* get my own pretend register */
9874 pretend_reg = bnx2x_get_pretend_reg(sc);
9875 REG_WR(sc, pretend_reg, pretend_func_val);
9876 REG_RD(sc, pretend_reg);
9880 static void bnx2x_setup_fan_failure_detection(struct bnx2x_softc *sc)
9887 val = (SHMEM_RD(sc, dev_info.shared_hw_config.config2) &
9888 SHARED_HW_CFG_FAN_FAILURE_MASK);
9890 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) {
9894 * The fan failure mechanism is usually related to the PHY type since
9895 * the power consumption of the board is affected by the PHY. Currently,
9896 * fan is required for most designs with SFX7101, BNX2X8727 and BNX2X8481.
9898 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) {
9899 for (port = PORT_0; port < PORT_MAX; port++) {
9900 is_required |= elink_fan_failure_det_req(sc,
9904 devinfo.shmem2_base,
9909 if (is_required == 0) {
9913 /* Fan failure is indicated by SPIO 5 */
9914 bnx2x_set_spio(sc, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
9916 /* set to active low mode */
9917 val = REG_RD(sc, MISC_REG_SPIO_INT);
9918 val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
9919 REG_WR(sc, MISC_REG_SPIO_INT, val);
9921 /* enable interrupt to signal the IGU */
9922 val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
9923 val |= MISC_SPIO_SPIO5;
9924 REG_WR(sc, MISC_REG_SPIO_EVENT_EN, val);
9927 static void bnx2x_enable_blocks_attention(struct bnx2x_softc *sc)
9931 REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0);
9932 if (!CHIP_IS_E1x(sc)) {
9933 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0x40);
9935 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0);
9937 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
9938 REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
9940 * mask read length error interrupts in brb for parser
9941 * (parsing unit and 'checksum and crc' unit)
9942 * these errors are legal (PU reads fixed length and CAC can cause
9943 * read length error on truncated packets)
9945 REG_WR(sc, BRB1_REG_BRB1_INT_MASK, 0xFC00);
9946 REG_WR(sc, QM_REG_QM_INT_MASK, 0);
9947 REG_WR(sc, TM_REG_TM_INT_MASK, 0);
9948 REG_WR(sc, XSDM_REG_XSDM_INT_MASK_0, 0);
9949 REG_WR(sc, XSDM_REG_XSDM_INT_MASK_1, 0);
9950 REG_WR(sc, XCM_REG_XCM_INT_MASK, 0);
9951 /* REG_WR(sc, XSEM_REG_XSEM_INT_MASK_0, 0); */
9952 /* REG_WR(sc, XSEM_REG_XSEM_INT_MASK_1, 0); */
9953 REG_WR(sc, USDM_REG_USDM_INT_MASK_0, 0);
9954 REG_WR(sc, USDM_REG_USDM_INT_MASK_1, 0);
9955 REG_WR(sc, UCM_REG_UCM_INT_MASK, 0);
9956 /* REG_WR(sc, USEM_REG_USEM_INT_MASK_0, 0); */
9957 /* REG_WR(sc, USEM_REG_USEM_INT_MASK_1, 0); */
9958 REG_WR(sc, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
9959 REG_WR(sc, CSDM_REG_CSDM_INT_MASK_0, 0);
9960 REG_WR(sc, CSDM_REG_CSDM_INT_MASK_1, 0);
9961 REG_WR(sc, CCM_REG_CCM_INT_MASK, 0);
9962 /* REG_WR(sc, CSEM_REG_CSEM_INT_MASK_0, 0); */
9963 /* REG_WR(sc, CSEM_REG_CSEM_INT_MASK_1, 0); */
9965 val = (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
9966 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
9967 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN);
9968 if (!CHIP_IS_E1x(sc)) {
9969 val |= (PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
9970 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED);
9972 REG_WR(sc, PXP2_REG_PXP2_INT_MASK_0, val);
9974 REG_WR(sc, TSDM_REG_TSDM_INT_MASK_0, 0);
9975 REG_WR(sc, TSDM_REG_TSDM_INT_MASK_1, 0);
9976 REG_WR(sc, TCM_REG_TCM_INT_MASK, 0);
9977 /* REG_WR(sc, TSEM_REG_TSEM_INT_MASK_0, 0); */
9979 if (!CHIP_IS_E1x(sc)) {
9980 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
9981 REG_WR(sc, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
9984 REG_WR(sc, CDU_REG_CDU_INT_MASK, 0);
9985 REG_WR(sc, DMAE_REG_DMAE_INT_MASK, 0);
9986 /* REG_WR(sc, MISC_REG_MISC_INT_MASK, 0); */
9987 REG_WR(sc, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
9991 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
9993 * @sc: driver handle
9995 static int bnx2x_init_hw_common(struct bnx2x_softc *sc)
9997 uint8_t abs_func_id;
10000 PMD_DRV_LOG(DEBUG, "starting common init for func %d", SC_ABS_FUNC(sc));
10003 * take the RESET lock to protect undi_unload flow from accessing
10004 * registers while we are resetting the chip
10006 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10008 bnx2x_reset_common(sc);
10010 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET), 0xffffffff);
10013 if (CHIP_IS_E3(sc)) {
10014 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
10015 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
10018 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET), val);
10020 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10022 ecore_init_block(sc, BLOCK_MISC, PHASE_COMMON);
10024 if (!CHIP_IS_E1x(sc)) {
10026 * 4-port mode or 2-port mode we need to turn off master-enable for
10027 * everyone. After that we turn it back on for self. So, we disregard
10028 * multi-function, and always disable all functions on the given path,
10029 * this means 0,2,4,6 for path 0 and 1,3,5,7 for path 1
10031 for (abs_func_id = SC_PATH(sc);
10032 abs_func_id < (E2_FUNC_MAX * 2); abs_func_id += 2) {
10033 if (abs_func_id == SC_ABS_FUNC(sc)) {
10035 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
10040 bnx2x_pretend_func(sc, abs_func_id);
10042 /* clear pf enable */
10043 bnx2x_pf_disable(sc);
10045 bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10049 ecore_init_block(sc, BLOCK_PXP, PHASE_COMMON);
10051 ecore_init_block(sc, BLOCK_PXP2, PHASE_COMMON);
10052 bnx2x_init_pxp(sc);
10054 #ifdef __BIG_ENDIAN
10055 REG_WR(sc, PXP2_REG_RQ_QM_ENDIAN_M, 1);
10056 REG_WR(sc, PXP2_REG_RQ_TM_ENDIAN_M, 1);
10057 REG_WR(sc, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
10058 REG_WR(sc, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
10059 REG_WR(sc, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
10060 /* make sure this value is 0 */
10061 REG_WR(sc, PXP2_REG_RQ_HC_ENDIAN_M, 0);
10063 //REG_WR(sc, PXP2_REG_RD_PBF_SWAP_MODE, 1);
10064 REG_WR(sc, PXP2_REG_RD_QM_SWAP_MODE, 1);
10065 REG_WR(sc, PXP2_REG_RD_TM_SWAP_MODE, 1);
10066 REG_WR(sc, PXP2_REG_RD_SRC_SWAP_MODE, 1);
10067 REG_WR(sc, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
10070 ecore_ilt_init_page_size(sc, INITOP_SET);
10072 if (CHIP_REV_IS_FPGA(sc) && CHIP_IS_E1H(sc)) {
10073 REG_WR(sc, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
10076 /* let the HW do it's magic... */
10079 /* finish PXP init */
10081 val = REG_RD(sc, PXP2_REG_RQ_CFG_DONE);
10083 PMD_DRV_LOG(NOTICE, "PXP2 CFG failed");
10086 val = REG_RD(sc, PXP2_REG_RD_INIT_DONE);
10088 PMD_DRV_LOG(NOTICE, "PXP2 RD_INIT failed");
10093 * Timer bug workaround for E2 only. We need to set the entire ILT to have
10094 * entries with value "0" and valid bit on. This needs to be done by the
10095 * first PF that is loaded in a path (i.e. common phase)
10097 if (!CHIP_IS_E1x(sc)) {
10099 * In E2 there is a bug in the timers block that can cause function 6 / 7
10100 * (i.e. vnic3) to start even if it is marked as "scan-off".
10101 * This occurs when a different function (func2,3) is being marked
10102 * as "scan-off". Real-life scenario for example: if a driver is being
10103 * load-unloaded while func6,7 are down. This will cause the timer to access
10104 * the ilt, translate to a logical address and send a request to read/write.
10105 * Since the ilt for the function that is down is not valid, this will cause
10106 * a translation error which is unrecoverable.
10107 * The Workaround is intended to make sure that when this happens nothing
10108 * fatal will occur. The workaround:
10109 * 1. First PF driver which loads on a path will:
10110 * a. After taking the chip out of reset, by using pretend,
10111 * it will write "0" to the following registers of
10113 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10114 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
10115 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
10116 * And for itself it will write '1' to
10117 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
10118 * dmae-operations (writing to pram for example.)
10119 * note: can be done for only function 6,7 but cleaner this
10121 * b. Write zero+valid to the entire ILT.
10122 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
10123 * VNIC3 (of that port). The range allocated will be the
10124 * entire ILT. This is needed to prevent ILT range error.
10125 * 2. Any PF driver load flow:
10126 * a. ILT update with the physical addresses of the allocated
10128 * b. Wait 20msec. - note that this timeout is needed to make
10129 * sure there are no requests in one of the PXP internal
10130 * queues with "old" ILT addresses.
10131 * c. PF enable in the PGLC.
10132 * d. Clear the was_error of the PF in the PGLC. (could have
10133 * occurred while driver was down)
10134 * e. PF enable in the CFC (WEAK + STRONG)
10135 * f. Timers scan enable
10136 * 3. PF driver unload flow:
10137 * a. Clear the Timers scan_en.
10138 * b. Polling for scan_on=0 for that PF.
10139 * c. Clear the PF enable bit in the PXP.
10140 * d. Clear the PF enable in the CFC (WEAK + STRONG)
10141 * e. Write zero+valid to all ILT entries (The valid bit must
10143 * f. If this is VNIC 3 of a port then also init
10144 * first_timers_ilt_entry to zero and last_timers_ilt_entry
10145 * to the last enrty in the ILT.
10148 * Currently the PF error in the PGLC is non recoverable.
10149 * In the future the there will be a recovery routine for this error.
10150 * Currently attention is masked.
10151 * Having an MCP lock on the load/unload process does not guarantee that
10152 * there is no Timer disable during Func6/7 enable. This is because the
10153 * Timers scan is currently being cleared by the MCP on FLR.
10154 * Step 2.d can be done only for PF6/7 and the driver can also check if
10155 * there is error before clearing it. But the flow above is simpler and
10157 * All ILT entries are written by zero+valid and not just PF6/7
10158 * ILT entries since in the future the ILT entries allocation for
10159 * PF-s might be dynamic.
10161 struct ilt_client_info ilt_cli;
10162 struct ecore_ilt ilt;
10164 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
10165 memset(&ilt, 0, sizeof(struct ecore_ilt));
10167 /* initialize dummy TM client */
10169 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
10170 ilt_cli.client_num = ILT_CLIENT_TM;
10173 * Step 1: set zeroes to all ilt page entries with valid bit on
10174 * Step 2: set the timers first/last ilt entry to point
10175 * to the entire range to prevent ILT range error for 3rd/4th
10176 * vnic (this code assumes existence of the vnic)
10178 * both steps performed by call to ecore_ilt_client_init_op()
10179 * with dummy TM client
10181 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
10182 * and his brother are split registers
10185 bnx2x_pretend_func(sc, (SC_PATH(sc) + 6));
10186 ecore_ilt_client_init_op_ilt(sc, &ilt, &ilt_cli, INITOP_CLEAR);
10187 bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10189 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
10190 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
10191 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
10194 REG_WR(sc, PXP2_REG_RQ_DISABLE_INPUTS, 0);
10195 REG_WR(sc, PXP2_REG_RD_DISABLE_INPUTS, 0);
10197 if (!CHIP_IS_E1x(sc)) {
10200 ecore_init_block(sc, BLOCK_PGLUE_B, PHASE_COMMON);
10201 ecore_init_block(sc, BLOCK_ATC, PHASE_COMMON);
10203 /* let the HW do it's magic... */
10206 val = REG_RD(sc, ATC_REG_ATC_INIT_DONE);
10207 } while (factor-- && (val != 1));
10210 PMD_DRV_LOG(NOTICE, "ATC_INIT failed");
10215 ecore_init_block(sc, BLOCK_DMAE, PHASE_COMMON);
10217 /* clean the DMAE memory */
10218 sc->dmae_ready = 1;
10219 ecore_init_fill(sc, TSEM_REG_PRAM, 0, 8);
10221 ecore_init_block(sc, BLOCK_TCM, PHASE_COMMON);
10223 ecore_init_block(sc, BLOCK_UCM, PHASE_COMMON);
10225 ecore_init_block(sc, BLOCK_CCM, PHASE_COMMON);
10227 ecore_init_block(sc, BLOCK_XCM, PHASE_COMMON);
10229 bnx2x_read_dmae(sc, XSEM_REG_PASSIVE_BUFFER, 3);
10230 bnx2x_read_dmae(sc, CSEM_REG_PASSIVE_BUFFER, 3);
10231 bnx2x_read_dmae(sc, TSEM_REG_PASSIVE_BUFFER, 3);
10232 bnx2x_read_dmae(sc, USEM_REG_PASSIVE_BUFFER, 3);
10234 ecore_init_block(sc, BLOCK_QM, PHASE_COMMON);
10236 /* QM queues pointers table */
10237 ecore_qm_init_ptr_table(sc, sc->qm_cid_count, INITOP_SET);
10239 /* soft reset pulse */
10240 REG_WR(sc, QM_REG_SOFT_RESET, 1);
10241 REG_WR(sc, QM_REG_SOFT_RESET, 0);
10243 if (CNIC_SUPPORT(sc))
10244 ecore_init_block(sc, BLOCK_TM, PHASE_COMMON);
10246 ecore_init_block(sc, BLOCK_DORQ, PHASE_COMMON);
10247 REG_WR(sc, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
10249 if (!CHIP_REV_IS_SLOW(sc)) {
10250 /* enable hw interrupt from doorbell Q */
10251 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
10254 ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON);
10256 ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON);
10257 REG_WR(sc, PRS_REG_A_PRSU_20, 0xf);
10258 REG_WR(sc, PRS_REG_E1HOV_MODE, sc->devinfo.mf_info.path_has_ovlan);
10260 if (!CHIP_IS_E1x(sc) && !CHIP_IS_E3B0(sc)) {
10261 if (IS_MF_AFEX(sc)) {
10263 * configure that AFEX and VLAN headers must be
10264 * received in AFEX mode
10266 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC, 0xE);
10267 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS, 0xA);
10268 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
10269 REG_WR(sc, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
10270 REG_WR(sc, PRS_REG_TAG_LEN_0, 0x4);
10273 * Bit-map indicating which L2 hdrs may appear
10274 * after the basic Ethernet header
10276 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC,
10277 sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10281 ecore_init_block(sc, BLOCK_TSDM, PHASE_COMMON);
10282 ecore_init_block(sc, BLOCK_CSDM, PHASE_COMMON);
10283 ecore_init_block(sc, BLOCK_USDM, PHASE_COMMON);
10284 ecore_init_block(sc, BLOCK_XSDM, PHASE_COMMON);
10286 if (!CHIP_IS_E1x(sc)) {
10287 /* reset VFC memories */
10288 REG_WR(sc, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10289 VFC_MEMORIES_RST_REG_CAM_RST |
10290 VFC_MEMORIES_RST_REG_RAM_RST);
10291 REG_WR(sc, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10292 VFC_MEMORIES_RST_REG_CAM_RST |
10293 VFC_MEMORIES_RST_REG_RAM_RST);
10298 ecore_init_block(sc, BLOCK_TSEM, PHASE_COMMON);
10299 ecore_init_block(sc, BLOCK_USEM, PHASE_COMMON);
10300 ecore_init_block(sc, BLOCK_CSEM, PHASE_COMMON);
10301 ecore_init_block(sc, BLOCK_XSEM, PHASE_COMMON);
10303 /* sync semi rtc */
10304 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x80000000);
10305 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x80000000);
10307 ecore_init_block(sc, BLOCK_UPB, PHASE_COMMON);
10308 ecore_init_block(sc, BLOCK_XPB, PHASE_COMMON);
10309 ecore_init_block(sc, BLOCK_PBF, PHASE_COMMON);
10311 if (!CHIP_IS_E1x(sc)) {
10312 if (IS_MF_AFEX(sc)) {
10314 * configure that AFEX and VLAN headers must be
10315 * sent in AFEX mode
10317 REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC, 0xE);
10318 REG_WR(sc, PBF_REG_MUST_HAVE_HDRS, 0xA);
10319 REG_WR(sc, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
10320 REG_WR(sc, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
10321 REG_WR(sc, PBF_REG_TAG_LEN_0, 0x4);
10323 REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC,
10324 sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10328 REG_WR(sc, SRC_REG_SOFT_RST, 1);
10330 ecore_init_block(sc, BLOCK_SRC, PHASE_COMMON);
10332 if (CNIC_SUPPORT(sc)) {
10333 REG_WR(sc, SRC_REG_KEYSEARCH_0, 0x63285672);
10334 REG_WR(sc, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
10335 REG_WR(sc, SRC_REG_KEYSEARCH_2, 0x223aef9b);
10336 REG_WR(sc, SRC_REG_KEYSEARCH_3, 0x26001e3a);
10337 REG_WR(sc, SRC_REG_KEYSEARCH_4, 0x7ae91116);
10338 REG_WR(sc, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
10339 REG_WR(sc, SRC_REG_KEYSEARCH_6, 0x298d8adf);
10340 REG_WR(sc, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
10341 REG_WR(sc, SRC_REG_KEYSEARCH_8, 0x1830f82f);
10342 REG_WR(sc, SRC_REG_KEYSEARCH_9, 0x01e46be7);
10344 REG_WR(sc, SRC_REG_SOFT_RST, 0);
10346 if (sizeof(union cdu_context) != 1024) {
10347 /* we currently assume that a context is 1024 bytes */
10348 PMD_DRV_LOG(NOTICE,
10349 "please adjust the size of cdu_context(%ld)",
10350 (long)sizeof(union cdu_context));
10353 ecore_init_block(sc, BLOCK_CDU, PHASE_COMMON);
10354 val = (4 << 24) + (0 << 12) + 1024;
10355 REG_WR(sc, CDU_REG_CDU_GLOBAL_PARAMS, val);
10357 ecore_init_block(sc, BLOCK_CFC, PHASE_COMMON);
10359 REG_WR(sc, CFC_REG_INIT_REG, 0x7FF);
10360 /* enable context validation interrupt from CFC */
10361 REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
10363 /* set the thresholds to prevent CFC/CDU race */
10364 REG_WR(sc, CFC_REG_DEBUG0, 0x20020000);
10365 ecore_init_block(sc, BLOCK_HC, PHASE_COMMON);
10367 if (!CHIP_IS_E1x(sc) && BNX2X_NOMCP(sc)) {
10368 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x36);
10371 ecore_init_block(sc, BLOCK_IGU, PHASE_COMMON);
10372 ecore_init_block(sc, BLOCK_MISC_AEU, PHASE_COMMON);
10374 /* Reset PCIE errors for debug */
10375 REG_WR(sc, 0x2814, 0xffffffff);
10376 REG_WR(sc, 0x3820, 0xffffffff);
10378 if (!CHIP_IS_E1x(sc)) {
10379 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
10380 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
10381 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
10382 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
10383 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
10384 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
10385 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
10386 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
10387 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
10388 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
10389 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
10392 ecore_init_block(sc, BLOCK_NIG, PHASE_COMMON);
10394 /* in E3 this done in per-port section */
10395 if (!CHIP_IS_E3(sc))
10396 REG_WR(sc, NIG_REG_LLH_MF_MODE, IS_MF(sc));
10398 if (CHIP_IS_E1H(sc)) {
10399 /* not applicable for E2 (and above ...) */
10400 REG_WR(sc, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(sc));
10403 if (CHIP_REV_IS_SLOW(sc)) {
10407 /* finish CFC init */
10408 val = reg_poll(sc, CFC_REG_LL_INIT_DONE, 1, 100, 10);
10410 PMD_DRV_LOG(NOTICE, "CFC LL_INIT failed");
10413 val = reg_poll(sc, CFC_REG_AC_INIT_DONE, 1, 100, 10);
10415 PMD_DRV_LOG(NOTICE, "CFC AC_INIT failed");
10418 val = reg_poll(sc, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
10420 PMD_DRV_LOG(NOTICE, "CFC CAM_INIT failed");
10423 REG_WR(sc, CFC_REG_DEBUG0, 0);
10425 bnx2x_setup_fan_failure_detection(sc);
10427 /* clear PXP2 attentions */
10428 REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
10430 bnx2x_enable_blocks_attention(sc);
10432 if (!CHIP_REV_IS_SLOW(sc)) {
10433 ecore_enable_blocks_parity(sc);
10436 if (!BNX2X_NOMCP(sc)) {
10437 if (CHIP_IS_E1x(sc)) {
10438 bnx2x_common_init_phy(sc);
10446 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
10448 * @sc: driver handle
10450 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc)
10452 int rc = bnx2x_init_hw_common(sc);
10458 /* In E2 2-PORT mode, same ext phy is used for the two paths */
10459 if (!BNX2X_NOMCP(sc)) {
10460 bnx2x_common_init_phy(sc);
10466 static int bnx2x_init_hw_port(struct bnx2x_softc *sc)
10468 int port = SC_PORT(sc);
10469 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
10470 uint32_t low, high;
10473 PMD_DRV_LOG(DEBUG, "starting port init for port %d", port);
10475 REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
10477 ecore_init_block(sc, BLOCK_MISC, init_phase);
10478 ecore_init_block(sc, BLOCK_PXP, init_phase);
10479 ecore_init_block(sc, BLOCK_PXP2, init_phase);
10482 * Timers bug workaround: disables the pf_master bit in pglue at
10483 * common phase, we need to enable it here before any dmae access are
10484 * attempted. Therefore we manually added the enable-master to the
10485 * port phase (it also happens in the function phase)
10487 if (!CHIP_IS_E1x(sc)) {
10488 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
10491 ecore_init_block(sc, BLOCK_ATC, init_phase);
10492 ecore_init_block(sc, BLOCK_DMAE, init_phase);
10493 ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
10494 ecore_init_block(sc, BLOCK_QM, init_phase);
10496 ecore_init_block(sc, BLOCK_TCM, init_phase);
10497 ecore_init_block(sc, BLOCK_UCM, init_phase);
10498 ecore_init_block(sc, BLOCK_CCM, init_phase);
10499 ecore_init_block(sc, BLOCK_XCM, init_phase);
10501 /* QM cid (connection) count */
10502 ecore_qm_init_cid_count(sc, sc->qm_cid_count, INITOP_SET);
10504 if (CNIC_SUPPORT(sc)) {
10505 ecore_init_block(sc, BLOCK_TM, init_phase);
10506 REG_WR(sc, TM_REG_LIN0_SCAN_TIME + port * 4, 20);
10507 REG_WR(sc, TM_REG_LIN0_MAX_ACTIVE_CID + port * 4, 31);
10510 ecore_init_block(sc, BLOCK_DORQ, init_phase);
10512 ecore_init_block(sc, BLOCK_BRB1, init_phase);
10514 if (CHIP_IS_E1H(sc)) {
10516 low = (BNX2X_ONE_PORT(sc) ? 160 : 246);
10517 } else if (sc->mtu > 4096) {
10518 if (BNX2X_ONE_PORT(sc)) {
10522 /* (24*1024 + val*4)/256 */
10523 low = (96 + (val / 64) + ((val % 64) ? 1 : 0));
10526 low = (BNX2X_ONE_PORT(sc) ? 80 : 160);
10528 high = (low + 56); /* 14*1024/256 */
10529 REG_WR(sc, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port * 4, low);
10530 REG_WR(sc, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port * 4, high);
10533 if (CHIP_IS_MODE_4_PORT(sc)) {
10534 REG_WR(sc, SC_PORT(sc) ?
10535 BRB1_REG_MAC_GUARANTIED_1 :
10536 BRB1_REG_MAC_GUARANTIED_0, 40);
10539 ecore_init_block(sc, BLOCK_PRS, init_phase);
10540 if (CHIP_IS_E3B0(sc)) {
10541 if (IS_MF_AFEX(sc)) {
10542 /* configure headers for AFEX mode */
10544 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_1,
10546 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_1,
10548 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_1, 0xA);
10550 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10552 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_0,
10554 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
10557 /* Ovlan exists only if we are in multi-function +
10558 * switch-dependent mode, in switch-independent there
10559 * is no ovlan headers
10561 REG_WR(sc, SC_PORT(sc) ?
10562 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
10563 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10564 (sc->devinfo.mf_info.path_has_ovlan ? 7 : 6));
10568 ecore_init_block(sc, BLOCK_TSDM, init_phase);
10569 ecore_init_block(sc, BLOCK_CSDM, init_phase);
10570 ecore_init_block(sc, BLOCK_USDM, init_phase);
10571 ecore_init_block(sc, BLOCK_XSDM, init_phase);
10573 ecore_init_block(sc, BLOCK_TSEM, init_phase);
10574 ecore_init_block(sc, BLOCK_USEM, init_phase);
10575 ecore_init_block(sc, BLOCK_CSEM, init_phase);
10576 ecore_init_block(sc, BLOCK_XSEM, init_phase);
10578 ecore_init_block(sc, BLOCK_UPB, init_phase);
10579 ecore_init_block(sc, BLOCK_XPB, init_phase);
10581 ecore_init_block(sc, BLOCK_PBF, init_phase);
10583 if (CHIP_IS_E1x(sc)) {
10584 /* configure PBF to work without PAUSE mtu 9000 */
10585 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 0);
10587 /* update threshold */
10588 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, (9040 / 16));
10589 /* update init credit */
10590 REG_WR(sc, PBF_REG_P0_INIT_CRD + port * 4,
10591 (9040 / 16) + 553 - 22);
10593 /* probe changes */
10594 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 1);
10596 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0);
10599 if (CNIC_SUPPORT(sc)) {
10600 ecore_init_block(sc, BLOCK_SRC, init_phase);
10603 ecore_init_block(sc, BLOCK_CDU, init_phase);
10604 ecore_init_block(sc, BLOCK_CFC, init_phase);
10605 ecore_init_block(sc, BLOCK_HC, init_phase);
10606 ecore_init_block(sc, BLOCK_IGU, init_phase);
10607 ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
10608 /* init aeu_mask_attn_func_0/1:
10609 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
10610 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
10611 * bits 4-7 are used for "per vn group attention" */
10612 val = IS_MF(sc) ? 0xF7 : 0x7;
10614 REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, val);
10616 ecore_init_block(sc, BLOCK_NIG, init_phase);
10618 if (!CHIP_IS_E1x(sc)) {
10619 /* Bit-map indicating which L2 hdrs may appear after the
10620 * basic Ethernet header
10622 if (IS_MF_AFEX(sc)) {
10623 REG_WR(sc, SC_PORT(sc) ?
10624 NIG_REG_P1_HDRS_AFTER_BASIC :
10625 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
10627 REG_WR(sc, SC_PORT(sc) ?
10628 NIG_REG_P1_HDRS_AFTER_BASIC :
10629 NIG_REG_P0_HDRS_AFTER_BASIC,
10630 IS_MF_SD(sc) ? 7 : 6);
10633 if (CHIP_IS_E3(sc)) {
10634 REG_WR(sc, SC_PORT(sc) ?
10635 NIG_REG_LLH1_MF_MODE :
10636 NIG_REG_LLH_MF_MODE, IS_MF(sc));
10639 if (!CHIP_IS_E3(sc)) {
10640 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1);
10643 /* 0x2 disable mf_ov, 0x1 enable */
10644 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port * 4,
10645 (IS_MF_SD(sc) ? 0x1 : 0x2));
10647 if (!CHIP_IS_E1x(sc)) {
10649 switch (sc->devinfo.mf_info.mf_mode) {
10650 case MULTI_FUNCTION_SD:
10653 case MULTI_FUNCTION_SI:
10654 case MULTI_FUNCTION_AFEX:
10659 REG_WR(sc, (SC_PORT(sc) ? NIG_REG_LLH1_CLS_TYPE :
10660 NIG_REG_LLH0_CLS_TYPE), val);
10662 REG_WR(sc, NIG_REG_LLFC_ENABLE_0 + port * 4, 0);
10663 REG_WR(sc, NIG_REG_LLFC_OUT_EN_0 + port * 4, 0);
10664 REG_WR(sc, NIG_REG_PAUSE_ENABLE_0 + port * 4, 1);
10666 /* If SPIO5 is set to generate interrupts, enable it for this port */
10667 val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
10668 if (val & MISC_SPIO_SPIO5) {
10669 uint32_t reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
10670 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
10671 val = REG_RD(sc, reg_addr);
10672 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
10673 REG_WR(sc, reg_addr, val);
10680 bnx2x_flr_clnup_reg_poll(struct bnx2x_softc *sc, uint32_t reg,
10681 uint32_t expected, uint32_t poll_count)
10683 uint32_t cur_cnt = poll_count;
10686 while ((val = REG_RD(sc, reg)) != expected && cur_cnt--) {
10687 DELAY(FLR_WAIT_INTERVAL);
10694 bnx2x_flr_clnup_poll_hw_counter(struct bnx2x_softc *sc, uint32_t reg,
10695 __rte_unused const char *msg, uint32_t poll_cnt)
10697 uint32_t val = bnx2x_flr_clnup_reg_poll(sc, reg, 0, poll_cnt);
10700 PMD_DRV_LOG(NOTICE, "%s usage count=%d", msg, val);
10707 /* Common routines with VF FLR cleanup */
10708 static uint32_t bnx2x_flr_clnup_poll_count(struct bnx2x_softc *sc)
10710 /* adjust polling timeout */
10711 if (CHIP_REV_IS_EMUL(sc)) {
10712 return FLR_POLL_CNT * 2000;
10715 if (CHIP_REV_IS_FPGA(sc)) {
10716 return FLR_POLL_CNT * 120;
10719 return FLR_POLL_CNT;
10722 static int bnx2x_poll_hw_usage_counters(struct bnx2x_softc *sc, uint32_t poll_cnt)
10724 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
10725 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10726 CFC_REG_NUM_LCIDS_INSIDE_PF,
10727 "CFC PF usage counter timed out",
10732 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
10733 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10734 DORQ_REG_PF_USAGE_CNT,
10735 "DQ PF usage counter timed out",
10740 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
10741 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10742 QM_REG_PF_USG_CNT_0 + 4 * SC_FUNC(sc),
10743 "QM PF usage counter timed out",
10748 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
10749 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10750 TM_REG_LIN0_VNIC_UC + 4 * SC_PORT(sc),
10751 "Timers VNIC usage counter timed out",
10756 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10757 TM_REG_LIN0_NUM_SCANS +
10759 "Timers NUM_SCANS usage counter timed out",
10764 /* Wait DMAE PF usage counter to zero */
10765 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10766 dmae_reg_go_c[INIT_DMAE_C(sc)],
10767 "DMAE dommand register timed out",
10775 #define OP_GEN_PARAM(param) \
10776 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
10777 #define OP_GEN_TYPE(type) \
10778 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
10779 #define OP_GEN_AGG_VECT(index) \
10780 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
10783 bnx2x_send_final_clnup(struct bnx2x_softc *sc, uint8_t clnup_func,
10786 uint32_t op_gen_command = 0;
10787 uint32_t comp_addr = (BAR_CSTRORM_INTMEM +
10788 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func));
10791 if (REG_RD(sc, comp_addr)) {
10792 PMD_DRV_LOG(NOTICE,
10793 "Cleanup complete was not 0 before sending");
10797 op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
10798 op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
10799 op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
10800 op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
10802 REG_WR(sc, XSDM_REG_OPERATION_GEN, op_gen_command);
10804 if (bnx2x_flr_clnup_reg_poll(sc, comp_addr, 1, poll_cnt) != 1) {
10805 PMD_DRV_LOG(NOTICE, "FW final cleanup did not succeed");
10806 PMD_DRV_LOG(DEBUG, "At timeout completion address contained %x",
10807 (REG_RD(sc, comp_addr)));
10808 rte_panic("FLR cleanup failed");
10812 /* Zero completion for nxt FLR */
10813 REG_WR(sc, comp_addr, 0);
10819 bnx2x_pbf_pN_buf_flushed(struct bnx2x_softc *sc, struct pbf_pN_buf_regs *regs,
10820 uint32_t poll_count)
10822 uint32_t init_crd, crd, crd_start, crd_freed, crd_freed_start;
10823 uint32_t cur_cnt = poll_count;
10825 crd_freed = crd_freed_start = REG_RD(sc, regs->crd_freed);
10826 crd = crd_start = REG_RD(sc, regs->crd);
10827 init_crd = REG_RD(sc, regs->init_crd);
10829 while ((crd != init_crd) &&
10830 ((uint32_t) ((int32_t) crd_freed - (int32_t) crd_freed_start) <
10831 (init_crd - crd_start))) {
10833 DELAY(FLR_WAIT_INTERVAL);
10834 crd = REG_RD(sc, regs->crd);
10835 crd_freed = REG_RD(sc, regs->crd_freed);
10843 bnx2x_pbf_pN_cmd_flushed(struct bnx2x_softc *sc, struct pbf_pN_cmd_regs *regs,
10844 uint32_t poll_count)
10846 uint32_t occup, to_free, freed, freed_start;
10847 uint32_t cur_cnt = poll_count;
10849 occup = to_free = REG_RD(sc, regs->lines_occup);
10850 freed = freed_start = REG_RD(sc, regs->lines_freed);
10853 ((uint32_t) ((int32_t) freed - (int32_t) freed_start) <
10856 DELAY(FLR_WAIT_INTERVAL);
10857 occup = REG_RD(sc, regs->lines_occup);
10858 freed = REG_RD(sc, regs->lines_freed);
10865 static void bnx2x_tx_hw_flushed(struct bnx2x_softc *sc, uint32_t poll_count)
10867 struct pbf_pN_cmd_regs cmd_regs[] = {
10868 {0, (CHIP_IS_E3B0(sc)) ?
10869 PBF_REG_TQ_OCCUPANCY_Q0 : PBF_REG_P0_TQ_OCCUPANCY,
10870 (CHIP_IS_E3B0(sc)) ?
10871 PBF_REG_TQ_LINES_FREED_CNT_Q0 : PBF_REG_P0_TQ_LINES_FREED_CNT},
10872 {1, (CHIP_IS_E3B0(sc)) ?
10873 PBF_REG_TQ_OCCUPANCY_Q1 : PBF_REG_P1_TQ_OCCUPANCY,
10874 (CHIP_IS_E3B0(sc)) ?
10875 PBF_REG_TQ_LINES_FREED_CNT_Q1 : PBF_REG_P1_TQ_LINES_FREED_CNT},
10876 {4, (CHIP_IS_E3B0(sc)) ?
10877 PBF_REG_TQ_OCCUPANCY_LB_Q : PBF_REG_P4_TQ_OCCUPANCY,
10878 (CHIP_IS_E3B0(sc)) ?
10879 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
10880 PBF_REG_P4_TQ_LINES_FREED_CNT}
10883 struct pbf_pN_buf_regs buf_regs[] = {
10884 {0, (CHIP_IS_E3B0(sc)) ?
10885 PBF_REG_INIT_CRD_Q0 : PBF_REG_P0_INIT_CRD,
10886 (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q0 : PBF_REG_P0_CREDIT,
10887 (CHIP_IS_E3B0(sc)) ?
10888 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
10889 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
10890 {1, (CHIP_IS_E3B0(sc)) ?
10891 PBF_REG_INIT_CRD_Q1 : PBF_REG_P1_INIT_CRD,
10892 (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q1 : PBF_REG_P1_CREDIT,
10893 (CHIP_IS_E3B0(sc)) ?
10894 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
10895 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
10896 {4, (CHIP_IS_E3B0(sc)) ?
10897 PBF_REG_INIT_CRD_LB_Q : PBF_REG_P4_INIT_CRD,
10898 (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_LB_Q : PBF_REG_P4_CREDIT,
10899 (CHIP_IS_E3B0(sc)) ?
10900 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
10901 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
10906 /* Verify the command queues are flushed P0, P1, P4 */
10907 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) {
10908 bnx2x_pbf_pN_cmd_flushed(sc, &cmd_regs[i], poll_count);
10911 /* Verify the transmission buffers are flushed P0, P1, P4 */
10912 for (i = 0; i < ARRAY_SIZE(buf_regs); i++) {
10913 bnx2x_pbf_pN_buf_flushed(sc, &buf_regs[i], poll_count);
10917 static void bnx2x_hw_enable_status(struct bnx2x_softc *sc)
10919 __rte_unused uint32_t val;
10921 val = REG_RD(sc, CFC_REG_WEAK_ENABLE_PF);
10922 PMD_DRV_LOG(DEBUG, "CFC_REG_WEAK_ENABLE_PF is 0x%x", val);
10924 val = REG_RD(sc, PBF_REG_DISABLE_PF);
10925 PMD_DRV_LOG(DEBUG, "PBF_REG_DISABLE_PF is 0x%x", val);
10927 val = REG_RD(sc, IGU_REG_PCI_PF_MSI_EN);
10928 PMD_DRV_LOG(DEBUG, "IGU_REG_PCI_PF_MSI_EN is 0x%x", val);
10930 val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_EN);
10931 PMD_DRV_LOG(DEBUG, "IGU_REG_PCI_PF_MSIX_EN is 0x%x", val);
10933 val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
10934 PMD_DRV_LOG(DEBUG, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x", val);
10936 val = REG_RD(sc, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
10937 PMD_DRV_LOG(DEBUG, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x", val);
10939 val = REG_RD(sc, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
10940 PMD_DRV_LOG(DEBUG, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x", val);
10942 val = REG_RD(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
10943 PMD_DRV_LOG(DEBUG, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x",
10948 * bnx2x_pf_flr_clnup
10949 * a. re-enable target read on the PF
10950 * b. poll cfc per function usgae counter
10951 * c. poll the qm perfunction usage counter
10952 * d. poll the tm per function usage counter
10953 * e. poll the tm per function scan-done indication
10954 * f. clear the dmae channel associated wit hthe PF
10955 * g. zero the igu 'trailing edge' and 'leading edge' regs (attentions)
10956 * h. call the common flr cleanup code with -1 (pf indication)
10958 static int bnx2x_pf_flr_clnup(struct bnx2x_softc *sc)
10960 uint32_t poll_cnt = bnx2x_flr_clnup_poll_count(sc);
10962 /* Re-enable PF target read access */
10963 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
10965 /* Poll HW usage counters */
10966 if (bnx2x_poll_hw_usage_counters(sc, poll_cnt)) {
10970 /* Zero the igu 'trailing edge' and 'leading edge' */
10972 /* Send the FW cleanup command */
10973 if (bnx2x_send_final_clnup(sc, (uint8_t) SC_FUNC(sc), poll_cnt)) {
10979 /* Verify TX hw is flushed */
10980 bnx2x_tx_hw_flushed(sc, poll_cnt);
10982 /* Wait 100ms (not adjusted according to platform) */
10985 /* Verify no pending pci transactions */
10986 if (bnx2x_is_pcie_pending(sc)) {
10987 PMD_DRV_LOG(NOTICE, "PCIE Transactions still pending");
10991 bnx2x_hw_enable_status(sc);
10994 * Master enable - Due to WB DMAE writes performed before this
10995 * register is re-initialized as part of the regular function init
10997 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11002 static int bnx2x_init_hw_func(struct bnx2x_softc *sc)
11004 int port = SC_PORT(sc);
11005 int func = SC_FUNC(sc);
11006 int init_phase = PHASE_PF0 + func;
11007 struct ecore_ilt *ilt = sc->ilt;
11008 uint16_t cdu_ilt_start;
11009 uint32_t addr, val;
11010 uint32_t main_mem_base, main_mem_size, main_mem_prty_clr;
11011 int main_mem_width, rc;
11014 PMD_DRV_LOG(DEBUG, "starting func init for func %d", func);
11017 if (!CHIP_IS_E1x(sc)) {
11018 rc = bnx2x_pf_flr_clnup(sc);
11020 PMD_DRV_LOG(NOTICE, "FLR cleanup failed!");
11025 /* set MSI reconfigure capability */
11026 if (sc->devinfo.int_block == INT_BLOCK_HC) {
11027 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
11028 val = REG_RD(sc, addr);
11029 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
11030 REG_WR(sc, addr, val);
11033 ecore_init_block(sc, BLOCK_PXP, init_phase);
11034 ecore_init_block(sc, BLOCK_PXP2, init_phase);
11037 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
11039 for (i = 0; i < L2_ILT_LINES(sc); i++) {
11040 ilt->lines[cdu_ilt_start + i].page = sc->context[i].vcxt;
11041 ilt->lines[cdu_ilt_start + i].page_mapping =
11042 (rte_iova_t)sc->context[i].vcxt_dma.paddr;
11043 ilt->lines[cdu_ilt_start + i].size = sc->context[i].size;
11045 ecore_ilt_init_op(sc, INITOP_SET);
11047 REG_WR(sc, PRS_REG_NIC_MODE, 1);
11049 if (!CHIP_IS_E1x(sc)) {
11050 uint32_t pf_conf = IGU_PF_CONF_FUNC_EN;
11052 /* Turn on a single ISR mode in IGU if driver is going to use
11055 if ((sc->interrupt_mode != INTR_MODE_MSIX)
11056 || (sc->interrupt_mode != INTR_MODE_SINGLE_MSIX)) {
11057 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
11061 * Timers workaround bug: function init part.
11062 * Need to wait 20msec after initializing ILT,
11063 * needed to make sure there are no requests in
11064 * one of the PXP internal queues with "old" ILT addresses
11069 * Master enable - Due to WB DMAE writes performed before this
11070 * register is re-initialized as part of the regular function
11073 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11074 /* Enable the function in IGU */
11075 REG_WR(sc, IGU_REG_PF_CONFIGURATION, pf_conf);
11078 sc->dmae_ready = 1;
11080 ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
11082 if (!CHIP_IS_E1x(sc))
11083 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
11085 ecore_init_block(sc, BLOCK_ATC, init_phase);
11086 ecore_init_block(sc, BLOCK_DMAE, init_phase);
11087 ecore_init_block(sc, BLOCK_NIG, init_phase);
11088 ecore_init_block(sc, BLOCK_SRC, init_phase);
11089 ecore_init_block(sc, BLOCK_MISC, init_phase);
11090 ecore_init_block(sc, BLOCK_TCM, init_phase);
11091 ecore_init_block(sc, BLOCK_UCM, init_phase);
11092 ecore_init_block(sc, BLOCK_CCM, init_phase);
11093 ecore_init_block(sc, BLOCK_XCM, init_phase);
11094 ecore_init_block(sc, BLOCK_TSEM, init_phase);
11095 ecore_init_block(sc, BLOCK_USEM, init_phase);
11096 ecore_init_block(sc, BLOCK_CSEM, init_phase);
11097 ecore_init_block(sc, BLOCK_XSEM, init_phase);
11099 if (!CHIP_IS_E1x(sc))
11100 REG_WR(sc, QM_REG_PF_EN, 1);
11102 if (!CHIP_IS_E1x(sc)) {
11103 REG_WR(sc, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11104 REG_WR(sc, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11105 REG_WR(sc, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11106 REG_WR(sc, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11108 ecore_init_block(sc, BLOCK_QM, init_phase);
11110 ecore_init_block(sc, BLOCK_TM, init_phase);
11111 ecore_init_block(sc, BLOCK_DORQ, init_phase);
11113 ecore_init_block(sc, BLOCK_BRB1, init_phase);
11114 ecore_init_block(sc, BLOCK_PRS, init_phase);
11115 ecore_init_block(sc, BLOCK_TSDM, init_phase);
11116 ecore_init_block(sc, BLOCK_CSDM, init_phase);
11117 ecore_init_block(sc, BLOCK_USDM, init_phase);
11118 ecore_init_block(sc, BLOCK_XSDM, init_phase);
11119 ecore_init_block(sc, BLOCK_UPB, init_phase);
11120 ecore_init_block(sc, BLOCK_XPB, init_phase);
11121 ecore_init_block(sc, BLOCK_PBF, init_phase);
11122 if (!CHIP_IS_E1x(sc))
11123 REG_WR(sc, PBF_REG_DISABLE_PF, 0);
11125 ecore_init_block(sc, BLOCK_CDU, init_phase);
11127 ecore_init_block(sc, BLOCK_CFC, init_phase);
11129 if (!CHIP_IS_E1x(sc))
11130 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 1);
11133 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
11134 REG_WR(sc, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8, OVLAN(sc));
11137 ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
11139 /* HC init per function */
11140 if (sc->devinfo.int_block == INT_BLOCK_HC) {
11141 if (CHIP_IS_E1H(sc)) {
11142 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11144 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11145 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11147 ecore_init_block(sc, BLOCK_HC, init_phase);
11150 uint32_t num_segs, sb_idx, prod_offset;
11152 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11154 if (!CHIP_IS_E1x(sc)) {
11155 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11156 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11159 ecore_init_block(sc, BLOCK_IGU, init_phase);
11161 if (!CHIP_IS_E1x(sc)) {
11165 * E2 mode: address 0-135 match to the mapping memory;
11166 * 136 - PF0 default prod; 137 - PF1 default prod;
11167 * 138 - PF2 default prod; 139 - PF3 default prod;
11168 * 140 - PF0 attn prod; 141 - PF1 attn prod;
11169 * 142 - PF2 attn prod; 143 - PF3 attn prod;
11170 * 144-147 reserved.
11172 * E1.5 mode - In backward compatible mode;
11173 * for non default SB; each even line in the memory
11174 * holds the U producer and each odd line hold
11175 * the C producer. The first 128 producers are for
11176 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
11177 * producers are for the DSB for each PF.
11178 * Each PF has five segments: (the order inside each
11179 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
11180 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
11181 * 144-147 attn prods;
11183 /* non-default-status-blocks */
11184 num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11185 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
11186 for (sb_idx = 0; sb_idx < sc->igu_sb_cnt; sb_idx++) {
11187 prod_offset = (sc->igu_base_sb + sb_idx) *
11190 for (i = 0; i < num_segs; i++) {
11191 addr = IGU_REG_PROD_CONS_MEMORY +
11192 (prod_offset + i) * 4;
11193 REG_WR(sc, addr, 0);
11195 /* send consumer update with value 0 */
11196 bnx2x_ack_sb(sc, sc->igu_base_sb + sb_idx,
11197 USTORM_ID, 0, IGU_INT_NOP, 1);
11198 bnx2x_igu_clear_sb(sc, sc->igu_base_sb + sb_idx);
11201 /* default-status-blocks */
11202 num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11203 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
11205 if (CHIP_IS_MODE_4_PORT(sc))
11206 dsb_idx = SC_FUNC(sc);
11208 dsb_idx = SC_VN(sc);
11210 prod_offset = (CHIP_INT_MODE_IS_BC(sc) ?
11211 IGU_BC_BASE_DSB_PROD + dsb_idx :
11212 IGU_NORM_BASE_DSB_PROD + dsb_idx);
11215 * igu prods come in chunks of E1HVN_MAX (4) -
11216 * does not matters what is the current chip mode
11218 for (i = 0; i < (num_segs * E1HVN_MAX); i += E1HVN_MAX) {
11219 addr = IGU_REG_PROD_CONS_MEMORY +
11220 (prod_offset + i) * 4;
11221 REG_WR(sc, addr, 0);
11223 /* send consumer update with 0 */
11224 if (CHIP_INT_MODE_IS_BC(sc)) {
11225 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11226 USTORM_ID, 0, IGU_INT_NOP, 1);
11227 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11228 CSTORM_ID, 0, IGU_INT_NOP, 1);
11229 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11230 XSTORM_ID, 0, IGU_INT_NOP, 1);
11231 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11232 TSTORM_ID, 0, IGU_INT_NOP, 1);
11233 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11234 ATTENTION_ID, 0, IGU_INT_NOP, 1);
11236 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11237 USTORM_ID, 0, IGU_INT_NOP, 1);
11238 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11239 ATTENTION_ID, 0, IGU_INT_NOP, 1);
11241 bnx2x_igu_clear_sb(sc, sc->igu_dsb_id);
11243 /* !!! these should become driver const once
11244 rf-tool supports split-68 const */
11245 REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
11246 REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
11247 REG_WR(sc, IGU_REG_SB_MASK_LSB, 0);
11248 REG_WR(sc, IGU_REG_SB_MASK_MSB, 0);
11249 REG_WR(sc, IGU_REG_PBA_STATUS_LSB, 0);
11250 REG_WR(sc, IGU_REG_PBA_STATUS_MSB, 0);
11254 /* Reset PCIE errors for debug */
11255 REG_WR(sc, 0x2114, 0xffffffff);
11256 REG_WR(sc, 0x2120, 0xffffffff);
11258 if (CHIP_IS_E1x(sc)) {
11259 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords */
11260 main_mem_base = HC_REG_MAIN_MEMORY +
11261 SC_PORT(sc) * (main_mem_size * 4);
11262 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
11263 main_mem_width = 8;
11265 val = REG_RD(sc, main_mem_prty_clr);
11268 "Parity errors in HC block during function init (0x%x)!",
11272 /* Clear "false" parity errors in MSI-X table */
11273 for (i = main_mem_base;
11274 i < main_mem_base + main_mem_size * 4;
11275 i += main_mem_width) {
11276 bnx2x_read_dmae(sc, i, main_mem_width / 4);
11277 bnx2x_write_dmae(sc, BNX2X_SP_MAPPING(sc, wb_data),
11278 i, main_mem_width / 4);
11280 /* Clear HC parity attention */
11281 REG_RD(sc, main_mem_prty_clr);
11284 /* Enable STORMs SP logging */
11285 REG_WR8(sc, BAR_USTRORM_INTMEM +
11286 USTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11287 REG_WR8(sc, BAR_TSTRORM_INTMEM +
11288 TSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11289 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11290 CSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11291 REG_WR8(sc, BAR_XSTRORM_INTMEM +
11292 XSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11294 elink_phy_probe(&sc->link_params);
11299 static void bnx2x_link_reset(struct bnx2x_softc *sc)
11301 if (!BNX2X_NOMCP(sc)) {
11302 elink_lfa_reset(&sc->link_params, &sc->link_vars);
11304 if (!CHIP_REV_IS_SLOW(sc)) {
11305 PMD_DRV_LOG(WARNING,
11306 "Bootcode is missing - cannot reset link");
11311 static void bnx2x_reset_port(struct bnx2x_softc *sc)
11313 int port = SC_PORT(sc);
11316 /* reset physical Link */
11317 bnx2x_link_reset(sc);
11319 REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
11321 /* Do not rcv packets to BRB */
11322 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + port * 4, 0x0);
11323 /* Do not direct rcv packets that are not for MCP to the BRB */
11324 REG_WR(sc, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
11325 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
11327 /* Configure AEU */
11328 REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, 0);
11332 /* Check for BRB port occupancy */
11333 val = REG_RD(sc, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port * 4);
11336 "BRB1 is not empty, %d blocks are occupied", val);
11340 static void bnx2x_ilt_wr(struct bnx2x_softc *sc, uint32_t index, rte_iova_t addr)
11343 uint32_t wb_write[2];
11345 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index * 8;
11347 wb_write[0] = ONCHIP_ADDR1(addr);
11348 wb_write[1] = ONCHIP_ADDR2(addr);
11349 REG_WR_DMAE(sc, reg, wb_write, 2);
11352 static void bnx2x_clear_func_ilt(struct bnx2x_softc *sc, uint32_t func)
11354 uint32_t i, base = FUNC_ILT_BASE(func);
11355 for (i = base; i < base + ILT_PER_FUNC; i++) {
11356 bnx2x_ilt_wr(sc, i, 0);
11360 static void bnx2x_reset_func(struct bnx2x_softc *sc)
11362 struct bnx2x_fastpath *fp;
11363 int port = SC_PORT(sc);
11364 int func = SC_FUNC(sc);
11367 /* Disable the function in the FW */
11368 REG_WR8(sc, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
11369 REG_WR8(sc, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
11370 REG_WR8(sc, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
11371 REG_WR8(sc, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
11374 FOR_EACH_ETH_QUEUE(sc, i) {
11376 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11377 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
11382 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11383 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), SB_DISABLED);
11385 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) {
11386 REG_WR(sc, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
11390 /* Configure IGU */
11391 if (sc->devinfo.int_block == INT_BLOCK_HC) {
11392 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11393 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11395 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11396 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11399 if (CNIC_LOADED(sc)) {
11400 /* Disable Timer scan */
11401 REG_WR(sc, TM_REG_EN_LINEAR0_TIMER + port * 4, 0);
11403 * Wait for at least 10ms and up to 2 second for the timers
11406 for (i = 0; i < 200; i++) {
11408 if (!REG_RD(sc, TM_REG_LIN0_SCAN_ON + port * 4))
11414 bnx2x_clear_func_ilt(sc, func);
11417 * Timers workaround bug for E2: if this is vnic-3,
11418 * we need to set the entire ilt range for this timers.
11420 if (!CHIP_IS_E1x(sc) && SC_VN(sc) == 3) {
11421 struct ilt_client_info ilt_cli;
11422 /* use dummy TM client */
11423 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
11425 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
11426 ilt_cli.client_num = ILT_CLIENT_TM;
11428 ecore_ilt_boundry_init_op(sc, &ilt_cli, 0);
11431 /* this assumes that reset_port() called before reset_func() */
11432 if (!CHIP_IS_E1x(sc)) {
11433 bnx2x_pf_disable(sc);
11436 sc->dmae_ready = 0;
11439 static void bnx2x_release_firmware(struct bnx2x_softc *sc)
11441 rte_free(sc->init_ops);
11442 rte_free(sc->init_ops_offsets);
11443 rte_free(sc->init_data);
11444 rte_free(sc->iro_array);
11447 static int bnx2x_init_firmware(struct bnx2x_softc *sc)
11450 uint8_t *p = sc->firmware;
11453 for (i = 0; i < 24; ++i)
11454 off[i] = rte_be_to_cpu_32(*((uint32_t *) sc->firmware + i));
11457 sc->init_ops = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11460 bnx2x_data_to_init_ops(p + off[1], sc->init_ops, len);
11463 sc->init_ops_offsets = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11464 if (!sc->init_ops_offsets)
11466 bnx2x_data_to_init_offsets(p + off[3], sc->init_ops_offsets, len);
11469 sc->init_data = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11470 if (!sc->init_data)
11472 bnx2x_data_to_init_data(p + off[5], sc->init_data, len);
11474 sc->tsem_int_table_data = p + off[7];
11475 sc->tsem_pram_data = p + off[9];
11476 sc->usem_int_table_data = p + off[11];
11477 sc->usem_pram_data = p + off[13];
11478 sc->csem_int_table_data = p + off[15];
11479 sc->csem_pram_data = p + off[17];
11480 sc->xsem_int_table_data = p + off[19];
11481 sc->xsem_pram_data = p + off[21];
11484 sc->iro_array = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11485 if (!sc->iro_array)
11487 bnx2x_data_to_iro_array(p + off[23], sc->iro_array, len);
11492 bnx2x_release_firmware(sc);
11496 static int cut_gzip_prefix(const uint8_t * zbuf, int len)
11498 #define MIN_PREFIX_SIZE (10)
11500 int n = MIN_PREFIX_SIZE;
11503 if (!(zbuf[0] == 0x1f && zbuf[1] == 0x8b && zbuf[2] == Z_DEFLATED) ||
11504 len <= MIN_PREFIX_SIZE) {
11508 /* optional extra fields are present */
11509 if (zbuf[3] & 0x4) {
11516 /* file name is present */
11517 if (zbuf[3] & 0x8) {
11518 while ((zbuf[n++] != 0) && (n < len)) ;
11524 static int ecore_gunzip(struct bnx2x_softc *sc, const uint8_t * zbuf, int len)
11527 int data_begin = cut_gzip_prefix(zbuf, len);
11529 PMD_DRV_LOG(DEBUG, "ecore_gunzip %d", len);
11531 if (data_begin <= 0) {
11532 PMD_DRV_LOG(NOTICE, "bad gzip prefix");
11536 memset(&zlib_stream, 0, sizeof(zlib_stream));
11537 zlib_stream.next_in = zbuf + data_begin;
11538 zlib_stream.avail_in = len - data_begin;
11539 zlib_stream.next_out = sc->gz_buf;
11540 zlib_stream.avail_out = FW_BUF_SIZE;
11542 ret = inflateInit2(&zlib_stream, -MAX_WBITS);
11544 PMD_DRV_LOG(NOTICE, "zlib inflateInit2 error");
11548 ret = inflate(&zlib_stream, Z_FINISH);
11549 if ((ret != Z_STREAM_END) && (ret != Z_OK)) {
11550 PMD_DRV_LOG(NOTICE, "zlib inflate error: %d %s", ret,
11554 sc->gz_outlen = zlib_stream.total_out;
11555 if (sc->gz_outlen & 0x3) {
11556 PMD_DRV_LOG(NOTICE, "firmware is not aligned. gz_outlen == %d",
11559 sc->gz_outlen >>= 2;
11561 inflateEnd(&zlib_stream);
11563 if (ret == Z_STREAM_END)
11570 ecore_write_dmae_phys_len(struct bnx2x_softc *sc, rte_iova_t phys_addr,
11571 uint32_t addr, uint32_t len)
11573 bnx2x_write_dmae_phys_len(sc, phys_addr, addr, len);
11577 ecore_storm_memset_struct(struct bnx2x_softc *sc, uint32_t addr, size_t size,
11581 for (i = 0; i < size / 4; i++) {
11582 REG_WR(sc, addr + (i * 4), data[i]);
11586 static const char *get_ext_phy_type(uint32_t ext_phy_type)
11588 uint32_t phy_type_idx = ext_phy_type >> 8;
11589 static const char *types[] =
11590 { "DIRECT", "BNX2X-8071", "BNX2X-8072", "BNX2X-8073",
11591 "BNX2X-8705", "BNX2X-8706", "BNX2X-8726", "BNX2X-8481", "SFX-7101",
11593 "BNX2X-8727-NOC", "BNX2X-84823", "NOT_CONN", "FAILURE"
11596 if (phy_type_idx < 12)
11597 return types[phy_type_idx];
11598 else if (PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN == ext_phy_type)
11604 static const char *get_state(uint32_t state)
11606 uint32_t state_idx = state >> 12;
11607 static const char *states[] = { "CLOSED", "OPENING_WAIT4_LOAD",
11608 "OPENING_WAIT4_PORT", "OPEN", "CLOSING_WAIT4_HALT",
11609 "CLOSING_WAIT4_DELETE", "CLOSING_WAIT4_UNLOAD",
11610 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
11611 "UNKNOWN", "DISABLED", "DIAG", "ERROR", "UNDEFINED"
11614 if (state_idx <= 0xF)
11615 return states[state_idx];
11617 return states[0x10];
11620 static const char *get_recovery_state(uint32_t state)
11622 static const char *states[] = { "NONE", "DONE", "INIT",
11623 "WAIT", "FAILED", "NIC_LOADING"
11625 return states[state];
11628 static const char *get_rx_mode(uint32_t mode)
11630 static const char *modes[] = { "NONE", "NORMAL", "ALLMULTI",
11631 "PROMISC", "MAX_MULTICAST", "ERROR"
11635 return modes[mode];
11636 else if (BNX2X_MAX_MULTICAST == mode)
11642 #define BNX2X_INFO_STR_MAX 256
11643 static const char *get_bnx2x_flags(uint32_t flags)
11646 static const char *flag[] = { "ONE_PORT ", "NO_ISCSI ",
11647 "NO_FCOE ", "NO_WOL ", "USING_DAC ", "USING_MSIX ",
11648 "USING_MSI ", "DISABLE_MSI ", "UNKNOWN ", "NO_MCP ",
11649 "SAFC_TX_FLAG ", "MF_FUNC_DIS ", "TX_SWITCHING "
11651 static char flag_str[BNX2X_INFO_STR_MAX];
11652 memset(flag_str, 0, BNX2X_INFO_STR_MAX);
11654 for (i = 0; i < 5; i++)
11655 if (flags & (1 << i)) {
11656 strcat(flag_str, flag[i]);
11660 static char unknown[BNX2X_INFO_STR_MAX];
11661 snprintf(unknown, 32, "Unknown flag mask %x", flags);
11662 strcat(flag_str, unknown);
11668 * Prints useful adapter info.
11670 void bnx2x_print_adapter_info(struct bnx2x_softc *sc)
11673 __rte_unused uint32_t ext_phy_type;
11675 PMD_INIT_FUNC_TRACE();
11676 if (sc->link_vars.phy_flags & PHY_XGXS_FLAG)
11677 ext_phy_type = ELINK_XGXS_EXT_PHY_TYPE(REG_RD(sc,
11682 dev_info.port_hw_config
11683 [0].external_phy_config)));
11685 ext_phy_type = ELINK_SERDES_EXT_PHY_TYPE(REG_RD(sc,
11691 dev_info.port_hw_config
11692 [0].external_phy_config)));
11694 PMD_INIT_LOG(DEBUG, "\n\n===================================\n");
11695 /* Hardware chip info. */
11696 PMD_INIT_LOG(DEBUG, "%12s : %#08x", "ASIC", sc->devinfo.chip_id);
11697 PMD_INIT_LOG(DEBUG, "%12s : %c%d", "Rev", (CHIP_REV(sc) >> 12) + 'A',
11698 (CHIP_METAL(sc) >> 4));
11701 PMD_INIT_LOG(DEBUG, "%12s : %d, ", "Bus PCIe", sc->devinfo.pcie_link_width);
11702 switch (sc->devinfo.pcie_link_speed) {
11704 PMD_INIT_LOG(DEBUG, "%23s", "2.5 Gbps");
11707 PMD_INIT_LOG(DEBUG, "%21s", "5 Gbps");
11710 PMD_INIT_LOG(DEBUG, "%21s", "8 Gbps");
11713 PMD_INIT_LOG(DEBUG, "%33s", "Unknown link speed");
11716 /* Device features. */
11717 PMD_INIT_LOG(DEBUG, "%12s : ", "Flags");
11719 /* Miscellaneous flags. */
11720 if (sc->devinfo.pcie_cap_flags & BNX2X_MSI_CAPABLE_FLAG) {
11721 PMD_INIT_LOG(DEBUG, "%18s", "MSI");
11725 if (sc->devinfo.pcie_cap_flags & BNX2X_MSIX_CAPABLE_FLAG) {
11727 PMD_INIT_LOG(DEBUG, "|");
11728 PMD_INIT_LOG(DEBUG, "%20s", "MSI-X");
11733 PMD_INIT_LOG(DEBUG, "%12s : ", "Queues");
11734 switch (sc->sp->rss_rdata.rss_mode) {
11735 case ETH_RSS_MODE_DISABLED:
11736 PMD_INIT_LOG(DEBUG, "%19s", "None");
11738 case ETH_RSS_MODE_REGULAR:
11739 PMD_INIT_LOG(DEBUG, "%18s : %d", "RSS", sc->num_queues);
11742 PMD_INIT_LOG(DEBUG, "%22s", "Unknown");
11747 /* RTE and Driver versions */
11748 PMD_INIT_LOG(DEBUG, "%12s : %s", "DPDK",
11750 PMD_INIT_LOG(DEBUG, "%12s : %s", "Driver",
11751 bnx2x_pmd_version());
11753 /* Firmware versions and device features. */
11754 PMD_INIT_LOG(DEBUG, "%12s : %d.%d.%d",
11756 BNX2X_5710_FW_MAJOR_VERSION,
11757 BNX2X_5710_FW_MINOR_VERSION,
11758 BNX2X_5710_FW_REVISION_VERSION);
11759 PMD_INIT_LOG(DEBUG, "%12s : %s",
11760 "Bootcode", sc->devinfo.bc_ver_str);
11762 PMD_INIT_LOG(DEBUG, "\n\n===================================\n");
11763 PMD_INIT_LOG(DEBUG, "%12s : %u", "Bnx2x Func", sc->pcie_func);
11764 PMD_INIT_LOG(DEBUG, "%12s : %s", "Bnx2x Flags", get_bnx2x_flags(sc->flags));
11765 PMD_INIT_LOG(DEBUG, "%12s : %s", "DMAE Is",
11766 (sc->dmae_ready ? "Ready" : "Not Ready"));
11767 PMD_INIT_LOG(DEBUG, "%12s : %s", "OVLAN", (OVLAN(sc) ? "YES" : "NO"));
11768 PMD_INIT_LOG(DEBUG, "%12s : %s", "MF", (IS_MF(sc) ? "YES" : "NO"));
11769 PMD_INIT_LOG(DEBUG, "%12s : %u", "MTU", sc->mtu);
11770 PMD_INIT_LOG(DEBUG, "%12s : %s", "PHY Type", get_ext_phy_type(ext_phy_type));
11771 PMD_INIT_LOG(DEBUG, "%12s : %x:%x:%x:%x:%x:%x", "MAC Addr",
11772 sc->link_params.mac_addr[0],
11773 sc->link_params.mac_addr[1],
11774 sc->link_params.mac_addr[2],
11775 sc->link_params.mac_addr[3],
11776 sc->link_params.mac_addr[4],
11777 sc->link_params.mac_addr[5]);
11778 PMD_INIT_LOG(DEBUG, "%12s : %s", "RX Mode", get_rx_mode(sc->rx_mode));
11779 PMD_INIT_LOG(DEBUG, "%12s : %s", "State", get_state(sc->state));
11780 if (sc->recovery_state)
11781 PMD_INIT_LOG(DEBUG, "%12s : %s", "Recovery",
11782 get_recovery_state(sc->recovery_state));
11783 PMD_INIT_LOG(DEBUG, "%12s : CQ = %lx, EQ = %lx", "SPQ Left",
11784 sc->cq_spq_left, sc->eq_spq_left);
11785 PMD_INIT_LOG(DEBUG, "%12s : %x", "Switch", sc->link_params.switch_cfg);
11786 PMD_INIT_LOG(DEBUG, "\n\n===================================\n");