1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2007-2013 Broadcom Corporation.
4 * Eric Davis <edavis@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
6 * Gary Zambrano <zambrano@broadcom.com>
8 * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
9 * Copyright (c) 2015-2018 Cavium Inc.
10 * All rights reserved.
14 #define BNX2X_DRIVER_VERSION "1.78.18"
17 #include "bnx2x_vfpf.h"
19 #include "ecore_init.h"
20 #include "ecore_init_ops.h"
22 #include "rte_version.h"
24 #include <sys/types.h>
28 #include <rte_string_fns.h>
30 #define BNX2X_PMD_VER_PREFIX "BNX2X PMD"
31 #define BNX2X_PMD_VERSION_MAJOR 1
32 #define BNX2X_PMD_VERSION_MINOR 1
33 #define BNX2X_PMD_VERSION_REVISION 0
34 #define BNX2X_PMD_VERSION_PATCH 1
36 static inline const char *
37 bnx2x_pmd_version(void)
39 static char version[32];
41 snprintf(version, sizeof(version), "%s %s_%d.%d.%d.%d",
44 BNX2X_PMD_VERSION_MAJOR,
45 BNX2X_PMD_VERSION_MINOR,
46 BNX2X_PMD_VERSION_REVISION,
47 BNX2X_PMD_VERSION_PATCH);
52 static z_stream zlib_stream;
54 #define EVL_VLID_MASK 0x0FFF
56 #define BNX2X_DEF_SB_ATT_IDX 0x0001
57 #define BNX2X_DEF_SB_IDX 0x0002
60 * FLR Support - bnx2x_pf_flr_clnup() is called during nic_load in the per
61 * function HW initialization.
63 #define FLR_WAIT_USEC 10000 /* 10 msecs */
64 #define FLR_WAIT_INTERVAL 50 /* usecs */
65 #define FLR_POLL_CNT (FLR_WAIT_USEC / FLR_WAIT_INTERVAL) /* 200 */
67 struct pbf_pN_buf_regs {
74 struct pbf_pN_cmd_regs {
80 /* resources needed for unloading a previously loaded device */
82 #define BNX2X_PREV_WAIT_NEEDED 1
83 rte_spinlock_t bnx2x_prev_mtx;
84 struct bnx2x_prev_list_node {
85 LIST_ENTRY(bnx2x_prev_list_node) node;
93 static LIST_HEAD(, bnx2x_prev_list_node) bnx2x_prev_list
94 = LIST_HEAD_INITIALIZER(bnx2x_prev_list);
96 static int load_count[2][3] = { { 0 } };
97 /* per-path: 0-common, 1-port0, 2-port1 */
99 static void bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg,
101 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc);
102 static void storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng,
104 static void bnx2x_set_reset_global(struct bnx2x_softc *sc);
105 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc);
106 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine);
107 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc);
108 static uint8_t bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global,
110 static void bnx2x_int_disable(struct bnx2x_softc *sc);
111 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc);
112 static void bnx2x_pf_disable(struct bnx2x_softc *sc);
113 static void bnx2x_update_rx_prod(struct bnx2x_softc *sc,
114 struct bnx2x_fastpath *fp,
115 uint16_t rx_bd_prod, uint16_t rx_cq_prod);
116 static void bnx2x_link_report_locked(struct bnx2x_softc *sc);
117 static void bnx2x_link_report(struct bnx2x_softc *sc);
118 void bnx2x_link_status_update(struct bnx2x_softc *sc);
119 static int bnx2x_alloc_mem(struct bnx2x_softc *sc);
120 static void bnx2x_free_mem(struct bnx2x_softc *sc);
121 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc);
122 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc);
123 static __rte_noinline
124 int bnx2x_nic_load(struct bnx2x_softc *sc);
126 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc);
127 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp);
128 static void bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id,
129 uint8_t storm, uint16_t index, uint8_t op,
132 int bnx2x_test_bit(int nr, volatile unsigned long *addr)
137 res = ((*addr) & (1UL << nr)) != 0;
142 void bnx2x_set_bit(unsigned int nr, volatile unsigned long *addr)
144 __sync_fetch_and_or(addr, (1UL << nr));
147 void bnx2x_clear_bit(int nr, volatile unsigned long *addr)
149 __sync_fetch_and_and(addr, ~(1UL << nr));
152 int bnx2x_test_and_clear_bit(int nr, volatile unsigned long *addr)
154 unsigned long mask = (1UL << nr);
155 return __sync_fetch_and_and(addr, ~mask) & mask;
158 int bnx2x_cmpxchg(volatile int *addr, int old, int new)
160 return __sync_val_compare_and_swap(addr, old, new);
164 bnx2x_dma_alloc(struct bnx2x_softc *sc, size_t size, struct bnx2x_dma *dma,
165 const char *msg, uint32_t align)
167 char mz_name[RTE_MEMZONE_NAMESIZE];
168 const struct rte_memzone *z;
172 snprintf(mz_name, sizeof(mz_name), "bnx2x%d_%s_%" PRIx64, SC_ABS_FUNC(sc), msg,
173 rte_get_timer_cycles());
175 snprintf(mz_name, sizeof(mz_name), "bnx2x%d_%s_%" PRIx64, sc->pcie_device, msg,
176 rte_get_timer_cycles());
178 /* Caller must take care that strlen(mz_name) < RTE_MEMZONE_NAMESIZE */
179 z = rte_memzone_reserve_aligned(mz_name, (uint64_t)size,
181 RTE_MEMZONE_IOVA_CONTIG, align);
183 PMD_DRV_LOG(ERR, sc, "DMA alloc failed for %s", msg);
186 dma->paddr = (uint64_t) z->iova;
187 dma->vaddr = z->addr;
188 dma->mzone = (const void *)z;
190 PMD_DRV_LOG(DEBUG, sc,
191 "%s: virt=%p phys=%" PRIx64, msg, dma->vaddr, dma->paddr);
196 void bnx2x_dma_free(struct bnx2x_dma *dma)
198 if (dma->mzone == NULL)
201 rte_memzone_free((const struct rte_memzone *)dma->mzone);
209 static int bnx2x_acquire_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
211 uint32_t lock_status;
212 uint32_t resource_bit = (1 << resource);
213 int func = SC_FUNC(sc);
214 uint32_t hw_lock_control_reg;
217 #ifndef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
219 PMD_INIT_FUNC_TRACE(sc);
221 PMD_INIT_FUNC_TRACE(sc);
224 /* validate the resource is within range */
225 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
226 PMD_DRV_LOG(NOTICE, sc,
227 "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
233 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
235 hw_lock_control_reg =
236 (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
239 /* validate the resource is not already taken */
240 lock_status = REG_RD(sc, hw_lock_control_reg);
241 if (lock_status & resource_bit) {
242 PMD_DRV_LOG(NOTICE, sc,
243 "resource in use (status 0x%x bit 0x%x)",
244 lock_status, resource_bit);
248 /* try every 5ms for 5 seconds */
249 for (cnt = 0; cnt < 1000; cnt++) {
250 REG_WR(sc, (hw_lock_control_reg + 4), resource_bit);
251 lock_status = REG_RD(sc, hw_lock_control_reg);
252 if (lock_status & resource_bit) {
258 PMD_DRV_LOG(NOTICE, sc, "Resource 0x%x resource_bit 0x%x lock timeout!",
259 resource, resource_bit);
263 static int bnx2x_release_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
265 uint32_t lock_status;
266 uint32_t resource_bit = (1 << resource);
267 int func = SC_FUNC(sc);
268 uint32_t hw_lock_control_reg;
270 #ifndef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
272 PMD_INIT_FUNC_TRACE(sc);
274 PMD_INIT_FUNC_TRACE(sc);
277 /* validate the resource is within range */
278 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
279 PMD_DRV_LOG(NOTICE, sc,
280 "(resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE)"
281 " resource_bit 0x%x", resource, resource_bit);
286 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
288 hw_lock_control_reg =
289 (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
292 /* validate the resource is currently taken */
293 lock_status = REG_RD(sc, hw_lock_control_reg);
294 if (!(lock_status & resource_bit)) {
295 PMD_DRV_LOG(NOTICE, sc,
296 "resource not in use (status 0x%x bit 0x%x)",
297 lock_status, resource_bit);
301 REG_WR(sc, hw_lock_control_reg, resource_bit);
305 static void bnx2x_acquire_phy_lock(struct bnx2x_softc *sc)
308 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_MDIO);
311 static void bnx2x_release_phy_lock(struct bnx2x_softc *sc)
313 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_MDIO);
314 BNX2X_PHY_UNLOCK(sc);
317 /* copy command into DMAE command memory and set DMAE command Go */
318 void bnx2x_post_dmae(struct bnx2x_softc *sc, struct dmae_command *dmae, int idx)
323 cmd_offset = (DMAE_REG_CMD_MEM + (sizeof(struct dmae_command) * idx));
324 for (i = 0; i < ((sizeof(struct dmae_command) / 4)); i++) {
325 REG_WR(sc, (cmd_offset + (i * 4)), *(((uint32_t *) dmae) + i));
328 REG_WR(sc, dmae_reg_go_c[idx], 1);
331 uint32_t bnx2x_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type)
333 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
334 DMAE_COMMAND_C_TYPE_ENABLE);
337 uint32_t bnx2x_dmae_opcode_clr_src_reset(uint32_t opcode)
339 return opcode & ~DMAE_COMMAND_SRC_RESET;
343 bnx2x_dmae_opcode(struct bnx2x_softc * sc, uint8_t src_type, uint8_t dst_type,
344 uint8_t with_comp, uint8_t comp_type)
348 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
349 (dst_type << DMAE_COMMAND_DST_SHIFT));
351 opcode |= (DMAE_COMMAND_SRC_RESET | DMAE_COMMAND_DST_RESET);
353 opcode |= (SC_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
355 opcode |= ((SC_VN(sc) << DMAE_COMMAND_E1HVN_SHIFT) |
356 (SC_VN(sc) << DMAE_COMMAND_DST_VN_SHIFT));
358 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
361 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
363 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
367 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
374 bnx2x_prep_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae,
375 uint8_t src_type, uint8_t dst_type)
377 memset(dmae, 0, sizeof(struct dmae_command));
380 dmae->opcode = bnx2x_dmae_opcode(sc, src_type, dst_type,
381 TRUE, DMAE_COMP_PCI);
383 /* fill in the completion parameters */
384 dmae->comp_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_comp));
385 dmae->comp_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_comp));
386 dmae->comp_val = DMAE_COMP_VAL;
389 /* issue a DMAE command over the init channel and wait for completion */
391 bnx2x_issue_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae)
393 uint32_t *wb_comp = BNX2X_SP(sc, wb_comp);
394 int timeout = CHIP_REV_IS_SLOW(sc) ? 400000 : 4000;
396 /* reset completion */
399 /* post the command on the channel used for initializations */
400 bnx2x_post_dmae(sc, dmae, INIT_DMAE_C(sc));
402 /* wait for completion */
405 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
407 (sc->recovery_state != BNX2X_RECOVERY_DONE &&
408 sc->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
409 PMD_DRV_LOG(INFO, sc, "DMAE timeout!");
417 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
418 PMD_DRV_LOG(INFO, sc, "DMAE PCI error!");
419 return DMAE_PCI_ERROR;
425 void bnx2x_read_dmae(struct bnx2x_softc *sc, uint32_t src_addr, uint32_t len32)
427 struct dmae_command dmae;
432 if (!sc->dmae_ready) {
433 data = BNX2X_SP(sc, wb_data[0]);
435 for (i = 0; i < len32; i++) {
436 data[i] = REG_RD(sc, (src_addr + (i * 4)));
442 /* set opcode and fixed command fields */
443 bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
445 /* fill in addresses and len */
446 dmae.src_addr_lo = (src_addr >> 2); /* GRC addr has dword resolution */
447 dmae.src_addr_hi = 0;
448 dmae.dst_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_data));
449 dmae.dst_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_data));
452 /* issue the command and wait for completion */
453 if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
454 rte_panic("DMAE failed (%d)", rc);
459 bnx2x_write_dmae(struct bnx2x_softc *sc, rte_iova_t dma_addr, uint32_t dst_addr,
462 struct dmae_command dmae;
465 if (!sc->dmae_ready) {
466 ecore_init_str_wr(sc, dst_addr, BNX2X_SP(sc, wb_data[0]), len32);
470 /* set opcode and fixed command fields */
471 bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
473 /* fill in addresses and len */
474 dmae.src_addr_lo = U64_LO(dma_addr);
475 dmae.src_addr_hi = U64_HI(dma_addr);
476 dmae.dst_addr_lo = (dst_addr >> 2); /* GRC addr has dword resolution */
477 dmae.dst_addr_hi = 0;
480 /* issue the command and wait for completion */
481 if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
482 rte_panic("DMAE failed (%d)", rc);
487 bnx2x_write_dmae_phys_len(struct bnx2x_softc *sc, rte_iova_t phys_addr,
488 uint32_t addr, uint32_t len)
490 uint32_t dmae_wr_max = DMAE_LEN32_WR_MAX(sc);
493 while (len > dmae_wr_max) {
494 bnx2x_write_dmae(sc, (phys_addr + offset), /* src DMA address */
495 (addr + offset), /* dst GRC address */
497 offset += (dmae_wr_max * 4);
501 bnx2x_write_dmae(sc, (phys_addr + offset), /* src DMA address */
502 (addr + offset), /* dst GRC address */
507 bnx2x_set_ctx_validation(struct bnx2x_softc *sc, struct eth_context *cxt,
510 /* ustorm cxt validation */
511 cxt->ustorm_ag_context.cdu_usage =
512 CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
513 CDU_REGION_NUMBER_UCM_AG,
514 ETH_CONNECTION_TYPE);
515 /* xcontext validation */
516 cxt->xstorm_ag_context.cdu_reserved =
517 CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
518 CDU_REGION_NUMBER_XCM_AG,
519 ETH_CONNECTION_TYPE);
523 bnx2x_storm_memset_hc_timeout(struct bnx2x_softc *sc, uint8_t fw_sb_id,
524 uint8_t sb_index, uint8_t ticks)
527 (BAR_CSTRORM_INTMEM +
528 CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(fw_sb_id, sb_index));
530 REG_WR8(sc, addr, ticks);
534 bnx2x_storm_memset_hc_disable(struct bnx2x_softc *sc, uint16_t fw_sb_id,
535 uint8_t sb_index, uint8_t disable)
537 uint32_t enable_flag =
538 (disable) ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
540 (BAR_CSTRORM_INTMEM +
541 CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(fw_sb_id, sb_index));
545 flags = REG_RD8(sc, addr);
546 flags &= ~HC_INDEX_DATA_HC_ENABLED;
547 flags |= enable_flag;
548 REG_WR8(sc, addr, flags);
552 bnx2x_update_coalesce_sb_index(struct bnx2x_softc *sc, uint8_t fw_sb_id,
553 uint8_t sb_index, uint8_t disable, uint16_t usec)
555 uint8_t ticks = (usec / 4);
557 bnx2x_storm_memset_hc_timeout(sc, fw_sb_id, sb_index, ticks);
559 disable = (disable) ? 1 : ((usec) ? 0 : 1);
560 bnx2x_storm_memset_hc_disable(sc, fw_sb_id, sb_index, disable);
563 uint32_t elink_cb_reg_read(struct bnx2x_softc *sc, uint32_t reg_addr)
565 return REG_RD(sc, reg_addr);
568 void elink_cb_reg_write(struct bnx2x_softc *sc, uint32_t reg_addr, uint32_t val)
570 REG_WR(sc, reg_addr, val);
574 elink_cb_event_log(__rte_unused struct bnx2x_softc *sc,
575 __rte_unused const elink_log_id_t elink_log_id, ...)
577 PMD_DRV_LOG(DEBUG, sc, "ELINK EVENT LOG (%d)", elink_log_id);
580 static int bnx2x_set_spio(struct bnx2x_softc *sc, int spio, uint32_t mode)
584 /* Only 2 SPIOs are configurable */
585 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
586 PMD_DRV_LOG(NOTICE, sc, "Invalid SPIO 0x%x", spio);
590 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
592 /* read SPIO and mask except the float bits */
593 spio_reg = (REG_RD(sc, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
596 case MISC_SPIO_OUTPUT_LOW:
597 /* clear FLOAT and set CLR */
598 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
599 spio_reg |= (spio << MISC_SPIO_CLR_POS);
602 case MISC_SPIO_OUTPUT_HIGH:
603 /* clear FLOAT and set SET */
604 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
605 spio_reg |= (spio << MISC_SPIO_SET_POS);
608 case MISC_SPIO_INPUT_HI_Z:
610 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
617 REG_WR(sc, MISC_REG_SPIO, spio_reg);
618 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
623 static int bnx2x_gpio_read(struct bnx2x_softc *sc, int gpio_num, uint8_t port)
625 /* The GPIO should be swapped if swap register is set and active */
626 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
627 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
628 int gpio_shift = gpio_num;
630 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
632 uint32_t gpio_mask = (1 << gpio_shift);
635 if (gpio_num > MISC_REGISTERS_GPIO_3) {
636 PMD_DRV_LOG(NOTICE, sc, "Invalid GPIO %d", gpio_num);
640 /* read GPIO value */
641 gpio_reg = REG_RD(sc, MISC_REG_GPIO);
643 /* get the requested pin value */
644 return ((gpio_reg & gpio_mask) == gpio_mask) ? 1 : 0;
648 bnx2x_gpio_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode, uint8_t port)
650 /* The GPIO should be swapped if swap register is set and active */
651 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
652 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
653 int gpio_shift = gpio_num;
655 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
657 uint32_t gpio_mask = (1 << gpio_shift);
660 if (gpio_num > MISC_REGISTERS_GPIO_3) {
661 PMD_DRV_LOG(NOTICE, sc, "Invalid GPIO %d", gpio_num);
665 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
667 /* read GPIO and mask except the float bits */
668 gpio_reg = (REG_RD(sc, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
671 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
672 /* clear FLOAT and set CLR */
673 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
674 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
677 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
678 /* clear FLOAT and set SET */
679 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
680 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
683 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
685 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
692 REG_WR(sc, MISC_REG_GPIO, gpio_reg);
693 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
699 bnx2x_gpio_mult_write(struct bnx2x_softc *sc, uint8_t pins, uint32_t mode)
703 /* any port swapping should be handled by caller */
705 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
707 /* read GPIO and mask except the float bits */
708 gpio_reg = REG_RD(sc, MISC_REG_GPIO);
709 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
710 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
711 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
714 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
716 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
719 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
721 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
724 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
726 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
730 PMD_DRV_LOG(NOTICE, sc,
731 "Invalid GPIO mode assignment %d", mode);
732 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
736 REG_WR(sc, MISC_REG_GPIO, gpio_reg);
737 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
743 bnx2x_gpio_int_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode,
746 /* The GPIO should be swapped if swap register is set and active */
747 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
748 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
749 int gpio_shift = gpio_num;
751 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
753 uint32_t gpio_mask = (1 << gpio_shift);
756 if (gpio_num > MISC_REGISTERS_GPIO_3) {
757 PMD_DRV_LOG(NOTICE, sc, "Invalid GPIO %d", gpio_num);
761 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
764 gpio_reg = REG_RD(sc, MISC_REG_GPIO_INT);
767 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
768 /* clear SET and set CLR */
769 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
770 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
773 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
774 /* clear CLR and set SET */
775 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
776 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
783 REG_WR(sc, MISC_REG_GPIO_INT, gpio_reg);
784 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
790 elink_cb_gpio_read(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t port)
792 return bnx2x_gpio_read(sc, gpio_num, port);
795 uint8_t elink_cb_gpio_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode, /* 0=low 1=high */
798 return bnx2x_gpio_write(sc, gpio_num, mode, port);
802 elink_cb_gpio_mult_write(struct bnx2x_softc * sc, uint8_t pins,
803 uint8_t mode /* 0=low 1=high */ )
805 return bnx2x_gpio_mult_write(sc, pins, mode);
808 uint8_t elink_cb_gpio_int_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode, /* 0=low 1=high */
811 return bnx2x_gpio_int_write(sc, gpio_num, mode, port);
814 void elink_cb_notify_link_changed(struct bnx2x_softc *sc)
816 REG_WR(sc, (MISC_REG_AEU_GENERAL_ATTN_12 +
817 (SC_FUNC(sc) * sizeof(uint32_t))), 1);
820 /* send the MCP a request, block until there is a reply */
822 elink_cb_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
824 int mb_idx = SC_FW_MB_IDX(sc);
828 uint8_t delay = CHIP_REV_IS_SLOW(sc) ? 100 : 10;
831 SHMEM_WR(sc, func_mb[mb_idx].drv_mb_param, param);
832 SHMEM_WR(sc, func_mb[mb_idx].drv_mb_header, (command | seq));
834 PMD_DRV_LOG(DEBUG, sc,
835 "wrote command 0x%08x to FW MB param 0x%08x",
836 (command | seq), param);
838 /* Let the FW do it's magic. GIve it up to 5 seconds... */
841 rc = SHMEM_RD(sc, func_mb[mb_idx].fw_mb_header);
842 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
844 /* is this a reply to our command? */
845 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) {
846 rc &= FW_MSG_CODE_MASK;
849 PMD_DRV_LOG(NOTICE, sc, "FW failed to respond!");
857 bnx2x_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
859 return elink_cb_fw_command(sc, command, param);
863 __storm_memset_dma_mapping(struct bnx2x_softc *sc, uint32_t addr,
866 REG_WR(sc, addr, U64_LO(mapping));
867 REG_WR(sc, (addr + 4), U64_HI(mapping));
871 storm_memset_spq_addr(struct bnx2x_softc *sc, rte_iova_t mapping,
874 uint32_t addr = (XSEM_REG_FAST_MEMORY +
875 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid));
876 __storm_memset_dma_mapping(sc, addr, mapping);
880 storm_memset_vf_to_pf(struct bnx2x_softc *sc, uint16_t abs_fid, uint16_t pf_id)
882 REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid)),
884 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid)),
886 REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid)),
888 REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid)),
893 storm_memset_func_en(struct bnx2x_softc *sc, uint16_t abs_fid, uint8_t enable)
895 REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid)),
897 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid)),
899 REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid)),
901 REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid)),
906 storm_memset_eq_data(struct bnx2x_softc *sc, struct event_ring_data *eq_data,
912 addr = (BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid));
913 size = sizeof(struct event_ring_data);
914 ecore_storm_memset_struct(sc, addr, size, (uint32_t *) eq_data);
918 storm_memset_eq_prod(struct bnx2x_softc *sc, uint16_t eq_prod, uint16_t pfid)
920 uint32_t addr = (BAR_CSTRORM_INTMEM +
921 CSTORM_EVENT_RING_PROD_OFFSET(pfid));
922 REG_WR16(sc, addr, eq_prod);
926 * Post a slowpath command.
928 * A slowpath command is used to propagate a configuration change through
929 * the controller in a controlled manner, allowing each STORM processor and
930 * other H/W blocks to phase in the change. The commands sent on the
931 * slowpath are referred to as ramrods. Depending on the ramrod used the
932 * completion of the ramrod will occur in different ways. Here's a
933 * breakdown of ramrods and how they complete:
935 * RAMROD_CMD_ID_ETH_PORT_SETUP
936 * Used to setup the leading connection on a port. Completes on the
937 * Receive Completion Queue (RCQ) of that port (typically fp[0]).
939 * RAMROD_CMD_ID_ETH_CLIENT_SETUP
940 * Used to setup an additional connection on a port. Completes on the
941 * RCQ of the multi-queue/RSS connection being initialized.
943 * RAMROD_CMD_ID_ETH_STAT_QUERY
944 * Used to force the storm processors to update the statistics database
945 * in host memory. This ramrod is send on the leading connection CID and
946 * completes as an index increment of the CSTORM on the default status
949 * RAMROD_CMD_ID_ETH_UPDATE
950 * Used to update the state of the leading connection, usually to udpate
951 * the RSS indirection table. Completes on the RCQ of the leading
952 * connection. (Not currently used under FreeBSD until OS support becomes
955 * RAMROD_CMD_ID_ETH_HALT
956 * Used when tearing down a connection prior to driver unload. Completes
957 * on the RCQ of the multi-queue/RSS connection being torn down. Don't
958 * use this on the leading connection.
960 * RAMROD_CMD_ID_ETH_SET_MAC
961 * Sets the Unicast/Broadcast/Multicast used by the port. Completes on
962 * the RCQ of the leading connection.
964 * RAMROD_CMD_ID_ETH_CFC_DEL
965 * Used when tearing down a conneciton prior to driver unload. Completes
966 * on the RCQ of the leading connection (since the current connection
967 * has been completely removed from controller memory).
969 * RAMROD_CMD_ID_ETH_PORT_DEL
970 * Used to tear down the leading connection prior to driver unload,
971 * typically fp[0]. Completes as an index increment of the CSTORM on the
972 * default status block.
974 * RAMROD_CMD_ID_ETH_FORWARD_SETUP
975 * Used for connection offload. Completes on the RCQ of the multi-queue
976 * RSS connection that is being offloaded. (Not currently used under
979 * There can only be one command pending per function.
982 * 0 = Success, !0 = Failure.
985 /* must be called under the spq lock */
986 static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x_softc *sc)
988 struct eth_spe *next_spe = sc->spq_prod_bd;
990 if (sc->spq_prod_bd == sc->spq_last_bd) {
991 /* wrap back to the first eth_spq */
992 sc->spq_prod_bd = sc->spq;
993 sc->spq_prod_idx = 0;
1002 /* must be called under the spq lock */
1003 static void bnx2x_sp_prod_update(struct bnx2x_softc *sc)
1005 int func = SC_FUNC(sc);
1008 * Make sure that BD data is updated before writing the producer.
1009 * BD data is written to the memory, the producer is read from the
1010 * memory, thus we need a full memory barrier to ensure the ordering.
1014 REG_WR16(sc, (BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func)),
1021 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
1023 * @cmd: command to check
1024 * @cmd_type: command type
1026 static int bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
1028 if ((cmd_type == NONE_CONNECTION_TYPE) ||
1029 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
1030 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
1031 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
1032 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
1033 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
1034 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) {
1042 * bnx2x_sp_post - place a single command on an SP ring
1044 * @sc: driver handle
1045 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
1046 * @cid: SW CID the command is related to
1047 * @data_hi: command private data address (high 32 bits)
1048 * @data_lo: command private data address (low 32 bits)
1049 * @cmd_type: command type (e.g. NONE, ETH)
1051 * SP data is handled as if it's always an address pair, thus data fields are
1052 * not swapped to little endian in upper functions. Instead this function swaps
1053 * data as if it's two uint32 fields.
1056 bnx2x_sp_post(struct bnx2x_softc *sc, int command, int cid, uint32_t data_hi,
1057 uint32_t data_lo, int cmd_type)
1059 struct eth_spe *spe;
1063 common = bnx2x_is_contextless_ramrod(command, cmd_type);
1066 if (!atomic_load_acq_long(&sc->eq_spq_left)) {
1067 PMD_DRV_LOG(INFO, sc, "EQ ring is full!");
1071 if (!atomic_load_acq_long(&sc->cq_spq_left)) {
1072 PMD_DRV_LOG(INFO, sc, "SPQ ring is full!");
1077 spe = bnx2x_sp_get_next(sc);
1079 /* CID needs port number to be encoded int it */
1080 spe->hdr.conn_and_cmd_data =
1081 htole32((command << SPE_HDR_CMD_ID_SHIFT) | HW_CID(sc, cid));
1083 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
1085 /* TBD: Check if it works for VFs */
1086 type |= ((SC_FUNC(sc) << SPE_HDR_FUNCTION_ID_SHIFT) &
1087 SPE_HDR_FUNCTION_ID);
1089 spe->hdr.type = htole16(type);
1091 spe->data.update_data_addr.hi = htole32(data_hi);
1092 spe->data.update_data_addr.lo = htole32(data_lo);
1095 * It's ok if the actual decrement is issued towards the memory
1096 * somewhere between the lock and unlock. Thus no more explict
1097 * memory barrier is needed.
1100 atomic_subtract_acq_long(&sc->eq_spq_left, 1);
1102 atomic_subtract_acq_long(&sc->cq_spq_left, 1);
1105 PMD_DRV_LOG(DEBUG, sc,
1106 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x"
1107 "data (%x:%x) type(0x%x) left (CQ, EQ) (%lx,%lx)",
1109 (uint32_t) U64_HI(sc->spq_dma.paddr),
1110 (uint32_t) (U64_LO(sc->spq_dma.paddr) +
1111 (uint8_t *) sc->spq_prod_bd -
1112 (uint8_t *) sc->spq), command, common,
1113 HW_CID(sc, cid), data_hi, data_lo, type,
1114 atomic_load_acq_long(&sc->cq_spq_left),
1115 atomic_load_acq_long(&sc->eq_spq_left));
1117 /* RAMROD completion is processed in bnx2x_intr_legacy()
1118 * which can run from different contexts.
1119 * Ask bnx2x_intr_intr() to process RAMROD
1120 * completion whenever it gets scheduled.
1122 rte_atomic32_set(&sc->scan_fp, 1);
1123 bnx2x_sp_prod_update(sc);
1128 static void bnx2x_drv_pulse(struct bnx2x_softc *sc)
1130 SHMEM_WR(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb,
1131 sc->fw_drv_pulse_wr_seq);
1134 static int bnx2x_tx_queue_has_work(const struct bnx2x_fastpath *fp)
1137 struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1139 if (unlikely(!txq)) {
1140 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1144 mb(); /* status block fields can change */
1145 hw_cons = le16toh(*fp->tx_cons_sb);
1146 return hw_cons != txq->tx_pkt_head;
1149 static uint8_t bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
1151 /* expand this for multi-cos if ever supported */
1152 return bnx2x_tx_queue_has_work(fp);
1155 static int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
1157 uint16_t rx_cq_cons_sb;
1158 struct bnx2x_rx_queue *rxq;
1159 rxq = fp->sc->rx_queues[fp->index];
1160 if (unlikely(!rxq)) {
1161 PMD_RX_LOG(ERR, "ERROR: RX queue is NULL");
1165 mb(); /* status block fields can change */
1166 rx_cq_cons_sb = le16toh(*fp->rx_cq_cons_sb);
1167 if (unlikely((rx_cq_cons_sb & MAX_RCQ_ENTRIES(rxq)) ==
1168 MAX_RCQ_ENTRIES(rxq)))
1170 return rxq->rx_cq_head != rx_cq_cons_sb;
1174 bnx2x_sp_event(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
1175 union eth_rx_cqe *rr_cqe)
1177 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1178 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1179 enum ecore_queue_cmd drv_cmd = ECORE_Q_CMD_MAX;
1180 struct ecore_queue_sp_obj *q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
1182 PMD_DRV_LOG(DEBUG, sc,
1183 "fp=%d cid=%d got ramrod #%d state is %x type is %d",
1184 fp->index, cid, command, sc->state,
1185 rr_cqe->ramrod_cqe.ramrod_type);
1188 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1189 PMD_DRV_LOG(DEBUG, sc, "got UPDATE ramrod. CID %d", cid);
1190 drv_cmd = ECORE_Q_CMD_UPDATE;
1193 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1194 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] setup ramrod", cid);
1195 drv_cmd = ECORE_Q_CMD_SETUP;
1198 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1199 PMD_DRV_LOG(DEBUG, sc,
1200 "got MULTI[%d] tx-only setup ramrod", cid);
1201 drv_cmd = ECORE_Q_CMD_SETUP_TX_ONLY;
1204 case (RAMROD_CMD_ID_ETH_HALT):
1205 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] halt ramrod", cid);
1206 drv_cmd = ECORE_Q_CMD_HALT;
1209 case (RAMROD_CMD_ID_ETH_TERMINATE):
1210 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] teminate ramrod", cid);
1211 drv_cmd = ECORE_Q_CMD_TERMINATE;
1214 case (RAMROD_CMD_ID_ETH_EMPTY):
1215 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] empty ramrod", cid);
1216 drv_cmd = ECORE_Q_CMD_EMPTY;
1220 PMD_DRV_LOG(DEBUG, sc,
1221 "ERROR: unexpected MC reply (%d)"
1222 "on fp[%d]", command, fp->index);
1226 if ((drv_cmd != ECORE_Q_CMD_MAX) &&
1227 q_obj->complete_cmd(sc, q_obj, drv_cmd)) {
1229 * q_obj->complete_cmd() failure means that this was
1230 * an unexpected completion.
1232 * In this case we don't want to increase the sc->spq_left
1233 * because apparently we haven't sent this command the first
1236 // rte_panic("Unexpected SP completion");
1240 atomic_add_acq_long(&sc->cq_spq_left, 1);
1242 PMD_DRV_LOG(DEBUG, sc, "sc->cq_spq_left 0x%lx",
1243 atomic_load_acq_long(&sc->cq_spq_left));
1246 static uint8_t bnx2x_rxeof(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
1248 struct bnx2x_rx_queue *rxq;
1249 uint16_t bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
1250 uint16_t hw_cq_cons, sw_cq_cons, sw_cq_prod;
1252 rxq = sc->rx_queues[fp->index];
1254 PMD_RX_LOG(ERR, "RX queue %d is NULL", fp->index);
1258 /* CQ "next element" is of the size of the regular element */
1259 hw_cq_cons = le16toh(*fp->rx_cq_cons_sb);
1260 if (unlikely((hw_cq_cons & USABLE_RCQ_ENTRIES_PER_PAGE) ==
1261 USABLE_RCQ_ENTRIES_PER_PAGE)) {
1265 bd_cons = rxq->rx_bd_head;
1266 bd_prod = rxq->rx_bd_tail;
1267 bd_prod_fw = bd_prod;
1268 sw_cq_cons = rxq->rx_cq_head;
1269 sw_cq_prod = rxq->rx_cq_tail;
1272 * Memory barrier necessary as speculative reads of the rx
1273 * buffer can be ahead of the index in the status block
1277 while (sw_cq_cons != hw_cq_cons) {
1278 union eth_rx_cqe *cqe;
1279 struct eth_fast_path_rx_cqe *cqe_fp;
1280 uint8_t cqe_fp_flags;
1281 enum eth_rx_cqe_type cqe_fp_type;
1283 comp_ring_cons = RCQ_ENTRY(sw_cq_cons, rxq);
1284 bd_prod = RX_BD(bd_prod, rxq);
1285 bd_cons = RX_BD(bd_cons, rxq);
1287 cqe = &rxq->cq_ring[comp_ring_cons];
1288 cqe_fp = &cqe->fast_path_cqe;
1289 cqe_fp_flags = cqe_fp->type_error_flags;
1290 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
1292 /* is this a slowpath msg? */
1293 if (CQE_TYPE_SLOW(cqe_fp_type)) {
1294 bnx2x_sp_event(sc, fp, cqe);
1298 /* is this an error packet? */
1299 if (unlikely(cqe_fp_flags &
1300 ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG)) {
1301 PMD_RX_LOG(DEBUG, "flags 0x%x rx packet %u",
1302 cqe_fp_flags, sw_cq_cons);
1306 PMD_RX_LOG(DEBUG, "Dropping fastpath called from attn poller!");
1309 bd_cons = NEXT_RX_BD(bd_cons);
1310 bd_prod = NEXT_RX_BD(bd_prod);
1311 bd_prod_fw = NEXT_RX_BD(bd_prod_fw);
1314 sw_cq_prod = NEXT_RCQ_IDX(sw_cq_prod);
1315 sw_cq_cons = NEXT_RCQ_IDX(sw_cq_cons);
1317 } /* while work to do */
1319 rxq->rx_bd_head = bd_cons;
1320 rxq->rx_bd_tail = bd_prod_fw;
1321 rxq->rx_cq_head = sw_cq_cons;
1322 rxq->rx_cq_tail = sw_cq_prod;
1324 /* Update producers */
1325 bnx2x_update_rx_prod(sc, fp, bd_prod_fw, sw_cq_prod);
1327 return sw_cq_cons != hw_cq_cons;
1331 bnx2x_free_tx_pkt(__rte_unused struct bnx2x_fastpath *fp, struct bnx2x_tx_queue *txq,
1332 uint16_t pkt_idx, uint16_t bd_idx)
1334 struct eth_tx_start_bd *tx_start_bd =
1335 &txq->tx_ring[TX_BD(bd_idx, txq)].start_bd;
1336 uint16_t nbd = rte_le_to_cpu_16(tx_start_bd->nbd);
1337 struct rte_mbuf *tx_mbuf = txq->sw_ring[TX_BD(pkt_idx, txq)];
1339 if (likely(tx_mbuf != NULL)) {
1340 rte_pktmbuf_free_seg(tx_mbuf);
1342 PMD_RX_LOG(ERR, "fp[%02d] lost mbuf %lu",
1343 fp->index, (unsigned long)TX_BD(pkt_idx, txq));
1346 txq->sw_ring[TX_BD(pkt_idx, txq)] = NULL;
1347 txq->nb_tx_avail += nbd;
1350 bd_idx = NEXT_TX_BD(bd_idx);
1355 /* processes transmit completions */
1356 uint8_t bnx2x_txeof(__rte_unused struct bnx2x_softc * sc, struct bnx2x_fastpath * fp)
1358 uint16_t bd_cons, hw_cons, sw_cons;
1359 __rte_unused uint16_t tx_bd_avail;
1361 struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1363 if (unlikely(!txq)) {
1364 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1368 bd_cons = txq->tx_bd_head;
1369 hw_cons = rte_le_to_cpu_16(*fp->tx_cons_sb);
1370 sw_cons = txq->tx_pkt_head;
1372 while (sw_cons != hw_cons) {
1373 bd_cons = bnx2x_free_tx_pkt(fp, txq, sw_cons, bd_cons);
1377 txq->tx_pkt_head = sw_cons;
1378 txq->tx_bd_head = bd_cons;
1380 tx_bd_avail = txq->nb_tx_avail;
1382 PMD_TX_LOG(DEBUG, "fp[%02d] avail=%u cons_sb=%u, "
1383 "pkt_head=%u pkt_tail=%u bd_head=%u bd_tail=%u",
1384 fp->index, tx_bd_avail, hw_cons,
1385 txq->tx_pkt_head, txq->tx_pkt_tail,
1386 txq->tx_bd_head, txq->tx_bd_tail);
1390 static void bnx2x_drain_tx_queues(struct bnx2x_softc *sc)
1392 struct bnx2x_fastpath *fp;
1395 /* wait until all TX fastpath tasks have completed */
1396 for (i = 0; i < sc->num_queues; i++) {
1401 while (bnx2x_has_tx_work(fp)) {
1402 bnx2x_txeof(sc, fp);
1406 "Timeout waiting for fp[%d] "
1407 "transmits to complete!", i);
1408 rte_panic("tx drain failure");
1422 bnx2x_del_all_macs(struct bnx2x_softc *sc, struct ecore_vlan_mac_obj *mac_obj,
1423 int mac_type, uint8_t wait_for_comp)
1425 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1428 /* wait for completion of requested */
1429 if (wait_for_comp) {
1430 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1433 /* Set the mac type of addresses we want to clear */
1434 bnx2x_set_bit(mac_type, &vlan_mac_flags);
1436 rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1438 PMD_DRV_LOG(ERR, sc, "Failed to delete MACs (%d)", rc);
1444 bnx2x_fill_accept_flags(struct bnx2x_softc *sc, uint32_t rx_mode,
1445 unsigned long *rx_accept_flags,
1446 unsigned long *tx_accept_flags)
1448 /* Clear the flags first */
1449 *rx_accept_flags = 0;
1450 *tx_accept_flags = 0;
1453 case BNX2X_RX_MODE_NONE:
1455 * 'drop all' supersedes any accept flags that may have been
1456 * passed to the function.
1460 case BNX2X_RX_MODE_NORMAL:
1461 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1462 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, rx_accept_flags);
1463 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1465 /* internal switching mode */
1466 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1467 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, tx_accept_flags);
1468 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1472 case BNX2X_RX_MODE_ALLMULTI:
1473 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1474 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1475 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1477 /* internal switching mode */
1478 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1479 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1480 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1484 case BNX2X_RX_MODE_ALLMULTI_PROMISC:
1485 case BNX2X_RX_MODE_PROMISC:
1487 * According to deffinition of SI mode, iface in promisc mode
1488 * should receive matched and unmatched (in resolution of port)
1491 bnx2x_set_bit(ECORE_ACCEPT_UNMATCHED, rx_accept_flags);
1492 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1493 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1494 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1496 /* internal switching mode */
1497 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1498 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1501 bnx2x_set_bit(ECORE_ACCEPT_ALL_UNICAST, tx_accept_flags);
1503 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1509 PMD_RX_LOG(ERR, "Unknown rx_mode (%d)", rx_mode);
1513 /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
1514 if (rx_mode != BNX2X_RX_MODE_NONE) {
1515 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, rx_accept_flags);
1516 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, tx_accept_flags);
1523 bnx2x_set_q_rx_mode(struct bnx2x_softc *sc, uint8_t cl_id,
1524 unsigned long rx_mode_flags,
1525 unsigned long rx_accept_flags,
1526 unsigned long tx_accept_flags, unsigned long ramrod_flags)
1528 struct ecore_rx_mode_ramrod_params ramrod_param;
1531 memset(&ramrod_param, 0, sizeof(ramrod_param));
1533 /* Prepare ramrod parameters */
1534 ramrod_param.cid = 0;
1535 ramrod_param.cl_id = cl_id;
1536 ramrod_param.rx_mode_obj = &sc->rx_mode_obj;
1537 ramrod_param.func_id = SC_FUNC(sc);
1539 ramrod_param.pstate = &sc->sp_state;
1540 ramrod_param.state = ECORE_FILTER_RX_MODE_PENDING;
1542 ramrod_param.rdata = BNX2X_SP(sc, rx_mode_rdata);
1543 ramrod_param.rdata_mapping =
1544 (rte_iova_t)BNX2X_SP_MAPPING(sc, rx_mode_rdata),
1545 bnx2x_set_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
1547 ramrod_param.ramrod_flags = ramrod_flags;
1548 ramrod_param.rx_mode_flags = rx_mode_flags;
1550 ramrod_param.rx_accept_flags = rx_accept_flags;
1551 ramrod_param.tx_accept_flags = tx_accept_flags;
1553 rc = ecore_config_rx_mode(sc, &ramrod_param);
1555 PMD_RX_LOG(ERR, "Set rx_mode %d failed", sc->rx_mode);
1562 int bnx2x_set_storm_rx_mode(struct bnx2x_softc *sc)
1564 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
1565 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
1568 rc = bnx2x_fill_accept_flags(sc, sc->rx_mode, &rx_accept_flags,
1574 bnx2x_set_bit(RAMROD_RX, &ramrod_flags);
1575 bnx2x_set_bit(RAMROD_TX, &ramrod_flags);
1576 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1578 return bnx2x_set_q_rx_mode(sc, sc->fp[0].cl_id, rx_mode_flags,
1579 rx_accept_flags, tx_accept_flags,
1583 /* returns the "mcp load_code" according to global load_count array */
1584 static int bnx2x_nic_load_no_mcp(struct bnx2x_softc *sc)
1586 int path = SC_PATH(sc);
1587 int port = SC_PORT(sc);
1589 PMD_DRV_LOG(INFO, sc, "NO MCP - load counts[%d] %d, %d, %d",
1590 path, load_count[path][0], load_count[path][1],
1591 load_count[path][2]);
1593 load_count[path][0]++;
1594 load_count[path][1 + port]++;
1595 PMD_DRV_LOG(INFO, sc, "NO MCP - new load counts[%d] %d, %d, %d",
1596 path, load_count[path][0], load_count[path][1],
1597 load_count[path][2]);
1598 if (load_count[path][0] == 1)
1599 return FW_MSG_CODE_DRV_LOAD_COMMON;
1600 else if (load_count[path][1 + port] == 1)
1601 return FW_MSG_CODE_DRV_LOAD_PORT;
1603 return FW_MSG_CODE_DRV_LOAD_FUNCTION;
1606 /* returns the "mcp load_code" according to global load_count array */
1607 static int bnx2x_nic_unload_no_mcp(struct bnx2x_softc *sc)
1609 int port = SC_PORT(sc);
1610 int path = SC_PATH(sc);
1612 PMD_DRV_LOG(INFO, sc, "NO MCP - load counts[%d] %d, %d, %d",
1613 path, load_count[path][0], load_count[path][1],
1614 load_count[path][2]);
1615 load_count[path][0]--;
1616 load_count[path][1 + port]--;
1617 PMD_DRV_LOG(INFO, sc, "NO MCP - new load counts[%d] %d, %d, %d",
1618 path, load_count[path][0], load_count[path][1],
1619 load_count[path][2]);
1620 if (load_count[path][0] == 0) {
1621 return FW_MSG_CODE_DRV_UNLOAD_COMMON;
1622 } else if (load_count[path][1 + port] == 0) {
1623 return FW_MSG_CODE_DRV_UNLOAD_PORT;
1625 return FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
1629 /* request unload mode from the MCP: COMMON, PORT or FUNCTION */
1630 static uint32_t bnx2x_send_unload_req(struct bnx2x_softc *sc, int unload_mode)
1632 uint32_t reset_code = 0;
1634 /* Select the UNLOAD request mode */
1635 if (unload_mode == UNLOAD_NORMAL) {
1636 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1638 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1641 /* Send the request to the MCP */
1642 if (!BNX2X_NOMCP(sc)) {
1643 reset_code = bnx2x_fw_command(sc, reset_code, 0);
1645 reset_code = bnx2x_nic_unload_no_mcp(sc);
1651 /* send UNLOAD_DONE command to the MCP */
1652 static void bnx2x_send_unload_done(struct bnx2x_softc *sc, uint8_t keep_link)
1654 uint32_t reset_param =
1655 keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
1657 /* Report UNLOAD_DONE to MCP */
1658 if (!BNX2X_NOMCP(sc)) {
1659 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
1663 static int bnx2x_func_wait_started(struct bnx2x_softc *sc)
1667 if (!sc->port.pmf) {
1672 * (assumption: No Attention from MCP at this stage)
1673 * PMF probably in the middle of TX disable/enable transaction
1674 * 1. Sync IRS for default SB
1675 * 2. Sync SP queue - this guarantees us that attention handling started
1676 * 3. Wait, that TX disable/enable transaction completes
1678 * 1+2 guarantee that if DCBX attention was scheduled it already changed
1679 * pending bit of transaction from STARTED-->TX_STOPPED, if we already
1680 * received completion for the transaction the state is TX_STOPPED.
1681 * State will return to STARTED after completion of TX_STOPPED-->STARTED
1685 while (ecore_func_get_state(sc, &sc->func_obj) !=
1686 ECORE_F_STATE_STARTED && tout--) {
1690 if (ecore_func_get_state(sc, &sc->func_obj) != ECORE_F_STATE_STARTED) {
1692 * Failed to complete the transaction in a "good way"
1693 * Force both transactions with CLR bit.
1695 struct ecore_func_state_params func_params = { NULL };
1697 PMD_DRV_LOG(NOTICE, sc, "Unexpected function state! "
1698 "Forcing STARTED-->TX_STOPPED-->STARTED");
1700 func_params.f_obj = &sc->func_obj;
1701 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1703 /* STARTED-->TX_STOPPED */
1704 func_params.cmd = ECORE_F_CMD_TX_STOP;
1705 ecore_func_state_change(sc, &func_params);
1707 /* TX_STOPPED-->STARTED */
1708 func_params.cmd = ECORE_F_CMD_TX_START;
1709 return ecore_func_state_change(sc, &func_params);
1715 static int bnx2x_stop_queue(struct bnx2x_softc *sc, int index)
1717 struct bnx2x_fastpath *fp = &sc->fp[index];
1718 struct ecore_queue_state_params q_params = { NULL };
1721 PMD_DRV_LOG(DEBUG, sc, "stopping queue %d cid %d", index, fp->index);
1723 q_params.q_obj = &sc->sp_objs[fp->index].q_obj;
1724 /* We want to wait for completion in this context */
1725 bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
1727 /* Stop the primary connection: */
1729 /* ...halt the connection */
1730 q_params.cmd = ECORE_Q_CMD_HALT;
1731 rc = ecore_queue_state_change(sc, &q_params);
1736 /* ...terminate the connection */
1737 q_params.cmd = ECORE_Q_CMD_TERMINATE;
1738 memset(&q_params.params.terminate, 0,
1739 sizeof(q_params.params.terminate));
1740 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
1741 rc = ecore_queue_state_change(sc, &q_params);
1746 /* ...delete cfc entry */
1747 q_params.cmd = ECORE_Q_CMD_CFC_DEL;
1748 memset(&q_params.params.cfc_del, 0, sizeof(q_params.params.cfc_del));
1749 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
1750 return ecore_queue_state_change(sc, &q_params);
1753 /* wait for the outstanding SP commands */
1754 static uint8_t bnx2x_wait_sp_comp(struct bnx2x_softc *sc, unsigned long mask)
1757 int tout = 5000; /* wait for 5 secs tops */
1761 if (!(atomic_load_acq_long(&sc->sp_state) & mask)) {
1770 tmp = atomic_load_acq_long(&sc->sp_state);
1772 PMD_DRV_LOG(INFO, sc, "Filtering completion timed out: "
1773 "sp_state 0x%lx, mask 0x%lx", tmp, mask);
1780 static int bnx2x_func_stop(struct bnx2x_softc *sc)
1782 struct ecore_func_state_params func_params = { NULL };
1785 /* prepare parameters for function state transitions */
1786 bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1787 func_params.f_obj = &sc->func_obj;
1788 func_params.cmd = ECORE_F_CMD_STOP;
1791 * Try to stop the function the 'good way'. If it fails (in case
1792 * of a parity error during bnx2x_chip_cleanup()) and we are
1793 * not in a debug mode, perform a state transaction in order to
1794 * enable further HW_RESET transaction.
1796 rc = ecore_func_state_change(sc, &func_params);
1798 PMD_DRV_LOG(NOTICE, sc, "FUNC_STOP ramrod failed. "
1799 "Running a dry transaction");
1800 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1801 return ecore_func_state_change(sc, &func_params);
1807 static int bnx2x_reset_hw(struct bnx2x_softc *sc, uint32_t load_code)
1809 struct ecore_func_state_params func_params = { NULL };
1811 /* Prepare parameters for function state transitions */
1812 bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1814 func_params.f_obj = &sc->func_obj;
1815 func_params.cmd = ECORE_F_CMD_HW_RESET;
1817 func_params.params.hw_init.load_phase = load_code;
1819 return ecore_func_state_change(sc, &func_params);
1822 static void bnx2x_int_disable_sync(struct bnx2x_softc *sc, int disable_hw)
1825 /* prevent the HW from sending interrupts */
1826 bnx2x_int_disable(sc);
1831 bnx2x_chip_cleanup(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1833 int port = SC_PORT(sc);
1834 struct ecore_mcast_ramrod_params rparam = { NULL };
1835 uint32_t reset_code;
1838 bnx2x_drain_tx_queues(sc);
1840 /* give HW time to discard old tx messages */
1843 /* Clean all ETH MACs */
1844 rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_ETH_MAC,
1847 PMD_DRV_LOG(NOTICE, sc,
1848 "Failed to delete all ETH MACs (%d)", rc);
1851 /* Clean up UC list */
1852 rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_UC_LIST_MAC,
1855 PMD_DRV_LOG(NOTICE, sc,
1856 "Failed to delete UC MACs list (%d)", rc);
1860 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
1862 /* Set "drop all" to stop Rx */
1865 * We need to take the if_maddr_lock() here in order to prevent
1866 * a race between the completion code and this code.
1869 if (bnx2x_test_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) {
1870 bnx2x_set_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state);
1872 bnx2x_set_storm_rx_mode(sc);
1875 /* Clean up multicast configuration */
1876 rparam.mcast_obj = &sc->mcast_obj;
1877 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1879 PMD_DRV_LOG(NOTICE, sc,
1880 "Failed to send DEL MCAST command (%d)", rc);
1884 * Send the UNLOAD_REQUEST to the MCP. This will return if
1885 * this function should perform FUNCTION, PORT, or COMMON HW
1888 reset_code = bnx2x_send_unload_req(sc, unload_mode);
1891 * (assumption: No Attention from MCP at this stage)
1892 * PMF probably in the middle of TX disable/enable transaction
1894 rc = bnx2x_func_wait_started(sc);
1896 PMD_DRV_LOG(NOTICE, sc, "bnx2x_func_wait_started failed");
1900 * Close multi and leading connections
1901 * Completions for ramrods are collected in a synchronous way
1903 for (i = 0; i < sc->num_queues; i++) {
1904 if (bnx2x_stop_queue(sc, i)) {
1910 * If SP settings didn't get completed so far - something
1911 * very wrong has happen.
1913 if (!bnx2x_wait_sp_comp(sc, ~0x0UL)) {
1914 PMD_DRV_LOG(NOTICE, sc, "Common slow path ramrods got stuck!");
1919 rc = bnx2x_func_stop(sc);
1921 PMD_DRV_LOG(NOTICE, sc, "Function stop failed!");
1924 /* disable HW interrupts */
1925 bnx2x_int_disable_sync(sc, TRUE);
1927 /* Reset the chip */
1928 rc = bnx2x_reset_hw(sc, reset_code);
1930 PMD_DRV_LOG(NOTICE, sc, "Hardware reset failed");
1933 /* Report UNLOAD_DONE to MCP */
1934 bnx2x_send_unload_done(sc, keep_link);
1937 static void bnx2x_disable_close_the_gate(struct bnx2x_softc *sc)
1941 PMD_DRV_LOG(DEBUG, sc, "Disabling 'close the gates'");
1943 val = REG_RD(sc, MISC_REG_AEU_GENERAL_MASK);
1944 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
1945 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
1946 REG_WR(sc, MISC_REG_AEU_GENERAL_MASK, val);
1950 * Cleans the object that have internal lists without sending
1951 * ramrods. Should be run when interrutps are disabled.
1953 static void bnx2x_squeeze_objects(struct bnx2x_softc *sc)
1955 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1956 struct ecore_mcast_ramrod_params rparam = { NULL };
1957 struct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj;
1960 /* Cleanup MACs' object first... */
1962 /* Wait for completion of requested */
1963 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1964 /* Perform a dry cleanup */
1965 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &ramrod_flags);
1967 /* Clean ETH primary MAC */
1968 bnx2x_set_bit(ECORE_ETH_MAC, &vlan_mac_flags);
1969 rc = mac_obj->delete_all(sc, &sc->sp_objs->mac_obj, &vlan_mac_flags,
1972 PMD_DRV_LOG(NOTICE, sc, "Failed to clean ETH MACs (%d)", rc);
1975 /* Cleanup UC list */
1977 bnx2x_set_bit(ECORE_UC_LIST_MAC, &vlan_mac_flags);
1978 rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1980 PMD_DRV_LOG(NOTICE, sc,
1981 "Failed to clean UC list MACs (%d)", rc);
1984 /* Now clean mcast object... */
1986 rparam.mcast_obj = &sc->mcast_obj;
1987 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags);
1989 /* Add a DEL command... */
1990 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1992 PMD_DRV_LOG(NOTICE, sc,
1993 "Failed to send DEL MCAST command (%d)", rc);
1996 /* now wait until all pending commands are cleared */
1998 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
2001 PMD_DRV_LOG(NOTICE, sc,
2002 "Failed to clean MCAST object (%d)", rc);
2006 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
2010 /* stop the controller */
2013 bnx2x_nic_unload(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
2015 uint8_t global = FALSE;
2018 PMD_INIT_FUNC_TRACE(sc);
2020 PMD_DRV_LOG(DEBUG, sc, "Starting NIC unload...");
2022 /* mark driver as unloaded in shmem2 */
2023 if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
2024 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
2025 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
2026 val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
2029 if (IS_PF(sc) && sc->recovery_state != BNX2X_RECOVERY_DONE &&
2030 (sc->state == BNX2X_STATE_CLOSED || sc->state == BNX2X_STATE_ERROR)) {
2032 * We can get here if the driver has been unloaded
2033 * during parity error recovery and is either waiting for a
2034 * leader to complete or for other functions to unload and
2035 * then ifconfig down has been issued. In this case we want to
2036 * unload and let other functions to complete a recovery
2039 sc->recovery_state = BNX2X_RECOVERY_DONE;
2041 bnx2x_release_leader_lock(sc);
2044 PMD_DRV_LOG(NOTICE, sc, "Can't unload in closed or error state");
2049 * Nothing to do during unload if previous bnx2x_nic_load()
2050 * did not completed successfully - all resourses are released.
2052 if ((sc->state == BNX2X_STATE_CLOSED) || (sc->state == BNX2X_STATE_ERROR)) {
2056 sc->state = BNX2X_STATE_CLOSING_WAITING_HALT;
2059 sc->rx_mode = BNX2X_RX_MODE_NONE;
2060 bnx2x_set_rx_mode(sc);
2064 /* set ALWAYS_ALIVE bit in shmem */
2065 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2067 bnx2x_drv_pulse(sc);
2069 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2070 bnx2x_save_statistics(sc);
2073 /* wait till consumers catch up with producers in all queues */
2074 bnx2x_drain_tx_queues(sc);
2076 /* if VF indicate to PF this function is going down (PF will delete sp
2077 * elements and clear initializations
2080 bnx2x_vf_unload(sc);
2081 } else if (unload_mode != UNLOAD_RECOVERY) {
2082 /* if this is a normal/close unload need to clean up chip */
2083 bnx2x_chip_cleanup(sc, unload_mode, keep_link);
2085 /* Send the UNLOAD_REQUEST to the MCP */
2086 bnx2x_send_unload_req(sc, unload_mode);
2089 * Prevent transactions to host from the functions on the
2090 * engine that doesn't reset global blocks in case of global
2091 * attention once gloabl blocks are reset and gates are opened
2092 * (the engine which leader will perform the recovery
2095 if (!CHIP_IS_E1x(sc)) {
2096 bnx2x_pf_disable(sc);
2099 /* disable HW interrupts */
2100 bnx2x_int_disable_sync(sc, TRUE);
2102 /* Report UNLOAD_DONE to MCP */
2103 bnx2x_send_unload_done(sc, FALSE);
2107 * At this stage no more interrupts will arrive so we may safely clean
2108 * the queue'able objects here in case they failed to get cleaned so far.
2111 bnx2x_squeeze_objects(sc);
2114 /* There should be no more pending SP commands at this stage */
2123 /* free the host hardware/software hsi structures */
2124 bnx2x_free_hsi_mem(sc);
2126 bnx2x_free_fw_stats_mem(sc);
2128 sc->state = BNX2X_STATE_CLOSED;
2131 * Check if there are pending parity attentions. If there are - set
2132 * RECOVERY_IN_PROGRESS.
2134 if (IS_PF(sc) && bnx2x_chk_parity_attn(sc, &global, FALSE)) {
2135 bnx2x_set_reset_in_progress(sc);
2137 /* Set RESET_IS_GLOBAL if needed */
2139 bnx2x_set_reset_global(sc);
2144 * The last driver must disable a "close the gate" if there is no
2145 * parity attention or "process kill" pending.
2147 if (IS_PF(sc) && !bnx2x_clear_pf_load(sc) &&
2148 bnx2x_reset_is_done(sc, SC_PATH(sc))) {
2149 bnx2x_disable_close_the_gate(sc);
2152 PMD_DRV_LOG(DEBUG, sc, "Ended NIC unload");
2158 * Encapsulte an mbuf cluster into the tx bd chain and makes the memory
2159 * visible to the controller.
2161 * If an mbuf is submitted to this routine and cannot be given to the
2162 * controller (e.g. it has too many fragments) then the function may free
2163 * the mbuf and return to the caller.
2166 * int: Number of TX BDs used for the mbuf
2168 * Note the side effect that an mbuf may be freed if it causes a problem.
2170 int bnx2x_tx_encap(struct bnx2x_tx_queue *txq, struct rte_mbuf *m0)
2172 struct eth_tx_start_bd *tx_start_bd;
2173 uint16_t bd_prod, pkt_prod;
2174 struct bnx2x_softc *sc;
2178 bd_prod = txq->tx_bd_tail;
2179 pkt_prod = txq->tx_pkt_tail;
2181 txq->sw_ring[TX_BD(pkt_prod, txq)] = m0;
2183 tx_start_bd = &txq->tx_ring[TX_BD(bd_prod, txq)].start_bd;
2185 tx_start_bd->addr_lo =
2186 rte_cpu_to_le_32(U64_LO(rte_mbuf_data_iova(m0)));
2187 tx_start_bd->addr_hi =
2188 rte_cpu_to_le_32(U64_HI(rte_mbuf_data_iova(m0)));
2189 tx_start_bd->nbytes = rte_cpu_to_le_16(m0->data_len);
2190 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2191 tx_start_bd->general_data =
2192 (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
2194 tx_start_bd->nbd = rte_cpu_to_le_16(2);
2196 if (m0->ol_flags & PKT_TX_VLAN_PKT) {
2197 tx_start_bd->vlan_or_ethertype =
2198 rte_cpu_to_le_16(m0->vlan_tci);
2199 tx_start_bd->bd_flags.as_bitfield |=
2200 (X_ETH_OUTBAND_VLAN <<
2201 ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT);
2204 tx_start_bd->vlan_or_ethertype =
2205 rte_cpu_to_le_16(pkt_prod);
2207 struct rte_ether_hdr *eh =
2208 rte_pktmbuf_mtod(m0, struct rte_ether_hdr *);
2210 tx_start_bd->vlan_or_ethertype =
2211 rte_cpu_to_le_16(rte_be_to_cpu_16(eh->ether_type));
2215 bd_prod = NEXT_TX_BD(bd_prod);
2217 struct eth_tx_parse_bd_e2 *tx_parse_bd;
2218 const struct rte_ether_hdr *eh =
2219 rte_pktmbuf_mtod(m0, struct rte_ether_hdr *);
2220 uint8_t mac_type = UNICAST_ADDRESS;
2223 &txq->tx_ring[TX_BD(bd_prod, txq)].parse_bd_e2;
2224 if (rte_is_multicast_ether_addr(&eh->d_addr)) {
2225 if (rte_is_broadcast_ether_addr(&eh->d_addr))
2226 mac_type = BROADCAST_ADDRESS;
2228 mac_type = MULTICAST_ADDRESS;
2230 tx_parse_bd->parsing_data =
2231 (mac_type << ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT);
2233 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_hi,
2234 &eh->d_addr.addr_bytes[0], 2);
2235 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_mid,
2236 &eh->d_addr.addr_bytes[2], 2);
2237 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_lo,
2238 &eh->d_addr.addr_bytes[4], 2);
2239 rte_memcpy(&tx_parse_bd->data.mac_addr.src_hi,
2240 &eh->s_addr.addr_bytes[0], 2);
2241 rte_memcpy(&tx_parse_bd->data.mac_addr.src_mid,
2242 &eh->s_addr.addr_bytes[2], 2);
2243 rte_memcpy(&tx_parse_bd->data.mac_addr.src_lo,
2244 &eh->s_addr.addr_bytes[4], 2);
2246 tx_parse_bd->data.mac_addr.dst_hi =
2247 rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_hi);
2248 tx_parse_bd->data.mac_addr.dst_mid =
2249 rte_cpu_to_be_16(tx_parse_bd->data.
2251 tx_parse_bd->data.mac_addr.dst_lo =
2252 rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_lo);
2253 tx_parse_bd->data.mac_addr.src_hi =
2254 rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_hi);
2255 tx_parse_bd->data.mac_addr.src_mid =
2256 rte_cpu_to_be_16(tx_parse_bd->data.
2258 tx_parse_bd->data.mac_addr.src_lo =
2259 rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_lo);
2262 "PBD dst %x %x %x src %x %x %x p_data %x",
2263 tx_parse_bd->data.mac_addr.dst_hi,
2264 tx_parse_bd->data.mac_addr.dst_mid,
2265 tx_parse_bd->data.mac_addr.dst_lo,
2266 tx_parse_bd->data.mac_addr.src_hi,
2267 tx_parse_bd->data.mac_addr.src_mid,
2268 tx_parse_bd->data.mac_addr.src_lo,
2269 tx_parse_bd->parsing_data);
2273 "start bd: nbytes %d flags %x vlan %x",
2274 tx_start_bd->nbytes,
2275 tx_start_bd->bd_flags.as_bitfield,
2276 tx_start_bd->vlan_or_ethertype);
2278 bd_prod = NEXT_TX_BD(bd_prod);
2281 if (TX_IDX(bd_prod) < 2)
2284 txq->nb_tx_avail -= 2;
2285 txq->tx_bd_tail = bd_prod;
2286 txq->tx_pkt_tail = pkt_prod;
2291 static uint16_t bnx2x_cid_ilt_lines(struct bnx2x_softc *sc)
2293 return L2_ILT_LINES(sc);
2296 static void bnx2x_ilt_set_info(struct bnx2x_softc *sc)
2298 struct ilt_client_info *ilt_client;
2299 struct ecore_ilt *ilt = sc->ilt;
2302 PMD_INIT_FUNC_TRACE(sc);
2304 ilt->start_line = FUNC_ILT_BASE(SC_FUNC(sc));
2307 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
2308 ilt_client->client_num = ILT_CLIENT_CDU;
2309 ilt_client->page_size = CDU_ILT_PAGE_SZ;
2310 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
2311 ilt_client->start = line;
2312 line += bnx2x_cid_ilt_lines(sc);
2314 if (CNIC_SUPPORT(sc)) {
2315 line += CNIC_ILT_LINES;
2318 ilt_client->end = (line - 1);
2321 if (QM_INIT(sc->qm_cid_count)) {
2322 ilt_client = &ilt->clients[ILT_CLIENT_QM];
2323 ilt_client->client_num = ILT_CLIENT_QM;
2324 ilt_client->page_size = QM_ILT_PAGE_SZ;
2325 ilt_client->flags = 0;
2326 ilt_client->start = line;
2328 /* 4 bytes for each cid */
2329 line += DIV_ROUND_UP(sc->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
2332 ilt_client->end = (line - 1);
2335 if (CNIC_SUPPORT(sc)) {
2337 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
2338 ilt_client->client_num = ILT_CLIENT_SRC;
2339 ilt_client->page_size = SRC_ILT_PAGE_SZ;
2340 ilt_client->flags = 0;
2341 ilt_client->start = line;
2342 line += SRC_ILT_LINES;
2343 ilt_client->end = (line - 1);
2346 ilt_client = &ilt->clients[ILT_CLIENT_TM];
2347 ilt_client->client_num = ILT_CLIENT_TM;
2348 ilt_client->page_size = TM_ILT_PAGE_SZ;
2349 ilt_client->flags = 0;
2350 ilt_client->start = line;
2351 line += TM_ILT_LINES;
2352 ilt_client->end = (line - 1);
2355 assert((line <= ILT_MAX_LINES));
2358 static void bnx2x_set_fp_rx_buf_size(struct bnx2x_softc *sc)
2362 for (i = 0; i < sc->num_queues; i++) {
2363 /* get the Rx buffer size for RX frames */
2364 sc->fp[i].rx_buf_size =
2365 (IP_HEADER_ALIGNMENT_PADDING + ETH_OVERHEAD + sc->mtu);
2369 int bnx2x_alloc_ilt_mem(struct bnx2x_softc *sc)
2372 sc->ilt = rte_malloc("", sizeof(struct ecore_ilt), RTE_CACHE_LINE_SIZE);
2374 return sc->ilt == NULL;
2377 static int bnx2x_alloc_ilt_lines_mem(struct bnx2x_softc *sc)
2379 sc->ilt->lines = rte_calloc("",
2380 sizeof(struct ilt_line), ILT_MAX_LINES,
2381 RTE_CACHE_LINE_SIZE);
2382 return sc->ilt->lines == NULL;
2385 void bnx2x_free_ilt_mem(struct bnx2x_softc *sc)
2391 static void bnx2x_free_ilt_lines_mem(struct bnx2x_softc *sc)
2393 if (sc->ilt->lines != NULL) {
2394 rte_free(sc->ilt->lines);
2395 sc->ilt->lines = NULL;
2399 static void bnx2x_free_mem(struct bnx2x_softc *sc)
2403 for (i = 0; i < L2_ILT_LINES(sc); i++) {
2404 sc->context[i].vcxt = NULL;
2405 sc->context[i].size = 0;
2408 ecore_ilt_mem_op(sc, ILT_MEMOP_FREE);
2410 bnx2x_free_ilt_lines_mem(sc);
2413 static int bnx2x_alloc_mem(struct bnx2x_softc *sc)
2418 char cdu_name[RTE_MEMZONE_NAMESIZE];
2421 * Allocate memory for CDU context:
2422 * This memory is allocated separately and not in the generic ILT
2423 * functions because CDU differs in few aspects:
2424 * 1. There can be multiple entities allocating memory for context -
2425 * regular L2, CNIC, and SRIOV drivers. Each separately controls
2426 * its own ILT lines.
2427 * 2. Since CDU page-size is not a single 4KB page (which is the case
2428 * for the other ILT clients), to be efficient we want to support
2429 * allocation of sub-page-size in the last entry.
2430 * 3. Context pointers are used by the driver to pass to FW / update
2431 * the context (for the other ILT clients the pointers are used just to
2432 * free the memory during unload).
2434 context_size = (sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(sc));
2435 for (i = 0, allocated = 0; allocated < context_size; i++) {
2436 sc->context[i].size = min(CDU_ILT_PAGE_SZ,
2437 (context_size - allocated));
2439 snprintf(cdu_name, sizeof(cdu_name), "cdu_%d", i);
2440 if (bnx2x_dma_alloc(sc, sc->context[i].size,
2441 &sc->context[i].vcxt_dma,
2442 cdu_name, BNX2X_PAGE_SIZE) != 0) {
2447 sc->context[i].vcxt =
2448 (union cdu_context *)sc->context[i].vcxt_dma.vaddr;
2450 allocated += sc->context[i].size;
2453 bnx2x_alloc_ilt_lines_mem(sc);
2455 if (ecore_ilt_mem_op(sc, ILT_MEMOP_ALLOC)) {
2456 PMD_DRV_LOG(NOTICE, sc, "ecore_ilt_mem_op ILT_MEMOP_ALLOC failed");
2464 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc)
2466 bnx2x_dma_free(&sc->fw_stats_dma);
2467 sc->fw_stats_num = 0;
2469 sc->fw_stats_req_size = 0;
2470 sc->fw_stats_req = NULL;
2471 sc->fw_stats_req_mapping = 0;
2473 sc->fw_stats_data_size = 0;
2474 sc->fw_stats_data = NULL;
2475 sc->fw_stats_data_mapping = 0;
2478 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc)
2480 uint8_t num_queue_stats;
2481 int num_groups, vf_headroom = 0;
2483 /* number of queues for statistics is number of eth queues */
2484 num_queue_stats = BNX2X_NUM_ETH_QUEUES(sc);
2487 * Total number of FW statistics requests =
2488 * 1 for port stats + 1 for PF stats + num of queues
2490 sc->fw_stats_num = (2 + num_queue_stats);
2493 * Request is built from stats_query_header and an array of
2494 * stats_query_cmd_group each of which contains STATS_QUERY_CMD_COUNT
2495 * rules. The real number or requests is configured in the
2496 * stats_query_header.
2498 num_groups = (sc->fw_stats_num + vf_headroom) / STATS_QUERY_CMD_COUNT;
2499 if ((sc->fw_stats_num + vf_headroom) % STATS_QUERY_CMD_COUNT)
2502 sc->fw_stats_req_size =
2503 (sizeof(struct stats_query_header) +
2504 (num_groups * sizeof(struct stats_query_cmd_group)));
2507 * Data for statistics requests + stats_counter.
2508 * stats_counter holds per-STORM counters that are incremented when
2509 * STORM has finished with the current request. Memory for FCoE
2510 * offloaded statistics are counted anyway, even if they will not be sent.
2511 * VF stats are not accounted for here as the data of VF stats is stored
2512 * in memory allocated by the VF, not here.
2514 sc->fw_stats_data_size =
2515 (sizeof(struct stats_counter) +
2516 sizeof(struct per_port_stats) + sizeof(struct per_pf_stats) +
2517 /* sizeof(struct fcoe_statistics_params) + */
2518 (sizeof(struct per_queue_stats) * num_queue_stats));
2520 if (bnx2x_dma_alloc(sc, (sc->fw_stats_req_size + sc->fw_stats_data_size),
2521 &sc->fw_stats_dma, "fw_stats",
2522 RTE_CACHE_LINE_SIZE) != 0) {
2523 bnx2x_free_fw_stats_mem(sc);
2527 /* set up the shortcuts */
2529 sc->fw_stats_req = (struct bnx2x_fw_stats_req *)sc->fw_stats_dma.vaddr;
2530 sc->fw_stats_req_mapping = sc->fw_stats_dma.paddr;
2533 (struct bnx2x_fw_stats_data *)((uint8_t *) sc->fw_stats_dma.vaddr +
2534 sc->fw_stats_req_size);
2535 sc->fw_stats_data_mapping = (sc->fw_stats_dma.paddr +
2536 sc->fw_stats_req_size);
2543 * 0-7 - Engine0 load counter.
2544 * 8-15 - Engine1 load counter.
2545 * 16 - Engine0 RESET_IN_PROGRESS bit.
2546 * 17 - Engine1 RESET_IN_PROGRESS bit.
2547 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active
2548 * function on the engine
2549 * 19 - Engine1 ONE_IS_LOADED.
2550 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
2551 * leader to complete (check for both RESET_IN_PROGRESS bits and not
2552 * for just the one belonging to its engine).
2554 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
2555 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
2556 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
2557 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
2558 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
2559 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
2560 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
2561 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
2563 /* set the GLOBAL_RESET bit, should be run under rtnl lock */
2564 static void bnx2x_set_reset_global(struct bnx2x_softc *sc)
2567 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2568 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2569 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
2570 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2573 /* clear the GLOBAL_RESET bit, should be run under rtnl lock */
2574 static void bnx2x_clear_reset_global(struct bnx2x_softc *sc)
2577 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2578 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2579 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
2580 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2583 /* checks the GLOBAL_RESET bit, should be run under rtnl lock */
2584 static uint8_t bnx2x_reset_is_global(struct bnx2x_softc *sc)
2586 return REG_RD(sc, BNX2X_RECOVERY_GLOB_REG) & BNX2X_GLOBAL_RESET_BIT;
2589 /* clear RESET_IN_PROGRESS bit for the engine, should be run under rtnl lock */
2590 static void bnx2x_set_reset_done(struct bnx2x_softc *sc)
2593 uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2594 BNX2X_PATH0_RST_IN_PROG_BIT;
2596 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2598 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2601 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2603 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2606 /* set RESET_IN_PROGRESS for the engine, should be run under rtnl lock */
2607 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc)
2610 uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2611 BNX2X_PATH0_RST_IN_PROG_BIT;
2613 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2615 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2618 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2620 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2623 /* check RESET_IN_PROGRESS bit for an engine, should be run under rtnl lock */
2624 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine)
2626 uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2627 uint32_t bit = engine ? BNX2X_PATH1_RST_IN_PROG_BIT :
2628 BNX2X_PATH0_RST_IN_PROG_BIT;
2630 /* return false if bit is set */
2631 return (val & bit) ? FALSE : TRUE;
2634 /* get the load status for an engine, should be run under rtnl lock */
2635 static uint8_t bnx2x_get_load_status(struct bnx2x_softc *sc, int engine)
2637 uint32_t mask = engine ? BNX2X_PATH1_LOAD_CNT_MASK :
2638 BNX2X_PATH0_LOAD_CNT_MASK;
2639 uint32_t shift = engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2640 BNX2X_PATH0_LOAD_CNT_SHIFT;
2641 uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2643 val = ((val & mask) >> shift);
2648 /* set pf load mark */
2649 static void bnx2x_set_pf_load(struct bnx2x_softc *sc)
2653 uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2654 BNX2X_PATH0_LOAD_CNT_MASK;
2655 uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2656 BNX2X_PATH0_LOAD_CNT_SHIFT;
2658 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2660 PMD_INIT_FUNC_TRACE(sc);
2662 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2664 /* get the current counter value */
2665 val1 = ((val & mask) >> shift);
2667 /* set bit of this PF */
2668 val1 |= (1 << SC_ABS_FUNC(sc));
2670 /* clear the old value */
2673 /* set the new one */
2674 val |= ((val1 << shift) & mask);
2676 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2678 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2681 /* clear pf load mark */
2682 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc)
2685 uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2686 BNX2X_PATH0_LOAD_CNT_MASK;
2687 uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2688 BNX2X_PATH0_LOAD_CNT_SHIFT;
2690 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2691 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2693 /* get the current counter value */
2694 val1 = (val & mask) >> shift;
2696 /* clear bit of that PF */
2697 val1 &= ~(1 << SC_ABS_FUNC(sc));
2699 /* clear the old value */
2702 /* set the new one */
2703 val |= ((val1 << shift) & mask);
2705 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2706 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2710 /* send load requrest to mcp and analyze response */
2711 static int bnx2x_nic_load_request(struct bnx2x_softc *sc, uint32_t * load_code)
2713 PMD_INIT_FUNC_TRACE(sc);
2717 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
2718 DRV_MSG_SEQ_NUMBER_MASK);
2720 PMD_DRV_LOG(DEBUG, sc, "initial fw_seq 0x%04x", sc->fw_seq);
2723 /* get the current FW pulse sequence */
2724 sc->fw_drv_pulse_wr_seq =
2725 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb) &
2726 DRV_PULSE_SEQ_MASK);
2728 /* set ALWAYS_ALIVE bit in shmem */
2729 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2730 bnx2x_drv_pulse(sc);
2734 (*load_code) = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
2735 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
2737 /* if the MCP fails to respond we must abort */
2738 if (!(*load_code)) {
2739 PMD_DRV_LOG(NOTICE, sc, "MCP response failure!");
2743 /* if MCP refused then must abort */
2744 if ((*load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED) {
2745 PMD_DRV_LOG(NOTICE, sc, "MCP refused load request");
2753 * Check whether another PF has already loaded FW to chip. In virtualized
2754 * environments a pf from anoth VM may have already initialized the device
2755 * including loading FW.
2757 static int bnx2x_nic_load_analyze_req(struct bnx2x_softc *sc, uint32_t load_code)
2759 uint32_t my_fw, loaded_fw;
2761 /* is another pf loaded on this engine? */
2762 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
2763 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
2764 /* build my FW version dword */
2765 my_fw = (BNX2X_5710_FW_MAJOR_VERSION +
2766 (BNX2X_5710_FW_MINOR_VERSION << 8) +
2767 (BNX2X_5710_FW_REVISION_VERSION << 16) +
2768 (BNX2X_5710_FW_ENGINEERING_VERSION << 24));
2770 /* read loaded FW from chip */
2771 loaded_fw = REG_RD(sc, XSEM_REG_PRAM);
2772 PMD_DRV_LOG(DEBUG, sc, "loaded FW 0x%08x / my FW 0x%08x",
2775 /* abort nic load if version mismatch */
2776 if (my_fw != loaded_fw) {
2777 PMD_DRV_LOG(NOTICE, sc,
2778 "FW 0x%08x already loaded (mine is 0x%08x)",
2787 /* mark PMF if applicable */
2788 static void bnx2x_nic_load_pmf(struct bnx2x_softc *sc, uint32_t load_code)
2790 uint32_t ncsi_oem_data_addr;
2792 PMD_INIT_FUNC_TRACE(sc);
2794 if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
2795 (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
2796 (load_code == FW_MSG_CODE_DRV_LOAD_PORT)) {
2798 * Barrier here for ordering between the writing to sc->port.pmf here
2799 * and reading it from the periodic task.
2807 PMD_DRV_LOG(DEBUG, sc, "pmf %d", sc->port.pmf);
2809 if (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) {
2810 if (SHMEM2_HAS(sc, ncsi_oem_data_addr)) {
2811 ncsi_oem_data_addr = SHMEM2_RD(sc, ncsi_oem_data_addr);
2812 if (ncsi_oem_data_addr) {
2814 (ncsi_oem_data_addr +
2815 offsetof(struct glob_ncsi_oem_data,
2816 driver_version)), 0);
2822 static void bnx2x_read_mf_cfg(struct bnx2x_softc *sc)
2824 int n = (CHIP_IS_MODE_4_PORT(sc) ? 2 : 1);
2828 if (BNX2X_NOMCP(sc)) {
2829 return; /* what should be the default bvalue in this case */
2833 * The formula for computing the absolute function number is...
2834 * For 2 port configuration (4 functions per port):
2835 * abs_func = 2 * vn + SC_PORT + SC_PATH
2836 * For 4 port configuration (2 functions per port):
2837 * abs_func = 4 * vn + 2 * SC_PORT + SC_PATH
2839 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
2840 abs_func = (n * (2 * vn + SC_PORT(sc)) + SC_PATH(sc));
2841 if (abs_func >= E1H_FUNC_MAX) {
2844 sc->devinfo.mf_info.mf_config[vn] =
2845 MFCFG_RD(sc, func_mf_config[abs_func].config);
2848 if (sc->devinfo.mf_info.mf_config[SC_VN(sc)] &
2849 FUNC_MF_CFG_FUNC_DISABLED) {
2850 PMD_DRV_LOG(DEBUG, sc, "mf_cfg function disabled");
2851 sc->flags |= BNX2X_MF_FUNC_DIS;
2853 PMD_DRV_LOG(DEBUG, sc, "mf_cfg function enabled");
2854 sc->flags &= ~BNX2X_MF_FUNC_DIS;
2858 /* acquire split MCP access lock register */
2859 static int bnx2x_acquire_alr(struct bnx2x_softc *sc)
2863 for (j = 0; j < 1000; j++) {
2865 REG_WR(sc, GRCBASE_MCP + 0x9c, val);
2866 val = REG_RD(sc, GRCBASE_MCP + 0x9c);
2867 if (val & (1L << 31))
2873 if (!(val & (1L << 31))) {
2874 PMD_DRV_LOG(NOTICE, sc, "Cannot acquire MCP access lock register");
2881 /* release split MCP access lock register */
2882 static void bnx2x_release_alr(struct bnx2x_softc *sc)
2884 REG_WR(sc, GRCBASE_MCP + 0x9c, 0);
2887 static void bnx2x_fan_failure(struct bnx2x_softc *sc)
2889 int port = SC_PORT(sc);
2890 uint32_t ext_phy_config;
2892 /* mark the failure */
2894 SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
2896 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2897 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
2898 SHMEM_WR(sc, dev_info.port_hw_config[port].external_phy_config,
2901 /* log the failure */
2902 PMD_DRV_LOG(INFO, sc,
2903 "Fan Failure has caused the driver to shutdown "
2904 "the card to prevent permanent damage. "
2905 "Please contact OEM Support for assistance");
2907 rte_panic("Schedule task to handle fan failure");
2910 /* this function is called upon a link interrupt */
2911 static void bnx2x_link_attn(struct bnx2x_softc *sc)
2913 uint32_t pause_enabled = 0;
2914 struct host_port_stats *pstats;
2917 /* Make sure that we are synced with the current statistics */
2918 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2920 elink_link_update(&sc->link_params, &sc->link_vars);
2922 if (sc->link_vars.link_up) {
2924 /* dropless flow control */
2925 if (sc->dropless_fc) {
2928 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
2933 (BAR_USTRORM_INTMEM +
2934 USTORM_ETH_PAUSE_ENABLED_OFFSET(SC_PORT(sc))),
2938 if (sc->link_vars.mac_type != ELINK_MAC_TYPE_EMAC) {
2939 pstats = BNX2X_SP(sc, port_stats);
2940 /* reset old mac stats */
2941 memset(&(pstats->mac_stx[0]), 0,
2942 sizeof(struct mac_stx));
2945 if (sc->state == BNX2X_STATE_OPEN) {
2946 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
2950 if (sc->link_vars.link_up && sc->link_vars.line_speed) {
2951 cmng_fns = bnx2x_get_cmng_fns_mode(sc);
2953 if (cmng_fns != CMNG_FNS_NONE) {
2954 bnx2x_cmng_fns_init(sc, FALSE, cmng_fns);
2955 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
2959 bnx2x_link_report_locked(sc);
2962 bnx2x_link_sync_notify(sc);
2966 static void bnx2x_attn_int_asserted(struct bnx2x_softc *sc, uint32_t asserted)
2968 int port = SC_PORT(sc);
2969 uint32_t aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2970 MISC_REG_AEU_MASK_ATTN_FUNC_0;
2971 uint32_t nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2972 NIG_REG_MASK_INTERRUPT_PORT0;
2974 uint32_t nig_mask = 0;
2979 if (sc->attn_state & asserted) {
2980 PMD_DRV_LOG(ERR, sc, "IGU ERROR attn=0x%08x", asserted);
2983 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2985 aeu_mask = REG_RD(sc, aeu_addr);
2987 aeu_mask &= ~(asserted & 0x3ff);
2989 REG_WR(sc, aeu_addr, aeu_mask);
2991 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2993 sc->attn_state |= asserted;
2995 if (asserted & ATTN_HARD_WIRED_MASK) {
2996 if (asserted & ATTN_NIG_FOR_FUNC) {
2998 bnx2x_acquire_phy_lock(sc);
2999 /* save nig interrupt mask */
3000 nig_mask = REG_RD(sc, nig_int_mask_addr);
3002 /* If nig_mask is not set, no need to call the update function */
3004 REG_WR(sc, nig_int_mask_addr, 0);
3006 bnx2x_link_attn(sc);
3009 /* handle unicore attn? */
3012 if (asserted & ATTN_SW_TIMER_4_FUNC) {
3013 PMD_DRV_LOG(DEBUG, sc, "ATTN_SW_TIMER_4_FUNC!");
3016 if (asserted & GPIO_2_FUNC) {
3017 PMD_DRV_LOG(DEBUG, sc, "GPIO_2_FUNC!");
3020 if (asserted & GPIO_3_FUNC) {
3021 PMD_DRV_LOG(DEBUG, sc, "GPIO_3_FUNC!");
3024 if (asserted & GPIO_4_FUNC) {
3025 PMD_DRV_LOG(DEBUG, sc, "GPIO_4_FUNC!");
3029 if (asserted & ATTN_GENERAL_ATTN_1) {
3030 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_1!");
3031 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3033 if (asserted & ATTN_GENERAL_ATTN_2) {
3034 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_2!");
3035 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3037 if (asserted & ATTN_GENERAL_ATTN_3) {
3038 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_3!");
3039 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3042 if (asserted & ATTN_GENERAL_ATTN_4) {
3043 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_4!");
3044 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3046 if (asserted & ATTN_GENERAL_ATTN_5) {
3047 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_5!");
3048 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3050 if (asserted & ATTN_GENERAL_ATTN_6) {
3051 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_6!");
3052 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3057 if (sc->devinfo.int_block == INT_BLOCK_HC) {
3059 (HC_REG_COMMAND_REG + port * 32 +
3060 COMMAND_REG_ATTN_BITS_SET);
3062 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER * 8);
3065 PMD_DRV_LOG(DEBUG, sc, "about to mask 0x%08x at %s addr 0x%08x",
3067 (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
3069 REG_WR(sc, reg_addr, asserted);
3071 /* now set back the mask */
3072 if (asserted & ATTN_NIG_FOR_FUNC) {
3074 * Verify that IGU ack through BAR was written before restoring
3075 * NIG mask. This loop should exit after 2-3 iterations max.
3077 if (sc->devinfo.int_block != INT_BLOCK_HC) {
3082 REG_RD(sc, IGU_REG_ATTENTION_ACK_BITS);
3083 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0)
3084 && (++cnt < MAX_IGU_ATTN_ACK_TO));
3087 PMD_DRV_LOG(ERR, sc,
3088 "Failed to verify IGU ack on time");
3094 REG_WR(sc, nig_int_mask_addr, nig_mask);
3096 bnx2x_release_phy_lock(sc);
3101 bnx2x_print_next_block(__rte_unused struct bnx2x_softc *sc, __rte_unused int idx,
3102 __rte_unused const char *blk)
3104 PMD_DRV_LOG(INFO, sc, "%s%s", idx ? ", " : "", blk);
3108 bnx2x_check_blocks_with_parity0(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3111 uint32_t cur_bit = 0;
3114 for (i = 0; sig; i++) {
3115 cur_bit = ((uint32_t) 0x1 << i);
3116 if (sig & cur_bit) {
3118 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3120 bnx2x_print_next_block(sc, par_num++,
3123 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3125 bnx2x_print_next_block(sc, par_num++,
3128 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3130 bnx2x_print_next_block(sc, par_num++,
3133 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3135 bnx2x_print_next_block(sc, par_num++,
3138 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3140 bnx2x_print_next_block(sc, par_num++,
3143 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3145 bnx2x_print_next_block(sc, par_num++,
3148 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3150 bnx2x_print_next_block(sc, par_num++,
3164 bnx2x_check_blocks_with_parity1(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3165 uint8_t * global, uint8_t print)
3168 uint32_t cur_bit = 0;
3169 for (i = 0; sig; i++) {
3170 cur_bit = ((uint32_t) 0x1 << i);
3171 if (sig & cur_bit) {
3173 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3175 bnx2x_print_next_block(sc, par_num++,
3178 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3180 bnx2x_print_next_block(sc, par_num++,
3183 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3185 bnx2x_print_next_block(sc, par_num++,
3188 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3190 bnx2x_print_next_block(sc, par_num++,
3193 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
3195 bnx2x_print_next_block(sc, par_num++,
3198 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3200 bnx2x_print_next_block(sc, par_num++,
3203 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3205 bnx2x_print_next_block(sc, par_num++,
3208 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
3210 bnx2x_print_next_block(sc, par_num++,
3213 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3215 bnx2x_print_next_block(sc, par_num++,
3219 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3221 bnx2x_print_next_block(sc, par_num++,
3224 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3226 bnx2x_print_next_block(sc, par_num++,
3229 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
3231 bnx2x_print_next_block(sc, par_num++,
3234 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3236 bnx2x_print_next_block(sc, par_num++,
3239 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3241 bnx2x_print_next_block(sc, par_num++,
3244 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3246 bnx2x_print_next_block(sc, par_num++,
3249 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
3251 bnx2x_print_next_block(sc, par_num++,
3265 bnx2x_check_blocks_with_parity2(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3268 uint32_t cur_bit = 0;
3271 for (i = 0; sig; i++) {
3272 cur_bit = ((uint32_t) 0x1 << i);
3273 if (sig & cur_bit) {
3275 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3277 bnx2x_print_next_block(sc, par_num++,
3280 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3282 bnx2x_print_next_block(sc, par_num++,
3285 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3287 bnx2x_print_next_block(sc, par_num++,
3288 "PXPPCICLOCKCLIENT");
3290 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3292 bnx2x_print_next_block(sc, par_num++,
3295 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3297 bnx2x_print_next_block(sc, par_num++,
3300 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
3302 bnx2x_print_next_block(sc, par_num++,
3305 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3307 bnx2x_print_next_block(sc, par_num++,
3310 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3312 bnx2x_print_next_block(sc, par_num++,
3326 bnx2x_check_blocks_with_parity3(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3327 uint8_t * global, uint8_t print)
3329 uint32_t cur_bit = 0;
3332 for (i = 0; sig; i++) {
3333 cur_bit = ((uint32_t) 0x1 << i);
3334 if (sig & cur_bit) {
3336 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3338 bnx2x_print_next_block(sc, par_num++,
3342 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3344 bnx2x_print_next_block(sc, par_num++,
3348 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3350 bnx2x_print_next_block(sc, par_num++,
3354 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3356 bnx2x_print_next_block(sc, par_num++,
3371 bnx2x_check_blocks_with_parity4(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3374 uint32_t cur_bit = 0;
3377 for (i = 0; sig; i++) {
3378 cur_bit = ((uint32_t) 0x1 << i);
3379 if (sig & cur_bit) {
3381 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
3383 bnx2x_print_next_block(sc, par_num++,
3386 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
3388 bnx2x_print_next_block(sc, par_num++,
3402 bnx2x_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print,
3407 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
3408 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
3409 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
3410 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
3411 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
3412 PMD_DRV_LOG(ERR, sc,
3413 "Parity error: HW block parity attention:"
3414 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x",
3415 (uint32_t) (sig[0] & HW_PRTY_ASSERT_SET_0),
3416 (uint32_t) (sig[1] & HW_PRTY_ASSERT_SET_1),
3417 (uint32_t) (sig[2] & HW_PRTY_ASSERT_SET_2),
3418 (uint32_t) (sig[3] & HW_PRTY_ASSERT_SET_3),
3419 (uint32_t) (sig[4] & HW_PRTY_ASSERT_SET_4));
3422 PMD_DRV_LOG(INFO, sc, "Parity errors detected in blocks: ");
3425 bnx2x_check_blocks_with_parity0(sc, sig[0] &
3426 HW_PRTY_ASSERT_SET_0,
3429 bnx2x_check_blocks_with_parity1(sc, sig[1] &
3430 HW_PRTY_ASSERT_SET_1,
3431 par_num, global, print);
3433 bnx2x_check_blocks_with_parity2(sc, sig[2] &
3434 HW_PRTY_ASSERT_SET_2,
3437 bnx2x_check_blocks_with_parity3(sc, sig[3] &
3438 HW_PRTY_ASSERT_SET_3,
3439 par_num, global, print);
3441 bnx2x_check_blocks_with_parity4(sc, sig[4] &
3442 HW_PRTY_ASSERT_SET_4,
3446 PMD_DRV_LOG(INFO, sc, "");
3455 bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print)
3457 struct attn_route attn = { {0} };
3458 int port = SC_PORT(sc);
3460 attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
3461 attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
3462 attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
3463 attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
3465 if (!CHIP_IS_E1x(sc))
3467 REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
3469 return bnx2x_parity_attn(sc, global, print, attn.sig);
3472 static void bnx2x_attn_int_deasserted4(struct bnx2x_softc *sc, uint32_t attn)
3476 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
3477 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
3478 PMD_DRV_LOG(INFO, sc, "ERROR: PGLUE hw attention 0x%08x", val);
3479 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
3480 PMD_DRV_LOG(INFO, sc,
3481 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR");
3482 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
3483 PMD_DRV_LOG(INFO, sc,
3484 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR");
3485 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
3486 PMD_DRV_LOG(INFO, sc,
3487 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN");
3488 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
3489 PMD_DRV_LOG(INFO, sc,
3490 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN");
3492 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
3493 PMD_DRV_LOG(INFO, sc,
3494 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN");
3496 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
3497 PMD_DRV_LOG(INFO, sc,
3498 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN");
3499 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
3500 PMD_DRV_LOG(INFO, sc,
3501 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN");
3502 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
3503 PMD_DRV_LOG(INFO, sc,
3504 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN");
3505 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
3506 PMD_DRV_LOG(INFO, sc,
3507 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW");
3510 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
3511 val = REG_RD(sc, ATC_REG_ATC_INT_STS_CLR);
3512 PMD_DRV_LOG(INFO, sc, "ERROR: ATC hw attention 0x%08x", val);
3513 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
3514 PMD_DRV_LOG(INFO, sc,
3515 "ERROR: ATC_ATC_INT_STS_REG_ADDRESS_ERROR");
3516 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
3517 PMD_DRV_LOG(INFO, sc,
3518 "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND");
3519 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
3520 PMD_DRV_LOG(INFO, sc,
3521 "ERROR: ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS");
3522 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
3523 PMD_DRV_LOG(INFO, sc,
3524 "ERROR: ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT");
3525 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
3526 PMD_DRV_LOG(INFO, sc,
3527 "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR");
3528 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
3529 PMD_DRV_LOG(INFO, sc,
3530 "ERROR: ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU");
3533 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3534 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
3535 PMD_DRV_LOG(INFO, sc,
3536 "ERROR: FATAL parity attention set4 0x%08x",
3538 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
3540 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
3544 static void bnx2x_e1h_disable(struct bnx2x_softc *sc)
3546 int port = SC_PORT(sc);
3548 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
3551 static void bnx2x_e1h_enable(struct bnx2x_softc *sc)
3553 int port = SC_PORT(sc);
3555 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3559 * called due to MCP event (on pmf):
3560 * reread new bandwidth configuration
3562 * notify others function about the change
3564 static void bnx2x_config_mf_bw(struct bnx2x_softc *sc)
3566 if (sc->link_vars.link_up) {
3567 bnx2x_cmng_fns_init(sc, TRUE, CMNG_FNS_MINMAX);
3568 bnx2x_link_sync_notify(sc);
3571 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
3574 static void bnx2x_set_mf_bw(struct bnx2x_softc *sc)
3576 bnx2x_config_mf_bw(sc);
3577 bnx2x_fw_command(sc, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3580 static void bnx2x_handle_eee_event(struct bnx2x_softc *sc)
3582 bnx2x_fw_command(sc, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3585 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3587 static void bnx2x_drv_info_ether_stat(struct bnx2x_softc *sc)
3589 struct eth_stats_info *ether_stat = &sc->sp->drv_info_to_mcp.ether_stat;
3591 strncpy(ether_stat->version, BNX2X_DRIVER_VERSION,
3592 ETH_STAT_INFO_VERSION_LEN);
3594 sc->sp_objs[0].mac_obj.get_n_elements(sc, &sc->sp_objs[0].mac_obj,
3595 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3596 ether_stat->mac_local + MAC_PAD,
3599 ether_stat->mtu_size = sc->mtu;
3601 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3602 ether_stat->promiscuous_mode = 0; // (flags & PROMISC) ? 1 : 0;
3604 ether_stat->txq_size = sc->tx_ring_size;
3605 ether_stat->rxq_size = sc->rx_ring_size;
3608 static void bnx2x_handle_drv_info_req(struct bnx2x_softc *sc)
3610 enum drv_info_opcode op_code;
3611 uint32_t drv_info_ctl = SHMEM2_RD(sc, drv_info_control);
3613 /* if drv_info version supported by MFW doesn't match - send NACK */
3614 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3615 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3619 op_code = ((drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3620 DRV_INFO_CONTROL_OP_CODE_SHIFT);
3622 memset(&sc->sp->drv_info_to_mcp, 0, sizeof(union drv_info_to_mcp));
3625 case ETH_STATS_OPCODE:
3626 bnx2x_drv_info_ether_stat(sc);
3628 case FCOE_STATS_OPCODE:
3629 case ISCSI_STATS_OPCODE:
3631 /* if op code isn't supported - send NACK */
3632 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3637 * If we got drv_info attn from MFW then these fields are defined in
3640 SHMEM2_WR(sc, drv_info_host_addr_lo,
3641 U64_LO(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3642 SHMEM2_WR(sc, drv_info_host_addr_hi,
3643 U64_HI(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3645 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3648 static void bnx2x_dcc_event(struct bnx2x_softc *sc, uint32_t dcc_event)
3650 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3652 * This is the only place besides the function initialization
3653 * where the sc->flags can change so it is done without any
3657 mf_info.mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_DISABLED) {
3658 PMD_DRV_LOG(DEBUG, sc, "mf_cfg function disabled");
3659 sc->flags |= BNX2X_MF_FUNC_DIS;
3660 bnx2x_e1h_disable(sc);
3662 PMD_DRV_LOG(DEBUG, sc, "mf_cfg function enabled");
3663 sc->flags &= ~BNX2X_MF_FUNC_DIS;
3664 bnx2x_e1h_enable(sc);
3666 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3669 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3670 bnx2x_config_mf_bw(sc);
3671 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3674 /* Report results to MCP */
3676 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_FAILURE, 0);
3678 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_OK, 0);
3681 static void bnx2x_pmf_update(struct bnx2x_softc *sc)
3683 int port = SC_PORT(sc);
3689 * We need the mb() to ensure the ordering between the writing to
3690 * sc->port.pmf here and reading it from the bnx2x_periodic_task().
3694 /* enable nig attention */
3695 val = (0xff0f | (1 << (SC_VN(sc) + 4)));
3696 if (sc->devinfo.int_block == INT_BLOCK_HC) {
3697 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, val);
3698 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, val);
3699 } else if (!CHIP_IS_E1x(sc)) {
3700 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
3701 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
3704 bnx2x_stats_handle(sc, STATS_EVENT_PMF);
3707 static int bnx2x_mc_assert(struct bnx2x_softc *sc)
3711 __rte_unused uint32_t row0, row1, row2, row3;
3715 REG_RD8(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_INDEX_OFFSET);
3717 PMD_DRV_LOG(ERR, sc, "XSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3719 /* print the asserts */
3720 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3724 BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i));
3727 BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3731 BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3735 BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3738 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3739 PMD_DRV_LOG(ERR, sc,
3740 "XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3741 i, row3, row2, row1, row0);
3750 REG_RD8(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_INDEX_OFFSET);
3752 PMD_DRV_LOG(ERR, sc, "TSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3755 /* print the asserts */
3756 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3760 BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i));
3763 BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3767 BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3771 BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3774 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3775 PMD_DRV_LOG(ERR, sc,
3776 "TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3777 i, row3, row2, row1, row0);
3786 REG_RD8(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_INDEX_OFFSET);
3788 PMD_DRV_LOG(ERR, sc, "CSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3791 /* print the asserts */
3792 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3796 BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i));
3799 BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3803 BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3807 BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3810 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3811 PMD_DRV_LOG(ERR, sc,
3812 "CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3813 i, row3, row2, row1, row0);
3822 REG_RD8(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_INDEX_OFFSET);
3824 PMD_DRV_LOG(ERR, sc, "USTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3827 /* print the asserts */
3828 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3832 BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i));
3835 BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3839 BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3843 BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3846 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3847 PMD_DRV_LOG(ERR, sc,
3848 "USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3849 i, row3, row2, row1, row0);
3859 static void bnx2x_attn_int_deasserted3(struct bnx2x_softc *sc, uint32_t attn)
3861 int func = SC_FUNC(sc);
3864 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3866 if (attn & BNX2X_PMF_LINK_ASSERT(sc)) {
3868 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
3869 bnx2x_read_mf_cfg(sc);
3870 sc->devinfo.mf_info.mf_config[SC_VN(sc)] =
3872 func_mf_config[SC_ABS_FUNC(sc)].config);
3874 SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_status);
3876 if (val & DRV_STATUS_DCC_EVENT_MASK)
3879 DRV_STATUS_DCC_EVENT_MASK));
3881 if (val & DRV_STATUS_SET_MF_BW)
3882 bnx2x_set_mf_bw(sc);
3884 if (val & DRV_STATUS_DRV_INFO_REQ)
3885 bnx2x_handle_drv_info_req(sc);
3887 if ((sc->port.pmf == 0) && (val & DRV_STATUS_PMF))
3888 bnx2x_pmf_update(sc);
3890 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
3891 bnx2x_handle_eee_event(sc);
3893 if (sc->link_vars.periodic_flags &
3894 ELINK_PERIODIC_FLAGS_LINK_EVENT) {
3895 /* sync with link */
3896 bnx2x_acquire_phy_lock(sc);
3897 sc->link_vars.periodic_flags &=
3898 ~ELINK_PERIODIC_FLAGS_LINK_EVENT;
3899 bnx2x_release_phy_lock(sc);
3901 bnx2x_link_sync_notify(sc);
3903 bnx2x_link_report(sc);
3907 * Always call it here: bnx2x_link_report() will
3908 * prevent the link indication duplication.
3910 bnx2x_link_status_update(sc);
3912 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3914 PMD_DRV_LOG(ERR, sc, "MC assert!");
3915 bnx2x_mc_assert(sc);
3916 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3917 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3918 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3919 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3920 rte_panic("MC assert!");
3922 } else if (attn & BNX2X_MCP_ASSERT) {
3924 PMD_DRV_LOG(ERR, sc, "MCP assert!");
3925 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3928 PMD_DRV_LOG(ERR, sc,
3929 "Unknown HW assert! (attn 0x%08x)", attn);
3933 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3934 PMD_DRV_LOG(ERR, sc, "LATCHED attention 0x%08x (masked)", attn);
3935 if (attn & BNX2X_GRC_TIMEOUT) {
3936 val = REG_RD(sc, MISC_REG_GRC_TIMEOUT_ATTN);
3937 PMD_DRV_LOG(ERR, sc, "GRC time-out 0x%08x", val);
3939 if (attn & BNX2X_GRC_RSV) {
3940 val = REG_RD(sc, MISC_REG_GRC_RSV_ATTN);
3941 PMD_DRV_LOG(ERR, sc, "GRC reserved 0x%08x", val);
3943 REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3947 static void bnx2x_attn_int_deasserted2(struct bnx2x_softc *sc, uint32_t attn)
3949 int port = SC_PORT(sc);
3951 uint32_t val0, mask0, val1, mask1;
3954 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3955 val = REG_RD(sc, CFC_REG_CFC_INT_STS_CLR);
3956 PMD_DRV_LOG(ERR, sc, "CFC hw attention 0x%08x", val);
3957 /* CFC error attention */
3959 PMD_DRV_LOG(ERR, sc, "FATAL error from CFC");
3963 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3964 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_0);
3965 PMD_DRV_LOG(ERR, sc, "PXP hw attention-0 0x%08x", val);
3966 /* RQ_USDMDP_FIFO_OVERFLOW */
3967 if (val & 0x18000) {
3968 PMD_DRV_LOG(ERR, sc, "FATAL error from PXP");
3971 if (!CHIP_IS_E1x(sc)) {
3972 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_1);
3973 PMD_DRV_LOG(ERR, sc, "PXP hw attention-1 0x%08x", val);
3976 #define PXP2_EOP_ERROR_BIT PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR
3977 #define AEU_PXP2_HW_INT_BIT AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT
3979 if (attn & AEU_PXP2_HW_INT_BIT) {
3980 /* CQ47854 workaround do not panic on
3981 * PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3983 if (!CHIP_IS_E1x(sc)) {
3984 mask0 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_0);
3985 val1 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_1);
3986 mask1 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_1);
3987 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_0);
3989 * If the only PXP2_EOP_ERROR_BIT is set in
3990 * STS0 and STS1 - clear it
3992 * probably we lose additional attentions between
3993 * STS0 and STS_CLR0, in this case user will not
3994 * be notified about them
3996 if (val0 & mask0 & PXP2_EOP_ERROR_BIT &&
3998 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
4000 /* print the register, since no one can restore it */
4001 PMD_DRV_LOG(ERR, sc,
4002 "PXP2_REG_PXP2_INT_STS_CLR_0 0x%08x", val0);
4005 * if PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
4008 if (val0 & PXP2_EOP_ERROR_BIT) {
4009 PMD_DRV_LOG(ERR, sc, "PXP2_WR_PGLUE_EOP_ERROR");
4012 * if only PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR is
4013 * set then clear attention from PXP2 block without panic
4015 if (((val0 & mask0) == PXP2_EOP_ERROR_BIT) &&
4016 ((val1 & mask1) == 0))
4017 attn &= ~AEU_PXP2_HW_INT_BIT;
4022 if (attn & HW_INTERRUT_ASSERT_SET_2) {
4023 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
4024 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
4026 val = REG_RD(sc, reg_offset);
4027 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
4028 REG_WR(sc, reg_offset, val);
4030 PMD_DRV_LOG(ERR, sc,
4031 "FATAL HW block attention set2 0x%x",
4032 (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_2));
4033 rte_panic("HW block attention set2");
4037 static void bnx2x_attn_int_deasserted1(struct bnx2x_softc *sc, uint32_t attn)
4039 int port = SC_PORT(sc);
4043 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
4044 val = REG_RD(sc, DORQ_REG_DORQ_INT_STS_CLR);
4045 PMD_DRV_LOG(ERR, sc, "DB hw attention 0x%08x", val);
4046 /* DORQ discard attention */
4048 PMD_DRV_LOG(ERR, sc, "FATAL error from DORQ");
4052 if (attn & HW_INTERRUT_ASSERT_SET_1) {
4053 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4054 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4056 val = REG_RD(sc, reg_offset);
4057 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4058 REG_WR(sc, reg_offset, val);
4060 PMD_DRV_LOG(ERR, sc,
4061 "FATAL HW block attention set1 0x%08x",
4062 (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_1));
4063 rte_panic("HW block attention set1");
4067 static void bnx2x_attn_int_deasserted0(struct bnx2x_softc *sc, uint32_t attn)
4069 int port = SC_PORT(sc);
4073 reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4074 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
4076 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4077 val = REG_RD(sc, reg_offset);
4078 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4079 REG_WR(sc, reg_offset, val);
4081 PMD_DRV_LOG(WARNING, sc, "SPIO5 hw attention");
4083 /* Fan failure attention */
4084 elink_hw_reset_phy(&sc->link_params);
4085 bnx2x_fan_failure(sc);
4088 if ((attn & sc->link_vars.aeu_int_mask) && sc->port.pmf) {
4089 bnx2x_acquire_phy_lock(sc);
4090 elink_handle_module_detect_int(&sc->link_params);
4091 bnx2x_release_phy_lock(sc);
4094 if (attn & HW_INTERRUT_ASSERT_SET_0) {
4095 val = REG_RD(sc, reg_offset);
4096 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4097 REG_WR(sc, reg_offset, val);
4099 rte_panic("FATAL HW block attention set0 0x%lx",
4100 (attn & (unsigned long)HW_INTERRUT_ASSERT_SET_0));
4104 static void bnx2x_attn_int_deasserted(struct bnx2x_softc *sc, uint32_t deasserted)
4106 struct attn_route attn;
4107 struct attn_route *group_mask;
4108 int port = SC_PORT(sc);
4113 uint8_t global = FALSE;
4116 * Need to take HW lock because MCP or other port might also
4117 * try to handle this event.
4119 bnx2x_acquire_alr(sc);
4121 if (bnx2x_chk_parity_attn(sc, &global, TRUE)) {
4122 sc->recovery_state = BNX2X_RECOVERY_INIT;
4124 /* disable HW interrupts */
4125 bnx2x_int_disable(sc);
4126 bnx2x_release_alr(sc);
4130 attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
4131 attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
4132 attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
4133 attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
4134 if (!CHIP_IS_E1x(sc)) {
4136 REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
4141 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4142 if (deasserted & (1 << index)) {
4143 group_mask = &sc->attn_group[index];
4145 bnx2x_attn_int_deasserted4(sc,
4147 sig[4] & group_mask->sig[4]);
4148 bnx2x_attn_int_deasserted3(sc,
4150 sig[3] & group_mask->sig[3]);
4151 bnx2x_attn_int_deasserted1(sc,
4153 sig[1] & group_mask->sig[1]);
4154 bnx2x_attn_int_deasserted2(sc,
4156 sig[2] & group_mask->sig[2]);
4157 bnx2x_attn_int_deasserted0(sc,
4159 sig[0] & group_mask->sig[0]);
4163 bnx2x_release_alr(sc);
4165 if (sc->devinfo.int_block == INT_BLOCK_HC) {
4166 reg_addr = (HC_REG_COMMAND_REG + port * 32 +
4167 COMMAND_REG_ATTN_BITS_CLR);
4169 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER * 8);
4173 PMD_DRV_LOG(DEBUG, sc,
4174 "about to mask 0x%08x at %s addr 0x%08x", val,
4175 (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
4177 REG_WR(sc, reg_addr, val);
4179 if (~sc->attn_state & deasserted) {
4180 PMD_DRV_LOG(ERR, sc, "IGU error");
4183 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4184 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4186 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4188 aeu_mask = REG_RD(sc, reg_addr);
4190 aeu_mask |= (deasserted & 0x3ff);
4192 REG_WR(sc, reg_addr, aeu_mask);
4193 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4195 sc->attn_state &= ~deasserted;
4198 static void bnx2x_attn_int(struct bnx2x_softc *sc)
4200 /* read local copy of bits */
4201 uint32_t attn_bits = le32toh(sc->def_sb->atten_status_block.attn_bits);
4203 le32toh(sc->def_sb->atten_status_block.attn_bits_ack);
4204 uint32_t attn_state = sc->attn_state;
4206 /* look for changed bits */
4207 uint32_t asserted = attn_bits & ~attn_ack & ~attn_state;
4208 uint32_t deasserted = ~attn_bits & attn_ack & attn_state;
4210 PMD_DRV_LOG(DEBUG, sc,
4211 "attn_bits 0x%08x attn_ack 0x%08x asserted 0x%08x deasserted 0x%08x",
4212 attn_bits, attn_ack, asserted, deasserted);
4214 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) {
4215 PMD_DRV_LOG(ERR, sc, "BAD attention state");
4218 /* handle bits that were raised */
4220 bnx2x_attn_int_asserted(sc, asserted);
4224 bnx2x_attn_int_deasserted(sc, deasserted);
4228 static uint16_t bnx2x_update_dsb_idx(struct bnx2x_softc *sc)
4230 struct host_sp_status_block *def_sb = sc->def_sb;
4236 mb(); /* status block is written to by the chip */
4238 if (sc->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
4239 sc->def_att_idx = def_sb->atten_status_block.attn_bits_index;
4240 rc |= BNX2X_DEF_SB_ATT_IDX;
4243 if (sc->def_idx != def_sb->sp_sb.running_index) {
4244 sc->def_idx = def_sb->sp_sb.running_index;
4245 rc |= BNX2X_DEF_SB_IDX;
4253 static struct ecore_queue_sp_obj *bnx2x_cid_to_q_obj(struct bnx2x_softc *sc,
4256 return &sc->sp_objs[CID_TO_FP(cid, sc)].q_obj;
4259 static void bnx2x_handle_mcast_eqe(struct bnx2x_softc *sc)
4261 struct ecore_mcast_ramrod_params rparam;
4264 memset(&rparam, 0, sizeof(rparam));
4266 rparam.mcast_obj = &sc->mcast_obj;
4268 /* clear pending state for the last command */
4269 sc->mcast_obj.raw.clear_pending(&sc->mcast_obj.raw);
4271 /* if there are pending mcast commands - send them */
4272 if (sc->mcast_obj.check_pending(&sc->mcast_obj)) {
4273 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
4275 PMD_DRV_LOG(INFO, sc,
4276 "Failed to send pending mcast commands (%d)",
4283 bnx2x_handle_classification_eqe(struct bnx2x_softc *sc, union event_ring_elem *elem)
4285 unsigned long ramrod_flags = 0;
4287 uint32_t cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4288 struct ecore_vlan_mac_obj *vlan_mac_obj;
4290 /* always push next commands out, don't wait here */
4291 bnx2x_set_bit(RAMROD_CONT, &ramrod_flags);
4293 switch (le32toh(elem->message.data.eth_event.echo) >> BNX2X_SWCID_SHIFT) {
4294 case ECORE_FILTER_MAC_PENDING:
4295 PMD_DRV_LOG(DEBUG, sc, "Got SETUP_MAC completions");
4296 vlan_mac_obj = &sc->sp_objs[cid].mac_obj;
4299 case ECORE_FILTER_MCAST_PENDING:
4300 PMD_DRV_LOG(DEBUG, sc, "Got SETUP_MCAST completions");
4301 bnx2x_handle_mcast_eqe(sc);
4305 PMD_DRV_LOG(NOTICE, sc, "Unsupported classification command: %d",
4306 elem->message.data.eth_event.echo);
4310 rc = vlan_mac_obj->complete(sc, vlan_mac_obj, elem, &ramrod_flags);
4313 PMD_DRV_LOG(NOTICE, sc,
4314 "Failed to schedule new commands (%d)", rc);
4315 } else if (rc > 0) {
4316 PMD_DRV_LOG(DEBUG, sc, "Scheduled next pending commands...");
4320 static void bnx2x_handle_rx_mode_eqe(struct bnx2x_softc *sc)
4322 bnx2x_clear_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
4324 /* send rx_mode command again if was requested */
4325 if (bnx2x_test_and_clear_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state)) {
4326 bnx2x_set_storm_rx_mode(sc);
4330 static void bnx2x_update_eq_prod(struct bnx2x_softc *sc, uint16_t prod)
4332 storm_memset_eq_prod(sc, prod, SC_FUNC(sc));
4333 wmb(); /* keep prod updates ordered */
4336 static void bnx2x_eq_int(struct bnx2x_softc *sc)
4338 uint16_t hw_cons, sw_cons, sw_prod;
4339 union event_ring_elem *elem;
4344 struct ecore_queue_sp_obj *q_obj;
4345 struct ecore_func_sp_obj *f_obj = &sc->func_obj;
4346 struct ecore_raw_obj *rss_raw = &sc->rss_conf_obj.raw;
4348 hw_cons = le16toh(*sc->eq_cons_sb);
4351 * The hw_cons range is 1-255, 257 - the sw_cons range is 0-254, 256.
4352 * when we get to the next-page we need to adjust so the loop
4353 * condition below will be met. The next element is the size of a
4354 * regular element and hence incrementing by 1
4356 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) {
4361 * This function may never run in parallel with itself for a
4362 * specific sc and no need for a read memory barrier here.
4364 sw_cons = sc->eq_cons;
4365 sw_prod = sc->eq_prod;
4369 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4371 elem = &sc->eq[EQ_DESC(sw_cons)];
4373 /* elem CID originates from FW, actually LE */
4374 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4375 opcode = elem->message.opcode;
4377 /* handle eq element */
4379 case EVENT_RING_OPCODE_STAT_QUERY:
4380 PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "got statistics completion event %d",
4382 /* nothing to do with stats comp */
4385 case EVENT_RING_OPCODE_CFC_DEL:
4386 /* handle according to cid range */
4387 /* we may want to verify here that the sc state is HALTING */
4388 PMD_DRV_LOG(DEBUG, sc, "got delete ramrod for MULTI[%d]",
4390 q_obj = bnx2x_cid_to_q_obj(sc, cid);
4391 if (q_obj->complete_cmd(sc, q_obj, ECORE_Q_CMD_CFC_DEL)) {
4396 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4397 PMD_DRV_LOG(DEBUG, sc, "got STOP TRAFFIC");
4398 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_STOP)) {
4403 case EVENT_RING_OPCODE_START_TRAFFIC:
4404 PMD_DRV_LOG(DEBUG, sc, "got START TRAFFIC");
4405 if (f_obj->complete_cmd
4406 (sc, f_obj, ECORE_F_CMD_TX_START)) {
4411 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
4412 echo = elem->message.data.function_update_event.echo;
4413 if (echo == SWITCH_UPDATE) {
4414 PMD_DRV_LOG(DEBUG, sc,
4415 "got FUNC_SWITCH_UPDATE ramrod");
4416 if (f_obj->complete_cmd(sc, f_obj,
4417 ECORE_F_CMD_SWITCH_UPDATE))
4422 PMD_DRV_LOG(DEBUG, sc,
4423 "AFEX: ramrod completed FUNCTION_UPDATE");
4424 f_obj->complete_cmd(sc, f_obj,
4425 ECORE_F_CMD_AFEX_UPDATE);
4429 case EVENT_RING_OPCODE_FORWARD_SETUP:
4430 q_obj = &bnx2x_fwd_sp_obj(sc, q_obj);
4431 if (q_obj->complete_cmd(sc, q_obj,
4432 ECORE_Q_CMD_SETUP_TX_ONLY)) {
4437 case EVENT_RING_OPCODE_FUNCTION_START:
4438 PMD_DRV_LOG(DEBUG, sc, "got FUNC_START ramrod");
4439 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_START)) {
4444 case EVENT_RING_OPCODE_FUNCTION_STOP:
4445 PMD_DRV_LOG(DEBUG, sc, "got FUNC_STOP ramrod");
4446 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_STOP)) {
4452 switch (opcode | sc->state) {
4453 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPEN):
4454 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPENING_WAITING_PORT):
4456 elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4457 PMD_DRV_LOG(DEBUG, sc, "got RSS_UPDATE ramrod. CID %d",
4459 rss_raw->clear_pending(rss_raw);
4462 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4463 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4464 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_CLOSING_WAITING_HALT):
4465 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_OPEN):
4466 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_DIAG):
4467 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4468 PMD_DRV_LOG(DEBUG, sc,
4469 "got (un)set mac ramrod");
4470 bnx2x_handle_classification_eqe(sc, elem);
4473 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_OPEN):
4474 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_DIAG):
4475 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4476 PMD_DRV_LOG(DEBUG, sc,
4477 "got mcast ramrod");
4478 bnx2x_handle_mcast_eqe(sc);
4481 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_OPEN):
4482 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_DIAG):
4483 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4484 PMD_DRV_LOG(DEBUG, sc,
4485 "got rx_mode ramrod");
4486 bnx2x_handle_rx_mode_eqe(sc);
4490 /* unknown event log error and continue */
4491 PMD_DRV_LOG(INFO, sc, "Unknown EQ event %d, sc->state 0x%x",
4492 elem->message.opcode, sc->state);
4500 atomic_add_acq_long(&sc->eq_spq_left, spqe_cnt);
4502 sc->eq_cons = sw_cons;
4503 sc->eq_prod = sw_prod;
4505 /* make sure that above mem writes were issued towards the memory */
4508 /* update producer */
4509 bnx2x_update_eq_prod(sc, sc->eq_prod);
4512 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc)
4517 PMD_DRV_LOG(DEBUG, sc, "---> SP TASK <---");
4519 /* what work needs to be performed? */
4520 status = bnx2x_update_dsb_idx(sc);
4522 PMD_DRV_LOG(DEBUG, sc, "dsb status 0x%04x", status);
4525 if (status & BNX2X_DEF_SB_ATT_IDX) {
4526 PMD_DRV_LOG(DEBUG, sc, "---> ATTN INTR <---");
4528 status &= ~BNX2X_DEF_SB_ATT_IDX;
4532 /* SP events: STAT_QUERY and others */
4533 if (status & BNX2X_DEF_SB_IDX) {
4534 /* handle EQ completions */
4535 PMD_DRV_LOG(DEBUG, sc, "---> EQ INTR <---");
4537 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
4538 le16toh(sc->def_idx), IGU_INT_NOP, 1);
4539 status &= ~BNX2X_DEF_SB_IDX;
4542 /* if status is non zero then something went wrong */
4543 if (unlikely(status)) {
4544 PMD_DRV_LOG(INFO, sc,
4545 "Got an unknown SP interrupt! (0x%04x)", status);
4548 /* ack status block only if something was actually handled */
4549 bnx2x_ack_sb(sc, sc->igu_dsb_id, ATTENTION_ID,
4550 le16toh(sc->def_att_idx), IGU_INT_ENABLE, 1);
4555 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp)
4557 struct bnx2x_softc *sc = fp->sc;
4558 uint8_t more_rx = FALSE;
4560 /* Make sure FP is initialized */
4561 if (!fp->sb_running_index)
4564 PMD_DEBUG_PERIODIC_LOG(DEBUG, sc,
4565 "---> FP TASK QUEUE (%d) <--", fp->index);
4567 /* update the fastpath index */
4568 bnx2x_update_fp_sb_idx(fp);
4570 if (rte_atomic32_read(&sc->scan_fp) == 1) {
4571 if (bnx2x_has_rx_work(fp)) {
4572 more_rx = bnx2x_rxeof(sc, fp);
4576 /* still more work to do */
4577 bnx2x_handle_fp_tq(fp);
4582 /* Assuming we have completed slow path completion, clear the flag */
4583 rte_atomic32_set(&sc->scan_fp, 0);
4584 bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
4585 le16toh(fp->fp_hc_idx), IGU_INT_ENABLE, 1);
4589 * Legacy interrupt entry point.
4591 * Verifies that the controller generated the interrupt and
4592 * then calls a separate routine to handle the various
4593 * interrupt causes: link, RX, and TX.
4595 int bnx2x_intr_legacy(struct bnx2x_softc *sc)
4597 struct bnx2x_fastpath *fp;
4598 uint32_t status, mask;
4602 * 0 for ustorm, 1 for cstorm
4603 * the bits returned from ack_int() are 0-15
4604 * bit 0 = attention status block
4605 * bit 1 = fast path status block
4606 * a mask of 0x2 or more = tx/rx event
4607 * a mask of 1 = slow path event
4610 status = bnx2x_ack_int(sc);
4612 /* the interrupt is not for us */
4613 if (unlikely(status == 0)) {
4617 PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "Interrupt status 0x%04x", status);
4618 //bnx2x_dump_status_block(sc);
4620 FOR_EACH_ETH_QUEUE(sc, i) {
4622 mask = (0x2 << (fp->index + CNIC_SUPPORT(sc)));
4623 if (status & mask) {
4624 /* acknowledge and disable further fastpath interrupts */
4625 bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
4626 0, IGU_INT_DISABLE, 0);
4627 bnx2x_handle_fp_tq(fp);
4632 if (unlikely(status & 0x1)) {
4633 /* acknowledge and disable further slowpath interrupts */
4634 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
4635 0, IGU_INT_DISABLE, 0);
4636 rc = bnx2x_handle_sp_tq(sc);
4640 if (unlikely(status)) {
4641 PMD_DRV_LOG(WARNING, sc,
4642 "Unexpected fastpath status (0x%08x)!", status);
4648 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc);
4649 static int bnx2x_init_hw_common(struct bnx2x_softc *sc);
4650 static int bnx2x_init_hw_port(struct bnx2x_softc *sc);
4651 static int bnx2x_init_hw_func(struct bnx2x_softc *sc);
4652 static void bnx2x_reset_common(struct bnx2x_softc *sc);
4653 static void bnx2x_reset_port(struct bnx2x_softc *sc);
4654 static void bnx2x_reset_func(struct bnx2x_softc *sc);
4655 static int bnx2x_init_firmware(struct bnx2x_softc *sc);
4656 static void bnx2x_release_firmware(struct bnx2x_softc *sc);
4659 ecore_func_sp_drv_ops bnx2x_func_sp_drv = {
4660 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
4661 .init_hw_cmn = bnx2x_init_hw_common,
4662 .init_hw_port = bnx2x_init_hw_port,
4663 .init_hw_func = bnx2x_init_hw_func,
4665 .reset_hw_cmn = bnx2x_reset_common,
4666 .reset_hw_port = bnx2x_reset_port,
4667 .reset_hw_func = bnx2x_reset_func,
4669 .init_fw = bnx2x_init_firmware,
4670 .release_fw = bnx2x_release_firmware,
4673 static void bnx2x_init_func_obj(struct bnx2x_softc *sc)
4677 PMD_INIT_FUNC_TRACE(sc);
4679 ecore_init_func_obj(sc,
4681 BNX2X_SP(sc, func_rdata),
4682 (rte_iova_t)BNX2X_SP_MAPPING(sc, func_rdata),
4683 BNX2X_SP(sc, func_afex_rdata),
4684 (rte_iova_t)BNX2X_SP_MAPPING(sc, func_afex_rdata),
4685 &bnx2x_func_sp_drv);
4688 static int bnx2x_init_hw(struct bnx2x_softc *sc, uint32_t load_code)
4690 struct ecore_func_state_params func_params = { NULL };
4693 PMD_INIT_FUNC_TRACE(sc);
4695 /* prepare the parameters for function state transitions */
4696 bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
4698 func_params.f_obj = &sc->func_obj;
4699 func_params.cmd = ECORE_F_CMD_HW_INIT;
4701 func_params.params.hw_init.load_phase = load_code;
4704 * Via a plethora of function pointers, we will eventually reach
4705 * bnx2x_init_hw_common(), bnx2x_init_hw_port(), or bnx2x_init_hw_func().
4707 rc = ecore_func_state_change(sc, &func_params);
4713 bnx2x_fill(struct bnx2x_softc *sc, uint32_t addr, int fill, uint32_t len)
4717 if (!(len % 4) && !(addr % 4)) {
4718 for (i = 0; i < len; i += 4) {
4719 REG_WR(sc, (addr + i), fill);
4722 for (i = 0; i < len; i++) {
4723 REG_WR8(sc, (addr + i), fill);
4728 /* writes FP SP data to FW - data_size in dwords */
4730 bnx2x_wr_fp_sb_data(struct bnx2x_softc *sc, int fw_sb_id, uint32_t * sb_data_p,
4735 for (index = 0; index < data_size; index++) {
4737 (BAR_CSTRORM_INTMEM +
4738 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
4739 (sizeof(uint32_t) * index)), *(sb_data_p + index));
4743 static void bnx2x_zero_fp_sb(struct bnx2x_softc *sc, int fw_sb_id)
4745 struct hc_status_block_data_e2 sb_data_e2;
4746 struct hc_status_block_data_e1x sb_data_e1x;
4747 uint32_t *sb_data_p;
4748 uint32_t data_size = 0;
4750 if (!CHIP_IS_E1x(sc)) {
4751 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4752 sb_data_e2.common.state = SB_DISABLED;
4753 sb_data_e2.common.p_func.vf_valid = FALSE;
4754 sb_data_p = (uint32_t *) & sb_data_e2;
4755 data_size = (sizeof(struct hc_status_block_data_e2) /
4758 memset(&sb_data_e1x, 0,
4759 sizeof(struct hc_status_block_data_e1x));
4760 sb_data_e1x.common.state = SB_DISABLED;
4761 sb_data_e1x.common.p_func.vf_valid = FALSE;
4762 sb_data_p = (uint32_t *) & sb_data_e1x;
4763 data_size = (sizeof(struct hc_status_block_data_e1x) /
4767 bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4770 (BAR_CSTRORM_INTMEM + CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id)), 0,
4771 CSTORM_STATUS_BLOCK_SIZE);
4772 bnx2x_fill(sc, (BAR_CSTRORM_INTMEM + CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id)),
4773 0, CSTORM_SYNC_BLOCK_SIZE);
4777 bnx2x_wr_sp_sb_data(struct bnx2x_softc *sc,
4778 struct hc_sp_status_block_data *sp_sb_data)
4783 i < (sizeof(struct hc_sp_status_block_data) / sizeof(uint32_t));
4786 (BAR_CSTRORM_INTMEM +
4787 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(SC_FUNC(sc)) +
4788 (i * sizeof(uint32_t))),
4789 *((uint32_t *) sp_sb_data + i));
4793 static void bnx2x_zero_sp_sb(struct bnx2x_softc *sc)
4795 struct hc_sp_status_block_data sp_sb_data;
4797 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4799 sp_sb_data.state = SB_DISABLED;
4800 sp_sb_data.p_func.vf_valid = FALSE;
4802 bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
4805 (BAR_CSTRORM_INTMEM +
4806 CSTORM_SP_STATUS_BLOCK_OFFSET(SC_FUNC(sc))),
4807 0, CSTORM_SP_STATUS_BLOCK_SIZE);
4809 (BAR_CSTRORM_INTMEM +
4810 CSTORM_SP_SYNC_BLOCK_OFFSET(SC_FUNC(sc))),
4811 0, CSTORM_SP_SYNC_BLOCK_SIZE);
4815 bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, int igu_sb_id,
4818 hc_sm->igu_sb_id = igu_sb_id;
4819 hc_sm->igu_seg_id = igu_seg_id;
4820 hc_sm->timer_value = 0xFF;
4821 hc_sm->time_to_expire = 0xFFFFFFFF;
4824 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
4826 /* zero out state machine indices */
4829 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4832 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4833 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
4834 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
4835 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
4840 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
4841 (SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4844 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
4845 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4846 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
4847 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4848 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
4849 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4850 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
4851 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4855 bnx2x_init_sb(struct bnx2x_softc *sc, rte_iova_t busaddr, int vfid,
4856 uint8_t vf_valid, int fw_sb_id, int igu_sb_id)
4858 struct hc_status_block_data_e2 sb_data_e2;
4859 struct hc_status_block_data_e1x sb_data_e1x;
4860 struct hc_status_block_sm *hc_sm_p;
4861 uint32_t *sb_data_p;
4865 if (CHIP_INT_MODE_IS_BC(sc)) {
4866 igu_seg_id = HC_SEG_ACCESS_NORM;
4868 igu_seg_id = IGU_SEG_ACCESS_NORM;
4871 bnx2x_zero_fp_sb(sc, fw_sb_id);
4873 if (!CHIP_IS_E1x(sc)) {
4874 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4875 sb_data_e2.common.state = SB_ENABLED;
4876 sb_data_e2.common.p_func.pf_id = SC_FUNC(sc);
4877 sb_data_e2.common.p_func.vf_id = vfid;
4878 sb_data_e2.common.p_func.vf_valid = vf_valid;
4879 sb_data_e2.common.p_func.vnic_id = SC_VN(sc);
4880 sb_data_e2.common.same_igu_sb_1b = TRUE;
4881 sb_data_e2.common.host_sb_addr.hi = U64_HI(busaddr);
4882 sb_data_e2.common.host_sb_addr.lo = U64_LO(busaddr);
4883 hc_sm_p = sb_data_e2.common.state_machine;
4884 sb_data_p = (uint32_t *) & sb_data_e2;
4885 data_size = (sizeof(struct hc_status_block_data_e2) /
4887 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
4889 memset(&sb_data_e1x, 0,
4890 sizeof(struct hc_status_block_data_e1x));
4891 sb_data_e1x.common.state = SB_ENABLED;
4892 sb_data_e1x.common.p_func.pf_id = SC_FUNC(sc);
4893 sb_data_e1x.common.p_func.vf_id = 0xff;
4894 sb_data_e1x.common.p_func.vf_valid = FALSE;
4895 sb_data_e1x.common.p_func.vnic_id = SC_VN(sc);
4896 sb_data_e1x.common.same_igu_sb_1b = TRUE;
4897 sb_data_e1x.common.host_sb_addr.hi = U64_HI(busaddr);
4898 sb_data_e1x.common.host_sb_addr.lo = U64_LO(busaddr);
4899 hc_sm_p = sb_data_e1x.common.state_machine;
4900 sb_data_p = (uint32_t *) & sb_data_e1x;
4901 data_size = (sizeof(struct hc_status_block_data_e1x) /
4903 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
4906 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], igu_sb_id, igu_seg_id);
4907 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], igu_sb_id, igu_seg_id);
4909 /* write indices to HW - PCI guarantees endianity of regpairs */
4910 bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4913 static uint8_t bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp)
4915 if (CHIP_IS_E1x(fp->sc)) {
4916 return fp->cl_id + SC_PORT(fp->sc) * ETH_MAX_RX_CLIENTS_E1H;
4923 bnx2x_rx_ustorm_prods_offset(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
4925 uint32_t offset = BAR_USTRORM_INTMEM;
4928 return PXP_VF_ADDR_USDM_QUEUES_START +
4929 (sc->acquire_resp.resc.hw_qid[fp->index] *
4930 sizeof(struct ustorm_queue_zone_data));
4931 } else if (!CHIP_IS_E1x(sc)) {
4932 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
4934 offset += USTORM_RX_PRODS_E1X_OFFSET(SC_PORT(sc), fp->cl_id);
4940 static void bnx2x_init_eth_fp(struct bnx2x_softc *sc, int idx)
4942 struct bnx2x_fastpath *fp = &sc->fp[idx];
4943 uint32_t cids[ECORE_MULTI_TX_COS] = { 0 };
4944 unsigned long q_type = 0;
4950 fp->igu_sb_id = (sc->igu_base_sb + idx + CNIC_SUPPORT(sc));
4951 fp->fw_sb_id = (sc->base_fw_ndsb + idx + CNIC_SUPPORT(sc));
4953 if (CHIP_IS_E1x(sc))
4954 fp->cl_id = SC_L_ID(sc) + idx;
4956 /* want client ID same as IGU SB ID for non-E1 */
4957 fp->cl_id = fp->igu_sb_id;
4958 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
4960 /* setup sb indices */
4961 if (!CHIP_IS_E1x(sc)) {
4962 fp->sb_index_values = fp->status_block.e2_sb->sb.index_values;
4963 fp->sb_running_index = fp->status_block.e2_sb->sb.running_index;
4965 fp->sb_index_values = fp->status_block.e1x_sb->sb.index_values;
4966 fp->sb_running_index =
4967 fp->status_block.e1x_sb->sb.running_index;
4971 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(sc, fp);
4973 fp->rx_cq_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS];
4975 for (cos = 0; cos < sc->max_cos; cos++) {
4978 fp->tx_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0];
4980 /* nothing more for a VF to do */
4985 bnx2x_init_sb(sc, fp->sb_dma.paddr, BNX2X_VF_ID_INVALID, FALSE,
4986 fp->fw_sb_id, fp->igu_sb_id);
4988 bnx2x_update_fp_sb_idx(fp);
4990 /* Configure Queue State object */
4991 bnx2x_set_bit(ECORE_Q_TYPE_HAS_RX, &q_type);
4992 bnx2x_set_bit(ECORE_Q_TYPE_HAS_TX, &q_type);
4994 ecore_init_queue_obj(sc,
4995 &sc->sp_objs[idx].q_obj,
5000 BNX2X_SP(sc, q_rdata),
5001 (rte_iova_t)BNX2X_SP_MAPPING(sc, q_rdata),
5004 /* configure classification DBs */
5005 ecore_init_mac_obj(sc,
5006 &sc->sp_objs[idx].mac_obj,
5010 BNX2X_SP(sc, mac_rdata),
5011 (rte_iova_t)BNX2X_SP_MAPPING(sc, mac_rdata),
5012 ECORE_FILTER_MAC_PENDING, &sc->sp_state,
5013 ECORE_OBJ_TYPE_RX_TX, &sc->macs_pool);
5017 bnx2x_update_rx_prod(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
5018 uint16_t rx_bd_prod, uint16_t rx_cq_prod)
5020 struct ustorm_eth_rx_producers rx_prods;
5023 memset(&rx_prods, 0, sizeof(rx_prods));
5025 /* update producers */
5026 rx_prods.bd_prod = rx_bd_prod;
5027 rx_prods.cqe_prod = rx_cq_prod;
5030 * Make sure that the BD and SGE data is updated before updating the
5031 * producers since FW might read the BD/SGE right after the producer
5033 * This is only applicable for weak-ordered memory model archs such
5034 * as IA-64. The following barrier is also mandatory since FW will
5035 * assumes BDs must have buffers.
5039 for (i = 0; i < (sizeof(rx_prods) / 4); i++) {
5040 REG_WR(sc, (fp->ustorm_rx_prods_offset + (i * 4)),
5041 ((uint32_t *)&rx_prods)[i]);
5044 wmb(); /* keep prod updates ordered */
5047 static void bnx2x_init_rx_rings(struct bnx2x_softc *sc)
5049 struct bnx2x_fastpath *fp;
5051 struct bnx2x_rx_queue *rxq;
5053 for (i = 0; i < sc->num_queues; i++) {
5055 rxq = sc->rx_queues[fp->index];
5057 PMD_RX_LOG(ERR, "RX queue is NULL");
5061 rxq->rx_bd_head = 0;
5062 rxq->rx_bd_tail = rxq->nb_rx_desc;
5063 rxq->rx_cq_head = 0;
5064 rxq->rx_cq_tail = TOTAL_RCQ_ENTRIES(rxq);
5065 *fp->rx_cq_cons_sb = 0;
5068 * Activate the BD ring...
5069 * Warning, this will generate an interrupt (to the TSTORM)
5070 * so this can only be done after the chip is initialized
5072 bnx2x_update_rx_prod(sc, fp, rxq->rx_bd_tail, rxq->rx_cq_tail);
5080 static void bnx2x_init_tx_ring_one(struct bnx2x_fastpath *fp)
5082 struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
5084 fp->tx_db.data.header.header = 1 << DOORBELL_HDR_DB_TYPE_SHIFT;
5085 fp->tx_db.data.zero_fill1 = 0;
5086 fp->tx_db.data.prod = 0;
5089 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
5093 txq->tx_pkt_tail = 0;
5094 txq->tx_pkt_head = 0;
5095 txq->tx_bd_tail = 0;
5096 txq->tx_bd_head = 0;
5099 static void bnx2x_init_tx_rings(struct bnx2x_softc *sc)
5103 for (i = 0; i < sc->num_queues; i++) {
5104 bnx2x_init_tx_ring_one(&sc->fp[i]);
5108 static void bnx2x_init_def_sb(struct bnx2x_softc *sc)
5110 struct host_sp_status_block *def_sb = sc->def_sb;
5111 rte_iova_t mapping = sc->def_sb_dma.paddr;
5112 int igu_sp_sb_index;
5114 int port = SC_PORT(sc);
5115 int func = SC_FUNC(sc);
5116 int reg_offset, reg_offset_en5;
5119 struct hc_sp_status_block_data sp_sb_data;
5121 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5123 if (CHIP_INT_MODE_IS_BC(sc)) {
5124 igu_sp_sb_index = DEF_SB_IGU_ID;
5125 igu_seg_id = HC_SEG_ACCESS_DEF;
5127 igu_sp_sb_index = sc->igu_dsb_id;
5128 igu_seg_id = IGU_SEG_ACCESS_DEF;
5132 section = ((uint64_t) mapping +
5133 offsetof(struct host_sp_status_block, atten_status_block));
5134 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5137 reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5138 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
5140 reg_offset_en5 = (port) ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5141 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0;
5143 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5144 /* take care of sig[0]..sig[4] */
5145 for (sindex = 0; sindex < 4; sindex++) {
5146 sc->attn_group[index].sig[sindex] =
5148 (reg_offset + (sindex * 0x4) +
5152 if (!CHIP_IS_E1x(sc)) {
5154 * enable5 is separate from the rest of the registers,
5155 * and the address skip is 4 and not 16 between the
5158 sc->attn_group[index].sig[4] =
5159 REG_RD(sc, (reg_offset_en5 + (0x4 * index)));
5161 sc->attn_group[index].sig[4] = 0;
5165 if (sc->devinfo.int_block == INT_BLOCK_HC) {
5167 port ? HC_REG_ATTN_MSG1_ADDR_L : HC_REG_ATTN_MSG0_ADDR_L;
5168 REG_WR(sc, reg_offset, U64_LO(section));
5169 REG_WR(sc, (reg_offset + 4), U64_HI(section));
5170 } else if (!CHIP_IS_E1x(sc)) {
5171 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5172 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5175 section = ((uint64_t) mapping +
5176 offsetof(struct host_sp_status_block, sp_sb));
5178 bnx2x_zero_sp_sb(sc);
5180 /* PCI guarantees endianity of regpair */
5181 sp_sb_data.state = SB_ENABLED;
5182 sp_sb_data.host_sb_addr.lo = U64_LO(section);
5183 sp_sb_data.host_sb_addr.hi = U64_HI(section);
5184 sp_sb_data.igu_sb_id = igu_sp_sb_index;
5185 sp_sb_data.igu_seg_id = igu_seg_id;
5186 sp_sb_data.p_func.pf_id = func;
5187 sp_sb_data.p_func.vnic_id = SC_VN(sc);
5188 sp_sb_data.p_func.vf_id = 0xff;
5190 bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
5192 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5195 static void bnx2x_init_sp_ring(struct bnx2x_softc *sc)
5197 atomic_store_rel_long(&sc->cq_spq_left, MAX_SPQ_PENDING);
5198 sc->spq_prod_idx = 0;
5200 &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_ETH_DEF_CONS];
5201 sc->spq_prod_bd = sc->spq;
5202 sc->spq_last_bd = (sc->spq_prod_bd + MAX_SP_DESC_CNT);
5205 static void bnx2x_init_eq_ring(struct bnx2x_softc *sc)
5207 union event_ring_elem *elem;
5210 for (i = 1; i <= NUM_EQ_PAGES; i++) {
5211 elem = &sc->eq[EQ_DESC_CNT_PAGE * i - 1];
5213 elem->next_page.addr.hi = htole32(U64_HI(sc->eq_dma.paddr +
5215 (i % NUM_EQ_PAGES)));
5216 elem->next_page.addr.lo = htole32(U64_LO(sc->eq_dma.paddr +
5218 (i % NUM_EQ_PAGES)));
5222 sc->eq_prod = NUM_EQ_DESC;
5223 sc->eq_cons_sb = &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_EQ_CONS];
5225 atomic_store_rel_long(&sc->eq_spq_left,
5226 (min((MAX_SP_DESC_CNT - MAX_SPQ_PENDING),
5230 static void bnx2x_init_internal_common(struct bnx2x_softc *sc)
5235 * Zero this manually as its initialization is currently missing
5238 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) {
5240 (BAR_USTRORM_INTMEM + USTORM_AGG_DATA_OFFSET + (i * 4)),
5244 if (!CHIP_IS_E1x(sc)) {
5245 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET),
5246 CHIP_INT_MODE_IS_BC(sc) ? HC_IGU_BC_MODE :
5251 static void bnx2x_init_internal(struct bnx2x_softc *sc, uint32_t load_code)
5253 switch (load_code) {
5254 case FW_MSG_CODE_DRV_LOAD_COMMON:
5255 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5256 bnx2x_init_internal_common(sc);
5259 case FW_MSG_CODE_DRV_LOAD_PORT:
5263 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5264 /* internal memory per function is initialized inside bnx2x_pf_init */
5268 PMD_DRV_LOG(NOTICE, sc, "Unknown load_code (0x%x) from MCP",
5275 storm_memset_func_cfg(struct bnx2x_softc *sc,
5276 struct tstorm_eth_function_common_config *tcfg,
5282 addr = (BAR_TSTRORM_INTMEM +
5283 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid));
5284 size = sizeof(struct tstorm_eth_function_common_config);
5285 ecore_storm_memset_struct(sc, addr, size, (uint32_t *) tcfg);
5288 static void bnx2x_func_init(struct bnx2x_softc *sc, struct bnx2x_func_init_params *p)
5290 struct tstorm_eth_function_common_config tcfg = { 0 };
5292 if (CHIP_IS_E1x(sc)) {
5293 storm_memset_func_cfg(sc, &tcfg, p->func_id);
5296 /* Enable the function in the FW */
5297 storm_memset_vf_to_pf(sc, p->func_id, p->pf_id);
5298 storm_memset_func_en(sc, p->func_id, 1);
5301 if (p->func_flgs & FUNC_FLG_SPQ) {
5302 storm_memset_spq_addr(sc, p->spq_map, p->func_id);
5304 (XSEM_REG_FAST_MEMORY +
5305 XSTORM_SPQ_PROD_OFFSET(p->func_id)), p->spq_prod);
5310 * Calculates the sum of vn_min_rates.
5311 * It's needed for further normalizing of the min_rates.
5313 * sum of vn_min_rates.
5315 * 0 - if all the min_rates are 0.
5316 * In the later case fainess algorithm should be deactivated.
5317 * If all min rates are not zero then those that are zeroes will be set to 1.
5319 static void bnx2x_calc_vn_min(struct bnx2x_softc *sc, struct cmng_init_input *input)
5322 uint32_t vn_min_rate;
5326 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5327 vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5328 vn_min_rate = (((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
5329 FUNC_MF_CFG_MIN_BW_SHIFT) * 100);
5331 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5332 /* skip hidden VNs */
5334 } else if (!vn_min_rate) {
5335 /* If min rate is zero - set it to 100 */
5336 vn_min_rate = DEF_MIN_RATE;
5341 input->vnic_min_rate[vn] = vn_min_rate;
5344 /* if ETS or all min rates are zeros - disable fairness */
5346 input->flags.cmng_enables &= ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5348 input->flags.cmng_enables |= CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5353 bnx2x_extract_max_cfg(__rte_unused struct bnx2x_softc *sc, uint32_t mf_cfg)
5355 uint16_t max_cfg = ((mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
5356 FUNC_MF_CFG_MAX_BW_SHIFT);
5359 PMD_DRV_LOG(DEBUG, sc,
5360 "Max BW configured to 0 - using 100 instead");
5368 bnx2x_calc_vn_max(struct bnx2x_softc *sc, int vn, struct cmng_init_input *input)
5370 uint16_t vn_max_rate;
5371 uint32_t vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5374 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5377 max_cfg = bnx2x_extract_max_cfg(sc, vn_cfg);
5380 /* max_cfg in percents of linkspeed */
5382 ((sc->link_vars.line_speed * max_cfg) / 100);
5383 } else { /* SD modes */
5384 /* max_cfg is absolute in 100Mb units */
5385 vn_max_rate = (max_cfg * 100);
5389 input->vnic_max_rate[vn] = vn_max_rate;
5393 bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg, uint8_t cmng_type)
5395 struct cmng_init_input input;
5398 memset(&input, 0, sizeof(struct cmng_init_input));
5400 input.port_rate = sc->link_vars.line_speed;
5402 if (cmng_type == CMNG_FNS_MINMAX) {
5403 /* read mf conf from shmem */
5405 bnx2x_read_mf_cfg(sc);
5408 /* get VN min rate and enable fairness if not 0 */
5409 bnx2x_calc_vn_min(sc, &input);
5411 /* get VN max rate */
5413 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5414 bnx2x_calc_vn_max(sc, vn, &input);
5418 /* always enable rate shaping and fairness */
5419 input.flags.cmng_enables |= CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
5421 ecore_init_cmng(&input, &sc->cmng);
5426 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc)
5428 if (CHIP_REV_IS_SLOW(sc)) {
5429 return CMNG_FNS_NONE;
5433 return CMNG_FNS_MINMAX;
5436 return CMNG_FNS_NONE;
5440 storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng, uint8_t port)
5447 addr = (BAR_XSTRORM_INTMEM + XSTORM_CMNG_PER_PORT_VARS_OFFSET(port));
5448 size = sizeof(struct cmng_struct_per_port);
5449 ecore_storm_memset_struct(sc, addr, size, (uint32_t *) & cmng->port);
5451 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5452 func = func_by_vn(sc, vn);
5454 addr = (BAR_XSTRORM_INTMEM +
5455 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func));
5456 size = sizeof(struct rate_shaping_vars_per_vn);
5457 ecore_storm_memset_struct(sc, addr, size,
5458 (uint32_t *) & cmng->
5459 vnic.vnic_max_rate[vn]);
5461 addr = (BAR_XSTRORM_INTMEM +
5462 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func));
5463 size = sizeof(struct fairness_vars_per_vn);
5464 ecore_storm_memset_struct(sc, addr, size,
5465 (uint32_t *) & cmng->
5466 vnic.vnic_min_rate[vn]);
5470 static void bnx2x_pf_init(struct bnx2x_softc *sc)
5472 struct bnx2x_func_init_params func_init;
5473 struct event_ring_data eq_data;
5476 memset(&eq_data, 0, sizeof(struct event_ring_data));
5477 memset(&func_init, 0, sizeof(struct bnx2x_func_init_params));
5479 if (!CHIP_IS_E1x(sc)) {
5480 /* reset IGU PF statistics: MSIX + ATTN */
5483 (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5484 (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5485 ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5489 (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5490 (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5491 (BNX2X_IGU_STAS_MSG_PF_CNT * 4) +
5492 ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5496 /* function setup flags */
5497 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
5499 func_init.func_flgs = flags;
5500 func_init.pf_id = SC_FUNC(sc);
5501 func_init.func_id = SC_FUNC(sc);
5502 func_init.spq_map = sc->spq_dma.paddr;
5503 func_init.spq_prod = sc->spq_prod_idx;
5505 bnx2x_func_init(sc, &func_init);
5507 memset(&sc->cmng, 0, sizeof(struct cmng_struct_per_port));
5510 * Congestion management values depend on the link rate.
5511 * There is no active link so initial link rate is set to 10Gbps.
5512 * When the link comes up the congestion management values are
5513 * re-calculated according to the actual link rate.
5515 sc->link_vars.line_speed = SPEED_10000;
5516 bnx2x_cmng_fns_init(sc, TRUE, bnx2x_get_cmng_fns_mode(sc));
5518 /* Only the PMF sets the HW */
5520 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
5523 /* init Event Queue - PCI bus guarantees correct endainity */
5524 eq_data.base_addr.hi = U64_HI(sc->eq_dma.paddr);
5525 eq_data.base_addr.lo = U64_LO(sc->eq_dma.paddr);
5526 eq_data.producer = sc->eq_prod;
5527 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
5528 eq_data.sb_id = DEF_SB_ID;
5529 storm_memset_eq_data(sc, &eq_data, SC_FUNC(sc));
5532 static void bnx2x_hc_int_enable(struct bnx2x_softc *sc)
5534 int port = SC_PORT(sc);
5535 uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5536 uint32_t val = REG_RD(sc, addr);
5537 uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5538 || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5539 uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5540 uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5543 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5544 HC_CONFIG_0_REG_INT_LINE_EN_0);
5545 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5546 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5548 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
5551 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
5552 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5553 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5554 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5556 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5557 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5558 HC_CONFIG_0_REG_INT_LINE_EN_0 |
5559 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5561 REG_WR(sc, addr, val);
5563 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
5566 REG_WR(sc, addr, val);
5568 /* ensure that HC_CONFIG is written before leading/trailing edge config */
5571 /* init leading/trailing edge */
5573 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5575 /* enable nig and gpio3 attention */
5582 REG_WR(sc, (HC_REG_TRAILING_EDGE_0 + port * 8), val);
5583 REG_WR(sc, (HC_REG_LEADING_EDGE_0 + port * 8), val);
5585 /* make sure that interrupts are indeed enabled from here on */
5589 static void bnx2x_igu_int_enable(struct bnx2x_softc *sc)
5592 uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5593 || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5594 uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5595 uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5597 val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5600 val &= ~(IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5601 val |= (IGU_PF_CONF_MSI_MSIX_EN | IGU_PF_CONF_ATTN_BIT_EN);
5603 val |= IGU_PF_CONF_SINGLE_ISR_EN;
5606 val &= ~IGU_PF_CONF_INT_LINE_EN;
5607 val |= (IGU_PF_CONF_MSI_MSIX_EN |
5608 IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5610 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
5611 val |= (IGU_PF_CONF_INT_LINE_EN |
5612 IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5615 /* clean previous status - need to configure igu prior to ack */
5616 if ((!msix) || single_msix) {
5617 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5621 val |= IGU_PF_CONF_FUNC_EN;
5623 PMD_DRV_LOG(DEBUG, sc, "write 0x%x to IGU mode %s",
5624 val, ((msix) ? "MSI-X" : ((msi) ? "MSI" : "INTx")));
5626 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5630 /* init leading/trailing edge */
5632 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5634 /* enable nig and gpio3 attention */
5641 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
5642 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
5644 /* make sure that interrupts are indeed enabled from here on */
5648 static void bnx2x_int_enable(struct bnx2x_softc *sc)
5650 if (sc->devinfo.int_block == INT_BLOCK_HC) {
5651 bnx2x_hc_int_enable(sc);
5653 bnx2x_igu_int_enable(sc);
5657 static void bnx2x_hc_int_disable(struct bnx2x_softc *sc)
5659 int port = SC_PORT(sc);
5660 uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5661 uint32_t val = REG_RD(sc, addr);
5663 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5664 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5665 HC_CONFIG_0_REG_INT_LINE_EN_0 | HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5666 /* flush all outstanding writes */
5669 REG_WR(sc, addr, val);
5670 if (REG_RD(sc, addr) != val) {
5671 PMD_DRV_LOG(ERR, sc, "proper val not read from HC IGU!");
5675 static void bnx2x_igu_int_disable(struct bnx2x_softc *sc)
5677 uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5679 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
5680 IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_ATTN_BIT_EN);
5682 PMD_DRV_LOG(DEBUG, sc, "write %x to IGU", val);
5684 /* flush all outstanding writes */
5687 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5688 if (REG_RD(sc, IGU_REG_PF_CONFIGURATION) != val) {
5689 PMD_DRV_LOG(ERR, sc, "proper val not read from IGU!");
5693 static void bnx2x_int_disable(struct bnx2x_softc *sc)
5695 if (sc->devinfo.int_block == INT_BLOCK_HC) {
5696 bnx2x_hc_int_disable(sc);
5698 bnx2x_igu_int_disable(sc);
5702 static void bnx2x_nic_init(struct bnx2x_softc *sc, int load_code)
5706 PMD_INIT_FUNC_TRACE(sc);
5708 for (i = 0; i < sc->num_queues; i++) {
5709 bnx2x_init_eth_fp(sc, i);
5712 rmb(); /* ensure status block indices were read */
5714 bnx2x_init_rx_rings(sc);
5715 bnx2x_init_tx_rings(sc);
5718 bnx2x_memset_stats(sc);
5722 /* initialize MOD_ABS interrupts */
5723 elink_init_mod_abs_int(sc, &sc->link_vars,
5724 sc->devinfo.chip_id,
5725 sc->devinfo.shmem_base,
5726 sc->devinfo.shmem2_base, SC_PORT(sc));
5728 bnx2x_init_def_sb(sc);
5729 bnx2x_update_dsb_idx(sc);
5730 bnx2x_init_sp_ring(sc);
5731 bnx2x_init_eq_ring(sc);
5732 bnx2x_init_internal(sc, load_code);
5734 bnx2x_stats_init(sc);
5736 /* flush all before enabling interrupts */
5739 bnx2x_int_enable(sc);
5741 /* check for SPIO5 */
5742 bnx2x_attn_int_deasserted0(sc,
5744 (MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
5746 AEU_INPUTS_ATTN_BITS_SPIO5);
5749 static void bnx2x_init_objs(struct bnx2x_softc *sc)
5751 /* mcast rules must be added to tx if tx switching is enabled */
5752 ecore_obj_type o_type;
5753 if (sc->flags & BNX2X_TX_SWITCHING)
5754 o_type = ECORE_OBJ_TYPE_RX_TX;
5756 o_type = ECORE_OBJ_TYPE_RX;
5758 /* RX_MODE controlling object */
5759 ecore_init_rx_mode_obj(sc, &sc->rx_mode_obj);
5761 /* multicast configuration controlling object */
5762 ecore_init_mcast_obj(sc,
5768 BNX2X_SP(sc, mcast_rdata),
5769 (rte_iova_t)BNX2X_SP_MAPPING(sc, mcast_rdata),
5770 ECORE_FILTER_MCAST_PENDING,
5771 &sc->sp_state, o_type);
5773 /* Setup CAM credit pools */
5774 ecore_init_mac_credit_pool(sc,
5777 CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5778 VNICS_PER_PATH(sc));
5780 ecore_init_vlan_credit_pool(sc,
5782 SC_ABS_FUNC(sc) >> 1,
5783 CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5784 VNICS_PER_PATH(sc));
5786 /* RSS configuration object */
5787 ecore_init_rss_config_obj(sc, &sc->rss_conf_obj, sc->fp->cl_id,
5788 sc->fp->index, SC_FUNC(sc), SC_FUNC(sc),
5789 BNX2X_SP(sc, rss_rdata),
5790 (rte_iova_t)BNX2X_SP_MAPPING(sc, rss_rdata),
5791 ECORE_FILTER_RSS_CONF_PENDING, &sc->sp_state,
5796 * Initialize the function. This must be called before sending CLIENT_SETUP
5797 * for the first client.
5799 static int bnx2x_func_start(struct bnx2x_softc *sc)
5801 struct ecore_func_state_params func_params = { NULL };
5802 struct ecore_func_start_params *start_params =
5803 &func_params.params.start;
5805 /* Prepare parameters for function state transitions */
5806 bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
5808 func_params.f_obj = &sc->func_obj;
5809 func_params.cmd = ECORE_F_CMD_START;
5811 /* Function parameters */
5812 start_params->mf_mode = sc->devinfo.mf_info.mf_mode;
5813 start_params->sd_vlan_tag = OVLAN(sc);
5815 if (CHIP_IS_E2(sc) || CHIP_IS_E3(sc)) {
5816 start_params->network_cos_mode = STATIC_COS;
5817 } else { /* CHIP_IS_E1X */
5818 start_params->network_cos_mode = FW_WRR;
5821 return ecore_func_state_change(sc, &func_params);
5824 static int bnx2x_set_power_state(struct bnx2x_softc *sc, uint8_t state)
5828 /* If there is no power capability, silently succeed */
5829 if (!(sc->devinfo.pcie_cap_flags & BNX2X_PM_CAPABLE_FLAG)) {
5830 PMD_DRV_LOG(INFO, sc, "No power capability");
5834 pci_read(sc, (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS), &pmcsr,
5840 (sc->devinfo.pcie_pm_cap_reg +
5842 ((pmcsr & ~PCIM_PSTAT_DMASK) | PCIM_PSTAT_PME));
5844 if (pmcsr & PCIM_PSTAT_DMASK) {
5845 /* delay required during transition out of D3hot */
5852 /* don't shut down the power for emulation and FPGA */
5853 if (CHIP_REV_IS_SLOW(sc)) {
5857 pmcsr &= ~PCIM_PSTAT_DMASK;
5858 pmcsr |= PCIM_PSTAT_D3;
5861 pmcsr |= PCIM_PSTAT_PMEENABLE;
5865 (sc->devinfo.pcie_pm_cap_reg +
5866 PCIR_POWER_STATUS), pmcsr);
5869 * No more memory access after this point until device is brought back
5875 PMD_DRV_LOG(NOTICE, sc, "Can't support PCI power state = %d",
5883 /* return true if succeeded to acquire the lock */
5884 static uint8_t bnx2x_trylock_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
5886 uint32_t lock_status;
5887 uint32_t resource_bit = (1 << resource);
5888 int func = SC_FUNC(sc);
5889 uint32_t hw_lock_control_reg;
5891 /* Validating that the resource is within range */
5892 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
5893 PMD_DRV_LOG(INFO, sc,
5894 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)",
5895 resource, HW_LOCK_MAX_RESOURCE_VALUE);
5900 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func * 8);
5902 hw_lock_control_reg =
5903 (MISC_REG_DRIVER_CONTROL_7 + (func - 6) * 8);
5906 /* try to acquire the lock */
5907 REG_WR(sc, hw_lock_control_reg + 4, resource_bit);
5908 lock_status = REG_RD(sc, hw_lock_control_reg);
5909 if (lock_status & resource_bit) {
5913 PMD_DRV_LOG(NOTICE, sc, "Failed to get a resource lock 0x%x", resource);
5919 * Get the recovery leader resource id according to the engine this function
5920 * belongs to. Currently only only 2 engines is supported.
5922 static int bnx2x_get_leader_lock_resource(struct bnx2x_softc *sc)
5925 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
5927 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
5931 /* try to acquire a leader lock for current engine */
5932 static uint8_t bnx2x_trylock_leader_lock(struct bnx2x_softc *sc)
5934 return bnx2x_trylock_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5937 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc)
5939 return bnx2x_release_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5942 /* close gates #2, #3 and #4 */
5943 static void bnx2x_set_234_gates(struct bnx2x_softc *sc, uint8_t close)
5947 /* gates #2 and #4a are closed/opened */
5949 REG_WR(sc, PXP_REG_HST_DISCARD_DOORBELLS, ! !close);
5951 REG_WR(sc, PXP_REG_HST_DISCARD_INTERNAL_WRITES, ! !close);
5954 if (CHIP_IS_E1x(sc)) {
5955 /* prevent interrupts from HC on both ports */
5956 val = REG_RD(sc, HC_REG_CONFIG_1);
5958 REG_WR(sc, HC_REG_CONFIG_1, (val & ~(uint32_t)
5959 HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5961 REG_WR(sc, HC_REG_CONFIG_1,
5962 (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5964 val = REG_RD(sc, HC_REG_CONFIG_0);
5966 REG_WR(sc, HC_REG_CONFIG_0, (val & ~(uint32_t)
5967 HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5969 REG_WR(sc, HC_REG_CONFIG_0,
5970 (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5973 /* Prevent incoming interrupts in IGU */
5974 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
5977 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5979 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5981 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5983 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5989 /* poll for pending writes bit, it should get cleared in no more than 1s */
5990 static int bnx2x_er_poll_igu_vq(struct bnx2x_softc *sc)
5992 uint32_t cnt = 1000;
5993 uint32_t pend_bits = 0;
5996 pend_bits = REG_RD(sc, IGU_REG_PENDING_BITS_STATUS);
5998 if (pend_bits == 0) {
6003 } while (cnt-- > 0);
6006 PMD_DRV_LOG(NOTICE, sc, "Still pending IGU requests bits=0x%08x!",
6014 #define SHARED_MF_CLP_MAGIC 0x80000000 /* 'magic' bit */
6016 static void bnx2x_clp_reset_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
6018 /* Do some magic... */
6019 uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
6020 *magic_val = val & SHARED_MF_CLP_MAGIC;
6021 MFCFG_WR(sc, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
6024 /* restore the value of the 'magic' bit */
6025 static void bnx2x_clp_reset_done(struct bnx2x_softc *sc, uint32_t magic_val)
6027 /* Restore the 'magic' bit value... */
6028 uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
6029 MFCFG_WR(sc, shared_mf_config.clp_mb,
6030 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
6033 /* prepare for MCP reset, takes care of CLP configurations */
6034 static void bnx2x_reset_mcp_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
6037 uint32_t validity_offset;
6039 /* set `magic' bit in order to save MF config */
6040 bnx2x_clp_reset_prep(sc, magic_val);
6042 /* get shmem offset */
6043 shmem = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
6045 offsetof(struct shmem_region, validity_map[SC_PORT(sc)]);
6047 /* Clear validity map flags */
6049 REG_WR(sc, shmem + validity_offset, 0);
6053 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
6054 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
6056 static void bnx2x_mcp_wait_one(struct bnx2x_softc *sc)
6058 /* special handling for emulation and FPGA (10 times longer) */
6059 if (CHIP_REV_IS_SLOW(sc)) {
6060 DELAY((MCP_ONE_TIMEOUT * 10) * 1000);
6062 DELAY((MCP_ONE_TIMEOUT) * 1000);
6066 /* initialize shmem_base and waits for validity signature to appear */
6067 static int bnx2x_init_shmem(struct bnx2x_softc *sc)
6073 sc->devinfo.shmem_base =
6074 sc->link_params.shmem_base =
6075 REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
6077 if (sc->devinfo.shmem_base) {
6078 val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
6079 if (val & SHR_MEM_VALIDITY_MB)
6083 bnx2x_mcp_wait_one(sc);
6085 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
6087 PMD_DRV_LOG(NOTICE, sc, "BAD MCP validity signature");
6092 static int bnx2x_reset_mcp_comp(struct bnx2x_softc *sc, uint32_t magic_val)
6094 int rc = bnx2x_init_shmem(sc);
6096 /* Restore the `magic' bit value */
6097 bnx2x_clp_reset_done(sc, magic_val);
6102 static void bnx2x_pxp_prep(struct bnx2x_softc *sc)
6104 REG_WR(sc, PXP2_REG_RD_START_INIT, 0);
6105 REG_WR(sc, PXP2_REG_RQ_RBC_DONE, 0);
6110 * Reset the whole chip except for:
6112 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by one reset bit)
6114 * - MISC (including AEU)
6118 static void bnx2x_process_kill_chip_reset(struct bnx2x_softc *sc, uint8_t global)
6120 uint32_t not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
6121 uint32_t global_bits2, stay_reset2;
6124 * Bits that have to be set in reset_mask2 if we want to reset 'global'
6125 * (per chip) blocks.
6128 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
6129 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
6132 * Don't reset the following blocks.
6133 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
6134 * reset, as in 4 port device they might still be owned
6135 * by the MCP (there is only one leader per path).
6138 MISC_REGISTERS_RESET_REG_1_RST_HC |
6139 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
6140 MISC_REGISTERS_RESET_REG_1_RST_PXP;
6143 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
6144 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
6145 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
6146 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
6147 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
6148 MISC_REGISTERS_RESET_REG_2_RST_GRC |
6149 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
6150 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
6151 MISC_REGISTERS_RESET_REG_2_RST_ATC |
6152 MISC_REGISTERS_RESET_REG_2_PGLC |
6153 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
6154 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
6155 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
6156 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
6157 MISC_REGISTERS_RESET_REG_2_UMAC0 | MISC_REGISTERS_RESET_REG_2_UMAC1;
6160 * Keep the following blocks in reset:
6161 * - all xxMACs are handled by the elink code.
6164 MISC_REGISTERS_RESET_REG_2_XMAC |
6165 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
6167 /* Full reset masks according to the chip */
6168 reset_mask1 = 0xffffffff;
6170 if (CHIP_IS_E1H(sc))
6171 reset_mask2 = 0x1ffff;
6172 else if (CHIP_IS_E2(sc))
6173 reset_mask2 = 0xfffff;
6174 else /* CHIP_IS_E3 */
6175 reset_mask2 = 0x3ffffff;
6177 /* Don't reset global blocks unless we need to */
6179 reset_mask2 &= ~global_bits2;
6182 * In case of attention in the QM, we need to reset PXP
6183 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
6184 * because otherwise QM reset would release 'close the gates' shortly
6185 * before resetting the PXP, then the PSWRQ would send a write
6186 * request to PGLUE. Then when PXP is reset, PGLUE would try to
6187 * read the payload data from PSWWR, but PSWWR would not
6188 * respond. The write queue in PGLUE would stuck, dmae commands
6189 * would not return. Therefore it's important to reset the second
6190 * reset register (containing the
6191 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
6192 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
6195 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
6196 reset_mask2 & (~not_reset_mask2));
6198 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6199 reset_mask1 & (~not_reset_mask1));
6204 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
6205 reset_mask2 & (~stay_reset2));
6210 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
6214 static int bnx2x_process_kill(struct bnx2x_softc *sc, uint8_t global)
6218 uint32_t sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
6219 uint32_t tags_63_32 = 0;
6221 /* Empty the Tetris buffer, wait for 1s */
6223 sr_cnt = REG_RD(sc, PXP2_REG_RD_SR_CNT);
6224 blk_cnt = REG_RD(sc, PXP2_REG_RD_BLK_CNT);
6225 port_is_idle_0 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_0);
6226 port_is_idle_1 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_1);
6227 pgl_exp_rom2 = REG_RD(sc, PXP2_REG_PGL_EXP_ROM2);
6228 if (CHIP_IS_E3(sc)) {
6229 tags_63_32 = REG_RD(sc, PGLUE_B_REG_TAGS_63_32);
6232 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
6233 ((port_is_idle_0 & 0x1) == 0x1) &&
6234 ((port_is_idle_1 & 0x1) == 0x1) &&
6235 (pgl_exp_rom2 == 0xffffffff) &&
6236 (!CHIP_IS_E3(sc) || (tags_63_32 == 0xffffffff)))
6239 } while (cnt-- > 0);
6242 PMD_DRV_LOG(NOTICE, sc,
6243 "ERROR: Tetris buffer didn't get empty or there "
6244 "are still outstanding read requests after 1s! "
6245 "sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, "
6246 "port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x",
6247 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
6254 /* Close gates #2, #3 and #4 */
6255 bnx2x_set_234_gates(sc, TRUE);
6257 /* Poll for IGU VQs for 57712 and newer chips */
6258 if (!CHIP_IS_E1x(sc) && bnx2x_er_poll_igu_vq(sc)) {
6262 /* clear "unprepared" bit */
6263 REG_WR(sc, MISC_REG_UNPREPARED, 0);
6266 /* Make sure all is written to the chip before the reset */
6270 * Wait for 1ms to empty GLUE and PCI-E core queues,
6271 * PSWHST, GRC and PSWRD Tetris buffer.
6275 /* Prepare to chip reset: */
6278 bnx2x_reset_mcp_prep(sc, &val);
6285 /* reset the chip */
6286 bnx2x_process_kill_chip_reset(sc, global);
6289 /* Recover after reset: */
6291 if (global && bnx2x_reset_mcp_comp(sc, val)) {
6295 /* Open the gates #2, #3 and #4 */
6296 bnx2x_set_234_gates(sc, FALSE);
6301 static int bnx2x_leader_reset(struct bnx2x_softc *sc)
6304 uint8_t global = bnx2x_reset_is_global(sc);
6308 * If not going to reset MCP, load "fake" driver to reset HW while
6309 * driver is owner of the HW.
6311 if (!global && !BNX2X_NOMCP(sc)) {
6312 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
6313 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
6315 PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
6317 goto exit_leader_reset;
6320 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
6321 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
6322 PMD_DRV_LOG(NOTICE, sc,
6323 "MCP unexpected response, aborting");
6325 goto exit_leader_reset2;
6328 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
6330 PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
6332 goto exit_leader_reset2;
6336 /* try to recover after the failure */
6337 if (bnx2x_process_kill(sc, global)) {
6338 PMD_DRV_LOG(NOTICE, sc, "Something bad occurred on engine %d!",
6341 goto exit_leader_reset2;
6345 * Clear the RESET_IN_PROGRESS and RESET_GLOBAL bits and update the driver
6348 bnx2x_set_reset_done(sc);
6350 bnx2x_clear_reset_global(sc);
6355 /* unload "fake driver" if it was loaded */
6356 if (!global &&!BNX2X_NOMCP(sc)) {
6357 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
6358 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
6364 bnx2x_release_leader_lock(sc);
6371 * prepare INIT transition, parameters configured:
6372 * - HC configuration
6373 * - Queue's CDU context
6376 bnx2x_pf_q_prep_init(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6377 struct ecore_queue_init_params *init_params)
6380 int cxt_index, cxt_offset;
6382 bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->rx.flags);
6383 bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->tx.flags);
6385 bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->rx.flags);
6386 bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->tx.flags);
6389 init_params->rx.hc_rate =
6390 sc->hc_rx_ticks ? (1000000 / sc->hc_rx_ticks) : 0;
6391 init_params->tx.hc_rate =
6392 sc->hc_tx_ticks ? (1000000 / sc->hc_tx_ticks) : 0;
6395 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = fp->fw_sb_id;
6397 /* CQ index among the SB indices */
6398 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6399 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
6401 /* set maximum number of COSs supported by this queue */
6402 init_params->max_cos = sc->max_cos;
6404 /* set the context pointers queue object */
6405 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
6406 cxt_index = fp->index / ILT_PAGE_CIDS;
6407 cxt_offset = fp->index - (cxt_index * ILT_PAGE_CIDS);
6408 init_params->cxts[cos] =
6409 &sc->context[cxt_index].vcxt[cxt_offset].eth;
6413 /* set flags that are common for the Tx-only and not normal connections */
6414 static unsigned long
6415 bnx2x_get_common_flags(struct bnx2x_softc *sc, uint8_t zero_stats)
6417 unsigned long flags = 0;
6419 /* PF driver will always initialize the Queue to an ACTIVE state */
6420 bnx2x_set_bit(ECORE_Q_FLG_ACTIVE, &flags);
6423 * tx only connections collect statistics (on the same index as the
6424 * parent connection). The statistics are zeroed when the parent
6425 * connection is initialized.
6428 bnx2x_set_bit(ECORE_Q_FLG_STATS, &flags);
6430 bnx2x_set_bit(ECORE_Q_FLG_ZERO_STATS, &flags);
6434 * tx only connections can support tx-switching, though their
6435 * CoS-ness doesn't survive the loopback
6437 if (sc->flags & BNX2X_TX_SWITCHING) {
6438 bnx2x_set_bit(ECORE_Q_FLG_TX_SWITCH, &flags);
6441 bnx2x_set_bit(ECORE_Q_FLG_PCSUM_ON_PKT, &flags);
6446 static unsigned long bnx2x_get_q_flags(struct bnx2x_softc *sc, uint8_t leading)
6448 unsigned long flags = 0;
6451 bnx2x_set_bit(ECORE_Q_FLG_OV, &flags);
6455 bnx2x_set_bit(ECORE_Q_FLG_LEADING_RSS, &flags);
6456 bnx2x_set_bit(ECORE_Q_FLG_MCAST, &flags);
6459 bnx2x_set_bit(ECORE_Q_FLG_VLAN, &flags);
6461 /* merge with common flags */
6462 return flags | bnx2x_get_common_flags(sc, TRUE);
6466 bnx2x_pf_q_prep_general(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6467 struct ecore_general_setup_params *gen_init, uint8_t cos)
6469 gen_init->stat_id = bnx2x_stats_id(fp);
6470 gen_init->spcl_id = fp->cl_id;
6471 gen_init->mtu = sc->mtu;
6472 gen_init->cos = cos;
6476 bnx2x_pf_rx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6477 struct rxq_pause_params *pause,
6478 struct ecore_rxq_setup_params *rxq_init)
6480 struct bnx2x_rx_queue *rxq;
6482 rxq = sc->rx_queues[fp->index];
6484 PMD_RX_LOG(ERR, "RX queue is NULL");
6488 pause->bd_th_lo = BD_TH_LO(sc);
6489 pause->bd_th_hi = BD_TH_HI(sc);
6491 pause->rcq_th_lo = RCQ_TH_LO(sc);
6492 pause->rcq_th_hi = RCQ_TH_HI(sc);
6494 /* validate rings have enough entries to cross high thresholds */
6495 if (sc->dropless_fc &&
6496 pause->bd_th_hi + FW_PREFETCH_CNT > sc->rx_ring_size) {
6497 PMD_DRV_LOG(WARNING, sc, "rx bd ring threshold limit");
6500 if (sc->dropless_fc &&
6501 pause->rcq_th_hi + FW_PREFETCH_CNT > USABLE_RCQ_ENTRIES(rxq)) {
6502 PMD_DRV_LOG(WARNING, sc, "rcq ring threshold limit");
6508 rxq_init->dscr_map = (rte_iova_t)rxq->rx_ring_phys_addr;
6509 rxq_init->rcq_map = (rte_iova_t)rxq->cq_ring_phys_addr;
6510 rxq_init->rcq_np_map = (rte_iova_t)(rxq->cq_ring_phys_addr +
6514 * This should be a maximum number of data bytes that may be
6515 * placed on the BD (not including paddings).
6517 rxq_init->buf_sz = (fp->rx_buf_size - IP_HEADER_ALIGNMENT_PADDING);
6519 rxq_init->cl_qzone_id = fp->cl_qzone_id;
6520 rxq_init->rss_engine_id = SC_FUNC(sc);
6521 rxq_init->mcast_engine_id = SC_FUNC(sc);
6523 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
6524 rxq_init->fw_sb_id = fp->fw_sb_id;
6526 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6529 * configure silent vlan removal
6530 * if multi function mode is afex, then mask default vlan
6532 if (IS_MF_AFEX(sc)) {
6533 rxq_init->silent_removal_value =
6534 sc->devinfo.mf_info.afex_def_vlan_tag;
6535 rxq_init->silent_removal_mask = EVL_VLID_MASK;
6540 bnx2x_pf_tx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6541 struct ecore_txq_setup_params *txq_init, uint8_t cos)
6543 struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
6546 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
6549 txq_init->dscr_map = (rte_iova_t)txq->tx_ring_phys_addr;
6550 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
6551 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
6552 txq_init->fw_sb_id = fp->fw_sb_id;
6555 * set the TSS leading client id for TX classfication to the
6556 * leading RSS client id
6558 txq_init->tss_leading_cl_id = BNX2X_FP(sc, 0, cl_id);
6562 * This function performs 2 steps in a queue state machine:
6567 bnx2x_setup_queue(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp, uint8_t leading)
6569 struct ecore_queue_state_params q_params = { NULL };
6570 struct ecore_queue_setup_params *setup_params = &q_params.params.setup;
6573 PMD_DRV_LOG(DEBUG, sc, "setting up queue %d", fp->index);
6575 bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6577 q_params.q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
6579 /* we want to wait for completion in this context */
6580 bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
6582 /* prepare the INIT parameters */
6583 bnx2x_pf_q_prep_init(sc, fp, &q_params.params.init);
6585 /* Set the command */
6586 q_params.cmd = ECORE_Q_CMD_INIT;
6588 /* Change the state to INIT */
6589 rc = ecore_queue_state_change(sc, &q_params);
6591 PMD_DRV_LOG(NOTICE, sc, "Queue(%d) INIT failed", fp->index);
6595 PMD_DRV_LOG(DEBUG, sc, "init complete");
6597 /* now move the Queue to the SETUP state */
6598 memset(setup_params, 0, sizeof(*setup_params));
6600 /* set Queue flags */
6601 setup_params->flags = bnx2x_get_q_flags(sc, leading);
6603 /* set general SETUP parameters */
6604 bnx2x_pf_q_prep_general(sc, fp, &setup_params->gen_params,
6605 FIRST_TX_COS_INDEX);
6607 bnx2x_pf_rx_q_prep(sc, fp,
6608 &setup_params->pause_params,
6609 &setup_params->rxq_params);
6611 bnx2x_pf_tx_q_prep(sc, fp, &setup_params->txq_params, FIRST_TX_COS_INDEX);
6613 /* Set the command */
6614 q_params.cmd = ECORE_Q_CMD_SETUP;
6616 /* change the state to SETUP */
6617 rc = ecore_queue_state_change(sc, &q_params);
6619 PMD_DRV_LOG(NOTICE, sc, "Queue(%d) SETUP failed", fp->index);
6626 static int bnx2x_setup_leading(struct bnx2x_softc *sc)
6629 return bnx2x_setup_queue(sc, &sc->fp[0], TRUE);
6631 return bnx2x_vf_setup_queue(sc, &sc->fp[0], TRUE);
6635 bnx2x_config_rss_pf(struct bnx2x_softc *sc, struct ecore_rss_config_obj *rss_obj,
6636 uint8_t config_hash)
6638 struct ecore_config_rss_params params = { NULL };
6642 * Although RSS is meaningless when there is a single HW queue we
6643 * still need it enabled in order to have HW Rx hash generated.
6646 params.rss_obj = rss_obj;
6648 bnx2x_set_bit(RAMROD_COMP_WAIT, ¶ms.ramrod_flags);
6650 bnx2x_set_bit(ECORE_RSS_MODE_REGULAR, ¶ms.rss_flags);
6652 /* RSS configuration */
6653 bnx2x_set_bit(ECORE_RSS_IPV4, ¶ms.rss_flags);
6654 bnx2x_set_bit(ECORE_RSS_IPV4_TCP, ¶ms.rss_flags);
6655 bnx2x_set_bit(ECORE_RSS_IPV6, ¶ms.rss_flags);
6656 bnx2x_set_bit(ECORE_RSS_IPV6_TCP, ¶ms.rss_flags);
6657 if (rss_obj->udp_rss_v4) {
6658 bnx2x_set_bit(ECORE_RSS_IPV4_UDP, ¶ms.rss_flags);
6660 if (rss_obj->udp_rss_v6) {
6661 bnx2x_set_bit(ECORE_RSS_IPV6_UDP, ¶ms.rss_flags);
6665 params.rss_result_mask = MULTI_MASK;
6667 rte_memcpy(params.ind_table, rss_obj->ind_table,
6668 sizeof(params.ind_table));
6672 for (i = 0; i < sizeof(params.rss_key) / 4; i++) {
6673 params.rss_key[i] = (uint32_t) rte_rand();
6676 bnx2x_set_bit(ECORE_RSS_SET_SRCH, ¶ms.rss_flags);
6680 return ecore_config_rss(sc, ¶ms);
6682 return bnx2x_vf_config_rss(sc, ¶ms);
6685 static int bnx2x_config_rss_eth(struct bnx2x_softc *sc, uint8_t config_hash)
6687 return bnx2x_config_rss_pf(sc, &sc->rss_conf_obj, config_hash);
6690 static int bnx2x_init_rss_pf(struct bnx2x_softc *sc)
6692 uint8_t num_eth_queues = BNX2X_NUM_ETH_QUEUES(sc);
6696 * Prepare the initial contents of the indirection table if
6699 for (i = 0; i < sizeof(sc->rss_conf_obj.ind_table); i++) {
6700 sc->rss_conf_obj.ind_table[i] =
6701 (sc->fp->cl_id + (i % num_eth_queues));
6705 sc->rss_conf_obj.udp_rss_v4 = sc->rss_conf_obj.udp_rss_v6 = 1;
6709 * For 57711 SEARCHER configuration (rss_keys) is
6710 * per-port, so if explicit configuration is needed, do it only
6713 * For 57712 and newer it's a per-function configuration.
6715 return bnx2x_config_rss_eth(sc, sc->port.pmf || !CHIP_IS_E1x(sc));
6719 bnx2x_set_mac_one(struct bnx2x_softc *sc, uint8_t * mac,
6720 struct ecore_vlan_mac_obj *obj, uint8_t set, int mac_type,
6721 unsigned long *ramrod_flags)
6723 struct ecore_vlan_mac_ramrod_params ramrod_param;
6726 memset(&ramrod_param, 0, sizeof(ramrod_param));
6728 /* fill in general parameters */
6729 ramrod_param.vlan_mac_obj = obj;
6730 ramrod_param.ramrod_flags = *ramrod_flags;
6732 /* fill a user request section if needed */
6733 if (!bnx2x_test_bit(RAMROD_CONT, ramrod_flags)) {
6734 rte_memcpy(ramrod_param.user_req.u.mac.mac, mac,
6737 bnx2x_set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
6739 /* Set the command: ADD or DEL */
6740 ramrod_param.user_req.cmd = (set) ? ECORE_VLAN_MAC_ADD :
6744 rc = ecore_config_vlan_mac(sc, &ramrod_param);
6746 if (rc == ECORE_EXISTS) {
6747 PMD_DRV_LOG(INFO, sc, "Failed to schedule ADD operations (EEXIST)");
6748 /* do not treat adding same MAC as error */
6750 } else if (rc < 0) {
6751 PMD_DRV_LOG(ERR, sc,
6752 "%s MAC failed (%d)", (set ? "Set" : "Delete"), rc);
6758 static int bnx2x_set_eth_mac(struct bnx2x_softc *sc, uint8_t set)
6760 unsigned long ramrod_flags = 0;
6762 PMD_DRV_LOG(DEBUG, sc, "Adding Ethernet MAC");
6764 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
6766 /* Eth MAC is set on RSS leading client (fp[0]) */
6767 return bnx2x_set_mac_one(sc, sc->link_params.mac_addr,
6768 &sc->sp_objs->mac_obj,
6769 set, ECORE_ETH_MAC, &ramrod_flags);
6772 static int bnx2x_get_cur_phy_idx(struct bnx2x_softc *sc)
6774 uint32_t sel_phy_idx = 0;
6776 if (sc->link_params.num_phys <= 1) {
6777 return ELINK_INT_PHY;
6780 if (sc->link_vars.link_up) {
6781 sel_phy_idx = ELINK_EXT_PHY1;
6782 /* In case link is SERDES, check if the ELINK_EXT_PHY2 is the one */
6783 if ((sc->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
6784 (sc->link_params.phy[ELINK_EXT_PHY2].supported &
6785 ELINK_SUPPORTED_FIBRE))
6786 sel_phy_idx = ELINK_EXT_PHY2;
6788 switch (elink_phy_selection(&sc->link_params)) {
6789 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6790 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
6791 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6792 sel_phy_idx = ELINK_EXT_PHY1;
6794 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
6795 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6796 sel_phy_idx = ELINK_EXT_PHY2;
6804 static int bnx2x_get_link_cfg_idx(struct bnx2x_softc *sc)
6806 uint32_t sel_phy_idx = bnx2x_get_cur_phy_idx(sc);
6809 * The selected activated PHY is always after swapping (in case PHY
6810 * swapping is enabled). So when swapping is enabled, we need to reverse
6814 if (sc->link_params.multi_phy_config & PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
6815 if (sel_phy_idx == ELINK_EXT_PHY1)
6816 sel_phy_idx = ELINK_EXT_PHY2;
6817 else if (sel_phy_idx == ELINK_EXT_PHY2)
6818 sel_phy_idx = ELINK_EXT_PHY1;
6821 return ELINK_LINK_CONFIG_IDX(sel_phy_idx);
6824 static void bnx2x_set_requested_fc(struct bnx2x_softc *sc)
6827 * Initialize link parameters structure variables
6828 * It is recommended to turn off RX FC for jumbo frames
6829 * for better performance
6831 if (CHIP_IS_E1x(sc) && (sc->mtu > 5000)) {
6832 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_TX;
6834 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_BOTH;
6838 static void bnx2x_calc_fc_adv(struct bnx2x_softc *sc)
6840 uint8_t cfg_idx = bnx2x_get_link_cfg_idx(sc);
6841 switch (sc->link_vars.ieee_fc &
6842 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
6843 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
6845 sc->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
6849 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
6850 sc->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
6854 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
6855 sc->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
6860 static uint16_t bnx2x_get_mf_speed(struct bnx2x_softc *sc)
6862 uint16_t line_speed = sc->link_vars.line_speed;
6864 uint16_t maxCfg = bnx2x_extract_max_cfg(sc,
6866 mf_info.mf_config[SC_VN
6869 /* calculate the current MAX line speed limit for the MF devices */
6871 line_speed = (line_speed * maxCfg) / 100;
6872 } else { /* SD mode */
6873 uint16_t vn_max_rate = maxCfg * 100;
6875 if (vn_max_rate < line_speed) {
6876 line_speed = vn_max_rate;
6885 bnx2x_fill_report_data(struct bnx2x_softc *sc, struct bnx2x_link_report_data *data)
6887 uint16_t line_speed = bnx2x_get_mf_speed(sc);
6889 memset(data, 0, sizeof(*data));
6891 /* fill the report data with the effective line speed */
6892 data->line_speed = line_speed;
6895 if (!sc->link_vars.link_up || (sc->flags & BNX2X_MF_FUNC_DIS)) {
6896 bnx2x_set_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6897 &data->link_report_flags);
6901 if (sc->link_vars.duplex == DUPLEX_FULL) {
6902 bnx2x_set_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6903 &data->link_report_flags);
6906 /* Rx Flow Control is ON */
6907 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_RX) {
6908 bnx2x_set_bit(BNX2X_LINK_REPORT_RX_FC_ON, &data->link_report_flags);
6911 /* Tx Flow Control is ON */
6912 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
6913 bnx2x_set_bit(BNX2X_LINK_REPORT_TX_FC_ON, &data->link_report_flags);
6917 /* report link status to OS, should be called under phy_lock */
6918 static void bnx2x_link_report_locked(struct bnx2x_softc *sc)
6920 struct bnx2x_link_report_data cur_data;
6924 bnx2x_read_mf_cfg(sc);
6927 /* Read the current link report info */
6928 bnx2x_fill_report_data(sc, &cur_data);
6930 /* Don't report link down or exactly the same link status twice */
6931 if (!memcmp(&cur_data, &sc->last_reported_link, sizeof(cur_data)) ||
6932 (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6933 &sc->last_reported_link.link_report_flags) &&
6934 bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6935 &cur_data.link_report_flags))) {
6939 ELINK_DEBUG_P2(sc, "Change in link status : cur_data = %lx, last_reported_link = %lx",
6940 cur_data.link_report_flags,
6941 sc->last_reported_link.link_report_flags);
6945 ELINK_DEBUG_P1(sc, "link status change count = %x", sc->link_cnt);
6946 /* report new link params and remember the state for the next time */
6947 rte_memcpy(&sc->last_reported_link, &cur_data, sizeof(cur_data));
6949 if (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6950 &cur_data.link_report_flags)) {
6951 ELINK_DEBUG_P0(sc, "NIC Link is Down");
6953 __rte_unused const char *duplex;
6954 __rte_unused const char *flow;
6956 if (bnx2x_test_and_clear_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6957 &cur_data.link_report_flags)) {
6959 ELINK_DEBUG_P0(sc, "link set to full duplex");
6962 ELINK_DEBUG_P0(sc, "link set to half duplex");
6966 * Handle the FC at the end so that only these flags would be
6967 * possibly set. This way we may easily check if there is no FC
6970 if (cur_data.link_report_flags) {
6971 if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6972 &cur_data.link_report_flags) &&
6973 bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6974 &cur_data.link_report_flags)) {
6975 flow = "ON - receive & transmit";
6976 } else if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6977 &cur_data.link_report_flags) &&
6978 !bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6979 &cur_data.link_report_flags)) {
6980 flow = "ON - receive";
6981 } else if (!bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6982 &cur_data.link_report_flags) &&
6983 bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6984 &cur_data.link_report_flags)) {
6985 flow = "ON - transmit";
6987 flow = "none"; /* possible? */
6993 PMD_DRV_LOG(INFO, sc,
6994 "NIC Link is Up, %d Mbps %s duplex, Flow control: %s",
6995 cur_data.line_speed, duplex, flow);
7000 bnx2x_link_report(struct bnx2x_softc *sc)
7002 bnx2x_acquire_phy_lock(sc);
7003 bnx2x_link_report_locked(sc);
7004 bnx2x_release_phy_lock(sc);
7007 void bnx2x_link_status_update(struct bnx2x_softc *sc)
7009 if (sc->state != BNX2X_STATE_OPEN) {
7013 if (IS_PF(sc) && !CHIP_REV_IS_SLOW(sc)) {
7014 elink_link_status_update(&sc->link_params, &sc->link_vars);
7016 sc->port.supported[0] |= (ELINK_SUPPORTED_10baseT_Half |
7017 ELINK_SUPPORTED_10baseT_Full |
7018 ELINK_SUPPORTED_100baseT_Half |
7019 ELINK_SUPPORTED_100baseT_Full |
7020 ELINK_SUPPORTED_1000baseT_Full |
7021 ELINK_SUPPORTED_2500baseX_Full |
7022 ELINK_SUPPORTED_10000baseT_Full |
7023 ELINK_SUPPORTED_TP |
7024 ELINK_SUPPORTED_FIBRE |
7025 ELINK_SUPPORTED_Autoneg |
7026 ELINK_SUPPORTED_Pause |
7027 ELINK_SUPPORTED_Asym_Pause);
7028 sc->port.advertising[0] = sc->port.supported[0];
7030 sc->link_params.sc = sc;
7031 sc->link_params.port = SC_PORT(sc);
7032 sc->link_params.req_duplex[0] = DUPLEX_FULL;
7033 sc->link_params.req_flow_ctrl[0] = ELINK_FLOW_CTRL_NONE;
7034 sc->link_params.req_line_speed[0] = SPEED_10000;
7035 sc->link_params.speed_cap_mask[0] = 0x7f0000;
7036 sc->link_params.switch_cfg = ELINK_SWITCH_CFG_10G;
7038 if (CHIP_REV_IS_FPGA(sc)) {
7039 sc->link_vars.mac_type = ELINK_MAC_TYPE_EMAC;
7040 sc->link_vars.line_speed = ELINK_SPEED_1000;
7041 sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
7042 LINK_STATUS_SPEED_AND_DUPLEX_1000TFD);
7044 sc->link_vars.mac_type = ELINK_MAC_TYPE_BMAC;
7045 sc->link_vars.line_speed = ELINK_SPEED_10000;
7046 sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
7047 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
7050 sc->link_vars.link_up = 1;
7052 sc->link_vars.duplex = DUPLEX_FULL;
7053 sc->link_vars.flow_ctrl = ELINK_FLOW_CTRL_NONE;
7057 NIG_REG_EGRESS_DRAIN0_MODE +
7058 sc->link_params.port * 4, 0);
7059 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7060 bnx2x_link_report(sc);
7065 if (sc->link_vars.link_up) {
7066 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7068 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
7070 bnx2x_link_report(sc);
7072 bnx2x_link_report_locked(sc);
7073 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7077 static int bnx2x_initial_phy_init(struct bnx2x_softc *sc, int load_mode)
7079 int rc, cfg_idx = bnx2x_get_link_cfg_idx(sc);
7080 uint16_t req_line_speed = sc->link_params.req_line_speed[cfg_idx];
7081 struct elink_params *lp = &sc->link_params;
7083 bnx2x_set_requested_fc(sc);
7085 bnx2x_acquire_phy_lock(sc);
7087 if (load_mode == LOAD_DIAG) {
7088 lp->loopback_mode = ELINK_LOOPBACK_XGXS;
7089 /* Prefer doing PHY loopback at 10G speed, if possible */
7090 if (lp->req_line_speed[cfg_idx] < ELINK_SPEED_10000) {
7091 if (lp->speed_cap_mask[cfg_idx] &
7092 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
7093 lp->req_line_speed[cfg_idx] = ELINK_SPEED_10000;
7095 lp->req_line_speed[cfg_idx] = ELINK_SPEED_1000;
7100 if (load_mode == LOAD_LOOPBACK_EXT) {
7101 lp->loopback_mode = ELINK_LOOPBACK_EXT;
7104 rc = elink_phy_init(&sc->link_params, &sc->link_vars);
7106 bnx2x_release_phy_lock(sc);
7108 bnx2x_calc_fc_adv(sc);
7110 if (sc->link_vars.link_up) {
7111 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7112 bnx2x_link_report(sc);
7115 sc->link_params.req_line_speed[cfg_idx] = req_line_speed;
7119 /* update flags in shmem */
7121 bnx2x_update_drv_flags(struct bnx2x_softc *sc, uint32_t flags, uint32_t set)
7125 if (SHMEM2_HAS(sc, drv_flags)) {
7126 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7127 drv_flags = SHMEM2_RD(sc, drv_flags);
7132 drv_flags &= ~flags;
7135 SHMEM2_WR(sc, drv_flags, drv_flags);
7137 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7141 /* periodic timer callout routine, only runs when the interface is up */
7142 void bnx2x_periodic_callout(struct bnx2x_softc *sc)
7144 if ((sc->state != BNX2X_STATE_OPEN) ||
7145 (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_STOP)) {
7146 PMD_DRV_LOG(DEBUG, sc, "periodic callout exit (state=0x%x)",
7150 if (!CHIP_REV_IS_SLOW(sc)) {
7152 * This barrier is needed to ensure the ordering between the writing
7153 * to the sc->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
7158 bnx2x_acquire_phy_lock(sc);
7159 elink_period_func(&sc->link_params, &sc->link_vars);
7160 bnx2x_release_phy_lock(sc);
7164 if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7165 int mb_idx = SC_FW_MB_IDX(sc);
7169 ++sc->fw_drv_pulse_wr_seq;
7170 sc->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
7172 drv_pulse = sc->fw_drv_pulse_wr_seq;
7173 bnx2x_drv_pulse(sc);
7175 mcp_pulse = (SHMEM_RD(sc, func_mb[mb_idx].mcp_pulse_mb) &
7176 MCP_PULSE_SEQ_MASK);
7179 * The delta between driver pulse and mcp response should
7180 * be 1 (before mcp response) or 0 (after mcp response).
7182 if ((drv_pulse != mcp_pulse) &&
7183 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
7184 /* someone lost a heartbeat... */
7185 PMD_DRV_LOG(ERR, sc,
7186 "drv_pulse (0x%x) != mcp_pulse (0x%x)",
7187 drv_pulse, mcp_pulse);
7193 /* start the controller */
7194 static __rte_noinline
7195 int bnx2x_nic_load(struct bnx2x_softc *sc)
7198 uint32_t load_code = 0;
7201 PMD_INIT_FUNC_TRACE(sc);
7203 sc->state = BNX2X_STATE_OPENING_WAITING_LOAD;
7206 /* must be called before memory allocation and HW init */
7207 bnx2x_ilt_set_info(sc);
7210 bnx2x_set_fp_rx_buf_size(sc);
7213 if (bnx2x_alloc_mem(sc) != 0) {
7214 sc->state = BNX2X_STATE_CLOSED;
7216 goto bnx2x_nic_load_error0;
7220 /* allocate the host hardware/software hsi structures */
7221 if (bnx2x_alloc_hsi_mem(sc) != 0) {
7222 PMD_DRV_LOG(ERR, sc, "bnx2x_alloc_hsi_mem was failed");
7223 sc->state = BNX2X_STATE_CLOSED;
7225 goto bnx2x_nic_load_error0;
7228 if (bnx2x_alloc_fw_stats_mem(sc) != 0) {
7229 sc->state = BNX2X_STATE_CLOSED;
7231 goto bnx2x_nic_load_error0;
7235 rc = bnx2x_vf_init(sc);
7237 sc->state = BNX2X_STATE_ERROR;
7238 goto bnx2x_nic_load_error0;
7243 /* set pf load just before approaching the MCP */
7244 bnx2x_set_pf_load(sc);
7246 /* if MCP exists send load request and analyze response */
7247 if (!BNX2X_NOMCP(sc)) {
7248 /* attempt to load pf */
7249 if (bnx2x_nic_load_request(sc, &load_code) != 0) {
7250 sc->state = BNX2X_STATE_CLOSED;
7252 goto bnx2x_nic_load_error1;
7255 /* what did the MCP say? */
7256 if (bnx2x_nic_load_analyze_req(sc, load_code) != 0) {
7257 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7258 sc->state = BNX2X_STATE_CLOSED;
7260 goto bnx2x_nic_load_error2;
7263 PMD_DRV_LOG(INFO, sc, "Device has no MCP!");
7264 load_code = bnx2x_nic_load_no_mcp(sc);
7267 /* mark PMF if applicable */
7268 bnx2x_nic_load_pmf(sc, load_code);
7270 /* Init Function state controlling object */
7271 bnx2x_init_func_obj(sc);
7274 if (bnx2x_init_hw(sc, load_code) != 0) {
7275 PMD_DRV_LOG(NOTICE, sc, "HW init failed");
7276 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7277 sc->state = BNX2X_STATE_CLOSED;
7279 goto bnx2x_nic_load_error2;
7283 bnx2x_nic_init(sc, load_code);
7285 /* Init per-function objects */
7287 bnx2x_init_objs(sc);
7289 /* set AFEX default VLAN tag to an invalid value */
7290 sc->devinfo.mf_info.afex_def_vlan_tag = -1;
7292 sc->state = BNX2X_STATE_OPENING_WAITING_PORT;
7293 rc = bnx2x_func_start(sc);
7295 PMD_DRV_LOG(NOTICE, sc, "Function start failed!");
7296 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7297 sc->state = BNX2X_STATE_ERROR;
7298 goto bnx2x_nic_load_error3;
7301 /* send LOAD_DONE command to MCP */
7302 if (!BNX2X_NOMCP(sc)) {
7304 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7306 PMD_DRV_LOG(NOTICE, sc,
7307 "MCP response failure, aborting");
7308 sc->state = BNX2X_STATE_ERROR;
7310 goto bnx2x_nic_load_error3;
7315 rc = bnx2x_setup_leading(sc);
7317 PMD_DRV_LOG(NOTICE, sc, "Setup leading failed!");
7318 sc->state = BNX2X_STATE_ERROR;
7319 goto bnx2x_nic_load_error3;
7322 FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, i) {
7324 rc = bnx2x_setup_queue(sc, &sc->fp[i], FALSE);
7325 else /* IS_VF(sc) */
7326 rc = bnx2x_vf_setup_queue(sc, &sc->fp[i], FALSE);
7329 PMD_DRV_LOG(NOTICE, sc, "Queue(%d) setup failed", i);
7330 sc->state = BNX2X_STATE_ERROR;
7331 goto bnx2x_nic_load_error3;
7335 rc = bnx2x_init_rss_pf(sc);
7337 PMD_DRV_LOG(NOTICE, sc, "PF RSS init failed");
7338 sc->state = BNX2X_STATE_ERROR;
7339 goto bnx2x_nic_load_error3;
7342 /* now when Clients are configured we are ready to work */
7343 sc->state = BNX2X_STATE_OPEN;
7345 /* Configure a ucast MAC */
7347 rc = bnx2x_set_eth_mac(sc, TRUE);
7348 } else { /* IS_VF(sc) */
7349 rc = bnx2x_vf_set_mac(sc, TRUE);
7353 PMD_DRV_LOG(NOTICE, sc, "Setting Ethernet MAC failed");
7354 sc->state = BNX2X_STATE_ERROR;
7355 goto bnx2x_nic_load_error3;
7359 rc = bnx2x_initial_phy_init(sc, LOAD_OPEN);
7361 sc->state = BNX2X_STATE_ERROR;
7362 goto bnx2x_nic_load_error3;
7366 sc->link_params.feature_config_flags &=
7367 ~ELINK_FEATURE_CONFIG_BOOT_FROM_SAN;
7370 switch (LOAD_OPEN) {
7376 case LOAD_LOOPBACK_EXT:
7377 sc->state = BNX2X_STATE_DIAG;
7385 bnx2x_update_drv_flags(sc, 1 << DRV_FLAGS_PORT_MASK, 0);
7387 bnx2x_link_status_update(sc);
7390 if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
7391 /* mark driver is loaded in shmem2 */
7392 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
7393 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
7395 DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED |
7396 DRV_FLAGS_CAPABILITIES_LOADED_L2));
7399 /* start fast path */
7400 /* Initialize Rx filter */
7401 bnx2x_set_rx_mode(sc);
7403 /* wait for all pending SP commands to complete */
7404 if (IS_PF(sc) && !bnx2x_wait_sp_comp(sc, ~0x0UL)) {
7405 PMD_DRV_LOG(NOTICE, sc, "Timeout waiting for all SPs to complete!");
7406 bnx2x_periodic_stop(sc);
7407 bnx2x_nic_unload(sc, UNLOAD_CLOSE, FALSE);
7411 PMD_DRV_LOG(DEBUG, sc, "NIC successfully loaded");
7415 bnx2x_nic_load_error3:
7418 bnx2x_int_disable_sync(sc, 1);
7420 /* clean out queued objects */
7421 bnx2x_squeeze_objects(sc);
7424 bnx2x_nic_load_error2:
7426 if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7427 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
7428 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
7433 bnx2x_nic_load_error1:
7435 /* clear pf_load status, as it was already set */
7437 bnx2x_clear_pf_load(sc);
7440 bnx2x_nic_load_error0:
7442 bnx2x_free_fw_stats_mem(sc);
7443 bnx2x_free_hsi_mem(sc);
7450 * Handles controller initialization.
7452 int bnx2x_init(struct bnx2x_softc *sc)
7454 int other_engine = SC_PATH(sc) ? 0 : 1;
7455 uint8_t other_load_status, load_status;
7456 uint8_t global = FALSE;
7459 /* Check if the driver is still running and bail out if it is. */
7460 if (sc->state != BNX2X_STATE_CLOSED) {
7461 PMD_DRV_LOG(DEBUG, sc, "Init called while driver is running!");
7463 goto bnx2x_init_done;
7466 bnx2x_set_power_state(sc, PCI_PM_D0);
7469 * If parity occurred during the unload, then attentions and/or
7470 * RECOVERY_IN_PROGRESS may still be set. If so we want the first function
7471 * loaded on the current engine to complete the recovery. Parity recovery
7472 * is only relevant for PF driver.
7475 other_load_status = bnx2x_get_load_status(sc, other_engine);
7476 load_status = bnx2x_get_load_status(sc, SC_PATH(sc));
7478 if (!bnx2x_reset_is_done(sc, SC_PATH(sc)) ||
7479 bnx2x_chk_parity_attn(sc, &global, TRUE)) {
7482 * If there are attentions and they are in global blocks, set
7483 * the GLOBAL_RESET bit regardless whether it will be this
7484 * function that will complete the recovery or not.
7487 bnx2x_set_reset_global(sc);
7491 * Only the first function on the current engine should try
7492 * to recover in open. In case of attentions in global blocks
7493 * only the first in the chip should try to recover.
7496 && (!global ||!other_load_status))
7497 && bnx2x_trylock_leader_lock(sc)
7498 && !bnx2x_leader_reset(sc)) {
7499 PMD_DRV_LOG(INFO, sc,
7500 "Recovered during init");
7504 /* recovery has failed... */
7505 bnx2x_set_power_state(sc, PCI_PM_D3hot);
7507 sc->recovery_state = BNX2X_RECOVERY_FAILED;
7509 PMD_DRV_LOG(NOTICE, sc,
7510 "Recovery flow hasn't properly "
7511 "completed yet, try again later. "
7512 "If you still see this message after a "
7513 "few retries then power cycle is required.");
7516 goto bnx2x_init_done;
7521 sc->recovery_state = BNX2X_RECOVERY_DONE;
7523 rc = bnx2x_nic_load(sc);
7528 PMD_DRV_LOG(NOTICE, sc, "Initialization failed, "
7529 "stack notified driver is NOT running!");
7535 static void bnx2x_get_function_num(struct bnx2x_softc *sc)
7540 * Read the ME register to get the function number. The ME register
7541 * holds the relative-function number and absolute-function number. The
7542 * absolute-function number appears only in E2 and above. Before that
7543 * these bits always contained zero, therefore we cannot blindly use them.
7546 val = REG_RD(sc, BAR_ME_REGISTER);
7549 (uint8_t) ((val & ME_REG_PF_NUM) >> ME_REG_PF_NUM_SHIFT);
7551 (uint8_t) ((val & ME_REG_ABS_PF_NUM) >> ME_REG_ABS_PF_NUM_SHIFT) &
7554 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7555 sc->pfunc_abs = ((sc->pfunc_rel << 1) | sc->path_id);
7557 sc->pfunc_abs = (sc->pfunc_rel | sc->path_id);
7560 PMD_DRV_LOG(DEBUG, sc,
7561 "Relative function %d, Absolute function %d, Path %d",
7562 sc->pfunc_rel, sc->pfunc_abs, sc->path_id);
7565 static uint32_t bnx2x_get_shmem_mf_cfg_base(struct bnx2x_softc *sc)
7567 uint32_t shmem2_size;
7569 uint32_t mf_cfg_offset_value;
7572 offset = (SHMEM_ADDR(sc, func_mb) +
7573 (MAX_FUNC_NUM * sizeof(struct drv_func_mb)));
7576 if (sc->devinfo.shmem2_base != 0) {
7577 shmem2_size = SHMEM2_RD(sc, size);
7578 if (shmem2_size > offsetof(struct shmem2_region, mf_cfg_addr)) {
7579 mf_cfg_offset_value = SHMEM2_RD(sc, mf_cfg_addr);
7580 if (SHMEM_MF_CFG_ADDR_NONE != mf_cfg_offset_value) {
7581 offset = mf_cfg_offset_value;
7589 static uint32_t bnx2x_pcie_capability_read(struct bnx2x_softc *sc, int reg)
7592 struct bnx2x_pci_cap *caps;
7594 /* ensure PCIe capability is enabled */
7595 caps = pci_find_cap(sc, PCIY_EXPRESS, BNX2X_PCI_CAP);
7597 PMD_DRV_LOG(DEBUG, sc, "Found PCIe capability: "
7598 "id=0x%04X type=0x%04X addr=0x%08X",
7599 caps->id, caps->type, caps->addr);
7600 pci_read(sc, (caps->addr + reg), &ret, 2);
7604 PMD_DRV_LOG(WARNING, sc, "PCIe capability NOT FOUND!!!");
7609 static uint8_t bnx2x_is_pcie_pending(struct bnx2x_softc *sc)
7611 return bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_STA) &
7612 PCIM_EXP_STA_TRANSACTION_PND;
7616 * Walk the PCI capabiites list for the device to find what features are
7617 * supported. These capabilites may be enabled/disabled by firmware so it's
7618 * best to walk the list rather than make assumptions.
7620 static void bnx2x_probe_pci_caps(struct bnx2x_softc *sc)
7622 PMD_INIT_FUNC_TRACE(sc);
7624 struct bnx2x_pci_cap *caps;
7625 uint16_t link_status;
7628 /* check if PCI Power Management is enabled */
7629 caps = pci_find_cap(sc, PCIY_PMG, BNX2X_PCI_CAP);
7631 PMD_DRV_LOG(DEBUG, sc, "Found PM capability: "
7632 "id=0x%04X type=0x%04X addr=0x%08X",
7633 caps->id, caps->type, caps->addr);
7635 sc->devinfo.pcie_cap_flags |= BNX2X_PM_CAPABLE_FLAG;
7636 sc->devinfo.pcie_pm_cap_reg = caps->addr;
7639 link_status = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_LINK_STA);
7641 sc->devinfo.pcie_link_speed = (link_status & PCIM_LINK_STA_SPEED);
7642 sc->devinfo.pcie_link_width =
7643 ((link_status & PCIM_LINK_STA_WIDTH) >> 4);
7645 PMD_DRV_LOG(DEBUG, sc, "PCIe link speed=%d width=%d",
7646 sc->devinfo.pcie_link_speed, sc->devinfo.pcie_link_width);
7648 sc->devinfo.pcie_cap_flags |= BNX2X_PCIE_CAPABLE_FLAG;
7650 /* check if MSI capability is enabled */
7651 caps = pci_find_cap(sc, PCIY_MSI, BNX2X_PCI_CAP);
7653 PMD_DRV_LOG(DEBUG, sc, "Found MSI capability at 0x%04x", reg);
7655 sc->devinfo.pcie_cap_flags |= BNX2X_MSI_CAPABLE_FLAG;
7656 sc->devinfo.pcie_msi_cap_reg = caps->addr;
7659 /* check if MSI-X capability is enabled */
7660 caps = pci_find_cap(sc, PCIY_MSIX, BNX2X_PCI_CAP);
7662 PMD_DRV_LOG(DEBUG, sc, "Found MSI-X capability at 0x%04x", reg);
7664 sc->devinfo.pcie_cap_flags |= BNX2X_MSIX_CAPABLE_FLAG;
7665 sc->devinfo.pcie_msix_cap_reg = caps->addr;
7669 static int bnx2x_get_shmem_mf_cfg_info_sd(struct bnx2x_softc *sc)
7671 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7674 /* get the outer vlan if we're in switch-dependent mode */
7676 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7677 mf_info->ext_id = (uint16_t) val;
7679 mf_info->multi_vnics_mode = 1;
7681 if (!VALID_OVLAN(mf_info->ext_id)) {
7682 PMD_DRV_LOG(NOTICE, sc, "Invalid VLAN (%d)", mf_info->ext_id);
7686 /* get the capabilities */
7687 if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK) ==
7688 FUNC_MF_CFG_PROTOCOL_ISCSI) {
7689 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ISCSI;
7690 } else if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK)
7691 == FUNC_MF_CFG_PROTOCOL_FCOE) {
7692 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_FCOE;
7694 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ETHERNET;
7697 mf_info->vnics_per_port =
7698 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7703 static uint32_t bnx2x_get_shmem_ext_proto_support_flags(struct bnx2x_softc *sc)
7705 uint32_t retval = 0;
7708 val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7710 if (val & MACP_FUNC_CFG_FLAGS_ENABLED) {
7711 if (val & MACP_FUNC_CFG_FLAGS_ETHERNET) {
7712 retval |= MF_PROTO_SUPPORT_ETHERNET;
7714 if (val & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
7715 retval |= MF_PROTO_SUPPORT_ISCSI;
7717 if (val & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
7718 retval |= MF_PROTO_SUPPORT_FCOE;
7725 static int bnx2x_get_shmem_mf_cfg_info_si(struct bnx2x_softc *sc)
7727 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7731 * There is no outer vlan if we're in switch-independent mode.
7732 * If the mac is valid then assume multi-function.
7735 val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7737 mf_info->multi_vnics_mode = ((val & MACP_FUNC_CFG_FLAGS_MASK) != 0);
7739 mf_info->mf_protos_supported =
7740 bnx2x_get_shmem_ext_proto_support_flags(sc);
7742 mf_info->vnics_per_port =
7743 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7748 static int bnx2x_get_shmem_mf_cfg_info_niv(struct bnx2x_softc *sc)
7750 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7752 uint32_t func_config;
7753 uint32_t niv_config;
7755 mf_info->multi_vnics_mode = 1;
7757 e1hov_tag = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7758 func_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7759 niv_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].afex_config);
7762 (uint16_t) ((e1hov_tag & FUNC_MF_CFG_E1HOV_TAG_MASK) >>
7763 FUNC_MF_CFG_E1HOV_TAG_SHIFT);
7765 mf_info->default_vlan =
7766 (uint16_t) ((e1hov_tag & FUNC_MF_CFG_AFEX_VLAN_MASK) >>
7767 FUNC_MF_CFG_AFEX_VLAN_SHIFT);
7769 mf_info->niv_allowed_priorities =
7770 (uint8_t) ((niv_config & FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
7771 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT);
7773 mf_info->niv_default_cos =
7774 (uint8_t) ((func_config & FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
7775 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT);
7777 mf_info->afex_vlan_mode =
7778 ((niv_config & FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
7779 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT);
7781 mf_info->niv_mba_enabled =
7782 ((niv_config & FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK) >>
7783 FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT);
7785 mf_info->mf_protos_supported =
7786 bnx2x_get_shmem_ext_proto_support_flags(sc);
7788 mf_info->vnics_per_port =
7789 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7794 static int bnx2x_check_valid_mf_cfg(struct bnx2x_softc *sc)
7796 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7803 /* various MF mode sanity checks... */
7805 if (mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_HIDE) {
7806 PMD_DRV_LOG(NOTICE, sc,
7807 "Enumerated function %d is marked as hidden",
7812 if ((mf_info->vnics_per_port > 1) && !mf_info->multi_vnics_mode) {
7813 PMD_DRV_LOG(NOTICE, sc, "vnics_per_port=%d multi_vnics_mode=%d",
7814 mf_info->vnics_per_port, mf_info->multi_vnics_mode);
7818 if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7819 /* vnic id > 0 must have valid ovlan in switch-dependent mode */
7820 if ((SC_VN(sc) > 0) && !VALID_OVLAN(OVLAN(sc))) {
7821 PMD_DRV_LOG(NOTICE, sc, "mf_mode=SD vnic_id=%d ovlan=%d",
7822 SC_VN(sc), OVLAN(sc));
7826 if (!VALID_OVLAN(OVLAN(sc)) && mf_info->multi_vnics_mode) {
7827 PMD_DRV_LOG(NOTICE, sc,
7828 "mf_mode=SD multi_vnics_mode=%d ovlan=%d",
7829 mf_info->multi_vnics_mode, OVLAN(sc));
7834 * Verify all functions are either MF or SF mode. If MF, make sure
7835 * sure that all non-hidden functions have a valid ovlan. If SF,
7836 * make sure that all non-hidden functions have an invalid ovlan.
7838 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7839 mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7840 ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7841 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE) &&
7842 (((mf_info->multi_vnics_mode)
7843 && !VALID_OVLAN(ovlan1))
7844 || ((!mf_info->multi_vnics_mode)
7845 && VALID_OVLAN(ovlan1)))) {
7846 PMD_DRV_LOG(NOTICE, sc,
7847 "mf_mode=SD function %d MF config "
7848 "mismatch, multi_vnics_mode=%d ovlan=%d",
7849 i, mf_info->multi_vnics_mode,
7855 /* Verify all funcs on the same port each have a different ovlan. */
7856 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7857 mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7858 ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7859 /* iterate from the next function on the port to the max func */
7860 for (j = i + 2; j < MAX_FUNC_NUM; j += 2) {
7862 MFCFG_RD(sc, func_mf_config[j].config);
7864 MFCFG_RD(sc, func_mf_config[j].e1hov_tag);
7865 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE)
7866 && VALID_OVLAN(ovlan1)
7867 && !(mf_cfg2 & FUNC_MF_CFG_FUNC_HIDE)
7868 && VALID_OVLAN(ovlan2)
7869 && (ovlan1 == ovlan2)) {
7870 PMD_DRV_LOG(NOTICE, sc,
7871 "mf_mode=SD functions %d and %d "
7872 "have the same ovlan (%d)",
7879 /* MULTI_FUNCTION_SD */
7883 static int bnx2x_get_mf_cfg_info(struct bnx2x_softc *sc)
7885 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7886 uint32_t val, mac_upper;
7889 /* initialize mf_info defaults */
7890 mf_info->vnics_per_port = 1;
7891 mf_info->multi_vnics_mode = FALSE;
7892 mf_info->path_has_ovlan = FALSE;
7893 mf_info->mf_mode = SINGLE_FUNCTION;
7895 if (!CHIP_IS_MF_CAP(sc)) {
7899 if (sc->devinfo.mf_cfg_base == SHMEM_MF_CFG_ADDR_NONE) {
7900 PMD_DRV_LOG(NOTICE, sc, "Invalid mf_cfg_base!");
7904 /* get the MF mode (switch dependent / independent / single-function) */
7906 val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
7908 switch (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK) {
7909 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
7912 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7914 /* check for legal upper mac bytes */
7915 if (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT) {
7916 mf_info->mf_mode = MULTI_FUNCTION_SI;
7918 PMD_DRV_LOG(NOTICE, sc,
7919 "Invalid config for Switch Independent mode");
7924 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
7925 case SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4:
7927 /* get outer vlan configuration */
7928 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7930 if ((val & FUNC_MF_CFG_E1HOV_TAG_MASK) !=
7931 FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
7932 mf_info->mf_mode = MULTI_FUNCTION_SD;
7934 PMD_DRV_LOG(NOTICE, sc,
7935 "Invalid config for Switch Dependent mode");
7940 case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
7942 /* not in MF mode, vnics_per_port=1 and multi_vnics_mode=FALSE */
7945 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
7948 * Mark MF mode as NIV if MCP version includes NPAR-SD support
7949 * and the MAC address is valid.
7952 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7954 if ((SHMEM2_HAS(sc, afex_driver_support)) &&
7955 (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT)) {
7956 mf_info->mf_mode = MULTI_FUNCTION_AFEX;
7958 PMD_DRV_LOG(NOTICE, sc, "Invalid config for AFEX mode");
7965 PMD_DRV_LOG(NOTICE, sc, "Unknown MF mode (0x%08x)",
7966 (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK));
7971 /* set path mf_mode (which could be different than function mf_mode) */
7972 if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7973 mf_info->path_has_ovlan = TRUE;
7974 } else if (mf_info->mf_mode == SINGLE_FUNCTION) {
7976 * Decide on path multi vnics mode. If we're not in MF mode and in
7977 * 4-port mode, this is good enough to check vnic-0 of the other port
7980 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7981 uint8_t other_port = !(PORT_ID(sc) & 1);
7982 uint8_t abs_func_other_port =
7983 (SC_PATH(sc) + (2 * other_port));
7988 [abs_func_other_port].e1hov_tag);
7990 mf_info->path_has_ovlan = VALID_OVLAN((uint16_t) val);
7994 if (mf_info->mf_mode == SINGLE_FUNCTION) {
7995 /* invalid MF config */
7996 if (SC_VN(sc) >= 1) {
7997 PMD_DRV_LOG(NOTICE, sc, "VNIC ID >= 1 in SF mode");
8004 /* get the MF configuration */
8005 mf_info->mf_config[SC_VN(sc)] =
8006 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
8008 switch (mf_info->mf_mode) {
8009 case MULTI_FUNCTION_SD:
8011 bnx2x_get_shmem_mf_cfg_info_sd(sc);
8014 case MULTI_FUNCTION_SI:
8016 bnx2x_get_shmem_mf_cfg_info_si(sc);
8019 case MULTI_FUNCTION_AFEX:
8021 bnx2x_get_shmem_mf_cfg_info_niv(sc);
8026 PMD_DRV_LOG(NOTICE, sc, "Get MF config failed (mf_mode=0x%08x)",
8031 /* get the congestion management parameters */
8034 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
8035 /* get min/max bw */
8036 val = MFCFG_RD(sc, func_mf_config[i].config);
8037 mf_info->min_bw[vnic] =
8038 ((val & FUNC_MF_CFG_MIN_BW_MASK) >>
8039 FUNC_MF_CFG_MIN_BW_SHIFT);
8040 mf_info->max_bw[vnic] =
8041 ((val & FUNC_MF_CFG_MAX_BW_MASK) >>
8042 FUNC_MF_CFG_MAX_BW_SHIFT);
8046 return bnx2x_check_valid_mf_cfg(sc);
8049 static int bnx2x_get_shmem_info(struct bnx2x_softc *sc)
8052 uint32_t mac_hi, mac_lo, val;
8054 PMD_INIT_FUNC_TRACE(sc);
8057 mac_hi = mac_lo = 0;
8059 sc->link_params.sc = sc;
8060 sc->link_params.port = port;
8062 /* get the hardware config info */
8063 sc->devinfo.hw_config = SHMEM_RD(sc, dev_info.shared_hw_config.config);
8064 sc->devinfo.hw_config2 =
8065 SHMEM_RD(sc, dev_info.shared_hw_config.config2);
8067 sc->link_params.hw_led_mode =
8068 ((sc->devinfo.hw_config & SHARED_HW_CFG_LED_MODE_MASK) >>
8069 SHARED_HW_CFG_LED_MODE_SHIFT);
8071 /* get the port feature config */
8073 SHMEM_RD(sc, dev_info.port_feature_config[port].config);
8075 /* get the link params */
8076 sc->link_params.speed_cap_mask[ELINK_INT_PHY] =
8077 SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask)
8078 & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
8079 sc->link_params.speed_cap_mask[ELINK_EXT_PHY1] =
8080 SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask2)
8081 & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
8083 /* get the lane config */
8084 sc->link_params.lane_config =
8085 SHMEM_RD(sc, dev_info.port_hw_config[port].lane_config);
8087 /* get the link config */
8088 val = SHMEM_RD(sc, dev_info.port_feature_config[port].link_config);
8089 sc->port.link_config[ELINK_INT_PHY] = val;
8090 sc->link_params.switch_cfg = (val & PORT_FEATURE_CONNECTED_SWITCH_MASK);
8091 sc->port.link_config[ELINK_EXT_PHY1] =
8092 SHMEM_RD(sc, dev_info.port_feature_config[port].link_config2);
8094 /* get the override preemphasis flag and enable it or turn it off */
8095 val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
8096 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) {
8097 sc->link_params.feature_config_flags |=
8098 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8100 sc->link_params.feature_config_flags &=
8101 ~ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8104 val = sc->devinfo.bc_ver >> 8;
8105 if (val < BNX2X_BC_VER) {
8106 /* for now only warn later we might need to enforce this */
8107 PMD_DRV_LOG(NOTICE, sc, "This driver needs bc_ver %X but found %X, please upgrade BC\n",
8110 sc->link_params.feature_config_flags |=
8111 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
8112 ELINK_FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY :
8115 sc->link_params.feature_config_flags |=
8116 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
8117 ELINK_FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
8118 sc->link_params.feature_config_flags |=
8119 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
8120 ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
8121 sc->link_params.feature_config_flags |=
8122 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
8123 ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
8125 /* get the initial value of the link params */
8126 sc->link_params.multi_phy_config =
8127 SHMEM_RD(sc, dev_info.port_hw_config[port].multi_phy_config);
8129 /* get external phy info */
8130 sc->port.ext_phy_config =
8131 SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
8133 /* get the multifunction configuration */
8134 bnx2x_get_mf_cfg_info(sc);
8136 /* get the mac address */
8139 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
8141 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_lower);
8143 mac_hi = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_upper);
8144 mac_lo = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_lower);
8147 if ((mac_lo == 0) && (mac_hi == 0)) {
8148 *sc->mac_addr_str = 0;
8149 PMD_DRV_LOG(NOTICE, sc, "No Ethernet address programmed!");
8151 sc->link_params.mac_addr[0] = (uint8_t) (mac_hi >> 8);
8152 sc->link_params.mac_addr[1] = (uint8_t) (mac_hi);
8153 sc->link_params.mac_addr[2] = (uint8_t) (mac_lo >> 24);
8154 sc->link_params.mac_addr[3] = (uint8_t) (mac_lo >> 16);
8155 sc->link_params.mac_addr[4] = (uint8_t) (mac_lo >> 8);
8156 sc->link_params.mac_addr[5] = (uint8_t) (mac_lo);
8157 snprintf(sc->mac_addr_str, sizeof(sc->mac_addr_str),
8158 "%02x:%02x:%02x:%02x:%02x:%02x",
8159 sc->link_params.mac_addr[0],
8160 sc->link_params.mac_addr[1],
8161 sc->link_params.mac_addr[2],
8162 sc->link_params.mac_addr[3],
8163 sc->link_params.mac_addr[4],
8164 sc->link_params.mac_addr[5]);
8165 PMD_DRV_LOG(DEBUG, sc,
8166 "Ethernet address: %s", sc->mac_addr_str);
8172 static void bnx2x_media_detect(struct bnx2x_softc *sc)
8174 uint32_t phy_idx = bnx2x_get_cur_phy_idx(sc);
8175 switch (sc->link_params.phy[phy_idx].media_type) {
8176 case ELINK_ETH_PHY_SFPP_10G_FIBER:
8177 case ELINK_ETH_PHY_SFP_1G_FIBER:
8178 case ELINK_ETH_PHY_XFP_FIBER:
8179 case ELINK_ETH_PHY_KR:
8180 case ELINK_ETH_PHY_CX4:
8181 PMD_DRV_LOG(INFO, sc, "Found 10GBase-CX4 media.");
8182 sc->media = IFM_10G_CX4;
8184 case ELINK_ETH_PHY_DA_TWINAX:
8185 PMD_DRV_LOG(INFO, sc, "Found 10Gb Twinax media.");
8186 sc->media = IFM_10G_TWINAX;
8188 case ELINK_ETH_PHY_BASE_T:
8189 PMD_DRV_LOG(INFO, sc, "Found 10GBase-T media.");
8190 sc->media = IFM_10G_T;
8192 case ELINK_ETH_PHY_NOT_PRESENT:
8193 PMD_DRV_LOG(INFO, sc, "Media not present.");
8196 case ELINK_ETH_PHY_UNSPECIFIED:
8198 PMD_DRV_LOG(INFO, sc, "Unknown media!");
8204 #define GET_FIELD(value, fname) \
8205 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
8206 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
8207 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
8209 static int bnx2x_get_igu_cam_info(struct bnx2x_softc *sc)
8211 int pfid = SC_FUNC(sc);
8214 uint8_t fid, igu_sb_cnt = 0;
8216 sc->igu_base_sb = 0xff;
8218 if (CHIP_INT_MODE_IS_BC(sc)) {
8220 igu_sb_cnt = sc->igu_sb_cnt;
8221 sc->igu_base_sb = ((CHIP_IS_MODE_4_PORT(sc) ? pfid : vn) *
8223 sc->igu_dsb_id = (E1HVN_MAX * FP_SB_MAX_E1x +
8224 (CHIP_IS_MODE_4_PORT(sc) ? pfid : vn));
8228 /* IGU in normal mode - read CAM */
8230 igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; igu_sb_id++) {
8231 val = REG_RD(sc, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
8232 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) {
8236 if (fid & IGU_FID_ENCODE_IS_PF) {
8237 if ((fid & IGU_FID_PF_NUM_MASK) != pfid) {
8240 if (IGU_VEC(val) == 0) {
8241 /* default status block */
8242 sc->igu_dsb_id = igu_sb_id;
8244 if (sc->igu_base_sb == 0xff) {
8245 sc->igu_base_sb = igu_sb_id;
8253 * Due to new PF resource allocation by MFW T7.4 and above, it's optional
8254 * that number of CAM entries will not be equal to the value advertised in
8255 * PCI. Driver should use the minimal value of both as the actual status
8258 sc->igu_sb_cnt = min(sc->igu_sb_cnt, igu_sb_cnt);
8260 if (igu_sb_cnt == 0) {
8261 PMD_DRV_LOG(ERR, sc, "CAM configuration error");
8269 * Gather various information from the device config space, the device itself,
8270 * shmem, and the user input.
8272 static int bnx2x_get_device_info(struct bnx2x_softc *sc)
8277 /* get the chip revision (chip metal comes from pci config space) */
8278 sc->devinfo.chip_id = sc->link_params.chip_id =
8279 (((REG_RD(sc, MISC_REG_CHIP_NUM) & 0xffff) << 16) |
8280 ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12) |
8281 (((REG_RD(sc, PCICFG_OFFSET + PCI_ID_VAL3) >> 24) & 0xf) << 4) |
8282 ((REG_RD(sc, MISC_REG_BOND_ID) & 0xf) << 0));
8284 /* force 57811 according to MISC register */
8285 if (REG_RD(sc, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
8286 if (CHIP_IS_57810(sc)) {
8287 sc->devinfo.chip_id = ((CHIP_NUM_57811 << 16) |
8289 devinfo.chip_id & 0x0000ffff));
8290 } else if (CHIP_IS_57810_MF(sc)) {
8291 sc->devinfo.chip_id = ((CHIP_NUM_57811_MF << 16) |
8293 devinfo.chip_id & 0x0000ffff));
8295 sc->devinfo.chip_id |= 0x1;
8298 PMD_DRV_LOG(DEBUG, sc,
8299 "chip_id=0x%08x (num=0x%04x rev=0x%01x metal=0x%02x bond=0x%01x)",
8300 sc->devinfo.chip_id,
8301 ((sc->devinfo.chip_id >> 16) & 0xffff),
8302 ((sc->devinfo.chip_id >> 12) & 0xf),
8303 ((sc->devinfo.chip_id >> 4) & 0xff),
8304 ((sc->devinfo.chip_id >> 0) & 0xf));
8306 val = (REG_RD(sc, 0x2874) & 0x55);
8307 if ((sc->devinfo.chip_id & 0x1) || (CHIP_IS_E1H(sc) && (val == 0x55))) {
8308 sc->flags |= BNX2X_ONE_PORT_FLAG;
8309 PMD_DRV_LOG(DEBUG, sc, "single port device");
8312 /* set the doorbell size */
8313 sc->doorbell_size = (1 << BNX2X_DB_SHIFT);
8315 /* determine whether the device is in 2 port or 4 port mode */
8316 sc->devinfo.chip_port_mode = CHIP_PORT_MODE_NONE; /* E1h */
8317 if (CHIP_IS_E2E3(sc)) {
8319 * Read port4mode_en_ovwr[0]:
8320 * If 1, four port mode is in port4mode_en_ovwr[1].
8321 * If 0, four port mode is in port4mode_en[0].
8323 val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);
8325 val = ((val >> 1) & 1);
8327 val = REG_RD(sc, MISC_REG_PORT4MODE_EN);
8330 sc->devinfo.chip_port_mode =
8331 (val) ? CHIP_4_PORT_MODE : CHIP_2_PORT_MODE;
8333 PMD_DRV_LOG(DEBUG, sc, "Port mode = %s", (val) ? "4" : "2");
8336 /* get the function and path info for the device */
8337 bnx2x_get_function_num(sc);
8339 /* get the shared memory base address */
8340 sc->devinfo.shmem_base =
8341 sc->link_params.shmem_base = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
8342 sc->devinfo.shmem2_base =
8343 REG_RD(sc, (SC_PATH(sc) ? MISC_REG_GENERIC_CR_1 :
8344 MISC_REG_GENERIC_CR_0));
8346 if (!sc->devinfo.shmem_base) {
8347 /* this should ONLY prevent upcoming shmem reads */
8348 PMD_DRV_LOG(INFO, sc, "MCP not active");
8349 sc->flags |= BNX2X_NO_MCP_FLAG;
8353 /* make sure the shared memory contents are valid */
8354 val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
8355 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) !=
8356 (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) {
8357 PMD_DRV_LOG(NOTICE, sc, "Invalid SHMEM validity signature: 0x%08x",
8362 /* get the bootcode version */
8363 sc->devinfo.bc_ver = SHMEM_RD(sc, dev_info.bc_rev);
8364 snprintf(sc->devinfo.bc_ver_str,
8365 sizeof(sc->devinfo.bc_ver_str),
8367 ((sc->devinfo.bc_ver >> 24) & 0xff),
8368 ((sc->devinfo.bc_ver >> 16) & 0xff),
8369 ((sc->devinfo.bc_ver >> 8) & 0xff));
8370 PMD_DRV_LOG(DEBUG, sc, "Bootcode version: %s", sc->devinfo.bc_ver_str);
8372 /* get the bootcode shmem address */
8373 sc->devinfo.mf_cfg_base = bnx2x_get_shmem_mf_cfg_base(sc);
8375 /* clean indirect addresses as they're not used */
8376 pci_write_long(sc, PCICFG_GRC_ADDRESS, 0);
8378 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F0, 0);
8379 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F0, 0);
8380 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F0, 0);
8381 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F0, 0);
8382 if (CHIP_IS_E1x(sc)) {
8383 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F1, 0);
8384 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F1, 0);
8385 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F1, 0);
8386 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F1, 0);
8390 /* get the nvram size */
8391 val = REG_RD(sc, MCP_REG_MCPR_NVM_CFG4);
8392 sc->devinfo.flash_size =
8393 (NVRAM_1MB_SIZE << (val & MCPR_NVM_CFG4_FLASH_SIZE));
8395 bnx2x_set_power_state(sc, PCI_PM_D0);
8396 /* get various configuration parameters from shmem */
8397 bnx2x_get_shmem_info(sc);
8399 /* initialize IGU parameters */
8400 if (CHIP_IS_E1x(sc)) {
8401 sc->devinfo.int_block = INT_BLOCK_HC;
8402 sc->igu_dsb_id = DEF_SB_IGU_ID;
8403 sc->igu_base_sb = 0;
8405 sc->devinfo.int_block = INT_BLOCK_IGU;
8407 /* do not allow device reset during IGU info preocessing */
8408 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8410 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
8412 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8415 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
8416 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION, val);
8417 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x7f);
8419 while (tout && REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8424 if (REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8425 PMD_DRV_LOG(NOTICE, sc,
8426 "FORCING IGU Normal Mode failed!!!");
8427 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8432 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8433 PMD_DRV_LOG(DEBUG, sc, "IGU Backward Compatible Mode");
8434 sc->devinfo.int_block |= INT_BLOCK_MODE_BW_COMP;
8436 PMD_DRV_LOG(DEBUG, sc, "IGU Normal Mode");
8439 rc = bnx2x_get_igu_cam_info(sc);
8441 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8449 * Get base FW non-default (fast path) status block ID. This value is
8450 * used to initialize the fw_sb_id saved on the fp/queue structure to
8451 * determine the id used by the FW.
8453 if (CHIP_IS_E1x(sc)) {
8455 ((SC_PORT(sc) * FP_SB_MAX_E1x) + SC_L_ID(sc));
8458 * 57712+ - We currently use one FW SB per IGU SB (Rx and Tx of
8459 * the same queue are indicated on the same IGU SB). So we prefer
8460 * FW and IGU SBs to be the same value.
8462 sc->base_fw_ndsb = sc->igu_base_sb;
8465 elink_phy_probe(&sc->link_params);
8471 bnx2x_link_settings_supported(struct bnx2x_softc *sc, uint32_t switch_cfg)
8473 uint32_t cfg_size = 0;
8475 uint8_t port = SC_PORT(sc);
8477 /* aggregation of supported attributes of all external phys */
8478 sc->port.supported[0] = 0;
8479 sc->port.supported[1] = 0;
8481 switch (sc->link_params.num_phys) {
8483 sc->port.supported[0] =
8484 sc->link_params.phy[ELINK_INT_PHY].supported;
8488 sc->port.supported[0] =
8489 sc->link_params.phy[ELINK_EXT_PHY1].supported;
8493 if (sc->link_params.multi_phy_config &
8494 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
8495 sc->port.supported[1] =
8496 sc->link_params.phy[ELINK_EXT_PHY1].supported;
8497 sc->port.supported[0] =
8498 sc->link_params.phy[ELINK_EXT_PHY2].supported;
8500 sc->port.supported[0] =
8501 sc->link_params.phy[ELINK_EXT_PHY1].supported;
8502 sc->port.supported[1] =
8503 sc->link_params.phy[ELINK_EXT_PHY2].supported;
8509 if (!(sc->port.supported[0] || sc->port.supported[1])) {
8510 PMD_DRV_LOG(ERR, sc,
8511 "Invalid phy config in NVRAM (PHY1=0x%08x PHY2=0x%08x)",
8513 dev_info.port_hw_config
8514 [port].external_phy_config),
8516 dev_info.port_hw_config
8517 [port].external_phy_config2));
8522 sc->port.phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR);
8524 switch (switch_cfg) {
8525 case ELINK_SWITCH_CFG_1G:
8528 NIG_REG_SERDES0_CTRL_PHY_ADDR + port * 0x10);
8530 case ELINK_SWITCH_CFG_10G:
8533 NIG_REG_XGXS0_CTRL_PHY_ADDR + port * 0x18);
8536 PMD_DRV_LOG(ERR, sc,
8537 "Invalid switch config in"
8538 "link_config=0x%08x",
8539 sc->port.link_config[0]);
8544 PMD_DRV_LOG(INFO, sc, "PHY addr 0x%08x", sc->port.phy_addr);
8546 /* mask what we support according to speed_cap_mask per configuration */
8547 for (idx = 0; idx < cfg_size; idx++) {
8548 if (!(sc->link_params.speed_cap_mask[idx] &
8549 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) {
8550 sc->port.supported[idx] &=
8551 ~ELINK_SUPPORTED_10baseT_Half;
8554 if (!(sc->link_params.speed_cap_mask[idx] &
8555 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) {
8556 sc->port.supported[idx] &=
8557 ~ELINK_SUPPORTED_10baseT_Full;
8560 if (!(sc->link_params.speed_cap_mask[idx] &
8561 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) {
8562 sc->port.supported[idx] &=
8563 ~ELINK_SUPPORTED_100baseT_Half;
8566 if (!(sc->link_params.speed_cap_mask[idx] &
8567 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) {
8568 sc->port.supported[idx] &=
8569 ~ELINK_SUPPORTED_100baseT_Full;
8572 if (!(sc->link_params.speed_cap_mask[idx] &
8573 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) {
8574 sc->port.supported[idx] &=
8575 ~ELINK_SUPPORTED_1000baseT_Full;
8578 if (!(sc->link_params.speed_cap_mask[idx] &
8579 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) {
8580 sc->port.supported[idx] &=
8581 ~ELINK_SUPPORTED_2500baseX_Full;
8584 if (!(sc->link_params.speed_cap_mask[idx] &
8585 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8586 sc->port.supported[idx] &=
8587 ~ELINK_SUPPORTED_10000baseT_Full;
8590 if (!(sc->link_params.speed_cap_mask[idx] &
8591 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) {
8592 sc->port.supported[idx] &=
8593 ~ELINK_SUPPORTED_20000baseKR2_Full;
8597 PMD_DRV_LOG(INFO, sc, "PHY supported 0=0x%08x 1=0x%08x",
8598 sc->port.supported[0], sc->port.supported[1]);
8601 static void bnx2x_link_settings_requested(struct bnx2x_softc *sc)
8603 uint32_t link_config;
8605 uint32_t cfg_size = 0;
8607 sc->port.advertising[0] = 0;
8608 sc->port.advertising[1] = 0;
8610 switch (sc->link_params.num_phys) {
8620 for (idx = 0; idx < cfg_size; idx++) {
8621 sc->link_params.req_duplex[idx] = DUPLEX_FULL;
8622 link_config = sc->port.link_config[idx];
8624 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
8625 case PORT_FEATURE_LINK_SPEED_AUTO:
8626 if (sc->port.supported[idx] & ELINK_SUPPORTED_Autoneg) {
8627 sc->link_params.req_line_speed[idx] =
8628 ELINK_SPEED_AUTO_NEG;
8629 sc->port.advertising[idx] |=
8630 sc->port.supported[idx];
8631 if (sc->link_params.phy[ELINK_EXT_PHY1].type ==
8632 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833)
8633 sc->port.advertising[idx] |=
8634 (ELINK_SUPPORTED_100baseT_Half |
8635 ELINK_SUPPORTED_100baseT_Full);
8637 /* force 10G, no AN */
8638 sc->link_params.req_line_speed[idx] =
8640 sc->port.advertising[idx] |=
8641 (ADVERTISED_10000baseT_Full |
8647 case PORT_FEATURE_LINK_SPEED_10M_FULL:
8649 port.supported[idx] & ELINK_SUPPORTED_10baseT_Full)
8651 sc->link_params.req_line_speed[idx] =
8653 sc->port.advertising[idx] |=
8654 (ADVERTISED_10baseT_Full | ADVERTISED_TP);
8656 PMD_DRV_LOG(ERR, sc,
8657 "Invalid NVRAM config link_config=0x%08x "
8658 "speed_cap_mask=0x%08x",
8661 link_params.speed_cap_mask[idx]);
8666 case PORT_FEATURE_LINK_SPEED_10M_HALF:
8668 port.supported[idx] & ELINK_SUPPORTED_10baseT_Half)
8670 sc->link_params.req_line_speed[idx] =
8672 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8673 sc->port.advertising[idx] |=
8674 (ADVERTISED_10baseT_Half | ADVERTISED_TP);
8676 PMD_DRV_LOG(ERR, sc,
8677 "Invalid NVRAM config link_config=0x%08x "
8678 "speed_cap_mask=0x%08x",
8681 link_params.speed_cap_mask[idx]);
8686 case PORT_FEATURE_LINK_SPEED_100M_FULL:
8688 port.supported[idx] & ELINK_SUPPORTED_100baseT_Full)
8690 sc->link_params.req_line_speed[idx] =
8692 sc->port.advertising[idx] |=
8693 (ADVERTISED_100baseT_Full | ADVERTISED_TP);
8695 PMD_DRV_LOG(ERR, sc,
8696 "Invalid NVRAM config link_config=0x%08x "
8697 "speed_cap_mask=0x%08x",
8700 link_params.speed_cap_mask[idx]);
8705 case PORT_FEATURE_LINK_SPEED_100M_HALF:
8707 port.supported[idx] & ELINK_SUPPORTED_100baseT_Half)
8709 sc->link_params.req_line_speed[idx] =
8711 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8712 sc->port.advertising[idx] |=
8713 (ADVERTISED_100baseT_Half | ADVERTISED_TP);
8715 PMD_DRV_LOG(ERR, sc,
8716 "Invalid NVRAM config link_config=0x%08x "
8717 "speed_cap_mask=0x%08x",
8720 link_params.speed_cap_mask[idx]);
8725 case PORT_FEATURE_LINK_SPEED_1G:
8726 if (sc->port.supported[idx] &
8727 ELINK_SUPPORTED_1000baseT_Full) {
8728 sc->link_params.req_line_speed[idx] =
8730 sc->port.advertising[idx] |=
8731 (ADVERTISED_1000baseT_Full | ADVERTISED_TP);
8733 PMD_DRV_LOG(ERR, sc,
8734 "Invalid NVRAM config link_config=0x%08x "
8735 "speed_cap_mask=0x%08x",
8738 link_params.speed_cap_mask[idx]);
8743 case PORT_FEATURE_LINK_SPEED_2_5G:
8744 if (sc->port.supported[idx] &
8745 ELINK_SUPPORTED_2500baseX_Full) {
8746 sc->link_params.req_line_speed[idx] =
8748 sc->port.advertising[idx] |=
8749 (ADVERTISED_2500baseX_Full | ADVERTISED_TP);
8751 PMD_DRV_LOG(ERR, sc,
8752 "Invalid NVRAM config link_config=0x%08x "
8753 "speed_cap_mask=0x%08x",
8756 link_params.speed_cap_mask[idx]);
8761 case PORT_FEATURE_LINK_SPEED_10G_CX4:
8762 if (sc->port.supported[idx] &
8763 ELINK_SUPPORTED_10000baseT_Full) {
8764 sc->link_params.req_line_speed[idx] =
8766 sc->port.advertising[idx] |=
8767 (ADVERTISED_10000baseT_Full |
8770 PMD_DRV_LOG(ERR, sc,
8771 "Invalid NVRAM config link_config=0x%08x "
8772 "speed_cap_mask=0x%08x",
8775 link_params.speed_cap_mask[idx]);
8780 case PORT_FEATURE_LINK_SPEED_20G:
8781 sc->link_params.req_line_speed[idx] = ELINK_SPEED_20000;
8785 PMD_DRV_LOG(ERR, sc,
8786 "Invalid NVRAM config link_config=0x%08x "
8787 "speed_cap_mask=0x%08x", link_config,
8788 sc->link_params.speed_cap_mask[idx]);
8789 sc->link_params.req_line_speed[idx] =
8790 ELINK_SPEED_AUTO_NEG;
8791 sc->port.advertising[idx] = sc->port.supported[idx];
8795 sc->link_params.req_flow_ctrl[idx] =
8796 (link_config & PORT_FEATURE_FLOW_CONTROL_MASK);
8798 if (sc->link_params.req_flow_ctrl[idx] == ELINK_FLOW_CTRL_AUTO) {
8801 port.supported[idx] & ELINK_SUPPORTED_Autoneg)) {
8802 sc->link_params.req_flow_ctrl[idx] =
8803 ELINK_FLOW_CTRL_NONE;
8805 bnx2x_set_requested_fc(sc);
8811 static void bnx2x_get_phy_info(struct bnx2x_softc *sc)
8813 uint8_t port = SC_PORT(sc);
8816 PMD_INIT_FUNC_TRACE(sc);
8818 /* shmem data already read in bnx2x_get_shmem_info() */
8820 bnx2x_link_settings_supported(sc, sc->link_params.switch_cfg);
8821 bnx2x_link_settings_requested(sc);
8823 /* configure link feature according to nvram value */
8825 (((SHMEM_RD(sc, dev_info.port_feature_config[port].eee_power_mode))
8826 & PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
8827 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
8828 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
8829 sc->link_params.eee_mode = (ELINK_EEE_MODE_ADV_LPI |
8830 ELINK_EEE_MODE_ENABLE_LPI |
8831 ELINK_EEE_MODE_OUTPUT_TIME);
8833 sc->link_params.eee_mode = 0;
8836 /* get the media type */
8837 bnx2x_media_detect(sc);
8840 static void bnx2x_set_modes_bitmap(struct bnx2x_softc *sc)
8842 uint32_t flags = MODE_ASIC | MODE_PORT2;
8844 if (CHIP_IS_E2(sc)) {
8846 } else if (CHIP_IS_E3(sc)) {
8848 if (CHIP_REV(sc) == CHIP_REV_Ax) {
8849 flags |= MODE_E3_A0;
8850 } else { /*if (CHIP_REV(sc) == CHIP_REV_Bx) */
8852 flags |= MODE_E3_B0 | MODE_COS3;
8858 switch (sc->devinfo.mf_info.mf_mode) {
8859 case MULTI_FUNCTION_SD:
8860 flags |= MODE_MF_SD;
8862 case MULTI_FUNCTION_SI:
8863 flags |= MODE_MF_SI;
8865 case MULTI_FUNCTION_AFEX:
8866 flags |= MODE_MF_AFEX;
8873 #if defined(__LITTLE_ENDIAN)
8874 flags |= MODE_LITTLE_ENDIAN;
8875 #else /* __BIG_ENDIAN */
8876 flags |= MODE_BIG_ENDIAN;
8879 INIT_MODE_FLAGS(sc) = flags;
8882 int bnx2x_alloc_hsi_mem(struct bnx2x_softc *sc)
8884 struct bnx2x_fastpath *fp;
8889 /************************/
8890 /* DEFAULT STATUS BLOCK */
8891 /************************/
8893 if (bnx2x_dma_alloc(sc, sizeof(struct host_sp_status_block),
8894 &sc->def_sb_dma, "def_sb",
8895 RTE_CACHE_LINE_SIZE) != 0) {
8900 (struct host_sp_status_block *)sc->def_sb_dma.vaddr;
8905 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8906 &sc->eq_dma, "ev_queue",
8907 RTE_CACHE_LINE_SIZE) != 0) {
8912 sc->eq = (union event_ring_elem *)sc->eq_dma.vaddr;
8918 if (bnx2x_dma_alloc(sc, sizeof(struct bnx2x_slowpath),
8920 RTE_CACHE_LINE_SIZE) != 0) {
8926 sc->sp = (struct bnx2x_slowpath *)sc->sp_dma.vaddr;
8928 /*******************/
8929 /* SLOW PATH QUEUE */
8930 /*******************/
8932 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8933 &sc->spq_dma, "sp_queue",
8934 RTE_CACHE_LINE_SIZE) != 0) {
8941 sc->spq = (struct eth_spe *)sc->spq_dma.vaddr;
8943 /***************************/
8944 /* FW DECOMPRESSION BUFFER */
8945 /***************************/
8947 if (bnx2x_dma_alloc(sc, FW_BUF_SIZE, &sc->gz_buf_dma,
8948 "fw_buf", RTE_CACHE_LINE_SIZE) != 0) {
8956 sc->gz_buf = (void *)sc->gz_buf_dma.vaddr;
8963 /* allocate DMA memory for each fastpath structure */
8964 for (i = 0; i < sc->num_queues; i++) {
8969 /*******************/
8970 /* FP STATUS BLOCK */
8971 /*******************/
8973 snprintf(buf, sizeof(buf), "fp_%d_sb", i);
8974 if (bnx2x_dma_alloc(sc, sizeof(union bnx2x_host_hc_status_block),
8975 &fp->sb_dma, buf, RTE_CACHE_LINE_SIZE) != 0) {
8976 PMD_DRV_LOG(NOTICE, sc, "Failed to alloc %s", buf);
8979 if (CHIP_IS_E2E3(sc)) {
8980 fp->status_block.e2_sb =
8981 (struct host_hc_status_block_e2 *)
8984 fp->status_block.e1x_sb =
8985 (struct host_hc_status_block_e1x *)
8994 void bnx2x_free_hsi_mem(struct bnx2x_softc *sc)
8996 struct bnx2x_fastpath *fp;
8999 for (i = 0; i < sc->num_queues; i++) {
9002 /*******************/
9003 /* FP STATUS BLOCK */
9004 /*******************/
9006 memset(&fp->status_block, 0, sizeof(fp->status_block));
9007 bnx2x_dma_free(&fp->sb_dma);
9011 /***************************/
9012 /* FW DECOMPRESSION BUFFER */
9013 /***************************/
9015 bnx2x_dma_free(&sc->gz_buf_dma);
9018 /*******************/
9019 /* SLOW PATH QUEUE */
9020 /*******************/
9022 bnx2x_dma_free(&sc->spq_dma);
9029 bnx2x_dma_free(&sc->sp_dma);
9036 bnx2x_dma_free(&sc->eq_dma);
9039 /************************/
9040 /* DEFAULT STATUS BLOCK */
9041 /************************/
9043 bnx2x_dma_free(&sc->def_sb_dma);
9049 * Previous driver DMAE transaction may have occurred when pre-boot stage
9050 * ended and boot began. This would invalidate the addresses of the
9051 * transaction, resulting in was-error bit set in the PCI causing all
9052 * hw-to-host PCIe transactions to timeout. If this happened we want to clear
9053 * the interrupt which detected this from the pglueb and the was-done bit
9055 static void bnx2x_prev_interrupted_dmae(struct bnx2x_softc *sc)
9059 if (!CHIP_IS_E1x(sc)) {
9060 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS);
9061 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
9062 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
9068 static int bnx2x_prev_mcp_done(struct bnx2x_softc *sc)
9070 uint32_t rc = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE,
9071 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
9073 PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
9080 static struct bnx2x_prev_list_node *bnx2x_prev_path_get_entry(struct bnx2x_softc *sc)
9082 struct bnx2x_prev_list_node *tmp;
9084 LIST_FOREACH(tmp, &bnx2x_prev_list, node) {
9085 if ((sc->pcie_bus == tmp->bus) &&
9086 (sc->pcie_device == tmp->slot) &&
9087 (SC_PATH(sc) == tmp->path)) {
9095 static uint8_t bnx2x_prev_is_path_marked(struct bnx2x_softc *sc)
9097 struct bnx2x_prev_list_node *tmp;
9100 rte_spinlock_lock(&bnx2x_prev_mtx);
9102 tmp = bnx2x_prev_path_get_entry(sc);
9105 PMD_DRV_LOG(DEBUG, sc,
9106 "Path %d/%d/%d was marked by AER",
9107 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9110 PMD_DRV_LOG(DEBUG, sc,
9111 "Path %d/%d/%d was already cleaned from previous drivers",
9112 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9116 rte_spinlock_unlock(&bnx2x_prev_mtx);
9121 static int bnx2x_prev_mark_path(struct bnx2x_softc *sc, uint8_t after_undi)
9123 struct bnx2x_prev_list_node *tmp;
9125 rte_spinlock_lock(&bnx2x_prev_mtx);
9127 /* Check whether the entry for this path already exists */
9128 tmp = bnx2x_prev_path_get_entry(sc);
9131 PMD_DRV_LOG(DEBUG, sc,
9132 "Re-marking AER in path %d/%d/%d",
9133 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9135 PMD_DRV_LOG(DEBUG, sc,
9136 "Removing AER indication from path %d/%d/%d",
9137 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9141 rte_spinlock_unlock(&bnx2x_prev_mtx);
9145 rte_spinlock_unlock(&bnx2x_prev_mtx);
9147 /* Create an entry for this path and add it */
9148 tmp = rte_malloc("", sizeof(struct bnx2x_prev_list_node),
9149 RTE_CACHE_LINE_SIZE);
9151 PMD_DRV_LOG(NOTICE, sc, "Failed to allocate 'bnx2x_prev_list_node'");
9155 tmp->bus = sc->pcie_bus;
9156 tmp->slot = sc->pcie_device;
9157 tmp->path = SC_PATH(sc);
9159 tmp->undi = after_undi ? (1 << SC_PORT(sc)) : 0;
9161 rte_spinlock_lock(&bnx2x_prev_mtx);
9163 LIST_INSERT_HEAD(&bnx2x_prev_list, tmp, node);
9165 rte_spinlock_unlock(&bnx2x_prev_mtx);
9170 static int bnx2x_do_flr(struct bnx2x_softc *sc)
9174 /* only E2 and onwards support FLR */
9175 if (CHIP_IS_E1x(sc)) {
9176 PMD_DRV_LOG(WARNING, sc, "FLR not supported in E1H");
9180 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9181 if (sc->devinfo.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9182 PMD_DRV_LOG(WARNING, sc,
9183 "FLR not supported by BC_VER: 0x%08x",
9184 sc->devinfo.bc_ver);
9188 /* Wait for Transaction Pending bit clean */
9189 for (i = 0; i < 4; i++) {
9191 DELAY(((1 << (i - 1)) * 100) * 1000);
9194 if (!bnx2x_is_pcie_pending(sc)) {
9199 PMD_DRV_LOG(NOTICE, sc, "PCIE transaction is not cleared, "
9200 "proceeding with reset anyway");
9203 bnx2x_fw_command(sc, DRV_MSG_CODE_INITIATE_FLR, 0);
9208 struct bnx2x_mac_vals {
9216 uint32_t bmac_val[2];
9220 bnx2x_prev_unload_close_mac(struct bnx2x_softc *sc, struct bnx2x_mac_vals *vals)
9222 uint32_t val, base_addr, offset, mask, reset_reg;
9223 uint8_t mac_stopped = FALSE;
9224 uint8_t port = SC_PORT(sc);
9225 uint32_t wb_data[2];
9227 /* reset addresses as they also mark which values were changed */
9228 vals->bmac_addr = 0;
9229 vals->umac_addr = 0;
9230 vals->xmac_addr = 0;
9231 vals->emac_addr = 0;
9233 reset_reg = REG_RD(sc, MISC_REG_RESET_REG_2);
9235 if (!CHIP_IS_E3(sc)) {
9236 val = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9237 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9238 if ((mask & reset_reg) && val) {
9239 base_addr = SC_PORT(sc) ? NIG_REG_INGRESS_BMAC1_MEM
9240 : NIG_REG_INGRESS_BMAC0_MEM;
9241 offset = CHIP_IS_E2(sc) ? BIGMAC2_REGISTER_BMAC_CONTROL
9242 : BIGMAC_REGISTER_BMAC_CONTROL;
9245 * use rd/wr since we cannot use dmae. This is safe
9246 * since MCP won't access the bus due to the request
9247 * to unload, and no function on the path can be
9248 * loaded at this time.
9250 wb_data[0] = REG_RD(sc, base_addr + offset);
9251 wb_data[1] = REG_RD(sc, base_addr + offset + 0x4);
9252 vals->bmac_addr = base_addr + offset;
9253 vals->bmac_val[0] = wb_data[0];
9254 vals->bmac_val[1] = wb_data[1];
9255 wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE;
9256 REG_WR(sc, vals->bmac_addr, wb_data[0]);
9257 REG_WR(sc, vals->bmac_addr + 0x4, wb_data[1]);
9260 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + SC_PORT(sc) * 4;
9261 vals->emac_val = REG_RD(sc, vals->emac_addr);
9262 REG_WR(sc, vals->emac_addr, 0);
9265 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9266 base_addr = SC_PORT(sc) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9267 val = REG_RD(sc, base_addr + XMAC_REG_PFC_CTRL_HI);
9268 REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9270 REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9272 vals->xmac_addr = base_addr + XMAC_REG_CTRL;
9273 vals->xmac_val = REG_RD(sc, vals->xmac_addr);
9274 REG_WR(sc, vals->xmac_addr, 0);
9278 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9279 if (mask & reset_reg) {
9280 base_addr = SC_PORT(sc) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9281 vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
9282 vals->umac_val = REG_RD(sc, vals->umac_addr);
9283 REG_WR(sc, vals->umac_addr, 0);
9293 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9294 #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
9295 #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
9296 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
9299 bnx2x_prev_unload_undi_inc(struct bnx2x_softc *sc, uint8_t port, uint8_t inc)
9302 uint32_t tmp_reg = REG_RD(sc, BNX2X_PREV_UNDI_PROD_ADDR(port));
9304 rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9305 bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9307 tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9308 REG_WR(sc, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9311 static int bnx2x_prev_unload_common(struct bnx2x_softc *sc)
9313 uint32_t reset_reg, tmp_reg = 0, rc;
9314 uint8_t prev_undi = FALSE;
9315 struct bnx2x_mac_vals mac_vals;
9316 uint32_t timer_count = 1000;
9320 * It is possible a previous function received 'common' answer,
9321 * but hasn't loaded yet, therefore creating a scenario of
9322 * multiple functions receiving 'common' on the same path.
9324 memset(&mac_vals, 0, sizeof(mac_vals));
9326 if (bnx2x_prev_is_path_marked(sc)) {
9327 return bnx2x_prev_mcp_done(sc);
9330 reset_reg = REG_RD(sc, MISC_REG_RESET_REG_1);
9332 /* Reset should be performed after BRB is emptied */
9333 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
9334 /* Close the MAC Rx to prevent BRB from filling up */
9335 bnx2x_prev_unload_close_mac(sc, &mac_vals);
9337 /* close LLH filters towards the BRB */
9338 elink_set_rx_filter(&sc->link_params, 0);
9341 * Check if the UNDI driver was previously loaded.
9342 * UNDI driver initializes CID offset for normal bell to 0x7
9344 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
9345 tmp_reg = REG_RD(sc, DORQ_REG_NORM_CID_OFST);
9346 if (tmp_reg == 0x7) {
9347 PMD_DRV_LOG(DEBUG, sc, "UNDI previously loaded");
9349 /* clear the UNDI indication */
9350 REG_WR(sc, DORQ_REG_NORM_CID_OFST, 0);
9351 /* clear possible idle check errors */
9352 REG_RD(sc, NIG_REG_NIG_INT_STS_CLR_0);
9356 /* wait until BRB is empty */
9357 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9358 while (timer_count) {
9361 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9366 PMD_DRV_LOG(DEBUG, sc, "BRB still has 0x%08x", tmp_reg);
9368 /* reset timer as long as BRB actually gets emptied */
9369 if (prev_brb > tmp_reg) {
9375 /* If UNDI resides in memory, manually increment it */
9377 bnx2x_prev_unload_undi_inc(sc, SC_PORT(sc), 1);
9384 PMD_DRV_LOG(NOTICE, sc, "Failed to empty BRB");
9388 /* No packets are in the pipeline, path is ready for reset */
9389 bnx2x_reset_common(sc);
9391 if (mac_vals.xmac_addr) {
9392 REG_WR(sc, mac_vals.xmac_addr, mac_vals.xmac_val);
9394 if (mac_vals.umac_addr) {
9395 REG_WR(sc, mac_vals.umac_addr, mac_vals.umac_val);
9397 if (mac_vals.emac_addr) {
9398 REG_WR(sc, mac_vals.emac_addr, mac_vals.emac_val);
9400 if (mac_vals.bmac_addr) {
9401 REG_WR(sc, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
9402 REG_WR(sc, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
9405 rc = bnx2x_prev_mark_path(sc, prev_undi);
9407 bnx2x_prev_mcp_done(sc);
9411 return bnx2x_prev_mcp_done(sc);
9414 static int bnx2x_prev_unload_uncommon(struct bnx2x_softc *sc)
9418 /* Test if previous unload process was already finished for this path */
9419 if (bnx2x_prev_is_path_marked(sc)) {
9420 return bnx2x_prev_mcp_done(sc);
9424 * If function has FLR capabilities, and existing FW version matches
9425 * the one required, then FLR will be sufficient to clean any residue
9426 * left by previous driver
9428 rc = bnx2x_nic_load_analyze_req(sc, FW_MSG_CODE_DRV_LOAD_FUNCTION);
9430 /* fw version is good */
9431 rc = bnx2x_do_flr(sc);
9435 /* FLR was performed */
9439 PMD_DRV_LOG(INFO, sc, "Could not FLR");
9441 /* Close the MCP request, return failure */
9442 rc = bnx2x_prev_mcp_done(sc);
9444 rc = BNX2X_PREV_WAIT_NEEDED;
9450 static int bnx2x_prev_unload(struct bnx2x_softc *sc)
9452 int time_counter = 10;
9453 uint32_t fw, hw_lock_reg, hw_lock_val;
9456 PMD_INIT_FUNC_TRACE(sc);
9459 * Clear HW from errors which may have resulted from an interrupted
9462 bnx2x_prev_interrupted_dmae(sc);
9464 /* Release previously held locks */
9465 hw_lock_reg = (SC_FUNC(sc) <= 5) ?
9466 (MISC_REG_DRIVER_CONTROL_1 + SC_FUNC(sc) * 8) :
9467 (MISC_REG_DRIVER_CONTROL_7 + (SC_FUNC(sc) - 6) * 8);
9469 hw_lock_val = (REG_RD(sc, hw_lock_reg));
9471 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
9472 PMD_DRV_LOG(DEBUG, sc, "Releasing previously held NVRAM lock\n");
9473 REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
9474 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << SC_PORT(sc)));
9476 PMD_DRV_LOG(DEBUG, sc, "Releasing previously held HW lock\n");
9477 REG_WR(sc, hw_lock_reg, 0xffffffff);
9480 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(sc, MCP_REG_MCPR_ACCESS_LOCK)) {
9481 PMD_DRV_LOG(DEBUG, sc, "Releasing previously held ALR\n");
9482 REG_WR(sc, MCP_REG_MCPR_ACCESS_LOCK, 0);
9486 /* Lock MCP using an unload request */
9487 fw = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
9489 PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
9494 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
9495 rc = bnx2x_prev_unload_common(sc);
9499 /* non-common reply from MCP might require looping */
9500 rc = bnx2x_prev_unload_uncommon(sc);
9501 if (rc != BNX2X_PREV_WAIT_NEEDED) {
9506 } while (--time_counter);
9508 if (!time_counter || rc) {
9509 PMD_DRV_LOG(NOTICE, sc, "Failed to unload previous driver!");
9517 bnx2x_dcbx_set_state(struct bnx2x_softc *sc, uint8_t dcb_on, uint32_t dcbx_enabled)
9519 if (!CHIP_IS_E1x(sc)) {
9520 sc->dcb_state = dcb_on;
9521 sc->dcbx_enabled = dcbx_enabled;
9523 sc->dcb_state = FALSE;
9524 sc->dcbx_enabled = BNX2X_DCBX_ENABLED_INVALID;
9526 PMD_DRV_LOG(DEBUG, sc,
9527 "DCB state [%s:%s]",
9528 dcb_on ? "ON" : "OFF",
9529 (dcbx_enabled == BNX2X_DCBX_ENABLED_OFF) ? "user-mode" :
9531 BNX2X_DCBX_ENABLED_ON_NEG_OFF) ? "on-chip static"
9533 BNX2X_DCBX_ENABLED_ON_NEG_ON) ?
9534 "on-chip with negotiation" : "invalid");
9537 static int bnx2x_set_qm_cid_count(struct bnx2x_softc *sc)
9539 int cid_count = BNX2X_L2_MAX_CID(sc);
9541 if (CNIC_SUPPORT(sc)) {
9542 cid_count += CNIC_CID_MAX;
9545 return roundup(cid_count, QM_CID_ROUND);
9548 static void bnx2x_init_multi_cos(struct bnx2x_softc *sc)
9552 uint32_t pri_map = 0;
9554 for (pri = 0; pri < BNX2X_MAX_PRIORITY; pri++) {
9555 cos = ((pri_map & (0xf << (pri * 4))) >> (pri * 4));
9556 if (cos < sc->max_cos) {
9557 sc->prio_to_cos[pri] = cos;
9559 PMD_DRV_LOG(WARNING, sc,
9560 "Invalid COS %d for priority %d "
9561 "(max COS is %d), setting to 0", cos, pri,
9563 sc->prio_to_cos[pri] = 0;
9568 static int bnx2x_pci_get_caps(struct bnx2x_softc *sc)
9575 struct bnx2x_pci_cap *cap;
9577 cap = sc->pci_caps = rte_zmalloc("caps", sizeof(struct bnx2x_pci_cap),
9578 RTE_CACHE_LINE_SIZE);
9580 PMD_DRV_LOG(NOTICE, sc, "Failed to allocate memory");
9585 pci_read(sc, PCI_STATUS, &status, 2);
9586 if (!(status & PCI_STATUS_CAP_LIST)) {
9588 pci_read(sc, PCIR_STATUS, &status, 2);
9589 if (!(status & PCIM_STATUS_CAPPRESENT)) {
9591 PMD_DRV_LOG(NOTICE, sc, "PCIe capability reading failed");
9596 pci_read(sc, PCI_CAPABILITY_LIST, &pci_cap.next, 1);
9598 pci_read(sc, PCIR_CAP_PTR, &pci_cap.next, 1);
9600 while (pci_cap.next) {
9601 cap->addr = pci_cap.next & ~3;
9602 pci_read(sc, pci_cap.next & ~3, &pci_cap, 2);
9603 if (pci_cap.id == 0xff)
9605 cap->id = pci_cap.id;
9606 cap->type = BNX2X_PCI_CAP;
9607 cap->next = rte_zmalloc("pci_cap",
9608 sizeof(struct bnx2x_pci_cap),
9609 RTE_CACHE_LINE_SIZE);
9611 PMD_DRV_LOG(NOTICE, sc, "Failed to allocate memory");
9620 static void bnx2x_init_rte(struct bnx2x_softc *sc)
9623 sc->max_tx_queues = min(BNX2X_VF_MAX_QUEUES_PER_VF,
9625 sc->max_rx_queues = min(BNX2X_VF_MAX_QUEUES_PER_VF,
9628 sc->max_rx_queues = BNX2X_MAX_RSS_COUNT(sc);
9629 sc->max_tx_queues = sc->max_rx_queues;
9633 #define FW_HEADER_LEN 104
9634 #define FW_NAME_57711 "/lib/firmware/bnx2x/bnx2x-e1h-7.13.11.0.fw"
9635 #define FW_NAME_57810 "/lib/firmware/bnx2x/bnx2x-e2-7.13.11.0.fw"
9637 void bnx2x_load_firmware(struct bnx2x_softc *sc)
9643 fwname = sc->devinfo.device_id == CHIP_NUM_57711
9644 ? FW_NAME_57711 : FW_NAME_57810;
9645 f = open(fwname, O_RDONLY);
9647 PMD_DRV_LOG(NOTICE, sc, "Can't open firmware file");
9651 if (fstat(f, &st) < 0) {
9652 PMD_DRV_LOG(NOTICE, sc, "Can't stat firmware file");
9657 sc->firmware = rte_zmalloc("bnx2x_fw", st.st_size, RTE_CACHE_LINE_SIZE);
9658 if (!sc->firmware) {
9659 PMD_DRV_LOG(NOTICE, sc, "Can't allocate memory for firmware");
9664 if (read(f, sc->firmware, st.st_size) != st.st_size) {
9665 PMD_DRV_LOG(NOTICE, sc, "Can't read firmware data");
9671 sc->fw_len = st.st_size;
9672 if (sc->fw_len < FW_HEADER_LEN) {
9673 PMD_DRV_LOG(NOTICE, sc,
9674 "Invalid fw size: %" PRIu64, sc->fw_len);
9677 PMD_DRV_LOG(DEBUG, sc, "fw_len = %" PRIu64, sc->fw_len);
9681 bnx2x_data_to_init_ops(uint8_t * data, struct raw_op *dst, uint32_t len)
9683 uint32_t *src = (uint32_t *) data;
9686 for (i = 0, j = 0; i < len / 8; ++i, j += 2) {
9687 tmp = rte_be_to_cpu_32(src[j]);
9688 dst[i].op = (tmp >> 24) & 0xFF;
9689 dst[i].offset = tmp & 0xFFFFFF;
9690 dst[i].raw_data = rte_be_to_cpu_32(src[j + 1]);
9695 bnx2x_data_to_init_offsets(uint8_t * data, uint16_t * dst, uint32_t len)
9697 uint16_t *src = (uint16_t *) data;
9700 for (i = 0; i < len / 2; ++i)
9701 dst[i] = rte_be_to_cpu_16(src[i]);
9704 static void bnx2x_data_to_init_data(uint8_t * data, uint32_t * dst, uint32_t len)
9706 uint32_t *src = (uint32_t *) data;
9709 for (i = 0; i < len / 4; ++i)
9710 dst[i] = rte_be_to_cpu_32(src[i]);
9713 static void bnx2x_data_to_iro_array(uint8_t * data, struct iro *dst, uint32_t len)
9715 uint32_t *src = (uint32_t *) data;
9718 for (i = 0, j = 0; i < len / sizeof(struct iro); ++i, ++j) {
9719 dst[i].base = rte_be_to_cpu_32(src[j++]);
9720 tmp = rte_be_to_cpu_32(src[j]);
9721 dst[i].m1 = (tmp >> 16) & 0xFFFF;
9722 dst[i].m2 = tmp & 0xFFFF;
9724 tmp = rte_be_to_cpu_32(src[j]);
9725 dst[i].m3 = (tmp >> 16) & 0xFFFF;
9726 dst[i].size = tmp & 0xFFFF;
9731 * Device attach function.
9733 * Allocates device resources, performs secondary chip identification, and
9734 * initializes driver instance variables. This function is called from driver
9735 * load after a successful probe.
9738 * 0 = Success, >0 = Failure
9740 int bnx2x_attach(struct bnx2x_softc *sc)
9744 PMD_DRV_LOG(DEBUG, sc, "Starting attach...");
9746 rc = bnx2x_pci_get_caps(sc);
9748 PMD_DRV_LOG(NOTICE, sc, "PCIe caps reading was failed");
9752 sc->state = BNX2X_STATE_CLOSED;
9754 pci_write_long(sc, PCICFG_GRC_ADDRESS, PCICFG_VENDOR_ID_OFFSET);
9756 sc->igu_base_addr = IS_VF(sc) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
9758 /* get PCI capabilites */
9759 bnx2x_probe_pci_caps(sc);
9761 if (sc->devinfo.pcie_msix_cap_reg != 0) {
9764 (sc->devinfo.pcie_msix_cap_reg + PCIR_MSIX_CTRL), &val,
9766 sc->igu_sb_cnt = (val & PCIM_MSIXCTRL_TABLE_SIZE) + 1;
9771 /* Init RTE stuff */
9775 /* Enable internal target-read (in case we are probed after PF
9776 * FLR). Must be done prior to any BAR read access. Only for
9779 if (!CHIP_IS_E1x(sc)) {
9780 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ,
9785 /* get device info and set params */
9786 if (bnx2x_get_device_info(sc) != 0) {
9787 PMD_DRV_LOG(NOTICE, sc, "getting device info");
9791 /* get phy settings from shmem and 'and' against admin settings */
9792 bnx2x_get_phy_info(sc);
9794 /* Left mac of VF unfilled, PF should set it for VF */
9795 memset(sc->link_params.mac_addr, 0, RTE_ETHER_ADDR_LEN);
9800 /* set the default MTU (changed via ifconfig) */
9801 sc->mtu = RTE_ETHER_MTU;
9803 bnx2x_set_modes_bitmap(sc);
9805 /* need to reset chip if UNDI was active */
9806 if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
9809 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
9810 DRV_MSG_SEQ_NUMBER_MASK);
9811 PMD_DRV_LOG(DEBUG, sc, "prev unload fw_seq 0x%04x",
9813 bnx2x_prev_unload(sc);
9816 bnx2x_dcbx_set_state(sc, FALSE, BNX2X_DCBX_ENABLED_OFF);
9818 /* calculate qm_cid_count */
9819 sc->qm_cid_count = bnx2x_set_qm_cid_count(sc);
9822 bnx2x_init_multi_cos(sc);
9828 bnx2x_igu_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t segment,
9829 uint16_t index, uint8_t op, uint8_t update)
9831 uint32_t igu_addr = sc->igu_base_addr;
9832 igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
9833 bnx2x_igu_ack_sb_gen(sc, segment, index, op, update, igu_addr);
9837 bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t storm,
9838 uint16_t index, uint8_t op, uint8_t update)
9840 if (unlikely(sc->devinfo.int_block == INT_BLOCK_HC))
9841 bnx2x_hc_ack_sb(sc, igu_sb_id, storm, index, op, update);
9844 if (CHIP_INT_MODE_IS_BC(sc)) {
9846 } else if (igu_sb_id != sc->igu_dsb_id) {
9847 segment = IGU_SEG_ACCESS_DEF;
9848 } else if (storm == ATTENTION_ID) {
9849 segment = IGU_SEG_ACCESS_ATTN;
9851 segment = IGU_SEG_ACCESS_DEF;
9853 bnx2x_igu_ack_sb(sc, igu_sb_id, segment, index, op, update);
9858 bnx2x_igu_clear_sb_gen(struct bnx2x_softc *sc, uint8_t func, uint8_t idu_sb_id,
9861 uint32_t data, ctl, cnt = 100;
9862 uint32_t igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
9863 uint32_t igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
9864 uint32_t igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP +
9865 (idu_sb_id / 32) * 4;
9866 uint32_t sb_bit = 1 << (idu_sb_id % 32);
9867 uint32_t func_encode = func |
9868 (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
9869 uint32_t addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
9871 /* Not supported in BC mode */
9872 if (CHIP_INT_MODE_IS_BC(sc)) {
9876 data = ((IGU_USE_REGISTER_cstorm_type_0_sb_cleanup <<
9877 IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
9878 IGU_REGULAR_CLEANUP_SET | IGU_REGULAR_BCLEANUP);
9880 ctl = ((addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT) |
9881 (func_encode << IGU_CTRL_REG_FID_SHIFT) |
9882 (IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT));
9884 REG_WR(sc, igu_addr_data, data);
9888 PMD_DRV_LOG(DEBUG, sc, "write 0x%08x to IGU(via GRC) addr 0x%x",
9890 REG_WR(sc, igu_addr_ctl, ctl);
9894 /* wait for clean up to finish */
9895 while (!(REG_RD(sc, igu_addr_ack) & sb_bit) && --cnt) {
9899 if (!(REG_RD(sc, igu_addr_ack) & sb_bit)) {
9900 PMD_DRV_LOG(DEBUG, sc,
9901 "Unable to finish IGU cleanup: "
9902 "idu_sb_id %d offset %d bit %d (cnt %d)",
9903 idu_sb_id, idu_sb_id / 32, idu_sb_id % 32, cnt);
9907 static void bnx2x_igu_clear_sb(struct bnx2x_softc *sc, uint8_t idu_sb_id)
9909 bnx2x_igu_clear_sb_gen(sc, SC_FUNC(sc), idu_sb_id, TRUE /*PF*/);
9912 /*******************/
9913 /* ECORE CALLBACKS */
9914 /*******************/
9916 static void bnx2x_reset_common(struct bnx2x_softc *sc)
9918 uint32_t val = 0x1400;
9920 PMD_INIT_FUNC_TRACE(sc);
9923 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR),
9926 if (CHIP_IS_E3(sc)) {
9927 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
9928 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
9931 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR), val);
9934 static void bnx2x_common_init_phy(struct bnx2x_softc *sc)
9936 uint32_t shmem_base[2];
9937 uint32_t shmem2_base[2];
9939 /* Avoid common init in case MFW supports LFA */
9940 if (SHMEM2_RD(sc, size) >
9941 (uint32_t) offsetof(struct shmem2_region,
9942 lfa_host_addr[SC_PORT(sc)])) {
9946 shmem_base[0] = sc->devinfo.shmem_base;
9947 shmem2_base[0] = sc->devinfo.shmem2_base;
9949 if (!CHIP_IS_E1x(sc)) {
9950 shmem_base[1] = SHMEM2_RD(sc, other_shmem_base_addr);
9951 shmem2_base[1] = SHMEM2_RD(sc, other_shmem2_base_addr);
9954 bnx2x_acquire_phy_lock(sc);
9955 elink_common_init_phy(sc, shmem_base, shmem2_base,
9956 sc->devinfo.chip_id, 0);
9957 bnx2x_release_phy_lock(sc);
9960 static void bnx2x_pf_disable(struct bnx2x_softc *sc)
9962 uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
9964 val &= ~IGU_PF_CONF_FUNC_EN;
9966 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
9967 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
9968 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 0);
9971 static void bnx2x_init_pxp(struct bnx2x_softc *sc)
9974 int r_order, w_order;
9976 devctl = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_CTL);
9978 w_order = ((devctl & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5);
9979 r_order = ((devctl & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12);
9981 ecore_init_pxp_arb(sc, r_order, w_order);
9984 static uint32_t bnx2x_get_pretend_reg(struct bnx2x_softc *sc)
9986 uint32_t base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9987 uint32_t stride = (PXP2_REG_PGL_PRETEND_FUNC_F1 - base);
9988 return base + (SC_ABS_FUNC(sc)) * stride;
9992 * Called only on E1H or E2.
9993 * When pretending to be PF, the pretend value is the function number 0..7.
9994 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
9997 static int bnx2x_pretend_func(struct bnx2x_softc *sc, uint16_t pretend_func_val)
9999 uint32_t pretend_reg;
10001 if (CHIP_IS_E1H(sc) && (pretend_func_val > E1H_FUNC_MAX))
10004 /* get my own pretend register */
10005 pretend_reg = bnx2x_get_pretend_reg(sc);
10006 REG_WR(sc, pretend_reg, pretend_func_val);
10007 REG_RD(sc, pretend_reg);
10011 static void bnx2x_setup_fan_failure_detection(struct bnx2x_softc *sc)
10018 val = (SHMEM_RD(sc, dev_info.shared_hw_config.config2) &
10019 SHARED_HW_CFG_FAN_FAILURE_MASK);
10021 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) {
10025 * The fan failure mechanism is usually related to the PHY type since
10026 * the power consumption of the board is affected by the PHY. Currently,
10027 * fan is required for most designs with SFX7101, BNX2X8727 and BNX2X8481.
10029 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) {
10030 for (port = PORT_0; port < PORT_MAX; port++) {
10031 is_required |= elink_fan_failure_det_req(sc,
10033 devinfo.shmem_base,
10035 devinfo.shmem2_base,
10040 if (is_required == 0) {
10044 /* Fan failure is indicated by SPIO 5 */
10045 bnx2x_set_spio(sc, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
10047 /* set to active low mode */
10048 val = REG_RD(sc, MISC_REG_SPIO_INT);
10049 val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
10050 REG_WR(sc, MISC_REG_SPIO_INT, val);
10052 /* enable interrupt to signal the IGU */
10053 val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
10054 val |= MISC_SPIO_SPIO5;
10055 REG_WR(sc, MISC_REG_SPIO_EVENT_EN, val);
10058 static void bnx2x_enable_blocks_attention(struct bnx2x_softc *sc)
10062 REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0);
10063 if (!CHIP_IS_E1x(sc)) {
10064 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0x40);
10066 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0);
10068 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
10069 REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
10071 * mask read length error interrupts in brb for parser
10072 * (parsing unit and 'checksum and crc' unit)
10073 * these errors are legal (PU reads fixed length and CAC can cause
10074 * read length error on truncated packets)
10076 REG_WR(sc, BRB1_REG_BRB1_INT_MASK, 0xFC00);
10077 REG_WR(sc, QM_REG_QM_INT_MASK, 0);
10078 REG_WR(sc, TM_REG_TM_INT_MASK, 0);
10079 REG_WR(sc, XSDM_REG_XSDM_INT_MASK_0, 0);
10080 REG_WR(sc, XSDM_REG_XSDM_INT_MASK_1, 0);
10081 REG_WR(sc, XCM_REG_XCM_INT_MASK, 0);
10082 /* REG_WR(sc, XSEM_REG_XSEM_INT_MASK_0, 0); */
10083 /* REG_WR(sc, XSEM_REG_XSEM_INT_MASK_1, 0); */
10084 REG_WR(sc, USDM_REG_USDM_INT_MASK_0, 0);
10085 REG_WR(sc, USDM_REG_USDM_INT_MASK_1, 0);
10086 REG_WR(sc, UCM_REG_UCM_INT_MASK, 0);
10087 /* REG_WR(sc, USEM_REG_USEM_INT_MASK_0, 0); */
10088 /* REG_WR(sc, USEM_REG_USEM_INT_MASK_1, 0); */
10089 REG_WR(sc, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
10090 REG_WR(sc, CSDM_REG_CSDM_INT_MASK_0, 0);
10091 REG_WR(sc, CSDM_REG_CSDM_INT_MASK_1, 0);
10092 REG_WR(sc, CCM_REG_CCM_INT_MASK, 0);
10093 /* REG_WR(sc, CSEM_REG_CSEM_INT_MASK_0, 0); */
10094 /* REG_WR(sc, CSEM_REG_CSEM_INT_MASK_1, 0); */
10096 val = (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
10097 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
10098 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN);
10099 if (!CHIP_IS_E1x(sc)) {
10100 val |= (PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
10101 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED);
10103 REG_WR(sc, PXP2_REG_PXP2_INT_MASK_0, val);
10105 REG_WR(sc, TSDM_REG_TSDM_INT_MASK_0, 0);
10106 REG_WR(sc, TSDM_REG_TSDM_INT_MASK_1, 0);
10107 REG_WR(sc, TCM_REG_TCM_INT_MASK, 0);
10108 /* REG_WR(sc, TSEM_REG_TSEM_INT_MASK_0, 0); */
10110 if (!CHIP_IS_E1x(sc)) {
10111 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
10112 REG_WR(sc, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
10115 REG_WR(sc, CDU_REG_CDU_INT_MASK, 0);
10116 REG_WR(sc, DMAE_REG_DMAE_INT_MASK, 0);
10117 /* REG_WR(sc, MISC_REG_MISC_INT_MASK, 0); */
10118 REG_WR(sc, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
10122 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
10124 * @sc: driver handle
10126 static int bnx2x_init_hw_common(struct bnx2x_softc *sc)
10128 uint8_t abs_func_id;
10131 PMD_DRV_LOG(DEBUG, sc,
10132 "starting common init for func %d", SC_ABS_FUNC(sc));
10135 * take the RESET lock to protect undi_unload flow from accessing
10136 * registers while we are resetting the chip
10138 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10140 bnx2x_reset_common(sc);
10142 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET), 0xffffffff);
10145 if (CHIP_IS_E3(sc)) {
10146 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
10147 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
10150 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET), val);
10152 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10154 ecore_init_block(sc, BLOCK_MISC, PHASE_COMMON);
10156 if (!CHIP_IS_E1x(sc)) {
10158 * 4-port mode or 2-port mode we need to turn off master-enable for
10159 * everyone. After that we turn it back on for self. So, we disregard
10160 * multi-function, and always disable all functions on the given path,
10161 * this means 0,2,4,6 for path 0 and 1,3,5,7 for path 1
10163 for (abs_func_id = SC_PATH(sc);
10164 abs_func_id < (E2_FUNC_MAX * 2); abs_func_id += 2) {
10165 if (abs_func_id == SC_ABS_FUNC(sc)) {
10167 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
10172 bnx2x_pretend_func(sc, abs_func_id);
10174 /* clear pf enable */
10175 bnx2x_pf_disable(sc);
10177 bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10181 ecore_init_block(sc, BLOCK_PXP, PHASE_COMMON);
10183 ecore_init_block(sc, BLOCK_PXP2, PHASE_COMMON);
10184 bnx2x_init_pxp(sc);
10186 #ifdef __BIG_ENDIAN
10187 REG_WR(sc, PXP2_REG_RQ_QM_ENDIAN_M, 1);
10188 REG_WR(sc, PXP2_REG_RQ_TM_ENDIAN_M, 1);
10189 REG_WR(sc, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
10190 REG_WR(sc, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
10191 REG_WR(sc, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
10192 /* make sure this value is 0 */
10193 REG_WR(sc, PXP2_REG_RQ_HC_ENDIAN_M, 0);
10195 //REG_WR(sc, PXP2_REG_RD_PBF_SWAP_MODE, 1);
10196 REG_WR(sc, PXP2_REG_RD_QM_SWAP_MODE, 1);
10197 REG_WR(sc, PXP2_REG_RD_TM_SWAP_MODE, 1);
10198 REG_WR(sc, PXP2_REG_RD_SRC_SWAP_MODE, 1);
10199 REG_WR(sc, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
10202 ecore_ilt_init_page_size(sc, INITOP_SET);
10204 if (CHIP_REV_IS_FPGA(sc) && CHIP_IS_E1H(sc)) {
10205 REG_WR(sc, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
10208 /* let the HW do it's magic... */
10211 /* finish PXP init */
10213 val = REG_RD(sc, PXP2_REG_RQ_CFG_DONE);
10215 PMD_DRV_LOG(NOTICE, sc, "PXP2 CFG failed");
10218 val = REG_RD(sc, PXP2_REG_RD_INIT_DONE);
10220 PMD_DRV_LOG(NOTICE, sc, "PXP2 RD_INIT failed");
10225 * Timer bug workaround for E2 only. We need to set the entire ILT to have
10226 * entries with value "0" and valid bit on. This needs to be done by the
10227 * first PF that is loaded in a path (i.e. common phase)
10229 if (!CHIP_IS_E1x(sc)) {
10231 * In E2 there is a bug in the timers block that can cause function 6 / 7
10232 * (i.e. vnic3) to start even if it is marked as "scan-off".
10233 * This occurs when a different function (func2,3) is being marked
10234 * as "scan-off". Real-life scenario for example: if a driver is being
10235 * load-unloaded while func6,7 are down. This will cause the timer to access
10236 * the ilt, translate to a logical address and send a request to read/write.
10237 * Since the ilt for the function that is down is not valid, this will cause
10238 * a translation error which is unrecoverable.
10239 * The Workaround is intended to make sure that when this happens nothing
10240 * fatal will occur. The workaround:
10241 * 1. First PF driver which loads on a path will:
10242 * a. After taking the chip out of reset, by using pretend,
10243 * it will write "0" to the following registers of
10245 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10246 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
10247 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
10248 * And for itself it will write '1' to
10249 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
10250 * dmae-operations (writing to pram for example.)
10251 * note: can be done for only function 6,7 but cleaner this
10253 * b. Write zero+valid to the entire ILT.
10254 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
10255 * VNIC3 (of that port). The range allocated will be the
10256 * entire ILT. This is needed to prevent ILT range error.
10257 * 2. Any PF driver load flow:
10258 * a. ILT update with the physical addresses of the allocated
10260 * b. Wait 20msec. - note that this timeout is needed to make
10261 * sure there are no requests in one of the PXP internal
10262 * queues with "old" ILT addresses.
10263 * c. PF enable in the PGLC.
10264 * d. Clear the was_error of the PF in the PGLC. (could have
10265 * occurred while driver was down)
10266 * e. PF enable in the CFC (WEAK + STRONG)
10267 * f. Timers scan enable
10268 * 3. PF driver unload flow:
10269 * a. Clear the Timers scan_en.
10270 * b. Polling for scan_on=0 for that PF.
10271 * c. Clear the PF enable bit in the PXP.
10272 * d. Clear the PF enable in the CFC (WEAK + STRONG)
10273 * e. Write zero+valid to all ILT entries (The valid bit must
10275 * f. If this is VNIC 3 of a port then also init
10276 * first_timers_ilt_entry to zero and last_timers_ilt_entry
10277 * to the last enrty in the ILT.
10280 * Currently the PF error in the PGLC is non recoverable.
10281 * In the future the there will be a recovery routine for this error.
10282 * Currently attention is masked.
10283 * Having an MCP lock on the load/unload process does not guarantee that
10284 * there is no Timer disable during Func6/7 enable. This is because the
10285 * Timers scan is currently being cleared by the MCP on FLR.
10286 * Step 2.d can be done only for PF6/7 and the driver can also check if
10287 * there is error before clearing it. But the flow above is simpler and
10289 * All ILT entries are written by zero+valid and not just PF6/7
10290 * ILT entries since in the future the ILT entries allocation for
10291 * PF-s might be dynamic.
10293 struct ilt_client_info ilt_cli;
10294 struct ecore_ilt ilt;
10296 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
10297 memset(&ilt, 0, sizeof(struct ecore_ilt));
10299 /* initialize dummy TM client */
10301 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
10302 ilt_cli.client_num = ILT_CLIENT_TM;
10305 * Step 1: set zeroes to all ilt page entries with valid bit on
10306 * Step 2: set the timers first/last ilt entry to point
10307 * to the entire range to prevent ILT range error for 3rd/4th
10308 * vnic (this code assumes existence of the vnic)
10310 * both steps performed by call to ecore_ilt_client_init_op()
10311 * with dummy TM client
10313 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
10314 * and his brother are split registers
10317 bnx2x_pretend_func(sc, (SC_PATH(sc) + 6));
10318 ecore_ilt_client_init_op_ilt(sc, &ilt, &ilt_cli, INITOP_CLEAR);
10319 bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10321 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
10322 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
10323 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
10326 REG_WR(sc, PXP2_REG_RQ_DISABLE_INPUTS, 0);
10327 REG_WR(sc, PXP2_REG_RD_DISABLE_INPUTS, 0);
10329 if (!CHIP_IS_E1x(sc)) {
10332 ecore_init_block(sc, BLOCK_PGLUE_B, PHASE_COMMON);
10333 ecore_init_block(sc, BLOCK_ATC, PHASE_COMMON);
10335 /* let the HW do it's magic... */
10338 val = REG_RD(sc, ATC_REG_ATC_INIT_DONE);
10339 } while (factor-- && (val != 1));
10342 PMD_DRV_LOG(NOTICE, sc, "ATC_INIT failed");
10347 ecore_init_block(sc, BLOCK_DMAE, PHASE_COMMON);
10349 /* clean the DMAE memory */
10350 sc->dmae_ready = 1;
10351 ecore_init_fill(sc, TSEM_REG_PRAM, 0, 8, 1);
10353 ecore_init_block(sc, BLOCK_TCM, PHASE_COMMON);
10355 ecore_init_block(sc, BLOCK_UCM, PHASE_COMMON);
10357 ecore_init_block(sc, BLOCK_CCM, PHASE_COMMON);
10359 ecore_init_block(sc, BLOCK_XCM, PHASE_COMMON);
10361 bnx2x_read_dmae(sc, XSEM_REG_PASSIVE_BUFFER, 3);
10362 bnx2x_read_dmae(sc, CSEM_REG_PASSIVE_BUFFER, 3);
10363 bnx2x_read_dmae(sc, TSEM_REG_PASSIVE_BUFFER, 3);
10364 bnx2x_read_dmae(sc, USEM_REG_PASSIVE_BUFFER, 3);
10366 ecore_init_block(sc, BLOCK_QM, PHASE_COMMON);
10368 /* QM queues pointers table */
10369 ecore_qm_init_ptr_table(sc, sc->qm_cid_count, INITOP_SET);
10371 /* soft reset pulse */
10372 REG_WR(sc, QM_REG_SOFT_RESET, 1);
10373 REG_WR(sc, QM_REG_SOFT_RESET, 0);
10375 if (CNIC_SUPPORT(sc))
10376 ecore_init_block(sc, BLOCK_TM, PHASE_COMMON);
10378 ecore_init_block(sc, BLOCK_DORQ, PHASE_COMMON);
10380 if (!CHIP_REV_IS_SLOW(sc)) {
10381 /* enable hw interrupt from doorbell Q */
10382 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
10385 ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON);
10387 ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON);
10388 REG_WR(sc, PRS_REG_A_PRSU_20, 0xf);
10389 REG_WR(sc, PRS_REG_E1HOV_MODE, sc->devinfo.mf_info.path_has_ovlan);
10391 if (!CHIP_IS_E1x(sc) && !CHIP_IS_E3B0(sc)) {
10392 if (IS_MF_AFEX(sc)) {
10394 * configure that AFEX and VLAN headers must be
10395 * received in AFEX mode
10397 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC, 0xE);
10398 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS, 0xA);
10399 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
10400 REG_WR(sc, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
10401 REG_WR(sc, PRS_REG_TAG_LEN_0, 0x4);
10404 * Bit-map indicating which L2 hdrs may appear
10405 * after the basic Ethernet header
10407 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC,
10408 sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10412 ecore_init_block(sc, BLOCK_TSDM, PHASE_COMMON);
10413 ecore_init_block(sc, BLOCK_CSDM, PHASE_COMMON);
10414 ecore_init_block(sc, BLOCK_USDM, PHASE_COMMON);
10415 ecore_init_block(sc, BLOCK_XSDM, PHASE_COMMON);
10417 if (!CHIP_IS_E1x(sc)) {
10418 /* reset VFC memories */
10419 REG_WR(sc, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10420 VFC_MEMORIES_RST_REG_CAM_RST |
10421 VFC_MEMORIES_RST_REG_RAM_RST);
10422 REG_WR(sc, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10423 VFC_MEMORIES_RST_REG_CAM_RST |
10424 VFC_MEMORIES_RST_REG_RAM_RST);
10429 ecore_init_block(sc, BLOCK_TSEM, PHASE_COMMON);
10430 ecore_init_block(sc, BLOCK_USEM, PHASE_COMMON);
10431 ecore_init_block(sc, BLOCK_CSEM, PHASE_COMMON);
10432 ecore_init_block(sc, BLOCK_XSEM, PHASE_COMMON);
10434 /* sync semi rtc */
10435 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x80000000);
10436 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x80000000);
10438 ecore_init_block(sc, BLOCK_UPB, PHASE_COMMON);
10439 ecore_init_block(sc, BLOCK_XPB, PHASE_COMMON);
10440 ecore_init_block(sc, BLOCK_PBF, PHASE_COMMON);
10442 if (!CHIP_IS_E1x(sc)) {
10443 if (IS_MF_AFEX(sc)) {
10445 * configure that AFEX and VLAN headers must be
10446 * sent in AFEX mode
10448 REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC, 0xE);
10449 REG_WR(sc, PBF_REG_MUST_HAVE_HDRS, 0xA);
10450 REG_WR(sc, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
10451 REG_WR(sc, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
10452 REG_WR(sc, PBF_REG_TAG_LEN_0, 0x4);
10454 REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC,
10455 sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10459 REG_WR(sc, SRC_REG_SOFT_RST, 1);
10461 ecore_init_block(sc, BLOCK_SRC, PHASE_COMMON);
10463 if (CNIC_SUPPORT(sc)) {
10464 REG_WR(sc, SRC_REG_KEYSEARCH_0, 0x63285672);
10465 REG_WR(sc, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
10466 REG_WR(sc, SRC_REG_KEYSEARCH_2, 0x223aef9b);
10467 REG_WR(sc, SRC_REG_KEYSEARCH_3, 0x26001e3a);
10468 REG_WR(sc, SRC_REG_KEYSEARCH_4, 0x7ae91116);
10469 REG_WR(sc, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
10470 REG_WR(sc, SRC_REG_KEYSEARCH_6, 0x298d8adf);
10471 REG_WR(sc, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
10472 REG_WR(sc, SRC_REG_KEYSEARCH_8, 0x1830f82f);
10473 REG_WR(sc, SRC_REG_KEYSEARCH_9, 0x01e46be7);
10475 REG_WR(sc, SRC_REG_SOFT_RST, 0);
10477 if (sizeof(union cdu_context) != 1024) {
10478 /* we currently assume that a context is 1024 bytes */
10479 PMD_DRV_LOG(NOTICE, sc,
10480 "please adjust the size of cdu_context(%ld)",
10481 (long)sizeof(union cdu_context));
10484 ecore_init_block(sc, BLOCK_CDU, PHASE_COMMON);
10485 val = (4 << 24) + (0 << 12) + 1024;
10486 REG_WR(sc, CDU_REG_CDU_GLOBAL_PARAMS, val);
10488 ecore_init_block(sc, BLOCK_CFC, PHASE_COMMON);
10490 REG_WR(sc, CFC_REG_INIT_REG, 0x7FF);
10491 /* enable context validation interrupt from CFC */
10492 REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
10494 /* set the thresholds to prevent CFC/CDU race */
10495 REG_WR(sc, CFC_REG_DEBUG0, 0x20020000);
10496 ecore_init_block(sc, BLOCK_HC, PHASE_COMMON);
10498 if (!CHIP_IS_E1x(sc) && BNX2X_NOMCP(sc)) {
10499 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x36);
10502 ecore_init_block(sc, BLOCK_IGU, PHASE_COMMON);
10503 ecore_init_block(sc, BLOCK_MISC_AEU, PHASE_COMMON);
10505 /* Reset PCIE errors for debug */
10506 REG_WR(sc, 0x2814, 0xffffffff);
10507 REG_WR(sc, 0x3820, 0xffffffff);
10509 if (!CHIP_IS_E1x(sc)) {
10510 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
10511 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
10512 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
10513 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
10514 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
10515 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
10516 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
10517 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
10518 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
10519 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
10520 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
10523 ecore_init_block(sc, BLOCK_NIG, PHASE_COMMON);
10525 /* in E3 this done in per-port section */
10526 if (!CHIP_IS_E3(sc))
10527 REG_WR(sc, NIG_REG_LLH_MF_MODE, IS_MF(sc));
10529 if (CHIP_IS_E1H(sc)) {
10530 /* not applicable for E2 (and above ...) */
10531 REG_WR(sc, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(sc));
10534 if (CHIP_REV_IS_SLOW(sc)) {
10538 /* finish CFC init */
10539 val = reg_poll(sc, CFC_REG_LL_INIT_DONE, 1, 100, 10);
10541 PMD_DRV_LOG(NOTICE, sc, "CFC LL_INIT failed");
10544 val = reg_poll(sc, CFC_REG_AC_INIT_DONE, 1, 100, 10);
10546 PMD_DRV_LOG(NOTICE, sc, "CFC AC_INIT failed");
10549 val = reg_poll(sc, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
10551 PMD_DRV_LOG(NOTICE, sc, "CFC CAM_INIT failed");
10554 REG_WR(sc, CFC_REG_DEBUG0, 0);
10556 bnx2x_setup_fan_failure_detection(sc);
10558 /* clear PXP2 attentions */
10559 REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
10561 bnx2x_enable_blocks_attention(sc);
10563 if (!CHIP_REV_IS_SLOW(sc)) {
10564 ecore_enable_blocks_parity(sc);
10567 if (!BNX2X_NOMCP(sc)) {
10568 if (CHIP_IS_E1x(sc)) {
10569 bnx2x_common_init_phy(sc);
10577 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
10579 * @sc: driver handle
10581 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc)
10583 int rc = bnx2x_init_hw_common(sc);
10589 /* In E2 2-PORT mode, same ext phy is used for the two paths */
10590 if (!BNX2X_NOMCP(sc)) {
10591 bnx2x_common_init_phy(sc);
10597 static int bnx2x_init_hw_port(struct bnx2x_softc *sc)
10599 int port = SC_PORT(sc);
10600 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
10601 uint32_t low, high;
10604 PMD_DRV_LOG(DEBUG, sc, "starting port init for port %d", port);
10606 REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
10608 ecore_init_block(sc, BLOCK_MISC, init_phase);
10609 ecore_init_block(sc, BLOCK_PXP, init_phase);
10610 ecore_init_block(sc, BLOCK_PXP2, init_phase);
10613 * Timers bug workaround: disables the pf_master bit in pglue at
10614 * common phase, we need to enable it here before any dmae access are
10615 * attempted. Therefore we manually added the enable-master to the
10616 * port phase (it also happens in the function phase)
10618 if (!CHIP_IS_E1x(sc)) {
10619 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
10622 ecore_init_block(sc, BLOCK_ATC, init_phase);
10623 ecore_init_block(sc, BLOCK_DMAE, init_phase);
10624 ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
10625 ecore_init_block(sc, BLOCK_QM, init_phase);
10627 ecore_init_block(sc, BLOCK_TCM, init_phase);
10628 ecore_init_block(sc, BLOCK_UCM, init_phase);
10629 ecore_init_block(sc, BLOCK_CCM, init_phase);
10630 ecore_init_block(sc, BLOCK_XCM, init_phase);
10632 /* QM cid (connection) count */
10633 ecore_qm_init_cid_count(sc, sc->qm_cid_count, INITOP_SET);
10635 if (CNIC_SUPPORT(sc)) {
10636 ecore_init_block(sc, BLOCK_TM, init_phase);
10637 REG_WR(sc, TM_REG_LIN0_SCAN_TIME + port * 4, 20);
10638 REG_WR(sc, TM_REG_LIN0_MAX_ACTIVE_CID + port * 4, 31);
10641 ecore_init_block(sc, BLOCK_DORQ, init_phase);
10643 ecore_init_block(sc, BLOCK_BRB1, init_phase);
10645 if (CHIP_IS_E1H(sc)) {
10647 low = (BNX2X_ONE_PORT(sc) ? 160 : 246);
10648 } else if (sc->mtu > 4096) {
10649 if (BNX2X_ONE_PORT(sc)) {
10653 /* (24*1024 + val*4)/256 */
10654 low = (96 + (val / 64) + ((val % 64) ? 1 : 0));
10657 low = (BNX2X_ONE_PORT(sc) ? 80 : 160);
10659 high = (low + 56); /* 14*1024/256 */
10660 REG_WR(sc, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port * 4, low);
10661 REG_WR(sc, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port * 4, high);
10664 if (CHIP_IS_MODE_4_PORT(sc)) {
10665 REG_WR(sc, SC_PORT(sc) ?
10666 BRB1_REG_MAC_GUARANTIED_1 :
10667 BRB1_REG_MAC_GUARANTIED_0, 40);
10670 ecore_init_block(sc, BLOCK_PRS, init_phase);
10671 if (CHIP_IS_E3B0(sc)) {
10672 if (IS_MF_AFEX(sc)) {
10673 /* configure headers for AFEX mode */
10675 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_1,
10677 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_1,
10679 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_1, 0xA);
10681 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10683 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_0,
10685 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
10688 /* Ovlan exists only if we are in multi-function +
10689 * switch-dependent mode, in switch-independent there
10690 * is no ovlan headers
10692 REG_WR(sc, SC_PORT(sc) ?
10693 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
10694 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10695 (sc->devinfo.mf_info.path_has_ovlan ? 7 : 6));
10699 ecore_init_block(sc, BLOCK_TSDM, init_phase);
10700 ecore_init_block(sc, BLOCK_CSDM, init_phase);
10701 ecore_init_block(sc, BLOCK_USDM, init_phase);
10702 ecore_init_block(sc, BLOCK_XSDM, init_phase);
10704 ecore_init_block(sc, BLOCK_TSEM, init_phase);
10705 ecore_init_block(sc, BLOCK_USEM, init_phase);
10706 ecore_init_block(sc, BLOCK_CSEM, init_phase);
10707 ecore_init_block(sc, BLOCK_XSEM, init_phase);
10709 ecore_init_block(sc, BLOCK_UPB, init_phase);
10710 ecore_init_block(sc, BLOCK_XPB, init_phase);
10712 ecore_init_block(sc, BLOCK_PBF, init_phase);
10714 if (CHIP_IS_E1x(sc)) {
10715 /* configure PBF to work without PAUSE mtu 9000 */
10716 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 0);
10718 /* update threshold */
10719 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, (9040 / 16));
10720 /* update init credit */
10721 REG_WR(sc, PBF_REG_P0_INIT_CRD + port * 4,
10722 (9040 / 16) + 553 - 22);
10724 /* probe changes */
10725 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 1);
10727 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0);
10730 if (CNIC_SUPPORT(sc)) {
10731 ecore_init_block(sc, BLOCK_SRC, init_phase);
10734 ecore_init_block(sc, BLOCK_CDU, init_phase);
10735 ecore_init_block(sc, BLOCK_CFC, init_phase);
10736 ecore_init_block(sc, BLOCK_HC, init_phase);
10737 ecore_init_block(sc, BLOCK_IGU, init_phase);
10738 ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
10739 /* init aeu_mask_attn_func_0/1:
10740 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
10741 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
10742 * bits 4-7 are used for "per vn group attention" */
10743 val = IS_MF(sc) ? 0xF7 : 0x7;
10745 REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, val);
10747 ecore_init_block(sc, BLOCK_NIG, init_phase);
10749 if (!CHIP_IS_E1x(sc)) {
10750 /* Bit-map indicating which L2 hdrs may appear after the
10751 * basic Ethernet header
10753 if (IS_MF_AFEX(sc)) {
10754 REG_WR(sc, SC_PORT(sc) ?
10755 NIG_REG_P1_HDRS_AFTER_BASIC :
10756 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
10758 REG_WR(sc, SC_PORT(sc) ?
10759 NIG_REG_P1_HDRS_AFTER_BASIC :
10760 NIG_REG_P0_HDRS_AFTER_BASIC,
10761 IS_MF_SD(sc) ? 7 : 6);
10764 if (CHIP_IS_E3(sc)) {
10765 REG_WR(sc, SC_PORT(sc) ?
10766 NIG_REG_LLH1_MF_MODE :
10767 NIG_REG_LLH_MF_MODE, IS_MF(sc));
10770 if (!CHIP_IS_E3(sc)) {
10771 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1);
10774 /* 0x2 disable mf_ov, 0x1 enable */
10775 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port * 4,
10776 (IS_MF_SD(sc) ? 0x1 : 0x2));
10778 if (!CHIP_IS_E1x(sc)) {
10780 switch (sc->devinfo.mf_info.mf_mode) {
10781 case MULTI_FUNCTION_SD:
10784 case MULTI_FUNCTION_SI:
10785 case MULTI_FUNCTION_AFEX:
10790 REG_WR(sc, (SC_PORT(sc) ? NIG_REG_LLH1_CLS_TYPE :
10791 NIG_REG_LLH0_CLS_TYPE), val);
10793 REG_WR(sc, NIG_REG_LLFC_ENABLE_0 + port * 4, 0);
10794 REG_WR(sc, NIG_REG_LLFC_OUT_EN_0 + port * 4, 0);
10795 REG_WR(sc, NIG_REG_PAUSE_ENABLE_0 + port * 4, 1);
10797 /* If SPIO5 is set to generate interrupts, enable it for this port */
10798 val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
10799 if (val & MISC_SPIO_SPIO5) {
10800 uint32_t reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
10801 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
10802 val = REG_RD(sc, reg_addr);
10803 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
10804 REG_WR(sc, reg_addr, val);
10811 bnx2x_flr_clnup_reg_poll(struct bnx2x_softc *sc, uint32_t reg,
10812 uint32_t expected, uint32_t poll_count)
10814 uint32_t cur_cnt = poll_count;
10817 while ((val = REG_RD(sc, reg)) != expected && cur_cnt--) {
10818 DELAY(FLR_WAIT_INTERVAL);
10825 bnx2x_flr_clnup_poll_hw_counter(struct bnx2x_softc *sc, uint32_t reg,
10826 __rte_unused const char *msg, uint32_t poll_cnt)
10828 uint32_t val = bnx2x_flr_clnup_reg_poll(sc, reg, 0, poll_cnt);
10831 PMD_DRV_LOG(NOTICE, sc, "%s usage count=%d", msg, val);
10838 /* Common routines with VF FLR cleanup */
10839 static uint32_t bnx2x_flr_clnup_poll_count(struct bnx2x_softc *sc)
10841 /* adjust polling timeout */
10842 if (CHIP_REV_IS_EMUL(sc)) {
10843 return FLR_POLL_CNT * 2000;
10846 if (CHIP_REV_IS_FPGA(sc)) {
10847 return FLR_POLL_CNT * 120;
10850 return FLR_POLL_CNT;
10853 static int bnx2x_poll_hw_usage_counters(struct bnx2x_softc *sc, uint32_t poll_cnt)
10855 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
10856 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10857 CFC_REG_NUM_LCIDS_INSIDE_PF,
10858 "CFC PF usage counter timed out",
10863 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
10864 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10865 DORQ_REG_PF_USAGE_CNT,
10866 "DQ PF usage counter timed out",
10871 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
10872 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10873 QM_REG_PF_USG_CNT_0 + 4 * SC_FUNC(sc),
10874 "QM PF usage counter timed out",
10879 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
10880 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10881 TM_REG_LIN0_VNIC_UC + 4 * SC_PORT(sc),
10882 "Timers VNIC usage counter timed out",
10887 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10888 TM_REG_LIN0_NUM_SCANS +
10890 "Timers NUM_SCANS usage counter timed out",
10895 /* Wait DMAE PF usage counter to zero */
10896 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10897 dmae_reg_go_c[INIT_DMAE_C(sc)],
10898 "DMAE dommand register timed out",
10906 #define OP_GEN_PARAM(param) \
10907 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
10908 #define OP_GEN_TYPE(type) \
10909 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
10910 #define OP_GEN_AGG_VECT(index) \
10911 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
10914 bnx2x_send_final_clnup(struct bnx2x_softc *sc, uint8_t clnup_func,
10917 uint32_t op_gen_command = 0;
10918 uint32_t comp_addr = (BAR_CSTRORM_INTMEM +
10919 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func));
10922 if (REG_RD(sc, comp_addr)) {
10923 PMD_DRV_LOG(NOTICE, sc,
10924 "Cleanup complete was not 0 before sending");
10928 op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
10929 op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
10930 op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
10931 op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
10933 REG_WR(sc, XSDM_REG_OPERATION_GEN, op_gen_command);
10935 if (bnx2x_flr_clnup_reg_poll(sc, comp_addr, 1, poll_cnt) != 1) {
10936 PMD_DRV_LOG(NOTICE, sc, "FW final cleanup did not succeed");
10937 PMD_DRV_LOG(DEBUG, sc, "At timeout completion address contained %x",
10938 (REG_RD(sc, comp_addr)));
10939 rte_panic("FLR cleanup failed");
10943 /* Zero completion for nxt FLR */
10944 REG_WR(sc, comp_addr, 0);
10950 bnx2x_pbf_pN_buf_flushed(struct bnx2x_softc *sc, struct pbf_pN_buf_regs *regs,
10951 uint32_t poll_count)
10953 uint32_t init_crd, crd, crd_start, crd_freed, crd_freed_start;
10954 uint32_t cur_cnt = poll_count;
10956 crd_freed = crd_freed_start = REG_RD(sc, regs->crd_freed);
10957 crd = crd_start = REG_RD(sc, regs->crd);
10958 init_crd = REG_RD(sc, regs->init_crd);
10960 while ((crd != init_crd) &&
10961 ((uint32_t) ((int32_t) crd_freed - (int32_t) crd_freed_start) <
10962 (init_crd - crd_start))) {
10964 DELAY(FLR_WAIT_INTERVAL);
10965 crd = REG_RD(sc, regs->crd);
10966 crd_freed = REG_RD(sc, regs->crd_freed);
10974 bnx2x_pbf_pN_cmd_flushed(struct bnx2x_softc *sc, struct pbf_pN_cmd_regs *regs,
10975 uint32_t poll_count)
10977 uint32_t occup, to_free, freed, freed_start;
10978 uint32_t cur_cnt = poll_count;
10980 occup = to_free = REG_RD(sc, regs->lines_occup);
10981 freed = freed_start = REG_RD(sc, regs->lines_freed);
10984 ((uint32_t) ((int32_t) freed - (int32_t) freed_start) <
10987 DELAY(FLR_WAIT_INTERVAL);
10988 occup = REG_RD(sc, regs->lines_occup);
10989 freed = REG_RD(sc, regs->lines_freed);
10996 static void bnx2x_tx_hw_flushed(struct bnx2x_softc *sc, uint32_t poll_count)
10998 struct pbf_pN_cmd_regs cmd_regs[] = {
10999 {0, (CHIP_IS_E3B0(sc)) ?
11000 PBF_REG_TQ_OCCUPANCY_Q0 : PBF_REG_P0_TQ_OCCUPANCY,
11001 (CHIP_IS_E3B0(sc)) ?
11002 PBF_REG_TQ_LINES_FREED_CNT_Q0 : PBF_REG_P0_TQ_LINES_FREED_CNT},
11003 {1, (CHIP_IS_E3B0(sc)) ?
11004 PBF_REG_TQ_OCCUPANCY_Q1 : PBF_REG_P1_TQ_OCCUPANCY,
11005 (CHIP_IS_E3B0(sc)) ?
11006 PBF_REG_TQ_LINES_FREED_CNT_Q1 : PBF_REG_P1_TQ_LINES_FREED_CNT},
11007 {4, (CHIP_IS_E3B0(sc)) ?
11008 PBF_REG_TQ_OCCUPANCY_LB_Q : PBF_REG_P4_TQ_OCCUPANCY,
11009 (CHIP_IS_E3B0(sc)) ?
11010 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
11011 PBF_REG_P4_TQ_LINES_FREED_CNT}
11014 struct pbf_pN_buf_regs buf_regs[] = {
11015 {0, (CHIP_IS_E3B0(sc)) ?
11016 PBF_REG_INIT_CRD_Q0 : PBF_REG_P0_INIT_CRD,
11017 (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q0 : PBF_REG_P0_CREDIT,
11018 (CHIP_IS_E3B0(sc)) ?
11019 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
11020 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
11021 {1, (CHIP_IS_E3B0(sc)) ?
11022 PBF_REG_INIT_CRD_Q1 : PBF_REG_P1_INIT_CRD,
11023 (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q1 : PBF_REG_P1_CREDIT,
11024 (CHIP_IS_E3B0(sc)) ?
11025 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
11026 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
11027 {4, (CHIP_IS_E3B0(sc)) ?
11028 PBF_REG_INIT_CRD_LB_Q : PBF_REG_P4_INIT_CRD,
11029 (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_LB_Q : PBF_REG_P4_CREDIT,
11030 (CHIP_IS_E3B0(sc)) ?
11031 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
11032 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
11037 /* Verify the command queues are flushed P0, P1, P4 */
11038 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) {
11039 bnx2x_pbf_pN_cmd_flushed(sc, &cmd_regs[i], poll_count);
11042 /* Verify the transmission buffers are flushed P0, P1, P4 */
11043 for (i = 0; i < ARRAY_SIZE(buf_regs); i++) {
11044 bnx2x_pbf_pN_buf_flushed(sc, &buf_regs[i], poll_count);
11048 static void bnx2x_hw_enable_status(struct bnx2x_softc *sc)
11050 __rte_unused uint32_t val;
11052 val = REG_RD(sc, CFC_REG_WEAK_ENABLE_PF);
11053 PMD_DRV_LOG(DEBUG, sc, "CFC_REG_WEAK_ENABLE_PF is 0x%x", val);
11055 val = REG_RD(sc, PBF_REG_DISABLE_PF);
11056 PMD_DRV_LOG(DEBUG, sc, "PBF_REG_DISABLE_PF is 0x%x", val);
11058 val = REG_RD(sc, IGU_REG_PCI_PF_MSI_EN);
11059 PMD_DRV_LOG(DEBUG, sc, "IGU_REG_PCI_PF_MSI_EN is 0x%x", val);
11061 val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_EN);
11062 PMD_DRV_LOG(DEBUG, sc, "IGU_REG_PCI_PF_MSIX_EN is 0x%x", val);
11064 val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
11065 PMD_DRV_LOG(DEBUG, sc, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x", val);
11067 val = REG_RD(sc, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
11068 PMD_DRV_LOG(DEBUG, sc,
11069 "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x", val);
11071 val = REG_RD(sc, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
11072 PMD_DRV_LOG(DEBUG, sc,
11073 "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x", val);
11075 val = REG_RD(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
11076 PMD_DRV_LOG(DEBUG, sc, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x",
11081 * bnx2x_pf_flr_clnup
11082 * a. re-enable target read on the PF
11083 * b. poll cfc per function usgae counter
11084 * c. poll the qm perfunction usage counter
11085 * d. poll the tm per function usage counter
11086 * e. poll the tm per function scan-done indication
11087 * f. clear the dmae channel associated wit hthe PF
11088 * g. zero the igu 'trailing edge' and 'leading edge' regs (attentions)
11089 * h. call the common flr cleanup code with -1 (pf indication)
11091 static int bnx2x_pf_flr_clnup(struct bnx2x_softc *sc)
11093 uint32_t poll_cnt = bnx2x_flr_clnup_poll_count(sc);
11095 /* Re-enable PF target read access */
11096 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
11098 /* Poll HW usage counters */
11099 if (bnx2x_poll_hw_usage_counters(sc, poll_cnt)) {
11103 /* Zero the igu 'trailing edge' and 'leading edge' */
11105 /* Send the FW cleanup command */
11106 if (bnx2x_send_final_clnup(sc, (uint8_t) SC_FUNC(sc), poll_cnt)) {
11112 /* Verify TX hw is flushed */
11113 bnx2x_tx_hw_flushed(sc, poll_cnt);
11115 /* Wait 100ms (not adjusted according to platform) */
11118 /* Verify no pending pci transactions */
11119 if (bnx2x_is_pcie_pending(sc)) {
11120 PMD_DRV_LOG(NOTICE, sc, "PCIE Transactions still pending");
11124 bnx2x_hw_enable_status(sc);
11127 * Master enable - Due to WB DMAE writes performed before this
11128 * register is re-initialized as part of the regular function init
11130 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11135 static int bnx2x_init_hw_func(struct bnx2x_softc *sc)
11137 int port = SC_PORT(sc);
11138 int func = SC_FUNC(sc);
11139 int init_phase = PHASE_PF0 + func;
11140 struct ecore_ilt *ilt = sc->ilt;
11141 uint16_t cdu_ilt_start;
11142 uint32_t addr, val;
11143 uint32_t main_mem_base, main_mem_size, main_mem_prty_clr;
11144 int main_mem_width, rc;
11147 PMD_DRV_LOG(DEBUG, sc, "starting func init for func %d", func);
11150 if (!CHIP_IS_E1x(sc)) {
11151 rc = bnx2x_pf_flr_clnup(sc);
11153 PMD_DRV_LOG(NOTICE, sc, "FLR cleanup failed!");
11158 /* set MSI reconfigure capability */
11159 if (sc->devinfo.int_block == INT_BLOCK_HC) {
11160 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
11161 val = REG_RD(sc, addr);
11162 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
11163 REG_WR(sc, addr, val);
11166 ecore_init_block(sc, BLOCK_PXP, init_phase);
11167 ecore_init_block(sc, BLOCK_PXP2, init_phase);
11170 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
11172 for (i = 0; i < L2_ILT_LINES(sc); i++) {
11173 ilt->lines[cdu_ilt_start + i].page = sc->context[i].vcxt;
11174 ilt->lines[cdu_ilt_start + i].page_mapping =
11175 (rte_iova_t)sc->context[i].vcxt_dma.paddr;
11176 ilt->lines[cdu_ilt_start + i].size = sc->context[i].size;
11178 ecore_ilt_init_op(sc, INITOP_SET);
11180 REG_WR(sc, PRS_REG_NIC_MODE, 1);
11182 if (!CHIP_IS_E1x(sc)) {
11183 uint32_t pf_conf = IGU_PF_CONF_FUNC_EN;
11185 /* Turn on a single ISR mode in IGU if driver is going to use
11188 if ((sc->interrupt_mode != INTR_MODE_MSIX)
11189 || (sc->interrupt_mode != INTR_MODE_SINGLE_MSIX)) {
11190 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
11194 * Timers workaround bug: function init part.
11195 * Need to wait 20msec after initializing ILT,
11196 * needed to make sure there are no requests in
11197 * one of the PXP internal queues with "old" ILT addresses
11202 * Master enable - Due to WB DMAE writes performed before this
11203 * register is re-initialized as part of the regular function
11206 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11207 /* Enable the function in IGU */
11208 REG_WR(sc, IGU_REG_PF_CONFIGURATION, pf_conf);
11211 sc->dmae_ready = 1;
11213 ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
11215 if (!CHIP_IS_E1x(sc))
11216 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
11218 ecore_init_block(sc, BLOCK_ATC, init_phase);
11219 ecore_init_block(sc, BLOCK_DMAE, init_phase);
11220 ecore_init_block(sc, BLOCK_NIG, init_phase);
11221 ecore_init_block(sc, BLOCK_SRC, init_phase);
11222 ecore_init_block(sc, BLOCK_MISC, init_phase);
11223 ecore_init_block(sc, BLOCK_TCM, init_phase);
11224 ecore_init_block(sc, BLOCK_UCM, init_phase);
11225 ecore_init_block(sc, BLOCK_CCM, init_phase);
11226 ecore_init_block(sc, BLOCK_XCM, init_phase);
11227 ecore_init_block(sc, BLOCK_TSEM, init_phase);
11228 ecore_init_block(sc, BLOCK_USEM, init_phase);
11229 ecore_init_block(sc, BLOCK_CSEM, init_phase);
11230 ecore_init_block(sc, BLOCK_XSEM, init_phase);
11232 if (!CHIP_IS_E1x(sc))
11233 REG_WR(sc, QM_REG_PF_EN, 1);
11235 if (!CHIP_IS_E1x(sc)) {
11236 REG_WR(sc, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11237 REG_WR(sc, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11238 REG_WR(sc, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11239 REG_WR(sc, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11241 ecore_init_block(sc, BLOCK_QM, init_phase);
11243 ecore_init_block(sc, BLOCK_TM, init_phase);
11244 ecore_init_block(sc, BLOCK_DORQ, init_phase);
11246 ecore_init_block(sc, BLOCK_BRB1, init_phase);
11247 ecore_init_block(sc, BLOCK_PRS, init_phase);
11248 ecore_init_block(sc, BLOCK_TSDM, init_phase);
11249 ecore_init_block(sc, BLOCK_CSDM, init_phase);
11250 ecore_init_block(sc, BLOCK_USDM, init_phase);
11251 ecore_init_block(sc, BLOCK_XSDM, init_phase);
11252 ecore_init_block(sc, BLOCK_UPB, init_phase);
11253 ecore_init_block(sc, BLOCK_XPB, init_phase);
11254 ecore_init_block(sc, BLOCK_PBF, init_phase);
11255 if (!CHIP_IS_E1x(sc))
11256 REG_WR(sc, PBF_REG_DISABLE_PF, 0);
11258 ecore_init_block(sc, BLOCK_CDU, init_phase);
11260 ecore_init_block(sc, BLOCK_CFC, init_phase);
11262 if (!CHIP_IS_E1x(sc))
11263 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 1);
11266 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
11267 REG_WR(sc, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8, OVLAN(sc));
11270 ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
11272 /* HC init per function */
11273 if (sc->devinfo.int_block == INT_BLOCK_HC) {
11274 if (CHIP_IS_E1H(sc)) {
11275 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11277 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11278 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11280 ecore_init_block(sc, BLOCK_HC, init_phase);
11283 uint32_t num_segs, sb_idx, prod_offset;
11285 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11287 if (!CHIP_IS_E1x(sc)) {
11288 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11289 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11292 ecore_init_block(sc, BLOCK_IGU, init_phase);
11294 if (!CHIP_IS_E1x(sc)) {
11298 * E2 mode: address 0-135 match to the mapping memory;
11299 * 136 - PF0 default prod; 137 - PF1 default prod;
11300 * 138 - PF2 default prod; 139 - PF3 default prod;
11301 * 140 - PF0 attn prod; 141 - PF1 attn prod;
11302 * 142 - PF2 attn prod; 143 - PF3 attn prod;
11303 * 144-147 reserved.
11305 * E1.5 mode - In backward compatible mode;
11306 * for non default SB; each even line in the memory
11307 * holds the U producer and each odd line hold
11308 * the C producer. The first 128 producers are for
11309 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
11310 * producers are for the DSB for each PF.
11311 * Each PF has five segments: (the order inside each
11312 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
11313 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
11314 * 144-147 attn prods;
11316 /* non-default-status-blocks */
11317 num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11318 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
11319 for (sb_idx = 0; sb_idx < sc->igu_sb_cnt; sb_idx++) {
11320 prod_offset = (sc->igu_base_sb + sb_idx) *
11323 for (i = 0; i < num_segs; i++) {
11324 addr = IGU_REG_PROD_CONS_MEMORY +
11325 (prod_offset + i) * 4;
11326 REG_WR(sc, addr, 0);
11328 /* send consumer update with value 0 */
11329 bnx2x_ack_sb(sc, sc->igu_base_sb + sb_idx,
11330 USTORM_ID, 0, IGU_INT_NOP, 1);
11331 bnx2x_igu_clear_sb(sc, sc->igu_base_sb + sb_idx);
11334 /* default-status-blocks */
11335 num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11336 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
11338 if (CHIP_IS_MODE_4_PORT(sc))
11339 dsb_idx = SC_FUNC(sc);
11341 dsb_idx = SC_VN(sc);
11343 prod_offset = (CHIP_INT_MODE_IS_BC(sc) ?
11344 IGU_BC_BASE_DSB_PROD + dsb_idx :
11345 IGU_NORM_BASE_DSB_PROD + dsb_idx);
11348 * igu prods come in chunks of E1HVN_MAX (4) -
11349 * does not matters what is the current chip mode
11351 for (i = 0; i < (num_segs * E1HVN_MAX); i += E1HVN_MAX) {
11352 addr = IGU_REG_PROD_CONS_MEMORY +
11353 (prod_offset + i) * 4;
11354 REG_WR(sc, addr, 0);
11356 /* send consumer update with 0 */
11357 if (CHIP_INT_MODE_IS_BC(sc)) {
11358 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11359 USTORM_ID, 0, IGU_INT_NOP, 1);
11360 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11361 CSTORM_ID, 0, IGU_INT_NOP, 1);
11362 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11363 XSTORM_ID, 0, IGU_INT_NOP, 1);
11364 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11365 TSTORM_ID, 0, IGU_INT_NOP, 1);
11366 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11367 ATTENTION_ID, 0, IGU_INT_NOP, 1);
11369 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11370 USTORM_ID, 0, IGU_INT_NOP, 1);
11371 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11372 ATTENTION_ID, 0, IGU_INT_NOP, 1);
11374 bnx2x_igu_clear_sb(sc, sc->igu_dsb_id);
11376 /* !!! these should become driver const once
11377 rf-tool supports split-68 const */
11378 REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
11379 REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
11380 REG_WR(sc, IGU_REG_SB_MASK_LSB, 0);
11381 REG_WR(sc, IGU_REG_SB_MASK_MSB, 0);
11382 REG_WR(sc, IGU_REG_PBA_STATUS_LSB, 0);
11383 REG_WR(sc, IGU_REG_PBA_STATUS_MSB, 0);
11387 /* Reset PCIE errors for debug */
11388 REG_WR(sc, 0x2114, 0xffffffff);
11389 REG_WR(sc, 0x2120, 0xffffffff);
11391 if (CHIP_IS_E1x(sc)) {
11392 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords */
11393 main_mem_base = HC_REG_MAIN_MEMORY +
11394 SC_PORT(sc) * (main_mem_size * 4);
11395 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
11396 main_mem_width = 8;
11398 val = REG_RD(sc, main_mem_prty_clr);
11400 PMD_DRV_LOG(DEBUG, sc,
11401 "Parity errors in HC block during function init (0x%x)!",
11405 /* Clear "false" parity errors in MSI-X table */
11406 for (i = main_mem_base;
11407 i < main_mem_base + main_mem_size * 4;
11408 i += main_mem_width) {
11409 bnx2x_read_dmae(sc, i, main_mem_width / 4);
11410 bnx2x_write_dmae(sc, BNX2X_SP_MAPPING(sc, wb_data),
11411 i, main_mem_width / 4);
11413 /* Clear HC parity attention */
11414 REG_RD(sc, main_mem_prty_clr);
11417 /* Enable STORMs SP logging */
11418 REG_WR8(sc, BAR_USTRORM_INTMEM +
11419 USTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11420 REG_WR8(sc, BAR_TSTRORM_INTMEM +
11421 TSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11422 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11423 CSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11424 REG_WR8(sc, BAR_XSTRORM_INTMEM +
11425 XSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11427 elink_phy_probe(&sc->link_params);
11432 static void bnx2x_link_reset(struct bnx2x_softc *sc)
11434 if (!BNX2X_NOMCP(sc)) {
11435 bnx2x_acquire_phy_lock(sc);
11436 elink_lfa_reset(&sc->link_params, &sc->link_vars);
11437 bnx2x_release_phy_lock(sc);
11439 if (!CHIP_REV_IS_SLOW(sc)) {
11440 PMD_DRV_LOG(WARNING, sc,
11441 "Bootcode is missing - cannot reset link");
11446 static void bnx2x_reset_port(struct bnx2x_softc *sc)
11448 int port = SC_PORT(sc);
11451 /* reset physical Link */
11452 bnx2x_link_reset(sc);
11454 REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
11456 /* Do not rcv packets to BRB */
11457 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + port * 4, 0x0);
11458 /* Do not direct rcv packets that are not for MCP to the BRB */
11459 REG_WR(sc, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
11460 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
11462 /* Configure AEU */
11463 REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, 0);
11467 /* Check for BRB port occupancy */
11468 val = REG_RD(sc, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port * 4);
11470 PMD_DRV_LOG(DEBUG, sc,
11471 "BRB1 is not empty, %d blocks are occupied", val);
11475 static void bnx2x_ilt_wr(struct bnx2x_softc *sc, uint32_t index, rte_iova_t addr)
11478 uint32_t wb_write[2];
11480 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index * 8;
11482 wb_write[0] = ONCHIP_ADDR1(addr);
11483 wb_write[1] = ONCHIP_ADDR2(addr);
11484 REG_WR_DMAE(sc, reg, wb_write, 2);
11487 static void bnx2x_clear_func_ilt(struct bnx2x_softc *sc, uint32_t func)
11489 uint32_t i, base = FUNC_ILT_BASE(func);
11490 for (i = base; i < base + ILT_PER_FUNC; i++) {
11491 bnx2x_ilt_wr(sc, i, 0);
11495 static void bnx2x_reset_func(struct bnx2x_softc *sc)
11497 struct bnx2x_fastpath *fp;
11498 int port = SC_PORT(sc);
11499 int func = SC_FUNC(sc);
11502 /* Disable the function in the FW */
11503 REG_WR8(sc, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
11504 REG_WR8(sc, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
11505 REG_WR8(sc, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
11506 REG_WR8(sc, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
11509 FOR_EACH_ETH_QUEUE(sc, i) {
11511 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11512 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
11517 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11518 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), SB_DISABLED);
11520 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) {
11521 REG_WR(sc, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
11525 /* Configure IGU */
11526 if (sc->devinfo.int_block == INT_BLOCK_HC) {
11527 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11528 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11530 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11531 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11534 if (CNIC_LOADED(sc)) {
11535 /* Disable Timer scan */
11536 REG_WR(sc, TM_REG_EN_LINEAR0_TIMER + port * 4, 0);
11538 * Wait for at least 10ms and up to 2 second for the timers
11541 for (i = 0; i < 200; i++) {
11543 if (!REG_RD(sc, TM_REG_LIN0_SCAN_ON + port * 4))
11549 bnx2x_clear_func_ilt(sc, func);
11552 * Timers workaround bug for E2: if this is vnic-3,
11553 * we need to set the entire ilt range for this timers.
11555 if (!CHIP_IS_E1x(sc) && SC_VN(sc) == 3) {
11556 struct ilt_client_info ilt_cli;
11557 /* use dummy TM client */
11558 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
11560 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
11561 ilt_cli.client_num = ILT_CLIENT_TM;
11563 ecore_ilt_boundary_init_op(sc, &ilt_cli, 0, INITOP_CLEAR);
11566 /* this assumes that reset_port() called before reset_func() */
11567 if (!CHIP_IS_E1x(sc)) {
11568 bnx2x_pf_disable(sc);
11571 sc->dmae_ready = 0;
11574 static void bnx2x_release_firmware(struct bnx2x_softc *sc)
11576 rte_free(sc->init_ops);
11577 rte_free(sc->init_ops_offsets);
11578 rte_free(sc->init_data);
11579 rte_free(sc->iro_array);
11582 static int bnx2x_init_firmware(struct bnx2x_softc *sc)
11585 uint8_t *p = sc->firmware;
11588 for (i = 0; i < 24; ++i)
11589 off[i] = rte_be_to_cpu_32(*((uint32_t *) sc->firmware + i));
11592 sc->init_ops = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11595 bnx2x_data_to_init_ops(p + off[1], sc->init_ops, len);
11598 sc->init_ops_offsets = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11599 if (!sc->init_ops_offsets)
11601 bnx2x_data_to_init_offsets(p + off[3], sc->init_ops_offsets, len);
11604 sc->init_data = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11605 if (!sc->init_data)
11607 bnx2x_data_to_init_data(p + off[5], sc->init_data, len);
11609 sc->tsem_int_table_data = p + off[7];
11610 sc->tsem_pram_data = p + off[9];
11611 sc->usem_int_table_data = p + off[11];
11612 sc->usem_pram_data = p + off[13];
11613 sc->csem_int_table_data = p + off[15];
11614 sc->csem_pram_data = p + off[17];
11615 sc->xsem_int_table_data = p + off[19];
11616 sc->xsem_pram_data = p + off[21];
11619 sc->iro_array = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11620 if (!sc->iro_array)
11622 bnx2x_data_to_iro_array(p + off[23], sc->iro_array, len);
11627 bnx2x_release_firmware(sc);
11631 static int cut_gzip_prefix(const uint8_t * zbuf, int len)
11633 #define MIN_PREFIX_SIZE (10)
11635 int n = MIN_PREFIX_SIZE;
11638 if (!(zbuf[0] == 0x1f && zbuf[1] == 0x8b && zbuf[2] == Z_DEFLATED) ||
11639 len <= MIN_PREFIX_SIZE) {
11643 /* optional extra fields are present */
11644 if (zbuf[3] & 0x4) {
11651 /* file name is present */
11652 if (zbuf[3] & 0x8) {
11653 while ((zbuf[n++] != 0) && (n < len)) ;
11659 static int ecore_gunzip(struct bnx2x_softc *sc, const uint8_t * zbuf, int len)
11662 int data_begin = cut_gzip_prefix(zbuf, len);
11664 PMD_DRV_LOG(DEBUG, sc, "ecore_gunzip %d", len);
11666 if (data_begin <= 0) {
11667 PMD_DRV_LOG(NOTICE, sc, "bad gzip prefix");
11671 memset(&zlib_stream, 0, sizeof(zlib_stream));
11672 zlib_stream.next_in = zbuf + data_begin;
11673 zlib_stream.avail_in = len - data_begin;
11674 zlib_stream.next_out = sc->gz_buf;
11675 zlib_stream.avail_out = FW_BUF_SIZE;
11677 ret = inflateInit2(&zlib_stream, -MAX_WBITS);
11679 PMD_DRV_LOG(NOTICE, sc, "zlib inflateInit2 error");
11683 ret = inflate(&zlib_stream, Z_FINISH);
11684 if ((ret != Z_STREAM_END) && (ret != Z_OK)) {
11685 PMD_DRV_LOG(NOTICE, sc, "zlib inflate error: %d %s", ret,
11689 sc->gz_outlen = zlib_stream.total_out;
11690 if (sc->gz_outlen & 0x3) {
11691 PMD_DRV_LOG(NOTICE, sc, "firmware is not aligned. gz_outlen == %d",
11694 sc->gz_outlen >>= 2;
11696 inflateEnd(&zlib_stream);
11698 if (ret == Z_STREAM_END)
11705 ecore_write_dmae_phys_len(struct bnx2x_softc *sc, rte_iova_t phys_addr,
11706 uint32_t addr, uint32_t len)
11708 bnx2x_write_dmae_phys_len(sc, phys_addr, addr, len);
11712 ecore_storm_memset_struct(struct bnx2x_softc *sc, uint32_t addr, size_t size,
11716 for (i = 0; i < size / 4; i++) {
11717 REG_WR(sc, addr + (i * 4), data[i]);
11721 static const char *get_ext_phy_type(uint32_t ext_phy_type)
11723 uint32_t phy_type_idx = ext_phy_type >> 8;
11724 static const char *types[] =
11725 { "DIRECT", "BNX2X-8071", "BNX2X-8072", "BNX2X-8073",
11726 "BNX2X-8705", "BNX2X-8706", "BNX2X-8726", "BNX2X-8481", "SFX-7101",
11728 "BNX2X-8727-NOC", "BNX2X-84823", "NOT_CONN", "FAILURE"
11731 if (phy_type_idx < 12)
11732 return types[phy_type_idx];
11733 else if (PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN == ext_phy_type)
11739 static const char *get_state(uint32_t state)
11741 uint32_t state_idx = state >> 12;
11742 static const char *states[] = { "CLOSED", "OPENING_WAIT4_LOAD",
11743 "OPENING_WAIT4_PORT", "OPEN", "CLOSING_WAIT4_HALT",
11744 "CLOSING_WAIT4_DELETE", "CLOSING_WAIT4_UNLOAD",
11745 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
11746 "UNKNOWN", "DISABLED", "DIAG", "ERROR", "UNDEFINED"
11749 if (state_idx <= 0xF)
11750 return states[state_idx];
11752 return states[0x10];
11755 static const char *get_recovery_state(uint32_t state)
11757 static const char *states[] = { "NONE", "DONE", "INIT",
11758 "WAIT", "FAILED", "NIC_LOADING"
11760 return states[state];
11763 static const char *get_rx_mode(uint32_t mode)
11765 static const char *modes[] = { "NONE", "NORMAL", "ALLMULTI",
11766 "PROMISC", "MAX_MULTICAST", "ERROR"
11770 return modes[mode];
11771 else if (BNX2X_MAX_MULTICAST == mode)
11777 #define BNX2X_INFO_STR_MAX 256
11778 static const char *get_bnx2x_flags(uint32_t flags)
11781 static const char *flag[] = { "ONE_PORT ", "NO_ISCSI ",
11782 "NO_FCOE ", "NO_WOL ", "USING_DAC ", "USING_MSIX ",
11783 "USING_MSI ", "DISABLE_MSI ", "UNKNOWN ", "NO_MCP ",
11784 "SAFC_TX_FLAG ", "MF_FUNC_DIS ", "TX_SWITCHING "
11786 static char flag_str[BNX2X_INFO_STR_MAX];
11787 memset(flag_str, 0, BNX2X_INFO_STR_MAX);
11789 for (i = 0; i < 5; i++)
11790 if (flags & (1 << i)) {
11791 strlcat(flag_str, flag[i], sizeof(flag_str));
11795 static char unknown[BNX2X_INFO_STR_MAX];
11796 snprintf(unknown, 32, "Unknown flag mask %x", flags);
11797 strlcat(flag_str, unknown, sizeof(flag_str));
11802 /* Prints useful adapter info. */
11803 void bnx2x_print_adapter_info(struct bnx2x_softc *sc)
11807 PMD_DRV_LOG(INFO, sc, "========================================");
11808 /* DPDK and Driver versions */
11809 PMD_DRV_LOG(INFO, sc, "%12s : %s", "DPDK",
11811 PMD_DRV_LOG(INFO, sc, "%12s : %s", "Driver",
11812 bnx2x_pmd_version());
11813 /* Firmware versions. */
11814 PMD_DRV_LOG(INFO, sc, "%12s : %d.%d.%d",
11816 BNX2X_5710_FW_MAJOR_VERSION,
11817 BNX2X_5710_FW_MINOR_VERSION,
11818 BNX2X_5710_FW_REVISION_VERSION);
11819 PMD_DRV_LOG(INFO, sc, "%12s : %s",
11820 "Bootcode", sc->devinfo.bc_ver_str);
11821 /* Hardware chip info. */
11822 PMD_DRV_LOG(INFO, sc, "%12s : %#08x", "ASIC", sc->devinfo.chip_id);
11823 PMD_DRV_LOG(INFO, sc, "%12s : %c%d", "Rev", (CHIP_REV(sc) >> 12) + 'A',
11824 (CHIP_METAL(sc) >> 4));
11825 /* Bus PCIe info. */
11826 PMD_DRV_LOG(INFO, sc, "%12s : 0x%x", "Vendor Id",
11827 sc->devinfo.vendor_id);
11828 PMD_DRV_LOG(INFO, sc, "%12s : 0x%x", "Device Id",
11829 sc->devinfo.device_id);
11830 PMD_DRV_LOG(INFO, sc, "%12s : width x%d, ", "Bus PCIe",
11831 sc->devinfo.pcie_link_width);
11832 switch (sc->devinfo.pcie_link_speed) {
11834 PMD_DRV_LOG(INFO, sc, "%23s", "2.5 Gbps");
11837 PMD_DRV_LOG(INFO, sc, "%21s", "5 Gbps");
11840 PMD_DRV_LOG(INFO, sc, "%21s", "8 Gbps");
11843 PMD_DRV_LOG(INFO, sc, "%33s", "Unknown link speed");
11845 /* Device features. */
11846 PMD_DRV_LOG(INFO, sc, "%12s : ", "Flags");
11847 /* Miscellaneous flags. */
11848 if (sc->devinfo.pcie_cap_flags & BNX2X_MSI_CAPABLE_FLAG) {
11849 PMD_DRV_LOG(INFO, sc, "%18s", "MSI");
11852 if (sc->devinfo.pcie_cap_flags & BNX2X_MSIX_CAPABLE_FLAG) {
11854 PMD_DRV_LOG(INFO, sc, "|");
11855 PMD_DRV_LOG(INFO, sc, "%20s", "MSI-X");
11858 PMD_DRV_LOG(INFO, sc, "%12s : %s", "OVLAN", (OVLAN(sc) ? "YES" : "NO"));
11859 PMD_DRV_LOG(INFO, sc, "%12s : %s", "MF", (IS_MF(sc) ? "YES" : "NO"));
11860 PMD_DRV_LOG(INFO, sc, "========================================");
11863 /* Prints useful device info. */
11864 void bnx2x_print_device_info(struct bnx2x_softc *sc)
11866 __rte_unused uint32_t ext_phy_type;
11867 uint32_t offset, reg_val;
11869 PMD_INIT_FUNC_TRACE(sc);
11870 offset = offsetof(struct shmem_region,
11871 dev_info.port_hw_config[0].external_phy_config);
11872 reg_val = REG_RD(sc, sc->devinfo.shmem_base + offset);
11873 if (sc->link_vars.phy_flags & PHY_XGXS_FLAG)
11874 ext_phy_type = ELINK_XGXS_EXT_PHY_TYPE(reg_val);
11876 ext_phy_type = ELINK_SERDES_EXT_PHY_TYPE(reg_val);
11878 /* Device features. */
11879 PMD_DRV_LOG(INFO, sc, "%12s : %u", "Bnx2x Func", sc->pcie_func);
11880 PMD_DRV_LOG(INFO, sc,
11881 "%12s : %s", "Bnx2x Flags", get_bnx2x_flags(sc->flags));
11882 PMD_DRV_LOG(INFO, sc, "%12s : %s", "DMAE Is",
11883 (sc->dmae_ready ? "Ready" : "Not Ready"));
11884 PMD_DRV_LOG(INFO, sc, "%12s : %u", "MTU", sc->mtu);
11885 PMD_DRV_LOG(INFO, sc,
11886 "%12s : %s", "PHY Type", get_ext_phy_type(ext_phy_type));
11887 PMD_DRV_LOG(INFO, sc, "%12s : %x:%x:%x:%x:%x:%x", "MAC Addr",
11888 sc->link_params.mac_addr[0],
11889 sc->link_params.mac_addr[1],
11890 sc->link_params.mac_addr[2],
11891 sc->link_params.mac_addr[3],
11892 sc->link_params.mac_addr[4],
11893 sc->link_params.mac_addr[5]);
11894 PMD_DRV_LOG(INFO, sc, "%12s : %s", "RX Mode", get_rx_mode(sc->rx_mode));
11895 PMD_DRV_LOG(INFO, sc, "%12s : %s", "State", get_state(sc->state));
11896 if (sc->recovery_state)
11897 PMD_DRV_LOG(INFO, sc, "%12s : %s", "Recovery",
11898 get_recovery_state(sc->recovery_state));
11901 switch (sc->sp->rss_rdata.rss_mode) {
11902 case ETH_RSS_MODE_DISABLED:
11903 PMD_DRV_LOG(INFO, sc, "%12s : %s", "Queues", "RSS mode - None");
11905 case ETH_RSS_MODE_REGULAR:
11906 PMD_DRV_LOG(INFO, sc, "%12s : %s,", "Queues", "RSS mode - Regular");
11907 PMD_DRV_LOG(INFO, sc, "%16d", sc->num_queues);
11910 PMD_DRV_LOG(INFO, sc, "%12s : %s", "Queues", "RSS mode - Unknown");
11914 PMD_DRV_LOG(INFO, sc, "%12s : CQ = %lx, EQ = %lx", "SPQ Left",
11915 sc->cq_spq_left, sc->eq_spq_left);
11917 PMD_DRV_LOG(INFO, sc,
11918 "%12s : %x", "Switch", sc->link_params.switch_cfg);
11919 PMD_DRV_LOG(INFO, sc, "pcie_bus=%d, pcie_device=%d",
11920 sc->pcie_bus, sc->pcie_device);
11921 PMD_DRV_LOG(INFO, sc, "bar0.addr=%p, bar1.addr=%p",
11922 sc->bar[BAR0].base_addr, sc->bar[BAR1].base_addr);
11923 PMD_DRV_LOG(INFO, sc, "port=%d, path=%d, vnic=%d, func=%d",
11924 PORT_ID(sc), PATH_ID(sc), VNIC_ID(sc), FUNC_ID(sc));