1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2007-2013 Broadcom Corporation.
4 * Eric Davis <edavis@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
6 * Gary Zambrano <zambrano@broadcom.com>
8 * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
9 * Copyright (c) 2015-2018 Cavium Inc.
10 * All rights reserved.
14 #define BNX2X_DRIVER_VERSION "1.78.18"
17 #include "bnx2x_vfpf.h"
19 #include "ecore_init.h"
20 #include "ecore_init_ops.h"
22 #include "rte_version.h"
24 #include <sys/types.h>
28 #include <rte_string_fns.h>
30 #define BNX2X_PMD_VER_PREFIX "BNX2X PMD"
31 #define BNX2X_PMD_VERSION_MAJOR 1
32 #define BNX2X_PMD_VERSION_MINOR 1
33 #define BNX2X_PMD_VERSION_REVISION 0
34 #define BNX2X_PMD_VERSION_PATCH 1
36 static inline const char *
37 bnx2x_pmd_version(void)
39 static char version[32];
41 snprintf(version, sizeof(version), "%s %s_%d.%d.%d.%d",
44 BNX2X_PMD_VERSION_MAJOR,
45 BNX2X_PMD_VERSION_MINOR,
46 BNX2X_PMD_VERSION_REVISION,
47 BNX2X_PMD_VERSION_PATCH);
52 static z_stream zlib_stream;
54 #define EVL_VLID_MASK 0x0FFF
56 #define BNX2X_DEF_SB_ATT_IDX 0x0001
57 #define BNX2X_DEF_SB_IDX 0x0002
60 * FLR Support - bnx2x_pf_flr_clnup() is called during nic_load in the per
61 * function HW initialization.
63 #define FLR_WAIT_USEC 10000 /* 10 msecs */
64 #define FLR_WAIT_INTERVAL 50 /* usecs */
65 #define FLR_POLL_CNT (FLR_WAIT_USEC / FLR_WAIT_INTERVAL) /* 200 */
67 struct pbf_pN_buf_regs {
74 struct pbf_pN_cmd_regs {
80 /* resources needed for unloading a previously loaded device */
82 #define BNX2X_PREV_WAIT_NEEDED 1
83 rte_spinlock_t bnx2x_prev_mtx;
84 struct bnx2x_prev_list_node {
85 LIST_ENTRY(bnx2x_prev_list_node) node;
93 static LIST_HEAD(, bnx2x_prev_list_node) bnx2x_prev_list
94 = LIST_HEAD_INITIALIZER(bnx2x_prev_list);
96 static int load_count[2][3] = { { 0 } };
97 /* per-path: 0-common, 1-port0, 2-port1 */
99 static void bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg,
101 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc);
102 static void storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng,
104 static void bnx2x_set_reset_global(struct bnx2x_softc *sc);
105 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc);
106 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine);
107 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc);
108 static uint8_t bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global,
110 static void bnx2x_int_disable(struct bnx2x_softc *sc);
111 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc);
112 static void bnx2x_pf_disable(struct bnx2x_softc *sc);
113 static void bnx2x_update_rx_prod(struct bnx2x_softc *sc,
114 struct bnx2x_fastpath *fp,
115 uint16_t rx_bd_prod, uint16_t rx_cq_prod);
116 static void bnx2x_link_report_locked(struct bnx2x_softc *sc);
117 static void bnx2x_link_report(struct bnx2x_softc *sc);
118 void bnx2x_link_status_update(struct bnx2x_softc *sc);
119 static int bnx2x_alloc_mem(struct bnx2x_softc *sc);
120 static void bnx2x_free_mem(struct bnx2x_softc *sc);
121 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc);
122 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc);
123 static __rte_noinline
124 int bnx2x_nic_load(struct bnx2x_softc *sc);
126 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc);
127 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp);
128 static void bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id,
129 uint8_t storm, uint16_t index, uint8_t op,
132 int bnx2x_test_bit(int nr, volatile unsigned long *addr)
137 res = ((*addr) & (1UL << nr)) != 0;
142 void bnx2x_set_bit(unsigned int nr, volatile unsigned long *addr)
144 __sync_fetch_and_or(addr, (1UL << nr));
147 void bnx2x_clear_bit(int nr, volatile unsigned long *addr)
149 __sync_fetch_and_and(addr, ~(1UL << nr));
152 int bnx2x_test_and_clear_bit(int nr, volatile unsigned long *addr)
154 unsigned long mask = (1UL << nr);
155 return __sync_fetch_and_and(addr, ~mask) & mask;
158 int bnx2x_cmpxchg(volatile int *addr, int old, int new)
160 return __sync_val_compare_and_swap(addr, old, new);
164 bnx2x_dma_alloc(struct bnx2x_softc *sc, size_t size, struct bnx2x_dma *dma,
165 const char *msg, uint32_t align)
167 char mz_name[RTE_MEMZONE_NAMESIZE];
168 const struct rte_memzone *z;
172 snprintf(mz_name, sizeof(mz_name), "bnx2x%d_%s_%" PRIx64, SC_ABS_FUNC(sc), msg,
173 rte_get_timer_cycles());
175 snprintf(mz_name, sizeof(mz_name), "bnx2x%d_%s_%" PRIx64, sc->pcie_device, msg,
176 rte_get_timer_cycles());
178 /* Caller must take care that strlen(mz_name) < RTE_MEMZONE_NAMESIZE */
179 z = rte_memzone_reserve_aligned(mz_name, (uint64_t)size,
181 RTE_MEMZONE_IOVA_CONTIG, align);
183 PMD_DRV_LOG(ERR, sc, "DMA alloc failed for %s", msg);
186 dma->paddr = (uint64_t) z->iova;
187 dma->vaddr = z->addr;
188 dma->mzone = (const void *)z;
190 PMD_DRV_LOG(DEBUG, sc,
191 "%s: virt=%p phys=%" PRIx64, msg, dma->vaddr, dma->paddr);
196 void bnx2x_dma_free(struct bnx2x_dma *dma)
198 if (dma->mzone == NULL)
201 rte_memzone_free((const struct rte_memzone *)dma->mzone);
209 static int bnx2x_acquire_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
211 uint32_t lock_status;
212 uint32_t resource_bit = (1 << resource);
213 int func = SC_FUNC(sc);
214 uint32_t hw_lock_control_reg;
217 #ifndef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
219 PMD_INIT_FUNC_TRACE(sc);
221 PMD_INIT_FUNC_TRACE(sc);
224 /* validate the resource is within range */
225 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
226 PMD_DRV_LOG(NOTICE, sc,
227 "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
233 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
235 hw_lock_control_reg =
236 (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
239 /* validate the resource is not already taken */
240 lock_status = REG_RD(sc, hw_lock_control_reg);
241 if (lock_status & resource_bit) {
242 PMD_DRV_LOG(NOTICE, sc,
243 "resource in use (status 0x%x bit 0x%x)",
244 lock_status, resource_bit);
248 /* try every 5ms for 5 seconds */
249 for (cnt = 0; cnt < 1000; cnt++) {
250 REG_WR(sc, (hw_lock_control_reg + 4), resource_bit);
251 lock_status = REG_RD(sc, hw_lock_control_reg);
252 if (lock_status & resource_bit) {
258 PMD_DRV_LOG(NOTICE, sc, "Resource 0x%x resource_bit 0x%x lock timeout!",
259 resource, resource_bit);
263 static int bnx2x_release_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
265 uint32_t lock_status;
266 uint32_t resource_bit = (1 << resource);
267 int func = SC_FUNC(sc);
268 uint32_t hw_lock_control_reg;
270 #ifndef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
272 PMD_INIT_FUNC_TRACE(sc);
274 PMD_INIT_FUNC_TRACE(sc);
277 /* validate the resource is within range */
278 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
279 PMD_DRV_LOG(NOTICE, sc,
280 "(resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE)"
281 " resource_bit 0x%x", resource, resource_bit);
286 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
288 hw_lock_control_reg =
289 (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
292 /* validate the resource is currently taken */
293 lock_status = REG_RD(sc, hw_lock_control_reg);
294 if (!(lock_status & resource_bit)) {
295 PMD_DRV_LOG(NOTICE, sc,
296 "resource not in use (status 0x%x bit 0x%x)",
297 lock_status, resource_bit);
301 REG_WR(sc, hw_lock_control_reg, resource_bit);
305 static void bnx2x_acquire_phy_lock(struct bnx2x_softc *sc)
308 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_MDIO);
311 static void bnx2x_release_phy_lock(struct bnx2x_softc *sc)
313 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_MDIO);
314 BNX2X_PHY_UNLOCK(sc);
317 /* copy command into DMAE command memory and set DMAE command Go */
318 void bnx2x_post_dmae(struct bnx2x_softc *sc, struct dmae_command *dmae, int idx)
323 cmd_offset = (DMAE_REG_CMD_MEM + (sizeof(struct dmae_command) * idx));
324 for (i = 0; i < ((sizeof(struct dmae_command) / 4)); i++) {
325 REG_WR(sc, (cmd_offset + (i * 4)), *(((uint32_t *) dmae) + i));
328 REG_WR(sc, dmae_reg_go_c[idx], 1);
331 uint32_t bnx2x_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type)
333 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
334 DMAE_COMMAND_C_TYPE_ENABLE);
337 uint32_t bnx2x_dmae_opcode_clr_src_reset(uint32_t opcode)
339 return opcode & ~DMAE_COMMAND_SRC_RESET;
343 bnx2x_dmae_opcode(struct bnx2x_softc * sc, uint8_t src_type, uint8_t dst_type,
344 uint8_t with_comp, uint8_t comp_type)
348 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
349 (dst_type << DMAE_COMMAND_DST_SHIFT));
351 opcode |= (DMAE_COMMAND_SRC_RESET | DMAE_COMMAND_DST_RESET);
353 opcode |= (SC_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
355 opcode |= ((SC_VN(sc) << DMAE_COMMAND_E1HVN_SHIFT) |
356 (SC_VN(sc) << DMAE_COMMAND_DST_VN_SHIFT));
358 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
361 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
363 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
367 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
374 bnx2x_prep_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae,
375 uint8_t src_type, uint8_t dst_type)
377 memset(dmae, 0, sizeof(struct dmae_command));
380 dmae->opcode = bnx2x_dmae_opcode(sc, src_type, dst_type,
381 TRUE, DMAE_COMP_PCI);
383 /* fill in the completion parameters */
384 dmae->comp_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_comp));
385 dmae->comp_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_comp));
386 dmae->comp_val = DMAE_COMP_VAL;
389 /* issue a DMAE command over the init channel and wait for completion */
391 bnx2x_issue_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae)
393 uint32_t *wb_comp = BNX2X_SP(sc, wb_comp);
394 int timeout = CHIP_REV_IS_SLOW(sc) ? 400000 : 4000;
396 /* reset completion */
399 /* post the command on the channel used for initializations */
400 bnx2x_post_dmae(sc, dmae, INIT_DMAE_C(sc));
402 /* wait for completion */
405 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
407 (sc->recovery_state != BNX2X_RECOVERY_DONE &&
408 sc->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
409 PMD_DRV_LOG(INFO, sc, "DMAE timeout!");
417 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
418 PMD_DRV_LOG(INFO, sc, "DMAE PCI error!");
419 return DMAE_PCI_ERROR;
425 void bnx2x_read_dmae(struct bnx2x_softc *sc, uint32_t src_addr, uint32_t len32)
427 struct dmae_command dmae;
432 if (!sc->dmae_ready) {
433 data = BNX2X_SP(sc, wb_data[0]);
435 for (i = 0; i < len32; i++) {
436 data[i] = REG_RD(sc, (src_addr + (i * 4)));
442 /* set opcode and fixed command fields */
443 bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
445 /* fill in addresses and len */
446 dmae.src_addr_lo = (src_addr >> 2); /* GRC addr has dword resolution */
447 dmae.src_addr_hi = 0;
448 dmae.dst_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_data));
449 dmae.dst_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_data));
452 /* issue the command and wait for completion */
453 if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
454 rte_panic("DMAE failed (%d)", rc);
459 bnx2x_write_dmae(struct bnx2x_softc *sc, rte_iova_t dma_addr, uint32_t dst_addr,
462 struct dmae_command dmae;
465 if (!sc->dmae_ready) {
466 ecore_init_str_wr(sc, dst_addr, BNX2X_SP(sc, wb_data[0]), len32);
470 /* set opcode and fixed command fields */
471 bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
473 /* fill in addresses and len */
474 dmae.src_addr_lo = U64_LO(dma_addr);
475 dmae.src_addr_hi = U64_HI(dma_addr);
476 dmae.dst_addr_lo = (dst_addr >> 2); /* GRC addr has dword resolution */
477 dmae.dst_addr_hi = 0;
480 /* issue the command and wait for completion */
481 if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
482 rte_panic("DMAE failed (%d)", rc);
487 bnx2x_write_dmae_phys_len(struct bnx2x_softc *sc, rte_iova_t phys_addr,
488 uint32_t addr, uint32_t len)
490 uint32_t dmae_wr_max = DMAE_LEN32_WR_MAX(sc);
493 while (len > dmae_wr_max) {
494 bnx2x_write_dmae(sc, (phys_addr + offset), /* src DMA address */
495 (addr + offset), /* dst GRC address */
497 offset += (dmae_wr_max * 4);
501 bnx2x_write_dmae(sc, (phys_addr + offset), /* src DMA address */
502 (addr + offset), /* dst GRC address */
507 bnx2x_set_ctx_validation(struct bnx2x_softc *sc, struct eth_context *cxt,
510 /* ustorm cxt validation */
511 cxt->ustorm_ag_context.cdu_usage =
512 CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
513 CDU_REGION_NUMBER_UCM_AG,
514 ETH_CONNECTION_TYPE);
515 /* xcontext validation */
516 cxt->xstorm_ag_context.cdu_reserved =
517 CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
518 CDU_REGION_NUMBER_XCM_AG,
519 ETH_CONNECTION_TYPE);
523 bnx2x_storm_memset_hc_timeout(struct bnx2x_softc *sc, uint8_t fw_sb_id,
524 uint8_t sb_index, uint8_t ticks)
527 (BAR_CSTRORM_INTMEM +
528 CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(fw_sb_id, sb_index));
530 REG_WR8(sc, addr, ticks);
534 bnx2x_storm_memset_hc_disable(struct bnx2x_softc *sc, uint16_t fw_sb_id,
535 uint8_t sb_index, uint8_t disable)
537 uint32_t enable_flag =
538 (disable) ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
540 (BAR_CSTRORM_INTMEM +
541 CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(fw_sb_id, sb_index));
545 flags = REG_RD8(sc, addr);
546 flags &= ~HC_INDEX_DATA_HC_ENABLED;
547 flags |= enable_flag;
548 REG_WR8(sc, addr, flags);
552 bnx2x_update_coalesce_sb_index(struct bnx2x_softc *sc, uint8_t fw_sb_id,
553 uint8_t sb_index, uint8_t disable, uint16_t usec)
555 uint8_t ticks = (usec / 4);
557 bnx2x_storm_memset_hc_timeout(sc, fw_sb_id, sb_index, ticks);
559 disable = (disable) ? 1 : ((usec) ? 0 : 1);
560 bnx2x_storm_memset_hc_disable(sc, fw_sb_id, sb_index, disable);
563 uint32_t elink_cb_reg_read(struct bnx2x_softc *sc, uint32_t reg_addr)
565 return REG_RD(sc, reg_addr);
568 void elink_cb_reg_write(struct bnx2x_softc *sc, uint32_t reg_addr, uint32_t val)
570 REG_WR(sc, reg_addr, val);
574 elink_cb_event_log(__rte_unused struct bnx2x_softc *sc,
575 __rte_unused const elink_log_id_t elink_log_id, ...)
577 PMD_DRV_LOG(DEBUG, sc, "ELINK EVENT LOG (%d)", elink_log_id);
580 static int bnx2x_set_spio(struct bnx2x_softc *sc, int spio, uint32_t mode)
584 /* Only 2 SPIOs are configurable */
585 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
586 PMD_DRV_LOG(NOTICE, sc, "Invalid SPIO 0x%x", spio);
590 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
592 /* read SPIO and mask except the float bits */
593 spio_reg = (REG_RD(sc, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
596 case MISC_SPIO_OUTPUT_LOW:
597 /* clear FLOAT and set CLR */
598 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
599 spio_reg |= (spio << MISC_SPIO_CLR_POS);
602 case MISC_SPIO_OUTPUT_HIGH:
603 /* clear FLOAT and set SET */
604 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
605 spio_reg |= (spio << MISC_SPIO_SET_POS);
608 case MISC_SPIO_INPUT_HI_Z:
610 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
617 REG_WR(sc, MISC_REG_SPIO, spio_reg);
618 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
623 static int bnx2x_gpio_read(struct bnx2x_softc *sc, int gpio_num, uint8_t port)
625 /* The GPIO should be swapped if swap register is set and active */
626 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
627 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
628 int gpio_shift = gpio_num;
630 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
632 uint32_t gpio_mask = (1 << gpio_shift);
635 if (gpio_num > MISC_REGISTERS_GPIO_3) {
636 PMD_DRV_LOG(NOTICE, sc, "Invalid GPIO %d", gpio_num);
640 /* read GPIO value */
641 gpio_reg = REG_RD(sc, MISC_REG_GPIO);
643 /* get the requested pin value */
644 return ((gpio_reg & gpio_mask) == gpio_mask) ? 1 : 0;
648 bnx2x_gpio_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode, uint8_t port)
650 /* The GPIO should be swapped if swap register is set and active */
651 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
652 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
653 int gpio_shift = gpio_num;
655 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
657 uint32_t gpio_mask = (1 << gpio_shift);
660 if (gpio_num > MISC_REGISTERS_GPIO_3) {
661 PMD_DRV_LOG(NOTICE, sc, "Invalid GPIO %d", gpio_num);
665 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
667 /* read GPIO and mask except the float bits */
668 gpio_reg = (REG_RD(sc, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
671 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
672 /* clear FLOAT and set CLR */
673 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
674 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
677 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
678 /* clear FLOAT and set SET */
679 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
680 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
683 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
685 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
692 REG_WR(sc, MISC_REG_GPIO, gpio_reg);
693 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
699 bnx2x_gpio_mult_write(struct bnx2x_softc *sc, uint8_t pins, uint32_t mode)
703 /* any port swapping should be handled by caller */
705 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
707 /* read GPIO and mask except the float bits */
708 gpio_reg = REG_RD(sc, MISC_REG_GPIO);
709 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
710 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
711 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
714 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
716 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
719 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
721 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
724 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
726 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
730 PMD_DRV_LOG(NOTICE, sc,
731 "Invalid GPIO mode assignment %d", mode);
732 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
736 REG_WR(sc, MISC_REG_GPIO, gpio_reg);
737 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
743 bnx2x_gpio_int_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode,
746 /* The GPIO should be swapped if swap register is set and active */
747 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
748 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
749 int gpio_shift = gpio_num;
751 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
753 uint32_t gpio_mask = (1 << gpio_shift);
756 if (gpio_num > MISC_REGISTERS_GPIO_3) {
757 PMD_DRV_LOG(NOTICE, sc, "Invalid GPIO %d", gpio_num);
761 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
764 gpio_reg = REG_RD(sc, MISC_REG_GPIO_INT);
767 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
768 /* clear SET and set CLR */
769 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
770 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
773 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
774 /* clear CLR and set SET */
775 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
776 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
783 REG_WR(sc, MISC_REG_GPIO_INT, gpio_reg);
784 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
790 elink_cb_gpio_read(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t port)
792 return bnx2x_gpio_read(sc, gpio_num, port);
795 uint8_t elink_cb_gpio_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode, /* 0=low 1=high */
798 return bnx2x_gpio_write(sc, gpio_num, mode, port);
802 elink_cb_gpio_mult_write(struct bnx2x_softc * sc, uint8_t pins,
803 uint8_t mode /* 0=low 1=high */ )
805 return bnx2x_gpio_mult_write(sc, pins, mode);
808 uint8_t elink_cb_gpio_int_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode, /* 0=low 1=high */
811 return bnx2x_gpio_int_write(sc, gpio_num, mode, port);
814 void elink_cb_notify_link_changed(struct bnx2x_softc *sc)
816 REG_WR(sc, (MISC_REG_AEU_GENERAL_ATTN_12 +
817 (SC_FUNC(sc) * sizeof(uint32_t))), 1);
820 /* send the MCP a request, block until there is a reply */
822 elink_cb_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
824 int mb_idx = SC_FW_MB_IDX(sc);
828 uint8_t delay = CHIP_REV_IS_SLOW(sc) ? 100 : 10;
831 SHMEM_WR(sc, func_mb[mb_idx].drv_mb_param, param);
832 SHMEM_WR(sc, func_mb[mb_idx].drv_mb_header, (command | seq));
834 PMD_DRV_LOG(DEBUG, sc,
835 "wrote command 0x%08x to FW MB param 0x%08x",
836 (command | seq), param);
838 /* Let the FW do it's magic. GIve it up to 5 seconds... */
841 rc = SHMEM_RD(sc, func_mb[mb_idx].fw_mb_header);
842 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
844 /* is this a reply to our command? */
845 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) {
846 rc &= FW_MSG_CODE_MASK;
849 PMD_DRV_LOG(NOTICE, sc, "FW failed to respond!");
857 bnx2x_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
859 return elink_cb_fw_command(sc, command, param);
863 __storm_memset_dma_mapping(struct bnx2x_softc *sc, uint32_t addr,
866 REG_WR(sc, addr, U64_LO(mapping));
867 REG_WR(sc, (addr + 4), U64_HI(mapping));
871 storm_memset_spq_addr(struct bnx2x_softc *sc, rte_iova_t mapping,
874 uint32_t addr = (XSEM_REG_FAST_MEMORY +
875 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid));
876 __storm_memset_dma_mapping(sc, addr, mapping);
880 storm_memset_vf_to_pf(struct bnx2x_softc *sc, uint16_t abs_fid, uint16_t pf_id)
882 REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid)),
884 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid)),
886 REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid)),
888 REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid)),
893 storm_memset_func_en(struct bnx2x_softc *sc, uint16_t abs_fid, uint8_t enable)
895 REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid)),
897 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid)),
899 REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid)),
901 REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid)),
906 storm_memset_eq_data(struct bnx2x_softc *sc, struct event_ring_data *eq_data,
912 addr = (BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid));
913 size = sizeof(struct event_ring_data);
914 ecore_storm_memset_struct(sc, addr, size, (uint32_t *) eq_data);
918 storm_memset_eq_prod(struct bnx2x_softc *sc, uint16_t eq_prod, uint16_t pfid)
920 uint32_t addr = (BAR_CSTRORM_INTMEM +
921 CSTORM_EVENT_RING_PROD_OFFSET(pfid));
922 REG_WR16(sc, addr, eq_prod);
926 * Post a slowpath command.
928 * A slowpath command is used to propagate a configuration change through
929 * the controller in a controlled manner, allowing each STORM processor and
930 * other H/W blocks to phase in the change. The commands sent on the
931 * slowpath are referred to as ramrods. Depending on the ramrod used the
932 * completion of the ramrod will occur in different ways. Here's a
933 * breakdown of ramrods and how they complete:
935 * RAMROD_CMD_ID_ETH_PORT_SETUP
936 * Used to setup the leading connection on a port. Completes on the
937 * Receive Completion Queue (RCQ) of that port (typically fp[0]).
939 * RAMROD_CMD_ID_ETH_CLIENT_SETUP
940 * Used to setup an additional connection on a port. Completes on the
941 * RCQ of the multi-queue/RSS connection being initialized.
943 * RAMROD_CMD_ID_ETH_STAT_QUERY
944 * Used to force the storm processors to update the statistics database
945 * in host memory. This ramrod is send on the leading connection CID and
946 * completes as an index increment of the CSTORM on the default status
949 * RAMROD_CMD_ID_ETH_UPDATE
950 * Used to update the state of the leading connection, usually to udpate
951 * the RSS indirection table. Completes on the RCQ of the leading
952 * connection. (Not currently used under FreeBSD until OS support becomes
955 * RAMROD_CMD_ID_ETH_HALT
956 * Used when tearing down a connection prior to driver unload. Completes
957 * on the RCQ of the multi-queue/RSS connection being torn down. Don't
958 * use this on the leading connection.
960 * RAMROD_CMD_ID_ETH_SET_MAC
961 * Sets the Unicast/Broadcast/Multicast used by the port. Completes on
962 * the RCQ of the leading connection.
964 * RAMROD_CMD_ID_ETH_CFC_DEL
965 * Used when tearing down a conneciton prior to driver unload. Completes
966 * on the RCQ of the leading connection (since the current connection
967 * has been completely removed from controller memory).
969 * RAMROD_CMD_ID_ETH_PORT_DEL
970 * Used to tear down the leading connection prior to driver unload,
971 * typically fp[0]. Completes as an index increment of the CSTORM on the
972 * default status block.
974 * RAMROD_CMD_ID_ETH_FORWARD_SETUP
975 * Used for connection offload. Completes on the RCQ of the multi-queue
976 * RSS connection that is being offloaded. (Not currently used under
979 * There can only be one command pending per function.
982 * 0 = Success, !0 = Failure.
985 /* must be called under the spq lock */
986 static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x_softc *sc)
988 struct eth_spe *next_spe = sc->spq_prod_bd;
990 if (sc->spq_prod_bd == sc->spq_last_bd) {
991 /* wrap back to the first eth_spq */
992 sc->spq_prod_bd = sc->spq;
993 sc->spq_prod_idx = 0;
1002 /* must be called under the spq lock */
1003 static void bnx2x_sp_prod_update(struct bnx2x_softc *sc)
1005 int func = SC_FUNC(sc);
1008 * Make sure that BD data is updated before writing the producer.
1009 * BD data is written to the memory, the producer is read from the
1010 * memory, thus we need a full memory barrier to ensure the ordering.
1014 REG_WR16(sc, (BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func)),
1021 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
1023 * @cmd: command to check
1024 * @cmd_type: command type
1026 static int bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
1028 if ((cmd_type == NONE_CONNECTION_TYPE) ||
1029 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
1030 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
1031 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
1032 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
1033 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
1034 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) {
1042 * bnx2x_sp_post - place a single command on an SP ring
1044 * @sc: driver handle
1045 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
1046 * @cid: SW CID the command is related to
1047 * @data_hi: command private data address (high 32 bits)
1048 * @data_lo: command private data address (low 32 bits)
1049 * @cmd_type: command type (e.g. NONE, ETH)
1051 * SP data is handled as if it's always an address pair, thus data fields are
1052 * not swapped to little endian in upper functions. Instead this function swaps
1053 * data as if it's two uint32 fields.
1056 bnx2x_sp_post(struct bnx2x_softc *sc, int command, int cid, uint32_t data_hi,
1057 uint32_t data_lo, int cmd_type)
1059 struct eth_spe *spe;
1063 common = bnx2x_is_contextless_ramrod(command, cmd_type);
1066 if (!atomic_load_acq_long(&sc->eq_spq_left)) {
1067 PMD_DRV_LOG(INFO, sc, "EQ ring is full!");
1071 if (!atomic_load_acq_long(&sc->cq_spq_left)) {
1072 PMD_DRV_LOG(INFO, sc, "SPQ ring is full!");
1077 spe = bnx2x_sp_get_next(sc);
1079 /* CID needs port number to be encoded int it */
1080 spe->hdr.conn_and_cmd_data =
1081 htole32((command << SPE_HDR_CMD_ID_SHIFT) | HW_CID(sc, cid));
1083 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
1085 /* TBD: Check if it works for VFs */
1086 type |= ((SC_FUNC(sc) << SPE_HDR_FUNCTION_ID_SHIFT) &
1087 SPE_HDR_FUNCTION_ID);
1089 spe->hdr.type = htole16(type);
1091 spe->data.update_data_addr.hi = htole32(data_hi);
1092 spe->data.update_data_addr.lo = htole32(data_lo);
1095 * It's ok if the actual decrement is issued towards the memory
1096 * somewhere between the lock and unlock. Thus no more explict
1097 * memory barrier is needed.
1100 atomic_subtract_acq_long(&sc->eq_spq_left, 1);
1102 atomic_subtract_acq_long(&sc->cq_spq_left, 1);
1105 PMD_DRV_LOG(DEBUG, sc,
1106 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x"
1107 "data (%x:%x) type(0x%x) left (CQ, EQ) (%lx,%lx)",
1109 (uint32_t) U64_HI(sc->spq_dma.paddr),
1110 (uint32_t) (U64_LO(sc->spq_dma.paddr) +
1111 (uint8_t *) sc->spq_prod_bd -
1112 (uint8_t *) sc->spq), command, common,
1113 HW_CID(sc, cid), data_hi, data_lo, type,
1114 atomic_load_acq_long(&sc->cq_spq_left),
1115 atomic_load_acq_long(&sc->eq_spq_left));
1117 /* RAMROD completion is processed in bnx2x_intr_legacy()
1118 * which can run from different contexts.
1119 * Ask bnx2x_intr_intr() to process RAMROD
1120 * completion whenever it gets scheduled.
1122 rte_atomic32_set(&sc->scan_fp, 1);
1123 bnx2x_sp_prod_update(sc);
1128 static void bnx2x_drv_pulse(struct bnx2x_softc *sc)
1130 SHMEM_WR(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb,
1131 sc->fw_drv_pulse_wr_seq);
1134 static int bnx2x_tx_queue_has_work(const struct bnx2x_fastpath *fp)
1137 struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1139 if (unlikely(!txq)) {
1140 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1144 mb(); /* status block fields can change */
1145 hw_cons = le16toh(*fp->tx_cons_sb);
1146 return hw_cons != txq->tx_pkt_head;
1149 static uint8_t bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
1151 /* expand this for multi-cos if ever supported */
1152 return bnx2x_tx_queue_has_work(fp);
1155 static int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
1157 uint16_t rx_cq_cons_sb;
1158 struct bnx2x_rx_queue *rxq;
1159 rxq = fp->sc->rx_queues[fp->index];
1160 if (unlikely(!rxq)) {
1161 PMD_RX_LOG(ERR, "ERROR: RX queue is NULL");
1165 mb(); /* status block fields can change */
1166 rx_cq_cons_sb = le16toh(*fp->rx_cq_cons_sb);
1167 if (unlikely((rx_cq_cons_sb & MAX_RCQ_ENTRIES(rxq)) ==
1168 MAX_RCQ_ENTRIES(rxq)))
1171 PMD_RX_LOG(DEBUG, "hw CQ cons = %d, sw CQ cons = %d",
1172 rx_cq_cons_sb, rxq->rx_cq_head);
1174 return rxq->rx_cq_head != rx_cq_cons_sb;
1178 bnx2x_sp_event(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
1179 union eth_rx_cqe *rr_cqe)
1181 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1182 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1183 enum ecore_queue_cmd drv_cmd = ECORE_Q_CMD_MAX;
1184 struct ecore_queue_sp_obj *q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
1186 PMD_DRV_LOG(DEBUG, sc,
1187 "fp=%d cid=%d got ramrod #%d state is %x type is %d",
1188 fp->index, cid, command, sc->state,
1189 rr_cqe->ramrod_cqe.ramrod_type);
1192 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1193 PMD_DRV_LOG(DEBUG, sc, "got UPDATE ramrod. CID %d", cid);
1194 drv_cmd = ECORE_Q_CMD_UPDATE;
1197 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1198 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] setup ramrod", cid);
1199 drv_cmd = ECORE_Q_CMD_SETUP;
1202 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1203 PMD_DRV_LOG(DEBUG, sc,
1204 "got MULTI[%d] tx-only setup ramrod", cid);
1205 drv_cmd = ECORE_Q_CMD_SETUP_TX_ONLY;
1208 case (RAMROD_CMD_ID_ETH_HALT):
1209 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] halt ramrod", cid);
1210 drv_cmd = ECORE_Q_CMD_HALT;
1213 case (RAMROD_CMD_ID_ETH_TERMINATE):
1214 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] teminate ramrod", cid);
1215 drv_cmd = ECORE_Q_CMD_TERMINATE;
1218 case (RAMROD_CMD_ID_ETH_EMPTY):
1219 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] empty ramrod", cid);
1220 drv_cmd = ECORE_Q_CMD_EMPTY;
1224 PMD_DRV_LOG(DEBUG, sc,
1225 "ERROR: unexpected MC reply (%d)"
1226 "on fp[%d]", command, fp->index);
1230 if ((drv_cmd != ECORE_Q_CMD_MAX) &&
1231 q_obj->complete_cmd(sc, q_obj, drv_cmd)) {
1233 * q_obj->complete_cmd() failure means that this was
1234 * an unexpected completion.
1236 * In this case we don't want to increase the sc->spq_left
1237 * because apparently we haven't sent this command the first
1240 // rte_panic("Unexpected SP completion");
1244 atomic_add_acq_long(&sc->cq_spq_left, 1);
1246 PMD_DRV_LOG(DEBUG, sc, "sc->cq_spq_left 0x%lx",
1247 atomic_load_acq_long(&sc->cq_spq_left));
1250 static uint8_t bnx2x_rxeof(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
1252 struct bnx2x_rx_queue *rxq;
1253 uint16_t bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
1254 uint16_t hw_cq_cons, sw_cq_cons, sw_cq_prod;
1256 rte_spinlock_lock(&(fp)->rx_mtx);
1258 rxq = sc->rx_queues[fp->index];
1260 PMD_RX_LOG(ERR, "RX queue %d is NULL", fp->index);
1261 rte_spinlock_unlock(&(fp)->rx_mtx);
1265 /* CQ "next element" is of the size of the regular element */
1266 hw_cq_cons = le16toh(*fp->rx_cq_cons_sb);
1267 if (unlikely((hw_cq_cons & USABLE_RCQ_ENTRIES_PER_PAGE) ==
1268 USABLE_RCQ_ENTRIES_PER_PAGE)) {
1272 bd_cons = rxq->rx_bd_head;
1273 bd_prod = rxq->rx_bd_tail;
1274 bd_prod_fw = bd_prod;
1275 sw_cq_cons = rxq->rx_cq_head;
1276 sw_cq_prod = rxq->rx_cq_tail;
1279 * Memory barrier necessary as speculative reads of the rx
1280 * buffer can be ahead of the index in the status block
1284 while (sw_cq_cons != hw_cq_cons) {
1285 union eth_rx_cqe *cqe;
1286 struct eth_fast_path_rx_cqe *cqe_fp;
1287 uint8_t cqe_fp_flags;
1288 enum eth_rx_cqe_type cqe_fp_type;
1290 comp_ring_cons = RCQ_ENTRY(sw_cq_cons, rxq);
1291 bd_prod = RX_BD(bd_prod, rxq);
1292 bd_cons = RX_BD(bd_cons, rxq);
1294 cqe = &rxq->cq_ring[comp_ring_cons];
1295 cqe_fp = &cqe->fast_path_cqe;
1296 cqe_fp_flags = cqe_fp->type_error_flags;
1297 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
1299 /* is this a slowpath msg? */
1300 if (CQE_TYPE_SLOW(cqe_fp_type)) {
1301 bnx2x_sp_event(sc, fp, cqe);
1305 /* is this an error packet? */
1306 if (unlikely(cqe_fp_flags &
1307 ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG)) {
1308 PMD_RX_LOG(DEBUG, "flags 0x%x rx packet %u",
1309 cqe_fp_flags, sw_cq_cons);
1313 PMD_RX_LOG(DEBUG, "Dropping fastpath called from attn poller!");
1316 bd_cons = NEXT_RX_BD(bd_cons);
1317 bd_prod = NEXT_RX_BD(bd_prod);
1318 bd_prod_fw = NEXT_RX_BD(bd_prod_fw);
1321 sw_cq_prod = NEXT_RCQ_IDX(sw_cq_prod);
1322 sw_cq_cons = NEXT_RCQ_IDX(sw_cq_cons);
1324 } /* while work to do */
1326 rxq->rx_bd_head = bd_cons;
1327 rxq->rx_bd_tail = bd_prod_fw;
1328 rxq->rx_cq_head = sw_cq_cons;
1329 rxq->rx_cq_tail = sw_cq_prod;
1331 PMD_RX_LOG(DEBUG, "BD prod = %d, sw CQ prod = %d",
1332 bd_prod_fw, sw_cq_prod);
1334 /* Update producers */
1335 bnx2x_update_rx_prod(sc, fp, bd_prod_fw, sw_cq_prod);
1337 rte_spinlock_unlock(&(fp)->rx_mtx);
1339 return sw_cq_cons != hw_cq_cons;
1343 bnx2x_free_tx_pkt(__rte_unused struct bnx2x_fastpath *fp, struct bnx2x_tx_queue *txq,
1344 uint16_t pkt_idx, uint16_t bd_idx)
1346 struct eth_tx_start_bd *tx_start_bd =
1347 &txq->tx_ring[TX_BD(bd_idx, txq)].start_bd;
1348 uint16_t nbd = rte_le_to_cpu_16(tx_start_bd->nbd);
1349 struct rte_mbuf *tx_mbuf = txq->sw_ring[TX_BD(pkt_idx, txq)];
1351 if (likely(tx_mbuf != NULL)) {
1352 rte_pktmbuf_free_seg(tx_mbuf);
1354 PMD_RX_LOG(ERR, "fp[%02d] lost mbuf %lu",
1355 fp->index, (unsigned long)TX_BD(pkt_idx, txq));
1358 txq->sw_ring[TX_BD(pkt_idx, txq)] = NULL;
1359 txq->nb_tx_avail += nbd;
1362 bd_idx = NEXT_TX_BD(bd_idx);
1367 /* processes transmit completions */
1368 uint8_t bnx2x_txeof(__rte_unused struct bnx2x_softc * sc, struct bnx2x_fastpath * fp)
1370 uint16_t bd_cons, hw_cons, sw_cons;
1371 __rte_unused uint16_t tx_bd_avail;
1373 struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1375 if (unlikely(!txq)) {
1376 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1380 bd_cons = txq->tx_bd_head;
1381 hw_cons = rte_le_to_cpu_16(*fp->tx_cons_sb);
1382 sw_cons = txq->tx_pkt_head;
1384 while (sw_cons != hw_cons) {
1385 bd_cons = bnx2x_free_tx_pkt(fp, txq, sw_cons, bd_cons);
1389 txq->tx_pkt_head = sw_cons;
1390 txq->tx_bd_head = bd_cons;
1392 tx_bd_avail = txq->nb_tx_avail;
1394 PMD_TX_LOG(DEBUG, "fp[%02d] avail=%u cons_sb=%u, "
1395 "pkt_head=%u pkt_tail=%u bd_head=%u bd_tail=%u",
1396 fp->index, tx_bd_avail, hw_cons,
1397 txq->tx_pkt_head, txq->tx_pkt_tail,
1398 txq->tx_bd_head, txq->tx_bd_tail);
1402 static void bnx2x_drain_tx_queues(struct bnx2x_softc *sc)
1404 struct bnx2x_fastpath *fp;
1407 /* wait until all TX fastpath tasks have completed */
1408 for (i = 0; i < sc->num_queues; i++) {
1413 while (bnx2x_has_tx_work(fp)) {
1414 bnx2x_txeof(sc, fp);
1418 "Timeout waiting for fp[%d] "
1419 "transmits to complete!", i);
1420 rte_panic("tx drain failure");
1434 bnx2x_del_all_macs(struct bnx2x_softc *sc, struct ecore_vlan_mac_obj *mac_obj,
1435 int mac_type, uint8_t wait_for_comp)
1437 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1440 /* wait for completion of requested */
1441 if (wait_for_comp) {
1442 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1445 /* Set the mac type of addresses we want to clear */
1446 bnx2x_set_bit(mac_type, &vlan_mac_flags);
1448 rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1450 PMD_DRV_LOG(ERR, sc, "Failed to delete MACs (%d)", rc);
1456 bnx2x_fill_accept_flags(struct bnx2x_softc *sc, uint32_t rx_mode,
1457 unsigned long *rx_accept_flags,
1458 unsigned long *tx_accept_flags)
1460 /* Clear the flags first */
1461 *rx_accept_flags = 0;
1462 *tx_accept_flags = 0;
1465 case BNX2X_RX_MODE_NONE:
1467 * 'drop all' supersedes any accept flags that may have been
1468 * passed to the function.
1472 case BNX2X_RX_MODE_NORMAL:
1473 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1474 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, rx_accept_flags);
1475 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1477 /* internal switching mode */
1478 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1479 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, tx_accept_flags);
1480 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1484 case BNX2X_RX_MODE_ALLMULTI:
1485 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1486 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1487 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1489 /* internal switching mode */
1490 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1491 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1492 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1496 case BNX2X_RX_MODE_ALLMULTI_PROMISC:
1497 case BNX2X_RX_MODE_PROMISC:
1499 * According to deffinition of SI mode, iface in promisc mode
1500 * should receive matched and unmatched (in resolution of port)
1503 bnx2x_set_bit(ECORE_ACCEPT_UNMATCHED, rx_accept_flags);
1504 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1505 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1506 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1508 /* internal switching mode */
1509 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1510 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1513 bnx2x_set_bit(ECORE_ACCEPT_ALL_UNICAST, tx_accept_flags);
1515 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1521 PMD_RX_LOG(ERR, "Unknown rx_mode (%d)", rx_mode);
1525 /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
1526 if (rx_mode != BNX2X_RX_MODE_NONE) {
1527 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, rx_accept_flags);
1528 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, tx_accept_flags);
1535 bnx2x_set_q_rx_mode(struct bnx2x_softc *sc, uint8_t cl_id,
1536 unsigned long rx_mode_flags,
1537 unsigned long rx_accept_flags,
1538 unsigned long tx_accept_flags, unsigned long ramrod_flags)
1540 struct ecore_rx_mode_ramrod_params ramrod_param;
1543 memset(&ramrod_param, 0, sizeof(ramrod_param));
1545 /* Prepare ramrod parameters */
1546 ramrod_param.cid = 0;
1547 ramrod_param.cl_id = cl_id;
1548 ramrod_param.rx_mode_obj = &sc->rx_mode_obj;
1549 ramrod_param.func_id = SC_FUNC(sc);
1551 ramrod_param.pstate = &sc->sp_state;
1552 ramrod_param.state = ECORE_FILTER_RX_MODE_PENDING;
1554 ramrod_param.rdata = BNX2X_SP(sc, rx_mode_rdata);
1555 ramrod_param.rdata_mapping =
1556 (rte_iova_t)BNX2X_SP_MAPPING(sc, rx_mode_rdata),
1557 bnx2x_set_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
1559 ramrod_param.ramrod_flags = ramrod_flags;
1560 ramrod_param.rx_mode_flags = rx_mode_flags;
1562 ramrod_param.rx_accept_flags = rx_accept_flags;
1563 ramrod_param.tx_accept_flags = tx_accept_flags;
1565 rc = ecore_config_rx_mode(sc, &ramrod_param);
1567 PMD_RX_LOG(ERR, "Set rx_mode %d failed", sc->rx_mode);
1574 int bnx2x_set_storm_rx_mode(struct bnx2x_softc *sc)
1576 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
1577 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
1580 rc = bnx2x_fill_accept_flags(sc, sc->rx_mode, &rx_accept_flags,
1586 bnx2x_set_bit(RAMROD_RX, &ramrod_flags);
1587 bnx2x_set_bit(RAMROD_TX, &ramrod_flags);
1588 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1590 return bnx2x_set_q_rx_mode(sc, sc->fp[0].cl_id, rx_mode_flags,
1591 rx_accept_flags, tx_accept_flags,
1595 /* returns the "mcp load_code" according to global load_count array */
1596 static int bnx2x_nic_load_no_mcp(struct bnx2x_softc *sc)
1598 int path = SC_PATH(sc);
1599 int port = SC_PORT(sc);
1601 PMD_DRV_LOG(INFO, sc, "NO MCP - load counts[%d] %d, %d, %d",
1602 path, load_count[path][0], load_count[path][1],
1603 load_count[path][2]);
1605 load_count[path][0]++;
1606 load_count[path][1 + port]++;
1607 PMD_DRV_LOG(INFO, sc, "NO MCP - new load counts[%d] %d, %d, %d",
1608 path, load_count[path][0], load_count[path][1],
1609 load_count[path][2]);
1610 if (load_count[path][0] == 1)
1611 return FW_MSG_CODE_DRV_LOAD_COMMON;
1612 else if (load_count[path][1 + port] == 1)
1613 return FW_MSG_CODE_DRV_LOAD_PORT;
1615 return FW_MSG_CODE_DRV_LOAD_FUNCTION;
1618 /* returns the "mcp load_code" according to global load_count array */
1619 static int bnx2x_nic_unload_no_mcp(struct bnx2x_softc *sc)
1621 int port = SC_PORT(sc);
1622 int path = SC_PATH(sc);
1624 PMD_DRV_LOG(INFO, sc, "NO MCP - load counts[%d] %d, %d, %d",
1625 path, load_count[path][0], load_count[path][1],
1626 load_count[path][2]);
1627 load_count[path][0]--;
1628 load_count[path][1 + port]--;
1629 PMD_DRV_LOG(INFO, sc, "NO MCP - new load counts[%d] %d, %d, %d",
1630 path, load_count[path][0], load_count[path][1],
1631 load_count[path][2]);
1632 if (load_count[path][0] == 0) {
1633 return FW_MSG_CODE_DRV_UNLOAD_COMMON;
1634 } else if (load_count[path][1 + port] == 0) {
1635 return FW_MSG_CODE_DRV_UNLOAD_PORT;
1637 return FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
1641 /* request unload mode from the MCP: COMMON, PORT or FUNCTION */
1642 static uint32_t bnx2x_send_unload_req(struct bnx2x_softc *sc, int unload_mode)
1644 uint32_t reset_code = 0;
1646 /* Select the UNLOAD request mode */
1647 if (unload_mode == UNLOAD_NORMAL) {
1648 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1650 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1653 /* Send the request to the MCP */
1654 if (!BNX2X_NOMCP(sc)) {
1655 reset_code = bnx2x_fw_command(sc, reset_code, 0);
1657 reset_code = bnx2x_nic_unload_no_mcp(sc);
1663 /* send UNLOAD_DONE command to the MCP */
1664 static void bnx2x_send_unload_done(struct bnx2x_softc *sc, uint8_t keep_link)
1666 uint32_t reset_param =
1667 keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
1669 /* Report UNLOAD_DONE to MCP */
1670 if (!BNX2X_NOMCP(sc)) {
1671 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
1675 static int bnx2x_func_wait_started(struct bnx2x_softc *sc)
1679 if (!sc->port.pmf) {
1684 * (assumption: No Attention from MCP at this stage)
1685 * PMF probably in the middle of TX disable/enable transaction
1686 * 1. Sync IRS for default SB
1687 * 2. Sync SP queue - this guarantees us that attention handling started
1688 * 3. Wait, that TX disable/enable transaction completes
1690 * 1+2 guarantee that if DCBX attention was scheduled it already changed
1691 * pending bit of transaction from STARTED-->TX_STOPPED, if we already
1692 * received completion for the transaction the state is TX_STOPPED.
1693 * State will return to STARTED after completion of TX_STOPPED-->STARTED
1697 while (ecore_func_get_state(sc, &sc->func_obj) !=
1698 ECORE_F_STATE_STARTED && tout--) {
1702 if (ecore_func_get_state(sc, &sc->func_obj) != ECORE_F_STATE_STARTED) {
1704 * Failed to complete the transaction in a "good way"
1705 * Force both transactions with CLR bit.
1707 struct ecore_func_state_params func_params = { NULL };
1709 PMD_DRV_LOG(NOTICE, sc, "Unexpected function state! "
1710 "Forcing STARTED-->TX_STOPPED-->STARTED");
1712 func_params.f_obj = &sc->func_obj;
1713 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1715 /* STARTED-->TX_STOPPED */
1716 func_params.cmd = ECORE_F_CMD_TX_STOP;
1717 ecore_func_state_change(sc, &func_params);
1719 /* TX_STOPPED-->STARTED */
1720 func_params.cmd = ECORE_F_CMD_TX_START;
1721 return ecore_func_state_change(sc, &func_params);
1727 static int bnx2x_stop_queue(struct bnx2x_softc *sc, int index)
1729 struct bnx2x_fastpath *fp = &sc->fp[index];
1730 struct ecore_queue_state_params q_params = { NULL };
1733 PMD_DRV_LOG(DEBUG, sc, "stopping queue %d cid %d", index, fp->index);
1735 q_params.q_obj = &sc->sp_objs[fp->index].q_obj;
1736 /* We want to wait for completion in this context */
1737 bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
1739 /* Stop the primary connection: */
1741 /* ...halt the connection */
1742 q_params.cmd = ECORE_Q_CMD_HALT;
1743 rc = ecore_queue_state_change(sc, &q_params);
1748 /* ...terminate the connection */
1749 q_params.cmd = ECORE_Q_CMD_TERMINATE;
1750 memset(&q_params.params.terminate, 0,
1751 sizeof(q_params.params.terminate));
1752 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
1753 rc = ecore_queue_state_change(sc, &q_params);
1758 /* ...delete cfc entry */
1759 q_params.cmd = ECORE_Q_CMD_CFC_DEL;
1760 memset(&q_params.params.cfc_del, 0, sizeof(q_params.params.cfc_del));
1761 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
1762 return ecore_queue_state_change(sc, &q_params);
1765 /* wait for the outstanding SP commands */
1766 static uint8_t bnx2x_wait_sp_comp(struct bnx2x_softc *sc, unsigned long mask)
1769 int tout = 5000; /* wait for 5 secs tops */
1773 if (!(atomic_load_acq_long(&sc->sp_state) & mask)) {
1782 tmp = atomic_load_acq_long(&sc->sp_state);
1784 PMD_DRV_LOG(INFO, sc, "Filtering completion timed out: "
1785 "sp_state 0x%lx, mask 0x%lx", tmp, mask);
1792 static int bnx2x_func_stop(struct bnx2x_softc *sc)
1794 struct ecore_func_state_params func_params = { NULL };
1797 /* prepare parameters for function state transitions */
1798 bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1799 func_params.f_obj = &sc->func_obj;
1800 func_params.cmd = ECORE_F_CMD_STOP;
1803 * Try to stop the function the 'good way'. If it fails (in case
1804 * of a parity error during bnx2x_chip_cleanup()) and we are
1805 * not in a debug mode, perform a state transaction in order to
1806 * enable further HW_RESET transaction.
1808 rc = ecore_func_state_change(sc, &func_params);
1810 PMD_DRV_LOG(NOTICE, sc, "FUNC_STOP ramrod failed. "
1811 "Running a dry transaction");
1812 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1813 return ecore_func_state_change(sc, &func_params);
1819 static int bnx2x_reset_hw(struct bnx2x_softc *sc, uint32_t load_code)
1821 struct ecore_func_state_params func_params = { NULL };
1823 /* Prepare parameters for function state transitions */
1824 bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1826 func_params.f_obj = &sc->func_obj;
1827 func_params.cmd = ECORE_F_CMD_HW_RESET;
1829 func_params.params.hw_init.load_phase = load_code;
1831 return ecore_func_state_change(sc, &func_params);
1834 static void bnx2x_int_disable_sync(struct bnx2x_softc *sc, int disable_hw)
1837 /* prevent the HW from sending interrupts */
1838 bnx2x_int_disable(sc);
1843 bnx2x_chip_cleanup(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1845 int port = SC_PORT(sc);
1846 struct ecore_mcast_ramrod_params rparam = { NULL };
1847 uint32_t reset_code;
1850 bnx2x_drain_tx_queues(sc);
1852 /* give HW time to discard old tx messages */
1855 /* Clean all ETH MACs */
1856 rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_ETH_MAC,
1859 PMD_DRV_LOG(NOTICE, sc,
1860 "Failed to delete all ETH MACs (%d)", rc);
1863 /* Clean up UC list */
1864 rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_UC_LIST_MAC,
1867 PMD_DRV_LOG(NOTICE, sc,
1868 "Failed to delete UC MACs list (%d)", rc);
1872 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
1874 /* Set "drop all" to stop Rx */
1877 * We need to take the if_maddr_lock() here in order to prevent
1878 * a race between the completion code and this code.
1881 if (bnx2x_test_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) {
1882 bnx2x_set_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state);
1884 bnx2x_set_storm_rx_mode(sc);
1887 /* Clean up multicast configuration */
1888 rparam.mcast_obj = &sc->mcast_obj;
1889 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1891 PMD_DRV_LOG(NOTICE, sc,
1892 "Failed to send DEL MCAST command (%d)", rc);
1896 * Send the UNLOAD_REQUEST to the MCP. This will return if
1897 * this function should perform FUNCTION, PORT, or COMMON HW
1900 reset_code = bnx2x_send_unload_req(sc, unload_mode);
1903 * (assumption: No Attention from MCP at this stage)
1904 * PMF probably in the middle of TX disable/enable transaction
1906 rc = bnx2x_func_wait_started(sc);
1908 PMD_DRV_LOG(NOTICE, sc, "bnx2x_func_wait_started failed");
1912 * Close multi and leading connections
1913 * Completions for ramrods are collected in a synchronous way
1915 for (i = 0; i < sc->num_queues; i++) {
1916 if (bnx2x_stop_queue(sc, i)) {
1922 * If SP settings didn't get completed so far - something
1923 * very wrong has happen.
1925 if (!bnx2x_wait_sp_comp(sc, ~0x0UL)) {
1926 PMD_DRV_LOG(NOTICE, sc, "Common slow path ramrods got stuck!");
1931 rc = bnx2x_func_stop(sc);
1933 PMD_DRV_LOG(NOTICE, sc, "Function stop failed!");
1936 /* disable HW interrupts */
1937 bnx2x_int_disable_sync(sc, TRUE);
1939 /* Reset the chip */
1940 rc = bnx2x_reset_hw(sc, reset_code);
1942 PMD_DRV_LOG(NOTICE, sc, "Hardware reset failed");
1945 /* Report UNLOAD_DONE to MCP */
1946 bnx2x_send_unload_done(sc, keep_link);
1949 static void bnx2x_disable_close_the_gate(struct bnx2x_softc *sc)
1953 PMD_DRV_LOG(DEBUG, sc, "Disabling 'close the gates'");
1955 val = REG_RD(sc, MISC_REG_AEU_GENERAL_MASK);
1956 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
1957 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
1958 REG_WR(sc, MISC_REG_AEU_GENERAL_MASK, val);
1962 * Cleans the object that have internal lists without sending
1963 * ramrods. Should be run when interrutps are disabled.
1965 static void bnx2x_squeeze_objects(struct bnx2x_softc *sc)
1967 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1968 struct ecore_mcast_ramrod_params rparam = { NULL };
1969 struct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj;
1972 /* Cleanup MACs' object first... */
1974 /* Wait for completion of requested */
1975 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1976 /* Perform a dry cleanup */
1977 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &ramrod_flags);
1979 /* Clean ETH primary MAC */
1980 bnx2x_set_bit(ECORE_ETH_MAC, &vlan_mac_flags);
1981 rc = mac_obj->delete_all(sc, &sc->sp_objs->mac_obj, &vlan_mac_flags,
1984 PMD_DRV_LOG(NOTICE, sc, "Failed to clean ETH MACs (%d)", rc);
1987 /* Cleanup UC list */
1989 bnx2x_set_bit(ECORE_UC_LIST_MAC, &vlan_mac_flags);
1990 rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1992 PMD_DRV_LOG(NOTICE, sc,
1993 "Failed to clean UC list MACs (%d)", rc);
1996 /* Now clean mcast object... */
1998 rparam.mcast_obj = &sc->mcast_obj;
1999 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags);
2001 /* Add a DEL command... */
2002 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
2004 PMD_DRV_LOG(NOTICE, sc,
2005 "Failed to send DEL MCAST command (%d)", rc);
2008 /* now wait until all pending commands are cleared */
2010 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
2013 PMD_DRV_LOG(NOTICE, sc,
2014 "Failed to clean MCAST object (%d)", rc);
2018 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
2022 /* stop the controller */
2025 bnx2x_nic_unload(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
2027 uint8_t global = FALSE;
2030 PMD_INIT_FUNC_TRACE(sc);
2032 PMD_DRV_LOG(DEBUG, sc, "Starting NIC unload...");
2034 /* mark driver as unloaded in shmem2 */
2035 if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
2036 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
2037 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
2038 val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
2041 if (IS_PF(sc) && sc->recovery_state != BNX2X_RECOVERY_DONE &&
2042 (sc->state == BNX2X_STATE_CLOSED || sc->state == BNX2X_STATE_ERROR)) {
2044 * We can get here if the driver has been unloaded
2045 * during parity error recovery and is either waiting for a
2046 * leader to complete or for other functions to unload and
2047 * then ifconfig down has been issued. In this case we want to
2048 * unload and let other functions to complete a recovery
2051 sc->recovery_state = BNX2X_RECOVERY_DONE;
2053 bnx2x_release_leader_lock(sc);
2056 PMD_DRV_LOG(NOTICE, sc, "Can't unload in closed or error state");
2061 * Nothing to do during unload if previous bnx2x_nic_load()
2062 * did not completed successfully - all resourses are released.
2064 if ((sc->state == BNX2X_STATE_CLOSED) || (sc->state == BNX2X_STATE_ERROR)) {
2068 sc->state = BNX2X_STATE_CLOSING_WAITING_HALT;
2071 sc->rx_mode = BNX2X_RX_MODE_NONE;
2072 bnx2x_set_rx_mode(sc);
2076 /* set ALWAYS_ALIVE bit in shmem */
2077 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2079 bnx2x_drv_pulse(sc);
2081 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2082 bnx2x_save_statistics(sc);
2085 /* wait till consumers catch up with producers in all queues */
2086 bnx2x_drain_tx_queues(sc);
2088 /* if VF indicate to PF this function is going down (PF will delete sp
2089 * elements and clear initializations
2092 bnx2x_vf_unload(sc);
2093 } else if (unload_mode != UNLOAD_RECOVERY) {
2094 /* if this is a normal/close unload need to clean up chip */
2095 bnx2x_chip_cleanup(sc, unload_mode, keep_link);
2097 /* Send the UNLOAD_REQUEST to the MCP */
2098 bnx2x_send_unload_req(sc, unload_mode);
2101 * Prevent transactions to host from the functions on the
2102 * engine that doesn't reset global blocks in case of global
2103 * attention once gloabl blocks are reset and gates are opened
2104 * (the engine which leader will perform the recovery
2107 if (!CHIP_IS_E1x(sc)) {
2108 bnx2x_pf_disable(sc);
2111 /* disable HW interrupts */
2112 bnx2x_int_disable_sync(sc, TRUE);
2114 /* Report UNLOAD_DONE to MCP */
2115 bnx2x_send_unload_done(sc, FALSE);
2119 * At this stage no more interrupts will arrive so we may safely clean
2120 * the queue'able objects here in case they failed to get cleaned so far.
2123 bnx2x_squeeze_objects(sc);
2126 /* There should be no more pending SP commands at this stage */
2135 /* free the host hardware/software hsi structures */
2136 bnx2x_free_hsi_mem(sc);
2138 bnx2x_free_fw_stats_mem(sc);
2140 sc->state = BNX2X_STATE_CLOSED;
2143 * Check if there are pending parity attentions. If there are - set
2144 * RECOVERY_IN_PROGRESS.
2146 if (IS_PF(sc) && bnx2x_chk_parity_attn(sc, &global, FALSE)) {
2147 bnx2x_set_reset_in_progress(sc);
2149 /* Set RESET_IS_GLOBAL if needed */
2151 bnx2x_set_reset_global(sc);
2156 * The last driver must disable a "close the gate" if there is no
2157 * parity attention or "process kill" pending.
2159 if (IS_PF(sc) && !bnx2x_clear_pf_load(sc) &&
2160 bnx2x_reset_is_done(sc, SC_PATH(sc))) {
2161 bnx2x_disable_close_the_gate(sc);
2164 PMD_DRV_LOG(DEBUG, sc, "Ended NIC unload");
2170 * Encapsulte an mbuf cluster into the tx bd chain and makes the memory
2171 * visible to the controller.
2173 * If an mbuf is submitted to this routine and cannot be given to the
2174 * controller (e.g. it has too many fragments) then the function may free
2175 * the mbuf and return to the caller.
2178 * int: Number of TX BDs used for the mbuf
2180 * Note the side effect that an mbuf may be freed if it causes a problem.
2182 int bnx2x_tx_encap(struct bnx2x_tx_queue *txq, struct rte_mbuf *m0)
2184 struct eth_tx_start_bd *tx_start_bd;
2185 uint16_t bd_prod, pkt_prod;
2186 struct bnx2x_softc *sc;
2190 bd_prod = txq->tx_bd_tail;
2191 pkt_prod = txq->tx_pkt_tail;
2193 txq->sw_ring[TX_BD(pkt_prod, txq)] = m0;
2195 tx_start_bd = &txq->tx_ring[TX_BD(bd_prod, txq)].start_bd;
2197 tx_start_bd->addr_lo =
2198 rte_cpu_to_le_32(U64_LO(rte_mbuf_data_iova(m0)));
2199 tx_start_bd->addr_hi =
2200 rte_cpu_to_le_32(U64_HI(rte_mbuf_data_iova(m0)));
2201 tx_start_bd->nbytes = rte_cpu_to_le_16(m0->data_len);
2202 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2203 tx_start_bd->general_data =
2204 (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
2206 tx_start_bd->nbd = rte_cpu_to_le_16(2);
2208 if (m0->ol_flags & PKT_TX_VLAN_PKT) {
2209 tx_start_bd->vlan_or_ethertype =
2210 rte_cpu_to_le_16(m0->vlan_tci);
2211 tx_start_bd->bd_flags.as_bitfield |=
2212 (X_ETH_OUTBAND_VLAN <<
2213 ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT);
2216 tx_start_bd->vlan_or_ethertype =
2217 rte_cpu_to_le_16(pkt_prod);
2219 /* when transmitting in a vf, start bd
2220 * must hold the ethertype for fw to enforce it
2222 struct rte_ether_hdr *eh =
2223 rte_pktmbuf_mtod(m0, struct rte_ether_hdr *);
2225 /* Still need to consider inband vlan for enforced */
2226 if (eh->ether_type ==
2227 rte_cpu_to_be_16(RTE_ETHER_TYPE_VLAN)) {
2228 struct rte_vlan_hdr *vh =
2229 (struct rte_vlan_hdr *)(eh + 1);
2230 tx_start_bd->bd_flags.as_bitfield |=
2231 (X_ETH_INBAND_VLAN <<
2232 ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT);
2233 tx_start_bd->vlan_or_ethertype =
2234 rte_cpu_to_le_16(ntohs(vh->vlan_tci));
2236 tx_start_bd->vlan_or_ethertype =
2238 (rte_be_to_cpu_16(eh->ether_type)));
2243 bd_prod = NEXT_TX_BD(bd_prod);
2245 struct eth_tx_parse_bd_e2 *tx_parse_bd;
2246 const struct rte_ether_hdr *eh =
2247 rte_pktmbuf_mtod(m0, struct rte_ether_hdr *);
2248 uint8_t mac_type = UNICAST_ADDRESS;
2251 &txq->tx_ring[TX_BD(bd_prod, txq)].parse_bd_e2;
2252 if (rte_is_multicast_ether_addr(&eh->d_addr)) {
2253 if (rte_is_broadcast_ether_addr(&eh->d_addr))
2254 mac_type = BROADCAST_ADDRESS;
2256 mac_type = MULTICAST_ADDRESS;
2258 tx_parse_bd->parsing_data =
2259 (mac_type << ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT);
2261 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_hi,
2262 &eh->d_addr.addr_bytes[0], 2);
2263 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_mid,
2264 &eh->d_addr.addr_bytes[2], 2);
2265 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_lo,
2266 &eh->d_addr.addr_bytes[4], 2);
2267 rte_memcpy(&tx_parse_bd->data.mac_addr.src_hi,
2268 &eh->s_addr.addr_bytes[0], 2);
2269 rte_memcpy(&tx_parse_bd->data.mac_addr.src_mid,
2270 &eh->s_addr.addr_bytes[2], 2);
2271 rte_memcpy(&tx_parse_bd->data.mac_addr.src_lo,
2272 &eh->s_addr.addr_bytes[4], 2);
2274 tx_parse_bd->data.mac_addr.dst_hi =
2275 rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_hi);
2276 tx_parse_bd->data.mac_addr.dst_mid =
2277 rte_cpu_to_be_16(tx_parse_bd->data.
2279 tx_parse_bd->data.mac_addr.dst_lo =
2280 rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_lo);
2281 tx_parse_bd->data.mac_addr.src_hi =
2282 rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_hi);
2283 tx_parse_bd->data.mac_addr.src_mid =
2284 rte_cpu_to_be_16(tx_parse_bd->data.
2286 tx_parse_bd->data.mac_addr.src_lo =
2287 rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_lo);
2290 "PBD dst %x %x %x src %x %x %x p_data %x",
2291 tx_parse_bd->data.mac_addr.dst_hi,
2292 tx_parse_bd->data.mac_addr.dst_mid,
2293 tx_parse_bd->data.mac_addr.dst_lo,
2294 tx_parse_bd->data.mac_addr.src_hi,
2295 tx_parse_bd->data.mac_addr.src_mid,
2296 tx_parse_bd->data.mac_addr.src_lo,
2297 tx_parse_bd->parsing_data);
2301 "start bd: nbytes %d flags %x vlan %x",
2302 tx_start_bd->nbytes,
2303 tx_start_bd->bd_flags.as_bitfield,
2304 tx_start_bd->vlan_or_ethertype);
2306 bd_prod = NEXT_TX_BD(bd_prod);
2309 if (TX_IDX(bd_prod) < 2)
2312 txq->nb_tx_avail -= 2;
2313 txq->tx_bd_tail = bd_prod;
2314 txq->tx_pkt_tail = pkt_prod;
2319 static uint16_t bnx2x_cid_ilt_lines(struct bnx2x_softc *sc)
2321 return L2_ILT_LINES(sc);
2324 static void bnx2x_ilt_set_info(struct bnx2x_softc *sc)
2326 struct ilt_client_info *ilt_client;
2327 struct ecore_ilt *ilt = sc->ilt;
2330 PMD_INIT_FUNC_TRACE(sc);
2332 ilt->start_line = FUNC_ILT_BASE(SC_FUNC(sc));
2335 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
2336 ilt_client->client_num = ILT_CLIENT_CDU;
2337 ilt_client->page_size = CDU_ILT_PAGE_SZ;
2338 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
2339 ilt_client->start = line;
2340 line += bnx2x_cid_ilt_lines(sc);
2342 if (CNIC_SUPPORT(sc)) {
2343 line += CNIC_ILT_LINES;
2346 ilt_client->end = (line - 1);
2349 if (QM_INIT(sc->qm_cid_count)) {
2350 ilt_client = &ilt->clients[ILT_CLIENT_QM];
2351 ilt_client->client_num = ILT_CLIENT_QM;
2352 ilt_client->page_size = QM_ILT_PAGE_SZ;
2353 ilt_client->flags = 0;
2354 ilt_client->start = line;
2356 /* 4 bytes for each cid */
2357 line += DIV_ROUND_UP(sc->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
2360 ilt_client->end = (line - 1);
2363 if (CNIC_SUPPORT(sc)) {
2365 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
2366 ilt_client->client_num = ILT_CLIENT_SRC;
2367 ilt_client->page_size = SRC_ILT_PAGE_SZ;
2368 ilt_client->flags = 0;
2369 ilt_client->start = line;
2370 line += SRC_ILT_LINES;
2371 ilt_client->end = (line - 1);
2374 ilt_client = &ilt->clients[ILT_CLIENT_TM];
2375 ilt_client->client_num = ILT_CLIENT_TM;
2376 ilt_client->page_size = TM_ILT_PAGE_SZ;
2377 ilt_client->flags = 0;
2378 ilt_client->start = line;
2379 line += TM_ILT_LINES;
2380 ilt_client->end = (line - 1);
2383 assert((line <= ILT_MAX_LINES));
2386 static void bnx2x_set_fp_rx_buf_size(struct bnx2x_softc *sc)
2390 for (i = 0; i < sc->num_queues; i++) {
2391 /* get the Rx buffer size for RX frames */
2392 sc->fp[i].rx_buf_size =
2393 (IP_HEADER_ALIGNMENT_PADDING + ETH_OVERHEAD + sc->mtu);
2397 int bnx2x_alloc_ilt_mem(struct bnx2x_softc *sc)
2400 sc->ilt = rte_malloc("", sizeof(struct ecore_ilt), RTE_CACHE_LINE_SIZE);
2402 return sc->ilt == NULL;
2405 static int bnx2x_alloc_ilt_lines_mem(struct bnx2x_softc *sc)
2407 sc->ilt->lines = rte_calloc("",
2408 sizeof(struct ilt_line), ILT_MAX_LINES,
2409 RTE_CACHE_LINE_SIZE);
2410 return sc->ilt->lines == NULL;
2413 void bnx2x_free_ilt_mem(struct bnx2x_softc *sc)
2419 static void bnx2x_free_ilt_lines_mem(struct bnx2x_softc *sc)
2421 if (sc->ilt->lines != NULL) {
2422 rte_free(sc->ilt->lines);
2423 sc->ilt->lines = NULL;
2427 static void bnx2x_free_mem(struct bnx2x_softc *sc)
2431 for (i = 0; i < L2_ILT_LINES(sc); i++) {
2432 sc->context[i].vcxt = NULL;
2433 sc->context[i].size = 0;
2436 ecore_ilt_mem_op(sc, ILT_MEMOP_FREE);
2438 bnx2x_free_ilt_lines_mem(sc);
2441 static int bnx2x_alloc_mem(struct bnx2x_softc *sc)
2446 char cdu_name[RTE_MEMZONE_NAMESIZE];
2449 * Allocate memory for CDU context:
2450 * This memory is allocated separately and not in the generic ILT
2451 * functions because CDU differs in few aspects:
2452 * 1. There can be multiple entities allocating memory for context -
2453 * regular L2, CNIC, and SRIOV drivers. Each separately controls
2454 * its own ILT lines.
2455 * 2. Since CDU page-size is not a single 4KB page (which is the case
2456 * for the other ILT clients), to be efficient we want to support
2457 * allocation of sub-page-size in the last entry.
2458 * 3. Context pointers are used by the driver to pass to FW / update
2459 * the context (for the other ILT clients the pointers are used just to
2460 * free the memory during unload).
2462 context_size = (sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(sc));
2463 for (i = 0, allocated = 0; allocated < context_size; i++) {
2464 sc->context[i].size = min(CDU_ILT_PAGE_SZ,
2465 (context_size - allocated));
2467 snprintf(cdu_name, sizeof(cdu_name), "cdu_%d", i);
2468 if (bnx2x_dma_alloc(sc, sc->context[i].size,
2469 &sc->context[i].vcxt_dma,
2470 cdu_name, BNX2X_PAGE_SIZE) != 0) {
2475 sc->context[i].vcxt =
2476 (union cdu_context *)sc->context[i].vcxt_dma.vaddr;
2478 allocated += sc->context[i].size;
2481 bnx2x_alloc_ilt_lines_mem(sc);
2483 if (ecore_ilt_mem_op(sc, ILT_MEMOP_ALLOC)) {
2484 PMD_DRV_LOG(NOTICE, sc, "ecore_ilt_mem_op ILT_MEMOP_ALLOC failed");
2492 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc)
2494 bnx2x_dma_free(&sc->fw_stats_dma);
2495 sc->fw_stats_num = 0;
2497 sc->fw_stats_req_size = 0;
2498 sc->fw_stats_req = NULL;
2499 sc->fw_stats_req_mapping = 0;
2501 sc->fw_stats_data_size = 0;
2502 sc->fw_stats_data = NULL;
2503 sc->fw_stats_data_mapping = 0;
2506 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc)
2508 uint8_t num_queue_stats;
2509 int num_groups, vf_headroom = 0;
2511 /* number of queues for statistics is number of eth queues */
2512 num_queue_stats = BNX2X_NUM_ETH_QUEUES(sc);
2515 * Total number of FW statistics requests =
2516 * 1 for port stats + 1 for PF stats + num of queues
2518 sc->fw_stats_num = (2 + num_queue_stats);
2521 * Request is built from stats_query_header and an array of
2522 * stats_query_cmd_group each of which contains STATS_QUERY_CMD_COUNT
2523 * rules. The real number or requests is configured in the
2524 * stats_query_header.
2526 num_groups = (sc->fw_stats_num + vf_headroom) / STATS_QUERY_CMD_COUNT;
2527 if ((sc->fw_stats_num + vf_headroom) % STATS_QUERY_CMD_COUNT)
2530 sc->fw_stats_req_size =
2531 (sizeof(struct stats_query_header) +
2532 (num_groups * sizeof(struct stats_query_cmd_group)));
2535 * Data for statistics requests + stats_counter.
2536 * stats_counter holds per-STORM counters that are incremented when
2537 * STORM has finished with the current request. Memory for FCoE
2538 * offloaded statistics are counted anyway, even if they will not be sent.
2539 * VF stats are not accounted for here as the data of VF stats is stored
2540 * in memory allocated by the VF, not here.
2542 sc->fw_stats_data_size =
2543 (sizeof(struct stats_counter) +
2544 sizeof(struct per_port_stats) + sizeof(struct per_pf_stats) +
2545 /* sizeof(struct fcoe_statistics_params) + */
2546 (sizeof(struct per_queue_stats) * num_queue_stats));
2548 if (bnx2x_dma_alloc(sc, (sc->fw_stats_req_size + sc->fw_stats_data_size),
2549 &sc->fw_stats_dma, "fw_stats",
2550 RTE_CACHE_LINE_SIZE) != 0) {
2551 bnx2x_free_fw_stats_mem(sc);
2555 /* set up the shortcuts */
2557 sc->fw_stats_req = (struct bnx2x_fw_stats_req *)sc->fw_stats_dma.vaddr;
2558 sc->fw_stats_req_mapping = sc->fw_stats_dma.paddr;
2561 (struct bnx2x_fw_stats_data *)((uint8_t *) sc->fw_stats_dma.vaddr +
2562 sc->fw_stats_req_size);
2563 sc->fw_stats_data_mapping = (sc->fw_stats_dma.paddr +
2564 sc->fw_stats_req_size);
2571 * 0-7 - Engine0 load counter.
2572 * 8-15 - Engine1 load counter.
2573 * 16 - Engine0 RESET_IN_PROGRESS bit.
2574 * 17 - Engine1 RESET_IN_PROGRESS bit.
2575 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active
2576 * function on the engine
2577 * 19 - Engine1 ONE_IS_LOADED.
2578 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
2579 * leader to complete (check for both RESET_IN_PROGRESS bits and not
2580 * for just the one belonging to its engine).
2582 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
2583 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
2584 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
2585 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
2586 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
2587 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
2588 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
2589 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
2591 /* set the GLOBAL_RESET bit, should be run under rtnl lock */
2592 static void bnx2x_set_reset_global(struct bnx2x_softc *sc)
2595 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2596 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2597 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
2598 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2601 /* clear the GLOBAL_RESET bit, should be run under rtnl lock */
2602 static void bnx2x_clear_reset_global(struct bnx2x_softc *sc)
2605 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2606 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2607 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
2608 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2611 /* checks the GLOBAL_RESET bit, should be run under rtnl lock */
2612 static uint8_t bnx2x_reset_is_global(struct bnx2x_softc *sc)
2614 return REG_RD(sc, BNX2X_RECOVERY_GLOB_REG) & BNX2X_GLOBAL_RESET_BIT;
2617 /* clear RESET_IN_PROGRESS bit for the engine, should be run under rtnl lock */
2618 static void bnx2x_set_reset_done(struct bnx2x_softc *sc)
2621 uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2622 BNX2X_PATH0_RST_IN_PROG_BIT;
2624 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2626 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2629 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2631 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2634 /* set RESET_IN_PROGRESS for the engine, should be run under rtnl lock */
2635 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc)
2638 uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2639 BNX2X_PATH0_RST_IN_PROG_BIT;
2641 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2643 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2646 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2648 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2651 /* check RESET_IN_PROGRESS bit for an engine, should be run under rtnl lock */
2652 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine)
2654 uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2655 uint32_t bit = engine ? BNX2X_PATH1_RST_IN_PROG_BIT :
2656 BNX2X_PATH0_RST_IN_PROG_BIT;
2658 /* return false if bit is set */
2659 return (val & bit) ? FALSE : TRUE;
2662 /* get the load status for an engine, should be run under rtnl lock */
2663 static uint8_t bnx2x_get_load_status(struct bnx2x_softc *sc, int engine)
2665 uint32_t mask = engine ? BNX2X_PATH1_LOAD_CNT_MASK :
2666 BNX2X_PATH0_LOAD_CNT_MASK;
2667 uint32_t shift = engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2668 BNX2X_PATH0_LOAD_CNT_SHIFT;
2669 uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2671 val = ((val & mask) >> shift);
2676 /* set pf load mark */
2677 static void bnx2x_set_pf_load(struct bnx2x_softc *sc)
2681 uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2682 BNX2X_PATH0_LOAD_CNT_MASK;
2683 uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2684 BNX2X_PATH0_LOAD_CNT_SHIFT;
2686 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2688 PMD_INIT_FUNC_TRACE(sc);
2690 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2692 /* get the current counter value */
2693 val1 = ((val & mask) >> shift);
2695 /* set bit of this PF */
2696 val1 |= (1 << SC_ABS_FUNC(sc));
2698 /* clear the old value */
2701 /* set the new one */
2702 val |= ((val1 << shift) & mask);
2704 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2706 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2709 /* clear pf load mark */
2710 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc)
2713 uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2714 BNX2X_PATH0_LOAD_CNT_MASK;
2715 uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2716 BNX2X_PATH0_LOAD_CNT_SHIFT;
2718 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2719 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2721 /* get the current counter value */
2722 val1 = (val & mask) >> shift;
2724 /* clear bit of that PF */
2725 val1 &= ~(1 << SC_ABS_FUNC(sc));
2727 /* clear the old value */
2730 /* set the new one */
2731 val |= ((val1 << shift) & mask);
2733 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2734 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2738 /* send load requrest to mcp and analyze response */
2739 static int bnx2x_nic_load_request(struct bnx2x_softc *sc, uint32_t * load_code)
2741 PMD_INIT_FUNC_TRACE(sc);
2745 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
2746 DRV_MSG_SEQ_NUMBER_MASK);
2748 PMD_DRV_LOG(DEBUG, sc, "initial fw_seq 0x%04x", sc->fw_seq);
2751 /* get the current FW pulse sequence */
2752 sc->fw_drv_pulse_wr_seq =
2753 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb) &
2754 DRV_PULSE_SEQ_MASK);
2756 /* set ALWAYS_ALIVE bit in shmem */
2757 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2758 bnx2x_drv_pulse(sc);
2762 (*load_code) = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
2763 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
2765 /* if the MCP fails to respond we must abort */
2766 if (!(*load_code)) {
2767 PMD_DRV_LOG(NOTICE, sc, "MCP response failure!");
2771 /* if MCP refused then must abort */
2772 if ((*load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED) {
2773 PMD_DRV_LOG(NOTICE, sc, "MCP refused load request");
2781 * Check whether another PF has already loaded FW to chip. In virtualized
2782 * environments a pf from anoth VM may have already initialized the device
2783 * including loading FW.
2785 static int bnx2x_nic_load_analyze_req(struct bnx2x_softc *sc, uint32_t load_code)
2787 uint32_t my_fw, loaded_fw;
2789 /* is another pf loaded on this engine? */
2790 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
2791 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
2792 /* build my FW version dword */
2793 my_fw = (BNX2X_5710_FW_MAJOR_VERSION +
2794 (BNX2X_5710_FW_MINOR_VERSION << 8) +
2795 (BNX2X_5710_FW_REVISION_VERSION << 16) +
2796 (BNX2X_5710_FW_ENGINEERING_VERSION << 24));
2798 /* read loaded FW from chip */
2799 loaded_fw = REG_RD(sc, XSEM_REG_PRAM);
2800 PMD_DRV_LOG(DEBUG, sc, "loaded FW 0x%08x / my FW 0x%08x",
2803 /* abort nic load if version mismatch */
2804 if (my_fw != loaded_fw) {
2805 PMD_DRV_LOG(NOTICE, sc,
2806 "FW 0x%08x already loaded (mine is 0x%08x)",
2815 /* mark PMF if applicable */
2816 static void bnx2x_nic_load_pmf(struct bnx2x_softc *sc, uint32_t load_code)
2818 uint32_t ncsi_oem_data_addr;
2820 PMD_INIT_FUNC_TRACE(sc);
2822 if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
2823 (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
2824 (load_code == FW_MSG_CODE_DRV_LOAD_PORT)) {
2826 * Barrier here for ordering between the writing to sc->port.pmf here
2827 * and reading it from the periodic task.
2835 PMD_DRV_LOG(DEBUG, sc, "pmf %d", sc->port.pmf);
2837 if (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) {
2838 if (SHMEM2_HAS(sc, ncsi_oem_data_addr)) {
2839 ncsi_oem_data_addr = SHMEM2_RD(sc, ncsi_oem_data_addr);
2840 if (ncsi_oem_data_addr) {
2842 (ncsi_oem_data_addr +
2843 offsetof(struct glob_ncsi_oem_data,
2844 driver_version)), 0);
2850 static void bnx2x_read_mf_cfg(struct bnx2x_softc *sc)
2852 int n = (CHIP_IS_MODE_4_PORT(sc) ? 2 : 1);
2856 if (BNX2X_NOMCP(sc)) {
2857 return; /* what should be the default bvalue in this case */
2861 * The formula for computing the absolute function number is...
2862 * For 2 port configuration (4 functions per port):
2863 * abs_func = 2 * vn + SC_PORT + SC_PATH
2864 * For 4 port configuration (2 functions per port):
2865 * abs_func = 4 * vn + 2 * SC_PORT + SC_PATH
2867 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
2868 abs_func = (n * (2 * vn + SC_PORT(sc)) + SC_PATH(sc));
2869 if (abs_func >= E1H_FUNC_MAX) {
2872 sc->devinfo.mf_info.mf_config[vn] =
2873 MFCFG_RD(sc, func_mf_config[abs_func].config);
2876 if (sc->devinfo.mf_info.mf_config[SC_VN(sc)] &
2877 FUNC_MF_CFG_FUNC_DISABLED) {
2878 PMD_DRV_LOG(DEBUG, sc, "mf_cfg function disabled");
2879 sc->flags |= BNX2X_MF_FUNC_DIS;
2881 PMD_DRV_LOG(DEBUG, sc, "mf_cfg function enabled");
2882 sc->flags &= ~BNX2X_MF_FUNC_DIS;
2886 /* acquire split MCP access lock register */
2887 static int bnx2x_acquire_alr(struct bnx2x_softc *sc)
2891 for (j = 0; j < 1000; j++) {
2893 REG_WR(sc, GRCBASE_MCP + 0x9c, val);
2894 val = REG_RD(sc, GRCBASE_MCP + 0x9c);
2895 if (val & (1L << 31))
2901 if (!(val & (1L << 31))) {
2902 PMD_DRV_LOG(NOTICE, sc, "Cannot acquire MCP access lock register");
2909 /* release split MCP access lock register */
2910 static void bnx2x_release_alr(struct bnx2x_softc *sc)
2912 REG_WR(sc, GRCBASE_MCP + 0x9c, 0);
2915 static void bnx2x_fan_failure(struct bnx2x_softc *sc)
2917 int port = SC_PORT(sc);
2918 uint32_t ext_phy_config;
2920 /* mark the failure */
2922 SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
2924 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2925 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
2926 SHMEM_WR(sc, dev_info.port_hw_config[port].external_phy_config,
2929 /* log the failure */
2930 PMD_DRV_LOG(INFO, sc,
2931 "Fan Failure has caused the driver to shutdown "
2932 "the card to prevent permanent damage. "
2933 "Please contact OEM Support for assistance");
2935 rte_panic("Schedule task to handle fan failure");
2938 /* this function is called upon a link interrupt */
2939 static void bnx2x_link_attn(struct bnx2x_softc *sc)
2941 uint32_t pause_enabled = 0;
2942 struct host_port_stats *pstats;
2945 /* Make sure that we are synced with the current statistics */
2946 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2948 elink_link_update(&sc->link_params, &sc->link_vars);
2950 if (sc->link_vars.link_up) {
2952 /* dropless flow control */
2953 if (sc->dropless_fc) {
2956 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
2961 (BAR_USTRORM_INTMEM +
2962 USTORM_ETH_PAUSE_ENABLED_OFFSET(SC_PORT(sc))),
2966 if (sc->link_vars.mac_type != ELINK_MAC_TYPE_EMAC) {
2967 pstats = BNX2X_SP(sc, port_stats);
2968 /* reset old mac stats */
2969 memset(&(pstats->mac_stx[0]), 0,
2970 sizeof(struct mac_stx));
2973 if (sc->state == BNX2X_STATE_OPEN) {
2974 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
2978 if (sc->link_vars.link_up && sc->link_vars.line_speed) {
2979 cmng_fns = bnx2x_get_cmng_fns_mode(sc);
2981 if (cmng_fns != CMNG_FNS_NONE) {
2982 bnx2x_cmng_fns_init(sc, FALSE, cmng_fns);
2983 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
2987 bnx2x_link_report_locked(sc);
2990 bnx2x_link_sync_notify(sc);
2994 static void bnx2x_attn_int_asserted(struct bnx2x_softc *sc, uint32_t asserted)
2996 int port = SC_PORT(sc);
2997 uint32_t aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2998 MISC_REG_AEU_MASK_ATTN_FUNC_0;
2999 uint32_t nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3000 NIG_REG_MASK_INTERRUPT_PORT0;
3002 uint32_t nig_mask = 0;
3007 if (sc->attn_state & asserted) {
3008 PMD_DRV_LOG(ERR, sc, "IGU ERROR attn=0x%08x", asserted);
3011 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3013 aeu_mask = REG_RD(sc, aeu_addr);
3015 aeu_mask &= ~(asserted & 0x3ff);
3017 REG_WR(sc, aeu_addr, aeu_mask);
3019 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3021 sc->attn_state |= asserted;
3023 if (asserted & ATTN_HARD_WIRED_MASK) {
3024 if (asserted & ATTN_NIG_FOR_FUNC) {
3026 bnx2x_acquire_phy_lock(sc);
3027 /* save nig interrupt mask */
3028 nig_mask = REG_RD(sc, nig_int_mask_addr);
3030 /* If nig_mask is not set, no need to call the update function */
3032 REG_WR(sc, nig_int_mask_addr, 0);
3034 bnx2x_link_attn(sc);
3037 /* handle unicore attn? */
3040 if (asserted & ATTN_SW_TIMER_4_FUNC) {
3041 PMD_DRV_LOG(DEBUG, sc, "ATTN_SW_TIMER_4_FUNC!");
3044 if (asserted & GPIO_2_FUNC) {
3045 PMD_DRV_LOG(DEBUG, sc, "GPIO_2_FUNC!");
3048 if (asserted & GPIO_3_FUNC) {
3049 PMD_DRV_LOG(DEBUG, sc, "GPIO_3_FUNC!");
3052 if (asserted & GPIO_4_FUNC) {
3053 PMD_DRV_LOG(DEBUG, sc, "GPIO_4_FUNC!");
3057 if (asserted & ATTN_GENERAL_ATTN_1) {
3058 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_1!");
3059 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3061 if (asserted & ATTN_GENERAL_ATTN_2) {
3062 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_2!");
3063 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3065 if (asserted & ATTN_GENERAL_ATTN_3) {
3066 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_3!");
3067 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3070 if (asserted & ATTN_GENERAL_ATTN_4) {
3071 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_4!");
3072 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3074 if (asserted & ATTN_GENERAL_ATTN_5) {
3075 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_5!");
3076 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3078 if (asserted & ATTN_GENERAL_ATTN_6) {
3079 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_6!");
3080 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3085 if (sc->devinfo.int_block == INT_BLOCK_HC) {
3087 (HC_REG_COMMAND_REG + port * 32 +
3088 COMMAND_REG_ATTN_BITS_SET);
3090 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER * 8);
3093 PMD_DRV_LOG(DEBUG, sc, "about to mask 0x%08x at %s addr 0x%08x",
3095 (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
3097 REG_WR(sc, reg_addr, asserted);
3099 /* now set back the mask */
3100 if (asserted & ATTN_NIG_FOR_FUNC) {
3102 * Verify that IGU ack through BAR was written before restoring
3103 * NIG mask. This loop should exit after 2-3 iterations max.
3105 if (sc->devinfo.int_block != INT_BLOCK_HC) {
3110 REG_RD(sc, IGU_REG_ATTENTION_ACK_BITS);
3111 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0)
3112 && (++cnt < MAX_IGU_ATTN_ACK_TO));
3115 PMD_DRV_LOG(ERR, sc,
3116 "Failed to verify IGU ack on time");
3122 REG_WR(sc, nig_int_mask_addr, nig_mask);
3124 bnx2x_release_phy_lock(sc);
3129 bnx2x_print_next_block(__rte_unused struct bnx2x_softc *sc, __rte_unused int idx,
3130 __rte_unused const char *blk)
3132 PMD_DRV_LOG(INFO, sc, "%s%s", idx ? ", " : "", blk);
3136 bnx2x_check_blocks_with_parity0(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3139 uint32_t cur_bit = 0;
3142 for (i = 0; sig; i++) {
3143 cur_bit = ((uint32_t) 0x1 << i);
3144 if (sig & cur_bit) {
3146 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3148 bnx2x_print_next_block(sc, par_num++,
3151 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3153 bnx2x_print_next_block(sc, par_num++,
3156 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3158 bnx2x_print_next_block(sc, par_num++,
3161 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3163 bnx2x_print_next_block(sc, par_num++,
3166 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3168 bnx2x_print_next_block(sc, par_num++,
3171 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3173 bnx2x_print_next_block(sc, par_num++,
3176 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3178 bnx2x_print_next_block(sc, par_num++,
3192 bnx2x_check_blocks_with_parity1(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3193 uint8_t * global, uint8_t print)
3196 uint32_t cur_bit = 0;
3197 for (i = 0; sig; i++) {
3198 cur_bit = ((uint32_t) 0x1 << i);
3199 if (sig & cur_bit) {
3201 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3203 bnx2x_print_next_block(sc, par_num++,
3206 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3208 bnx2x_print_next_block(sc, par_num++,
3211 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3213 bnx2x_print_next_block(sc, par_num++,
3216 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3218 bnx2x_print_next_block(sc, par_num++,
3221 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
3223 bnx2x_print_next_block(sc, par_num++,
3226 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3228 bnx2x_print_next_block(sc, par_num++,
3231 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3233 bnx2x_print_next_block(sc, par_num++,
3236 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
3238 bnx2x_print_next_block(sc, par_num++,
3241 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3243 bnx2x_print_next_block(sc, par_num++,
3247 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3249 bnx2x_print_next_block(sc, par_num++,
3252 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3254 bnx2x_print_next_block(sc, par_num++,
3257 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
3259 bnx2x_print_next_block(sc, par_num++,
3262 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3264 bnx2x_print_next_block(sc, par_num++,
3267 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3269 bnx2x_print_next_block(sc, par_num++,
3272 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3274 bnx2x_print_next_block(sc, par_num++,
3277 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
3279 bnx2x_print_next_block(sc, par_num++,
3293 bnx2x_check_blocks_with_parity2(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3296 uint32_t cur_bit = 0;
3299 for (i = 0; sig; i++) {
3300 cur_bit = ((uint32_t) 0x1 << i);
3301 if (sig & cur_bit) {
3303 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3305 bnx2x_print_next_block(sc, par_num++,
3308 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3310 bnx2x_print_next_block(sc, par_num++,
3313 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3315 bnx2x_print_next_block(sc, par_num++,
3316 "PXPPCICLOCKCLIENT");
3318 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3320 bnx2x_print_next_block(sc, par_num++,
3323 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3325 bnx2x_print_next_block(sc, par_num++,
3328 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
3330 bnx2x_print_next_block(sc, par_num++,
3333 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3335 bnx2x_print_next_block(sc, par_num++,
3338 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3340 bnx2x_print_next_block(sc, par_num++,
3354 bnx2x_check_blocks_with_parity3(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3355 uint8_t * global, uint8_t print)
3357 uint32_t cur_bit = 0;
3360 for (i = 0; sig; i++) {
3361 cur_bit = ((uint32_t) 0x1 << i);
3362 if (sig & cur_bit) {
3364 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3366 bnx2x_print_next_block(sc, par_num++,
3370 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3372 bnx2x_print_next_block(sc, par_num++,
3376 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3378 bnx2x_print_next_block(sc, par_num++,
3382 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3384 bnx2x_print_next_block(sc, par_num++,
3399 bnx2x_check_blocks_with_parity4(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3402 uint32_t cur_bit = 0;
3405 for (i = 0; sig; i++) {
3406 cur_bit = ((uint32_t) 0x1 << i);
3407 if (sig & cur_bit) {
3409 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
3411 bnx2x_print_next_block(sc, par_num++,
3414 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
3416 bnx2x_print_next_block(sc, par_num++,
3430 bnx2x_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print,
3435 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
3436 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
3437 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
3438 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
3439 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
3440 PMD_DRV_LOG(ERR, sc,
3441 "Parity error: HW block parity attention:"
3442 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x",
3443 (uint32_t) (sig[0] & HW_PRTY_ASSERT_SET_0),
3444 (uint32_t) (sig[1] & HW_PRTY_ASSERT_SET_1),
3445 (uint32_t) (sig[2] & HW_PRTY_ASSERT_SET_2),
3446 (uint32_t) (sig[3] & HW_PRTY_ASSERT_SET_3),
3447 (uint32_t) (sig[4] & HW_PRTY_ASSERT_SET_4));
3450 PMD_DRV_LOG(INFO, sc, "Parity errors detected in blocks: ");
3453 bnx2x_check_blocks_with_parity0(sc, sig[0] &
3454 HW_PRTY_ASSERT_SET_0,
3457 bnx2x_check_blocks_with_parity1(sc, sig[1] &
3458 HW_PRTY_ASSERT_SET_1,
3459 par_num, global, print);
3461 bnx2x_check_blocks_with_parity2(sc, sig[2] &
3462 HW_PRTY_ASSERT_SET_2,
3465 bnx2x_check_blocks_with_parity3(sc, sig[3] &
3466 HW_PRTY_ASSERT_SET_3,
3467 par_num, global, print);
3469 bnx2x_check_blocks_with_parity4(sc, sig[4] &
3470 HW_PRTY_ASSERT_SET_4,
3474 PMD_DRV_LOG(INFO, sc, "");
3483 bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print)
3485 struct attn_route attn = { {0} };
3486 int port = SC_PORT(sc);
3488 attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
3489 attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
3490 attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
3491 attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
3493 if (!CHIP_IS_E1x(sc))
3495 REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
3497 return bnx2x_parity_attn(sc, global, print, attn.sig);
3500 static void bnx2x_attn_int_deasserted4(struct bnx2x_softc *sc, uint32_t attn)
3504 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
3505 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
3506 PMD_DRV_LOG(INFO, sc, "ERROR: PGLUE hw attention 0x%08x", val);
3507 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
3508 PMD_DRV_LOG(INFO, sc,
3509 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR");
3510 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
3511 PMD_DRV_LOG(INFO, sc,
3512 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR");
3513 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
3514 PMD_DRV_LOG(INFO, sc,
3515 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN");
3516 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
3517 PMD_DRV_LOG(INFO, sc,
3518 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN");
3520 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
3521 PMD_DRV_LOG(INFO, sc,
3522 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN");
3524 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
3525 PMD_DRV_LOG(INFO, sc,
3526 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN");
3527 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
3528 PMD_DRV_LOG(INFO, sc,
3529 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN");
3530 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
3531 PMD_DRV_LOG(INFO, sc,
3532 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN");
3533 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
3534 PMD_DRV_LOG(INFO, sc,
3535 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW");
3538 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
3539 val = REG_RD(sc, ATC_REG_ATC_INT_STS_CLR);
3540 PMD_DRV_LOG(INFO, sc, "ERROR: ATC hw attention 0x%08x", val);
3541 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
3542 PMD_DRV_LOG(INFO, sc,
3543 "ERROR: ATC_ATC_INT_STS_REG_ADDRESS_ERROR");
3544 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
3545 PMD_DRV_LOG(INFO, sc,
3546 "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND");
3547 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
3548 PMD_DRV_LOG(INFO, sc,
3549 "ERROR: ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS");
3550 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
3551 PMD_DRV_LOG(INFO, sc,
3552 "ERROR: ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT");
3553 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
3554 PMD_DRV_LOG(INFO, sc,
3555 "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR");
3556 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
3557 PMD_DRV_LOG(INFO, sc,
3558 "ERROR: ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU");
3561 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3562 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
3563 PMD_DRV_LOG(INFO, sc,
3564 "ERROR: FATAL parity attention set4 0x%08x",
3566 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
3568 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
3572 static void bnx2x_e1h_disable(struct bnx2x_softc *sc)
3574 int port = SC_PORT(sc);
3576 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
3579 static void bnx2x_e1h_enable(struct bnx2x_softc *sc)
3581 int port = SC_PORT(sc);
3583 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3587 * called due to MCP event (on pmf):
3588 * reread new bandwidth configuration
3590 * notify others function about the change
3592 static void bnx2x_config_mf_bw(struct bnx2x_softc *sc)
3594 if (sc->link_vars.link_up) {
3595 bnx2x_cmng_fns_init(sc, TRUE, CMNG_FNS_MINMAX);
3596 bnx2x_link_sync_notify(sc);
3599 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
3602 static void bnx2x_set_mf_bw(struct bnx2x_softc *sc)
3604 bnx2x_config_mf_bw(sc);
3605 bnx2x_fw_command(sc, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3608 static void bnx2x_handle_eee_event(struct bnx2x_softc *sc)
3610 bnx2x_fw_command(sc, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3613 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3615 static void bnx2x_drv_info_ether_stat(struct bnx2x_softc *sc)
3617 struct eth_stats_info *ether_stat = &sc->sp->drv_info_to_mcp.ether_stat;
3619 strncpy(ether_stat->version, BNX2X_DRIVER_VERSION,
3620 ETH_STAT_INFO_VERSION_LEN);
3622 sc->sp_objs[0].mac_obj.get_n_elements(sc, &sc->sp_objs[0].mac_obj,
3623 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3624 ether_stat->mac_local + MAC_PAD,
3627 ether_stat->mtu_size = sc->mtu;
3629 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3630 ether_stat->promiscuous_mode = 0; // (flags & PROMISC) ? 1 : 0;
3632 ether_stat->txq_size = sc->tx_ring_size;
3633 ether_stat->rxq_size = sc->rx_ring_size;
3636 static void bnx2x_handle_drv_info_req(struct bnx2x_softc *sc)
3638 enum drv_info_opcode op_code;
3639 uint32_t drv_info_ctl = SHMEM2_RD(sc, drv_info_control);
3641 /* if drv_info version supported by MFW doesn't match - send NACK */
3642 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3643 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3647 op_code = ((drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3648 DRV_INFO_CONTROL_OP_CODE_SHIFT);
3650 memset(&sc->sp->drv_info_to_mcp, 0, sizeof(union drv_info_to_mcp));
3653 case ETH_STATS_OPCODE:
3654 bnx2x_drv_info_ether_stat(sc);
3656 case FCOE_STATS_OPCODE:
3657 case ISCSI_STATS_OPCODE:
3659 /* if op code isn't supported - send NACK */
3660 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3665 * If we got drv_info attn from MFW then these fields are defined in
3668 SHMEM2_WR(sc, drv_info_host_addr_lo,
3669 U64_LO(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3670 SHMEM2_WR(sc, drv_info_host_addr_hi,
3671 U64_HI(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3673 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3676 static void bnx2x_dcc_event(struct bnx2x_softc *sc, uint32_t dcc_event)
3678 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3680 * This is the only place besides the function initialization
3681 * where the sc->flags can change so it is done without any
3685 mf_info.mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_DISABLED) {
3686 PMD_DRV_LOG(DEBUG, sc, "mf_cfg function disabled");
3687 sc->flags |= BNX2X_MF_FUNC_DIS;
3688 bnx2x_e1h_disable(sc);
3690 PMD_DRV_LOG(DEBUG, sc, "mf_cfg function enabled");
3691 sc->flags &= ~BNX2X_MF_FUNC_DIS;
3692 bnx2x_e1h_enable(sc);
3694 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3697 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3698 bnx2x_config_mf_bw(sc);
3699 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3702 /* Report results to MCP */
3704 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_FAILURE, 0);
3706 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_OK, 0);
3709 static void bnx2x_pmf_update(struct bnx2x_softc *sc)
3711 int port = SC_PORT(sc);
3717 * We need the mb() to ensure the ordering between the writing to
3718 * sc->port.pmf here and reading it from the bnx2x_periodic_task().
3722 /* enable nig attention */
3723 val = (0xff0f | (1 << (SC_VN(sc) + 4)));
3724 if (sc->devinfo.int_block == INT_BLOCK_HC) {
3725 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, val);
3726 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, val);
3727 } else if (!CHIP_IS_E1x(sc)) {
3728 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
3729 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
3732 bnx2x_stats_handle(sc, STATS_EVENT_PMF);
3735 static int bnx2x_mc_assert(struct bnx2x_softc *sc)
3739 __rte_unused uint32_t row0, row1, row2, row3;
3743 REG_RD8(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_INDEX_OFFSET);
3745 PMD_DRV_LOG(ERR, sc, "XSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3747 /* print the asserts */
3748 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3752 BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i));
3755 BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3759 BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3763 BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3766 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3767 PMD_DRV_LOG(ERR, sc,
3768 "XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3769 i, row3, row2, row1, row0);
3778 REG_RD8(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_INDEX_OFFSET);
3780 PMD_DRV_LOG(ERR, sc, "TSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3783 /* print the asserts */
3784 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3788 BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i));
3791 BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3795 BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3799 BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3802 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3803 PMD_DRV_LOG(ERR, sc,
3804 "TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3805 i, row3, row2, row1, row0);
3814 REG_RD8(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_INDEX_OFFSET);
3816 PMD_DRV_LOG(ERR, sc, "CSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3819 /* print the asserts */
3820 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3824 BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i));
3827 BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3831 BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3835 BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3838 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3839 PMD_DRV_LOG(ERR, sc,
3840 "CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3841 i, row3, row2, row1, row0);
3850 REG_RD8(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_INDEX_OFFSET);
3852 PMD_DRV_LOG(ERR, sc, "USTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3855 /* print the asserts */
3856 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3860 BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i));
3863 BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3867 BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3871 BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3874 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3875 PMD_DRV_LOG(ERR, sc,
3876 "USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3877 i, row3, row2, row1, row0);
3887 static void bnx2x_attn_int_deasserted3(struct bnx2x_softc *sc, uint32_t attn)
3889 int func = SC_FUNC(sc);
3892 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3894 if (attn & BNX2X_PMF_LINK_ASSERT(sc)) {
3896 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
3897 bnx2x_read_mf_cfg(sc);
3898 sc->devinfo.mf_info.mf_config[SC_VN(sc)] =
3900 func_mf_config[SC_ABS_FUNC(sc)].config);
3902 SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_status);
3904 if (val & DRV_STATUS_DCC_EVENT_MASK)
3907 DRV_STATUS_DCC_EVENT_MASK));
3909 if (val & DRV_STATUS_SET_MF_BW)
3910 bnx2x_set_mf_bw(sc);
3912 if (val & DRV_STATUS_DRV_INFO_REQ)
3913 bnx2x_handle_drv_info_req(sc);
3915 if ((sc->port.pmf == 0) && (val & DRV_STATUS_PMF))
3916 bnx2x_pmf_update(sc);
3918 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
3919 bnx2x_handle_eee_event(sc);
3921 if (sc->link_vars.periodic_flags &
3922 ELINK_PERIODIC_FLAGS_LINK_EVENT) {
3923 /* sync with link */
3924 bnx2x_acquire_phy_lock(sc);
3925 sc->link_vars.periodic_flags &=
3926 ~ELINK_PERIODIC_FLAGS_LINK_EVENT;
3927 bnx2x_release_phy_lock(sc);
3929 bnx2x_link_sync_notify(sc);
3931 bnx2x_link_report(sc);
3935 * Always call it here: bnx2x_link_report() will
3936 * prevent the link indication duplication.
3938 bnx2x_link_status_update(sc);
3940 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3942 PMD_DRV_LOG(ERR, sc, "MC assert!");
3943 bnx2x_mc_assert(sc);
3944 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3945 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3946 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3947 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3948 rte_panic("MC assert!");
3950 } else if (attn & BNX2X_MCP_ASSERT) {
3952 PMD_DRV_LOG(ERR, sc, "MCP assert!");
3953 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3956 PMD_DRV_LOG(ERR, sc,
3957 "Unknown HW assert! (attn 0x%08x)", attn);
3961 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3962 PMD_DRV_LOG(ERR, sc, "LATCHED attention 0x%08x (masked)", attn);
3963 if (attn & BNX2X_GRC_TIMEOUT) {
3964 val = REG_RD(sc, MISC_REG_GRC_TIMEOUT_ATTN);
3965 PMD_DRV_LOG(ERR, sc, "GRC time-out 0x%08x", val);
3967 if (attn & BNX2X_GRC_RSV) {
3968 val = REG_RD(sc, MISC_REG_GRC_RSV_ATTN);
3969 PMD_DRV_LOG(ERR, sc, "GRC reserved 0x%08x", val);
3971 REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3975 static void bnx2x_attn_int_deasserted2(struct bnx2x_softc *sc, uint32_t attn)
3977 int port = SC_PORT(sc);
3979 uint32_t val0, mask0, val1, mask1;
3982 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3983 val = REG_RD(sc, CFC_REG_CFC_INT_STS_CLR);
3984 PMD_DRV_LOG(ERR, sc, "CFC hw attention 0x%08x", val);
3985 /* CFC error attention */
3987 PMD_DRV_LOG(ERR, sc, "FATAL error from CFC");
3991 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3992 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_0);
3993 PMD_DRV_LOG(ERR, sc, "PXP hw attention-0 0x%08x", val);
3994 /* RQ_USDMDP_FIFO_OVERFLOW */
3995 if (val & 0x18000) {
3996 PMD_DRV_LOG(ERR, sc, "FATAL error from PXP");
3999 if (!CHIP_IS_E1x(sc)) {
4000 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_1);
4001 PMD_DRV_LOG(ERR, sc, "PXP hw attention-1 0x%08x", val);
4004 #define PXP2_EOP_ERROR_BIT PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR
4005 #define AEU_PXP2_HW_INT_BIT AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT
4007 if (attn & AEU_PXP2_HW_INT_BIT) {
4008 /* CQ47854 workaround do not panic on
4009 * PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
4011 if (!CHIP_IS_E1x(sc)) {
4012 mask0 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_0);
4013 val1 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_1);
4014 mask1 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_1);
4015 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_0);
4017 * If the only PXP2_EOP_ERROR_BIT is set in
4018 * STS0 and STS1 - clear it
4020 * probably we lose additional attentions between
4021 * STS0 and STS_CLR0, in this case user will not
4022 * be notified about them
4024 if (val0 & mask0 & PXP2_EOP_ERROR_BIT &&
4026 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
4028 /* print the register, since no one can restore it */
4029 PMD_DRV_LOG(ERR, sc,
4030 "PXP2_REG_PXP2_INT_STS_CLR_0 0x%08x", val0);
4033 * if PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
4036 if (val0 & PXP2_EOP_ERROR_BIT) {
4037 PMD_DRV_LOG(ERR, sc, "PXP2_WR_PGLUE_EOP_ERROR");
4040 * if only PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR is
4041 * set then clear attention from PXP2 block without panic
4043 if (((val0 & mask0) == PXP2_EOP_ERROR_BIT) &&
4044 ((val1 & mask1) == 0))
4045 attn &= ~AEU_PXP2_HW_INT_BIT;
4050 if (attn & HW_INTERRUT_ASSERT_SET_2) {
4051 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
4052 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
4054 val = REG_RD(sc, reg_offset);
4055 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
4056 REG_WR(sc, reg_offset, val);
4058 PMD_DRV_LOG(ERR, sc,
4059 "FATAL HW block attention set2 0x%x",
4060 (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_2));
4061 rte_panic("HW block attention set2");
4065 static void bnx2x_attn_int_deasserted1(struct bnx2x_softc *sc, uint32_t attn)
4067 int port = SC_PORT(sc);
4071 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
4072 val = REG_RD(sc, DORQ_REG_DORQ_INT_STS_CLR);
4073 PMD_DRV_LOG(ERR, sc, "DB hw attention 0x%08x", val);
4074 /* DORQ discard attention */
4076 PMD_DRV_LOG(ERR, sc, "FATAL error from DORQ");
4080 if (attn & HW_INTERRUT_ASSERT_SET_1) {
4081 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4082 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4084 val = REG_RD(sc, reg_offset);
4085 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4086 REG_WR(sc, reg_offset, val);
4088 PMD_DRV_LOG(ERR, sc,
4089 "FATAL HW block attention set1 0x%08x",
4090 (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_1));
4091 rte_panic("HW block attention set1");
4095 static void bnx2x_attn_int_deasserted0(struct bnx2x_softc *sc, uint32_t attn)
4097 int port = SC_PORT(sc);
4101 reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4102 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
4104 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4105 val = REG_RD(sc, reg_offset);
4106 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4107 REG_WR(sc, reg_offset, val);
4109 PMD_DRV_LOG(WARNING, sc, "SPIO5 hw attention");
4111 /* Fan failure attention */
4112 elink_hw_reset_phy(&sc->link_params);
4113 bnx2x_fan_failure(sc);
4116 if ((attn & sc->link_vars.aeu_int_mask) && sc->port.pmf) {
4117 bnx2x_acquire_phy_lock(sc);
4118 elink_handle_module_detect_int(&sc->link_params);
4119 bnx2x_release_phy_lock(sc);
4122 if (attn & HW_INTERRUT_ASSERT_SET_0) {
4123 val = REG_RD(sc, reg_offset);
4124 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4125 REG_WR(sc, reg_offset, val);
4127 rte_panic("FATAL HW block attention set0 0x%lx",
4128 (attn & (unsigned long)HW_INTERRUT_ASSERT_SET_0));
4132 static void bnx2x_attn_int_deasserted(struct bnx2x_softc *sc, uint32_t deasserted)
4134 struct attn_route attn;
4135 struct attn_route *group_mask;
4136 int port = SC_PORT(sc);
4141 uint8_t global = FALSE;
4144 * Need to take HW lock because MCP or other port might also
4145 * try to handle this event.
4147 bnx2x_acquire_alr(sc);
4149 if (bnx2x_chk_parity_attn(sc, &global, TRUE)) {
4150 sc->recovery_state = BNX2X_RECOVERY_INIT;
4152 /* disable HW interrupts */
4153 bnx2x_int_disable(sc);
4154 bnx2x_release_alr(sc);
4158 attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
4159 attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
4160 attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
4161 attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
4162 if (!CHIP_IS_E1x(sc)) {
4164 REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
4169 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4170 if (deasserted & (1 << index)) {
4171 group_mask = &sc->attn_group[index];
4173 bnx2x_attn_int_deasserted4(sc,
4175 sig[4] & group_mask->sig[4]);
4176 bnx2x_attn_int_deasserted3(sc,
4178 sig[3] & group_mask->sig[3]);
4179 bnx2x_attn_int_deasserted1(sc,
4181 sig[1] & group_mask->sig[1]);
4182 bnx2x_attn_int_deasserted2(sc,
4184 sig[2] & group_mask->sig[2]);
4185 bnx2x_attn_int_deasserted0(sc,
4187 sig[0] & group_mask->sig[0]);
4191 bnx2x_release_alr(sc);
4193 if (sc->devinfo.int_block == INT_BLOCK_HC) {
4194 reg_addr = (HC_REG_COMMAND_REG + port * 32 +
4195 COMMAND_REG_ATTN_BITS_CLR);
4197 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER * 8);
4201 PMD_DRV_LOG(DEBUG, sc,
4202 "about to mask 0x%08x at %s addr 0x%08x", val,
4203 (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
4205 REG_WR(sc, reg_addr, val);
4207 if (~sc->attn_state & deasserted) {
4208 PMD_DRV_LOG(ERR, sc, "IGU error");
4211 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4212 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4214 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4216 aeu_mask = REG_RD(sc, reg_addr);
4218 aeu_mask |= (deasserted & 0x3ff);
4220 REG_WR(sc, reg_addr, aeu_mask);
4221 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4223 sc->attn_state &= ~deasserted;
4226 static void bnx2x_attn_int(struct bnx2x_softc *sc)
4228 /* read local copy of bits */
4229 uint32_t attn_bits = le32toh(sc->def_sb->atten_status_block.attn_bits);
4231 le32toh(sc->def_sb->atten_status_block.attn_bits_ack);
4232 uint32_t attn_state = sc->attn_state;
4234 /* look for changed bits */
4235 uint32_t asserted = attn_bits & ~attn_ack & ~attn_state;
4236 uint32_t deasserted = ~attn_bits & attn_ack & attn_state;
4238 PMD_DRV_LOG(DEBUG, sc,
4239 "attn_bits 0x%08x attn_ack 0x%08x asserted 0x%08x deasserted 0x%08x",
4240 attn_bits, attn_ack, asserted, deasserted);
4242 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) {
4243 PMD_DRV_LOG(ERR, sc, "BAD attention state");
4246 /* handle bits that were raised */
4248 bnx2x_attn_int_asserted(sc, asserted);
4252 bnx2x_attn_int_deasserted(sc, deasserted);
4256 static uint16_t bnx2x_update_dsb_idx(struct bnx2x_softc *sc)
4258 struct host_sp_status_block *def_sb = sc->def_sb;
4264 mb(); /* status block is written to by the chip */
4266 if (sc->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
4267 sc->def_att_idx = def_sb->atten_status_block.attn_bits_index;
4268 rc |= BNX2X_DEF_SB_ATT_IDX;
4271 if (sc->def_idx != def_sb->sp_sb.running_index) {
4272 sc->def_idx = def_sb->sp_sb.running_index;
4273 rc |= BNX2X_DEF_SB_IDX;
4281 static struct ecore_queue_sp_obj *bnx2x_cid_to_q_obj(struct bnx2x_softc *sc,
4284 return &sc->sp_objs[CID_TO_FP(cid, sc)].q_obj;
4287 static void bnx2x_handle_mcast_eqe(struct bnx2x_softc *sc)
4289 struct ecore_mcast_ramrod_params rparam;
4292 memset(&rparam, 0, sizeof(rparam));
4294 rparam.mcast_obj = &sc->mcast_obj;
4296 /* clear pending state for the last command */
4297 sc->mcast_obj.raw.clear_pending(&sc->mcast_obj.raw);
4299 /* if there are pending mcast commands - send them */
4300 if (sc->mcast_obj.check_pending(&sc->mcast_obj)) {
4301 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
4303 PMD_DRV_LOG(INFO, sc,
4304 "Failed to send pending mcast commands (%d)",
4311 bnx2x_handle_classification_eqe(struct bnx2x_softc *sc, union event_ring_elem *elem)
4313 unsigned long ramrod_flags = 0;
4315 uint32_t cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4316 struct ecore_vlan_mac_obj *vlan_mac_obj;
4318 /* always push next commands out, don't wait here */
4319 bnx2x_set_bit(RAMROD_CONT, &ramrod_flags);
4321 switch (le32toh(elem->message.data.eth_event.echo) >> BNX2X_SWCID_SHIFT) {
4322 case ECORE_FILTER_MAC_PENDING:
4323 PMD_DRV_LOG(DEBUG, sc, "Got SETUP_MAC completions");
4324 vlan_mac_obj = &sc->sp_objs[cid].mac_obj;
4327 case ECORE_FILTER_MCAST_PENDING:
4328 PMD_DRV_LOG(DEBUG, sc, "Got SETUP_MCAST completions");
4329 bnx2x_handle_mcast_eqe(sc);
4333 PMD_DRV_LOG(NOTICE, sc, "Unsupported classification command: %d",
4334 elem->message.data.eth_event.echo);
4338 rc = vlan_mac_obj->complete(sc, vlan_mac_obj, elem, &ramrod_flags);
4341 PMD_DRV_LOG(NOTICE, sc,
4342 "Failed to schedule new commands (%d)", rc);
4343 } else if (rc > 0) {
4344 PMD_DRV_LOG(DEBUG, sc, "Scheduled next pending commands...");
4348 static void bnx2x_handle_rx_mode_eqe(struct bnx2x_softc *sc)
4350 bnx2x_clear_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
4352 /* send rx_mode command again if was requested */
4353 if (bnx2x_test_and_clear_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state)) {
4354 bnx2x_set_storm_rx_mode(sc);
4358 static void bnx2x_update_eq_prod(struct bnx2x_softc *sc, uint16_t prod)
4360 storm_memset_eq_prod(sc, prod, SC_FUNC(sc));
4361 wmb(); /* keep prod updates ordered */
4364 static void bnx2x_eq_int(struct bnx2x_softc *sc)
4366 uint16_t hw_cons, sw_cons, sw_prod;
4367 union event_ring_elem *elem;
4372 struct ecore_queue_sp_obj *q_obj;
4373 struct ecore_func_sp_obj *f_obj = &sc->func_obj;
4374 struct ecore_raw_obj *rss_raw = &sc->rss_conf_obj.raw;
4376 hw_cons = le16toh(*sc->eq_cons_sb);
4379 * The hw_cons range is 1-255, 257 - the sw_cons range is 0-254, 256.
4380 * when we get to the next-page we need to adjust so the loop
4381 * condition below will be met. The next element is the size of a
4382 * regular element and hence incrementing by 1
4384 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) {
4389 * This function may never run in parallel with itself for a
4390 * specific sc and no need for a read memory barrier here.
4392 sw_cons = sc->eq_cons;
4393 sw_prod = sc->eq_prod;
4397 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4399 elem = &sc->eq[EQ_DESC(sw_cons)];
4401 /* elem CID originates from FW, actually LE */
4402 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4403 opcode = elem->message.opcode;
4405 /* handle eq element */
4407 case EVENT_RING_OPCODE_STAT_QUERY:
4408 PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "got statistics completion event %d",
4410 /* nothing to do with stats comp */
4413 case EVENT_RING_OPCODE_CFC_DEL:
4414 /* handle according to cid range */
4415 /* we may want to verify here that the sc state is HALTING */
4416 PMD_DRV_LOG(DEBUG, sc, "got delete ramrod for MULTI[%d]",
4418 q_obj = bnx2x_cid_to_q_obj(sc, cid);
4419 if (q_obj->complete_cmd(sc, q_obj, ECORE_Q_CMD_CFC_DEL)) {
4424 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4425 PMD_DRV_LOG(DEBUG, sc, "got STOP TRAFFIC");
4426 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_STOP)) {
4431 case EVENT_RING_OPCODE_START_TRAFFIC:
4432 PMD_DRV_LOG(DEBUG, sc, "got START TRAFFIC");
4433 if (f_obj->complete_cmd
4434 (sc, f_obj, ECORE_F_CMD_TX_START)) {
4439 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
4440 echo = elem->message.data.function_update_event.echo;
4441 if (echo == SWITCH_UPDATE) {
4442 PMD_DRV_LOG(DEBUG, sc,
4443 "got FUNC_SWITCH_UPDATE ramrod");
4444 if (f_obj->complete_cmd(sc, f_obj,
4445 ECORE_F_CMD_SWITCH_UPDATE))
4450 PMD_DRV_LOG(DEBUG, sc,
4451 "AFEX: ramrod completed FUNCTION_UPDATE");
4452 f_obj->complete_cmd(sc, f_obj,
4453 ECORE_F_CMD_AFEX_UPDATE);
4457 case EVENT_RING_OPCODE_FORWARD_SETUP:
4458 q_obj = &bnx2x_fwd_sp_obj(sc, q_obj);
4459 if (q_obj->complete_cmd(sc, q_obj,
4460 ECORE_Q_CMD_SETUP_TX_ONLY)) {
4465 case EVENT_RING_OPCODE_FUNCTION_START:
4466 PMD_DRV_LOG(DEBUG, sc, "got FUNC_START ramrod");
4467 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_START)) {
4472 case EVENT_RING_OPCODE_FUNCTION_STOP:
4473 PMD_DRV_LOG(DEBUG, sc, "got FUNC_STOP ramrod");
4474 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_STOP)) {
4480 switch (opcode | sc->state) {
4481 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPEN):
4482 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPENING_WAITING_PORT):
4484 elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4485 PMD_DRV_LOG(DEBUG, sc, "got RSS_UPDATE ramrod. CID %d",
4487 rss_raw->clear_pending(rss_raw);
4490 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4491 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4492 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_CLOSING_WAITING_HALT):
4493 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_OPEN):
4494 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_DIAG):
4495 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4496 PMD_DRV_LOG(DEBUG, sc,
4497 "got (un)set mac ramrod");
4498 bnx2x_handle_classification_eqe(sc, elem);
4501 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_OPEN):
4502 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_DIAG):
4503 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4504 PMD_DRV_LOG(DEBUG, sc,
4505 "got mcast ramrod");
4506 bnx2x_handle_mcast_eqe(sc);
4509 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_OPEN):
4510 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_DIAG):
4511 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4512 PMD_DRV_LOG(DEBUG, sc,
4513 "got rx_mode ramrod");
4514 bnx2x_handle_rx_mode_eqe(sc);
4518 /* unknown event log error and continue */
4519 PMD_DRV_LOG(INFO, sc, "Unknown EQ event %d, sc->state 0x%x",
4520 elem->message.opcode, sc->state);
4528 atomic_add_acq_long(&sc->eq_spq_left, spqe_cnt);
4530 sc->eq_cons = sw_cons;
4531 sc->eq_prod = sw_prod;
4533 /* make sure that above mem writes were issued towards the memory */
4536 /* update producer */
4537 bnx2x_update_eq_prod(sc, sc->eq_prod);
4540 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc)
4545 PMD_DRV_LOG(DEBUG, sc, "---> SP TASK <---");
4547 /* what work needs to be performed? */
4548 status = bnx2x_update_dsb_idx(sc);
4550 PMD_DRV_LOG(DEBUG, sc, "dsb status 0x%04x", status);
4553 if (status & BNX2X_DEF_SB_ATT_IDX) {
4554 PMD_DRV_LOG(DEBUG, sc, "---> ATTN INTR <---");
4556 status &= ~BNX2X_DEF_SB_ATT_IDX;
4560 /* SP events: STAT_QUERY and others */
4561 if (status & BNX2X_DEF_SB_IDX) {
4562 /* handle EQ completions */
4563 PMD_DRV_LOG(DEBUG, sc, "---> EQ INTR <---");
4565 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
4566 le16toh(sc->def_idx), IGU_INT_NOP, 1);
4567 status &= ~BNX2X_DEF_SB_IDX;
4570 /* if status is non zero then something went wrong */
4571 if (unlikely(status)) {
4572 PMD_DRV_LOG(INFO, sc,
4573 "Got an unknown SP interrupt! (0x%04x)", status);
4576 /* ack status block only if something was actually handled */
4577 bnx2x_ack_sb(sc, sc->igu_dsb_id, ATTENTION_ID,
4578 le16toh(sc->def_att_idx), IGU_INT_ENABLE, 1);
4583 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp)
4585 struct bnx2x_softc *sc = fp->sc;
4586 uint8_t more_rx = FALSE;
4588 /* Make sure FP is initialized */
4589 if (!fp->sb_running_index)
4592 PMD_DEBUG_PERIODIC_LOG(DEBUG, sc,
4593 "---> FP TASK QUEUE (%d) <--", fp->index);
4595 /* update the fastpath index */
4596 bnx2x_update_fp_sb_idx(fp);
4598 if (rte_atomic32_read(&sc->scan_fp) == 1) {
4599 if (bnx2x_has_rx_work(fp)) {
4600 more_rx = bnx2x_rxeof(sc, fp);
4604 /* still more work to do */
4605 bnx2x_handle_fp_tq(fp);
4608 /* We have completed slow path completion, clear the flag */
4609 rte_atomic32_set(&sc->scan_fp, 0);
4612 bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
4613 le16toh(fp->fp_hc_idx), IGU_INT_ENABLE, 1);
4617 * Legacy interrupt entry point.
4619 * Verifies that the controller generated the interrupt and
4620 * then calls a separate routine to handle the various
4621 * interrupt causes: link, RX, and TX.
4623 int bnx2x_intr_legacy(struct bnx2x_softc *sc)
4625 struct bnx2x_fastpath *fp;
4626 uint32_t status, mask;
4630 * 0 for ustorm, 1 for cstorm
4631 * the bits returned from ack_int() are 0-15
4632 * bit 0 = attention status block
4633 * bit 1 = fast path status block
4634 * a mask of 0x2 or more = tx/rx event
4635 * a mask of 1 = slow path event
4638 status = bnx2x_ack_int(sc);
4640 /* the interrupt is not for us */
4641 if (unlikely(status == 0)) {
4645 PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "Interrupt status 0x%04x", status);
4646 //bnx2x_dump_status_block(sc);
4648 FOR_EACH_ETH_QUEUE(sc, i) {
4650 mask = (0x2 << (fp->index + CNIC_SUPPORT(sc)));
4651 if (status & mask) {
4652 /* acknowledge and disable further fastpath interrupts */
4653 bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
4654 0, IGU_INT_DISABLE, 0);
4655 bnx2x_handle_fp_tq(fp);
4660 if (unlikely(status & 0x1)) {
4661 /* acknowledge and disable further slowpath interrupts */
4662 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
4663 0, IGU_INT_DISABLE, 0);
4664 rc = bnx2x_handle_sp_tq(sc);
4668 if (unlikely(status)) {
4669 PMD_DRV_LOG(WARNING, sc,
4670 "Unexpected fastpath status (0x%08x)!", status);
4676 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc);
4677 static int bnx2x_init_hw_common(struct bnx2x_softc *sc);
4678 static int bnx2x_init_hw_port(struct bnx2x_softc *sc);
4679 static int bnx2x_init_hw_func(struct bnx2x_softc *sc);
4680 static void bnx2x_reset_common(struct bnx2x_softc *sc);
4681 static void bnx2x_reset_port(struct bnx2x_softc *sc);
4682 static void bnx2x_reset_func(struct bnx2x_softc *sc);
4683 static int bnx2x_init_firmware(struct bnx2x_softc *sc);
4684 static void bnx2x_release_firmware(struct bnx2x_softc *sc);
4687 ecore_func_sp_drv_ops bnx2x_func_sp_drv = {
4688 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
4689 .init_hw_cmn = bnx2x_init_hw_common,
4690 .init_hw_port = bnx2x_init_hw_port,
4691 .init_hw_func = bnx2x_init_hw_func,
4693 .reset_hw_cmn = bnx2x_reset_common,
4694 .reset_hw_port = bnx2x_reset_port,
4695 .reset_hw_func = bnx2x_reset_func,
4697 .init_fw = bnx2x_init_firmware,
4698 .release_fw = bnx2x_release_firmware,
4701 static void bnx2x_init_func_obj(struct bnx2x_softc *sc)
4705 PMD_INIT_FUNC_TRACE(sc);
4707 ecore_init_func_obj(sc,
4709 BNX2X_SP(sc, func_rdata),
4710 (rte_iova_t)BNX2X_SP_MAPPING(sc, func_rdata),
4711 BNX2X_SP(sc, func_afex_rdata),
4712 (rte_iova_t)BNX2X_SP_MAPPING(sc, func_afex_rdata),
4713 &bnx2x_func_sp_drv);
4716 static int bnx2x_init_hw(struct bnx2x_softc *sc, uint32_t load_code)
4718 struct ecore_func_state_params func_params = { NULL };
4721 PMD_INIT_FUNC_TRACE(sc);
4723 /* prepare the parameters for function state transitions */
4724 bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
4726 func_params.f_obj = &sc->func_obj;
4727 func_params.cmd = ECORE_F_CMD_HW_INIT;
4729 func_params.params.hw_init.load_phase = load_code;
4732 * Via a plethora of function pointers, we will eventually reach
4733 * bnx2x_init_hw_common(), bnx2x_init_hw_port(), or bnx2x_init_hw_func().
4735 rc = ecore_func_state_change(sc, &func_params);
4741 bnx2x_fill(struct bnx2x_softc *sc, uint32_t addr, int fill, uint32_t len)
4745 if (!(len % 4) && !(addr % 4)) {
4746 for (i = 0; i < len; i += 4) {
4747 REG_WR(sc, (addr + i), fill);
4750 for (i = 0; i < len; i++) {
4751 REG_WR8(sc, (addr + i), fill);
4756 /* writes FP SP data to FW - data_size in dwords */
4758 bnx2x_wr_fp_sb_data(struct bnx2x_softc *sc, int fw_sb_id, uint32_t * sb_data_p,
4763 for (index = 0; index < data_size; index++) {
4765 (BAR_CSTRORM_INTMEM +
4766 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
4767 (sizeof(uint32_t) * index)), *(sb_data_p + index));
4771 static void bnx2x_zero_fp_sb(struct bnx2x_softc *sc, int fw_sb_id)
4773 struct hc_status_block_data_e2 sb_data_e2;
4774 struct hc_status_block_data_e1x sb_data_e1x;
4775 uint32_t *sb_data_p;
4776 uint32_t data_size = 0;
4778 if (!CHIP_IS_E1x(sc)) {
4779 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4780 sb_data_e2.common.state = SB_DISABLED;
4781 sb_data_e2.common.p_func.vf_valid = FALSE;
4782 sb_data_p = (uint32_t *) & sb_data_e2;
4783 data_size = (sizeof(struct hc_status_block_data_e2) /
4786 memset(&sb_data_e1x, 0,
4787 sizeof(struct hc_status_block_data_e1x));
4788 sb_data_e1x.common.state = SB_DISABLED;
4789 sb_data_e1x.common.p_func.vf_valid = FALSE;
4790 sb_data_p = (uint32_t *) & sb_data_e1x;
4791 data_size = (sizeof(struct hc_status_block_data_e1x) /
4795 bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4798 (BAR_CSTRORM_INTMEM + CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id)), 0,
4799 CSTORM_STATUS_BLOCK_SIZE);
4800 bnx2x_fill(sc, (BAR_CSTRORM_INTMEM + CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id)),
4801 0, CSTORM_SYNC_BLOCK_SIZE);
4805 bnx2x_wr_sp_sb_data(struct bnx2x_softc *sc,
4806 struct hc_sp_status_block_data *sp_sb_data)
4811 i < (sizeof(struct hc_sp_status_block_data) / sizeof(uint32_t));
4814 (BAR_CSTRORM_INTMEM +
4815 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(SC_FUNC(sc)) +
4816 (i * sizeof(uint32_t))),
4817 *((uint32_t *) sp_sb_data + i));
4821 static void bnx2x_zero_sp_sb(struct bnx2x_softc *sc)
4823 struct hc_sp_status_block_data sp_sb_data;
4825 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4827 sp_sb_data.state = SB_DISABLED;
4828 sp_sb_data.p_func.vf_valid = FALSE;
4830 bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
4833 (BAR_CSTRORM_INTMEM +
4834 CSTORM_SP_STATUS_BLOCK_OFFSET(SC_FUNC(sc))),
4835 0, CSTORM_SP_STATUS_BLOCK_SIZE);
4837 (BAR_CSTRORM_INTMEM +
4838 CSTORM_SP_SYNC_BLOCK_OFFSET(SC_FUNC(sc))),
4839 0, CSTORM_SP_SYNC_BLOCK_SIZE);
4843 bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, int igu_sb_id,
4846 hc_sm->igu_sb_id = igu_sb_id;
4847 hc_sm->igu_seg_id = igu_seg_id;
4848 hc_sm->timer_value = 0xFF;
4849 hc_sm->time_to_expire = 0xFFFFFFFF;
4852 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
4854 /* zero out state machine indices */
4857 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4860 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4861 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
4862 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
4863 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
4868 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
4869 (SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4872 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
4873 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4874 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
4875 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4876 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
4877 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4878 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
4879 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4883 bnx2x_init_sb(struct bnx2x_softc *sc, rte_iova_t busaddr, int vfid,
4884 uint8_t vf_valid, int fw_sb_id, int igu_sb_id)
4886 struct hc_status_block_data_e2 sb_data_e2;
4887 struct hc_status_block_data_e1x sb_data_e1x;
4888 struct hc_status_block_sm *hc_sm_p;
4889 uint32_t *sb_data_p;
4893 if (CHIP_INT_MODE_IS_BC(sc)) {
4894 igu_seg_id = HC_SEG_ACCESS_NORM;
4896 igu_seg_id = IGU_SEG_ACCESS_NORM;
4899 bnx2x_zero_fp_sb(sc, fw_sb_id);
4901 if (!CHIP_IS_E1x(sc)) {
4902 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4903 sb_data_e2.common.state = SB_ENABLED;
4904 sb_data_e2.common.p_func.pf_id = SC_FUNC(sc);
4905 sb_data_e2.common.p_func.vf_id = vfid;
4906 sb_data_e2.common.p_func.vf_valid = vf_valid;
4907 sb_data_e2.common.p_func.vnic_id = SC_VN(sc);
4908 sb_data_e2.common.same_igu_sb_1b = TRUE;
4909 sb_data_e2.common.host_sb_addr.hi = U64_HI(busaddr);
4910 sb_data_e2.common.host_sb_addr.lo = U64_LO(busaddr);
4911 hc_sm_p = sb_data_e2.common.state_machine;
4912 sb_data_p = (uint32_t *) & sb_data_e2;
4913 data_size = (sizeof(struct hc_status_block_data_e2) /
4915 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
4917 memset(&sb_data_e1x, 0,
4918 sizeof(struct hc_status_block_data_e1x));
4919 sb_data_e1x.common.state = SB_ENABLED;
4920 sb_data_e1x.common.p_func.pf_id = SC_FUNC(sc);
4921 sb_data_e1x.common.p_func.vf_id = 0xff;
4922 sb_data_e1x.common.p_func.vf_valid = FALSE;
4923 sb_data_e1x.common.p_func.vnic_id = SC_VN(sc);
4924 sb_data_e1x.common.same_igu_sb_1b = TRUE;
4925 sb_data_e1x.common.host_sb_addr.hi = U64_HI(busaddr);
4926 sb_data_e1x.common.host_sb_addr.lo = U64_LO(busaddr);
4927 hc_sm_p = sb_data_e1x.common.state_machine;
4928 sb_data_p = (uint32_t *) & sb_data_e1x;
4929 data_size = (sizeof(struct hc_status_block_data_e1x) /
4931 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
4934 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], igu_sb_id, igu_seg_id);
4935 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], igu_sb_id, igu_seg_id);
4937 /* write indices to HW - PCI guarantees endianity of regpairs */
4938 bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4941 static uint8_t bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp)
4943 if (CHIP_IS_E1x(fp->sc)) {
4944 return fp->cl_id + SC_PORT(fp->sc) * ETH_MAX_RX_CLIENTS_E1H;
4951 bnx2x_rx_ustorm_prods_offset(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
4953 uint32_t offset = BAR_USTRORM_INTMEM;
4956 return PXP_VF_ADDR_USDM_QUEUES_START +
4957 (sc->acquire_resp.resc.hw_qid[fp->index] *
4958 sizeof(struct ustorm_queue_zone_data));
4959 } else if (!CHIP_IS_E1x(sc)) {
4960 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
4962 offset += USTORM_RX_PRODS_E1X_OFFSET(SC_PORT(sc), fp->cl_id);
4968 static void bnx2x_init_eth_fp(struct bnx2x_softc *sc, int idx)
4970 struct bnx2x_fastpath *fp = &sc->fp[idx];
4971 uint32_t cids[ECORE_MULTI_TX_COS] = { 0 };
4972 unsigned long q_type = 0;
4978 fp->igu_sb_id = (sc->igu_base_sb + idx + CNIC_SUPPORT(sc));
4979 fp->fw_sb_id = (sc->base_fw_ndsb + idx + CNIC_SUPPORT(sc));
4981 if (CHIP_IS_E1x(sc))
4982 fp->cl_id = SC_L_ID(sc) + idx;
4984 /* want client ID same as IGU SB ID for non-E1 */
4985 fp->cl_id = fp->igu_sb_id;
4986 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
4988 /* setup sb indices */
4989 if (!CHIP_IS_E1x(sc)) {
4990 fp->sb_index_values = fp->status_block.e2_sb->sb.index_values;
4991 fp->sb_running_index = fp->status_block.e2_sb->sb.running_index;
4993 fp->sb_index_values = fp->status_block.e1x_sb->sb.index_values;
4994 fp->sb_running_index =
4995 fp->status_block.e1x_sb->sb.running_index;
4999 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(sc, fp);
5001 fp->rx_cq_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS];
5003 for (cos = 0; cos < sc->max_cos; cos++) {
5006 fp->tx_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0];
5008 /* nothing more for a VF to do */
5013 bnx2x_init_sb(sc, fp->sb_dma.paddr, BNX2X_VF_ID_INVALID, FALSE,
5014 fp->fw_sb_id, fp->igu_sb_id);
5016 bnx2x_update_fp_sb_idx(fp);
5018 /* Configure Queue State object */
5019 bnx2x_set_bit(ECORE_Q_TYPE_HAS_RX, &q_type);
5020 bnx2x_set_bit(ECORE_Q_TYPE_HAS_TX, &q_type);
5022 ecore_init_queue_obj(sc,
5023 &sc->sp_objs[idx].q_obj,
5028 BNX2X_SP(sc, q_rdata),
5029 (rte_iova_t)BNX2X_SP_MAPPING(sc, q_rdata),
5032 /* configure classification DBs */
5033 ecore_init_mac_obj(sc,
5034 &sc->sp_objs[idx].mac_obj,
5038 BNX2X_SP(sc, mac_rdata),
5039 (rte_iova_t)BNX2X_SP_MAPPING(sc, mac_rdata),
5040 ECORE_FILTER_MAC_PENDING, &sc->sp_state,
5041 ECORE_OBJ_TYPE_RX_TX, &sc->macs_pool);
5045 bnx2x_update_rx_prod(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
5046 uint16_t rx_bd_prod, uint16_t rx_cq_prod)
5048 struct ustorm_eth_rx_producers rx_prods;
5051 memset(&rx_prods, 0, sizeof(rx_prods));
5053 /* update producers */
5054 rx_prods.bd_prod = rx_bd_prod;
5055 rx_prods.cqe_prod = rx_cq_prod;
5058 * Make sure that the BD and SGE data is updated before updating the
5059 * producers since FW might read the BD/SGE right after the producer
5061 * This is only applicable for weak-ordered memory model archs such
5062 * as IA-64. The following barrier is also mandatory since FW will
5063 * assumes BDs must have buffers.
5067 for (i = 0; i < (sizeof(rx_prods) / 4); i++) {
5068 REG_WR(sc, (fp->ustorm_rx_prods_offset + (i * 4)),
5069 ((uint32_t *)&rx_prods)[i]);
5072 wmb(); /* keep prod updates ordered */
5075 static void bnx2x_init_rx_rings(struct bnx2x_softc *sc)
5077 struct bnx2x_fastpath *fp;
5079 struct bnx2x_rx_queue *rxq;
5081 for (i = 0; i < sc->num_queues; i++) {
5083 rxq = sc->rx_queues[fp->index];
5085 PMD_RX_LOG(ERR, "RX queue is NULL");
5089 rxq->rx_bd_head = 0;
5090 rxq->rx_bd_tail = rxq->nb_rx_desc;
5091 rxq->rx_cq_head = 0;
5092 rxq->rx_cq_tail = TOTAL_RCQ_ENTRIES(rxq);
5093 *fp->rx_cq_cons_sb = 0;
5096 * Activate the BD ring...
5097 * Warning, this will generate an interrupt (to the TSTORM)
5098 * so this can only be done after the chip is initialized
5100 bnx2x_update_rx_prod(sc, fp, rxq->rx_bd_tail, rxq->rx_cq_tail);
5108 static void bnx2x_init_tx_ring_one(struct bnx2x_fastpath *fp)
5110 struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
5112 fp->tx_db.data.header.header = 1 << DOORBELL_HDR_DB_TYPE_SHIFT;
5113 fp->tx_db.data.zero_fill1 = 0;
5114 fp->tx_db.data.prod = 0;
5117 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
5121 txq->tx_pkt_tail = 0;
5122 txq->tx_pkt_head = 0;
5123 txq->tx_bd_tail = 0;
5124 txq->tx_bd_head = 0;
5127 static void bnx2x_init_tx_rings(struct bnx2x_softc *sc)
5131 for (i = 0; i < sc->num_queues; i++) {
5132 bnx2x_init_tx_ring_one(&sc->fp[i]);
5136 static void bnx2x_init_def_sb(struct bnx2x_softc *sc)
5138 struct host_sp_status_block *def_sb = sc->def_sb;
5139 rte_iova_t mapping = sc->def_sb_dma.paddr;
5140 int igu_sp_sb_index;
5142 int port = SC_PORT(sc);
5143 int func = SC_FUNC(sc);
5144 int reg_offset, reg_offset_en5;
5147 struct hc_sp_status_block_data sp_sb_data;
5149 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5151 if (CHIP_INT_MODE_IS_BC(sc)) {
5152 igu_sp_sb_index = DEF_SB_IGU_ID;
5153 igu_seg_id = HC_SEG_ACCESS_DEF;
5155 igu_sp_sb_index = sc->igu_dsb_id;
5156 igu_seg_id = IGU_SEG_ACCESS_DEF;
5160 section = ((uint64_t) mapping +
5161 offsetof(struct host_sp_status_block, atten_status_block));
5162 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5165 reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5166 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
5168 reg_offset_en5 = (port) ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5169 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0;
5171 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5172 /* take care of sig[0]..sig[4] */
5173 for (sindex = 0; sindex < 4; sindex++) {
5174 sc->attn_group[index].sig[sindex] =
5176 (reg_offset + (sindex * 0x4) +
5180 if (!CHIP_IS_E1x(sc)) {
5182 * enable5 is separate from the rest of the registers,
5183 * and the address skip is 4 and not 16 between the
5186 sc->attn_group[index].sig[4] =
5187 REG_RD(sc, (reg_offset_en5 + (0x4 * index)));
5189 sc->attn_group[index].sig[4] = 0;
5193 if (sc->devinfo.int_block == INT_BLOCK_HC) {
5195 port ? HC_REG_ATTN_MSG1_ADDR_L : HC_REG_ATTN_MSG0_ADDR_L;
5196 REG_WR(sc, reg_offset, U64_LO(section));
5197 REG_WR(sc, (reg_offset + 4), U64_HI(section));
5198 } else if (!CHIP_IS_E1x(sc)) {
5199 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5200 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5203 section = ((uint64_t) mapping +
5204 offsetof(struct host_sp_status_block, sp_sb));
5206 bnx2x_zero_sp_sb(sc);
5208 /* PCI guarantees endianity of regpair */
5209 sp_sb_data.state = SB_ENABLED;
5210 sp_sb_data.host_sb_addr.lo = U64_LO(section);
5211 sp_sb_data.host_sb_addr.hi = U64_HI(section);
5212 sp_sb_data.igu_sb_id = igu_sp_sb_index;
5213 sp_sb_data.igu_seg_id = igu_seg_id;
5214 sp_sb_data.p_func.pf_id = func;
5215 sp_sb_data.p_func.vnic_id = SC_VN(sc);
5216 sp_sb_data.p_func.vf_id = 0xff;
5218 bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
5220 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5223 static void bnx2x_init_sp_ring(struct bnx2x_softc *sc)
5225 atomic_store_rel_long(&sc->cq_spq_left, MAX_SPQ_PENDING);
5226 sc->spq_prod_idx = 0;
5228 &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_ETH_DEF_CONS];
5229 sc->spq_prod_bd = sc->spq;
5230 sc->spq_last_bd = (sc->spq_prod_bd + MAX_SP_DESC_CNT);
5233 static void bnx2x_init_eq_ring(struct bnx2x_softc *sc)
5235 union event_ring_elem *elem;
5238 for (i = 1; i <= NUM_EQ_PAGES; i++) {
5239 elem = &sc->eq[EQ_DESC_CNT_PAGE * i - 1];
5241 elem->next_page.addr.hi = htole32(U64_HI(sc->eq_dma.paddr +
5243 (i % NUM_EQ_PAGES)));
5244 elem->next_page.addr.lo = htole32(U64_LO(sc->eq_dma.paddr +
5246 (i % NUM_EQ_PAGES)));
5250 sc->eq_prod = NUM_EQ_DESC;
5251 sc->eq_cons_sb = &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_EQ_CONS];
5253 atomic_store_rel_long(&sc->eq_spq_left,
5254 (min((MAX_SP_DESC_CNT - MAX_SPQ_PENDING),
5258 static void bnx2x_init_internal_common(struct bnx2x_softc *sc)
5263 * Zero this manually as its initialization is currently missing
5266 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) {
5268 (BAR_USTRORM_INTMEM + USTORM_AGG_DATA_OFFSET + (i * 4)),
5272 if (!CHIP_IS_E1x(sc)) {
5273 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET),
5274 CHIP_INT_MODE_IS_BC(sc) ? HC_IGU_BC_MODE :
5279 static void bnx2x_init_internal(struct bnx2x_softc *sc, uint32_t load_code)
5281 switch (load_code) {
5282 case FW_MSG_CODE_DRV_LOAD_COMMON:
5283 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5284 bnx2x_init_internal_common(sc);
5287 case FW_MSG_CODE_DRV_LOAD_PORT:
5291 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5292 /* internal memory per function is initialized inside bnx2x_pf_init */
5296 PMD_DRV_LOG(NOTICE, sc, "Unknown load_code (0x%x) from MCP",
5303 storm_memset_func_cfg(struct bnx2x_softc *sc,
5304 struct tstorm_eth_function_common_config *tcfg,
5310 addr = (BAR_TSTRORM_INTMEM +
5311 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid));
5312 size = sizeof(struct tstorm_eth_function_common_config);
5313 ecore_storm_memset_struct(sc, addr, size, (uint32_t *) tcfg);
5316 static void bnx2x_func_init(struct bnx2x_softc *sc, struct bnx2x_func_init_params *p)
5318 struct tstorm_eth_function_common_config tcfg = { 0 };
5320 if (CHIP_IS_E1x(sc)) {
5321 storm_memset_func_cfg(sc, &tcfg, p->func_id);
5324 /* Enable the function in the FW */
5325 storm_memset_vf_to_pf(sc, p->func_id, p->pf_id);
5326 storm_memset_func_en(sc, p->func_id, 1);
5329 if (p->func_flgs & FUNC_FLG_SPQ) {
5330 storm_memset_spq_addr(sc, p->spq_map, p->func_id);
5332 (XSEM_REG_FAST_MEMORY +
5333 XSTORM_SPQ_PROD_OFFSET(p->func_id)), p->spq_prod);
5338 * Calculates the sum of vn_min_rates.
5339 * It's needed for further normalizing of the min_rates.
5341 * sum of vn_min_rates.
5343 * 0 - if all the min_rates are 0.
5344 * In the later case fainess algorithm should be deactivated.
5345 * If all min rates are not zero then those that are zeroes will be set to 1.
5347 static void bnx2x_calc_vn_min(struct bnx2x_softc *sc, struct cmng_init_input *input)
5350 uint32_t vn_min_rate;
5354 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5355 vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5356 vn_min_rate = (((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
5357 FUNC_MF_CFG_MIN_BW_SHIFT) * 100);
5359 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5360 /* skip hidden VNs */
5362 } else if (!vn_min_rate) {
5363 /* If min rate is zero - set it to 100 */
5364 vn_min_rate = DEF_MIN_RATE;
5369 input->vnic_min_rate[vn] = vn_min_rate;
5372 /* if ETS or all min rates are zeros - disable fairness */
5374 input->flags.cmng_enables &= ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5376 input->flags.cmng_enables |= CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5381 bnx2x_extract_max_cfg(__rte_unused struct bnx2x_softc *sc, uint32_t mf_cfg)
5383 uint16_t max_cfg = ((mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
5384 FUNC_MF_CFG_MAX_BW_SHIFT);
5387 PMD_DRV_LOG(DEBUG, sc,
5388 "Max BW configured to 0 - using 100 instead");
5396 bnx2x_calc_vn_max(struct bnx2x_softc *sc, int vn, struct cmng_init_input *input)
5398 uint16_t vn_max_rate;
5399 uint32_t vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5402 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5405 max_cfg = bnx2x_extract_max_cfg(sc, vn_cfg);
5408 /* max_cfg in percents of linkspeed */
5410 ((sc->link_vars.line_speed * max_cfg) / 100);
5411 } else { /* SD modes */
5412 /* max_cfg is absolute in 100Mb units */
5413 vn_max_rate = (max_cfg * 100);
5417 input->vnic_max_rate[vn] = vn_max_rate;
5421 bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg, uint8_t cmng_type)
5423 struct cmng_init_input input;
5426 memset(&input, 0, sizeof(struct cmng_init_input));
5428 input.port_rate = sc->link_vars.line_speed;
5430 if (cmng_type == CMNG_FNS_MINMAX) {
5431 /* read mf conf from shmem */
5433 bnx2x_read_mf_cfg(sc);
5436 /* get VN min rate and enable fairness if not 0 */
5437 bnx2x_calc_vn_min(sc, &input);
5439 /* get VN max rate */
5441 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5442 bnx2x_calc_vn_max(sc, vn, &input);
5446 /* always enable rate shaping and fairness */
5447 input.flags.cmng_enables |= CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
5449 ecore_init_cmng(&input, &sc->cmng);
5454 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc)
5456 if (CHIP_REV_IS_SLOW(sc)) {
5457 return CMNG_FNS_NONE;
5461 return CMNG_FNS_MINMAX;
5464 return CMNG_FNS_NONE;
5468 storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng, uint8_t port)
5475 addr = (BAR_XSTRORM_INTMEM + XSTORM_CMNG_PER_PORT_VARS_OFFSET(port));
5476 size = sizeof(struct cmng_struct_per_port);
5477 ecore_storm_memset_struct(sc, addr, size, (uint32_t *) & cmng->port);
5479 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5480 func = func_by_vn(sc, vn);
5482 addr = (BAR_XSTRORM_INTMEM +
5483 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func));
5484 size = sizeof(struct rate_shaping_vars_per_vn);
5485 ecore_storm_memset_struct(sc, addr, size,
5486 (uint32_t *) & cmng->
5487 vnic.vnic_max_rate[vn]);
5489 addr = (BAR_XSTRORM_INTMEM +
5490 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func));
5491 size = sizeof(struct fairness_vars_per_vn);
5492 ecore_storm_memset_struct(sc, addr, size,
5493 (uint32_t *) & cmng->
5494 vnic.vnic_min_rate[vn]);
5498 static void bnx2x_pf_init(struct bnx2x_softc *sc)
5500 struct bnx2x_func_init_params func_init;
5501 struct event_ring_data eq_data;
5504 memset(&eq_data, 0, sizeof(struct event_ring_data));
5505 memset(&func_init, 0, sizeof(struct bnx2x_func_init_params));
5507 if (!CHIP_IS_E1x(sc)) {
5508 /* reset IGU PF statistics: MSIX + ATTN */
5511 (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5512 (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5513 ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5517 (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5518 (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5519 (BNX2X_IGU_STAS_MSG_PF_CNT * 4) +
5520 ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5524 /* function setup flags */
5525 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
5527 func_init.func_flgs = flags;
5528 func_init.pf_id = SC_FUNC(sc);
5529 func_init.func_id = SC_FUNC(sc);
5530 func_init.spq_map = sc->spq_dma.paddr;
5531 func_init.spq_prod = sc->spq_prod_idx;
5533 bnx2x_func_init(sc, &func_init);
5535 memset(&sc->cmng, 0, sizeof(struct cmng_struct_per_port));
5538 * Congestion management values depend on the link rate.
5539 * There is no active link so initial link rate is set to 10Gbps.
5540 * When the link comes up the congestion management values are
5541 * re-calculated according to the actual link rate.
5543 sc->link_vars.line_speed = SPEED_10000;
5544 bnx2x_cmng_fns_init(sc, TRUE, bnx2x_get_cmng_fns_mode(sc));
5546 /* Only the PMF sets the HW */
5548 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
5551 /* init Event Queue - PCI bus guarantees correct endainity */
5552 eq_data.base_addr.hi = U64_HI(sc->eq_dma.paddr);
5553 eq_data.base_addr.lo = U64_LO(sc->eq_dma.paddr);
5554 eq_data.producer = sc->eq_prod;
5555 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
5556 eq_data.sb_id = DEF_SB_ID;
5557 storm_memset_eq_data(sc, &eq_data, SC_FUNC(sc));
5560 static void bnx2x_hc_int_enable(struct bnx2x_softc *sc)
5562 int port = SC_PORT(sc);
5563 uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5564 uint32_t val = REG_RD(sc, addr);
5565 uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5566 || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5567 uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5568 uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5571 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5572 HC_CONFIG_0_REG_INT_LINE_EN_0);
5573 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5574 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5576 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
5579 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
5580 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5581 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5582 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5584 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5585 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5586 HC_CONFIG_0_REG_INT_LINE_EN_0 |
5587 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5589 REG_WR(sc, addr, val);
5591 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
5594 REG_WR(sc, addr, val);
5596 /* ensure that HC_CONFIG is written before leading/trailing edge config */
5599 /* init leading/trailing edge */
5601 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5603 /* enable nig and gpio3 attention */
5610 REG_WR(sc, (HC_REG_TRAILING_EDGE_0 + port * 8), val);
5611 REG_WR(sc, (HC_REG_LEADING_EDGE_0 + port * 8), val);
5613 /* make sure that interrupts are indeed enabled from here on */
5617 static void bnx2x_igu_int_enable(struct bnx2x_softc *sc)
5620 uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5621 || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5622 uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5623 uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5625 val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5628 val &= ~(IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5629 val |= (IGU_PF_CONF_MSI_MSIX_EN | IGU_PF_CONF_ATTN_BIT_EN);
5631 val |= IGU_PF_CONF_SINGLE_ISR_EN;
5634 val &= ~IGU_PF_CONF_INT_LINE_EN;
5635 val |= (IGU_PF_CONF_MSI_MSIX_EN |
5636 IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5638 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
5639 val |= (IGU_PF_CONF_INT_LINE_EN |
5640 IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5643 /* clean previous status - need to configure igu prior to ack */
5644 if ((!msix) || single_msix) {
5645 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5649 val |= IGU_PF_CONF_FUNC_EN;
5651 PMD_DRV_LOG(DEBUG, sc, "write 0x%x to IGU mode %s",
5652 val, ((msix) ? "MSI-X" : ((msi) ? "MSI" : "INTx")));
5654 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5658 /* init leading/trailing edge */
5660 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5662 /* enable nig and gpio3 attention */
5669 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
5670 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
5672 /* make sure that interrupts are indeed enabled from here on */
5676 static void bnx2x_int_enable(struct bnx2x_softc *sc)
5678 if (sc->devinfo.int_block == INT_BLOCK_HC) {
5679 bnx2x_hc_int_enable(sc);
5681 bnx2x_igu_int_enable(sc);
5685 static void bnx2x_hc_int_disable(struct bnx2x_softc *sc)
5687 int port = SC_PORT(sc);
5688 uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5689 uint32_t val = REG_RD(sc, addr);
5691 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5692 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5693 HC_CONFIG_0_REG_INT_LINE_EN_0 | HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5694 /* flush all outstanding writes */
5697 REG_WR(sc, addr, val);
5698 if (REG_RD(sc, addr) != val) {
5699 PMD_DRV_LOG(ERR, sc, "proper val not read from HC IGU!");
5703 static void bnx2x_igu_int_disable(struct bnx2x_softc *sc)
5705 uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5707 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
5708 IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_ATTN_BIT_EN);
5710 PMD_DRV_LOG(DEBUG, sc, "write %x to IGU", val);
5712 /* flush all outstanding writes */
5715 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5716 if (REG_RD(sc, IGU_REG_PF_CONFIGURATION) != val) {
5717 PMD_DRV_LOG(ERR, sc, "proper val not read from IGU!");
5721 static void bnx2x_int_disable(struct bnx2x_softc *sc)
5723 if (sc->devinfo.int_block == INT_BLOCK_HC) {
5724 bnx2x_hc_int_disable(sc);
5726 bnx2x_igu_int_disable(sc);
5730 static void bnx2x_nic_init(struct bnx2x_softc *sc, int load_code)
5734 PMD_INIT_FUNC_TRACE(sc);
5736 for (i = 0; i < sc->num_queues; i++) {
5737 bnx2x_init_eth_fp(sc, i);
5740 rmb(); /* ensure status block indices were read */
5742 bnx2x_init_rx_rings(sc);
5743 bnx2x_init_tx_rings(sc);
5746 bnx2x_memset_stats(sc);
5750 /* initialize MOD_ABS interrupts */
5751 elink_init_mod_abs_int(sc, &sc->link_vars,
5752 sc->devinfo.chip_id,
5753 sc->devinfo.shmem_base,
5754 sc->devinfo.shmem2_base, SC_PORT(sc));
5756 bnx2x_init_def_sb(sc);
5757 bnx2x_update_dsb_idx(sc);
5758 bnx2x_init_sp_ring(sc);
5759 bnx2x_init_eq_ring(sc);
5760 bnx2x_init_internal(sc, load_code);
5762 bnx2x_stats_init(sc);
5764 /* flush all before enabling interrupts */
5767 bnx2x_int_enable(sc);
5769 /* check for SPIO5 */
5770 bnx2x_attn_int_deasserted0(sc,
5772 (MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
5774 AEU_INPUTS_ATTN_BITS_SPIO5);
5777 static void bnx2x_init_objs(struct bnx2x_softc *sc)
5779 /* mcast rules must be added to tx if tx switching is enabled */
5780 ecore_obj_type o_type;
5781 if (sc->flags & BNX2X_TX_SWITCHING)
5782 o_type = ECORE_OBJ_TYPE_RX_TX;
5784 o_type = ECORE_OBJ_TYPE_RX;
5786 /* RX_MODE controlling object */
5787 ecore_init_rx_mode_obj(sc, &sc->rx_mode_obj);
5789 /* multicast configuration controlling object */
5790 ecore_init_mcast_obj(sc,
5796 BNX2X_SP(sc, mcast_rdata),
5797 (rte_iova_t)BNX2X_SP_MAPPING(sc, mcast_rdata),
5798 ECORE_FILTER_MCAST_PENDING,
5799 &sc->sp_state, o_type);
5801 /* Setup CAM credit pools */
5802 ecore_init_mac_credit_pool(sc,
5805 CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5806 VNICS_PER_PATH(sc));
5808 ecore_init_vlan_credit_pool(sc,
5810 SC_ABS_FUNC(sc) >> 1,
5811 CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5812 VNICS_PER_PATH(sc));
5814 /* RSS configuration object */
5815 ecore_init_rss_config_obj(sc, &sc->rss_conf_obj, sc->fp->cl_id,
5816 sc->fp->index, SC_FUNC(sc), SC_FUNC(sc),
5817 BNX2X_SP(sc, rss_rdata),
5818 (rte_iova_t)BNX2X_SP_MAPPING(sc, rss_rdata),
5819 ECORE_FILTER_RSS_CONF_PENDING, &sc->sp_state,
5824 * Initialize the function. This must be called before sending CLIENT_SETUP
5825 * for the first client.
5827 static int bnx2x_func_start(struct bnx2x_softc *sc)
5829 struct ecore_func_state_params func_params = { NULL };
5830 struct ecore_func_start_params *start_params =
5831 &func_params.params.start;
5833 /* Prepare parameters for function state transitions */
5834 bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
5836 func_params.f_obj = &sc->func_obj;
5837 func_params.cmd = ECORE_F_CMD_START;
5839 /* Function parameters */
5840 start_params->mf_mode = sc->devinfo.mf_info.mf_mode;
5841 start_params->sd_vlan_tag = OVLAN(sc);
5843 if (CHIP_IS_E2(sc) || CHIP_IS_E3(sc)) {
5844 start_params->network_cos_mode = STATIC_COS;
5845 } else { /* CHIP_IS_E1X */
5846 start_params->network_cos_mode = FW_WRR;
5849 return ecore_func_state_change(sc, &func_params);
5852 static int bnx2x_set_power_state(struct bnx2x_softc *sc, uint8_t state)
5856 /* If there is no power capability, silently succeed */
5857 if (!(sc->devinfo.pcie_cap_flags & BNX2X_PM_CAPABLE_FLAG)) {
5858 PMD_DRV_LOG(INFO, sc, "No power capability");
5862 pci_read(sc, (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS), &pmcsr,
5868 (sc->devinfo.pcie_pm_cap_reg +
5870 ((pmcsr & ~PCIM_PSTAT_DMASK) | PCIM_PSTAT_PME));
5872 if (pmcsr & PCIM_PSTAT_DMASK) {
5873 /* delay required during transition out of D3hot */
5880 /* don't shut down the power for emulation and FPGA */
5881 if (CHIP_REV_IS_SLOW(sc)) {
5885 pmcsr &= ~PCIM_PSTAT_DMASK;
5886 pmcsr |= PCIM_PSTAT_D3;
5889 pmcsr |= PCIM_PSTAT_PMEENABLE;
5893 (sc->devinfo.pcie_pm_cap_reg +
5894 PCIR_POWER_STATUS), pmcsr);
5897 * No more memory access after this point until device is brought back
5903 PMD_DRV_LOG(NOTICE, sc, "Can't support PCI power state = %d",
5911 /* return true if succeeded to acquire the lock */
5912 static uint8_t bnx2x_trylock_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
5914 uint32_t lock_status;
5915 uint32_t resource_bit = (1 << resource);
5916 int func = SC_FUNC(sc);
5917 uint32_t hw_lock_control_reg;
5919 /* Validating that the resource is within range */
5920 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
5921 PMD_DRV_LOG(INFO, sc,
5922 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)",
5923 resource, HW_LOCK_MAX_RESOURCE_VALUE);
5928 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func * 8);
5930 hw_lock_control_reg =
5931 (MISC_REG_DRIVER_CONTROL_7 + (func - 6) * 8);
5934 /* try to acquire the lock */
5935 REG_WR(sc, hw_lock_control_reg + 4, resource_bit);
5936 lock_status = REG_RD(sc, hw_lock_control_reg);
5937 if (lock_status & resource_bit) {
5941 PMD_DRV_LOG(NOTICE, sc, "Failed to get a resource lock 0x%x", resource);
5947 * Get the recovery leader resource id according to the engine this function
5948 * belongs to. Currently only only 2 engines is supported.
5950 static int bnx2x_get_leader_lock_resource(struct bnx2x_softc *sc)
5953 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
5955 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
5959 /* try to acquire a leader lock for current engine */
5960 static uint8_t bnx2x_trylock_leader_lock(struct bnx2x_softc *sc)
5962 return bnx2x_trylock_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5965 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc)
5967 return bnx2x_release_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5970 /* close gates #2, #3 and #4 */
5971 static void bnx2x_set_234_gates(struct bnx2x_softc *sc, uint8_t close)
5975 /* gates #2 and #4a are closed/opened */
5977 REG_WR(sc, PXP_REG_HST_DISCARD_DOORBELLS, ! !close);
5979 REG_WR(sc, PXP_REG_HST_DISCARD_INTERNAL_WRITES, ! !close);
5982 if (CHIP_IS_E1x(sc)) {
5983 /* prevent interrupts from HC on both ports */
5984 val = REG_RD(sc, HC_REG_CONFIG_1);
5986 REG_WR(sc, HC_REG_CONFIG_1, (val & ~(uint32_t)
5987 HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5989 REG_WR(sc, HC_REG_CONFIG_1,
5990 (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5992 val = REG_RD(sc, HC_REG_CONFIG_0);
5994 REG_WR(sc, HC_REG_CONFIG_0, (val & ~(uint32_t)
5995 HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5997 REG_WR(sc, HC_REG_CONFIG_0,
5998 (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0));
6001 /* Prevent incoming interrupts in IGU */
6002 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
6005 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
6007 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
6009 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
6011 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
6017 /* poll for pending writes bit, it should get cleared in no more than 1s */
6018 static int bnx2x_er_poll_igu_vq(struct bnx2x_softc *sc)
6020 uint32_t cnt = 1000;
6021 uint32_t pend_bits = 0;
6024 pend_bits = REG_RD(sc, IGU_REG_PENDING_BITS_STATUS);
6026 if (pend_bits == 0) {
6031 } while (cnt-- > 0);
6034 PMD_DRV_LOG(NOTICE, sc, "Still pending IGU requests bits=0x%08x!",
6042 #define SHARED_MF_CLP_MAGIC 0x80000000 /* 'magic' bit */
6044 static void bnx2x_clp_reset_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
6046 /* Do some magic... */
6047 uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
6048 *magic_val = val & SHARED_MF_CLP_MAGIC;
6049 MFCFG_WR(sc, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
6052 /* restore the value of the 'magic' bit */
6053 static void bnx2x_clp_reset_done(struct bnx2x_softc *sc, uint32_t magic_val)
6055 /* Restore the 'magic' bit value... */
6056 uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
6057 MFCFG_WR(sc, shared_mf_config.clp_mb,
6058 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
6061 /* prepare for MCP reset, takes care of CLP configurations */
6062 static void bnx2x_reset_mcp_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
6065 uint32_t validity_offset;
6067 /* set `magic' bit in order to save MF config */
6068 bnx2x_clp_reset_prep(sc, magic_val);
6070 /* get shmem offset */
6071 shmem = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
6073 offsetof(struct shmem_region, validity_map[SC_PORT(sc)]);
6075 /* Clear validity map flags */
6077 REG_WR(sc, shmem + validity_offset, 0);
6081 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
6082 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
6084 static void bnx2x_mcp_wait_one(struct bnx2x_softc *sc)
6086 /* special handling for emulation and FPGA (10 times longer) */
6087 if (CHIP_REV_IS_SLOW(sc)) {
6088 DELAY((MCP_ONE_TIMEOUT * 10) * 1000);
6090 DELAY((MCP_ONE_TIMEOUT) * 1000);
6094 /* initialize shmem_base and waits for validity signature to appear */
6095 static int bnx2x_init_shmem(struct bnx2x_softc *sc)
6101 sc->devinfo.shmem_base =
6102 sc->link_params.shmem_base =
6103 REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
6105 if (sc->devinfo.shmem_base) {
6106 val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
6107 if (val & SHR_MEM_VALIDITY_MB)
6111 bnx2x_mcp_wait_one(sc);
6113 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
6115 PMD_DRV_LOG(NOTICE, sc, "BAD MCP validity signature");
6120 static int bnx2x_reset_mcp_comp(struct bnx2x_softc *sc, uint32_t magic_val)
6122 int rc = bnx2x_init_shmem(sc);
6124 /* Restore the `magic' bit value */
6125 bnx2x_clp_reset_done(sc, magic_val);
6130 static void bnx2x_pxp_prep(struct bnx2x_softc *sc)
6132 REG_WR(sc, PXP2_REG_RD_START_INIT, 0);
6133 REG_WR(sc, PXP2_REG_RQ_RBC_DONE, 0);
6138 * Reset the whole chip except for:
6140 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by one reset bit)
6142 * - MISC (including AEU)
6146 static void bnx2x_process_kill_chip_reset(struct bnx2x_softc *sc, uint8_t global)
6148 uint32_t not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
6149 uint32_t global_bits2, stay_reset2;
6152 * Bits that have to be set in reset_mask2 if we want to reset 'global'
6153 * (per chip) blocks.
6156 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
6157 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
6160 * Don't reset the following blocks.
6161 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
6162 * reset, as in 4 port device they might still be owned
6163 * by the MCP (there is only one leader per path).
6166 MISC_REGISTERS_RESET_REG_1_RST_HC |
6167 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
6168 MISC_REGISTERS_RESET_REG_1_RST_PXP;
6171 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
6172 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
6173 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
6174 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
6175 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
6176 MISC_REGISTERS_RESET_REG_2_RST_GRC |
6177 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
6178 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
6179 MISC_REGISTERS_RESET_REG_2_RST_ATC |
6180 MISC_REGISTERS_RESET_REG_2_PGLC |
6181 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
6182 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
6183 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
6184 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
6185 MISC_REGISTERS_RESET_REG_2_UMAC0 | MISC_REGISTERS_RESET_REG_2_UMAC1;
6188 * Keep the following blocks in reset:
6189 * - all xxMACs are handled by the elink code.
6192 MISC_REGISTERS_RESET_REG_2_XMAC |
6193 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
6195 /* Full reset masks according to the chip */
6196 reset_mask1 = 0xffffffff;
6198 if (CHIP_IS_E1H(sc))
6199 reset_mask2 = 0x1ffff;
6200 else if (CHIP_IS_E2(sc))
6201 reset_mask2 = 0xfffff;
6202 else /* CHIP_IS_E3 */
6203 reset_mask2 = 0x3ffffff;
6205 /* Don't reset global blocks unless we need to */
6207 reset_mask2 &= ~global_bits2;
6210 * In case of attention in the QM, we need to reset PXP
6211 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
6212 * because otherwise QM reset would release 'close the gates' shortly
6213 * before resetting the PXP, then the PSWRQ would send a write
6214 * request to PGLUE. Then when PXP is reset, PGLUE would try to
6215 * read the payload data from PSWWR, but PSWWR would not
6216 * respond. The write queue in PGLUE would stuck, dmae commands
6217 * would not return. Therefore it's important to reset the second
6218 * reset register (containing the
6219 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
6220 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
6223 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
6224 reset_mask2 & (~not_reset_mask2));
6226 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6227 reset_mask1 & (~not_reset_mask1));
6232 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
6233 reset_mask2 & (~stay_reset2));
6238 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
6242 static int bnx2x_process_kill(struct bnx2x_softc *sc, uint8_t global)
6246 uint32_t sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
6247 uint32_t tags_63_32 = 0;
6249 /* Empty the Tetris buffer, wait for 1s */
6251 sr_cnt = REG_RD(sc, PXP2_REG_RD_SR_CNT);
6252 blk_cnt = REG_RD(sc, PXP2_REG_RD_BLK_CNT);
6253 port_is_idle_0 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_0);
6254 port_is_idle_1 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_1);
6255 pgl_exp_rom2 = REG_RD(sc, PXP2_REG_PGL_EXP_ROM2);
6256 if (CHIP_IS_E3(sc)) {
6257 tags_63_32 = REG_RD(sc, PGLUE_B_REG_TAGS_63_32);
6260 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
6261 ((port_is_idle_0 & 0x1) == 0x1) &&
6262 ((port_is_idle_1 & 0x1) == 0x1) &&
6263 (pgl_exp_rom2 == 0xffffffff) &&
6264 (!CHIP_IS_E3(sc) || (tags_63_32 == 0xffffffff)))
6267 } while (cnt-- > 0);
6270 PMD_DRV_LOG(NOTICE, sc,
6271 "ERROR: Tetris buffer didn't get empty or there "
6272 "are still outstanding read requests after 1s! "
6273 "sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, "
6274 "port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x",
6275 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
6282 /* Close gates #2, #3 and #4 */
6283 bnx2x_set_234_gates(sc, TRUE);
6285 /* Poll for IGU VQs for 57712 and newer chips */
6286 if (!CHIP_IS_E1x(sc) && bnx2x_er_poll_igu_vq(sc)) {
6290 /* clear "unprepared" bit */
6291 REG_WR(sc, MISC_REG_UNPREPARED, 0);
6294 /* Make sure all is written to the chip before the reset */
6298 * Wait for 1ms to empty GLUE and PCI-E core queues,
6299 * PSWHST, GRC and PSWRD Tetris buffer.
6303 /* Prepare to chip reset: */
6306 bnx2x_reset_mcp_prep(sc, &val);
6313 /* reset the chip */
6314 bnx2x_process_kill_chip_reset(sc, global);
6317 /* Recover after reset: */
6319 if (global && bnx2x_reset_mcp_comp(sc, val)) {
6323 /* Open the gates #2, #3 and #4 */
6324 bnx2x_set_234_gates(sc, FALSE);
6329 static int bnx2x_leader_reset(struct bnx2x_softc *sc)
6332 uint8_t global = bnx2x_reset_is_global(sc);
6336 * If not going to reset MCP, load "fake" driver to reset HW while
6337 * driver is owner of the HW.
6339 if (!global && !BNX2X_NOMCP(sc)) {
6340 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
6341 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
6343 PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
6345 goto exit_leader_reset;
6348 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
6349 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
6350 PMD_DRV_LOG(NOTICE, sc,
6351 "MCP unexpected response, aborting");
6353 goto exit_leader_reset2;
6356 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
6358 PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
6360 goto exit_leader_reset2;
6364 /* try to recover after the failure */
6365 if (bnx2x_process_kill(sc, global)) {
6366 PMD_DRV_LOG(NOTICE, sc, "Something bad occurred on engine %d!",
6369 goto exit_leader_reset2;
6373 * Clear the RESET_IN_PROGRESS and RESET_GLOBAL bits and update the driver
6376 bnx2x_set_reset_done(sc);
6378 bnx2x_clear_reset_global(sc);
6383 /* unload "fake driver" if it was loaded */
6384 if (!global &&!BNX2X_NOMCP(sc)) {
6385 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
6386 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
6392 bnx2x_release_leader_lock(sc);
6399 * prepare INIT transition, parameters configured:
6400 * - HC configuration
6401 * - Queue's CDU context
6404 bnx2x_pf_q_prep_init(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6405 struct ecore_queue_init_params *init_params)
6408 int cxt_index, cxt_offset;
6410 bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->rx.flags);
6411 bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->tx.flags);
6413 bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->rx.flags);
6414 bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->tx.flags);
6417 init_params->rx.hc_rate =
6418 sc->hc_rx_ticks ? (1000000 / sc->hc_rx_ticks) : 0;
6419 init_params->tx.hc_rate =
6420 sc->hc_tx_ticks ? (1000000 / sc->hc_tx_ticks) : 0;
6423 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = fp->fw_sb_id;
6425 /* CQ index among the SB indices */
6426 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6427 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
6429 /* set maximum number of COSs supported by this queue */
6430 init_params->max_cos = sc->max_cos;
6432 /* set the context pointers queue object */
6433 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
6434 cxt_index = fp->index / ILT_PAGE_CIDS;
6435 cxt_offset = fp->index - (cxt_index * ILT_PAGE_CIDS);
6436 init_params->cxts[cos] =
6437 &sc->context[cxt_index].vcxt[cxt_offset].eth;
6441 /* set flags that are common for the Tx-only and not normal connections */
6442 static unsigned long
6443 bnx2x_get_common_flags(struct bnx2x_softc *sc, uint8_t zero_stats)
6445 unsigned long flags = 0;
6447 /* PF driver will always initialize the Queue to an ACTIVE state */
6448 bnx2x_set_bit(ECORE_Q_FLG_ACTIVE, &flags);
6451 * tx only connections collect statistics (on the same index as the
6452 * parent connection). The statistics are zeroed when the parent
6453 * connection is initialized.
6456 bnx2x_set_bit(ECORE_Q_FLG_STATS, &flags);
6458 bnx2x_set_bit(ECORE_Q_FLG_ZERO_STATS, &flags);
6462 * tx only connections can support tx-switching, though their
6463 * CoS-ness doesn't survive the loopback
6465 if (sc->flags & BNX2X_TX_SWITCHING) {
6466 bnx2x_set_bit(ECORE_Q_FLG_TX_SWITCH, &flags);
6469 bnx2x_set_bit(ECORE_Q_FLG_PCSUM_ON_PKT, &flags);
6474 static unsigned long bnx2x_get_q_flags(struct bnx2x_softc *sc, uint8_t leading)
6476 unsigned long flags = 0;
6479 bnx2x_set_bit(ECORE_Q_FLG_OV, &flags);
6483 bnx2x_set_bit(ECORE_Q_FLG_LEADING_RSS, &flags);
6484 bnx2x_set_bit(ECORE_Q_FLG_MCAST, &flags);
6487 bnx2x_set_bit(ECORE_Q_FLG_VLAN, &flags);
6489 /* merge with common flags */
6490 return flags | bnx2x_get_common_flags(sc, TRUE);
6494 bnx2x_pf_q_prep_general(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6495 struct ecore_general_setup_params *gen_init, uint8_t cos)
6497 gen_init->stat_id = bnx2x_stats_id(fp);
6498 gen_init->spcl_id = fp->cl_id;
6499 gen_init->mtu = sc->mtu;
6500 gen_init->cos = cos;
6504 bnx2x_pf_rx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6505 struct rxq_pause_params *pause,
6506 struct ecore_rxq_setup_params *rxq_init)
6508 struct bnx2x_rx_queue *rxq;
6510 rxq = sc->rx_queues[fp->index];
6512 PMD_RX_LOG(ERR, "RX queue is NULL");
6516 pause->bd_th_lo = BD_TH_LO(sc);
6517 pause->bd_th_hi = BD_TH_HI(sc);
6519 pause->rcq_th_lo = RCQ_TH_LO(sc);
6520 pause->rcq_th_hi = RCQ_TH_HI(sc);
6522 /* validate rings have enough entries to cross high thresholds */
6523 if (sc->dropless_fc &&
6524 pause->bd_th_hi + FW_PREFETCH_CNT > sc->rx_ring_size) {
6525 PMD_DRV_LOG(WARNING, sc, "rx bd ring threshold limit");
6528 if (sc->dropless_fc &&
6529 pause->rcq_th_hi + FW_PREFETCH_CNT > USABLE_RCQ_ENTRIES(rxq)) {
6530 PMD_DRV_LOG(WARNING, sc, "rcq ring threshold limit");
6536 rxq_init->dscr_map = (rte_iova_t)rxq->rx_ring_phys_addr;
6537 rxq_init->rcq_map = (rte_iova_t)rxq->cq_ring_phys_addr;
6538 rxq_init->rcq_np_map = (rte_iova_t)(rxq->cq_ring_phys_addr +
6542 * This should be a maximum number of data bytes that may be
6543 * placed on the BD (not including paddings).
6545 rxq_init->buf_sz = (fp->rx_buf_size - IP_HEADER_ALIGNMENT_PADDING);
6547 rxq_init->cl_qzone_id = fp->cl_qzone_id;
6548 rxq_init->rss_engine_id = SC_FUNC(sc);
6549 rxq_init->mcast_engine_id = SC_FUNC(sc);
6551 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
6552 rxq_init->fw_sb_id = fp->fw_sb_id;
6554 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6557 * configure silent vlan removal
6558 * if multi function mode is afex, then mask default vlan
6560 if (IS_MF_AFEX(sc)) {
6561 rxq_init->silent_removal_value =
6562 sc->devinfo.mf_info.afex_def_vlan_tag;
6563 rxq_init->silent_removal_mask = EVL_VLID_MASK;
6568 bnx2x_pf_tx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6569 struct ecore_txq_setup_params *txq_init, uint8_t cos)
6571 struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
6574 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
6577 txq_init->dscr_map = (rte_iova_t)txq->tx_ring_phys_addr;
6578 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
6579 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
6580 txq_init->fw_sb_id = fp->fw_sb_id;
6583 * set the TSS leading client id for TX classfication to the
6584 * leading RSS client id
6586 txq_init->tss_leading_cl_id = BNX2X_FP(sc, 0, cl_id);
6590 * This function performs 2 steps in a queue state machine:
6595 bnx2x_setup_queue(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp, uint8_t leading)
6597 struct ecore_queue_state_params q_params = { NULL };
6598 struct ecore_queue_setup_params *setup_params = &q_params.params.setup;
6601 PMD_DRV_LOG(DEBUG, sc, "setting up queue %d", fp->index);
6603 bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6605 q_params.q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
6607 /* we want to wait for completion in this context */
6608 bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
6610 /* prepare the INIT parameters */
6611 bnx2x_pf_q_prep_init(sc, fp, &q_params.params.init);
6613 /* Set the command */
6614 q_params.cmd = ECORE_Q_CMD_INIT;
6616 /* Change the state to INIT */
6617 rc = ecore_queue_state_change(sc, &q_params);
6619 PMD_DRV_LOG(NOTICE, sc, "Queue(%d) INIT failed", fp->index);
6623 PMD_DRV_LOG(DEBUG, sc, "init complete");
6625 /* now move the Queue to the SETUP state */
6626 memset(setup_params, 0, sizeof(*setup_params));
6628 /* set Queue flags */
6629 setup_params->flags = bnx2x_get_q_flags(sc, leading);
6631 /* set general SETUP parameters */
6632 bnx2x_pf_q_prep_general(sc, fp, &setup_params->gen_params,
6633 FIRST_TX_COS_INDEX);
6635 bnx2x_pf_rx_q_prep(sc, fp,
6636 &setup_params->pause_params,
6637 &setup_params->rxq_params);
6639 bnx2x_pf_tx_q_prep(sc, fp, &setup_params->txq_params, FIRST_TX_COS_INDEX);
6641 /* Set the command */
6642 q_params.cmd = ECORE_Q_CMD_SETUP;
6644 /* change the state to SETUP */
6645 rc = ecore_queue_state_change(sc, &q_params);
6647 PMD_DRV_LOG(NOTICE, sc, "Queue(%d) SETUP failed", fp->index);
6654 static int bnx2x_setup_leading(struct bnx2x_softc *sc)
6657 return bnx2x_setup_queue(sc, &sc->fp[0], TRUE);
6659 return bnx2x_vf_setup_queue(sc, &sc->fp[0], TRUE);
6663 bnx2x_config_rss_pf(struct bnx2x_softc *sc, struct ecore_rss_config_obj *rss_obj,
6664 uint8_t config_hash)
6666 struct ecore_config_rss_params params = { NULL };
6670 * Although RSS is meaningless when there is a single HW queue we
6671 * still need it enabled in order to have HW Rx hash generated.
6674 params.rss_obj = rss_obj;
6676 bnx2x_set_bit(RAMROD_COMP_WAIT, ¶ms.ramrod_flags);
6678 bnx2x_set_bit(ECORE_RSS_MODE_REGULAR, ¶ms.rss_flags);
6680 /* RSS configuration */
6681 bnx2x_set_bit(ECORE_RSS_IPV4, ¶ms.rss_flags);
6682 bnx2x_set_bit(ECORE_RSS_IPV4_TCP, ¶ms.rss_flags);
6683 bnx2x_set_bit(ECORE_RSS_IPV6, ¶ms.rss_flags);
6684 bnx2x_set_bit(ECORE_RSS_IPV6_TCP, ¶ms.rss_flags);
6685 if (rss_obj->udp_rss_v4) {
6686 bnx2x_set_bit(ECORE_RSS_IPV4_UDP, ¶ms.rss_flags);
6688 if (rss_obj->udp_rss_v6) {
6689 bnx2x_set_bit(ECORE_RSS_IPV6_UDP, ¶ms.rss_flags);
6693 params.rss_result_mask = MULTI_MASK;
6695 rte_memcpy(params.ind_table, rss_obj->ind_table,
6696 sizeof(params.ind_table));
6700 for (i = 0; i < sizeof(params.rss_key) / 4; i++) {
6701 params.rss_key[i] = (uint32_t) rte_rand();
6704 bnx2x_set_bit(ECORE_RSS_SET_SRCH, ¶ms.rss_flags);
6708 return ecore_config_rss(sc, ¶ms);
6710 return bnx2x_vf_config_rss(sc, ¶ms);
6713 static int bnx2x_config_rss_eth(struct bnx2x_softc *sc, uint8_t config_hash)
6715 return bnx2x_config_rss_pf(sc, &sc->rss_conf_obj, config_hash);
6718 static int bnx2x_init_rss_pf(struct bnx2x_softc *sc)
6720 uint8_t num_eth_queues = BNX2X_NUM_ETH_QUEUES(sc);
6724 * Prepare the initial contents of the indirection table if
6727 for (i = 0; i < sizeof(sc->rss_conf_obj.ind_table); i++) {
6728 sc->rss_conf_obj.ind_table[i] =
6729 (sc->fp->cl_id + (i % num_eth_queues));
6733 sc->rss_conf_obj.udp_rss_v4 = sc->rss_conf_obj.udp_rss_v6 = 1;
6737 * For 57711 SEARCHER configuration (rss_keys) is
6738 * per-port, so if explicit configuration is needed, do it only
6741 * For 57712 and newer it's a per-function configuration.
6743 return bnx2x_config_rss_eth(sc, sc->port.pmf || !CHIP_IS_E1x(sc));
6747 bnx2x_set_mac_one(struct bnx2x_softc *sc, uint8_t * mac,
6748 struct ecore_vlan_mac_obj *obj, uint8_t set, int mac_type,
6749 unsigned long *ramrod_flags)
6751 struct ecore_vlan_mac_ramrod_params ramrod_param;
6754 memset(&ramrod_param, 0, sizeof(ramrod_param));
6756 /* fill in general parameters */
6757 ramrod_param.vlan_mac_obj = obj;
6758 ramrod_param.ramrod_flags = *ramrod_flags;
6760 /* fill a user request section if needed */
6761 if (!bnx2x_test_bit(RAMROD_CONT, ramrod_flags)) {
6762 rte_memcpy(ramrod_param.user_req.u.mac.mac, mac,
6765 bnx2x_set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
6767 /* Set the command: ADD or DEL */
6768 ramrod_param.user_req.cmd = (set) ? ECORE_VLAN_MAC_ADD :
6772 rc = ecore_config_vlan_mac(sc, &ramrod_param);
6774 if (rc == ECORE_EXISTS) {
6775 PMD_DRV_LOG(INFO, sc, "Failed to schedule ADD operations (EEXIST)");
6776 /* do not treat adding same MAC as error */
6778 } else if (rc < 0) {
6779 PMD_DRV_LOG(ERR, sc,
6780 "%s MAC failed (%d)", (set ? "Set" : "Delete"), rc);
6786 static int bnx2x_set_eth_mac(struct bnx2x_softc *sc, uint8_t set)
6788 unsigned long ramrod_flags = 0;
6790 PMD_DRV_LOG(DEBUG, sc, "Adding Ethernet MAC");
6792 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
6794 /* Eth MAC is set on RSS leading client (fp[0]) */
6795 return bnx2x_set_mac_one(sc, sc->link_params.mac_addr,
6796 &sc->sp_objs->mac_obj,
6797 set, ECORE_ETH_MAC, &ramrod_flags);
6800 static int bnx2x_get_cur_phy_idx(struct bnx2x_softc *sc)
6802 uint32_t sel_phy_idx = 0;
6804 if (sc->link_params.num_phys <= 1) {
6805 return ELINK_INT_PHY;
6808 if (sc->link_vars.link_up) {
6809 sel_phy_idx = ELINK_EXT_PHY1;
6810 /* In case link is SERDES, check if the ELINK_EXT_PHY2 is the one */
6811 if ((sc->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
6812 (sc->link_params.phy[ELINK_EXT_PHY2].supported &
6813 ELINK_SUPPORTED_FIBRE))
6814 sel_phy_idx = ELINK_EXT_PHY2;
6816 switch (elink_phy_selection(&sc->link_params)) {
6817 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6818 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
6819 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6820 sel_phy_idx = ELINK_EXT_PHY1;
6822 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
6823 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6824 sel_phy_idx = ELINK_EXT_PHY2;
6832 static int bnx2x_get_link_cfg_idx(struct bnx2x_softc *sc)
6834 uint32_t sel_phy_idx = bnx2x_get_cur_phy_idx(sc);
6837 * The selected activated PHY is always after swapping (in case PHY
6838 * swapping is enabled). So when swapping is enabled, we need to reverse
6842 if (sc->link_params.multi_phy_config & PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
6843 if (sel_phy_idx == ELINK_EXT_PHY1)
6844 sel_phy_idx = ELINK_EXT_PHY2;
6845 else if (sel_phy_idx == ELINK_EXT_PHY2)
6846 sel_phy_idx = ELINK_EXT_PHY1;
6849 return ELINK_LINK_CONFIG_IDX(sel_phy_idx);
6852 static void bnx2x_set_requested_fc(struct bnx2x_softc *sc)
6855 * Initialize link parameters structure variables
6856 * It is recommended to turn off RX FC for jumbo frames
6857 * for better performance
6859 if (CHIP_IS_E1x(sc) && (sc->mtu > 5000)) {
6860 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_TX;
6862 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_BOTH;
6866 static void bnx2x_calc_fc_adv(struct bnx2x_softc *sc)
6868 uint8_t cfg_idx = bnx2x_get_link_cfg_idx(sc);
6869 switch (sc->link_vars.ieee_fc &
6870 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
6871 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
6873 sc->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
6877 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
6878 sc->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
6882 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
6883 sc->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
6888 static uint16_t bnx2x_get_mf_speed(struct bnx2x_softc *sc)
6890 uint16_t line_speed = sc->link_vars.line_speed;
6892 uint16_t maxCfg = bnx2x_extract_max_cfg(sc,
6894 mf_info.mf_config[SC_VN
6897 /* calculate the current MAX line speed limit for the MF devices */
6899 line_speed = (line_speed * maxCfg) / 100;
6900 } else { /* SD mode */
6901 uint16_t vn_max_rate = maxCfg * 100;
6903 if (vn_max_rate < line_speed) {
6904 line_speed = vn_max_rate;
6913 bnx2x_fill_report_data(struct bnx2x_softc *sc, struct bnx2x_link_report_data *data)
6915 uint16_t line_speed = bnx2x_get_mf_speed(sc);
6917 memset(data, 0, sizeof(*data));
6919 /* fill the report data with the effective line speed */
6920 data->line_speed = line_speed;
6923 if (!sc->link_vars.link_up || (sc->flags & BNX2X_MF_FUNC_DIS)) {
6924 bnx2x_set_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6925 &data->link_report_flags);
6929 if (sc->link_vars.duplex == DUPLEX_FULL) {
6930 bnx2x_set_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6931 &data->link_report_flags);
6934 /* Rx Flow Control is ON */
6935 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_RX) {
6936 bnx2x_set_bit(BNX2X_LINK_REPORT_RX_FC_ON, &data->link_report_flags);
6939 /* Tx Flow Control is ON */
6940 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
6941 bnx2x_set_bit(BNX2X_LINK_REPORT_TX_FC_ON, &data->link_report_flags);
6945 /* report link status to OS, should be called under phy_lock */
6946 static void bnx2x_link_report_locked(struct bnx2x_softc *sc)
6948 struct bnx2x_link_report_data cur_data;
6952 bnx2x_read_mf_cfg(sc);
6955 /* Read the current link report info */
6956 bnx2x_fill_report_data(sc, &cur_data);
6958 /* Don't report link down or exactly the same link status twice */
6959 if (!memcmp(&cur_data, &sc->last_reported_link, sizeof(cur_data)) ||
6960 (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6961 &sc->last_reported_link.link_report_flags) &&
6962 bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6963 &cur_data.link_report_flags))) {
6967 ELINK_DEBUG_P2(sc, "Change in link status : cur_data = %lx, last_reported_link = %lx",
6968 cur_data.link_report_flags,
6969 sc->last_reported_link.link_report_flags);
6973 ELINK_DEBUG_P1(sc, "link status change count = %x", sc->link_cnt);
6974 /* report new link params and remember the state for the next time */
6975 rte_memcpy(&sc->last_reported_link, &cur_data, sizeof(cur_data));
6977 if (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6978 &cur_data.link_report_flags)) {
6979 ELINK_DEBUG_P0(sc, "NIC Link is Down");
6981 __rte_unused const char *duplex;
6982 __rte_unused const char *flow;
6984 if (bnx2x_test_and_clear_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6985 &cur_data.link_report_flags)) {
6987 ELINK_DEBUG_P0(sc, "link set to full duplex");
6990 ELINK_DEBUG_P0(sc, "link set to half duplex");
6994 * Handle the FC at the end so that only these flags would be
6995 * possibly set. This way we may easily check if there is no FC
6998 if (cur_data.link_report_flags) {
6999 if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
7000 &cur_data.link_report_flags) &&
7001 bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
7002 &cur_data.link_report_flags)) {
7003 flow = "ON - receive & transmit";
7004 } else if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
7005 &cur_data.link_report_flags) &&
7006 !bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
7007 &cur_data.link_report_flags)) {
7008 flow = "ON - receive";
7009 } else if (!bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
7010 &cur_data.link_report_flags) &&
7011 bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
7012 &cur_data.link_report_flags)) {
7013 flow = "ON - transmit";
7015 flow = "none"; /* possible? */
7021 PMD_DRV_LOG(INFO, sc,
7022 "NIC Link is Up, %d Mbps %s duplex, Flow control: %s",
7023 cur_data.line_speed, duplex, flow);
7028 bnx2x_link_report(struct bnx2x_softc *sc)
7030 bnx2x_acquire_phy_lock(sc);
7031 bnx2x_link_report_locked(sc);
7032 bnx2x_release_phy_lock(sc);
7035 void bnx2x_link_status_update(struct bnx2x_softc *sc)
7037 if (sc->state != BNX2X_STATE_OPEN) {
7041 if (IS_PF(sc) && !CHIP_REV_IS_SLOW(sc)) {
7042 elink_link_status_update(&sc->link_params, &sc->link_vars);
7044 sc->port.supported[0] |= (ELINK_SUPPORTED_10baseT_Half |
7045 ELINK_SUPPORTED_10baseT_Full |
7046 ELINK_SUPPORTED_100baseT_Half |
7047 ELINK_SUPPORTED_100baseT_Full |
7048 ELINK_SUPPORTED_1000baseT_Full |
7049 ELINK_SUPPORTED_2500baseX_Full |
7050 ELINK_SUPPORTED_10000baseT_Full |
7051 ELINK_SUPPORTED_TP |
7052 ELINK_SUPPORTED_FIBRE |
7053 ELINK_SUPPORTED_Autoneg |
7054 ELINK_SUPPORTED_Pause |
7055 ELINK_SUPPORTED_Asym_Pause);
7056 sc->port.advertising[0] = sc->port.supported[0];
7058 sc->link_params.sc = sc;
7059 sc->link_params.port = SC_PORT(sc);
7060 sc->link_params.req_duplex[0] = DUPLEX_FULL;
7061 sc->link_params.req_flow_ctrl[0] = ELINK_FLOW_CTRL_NONE;
7062 sc->link_params.req_line_speed[0] = SPEED_10000;
7063 sc->link_params.speed_cap_mask[0] = 0x7f0000;
7064 sc->link_params.switch_cfg = ELINK_SWITCH_CFG_10G;
7066 if (CHIP_REV_IS_FPGA(sc)) {
7067 sc->link_vars.mac_type = ELINK_MAC_TYPE_EMAC;
7068 sc->link_vars.line_speed = ELINK_SPEED_1000;
7069 sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
7070 LINK_STATUS_SPEED_AND_DUPLEX_1000TFD);
7072 sc->link_vars.mac_type = ELINK_MAC_TYPE_BMAC;
7073 sc->link_vars.line_speed = ELINK_SPEED_10000;
7074 sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
7075 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
7078 sc->link_vars.link_up = 1;
7080 sc->link_vars.duplex = DUPLEX_FULL;
7081 sc->link_vars.flow_ctrl = ELINK_FLOW_CTRL_NONE;
7085 NIG_REG_EGRESS_DRAIN0_MODE +
7086 sc->link_params.port * 4, 0);
7087 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7088 bnx2x_link_report(sc);
7093 if (sc->link_vars.link_up) {
7094 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7096 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
7098 bnx2x_link_report(sc);
7100 bnx2x_link_report_locked(sc);
7101 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7105 static int bnx2x_initial_phy_init(struct bnx2x_softc *sc, int load_mode)
7107 int rc, cfg_idx = bnx2x_get_link_cfg_idx(sc);
7108 uint16_t req_line_speed = sc->link_params.req_line_speed[cfg_idx];
7109 struct elink_params *lp = &sc->link_params;
7111 bnx2x_set_requested_fc(sc);
7113 bnx2x_acquire_phy_lock(sc);
7115 if (load_mode == LOAD_DIAG) {
7116 lp->loopback_mode = ELINK_LOOPBACK_XGXS;
7117 /* Prefer doing PHY loopback at 10G speed, if possible */
7118 if (lp->req_line_speed[cfg_idx] < ELINK_SPEED_10000) {
7119 if (lp->speed_cap_mask[cfg_idx] &
7120 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
7121 lp->req_line_speed[cfg_idx] = ELINK_SPEED_10000;
7123 lp->req_line_speed[cfg_idx] = ELINK_SPEED_1000;
7128 if (load_mode == LOAD_LOOPBACK_EXT) {
7129 lp->loopback_mode = ELINK_LOOPBACK_EXT;
7132 rc = elink_phy_init(&sc->link_params, &sc->link_vars);
7134 bnx2x_release_phy_lock(sc);
7136 bnx2x_calc_fc_adv(sc);
7138 if (sc->link_vars.link_up) {
7139 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7140 bnx2x_link_report(sc);
7143 sc->link_params.req_line_speed[cfg_idx] = req_line_speed;
7147 /* update flags in shmem */
7149 bnx2x_update_drv_flags(struct bnx2x_softc *sc, uint32_t flags, uint32_t set)
7153 if (SHMEM2_HAS(sc, drv_flags)) {
7154 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7155 drv_flags = SHMEM2_RD(sc, drv_flags);
7160 drv_flags &= ~flags;
7163 SHMEM2_WR(sc, drv_flags, drv_flags);
7165 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7169 /* periodic timer callout routine, only runs when the interface is up */
7170 void bnx2x_periodic_callout(struct bnx2x_softc *sc)
7172 if ((sc->state != BNX2X_STATE_OPEN) ||
7173 (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_STOP)) {
7174 PMD_DRV_LOG(DEBUG, sc, "periodic callout exit (state=0x%x)",
7178 if (!CHIP_REV_IS_SLOW(sc)) {
7180 * This barrier is needed to ensure the ordering between the writing
7181 * to the sc->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
7186 bnx2x_acquire_phy_lock(sc);
7187 elink_period_func(&sc->link_params, &sc->link_vars);
7188 bnx2x_release_phy_lock(sc);
7192 if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7193 int mb_idx = SC_FW_MB_IDX(sc);
7197 ++sc->fw_drv_pulse_wr_seq;
7198 sc->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
7200 drv_pulse = sc->fw_drv_pulse_wr_seq;
7201 bnx2x_drv_pulse(sc);
7203 mcp_pulse = (SHMEM_RD(sc, func_mb[mb_idx].mcp_pulse_mb) &
7204 MCP_PULSE_SEQ_MASK);
7207 * The delta between driver pulse and mcp response should
7208 * be 1 (before mcp response) or 0 (after mcp response).
7210 if ((drv_pulse != mcp_pulse) &&
7211 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
7212 /* someone lost a heartbeat... */
7213 PMD_DRV_LOG(ERR, sc,
7214 "drv_pulse (0x%x) != mcp_pulse (0x%x)",
7215 drv_pulse, mcp_pulse);
7221 /* start the controller */
7222 static __rte_noinline
7223 int bnx2x_nic_load(struct bnx2x_softc *sc)
7226 uint32_t load_code = 0;
7229 PMD_INIT_FUNC_TRACE(sc);
7231 sc->state = BNX2X_STATE_OPENING_WAITING_LOAD;
7234 /* must be called before memory allocation and HW init */
7235 bnx2x_ilt_set_info(sc);
7238 bnx2x_set_fp_rx_buf_size(sc);
7241 if (bnx2x_alloc_mem(sc) != 0) {
7242 sc->state = BNX2X_STATE_CLOSED;
7244 goto bnx2x_nic_load_error0;
7248 /* allocate the host hardware/software hsi structures */
7249 if (bnx2x_alloc_hsi_mem(sc) != 0) {
7250 PMD_DRV_LOG(ERR, sc, "bnx2x_alloc_hsi_mem was failed");
7251 sc->state = BNX2X_STATE_CLOSED;
7253 goto bnx2x_nic_load_error0;
7256 if (bnx2x_alloc_fw_stats_mem(sc) != 0) {
7257 sc->state = BNX2X_STATE_CLOSED;
7259 goto bnx2x_nic_load_error0;
7263 rc = bnx2x_vf_init(sc);
7265 sc->state = BNX2X_STATE_ERROR;
7266 goto bnx2x_nic_load_error0;
7271 /* set pf load just before approaching the MCP */
7272 bnx2x_set_pf_load(sc);
7274 /* if MCP exists send load request and analyze response */
7275 if (!BNX2X_NOMCP(sc)) {
7276 /* attempt to load pf */
7277 if (bnx2x_nic_load_request(sc, &load_code) != 0) {
7278 sc->state = BNX2X_STATE_CLOSED;
7280 goto bnx2x_nic_load_error1;
7283 /* what did the MCP say? */
7284 if (bnx2x_nic_load_analyze_req(sc, load_code) != 0) {
7285 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7286 sc->state = BNX2X_STATE_CLOSED;
7288 goto bnx2x_nic_load_error2;
7291 PMD_DRV_LOG(INFO, sc, "Device has no MCP!");
7292 load_code = bnx2x_nic_load_no_mcp(sc);
7295 /* mark PMF if applicable */
7296 bnx2x_nic_load_pmf(sc, load_code);
7298 /* Init Function state controlling object */
7299 bnx2x_init_func_obj(sc);
7302 if (bnx2x_init_hw(sc, load_code) != 0) {
7303 PMD_DRV_LOG(NOTICE, sc, "HW init failed");
7304 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7305 sc->state = BNX2X_STATE_CLOSED;
7307 goto bnx2x_nic_load_error2;
7311 bnx2x_nic_init(sc, load_code);
7313 /* Init per-function objects */
7315 bnx2x_init_objs(sc);
7317 /* set AFEX default VLAN tag to an invalid value */
7318 sc->devinfo.mf_info.afex_def_vlan_tag = -1;
7320 sc->state = BNX2X_STATE_OPENING_WAITING_PORT;
7321 rc = bnx2x_func_start(sc);
7323 PMD_DRV_LOG(NOTICE, sc, "Function start failed!");
7324 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7325 sc->state = BNX2X_STATE_ERROR;
7326 goto bnx2x_nic_load_error3;
7329 /* send LOAD_DONE command to MCP */
7330 if (!BNX2X_NOMCP(sc)) {
7332 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7334 PMD_DRV_LOG(NOTICE, sc,
7335 "MCP response failure, aborting");
7336 sc->state = BNX2X_STATE_ERROR;
7338 goto bnx2x_nic_load_error3;
7343 rc = bnx2x_setup_leading(sc);
7345 PMD_DRV_LOG(NOTICE, sc, "Setup leading failed!");
7346 sc->state = BNX2X_STATE_ERROR;
7347 goto bnx2x_nic_load_error3;
7350 FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, i) {
7352 rc = bnx2x_setup_queue(sc, &sc->fp[i], FALSE);
7353 else /* IS_VF(sc) */
7354 rc = bnx2x_vf_setup_queue(sc, &sc->fp[i], FALSE);
7357 PMD_DRV_LOG(NOTICE, sc, "Queue(%d) setup failed", i);
7358 sc->state = BNX2X_STATE_ERROR;
7359 goto bnx2x_nic_load_error3;
7363 rc = bnx2x_init_rss_pf(sc);
7365 PMD_DRV_LOG(NOTICE, sc, "PF RSS init failed");
7366 sc->state = BNX2X_STATE_ERROR;
7367 goto bnx2x_nic_load_error3;
7370 /* now when Clients are configured we are ready to work */
7371 sc->state = BNX2X_STATE_OPEN;
7373 /* Configure a ucast MAC */
7375 rc = bnx2x_set_eth_mac(sc, TRUE);
7376 } else { /* IS_VF(sc) */
7377 rc = bnx2x_vf_set_mac(sc, TRUE);
7381 PMD_DRV_LOG(NOTICE, sc, "Setting Ethernet MAC failed");
7382 sc->state = BNX2X_STATE_ERROR;
7383 goto bnx2x_nic_load_error3;
7387 rc = bnx2x_initial_phy_init(sc, LOAD_OPEN);
7389 sc->state = BNX2X_STATE_ERROR;
7390 goto bnx2x_nic_load_error3;
7394 sc->link_params.feature_config_flags &=
7395 ~ELINK_FEATURE_CONFIG_BOOT_FROM_SAN;
7398 switch (LOAD_OPEN) {
7404 case LOAD_LOOPBACK_EXT:
7405 sc->state = BNX2X_STATE_DIAG;
7413 bnx2x_update_drv_flags(sc, 1 << DRV_FLAGS_PORT_MASK, 0);
7415 bnx2x_link_status_update(sc);
7418 if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
7419 /* mark driver is loaded in shmem2 */
7420 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
7421 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
7423 DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED |
7424 DRV_FLAGS_CAPABILITIES_LOADED_L2));
7427 /* start fast path */
7428 /* Initialize Rx filter */
7429 bnx2x_set_rx_mode(sc);
7431 /* wait for all pending SP commands to complete */
7432 if (IS_PF(sc) && !bnx2x_wait_sp_comp(sc, ~0x0UL)) {
7433 PMD_DRV_LOG(NOTICE, sc, "Timeout waiting for all SPs to complete!");
7434 bnx2x_periodic_stop(sc);
7435 bnx2x_nic_unload(sc, UNLOAD_CLOSE, FALSE);
7439 PMD_DRV_LOG(DEBUG, sc, "NIC successfully loaded");
7443 bnx2x_nic_load_error3:
7446 bnx2x_int_disable_sync(sc, 1);
7448 /* clean out queued objects */
7449 bnx2x_squeeze_objects(sc);
7452 bnx2x_nic_load_error2:
7454 if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7455 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
7456 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
7461 bnx2x_nic_load_error1:
7463 /* clear pf_load status, as it was already set */
7465 bnx2x_clear_pf_load(sc);
7468 bnx2x_nic_load_error0:
7470 bnx2x_free_fw_stats_mem(sc);
7471 bnx2x_free_hsi_mem(sc);
7478 * Handles controller initialization.
7480 int bnx2x_init(struct bnx2x_softc *sc)
7482 int other_engine = SC_PATH(sc) ? 0 : 1;
7483 uint8_t other_load_status, load_status;
7484 uint8_t global = FALSE;
7487 /* Check if the driver is still running and bail out if it is. */
7488 if (sc->state != BNX2X_STATE_CLOSED) {
7489 PMD_DRV_LOG(DEBUG, sc, "Init called while driver is running!");
7491 goto bnx2x_init_done;
7494 bnx2x_set_power_state(sc, PCI_PM_D0);
7497 * If parity occurred during the unload, then attentions and/or
7498 * RECOVERY_IN_PROGRESS may still be set. If so we want the first function
7499 * loaded on the current engine to complete the recovery. Parity recovery
7500 * is only relevant for PF driver.
7503 other_load_status = bnx2x_get_load_status(sc, other_engine);
7504 load_status = bnx2x_get_load_status(sc, SC_PATH(sc));
7506 if (!bnx2x_reset_is_done(sc, SC_PATH(sc)) ||
7507 bnx2x_chk_parity_attn(sc, &global, TRUE)) {
7510 * If there are attentions and they are in global blocks, set
7511 * the GLOBAL_RESET bit regardless whether it will be this
7512 * function that will complete the recovery or not.
7515 bnx2x_set_reset_global(sc);
7519 * Only the first function on the current engine should try
7520 * to recover in open. In case of attentions in global blocks
7521 * only the first in the chip should try to recover.
7524 && (!global ||!other_load_status))
7525 && bnx2x_trylock_leader_lock(sc)
7526 && !bnx2x_leader_reset(sc)) {
7527 PMD_DRV_LOG(INFO, sc,
7528 "Recovered during init");
7532 /* recovery has failed... */
7533 bnx2x_set_power_state(sc, PCI_PM_D3hot);
7535 sc->recovery_state = BNX2X_RECOVERY_FAILED;
7537 PMD_DRV_LOG(NOTICE, sc,
7538 "Recovery flow hasn't properly "
7539 "completed yet, try again later. "
7540 "If you still see this message after a "
7541 "few retries then power cycle is required.");
7544 goto bnx2x_init_done;
7549 sc->recovery_state = BNX2X_RECOVERY_DONE;
7551 rc = bnx2x_nic_load(sc);
7556 PMD_DRV_LOG(NOTICE, sc, "Initialization failed, "
7557 "stack notified driver is NOT running!");
7563 static void bnx2x_get_function_num(struct bnx2x_softc *sc)
7568 * Read the ME register to get the function number. The ME register
7569 * holds the relative-function number and absolute-function number. The
7570 * absolute-function number appears only in E2 and above. Before that
7571 * these bits always contained zero, therefore we cannot blindly use them.
7574 val = REG_RD(sc, BAR_ME_REGISTER);
7577 (uint8_t) ((val & ME_REG_PF_NUM) >> ME_REG_PF_NUM_SHIFT);
7579 (uint8_t) ((val & ME_REG_ABS_PF_NUM) >> ME_REG_ABS_PF_NUM_SHIFT) &
7582 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7583 sc->pfunc_abs = ((sc->pfunc_rel << 1) | sc->path_id);
7585 sc->pfunc_abs = (sc->pfunc_rel | sc->path_id);
7588 PMD_DRV_LOG(DEBUG, sc,
7589 "Relative function %d, Absolute function %d, Path %d",
7590 sc->pfunc_rel, sc->pfunc_abs, sc->path_id);
7593 static uint32_t bnx2x_get_shmem_mf_cfg_base(struct bnx2x_softc *sc)
7595 uint32_t shmem2_size;
7597 uint32_t mf_cfg_offset_value;
7600 offset = (SHMEM_ADDR(sc, func_mb) +
7601 (MAX_FUNC_NUM * sizeof(struct drv_func_mb)));
7604 if (sc->devinfo.shmem2_base != 0) {
7605 shmem2_size = SHMEM2_RD(sc, size);
7606 if (shmem2_size > offsetof(struct shmem2_region, mf_cfg_addr)) {
7607 mf_cfg_offset_value = SHMEM2_RD(sc, mf_cfg_addr);
7608 if (SHMEM_MF_CFG_ADDR_NONE != mf_cfg_offset_value) {
7609 offset = mf_cfg_offset_value;
7617 static uint32_t bnx2x_pcie_capability_read(struct bnx2x_softc *sc, int reg)
7620 struct bnx2x_pci_cap *caps;
7622 /* ensure PCIe capability is enabled */
7623 caps = pci_find_cap(sc, PCIY_EXPRESS, BNX2X_PCI_CAP);
7625 PMD_DRV_LOG(DEBUG, sc, "Found PCIe capability: "
7626 "id=0x%04X type=0x%04X addr=0x%08X",
7627 caps->id, caps->type, caps->addr);
7628 pci_read(sc, (caps->addr + reg), &ret, 2);
7632 PMD_DRV_LOG(WARNING, sc, "PCIe capability NOT FOUND!!!");
7637 static uint8_t bnx2x_is_pcie_pending(struct bnx2x_softc *sc)
7639 return bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_STA) &
7640 PCIM_EXP_STA_TRANSACTION_PND;
7644 * Walk the PCI capabiites list for the device to find what features are
7645 * supported. These capabilites may be enabled/disabled by firmware so it's
7646 * best to walk the list rather than make assumptions.
7648 static void bnx2x_probe_pci_caps(struct bnx2x_softc *sc)
7650 PMD_INIT_FUNC_TRACE(sc);
7652 struct bnx2x_pci_cap *caps;
7653 uint16_t link_status;
7656 /* check if PCI Power Management is enabled */
7657 caps = pci_find_cap(sc, PCIY_PMG, BNX2X_PCI_CAP);
7659 PMD_DRV_LOG(DEBUG, sc, "Found PM capability: "
7660 "id=0x%04X type=0x%04X addr=0x%08X",
7661 caps->id, caps->type, caps->addr);
7663 sc->devinfo.pcie_cap_flags |= BNX2X_PM_CAPABLE_FLAG;
7664 sc->devinfo.pcie_pm_cap_reg = caps->addr;
7667 link_status = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_LINK_STA);
7669 sc->devinfo.pcie_link_speed = (link_status & PCIM_LINK_STA_SPEED);
7670 sc->devinfo.pcie_link_width =
7671 ((link_status & PCIM_LINK_STA_WIDTH) >> 4);
7673 PMD_DRV_LOG(DEBUG, sc, "PCIe link speed=%d width=%d",
7674 sc->devinfo.pcie_link_speed, sc->devinfo.pcie_link_width);
7676 sc->devinfo.pcie_cap_flags |= BNX2X_PCIE_CAPABLE_FLAG;
7678 /* check if MSI capability is enabled */
7679 caps = pci_find_cap(sc, PCIY_MSI, BNX2X_PCI_CAP);
7681 PMD_DRV_LOG(DEBUG, sc, "Found MSI capability at 0x%04x", reg);
7683 sc->devinfo.pcie_cap_flags |= BNX2X_MSI_CAPABLE_FLAG;
7684 sc->devinfo.pcie_msi_cap_reg = caps->addr;
7687 /* check if MSI-X capability is enabled */
7688 caps = pci_find_cap(sc, PCIY_MSIX, BNX2X_PCI_CAP);
7690 PMD_DRV_LOG(DEBUG, sc, "Found MSI-X capability at 0x%04x", reg);
7692 sc->devinfo.pcie_cap_flags |= BNX2X_MSIX_CAPABLE_FLAG;
7693 sc->devinfo.pcie_msix_cap_reg = caps->addr;
7697 static int bnx2x_get_shmem_mf_cfg_info_sd(struct bnx2x_softc *sc)
7699 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7702 /* get the outer vlan if we're in switch-dependent mode */
7704 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7705 mf_info->ext_id = (uint16_t) val;
7707 mf_info->multi_vnics_mode = 1;
7709 if (!VALID_OVLAN(mf_info->ext_id)) {
7710 PMD_DRV_LOG(NOTICE, sc, "Invalid VLAN (%d)", mf_info->ext_id);
7714 /* get the capabilities */
7715 if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK) ==
7716 FUNC_MF_CFG_PROTOCOL_ISCSI) {
7717 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ISCSI;
7718 } else if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK)
7719 == FUNC_MF_CFG_PROTOCOL_FCOE) {
7720 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_FCOE;
7722 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ETHERNET;
7725 mf_info->vnics_per_port =
7726 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7731 static uint32_t bnx2x_get_shmem_ext_proto_support_flags(struct bnx2x_softc *sc)
7733 uint32_t retval = 0;
7736 val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7738 if (val & MACP_FUNC_CFG_FLAGS_ENABLED) {
7739 if (val & MACP_FUNC_CFG_FLAGS_ETHERNET) {
7740 retval |= MF_PROTO_SUPPORT_ETHERNET;
7742 if (val & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
7743 retval |= MF_PROTO_SUPPORT_ISCSI;
7745 if (val & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
7746 retval |= MF_PROTO_SUPPORT_FCOE;
7753 static int bnx2x_get_shmem_mf_cfg_info_si(struct bnx2x_softc *sc)
7755 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7759 * There is no outer vlan if we're in switch-independent mode.
7760 * If the mac is valid then assume multi-function.
7763 val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7765 mf_info->multi_vnics_mode = ((val & MACP_FUNC_CFG_FLAGS_MASK) != 0);
7767 mf_info->mf_protos_supported =
7768 bnx2x_get_shmem_ext_proto_support_flags(sc);
7770 mf_info->vnics_per_port =
7771 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7776 static int bnx2x_get_shmem_mf_cfg_info_niv(struct bnx2x_softc *sc)
7778 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7780 uint32_t func_config;
7781 uint32_t niv_config;
7783 mf_info->multi_vnics_mode = 1;
7785 e1hov_tag = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7786 func_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7787 niv_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].afex_config);
7790 (uint16_t) ((e1hov_tag & FUNC_MF_CFG_E1HOV_TAG_MASK) >>
7791 FUNC_MF_CFG_E1HOV_TAG_SHIFT);
7793 mf_info->default_vlan =
7794 (uint16_t) ((e1hov_tag & FUNC_MF_CFG_AFEX_VLAN_MASK) >>
7795 FUNC_MF_CFG_AFEX_VLAN_SHIFT);
7797 mf_info->niv_allowed_priorities =
7798 (uint8_t) ((niv_config & FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
7799 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT);
7801 mf_info->niv_default_cos =
7802 (uint8_t) ((func_config & FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
7803 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT);
7805 mf_info->afex_vlan_mode =
7806 ((niv_config & FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
7807 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT);
7809 mf_info->niv_mba_enabled =
7810 ((niv_config & FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK) >>
7811 FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT);
7813 mf_info->mf_protos_supported =
7814 bnx2x_get_shmem_ext_proto_support_flags(sc);
7816 mf_info->vnics_per_port =
7817 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7822 static int bnx2x_check_valid_mf_cfg(struct bnx2x_softc *sc)
7824 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7831 /* various MF mode sanity checks... */
7833 if (mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_HIDE) {
7834 PMD_DRV_LOG(NOTICE, sc,
7835 "Enumerated function %d is marked as hidden",
7840 if ((mf_info->vnics_per_port > 1) && !mf_info->multi_vnics_mode) {
7841 PMD_DRV_LOG(NOTICE, sc, "vnics_per_port=%d multi_vnics_mode=%d",
7842 mf_info->vnics_per_port, mf_info->multi_vnics_mode);
7846 if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7847 /* vnic id > 0 must have valid ovlan in switch-dependent mode */
7848 if ((SC_VN(sc) > 0) && !VALID_OVLAN(OVLAN(sc))) {
7849 PMD_DRV_LOG(NOTICE, sc, "mf_mode=SD vnic_id=%d ovlan=%d",
7850 SC_VN(sc), OVLAN(sc));
7854 if (!VALID_OVLAN(OVLAN(sc)) && mf_info->multi_vnics_mode) {
7855 PMD_DRV_LOG(NOTICE, sc,
7856 "mf_mode=SD multi_vnics_mode=%d ovlan=%d",
7857 mf_info->multi_vnics_mode, OVLAN(sc));
7862 * Verify all functions are either MF or SF mode. If MF, make sure
7863 * sure that all non-hidden functions have a valid ovlan. If SF,
7864 * make sure that all non-hidden functions have an invalid ovlan.
7866 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7867 mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7868 ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7869 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE) &&
7870 (((mf_info->multi_vnics_mode)
7871 && !VALID_OVLAN(ovlan1))
7872 || ((!mf_info->multi_vnics_mode)
7873 && VALID_OVLAN(ovlan1)))) {
7874 PMD_DRV_LOG(NOTICE, sc,
7875 "mf_mode=SD function %d MF config "
7876 "mismatch, multi_vnics_mode=%d ovlan=%d",
7877 i, mf_info->multi_vnics_mode,
7883 /* Verify all funcs on the same port each have a different ovlan. */
7884 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7885 mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7886 ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7887 /* iterate from the next function on the port to the max func */
7888 for (j = i + 2; j < MAX_FUNC_NUM; j += 2) {
7890 MFCFG_RD(sc, func_mf_config[j].config);
7892 MFCFG_RD(sc, func_mf_config[j].e1hov_tag);
7893 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE)
7894 && VALID_OVLAN(ovlan1)
7895 && !(mf_cfg2 & FUNC_MF_CFG_FUNC_HIDE)
7896 && VALID_OVLAN(ovlan2)
7897 && (ovlan1 == ovlan2)) {
7898 PMD_DRV_LOG(NOTICE, sc,
7899 "mf_mode=SD functions %d and %d "
7900 "have the same ovlan (%d)",
7907 /* MULTI_FUNCTION_SD */
7911 static int bnx2x_get_mf_cfg_info(struct bnx2x_softc *sc)
7913 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7914 uint32_t val, mac_upper;
7917 /* initialize mf_info defaults */
7918 mf_info->vnics_per_port = 1;
7919 mf_info->multi_vnics_mode = FALSE;
7920 mf_info->path_has_ovlan = FALSE;
7921 mf_info->mf_mode = SINGLE_FUNCTION;
7923 if (!CHIP_IS_MF_CAP(sc)) {
7927 if (sc->devinfo.mf_cfg_base == SHMEM_MF_CFG_ADDR_NONE) {
7928 PMD_DRV_LOG(NOTICE, sc, "Invalid mf_cfg_base!");
7932 /* get the MF mode (switch dependent / independent / single-function) */
7934 val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
7936 switch (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK) {
7937 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
7940 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7942 /* check for legal upper mac bytes */
7943 if (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT) {
7944 mf_info->mf_mode = MULTI_FUNCTION_SI;
7946 PMD_DRV_LOG(NOTICE, sc,
7947 "Invalid config for Switch Independent mode");
7952 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
7953 case SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4:
7955 /* get outer vlan configuration */
7956 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7958 if ((val & FUNC_MF_CFG_E1HOV_TAG_MASK) !=
7959 FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
7960 mf_info->mf_mode = MULTI_FUNCTION_SD;
7962 PMD_DRV_LOG(NOTICE, sc,
7963 "Invalid config for Switch Dependent mode");
7968 case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
7970 /* not in MF mode, vnics_per_port=1 and multi_vnics_mode=FALSE */
7973 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
7976 * Mark MF mode as NIV if MCP version includes NPAR-SD support
7977 * and the MAC address is valid.
7980 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7982 if ((SHMEM2_HAS(sc, afex_driver_support)) &&
7983 (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT)) {
7984 mf_info->mf_mode = MULTI_FUNCTION_AFEX;
7986 PMD_DRV_LOG(NOTICE, sc, "Invalid config for AFEX mode");
7993 PMD_DRV_LOG(NOTICE, sc, "Unknown MF mode (0x%08x)",
7994 (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK));
7999 /* set path mf_mode (which could be different than function mf_mode) */
8000 if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
8001 mf_info->path_has_ovlan = TRUE;
8002 } else if (mf_info->mf_mode == SINGLE_FUNCTION) {
8004 * Decide on path multi vnics mode. If we're not in MF mode and in
8005 * 4-port mode, this is good enough to check vnic-0 of the other port
8008 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
8009 uint8_t other_port = !(PORT_ID(sc) & 1);
8010 uint8_t abs_func_other_port =
8011 (SC_PATH(sc) + (2 * other_port));
8016 [abs_func_other_port].e1hov_tag);
8018 mf_info->path_has_ovlan = VALID_OVLAN((uint16_t) val);
8022 if (mf_info->mf_mode == SINGLE_FUNCTION) {
8023 /* invalid MF config */
8024 if (SC_VN(sc) >= 1) {
8025 PMD_DRV_LOG(NOTICE, sc, "VNIC ID >= 1 in SF mode");
8032 /* get the MF configuration */
8033 mf_info->mf_config[SC_VN(sc)] =
8034 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
8036 switch (mf_info->mf_mode) {
8037 case MULTI_FUNCTION_SD:
8039 bnx2x_get_shmem_mf_cfg_info_sd(sc);
8042 case MULTI_FUNCTION_SI:
8044 bnx2x_get_shmem_mf_cfg_info_si(sc);
8047 case MULTI_FUNCTION_AFEX:
8049 bnx2x_get_shmem_mf_cfg_info_niv(sc);
8054 PMD_DRV_LOG(NOTICE, sc, "Get MF config failed (mf_mode=0x%08x)",
8059 /* get the congestion management parameters */
8062 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
8063 /* get min/max bw */
8064 val = MFCFG_RD(sc, func_mf_config[i].config);
8065 mf_info->min_bw[vnic] =
8066 ((val & FUNC_MF_CFG_MIN_BW_MASK) >>
8067 FUNC_MF_CFG_MIN_BW_SHIFT);
8068 mf_info->max_bw[vnic] =
8069 ((val & FUNC_MF_CFG_MAX_BW_MASK) >>
8070 FUNC_MF_CFG_MAX_BW_SHIFT);
8074 return bnx2x_check_valid_mf_cfg(sc);
8077 static int bnx2x_get_shmem_info(struct bnx2x_softc *sc)
8080 uint32_t mac_hi, mac_lo, val;
8082 PMD_INIT_FUNC_TRACE(sc);
8085 mac_hi = mac_lo = 0;
8087 sc->link_params.sc = sc;
8088 sc->link_params.port = port;
8090 /* get the hardware config info */
8091 sc->devinfo.hw_config = SHMEM_RD(sc, dev_info.shared_hw_config.config);
8092 sc->devinfo.hw_config2 =
8093 SHMEM_RD(sc, dev_info.shared_hw_config.config2);
8095 sc->link_params.hw_led_mode =
8096 ((sc->devinfo.hw_config & SHARED_HW_CFG_LED_MODE_MASK) >>
8097 SHARED_HW_CFG_LED_MODE_SHIFT);
8099 /* get the port feature config */
8101 SHMEM_RD(sc, dev_info.port_feature_config[port].config);
8103 /* get the link params */
8104 sc->link_params.speed_cap_mask[ELINK_INT_PHY] =
8105 SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask)
8106 & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
8107 sc->link_params.speed_cap_mask[ELINK_EXT_PHY1] =
8108 SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask2)
8109 & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
8111 /* get the lane config */
8112 sc->link_params.lane_config =
8113 SHMEM_RD(sc, dev_info.port_hw_config[port].lane_config);
8115 /* get the link config */
8116 val = SHMEM_RD(sc, dev_info.port_feature_config[port].link_config);
8117 sc->port.link_config[ELINK_INT_PHY] = val;
8118 sc->link_params.switch_cfg = (val & PORT_FEATURE_CONNECTED_SWITCH_MASK);
8119 sc->port.link_config[ELINK_EXT_PHY1] =
8120 SHMEM_RD(sc, dev_info.port_feature_config[port].link_config2);
8122 /* get the override preemphasis flag and enable it or turn it off */
8123 val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
8124 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) {
8125 sc->link_params.feature_config_flags |=
8126 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8128 sc->link_params.feature_config_flags &=
8129 ~ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8132 val = sc->devinfo.bc_ver >> 8;
8133 if (val < BNX2X_BC_VER) {
8134 /* for now only warn later we might need to enforce this */
8135 PMD_DRV_LOG(NOTICE, sc, "This driver needs bc_ver %X but found %X, please upgrade BC\n",
8138 sc->link_params.feature_config_flags |=
8139 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
8140 ELINK_FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY :
8143 sc->link_params.feature_config_flags |=
8144 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
8145 ELINK_FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
8146 sc->link_params.feature_config_flags |=
8147 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
8148 ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
8149 sc->link_params.feature_config_flags |=
8150 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
8151 ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
8153 /* get the initial value of the link params */
8154 sc->link_params.multi_phy_config =
8155 SHMEM_RD(sc, dev_info.port_hw_config[port].multi_phy_config);
8157 /* get external phy info */
8158 sc->port.ext_phy_config =
8159 SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
8161 /* get the multifunction configuration */
8162 bnx2x_get_mf_cfg_info(sc);
8164 /* get the mac address */
8167 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
8169 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_lower);
8171 mac_hi = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_upper);
8172 mac_lo = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_lower);
8175 if ((mac_lo == 0) && (mac_hi == 0)) {
8176 *sc->mac_addr_str = 0;
8177 PMD_DRV_LOG(NOTICE, sc, "No Ethernet address programmed!");
8179 sc->link_params.mac_addr[0] = (uint8_t) (mac_hi >> 8);
8180 sc->link_params.mac_addr[1] = (uint8_t) (mac_hi);
8181 sc->link_params.mac_addr[2] = (uint8_t) (mac_lo >> 24);
8182 sc->link_params.mac_addr[3] = (uint8_t) (mac_lo >> 16);
8183 sc->link_params.mac_addr[4] = (uint8_t) (mac_lo >> 8);
8184 sc->link_params.mac_addr[5] = (uint8_t) (mac_lo);
8185 snprintf(sc->mac_addr_str, sizeof(sc->mac_addr_str),
8186 "%02x:%02x:%02x:%02x:%02x:%02x",
8187 sc->link_params.mac_addr[0],
8188 sc->link_params.mac_addr[1],
8189 sc->link_params.mac_addr[2],
8190 sc->link_params.mac_addr[3],
8191 sc->link_params.mac_addr[4],
8192 sc->link_params.mac_addr[5]);
8193 PMD_DRV_LOG(DEBUG, sc,
8194 "Ethernet address: %s", sc->mac_addr_str);
8200 static void bnx2x_media_detect(struct bnx2x_softc *sc)
8202 uint32_t phy_idx = bnx2x_get_cur_phy_idx(sc);
8203 switch (sc->link_params.phy[phy_idx].media_type) {
8204 case ELINK_ETH_PHY_SFPP_10G_FIBER:
8205 case ELINK_ETH_PHY_SFP_1G_FIBER:
8206 case ELINK_ETH_PHY_XFP_FIBER:
8207 case ELINK_ETH_PHY_KR:
8208 case ELINK_ETH_PHY_CX4:
8209 PMD_DRV_LOG(INFO, sc, "Found 10GBase-CX4 media.");
8210 sc->media = IFM_10G_CX4;
8212 case ELINK_ETH_PHY_DA_TWINAX:
8213 PMD_DRV_LOG(INFO, sc, "Found 10Gb Twinax media.");
8214 sc->media = IFM_10G_TWINAX;
8216 case ELINK_ETH_PHY_BASE_T:
8217 PMD_DRV_LOG(INFO, sc, "Found 10GBase-T media.");
8218 sc->media = IFM_10G_T;
8220 case ELINK_ETH_PHY_NOT_PRESENT:
8221 PMD_DRV_LOG(INFO, sc, "Media not present.");
8224 case ELINK_ETH_PHY_UNSPECIFIED:
8226 PMD_DRV_LOG(INFO, sc, "Unknown media!");
8232 #define GET_FIELD(value, fname) \
8233 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
8234 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
8235 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
8237 static int bnx2x_get_igu_cam_info(struct bnx2x_softc *sc)
8239 int pfid = SC_FUNC(sc);
8242 uint8_t fid, igu_sb_cnt = 0;
8244 sc->igu_base_sb = 0xff;
8246 if (CHIP_INT_MODE_IS_BC(sc)) {
8248 igu_sb_cnt = sc->igu_sb_cnt;
8249 sc->igu_base_sb = ((CHIP_IS_MODE_4_PORT(sc) ? pfid : vn) *
8251 sc->igu_dsb_id = (E1HVN_MAX * FP_SB_MAX_E1x +
8252 (CHIP_IS_MODE_4_PORT(sc) ? pfid : vn));
8256 /* IGU in normal mode - read CAM */
8258 igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; igu_sb_id++) {
8259 val = REG_RD(sc, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
8260 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) {
8264 if (fid & IGU_FID_ENCODE_IS_PF) {
8265 if ((fid & IGU_FID_PF_NUM_MASK) != pfid) {
8268 if (IGU_VEC(val) == 0) {
8269 /* default status block */
8270 sc->igu_dsb_id = igu_sb_id;
8272 if (sc->igu_base_sb == 0xff) {
8273 sc->igu_base_sb = igu_sb_id;
8281 * Due to new PF resource allocation by MFW T7.4 and above, it's optional
8282 * that number of CAM entries will not be equal to the value advertised in
8283 * PCI. Driver should use the minimal value of both as the actual status
8286 sc->igu_sb_cnt = min(sc->igu_sb_cnt, igu_sb_cnt);
8288 if (igu_sb_cnt == 0) {
8289 PMD_DRV_LOG(ERR, sc, "CAM configuration error");
8297 * Gather various information from the device config space, the device itself,
8298 * shmem, and the user input.
8300 static int bnx2x_get_device_info(struct bnx2x_softc *sc)
8305 /* get the chip revision (chip metal comes from pci config space) */
8306 sc->devinfo.chip_id = sc->link_params.chip_id =
8307 (((REG_RD(sc, MISC_REG_CHIP_NUM) & 0xffff) << 16) |
8308 ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12) |
8309 (((REG_RD(sc, PCICFG_OFFSET + PCI_ID_VAL3) >> 24) & 0xf) << 4) |
8310 ((REG_RD(sc, MISC_REG_BOND_ID) & 0xf) << 0));
8312 /* force 57811 according to MISC register */
8313 if (REG_RD(sc, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
8314 if (CHIP_IS_57810(sc)) {
8315 sc->devinfo.chip_id = ((CHIP_NUM_57811 << 16) |
8317 devinfo.chip_id & 0x0000ffff));
8318 } else if (CHIP_IS_57810_MF(sc)) {
8319 sc->devinfo.chip_id = ((CHIP_NUM_57811_MF << 16) |
8321 devinfo.chip_id & 0x0000ffff));
8323 sc->devinfo.chip_id |= 0x1;
8326 PMD_DRV_LOG(DEBUG, sc,
8327 "chip_id=0x%08x (num=0x%04x rev=0x%01x metal=0x%02x bond=0x%01x)",
8328 sc->devinfo.chip_id,
8329 ((sc->devinfo.chip_id >> 16) & 0xffff),
8330 ((sc->devinfo.chip_id >> 12) & 0xf),
8331 ((sc->devinfo.chip_id >> 4) & 0xff),
8332 ((sc->devinfo.chip_id >> 0) & 0xf));
8334 val = (REG_RD(sc, 0x2874) & 0x55);
8335 if ((sc->devinfo.chip_id & 0x1) || (CHIP_IS_E1H(sc) && (val == 0x55))) {
8336 sc->flags |= BNX2X_ONE_PORT_FLAG;
8337 PMD_DRV_LOG(DEBUG, sc, "single port device");
8340 /* set the doorbell size */
8341 sc->doorbell_size = (1 << BNX2X_DB_SHIFT);
8343 /* determine whether the device is in 2 port or 4 port mode */
8344 sc->devinfo.chip_port_mode = CHIP_PORT_MODE_NONE; /* E1h */
8345 if (CHIP_IS_E2E3(sc)) {
8347 * Read port4mode_en_ovwr[0]:
8348 * If 1, four port mode is in port4mode_en_ovwr[1].
8349 * If 0, four port mode is in port4mode_en[0].
8351 val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);
8353 val = ((val >> 1) & 1);
8355 val = REG_RD(sc, MISC_REG_PORT4MODE_EN);
8358 sc->devinfo.chip_port_mode =
8359 (val) ? CHIP_4_PORT_MODE : CHIP_2_PORT_MODE;
8361 PMD_DRV_LOG(DEBUG, sc, "Port mode = %s", (val) ? "4" : "2");
8364 /* get the function and path info for the device */
8365 bnx2x_get_function_num(sc);
8367 /* get the shared memory base address */
8368 sc->devinfo.shmem_base =
8369 sc->link_params.shmem_base = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
8370 sc->devinfo.shmem2_base =
8371 REG_RD(sc, (SC_PATH(sc) ? MISC_REG_GENERIC_CR_1 :
8372 MISC_REG_GENERIC_CR_0));
8374 if (!sc->devinfo.shmem_base) {
8375 /* this should ONLY prevent upcoming shmem reads */
8376 PMD_DRV_LOG(INFO, sc, "MCP not active");
8377 sc->flags |= BNX2X_NO_MCP_FLAG;
8381 /* make sure the shared memory contents are valid */
8382 val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
8383 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) !=
8384 (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) {
8385 PMD_DRV_LOG(NOTICE, sc, "Invalid SHMEM validity signature: 0x%08x",
8390 /* get the bootcode version */
8391 sc->devinfo.bc_ver = SHMEM_RD(sc, dev_info.bc_rev);
8392 snprintf(sc->devinfo.bc_ver_str,
8393 sizeof(sc->devinfo.bc_ver_str),
8395 ((sc->devinfo.bc_ver >> 24) & 0xff),
8396 ((sc->devinfo.bc_ver >> 16) & 0xff),
8397 ((sc->devinfo.bc_ver >> 8) & 0xff));
8398 PMD_DRV_LOG(DEBUG, sc, "Bootcode version: %s", sc->devinfo.bc_ver_str);
8400 /* get the bootcode shmem address */
8401 sc->devinfo.mf_cfg_base = bnx2x_get_shmem_mf_cfg_base(sc);
8403 /* clean indirect addresses as they're not used */
8404 pci_write_long(sc, PCICFG_GRC_ADDRESS, 0);
8406 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F0, 0);
8407 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F0, 0);
8408 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F0, 0);
8409 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F0, 0);
8410 if (CHIP_IS_E1x(sc)) {
8411 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F1, 0);
8412 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F1, 0);
8413 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F1, 0);
8414 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F1, 0);
8418 /* get the nvram size */
8419 val = REG_RD(sc, MCP_REG_MCPR_NVM_CFG4);
8420 sc->devinfo.flash_size =
8421 (NVRAM_1MB_SIZE << (val & MCPR_NVM_CFG4_FLASH_SIZE));
8423 bnx2x_set_power_state(sc, PCI_PM_D0);
8424 /* get various configuration parameters from shmem */
8425 bnx2x_get_shmem_info(sc);
8427 /* initialize IGU parameters */
8428 if (CHIP_IS_E1x(sc)) {
8429 sc->devinfo.int_block = INT_BLOCK_HC;
8430 sc->igu_dsb_id = DEF_SB_IGU_ID;
8431 sc->igu_base_sb = 0;
8433 sc->devinfo.int_block = INT_BLOCK_IGU;
8435 /* do not allow device reset during IGU info preocessing */
8436 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8438 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
8440 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8443 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
8444 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION, val);
8445 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x7f);
8447 while (tout && REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8452 if (REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8453 PMD_DRV_LOG(NOTICE, sc,
8454 "FORCING IGU Normal Mode failed!!!");
8455 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8460 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8461 PMD_DRV_LOG(DEBUG, sc, "IGU Backward Compatible Mode");
8462 sc->devinfo.int_block |= INT_BLOCK_MODE_BW_COMP;
8464 PMD_DRV_LOG(DEBUG, sc, "IGU Normal Mode");
8467 rc = bnx2x_get_igu_cam_info(sc);
8469 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8477 * Get base FW non-default (fast path) status block ID. This value is
8478 * used to initialize the fw_sb_id saved on the fp/queue structure to
8479 * determine the id used by the FW.
8481 if (CHIP_IS_E1x(sc)) {
8483 ((SC_PORT(sc) * FP_SB_MAX_E1x) + SC_L_ID(sc));
8486 * 57712+ - We currently use one FW SB per IGU SB (Rx and Tx of
8487 * the same queue are indicated on the same IGU SB). So we prefer
8488 * FW and IGU SBs to be the same value.
8490 sc->base_fw_ndsb = sc->igu_base_sb;
8493 elink_phy_probe(&sc->link_params);
8499 bnx2x_link_settings_supported(struct bnx2x_softc *sc, uint32_t switch_cfg)
8501 uint32_t cfg_size = 0;
8503 uint8_t port = SC_PORT(sc);
8505 /* aggregation of supported attributes of all external phys */
8506 sc->port.supported[0] = 0;
8507 sc->port.supported[1] = 0;
8509 switch (sc->link_params.num_phys) {
8511 sc->port.supported[0] =
8512 sc->link_params.phy[ELINK_INT_PHY].supported;
8516 sc->port.supported[0] =
8517 sc->link_params.phy[ELINK_EXT_PHY1].supported;
8521 if (sc->link_params.multi_phy_config &
8522 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
8523 sc->port.supported[1] =
8524 sc->link_params.phy[ELINK_EXT_PHY1].supported;
8525 sc->port.supported[0] =
8526 sc->link_params.phy[ELINK_EXT_PHY2].supported;
8528 sc->port.supported[0] =
8529 sc->link_params.phy[ELINK_EXT_PHY1].supported;
8530 sc->port.supported[1] =
8531 sc->link_params.phy[ELINK_EXT_PHY2].supported;
8537 if (!(sc->port.supported[0] || sc->port.supported[1])) {
8538 PMD_DRV_LOG(ERR, sc,
8539 "Invalid phy config in NVRAM (PHY1=0x%08x PHY2=0x%08x)",
8541 dev_info.port_hw_config
8542 [port].external_phy_config),
8544 dev_info.port_hw_config
8545 [port].external_phy_config2));
8550 sc->port.phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR);
8552 switch (switch_cfg) {
8553 case ELINK_SWITCH_CFG_1G:
8556 NIG_REG_SERDES0_CTRL_PHY_ADDR + port * 0x10);
8558 case ELINK_SWITCH_CFG_10G:
8561 NIG_REG_XGXS0_CTRL_PHY_ADDR + port * 0x18);
8564 PMD_DRV_LOG(ERR, sc,
8565 "Invalid switch config in"
8566 "link_config=0x%08x",
8567 sc->port.link_config[0]);
8572 PMD_DRV_LOG(INFO, sc, "PHY addr 0x%08x", sc->port.phy_addr);
8574 /* mask what we support according to speed_cap_mask per configuration */
8575 for (idx = 0; idx < cfg_size; idx++) {
8576 if (!(sc->link_params.speed_cap_mask[idx] &
8577 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) {
8578 sc->port.supported[idx] &=
8579 ~ELINK_SUPPORTED_10baseT_Half;
8582 if (!(sc->link_params.speed_cap_mask[idx] &
8583 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) {
8584 sc->port.supported[idx] &=
8585 ~ELINK_SUPPORTED_10baseT_Full;
8588 if (!(sc->link_params.speed_cap_mask[idx] &
8589 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) {
8590 sc->port.supported[idx] &=
8591 ~ELINK_SUPPORTED_100baseT_Half;
8594 if (!(sc->link_params.speed_cap_mask[idx] &
8595 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) {
8596 sc->port.supported[idx] &=
8597 ~ELINK_SUPPORTED_100baseT_Full;
8600 if (!(sc->link_params.speed_cap_mask[idx] &
8601 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) {
8602 sc->port.supported[idx] &=
8603 ~ELINK_SUPPORTED_1000baseT_Full;
8606 if (!(sc->link_params.speed_cap_mask[idx] &
8607 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) {
8608 sc->port.supported[idx] &=
8609 ~ELINK_SUPPORTED_2500baseX_Full;
8612 if (!(sc->link_params.speed_cap_mask[idx] &
8613 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8614 sc->port.supported[idx] &=
8615 ~ELINK_SUPPORTED_10000baseT_Full;
8618 if (!(sc->link_params.speed_cap_mask[idx] &
8619 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) {
8620 sc->port.supported[idx] &=
8621 ~ELINK_SUPPORTED_20000baseKR2_Full;
8625 PMD_DRV_LOG(INFO, sc, "PHY supported 0=0x%08x 1=0x%08x",
8626 sc->port.supported[0], sc->port.supported[1]);
8629 static void bnx2x_link_settings_requested(struct bnx2x_softc *sc)
8631 uint32_t link_config;
8633 uint32_t cfg_size = 0;
8635 sc->port.advertising[0] = 0;
8636 sc->port.advertising[1] = 0;
8638 switch (sc->link_params.num_phys) {
8648 for (idx = 0; idx < cfg_size; idx++) {
8649 sc->link_params.req_duplex[idx] = DUPLEX_FULL;
8650 link_config = sc->port.link_config[idx];
8652 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
8653 case PORT_FEATURE_LINK_SPEED_AUTO:
8654 if (sc->port.supported[idx] & ELINK_SUPPORTED_Autoneg) {
8655 sc->link_params.req_line_speed[idx] =
8656 ELINK_SPEED_AUTO_NEG;
8657 sc->port.advertising[idx] |=
8658 sc->port.supported[idx];
8659 if (sc->link_params.phy[ELINK_EXT_PHY1].type ==
8660 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833)
8661 sc->port.advertising[idx] |=
8662 (ELINK_SUPPORTED_100baseT_Half |
8663 ELINK_SUPPORTED_100baseT_Full);
8665 /* force 10G, no AN */
8666 sc->link_params.req_line_speed[idx] =
8668 sc->port.advertising[idx] |=
8669 (ADVERTISED_10000baseT_Full |
8675 case PORT_FEATURE_LINK_SPEED_10M_FULL:
8677 port.supported[idx] & ELINK_SUPPORTED_10baseT_Full)
8679 sc->link_params.req_line_speed[idx] =
8681 sc->port.advertising[idx] |=
8682 (ADVERTISED_10baseT_Full | ADVERTISED_TP);
8684 PMD_DRV_LOG(ERR, sc,
8685 "Invalid NVRAM config link_config=0x%08x "
8686 "speed_cap_mask=0x%08x",
8689 link_params.speed_cap_mask[idx]);
8694 case PORT_FEATURE_LINK_SPEED_10M_HALF:
8696 port.supported[idx] & ELINK_SUPPORTED_10baseT_Half)
8698 sc->link_params.req_line_speed[idx] =
8700 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8701 sc->port.advertising[idx] |=
8702 (ADVERTISED_10baseT_Half | ADVERTISED_TP);
8704 PMD_DRV_LOG(ERR, sc,
8705 "Invalid NVRAM config link_config=0x%08x "
8706 "speed_cap_mask=0x%08x",
8709 link_params.speed_cap_mask[idx]);
8714 case PORT_FEATURE_LINK_SPEED_100M_FULL:
8716 port.supported[idx] & ELINK_SUPPORTED_100baseT_Full)
8718 sc->link_params.req_line_speed[idx] =
8720 sc->port.advertising[idx] |=
8721 (ADVERTISED_100baseT_Full | ADVERTISED_TP);
8723 PMD_DRV_LOG(ERR, sc,
8724 "Invalid NVRAM config link_config=0x%08x "
8725 "speed_cap_mask=0x%08x",
8728 link_params.speed_cap_mask[idx]);
8733 case PORT_FEATURE_LINK_SPEED_100M_HALF:
8735 port.supported[idx] & ELINK_SUPPORTED_100baseT_Half)
8737 sc->link_params.req_line_speed[idx] =
8739 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8740 sc->port.advertising[idx] |=
8741 (ADVERTISED_100baseT_Half | ADVERTISED_TP);
8743 PMD_DRV_LOG(ERR, sc,
8744 "Invalid NVRAM config link_config=0x%08x "
8745 "speed_cap_mask=0x%08x",
8748 link_params.speed_cap_mask[idx]);
8753 case PORT_FEATURE_LINK_SPEED_1G:
8754 if (sc->port.supported[idx] &
8755 ELINK_SUPPORTED_1000baseT_Full) {
8756 sc->link_params.req_line_speed[idx] =
8758 sc->port.advertising[idx] |=
8759 (ADVERTISED_1000baseT_Full | ADVERTISED_TP);
8761 PMD_DRV_LOG(ERR, sc,
8762 "Invalid NVRAM config link_config=0x%08x "
8763 "speed_cap_mask=0x%08x",
8766 link_params.speed_cap_mask[idx]);
8771 case PORT_FEATURE_LINK_SPEED_2_5G:
8772 if (sc->port.supported[idx] &
8773 ELINK_SUPPORTED_2500baseX_Full) {
8774 sc->link_params.req_line_speed[idx] =
8776 sc->port.advertising[idx] |=
8777 (ADVERTISED_2500baseX_Full | ADVERTISED_TP);
8779 PMD_DRV_LOG(ERR, sc,
8780 "Invalid NVRAM config link_config=0x%08x "
8781 "speed_cap_mask=0x%08x",
8784 link_params.speed_cap_mask[idx]);
8789 case PORT_FEATURE_LINK_SPEED_10G_CX4:
8790 if (sc->port.supported[idx] &
8791 ELINK_SUPPORTED_10000baseT_Full) {
8792 sc->link_params.req_line_speed[idx] =
8794 sc->port.advertising[idx] |=
8795 (ADVERTISED_10000baseT_Full |
8798 PMD_DRV_LOG(ERR, sc,
8799 "Invalid NVRAM config link_config=0x%08x "
8800 "speed_cap_mask=0x%08x",
8803 link_params.speed_cap_mask[idx]);
8808 case PORT_FEATURE_LINK_SPEED_20G:
8809 sc->link_params.req_line_speed[idx] = ELINK_SPEED_20000;
8813 PMD_DRV_LOG(ERR, sc,
8814 "Invalid NVRAM config link_config=0x%08x "
8815 "speed_cap_mask=0x%08x", link_config,
8816 sc->link_params.speed_cap_mask[idx]);
8817 sc->link_params.req_line_speed[idx] =
8818 ELINK_SPEED_AUTO_NEG;
8819 sc->port.advertising[idx] = sc->port.supported[idx];
8823 sc->link_params.req_flow_ctrl[idx] =
8824 (link_config & PORT_FEATURE_FLOW_CONTROL_MASK);
8826 if (sc->link_params.req_flow_ctrl[idx] == ELINK_FLOW_CTRL_AUTO) {
8829 port.supported[idx] & ELINK_SUPPORTED_Autoneg)) {
8830 sc->link_params.req_flow_ctrl[idx] =
8831 ELINK_FLOW_CTRL_NONE;
8833 bnx2x_set_requested_fc(sc);
8839 static void bnx2x_get_phy_info(struct bnx2x_softc *sc)
8841 uint8_t port = SC_PORT(sc);
8844 PMD_INIT_FUNC_TRACE(sc);
8846 /* shmem data already read in bnx2x_get_shmem_info() */
8848 bnx2x_link_settings_supported(sc, sc->link_params.switch_cfg);
8849 bnx2x_link_settings_requested(sc);
8851 /* configure link feature according to nvram value */
8853 (((SHMEM_RD(sc, dev_info.port_feature_config[port].eee_power_mode))
8854 & PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
8855 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
8856 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
8857 sc->link_params.eee_mode = (ELINK_EEE_MODE_ADV_LPI |
8858 ELINK_EEE_MODE_ENABLE_LPI |
8859 ELINK_EEE_MODE_OUTPUT_TIME);
8861 sc->link_params.eee_mode = 0;
8864 /* get the media type */
8865 bnx2x_media_detect(sc);
8868 static void bnx2x_set_modes_bitmap(struct bnx2x_softc *sc)
8870 uint32_t flags = MODE_ASIC | MODE_PORT2;
8872 if (CHIP_IS_E2(sc)) {
8874 } else if (CHIP_IS_E3(sc)) {
8876 if (CHIP_REV(sc) == CHIP_REV_Ax) {
8877 flags |= MODE_E3_A0;
8878 } else { /*if (CHIP_REV(sc) == CHIP_REV_Bx) */
8880 flags |= MODE_E3_B0 | MODE_COS3;
8886 switch (sc->devinfo.mf_info.mf_mode) {
8887 case MULTI_FUNCTION_SD:
8888 flags |= MODE_MF_SD;
8890 case MULTI_FUNCTION_SI:
8891 flags |= MODE_MF_SI;
8893 case MULTI_FUNCTION_AFEX:
8894 flags |= MODE_MF_AFEX;
8901 #if defined(__LITTLE_ENDIAN)
8902 flags |= MODE_LITTLE_ENDIAN;
8903 #else /* __BIG_ENDIAN */
8904 flags |= MODE_BIG_ENDIAN;
8907 INIT_MODE_FLAGS(sc) = flags;
8910 int bnx2x_alloc_hsi_mem(struct bnx2x_softc *sc)
8912 struct bnx2x_fastpath *fp;
8917 /************************/
8918 /* DEFAULT STATUS BLOCK */
8919 /************************/
8921 if (bnx2x_dma_alloc(sc, sizeof(struct host_sp_status_block),
8922 &sc->def_sb_dma, "def_sb",
8923 RTE_CACHE_LINE_SIZE) != 0) {
8928 (struct host_sp_status_block *)sc->def_sb_dma.vaddr;
8933 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8934 &sc->eq_dma, "ev_queue",
8935 RTE_CACHE_LINE_SIZE) != 0) {
8940 sc->eq = (union event_ring_elem *)sc->eq_dma.vaddr;
8946 if (bnx2x_dma_alloc(sc, sizeof(struct bnx2x_slowpath),
8948 RTE_CACHE_LINE_SIZE) != 0) {
8954 sc->sp = (struct bnx2x_slowpath *)sc->sp_dma.vaddr;
8956 /*******************/
8957 /* SLOW PATH QUEUE */
8958 /*******************/
8960 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8961 &sc->spq_dma, "sp_queue",
8962 RTE_CACHE_LINE_SIZE) != 0) {
8969 sc->spq = (struct eth_spe *)sc->spq_dma.vaddr;
8971 /***************************/
8972 /* FW DECOMPRESSION BUFFER */
8973 /***************************/
8975 if (bnx2x_dma_alloc(sc, FW_BUF_SIZE, &sc->gz_buf_dma,
8976 "fw_buf", RTE_CACHE_LINE_SIZE) != 0) {
8984 sc->gz_buf = (void *)sc->gz_buf_dma.vaddr;
8991 /* allocate DMA memory for each fastpath structure */
8992 for (i = 0; i < sc->num_queues; i++) {
8997 /*******************/
8998 /* FP STATUS BLOCK */
8999 /*******************/
9001 snprintf(buf, sizeof(buf), "fp_%d_sb", i);
9002 if (bnx2x_dma_alloc(sc, sizeof(union bnx2x_host_hc_status_block),
9003 &fp->sb_dma, buf, RTE_CACHE_LINE_SIZE) != 0) {
9004 PMD_DRV_LOG(NOTICE, sc, "Failed to alloc %s", buf);
9007 if (CHIP_IS_E2E3(sc)) {
9008 fp->status_block.e2_sb =
9009 (struct host_hc_status_block_e2 *)
9012 fp->status_block.e1x_sb =
9013 (struct host_hc_status_block_e1x *)
9022 void bnx2x_free_hsi_mem(struct bnx2x_softc *sc)
9024 struct bnx2x_fastpath *fp;
9027 for (i = 0; i < sc->num_queues; i++) {
9030 /*******************/
9031 /* FP STATUS BLOCK */
9032 /*******************/
9034 memset(&fp->status_block, 0, sizeof(fp->status_block));
9035 bnx2x_dma_free(&fp->sb_dma);
9039 /***************************/
9040 /* FW DECOMPRESSION BUFFER */
9041 /***************************/
9043 bnx2x_dma_free(&sc->gz_buf_dma);
9046 /*******************/
9047 /* SLOW PATH QUEUE */
9048 /*******************/
9050 bnx2x_dma_free(&sc->spq_dma);
9057 bnx2x_dma_free(&sc->sp_dma);
9064 bnx2x_dma_free(&sc->eq_dma);
9067 /************************/
9068 /* DEFAULT STATUS BLOCK */
9069 /************************/
9071 bnx2x_dma_free(&sc->def_sb_dma);
9077 * Previous driver DMAE transaction may have occurred when pre-boot stage
9078 * ended and boot began. This would invalidate the addresses of the
9079 * transaction, resulting in was-error bit set in the PCI causing all
9080 * hw-to-host PCIe transactions to timeout. If this happened we want to clear
9081 * the interrupt which detected this from the pglueb and the was-done bit
9083 static void bnx2x_prev_interrupted_dmae(struct bnx2x_softc *sc)
9087 if (!CHIP_IS_E1x(sc)) {
9088 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS);
9089 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
9090 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
9096 static int bnx2x_prev_mcp_done(struct bnx2x_softc *sc)
9098 uint32_t rc = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE,
9099 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
9101 PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
9108 static struct bnx2x_prev_list_node *bnx2x_prev_path_get_entry(struct bnx2x_softc *sc)
9110 struct bnx2x_prev_list_node *tmp;
9112 LIST_FOREACH(tmp, &bnx2x_prev_list, node) {
9113 if ((sc->pcie_bus == tmp->bus) &&
9114 (sc->pcie_device == tmp->slot) &&
9115 (SC_PATH(sc) == tmp->path)) {
9123 static uint8_t bnx2x_prev_is_path_marked(struct bnx2x_softc *sc)
9125 struct bnx2x_prev_list_node *tmp;
9128 rte_spinlock_lock(&bnx2x_prev_mtx);
9130 tmp = bnx2x_prev_path_get_entry(sc);
9133 PMD_DRV_LOG(DEBUG, sc,
9134 "Path %d/%d/%d was marked by AER",
9135 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9138 PMD_DRV_LOG(DEBUG, sc,
9139 "Path %d/%d/%d was already cleaned from previous drivers",
9140 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9144 rte_spinlock_unlock(&bnx2x_prev_mtx);
9149 static int bnx2x_prev_mark_path(struct bnx2x_softc *sc, uint8_t after_undi)
9151 struct bnx2x_prev_list_node *tmp;
9153 rte_spinlock_lock(&bnx2x_prev_mtx);
9155 /* Check whether the entry for this path already exists */
9156 tmp = bnx2x_prev_path_get_entry(sc);
9159 PMD_DRV_LOG(DEBUG, sc,
9160 "Re-marking AER in path %d/%d/%d",
9161 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9163 PMD_DRV_LOG(DEBUG, sc,
9164 "Removing AER indication from path %d/%d/%d",
9165 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9169 rte_spinlock_unlock(&bnx2x_prev_mtx);
9173 rte_spinlock_unlock(&bnx2x_prev_mtx);
9175 /* Create an entry for this path and add it */
9176 tmp = rte_malloc("", sizeof(struct bnx2x_prev_list_node),
9177 RTE_CACHE_LINE_SIZE);
9179 PMD_DRV_LOG(NOTICE, sc, "Failed to allocate 'bnx2x_prev_list_node'");
9183 tmp->bus = sc->pcie_bus;
9184 tmp->slot = sc->pcie_device;
9185 tmp->path = SC_PATH(sc);
9187 tmp->undi = after_undi ? (1 << SC_PORT(sc)) : 0;
9189 rte_spinlock_lock(&bnx2x_prev_mtx);
9191 LIST_INSERT_HEAD(&bnx2x_prev_list, tmp, node);
9193 rte_spinlock_unlock(&bnx2x_prev_mtx);
9198 static int bnx2x_do_flr(struct bnx2x_softc *sc)
9202 /* only E2 and onwards support FLR */
9203 if (CHIP_IS_E1x(sc)) {
9204 PMD_DRV_LOG(WARNING, sc, "FLR not supported in E1H");
9208 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9209 if (sc->devinfo.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9210 PMD_DRV_LOG(WARNING, sc,
9211 "FLR not supported by BC_VER: 0x%08x",
9212 sc->devinfo.bc_ver);
9216 /* Wait for Transaction Pending bit clean */
9217 for (i = 0; i < 4; i++) {
9219 DELAY(((1 << (i - 1)) * 100) * 1000);
9222 if (!bnx2x_is_pcie_pending(sc)) {
9227 PMD_DRV_LOG(NOTICE, sc, "PCIE transaction is not cleared, "
9228 "proceeding with reset anyway");
9231 bnx2x_fw_command(sc, DRV_MSG_CODE_INITIATE_FLR, 0);
9236 struct bnx2x_mac_vals {
9244 uint32_t bmac_val[2];
9248 bnx2x_prev_unload_close_mac(struct bnx2x_softc *sc, struct bnx2x_mac_vals *vals)
9250 uint32_t val, base_addr, offset, mask, reset_reg;
9251 uint8_t mac_stopped = FALSE;
9252 uint8_t port = SC_PORT(sc);
9253 uint32_t wb_data[2];
9255 /* reset addresses as they also mark which values were changed */
9256 vals->bmac_addr = 0;
9257 vals->umac_addr = 0;
9258 vals->xmac_addr = 0;
9259 vals->emac_addr = 0;
9261 reset_reg = REG_RD(sc, MISC_REG_RESET_REG_2);
9263 if (!CHIP_IS_E3(sc)) {
9264 val = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9265 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9266 if ((mask & reset_reg) && val) {
9267 base_addr = SC_PORT(sc) ? NIG_REG_INGRESS_BMAC1_MEM
9268 : NIG_REG_INGRESS_BMAC0_MEM;
9269 offset = CHIP_IS_E2(sc) ? BIGMAC2_REGISTER_BMAC_CONTROL
9270 : BIGMAC_REGISTER_BMAC_CONTROL;
9273 * use rd/wr since we cannot use dmae. This is safe
9274 * since MCP won't access the bus due to the request
9275 * to unload, and no function on the path can be
9276 * loaded at this time.
9278 wb_data[0] = REG_RD(sc, base_addr + offset);
9279 wb_data[1] = REG_RD(sc, base_addr + offset + 0x4);
9280 vals->bmac_addr = base_addr + offset;
9281 vals->bmac_val[0] = wb_data[0];
9282 vals->bmac_val[1] = wb_data[1];
9283 wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE;
9284 REG_WR(sc, vals->bmac_addr, wb_data[0]);
9285 REG_WR(sc, vals->bmac_addr + 0x4, wb_data[1]);
9288 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + SC_PORT(sc) * 4;
9289 vals->emac_val = REG_RD(sc, vals->emac_addr);
9290 REG_WR(sc, vals->emac_addr, 0);
9293 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9294 base_addr = SC_PORT(sc) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9295 val = REG_RD(sc, base_addr + XMAC_REG_PFC_CTRL_HI);
9296 REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9298 REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9300 vals->xmac_addr = base_addr + XMAC_REG_CTRL;
9301 vals->xmac_val = REG_RD(sc, vals->xmac_addr);
9302 REG_WR(sc, vals->xmac_addr, 0);
9306 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9307 if (mask & reset_reg) {
9308 base_addr = SC_PORT(sc) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9309 vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
9310 vals->umac_val = REG_RD(sc, vals->umac_addr);
9311 REG_WR(sc, vals->umac_addr, 0);
9321 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9322 #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
9323 #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
9324 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
9327 bnx2x_prev_unload_undi_inc(struct bnx2x_softc *sc, uint8_t port, uint8_t inc)
9330 uint32_t tmp_reg = REG_RD(sc, BNX2X_PREV_UNDI_PROD_ADDR(port));
9332 rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9333 bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9335 tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9336 REG_WR(sc, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9339 static int bnx2x_prev_unload_common(struct bnx2x_softc *sc)
9341 uint32_t reset_reg, tmp_reg = 0, rc;
9342 uint8_t prev_undi = FALSE;
9343 struct bnx2x_mac_vals mac_vals;
9344 uint32_t timer_count = 1000;
9348 * It is possible a previous function received 'common' answer,
9349 * but hasn't loaded yet, therefore creating a scenario of
9350 * multiple functions receiving 'common' on the same path.
9352 memset(&mac_vals, 0, sizeof(mac_vals));
9354 if (bnx2x_prev_is_path_marked(sc)) {
9355 return bnx2x_prev_mcp_done(sc);
9358 reset_reg = REG_RD(sc, MISC_REG_RESET_REG_1);
9360 /* Reset should be performed after BRB is emptied */
9361 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
9362 /* Close the MAC Rx to prevent BRB from filling up */
9363 bnx2x_prev_unload_close_mac(sc, &mac_vals);
9365 /* close LLH filters towards the BRB */
9366 elink_set_rx_filter(&sc->link_params, 0);
9369 * Check if the UNDI driver was previously loaded.
9370 * UNDI driver initializes CID offset for normal bell to 0x7
9372 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
9373 tmp_reg = REG_RD(sc, DORQ_REG_NORM_CID_OFST);
9374 if (tmp_reg == 0x7) {
9375 PMD_DRV_LOG(DEBUG, sc, "UNDI previously loaded");
9377 /* clear the UNDI indication */
9378 REG_WR(sc, DORQ_REG_NORM_CID_OFST, 0);
9379 /* clear possible idle check errors */
9380 REG_RD(sc, NIG_REG_NIG_INT_STS_CLR_0);
9384 /* wait until BRB is empty */
9385 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9386 while (timer_count) {
9389 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9394 PMD_DRV_LOG(DEBUG, sc, "BRB still has 0x%08x", tmp_reg);
9396 /* reset timer as long as BRB actually gets emptied */
9397 if (prev_brb > tmp_reg) {
9403 /* If UNDI resides in memory, manually increment it */
9405 bnx2x_prev_unload_undi_inc(sc, SC_PORT(sc), 1);
9412 PMD_DRV_LOG(NOTICE, sc, "Failed to empty BRB");
9416 /* No packets are in the pipeline, path is ready for reset */
9417 bnx2x_reset_common(sc);
9419 if (mac_vals.xmac_addr) {
9420 REG_WR(sc, mac_vals.xmac_addr, mac_vals.xmac_val);
9422 if (mac_vals.umac_addr) {
9423 REG_WR(sc, mac_vals.umac_addr, mac_vals.umac_val);
9425 if (mac_vals.emac_addr) {
9426 REG_WR(sc, mac_vals.emac_addr, mac_vals.emac_val);
9428 if (mac_vals.bmac_addr) {
9429 REG_WR(sc, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
9430 REG_WR(sc, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
9433 rc = bnx2x_prev_mark_path(sc, prev_undi);
9435 bnx2x_prev_mcp_done(sc);
9439 return bnx2x_prev_mcp_done(sc);
9442 static int bnx2x_prev_unload_uncommon(struct bnx2x_softc *sc)
9446 /* Test if previous unload process was already finished for this path */
9447 if (bnx2x_prev_is_path_marked(sc)) {
9448 return bnx2x_prev_mcp_done(sc);
9452 * If function has FLR capabilities, and existing FW version matches
9453 * the one required, then FLR will be sufficient to clean any residue
9454 * left by previous driver
9456 rc = bnx2x_nic_load_analyze_req(sc, FW_MSG_CODE_DRV_LOAD_FUNCTION);
9458 /* fw version is good */
9459 rc = bnx2x_do_flr(sc);
9463 /* FLR was performed */
9467 PMD_DRV_LOG(INFO, sc, "Could not FLR");
9469 /* Close the MCP request, return failure */
9470 rc = bnx2x_prev_mcp_done(sc);
9472 rc = BNX2X_PREV_WAIT_NEEDED;
9478 static int bnx2x_prev_unload(struct bnx2x_softc *sc)
9480 int time_counter = 10;
9481 uint32_t fw, hw_lock_reg, hw_lock_val;
9484 PMD_INIT_FUNC_TRACE(sc);
9487 * Clear HW from errors which may have resulted from an interrupted
9490 bnx2x_prev_interrupted_dmae(sc);
9492 /* Release previously held locks */
9493 hw_lock_reg = (SC_FUNC(sc) <= 5) ?
9494 (MISC_REG_DRIVER_CONTROL_1 + SC_FUNC(sc) * 8) :
9495 (MISC_REG_DRIVER_CONTROL_7 + (SC_FUNC(sc) - 6) * 8);
9497 hw_lock_val = (REG_RD(sc, hw_lock_reg));
9499 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
9500 PMD_DRV_LOG(DEBUG, sc, "Releasing previously held NVRAM lock\n");
9501 REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
9502 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << SC_PORT(sc)));
9504 PMD_DRV_LOG(DEBUG, sc, "Releasing previously held HW lock\n");
9505 REG_WR(sc, hw_lock_reg, 0xffffffff);
9508 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(sc, MCP_REG_MCPR_ACCESS_LOCK)) {
9509 PMD_DRV_LOG(DEBUG, sc, "Releasing previously held ALR\n");
9510 REG_WR(sc, MCP_REG_MCPR_ACCESS_LOCK, 0);
9514 /* Lock MCP using an unload request */
9515 fw = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
9517 PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
9522 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
9523 rc = bnx2x_prev_unload_common(sc);
9527 /* non-common reply from MCP might require looping */
9528 rc = bnx2x_prev_unload_uncommon(sc);
9529 if (rc != BNX2X_PREV_WAIT_NEEDED) {
9534 } while (--time_counter);
9536 if (!time_counter || rc) {
9537 PMD_DRV_LOG(NOTICE, sc, "Failed to unload previous driver!");
9545 bnx2x_dcbx_set_state(struct bnx2x_softc *sc, uint8_t dcb_on, uint32_t dcbx_enabled)
9547 if (!CHIP_IS_E1x(sc)) {
9548 sc->dcb_state = dcb_on;
9549 sc->dcbx_enabled = dcbx_enabled;
9551 sc->dcb_state = FALSE;
9552 sc->dcbx_enabled = BNX2X_DCBX_ENABLED_INVALID;
9554 PMD_DRV_LOG(DEBUG, sc,
9555 "DCB state [%s:%s]",
9556 dcb_on ? "ON" : "OFF",
9557 (dcbx_enabled == BNX2X_DCBX_ENABLED_OFF) ? "user-mode" :
9559 BNX2X_DCBX_ENABLED_ON_NEG_OFF) ? "on-chip static"
9561 BNX2X_DCBX_ENABLED_ON_NEG_ON) ?
9562 "on-chip with negotiation" : "invalid");
9565 static int bnx2x_set_qm_cid_count(struct bnx2x_softc *sc)
9567 int cid_count = BNX2X_L2_MAX_CID(sc);
9569 if (CNIC_SUPPORT(sc)) {
9570 cid_count += CNIC_CID_MAX;
9573 return roundup(cid_count, QM_CID_ROUND);
9576 static void bnx2x_init_multi_cos(struct bnx2x_softc *sc)
9580 uint32_t pri_map = 0;
9582 for (pri = 0; pri < BNX2X_MAX_PRIORITY; pri++) {
9583 cos = ((pri_map & (0xf << (pri * 4))) >> (pri * 4));
9584 if (cos < sc->max_cos) {
9585 sc->prio_to_cos[pri] = cos;
9587 PMD_DRV_LOG(WARNING, sc,
9588 "Invalid COS %d for priority %d "
9589 "(max COS is %d), setting to 0", cos, pri,
9591 sc->prio_to_cos[pri] = 0;
9596 static int bnx2x_pci_get_caps(struct bnx2x_softc *sc)
9603 struct bnx2x_pci_cap *cap;
9605 cap = sc->pci_caps = rte_zmalloc("caps", sizeof(struct bnx2x_pci_cap),
9606 RTE_CACHE_LINE_SIZE);
9608 PMD_DRV_LOG(NOTICE, sc, "Failed to allocate memory");
9612 #ifndef RTE_EXEC_ENV_FREEBSD
9613 pci_read(sc, PCI_STATUS, &status, 2);
9614 if (!(status & PCI_STATUS_CAP_LIST)) {
9616 pci_read(sc, PCIR_STATUS, &status, 2);
9617 if (!(status & PCIM_STATUS_CAPPRESENT)) {
9619 PMD_DRV_LOG(NOTICE, sc, "PCIe capability reading failed");
9623 #ifndef RTE_EXEC_ENV_FREEBSD
9624 pci_read(sc, PCI_CAPABILITY_LIST, &pci_cap.next, 1);
9626 pci_read(sc, PCIR_CAP_PTR, &pci_cap.next, 1);
9628 while (pci_cap.next) {
9629 cap->addr = pci_cap.next & ~3;
9630 pci_read(sc, pci_cap.next & ~3, &pci_cap, 2);
9631 if (pci_cap.id == 0xff)
9633 cap->id = pci_cap.id;
9634 cap->type = BNX2X_PCI_CAP;
9635 cap->next = rte_zmalloc("pci_cap",
9636 sizeof(struct bnx2x_pci_cap),
9637 RTE_CACHE_LINE_SIZE);
9639 PMD_DRV_LOG(NOTICE, sc, "Failed to allocate memory");
9648 static void bnx2x_init_rte(struct bnx2x_softc *sc)
9651 sc->max_tx_queues = min(BNX2X_VF_MAX_QUEUES_PER_VF,
9653 sc->max_rx_queues = min(BNX2X_VF_MAX_QUEUES_PER_VF,
9656 sc->max_rx_queues = BNX2X_MAX_RSS_COUNT(sc);
9657 sc->max_tx_queues = sc->max_rx_queues;
9661 #define FW_HEADER_LEN 104
9662 #define FW_NAME_57711 "/lib/firmware/bnx2x/bnx2x-e1h-7.13.11.0.fw"
9663 #define FW_NAME_57810 "/lib/firmware/bnx2x/bnx2x-e2-7.13.11.0.fw"
9665 void bnx2x_load_firmware(struct bnx2x_softc *sc)
9671 fwname = sc->devinfo.device_id == CHIP_NUM_57711
9672 ? FW_NAME_57711 : FW_NAME_57810;
9673 f = open(fwname, O_RDONLY);
9675 PMD_DRV_LOG(NOTICE, sc, "Can't open firmware file");
9679 if (fstat(f, &st) < 0) {
9680 PMD_DRV_LOG(NOTICE, sc, "Can't stat firmware file");
9685 sc->firmware = rte_zmalloc("bnx2x_fw", st.st_size, RTE_CACHE_LINE_SIZE);
9686 if (!sc->firmware) {
9687 PMD_DRV_LOG(NOTICE, sc, "Can't allocate memory for firmware");
9692 if (read(f, sc->firmware, st.st_size) != st.st_size) {
9693 PMD_DRV_LOG(NOTICE, sc, "Can't read firmware data");
9699 sc->fw_len = st.st_size;
9700 if (sc->fw_len < FW_HEADER_LEN) {
9701 PMD_DRV_LOG(NOTICE, sc,
9702 "Invalid fw size: %" PRIu64, sc->fw_len);
9705 PMD_DRV_LOG(DEBUG, sc, "fw_len = %" PRIu64, sc->fw_len);
9709 bnx2x_data_to_init_ops(uint8_t * data, struct raw_op *dst, uint32_t len)
9711 uint32_t *src = (uint32_t *) data;
9714 for (i = 0, j = 0; i < len / 8; ++i, j += 2) {
9715 tmp = rte_be_to_cpu_32(src[j]);
9716 dst[i].op = (tmp >> 24) & 0xFF;
9717 dst[i].offset = tmp & 0xFFFFFF;
9718 dst[i].raw_data = rte_be_to_cpu_32(src[j + 1]);
9723 bnx2x_data_to_init_offsets(uint8_t * data, uint16_t * dst, uint32_t len)
9725 uint16_t *src = (uint16_t *) data;
9728 for (i = 0; i < len / 2; ++i)
9729 dst[i] = rte_be_to_cpu_16(src[i]);
9732 static void bnx2x_data_to_init_data(uint8_t * data, uint32_t * dst, uint32_t len)
9734 uint32_t *src = (uint32_t *) data;
9737 for (i = 0; i < len / 4; ++i)
9738 dst[i] = rte_be_to_cpu_32(src[i]);
9741 static void bnx2x_data_to_iro_array(uint8_t * data, struct iro *dst, uint32_t len)
9743 uint32_t *src = (uint32_t *) data;
9746 for (i = 0, j = 0; i < len / sizeof(struct iro); ++i, ++j) {
9747 dst[i].base = rte_be_to_cpu_32(src[j++]);
9748 tmp = rte_be_to_cpu_32(src[j]);
9749 dst[i].m1 = (tmp >> 16) & 0xFFFF;
9750 dst[i].m2 = tmp & 0xFFFF;
9752 tmp = rte_be_to_cpu_32(src[j]);
9753 dst[i].m3 = (tmp >> 16) & 0xFFFF;
9754 dst[i].size = tmp & 0xFFFF;
9759 * Device attach function.
9761 * Allocates device resources, performs secondary chip identification, and
9762 * initializes driver instance variables. This function is called from driver
9763 * load after a successful probe.
9766 * 0 = Success, >0 = Failure
9768 int bnx2x_attach(struct bnx2x_softc *sc)
9772 PMD_DRV_LOG(DEBUG, sc, "Starting attach...");
9774 rc = bnx2x_pci_get_caps(sc);
9776 PMD_DRV_LOG(NOTICE, sc, "PCIe caps reading was failed");
9780 sc->state = BNX2X_STATE_CLOSED;
9782 pci_write_long(sc, PCICFG_GRC_ADDRESS, PCICFG_VENDOR_ID_OFFSET);
9784 sc->igu_base_addr = IS_VF(sc) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
9786 /* get PCI capabilites */
9787 bnx2x_probe_pci_caps(sc);
9789 if (sc->devinfo.pcie_msix_cap_reg != 0) {
9792 (sc->devinfo.pcie_msix_cap_reg + PCIR_MSIX_CTRL), &val,
9794 sc->igu_sb_cnt = (val & PCIM_MSIXCTRL_TABLE_SIZE) + 1;
9799 /* Init RTE stuff */
9803 /* Enable internal target-read (in case we are probed after PF
9804 * FLR). Must be done prior to any BAR read access. Only for
9807 if (!CHIP_IS_E1x(sc)) {
9808 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ,
9813 /* get device info and set params */
9814 if (bnx2x_get_device_info(sc) != 0) {
9815 PMD_DRV_LOG(NOTICE, sc, "getting device info");
9819 /* get phy settings from shmem and 'and' against admin settings */
9820 bnx2x_get_phy_info(sc);
9822 /* Left mac of VF unfilled, PF should set it for VF */
9823 memset(sc->link_params.mac_addr, 0, RTE_ETHER_ADDR_LEN);
9828 /* set the default MTU (changed via ifconfig) */
9829 sc->mtu = RTE_ETHER_MTU;
9831 bnx2x_set_modes_bitmap(sc);
9833 /* need to reset chip if UNDI was active */
9834 if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
9837 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
9838 DRV_MSG_SEQ_NUMBER_MASK);
9839 PMD_DRV_LOG(DEBUG, sc, "prev unload fw_seq 0x%04x",
9841 bnx2x_prev_unload(sc);
9844 bnx2x_dcbx_set_state(sc, FALSE, BNX2X_DCBX_ENABLED_OFF);
9846 /* calculate qm_cid_count */
9847 sc->qm_cid_count = bnx2x_set_qm_cid_count(sc);
9850 bnx2x_init_multi_cos(sc);
9856 bnx2x_igu_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t segment,
9857 uint16_t index, uint8_t op, uint8_t update)
9859 uint32_t igu_addr = sc->igu_base_addr;
9860 igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
9861 bnx2x_igu_ack_sb_gen(sc, segment, index, op, update, igu_addr);
9865 bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t storm,
9866 uint16_t index, uint8_t op, uint8_t update)
9868 if (unlikely(sc->devinfo.int_block == INT_BLOCK_HC))
9869 bnx2x_hc_ack_sb(sc, igu_sb_id, storm, index, op, update);
9872 if (CHIP_INT_MODE_IS_BC(sc)) {
9874 } else if (igu_sb_id != sc->igu_dsb_id) {
9875 segment = IGU_SEG_ACCESS_DEF;
9876 } else if (storm == ATTENTION_ID) {
9877 segment = IGU_SEG_ACCESS_ATTN;
9879 segment = IGU_SEG_ACCESS_DEF;
9881 bnx2x_igu_ack_sb(sc, igu_sb_id, segment, index, op, update);
9886 bnx2x_igu_clear_sb_gen(struct bnx2x_softc *sc, uint8_t func, uint8_t idu_sb_id,
9889 uint32_t data, ctl, cnt = 100;
9890 uint32_t igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
9891 uint32_t igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
9892 uint32_t igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP +
9893 (idu_sb_id / 32) * 4;
9894 uint32_t sb_bit = 1 << (idu_sb_id % 32);
9895 uint32_t func_encode = func |
9896 (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
9897 uint32_t addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
9899 /* Not supported in BC mode */
9900 if (CHIP_INT_MODE_IS_BC(sc)) {
9904 data = ((IGU_USE_REGISTER_cstorm_type_0_sb_cleanup <<
9905 IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
9906 IGU_REGULAR_CLEANUP_SET | IGU_REGULAR_BCLEANUP);
9908 ctl = ((addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT) |
9909 (func_encode << IGU_CTRL_REG_FID_SHIFT) |
9910 (IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT));
9912 REG_WR(sc, igu_addr_data, data);
9916 PMD_DRV_LOG(DEBUG, sc, "write 0x%08x to IGU(via GRC) addr 0x%x",
9918 REG_WR(sc, igu_addr_ctl, ctl);
9922 /* wait for clean up to finish */
9923 while (!(REG_RD(sc, igu_addr_ack) & sb_bit) && --cnt) {
9927 if (!(REG_RD(sc, igu_addr_ack) & sb_bit)) {
9928 PMD_DRV_LOG(DEBUG, sc,
9929 "Unable to finish IGU cleanup: "
9930 "idu_sb_id %d offset %d bit %d (cnt %d)",
9931 idu_sb_id, idu_sb_id / 32, idu_sb_id % 32, cnt);
9935 static void bnx2x_igu_clear_sb(struct bnx2x_softc *sc, uint8_t idu_sb_id)
9937 bnx2x_igu_clear_sb_gen(sc, SC_FUNC(sc), idu_sb_id, TRUE /*PF*/);
9940 /*******************/
9941 /* ECORE CALLBACKS */
9942 /*******************/
9944 static void bnx2x_reset_common(struct bnx2x_softc *sc)
9946 uint32_t val = 0x1400;
9948 PMD_INIT_FUNC_TRACE(sc);
9951 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR),
9954 if (CHIP_IS_E3(sc)) {
9955 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
9956 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
9959 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR), val);
9962 static void bnx2x_common_init_phy(struct bnx2x_softc *sc)
9964 uint32_t shmem_base[2];
9965 uint32_t shmem2_base[2];
9967 /* Avoid common init in case MFW supports LFA */
9968 if (SHMEM2_RD(sc, size) >
9969 (uint32_t) offsetof(struct shmem2_region,
9970 lfa_host_addr[SC_PORT(sc)])) {
9974 shmem_base[0] = sc->devinfo.shmem_base;
9975 shmem2_base[0] = sc->devinfo.shmem2_base;
9977 if (!CHIP_IS_E1x(sc)) {
9978 shmem_base[1] = SHMEM2_RD(sc, other_shmem_base_addr);
9979 shmem2_base[1] = SHMEM2_RD(sc, other_shmem2_base_addr);
9982 bnx2x_acquire_phy_lock(sc);
9983 elink_common_init_phy(sc, shmem_base, shmem2_base,
9984 sc->devinfo.chip_id, 0);
9985 bnx2x_release_phy_lock(sc);
9988 static void bnx2x_pf_disable(struct bnx2x_softc *sc)
9990 uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
9992 val &= ~IGU_PF_CONF_FUNC_EN;
9994 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
9995 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
9996 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 0);
9999 static void bnx2x_init_pxp(struct bnx2x_softc *sc)
10002 int r_order, w_order;
10004 devctl = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_CTL);
10006 w_order = ((devctl & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5);
10007 r_order = ((devctl & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12);
10009 ecore_init_pxp_arb(sc, r_order, w_order);
10012 static uint32_t bnx2x_get_pretend_reg(struct bnx2x_softc *sc)
10014 uint32_t base = PXP2_REG_PGL_PRETEND_FUNC_F0;
10015 uint32_t stride = (PXP2_REG_PGL_PRETEND_FUNC_F1 - base);
10016 return base + (SC_ABS_FUNC(sc)) * stride;
10020 * Called only on E1H or E2.
10021 * When pretending to be PF, the pretend value is the function number 0..7.
10022 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
10025 static int bnx2x_pretend_func(struct bnx2x_softc *sc, uint16_t pretend_func_val)
10027 uint32_t pretend_reg;
10029 if (CHIP_IS_E1H(sc) && (pretend_func_val > E1H_FUNC_MAX))
10032 /* get my own pretend register */
10033 pretend_reg = bnx2x_get_pretend_reg(sc);
10034 REG_WR(sc, pretend_reg, pretend_func_val);
10035 REG_RD(sc, pretend_reg);
10039 static void bnx2x_setup_fan_failure_detection(struct bnx2x_softc *sc)
10046 val = (SHMEM_RD(sc, dev_info.shared_hw_config.config2) &
10047 SHARED_HW_CFG_FAN_FAILURE_MASK);
10049 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) {
10053 * The fan failure mechanism is usually related to the PHY type since
10054 * the power consumption of the board is affected by the PHY. Currently,
10055 * fan is required for most designs with SFX7101, BNX2X8727 and BNX2X8481.
10057 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) {
10058 for (port = PORT_0; port < PORT_MAX; port++) {
10059 is_required |= elink_fan_failure_det_req(sc,
10061 devinfo.shmem_base,
10063 devinfo.shmem2_base,
10068 if (is_required == 0) {
10072 /* Fan failure is indicated by SPIO 5 */
10073 bnx2x_set_spio(sc, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
10075 /* set to active low mode */
10076 val = REG_RD(sc, MISC_REG_SPIO_INT);
10077 val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
10078 REG_WR(sc, MISC_REG_SPIO_INT, val);
10080 /* enable interrupt to signal the IGU */
10081 val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
10082 val |= MISC_SPIO_SPIO5;
10083 REG_WR(sc, MISC_REG_SPIO_EVENT_EN, val);
10086 static void bnx2x_enable_blocks_attention(struct bnx2x_softc *sc)
10090 REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0);
10091 if (!CHIP_IS_E1x(sc)) {
10092 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0x40);
10094 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0);
10096 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
10097 REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
10099 * mask read length error interrupts in brb for parser
10100 * (parsing unit and 'checksum and crc' unit)
10101 * these errors are legal (PU reads fixed length and CAC can cause
10102 * read length error on truncated packets)
10104 REG_WR(sc, BRB1_REG_BRB1_INT_MASK, 0xFC00);
10105 REG_WR(sc, QM_REG_QM_INT_MASK, 0);
10106 REG_WR(sc, TM_REG_TM_INT_MASK, 0);
10107 REG_WR(sc, XSDM_REG_XSDM_INT_MASK_0, 0);
10108 REG_WR(sc, XSDM_REG_XSDM_INT_MASK_1, 0);
10109 REG_WR(sc, XCM_REG_XCM_INT_MASK, 0);
10110 /* REG_WR(sc, XSEM_REG_XSEM_INT_MASK_0, 0); */
10111 /* REG_WR(sc, XSEM_REG_XSEM_INT_MASK_1, 0); */
10112 REG_WR(sc, USDM_REG_USDM_INT_MASK_0, 0);
10113 REG_WR(sc, USDM_REG_USDM_INT_MASK_1, 0);
10114 REG_WR(sc, UCM_REG_UCM_INT_MASK, 0);
10115 /* REG_WR(sc, USEM_REG_USEM_INT_MASK_0, 0); */
10116 /* REG_WR(sc, USEM_REG_USEM_INT_MASK_1, 0); */
10117 REG_WR(sc, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
10118 REG_WR(sc, CSDM_REG_CSDM_INT_MASK_0, 0);
10119 REG_WR(sc, CSDM_REG_CSDM_INT_MASK_1, 0);
10120 REG_WR(sc, CCM_REG_CCM_INT_MASK, 0);
10121 /* REG_WR(sc, CSEM_REG_CSEM_INT_MASK_0, 0); */
10122 /* REG_WR(sc, CSEM_REG_CSEM_INT_MASK_1, 0); */
10124 val = (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
10125 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
10126 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN);
10127 if (!CHIP_IS_E1x(sc)) {
10128 val |= (PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
10129 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED);
10131 REG_WR(sc, PXP2_REG_PXP2_INT_MASK_0, val);
10133 REG_WR(sc, TSDM_REG_TSDM_INT_MASK_0, 0);
10134 REG_WR(sc, TSDM_REG_TSDM_INT_MASK_1, 0);
10135 REG_WR(sc, TCM_REG_TCM_INT_MASK, 0);
10136 /* REG_WR(sc, TSEM_REG_TSEM_INT_MASK_0, 0); */
10138 if (!CHIP_IS_E1x(sc)) {
10139 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
10140 REG_WR(sc, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
10143 REG_WR(sc, CDU_REG_CDU_INT_MASK, 0);
10144 REG_WR(sc, DMAE_REG_DMAE_INT_MASK, 0);
10145 /* REG_WR(sc, MISC_REG_MISC_INT_MASK, 0); */
10146 REG_WR(sc, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
10150 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
10152 * @sc: driver handle
10154 static int bnx2x_init_hw_common(struct bnx2x_softc *sc)
10156 uint8_t abs_func_id;
10159 PMD_DRV_LOG(DEBUG, sc,
10160 "starting common init for func %d", SC_ABS_FUNC(sc));
10163 * take the RESET lock to protect undi_unload flow from accessing
10164 * registers while we are resetting the chip
10166 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10168 bnx2x_reset_common(sc);
10170 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET), 0xffffffff);
10173 if (CHIP_IS_E3(sc)) {
10174 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
10175 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
10178 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET), val);
10180 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10182 ecore_init_block(sc, BLOCK_MISC, PHASE_COMMON);
10184 if (!CHIP_IS_E1x(sc)) {
10186 * 4-port mode or 2-port mode we need to turn off master-enable for
10187 * everyone. After that we turn it back on for self. So, we disregard
10188 * multi-function, and always disable all functions on the given path,
10189 * this means 0,2,4,6 for path 0 and 1,3,5,7 for path 1
10191 for (abs_func_id = SC_PATH(sc);
10192 abs_func_id < (E2_FUNC_MAX * 2); abs_func_id += 2) {
10193 if (abs_func_id == SC_ABS_FUNC(sc)) {
10195 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
10200 bnx2x_pretend_func(sc, abs_func_id);
10202 /* clear pf enable */
10203 bnx2x_pf_disable(sc);
10205 bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10209 ecore_init_block(sc, BLOCK_PXP, PHASE_COMMON);
10211 ecore_init_block(sc, BLOCK_PXP2, PHASE_COMMON);
10212 bnx2x_init_pxp(sc);
10214 #ifdef __BIG_ENDIAN
10215 REG_WR(sc, PXP2_REG_RQ_QM_ENDIAN_M, 1);
10216 REG_WR(sc, PXP2_REG_RQ_TM_ENDIAN_M, 1);
10217 REG_WR(sc, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
10218 REG_WR(sc, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
10219 REG_WR(sc, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
10220 /* make sure this value is 0 */
10221 REG_WR(sc, PXP2_REG_RQ_HC_ENDIAN_M, 0);
10223 //REG_WR(sc, PXP2_REG_RD_PBF_SWAP_MODE, 1);
10224 REG_WR(sc, PXP2_REG_RD_QM_SWAP_MODE, 1);
10225 REG_WR(sc, PXP2_REG_RD_TM_SWAP_MODE, 1);
10226 REG_WR(sc, PXP2_REG_RD_SRC_SWAP_MODE, 1);
10227 REG_WR(sc, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
10230 ecore_ilt_init_page_size(sc, INITOP_SET);
10232 if (CHIP_REV_IS_FPGA(sc) && CHIP_IS_E1H(sc)) {
10233 REG_WR(sc, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
10236 /* let the HW do it's magic... */
10239 /* finish PXP init */
10241 val = REG_RD(sc, PXP2_REG_RQ_CFG_DONE);
10243 PMD_DRV_LOG(NOTICE, sc, "PXP2 CFG failed");
10246 val = REG_RD(sc, PXP2_REG_RD_INIT_DONE);
10248 PMD_DRV_LOG(NOTICE, sc, "PXP2 RD_INIT failed");
10253 * Timer bug workaround for E2 only. We need to set the entire ILT to have
10254 * entries with value "0" and valid bit on. This needs to be done by the
10255 * first PF that is loaded in a path (i.e. common phase)
10257 if (!CHIP_IS_E1x(sc)) {
10259 * In E2 there is a bug in the timers block that can cause function 6 / 7
10260 * (i.e. vnic3) to start even if it is marked as "scan-off".
10261 * This occurs when a different function (func2,3) is being marked
10262 * as "scan-off". Real-life scenario for example: if a driver is being
10263 * load-unloaded while func6,7 are down. This will cause the timer to access
10264 * the ilt, translate to a logical address and send a request to read/write.
10265 * Since the ilt for the function that is down is not valid, this will cause
10266 * a translation error which is unrecoverable.
10267 * The Workaround is intended to make sure that when this happens nothing
10268 * fatal will occur. The workaround:
10269 * 1. First PF driver which loads on a path will:
10270 * a. After taking the chip out of reset, by using pretend,
10271 * it will write "0" to the following registers of
10273 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10274 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
10275 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
10276 * And for itself it will write '1' to
10277 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
10278 * dmae-operations (writing to pram for example.)
10279 * note: can be done for only function 6,7 but cleaner this
10281 * b. Write zero+valid to the entire ILT.
10282 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
10283 * VNIC3 (of that port). The range allocated will be the
10284 * entire ILT. This is needed to prevent ILT range error.
10285 * 2. Any PF driver load flow:
10286 * a. ILT update with the physical addresses of the allocated
10288 * b. Wait 20msec. - note that this timeout is needed to make
10289 * sure there are no requests in one of the PXP internal
10290 * queues with "old" ILT addresses.
10291 * c. PF enable in the PGLC.
10292 * d. Clear the was_error of the PF in the PGLC. (could have
10293 * occurred while driver was down)
10294 * e. PF enable in the CFC (WEAK + STRONG)
10295 * f. Timers scan enable
10296 * 3. PF driver unload flow:
10297 * a. Clear the Timers scan_en.
10298 * b. Polling for scan_on=0 for that PF.
10299 * c. Clear the PF enable bit in the PXP.
10300 * d. Clear the PF enable in the CFC (WEAK + STRONG)
10301 * e. Write zero+valid to all ILT entries (The valid bit must
10303 * f. If this is VNIC 3 of a port then also init
10304 * first_timers_ilt_entry to zero and last_timers_ilt_entry
10305 * to the last enrty in the ILT.
10308 * Currently the PF error in the PGLC is non recoverable.
10309 * In the future the there will be a recovery routine for this error.
10310 * Currently attention is masked.
10311 * Having an MCP lock on the load/unload process does not guarantee that
10312 * there is no Timer disable during Func6/7 enable. This is because the
10313 * Timers scan is currently being cleared by the MCP on FLR.
10314 * Step 2.d can be done only for PF6/7 and the driver can also check if
10315 * there is error before clearing it. But the flow above is simpler and
10317 * All ILT entries are written by zero+valid and not just PF6/7
10318 * ILT entries since in the future the ILT entries allocation for
10319 * PF-s might be dynamic.
10321 struct ilt_client_info ilt_cli;
10322 struct ecore_ilt ilt;
10324 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
10325 memset(&ilt, 0, sizeof(struct ecore_ilt));
10327 /* initialize dummy TM client */
10329 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
10330 ilt_cli.client_num = ILT_CLIENT_TM;
10333 * Step 1: set zeroes to all ilt page entries with valid bit on
10334 * Step 2: set the timers first/last ilt entry to point
10335 * to the entire range to prevent ILT range error for 3rd/4th
10336 * vnic (this code assumes existence of the vnic)
10338 * both steps performed by call to ecore_ilt_client_init_op()
10339 * with dummy TM client
10341 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
10342 * and his brother are split registers
10345 bnx2x_pretend_func(sc, (SC_PATH(sc) + 6));
10346 ecore_ilt_client_init_op_ilt(sc, &ilt, &ilt_cli, INITOP_CLEAR);
10347 bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10349 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
10350 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
10351 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
10354 REG_WR(sc, PXP2_REG_RQ_DISABLE_INPUTS, 0);
10355 REG_WR(sc, PXP2_REG_RD_DISABLE_INPUTS, 0);
10357 if (!CHIP_IS_E1x(sc)) {
10360 ecore_init_block(sc, BLOCK_PGLUE_B, PHASE_COMMON);
10361 ecore_init_block(sc, BLOCK_ATC, PHASE_COMMON);
10363 /* let the HW do it's magic... */
10366 val = REG_RD(sc, ATC_REG_ATC_INIT_DONE);
10367 } while (factor-- && (val != 1));
10370 PMD_DRV_LOG(NOTICE, sc, "ATC_INIT failed");
10375 ecore_init_block(sc, BLOCK_DMAE, PHASE_COMMON);
10377 /* clean the DMAE memory */
10378 sc->dmae_ready = 1;
10379 ecore_init_fill(sc, TSEM_REG_PRAM, 0, 8, 1);
10381 ecore_init_block(sc, BLOCK_TCM, PHASE_COMMON);
10383 ecore_init_block(sc, BLOCK_UCM, PHASE_COMMON);
10385 ecore_init_block(sc, BLOCK_CCM, PHASE_COMMON);
10387 ecore_init_block(sc, BLOCK_XCM, PHASE_COMMON);
10389 bnx2x_read_dmae(sc, XSEM_REG_PASSIVE_BUFFER, 3);
10390 bnx2x_read_dmae(sc, CSEM_REG_PASSIVE_BUFFER, 3);
10391 bnx2x_read_dmae(sc, TSEM_REG_PASSIVE_BUFFER, 3);
10392 bnx2x_read_dmae(sc, USEM_REG_PASSIVE_BUFFER, 3);
10394 ecore_init_block(sc, BLOCK_QM, PHASE_COMMON);
10396 /* QM queues pointers table */
10397 ecore_qm_init_ptr_table(sc, sc->qm_cid_count, INITOP_SET);
10399 /* soft reset pulse */
10400 REG_WR(sc, QM_REG_SOFT_RESET, 1);
10401 REG_WR(sc, QM_REG_SOFT_RESET, 0);
10403 if (CNIC_SUPPORT(sc))
10404 ecore_init_block(sc, BLOCK_TM, PHASE_COMMON);
10406 ecore_init_block(sc, BLOCK_DORQ, PHASE_COMMON);
10408 if (!CHIP_REV_IS_SLOW(sc)) {
10409 /* enable hw interrupt from doorbell Q */
10410 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
10413 ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON);
10415 ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON);
10416 REG_WR(sc, PRS_REG_A_PRSU_20, 0xf);
10417 REG_WR(sc, PRS_REG_E1HOV_MODE, sc->devinfo.mf_info.path_has_ovlan);
10419 if (!CHIP_IS_E1x(sc) && !CHIP_IS_E3B0(sc)) {
10420 if (IS_MF_AFEX(sc)) {
10422 * configure that AFEX and VLAN headers must be
10423 * received in AFEX mode
10425 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC, 0xE);
10426 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS, 0xA);
10427 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
10428 REG_WR(sc, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
10429 REG_WR(sc, PRS_REG_TAG_LEN_0, 0x4);
10432 * Bit-map indicating which L2 hdrs may appear
10433 * after the basic Ethernet header
10435 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC,
10436 sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10440 ecore_init_block(sc, BLOCK_TSDM, PHASE_COMMON);
10441 ecore_init_block(sc, BLOCK_CSDM, PHASE_COMMON);
10442 ecore_init_block(sc, BLOCK_USDM, PHASE_COMMON);
10443 ecore_init_block(sc, BLOCK_XSDM, PHASE_COMMON);
10445 if (!CHIP_IS_E1x(sc)) {
10446 /* reset VFC memories */
10447 REG_WR(sc, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10448 VFC_MEMORIES_RST_REG_CAM_RST |
10449 VFC_MEMORIES_RST_REG_RAM_RST);
10450 REG_WR(sc, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10451 VFC_MEMORIES_RST_REG_CAM_RST |
10452 VFC_MEMORIES_RST_REG_RAM_RST);
10457 ecore_init_block(sc, BLOCK_TSEM, PHASE_COMMON);
10458 ecore_init_block(sc, BLOCK_USEM, PHASE_COMMON);
10459 ecore_init_block(sc, BLOCK_CSEM, PHASE_COMMON);
10460 ecore_init_block(sc, BLOCK_XSEM, PHASE_COMMON);
10462 /* sync semi rtc */
10463 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x80000000);
10464 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x80000000);
10466 ecore_init_block(sc, BLOCK_UPB, PHASE_COMMON);
10467 ecore_init_block(sc, BLOCK_XPB, PHASE_COMMON);
10468 ecore_init_block(sc, BLOCK_PBF, PHASE_COMMON);
10470 if (!CHIP_IS_E1x(sc)) {
10471 if (IS_MF_AFEX(sc)) {
10473 * configure that AFEX and VLAN headers must be
10474 * sent in AFEX mode
10476 REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC, 0xE);
10477 REG_WR(sc, PBF_REG_MUST_HAVE_HDRS, 0xA);
10478 REG_WR(sc, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
10479 REG_WR(sc, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
10480 REG_WR(sc, PBF_REG_TAG_LEN_0, 0x4);
10482 REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC,
10483 sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10487 REG_WR(sc, SRC_REG_SOFT_RST, 1);
10489 ecore_init_block(sc, BLOCK_SRC, PHASE_COMMON);
10491 if (CNIC_SUPPORT(sc)) {
10492 REG_WR(sc, SRC_REG_KEYSEARCH_0, 0x63285672);
10493 REG_WR(sc, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
10494 REG_WR(sc, SRC_REG_KEYSEARCH_2, 0x223aef9b);
10495 REG_WR(sc, SRC_REG_KEYSEARCH_3, 0x26001e3a);
10496 REG_WR(sc, SRC_REG_KEYSEARCH_4, 0x7ae91116);
10497 REG_WR(sc, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
10498 REG_WR(sc, SRC_REG_KEYSEARCH_6, 0x298d8adf);
10499 REG_WR(sc, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
10500 REG_WR(sc, SRC_REG_KEYSEARCH_8, 0x1830f82f);
10501 REG_WR(sc, SRC_REG_KEYSEARCH_9, 0x01e46be7);
10503 REG_WR(sc, SRC_REG_SOFT_RST, 0);
10505 if (sizeof(union cdu_context) != 1024) {
10506 /* we currently assume that a context is 1024 bytes */
10507 PMD_DRV_LOG(NOTICE, sc,
10508 "please adjust the size of cdu_context(%ld)",
10509 (long)sizeof(union cdu_context));
10512 ecore_init_block(sc, BLOCK_CDU, PHASE_COMMON);
10513 val = (4 << 24) + (0 << 12) + 1024;
10514 REG_WR(sc, CDU_REG_CDU_GLOBAL_PARAMS, val);
10516 ecore_init_block(sc, BLOCK_CFC, PHASE_COMMON);
10518 REG_WR(sc, CFC_REG_INIT_REG, 0x7FF);
10519 /* enable context validation interrupt from CFC */
10520 REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
10522 /* set the thresholds to prevent CFC/CDU race */
10523 REG_WR(sc, CFC_REG_DEBUG0, 0x20020000);
10524 ecore_init_block(sc, BLOCK_HC, PHASE_COMMON);
10526 if (!CHIP_IS_E1x(sc) && BNX2X_NOMCP(sc)) {
10527 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x36);
10530 ecore_init_block(sc, BLOCK_IGU, PHASE_COMMON);
10531 ecore_init_block(sc, BLOCK_MISC_AEU, PHASE_COMMON);
10533 /* Reset PCIE errors for debug */
10534 REG_WR(sc, 0x2814, 0xffffffff);
10535 REG_WR(sc, 0x3820, 0xffffffff);
10537 if (!CHIP_IS_E1x(sc)) {
10538 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
10539 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
10540 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
10541 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
10542 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
10543 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
10544 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
10545 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
10546 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
10547 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
10548 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
10551 ecore_init_block(sc, BLOCK_NIG, PHASE_COMMON);
10553 /* in E3 this done in per-port section */
10554 if (!CHIP_IS_E3(sc))
10555 REG_WR(sc, NIG_REG_LLH_MF_MODE, IS_MF(sc));
10557 if (CHIP_IS_E1H(sc)) {
10558 /* not applicable for E2 (and above ...) */
10559 REG_WR(sc, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(sc));
10562 if (CHIP_REV_IS_SLOW(sc)) {
10566 /* finish CFC init */
10567 val = reg_poll(sc, CFC_REG_LL_INIT_DONE, 1, 100, 10);
10569 PMD_DRV_LOG(NOTICE, sc, "CFC LL_INIT failed");
10572 val = reg_poll(sc, CFC_REG_AC_INIT_DONE, 1, 100, 10);
10574 PMD_DRV_LOG(NOTICE, sc, "CFC AC_INIT failed");
10577 val = reg_poll(sc, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
10579 PMD_DRV_LOG(NOTICE, sc, "CFC CAM_INIT failed");
10582 REG_WR(sc, CFC_REG_DEBUG0, 0);
10584 bnx2x_setup_fan_failure_detection(sc);
10586 /* clear PXP2 attentions */
10587 REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
10589 bnx2x_enable_blocks_attention(sc);
10591 if (!CHIP_REV_IS_SLOW(sc)) {
10592 ecore_enable_blocks_parity(sc);
10595 if (!BNX2X_NOMCP(sc)) {
10596 if (CHIP_IS_E1x(sc)) {
10597 bnx2x_common_init_phy(sc);
10605 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
10607 * @sc: driver handle
10609 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc)
10611 int rc = bnx2x_init_hw_common(sc);
10617 /* In E2 2-PORT mode, same ext phy is used for the two paths */
10618 if (!BNX2X_NOMCP(sc)) {
10619 bnx2x_common_init_phy(sc);
10625 static int bnx2x_init_hw_port(struct bnx2x_softc *sc)
10627 int port = SC_PORT(sc);
10628 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
10629 uint32_t low, high;
10632 PMD_DRV_LOG(DEBUG, sc, "starting port init for port %d", port);
10634 REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
10636 ecore_init_block(sc, BLOCK_MISC, init_phase);
10637 ecore_init_block(sc, BLOCK_PXP, init_phase);
10638 ecore_init_block(sc, BLOCK_PXP2, init_phase);
10641 * Timers bug workaround: disables the pf_master bit in pglue at
10642 * common phase, we need to enable it here before any dmae access are
10643 * attempted. Therefore we manually added the enable-master to the
10644 * port phase (it also happens in the function phase)
10646 if (!CHIP_IS_E1x(sc)) {
10647 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
10650 ecore_init_block(sc, BLOCK_ATC, init_phase);
10651 ecore_init_block(sc, BLOCK_DMAE, init_phase);
10652 ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
10653 ecore_init_block(sc, BLOCK_QM, init_phase);
10655 ecore_init_block(sc, BLOCK_TCM, init_phase);
10656 ecore_init_block(sc, BLOCK_UCM, init_phase);
10657 ecore_init_block(sc, BLOCK_CCM, init_phase);
10658 ecore_init_block(sc, BLOCK_XCM, init_phase);
10660 /* QM cid (connection) count */
10661 ecore_qm_init_cid_count(sc, sc->qm_cid_count, INITOP_SET);
10663 if (CNIC_SUPPORT(sc)) {
10664 ecore_init_block(sc, BLOCK_TM, init_phase);
10665 REG_WR(sc, TM_REG_LIN0_SCAN_TIME + port * 4, 20);
10666 REG_WR(sc, TM_REG_LIN0_MAX_ACTIVE_CID + port * 4, 31);
10669 ecore_init_block(sc, BLOCK_DORQ, init_phase);
10671 ecore_init_block(sc, BLOCK_BRB1, init_phase);
10673 if (CHIP_IS_E1H(sc)) {
10675 low = (BNX2X_ONE_PORT(sc) ? 160 : 246);
10676 } else if (sc->mtu > 4096) {
10677 if (BNX2X_ONE_PORT(sc)) {
10681 /* (24*1024 + val*4)/256 */
10682 low = (96 + (val / 64) + ((val % 64) ? 1 : 0));
10685 low = (BNX2X_ONE_PORT(sc) ? 80 : 160);
10687 high = (low + 56); /* 14*1024/256 */
10688 REG_WR(sc, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port * 4, low);
10689 REG_WR(sc, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port * 4, high);
10692 if (CHIP_IS_MODE_4_PORT(sc)) {
10693 REG_WR(sc, SC_PORT(sc) ?
10694 BRB1_REG_MAC_GUARANTIED_1 :
10695 BRB1_REG_MAC_GUARANTIED_0, 40);
10698 ecore_init_block(sc, BLOCK_PRS, init_phase);
10699 if (CHIP_IS_E3B0(sc)) {
10700 if (IS_MF_AFEX(sc)) {
10701 /* configure headers for AFEX mode */
10703 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_1,
10705 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_1,
10707 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_1, 0xA);
10709 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10711 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_0,
10713 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
10716 /* Ovlan exists only if we are in multi-function +
10717 * switch-dependent mode, in switch-independent there
10718 * is no ovlan headers
10720 REG_WR(sc, SC_PORT(sc) ?
10721 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
10722 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10723 (sc->devinfo.mf_info.path_has_ovlan ? 7 : 6));
10727 ecore_init_block(sc, BLOCK_TSDM, init_phase);
10728 ecore_init_block(sc, BLOCK_CSDM, init_phase);
10729 ecore_init_block(sc, BLOCK_USDM, init_phase);
10730 ecore_init_block(sc, BLOCK_XSDM, init_phase);
10732 ecore_init_block(sc, BLOCK_TSEM, init_phase);
10733 ecore_init_block(sc, BLOCK_USEM, init_phase);
10734 ecore_init_block(sc, BLOCK_CSEM, init_phase);
10735 ecore_init_block(sc, BLOCK_XSEM, init_phase);
10737 ecore_init_block(sc, BLOCK_UPB, init_phase);
10738 ecore_init_block(sc, BLOCK_XPB, init_phase);
10740 ecore_init_block(sc, BLOCK_PBF, init_phase);
10742 if (CHIP_IS_E1x(sc)) {
10743 /* configure PBF to work without PAUSE mtu 9000 */
10744 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 0);
10746 /* update threshold */
10747 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, (9040 / 16));
10748 /* update init credit */
10749 REG_WR(sc, PBF_REG_P0_INIT_CRD + port * 4,
10750 (9040 / 16) + 553 - 22);
10752 /* probe changes */
10753 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 1);
10755 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0);
10758 if (CNIC_SUPPORT(sc)) {
10759 ecore_init_block(sc, BLOCK_SRC, init_phase);
10762 ecore_init_block(sc, BLOCK_CDU, init_phase);
10763 ecore_init_block(sc, BLOCK_CFC, init_phase);
10764 ecore_init_block(sc, BLOCK_HC, init_phase);
10765 ecore_init_block(sc, BLOCK_IGU, init_phase);
10766 ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
10767 /* init aeu_mask_attn_func_0/1:
10768 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
10769 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
10770 * bits 4-7 are used for "per vn group attention" */
10771 val = IS_MF(sc) ? 0xF7 : 0x7;
10773 REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, val);
10775 ecore_init_block(sc, BLOCK_NIG, init_phase);
10777 if (!CHIP_IS_E1x(sc)) {
10778 /* Bit-map indicating which L2 hdrs may appear after the
10779 * basic Ethernet header
10781 if (IS_MF_AFEX(sc)) {
10782 REG_WR(sc, SC_PORT(sc) ?
10783 NIG_REG_P1_HDRS_AFTER_BASIC :
10784 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
10786 REG_WR(sc, SC_PORT(sc) ?
10787 NIG_REG_P1_HDRS_AFTER_BASIC :
10788 NIG_REG_P0_HDRS_AFTER_BASIC,
10789 IS_MF_SD(sc) ? 7 : 6);
10792 if (CHIP_IS_E3(sc)) {
10793 REG_WR(sc, SC_PORT(sc) ?
10794 NIG_REG_LLH1_MF_MODE :
10795 NIG_REG_LLH_MF_MODE, IS_MF(sc));
10798 if (!CHIP_IS_E3(sc)) {
10799 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1);
10802 /* 0x2 disable mf_ov, 0x1 enable */
10803 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port * 4,
10804 (IS_MF_SD(sc) ? 0x1 : 0x2));
10806 if (!CHIP_IS_E1x(sc)) {
10808 switch (sc->devinfo.mf_info.mf_mode) {
10809 case MULTI_FUNCTION_SD:
10812 case MULTI_FUNCTION_SI:
10813 case MULTI_FUNCTION_AFEX:
10818 REG_WR(sc, (SC_PORT(sc) ? NIG_REG_LLH1_CLS_TYPE :
10819 NIG_REG_LLH0_CLS_TYPE), val);
10821 REG_WR(sc, NIG_REG_LLFC_ENABLE_0 + port * 4, 0);
10822 REG_WR(sc, NIG_REG_LLFC_OUT_EN_0 + port * 4, 0);
10823 REG_WR(sc, NIG_REG_PAUSE_ENABLE_0 + port * 4, 1);
10825 /* If SPIO5 is set to generate interrupts, enable it for this port */
10826 val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
10827 if (val & MISC_SPIO_SPIO5) {
10828 uint32_t reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
10829 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
10830 val = REG_RD(sc, reg_addr);
10831 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
10832 REG_WR(sc, reg_addr, val);
10839 bnx2x_flr_clnup_reg_poll(struct bnx2x_softc *sc, uint32_t reg,
10840 uint32_t expected, uint32_t poll_count)
10842 uint32_t cur_cnt = poll_count;
10845 while ((val = REG_RD(sc, reg)) != expected && cur_cnt--) {
10846 DELAY(FLR_WAIT_INTERVAL);
10853 bnx2x_flr_clnup_poll_hw_counter(struct bnx2x_softc *sc, uint32_t reg,
10854 __rte_unused const char *msg, uint32_t poll_cnt)
10856 uint32_t val = bnx2x_flr_clnup_reg_poll(sc, reg, 0, poll_cnt);
10859 PMD_DRV_LOG(NOTICE, sc, "%s usage count=%d", msg, val);
10866 /* Common routines with VF FLR cleanup */
10867 static uint32_t bnx2x_flr_clnup_poll_count(struct bnx2x_softc *sc)
10869 /* adjust polling timeout */
10870 if (CHIP_REV_IS_EMUL(sc)) {
10871 return FLR_POLL_CNT * 2000;
10874 if (CHIP_REV_IS_FPGA(sc)) {
10875 return FLR_POLL_CNT * 120;
10878 return FLR_POLL_CNT;
10881 static int bnx2x_poll_hw_usage_counters(struct bnx2x_softc *sc, uint32_t poll_cnt)
10883 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
10884 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10885 CFC_REG_NUM_LCIDS_INSIDE_PF,
10886 "CFC PF usage counter timed out",
10891 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
10892 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10893 DORQ_REG_PF_USAGE_CNT,
10894 "DQ PF usage counter timed out",
10899 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
10900 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10901 QM_REG_PF_USG_CNT_0 + 4 * SC_FUNC(sc),
10902 "QM PF usage counter timed out",
10907 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
10908 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10909 TM_REG_LIN0_VNIC_UC + 4 * SC_PORT(sc),
10910 "Timers VNIC usage counter timed out",
10915 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10916 TM_REG_LIN0_NUM_SCANS +
10918 "Timers NUM_SCANS usage counter timed out",
10923 /* Wait DMAE PF usage counter to zero */
10924 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10925 dmae_reg_go_c[INIT_DMAE_C(sc)],
10926 "DMAE dommand register timed out",
10934 #define OP_GEN_PARAM(param) \
10935 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
10936 #define OP_GEN_TYPE(type) \
10937 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
10938 #define OP_GEN_AGG_VECT(index) \
10939 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
10942 bnx2x_send_final_clnup(struct bnx2x_softc *sc, uint8_t clnup_func,
10945 uint32_t op_gen_command = 0;
10946 uint32_t comp_addr = (BAR_CSTRORM_INTMEM +
10947 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func));
10950 if (REG_RD(sc, comp_addr)) {
10951 PMD_DRV_LOG(NOTICE, sc,
10952 "Cleanup complete was not 0 before sending");
10956 op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
10957 op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
10958 op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
10959 op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
10961 REG_WR(sc, XSDM_REG_OPERATION_GEN, op_gen_command);
10963 if (bnx2x_flr_clnup_reg_poll(sc, comp_addr, 1, poll_cnt) != 1) {
10964 PMD_DRV_LOG(NOTICE, sc, "FW final cleanup did not succeed");
10965 PMD_DRV_LOG(DEBUG, sc, "At timeout completion address contained %x",
10966 (REG_RD(sc, comp_addr)));
10967 rte_panic("FLR cleanup failed");
10971 /* Zero completion for nxt FLR */
10972 REG_WR(sc, comp_addr, 0);
10978 bnx2x_pbf_pN_buf_flushed(struct bnx2x_softc *sc, struct pbf_pN_buf_regs *regs,
10979 uint32_t poll_count)
10981 uint32_t init_crd, crd, crd_start, crd_freed, crd_freed_start;
10982 uint32_t cur_cnt = poll_count;
10984 crd_freed = crd_freed_start = REG_RD(sc, regs->crd_freed);
10985 crd = crd_start = REG_RD(sc, regs->crd);
10986 init_crd = REG_RD(sc, regs->init_crd);
10988 while ((crd != init_crd) &&
10989 ((uint32_t) ((int32_t) crd_freed - (int32_t) crd_freed_start) <
10990 (init_crd - crd_start))) {
10992 DELAY(FLR_WAIT_INTERVAL);
10993 crd = REG_RD(sc, regs->crd);
10994 crd_freed = REG_RD(sc, regs->crd_freed);
11002 bnx2x_pbf_pN_cmd_flushed(struct bnx2x_softc *sc, struct pbf_pN_cmd_regs *regs,
11003 uint32_t poll_count)
11005 uint32_t occup, to_free, freed, freed_start;
11006 uint32_t cur_cnt = poll_count;
11008 occup = to_free = REG_RD(sc, regs->lines_occup);
11009 freed = freed_start = REG_RD(sc, regs->lines_freed);
11012 ((uint32_t) ((int32_t) freed - (int32_t) freed_start) <
11015 DELAY(FLR_WAIT_INTERVAL);
11016 occup = REG_RD(sc, regs->lines_occup);
11017 freed = REG_RD(sc, regs->lines_freed);
11024 static void bnx2x_tx_hw_flushed(struct bnx2x_softc *sc, uint32_t poll_count)
11026 struct pbf_pN_cmd_regs cmd_regs[] = {
11027 {0, (CHIP_IS_E3B0(sc)) ?
11028 PBF_REG_TQ_OCCUPANCY_Q0 : PBF_REG_P0_TQ_OCCUPANCY,
11029 (CHIP_IS_E3B0(sc)) ?
11030 PBF_REG_TQ_LINES_FREED_CNT_Q0 : PBF_REG_P0_TQ_LINES_FREED_CNT},
11031 {1, (CHIP_IS_E3B0(sc)) ?
11032 PBF_REG_TQ_OCCUPANCY_Q1 : PBF_REG_P1_TQ_OCCUPANCY,
11033 (CHIP_IS_E3B0(sc)) ?
11034 PBF_REG_TQ_LINES_FREED_CNT_Q1 : PBF_REG_P1_TQ_LINES_FREED_CNT},
11035 {4, (CHIP_IS_E3B0(sc)) ?
11036 PBF_REG_TQ_OCCUPANCY_LB_Q : PBF_REG_P4_TQ_OCCUPANCY,
11037 (CHIP_IS_E3B0(sc)) ?
11038 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
11039 PBF_REG_P4_TQ_LINES_FREED_CNT}
11042 struct pbf_pN_buf_regs buf_regs[] = {
11043 {0, (CHIP_IS_E3B0(sc)) ?
11044 PBF_REG_INIT_CRD_Q0 : PBF_REG_P0_INIT_CRD,
11045 (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q0 : PBF_REG_P0_CREDIT,
11046 (CHIP_IS_E3B0(sc)) ?
11047 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
11048 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
11049 {1, (CHIP_IS_E3B0(sc)) ?
11050 PBF_REG_INIT_CRD_Q1 : PBF_REG_P1_INIT_CRD,
11051 (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q1 : PBF_REG_P1_CREDIT,
11052 (CHIP_IS_E3B0(sc)) ?
11053 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
11054 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
11055 {4, (CHIP_IS_E3B0(sc)) ?
11056 PBF_REG_INIT_CRD_LB_Q : PBF_REG_P4_INIT_CRD,
11057 (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_LB_Q : PBF_REG_P4_CREDIT,
11058 (CHIP_IS_E3B0(sc)) ?
11059 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
11060 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
11065 /* Verify the command queues are flushed P0, P1, P4 */
11066 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) {
11067 bnx2x_pbf_pN_cmd_flushed(sc, &cmd_regs[i], poll_count);
11070 /* Verify the transmission buffers are flushed P0, P1, P4 */
11071 for (i = 0; i < ARRAY_SIZE(buf_regs); i++) {
11072 bnx2x_pbf_pN_buf_flushed(sc, &buf_regs[i], poll_count);
11076 static void bnx2x_hw_enable_status(struct bnx2x_softc *sc)
11078 __rte_unused uint32_t val;
11080 val = REG_RD(sc, CFC_REG_WEAK_ENABLE_PF);
11081 PMD_DRV_LOG(DEBUG, sc, "CFC_REG_WEAK_ENABLE_PF is 0x%x", val);
11083 val = REG_RD(sc, PBF_REG_DISABLE_PF);
11084 PMD_DRV_LOG(DEBUG, sc, "PBF_REG_DISABLE_PF is 0x%x", val);
11086 val = REG_RD(sc, IGU_REG_PCI_PF_MSI_EN);
11087 PMD_DRV_LOG(DEBUG, sc, "IGU_REG_PCI_PF_MSI_EN is 0x%x", val);
11089 val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_EN);
11090 PMD_DRV_LOG(DEBUG, sc, "IGU_REG_PCI_PF_MSIX_EN is 0x%x", val);
11092 val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
11093 PMD_DRV_LOG(DEBUG, sc, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x", val);
11095 val = REG_RD(sc, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
11096 PMD_DRV_LOG(DEBUG, sc,
11097 "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x", val);
11099 val = REG_RD(sc, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
11100 PMD_DRV_LOG(DEBUG, sc,
11101 "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x", val);
11103 val = REG_RD(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
11104 PMD_DRV_LOG(DEBUG, sc, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x",
11109 * bnx2x_pf_flr_clnup
11110 * a. re-enable target read on the PF
11111 * b. poll cfc per function usgae counter
11112 * c. poll the qm perfunction usage counter
11113 * d. poll the tm per function usage counter
11114 * e. poll the tm per function scan-done indication
11115 * f. clear the dmae channel associated wit hthe PF
11116 * g. zero the igu 'trailing edge' and 'leading edge' regs (attentions)
11117 * h. call the common flr cleanup code with -1 (pf indication)
11119 static int bnx2x_pf_flr_clnup(struct bnx2x_softc *sc)
11121 uint32_t poll_cnt = bnx2x_flr_clnup_poll_count(sc);
11123 /* Re-enable PF target read access */
11124 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
11126 /* Poll HW usage counters */
11127 if (bnx2x_poll_hw_usage_counters(sc, poll_cnt)) {
11131 /* Zero the igu 'trailing edge' and 'leading edge' */
11133 /* Send the FW cleanup command */
11134 if (bnx2x_send_final_clnup(sc, (uint8_t) SC_FUNC(sc), poll_cnt)) {
11140 /* Verify TX hw is flushed */
11141 bnx2x_tx_hw_flushed(sc, poll_cnt);
11143 /* Wait 100ms (not adjusted according to platform) */
11146 /* Verify no pending pci transactions */
11147 if (bnx2x_is_pcie_pending(sc)) {
11148 PMD_DRV_LOG(NOTICE, sc, "PCIE Transactions still pending");
11152 bnx2x_hw_enable_status(sc);
11155 * Master enable - Due to WB DMAE writes performed before this
11156 * register is re-initialized as part of the regular function init
11158 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11163 static int bnx2x_init_hw_func(struct bnx2x_softc *sc)
11165 int port = SC_PORT(sc);
11166 int func = SC_FUNC(sc);
11167 int init_phase = PHASE_PF0 + func;
11168 struct ecore_ilt *ilt = sc->ilt;
11169 uint16_t cdu_ilt_start;
11170 uint32_t addr, val;
11171 uint32_t main_mem_base, main_mem_size, main_mem_prty_clr;
11172 int main_mem_width, rc;
11175 PMD_DRV_LOG(DEBUG, sc, "starting func init for func %d", func);
11178 if (!CHIP_IS_E1x(sc)) {
11179 rc = bnx2x_pf_flr_clnup(sc);
11181 PMD_DRV_LOG(NOTICE, sc, "FLR cleanup failed!");
11186 /* set MSI reconfigure capability */
11187 if (sc->devinfo.int_block == INT_BLOCK_HC) {
11188 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
11189 val = REG_RD(sc, addr);
11190 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
11191 REG_WR(sc, addr, val);
11194 ecore_init_block(sc, BLOCK_PXP, init_phase);
11195 ecore_init_block(sc, BLOCK_PXP2, init_phase);
11198 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
11200 for (i = 0; i < L2_ILT_LINES(sc); i++) {
11201 ilt->lines[cdu_ilt_start + i].page = sc->context[i].vcxt;
11202 ilt->lines[cdu_ilt_start + i].page_mapping =
11203 (rte_iova_t)sc->context[i].vcxt_dma.paddr;
11204 ilt->lines[cdu_ilt_start + i].size = sc->context[i].size;
11206 ecore_ilt_init_op(sc, INITOP_SET);
11208 REG_WR(sc, PRS_REG_NIC_MODE, 1);
11210 if (!CHIP_IS_E1x(sc)) {
11211 uint32_t pf_conf = IGU_PF_CONF_FUNC_EN;
11213 /* Turn on a single ISR mode in IGU if driver is going to use
11216 if ((sc->interrupt_mode != INTR_MODE_MSIX)
11217 || (sc->interrupt_mode != INTR_MODE_SINGLE_MSIX)) {
11218 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
11222 * Timers workaround bug: function init part.
11223 * Need to wait 20msec after initializing ILT,
11224 * needed to make sure there are no requests in
11225 * one of the PXP internal queues with "old" ILT addresses
11230 * Master enable - Due to WB DMAE writes performed before this
11231 * register is re-initialized as part of the regular function
11234 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11235 /* Enable the function in IGU */
11236 REG_WR(sc, IGU_REG_PF_CONFIGURATION, pf_conf);
11239 sc->dmae_ready = 1;
11241 ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
11243 if (!CHIP_IS_E1x(sc))
11244 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
11246 ecore_init_block(sc, BLOCK_ATC, init_phase);
11247 ecore_init_block(sc, BLOCK_DMAE, init_phase);
11248 ecore_init_block(sc, BLOCK_NIG, init_phase);
11249 ecore_init_block(sc, BLOCK_SRC, init_phase);
11250 ecore_init_block(sc, BLOCK_MISC, init_phase);
11251 ecore_init_block(sc, BLOCK_TCM, init_phase);
11252 ecore_init_block(sc, BLOCK_UCM, init_phase);
11253 ecore_init_block(sc, BLOCK_CCM, init_phase);
11254 ecore_init_block(sc, BLOCK_XCM, init_phase);
11255 ecore_init_block(sc, BLOCK_TSEM, init_phase);
11256 ecore_init_block(sc, BLOCK_USEM, init_phase);
11257 ecore_init_block(sc, BLOCK_CSEM, init_phase);
11258 ecore_init_block(sc, BLOCK_XSEM, init_phase);
11260 if (!CHIP_IS_E1x(sc))
11261 REG_WR(sc, QM_REG_PF_EN, 1);
11263 if (!CHIP_IS_E1x(sc)) {
11264 REG_WR(sc, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11265 REG_WR(sc, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11266 REG_WR(sc, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11267 REG_WR(sc, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11269 ecore_init_block(sc, BLOCK_QM, init_phase);
11271 ecore_init_block(sc, BLOCK_TM, init_phase);
11272 ecore_init_block(sc, BLOCK_DORQ, init_phase);
11274 ecore_init_block(sc, BLOCK_BRB1, init_phase);
11275 ecore_init_block(sc, BLOCK_PRS, init_phase);
11276 ecore_init_block(sc, BLOCK_TSDM, init_phase);
11277 ecore_init_block(sc, BLOCK_CSDM, init_phase);
11278 ecore_init_block(sc, BLOCK_USDM, init_phase);
11279 ecore_init_block(sc, BLOCK_XSDM, init_phase);
11280 ecore_init_block(sc, BLOCK_UPB, init_phase);
11281 ecore_init_block(sc, BLOCK_XPB, init_phase);
11282 ecore_init_block(sc, BLOCK_PBF, init_phase);
11283 if (!CHIP_IS_E1x(sc))
11284 REG_WR(sc, PBF_REG_DISABLE_PF, 0);
11286 ecore_init_block(sc, BLOCK_CDU, init_phase);
11288 ecore_init_block(sc, BLOCK_CFC, init_phase);
11290 if (!CHIP_IS_E1x(sc))
11291 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 1);
11294 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
11295 REG_WR(sc, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8, OVLAN(sc));
11298 ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
11300 /* HC init per function */
11301 if (sc->devinfo.int_block == INT_BLOCK_HC) {
11302 if (CHIP_IS_E1H(sc)) {
11303 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11305 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11306 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11308 ecore_init_block(sc, BLOCK_HC, init_phase);
11311 uint32_t num_segs, sb_idx, prod_offset;
11313 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11315 if (!CHIP_IS_E1x(sc)) {
11316 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11317 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11320 ecore_init_block(sc, BLOCK_IGU, init_phase);
11322 if (!CHIP_IS_E1x(sc)) {
11326 * E2 mode: address 0-135 match to the mapping memory;
11327 * 136 - PF0 default prod; 137 - PF1 default prod;
11328 * 138 - PF2 default prod; 139 - PF3 default prod;
11329 * 140 - PF0 attn prod; 141 - PF1 attn prod;
11330 * 142 - PF2 attn prod; 143 - PF3 attn prod;
11331 * 144-147 reserved.
11333 * E1.5 mode - In backward compatible mode;
11334 * for non default SB; each even line in the memory
11335 * holds the U producer and each odd line hold
11336 * the C producer. The first 128 producers are for
11337 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
11338 * producers are for the DSB for each PF.
11339 * Each PF has five segments: (the order inside each
11340 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
11341 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
11342 * 144-147 attn prods;
11344 /* non-default-status-blocks */
11345 num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11346 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
11347 for (sb_idx = 0; sb_idx < sc->igu_sb_cnt; sb_idx++) {
11348 prod_offset = (sc->igu_base_sb + sb_idx) *
11351 for (i = 0; i < num_segs; i++) {
11352 addr = IGU_REG_PROD_CONS_MEMORY +
11353 (prod_offset + i) * 4;
11354 REG_WR(sc, addr, 0);
11356 /* send consumer update with value 0 */
11357 bnx2x_ack_sb(sc, sc->igu_base_sb + sb_idx,
11358 USTORM_ID, 0, IGU_INT_NOP, 1);
11359 bnx2x_igu_clear_sb(sc, sc->igu_base_sb + sb_idx);
11362 /* default-status-blocks */
11363 num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11364 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
11366 if (CHIP_IS_MODE_4_PORT(sc))
11367 dsb_idx = SC_FUNC(sc);
11369 dsb_idx = SC_VN(sc);
11371 prod_offset = (CHIP_INT_MODE_IS_BC(sc) ?
11372 IGU_BC_BASE_DSB_PROD + dsb_idx :
11373 IGU_NORM_BASE_DSB_PROD + dsb_idx);
11376 * igu prods come in chunks of E1HVN_MAX (4) -
11377 * does not matters what is the current chip mode
11379 for (i = 0; i < (num_segs * E1HVN_MAX); i += E1HVN_MAX) {
11380 addr = IGU_REG_PROD_CONS_MEMORY +
11381 (prod_offset + i) * 4;
11382 REG_WR(sc, addr, 0);
11384 /* send consumer update with 0 */
11385 if (CHIP_INT_MODE_IS_BC(sc)) {
11386 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11387 USTORM_ID, 0, IGU_INT_NOP, 1);
11388 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11389 CSTORM_ID, 0, IGU_INT_NOP, 1);
11390 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11391 XSTORM_ID, 0, IGU_INT_NOP, 1);
11392 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11393 TSTORM_ID, 0, IGU_INT_NOP, 1);
11394 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11395 ATTENTION_ID, 0, IGU_INT_NOP, 1);
11397 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11398 USTORM_ID, 0, IGU_INT_NOP, 1);
11399 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11400 ATTENTION_ID, 0, IGU_INT_NOP, 1);
11402 bnx2x_igu_clear_sb(sc, sc->igu_dsb_id);
11404 /* !!! these should become driver const once
11405 rf-tool supports split-68 const */
11406 REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
11407 REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
11408 REG_WR(sc, IGU_REG_SB_MASK_LSB, 0);
11409 REG_WR(sc, IGU_REG_SB_MASK_MSB, 0);
11410 REG_WR(sc, IGU_REG_PBA_STATUS_LSB, 0);
11411 REG_WR(sc, IGU_REG_PBA_STATUS_MSB, 0);
11415 /* Reset PCIE errors for debug */
11416 REG_WR(sc, 0x2114, 0xffffffff);
11417 REG_WR(sc, 0x2120, 0xffffffff);
11419 if (CHIP_IS_E1x(sc)) {
11420 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords */
11421 main_mem_base = HC_REG_MAIN_MEMORY +
11422 SC_PORT(sc) * (main_mem_size * 4);
11423 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
11424 main_mem_width = 8;
11426 val = REG_RD(sc, main_mem_prty_clr);
11428 PMD_DRV_LOG(DEBUG, sc,
11429 "Parity errors in HC block during function init (0x%x)!",
11433 /* Clear "false" parity errors in MSI-X table */
11434 for (i = main_mem_base;
11435 i < main_mem_base + main_mem_size * 4;
11436 i += main_mem_width) {
11437 bnx2x_read_dmae(sc, i, main_mem_width / 4);
11438 bnx2x_write_dmae(sc, BNX2X_SP_MAPPING(sc, wb_data),
11439 i, main_mem_width / 4);
11441 /* Clear HC parity attention */
11442 REG_RD(sc, main_mem_prty_clr);
11445 /* Enable STORMs SP logging */
11446 REG_WR8(sc, BAR_USTRORM_INTMEM +
11447 USTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11448 REG_WR8(sc, BAR_TSTRORM_INTMEM +
11449 TSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11450 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11451 CSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11452 REG_WR8(sc, BAR_XSTRORM_INTMEM +
11453 XSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11455 elink_phy_probe(&sc->link_params);
11460 static void bnx2x_link_reset(struct bnx2x_softc *sc)
11462 if (!BNX2X_NOMCP(sc)) {
11463 bnx2x_acquire_phy_lock(sc);
11464 elink_lfa_reset(&sc->link_params, &sc->link_vars);
11465 bnx2x_release_phy_lock(sc);
11467 if (!CHIP_REV_IS_SLOW(sc)) {
11468 PMD_DRV_LOG(WARNING, sc,
11469 "Bootcode is missing - cannot reset link");
11474 static void bnx2x_reset_port(struct bnx2x_softc *sc)
11476 int port = SC_PORT(sc);
11479 /* reset physical Link */
11480 bnx2x_link_reset(sc);
11482 REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
11484 /* Do not rcv packets to BRB */
11485 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + port * 4, 0x0);
11486 /* Do not direct rcv packets that are not for MCP to the BRB */
11487 REG_WR(sc, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
11488 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
11490 /* Configure AEU */
11491 REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, 0);
11495 /* Check for BRB port occupancy */
11496 val = REG_RD(sc, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port * 4);
11498 PMD_DRV_LOG(DEBUG, sc,
11499 "BRB1 is not empty, %d blocks are occupied", val);
11503 static void bnx2x_ilt_wr(struct bnx2x_softc *sc, uint32_t index, rte_iova_t addr)
11506 uint32_t wb_write[2];
11508 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index * 8;
11510 wb_write[0] = ONCHIP_ADDR1(addr);
11511 wb_write[1] = ONCHIP_ADDR2(addr);
11512 REG_WR_DMAE(sc, reg, wb_write, 2);
11515 static void bnx2x_clear_func_ilt(struct bnx2x_softc *sc, uint32_t func)
11517 uint32_t i, base = FUNC_ILT_BASE(func);
11518 for (i = base; i < base + ILT_PER_FUNC; i++) {
11519 bnx2x_ilt_wr(sc, i, 0);
11523 static void bnx2x_reset_func(struct bnx2x_softc *sc)
11525 struct bnx2x_fastpath *fp;
11526 int port = SC_PORT(sc);
11527 int func = SC_FUNC(sc);
11530 /* Disable the function in the FW */
11531 REG_WR8(sc, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
11532 REG_WR8(sc, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
11533 REG_WR8(sc, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
11534 REG_WR8(sc, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
11537 FOR_EACH_ETH_QUEUE(sc, i) {
11539 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11540 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
11545 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11546 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), SB_DISABLED);
11548 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) {
11549 REG_WR(sc, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
11553 /* Configure IGU */
11554 if (sc->devinfo.int_block == INT_BLOCK_HC) {
11555 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11556 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11558 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11559 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11562 if (CNIC_LOADED(sc)) {
11563 /* Disable Timer scan */
11564 REG_WR(sc, TM_REG_EN_LINEAR0_TIMER + port * 4, 0);
11566 * Wait for at least 10ms and up to 2 second for the timers
11569 for (i = 0; i < 200; i++) {
11571 if (!REG_RD(sc, TM_REG_LIN0_SCAN_ON + port * 4))
11577 bnx2x_clear_func_ilt(sc, func);
11580 * Timers workaround bug for E2: if this is vnic-3,
11581 * we need to set the entire ilt range for this timers.
11583 if (!CHIP_IS_E1x(sc) && SC_VN(sc) == 3) {
11584 struct ilt_client_info ilt_cli;
11585 /* use dummy TM client */
11586 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
11588 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
11589 ilt_cli.client_num = ILT_CLIENT_TM;
11591 ecore_ilt_boundary_init_op(sc, &ilt_cli, 0, INITOP_CLEAR);
11594 /* this assumes that reset_port() called before reset_func() */
11595 if (!CHIP_IS_E1x(sc)) {
11596 bnx2x_pf_disable(sc);
11599 sc->dmae_ready = 0;
11602 static void bnx2x_release_firmware(struct bnx2x_softc *sc)
11604 rte_free(sc->init_ops);
11605 rte_free(sc->init_ops_offsets);
11606 rte_free(sc->init_data);
11607 rte_free(sc->iro_array);
11610 static int bnx2x_init_firmware(struct bnx2x_softc *sc)
11613 uint8_t *p = sc->firmware;
11616 for (i = 0; i < 24; ++i)
11617 off[i] = rte_be_to_cpu_32(*((uint32_t *) sc->firmware + i));
11620 sc->init_ops = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11623 bnx2x_data_to_init_ops(p + off[1], sc->init_ops, len);
11626 sc->init_ops_offsets = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11627 if (!sc->init_ops_offsets)
11629 bnx2x_data_to_init_offsets(p + off[3], sc->init_ops_offsets, len);
11632 sc->init_data = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11633 if (!sc->init_data)
11635 bnx2x_data_to_init_data(p + off[5], sc->init_data, len);
11637 sc->tsem_int_table_data = p + off[7];
11638 sc->tsem_pram_data = p + off[9];
11639 sc->usem_int_table_data = p + off[11];
11640 sc->usem_pram_data = p + off[13];
11641 sc->csem_int_table_data = p + off[15];
11642 sc->csem_pram_data = p + off[17];
11643 sc->xsem_int_table_data = p + off[19];
11644 sc->xsem_pram_data = p + off[21];
11647 sc->iro_array = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11648 if (!sc->iro_array)
11650 bnx2x_data_to_iro_array(p + off[23], sc->iro_array, len);
11655 bnx2x_release_firmware(sc);
11659 static int cut_gzip_prefix(const uint8_t * zbuf, int len)
11661 #define MIN_PREFIX_SIZE (10)
11663 int n = MIN_PREFIX_SIZE;
11666 if (!(zbuf[0] == 0x1f && zbuf[1] == 0x8b && zbuf[2] == Z_DEFLATED) ||
11667 len <= MIN_PREFIX_SIZE) {
11671 /* optional extra fields are present */
11672 if (zbuf[3] & 0x4) {
11679 /* file name is present */
11680 if (zbuf[3] & 0x8) {
11681 while ((zbuf[n++] != 0) && (n < len)) ;
11687 static int ecore_gunzip(struct bnx2x_softc *sc, const uint8_t * zbuf, int len)
11690 int data_begin = cut_gzip_prefix(zbuf, len);
11692 PMD_DRV_LOG(DEBUG, sc, "ecore_gunzip %d", len);
11694 if (data_begin <= 0) {
11695 PMD_DRV_LOG(NOTICE, sc, "bad gzip prefix");
11699 memset(&zlib_stream, 0, sizeof(zlib_stream));
11700 zlib_stream.next_in = zbuf + data_begin;
11701 zlib_stream.avail_in = len - data_begin;
11702 zlib_stream.next_out = sc->gz_buf;
11703 zlib_stream.avail_out = FW_BUF_SIZE;
11705 ret = inflateInit2(&zlib_stream, -MAX_WBITS);
11707 PMD_DRV_LOG(NOTICE, sc, "zlib inflateInit2 error");
11711 ret = inflate(&zlib_stream, Z_FINISH);
11712 if ((ret != Z_STREAM_END) && (ret != Z_OK)) {
11713 PMD_DRV_LOG(NOTICE, sc, "zlib inflate error: %d %s", ret,
11717 sc->gz_outlen = zlib_stream.total_out;
11718 if (sc->gz_outlen & 0x3) {
11719 PMD_DRV_LOG(NOTICE, sc, "firmware is not aligned. gz_outlen == %d",
11722 sc->gz_outlen >>= 2;
11724 inflateEnd(&zlib_stream);
11726 if (ret == Z_STREAM_END)
11733 ecore_write_dmae_phys_len(struct bnx2x_softc *sc, rte_iova_t phys_addr,
11734 uint32_t addr, uint32_t len)
11736 bnx2x_write_dmae_phys_len(sc, phys_addr, addr, len);
11740 ecore_storm_memset_struct(struct bnx2x_softc *sc, uint32_t addr, size_t size,
11744 for (i = 0; i < size / 4; i++) {
11745 REG_WR(sc, addr + (i * 4), data[i]);
11749 static const char *get_ext_phy_type(uint32_t ext_phy_type)
11751 uint32_t phy_type_idx = ext_phy_type >> 8;
11752 static const char *types[] =
11753 { "DIRECT", "BNX2X-8071", "BNX2X-8072", "BNX2X-8073",
11754 "BNX2X-8705", "BNX2X-8706", "BNX2X-8726", "BNX2X-8481", "SFX-7101",
11756 "BNX2X-8727-NOC", "BNX2X-84823", "NOT_CONN", "FAILURE"
11759 if (phy_type_idx < 12)
11760 return types[phy_type_idx];
11761 else if (PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN == ext_phy_type)
11767 static const char *get_state(uint32_t state)
11769 uint32_t state_idx = state >> 12;
11770 static const char *states[] = { "CLOSED", "OPENING_WAIT4_LOAD",
11771 "OPENING_WAIT4_PORT", "OPEN", "CLOSING_WAIT4_HALT",
11772 "CLOSING_WAIT4_DELETE", "CLOSING_WAIT4_UNLOAD",
11773 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
11774 "UNKNOWN", "DISABLED", "DIAG", "ERROR", "UNDEFINED"
11777 if (state_idx <= 0xF)
11778 return states[state_idx];
11780 return states[0x10];
11783 static const char *get_recovery_state(uint32_t state)
11785 static const char *states[] = { "NONE", "DONE", "INIT",
11786 "WAIT", "FAILED", "NIC_LOADING"
11788 return states[state];
11791 static const char *get_rx_mode(uint32_t mode)
11793 static const char *modes[] = { "NONE", "NORMAL", "ALLMULTI",
11794 "PROMISC", "MAX_MULTICAST", "ERROR"
11798 return modes[mode];
11799 else if (BNX2X_MAX_MULTICAST == mode)
11805 #define BNX2X_INFO_STR_MAX 256
11806 static const char *get_bnx2x_flags(uint32_t flags)
11809 static const char *flag[] = { "ONE_PORT ", "NO_ISCSI ",
11810 "NO_FCOE ", "NO_WOL ", "USING_DAC ", "USING_MSIX ",
11811 "USING_MSI ", "DISABLE_MSI ", "UNKNOWN ", "NO_MCP ",
11812 "SAFC_TX_FLAG ", "MF_FUNC_DIS ", "TX_SWITCHING "
11814 static char flag_str[BNX2X_INFO_STR_MAX];
11815 memset(flag_str, 0, BNX2X_INFO_STR_MAX);
11817 for (i = 0; i < 5; i++)
11818 if (flags & (1 << i)) {
11819 strlcat(flag_str, flag[i], sizeof(flag_str));
11823 static char unknown[BNX2X_INFO_STR_MAX];
11824 snprintf(unknown, 32, "Unknown flag mask %x", flags);
11825 strlcat(flag_str, unknown, sizeof(flag_str));
11830 /* Prints useful adapter info. */
11831 void bnx2x_print_adapter_info(struct bnx2x_softc *sc)
11835 PMD_DRV_LOG(INFO, sc, "========================================");
11836 /* DPDK and Driver versions */
11837 PMD_DRV_LOG(INFO, sc, "%12s : %s", "DPDK",
11839 PMD_DRV_LOG(INFO, sc, "%12s : %s", "Driver",
11840 bnx2x_pmd_version());
11841 /* Firmware versions. */
11842 PMD_DRV_LOG(INFO, sc, "%12s : %d.%d.%d",
11844 BNX2X_5710_FW_MAJOR_VERSION,
11845 BNX2X_5710_FW_MINOR_VERSION,
11846 BNX2X_5710_FW_REVISION_VERSION);
11847 PMD_DRV_LOG(INFO, sc, "%12s : %s",
11848 "Bootcode", sc->devinfo.bc_ver_str);
11849 /* Hardware chip info. */
11850 PMD_DRV_LOG(INFO, sc, "%12s : %#08x", "ASIC", sc->devinfo.chip_id);
11851 PMD_DRV_LOG(INFO, sc, "%12s : %c%d", "Rev", (CHIP_REV(sc) >> 12) + 'A',
11852 (CHIP_METAL(sc) >> 4));
11853 /* Bus PCIe info. */
11854 PMD_DRV_LOG(INFO, sc, "%12s : 0x%x", "Vendor Id",
11855 sc->devinfo.vendor_id);
11856 PMD_DRV_LOG(INFO, sc, "%12s : 0x%x", "Device Id",
11857 sc->devinfo.device_id);
11858 PMD_DRV_LOG(INFO, sc, "%12s : width x%d, ", "Bus PCIe",
11859 sc->devinfo.pcie_link_width);
11860 switch (sc->devinfo.pcie_link_speed) {
11862 PMD_DRV_LOG(INFO, sc, "%23s", "2.5 Gbps");
11865 PMD_DRV_LOG(INFO, sc, "%21s", "5 Gbps");
11868 PMD_DRV_LOG(INFO, sc, "%21s", "8 Gbps");
11871 PMD_DRV_LOG(INFO, sc, "%33s", "Unknown link speed");
11873 /* Device features. */
11874 PMD_DRV_LOG(INFO, sc, "%12s : ", "Flags");
11875 /* Miscellaneous flags. */
11876 if (sc->devinfo.pcie_cap_flags & BNX2X_MSI_CAPABLE_FLAG) {
11877 PMD_DRV_LOG(INFO, sc, "%18s", "MSI");
11880 if (sc->devinfo.pcie_cap_flags & BNX2X_MSIX_CAPABLE_FLAG) {
11882 PMD_DRV_LOG(INFO, sc, "|");
11883 PMD_DRV_LOG(INFO, sc, "%20s", "MSI-X");
11886 PMD_DRV_LOG(INFO, sc, "%12s : %s", "OVLAN", (OVLAN(sc) ? "YES" : "NO"));
11887 PMD_DRV_LOG(INFO, sc, "%12s : %s", "MF", (IS_MF(sc) ? "YES" : "NO"));
11888 PMD_DRV_LOG(INFO, sc, "========================================");
11891 /* Prints useful device info. */
11892 void bnx2x_print_device_info(struct bnx2x_softc *sc)
11894 __rte_unused uint32_t ext_phy_type;
11895 uint32_t offset, reg_val;
11897 PMD_INIT_FUNC_TRACE(sc);
11898 offset = offsetof(struct shmem_region,
11899 dev_info.port_hw_config[0].external_phy_config);
11900 reg_val = REG_RD(sc, sc->devinfo.shmem_base + offset);
11901 if (sc->link_vars.phy_flags & PHY_XGXS_FLAG)
11902 ext_phy_type = ELINK_XGXS_EXT_PHY_TYPE(reg_val);
11904 ext_phy_type = ELINK_SERDES_EXT_PHY_TYPE(reg_val);
11906 /* Device features. */
11907 PMD_DRV_LOG(INFO, sc, "%12s : %u", "Bnx2x Func", sc->pcie_func);
11908 PMD_DRV_LOG(INFO, sc,
11909 "%12s : %s", "Bnx2x Flags", get_bnx2x_flags(sc->flags));
11910 PMD_DRV_LOG(INFO, sc, "%12s : %s", "DMAE Is",
11911 (sc->dmae_ready ? "Ready" : "Not Ready"));
11912 PMD_DRV_LOG(INFO, sc, "%12s : %u", "MTU", sc->mtu);
11913 PMD_DRV_LOG(INFO, sc,
11914 "%12s : %s", "PHY Type", get_ext_phy_type(ext_phy_type));
11915 PMD_DRV_LOG(INFO, sc, "%12s : %x:%x:%x:%x:%x:%x", "MAC Addr",
11916 sc->link_params.mac_addr[0],
11917 sc->link_params.mac_addr[1],
11918 sc->link_params.mac_addr[2],
11919 sc->link_params.mac_addr[3],
11920 sc->link_params.mac_addr[4],
11921 sc->link_params.mac_addr[5]);
11922 PMD_DRV_LOG(INFO, sc, "%12s : %s", "RX Mode", get_rx_mode(sc->rx_mode));
11923 PMD_DRV_LOG(INFO, sc, "%12s : %s", "State", get_state(sc->state));
11924 if (sc->recovery_state)
11925 PMD_DRV_LOG(INFO, sc, "%12s : %s", "Recovery",
11926 get_recovery_state(sc->recovery_state));
11929 switch (sc->sp->rss_rdata.rss_mode) {
11930 case ETH_RSS_MODE_DISABLED:
11931 PMD_DRV_LOG(INFO, sc, "%12s : %s", "Queues", "RSS mode - None");
11933 case ETH_RSS_MODE_REGULAR:
11934 PMD_DRV_LOG(INFO, sc, "%12s : %s,", "Queues", "RSS mode - Regular");
11935 PMD_DRV_LOG(INFO, sc, "%16d", sc->num_queues);
11938 PMD_DRV_LOG(INFO, sc, "%12s : %s", "Queues", "RSS mode - Unknown");
11942 PMD_DRV_LOG(INFO, sc, "%12s : CQ = %lx, EQ = %lx", "SPQ Left",
11943 sc->cq_spq_left, sc->eq_spq_left);
11945 PMD_DRV_LOG(INFO, sc,
11946 "%12s : %x", "Switch", sc->link_params.switch_cfg);
11947 PMD_DRV_LOG(INFO, sc, "pcie_bus=%d, pcie_device=%d",
11948 sc->pcie_bus, sc->pcie_device);
11949 PMD_DRV_LOG(INFO, sc, "bar0.addr=%p, bar1.addr=%p",
11950 sc->bar[BAR0].base_addr, sc->bar[BAR1].base_addr);
11951 PMD_DRV_LOG(INFO, sc, "port=%d, path=%d, vnic=%d, func=%d",
11952 PORT_ID(sc), PATH_ID(sc), VNIC_ID(sc), FUNC_ID(sc));