1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2007-2013 Broadcom Corporation.
4 * Eric Davis <edavis@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
6 * Gary Zambrano <zambrano@broadcom.com>
8 * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
9 * Copyright (c) 2015-2018 Cavium Inc.
10 * All rights reserved.
17 #include <rte_byteorder.h>
18 #include <rte_spinlock.h>
19 #include <rte_bus_pci.h>
22 #include "bnx2x_osal.h"
23 #include "bnx2x_ethdev.h"
24 #include "ecore_mfw_req.h"
25 #include "ecore_fw_defs.h"
26 #include "ecore_hsi.h"
27 #include "ecore_reg.h"
28 #include "bnx2x_stats.h"
29 #include "bnx2x_vfpf.h"
34 #include <linux/pci_regs.h>
36 #define PCIY_PMG PCI_CAP_ID_PM
37 #define PCIY_MSI PCI_CAP_ID_MSI
38 #define PCIY_EXPRESS PCI_CAP_ID_EXP
39 #define PCIY_MSIX PCI_CAP_ID_MSIX
40 #define PCIR_EXPRESS_DEVICE_STA PCI_EXP_TYPE_RC_EC
41 #define PCIM_EXP_STA_TRANSACTION_PND PCI_EXP_DEVSTA_TRPND
42 #define PCIR_EXPRESS_LINK_STA PCI_EXP_LNKSTA
43 #define PCIM_LINK_STA_WIDTH PCI_EXP_LNKSTA_NLW
44 #define PCIM_LINK_STA_SPEED PCI_EXP_LNKSTA_CLS
45 #define PCIR_EXPRESS_DEVICE_CTL PCI_EXP_DEVCTL
46 #define PCIM_EXP_CTL_MAX_PAYLOAD PCI_EXP_DEVCTL_PAYLOAD
47 #define PCIM_EXP_CTL_MAX_READ_REQUEST PCI_EXP_DEVCTL_READRQ
48 #define PCIR_POWER_STATUS PCI_PM_CTRL
49 #define PCIM_PSTAT_DMASK PCI_PM_CTRL_STATE_MASK
50 #define PCIM_PSTAT_PME PCI_PM_CTRL_PME_STATUS
51 #define PCIM_PSTAT_D3 0x3
52 #define PCIM_PSTAT_PMEENABLE PCI_PM_CTRL_PME_ENABLE
53 #define PCIR_MSIX_CTRL PCI_MSIX_FLAGS
54 #define PCIM_MSIXCTRL_TABLE_SIZE PCI_MSIX_FLAGS_QSIZE
56 #include <dev/pci/pcireg.h>
59 #define IFM_10G_CX4 20 /* 10GBase CX4 copper */
60 #define IFM_10G_TWINAX 22 /* 10GBase Twinax copper */
61 #define IFM_10G_T 26 /* 10GBase-T - RJ45 */
64 #define PCIR_EXPRESS_DEVICE_STA PCI_EXP_TYPE_RC_EC
65 #define PCIM_EXP_STA_TRANSACTION_PND PCI_EXP_DEVSTA_TRPND
66 #define PCIR_EXPRESS_LINK_STA PCI_EXP_LNKSTA
67 #define PCIM_LINK_STA_WIDTH PCI_EXP_LNKSTA_NLW
68 #define PCIM_LINK_STA_SPEED PCI_EXP_LNKSTA_CLS
69 #define PCIR_EXPRESS_DEVICE_CTL PCI_EXP_DEVCTL
70 #define PCIM_EXP_CTL_MAX_PAYLOAD PCI_EXP_DEVCTL_PAYLOAD
71 #define PCIM_EXP_CTL_MAX_READ_REQUEST PCI_EXP_DEVCTL_READRQ
73 #define PCIR_EXPRESS_DEVICE_STA PCIER_DEVICE_STA
74 #define PCIM_EXP_STA_TRANSACTION_PND PCIEM_STA_TRANSACTION_PND
75 #define PCIR_EXPRESS_LINK_STA PCIER_LINK_STA
76 #define PCIM_LINK_STA_WIDTH PCIEM_LINK_STA_WIDTH
77 #define PCIM_LINK_STA_SPEED PCIEM_LINK_STA_SPEED
78 #define PCIR_EXPRESS_DEVICE_CTL PCIER_DEVICE_CTL
79 #define PCIM_EXP_CTL_MAX_PAYLOAD PCIEM_CTL_MAX_PAYLOAD
80 #define PCIM_EXP_CTL_MAX_READ_REQUEST PCIEM_CTL_MAX_READ_REQUEST
84 #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
87 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
90 #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
94 int bnx2x_ilog2(int x)
105 #define ilog2(x) bnx2x_ilog2(x)
108 #define BNX2X_BC_VER 0x040200
110 #include "ecore_sp.h"
112 struct bnx2x_device_type {
120 #define BNX2X_PAGE_SHIFT 12
121 #define BNX2X_PAGE_SIZE (1 << BNX2X_PAGE_SHIFT)
122 #define BNX2X_PAGE_MASK (~(BNX2X_PAGE_SIZE - 1))
123 #define BNX2X_PAGE_ALIGN(addr) ((addr + BNX2X_PAGE_SIZE - 1) & BNX2X_PAGE_MASK)
125 #if BNX2X_PAGE_SIZE != 4096
126 #error Page sizes other than 4KB are unsupported!
129 #define U64_LO(addr) ((uint32_t)(((uint64_t)(addr)) & 0xFFFFFFFF))
130 #define U64_HI(addr) ((uint32_t)(((uint64_t)(addr)) >> 32))
131 #define HILO_U64(hi, lo) ((((uint64_t)(hi)) << 32) + (lo))
133 /* dropless fc FW/HW related params */
134 #define BRB_SIZE(sc) (CHIP_IS_E3(sc) ? 1024 : 512)
135 #define MAX_AGG_QS(sc) ETH_MAX_AGGREGATION_QUEUES_E1H_E2
136 #define FW_DROP_LEVEL(sc) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(sc))
137 #define FW_PREFETCH_CNT 16U
138 #define DROPLESS_FC_HEADROOM 100
141 * Transmit Buffer Descriptor (tx_bd) definitions*
143 /* NUM_TX_PAGES must be a power of 2. */
144 #define NUM_TX_PAGES 16
145 #define TOTAL_TX_BD_PER_PAGE (BNX2X_PAGE_SIZE / sizeof(union eth_tx_bd_types)) /* 256 */
146 #define USABLE_TX_BD_PER_PAGE (TOTAL_TX_BD_PER_PAGE - 1) /* 255 */
148 #define TOTAL_TX_BD(q) (TOTAL_TX_BD_PER_PAGE * q->nb_tx_pages) /* 512 */
149 #define USABLE_TX_BD(q) (USABLE_TX_BD_PER_PAGE * q->nb_tx_pages) /* 510 */
150 #define MAX_TX_BD(q) (TOTAL_TX_BD(q) - 1) /* 511 */
151 #define MAX_TX_AVAIL (USABLE_TX_BD_PER_PAGE * NUM_TX_PAGES - 2)
152 #define NEXT_TX_BD(x) \
153 ((((x) & USABLE_TX_BD_PER_PAGE) == \
154 (USABLE_TX_BD_PER_PAGE - 1)) ? (x) + 2 : (x) + 1)
156 #define TX_BD(x, q) ((x) & MAX_TX_BD(q))
157 #define TX_PAGE(x) (((x) & ~USABLE_TX_BD_PER_PAGE) >> 8)
158 #define TX_IDX(x) ((x) & USABLE_TX_BD_PER_PAGE)
160 #define BDS_PER_TX_PKT (3)
163 * Trigger pending transmits when the number of available BDs is greater
164 * than 1/8 of the total number of usable BDs.
166 #define BNX2X_TX_CLEANUP_THRESHOLD(q) (USABLE_TX_BD(q) / 8)
167 #define BNX2X_TX_TIMEOUT 5
170 * Receive Buffer Descriptor (rx_bd) definitions*
172 #define MAX_RX_PAGES 8
173 #define TOTAL_RX_BD_PER_PAGE (BNX2X_PAGE_SIZE / sizeof(struct eth_rx_bd)) /* 512 */
174 #define USABLE_RX_BD_PER_PAGE (TOTAL_RX_BD_PER_PAGE - 2) /* 510 */
175 #define RX_BD_PER_PAGE_MASK (TOTAL_RX_BD_PER_PAGE - 1) /* 511 */
176 #define TOTAL_RX_BD(q) (TOTAL_RX_BD_PER_PAGE * q->nb_rx_pages) /* 512 */
177 #define USABLE_RX_BD(q) (USABLE_RX_BD_PER_PAGE * q->nb_rx_pages) /* 510 */
178 #define MAX_RX_BD(q) (TOTAL_RX_BD(q) - 1) /* 511 */
179 #define MAX_RX_AVAIL (USABLE_RX_BD_PER_PAGE * MAX_RX_PAGES - 2)
180 #define RX_BD_NEXT_PAGE_DESC_CNT 2
182 #define NEXT_RX_BD(x) \
183 ((((x) & RX_BD_PER_PAGE_MASK) == \
184 (USABLE_RX_BD_PER_PAGE - 1)) ? (x) + 3 : (x) + 1)
187 #define RX_BD(x, q) ((x) & MAX_RX_BD(q))
188 #define RX_PAGE(x) (((x) & ~RX_BD_PER_PAGE_MASK) >> 9)
189 #define RX_IDX(x) ((x) & RX_BD_PER_PAGE_MASK)
192 * Receive Completion Queue definitions*
194 //#define NUM_RCQ_PAGES (NUM_RX_PAGES * 4)
195 #define TOTAL_RCQ_ENTRIES_PER_PAGE (BNX2X_PAGE_SIZE / sizeof(union eth_rx_cqe)) /* 128 */
196 #define USABLE_RCQ_ENTRIES_PER_PAGE (TOTAL_RCQ_ENTRIES_PER_PAGE - 1) /* 127 */
197 #define TOTAL_RCQ_ENTRIES(q) (TOTAL_RCQ_ENTRIES_PER_PAGE * q->nb_cq_pages) /* 512 */
198 #define USABLE_RCQ_ENTRIES(q) (USABLE_RCQ_ENTRIES_PER_PAGE * q->nb_cq_pages) /* 508 */
199 #define MAX_RCQ_ENTRIES(q) (TOTAL_RCQ_ENTRIES(q) - 1) /* 511 */
200 #define RCQ_NEXT_PAGE_DESC_CNT 1
202 #define NEXT_RCQ_IDX(x) \
203 ((((x) & USABLE_RCQ_ENTRIES_PER_PAGE) == \
204 (USABLE_RCQ_ENTRIES_PER_PAGE - 1)) ? (x) + 2 : (x) + 1)
207 (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd))
209 #define RCQ_BD_PAGES(q) \
210 (q->nb_rx_pages * CQE_BD_REL)
212 #define RCQ_ENTRY(x, q) ((x) & MAX_RCQ_ENTRIES(q))
213 #define RCQ_PAGE(x) (((x) & ~USABLE_RCQ_ENTRIES_PER_PAGE) >> 7)
214 #define RCQ_IDX(x) ((x) & USABLE_RCQ_ENTRIES_PER_PAGE)
217 * dropless fc calculations for BDs
218 * Number of BDs should be as number of buffers in BRB:
219 * Low threshold takes into account RX_BD_NEXT_PAGE_DESC_CNT
220 * "next" elements on each page
222 #define NUM_BD_REQ(sc) \
224 #define NUM_BD_PG_REQ(sc) \
225 ((NUM_BD_REQ(sc) + USABLE_RX_BD_PER_PAGE - 1) / USABLE_RX_BD_PER_PAGE)
226 #define BD_TH_LO(sc) \
228 NUM_BD_PG_REQ(sc) * RX_BD_NEXT_PAGE_DESC_CNT + \
230 #define BD_TH_HI(sc) \
231 (BD_TH_LO(sc) + DROPLESS_FC_HEADROOM)
232 #define MIN_RX_AVAIL(sc) \
233 ((sc)->dropless_fc ? BD_TH_HI(sc) + 128 : 128)
235 #define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA
236 #define MIN_RX_SIZE_NONTPA (RTE_MAX((uint32_t)MIN_RX_SIZE_NONTPA_HW,\
237 (uint32_t)MIN_RX_AVAIL(sc)))
240 * dropless fc calculations for RCQs
241 * Number of RCQs should be as number of buffers in BRB:
242 * Low threshold takes into account RCQ_NEXT_PAGE_DESC_CNT
243 * "next" elements on each page
245 #define NUM_RCQ_REQ(sc) \
247 #define NUM_RCQ_PG_REQ(sc) \
248 ((NUM_RCQ_REQ(sc) + USABLE_RCQ_ENTRIES_PER_PAGE - 1) / USABLE_RCQ_ENTRIES_PER_PAGE)
249 #define RCQ_TH_LO(sc) \
251 NUM_RCQ_PG_REQ(sc) * RCQ_NEXT_PAGE_DESC_CNT + \
253 #define RCQ_TH_HI(sc) \
254 (RCQ_TH_LO(sc) + DROPLESS_FC_HEADROOM)
256 /* Load / Unload modes */
257 #define LOAD_NORMAL 0
260 #define LOAD_LOOPBACK_EXT 3
261 #define UNLOAD_NORMAL 0
262 #define UNLOAD_CLOSE 1
263 #define UNLOAD_RECOVERY 2
265 /* Some constants... */
266 //#define MAX_PATH_NUM 2
267 //#define E2_MAX_NUM_OF_VFS 64
268 //#define E1H_FUNC_MAX 8
269 //#define E2_FUNC_MAX 4 /* per path */
270 #define MAX_VNIC_NUM 4
271 #define MAX_FUNC_NUM 8 /* common to all chips */
272 //#define MAX_NDSB HC_SB_MAX_SB_E2 /* max non-default status block */
273 #define MAX_RSS_CHAINS 16 /* a constant for HW limit */
274 #define MAX_MSI_VECTOR 8 /* a constant for HW limit */
276 #define ILT_NUM_PAGE_ENTRIES 3072
278 * 57711 we use whole table since we have 8 functions.
279 * 57712 we have only 4 functions, but use same size per func, so only half
280 * of the table is used.
282 #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES / 8)
283 #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC)
285 * the phys address is shifted right 12 bits and has an added
286 * 1=valid bit added to the 53rd bit
287 * then since this is a wide register(TM)
288 * we split it into two 32 bit writes
290 #define ONCHIP_ADDR1(x) ((uint32_t)(((uint64_t)x >> 12) & 0xFFFFFFFF))
291 #define ONCHIP_ADDR2(x) ((uint32_t)((1 << 20) | ((uint64_t)x >> 44)))
293 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
295 #define ETH_OVERHEAD (ETH_HLEN + 8 + 8)
296 #define ETH_MIN_PACKET_SIZE 60
297 #define ETH_MAX_PACKET_SIZE ETHERMTU /* 1500 */
298 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
299 /* TCP with Timestamp Option (32) + IPv6 (40) */
301 /* max supported alignment is 256 (8 shift) */
302 #define BNX2X_RX_ALIGN_SHIFT RTE_MAX(6, min(8, RTE_CACHE_LINE_SIZE_LOG2))
304 #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5)
310 /* Used to manage DMA allocations. */
312 struct bnx2x_softc *sc;
317 char msg[RTE_MEMZONE_NAMESIZE - 6];
320 /* attn group wiring */
321 #define MAX_DYNAMIC_ATTN_GRPS 8
335 union bnx2x_host_hc_status_block {
336 /* pointer to fp status block e2 */
337 struct host_hc_status_block_e2 *e2_sb;
338 /* pointer to fp status block e1x */
339 struct host_hc_status_block_e1x *e1x_sb;
342 union bnx2x_db_prod {
343 struct doorbell_set_prod data;
347 struct bnx2x_sw_tx_bd {
351 /* set on the first BD descriptor when there is a split BD */
352 #define BNX2X_TSO_SPLIT_BD (1 << 0)
356 * This is the HSI fastpath data structure. There can be up to MAX_RSS_CHAIN
357 * instances of the fastpath structure when using multiple queues.
359 struct bnx2x_fastpath {
360 /* pointer back to parent structure */
361 struct bnx2x_softc *sc;
364 struct bnx2x_dma sb_dma;
365 union bnx2x_host_hc_status_block status_block;
367 rte_iova_t tx_desc_mapping;
369 rte_iova_t rx_desc_mapping;
370 rte_iova_t rx_comp_mapping;
372 uint16_t *sb_index_values;
373 uint16_t *sb_running_index;
374 uint32_t ustorm_rx_prods_offset;
376 uint8_t igu_sb_id; /* status block number in HW */
377 uint8_t fw_sb_id; /* status block number in FW */
379 uint32_t rx_buf_size;
382 #define BNX2X_FP_STATE_CLOSED 0x01
383 #define BNX2X_FP_STATE_IRQ 0x02
384 #define BNX2X_FP_STATE_OPENING 0x04
385 #define BNX2X_FP_STATE_OPEN 0x08
386 #define BNX2X_FP_STATE_HALTING 0x10
387 #define BNX2X_FP_STATE_HALTED 0x20
389 /* reference back to this fastpath queue number */
390 uint8_t index; /* this is also the 'cid' */
391 #define FP_IDX(fp) (fp->index)
393 /* ethernet client ID (each fastpath set of RX/TX/CQE is a client) */
395 #define FP_CL_ID(fp) (fp->cl_id)
400 union bnx2x_db_prod tx_db;
402 struct tstorm_per_queue_stats old_tclient;
403 struct ustorm_per_queue_stats old_uclient;
404 struct xstorm_per_queue_stats old_xclient;
405 struct bnx2x_eth_q_stats eth_q_stats;
406 struct bnx2x_eth_q_stats_old eth_q_stats_old;
408 /* Pointer to the receive consumer in the status block */
409 uint16_t *rx_cq_cons_sb;
411 /* Pointer to the transmit consumer in the status block */
412 uint16_t *tx_cons_sb;
414 /* transmit timeout until chip reset */
417 }; /* struct bnx2x_fastpath */
419 #define BNX2X_MAX_NUM_OF_VFS 64
420 #define BNX2X_VF_ID_INVALID 0xFF
422 /* maximum number of fast-path interrupt contexts */
423 #define FP_SB_MAX_E1x 16
424 #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2
427 struct eth_context eth;
431 /* CDU host DB constants */
432 #define CDU_ILT_PAGE_SZ_HW 2
433 #define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */
434 #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context))
436 #define CNIC_ISCSI_CID_MAX 256
437 #define CNIC_FCOE_CID_MAX 2048
438 #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX)
439 #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS)
441 #define QM_ILT_PAGE_SZ_HW 0
442 #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */
443 #define QM_CID_ROUND 1024
445 /* TM (timers) host DB constants */
446 #define TM_ILT_PAGE_SZ_HW 0
447 #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */
448 /*#define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */
449 #define TM_CONN_NUM 1024
450 #define TM_ILT_SZ (8 * TM_CONN_NUM)
451 #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ)
453 /* SRC (Searcher) host DB constants */
454 #define SRC_ILT_PAGE_SZ_HW 0
455 #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */
456 #define SRC_HASH_BITS 10
457 #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */
458 #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM)
459 #define SRC_T2_SZ SRC_ILT_SZ
460 #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ)
463 struct bnx2x_dma vcxt_dma;
464 union cdu_context *vcxt;
465 //rte_iova_t cxt_mapping;
472 /* defines for multiple tx priority indices */
473 #define FIRST_TX_ONLY_COS_INDEX 1
474 #define FIRST_TX_COS_INDEX 0
476 #define CID_TO_FP(cid, sc) ((cid) % BNX2X_NUM_NON_CNIC_QUEUES(sc))
478 #define HC_INDEX_ETH_RX_CQ_CONS 1
479 #define HC_INDEX_OOO_TX_CQ_CONS 4
480 #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5
481 #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6
482 #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7
483 #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0
485 /* congestion management fairness mode */
486 #define CMNG_FNS_NONE 0
487 #define CMNG_FNS_MINMAX 1
489 /* CMNG constants, as derived from system spec calculations */
490 /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */
491 #define DEF_MIN_RATE 100
492 /* resolution of the rate shaping timer - 400 usec */
493 #define RS_PERIODIC_TIMEOUT_USEC 400
494 /* number of bytes in single QM arbitration cycle -
495 * coefficient for calculating the fairness timer */
496 #define QM_ARB_BYTES 160000
497 /* resolution of Min algorithm 1:100 */
499 /* how many bytes above threshold for the minimal credit of Min algorithm*/
500 #define MIN_ABOVE_THRESH 32768
501 /* fairness algorithm integration time coefficient -
502 * for calculating the actual Tfair */
503 #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES)
504 /* memory of fairness algorithm - 2 cycles */
507 #define HC_SEG_ACCESS_DEF 0 /* Driver decision 0-3 */
508 #define HC_SEG_ACCESS_ATTN 4
509 #define HC_SEG_ACCESS_NORM 0 /* Driver decision 0-1 */
512 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is
513 * control by the number of fast-path status blocks supported by the
514 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default
515 * status block represents an independent interrupts context that can
516 * serve a regular L2 networking queue. However special L2 queues such
517 * as the FCoE queue do not require a FP-SB and other components like
518 * the CNIC may consume FP-SB reducing the number of possible L2 queues
520 * If the maximum number of FP-SB available is X then:
521 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of
522 * regular L2 queues is Y=X-1
523 * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor)
524 * c. If the FCoE L2 queue is supported the actual number of L2 queues
526 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for
527 * slow-path interrupts) or Y+2 if CNIC is supported (one additional
528 * FP interrupt context for the CNIC).
529 * e. The number of HW context (CID count) is always X or X+1 if FCoE
530 * L2 queue is supported. the cid for the FCoE L2 queue is always X.
532 * So this is quite simple for now as no ULPs are supported yet. :-)
534 #define BNX2X_NUM_QUEUES(sc) ((sc)->num_queues)
535 #define BNX2X_NUM_ETH_QUEUES(sc) BNX2X_NUM_QUEUES(sc)
536 #define BNX2X_NUM_NON_CNIC_QUEUES(sc) BNX2X_NUM_QUEUES(sc)
537 #define BNX2X_NUM_RX_QUEUES(sc) BNX2X_NUM_QUEUES(sc)
539 #define FOR_EACH_QUEUE(sc, var) \
540 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(sc); (var)++)
542 #define FOR_EACH_NONDEFAULT_QUEUE(sc, var) \
543 for ((var) = 1; (var) < BNX2X_NUM_QUEUES(sc); (var)++)
545 #define FOR_EACH_ETH_QUEUE(sc, var) \
546 for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(sc); (var)++)
548 #define FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, var) \
549 for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(sc); (var)++)
551 #define FOR_EACH_COS_IN_TX_QUEUE(sc, var) \
552 for ((var) = 0; (var) < (sc)->max_cos; (var)++)
554 #define FOR_EACH_CNIC_QUEUE(sc, var) \
555 for ((var) = BNX2X_NUM_ETH_QUEUES(sc); \
556 (var) < BNX2X_NUM_QUEUES(sc); \
565 #define FCOE_IDX(sc) (BNX2X_NUM_NON_CNIC_QUEUES(sc) + FCOE_IDX_OFFSET)
566 #define bnx2x_fcoe_fp(sc) (&sc->fp[FCOE_IDX(sc)])
567 #define bnx2x_fcoe(sc, var) (bnx2x_fcoe_fp(sc)->var)
568 #define bnx2x_fcoe_inner_sp_obj(sc) (&sc->sp_objs[FCOE_IDX(sc)])
569 #define bnx2x_fcoe_sp_obj(sc, var) (bnx2x_fcoe_inner_sp_obj(sc)->var)
570 #define bnx2x_fcoe_tx(sc, var) (bnx2x_fcoe_fp(sc)->txdata_ptr[FIRST_TX_COS_INDEX]->var)
572 #define OOO_IDX(sc) (BNX2X_NUM_NON_CNIC_QUEUES(sc) + OOO_IDX_OFFSET)
573 #define bnx2x_ooo_fp(sc) (&sc->fp[OOO_IDX(sc)])
574 #define bnx2x_ooo(sc, var) (bnx2x_ooo_fp(sc)->var)
575 #define bnx2x_ooo_inner_sp_obj(sc) (&sc->sp_objs[OOO_IDX(sc)])
576 #define bnx2x_ooo_sp_obj(sc, var) (bnx2x_ooo_inner_sp_obj(sc)->var)
578 #define FWD_IDX(sc) (BNX2X_NUM_NON_CNIC_QUEUES(sc) + FWD_IDX_OFFSET)
579 #define bnx2x_fwd_fp(sc) (&sc->fp[FWD_IDX(sc)])
580 #define bnx2x_fwd(sc, var) (bnx2x_fwd_fp(sc)->var)
581 #define bnx2x_fwd_inner_sp_obj(sc) (&sc->sp_objs[FWD_IDX(sc)])
582 #define bnx2x_fwd_sp_obj(sc, var) (bnx2x_fwd_inner_sp_obj(sc)->var)
583 #define bnx2x_fwd_txdata(fp) (fp->txdata_ptr[FIRST_TX_COS_INDEX])
585 #define IS_ETH_FP(fp) ((fp)->index < BNX2X_NUM_ETH_QUEUES((fp)->sc))
586 #define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->sc))
587 #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(sc))
588 #define IS_FWD_FP(fp) ((fp)->index == FWD_IDX((fp)->sc))
589 #define IS_FWD_IDX(idx) ((idx) == FWD_IDX(sc))
590 #define IS_OOO_FP(fp) ((fp)->index == OOO_IDX((fp)->sc))
591 #define IS_OOO_IDX(idx) ((idx) == OOO_IDX(sc))
594 BNX2X_PORT_QUERY_IDX,
596 BNX2X_FCOE_QUERY_IDX,
597 BNX2X_FIRST_QUEUE_QUERY_IDX,
600 struct bnx2x_fw_stats_req {
601 struct stats_query_header hdr;
602 struct stats_query_entry query[FP_SB_MAX_E1x +
603 BNX2X_FIRST_QUEUE_QUERY_IDX];
606 struct bnx2x_fw_stats_data {
607 struct stats_counter storm_counters;
608 struct per_port_stats port;
609 struct per_pf_stats pf;
610 struct per_queue_stats queue_stats[1];
613 /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */
614 #define BNX2X_IGU_STAS_MSG_VF_CNT 64
615 #define BNX2X_IGU_STAS_MSG_PF_CNT 4
620 * This is the slowpath data structure. It is mapped into non-paged memory
621 * so that the hardware can access it's contents directly and must be page
624 struct bnx2x_slowpath {
626 /* used by the DMAE command executer */
627 struct dmae_command dmae[MAX_DMAE_C];
629 /* statistics completion */
632 /* firmware defined statistics blocks */
633 union mac_stats mac_stats;
634 struct nig_stats nig_stats;
635 struct host_port_stats port_stats;
636 struct host_func_stats func_stats;
638 /* DMAE completion value and data source/sink */
643 struct mac_configuration_cmd e1x;
644 struct eth_classify_rules_ramrod_data e2;
648 struct tstorm_eth_mac_filter_config e1x;
649 struct eth_filter_rules_ramrod_data e2;
652 struct eth_rss_update_ramrod_data rss_rdata;
655 struct mac_configuration_cmd e1;
656 struct eth_multicast_rules_ramrod_data e2;
660 struct function_start_data func_start;
661 struct flow_control_configuration pfc_config; /* for DCBX ramrod */
664 /* Queue State related ramrods */
666 struct client_init_ramrod_data init_data;
667 struct client_update_ramrod_data update_data;
671 * AFEX ramrod can not be a part of func_rdata union because these
672 * events might arrive in parallel to other events from func_rdata.
673 * If they were defined in the same union the data can get corrupted.
675 struct afex_vif_list_ramrod_data func_afex_rdata;
677 union drv_info_to_mcp drv_info_to_mcp;
678 }; /* struct bnx2x_slowpath */
681 * Port specifc data structure.
685 * Port Management Function (for 57711E only).
686 * When this field is set the driver instance is
687 * responsible for managing port specifc
688 * configurations such as handling link attentions.
692 /* Ethernet maximum transmission unit. */
695 uint32_t link_config[ELINK_LINK_CONFIG_SIZE];
697 uint32_t ext_phy_config;
699 /* Port feature config.*/
702 /* Defines the features supported by the PHY. */
703 uint32_t supported[ELINK_LINK_CONFIG_SIZE];
705 /* Defines the features advertised by the PHY. */
706 uint32_t advertising[ELINK_LINK_CONFIG_SIZE];
707 #define ADVERTISED_10baseT_Half (1 << 1)
708 #define ADVERTISED_10baseT_Full (1 << 2)
709 #define ADVERTISED_100baseT_Half (1 << 3)
710 #define ADVERTISED_100baseT_Full (1 << 4)
711 #define ADVERTISED_1000baseT_Half (1 << 5)
712 #define ADVERTISED_1000baseT_Full (1 << 6)
713 #define ADVERTISED_TP (1 << 7)
714 #define ADVERTISED_FIBRE (1 << 8)
715 #define ADVERTISED_Autoneg (1 << 9)
716 #define ADVERTISED_Asym_Pause (1 << 10)
717 #define ADVERTISED_Pause (1 << 11)
718 #define ADVERTISED_2500baseX_Full (1 << 15)
719 #define ADVERTISED_10000baseT_Full (1 << 16)
723 /* Used to synchronize phy accesses. */
724 rte_spinlock_t phy_mtx;
725 char phy_mtx_name[32];
727 #define BNX2X_PHY_LOCK(sc) rte_spinlock_lock(&sc->port.phy_mtx)
728 #define BNX2X_PHY_UNLOCK(sc) rte_spinlock_unlock(&sc->port.phy_mtx)
731 * MCP scratchpad address for port specific statistics.
732 * The device is responsible for writing statistcss
733 * back to the MCP for use with management firmware such
738 struct nig_stats old_nig_stats;
739 }; /* struct bnx2x_port */
741 struct bnx2x_mf_info {
742 uint32_t mf_config[E1HVN_MAX];
744 uint32_t vnics_per_port; /* 1, 2 or 4 */
745 uint32_t multi_vnics_mode; /* can be set even if vnics_per_port = 1 */
746 uint32_t path_has_ovlan; /* MF mode in the path (can be different than the MF mode of the function */
748 #define IS_MULTI_VNIC(sc) ((sc)->devinfo.mf_info.multi_vnics_mode)
749 #define VNICS_PER_PORT(sc) ((sc)->devinfo.mf_info.vnics_per_port)
750 #define VNICS_PER_PATH(sc) \
751 ((sc)->devinfo.mf_info.vnics_per_port * \
752 ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 1 ))
754 uint8_t min_bw[MAX_VNIC_NUM];
755 uint8_t max_bw[MAX_VNIC_NUM];
757 uint16_t ext_id; /* vnic outer vlan or VIF ID */
758 #define VALID_OVLAN(ovlan) ((ovlan) <= 4096)
759 #define INVALID_VIF_ID 0xFFFF
760 #define OVLAN(sc) ((sc)->devinfo.mf_info.ext_id)
761 #define VIF_ID(sc) ((sc)->devinfo.mf_info.ext_id)
763 uint16_t default_vlan;
764 #define NIV_DEFAULT_VLAN(sc) ((sc)->devinfo.mf_info.default_vlan)
766 uint8_t niv_allowed_priorities;
767 #define NIV_ALLOWED_PRIORITIES(sc) ((sc)->devinfo.mf_info.niv_allowed_priorities)
769 uint8_t niv_default_cos;
770 #define NIV_DEFAULT_COS(sc) ((sc)->devinfo.mf_info.niv_default_cos)
772 uint8_t niv_mba_enabled;
774 enum mf_cfg_afex_vlan_mode afex_vlan_mode;
775 #define AFEX_VLAN_MODE(sc) ((sc)->devinfo.mf_info.afex_vlan_mode)
776 int afex_def_vlan_tag;
777 uint32_t pending_max;
780 #define MF_INFO_VALID_MAC 0x0001
783 uint8_t mf_mode; /* Switch-Dependent or Switch-Independent */
785 (IS_MULTI_VNIC(sc) && \
786 ((sc)->devinfo.mf_info.mf_mode != 0))
787 #define IS_MF_SD(sc) \
788 (IS_MULTI_VNIC(sc) && \
789 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SD))
790 #define IS_MF_SI(sc) \
791 (IS_MULTI_VNIC(sc) && \
792 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SI))
793 #define IS_MF_AFEX(sc) \
794 (IS_MULTI_VNIC(sc) && \
795 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_AFEX))
796 #define IS_MF_SD_MODE(sc) IS_MF_SD(sc)
797 #define IS_MF_SI_MODE(sc) IS_MF_SI(sc)
798 #define IS_MF_AFEX_MODE(sc) IS_MF_AFEX(sc)
800 uint32_t mf_protos_supported;
801 #define MF_PROTO_SUPPORT_ETHERNET 0x1
802 #define MF_PROTO_SUPPORT_ISCSI 0x2
803 #define MF_PROTO_SUPPORT_FCOE 0x4
804 }; /* struct bnx2x_mf_info */
806 /* Device information data structure. */
807 struct bnx2x_devinfo {
809 #define NAME_SIZE 128
810 char name[NAME_SIZE];
815 uint16_t subvendor_id;
816 uint16_t subdevice_id;
819 * chip_id = 0b'CCCCCCCCCCCCCCCCRRRRMMMMMMMMBBBB'
820 * C = Chip Number (bits 16-31)
821 * R = Chip Revision (bits 12-15)
822 * M = Chip Metal (bits 4-11)
823 * B = Chip Bond ID (bits 0-3)
826 #define CHIP_ID(sc) ((sc)->devinfo.chip_id & 0xffff0000)
827 #define CHIP_NUM(sc) ((sc)->devinfo.chip_id >> 16)
829 #define CHIP_NUM_57710 0x164e
830 #define CHIP_NUM_57711 0x164f
831 #define CHIP_NUM_57711E 0x1650
832 #define CHIP_NUM_57712 0x1662
833 #define CHIP_NUM_57712_MF 0x1663
834 #define CHIP_NUM_57712_VF 0x166f
835 #define CHIP_NUM_57800 0x168a
836 #define CHIP_NUM_57800_MF 0x16a5
837 #define CHIP_NUM_57800_VF 0x16a9
838 #define CHIP_NUM_57810 0x168e
839 #define CHIP_NUM_57810_MF 0x16ae
840 #define CHIP_NUM_57810_VF 0x16af
841 #define CHIP_NUM_57811 0x163d
842 #define CHIP_NUM_57811_MF 0x163e
843 #define CHIP_NUM_57811_VF 0x163f
844 #define CHIP_NUM_57840_OBS 0x168d
845 #define CHIP_NUM_57840_OBS_MF 0x16ab
846 #define CHIP_NUM_57840_4_10 0x16a1
847 #define CHIP_NUM_57840_2_20 0x16a2
848 #define CHIP_NUM_57840_MF 0x16a4
849 #define CHIP_NUM_57840_VF 0x16ad
851 #define CHIP_REV_SHIFT 12
852 #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT)
853 #define CHIP_REV(sc) ((sc)->devinfo.chip_id & CHIP_REV_MASK)
855 #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT)
856 #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT)
857 #define CHIP_REV_Cx (0x2 << CHIP_REV_SHIFT)
859 #define CHIP_REV_IS_SLOW(sc) \
860 (CHIP_REV(sc) > 0x00005000)
861 #define CHIP_REV_IS_FPGA(sc) \
862 (CHIP_REV_IS_SLOW(sc) && (CHIP_REV(sc) & 0x00001000))
863 #define CHIP_REV_IS_EMUL(sc) \
864 (CHIP_REV_IS_SLOW(sc) && !(CHIP_REV(sc) & 0x00001000))
865 #define CHIP_REV_IS_ASIC(sc) \
866 (!CHIP_REV_IS_SLOW(sc))
868 #define CHIP_METAL(sc) ((sc->devinfo.chip_id) & 0x00000ff0)
869 #define CHIP_BOND_ID(sc) ((sc->devinfo.chip_id) & 0x0000000f)
871 #define CHIP_IS_E1(sc) (CHIP_NUM(sc) == CHIP_NUM_57710)
872 #define CHIP_IS_57710(sc) (CHIP_NUM(sc) == CHIP_NUM_57710)
873 #define CHIP_IS_57711(sc) (CHIP_NUM(sc) == CHIP_NUM_57711)
874 #define CHIP_IS_57711E(sc) (CHIP_NUM(sc) == CHIP_NUM_57711E)
875 #define CHIP_IS_E1H(sc) ((CHIP_IS_57711(sc)) || \
876 (CHIP_IS_57711E(sc)))
877 #define CHIP_IS_E1x(sc) CHIP_IS_E1H(sc)
879 #define CHIP_IS_57712(sc) (CHIP_NUM(sc) == CHIP_NUM_57712)
880 #define CHIP_IS_57712_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_MF)
881 #define CHIP_IS_57712_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_VF)
882 #define CHIP_IS_E2(sc) (CHIP_IS_57712(sc) || \
883 CHIP_IS_57712_MF(sc))
885 #define CHIP_IS_57800(sc) (CHIP_NUM(sc) == CHIP_NUM_57800)
886 #define CHIP_IS_57800_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_MF)
887 #define CHIP_IS_57800_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_VF)
888 #define CHIP_IS_57810(sc) (CHIP_NUM(sc) == CHIP_NUM_57810)
889 #define CHIP_IS_57810_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_MF)
890 #define CHIP_IS_57810_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_VF)
891 #define CHIP_IS_57811(sc) (CHIP_NUM(sc) == CHIP_NUM_57811)
892 #define CHIP_IS_57811_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_MF)
893 #define CHIP_IS_57811_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_VF)
894 #define CHIP_IS_57840(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS) || \
895 (CHIP_NUM(sc) == CHIP_NUM_57840_4_10) || \
896 (CHIP_NUM(sc) == CHIP_NUM_57840_2_20))
897 #define CHIP_IS_57840_MF(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS_MF) || \
898 (CHIP_NUM(sc) == CHIP_NUM_57840_MF))
899 #define CHIP_IS_57840_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57840_VF)
901 #define CHIP_IS_E3(sc) (CHIP_IS_57800(sc) || \
902 CHIP_IS_57800_MF(sc) || \
903 CHIP_IS_57800_VF(sc) || \
904 CHIP_IS_57810(sc) || \
905 CHIP_IS_57810_MF(sc) || \
906 CHIP_IS_57810_VF(sc) || \
907 CHIP_IS_57811(sc) || \
908 CHIP_IS_57811_MF(sc) || \
909 CHIP_IS_57811_VF(sc) || \
910 CHIP_IS_57840(sc) || \
911 CHIP_IS_57840_MF(sc) || \
912 CHIP_IS_57840_VF(sc))
913 #define CHIP_IS_E3A0(sc) (CHIP_IS_E3(sc) && \
914 (CHIP_REV(sc) == CHIP_REV_Ax))
915 #define CHIP_IS_E3B0(sc) (CHIP_IS_E3(sc) && \
916 (CHIP_REV(sc) == CHIP_REV_Bx))
918 #define USES_WARPCORE(sc) (CHIP_IS_E3(sc))
919 #define CHIP_IS_E2E3(sc) (CHIP_IS_E2(sc) || \
922 #define CHIP_IS_MF_CAP(sc) (CHIP_IS_57711E(sc) || \
923 CHIP_IS_57712_MF(sc) || \
926 #define IS_VF(sc) ((sc)->flags & BNX2X_IS_VF_FLAG)
927 #define IS_PF(sc) (!IS_VF(sc))
930 * This define is used in two main places:
931 * 1. In the early stages of nic_load, to know if to configure Parser/Searcher
932 * to nic-only mode or to offload mode. Offload mode is configured if either
933 * the chip is E1x (where NIC_MODE register is not applicable), or if cnic
934 * already registered for this port (which means that the user wants storage
936 * 2. During cnic-related load, to know if offload mode is already configured
937 * in the HW or needs to be configrued. Since the transition from nic-mode to
938 * offload-mode in HW causes traffic coruption, nic-mode is configured only
939 * in ports on which storage services where never requested.
941 #define CONFIGURE_NIC_MODE(sc) (!CHIP_IS_E1x(sc) && !CNIC_ENABLED(sc))
943 uint8_t chip_port_mode;
944 #define CHIP_4_PORT_MODE 0x0
945 #define CHIP_2_PORT_MODE 0x1
946 #define CHIP_PORT_MODE_NONE 0x2
947 #define CHIP_PORT_MODE(sc) ((sc)->devinfo.chip_port_mode)
948 #define CHIP_IS_MODE_4_PORT(sc) (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE)
951 #define INT_BLOCK_HC 0
952 #define INT_BLOCK_IGU 1
953 #define INT_BLOCK_MODE_NORMAL 0
954 #define INT_BLOCK_MODE_BW_COMP 2
955 #define CHIP_INT_MODE_IS_NBC(sc) \
956 (!CHIP_IS_E1x(sc) && \
957 !((sc)->devinfo.int_block & INT_BLOCK_MODE_BW_COMP))
958 #define CHIP_INT_MODE_IS_BC(sc) (!CHIP_INT_MODE_IS_NBC(sc))
961 uint32_t shmem2_base;
964 uint32_t mf_cfg_base; /* bootcode shmem address in BAR memory */
965 struct bnx2x_mf_info mf_info;
968 #define NVRAM_1MB_SIZE 0x20000
969 #define NVRAM_TIMEOUT_COUNT 30000
970 #define NVRAM_PAGE_SIZE 256
972 /* PCIe capability information */
973 uint32_t pcie_cap_flags;
974 #define BNX2X_PM_CAPABLE_FLAG 0x00000001
975 #define BNX2X_PCIE_CAPABLE_FLAG 0x00000002
976 #define BNX2X_MSI_CAPABLE_FLAG 0x00000004
977 #define BNX2X_MSIX_CAPABLE_FLAG 0x00000008
978 uint16_t pcie_pm_cap_reg;
979 uint16_t pcie_link_width;
980 uint16_t pcie_link_speed;
981 uint16_t pcie_msi_cap_reg;
982 uint16_t pcie_msix_cap_reg;
984 /* device configuration read from bootcode shared memory */
987 }; /* struct bnx2x_devinfo */
989 struct bnx2x_sp_objs {
990 struct ecore_vlan_mac_obj mac_obj; /* MACs object */
991 struct ecore_queue_sp_obj q_obj; /* Queue State object */
992 }; /* struct bnx2x_sp_objs */
995 * Data that will be used to create a link report message. We will keep the
996 * data used for the last link report in order to prevent reporting the same
997 * link parameters twice.
999 struct bnx2x_link_report_data {
1000 uint16_t line_speed; /* Effective line speed */
1001 unsigned long link_report_flags; /* BNX2X_LINK_REPORT_XXX flags */
1005 BNX2X_LINK_REPORT_FULL_DUPLEX,
1006 BNX2X_LINK_REPORT_LINK_DOWN,
1007 BNX2X_LINK_REPORT_RX_FC_ON,
1008 BNX2X_LINK_REPORT_TX_FC_ON
1011 #define BNX2X_RX_CHAIN_PAGE_SZ BNX2X_PAGE_SIZE
1013 struct bnx2x_pci_cap {
1014 struct bnx2x_pci_cap *next;
1024 /* Top level device private data structure. */
1025 struct bnx2x_softc {
1029 uint32_t max_tx_queues;
1030 uint32_t max_rx_queues;
1031 const struct rte_pci_device *pci_dev;
1033 struct bnx2x_pci_cap *pci_caps;
1034 #define BNX2X_INTRS_POLL_PERIOD 1
1039 /* MAC address operations */
1040 struct bnx2x_mac_ops mac_ops;
1042 /* structures for VF mbox/response/bulletin */
1043 struct bnx2x_vf_mbx_msg *vf2pf_mbox;
1044 struct bnx2x_dma vf2pf_mbox_mapping;
1045 struct vf_acquire_resp_tlv acquire_resp;
1046 struct bnx2x_vf_bulletin *pf2vf_bulletin;
1047 struct bnx2x_dma pf2vf_bulletin_mapping;
1048 struct bnx2x_vf_bulletin old_bulletin;
1049 rte_spinlock_t vf2pf_lock;
1053 int state; /* device state */
1054 #define BNX2X_STATE_CLOSED 0x0000
1055 #define BNX2X_STATE_OPENING_WAITING_LOAD 0x1000
1056 #define BNX2X_STATE_OPENING_WAITING_PORT 0x2000
1057 #define BNX2X_STATE_OPEN 0x3000
1058 #define BNX2X_STATE_CLOSING_WAITING_HALT 0x4000
1059 #define BNX2X_STATE_CLOSING_WAITING_DELETE 0x5000
1060 #define BNX2X_STATE_CLOSING_WAITING_UNLOAD 0x6000
1061 #define BNX2X_STATE_DISABLED 0xD000
1062 #define BNX2X_STATE_DIAG 0xE000
1063 #define BNX2X_STATE_ERROR 0xF000
1066 #define BNX2X_ONE_PORT_FLAG 0x1
1067 #define BNX2X_NO_FCOE_FLAG 0x2
1068 #define BNX2X_NO_WOL_FLAG 0x4
1069 #define BNX2X_NO_MCP_FLAG 0x8
1070 #define BNX2X_NO_ISCSI_OOO_FLAG 0x10
1071 #define BNX2X_NO_ISCSI_FLAG 0x20
1072 #define BNX2X_MF_FUNC_DIS 0x40
1073 #define BNX2X_TX_SWITCHING 0x80
1074 #define BNX2X_IS_VF_FLAG 0x100
1076 #define BNX2X_ONE_PORT(sc) (sc->flags & BNX2X_ONE_PORT_FLAG)
1077 #define BNX2X_NOFCOE(sc) (sc->flags & BNX2X_NO_FCOE_FLAG)
1078 #define BNX2X_NOMCP(sc) (sc->flags & BNX2X_NO_MCP_FLAG)
1081 struct bnx2x_bar bar[MAX_BARS]; /* map BARs 0, 2, 4 */
1083 uint16_t doorbell_size;
1085 /* periodic timer callout */
1086 #define PERIODIC_STOP 0
1087 #define PERIODIC_GO 1
1088 volatile unsigned long periodic_flags;
1089 rte_atomic32_t scan_fp;
1090 struct bnx2x_fastpath fp[MAX_RSS_CHAINS];
1091 struct bnx2x_sp_objs sp_objs[MAX_RSS_CHAINS];
1093 uint8_t unit; /* driver instance number */
1095 int pcie_bus; /* PCIe bus number */
1096 int pcie_device; /* PCIe device/slot number */
1097 int pcie_func; /* PCIe function number */
1099 uint8_t pfunc_rel; /* function relative */
1100 uint8_t pfunc_abs; /* function absolute */
1101 uint8_t path_id; /* function absolute */
1102 #define SC_PATH(sc) (sc->path_id)
1103 #define SC_PORT(sc) (sc->pfunc_rel & 1)
1104 #define SC_FUNC(sc) (sc->pfunc_rel)
1105 #define SC_ABS_FUNC(sc) (sc->pfunc_abs)
1106 #define SC_VN(sc) (sc->pfunc_rel >> 1)
1107 #define SC_L_ID(sc) (SC_VN(sc) << 2)
1108 #define PORT_ID(sc) SC_PORT(sc)
1109 #define PATH_ID(sc) SC_PATH(sc)
1110 #define VNIC_ID(sc) SC_VN(sc)
1111 #define FUNC_ID(sc) SC_FUNC(sc)
1112 #define ABS_FUNC_ID(sc) SC_ABS_FUNC(sc)
1113 #define SC_FW_MB_IDX_VN(sc, vn) \
1114 (SC_PORT(sc) + (vn) * \
1115 ((CHIP_IS_E1x(sc) || (CHIP_IS_MODE_4_PORT(sc))) ? 2 : 1))
1116 #define SC_FW_MB_IDX(sc) SC_FW_MB_IDX_VN(sc, SC_VN(sc))
1118 int if_capen; /* enabled interface capabilities */
1120 struct bnx2x_devinfo devinfo;
1121 char fw_ver_str[32];
1122 char mf_mode_str[32];
1123 char pci_link_str[32];
1125 struct iro *iro_array;
1128 #define DMAE_READY(sc) (sc->dmae_ready)
1130 struct ecore_credit_pool_obj vlans_pool;
1131 struct ecore_credit_pool_obj macs_pool;
1132 struct ecore_rx_mode_obj rx_mode_obj;
1133 struct ecore_mcast_obj mcast_obj;
1134 struct ecore_rss_config_obj rss_conf_obj;
1135 struct ecore_func_sp_obj func_obj;
1138 uint16_t fw_drv_pulse_wr_seq;
1141 struct elink_params link_params;
1142 struct elink_vars link_vars;
1144 struct bnx2x_link_report_data last_reported_link;
1145 char mac_addr_str[32];
1147 uint32_t tx_ring_size;
1148 uint32_t rx_ring_size;
1153 #define BNX2X_RECOVERY_DONE 1
1154 #define BNX2X_RECOVERY_INIT 2
1155 #define BNX2X_RECOVERY_WAIT 3
1156 #define BNX2X_RECOVERY_FAILED 4
1157 #define BNX2X_RECOVERY_NIC_LOADING 5
1160 #define BNX2X_RX_MODE_NONE 0
1161 #define BNX2X_RX_MODE_NORMAL 1
1162 #define BNX2X_RX_MODE_ALLMULTI 2
1163 #define BNX2X_RX_MODE_ALLMULTI_PROMISC 3
1164 #define BNX2X_RX_MODE_PROMISC 4
1165 #define BNX2X_MAX_MULTICAST 64
1167 struct bnx2x_port port;
1169 struct cmng_init cmng;
1177 #define INTR_MODE_INTX 0
1178 #define INTR_MODE_MSI 1
1179 #define INTR_MODE_MSIX 2
1180 #define INTR_MODE_SINGLE_MSIX 3
1184 uint8_t igu_base_sb;
1186 uint32_t igu_base_addr;
1187 uint8_t base_fw_ndsb;
1188 #define DEF_SB_IGU_ID 16
1189 #define DEF_SB_ID HC_SP_SB_ID
1191 /* default status block */
1192 struct bnx2x_dma def_sb_dma;
1193 struct host_sp_status_block *def_sb;
1195 uint16_t def_att_idx;
1196 uint32_t attn_state;
1197 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
1199 /* general SP events - stats query, cfc delete, etc */
1200 #define HC_SP_INDEX_ETH_DEF_CONS 3
1201 /* EQ completions */
1202 #define HC_SP_INDEX_EQ_CONS 7
1203 /* FCoE L2 connection completions */
1204 #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6
1205 #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4
1207 #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5
1208 #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1
1211 struct bnx2x_dma eq_dma;
1212 union event_ring_elem *eq;
1215 uint16_t *eq_cons_sb;
1216 #define NUM_EQ_PAGES 1 /* must be a power of 2 */
1217 #define EQ_DESC_CNT_PAGE (BNX2X_PAGE_SIZE / sizeof(union event_ring_elem))
1218 #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1)
1219 #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES)
1220 #define EQ_DESC_MASK (NUM_EQ_DESC - 1)
1221 #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2)
1222 /* depends on EQ_DESC_CNT_PAGE being a power of 2 */
1223 #define NEXT_EQ_IDX(x) \
1224 ((((x) & EQ_DESC_MAX_PAGE) == (EQ_DESC_MAX_PAGE - 1)) ? \
1225 ((x) + 2) : ((x) + 1))
1226 /* depends on the above and on NUM_EQ_PAGES being a power of 2 */
1227 #define EQ_DESC(x) ((x) & EQ_DESC_MASK)
1230 struct bnx2x_dma sp_dma;
1231 struct bnx2x_slowpath *sp;
1232 unsigned long sp_state;
1234 /* slow path queue */
1235 struct bnx2x_dma spq_dma;
1236 struct eth_spe *spq;
1237 #define SP_DESC_CNT (BNX2X_PAGE_SIZE / sizeof(struct eth_spe))
1238 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
1239 #define MAX_SPQ_PENDING 8
1241 uint16_t spq_prod_idx;
1242 struct eth_spe *spq_prod_bd;
1243 struct eth_spe *spq_last_bd;
1244 uint16_t *dsb_sp_prod;
1246 volatile unsigned long eq_spq_left; /* COMMON_xxx ramrod credit */
1247 volatile unsigned long cq_spq_left; /* ETH_xxx ramrod credit */
1249 /* fw decompression buffer */
1250 struct bnx2x_dma gz_buf_dma;
1253 #define GUNZIP_BUF(sc) (sc->gz_buf)
1254 #define GUNZIP_OUTLEN(sc) (sc->gz_outlen)
1255 #define GUNZIP_PHYS(sc) (rte_iova_t)(sc->gz_buf_dma.paddr)
1256 #define FW_BUF_SIZE 0x40000
1258 struct raw_op *init_ops;
1259 uint16_t *init_ops_offsets; /* init block offsets inside init_ops */
1260 uint32_t *init_data; /* data blob, 32 bit granularity */
1261 uint32_t init_mode_flags;
1262 #define INIT_MODE_FLAGS(sc) (sc->init_mode_flags)
1263 /* PRAM blobs - raw data */
1264 const uint8_t *tsem_int_table_data;
1265 const uint8_t *tsem_pram_data;
1266 const uint8_t *usem_int_table_data;
1267 const uint8_t *usem_pram_data;
1268 const uint8_t *xsem_int_table_data;
1269 const uint8_t *xsem_pram_data;
1270 const uint8_t *csem_int_table_data;
1271 const uint8_t *csem_pram_data;
1272 #define INIT_OPS(sc) (sc->init_ops)
1273 #define INIT_OPS_OFFSETS(sc) (sc->init_ops_offsets)
1274 #define INIT_DATA(sc) (sc->init_data)
1275 #define INIT_TSEM_INT_TABLE_DATA(sc) (sc->tsem_int_table_data)
1276 #define INIT_TSEM_PRAM_DATA(sc) (sc->tsem_pram_data)
1277 #define INIT_USEM_INT_TABLE_DATA(sc) (sc->usem_int_table_data)
1278 #define INIT_USEM_PRAM_DATA(sc) (sc->usem_pram_data)
1279 #define INIT_XSEM_INT_TABLE_DATA(sc) (sc->xsem_int_table_data)
1280 #define INIT_XSEM_PRAM_DATA(sc) (sc->xsem_pram_data)
1281 #define INIT_CSEM_INT_TABLE_DATA(sc) (sc->csem_int_table_data)
1282 #define INIT_CSEM_PRAM_DATA(sc) (sc->csem_pram_data)
1284 #define PHY_FW_VER_LEN 20
1288 * For max 196 cids (64*3 + non-eth), 32KB ILT page size and 1KB
1289 * context size we need 8 ILT entries.
1291 #define ILT_MAX_L2_LINES 8
1292 struct hw_context context[ILT_MAX_L2_LINES];
1293 struct ecore_ilt *ilt;
1294 #define ILT_MAX_LINES 256
1296 /* max supported number of RSS queues: IGU SBs minus one for CNIC */
1297 #define BNX2X_MAX_RSS_COUNT(sc) ((sc)->igu_sb_cnt - CNIC_SUPPORT(sc))
1298 /* max CID count: Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI */
1299 #define BNX2X_L2_MAX_CID(sc) \
1300 (BNX2X_MAX_RSS_COUNT(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc))
1301 #define BNX2X_L2_CID_COUNT(sc) \
1302 (BNX2X_NUM_ETH_QUEUES(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc))
1303 #define L2_ILT_LINES(sc) \
1304 (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(sc), ILT_PAGE_CIDS))
1308 uint8_t dropless_fc;
1310 /* total number of FW statistics requests */
1311 uint8_t fw_stats_num;
1313 * This is a memory buffer that will contain both statistics ramrod
1316 struct bnx2x_dma fw_stats_dma;
1318 * FW statistics request shortcut (points at the beginning of fw_stats
1321 int fw_stats_req_size;
1322 struct bnx2x_fw_stats_req *fw_stats_req;
1323 rte_iova_t fw_stats_req_mapping;
1325 * FW statistics data shortcut (points at the beginning of fw_stats
1326 * buffer + fw_stats_req_size).
1328 int fw_stats_data_size;
1329 struct bnx2x_fw_stats_data *fw_stats_data;
1330 rte_iova_t fw_stats_data_mapping;
1332 /* tracking a pending STAT_QUERY ramrod */
1333 uint16_t stats_pending;
1334 /* number of completed statistics ramrods */
1335 uint16_t stats_comp;
1336 uint16_t stats_counter;
1340 struct bnx2x_eth_stats eth_stats;
1341 struct host_func_stats func_stats;
1342 struct bnx2x_eth_stats_old eth_stats_old;
1343 struct bnx2x_net_stats_old net_stats_old;
1344 struct bnx2x_fw_port_stats_old fw_stats_old;
1346 struct dmae_command stats_dmae; /* used by dmae command loader */
1351 /* DCB support on/off */
1353 #define BNX2X_DCB_STATE_OFF 0
1354 #define BNX2X_DCB_STATE_ON 1
1355 /* DCBX engine mode */
1357 #define BNX2X_DCBX_ENABLED_OFF 0
1358 #define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1
1359 #define BNX2X_DCBX_ENABLED_ON_NEG_ON 2
1360 #define BNX2X_DCBX_ENABLED_INVALID -1
1362 uint8_t cnic_support;
1363 uint8_t cnic_enabled;
1364 uint8_t cnic_loaded;
1365 #define CNIC_SUPPORT(sc) 0 /* ((sc)->cnic_support) */
1366 #define CNIC_ENABLED(sc) 0 /* ((sc)->cnic_enabled) */
1367 #define CNIC_LOADED(sc) 0 /* ((sc)->cnic_loaded) */
1369 /* multiple tx classes of service */
1371 #define BNX2X_MAX_PRIORITY 8
1372 /* priority to cos mapping */
1373 uint8_t prio_to_cos[BNX2X_MAX_PRIORITY];
1376 }; /* struct bnx2x_softc */
1378 /* IOCTL sub-commands for edebug and firmware upgrade */
1379 #define BNX2X_IOC_RD_NVRAM 1
1380 #define BNX2X_IOC_WR_NVRAM 2
1381 #define BNX2X_IOC_STATS_SHOW_NUM 3
1382 #define BNX2X_IOC_STATS_SHOW_STR 4
1383 #define BNX2X_IOC_STATS_SHOW_CNT 5
1385 struct bnx2x_nvram_data {
1386 uint32_t op; /* ioctl sub-command */
1389 uint32_t value[1]; /* variable */
1392 union bnx2x_stats_show_data {
1393 uint32_t op; /* ioctl sub-command */
1396 uint32_t num; /* return number of stats */
1397 uint32_t len; /* length of each string item */
1400 /* variable length... */
1401 char str[1]; /* holds names of desc.num stats, each desc.len in length */
1403 /* variable length... */
1404 uint64_t stats[1]; /* holds all stats */
1407 /* function init flags */
1408 #define FUNC_FLG_RSS 0x0001
1409 #define FUNC_FLG_STATS 0x0002
1410 /* FUNC_FLG_UNMATCHED 0x0004 */
1411 #define FUNC_FLG_SPQ 0x0010
1412 #define FUNC_FLG_LEADING 0x0020 /* PF only */
1414 struct bnx2x_func_init_params {
1415 rte_iova_t fw_stat_map; /* (dma) valid if FUNC_FLG_STATS */
1416 rte_iova_t spq_map; /* (dma) valid if FUNC_FLG_SPQ */
1418 uint16_t func_id; /* abs function id */
1420 uint16_t spq_prod; /* valid if FUNC_FLG_SPQ */
1423 /* memory resources reside at BARs 0, 2, 4 */
1424 /* Run `pciconf -lb` to see mappings */
1430 bnx2x_reg_write8(struct bnx2x_softc *sc, size_t offset, uint8_t val)
1432 PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "offset=0x%08lx val=0x%02x",
1433 (unsigned long)offset, val);
1434 rte_write8(val, ((uint8_t *)sc->bar[BAR0].base_addr + offset));
1438 bnx2x_reg_write16(struct bnx2x_softc *sc, size_t offset, uint16_t val)
1440 #ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
1441 if ((offset % 2) != 0)
1442 PMD_DRV_LOG(NOTICE, sc, "Unaligned 16-bit write to 0x%08lx",
1443 (unsigned long)offset);
1445 PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "offset=0x%08lx val=0x%04x",
1446 (unsigned long)offset, val);
1447 rte_write16(val, ((uint8_t *)sc->bar[BAR0].base_addr + offset));
1452 bnx2x_reg_write32(struct bnx2x_softc *sc, size_t offset, uint32_t val)
1454 #ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
1455 if ((offset % 4) != 0)
1456 PMD_DRV_LOG(NOTICE, sc, "Unaligned 32-bit write to 0x%08lx",
1457 (unsigned long)offset);
1460 PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "offset=0x%08lx val=0x%08x",
1461 (unsigned long)offset, val);
1462 rte_write32(val, ((uint8_t *)sc->bar[BAR0].base_addr + offset));
1465 static inline uint8_t
1466 bnx2x_reg_read8(struct bnx2x_softc *sc, size_t offset)
1470 val = rte_read8((uint8_t *)sc->bar[BAR0].base_addr + offset);
1471 PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "offset=0x%08lx val=0x%02x",
1472 (unsigned long)offset, val);
1477 static inline uint16_t
1478 bnx2x_reg_read16(struct bnx2x_softc *sc, size_t offset)
1482 #ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
1483 if ((offset % 2) != 0)
1484 PMD_DRV_LOG(NOTICE, sc, "Unaligned 16-bit read from 0x%08lx",
1485 (unsigned long)offset);
1488 val = rte_read16(((uint8_t *)sc->bar[BAR0].base_addr + offset));
1489 PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "offset=0x%08lx val=0x%08x",
1490 (unsigned long)offset, val);
1495 static inline uint32_t
1496 bnx2x_reg_read32(struct bnx2x_softc *sc, size_t offset)
1500 #ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
1501 if ((offset % 4) != 0)
1502 PMD_DRV_LOG(NOTICE, sc, "Unaligned 32-bit read from 0x%08lx",
1503 (unsigned long)offset);
1506 val = rte_read32(((uint8_t *)sc->bar[BAR0].base_addr + offset));
1507 PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "offset=0x%08lx val=0x%08x",
1508 (unsigned long)offset, val);
1513 #define REG_ADDR(sc, offset) (((uint64_t)sc->bar[BAR0].base_addr) + (offset))
1515 #define REG_RD8(sc, offset) bnx2x_reg_read8(sc, (offset))
1516 #define REG_RD16(sc, offset) bnx2x_reg_read16(sc, (offset))
1517 #define REG_RD32(sc, offset) bnx2x_reg_read32(sc, (offset))
1519 #define REG_WR8(sc, offset, val) bnx2x_reg_write8(sc, (offset), val)
1520 #define REG_WR16(sc, offset, val) bnx2x_reg_write16(sc, (offset), val)
1521 #define REG_WR32(sc, offset, val) bnx2x_reg_write32(sc, (offset), val)
1523 #define REG_RD(sc, offset) REG_RD32(sc, offset)
1524 #define REG_WR(sc, offset, val) REG_WR32(sc, offset, val)
1526 #define BNX2X_SP(sc, var) (&(sc)->sp->var)
1527 #define BNX2X_SP_MAPPING(sc, var) \
1528 (sc->sp_dma.paddr + offsetof(struct bnx2x_slowpath, var))
1530 #define BNX2X_FP(sc, nr, var) ((sc)->fp[(nr)].var)
1531 #define BNX2X_SP_OBJ(sc, fp) ((sc)->sp_objs[(fp)->index])
1533 #define bnx2x_fp(sc, nr, var) ((sc)->fp[nr].var)
1535 #define REG_RD_DMAE(sc, offset, valp, len32) \
1537 (void)bnx2x_read_dmae(sc, offset, len32); \
1538 rte_memcpy(valp, BNX2X_SP(sc, wb_data[0]), (len32) * 4); \
1541 #define REG_WR_DMAE(sc, offset, valp, len32) \
1543 rte_memcpy(BNX2X_SP(sc, wb_data[0]), valp, (len32) * 4); \
1544 (void)bnx2x_write_dmae(sc, BNX2X_SP_MAPPING(sc, wb_data), offset, len32); \
1547 #define REG_WR_DMAE_LEN(sc, offset, valp, len32) \
1548 REG_WR_DMAE(sc, offset, valp, len32)
1550 #define REG_RD_DMAE_LEN(sc, offset, valp, len32) \
1551 REG_RD_DMAE(sc, offset, valp, len32)
1553 #define VIRT_WR_DMAE_LEN(sc, data, addr, len32, le32_swap) \
1555 /* if (le32_swap) { */ \
1556 /* PMD_PWARN_LOG(sc, "VIRT_WR_DMAE_LEN with le32_swap=1"); */ \
1558 rte_memcpy(GUNZIP_BUF(sc), data, len32 * 4); \
1559 ecore_write_big_buf_wb(sc, addr, len32); \
1562 #define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */
1563 #define BNX2X_DB_SHIFT 7 /* 128 bytes */
1564 #if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT)
1565 #error "Minimum DB doorbell stride is 8"
1567 #define DPM_TRIGGER_TYPE 0x40
1569 /* Doorbell macro */
1570 #define BNX2X_DB_WRITE(db_bar, val) rte_write32_relaxed((val), (db_bar))
1572 #define BNX2X_DB_READ(db_bar) rte_read32_relaxed(db_bar)
1574 #define DOORBELL_ADDR(sc, offset) \
1575 (volatile uint32_t *)(((char *)(sc)->bar[BAR1].base_addr + (offset)))
1577 #define DOORBELL(sc, cid, val) \
1579 BNX2X_DB_WRITE((DOORBELL_ADDR(sc, sc->doorbell_size * (cid) + DPM_TRIGGER_TYPE)), (val)); \
1581 BNX2X_DB_WRITE((DOORBELL_ADDR(sc, sc->doorbell_size * (cid))), (val)) \
1583 #define SHMEM_ADDR(sc, field) \
1584 (sc->devinfo.shmem_base + offsetof(struct shmem_region, field))
1585 #define SHMEM_RD(sc, field) REG_RD(sc, SHMEM_ADDR(sc, field))
1586 #define SHMEM_RD16(sc, field) REG_RD16(sc, SHMEM_ADDR(sc, field))
1587 #define SHMEM_WR(sc, field, val) REG_WR(sc, SHMEM_ADDR(sc, field), val)
1589 #define SHMEM2_ADDR(sc, field) \
1590 (sc->devinfo.shmem2_base + offsetof(struct shmem2_region, field))
1591 #define SHMEM2_HAS(sc, field) \
1592 (sc->devinfo.shmem2_base && (REG_RD(sc, SHMEM2_ADDR(sc, size)) > \
1593 offsetof(struct shmem2_region, field)))
1594 #define SHMEM2_RD(sc, field) REG_RD(sc, SHMEM2_ADDR(sc, field))
1595 #define SHMEM2_WR(sc, field, val) REG_WR(sc, SHMEM2_ADDR(sc, field), val)
1597 #define MFCFG_ADDR(sc, field) \
1598 (sc->devinfo.mf_cfg_base + offsetof(struct mf_cfg, field))
1599 #define MFCFG_RD(sc, field) REG_RD(sc, MFCFG_ADDR(sc, field))
1600 #define MFCFG_RD16(sc, field) REG_RD16(sc, MFCFG_ADDR(sc, field))
1601 #define MFCFG_WR(sc, field, val) REG_WR(sc, MFCFG_ADDR(sc, field), val)
1603 /* DMAE command defines */
1605 #define DMAE_TIMEOUT -1
1606 #define DMAE_PCI_ERROR -2 /* E2 and onward */
1607 #define DMAE_NOT_RDY -3
1608 #define DMAE_PCI_ERR_FLAG 0x80000000
1610 #define DMAE_SRC_PCI 0
1611 #define DMAE_SRC_GRC 1
1613 #define DMAE_DST_NONE 0
1614 #define DMAE_DST_PCI 1
1615 #define DMAE_DST_GRC 2
1617 #define DMAE_COMP_PCI 0
1618 #define DMAE_COMP_GRC 1
1620 #define DMAE_COMP_REGULAR 0
1621 #define DMAE_COM_SET_ERR 1
1623 #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << DMAE_COMMAND_SRC_SHIFT)
1624 #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << DMAE_COMMAND_SRC_SHIFT)
1625 #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << DMAE_COMMAND_DST_SHIFT)
1626 #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << DMAE_COMMAND_DST_SHIFT)
1628 #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << DMAE_COMMAND_C_DST_SHIFT)
1629 #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << DMAE_COMMAND_C_DST_SHIFT)
1631 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
1632 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
1633 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
1634 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
1636 #define DMAE_CMD_PORT_0 0
1637 #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
1639 #define DMAE_SRC_PF 0
1640 #define DMAE_SRC_VF 1
1642 #define DMAE_DST_PF 0
1643 #define DMAE_DST_VF 1
1645 #define DMAE_C_SRC 0
1646 #define DMAE_C_DST 1
1648 #define DMAE_LEN32_RD_MAX 0x80
1649 #define DMAE_LEN32_WR_MAX(sc) 0x2000
1651 #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and beyond, upper bit indicates error */
1653 #define MAX_DMAE_C_PER_PORT 8
1654 #define INIT_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + SC_VN(sc))
1655 #define PMF_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + E1HVN_MAX)
1657 static const uint32_t dmae_reg_go_c[] = {
1658 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
1659 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
1660 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
1661 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
1664 #define ATTN_NIG_FOR_FUNC (1L << 8)
1665 #define ATTN_SW_TIMER_4_FUNC (1L << 9)
1666 #define GPIO_2_FUNC (1L << 10)
1667 #define GPIO_3_FUNC (1L << 11)
1668 #define GPIO_4_FUNC (1L << 12)
1669 #define ATTN_GENERAL_ATTN_1 (1L << 13)
1670 #define ATTN_GENERAL_ATTN_2 (1L << 14)
1671 #define ATTN_GENERAL_ATTN_3 (1L << 15)
1672 #define ATTN_GENERAL_ATTN_4 (1L << 13)
1673 #define ATTN_GENERAL_ATTN_5 (1L << 14)
1674 #define ATTN_GENERAL_ATTN_6 (1L << 15)
1675 #define ATTN_HARD_WIRED_MASK 0xff00
1676 #define ATTENTION_ID 4
1678 #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \
1679 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
1681 #define MAX_IGU_ATTN_ACK_TO 100
1683 #define STORM_ASSERT_ARRAY_SIZE 50
1685 #define BNX2X_PMF_LINK_ASSERT(sc) \
1686 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + SC_FUNC(sc))
1688 #define BNX2X_MC_ASSERT_BITS \
1689 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1690 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1691 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1692 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
1694 #define BNX2X_MCP_ASSERT \
1695 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
1697 #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
1698 #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
1699 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
1700 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
1701 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
1702 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
1703 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
1705 #define HW_INTERRUT_ASSERT_SET_0 \
1706 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
1707 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
1708 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
1709 AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT | \
1710 AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT)
1711 #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
1712 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
1713 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
1714 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
1715 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\
1716 AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\
1717 AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR)
1718 #define HW_INTERRUT_ASSERT_SET_1 \
1719 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
1720 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
1721 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
1722 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
1723 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
1724 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
1725 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
1726 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
1727 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
1728 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
1729 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
1730 #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\
1731 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
1732 AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\
1733 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
1734 AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\
1735 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
1736 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
1737 AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\
1738 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
1739 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
1740 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
1741 AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\
1742 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
1743 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
1744 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\
1745 AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR)
1746 #define HW_INTERRUT_ASSERT_SET_2 \
1747 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
1748 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
1749 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
1750 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
1751 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
1752 #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
1753 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
1754 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
1755 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
1756 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
1757 AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\
1758 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
1759 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
1761 #define HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD \
1762 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
1763 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
1764 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY)
1766 #define HW_PRTY_ASSERT_SET_3 (HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD | \
1767 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
1769 #define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \
1770 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)
1772 #define MULTI_MASK 0x7f
1774 #define PFS_PER_PORT(sc) \
1775 ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4)
1776 #define SC_MAX_VN_NUM(sc) PFS_PER_PORT(sc)
1778 #define FIRST_ABS_FUNC_IN_PORT(sc) \
1779 ((CHIP_PORT_MODE(sc) == CHIP_PORT_MODE_NONE) ? \
1780 PORT_ID(sc) : (PATH_ID(sc) + (2 * PORT_ID(sc))))
1782 #define FOREACH_ABS_FUNC_IN_PORT(sc, i) \
1783 for ((i) = FIRST_ABS_FUNC_IN_PORT(sc); \
1784 (i) < MAX_FUNC_NUM; \
1785 (i) += (MAX_FUNC_NUM / PFS_PER_PORT(sc)))
1787 #define BNX2X_SWCID_SHIFT 17
1788 #define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1)
1790 #define SW_CID(x) (le32toh(x) & BNX2X_SWCID_MASK)
1791 #define CQE_CMD(x) (le32toh(x) >> COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
1793 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
1794 #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG)
1795 #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG)
1796 #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD)
1797 #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH)
1799 /* must be used on a CID before placing it on a HW ring */
1800 #define HW_CID(sc, x) \
1801 ((SC_PORT(sc) << 23) | (SC_VN(sc) << BNX2X_SWCID_SHIFT) | (x))
1804 #define SPEED_100 100
1805 #define SPEED_1000 1000
1806 #define SPEED_2500 2500
1807 #define SPEED_10000 10000
1810 #define PCI_PM_D3hot 2
1812 int bnx2x_test_bit(int nr, volatile unsigned long * addr);
1813 void bnx2x_set_bit(unsigned int nr, volatile unsigned long * addr);
1814 void bnx2x_clear_bit(int nr, volatile unsigned long * addr);
1815 int bnx2x_test_and_clear_bit(int nr, volatile unsigned long * addr);
1816 int bnx2x_cmpxchg(volatile int *addr, int old, int new);
1818 int bnx2x_dma_alloc(struct bnx2x_softc *sc, size_t size,
1819 struct bnx2x_dma *dma, const char *msg, uint32_t align);
1820 void bnx2x_dma_free(struct bnx2x_dma *dma);
1821 uint32_t bnx2x_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type);
1822 uint32_t bnx2x_dmae_opcode_clr_src_reset(uint32_t opcode);
1823 uint32_t bnx2x_dmae_opcode(struct bnx2x_softc *sc, uint8_t src_type,
1824 uint8_t dst_type, uint8_t with_comp,
1826 void bnx2x_post_dmae(struct bnx2x_softc *sc, struct dmae_command *dmae, int idx);
1827 void bnx2x_read_dmae(struct bnx2x_softc *sc, uint32_t src_addr, uint32_t len32);
1828 void bnx2x_write_dmae(struct bnx2x_softc *sc, rte_iova_t dma_addr,
1829 uint32_t dst_addr, uint32_t len32);
1830 void bnx2x_set_ctx_validation(struct bnx2x_softc *sc, struct eth_context *cxt,
1832 void bnx2x_update_coalesce_sb_index(struct bnx2x_softc *sc, uint8_t fw_sb_id,
1833 uint8_t sb_index, uint8_t disable,
1836 int bnx2x_sp_post(struct bnx2x_softc *sc, int command, int cid,
1837 uint32_t data_hi, uint32_t data_lo, int cmd_type);
1839 void ecore_init_e1h_firmware(struct bnx2x_softc *sc);
1840 void ecore_init_e2_firmware(struct bnx2x_softc *sc);
1842 void ecore_storm_memset_struct(struct bnx2x_softc *sc, uint32_t addr,
1843 size_t size, uint32_t *data);
1845 #define CATC_TRIGGER(sc, data) REG_WR((sc), 0x2000, (data));
1846 #define CATC_TRIGGER_START(sc) CATC_TRIGGER((sc), 0xcafecafe)
1848 #define BNX2X_MAC_FMT "%pM"
1849 #define BNX2X_MAC_PRN_LIST(mac) (mac)
1855 static inline uint32_t
1856 reg_poll(struct bnx2x_softc *sc, uint32_t reg, uint32_t expected, int ms, int wait)
1860 val = REG_RD(sc, reg);
1861 if (val == expected) {
1872 bnx2x_update_fp_sb_idx(struct bnx2x_fastpath *fp)
1874 mb(); /* status block is written to by the chip */
1875 fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID];
1879 bnx2x_igu_ack_sb_gen(struct bnx2x_softc *sc, uint8_t segment,
1880 uint16_t index, uint8_t op, uint8_t update, uint32_t igu_addr)
1882 struct igu_regular cmd_data = {0};
1884 cmd_data.sb_id_and_flags =
1885 ((index << IGU_REGULAR_SB_INDEX_SHIFT) |
1886 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
1887 (update << IGU_REGULAR_BUPDATE_SHIFT) |
1888 (op << IGU_REGULAR_ENABLE_INT_SHIFT));
1890 REG_WR(sc, igu_addr, cmd_data.sb_id_and_flags);
1892 /* Make sure that ACK is written */
1897 bnx2x_hc_ack_sb(struct bnx2x_softc *sc, uint8_t sb_id, uint8_t storm,
1898 uint16_t index, uint8_t op, uint8_t update)
1900 uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc) * 32 +
1901 COMMAND_REG_INT_ACK);
1902 struct igu_ack_register igu_ack;
1903 uint32_t *val = NULL;
1905 igu_ack.status_block_index = index;
1906 igu_ack.sb_id_and_flags =
1907 ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
1908 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
1909 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
1910 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
1912 val = (uint32_t *)&igu_ack;
1913 REG_WR(sc, hc_addr, *val);
1915 /* Make sure that ACK is written */
1919 static inline uint32_t
1920 bnx2x_hc_ack_int(struct bnx2x_softc *sc)
1922 uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc) * 32 +
1923 COMMAND_REG_SIMD_MASK);
1924 uint32_t result = REG_RD(sc, hc_addr);
1930 static inline uint32_t
1931 bnx2x_igu_ack_int(struct bnx2x_softc *sc)
1933 uint32_t igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER * 8);
1934 uint32_t result = REG_RD(sc, igu_addr);
1936 /* PMD_PDEBUG_LOG(sc, DBG_INTR, "read 0x%08x from IGU addr 0x%x",
1937 result, igu_addr); */
1943 static inline uint32_t
1944 bnx2x_ack_int(struct bnx2x_softc *sc)
1947 if (sc->devinfo.int_block == INT_BLOCK_HC) {
1948 return bnx2x_hc_ack_int(sc);
1950 return bnx2x_igu_ack_int(sc);
1955 func_by_vn(struct bnx2x_softc *sc, int vn)
1957 return 2 * vn + SC_PORT(sc);
1961 * send notification to other functions.
1964 bnx2x_link_sync_notify(struct bnx2x_softc *sc)
1968 /* Set the attention towards other drivers on the same port */
1969 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
1970 if (vn == SC_VN(sc))
1973 func = func_by_vn(sc, vn);
1974 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_0 +
1975 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func) * 4, 1);
1980 * Statistics ID are global per chip/path, while Client IDs for E1x
1983 static inline uint8_t
1984 bnx2x_stats_id(struct bnx2x_fastpath *fp)
1986 struct bnx2x_softc *sc = fp->sc;
1988 if (!CHIP_IS_E1x(sc)) {
1992 return fp->cl_id + SC_PORT(sc) * FP_SB_MAX_E1x;
1995 int bnx2x_init(struct bnx2x_softc *sc);
1996 void bnx2x_load_firmware(struct bnx2x_softc *sc);
1997 int bnx2x_attach(struct bnx2x_softc *sc);
1998 int bnx2x_nic_unload(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link);
1999 int bnx2x_alloc_hsi_mem(struct bnx2x_softc *sc);
2000 int bnx2x_alloc_ilt_mem(struct bnx2x_softc *sc);
2001 void bnx2x_free_ilt_mem(struct bnx2x_softc *sc);
2002 void bnx2x_dump_tx_chain(struct bnx2x_fastpath * fp, int bd_prod, int count);
2003 int bnx2x_tx_encap(struct bnx2x_tx_queue *txq, struct rte_mbuf *m0);
2004 uint8_t bnx2x_txeof(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp);
2005 void bnx2x_print_adapter_info(struct bnx2x_softc *sc);
2006 void bnx2x_print_device_info(struct bnx2x_softc *sc);
2007 int bnx2x_intr_legacy(struct bnx2x_softc *sc);
2008 void bnx2x_link_status_update(struct bnx2x_softc *sc);
2009 int bnx2x_complete_sp(struct bnx2x_softc *sc);
2010 int bnx2x_set_storm_rx_mode(struct bnx2x_softc *sc);
2011 void bnx2x_periodic_callout(struct bnx2x_softc *sc);
2012 void bnx2x_periodic_stop(void *param);
2014 int bnx2x_vf_get_resources(struct bnx2x_softc *sc, uint8_t tx_count, uint8_t rx_count);
2015 void bnx2x_vf_close(struct bnx2x_softc *sc);
2016 int bnx2x_vf_init(struct bnx2x_softc *sc);
2017 void bnx2x_vf_unload(struct bnx2x_softc *sc);
2018 int bnx2x_vf_setup_queue(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
2020 void bnx2x_free_hsi_mem(struct bnx2x_softc *sc);
2021 int bnx2x_vf_set_rx_mode(struct bnx2x_softc *sc);
2022 int bnx2x_check_bull(struct bnx2x_softc *sc);
2024 //#define BNX2X_PULSE
2026 #define BNX2X_PCI_CAP 1
2027 #define BNX2X_PCI_ECAP 2
2029 static inline struct bnx2x_pci_cap*
2030 pci_find_cap(struct bnx2x_softc *sc, uint8_t id, uint8_t type)
2032 struct bnx2x_pci_cap *cap = sc->pci_caps;
2035 if (cap->id == id && cap->type == type)
2044 bnx2x_set_rx_mode(struct bnx2x_softc *sc)
2046 if (sc->state == BNX2X_STATE_OPEN) {
2048 bnx2x_set_storm_rx_mode(sc);
2050 sc->rx_mode = BNX2X_RX_MODE_PROMISC;
2051 bnx2x_vf_set_rx_mode(sc);
2054 PMD_DRV_LOG(INFO, sc, "Card is not ready to change mode");
2058 static inline int pci_read(struct bnx2x_softc *sc, size_t addr,
2059 void *val, uint8_t size)
2061 if (rte_pci_read_config(sc->pci_dev, val, size, addr) <= 0) {
2062 PMD_DRV_LOG(ERR, sc, "Can't read from PCI config space");
2069 static inline int pci_write_word(struct bnx2x_softc *sc, size_t addr, off_t val)
2071 uint16_t val16 = val;
2073 if (rte_pci_write_config(sc->pci_dev, &val16,
2074 sizeof(val16), addr) <= 0) {
2075 PMD_DRV_LOG(ERR, sc, "Can't write to PCI config space");
2082 static inline int pci_write_long(struct bnx2x_softc *sc, size_t addr, off_t val)
2084 uint32_t val32 = val;
2085 if (rte_pci_write_config(sc->pci_dev, &val32,
2086 sizeof(val32), addr) <= 0) {
2087 PMD_DRV_LOG(ERR, sc, "Can't write to PCI config space");
2094 #endif /* __BNX2X_H__ */