2 * Copyright (c) 2007-2013 Broadcom Corporation.
4 * Eric Davis <edavis@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
6 * Gary Zambrano <zambrano@broadcom.com>
8 * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
9 * Copyright (c) 2015 QLogic Corporation.
10 * All rights reserved.
13 * See LICENSE.bnx2x_pmd for copyright and licensing details.
19 #include <rte_byteorder.h>
21 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
22 #ifndef __LITTLE_ENDIAN
23 #define __LITTLE_ENDIAN RTE_LITTLE_ENDIAN
26 #elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN
28 #define __BIG_ENDIAN RTE_BIG_ENDIAN
30 #undef __LITTLE_ENDIAN
33 #include "bnx2x_ethdev.h"
34 #include "ecore_mfw_req.h"
35 #include "ecore_fw_defs.h"
36 #include "ecore_hsi.h"
37 #include "ecore_reg.h"
38 #include "bnx2x_stats.h"
39 #include "bnx2x_vfpf.h"
44 #include <linux/pci_regs.h>
46 #define PCIY_PMG PCI_CAP_ID_PM
47 #define PCIY_MSI PCI_CAP_ID_MSI
48 #define PCIY_EXPRESS PCI_CAP_ID_EXP
49 #define PCIY_MSIX PCI_CAP_ID_MSIX
50 #define PCIR_EXPRESS_DEVICE_STA PCI_EXP_TYPE_RC_EC
51 #define PCIM_EXP_STA_TRANSACTION_PND PCI_EXP_DEVSTA_TRPND
52 #define PCIR_EXPRESS_LINK_STA PCI_EXP_LNKSTA
53 #define PCIM_LINK_STA_WIDTH PCI_EXP_LNKSTA_NLW
54 #define PCIM_LINK_STA_SPEED PCI_EXP_LNKSTA_CLS
55 #define PCIR_EXPRESS_DEVICE_CTL PCI_EXP_DEVCTL
56 #define PCIM_EXP_CTL_MAX_PAYLOAD PCI_EXP_DEVCTL_PAYLOAD
57 #define PCIM_EXP_CTL_MAX_READ_REQUEST PCI_EXP_DEVCTL_READRQ
58 #define PCIR_POWER_STATUS PCI_PM_CTRL
59 #define PCIM_PSTAT_DMASK PCI_PM_CTRL_STATE_MASK
60 #define PCIM_PSTAT_PME PCI_PM_CTRL_PME_STATUS
61 #define PCIM_PSTAT_D3 0x3
62 #define PCIM_PSTAT_PMEENABLE PCI_PM_CTRL_PME_ENABLE
63 #define PCIR_MSIX_CTRL PCI_MSIX_FLAGS
64 #define PCIM_MSIXCTRL_TABLE_SIZE PCI_MSIX_FLAGS_QSIZE
66 #include <dev/pci/pcireg.h>
69 #define IFM_10G_CX4 20 /* 10GBase CX4 copper */
70 #define IFM_10G_TWINAX 22 /* 10GBase Twinax copper */
71 #define IFM_10G_T 26 /* 10GBase-T - RJ45 */
74 #define PCIR_EXPRESS_DEVICE_STA PCI_EXP_TYPE_RC_EC
75 #define PCIM_EXP_STA_TRANSACTION_PND PCI_EXP_DEVSTA_TRPND
76 #define PCIR_EXPRESS_LINK_STA PCI_EXP_LNKSTA
77 #define PCIM_LINK_STA_WIDTH PCI_EXP_LNKSTA_NLW
78 #define PCIM_LINK_STA_SPEED PCI_EXP_LNKSTA_CLS
79 #define PCIR_EXPRESS_DEVICE_CTL PCI_EXP_DEVCTL
80 #define PCIM_EXP_CTL_MAX_PAYLOAD PCI_EXP_DEVCTL_PAYLOAD
81 #define PCIM_EXP_CTL_MAX_READ_REQUEST PCI_EXP_DEVCTL_READRQ
83 #define PCIR_EXPRESS_DEVICE_STA PCIER_DEVICE_STA
84 #define PCIM_EXP_STA_TRANSACTION_PND PCIEM_STA_TRANSACTION_PND
85 #define PCIR_EXPRESS_LINK_STA PCIER_LINK_STA
86 #define PCIM_LINK_STA_WIDTH PCIEM_LINK_STA_WIDTH
87 #define PCIM_LINK_STA_SPEED PCIEM_LINK_STA_SPEED
88 #define PCIR_EXPRESS_DEVICE_CTL PCIER_DEVICE_CTL
89 #define PCIM_EXP_CTL_MAX_PAYLOAD PCIEM_CTL_MAX_PAYLOAD
90 #define PCIM_EXP_CTL_MAX_READ_REQUEST PCIEM_CTL_MAX_READ_REQUEST
94 #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
97 #define ARRSIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
100 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
103 #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
107 int bnx2x_ilog2(int x)
118 #define ilog2(x) bnx2x_ilog2(x)
121 #include "ecore_sp.h"
123 struct bnx2x_device_type {
131 #define BNX2X_PAGE_SHIFT 12
132 #define BNX2X_PAGE_SIZE (1 << BNX2X_PAGE_SHIFT)
133 #define BNX2X_PAGE_MASK (~(BNX2X_PAGE_SIZE - 1))
134 #define BNX2X_PAGE_ALIGN(addr) ((addr + BNX2X_PAGE_SIZE - 1) & BNX2X_PAGE_MASK)
136 #if BNX2X_PAGE_SIZE != 4096
137 #error Page sizes other than 4KB are unsupported!
140 #define U64_LO(addr) ((uint32_t)(((uint64_t)(addr)) & 0xFFFFFFFF))
141 #define U64_HI(addr) ((uint32_t)(((uint64_t)(addr)) >> 32))
142 #define HILO_U64(hi, lo) ((((uint64_t)(hi)) << 32) + (lo))
144 /* dropless fc FW/HW related params */
145 #define BRB_SIZE(sc) (CHIP_IS_E3(sc) ? 1024 : 512)
146 #define MAX_AGG_QS(sc) ETH_MAX_AGGREGATION_QUEUES_E1H_E2
147 #define FW_DROP_LEVEL(sc) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(sc))
148 #define FW_PREFETCH_CNT 16U
149 #define DROPLESS_FC_HEADROOM 100
154 #define MCLBYTES (1 << MCLSHIFT)
156 #if !defined(MJUMPAGESIZE)
157 #if BNX2X_PAGE_SIZE < 2048
158 #define MJUMPAGESIZE MCLBYTES
159 #elif BNX2X_PAGE_SIZE <= 8192
160 #define MJUMPAGESIZE BNX2X_PAGE_SIZE
162 #define MJUMPAGESIZE (8 * 1024)
165 #define MJUM9BYTES (9 * 1024)
166 #define MJUM16BYTES (16 * 1024)
169 * Transmit Buffer Descriptor (tx_bd) definitions*
171 /* NUM_TX_PAGES must be a power of 2. */
172 #define TOTAL_TX_BD_PER_PAGE (BNX2X_PAGE_SIZE / sizeof(union eth_tx_bd_types)) /* 256 */
173 #define USABLE_TX_BD_PER_PAGE (TOTAL_TX_BD_PER_PAGE - 1) /* 255 */
175 #define TOTAL_TX_BD(q) (TOTAL_TX_BD_PER_PAGE * q->nb_tx_pages) /* 512 */
176 #define USABLE_TX_BD(q) (USABLE_TX_BD_PER_PAGE * q->nb_tx_pages) /* 510 */
177 #define MAX_TX_BD(q) (TOTAL_TX_BD(q) - 1) /* 511 */
179 #define NEXT_TX_BD(x) \
180 ((((x) & USABLE_TX_BD_PER_PAGE) == \
181 (USABLE_TX_BD_PER_PAGE - 1)) ? (x) + 2 : (x) + 1)
183 #define TX_BD(x, q) ((x) & MAX_TX_BD(q))
184 #define TX_PAGE(x) (((x) & ~USABLE_TX_BD_PER_PAGE) >> 8)
185 #define TX_IDX(x) ((x) & USABLE_TX_BD_PER_PAGE)
188 * Trigger pending transmits when the number of available BDs is greater
189 * than 1/8 of the total number of usable BDs.
191 #define BNX2X_TX_CLEANUP_THRESHOLD(q) (USABLE_TX_BD(q) / 8)
192 #define BNX2X_TX_TIMEOUT 5
195 * Receive Buffer Descriptor (rx_bd) definitions*
197 //#define NUM_RX_PAGES 1
198 #define TOTAL_RX_BD_PER_PAGE (BNX2X_PAGE_SIZE / sizeof(struct eth_rx_bd)) /* 512 */
199 #define USABLE_RX_BD_PER_PAGE (TOTAL_RX_BD_PER_PAGE - 2) /* 510 */
200 #define RX_BD_PER_PAGE_MASK (TOTAL_RX_BD_PER_PAGE - 1) /* 511 */
201 #define TOTAL_RX_BD(q) (TOTAL_RX_BD_PER_PAGE * q->nb_rx_pages) /* 512 */
202 #define USABLE_RX_BD(q) (USABLE_RX_BD_PER_PAGE * q->nb_rx_pages) /* 510 */
203 #define MAX_RX_BD(q) (TOTAL_RX_BD(q) - 1) /* 511 */
204 #define RX_BD_NEXT_PAGE_DESC_CNT 2
206 #define NEXT_RX_BD(x) \
207 ((((x) & RX_BD_PER_PAGE_MASK) == \
208 (USABLE_RX_BD_PER_PAGE - 1)) ? (x) + 3 : (x) + 1)
211 #define RX_BD(x, q) ((x) & MAX_RX_BD(q))
212 #define RX_PAGE(x) (((x) & ~RX_BD_PER_PAGE_MASK) >> 9)
213 #define RX_IDX(x) ((x) & RX_BD_PER_PAGE_MASK)
216 * Receive Completion Queue definitions*
218 //#define NUM_RCQ_PAGES (NUM_RX_PAGES * 4)
219 #define TOTAL_RCQ_ENTRIES_PER_PAGE (BNX2X_PAGE_SIZE / sizeof(union eth_rx_cqe)) /* 128 */
220 #define USABLE_RCQ_ENTRIES_PER_PAGE (TOTAL_RCQ_ENTRIES_PER_PAGE - 1) /* 127 */
221 #define TOTAL_RCQ_ENTRIES(q) (TOTAL_RCQ_ENTRIES_PER_PAGE * q->nb_cq_pages) /* 512 */
222 #define USABLE_RCQ_ENTRIES(q) (USABLE_RCQ_ENTRIES_PER_PAGE * q->nb_cq_pages) /* 508 */
223 #define MAX_RCQ_ENTRIES(q) (TOTAL_RCQ_ENTRIES(q) - 1) /* 511 */
224 #define RCQ_NEXT_PAGE_DESC_CNT 1
226 #define NEXT_RCQ_IDX(x) \
227 ((((x) & USABLE_RCQ_ENTRIES_PER_PAGE) == \
228 (USABLE_RCQ_ENTRIES_PER_PAGE - 1)) ? (x) + 2 : (x) + 1)
231 (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd))
233 #define RCQ_BD_PAGES(q) \
234 (q->nb_rx_pages * CQE_BD_REL)
236 #define RCQ_ENTRY(x, q) ((x) & MAX_RCQ_ENTRIES(q))
237 #define RCQ_PAGE(x) (((x) & ~USABLE_RCQ_ENTRIES_PER_PAGE) >> 7)
238 #define RCQ_IDX(x) ((x) & USABLE_RCQ_ENTRIES_PER_PAGE)
241 * dropless fc calculations for BDs
242 * Number of BDs should be as number of buffers in BRB:
243 * Low threshold takes into account RX_BD_NEXT_PAGE_DESC_CNT
244 * "next" elements on each page
246 #define NUM_BD_REQ(sc) \
248 #define NUM_BD_PG_REQ(sc) \
249 ((NUM_BD_REQ(sc) + USABLE_RX_BD_PER_PAGE - 1) / USABLE_RX_BD_PER_PAGE)
250 #define BD_TH_LO(sc) \
252 NUM_BD_PG_REQ(sc) * RX_BD_NEXT_PAGE_DESC_CNT + \
254 #define BD_TH_HI(sc) \
255 (BD_TH_LO(sc) + DROPLESS_FC_HEADROOM)
256 #define MIN_RX_AVAIL(sc) \
257 ((sc)->dropless_fc ? BD_TH_HI(sc) + 128 : 128)
260 * dropless fc calculations for RCQs
261 * Number of RCQs should be as number of buffers in BRB:
262 * Low threshold takes into account RCQ_NEXT_PAGE_DESC_CNT
263 * "next" elements on each page
265 #define NUM_RCQ_REQ(sc) \
267 #define NUM_RCQ_PG_REQ(sc) \
268 ((NUM_RCQ_REQ(sc) + USABLE_RCQ_ENTRIES_PER_PAGE - 1) / USABLE_RCQ_ENTRIES_PER_PAGE)
269 #define RCQ_TH_LO(sc) \
271 NUM_RCQ_PG_REQ(sc) * RCQ_NEXT_PAGE_DESC_CNT + \
273 #define RCQ_TH_HI(sc) \
274 (RCQ_TH_LO(sc) + DROPLESS_FC_HEADROOM)
276 /* Load / Unload modes */
277 #define LOAD_NORMAL 0
280 #define LOAD_LOOPBACK_EXT 3
281 #define UNLOAD_NORMAL 0
282 #define UNLOAD_CLOSE 1
283 #define UNLOAD_RECOVERY 2
285 /* Some constants... */
286 //#define MAX_PATH_NUM 2
287 //#define E2_MAX_NUM_OF_VFS 64
288 //#define E1H_FUNC_MAX 8
289 //#define E2_FUNC_MAX 4 /* per path */
290 #define MAX_VNIC_NUM 4
291 #define MAX_FUNC_NUM 8 /* common to all chips */
292 //#define MAX_NDSB HC_SB_MAX_SB_E2 /* max non-default status block */
293 #define MAX_RSS_CHAINS 16 /* a constant for HW limit */
294 #define MAX_MSI_VECTOR 8 /* a constant for HW limit */
296 #define ILT_NUM_PAGE_ENTRIES 3072
298 * 57711 we use whole table since we have 8 functions.
299 * 57712 we have only 4 functions, but use same size per func, so only half
300 * of the table is used.
302 #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES / 8)
303 #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC)
305 * the phys address is shifted right 12 bits and has an added
306 * 1=valid bit added to the 53rd bit
307 * then since this is a wide register(TM)
308 * we split it into two 32 bit writes
310 #define ONCHIP_ADDR1(x) ((uint32_t)(((uint64_t)x >> 12) & 0xFFFFFFFF))
311 #define ONCHIP_ADDR2(x) ((uint32_t)((1 << 20) | ((uint64_t)x >> 44)))
313 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
315 #define ETH_OVERHEAD (ETH_HLEN + 8 + 8)
316 #define ETH_MIN_PACKET_SIZE 60
317 #define ETH_MAX_PACKET_SIZE ETHERMTU /* 1500 */
318 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
319 /* TCP with Timestamp Option (32) + IPv6 (40) */
321 /* max supported alignment is 256 (8 shift) */
322 #define BNX2X_RX_ALIGN_SHIFT 8
323 /* FW uses 2 cache lines alignment for start packet and size */
324 #define BNX2X_FW_RX_ALIGN_START (1 << BNX2X_RX_ALIGN_SHIFT)
325 #define BNX2X_FW_RX_ALIGN_END (1 << BNX2X_RX_ALIGN_SHIFT)
327 #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5)
333 /* Used to manage DMA allocations. */
335 struct bnx2x_softc *sc;
339 char msg[RTE_MEMZONE_NAMESIZE - 6];
342 /* attn group wiring */
343 #define MAX_DYNAMIC_ATTN_GRPS 8
357 union bnx2x_host_hc_status_block {
358 /* pointer to fp status block e2 */
359 struct host_hc_status_block_e2 *e2_sb;
360 /* pointer to fp status block e1x */
361 struct host_hc_status_block_e1x *e1x_sb;
364 union bnx2x_db_prod {
365 struct doorbell_set_prod data;
369 struct bnx2x_sw_tx_bd {
373 /* set on the first BD descriptor when there is a split BD */
374 #define BNX2X_TSO_SPLIT_BD (1 << 0)
378 * This is the HSI fastpath data structure. There can be up to MAX_RSS_CHAIN
379 * instances of the fastpath structure when using multiple queues.
381 struct bnx2x_fastpath {
382 /* pointer back to parent structure */
383 struct bnx2x_softc *sc;
386 struct bnx2x_dma sb_dma;
387 union bnx2x_host_hc_status_block status_block;
389 phys_addr_t tx_desc_mapping;
391 phys_addr_t rx_desc_mapping;
392 phys_addr_t rx_comp_mapping;
394 uint16_t *sb_index_values;
395 uint16_t *sb_running_index;
396 uint32_t ustorm_rx_prods_offset;
398 uint8_t igu_sb_id; /* status block number in HW */
399 uint8_t fw_sb_id; /* status block number in FW */
401 uint32_t rx_buf_size;
405 #define BNX2X_FP_STATE_CLOSED 0x01
406 #define BNX2X_FP_STATE_IRQ 0x02
407 #define BNX2X_FP_STATE_OPENING 0x04
408 #define BNX2X_FP_STATE_OPEN 0x08
409 #define BNX2X_FP_STATE_HALTING 0x10
410 #define BNX2X_FP_STATE_HALTED 0x20
412 /* reference back to this fastpath queue number */
413 uint8_t index; /* this is also the 'cid' */
414 #define FP_IDX(fp) (fp->index)
416 /* ethernet client ID (each fastpath set of RX/TX/CQE is a client) */
418 #define FP_CL_ID(fp) (fp->cl_id)
423 union bnx2x_db_prod tx_db;
425 struct tstorm_per_queue_stats old_tclient;
426 struct ustorm_per_queue_stats old_uclient;
427 struct xstorm_per_queue_stats old_xclient;
428 struct bnx2x_eth_q_stats eth_q_stats;
429 struct bnx2x_eth_q_stats_old eth_q_stats_old;
431 /* Pointer to the receive consumer in the status block */
432 uint16_t *rx_cq_cons_sb;
434 /* Pointer to the transmit consumer in the status block */
435 uint16_t *tx_cons_sb;
437 /* transmit timeout until chip reset */
440 }; /* struct bnx2x_fastpath */
442 #define BNX2X_MAX_NUM_OF_VFS 64
443 #define BNX2X_VF_ID_INVALID 0xFF
445 /* maximum number of fast-path interrupt contexts */
446 #define FP_SB_MAX_E1x 16
447 #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2
450 struct eth_context eth;
454 /* CDU host DB constants */
455 #define CDU_ILT_PAGE_SZ_HW 2
456 #define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */
457 #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context))
459 #define CNIC_ISCSI_CID_MAX 256
460 #define CNIC_FCOE_CID_MAX 2048
461 #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX)
462 #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS)
464 #define QM_ILT_PAGE_SZ_HW 0
465 #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */
466 #define QM_CID_ROUND 1024
468 /* TM (timers) host DB constants */
469 #define TM_ILT_PAGE_SZ_HW 0
470 #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */
471 /*#define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */
472 #define TM_CONN_NUM 1024
473 #define TM_ILT_SZ (8 * TM_CONN_NUM)
474 #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ)
476 /* SRC (Searcher) host DB constants */
477 #define SRC_ILT_PAGE_SZ_HW 0
478 #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */
479 #define SRC_HASH_BITS 10
480 #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */
481 #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM)
482 #define SRC_T2_SZ SRC_ILT_SZ
483 #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ)
486 struct bnx2x_dma vcxt_dma;
487 union cdu_context *vcxt;
488 //phys_addr_t cxt_mapping;
495 /* defines for multiple tx priority indices */
496 #define FIRST_TX_ONLY_COS_INDEX 1
497 #define FIRST_TX_COS_INDEX 0
499 #define CID_TO_FP(cid, sc) ((cid) % BNX2X_NUM_NON_CNIC_QUEUES(sc))
501 #define HC_INDEX_ETH_RX_CQ_CONS 1
502 #define HC_INDEX_OOO_TX_CQ_CONS 4
503 #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5
504 #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6
505 #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7
506 #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0
508 /* congestion management fairness mode */
509 #define CMNG_FNS_NONE 0
510 #define CMNG_FNS_MINMAX 1
512 /* CMNG constants, as derived from system spec calculations */
513 /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */
514 #define DEF_MIN_RATE 100
515 /* resolution of the rate shaping timer - 400 usec */
516 #define RS_PERIODIC_TIMEOUT_USEC 400
517 /* number of bytes in single QM arbitration cycle -
518 * coefficient for calculating the fairness timer */
519 #define QM_ARB_BYTES 160000
520 /* resolution of Min algorithm 1:100 */
522 /* how many bytes above threshold for the minimal credit of Min algorithm*/
523 #define MIN_ABOVE_THRESH 32768
524 /* fairness algorithm integration time coefficient -
525 * for calculating the actual Tfair */
526 #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES)
527 /* memory of fairness algorithm - 2 cycles */
530 #define HC_SEG_ACCESS_DEF 0 /* Driver decision 0-3 */
531 #define HC_SEG_ACCESS_ATTN 4
532 #define HC_SEG_ACCESS_NORM 0 /* Driver decision 0-1 */
535 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is
536 * control by the number of fast-path status blocks supported by the
537 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default
538 * status block represents an independent interrupts context that can
539 * serve a regular L2 networking queue. However special L2 queues such
540 * as the FCoE queue do not require a FP-SB and other components like
541 * the CNIC may consume FP-SB reducing the number of possible L2 queues
543 * If the maximum number of FP-SB available is X then:
544 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of
545 * regular L2 queues is Y=X-1
546 * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor)
547 * c. If the FCoE L2 queue is supported the actual number of L2 queues
549 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for
550 * slow-path interrupts) or Y+2 if CNIC is supported (one additional
551 * FP interrupt context for the CNIC).
552 * e. The number of HW context (CID count) is always X or X+1 if FCoE
553 * L2 queue is supported. the cid for the FCoE L2 queue is always X.
555 * So this is quite simple for now as no ULPs are supported yet. :-)
557 #define BNX2X_NUM_QUEUES(sc) ((sc)->num_queues)
558 #define BNX2X_NUM_ETH_QUEUES(sc) BNX2X_NUM_QUEUES(sc)
559 #define BNX2X_NUM_NON_CNIC_QUEUES(sc) BNX2X_NUM_QUEUES(sc)
560 #define BNX2X_NUM_RX_QUEUES(sc) BNX2X_NUM_QUEUES(sc)
562 #define FOR_EACH_QUEUE(sc, var) \
563 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(sc); (var)++)
565 #define FOR_EACH_NONDEFAULT_QUEUE(sc, var) \
566 for ((var) = 1; (var) < BNX2X_NUM_QUEUES(sc); (var)++)
568 #define FOR_EACH_ETH_QUEUE(sc, var) \
569 for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(sc); (var)++)
571 #define FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, var) \
572 for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(sc); (var)++)
574 #define FOR_EACH_COS_IN_TX_QUEUE(sc, var) \
575 for ((var) = 0; (var) < (sc)->max_cos; (var)++)
577 #define FOR_EACH_CNIC_QUEUE(sc, var) \
578 for ((var) = BNX2X_NUM_ETH_QUEUES(sc); \
579 (var) < BNX2X_NUM_QUEUES(sc); \
588 #define FCOE_IDX(sc) (BNX2X_NUM_NON_CNIC_QUEUES(sc) + FCOE_IDX_OFFSET)
589 #define bnx2x_fcoe_fp(sc) (&sc->fp[FCOE_IDX(sc)])
590 #define bnx2x_fcoe(sc, var) (bnx2x_fcoe_fp(sc)->var)
591 #define bnx2x_fcoe_inner_sp_obj(sc) (&sc->sp_objs[FCOE_IDX(sc)])
592 #define bnx2x_fcoe_sp_obj(sc, var) (bnx2x_fcoe_inner_sp_obj(sc)->var)
593 #define bnx2x_fcoe_tx(sc, var) (bnx2x_fcoe_fp(sc)->txdata_ptr[FIRST_TX_COS_INDEX]->var)
595 #define OOO_IDX(sc) (BNX2X_NUM_NON_CNIC_QUEUES(sc) + OOO_IDX_OFFSET)
596 #define bnx2x_ooo_fp(sc) (&sc->fp[OOO_IDX(sc)])
597 #define bnx2x_ooo(sc, var) (bnx2x_ooo_fp(sc)->var)
598 #define bnx2x_ooo_inner_sp_obj(sc) (&sc->sp_objs[OOO_IDX(sc)])
599 #define bnx2x_ooo_sp_obj(sc, var) (bnx2x_ooo_inner_sp_obj(sc)->var)
601 #define FWD_IDX(sc) (BNX2X_NUM_NON_CNIC_QUEUES(sc) + FWD_IDX_OFFSET)
602 #define bnx2x_fwd_fp(sc) (&sc->fp[FWD_IDX(sc)])
603 #define bnx2x_fwd(sc, var) (bnx2x_fwd_fp(sc)->var)
604 #define bnx2x_fwd_inner_sp_obj(sc) (&sc->sp_objs[FWD_IDX(sc)])
605 #define bnx2x_fwd_sp_obj(sc, var) (bnx2x_fwd_inner_sp_obj(sc)->var)
606 #define bnx2x_fwd_txdata(fp) (fp->txdata_ptr[FIRST_TX_COS_INDEX])
608 #define IS_ETH_FP(fp) ((fp)->index < BNX2X_NUM_ETH_QUEUES((fp)->sc))
609 #define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->sc))
610 #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(sc))
611 #define IS_FWD_FP(fp) ((fp)->index == FWD_IDX((fp)->sc))
612 #define IS_FWD_IDX(idx) ((idx) == FWD_IDX(sc))
613 #define IS_OOO_FP(fp) ((fp)->index == OOO_IDX((fp)->sc))
614 #define IS_OOO_IDX(idx) ((idx) == OOO_IDX(sc))
617 BNX2X_PORT_QUERY_IDX,
619 BNX2X_FCOE_QUERY_IDX,
620 BNX2X_FIRST_QUEUE_QUERY_IDX,
623 struct bnx2x_fw_stats_req {
624 struct stats_query_header hdr;
625 struct stats_query_entry query[FP_SB_MAX_E1x +
626 BNX2X_FIRST_QUEUE_QUERY_IDX];
629 struct bnx2x_fw_stats_data {
630 struct stats_counter storm_counters;
631 struct per_port_stats port;
632 struct per_pf_stats pf;
633 struct per_queue_stats queue_stats[1];
636 /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */
637 #define BNX2X_IGU_STAS_MSG_VF_CNT 64
638 #define BNX2X_IGU_STAS_MSG_PF_CNT 4
643 * This is the slowpath data structure. It is mapped into non-paged memory
644 * so that the hardware can access it's contents directly and must be page
647 struct bnx2x_slowpath {
649 /* used by the DMAE command executer */
650 struct dmae_command dmae[MAX_DMAE_C];
652 /* statistics completion */
655 /* firmware defined statistics blocks */
656 union mac_stats mac_stats;
657 struct nig_stats nig_stats;
658 struct host_port_stats port_stats;
659 struct host_func_stats func_stats;
661 /* DMAE completion value and data source/sink */
666 struct mac_configuration_cmd e1x;
667 struct eth_classify_rules_ramrod_data e2;
671 struct tstorm_eth_mac_filter_config e1x;
672 struct eth_filter_rules_ramrod_data e2;
675 struct eth_rss_update_ramrod_data rss_rdata;
678 struct mac_configuration_cmd e1;
679 struct eth_multicast_rules_ramrod_data e2;
683 struct function_start_data func_start;
684 struct flow_control_configuration pfc_config; /* for DCBX ramrod */
687 /* Queue State related ramrods */
689 struct client_init_ramrod_data init_data;
690 struct client_update_ramrod_data update_data;
694 * AFEX ramrod can not be a part of func_rdata union because these
695 * events might arrive in parallel to other events from func_rdata.
696 * If they were defined in the same union the data can get corrupted.
698 struct afex_vif_list_ramrod_data func_afex_rdata;
700 union drv_info_to_mcp drv_info_to_mcp;
701 }; /* struct bnx2x_slowpath */
704 * Port specifc data structure.
708 * Port Management Function (for 57711E only).
709 * When this field is set the driver instance is
710 * responsible for managing port specifc
711 * configurations such as handling link attentions.
715 /* Ethernet maximum transmission unit. */
718 uint32_t link_config[ELINK_LINK_CONFIG_SIZE];
720 uint32_t ext_phy_config;
722 /* Port feature config.*/
725 /* Defines the features supported by the PHY. */
726 uint32_t supported[ELINK_LINK_CONFIG_SIZE];
728 /* Defines the features advertised by the PHY. */
729 uint32_t advertising[ELINK_LINK_CONFIG_SIZE];
730 #define ADVERTISED_10baseT_Half (1 << 1)
731 #define ADVERTISED_10baseT_Full (1 << 2)
732 #define ADVERTISED_100baseT_Half (1 << 3)
733 #define ADVERTISED_100baseT_Full (1 << 4)
734 #define ADVERTISED_1000baseT_Half (1 << 5)
735 #define ADVERTISED_1000baseT_Full (1 << 6)
736 #define ADVERTISED_TP (1 << 7)
737 #define ADVERTISED_FIBRE (1 << 8)
738 #define ADVERTISED_Autoneg (1 << 9)
739 #define ADVERTISED_Asym_Pause (1 << 10)
740 #define ADVERTISED_Pause (1 << 11)
741 #define ADVERTISED_2500baseX_Full (1 << 15)
742 #define ADVERTISED_10000baseT_Full (1 << 16)
747 * MCP scratchpad address for port specific statistics.
748 * The device is responsible for writing statistcss
749 * back to the MCP for use with management firmware such
754 struct nig_stats old_nig_stats;
755 }; /* struct bnx2x_port */
757 struct bnx2x_mf_info {
758 uint32_t mf_config[E1HVN_MAX];
760 uint32_t vnics_per_port; /* 1, 2 or 4 */
761 uint32_t multi_vnics_mode; /* can be set even if vnics_per_port = 1 */
762 uint32_t path_has_ovlan; /* MF mode in the path (can be different than the MF mode of the function */
764 #define IS_MULTI_VNIC(sc) ((sc)->devinfo.mf_info.multi_vnics_mode)
765 #define VNICS_PER_PORT(sc) ((sc)->devinfo.mf_info.vnics_per_port)
766 #define VNICS_PER_PATH(sc) \
767 ((sc)->devinfo.mf_info.vnics_per_port * \
768 ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 1 ))
770 uint8_t min_bw[MAX_VNIC_NUM];
771 uint8_t max_bw[MAX_VNIC_NUM];
773 uint16_t ext_id; /* vnic outer vlan or VIF ID */
774 #define VALID_OVLAN(ovlan) ((ovlan) <= 4096)
775 #define INVALID_VIF_ID 0xFFFF
776 #define OVLAN(sc) ((sc)->devinfo.mf_info.ext_id)
777 #define VIF_ID(sc) ((sc)->devinfo.mf_info.ext_id)
779 uint16_t default_vlan;
780 #define NIV_DEFAULT_VLAN(sc) ((sc)->devinfo.mf_info.default_vlan)
782 uint8_t niv_allowed_priorities;
783 #define NIV_ALLOWED_PRIORITIES(sc) ((sc)->devinfo.mf_info.niv_allowed_priorities)
785 uint8_t niv_default_cos;
786 #define NIV_DEFAULT_COS(sc) ((sc)->devinfo.mf_info.niv_default_cos)
788 uint8_t niv_mba_enabled;
790 enum mf_cfg_afex_vlan_mode afex_vlan_mode;
791 #define AFEX_VLAN_MODE(sc) ((sc)->devinfo.mf_info.afex_vlan_mode)
792 int afex_def_vlan_tag;
793 uint32_t pending_max;
796 #define MF_INFO_VALID_MAC 0x0001
799 uint8_t mf_mode; /* Switch-Dependent or Switch-Independent */
801 (IS_MULTI_VNIC(sc) && \
802 ((sc)->devinfo.mf_info.mf_mode != 0))
803 #define IS_MF_SD(sc) \
804 (IS_MULTI_VNIC(sc) && \
805 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SD))
806 #define IS_MF_SI(sc) \
807 (IS_MULTI_VNIC(sc) && \
808 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SI))
809 #define IS_MF_AFEX(sc) \
810 (IS_MULTI_VNIC(sc) && \
811 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_AFEX))
812 #define IS_MF_SD_MODE(sc) IS_MF_SD(sc)
813 #define IS_MF_SI_MODE(sc) IS_MF_SI(sc)
814 #define IS_MF_AFEX_MODE(sc) IS_MF_AFEX(sc)
816 uint32_t mf_protos_supported;
817 #define MF_PROTO_SUPPORT_ETHERNET 0x1
818 #define MF_PROTO_SUPPORT_ISCSI 0x2
819 #define MF_PROTO_SUPPORT_FCOE 0x4
820 }; /* struct bnx2x_mf_info */
822 /* Device information data structure. */
823 struct bnx2x_devinfo {
827 uint16_t subvendor_id;
828 uint16_t subdevice_id;
831 * chip_id = 0b'CCCCCCCCCCCCCCCCRRRRMMMMMMMMBBBB'
832 * C = Chip Number (bits 16-31)
833 * R = Chip Revision (bits 12-15)
834 * M = Chip Metal (bits 4-11)
835 * B = Chip Bond ID (bits 0-3)
838 #define CHIP_ID(sc) ((sc)->devinfo.chip_id & 0xffff0000)
839 #define CHIP_NUM(sc) ((sc)->devinfo.chip_id >> 16)
841 #define CHIP_NUM_57711 0x164f
842 #define CHIP_NUM_57711E 0x1650
843 #define CHIP_NUM_57712 0x1662
844 #define CHIP_NUM_57712_MF 0x1663
845 #define CHIP_NUM_57712_VF 0x166f
846 #define CHIP_NUM_57800 0x168a
847 #define CHIP_NUM_57800_MF 0x16a5
848 #define CHIP_NUM_57800_VF 0x16a9
849 #define CHIP_NUM_57810 0x168e
850 #define CHIP_NUM_57810_MF 0x16ae
851 #define CHIP_NUM_57810_VF 0x16af
852 #define CHIP_NUM_57811 0x163d
853 #define CHIP_NUM_57811_MF 0x163e
854 #define CHIP_NUM_57811_VF 0x163f
855 #define CHIP_NUM_57840_OBS 0x168d
856 #define CHIP_NUM_57840_OBS_MF 0x16ab
857 #define CHIP_NUM_57840_4_10 0x16a1
858 #define CHIP_NUM_57840_2_20 0x16a2
859 #define CHIP_NUM_57840_MF 0x16a4
860 #define CHIP_NUM_57840_VF 0x16ad
862 #define CHIP_REV_SHIFT 12
863 #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT)
864 #define CHIP_REV(sc) ((sc)->devinfo.chip_id & CHIP_REV_MASK)
866 #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT)
867 #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT)
868 #define CHIP_REV_Cx (0x2 << CHIP_REV_SHIFT)
870 #define CHIP_REV_IS_SLOW(sc) \
871 (CHIP_REV(sc) > 0x00005000)
872 #define CHIP_REV_IS_FPGA(sc) \
873 (CHIP_REV_IS_SLOW(sc) && (CHIP_REV(sc) & 0x00001000))
874 #define CHIP_REV_IS_EMUL(sc) \
875 (CHIP_REV_IS_SLOW(sc) && !(CHIP_REV(sc) & 0x00001000))
876 #define CHIP_REV_IS_ASIC(sc) \
877 (!CHIP_REV_IS_SLOW(sc))
879 #define CHIP_METAL(sc) ((sc->devinfo.chip_id) & 0x00000ff0)
880 #define CHIP_BOND_ID(sc) ((sc->devinfo.chip_id) & 0x0000000f)
882 #define CHIP_IS_57711(sc) (CHIP_NUM(sc) == CHIP_NUM_57711)
883 #define CHIP_IS_57711E(sc) (CHIP_NUM(sc) == CHIP_NUM_57711E)
884 #define CHIP_IS_E1H(sc) ((CHIP_IS_57711(sc)) || \
885 (CHIP_IS_57711E(sc)))
886 #define CHIP_IS_E1x(sc) CHIP_IS_E1H(sc)
888 #define CHIP_IS_57712(sc) (CHIP_NUM(sc) == CHIP_NUM_57712)
889 #define CHIP_IS_57712_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_MF)
890 #define CHIP_IS_57712_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_VF)
891 #define CHIP_IS_E2(sc) (CHIP_IS_57712(sc) || \
892 CHIP_IS_57712_MF(sc))
894 #define CHIP_IS_57800(sc) (CHIP_NUM(sc) == CHIP_NUM_57800)
895 #define CHIP_IS_57800_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_MF)
896 #define CHIP_IS_57800_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_VF)
897 #define CHIP_IS_57810(sc) (CHIP_NUM(sc) == CHIP_NUM_57810)
898 #define CHIP_IS_57810_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_MF)
899 #define CHIP_IS_57810_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_VF)
900 #define CHIP_IS_57811(sc) (CHIP_NUM(sc) == CHIP_NUM_57811)
901 #define CHIP_IS_57811_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_MF)
902 #define CHIP_IS_57811_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_VF)
903 #define CHIP_IS_57840(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS) || \
904 (CHIP_NUM(sc) == CHIP_NUM_57840_4_10) || \
905 (CHIP_NUM(sc) == CHIP_NUM_57840_2_20))
906 #define CHIP_IS_57840_MF(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS_MF) || \
907 (CHIP_NUM(sc) == CHIP_NUM_57840_MF))
908 #define CHIP_IS_57840_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57840_VF)
910 #define CHIP_IS_E3(sc) (CHIP_IS_57800(sc) || \
911 CHIP_IS_57800_MF(sc) || \
912 CHIP_IS_57800_VF(sc) || \
913 CHIP_IS_57810(sc) || \
914 CHIP_IS_57810_MF(sc) || \
915 CHIP_IS_57810_VF(sc) || \
916 CHIP_IS_57811(sc) || \
917 CHIP_IS_57811_MF(sc) || \
918 CHIP_IS_57811_VF(sc) || \
919 CHIP_IS_57840(sc) || \
920 CHIP_IS_57840_MF(sc) || \
921 CHIP_IS_57840_VF(sc))
922 #define CHIP_IS_E3A0(sc) (CHIP_IS_E3(sc) && \
923 (CHIP_REV(sc) == CHIP_REV_Ax))
924 #define CHIP_IS_E3B0(sc) (CHIP_IS_E3(sc) && \
925 (CHIP_REV(sc) == CHIP_REV_Bx))
927 #define USES_WARPCORE(sc) (CHIP_IS_E3(sc))
928 #define CHIP_IS_E2E3(sc) (CHIP_IS_E2(sc) || \
931 #define CHIP_IS_MF_CAP(sc) (CHIP_IS_57711E(sc) || \
932 CHIP_IS_57712_MF(sc) || \
935 #define IS_VF(sc) ((sc)->flags & BNX2X_IS_VF_FLAG)
936 #define IS_PF(sc) (!IS_VF(sc))
939 * This define is used in two main places:
940 * 1. In the early stages of nic_load, to know if to configure Parser/Searcher
941 * to nic-only mode or to offload mode. Offload mode is configured if either
942 * the chip is E1x (where NIC_MODE register is not applicable), or if cnic
943 * already registered for this port (which means that the user wants storage
945 * 2. During cnic-related load, to know if offload mode is already configured
946 * in the HW or needs to be configrued. Since the transition from nic-mode to
947 * offload-mode in HW causes traffic coruption, nic-mode is configured only
948 * in ports on which storage services where never requested.
950 #define CONFIGURE_NIC_MODE(sc) (!CHIP_IS_E1x(sc) && !CNIC_ENABLED(sc))
952 uint8_t chip_port_mode;
953 #define CHIP_4_PORT_MODE 0x0
954 #define CHIP_2_PORT_MODE 0x1
955 #define CHIP_PORT_MODE_NONE 0x2
956 #define CHIP_PORT_MODE(sc) ((sc)->devinfo.chip_port_mode)
957 #define CHIP_IS_MODE_4_PORT(sc) (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE)
960 #define INT_BLOCK_HC 0
961 #define INT_BLOCK_IGU 1
962 #define INT_BLOCK_MODE_NORMAL 0
963 #define INT_BLOCK_MODE_BW_COMP 2
964 #define CHIP_INT_MODE_IS_NBC(sc) \
965 (!CHIP_IS_E1x(sc) && \
966 !((sc)->devinfo.int_block & INT_BLOCK_MODE_BW_COMP))
967 #define CHIP_INT_MODE_IS_BC(sc) (!CHIP_INT_MODE_IS_NBC(sc))
970 uint32_t shmem2_base;
973 uint32_t mf_cfg_base; /* bootcode shmem address in BAR memory */
974 struct bnx2x_mf_info mf_info;
977 #define NVRAM_1MB_SIZE 0x20000
978 #define NVRAM_TIMEOUT_COUNT 30000
979 #define NVRAM_PAGE_SIZE 256
981 /* PCIe capability information */
982 uint32_t pcie_cap_flags;
983 #define BNX2X_PM_CAPABLE_FLAG 0x00000001
984 #define BNX2X_PCIE_CAPABLE_FLAG 0x00000002
985 #define BNX2X_MSI_CAPABLE_FLAG 0x00000004
986 #define BNX2X_MSIX_CAPABLE_FLAG 0x00000008
987 uint16_t pcie_pm_cap_reg;
988 uint16_t pcie_link_width;
989 uint16_t pcie_link_speed;
990 uint16_t pcie_msi_cap_reg;
991 uint16_t pcie_msix_cap_reg;
993 /* device configuration read from bootcode shared memory */
996 }; /* struct bnx2x_devinfo */
998 struct bnx2x_sp_objs {
999 struct ecore_vlan_mac_obj mac_obj; /* MACs object */
1000 struct ecore_queue_sp_obj q_obj; /* Queue State object */
1001 }; /* struct bnx2x_sp_objs */
1004 * Data that will be used to create a link report message. We will keep the
1005 * data used for the last link report in order to prevent reporting the same
1006 * link parameters twice.
1008 struct bnx2x_link_report_data {
1009 uint16_t line_speed; /* Effective line speed */
1010 unsigned long link_report_flags; /* BNX2X_LINK_REPORT_XXX flags */
1014 BNX2X_LINK_REPORT_FULL_DUPLEX,
1015 BNX2X_LINK_REPORT_LINK_DOWN,
1016 BNX2X_LINK_REPORT_RX_FC_ON,
1017 BNX2X_LINK_REPORT_TX_FC_ON
1020 #define BNX2X_RX_CHAIN_PAGE_SZ BNX2X_PAGE_SIZE
1022 struct bnx2x_pci_cap {
1023 struct bnx2x_pci_cap *next;
1031 /* Top level device private data structure. */
1032 struct bnx2x_softc {
1036 uint32_t max_tx_queues;
1037 uint32_t max_rx_queues;
1038 const struct rte_pci_device *pci_dev;
1040 struct bnx2x_pci_cap *pci_caps;
1041 #define BNX2X_INTRS_POLL_PERIOD 1
1046 /* MAC address operations */
1047 struct bnx2x_mac_ops mac_ops;
1049 /* structures for VF mbox/response/bulletin */
1050 struct bnx2x_vf_mbx_msg *vf2pf_mbox;
1051 struct bnx2x_dma vf2pf_mbox_mapping;
1052 struct vf_acquire_resp_tlv acquire_resp;
1053 struct bnx2x_vf_bulletin *pf2vf_bulletin;
1054 struct bnx2x_dma pf2vf_bulletin_mapping;
1055 struct bnx2x_vf_bulletin old_bulletin;
1059 int state; /* device state */
1060 #define BNX2X_STATE_CLOSED 0x0000
1061 #define BNX2X_STATE_OPENING_WAITING_LOAD 0x1000
1062 #define BNX2X_STATE_OPENING_WAITING_PORT 0x2000
1063 #define BNX2X_STATE_OPEN 0x3000
1064 #define BNX2X_STATE_CLOSING_WAITING_HALT 0x4000
1065 #define BNX2X_STATE_CLOSING_WAITING_DELETE 0x5000
1066 #define BNX2X_STATE_CLOSING_WAITING_UNLOAD 0x6000
1067 #define BNX2X_STATE_DISABLED 0xD000
1068 #define BNX2X_STATE_DIAG 0xE000
1069 #define BNX2X_STATE_ERROR 0xF000
1072 #define BNX2X_ONE_PORT_FLAG 0x1
1073 #define BNX2X_NO_FCOE_FLAG 0x2
1074 #define BNX2X_NO_WOL_FLAG 0x4
1075 #define BNX2X_NO_MCP_FLAG 0x8
1076 #define BNX2X_NO_ISCSI_OOO_FLAG 0x10
1077 #define BNX2X_NO_ISCSI_FLAG 0x20
1078 #define BNX2X_MF_FUNC_DIS 0x40
1079 #define BNX2X_TX_SWITCHING 0x80
1080 #define BNX2X_IS_VF_FLAG 0x100
1082 #define BNX2X_ONE_PORT(sc) (sc->flags & BNX2X_ONE_PORT_FLAG)
1083 #define BNX2X_NOFCOE(sc) (sc->flags & BNX2X_NO_FCOE_FLAG)
1084 #define BNX2X_NOMCP(sc) (sc->flags & BNX2X_NO_MCP_FLAG)
1087 struct bnx2x_bar bar[MAX_BARS]; /* map BARs 0, 2, 4 */
1089 uint16_t doorbell_size;
1091 /* periodic timer callout */
1092 #define PERIODIC_STOP 0
1093 #define PERIODIC_GO 1
1094 volatile unsigned long periodic_flags;
1096 struct bnx2x_fastpath fp[MAX_RSS_CHAINS];
1097 struct bnx2x_sp_objs sp_objs[MAX_RSS_CHAINS];
1099 uint8_t unit; /* driver instance number */
1101 int pcie_bus; /* PCIe bus number */
1102 int pcie_device; /* PCIe device/slot number */
1103 int pcie_func; /* PCIe function number */
1105 uint8_t pfunc_rel; /* function relative */
1106 uint8_t pfunc_abs; /* function absolute */
1107 uint8_t path_id; /* function absolute */
1108 #define SC_PATH(sc) (sc->path_id)
1109 #define SC_PORT(sc) (sc->pfunc_rel & 1)
1110 #define SC_FUNC(sc) (sc->pfunc_rel)
1111 #define SC_ABS_FUNC(sc) (sc->pfunc_abs)
1112 #define SC_VN(sc) (sc->pfunc_rel >> 1)
1113 #define SC_L_ID(sc) (SC_VN(sc) << 2)
1114 #define PORT_ID(sc) SC_PORT(sc)
1115 #define PATH_ID(sc) SC_PATH(sc)
1116 #define VNIC_ID(sc) SC_VN(sc)
1117 #define FUNC_ID(sc) SC_FUNC(sc)
1118 #define ABS_FUNC_ID(sc) SC_ABS_FUNC(sc)
1119 #define SC_FW_MB_IDX_VN(sc, vn) \
1120 (SC_PORT(sc) + (vn) * \
1121 ((CHIP_IS_E1x(sc) || (CHIP_IS_MODE_4_PORT(sc))) ? 2 : 1))
1122 #define SC_FW_MB_IDX(sc) SC_FW_MB_IDX_VN(sc, SC_VN(sc))
1124 int if_capen; /* enabled interface capabilities */
1126 struct bnx2x_devinfo devinfo;
1127 char fw_ver_str[32];
1128 char mf_mode_str[32];
1129 char pci_link_str[32];
1131 struct iro *iro_array;
1134 #define DMAE_READY(sc) (sc->dmae_ready)
1136 struct ecore_credit_pool_obj vlans_pool;
1137 struct ecore_credit_pool_obj macs_pool;
1138 struct ecore_rx_mode_obj rx_mode_obj;
1139 struct ecore_mcast_obj mcast_obj;
1140 struct ecore_rss_config_obj rss_conf_obj;
1141 struct ecore_func_sp_obj func_obj;
1144 uint16_t fw_drv_pulse_wr_seq;
1147 struct elink_params link_params;
1148 struct elink_vars link_vars;
1150 struct bnx2x_link_report_data last_reported_link;
1151 char mac_addr_str[32];
1153 uint32_t tx_ring_size;
1154 uint32_t rx_ring_size;
1159 #define BNX2X_RECOVERY_DONE 1
1160 #define BNX2X_RECOVERY_INIT 2
1161 #define BNX2X_RECOVERY_WAIT 3
1162 #define BNX2X_RECOVERY_FAILED 4
1163 #define BNX2X_RECOVERY_NIC_LOADING 5
1166 #define BNX2X_RX_MODE_NONE 0
1167 #define BNX2X_RX_MODE_NORMAL 1
1168 #define BNX2X_RX_MODE_ALLMULTI 2
1169 #define BNX2X_RX_MODE_PROMISC 3
1170 #define BNX2X_MAX_MULTICAST 64
1172 struct bnx2x_port port;
1174 struct cmng_init cmng;
1182 #define INTR_MODE_INTX 0
1183 #define INTR_MODE_MSI 1
1184 #define INTR_MODE_MSIX 2
1185 #define INTR_MODE_SINGLE_MSIX 3
1189 uint8_t igu_base_sb;
1191 uint32_t igu_base_addr;
1192 uint8_t base_fw_ndsb;
1193 #define DEF_SB_IGU_ID 16
1194 #define DEF_SB_ID HC_SP_SB_ID
1196 /* default status block */
1197 struct bnx2x_dma def_sb_dma;
1198 struct host_sp_status_block *def_sb;
1200 uint16_t def_att_idx;
1201 uint32_t attn_state;
1202 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
1204 /* general SP events - stats query, cfc delete, etc */
1205 #define HC_SP_INDEX_ETH_DEF_CONS 3
1206 /* EQ completions */
1207 #define HC_SP_INDEX_EQ_CONS 7
1208 /* FCoE L2 connection completions */
1209 #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6
1210 #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4
1212 #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5
1213 #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1
1216 struct bnx2x_dma eq_dma;
1217 union event_ring_elem *eq;
1220 uint16_t *eq_cons_sb;
1221 #define NUM_EQ_PAGES 1 /* must be a power of 2 */
1222 #define EQ_DESC_CNT_PAGE (BNX2X_PAGE_SIZE / sizeof(union event_ring_elem))
1223 #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1)
1224 #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES)
1225 #define EQ_DESC_MASK (NUM_EQ_DESC - 1)
1226 #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2)
1227 /* depends on EQ_DESC_CNT_PAGE being a power of 2 */
1228 #define NEXT_EQ_IDX(x) \
1229 ((((x) & EQ_DESC_MAX_PAGE) == (EQ_DESC_MAX_PAGE - 1)) ? \
1230 ((x) + 2) : ((x) + 1))
1231 /* depends on the above and on NUM_EQ_PAGES being a power of 2 */
1232 #define EQ_DESC(x) ((x) & EQ_DESC_MASK)
1235 struct bnx2x_dma sp_dma;
1236 struct bnx2x_slowpath *sp;
1237 unsigned long sp_state;
1239 /* slow path queue */
1240 struct bnx2x_dma spq_dma;
1241 struct eth_spe *spq;
1242 #define SP_DESC_CNT (BNX2X_PAGE_SIZE / sizeof(struct eth_spe))
1243 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
1244 #define MAX_SPQ_PENDING 8
1246 uint16_t spq_prod_idx;
1247 struct eth_spe *spq_prod_bd;
1248 struct eth_spe *spq_last_bd;
1249 uint16_t *dsb_sp_prod;
1251 volatile unsigned long eq_spq_left; /* COMMON_xxx ramrod credit */
1252 volatile unsigned long cq_spq_left; /* ETH_xxx ramrod credit */
1254 /* fw decompression buffer */
1255 struct bnx2x_dma gz_buf_dma;
1258 #define GUNZIP_BUF(sc) (sc->gz_buf)
1259 #define GUNZIP_OUTLEN(sc) (sc->gz_outlen)
1260 #define GUNZIP_PHYS(sc) (phys_addr_t)(sc->gz_buf_dma.paddr)
1261 #define FW_BUF_SIZE 0x40000
1263 struct raw_op *init_ops;
1264 uint16_t *init_ops_offsets; /* init block offsets inside init_ops */
1265 uint32_t *init_data; /* data blob, 32 bit granularity */
1266 uint32_t init_mode_flags;
1267 #define INIT_MODE_FLAGS(sc) (sc->init_mode_flags)
1268 /* PRAM blobs - raw data */
1269 const uint8_t *tsem_int_table_data;
1270 const uint8_t *tsem_pram_data;
1271 const uint8_t *usem_int_table_data;
1272 const uint8_t *usem_pram_data;
1273 const uint8_t *xsem_int_table_data;
1274 const uint8_t *xsem_pram_data;
1275 const uint8_t *csem_int_table_data;
1276 const uint8_t *csem_pram_data;
1277 #define INIT_OPS(sc) (sc->init_ops)
1278 #define INIT_OPS_OFFSETS(sc) (sc->init_ops_offsets)
1279 #define INIT_DATA(sc) (sc->init_data)
1280 #define INIT_TSEM_INT_TABLE_DATA(sc) (sc->tsem_int_table_data)
1281 #define INIT_TSEM_PRAM_DATA(sc) (sc->tsem_pram_data)
1282 #define INIT_USEM_INT_TABLE_DATA(sc) (sc->usem_int_table_data)
1283 #define INIT_USEM_PRAM_DATA(sc) (sc->usem_pram_data)
1284 #define INIT_XSEM_INT_TABLE_DATA(sc) (sc->xsem_int_table_data)
1285 #define INIT_XSEM_PRAM_DATA(sc) (sc->xsem_pram_data)
1286 #define INIT_CSEM_INT_TABLE_DATA(sc) (sc->csem_int_table_data)
1287 #define INIT_CSEM_PRAM_DATA(sc) (sc->csem_pram_data)
1289 #define PHY_FW_VER_LEN 20
1293 * For max 196 cids (64*3 + non-eth), 32KB ILT page size and 1KB
1294 * context size we need 8 ILT entries.
1296 #define ILT_MAX_L2_LINES 8
1297 struct hw_context context[ILT_MAX_L2_LINES];
1298 struct ecore_ilt *ilt;
1299 #define ILT_MAX_LINES 256
1301 /* max supported number of RSS queues: IGU SBs minus one for CNIC */
1302 #define BNX2X_MAX_RSS_COUNT(sc) ((sc)->igu_sb_cnt - CNIC_SUPPORT(sc))
1303 /* max CID count: Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI */
1304 #define BNX2X_L2_MAX_CID(sc) \
1305 (BNX2X_MAX_RSS_COUNT(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc))
1306 #define BNX2X_L2_CID_COUNT(sc) \
1307 (BNX2X_NUM_ETH_QUEUES(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc))
1308 #define L2_ILT_LINES(sc) \
1309 (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(sc), ILT_PAGE_CIDS))
1313 uint8_t dropless_fc;
1315 /* total number of FW statistics requests */
1316 uint8_t fw_stats_num;
1318 * This is a memory buffer that will contain both statistics ramrod
1321 struct bnx2x_dma fw_stats_dma;
1323 * FW statistics request shortcut (points at the beginning of fw_stats
1326 int fw_stats_req_size;
1327 struct bnx2x_fw_stats_req *fw_stats_req;
1328 phys_addr_t fw_stats_req_mapping;
1330 * FW statistics data shortcut (points at the beginning of fw_stats
1331 * buffer + fw_stats_req_size).
1333 int fw_stats_data_size;
1334 struct bnx2x_fw_stats_data *fw_stats_data;
1335 phys_addr_t fw_stats_data_mapping;
1337 /* tracking a pending STAT_QUERY ramrod */
1338 uint16_t stats_pending;
1339 /* number of completed statistics ramrods */
1340 uint16_t stats_comp;
1341 uint16_t stats_counter;
1345 struct bnx2x_eth_stats eth_stats;
1346 struct host_func_stats func_stats;
1347 struct bnx2x_eth_stats_old eth_stats_old;
1348 struct bnx2x_net_stats_old net_stats_old;
1349 struct bnx2x_fw_port_stats_old fw_stats_old;
1351 struct dmae_command stats_dmae; /* used by dmae command loader */
1356 /* DCB support on/off */
1358 #define BNX2X_DCB_STATE_OFF 0
1359 #define BNX2X_DCB_STATE_ON 1
1360 /* DCBX engine mode */
1362 #define BNX2X_DCBX_ENABLED_OFF 0
1363 #define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1
1364 #define BNX2X_DCBX_ENABLED_ON_NEG_ON 2
1365 #define BNX2X_DCBX_ENABLED_INVALID -1
1367 uint8_t cnic_support;
1368 uint8_t cnic_enabled;
1369 uint8_t cnic_loaded;
1370 #define CNIC_SUPPORT(sc) 0 /* ((sc)->cnic_support) */
1371 #define CNIC_ENABLED(sc) 0 /* ((sc)->cnic_enabled) */
1372 #define CNIC_LOADED(sc) 0 /* ((sc)->cnic_loaded) */
1374 /* multiple tx classes of service */
1376 #define BNX2X_MAX_PRIORITY 8
1377 /* priority to cos mapping */
1378 uint8_t prio_to_cos[BNX2X_MAX_PRIORITY];
1381 }; /* struct bnx2x_softc */
1383 /* IOCTL sub-commands for edebug and firmware upgrade */
1384 #define BNX2X_IOC_RD_NVRAM 1
1385 #define BNX2X_IOC_WR_NVRAM 2
1386 #define BNX2X_IOC_STATS_SHOW_NUM 3
1387 #define BNX2X_IOC_STATS_SHOW_STR 4
1388 #define BNX2X_IOC_STATS_SHOW_CNT 5
1390 struct bnx2x_nvram_data {
1391 uint32_t op; /* ioctl sub-command */
1394 uint32_t value[1]; /* variable */
1397 union bnx2x_stats_show_data {
1398 uint32_t op; /* ioctl sub-command */
1401 uint32_t num; /* return number of stats */
1402 uint32_t len; /* length of each string item */
1405 /* variable length... */
1406 char str[1]; /* holds names of desc.num stats, each desc.len in length */
1408 /* variable length... */
1409 uint64_t stats[1]; /* holds all stats */
1412 /* function init flags */
1413 #define FUNC_FLG_RSS 0x0001
1414 #define FUNC_FLG_STATS 0x0002
1415 /* FUNC_FLG_UNMATCHED 0x0004 */
1416 #define FUNC_FLG_SPQ 0x0010
1417 #define FUNC_FLG_LEADING 0x0020 /* PF only */
1419 struct bnx2x_func_init_params {
1420 phys_addr_t fw_stat_map; /* (dma) valid if FUNC_FLG_STATS */
1421 phys_addr_t spq_map; /* (dma) valid if FUNC_FLG_SPQ */
1423 uint16_t func_id; /* abs function id */
1425 uint16_t spq_prod; /* valid if FUNC_FLG_SPQ */
1428 /* memory resources reside at BARs 0, 2, 4 */
1429 /* Run `pciconf -lb` to see mappings */
1434 #ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
1435 uint8_t bnx2x_reg_read8(struct bnx2x_softc *sc, size_t offset);
1436 uint16_t bnx2x_reg_read16(struct bnx2x_softc *sc, size_t offset);
1437 uint32_t bnx2x_reg_read32(struct bnx2x_softc *sc, size_t offset);
1439 void bnx2x_reg_write8(struct bnx2x_softc *sc, size_t offset, uint8_t val);
1440 void bnx2x_reg_write16(struct bnx2x_softc *sc, size_t offset, uint16_t val);
1441 void bnx2x_reg_write32(struct bnx2x_softc *sc, size_t offset, uint32_t val);
1443 #define bnx2x_reg_write8(sc, offset, val)\
1444 *((volatile uint8_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val
1446 #define bnx2x_reg_write16(sc, offset, val)\
1447 *((volatile uint16_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val
1449 #define bnx2x_reg_write32(sc, offset, val)\
1450 *((volatile uint32_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val
1452 #define bnx2x_reg_read8(sc, offset)\
1453 (*((volatile uint8_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset)))
1455 #define bnx2x_reg_read16(sc, offset)\
1456 (*((volatile uint16_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset)))
1458 #define bnx2x_reg_read32(sc, offset)\
1459 (*((volatile uint32_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset)))
1462 #define REG_ADDR(sc, offset) (((uint64_t)sc->bar[BAR0].base_addr) + (offset))
1464 #define REG_RD8(sc, offset) bnx2x_reg_read8(sc, (offset))
1465 #define REG_RD16(sc, offset) bnx2x_reg_read16(sc, (offset))
1466 #define REG_RD32(sc, offset) bnx2x_reg_read32(sc, (offset))
1468 #define REG_WR8(sc, offset, val) bnx2x_reg_write8(sc, (offset), val)
1469 #define REG_WR16(sc, offset, val) bnx2x_reg_write16(sc, (offset), val)
1470 #define REG_WR32(sc, offset, val) bnx2x_reg_write32(sc, (offset), val)
1472 #define REG_RD(sc, offset) REG_RD32(sc, offset)
1473 #define REG_WR(sc, offset, val) REG_WR32(sc, offset, val)
1475 #define BNX2X_SP(sc, var) (&(sc)->sp->var)
1476 #define BNX2X_SP_MAPPING(sc, var) \
1477 (sc->sp_dma.paddr + offsetof(struct bnx2x_slowpath, var))
1479 #define BNX2X_FP(sc, nr, var) ((sc)->fp[(nr)].var)
1480 #define BNX2X_SP_OBJ(sc, fp) ((sc)->sp_objs[(fp)->index])
1482 #define bnx2x_fp(sc, nr, var) ((sc)->fp[nr].var)
1484 #define REG_RD_DMAE(sc, offset, valp, len32) \
1486 (void)bnx2x_read_dmae(sc, offset, len32); \
1487 (void)rte_memcpy(valp, BNX2X_SP(sc, wb_data[0]), (len32) * 4); \
1490 #define REG_WR_DMAE(sc, offset, valp, len32) \
1492 (void)rte_memcpy(BNX2X_SP(sc, wb_data[0]), valp, (len32) * 4); \
1493 (void)bnx2x_write_dmae(sc, BNX2X_SP_MAPPING(sc, wb_data), offset, len32); \
1496 #define REG_WR_DMAE_LEN(sc, offset, valp, len32) \
1497 REG_WR_DMAE(sc, offset, valp, len32)
1499 #define REG_RD_DMAE_LEN(sc, offset, valp, len32) \
1500 REG_RD_DMAE(sc, offset, valp, len32)
1502 #define VIRT_WR_DMAE_LEN(sc, data, addr, len32, le32_swap) \
1504 /* if (le32_swap) { */ \
1505 /* PMD_PWARN_LOG(sc, "VIRT_WR_DMAE_LEN with le32_swap=1"); */ \
1507 rte_memcpy(GUNZIP_BUF(sc), data, len32 * 4); \
1508 ecore_write_big_buf_wb(sc, addr, len32); \
1511 #define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */
1512 #define BNX2X_DB_SHIFT 7 /* 128 bytes */
1513 #if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT)
1514 #error "Minimum DB doorbell stride is 8"
1516 #define DPM_TRIGGER_TYPE 0x40
1518 /* Doorbell macro */
1519 #define BNX2X_DB_WRITE(db_bar, val) \
1520 *((volatile uint32_t *)(db_bar)) = (val)
1522 #define BNX2X_DB_READ(db_bar) \
1523 *((volatile uint32_t *)(db_bar))
1525 #define DOORBELL_ADDR(sc, offset) \
1526 (volatile uint32_t *)(((char *)(sc)->bar[BAR1].base_addr + (offset)))
1528 #define DOORBELL(sc, cid, val) \
1530 BNX2X_DB_WRITE((DOORBELL_ADDR(sc, sc->doorbell_size * (cid) + DPM_TRIGGER_TYPE)), (val)); \
1532 BNX2X_DB_WRITE((DOORBELL_ADDR(sc, sc->doorbell_size * (cid))), (val)) \
1534 #define SHMEM_ADDR(sc, field) \
1535 (sc->devinfo.shmem_base + offsetof(struct shmem_region, field))
1536 #define SHMEM_RD(sc, field) REG_RD(sc, SHMEM_ADDR(sc, field))
1537 #define SHMEM_RD16(sc, field) REG_RD16(sc, SHMEM_ADDR(sc, field))
1538 #define SHMEM_WR(sc, field, val) REG_WR(sc, SHMEM_ADDR(sc, field), val)
1540 #define SHMEM2_ADDR(sc, field) \
1541 (sc->devinfo.shmem2_base + offsetof(struct shmem2_region, field))
1542 #define SHMEM2_HAS(sc, field) \
1543 (sc->devinfo.shmem2_base && (REG_RD(sc, SHMEM2_ADDR(sc, size)) > \
1544 offsetof(struct shmem2_region, field)))
1545 #define SHMEM2_RD(sc, field) REG_RD(sc, SHMEM2_ADDR(sc, field))
1546 #define SHMEM2_WR(sc, field, val) REG_WR(sc, SHMEM2_ADDR(sc, field), val)
1548 #define MFCFG_ADDR(sc, field) \
1549 (sc->devinfo.mf_cfg_base + offsetof(struct mf_cfg, field))
1550 #define MFCFG_RD(sc, field) REG_RD(sc, MFCFG_ADDR(sc, field))
1551 #define MFCFG_RD16(sc, field) REG_RD16(sc, MFCFG_ADDR(sc, field))
1552 #define MFCFG_WR(sc, field, val) REG_WR(sc, MFCFG_ADDR(sc, field), val)
1554 /* DMAE command defines */
1556 #define DMAE_TIMEOUT -1
1557 #define DMAE_PCI_ERROR -2 /* E2 and onward */
1558 #define DMAE_NOT_RDY -3
1559 #define DMAE_PCI_ERR_FLAG 0x80000000
1561 #define DMAE_SRC_PCI 0
1562 #define DMAE_SRC_GRC 1
1564 #define DMAE_DST_NONE 0
1565 #define DMAE_DST_PCI 1
1566 #define DMAE_DST_GRC 2
1568 #define DMAE_COMP_PCI 0
1569 #define DMAE_COMP_GRC 1
1571 #define DMAE_COMP_REGULAR 0
1572 #define DMAE_COM_SET_ERR 1
1574 #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << DMAE_COMMAND_SRC_SHIFT)
1575 #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << DMAE_COMMAND_SRC_SHIFT)
1576 #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << DMAE_COMMAND_DST_SHIFT)
1577 #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << DMAE_COMMAND_DST_SHIFT)
1579 #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << DMAE_COMMAND_C_DST_SHIFT)
1580 #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << DMAE_COMMAND_C_DST_SHIFT)
1582 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
1583 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
1584 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
1585 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
1587 #define DMAE_CMD_PORT_0 0
1588 #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
1590 #define DMAE_SRC_PF 0
1591 #define DMAE_SRC_VF 1
1593 #define DMAE_DST_PF 0
1594 #define DMAE_DST_VF 1
1596 #define DMAE_C_SRC 0
1597 #define DMAE_C_DST 1
1599 #define DMAE_LEN32_RD_MAX 0x80
1600 #define DMAE_LEN32_WR_MAX(sc) 0x2000
1602 #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and beyond, upper bit indicates error */
1604 #define MAX_DMAE_C_PER_PORT 8
1605 #define INIT_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + SC_VN(sc))
1606 #define PMF_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + E1HVN_MAX)
1608 static const uint32_t dmae_reg_go_c[] = {
1609 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
1610 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
1611 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
1612 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
1615 #define ATTN_NIG_FOR_FUNC (1L << 8)
1616 #define ATTN_SW_TIMER_4_FUNC (1L << 9)
1617 #define GPIO_2_FUNC (1L << 10)
1618 #define GPIO_3_FUNC (1L << 11)
1619 #define GPIO_4_FUNC (1L << 12)
1620 #define ATTN_GENERAL_ATTN_1 (1L << 13)
1621 #define ATTN_GENERAL_ATTN_2 (1L << 14)
1622 #define ATTN_GENERAL_ATTN_3 (1L << 15)
1623 #define ATTN_GENERAL_ATTN_4 (1L << 13)
1624 #define ATTN_GENERAL_ATTN_5 (1L << 14)
1625 #define ATTN_GENERAL_ATTN_6 (1L << 15)
1626 #define ATTN_HARD_WIRED_MASK 0xff00
1627 #define ATTENTION_ID 4
1629 #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \
1630 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
1632 #define MAX_IGU_ATTN_ACK_TO 100
1634 #define STORM_ASSERT_ARRAY_SIZE 50
1636 #define BNX2X_PMF_LINK_ASSERT(sc) \
1637 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + SC_FUNC(sc))
1639 #define BNX2X_MC_ASSERT_BITS \
1640 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1641 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1642 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1643 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
1645 #define BNX2X_MCP_ASSERT \
1646 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
1648 #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
1649 #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
1650 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
1651 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
1652 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
1653 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
1654 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
1656 #define MULTI_MASK 0x7f
1658 #define PFS_PER_PORT(sc) \
1659 ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4)
1660 #define SC_MAX_VN_NUM(sc) PFS_PER_PORT(sc)
1662 #define FIRST_ABS_FUNC_IN_PORT(sc) \
1663 ((CHIP_PORT_MODE(sc) == CHIP_PORT_MODE_NONE) ? \
1664 PORT_ID(sc) : (PATH_ID(sc) + (2 * PORT_ID(sc))))
1666 #define FOREACH_ABS_FUNC_IN_PORT(sc, i) \
1667 for ((i) = FIRST_ABS_FUNC_IN_PORT(sc); \
1668 (i) < MAX_FUNC_NUM; \
1669 (i) += (MAX_FUNC_NUM / PFS_PER_PORT(sc)))
1671 #define BNX2X_SWCID_SHIFT 17
1672 #define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1)
1674 #define SW_CID(x) (le32toh(x) & BNX2X_SWCID_MASK)
1675 #define CQE_CMD(x) (le32toh(x) >> COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
1677 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
1678 #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG)
1679 #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG)
1680 #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD)
1681 #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH)
1683 /* must be used on a CID before placing it on a HW ring */
1684 #define HW_CID(sc, x) \
1685 ((SC_PORT(sc) << 23) | (SC_VN(sc) << BNX2X_SWCID_SHIFT) | (x))
1688 #define SPEED_100 100
1689 #define SPEED_1000 1000
1690 #define SPEED_2500 2500
1691 #define SPEED_10000 10000
1694 #define PCI_PM_D3hot 2
1696 int bnx2x_test_bit(int nr, volatile unsigned long * addr);
1697 void bnx2x_set_bit(unsigned int nr, volatile unsigned long * addr);
1698 void bnx2x_clear_bit(int nr, volatile unsigned long * addr);
1699 int bnx2x_test_and_clear_bit(int nr, volatile unsigned long * addr);
1700 int bnx2x_cmpxchg(volatile int *addr, int old, int new);
1702 int bnx2x_dma_alloc(struct bnx2x_softc *sc, size_t size,
1703 struct bnx2x_dma *dma, const char *msg, uint32_t align);
1705 uint32_t bnx2x_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type);
1706 uint32_t bnx2x_dmae_opcode_clr_src_reset(uint32_t opcode);
1707 uint32_t bnx2x_dmae_opcode(struct bnx2x_softc *sc, uint8_t src_type,
1708 uint8_t dst_type, uint8_t with_comp,
1710 void bnx2x_post_dmae(struct bnx2x_softc *sc, struct dmae_command *dmae, int idx);
1711 void bnx2x_read_dmae(struct bnx2x_softc *sc, uint32_t src_addr, uint32_t len32);
1712 void bnx2x_write_dmae(struct bnx2x_softc *sc, phys_addr_t dma_addr,
1713 uint32_t dst_addr, uint32_t len32);
1714 void bnx2x_set_ctx_validation(struct bnx2x_softc *sc, struct eth_context *cxt,
1716 void bnx2x_update_coalesce_sb_index(struct bnx2x_softc *sc, uint8_t fw_sb_id,
1717 uint8_t sb_index, uint8_t disable,
1720 int bnx2x_sp_post(struct bnx2x_softc *sc, int command, int cid,
1721 uint32_t data_hi, uint32_t data_lo, int cmd_type);
1723 void ecore_init_e1h_firmware(struct bnx2x_softc *sc);
1724 void ecore_init_e2_firmware(struct bnx2x_softc *sc);
1726 void ecore_storm_memset_struct(struct bnx2x_softc *sc, uint32_t addr,
1727 size_t size, uint32_t *data);
1729 #define CATC_TRIGGER(sc, data) REG_WR((sc), 0x2000, (data));
1730 #define CATC_TRIGGER_START(sc) CATC_TRIGGER((sc), 0xcafecafe)
1732 #define BNX2X_MAC_FMT "%pM"
1733 #define BNX2X_MAC_PRN_LIST(mac) (mac)
1739 static inline uint32_t
1740 reg_poll(struct bnx2x_softc *sc, uint32_t reg, uint32_t expected, int ms, int wait)
1744 val = REG_RD(sc, reg);
1745 if (val == expected) {
1756 bnx2x_update_fp_sb_idx(struct bnx2x_fastpath *fp)
1758 mb(); /* status block is written to by the chip */
1759 fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID];
1763 bnx2x_igu_ack_sb_gen(struct bnx2x_softc *sc, uint8_t segment,
1764 uint16_t index, uint8_t op, uint8_t update, uint32_t igu_addr)
1766 struct igu_regular cmd_data = {0};
1768 cmd_data.sb_id_and_flags =
1769 ((index << IGU_REGULAR_SB_INDEX_SHIFT) |
1770 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
1771 (update << IGU_REGULAR_BUPDATE_SHIFT) |
1772 (op << IGU_REGULAR_ENABLE_INT_SHIFT));
1774 REG_WR(sc, igu_addr, cmd_data.sb_id_and_flags);
1776 /* Make sure that ACK is written */
1781 bnx2x_hc_ack_sb(struct bnx2x_softc *sc, uint8_t sb_id, uint8_t storm,
1782 uint16_t index, uint8_t op, uint8_t update)
1784 uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc) * 32 +
1785 COMMAND_REG_INT_ACK);
1786 union igu_ack_register igu_ack;
1788 igu_ack.sb.status_block_index = index;
1789 igu_ack.sb.sb_id_and_flags =
1790 ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
1791 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
1792 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
1793 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
1795 REG_WR(sc, hc_addr, igu_ack.raw_data);
1797 /* Make sure that ACK is written */
1801 static inline uint32_t
1802 bnx2x_hc_ack_int(struct bnx2x_softc *sc)
1804 uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc) * 32 +
1805 COMMAND_REG_SIMD_MASK);
1806 uint32_t result = REG_RD(sc, hc_addr);
1812 static inline uint32_t
1813 bnx2x_igu_ack_int(struct bnx2x_softc *sc)
1815 uint32_t igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER * 8);
1816 uint32_t result = REG_RD(sc, igu_addr);
1818 /* PMD_PDEBUG_LOG(sc, DBG_INTR, "read 0x%08x from IGU addr 0x%x",
1819 result, igu_addr); */
1825 static inline uint32_t
1826 bnx2x_ack_int(struct bnx2x_softc *sc)
1829 if (sc->devinfo.int_block == INT_BLOCK_HC) {
1830 return bnx2x_hc_ack_int(sc);
1832 return bnx2x_igu_ack_int(sc);
1837 func_by_vn(struct bnx2x_softc *sc, int vn)
1839 return 2 * vn + SC_PORT(sc);
1843 * send notification to other functions.
1846 bnx2x_link_sync_notify(struct bnx2x_softc *sc)
1850 /* Set the attention towards other drivers on the same port */
1851 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
1852 if (vn == SC_VN(sc))
1855 func = func_by_vn(sc, vn);
1856 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_0 +
1857 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func) * 4, 1);
1862 * Statistics ID are global per chip/path, while Client IDs for E1x
1865 static inline uint8_t
1866 bnx2x_stats_id(struct bnx2x_fastpath *fp)
1868 struct bnx2x_softc *sc = fp->sc;
1870 if (!CHIP_IS_E1x(sc)) {
1874 return fp->cl_id + SC_PORT(sc) * FP_SB_MAX_E1x;
1877 int bnx2x_init(struct bnx2x_softc *sc);
1878 void bnx2x_load_firmware(struct bnx2x_softc *sc);
1879 int bnx2x_attach(struct bnx2x_softc *sc);
1880 int bnx2x_nic_unload(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link);
1881 int bnx2x_alloc_hsi_mem(struct bnx2x_softc *sc);
1882 int bnx2x_alloc_ilt_mem(struct bnx2x_softc *sc);
1883 void bnx2x_free_ilt_mem(struct bnx2x_softc *sc);
1884 void bnx2x_dump_tx_chain(struct bnx2x_fastpath * fp, int bd_prod, int count);
1885 int bnx2x_tx_encap(struct bnx2x_tx_queue *txq, struct rte_mbuf **m_head, int m_pkts);
1886 uint8_t bnx2x_txeof(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp);
1887 void bnx2x_print_adapter_info(struct bnx2x_softc *sc);
1888 int bnx2x_intr_legacy(struct bnx2x_softc *sc, int scan_fp);
1889 void bnx2x_link_status_update(struct bnx2x_softc *sc);
1890 int bnx2x_complete_sp(struct bnx2x_softc *sc);
1891 int bnx2x_set_storm_rx_mode(struct bnx2x_softc *sc);
1892 void bnx2x_periodic_callout(struct bnx2x_softc *sc);
1894 int bnx2x_vf_get_resources(struct bnx2x_softc *sc, uint8_t tx_count, uint8_t rx_count);
1895 void bnx2x_vf_close(struct bnx2x_softc *sc);
1896 int bnx2x_vf_init(struct bnx2x_softc *sc);
1897 void bnx2x_vf_unload(struct bnx2x_softc *sc);
1898 int bnx2x_vf_setup_queue(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
1900 void bnx2x_free_hsi_mem(struct bnx2x_softc *sc);
1901 int bnx2x_vf_set_rx_mode(struct bnx2x_softc *sc);
1902 int bnx2x_fill_accept_flags(struct bnx2x_softc *sc, uint32_t rx_mode,
1903 unsigned long *rx_accept_flags, unsigned long *tx_accept_flags);
1904 int bnx2x_check_bull(struct bnx2x_softc *sc);
1906 //#define BNX2X_PULSE
1908 #define BNX2X_PCI_CAP 1
1909 #define BNX2X_PCI_ECAP 2
1911 static inline struct bnx2x_pci_cap*
1912 pci_find_cap(struct bnx2x_softc *sc, uint8_t id, uint8_t type)
1914 struct bnx2x_pci_cap *cap = sc->pci_caps;
1917 if (cap->id == id && cap->type == type)
1925 static inline int is_valid_ether_addr(uint8_t *addr)
1927 if (!(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5]))
1934 bnx2x_set_rx_mode(struct bnx2x_softc *sc)
1936 if (sc->state == BNX2X_STATE_OPEN) {
1938 bnx2x_set_storm_rx_mode(sc);
1940 sc->rx_mode = BNX2X_RX_MODE_PROMISC;
1941 bnx2x_vf_set_rx_mode(sc);
1944 PMD_DRV_LOG(NOTICE, "Card is not ready to change mode");
1948 static inline int pci_read(struct bnx2x_softc *sc, size_t addr,
1949 void *val, uint8_t size)
1951 if (rte_eal_pci_read_config(sc->pci_dev, val, size, addr) <= 0) {
1952 PMD_DRV_LOG(ERR, "Can't read from PCI config space");
1959 static inline int pci_write_word(struct bnx2x_softc *sc, size_t addr, off_t val)
1961 uint16_t val16 = val;
1963 if (rte_eal_pci_write_config(sc->pci_dev, &val16,
1964 sizeof(val16), addr) <= 0) {
1965 PMD_DRV_LOG(ERR, "Can't write to PCI config space");
1972 static inline int pci_write_long(struct bnx2x_softc *sc, size_t addr, off_t val)
1974 uint32_t val32 = val;
1975 if (rte_eal_pci_write_config(sc->pci_dev, &val32,
1976 sizeof(val32), addr) <= 0) {
1977 PMD_DRV_LOG(ERR, "Can't write to PCI config space");
1984 #endif /* __BNX2X_H__ */