1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2007-2013 Broadcom Corporation.
4 * Eric Davis <edavis@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
6 * Gary Zambrano <zambrano@broadcom.com>
8 * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
9 * Copyright (c) 2015-2018 Cavium Inc.
10 * All rights reserved.
17 #include <rte_byteorder.h>
18 #include <rte_spinlock.h>
19 #include <rte_bus_pci.h>
22 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
23 #ifndef __LITTLE_ENDIAN
24 #define __LITTLE_ENDIAN RTE_LITTLE_ENDIAN
27 #elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN
29 #define __BIG_ENDIAN RTE_BIG_ENDIAN
31 #undef __LITTLE_ENDIAN
34 #include "bnx2x_ethdev.h"
35 #include "ecore_mfw_req.h"
36 #include "ecore_fw_defs.h"
37 #include "ecore_hsi.h"
38 #include "ecore_reg.h"
39 #include "bnx2x_stats.h"
40 #include "bnx2x_vfpf.h"
45 #include <linux/pci_regs.h>
47 #define PCIY_PMG PCI_CAP_ID_PM
48 #define PCIY_MSI PCI_CAP_ID_MSI
49 #define PCIY_EXPRESS PCI_CAP_ID_EXP
50 #define PCIY_MSIX PCI_CAP_ID_MSIX
51 #define PCIR_EXPRESS_DEVICE_STA PCI_EXP_TYPE_RC_EC
52 #define PCIM_EXP_STA_TRANSACTION_PND PCI_EXP_DEVSTA_TRPND
53 #define PCIR_EXPRESS_LINK_STA PCI_EXP_LNKSTA
54 #define PCIM_LINK_STA_WIDTH PCI_EXP_LNKSTA_NLW
55 #define PCIM_LINK_STA_SPEED PCI_EXP_LNKSTA_CLS
56 #define PCIR_EXPRESS_DEVICE_CTL PCI_EXP_DEVCTL
57 #define PCIM_EXP_CTL_MAX_PAYLOAD PCI_EXP_DEVCTL_PAYLOAD
58 #define PCIM_EXP_CTL_MAX_READ_REQUEST PCI_EXP_DEVCTL_READRQ
59 #define PCIR_POWER_STATUS PCI_PM_CTRL
60 #define PCIM_PSTAT_DMASK PCI_PM_CTRL_STATE_MASK
61 #define PCIM_PSTAT_PME PCI_PM_CTRL_PME_STATUS
62 #define PCIM_PSTAT_D3 0x3
63 #define PCIM_PSTAT_PMEENABLE PCI_PM_CTRL_PME_ENABLE
64 #define PCIR_MSIX_CTRL PCI_MSIX_FLAGS
65 #define PCIM_MSIXCTRL_TABLE_SIZE PCI_MSIX_FLAGS_QSIZE
67 #include <dev/pci/pcireg.h>
70 #define IFM_10G_CX4 20 /* 10GBase CX4 copper */
71 #define IFM_10G_TWINAX 22 /* 10GBase Twinax copper */
72 #define IFM_10G_T 26 /* 10GBase-T - RJ45 */
75 #define PCIR_EXPRESS_DEVICE_STA PCI_EXP_TYPE_RC_EC
76 #define PCIM_EXP_STA_TRANSACTION_PND PCI_EXP_DEVSTA_TRPND
77 #define PCIR_EXPRESS_LINK_STA PCI_EXP_LNKSTA
78 #define PCIM_LINK_STA_WIDTH PCI_EXP_LNKSTA_NLW
79 #define PCIM_LINK_STA_SPEED PCI_EXP_LNKSTA_CLS
80 #define PCIR_EXPRESS_DEVICE_CTL PCI_EXP_DEVCTL
81 #define PCIM_EXP_CTL_MAX_PAYLOAD PCI_EXP_DEVCTL_PAYLOAD
82 #define PCIM_EXP_CTL_MAX_READ_REQUEST PCI_EXP_DEVCTL_READRQ
84 #define PCIR_EXPRESS_DEVICE_STA PCIER_DEVICE_STA
85 #define PCIM_EXP_STA_TRANSACTION_PND PCIEM_STA_TRANSACTION_PND
86 #define PCIR_EXPRESS_LINK_STA PCIER_LINK_STA
87 #define PCIM_LINK_STA_WIDTH PCIEM_LINK_STA_WIDTH
88 #define PCIM_LINK_STA_SPEED PCIEM_LINK_STA_SPEED
89 #define PCIR_EXPRESS_DEVICE_CTL PCIER_DEVICE_CTL
90 #define PCIM_EXP_CTL_MAX_PAYLOAD PCIEM_CTL_MAX_PAYLOAD
91 #define PCIM_EXP_CTL_MAX_READ_REQUEST PCIEM_CTL_MAX_READ_REQUEST
95 #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
98 #define ARRSIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
101 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
104 #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
108 int bnx2x_ilog2(int x)
119 #define ilog2(x) bnx2x_ilog2(x)
122 #define BNX2X_BC_VER 0x040200
124 #include "ecore_sp.h"
126 struct bnx2x_device_type {
134 #define BNX2X_PAGE_SHIFT 12
135 #define BNX2X_PAGE_SIZE (1 << BNX2X_PAGE_SHIFT)
136 #define BNX2X_PAGE_MASK (~(BNX2X_PAGE_SIZE - 1))
137 #define BNX2X_PAGE_ALIGN(addr) ((addr + BNX2X_PAGE_SIZE - 1) & BNX2X_PAGE_MASK)
139 #if BNX2X_PAGE_SIZE != 4096
140 #error Page sizes other than 4KB are unsupported!
143 #define U64_LO(addr) ((uint32_t)(((uint64_t)(addr)) & 0xFFFFFFFF))
144 #define U64_HI(addr) ((uint32_t)(((uint64_t)(addr)) >> 32))
145 #define HILO_U64(hi, lo) ((((uint64_t)(hi)) << 32) + (lo))
147 /* dropless fc FW/HW related params */
148 #define BRB_SIZE(sc) (CHIP_IS_E3(sc) ? 1024 : 512)
149 #define MAX_AGG_QS(sc) ETH_MAX_AGGREGATION_QUEUES_E1H_E2
150 #define FW_DROP_LEVEL(sc) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(sc))
151 #define FW_PREFETCH_CNT 16U
152 #define DROPLESS_FC_HEADROOM 100
155 * Transmit Buffer Descriptor (tx_bd) definitions*
157 /* NUM_TX_PAGES must be a power of 2. */
158 #define NUM_TX_PAGES 16
159 #define TOTAL_TX_BD_PER_PAGE (BNX2X_PAGE_SIZE / sizeof(union eth_tx_bd_types)) /* 256 */
160 #define USABLE_TX_BD_PER_PAGE (TOTAL_TX_BD_PER_PAGE - 1) /* 255 */
162 #define TOTAL_TX_BD(q) (TOTAL_TX_BD_PER_PAGE * q->nb_tx_pages) /* 512 */
163 #define USABLE_TX_BD(q) (USABLE_TX_BD_PER_PAGE * q->nb_tx_pages) /* 510 */
164 #define MAX_TX_BD(q) (TOTAL_TX_BD(q) - 1) /* 511 */
165 #define MAX_TX_AVAIL (USABLE_TX_BD_PER_PAGE * NUM_TX_PAGES - 2)
166 #define NEXT_TX_BD(x) \
167 ((((x) & USABLE_TX_BD_PER_PAGE) == \
168 (USABLE_TX_BD_PER_PAGE - 1)) ? (x) + 2 : (x) + 1)
170 #define TX_BD(x, q) ((x) & MAX_TX_BD(q))
171 #define TX_PAGE(x) (((x) & ~USABLE_TX_BD_PER_PAGE) >> 8)
172 #define TX_IDX(x) ((x) & USABLE_TX_BD_PER_PAGE)
174 #define BDS_PER_TX_PKT (3)
177 * Trigger pending transmits when the number of available BDs is greater
178 * than 1/8 of the total number of usable BDs.
180 #define BNX2X_TX_CLEANUP_THRESHOLD(q) (USABLE_TX_BD(q) / 8)
181 #define BNX2X_TX_TIMEOUT 5
184 * Receive Buffer Descriptor (rx_bd) definitions*
186 #define MAX_RX_PAGES 8
187 #define TOTAL_RX_BD_PER_PAGE (BNX2X_PAGE_SIZE / sizeof(struct eth_rx_bd)) /* 512 */
188 #define USABLE_RX_BD_PER_PAGE (TOTAL_RX_BD_PER_PAGE - 2) /* 510 */
189 #define RX_BD_PER_PAGE_MASK (TOTAL_RX_BD_PER_PAGE - 1) /* 511 */
190 #define TOTAL_RX_BD(q) (TOTAL_RX_BD_PER_PAGE * q->nb_rx_pages) /* 512 */
191 #define USABLE_RX_BD(q) (USABLE_RX_BD_PER_PAGE * q->nb_rx_pages) /* 510 */
192 #define MAX_RX_BD(q) (TOTAL_RX_BD(q) - 1) /* 511 */
193 #define MAX_RX_AVAIL (USABLE_RX_BD_PER_PAGE * MAX_RX_PAGES - 2)
194 #define RX_BD_NEXT_PAGE_DESC_CNT 2
196 #define NEXT_RX_BD(x) \
197 ((((x) & RX_BD_PER_PAGE_MASK) == \
198 (USABLE_RX_BD_PER_PAGE - 1)) ? (x) + 3 : (x) + 1)
201 #define RX_BD(x, q) ((x) & MAX_RX_BD(q))
202 #define RX_PAGE(x) (((x) & ~RX_BD_PER_PAGE_MASK) >> 9)
203 #define RX_IDX(x) ((x) & RX_BD_PER_PAGE_MASK)
206 * Receive Completion Queue definitions*
208 //#define NUM_RCQ_PAGES (NUM_RX_PAGES * 4)
209 #define TOTAL_RCQ_ENTRIES_PER_PAGE (BNX2X_PAGE_SIZE / sizeof(union eth_rx_cqe)) /* 128 */
210 #define USABLE_RCQ_ENTRIES_PER_PAGE (TOTAL_RCQ_ENTRIES_PER_PAGE - 1) /* 127 */
211 #define TOTAL_RCQ_ENTRIES(q) (TOTAL_RCQ_ENTRIES_PER_PAGE * q->nb_cq_pages) /* 512 */
212 #define USABLE_RCQ_ENTRIES(q) (USABLE_RCQ_ENTRIES_PER_PAGE * q->nb_cq_pages) /* 508 */
213 #define MAX_RCQ_ENTRIES(q) (TOTAL_RCQ_ENTRIES(q) - 1) /* 511 */
214 #define RCQ_NEXT_PAGE_DESC_CNT 1
216 #define NEXT_RCQ_IDX(x) \
217 ((((x) & USABLE_RCQ_ENTRIES_PER_PAGE) == \
218 (USABLE_RCQ_ENTRIES_PER_PAGE - 1)) ? (x) + 2 : (x) + 1)
221 (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd))
223 #define RCQ_BD_PAGES(q) \
224 (q->nb_rx_pages * CQE_BD_REL)
226 #define RCQ_ENTRY(x, q) ((x) & MAX_RCQ_ENTRIES(q))
227 #define RCQ_PAGE(x) (((x) & ~USABLE_RCQ_ENTRIES_PER_PAGE) >> 7)
228 #define RCQ_IDX(x) ((x) & USABLE_RCQ_ENTRIES_PER_PAGE)
231 * dropless fc calculations for BDs
232 * Number of BDs should be as number of buffers in BRB:
233 * Low threshold takes into account RX_BD_NEXT_PAGE_DESC_CNT
234 * "next" elements on each page
236 #define NUM_BD_REQ(sc) \
238 #define NUM_BD_PG_REQ(sc) \
239 ((NUM_BD_REQ(sc) + USABLE_RX_BD_PER_PAGE - 1) / USABLE_RX_BD_PER_PAGE)
240 #define BD_TH_LO(sc) \
242 NUM_BD_PG_REQ(sc) * RX_BD_NEXT_PAGE_DESC_CNT + \
244 #define BD_TH_HI(sc) \
245 (BD_TH_LO(sc) + DROPLESS_FC_HEADROOM)
246 #define MIN_RX_AVAIL(sc) \
247 ((sc)->dropless_fc ? BD_TH_HI(sc) + 128 : 128)
249 #define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA
250 #define MIN_RX_SIZE_NONTPA (RTE_MAX((uint32_t)MIN_RX_SIZE_NONTPA_HW,\
251 (uint32_t)MIN_RX_AVAIL(sc)))
254 * dropless fc calculations for RCQs
255 * Number of RCQs should be as number of buffers in BRB:
256 * Low threshold takes into account RCQ_NEXT_PAGE_DESC_CNT
257 * "next" elements on each page
259 #define NUM_RCQ_REQ(sc) \
261 #define NUM_RCQ_PG_REQ(sc) \
262 ((NUM_RCQ_REQ(sc) + USABLE_RCQ_ENTRIES_PER_PAGE - 1) / USABLE_RCQ_ENTRIES_PER_PAGE)
263 #define RCQ_TH_LO(sc) \
265 NUM_RCQ_PG_REQ(sc) * RCQ_NEXT_PAGE_DESC_CNT + \
267 #define RCQ_TH_HI(sc) \
268 (RCQ_TH_LO(sc) + DROPLESS_FC_HEADROOM)
270 /* Load / Unload modes */
271 #define LOAD_NORMAL 0
274 #define LOAD_LOOPBACK_EXT 3
275 #define UNLOAD_NORMAL 0
276 #define UNLOAD_CLOSE 1
277 #define UNLOAD_RECOVERY 2
279 /* Some constants... */
280 //#define MAX_PATH_NUM 2
281 //#define E2_MAX_NUM_OF_VFS 64
282 //#define E1H_FUNC_MAX 8
283 //#define E2_FUNC_MAX 4 /* per path */
284 #define MAX_VNIC_NUM 4
285 #define MAX_FUNC_NUM 8 /* common to all chips */
286 //#define MAX_NDSB HC_SB_MAX_SB_E2 /* max non-default status block */
287 #define MAX_RSS_CHAINS 16 /* a constant for HW limit */
288 #define MAX_MSI_VECTOR 8 /* a constant for HW limit */
290 #define ILT_NUM_PAGE_ENTRIES 3072
292 * 57711 we use whole table since we have 8 functions.
293 * 57712 we have only 4 functions, but use same size per func, so only half
294 * of the table is used.
296 #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES / 8)
297 #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC)
299 * the phys address is shifted right 12 bits and has an added
300 * 1=valid bit added to the 53rd bit
301 * then since this is a wide register(TM)
302 * we split it into two 32 bit writes
304 #define ONCHIP_ADDR1(x) ((uint32_t)(((uint64_t)x >> 12) & 0xFFFFFFFF))
305 #define ONCHIP_ADDR2(x) ((uint32_t)((1 << 20) | ((uint64_t)x >> 44)))
307 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
309 #define ETH_OVERHEAD (ETH_HLEN + 8 + 8)
310 #define ETH_MIN_PACKET_SIZE 60
311 #define ETH_MAX_PACKET_SIZE ETHERMTU /* 1500 */
312 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
313 /* TCP with Timestamp Option (32) + IPv6 (40) */
315 /* max supported alignment is 256 (8 shift) */
316 #define BNX2X_RX_ALIGN_SHIFT RTE_MAX(6, min(8, RTE_CACHE_LINE_SIZE_LOG2))
318 #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5)
324 /* Used to manage DMA allocations. */
326 struct bnx2x_softc *sc;
331 char msg[RTE_MEMZONE_NAMESIZE - 6];
334 /* attn group wiring */
335 #define MAX_DYNAMIC_ATTN_GRPS 8
349 union bnx2x_host_hc_status_block {
350 /* pointer to fp status block e2 */
351 struct host_hc_status_block_e2 *e2_sb;
352 /* pointer to fp status block e1x */
353 struct host_hc_status_block_e1x *e1x_sb;
356 union bnx2x_db_prod {
357 struct doorbell_set_prod data;
361 struct bnx2x_sw_tx_bd {
365 /* set on the first BD descriptor when there is a split BD */
366 #define BNX2X_TSO_SPLIT_BD (1 << 0)
370 * This is the HSI fastpath data structure. There can be up to MAX_RSS_CHAIN
371 * instances of the fastpath structure when using multiple queues.
373 struct bnx2x_fastpath {
374 /* pointer back to parent structure */
375 struct bnx2x_softc *sc;
378 struct bnx2x_dma sb_dma;
379 union bnx2x_host_hc_status_block status_block;
381 rte_iova_t tx_desc_mapping;
383 rte_iova_t rx_desc_mapping;
384 rte_iova_t rx_comp_mapping;
386 uint16_t *sb_index_values;
387 uint16_t *sb_running_index;
388 uint32_t ustorm_rx_prods_offset;
390 uint8_t igu_sb_id; /* status block number in HW */
391 uint8_t fw_sb_id; /* status block number in FW */
393 uint32_t rx_buf_size;
396 #define BNX2X_FP_STATE_CLOSED 0x01
397 #define BNX2X_FP_STATE_IRQ 0x02
398 #define BNX2X_FP_STATE_OPENING 0x04
399 #define BNX2X_FP_STATE_OPEN 0x08
400 #define BNX2X_FP_STATE_HALTING 0x10
401 #define BNX2X_FP_STATE_HALTED 0x20
403 /* reference back to this fastpath queue number */
404 uint8_t index; /* this is also the 'cid' */
405 #define FP_IDX(fp) (fp->index)
407 /* ethernet client ID (each fastpath set of RX/TX/CQE is a client) */
409 #define FP_CL_ID(fp) (fp->cl_id)
414 union bnx2x_db_prod tx_db;
416 struct tstorm_per_queue_stats old_tclient;
417 struct ustorm_per_queue_stats old_uclient;
418 struct xstorm_per_queue_stats old_xclient;
419 struct bnx2x_eth_q_stats eth_q_stats;
420 struct bnx2x_eth_q_stats_old eth_q_stats_old;
422 /* Pointer to the receive consumer in the status block */
423 uint16_t *rx_cq_cons_sb;
425 /* Pointer to the transmit consumer in the status block */
426 uint16_t *tx_cons_sb;
428 /* transmit timeout until chip reset */
431 }; /* struct bnx2x_fastpath */
433 #define BNX2X_MAX_NUM_OF_VFS 64
434 #define BNX2X_VF_ID_INVALID 0xFF
436 /* maximum number of fast-path interrupt contexts */
437 #define FP_SB_MAX_E1x 16
438 #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2
441 struct eth_context eth;
445 /* CDU host DB constants */
446 #define CDU_ILT_PAGE_SZ_HW 2
447 #define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */
448 #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context))
450 #define CNIC_ISCSI_CID_MAX 256
451 #define CNIC_FCOE_CID_MAX 2048
452 #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX)
453 #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS)
455 #define QM_ILT_PAGE_SZ_HW 0
456 #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */
457 #define QM_CID_ROUND 1024
459 /* TM (timers) host DB constants */
460 #define TM_ILT_PAGE_SZ_HW 0
461 #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */
462 /*#define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */
463 #define TM_CONN_NUM 1024
464 #define TM_ILT_SZ (8 * TM_CONN_NUM)
465 #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ)
467 /* SRC (Searcher) host DB constants */
468 #define SRC_ILT_PAGE_SZ_HW 0
469 #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */
470 #define SRC_HASH_BITS 10
471 #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */
472 #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM)
473 #define SRC_T2_SZ SRC_ILT_SZ
474 #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ)
477 struct bnx2x_dma vcxt_dma;
478 union cdu_context *vcxt;
479 //rte_iova_t cxt_mapping;
486 /* defines for multiple tx priority indices */
487 #define FIRST_TX_ONLY_COS_INDEX 1
488 #define FIRST_TX_COS_INDEX 0
490 #define CID_TO_FP(cid, sc) ((cid) % BNX2X_NUM_NON_CNIC_QUEUES(sc))
492 #define HC_INDEX_ETH_RX_CQ_CONS 1
493 #define HC_INDEX_OOO_TX_CQ_CONS 4
494 #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5
495 #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6
496 #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7
497 #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0
499 /* congestion management fairness mode */
500 #define CMNG_FNS_NONE 0
501 #define CMNG_FNS_MINMAX 1
503 /* CMNG constants, as derived from system spec calculations */
504 /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */
505 #define DEF_MIN_RATE 100
506 /* resolution of the rate shaping timer - 400 usec */
507 #define RS_PERIODIC_TIMEOUT_USEC 400
508 /* number of bytes in single QM arbitration cycle -
509 * coefficient for calculating the fairness timer */
510 #define QM_ARB_BYTES 160000
511 /* resolution of Min algorithm 1:100 */
513 /* how many bytes above threshold for the minimal credit of Min algorithm*/
514 #define MIN_ABOVE_THRESH 32768
515 /* fairness algorithm integration time coefficient -
516 * for calculating the actual Tfair */
517 #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES)
518 /* memory of fairness algorithm - 2 cycles */
521 #define HC_SEG_ACCESS_DEF 0 /* Driver decision 0-3 */
522 #define HC_SEG_ACCESS_ATTN 4
523 #define HC_SEG_ACCESS_NORM 0 /* Driver decision 0-1 */
526 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is
527 * control by the number of fast-path status blocks supported by the
528 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default
529 * status block represents an independent interrupts context that can
530 * serve a regular L2 networking queue. However special L2 queues such
531 * as the FCoE queue do not require a FP-SB and other components like
532 * the CNIC may consume FP-SB reducing the number of possible L2 queues
534 * If the maximum number of FP-SB available is X then:
535 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of
536 * regular L2 queues is Y=X-1
537 * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor)
538 * c. If the FCoE L2 queue is supported the actual number of L2 queues
540 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for
541 * slow-path interrupts) or Y+2 if CNIC is supported (one additional
542 * FP interrupt context for the CNIC).
543 * e. The number of HW context (CID count) is always X or X+1 if FCoE
544 * L2 queue is supported. the cid for the FCoE L2 queue is always X.
546 * So this is quite simple for now as no ULPs are supported yet. :-)
548 #define BNX2X_NUM_QUEUES(sc) ((sc)->num_queues)
549 #define BNX2X_NUM_ETH_QUEUES(sc) BNX2X_NUM_QUEUES(sc)
550 #define BNX2X_NUM_NON_CNIC_QUEUES(sc) BNX2X_NUM_QUEUES(sc)
551 #define BNX2X_NUM_RX_QUEUES(sc) BNX2X_NUM_QUEUES(sc)
553 #define FOR_EACH_QUEUE(sc, var) \
554 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(sc); (var)++)
556 #define FOR_EACH_NONDEFAULT_QUEUE(sc, var) \
557 for ((var) = 1; (var) < BNX2X_NUM_QUEUES(sc); (var)++)
559 #define FOR_EACH_ETH_QUEUE(sc, var) \
560 for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(sc); (var)++)
562 #define FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, var) \
563 for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(sc); (var)++)
565 #define FOR_EACH_COS_IN_TX_QUEUE(sc, var) \
566 for ((var) = 0; (var) < (sc)->max_cos; (var)++)
568 #define FOR_EACH_CNIC_QUEUE(sc, var) \
569 for ((var) = BNX2X_NUM_ETH_QUEUES(sc); \
570 (var) < BNX2X_NUM_QUEUES(sc); \
579 #define FCOE_IDX(sc) (BNX2X_NUM_NON_CNIC_QUEUES(sc) + FCOE_IDX_OFFSET)
580 #define bnx2x_fcoe_fp(sc) (&sc->fp[FCOE_IDX(sc)])
581 #define bnx2x_fcoe(sc, var) (bnx2x_fcoe_fp(sc)->var)
582 #define bnx2x_fcoe_inner_sp_obj(sc) (&sc->sp_objs[FCOE_IDX(sc)])
583 #define bnx2x_fcoe_sp_obj(sc, var) (bnx2x_fcoe_inner_sp_obj(sc)->var)
584 #define bnx2x_fcoe_tx(sc, var) (bnx2x_fcoe_fp(sc)->txdata_ptr[FIRST_TX_COS_INDEX]->var)
586 #define OOO_IDX(sc) (BNX2X_NUM_NON_CNIC_QUEUES(sc) + OOO_IDX_OFFSET)
587 #define bnx2x_ooo_fp(sc) (&sc->fp[OOO_IDX(sc)])
588 #define bnx2x_ooo(sc, var) (bnx2x_ooo_fp(sc)->var)
589 #define bnx2x_ooo_inner_sp_obj(sc) (&sc->sp_objs[OOO_IDX(sc)])
590 #define bnx2x_ooo_sp_obj(sc, var) (bnx2x_ooo_inner_sp_obj(sc)->var)
592 #define FWD_IDX(sc) (BNX2X_NUM_NON_CNIC_QUEUES(sc) + FWD_IDX_OFFSET)
593 #define bnx2x_fwd_fp(sc) (&sc->fp[FWD_IDX(sc)])
594 #define bnx2x_fwd(sc, var) (bnx2x_fwd_fp(sc)->var)
595 #define bnx2x_fwd_inner_sp_obj(sc) (&sc->sp_objs[FWD_IDX(sc)])
596 #define bnx2x_fwd_sp_obj(sc, var) (bnx2x_fwd_inner_sp_obj(sc)->var)
597 #define bnx2x_fwd_txdata(fp) (fp->txdata_ptr[FIRST_TX_COS_INDEX])
599 #define IS_ETH_FP(fp) ((fp)->index < BNX2X_NUM_ETH_QUEUES((fp)->sc))
600 #define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->sc))
601 #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(sc))
602 #define IS_FWD_FP(fp) ((fp)->index == FWD_IDX((fp)->sc))
603 #define IS_FWD_IDX(idx) ((idx) == FWD_IDX(sc))
604 #define IS_OOO_FP(fp) ((fp)->index == OOO_IDX((fp)->sc))
605 #define IS_OOO_IDX(idx) ((idx) == OOO_IDX(sc))
608 BNX2X_PORT_QUERY_IDX,
610 BNX2X_FCOE_QUERY_IDX,
611 BNX2X_FIRST_QUEUE_QUERY_IDX,
614 struct bnx2x_fw_stats_req {
615 struct stats_query_header hdr;
616 struct stats_query_entry query[FP_SB_MAX_E1x +
617 BNX2X_FIRST_QUEUE_QUERY_IDX];
620 struct bnx2x_fw_stats_data {
621 struct stats_counter storm_counters;
622 struct per_port_stats port;
623 struct per_pf_stats pf;
624 struct per_queue_stats queue_stats[1];
627 /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */
628 #define BNX2X_IGU_STAS_MSG_VF_CNT 64
629 #define BNX2X_IGU_STAS_MSG_PF_CNT 4
634 * This is the slowpath data structure. It is mapped into non-paged memory
635 * so that the hardware can access it's contents directly and must be page
638 struct bnx2x_slowpath {
640 /* used by the DMAE command executer */
641 struct dmae_command dmae[MAX_DMAE_C];
643 /* statistics completion */
646 /* firmware defined statistics blocks */
647 union mac_stats mac_stats;
648 struct nig_stats nig_stats;
649 struct host_port_stats port_stats;
650 struct host_func_stats func_stats;
652 /* DMAE completion value and data source/sink */
657 struct mac_configuration_cmd e1x;
658 struct eth_classify_rules_ramrod_data e2;
662 struct tstorm_eth_mac_filter_config e1x;
663 struct eth_filter_rules_ramrod_data e2;
666 struct eth_rss_update_ramrod_data rss_rdata;
669 struct mac_configuration_cmd e1;
670 struct eth_multicast_rules_ramrod_data e2;
674 struct function_start_data func_start;
675 struct flow_control_configuration pfc_config; /* for DCBX ramrod */
678 /* Queue State related ramrods */
680 struct client_init_ramrod_data init_data;
681 struct client_update_ramrod_data update_data;
685 * AFEX ramrod can not be a part of func_rdata union because these
686 * events might arrive in parallel to other events from func_rdata.
687 * If they were defined in the same union the data can get corrupted.
689 struct afex_vif_list_ramrod_data func_afex_rdata;
691 union drv_info_to_mcp drv_info_to_mcp;
692 }; /* struct bnx2x_slowpath */
695 * Port specifc data structure.
699 * Port Management Function (for 57711E only).
700 * When this field is set the driver instance is
701 * responsible for managing port specifc
702 * configurations such as handling link attentions.
706 /* Ethernet maximum transmission unit. */
709 uint32_t link_config[ELINK_LINK_CONFIG_SIZE];
711 uint32_t ext_phy_config;
713 /* Port feature config.*/
716 /* Defines the features supported by the PHY. */
717 uint32_t supported[ELINK_LINK_CONFIG_SIZE];
719 /* Defines the features advertised by the PHY. */
720 uint32_t advertising[ELINK_LINK_CONFIG_SIZE];
721 #define ADVERTISED_10baseT_Half (1 << 1)
722 #define ADVERTISED_10baseT_Full (1 << 2)
723 #define ADVERTISED_100baseT_Half (1 << 3)
724 #define ADVERTISED_100baseT_Full (1 << 4)
725 #define ADVERTISED_1000baseT_Half (1 << 5)
726 #define ADVERTISED_1000baseT_Full (1 << 6)
727 #define ADVERTISED_TP (1 << 7)
728 #define ADVERTISED_FIBRE (1 << 8)
729 #define ADVERTISED_Autoneg (1 << 9)
730 #define ADVERTISED_Asym_Pause (1 << 10)
731 #define ADVERTISED_Pause (1 << 11)
732 #define ADVERTISED_2500baseX_Full (1 << 15)
733 #define ADVERTISED_10000baseT_Full (1 << 16)
737 /* Used to synchronize phy accesses. */
738 rte_spinlock_t phy_mtx;
739 char phy_mtx_name[32];
741 #define BNX2X_PHY_LOCK(sc) rte_spinlock_lock(&sc->port.phy_mtx)
742 #define BNX2X_PHY_UNLOCK(sc) rte_spinlock_unlock(&sc->port.phy_mtx)
745 * MCP scratchpad address for port specific statistics.
746 * The device is responsible for writing statistcss
747 * back to the MCP for use with management firmware such
752 struct nig_stats old_nig_stats;
753 }; /* struct bnx2x_port */
755 struct bnx2x_mf_info {
756 uint32_t mf_config[E1HVN_MAX];
758 uint32_t vnics_per_port; /* 1, 2 or 4 */
759 uint32_t multi_vnics_mode; /* can be set even if vnics_per_port = 1 */
760 uint32_t path_has_ovlan; /* MF mode in the path (can be different than the MF mode of the function */
762 #define IS_MULTI_VNIC(sc) ((sc)->devinfo.mf_info.multi_vnics_mode)
763 #define VNICS_PER_PORT(sc) ((sc)->devinfo.mf_info.vnics_per_port)
764 #define VNICS_PER_PATH(sc) \
765 ((sc)->devinfo.mf_info.vnics_per_port * \
766 ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 1 ))
768 uint8_t min_bw[MAX_VNIC_NUM];
769 uint8_t max_bw[MAX_VNIC_NUM];
771 uint16_t ext_id; /* vnic outer vlan or VIF ID */
772 #define VALID_OVLAN(ovlan) ((ovlan) <= 4096)
773 #define INVALID_VIF_ID 0xFFFF
774 #define OVLAN(sc) ((sc)->devinfo.mf_info.ext_id)
775 #define VIF_ID(sc) ((sc)->devinfo.mf_info.ext_id)
777 uint16_t default_vlan;
778 #define NIV_DEFAULT_VLAN(sc) ((sc)->devinfo.mf_info.default_vlan)
780 uint8_t niv_allowed_priorities;
781 #define NIV_ALLOWED_PRIORITIES(sc) ((sc)->devinfo.mf_info.niv_allowed_priorities)
783 uint8_t niv_default_cos;
784 #define NIV_DEFAULT_COS(sc) ((sc)->devinfo.mf_info.niv_default_cos)
786 uint8_t niv_mba_enabled;
788 enum mf_cfg_afex_vlan_mode afex_vlan_mode;
789 #define AFEX_VLAN_MODE(sc) ((sc)->devinfo.mf_info.afex_vlan_mode)
790 int afex_def_vlan_tag;
791 uint32_t pending_max;
794 #define MF_INFO_VALID_MAC 0x0001
797 uint8_t mf_mode; /* Switch-Dependent or Switch-Independent */
799 (IS_MULTI_VNIC(sc) && \
800 ((sc)->devinfo.mf_info.mf_mode != 0))
801 #define IS_MF_SD(sc) \
802 (IS_MULTI_VNIC(sc) && \
803 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SD))
804 #define IS_MF_SI(sc) \
805 (IS_MULTI_VNIC(sc) && \
806 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SI))
807 #define IS_MF_AFEX(sc) \
808 (IS_MULTI_VNIC(sc) && \
809 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_AFEX))
810 #define IS_MF_SD_MODE(sc) IS_MF_SD(sc)
811 #define IS_MF_SI_MODE(sc) IS_MF_SI(sc)
812 #define IS_MF_AFEX_MODE(sc) IS_MF_AFEX(sc)
814 uint32_t mf_protos_supported;
815 #define MF_PROTO_SUPPORT_ETHERNET 0x1
816 #define MF_PROTO_SUPPORT_ISCSI 0x2
817 #define MF_PROTO_SUPPORT_FCOE 0x4
818 }; /* struct bnx2x_mf_info */
820 /* Device information data structure. */
821 struct bnx2x_devinfo {
823 #define NAME_SIZE 128
824 char name[NAME_SIZE];
829 uint16_t subvendor_id;
830 uint16_t subdevice_id;
833 * chip_id = 0b'CCCCCCCCCCCCCCCCRRRRMMMMMMMMBBBB'
834 * C = Chip Number (bits 16-31)
835 * R = Chip Revision (bits 12-15)
836 * M = Chip Metal (bits 4-11)
837 * B = Chip Bond ID (bits 0-3)
840 #define CHIP_ID(sc) ((sc)->devinfo.chip_id & 0xffff0000)
841 #define CHIP_NUM(sc) ((sc)->devinfo.chip_id >> 16)
843 #define CHIP_NUM_57710 0x164e
844 #define CHIP_NUM_57711 0x164f
845 #define CHIP_NUM_57711E 0x1650
846 #define CHIP_NUM_57712 0x1662
847 #define CHIP_NUM_57712_MF 0x1663
848 #define CHIP_NUM_57712_VF 0x166f
849 #define CHIP_NUM_57800 0x168a
850 #define CHIP_NUM_57800_MF 0x16a5
851 #define CHIP_NUM_57800_VF 0x16a9
852 #define CHIP_NUM_57810 0x168e
853 #define CHIP_NUM_57810_MF 0x16ae
854 #define CHIP_NUM_57810_VF 0x16af
855 #define CHIP_NUM_57811 0x163d
856 #define CHIP_NUM_57811_MF 0x163e
857 #define CHIP_NUM_57811_VF 0x163f
858 #define CHIP_NUM_57840_OBS 0x168d
859 #define CHIP_NUM_57840_OBS_MF 0x16ab
860 #define CHIP_NUM_57840_4_10 0x16a1
861 #define CHIP_NUM_57840_2_20 0x16a2
862 #define CHIP_NUM_57840_MF 0x16a4
863 #define CHIP_NUM_57840_VF 0x16ad
865 #define CHIP_REV_SHIFT 12
866 #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT)
867 #define CHIP_REV(sc) ((sc)->devinfo.chip_id & CHIP_REV_MASK)
869 #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT)
870 #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT)
871 #define CHIP_REV_Cx (0x2 << CHIP_REV_SHIFT)
873 #define CHIP_REV_IS_SLOW(sc) \
874 (CHIP_REV(sc) > 0x00005000)
875 #define CHIP_REV_IS_FPGA(sc) \
876 (CHIP_REV_IS_SLOW(sc) && (CHIP_REV(sc) & 0x00001000))
877 #define CHIP_REV_IS_EMUL(sc) \
878 (CHIP_REV_IS_SLOW(sc) && !(CHIP_REV(sc) & 0x00001000))
879 #define CHIP_REV_IS_ASIC(sc) \
880 (!CHIP_REV_IS_SLOW(sc))
882 #define CHIP_METAL(sc) ((sc->devinfo.chip_id) & 0x00000ff0)
883 #define CHIP_BOND_ID(sc) ((sc->devinfo.chip_id) & 0x0000000f)
885 #define CHIP_IS_E1(sc) (CHIP_NUM(sc) == CHIP_NUM_57710)
886 #define CHIP_IS_57710(sc) (CHIP_NUM(sc) == CHIP_NUM_57710)
887 #define CHIP_IS_57711(sc) (CHIP_NUM(sc) == CHIP_NUM_57711)
888 #define CHIP_IS_57711E(sc) (CHIP_NUM(sc) == CHIP_NUM_57711E)
889 #define CHIP_IS_E1H(sc) ((CHIP_IS_57711(sc)) || \
890 (CHIP_IS_57711E(sc)))
891 #define CHIP_IS_E1x(sc) CHIP_IS_E1H(sc)
893 #define CHIP_IS_57712(sc) (CHIP_NUM(sc) == CHIP_NUM_57712)
894 #define CHIP_IS_57712_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_MF)
895 #define CHIP_IS_57712_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_VF)
896 #define CHIP_IS_E2(sc) (CHIP_IS_57712(sc) || \
897 CHIP_IS_57712_MF(sc))
899 #define CHIP_IS_57800(sc) (CHIP_NUM(sc) == CHIP_NUM_57800)
900 #define CHIP_IS_57800_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_MF)
901 #define CHIP_IS_57800_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_VF)
902 #define CHIP_IS_57810(sc) (CHIP_NUM(sc) == CHIP_NUM_57810)
903 #define CHIP_IS_57810_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_MF)
904 #define CHIP_IS_57810_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_VF)
905 #define CHIP_IS_57811(sc) (CHIP_NUM(sc) == CHIP_NUM_57811)
906 #define CHIP_IS_57811_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_MF)
907 #define CHIP_IS_57811_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_VF)
908 #define CHIP_IS_57840(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS) || \
909 (CHIP_NUM(sc) == CHIP_NUM_57840_4_10) || \
910 (CHIP_NUM(sc) == CHIP_NUM_57840_2_20))
911 #define CHIP_IS_57840_MF(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS_MF) || \
912 (CHIP_NUM(sc) == CHIP_NUM_57840_MF))
913 #define CHIP_IS_57840_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57840_VF)
915 #define CHIP_IS_E3(sc) (CHIP_IS_57800(sc) || \
916 CHIP_IS_57800_MF(sc) || \
917 CHIP_IS_57800_VF(sc) || \
918 CHIP_IS_57810(sc) || \
919 CHIP_IS_57810_MF(sc) || \
920 CHIP_IS_57810_VF(sc) || \
921 CHIP_IS_57811(sc) || \
922 CHIP_IS_57811_MF(sc) || \
923 CHIP_IS_57811_VF(sc) || \
924 CHIP_IS_57840(sc) || \
925 CHIP_IS_57840_MF(sc) || \
926 CHIP_IS_57840_VF(sc))
927 #define CHIP_IS_E3A0(sc) (CHIP_IS_E3(sc) && \
928 (CHIP_REV(sc) == CHIP_REV_Ax))
929 #define CHIP_IS_E3B0(sc) (CHIP_IS_E3(sc) && \
930 (CHIP_REV(sc) == CHIP_REV_Bx))
932 #define USES_WARPCORE(sc) (CHIP_IS_E3(sc))
933 #define CHIP_IS_E2E3(sc) (CHIP_IS_E2(sc) || \
936 #define CHIP_IS_MF_CAP(sc) (CHIP_IS_57711E(sc) || \
937 CHIP_IS_57712_MF(sc) || \
940 #define IS_VF(sc) ((sc)->flags & BNX2X_IS_VF_FLAG)
941 #define IS_PF(sc) (!IS_VF(sc))
944 * This define is used in two main places:
945 * 1. In the early stages of nic_load, to know if to configure Parser/Searcher
946 * to nic-only mode or to offload mode. Offload mode is configured if either
947 * the chip is E1x (where NIC_MODE register is not applicable), or if cnic
948 * already registered for this port (which means that the user wants storage
950 * 2. During cnic-related load, to know if offload mode is already configured
951 * in the HW or needs to be configrued. Since the transition from nic-mode to
952 * offload-mode in HW causes traffic coruption, nic-mode is configured only
953 * in ports on which storage services where never requested.
955 #define CONFIGURE_NIC_MODE(sc) (!CHIP_IS_E1x(sc) && !CNIC_ENABLED(sc))
957 uint8_t chip_port_mode;
958 #define CHIP_4_PORT_MODE 0x0
959 #define CHIP_2_PORT_MODE 0x1
960 #define CHIP_PORT_MODE_NONE 0x2
961 #define CHIP_PORT_MODE(sc) ((sc)->devinfo.chip_port_mode)
962 #define CHIP_IS_MODE_4_PORT(sc) (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE)
965 #define INT_BLOCK_HC 0
966 #define INT_BLOCK_IGU 1
967 #define INT_BLOCK_MODE_NORMAL 0
968 #define INT_BLOCK_MODE_BW_COMP 2
969 #define CHIP_INT_MODE_IS_NBC(sc) \
970 (!CHIP_IS_E1x(sc) && \
971 !((sc)->devinfo.int_block & INT_BLOCK_MODE_BW_COMP))
972 #define CHIP_INT_MODE_IS_BC(sc) (!CHIP_INT_MODE_IS_NBC(sc))
975 uint32_t shmem2_base;
978 uint32_t mf_cfg_base; /* bootcode shmem address in BAR memory */
979 struct bnx2x_mf_info mf_info;
982 #define NVRAM_1MB_SIZE 0x20000
983 #define NVRAM_TIMEOUT_COUNT 30000
984 #define NVRAM_PAGE_SIZE 256
986 /* PCIe capability information */
987 uint32_t pcie_cap_flags;
988 #define BNX2X_PM_CAPABLE_FLAG 0x00000001
989 #define BNX2X_PCIE_CAPABLE_FLAG 0x00000002
990 #define BNX2X_MSI_CAPABLE_FLAG 0x00000004
991 #define BNX2X_MSIX_CAPABLE_FLAG 0x00000008
992 uint16_t pcie_pm_cap_reg;
993 uint16_t pcie_link_width;
994 uint16_t pcie_link_speed;
995 uint16_t pcie_msi_cap_reg;
996 uint16_t pcie_msix_cap_reg;
998 /* device configuration read from bootcode shared memory */
1000 uint32_t hw_config2;
1001 }; /* struct bnx2x_devinfo */
1003 struct bnx2x_sp_objs {
1004 struct ecore_vlan_mac_obj mac_obj; /* MACs object */
1005 struct ecore_queue_sp_obj q_obj; /* Queue State object */
1006 }; /* struct bnx2x_sp_objs */
1009 * Data that will be used to create a link report message. We will keep the
1010 * data used for the last link report in order to prevent reporting the same
1011 * link parameters twice.
1013 struct bnx2x_link_report_data {
1014 uint16_t line_speed; /* Effective line speed */
1015 unsigned long link_report_flags; /* BNX2X_LINK_REPORT_XXX flags */
1019 BNX2X_LINK_REPORT_FULL_DUPLEX,
1020 BNX2X_LINK_REPORT_LINK_DOWN,
1021 BNX2X_LINK_REPORT_RX_FC_ON,
1022 BNX2X_LINK_REPORT_TX_FC_ON
1025 #define BNX2X_RX_CHAIN_PAGE_SZ BNX2X_PAGE_SIZE
1027 struct bnx2x_pci_cap {
1028 struct bnx2x_pci_cap *next;
1036 /* Top level device private data structure. */
1037 struct bnx2x_softc {
1041 uint32_t max_tx_queues;
1042 uint32_t max_rx_queues;
1043 const struct rte_pci_device *pci_dev;
1045 struct bnx2x_pci_cap *pci_caps;
1046 #define BNX2X_INTRS_POLL_PERIOD 1
1051 /* MAC address operations */
1052 struct bnx2x_mac_ops mac_ops;
1054 /* structures for VF mbox/response/bulletin */
1055 struct bnx2x_vf_mbx_msg *vf2pf_mbox;
1056 struct bnx2x_dma vf2pf_mbox_mapping;
1057 struct vf_acquire_resp_tlv acquire_resp;
1058 struct bnx2x_vf_bulletin *pf2vf_bulletin;
1059 struct bnx2x_dma pf2vf_bulletin_mapping;
1060 struct bnx2x_vf_bulletin old_bulletin;
1061 rte_spinlock_t vf2pf_lock;
1065 int state; /* device state */
1066 #define BNX2X_STATE_CLOSED 0x0000
1067 #define BNX2X_STATE_OPENING_WAITING_LOAD 0x1000
1068 #define BNX2X_STATE_OPENING_WAITING_PORT 0x2000
1069 #define BNX2X_STATE_OPEN 0x3000
1070 #define BNX2X_STATE_CLOSING_WAITING_HALT 0x4000
1071 #define BNX2X_STATE_CLOSING_WAITING_DELETE 0x5000
1072 #define BNX2X_STATE_CLOSING_WAITING_UNLOAD 0x6000
1073 #define BNX2X_STATE_DISABLED 0xD000
1074 #define BNX2X_STATE_DIAG 0xE000
1075 #define BNX2X_STATE_ERROR 0xF000
1078 #define BNX2X_ONE_PORT_FLAG 0x1
1079 #define BNX2X_NO_FCOE_FLAG 0x2
1080 #define BNX2X_NO_WOL_FLAG 0x4
1081 #define BNX2X_NO_MCP_FLAG 0x8
1082 #define BNX2X_NO_ISCSI_OOO_FLAG 0x10
1083 #define BNX2X_NO_ISCSI_FLAG 0x20
1084 #define BNX2X_MF_FUNC_DIS 0x40
1085 #define BNX2X_TX_SWITCHING 0x80
1086 #define BNX2X_IS_VF_FLAG 0x100
1088 #define BNX2X_ONE_PORT(sc) (sc->flags & BNX2X_ONE_PORT_FLAG)
1089 #define BNX2X_NOFCOE(sc) (sc->flags & BNX2X_NO_FCOE_FLAG)
1090 #define BNX2X_NOMCP(sc) (sc->flags & BNX2X_NO_MCP_FLAG)
1093 struct bnx2x_bar bar[MAX_BARS]; /* map BARs 0, 2, 4 */
1095 uint16_t doorbell_size;
1097 /* periodic timer callout */
1098 #define PERIODIC_STOP 0
1099 #define PERIODIC_GO 1
1100 volatile unsigned long periodic_flags;
1101 rte_atomic32_t scan_fp;
1102 struct bnx2x_fastpath fp[MAX_RSS_CHAINS];
1103 struct bnx2x_sp_objs sp_objs[MAX_RSS_CHAINS];
1105 uint8_t unit; /* driver instance number */
1107 int pcie_bus; /* PCIe bus number */
1108 int pcie_device; /* PCIe device/slot number */
1109 int pcie_func; /* PCIe function number */
1111 uint8_t pfunc_rel; /* function relative */
1112 uint8_t pfunc_abs; /* function absolute */
1113 uint8_t path_id; /* function absolute */
1114 #define SC_PATH(sc) (sc->path_id)
1115 #define SC_PORT(sc) (sc->pfunc_rel & 1)
1116 #define SC_FUNC(sc) (sc->pfunc_rel)
1117 #define SC_ABS_FUNC(sc) (sc->pfunc_abs)
1118 #define SC_VN(sc) (sc->pfunc_rel >> 1)
1119 #define SC_L_ID(sc) (SC_VN(sc) << 2)
1120 #define PORT_ID(sc) SC_PORT(sc)
1121 #define PATH_ID(sc) SC_PATH(sc)
1122 #define VNIC_ID(sc) SC_VN(sc)
1123 #define FUNC_ID(sc) SC_FUNC(sc)
1124 #define ABS_FUNC_ID(sc) SC_ABS_FUNC(sc)
1125 #define SC_FW_MB_IDX_VN(sc, vn) \
1126 (SC_PORT(sc) + (vn) * \
1127 ((CHIP_IS_E1x(sc) || (CHIP_IS_MODE_4_PORT(sc))) ? 2 : 1))
1128 #define SC_FW_MB_IDX(sc) SC_FW_MB_IDX_VN(sc, SC_VN(sc))
1130 int if_capen; /* enabled interface capabilities */
1132 struct bnx2x_devinfo devinfo;
1133 char fw_ver_str[32];
1134 char mf_mode_str[32];
1135 char pci_link_str[32];
1137 struct iro *iro_array;
1140 #define DMAE_READY(sc) (sc->dmae_ready)
1142 struct ecore_credit_pool_obj vlans_pool;
1143 struct ecore_credit_pool_obj macs_pool;
1144 struct ecore_rx_mode_obj rx_mode_obj;
1145 struct ecore_mcast_obj mcast_obj;
1146 struct ecore_rss_config_obj rss_conf_obj;
1147 struct ecore_func_sp_obj func_obj;
1150 uint16_t fw_drv_pulse_wr_seq;
1153 struct elink_params link_params;
1154 struct elink_vars link_vars;
1156 struct bnx2x_link_report_data last_reported_link;
1157 char mac_addr_str[32];
1159 uint32_t tx_ring_size;
1160 uint32_t rx_ring_size;
1165 #define BNX2X_RECOVERY_DONE 1
1166 #define BNX2X_RECOVERY_INIT 2
1167 #define BNX2X_RECOVERY_WAIT 3
1168 #define BNX2X_RECOVERY_FAILED 4
1169 #define BNX2X_RECOVERY_NIC_LOADING 5
1172 #define BNX2X_RX_MODE_NONE 0
1173 #define BNX2X_RX_MODE_NORMAL 1
1174 #define BNX2X_RX_MODE_ALLMULTI 2
1175 #define BNX2X_RX_MODE_ALLMULTI_PROMISC 3
1176 #define BNX2X_RX_MODE_PROMISC 4
1177 #define BNX2X_MAX_MULTICAST 64
1179 struct bnx2x_port port;
1181 struct cmng_init cmng;
1189 #define INTR_MODE_INTX 0
1190 #define INTR_MODE_MSI 1
1191 #define INTR_MODE_MSIX 2
1192 #define INTR_MODE_SINGLE_MSIX 3
1196 uint8_t igu_base_sb;
1198 uint32_t igu_base_addr;
1199 uint8_t base_fw_ndsb;
1200 #define DEF_SB_IGU_ID 16
1201 #define DEF_SB_ID HC_SP_SB_ID
1203 /* default status block */
1204 struct bnx2x_dma def_sb_dma;
1205 struct host_sp_status_block *def_sb;
1207 uint16_t def_att_idx;
1208 uint32_t attn_state;
1209 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
1211 /* general SP events - stats query, cfc delete, etc */
1212 #define HC_SP_INDEX_ETH_DEF_CONS 3
1213 /* EQ completions */
1214 #define HC_SP_INDEX_EQ_CONS 7
1215 /* FCoE L2 connection completions */
1216 #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6
1217 #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4
1219 #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5
1220 #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1
1223 struct bnx2x_dma eq_dma;
1224 union event_ring_elem *eq;
1227 uint16_t *eq_cons_sb;
1228 #define NUM_EQ_PAGES 1 /* must be a power of 2 */
1229 #define EQ_DESC_CNT_PAGE (BNX2X_PAGE_SIZE / sizeof(union event_ring_elem))
1230 #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1)
1231 #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES)
1232 #define EQ_DESC_MASK (NUM_EQ_DESC - 1)
1233 #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2)
1234 /* depends on EQ_DESC_CNT_PAGE being a power of 2 */
1235 #define NEXT_EQ_IDX(x) \
1236 ((((x) & EQ_DESC_MAX_PAGE) == (EQ_DESC_MAX_PAGE - 1)) ? \
1237 ((x) + 2) : ((x) + 1))
1238 /* depends on the above and on NUM_EQ_PAGES being a power of 2 */
1239 #define EQ_DESC(x) ((x) & EQ_DESC_MASK)
1242 struct bnx2x_dma sp_dma;
1243 struct bnx2x_slowpath *sp;
1244 unsigned long sp_state;
1246 /* slow path queue */
1247 struct bnx2x_dma spq_dma;
1248 struct eth_spe *spq;
1249 #define SP_DESC_CNT (BNX2X_PAGE_SIZE / sizeof(struct eth_spe))
1250 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
1251 #define MAX_SPQ_PENDING 8
1253 uint16_t spq_prod_idx;
1254 struct eth_spe *spq_prod_bd;
1255 struct eth_spe *spq_last_bd;
1256 uint16_t *dsb_sp_prod;
1258 volatile unsigned long eq_spq_left; /* COMMON_xxx ramrod credit */
1259 volatile unsigned long cq_spq_left; /* ETH_xxx ramrod credit */
1261 /* fw decompression buffer */
1262 struct bnx2x_dma gz_buf_dma;
1265 #define GUNZIP_BUF(sc) (sc->gz_buf)
1266 #define GUNZIP_OUTLEN(sc) (sc->gz_outlen)
1267 #define GUNZIP_PHYS(sc) (rte_iova_t)(sc->gz_buf_dma.paddr)
1268 #define FW_BUF_SIZE 0x40000
1270 struct raw_op *init_ops;
1271 uint16_t *init_ops_offsets; /* init block offsets inside init_ops */
1272 uint32_t *init_data; /* data blob, 32 bit granularity */
1273 uint32_t init_mode_flags;
1274 #define INIT_MODE_FLAGS(sc) (sc->init_mode_flags)
1275 /* PRAM blobs - raw data */
1276 const uint8_t *tsem_int_table_data;
1277 const uint8_t *tsem_pram_data;
1278 const uint8_t *usem_int_table_data;
1279 const uint8_t *usem_pram_data;
1280 const uint8_t *xsem_int_table_data;
1281 const uint8_t *xsem_pram_data;
1282 const uint8_t *csem_int_table_data;
1283 const uint8_t *csem_pram_data;
1284 #define INIT_OPS(sc) (sc->init_ops)
1285 #define INIT_OPS_OFFSETS(sc) (sc->init_ops_offsets)
1286 #define INIT_DATA(sc) (sc->init_data)
1287 #define INIT_TSEM_INT_TABLE_DATA(sc) (sc->tsem_int_table_data)
1288 #define INIT_TSEM_PRAM_DATA(sc) (sc->tsem_pram_data)
1289 #define INIT_USEM_INT_TABLE_DATA(sc) (sc->usem_int_table_data)
1290 #define INIT_USEM_PRAM_DATA(sc) (sc->usem_pram_data)
1291 #define INIT_XSEM_INT_TABLE_DATA(sc) (sc->xsem_int_table_data)
1292 #define INIT_XSEM_PRAM_DATA(sc) (sc->xsem_pram_data)
1293 #define INIT_CSEM_INT_TABLE_DATA(sc) (sc->csem_int_table_data)
1294 #define INIT_CSEM_PRAM_DATA(sc) (sc->csem_pram_data)
1296 #define PHY_FW_VER_LEN 20
1300 * For max 196 cids (64*3 + non-eth), 32KB ILT page size and 1KB
1301 * context size we need 8 ILT entries.
1303 #define ILT_MAX_L2_LINES 8
1304 struct hw_context context[ILT_MAX_L2_LINES];
1305 struct ecore_ilt *ilt;
1306 #define ILT_MAX_LINES 256
1308 /* max supported number of RSS queues: IGU SBs minus one for CNIC */
1309 #define BNX2X_MAX_RSS_COUNT(sc) ((sc)->igu_sb_cnt - CNIC_SUPPORT(sc))
1310 /* max CID count: Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI */
1311 #define BNX2X_L2_MAX_CID(sc) \
1312 (BNX2X_MAX_RSS_COUNT(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc))
1313 #define BNX2X_L2_CID_COUNT(sc) \
1314 (BNX2X_NUM_ETH_QUEUES(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc))
1315 #define L2_ILT_LINES(sc) \
1316 (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(sc), ILT_PAGE_CIDS))
1320 uint8_t dropless_fc;
1322 /* total number of FW statistics requests */
1323 uint8_t fw_stats_num;
1325 * This is a memory buffer that will contain both statistics ramrod
1328 struct bnx2x_dma fw_stats_dma;
1330 * FW statistics request shortcut (points at the beginning of fw_stats
1333 int fw_stats_req_size;
1334 struct bnx2x_fw_stats_req *fw_stats_req;
1335 rte_iova_t fw_stats_req_mapping;
1337 * FW statistics data shortcut (points at the beginning of fw_stats
1338 * buffer + fw_stats_req_size).
1340 int fw_stats_data_size;
1341 struct bnx2x_fw_stats_data *fw_stats_data;
1342 rte_iova_t fw_stats_data_mapping;
1344 /* tracking a pending STAT_QUERY ramrod */
1345 uint16_t stats_pending;
1346 /* number of completed statistics ramrods */
1347 uint16_t stats_comp;
1348 uint16_t stats_counter;
1352 struct bnx2x_eth_stats eth_stats;
1353 struct host_func_stats func_stats;
1354 struct bnx2x_eth_stats_old eth_stats_old;
1355 struct bnx2x_net_stats_old net_stats_old;
1356 struct bnx2x_fw_port_stats_old fw_stats_old;
1358 struct dmae_command stats_dmae; /* used by dmae command loader */
1363 /* DCB support on/off */
1365 #define BNX2X_DCB_STATE_OFF 0
1366 #define BNX2X_DCB_STATE_ON 1
1367 /* DCBX engine mode */
1369 #define BNX2X_DCBX_ENABLED_OFF 0
1370 #define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1
1371 #define BNX2X_DCBX_ENABLED_ON_NEG_ON 2
1372 #define BNX2X_DCBX_ENABLED_INVALID -1
1374 uint8_t cnic_support;
1375 uint8_t cnic_enabled;
1376 uint8_t cnic_loaded;
1377 #define CNIC_SUPPORT(sc) 0 /* ((sc)->cnic_support) */
1378 #define CNIC_ENABLED(sc) 0 /* ((sc)->cnic_enabled) */
1379 #define CNIC_LOADED(sc) 0 /* ((sc)->cnic_loaded) */
1381 /* multiple tx classes of service */
1383 #define BNX2X_MAX_PRIORITY 8
1384 /* priority to cos mapping */
1385 uint8_t prio_to_cos[BNX2X_MAX_PRIORITY];
1388 }; /* struct bnx2x_softc */
1390 /* IOCTL sub-commands for edebug and firmware upgrade */
1391 #define BNX2X_IOC_RD_NVRAM 1
1392 #define BNX2X_IOC_WR_NVRAM 2
1393 #define BNX2X_IOC_STATS_SHOW_NUM 3
1394 #define BNX2X_IOC_STATS_SHOW_STR 4
1395 #define BNX2X_IOC_STATS_SHOW_CNT 5
1397 struct bnx2x_nvram_data {
1398 uint32_t op; /* ioctl sub-command */
1401 uint32_t value[1]; /* variable */
1404 union bnx2x_stats_show_data {
1405 uint32_t op; /* ioctl sub-command */
1408 uint32_t num; /* return number of stats */
1409 uint32_t len; /* length of each string item */
1412 /* variable length... */
1413 char str[1]; /* holds names of desc.num stats, each desc.len in length */
1415 /* variable length... */
1416 uint64_t stats[1]; /* holds all stats */
1419 /* function init flags */
1420 #define FUNC_FLG_RSS 0x0001
1421 #define FUNC_FLG_STATS 0x0002
1422 /* FUNC_FLG_UNMATCHED 0x0004 */
1423 #define FUNC_FLG_SPQ 0x0010
1424 #define FUNC_FLG_LEADING 0x0020 /* PF only */
1426 struct bnx2x_func_init_params {
1427 rte_iova_t fw_stat_map; /* (dma) valid if FUNC_FLG_STATS */
1428 rte_iova_t spq_map; /* (dma) valid if FUNC_FLG_SPQ */
1430 uint16_t func_id; /* abs function id */
1432 uint16_t spq_prod; /* valid if FUNC_FLG_SPQ */
1435 /* memory resources reside at BARs 0, 2, 4 */
1436 /* Run `pciconf -lb` to see mappings */
1442 bnx2x_reg_write8(struct bnx2x_softc *sc, size_t offset, uint8_t val)
1444 PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "offset=0x%08lx val=0x%02x",
1445 (unsigned long)offset, val);
1446 rte_write8(val, ((uint8_t *)sc->bar[BAR0].base_addr + offset));
1450 bnx2x_reg_write16(struct bnx2x_softc *sc, size_t offset, uint16_t val)
1452 #ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
1453 if ((offset % 2) != 0)
1454 PMD_DRV_LOG(NOTICE, sc, "Unaligned 16-bit write to 0x%08lx",
1455 (unsigned long)offset);
1457 PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "offset=0x%08lx val=0x%04x",
1458 (unsigned long)offset, val);
1459 rte_write16(val, ((uint8_t *)sc->bar[BAR0].base_addr + offset));
1464 bnx2x_reg_write32(struct bnx2x_softc *sc, size_t offset, uint32_t val)
1466 #ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
1467 if ((offset % 4) != 0)
1468 PMD_DRV_LOG(NOTICE, sc, "Unaligned 32-bit write to 0x%08lx",
1469 (unsigned long)offset);
1472 PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "offset=0x%08lx val=0x%08x",
1473 (unsigned long)offset, val);
1474 rte_write32(val, ((uint8_t *)sc->bar[BAR0].base_addr + offset));
1477 static inline uint8_t
1478 bnx2x_reg_read8(struct bnx2x_softc *sc, size_t offset)
1482 val = rte_read8((uint8_t *)sc->bar[BAR0].base_addr + offset);
1483 PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "offset=0x%08lx val=0x%02x",
1484 (unsigned long)offset, val);
1489 static inline uint16_t
1490 bnx2x_reg_read16(struct bnx2x_softc *sc, size_t offset)
1494 #ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
1495 if ((offset % 2) != 0)
1496 PMD_DRV_LOG(NOTICE, sc, "Unaligned 16-bit read from 0x%08lx",
1497 (unsigned long)offset);
1500 val = rte_read16(((uint8_t *)sc->bar[BAR0].base_addr + offset));
1501 PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "offset=0x%08lx val=0x%08x",
1502 (unsigned long)offset, val);
1507 static inline uint32_t
1508 bnx2x_reg_read32(struct bnx2x_softc *sc, size_t offset)
1512 #ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
1513 if ((offset % 4) != 0)
1514 PMD_DRV_LOG(NOTICE, sc, "Unaligned 32-bit read from 0x%08lx",
1515 (unsigned long)offset);
1518 val = rte_read32(((uint8_t *)sc->bar[BAR0].base_addr + offset));
1519 PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "offset=0x%08lx val=0x%08x",
1520 (unsigned long)offset, val);
1525 #define REG_ADDR(sc, offset) (((uint64_t)sc->bar[BAR0].base_addr) + (offset))
1527 #define REG_RD8(sc, offset) bnx2x_reg_read8(sc, (offset))
1528 #define REG_RD16(sc, offset) bnx2x_reg_read16(sc, (offset))
1529 #define REG_RD32(sc, offset) bnx2x_reg_read32(sc, (offset))
1531 #define REG_WR8(sc, offset, val) bnx2x_reg_write8(sc, (offset), val)
1532 #define REG_WR16(sc, offset, val) bnx2x_reg_write16(sc, (offset), val)
1533 #define REG_WR32(sc, offset, val) bnx2x_reg_write32(sc, (offset), val)
1535 #define REG_RD(sc, offset) REG_RD32(sc, offset)
1536 #define REG_WR(sc, offset, val) REG_WR32(sc, offset, val)
1538 #define BNX2X_SP(sc, var) (&(sc)->sp->var)
1539 #define BNX2X_SP_MAPPING(sc, var) \
1540 (sc->sp_dma.paddr + offsetof(struct bnx2x_slowpath, var))
1542 #define BNX2X_FP(sc, nr, var) ((sc)->fp[(nr)].var)
1543 #define BNX2X_SP_OBJ(sc, fp) ((sc)->sp_objs[(fp)->index])
1545 #define bnx2x_fp(sc, nr, var) ((sc)->fp[nr].var)
1547 #define REG_RD_DMAE(sc, offset, valp, len32) \
1549 (void)bnx2x_read_dmae(sc, offset, len32); \
1550 rte_memcpy(valp, BNX2X_SP(sc, wb_data[0]), (len32) * 4); \
1553 #define REG_WR_DMAE(sc, offset, valp, len32) \
1555 rte_memcpy(BNX2X_SP(sc, wb_data[0]), valp, (len32) * 4); \
1556 (void)bnx2x_write_dmae(sc, BNX2X_SP_MAPPING(sc, wb_data), offset, len32); \
1559 #define REG_WR_DMAE_LEN(sc, offset, valp, len32) \
1560 REG_WR_DMAE(sc, offset, valp, len32)
1562 #define REG_RD_DMAE_LEN(sc, offset, valp, len32) \
1563 REG_RD_DMAE(sc, offset, valp, len32)
1565 #define VIRT_WR_DMAE_LEN(sc, data, addr, len32, le32_swap) \
1567 /* if (le32_swap) { */ \
1568 /* PMD_PWARN_LOG(sc, "VIRT_WR_DMAE_LEN with le32_swap=1"); */ \
1570 rte_memcpy(GUNZIP_BUF(sc), data, len32 * 4); \
1571 ecore_write_big_buf_wb(sc, addr, len32); \
1574 #define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */
1575 #define BNX2X_DB_SHIFT 7 /* 128 bytes */
1576 #if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT)
1577 #error "Minimum DB doorbell stride is 8"
1579 #define DPM_TRIGGER_TYPE 0x40
1581 /* Doorbell macro */
1582 #define BNX2X_DB_WRITE(db_bar, val) rte_write32_relaxed((val), (db_bar))
1584 #define BNX2X_DB_READ(db_bar) rte_read32_relaxed(db_bar)
1586 #define DOORBELL_ADDR(sc, offset) \
1587 (volatile uint32_t *)(((char *)(sc)->bar[BAR1].base_addr + (offset)))
1589 #define DOORBELL(sc, cid, val) \
1591 BNX2X_DB_WRITE((DOORBELL_ADDR(sc, sc->doorbell_size * (cid) + DPM_TRIGGER_TYPE)), (val)); \
1593 BNX2X_DB_WRITE((DOORBELL_ADDR(sc, sc->doorbell_size * (cid))), (val)) \
1595 #define SHMEM_ADDR(sc, field) \
1596 (sc->devinfo.shmem_base + offsetof(struct shmem_region, field))
1597 #define SHMEM_RD(sc, field) REG_RD(sc, SHMEM_ADDR(sc, field))
1598 #define SHMEM_RD16(sc, field) REG_RD16(sc, SHMEM_ADDR(sc, field))
1599 #define SHMEM_WR(sc, field, val) REG_WR(sc, SHMEM_ADDR(sc, field), val)
1601 #define SHMEM2_ADDR(sc, field) \
1602 (sc->devinfo.shmem2_base + offsetof(struct shmem2_region, field))
1603 #define SHMEM2_HAS(sc, field) \
1604 (sc->devinfo.shmem2_base && (REG_RD(sc, SHMEM2_ADDR(sc, size)) > \
1605 offsetof(struct shmem2_region, field)))
1606 #define SHMEM2_RD(sc, field) REG_RD(sc, SHMEM2_ADDR(sc, field))
1607 #define SHMEM2_WR(sc, field, val) REG_WR(sc, SHMEM2_ADDR(sc, field), val)
1609 #define MFCFG_ADDR(sc, field) \
1610 (sc->devinfo.mf_cfg_base + offsetof(struct mf_cfg, field))
1611 #define MFCFG_RD(sc, field) REG_RD(sc, MFCFG_ADDR(sc, field))
1612 #define MFCFG_RD16(sc, field) REG_RD16(sc, MFCFG_ADDR(sc, field))
1613 #define MFCFG_WR(sc, field, val) REG_WR(sc, MFCFG_ADDR(sc, field), val)
1615 /* DMAE command defines */
1617 #define DMAE_TIMEOUT -1
1618 #define DMAE_PCI_ERROR -2 /* E2 and onward */
1619 #define DMAE_NOT_RDY -3
1620 #define DMAE_PCI_ERR_FLAG 0x80000000
1622 #define DMAE_SRC_PCI 0
1623 #define DMAE_SRC_GRC 1
1625 #define DMAE_DST_NONE 0
1626 #define DMAE_DST_PCI 1
1627 #define DMAE_DST_GRC 2
1629 #define DMAE_COMP_PCI 0
1630 #define DMAE_COMP_GRC 1
1632 #define DMAE_COMP_REGULAR 0
1633 #define DMAE_COM_SET_ERR 1
1635 #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << DMAE_COMMAND_SRC_SHIFT)
1636 #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << DMAE_COMMAND_SRC_SHIFT)
1637 #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << DMAE_COMMAND_DST_SHIFT)
1638 #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << DMAE_COMMAND_DST_SHIFT)
1640 #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << DMAE_COMMAND_C_DST_SHIFT)
1641 #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << DMAE_COMMAND_C_DST_SHIFT)
1643 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
1644 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
1645 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
1646 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
1648 #define DMAE_CMD_PORT_0 0
1649 #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
1651 #define DMAE_SRC_PF 0
1652 #define DMAE_SRC_VF 1
1654 #define DMAE_DST_PF 0
1655 #define DMAE_DST_VF 1
1657 #define DMAE_C_SRC 0
1658 #define DMAE_C_DST 1
1660 #define DMAE_LEN32_RD_MAX 0x80
1661 #define DMAE_LEN32_WR_MAX(sc) 0x2000
1663 #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and beyond, upper bit indicates error */
1665 #define MAX_DMAE_C_PER_PORT 8
1666 #define INIT_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + SC_VN(sc))
1667 #define PMF_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + E1HVN_MAX)
1669 static const uint32_t dmae_reg_go_c[] = {
1670 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
1671 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
1672 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
1673 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
1676 #define ATTN_NIG_FOR_FUNC (1L << 8)
1677 #define ATTN_SW_TIMER_4_FUNC (1L << 9)
1678 #define GPIO_2_FUNC (1L << 10)
1679 #define GPIO_3_FUNC (1L << 11)
1680 #define GPIO_4_FUNC (1L << 12)
1681 #define ATTN_GENERAL_ATTN_1 (1L << 13)
1682 #define ATTN_GENERAL_ATTN_2 (1L << 14)
1683 #define ATTN_GENERAL_ATTN_3 (1L << 15)
1684 #define ATTN_GENERAL_ATTN_4 (1L << 13)
1685 #define ATTN_GENERAL_ATTN_5 (1L << 14)
1686 #define ATTN_GENERAL_ATTN_6 (1L << 15)
1687 #define ATTN_HARD_WIRED_MASK 0xff00
1688 #define ATTENTION_ID 4
1690 #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \
1691 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
1693 #define MAX_IGU_ATTN_ACK_TO 100
1695 #define STORM_ASSERT_ARRAY_SIZE 50
1697 #define BNX2X_PMF_LINK_ASSERT(sc) \
1698 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + SC_FUNC(sc))
1700 #define BNX2X_MC_ASSERT_BITS \
1701 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1702 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1703 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1704 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
1706 #define BNX2X_MCP_ASSERT \
1707 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
1709 #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
1710 #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
1711 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
1712 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
1713 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
1714 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
1715 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
1717 #define MULTI_MASK 0x7f
1719 #define PFS_PER_PORT(sc) \
1720 ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4)
1721 #define SC_MAX_VN_NUM(sc) PFS_PER_PORT(sc)
1723 #define FIRST_ABS_FUNC_IN_PORT(sc) \
1724 ((CHIP_PORT_MODE(sc) == CHIP_PORT_MODE_NONE) ? \
1725 PORT_ID(sc) : (PATH_ID(sc) + (2 * PORT_ID(sc))))
1727 #define FOREACH_ABS_FUNC_IN_PORT(sc, i) \
1728 for ((i) = FIRST_ABS_FUNC_IN_PORT(sc); \
1729 (i) < MAX_FUNC_NUM; \
1730 (i) += (MAX_FUNC_NUM / PFS_PER_PORT(sc)))
1732 #define BNX2X_SWCID_SHIFT 17
1733 #define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1)
1735 #define SW_CID(x) (le32toh(x) & BNX2X_SWCID_MASK)
1736 #define CQE_CMD(x) (le32toh(x) >> COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
1738 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
1739 #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG)
1740 #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG)
1741 #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD)
1742 #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH)
1744 /* must be used on a CID before placing it on a HW ring */
1745 #define HW_CID(sc, x) \
1746 ((SC_PORT(sc) << 23) | (SC_VN(sc) << BNX2X_SWCID_SHIFT) | (x))
1749 #define SPEED_100 100
1750 #define SPEED_1000 1000
1751 #define SPEED_2500 2500
1752 #define SPEED_10000 10000
1755 #define PCI_PM_D3hot 2
1757 int bnx2x_test_bit(int nr, volatile unsigned long * addr);
1758 void bnx2x_set_bit(unsigned int nr, volatile unsigned long * addr);
1759 void bnx2x_clear_bit(int nr, volatile unsigned long * addr);
1760 int bnx2x_test_and_clear_bit(int nr, volatile unsigned long * addr);
1761 int bnx2x_cmpxchg(volatile int *addr, int old, int new);
1763 int bnx2x_dma_alloc(struct bnx2x_softc *sc, size_t size,
1764 struct bnx2x_dma *dma, const char *msg, uint32_t align);
1765 void bnx2x_dma_free(struct bnx2x_dma *dma);
1766 uint32_t bnx2x_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type);
1767 uint32_t bnx2x_dmae_opcode_clr_src_reset(uint32_t opcode);
1768 uint32_t bnx2x_dmae_opcode(struct bnx2x_softc *sc, uint8_t src_type,
1769 uint8_t dst_type, uint8_t with_comp,
1771 void bnx2x_post_dmae(struct bnx2x_softc *sc, struct dmae_command *dmae, int idx);
1772 void bnx2x_read_dmae(struct bnx2x_softc *sc, uint32_t src_addr, uint32_t len32);
1773 void bnx2x_write_dmae(struct bnx2x_softc *sc, rte_iova_t dma_addr,
1774 uint32_t dst_addr, uint32_t len32);
1775 void bnx2x_set_ctx_validation(struct bnx2x_softc *sc, struct eth_context *cxt,
1777 void bnx2x_update_coalesce_sb_index(struct bnx2x_softc *sc, uint8_t fw_sb_id,
1778 uint8_t sb_index, uint8_t disable,
1781 int bnx2x_sp_post(struct bnx2x_softc *sc, int command, int cid,
1782 uint32_t data_hi, uint32_t data_lo, int cmd_type);
1784 void ecore_init_e1h_firmware(struct bnx2x_softc *sc);
1785 void ecore_init_e2_firmware(struct bnx2x_softc *sc);
1787 void ecore_storm_memset_struct(struct bnx2x_softc *sc, uint32_t addr,
1788 size_t size, uint32_t *data);
1790 #define CATC_TRIGGER(sc, data) REG_WR((sc), 0x2000, (data));
1791 #define CATC_TRIGGER_START(sc) CATC_TRIGGER((sc), 0xcafecafe)
1793 #define BNX2X_MAC_FMT "%pM"
1794 #define BNX2X_MAC_PRN_LIST(mac) (mac)
1800 static inline uint32_t
1801 reg_poll(struct bnx2x_softc *sc, uint32_t reg, uint32_t expected, int ms, int wait)
1805 val = REG_RD(sc, reg);
1806 if (val == expected) {
1817 bnx2x_update_fp_sb_idx(struct bnx2x_fastpath *fp)
1819 mb(); /* status block is written to by the chip */
1820 fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID];
1824 bnx2x_igu_ack_sb_gen(struct bnx2x_softc *sc, uint8_t segment,
1825 uint16_t index, uint8_t op, uint8_t update, uint32_t igu_addr)
1827 struct igu_regular cmd_data = {0};
1829 cmd_data.sb_id_and_flags =
1830 ((index << IGU_REGULAR_SB_INDEX_SHIFT) |
1831 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
1832 (update << IGU_REGULAR_BUPDATE_SHIFT) |
1833 (op << IGU_REGULAR_ENABLE_INT_SHIFT));
1835 REG_WR(sc, igu_addr, cmd_data.sb_id_and_flags);
1837 /* Make sure that ACK is written */
1842 bnx2x_hc_ack_sb(struct bnx2x_softc *sc, uint8_t sb_id, uint8_t storm,
1843 uint16_t index, uint8_t op, uint8_t update)
1845 uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc) * 32 +
1846 COMMAND_REG_INT_ACK);
1847 union igu_ack_register igu_ack;
1849 igu_ack.sb.status_block_index = index;
1850 igu_ack.sb.sb_id_and_flags =
1851 ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
1852 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
1853 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
1854 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
1856 REG_WR(sc, hc_addr, igu_ack.raw_data);
1858 /* Make sure that ACK is written */
1862 static inline uint32_t
1863 bnx2x_hc_ack_int(struct bnx2x_softc *sc)
1865 uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc) * 32 +
1866 COMMAND_REG_SIMD_MASK);
1867 uint32_t result = REG_RD(sc, hc_addr);
1873 static inline uint32_t
1874 bnx2x_igu_ack_int(struct bnx2x_softc *sc)
1876 uint32_t igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER * 8);
1877 uint32_t result = REG_RD(sc, igu_addr);
1879 /* PMD_PDEBUG_LOG(sc, DBG_INTR, "read 0x%08x from IGU addr 0x%x",
1880 result, igu_addr); */
1886 static inline uint32_t
1887 bnx2x_ack_int(struct bnx2x_softc *sc)
1890 if (sc->devinfo.int_block == INT_BLOCK_HC) {
1891 return bnx2x_hc_ack_int(sc);
1893 return bnx2x_igu_ack_int(sc);
1898 func_by_vn(struct bnx2x_softc *sc, int vn)
1900 return 2 * vn + SC_PORT(sc);
1904 * send notification to other functions.
1907 bnx2x_link_sync_notify(struct bnx2x_softc *sc)
1911 /* Set the attention towards other drivers on the same port */
1912 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
1913 if (vn == SC_VN(sc))
1916 func = func_by_vn(sc, vn);
1917 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_0 +
1918 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func) * 4, 1);
1923 * Statistics ID are global per chip/path, while Client IDs for E1x
1926 static inline uint8_t
1927 bnx2x_stats_id(struct bnx2x_fastpath *fp)
1929 struct bnx2x_softc *sc = fp->sc;
1931 if (!CHIP_IS_E1x(sc)) {
1935 return fp->cl_id + SC_PORT(sc) * FP_SB_MAX_E1x;
1938 int bnx2x_init(struct bnx2x_softc *sc);
1939 void bnx2x_load_firmware(struct bnx2x_softc *sc);
1940 int bnx2x_attach(struct bnx2x_softc *sc);
1941 int bnx2x_nic_unload(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link);
1942 int bnx2x_alloc_hsi_mem(struct bnx2x_softc *sc);
1943 int bnx2x_alloc_ilt_mem(struct bnx2x_softc *sc);
1944 void bnx2x_free_ilt_mem(struct bnx2x_softc *sc);
1945 void bnx2x_dump_tx_chain(struct bnx2x_fastpath * fp, int bd_prod, int count);
1946 int bnx2x_tx_encap(struct bnx2x_tx_queue *txq, struct rte_mbuf *m0);
1947 uint8_t bnx2x_txeof(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp);
1948 void bnx2x_print_adapter_info(struct bnx2x_softc *sc);
1949 void bnx2x_print_device_info(struct bnx2x_softc *sc);
1950 int bnx2x_intr_legacy(struct bnx2x_softc *sc);
1951 void bnx2x_link_status_update(struct bnx2x_softc *sc);
1952 int bnx2x_complete_sp(struct bnx2x_softc *sc);
1953 int bnx2x_set_storm_rx_mode(struct bnx2x_softc *sc);
1954 void bnx2x_periodic_callout(struct bnx2x_softc *sc);
1955 void bnx2x_periodic_stop(void *param);
1957 int bnx2x_vf_get_resources(struct bnx2x_softc *sc, uint8_t tx_count, uint8_t rx_count);
1958 void bnx2x_vf_close(struct bnx2x_softc *sc);
1959 int bnx2x_vf_init(struct bnx2x_softc *sc);
1960 void bnx2x_vf_unload(struct bnx2x_softc *sc);
1961 int bnx2x_vf_setup_queue(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
1963 void bnx2x_free_hsi_mem(struct bnx2x_softc *sc);
1964 int bnx2x_vf_set_rx_mode(struct bnx2x_softc *sc);
1965 int bnx2x_check_bull(struct bnx2x_softc *sc);
1967 //#define BNX2X_PULSE
1969 #define BNX2X_PCI_CAP 1
1970 #define BNX2X_PCI_ECAP 2
1972 static inline struct bnx2x_pci_cap*
1973 pci_find_cap(struct bnx2x_softc *sc, uint8_t id, uint8_t type)
1975 struct bnx2x_pci_cap *cap = sc->pci_caps;
1978 if (cap->id == id && cap->type == type)
1987 bnx2x_set_rx_mode(struct bnx2x_softc *sc)
1989 if (sc->state == BNX2X_STATE_OPEN) {
1991 bnx2x_set_storm_rx_mode(sc);
1993 sc->rx_mode = BNX2X_RX_MODE_PROMISC;
1994 bnx2x_vf_set_rx_mode(sc);
1997 PMD_DRV_LOG(INFO, sc, "Card is not ready to change mode");
2001 static inline int pci_read(struct bnx2x_softc *sc, size_t addr,
2002 void *val, uint8_t size)
2004 if (rte_pci_read_config(sc->pci_dev, val, size, addr) <= 0) {
2005 PMD_DRV_LOG(ERR, sc, "Can't read from PCI config space");
2012 static inline int pci_write_word(struct bnx2x_softc *sc, size_t addr, off_t val)
2014 uint16_t val16 = val;
2016 if (rte_pci_write_config(sc->pci_dev, &val16,
2017 sizeof(val16), addr) <= 0) {
2018 PMD_DRV_LOG(ERR, sc, "Can't write to PCI config space");
2025 static inline int pci_write_long(struct bnx2x_softc *sc, size_t addr, off_t val)
2027 uint32_t val32 = val;
2028 if (rte_pci_write_config(sc->pci_dev, &val32,
2029 sizeof(val32), addr) <= 0) {
2030 PMD_DRV_LOG(ERR, sc, "Can't write to PCI config space");
2037 #endif /* __BNX2X_H__ */