2 * Copyright (c) 2007-2013 QLogic Corporation. All rights reserved.
4 * Eric Davis <edavis@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
6 * Gary Zambrano <zambrano@broadcom.com>
8 * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. Neither the name of Broadcom Corporation nor the name of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written consent.
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
34 * THE POSSIBILITY OF SUCH DAMAGE.
38 #include "bnx2x_stats.h"
41 #define BITS_PER_LONG 32
43 #define BITS_PER_LONG 64
46 static inline uint16_t
47 bnx2x_get_port_stats_dma_len(struct bnx2x_softc *sc)
52 /* 'newest' convention - shmem2 contains the size of the port stats */
53 if (SHMEM2_HAS(sc, sizeof_port_stats)) {
54 size = SHMEM2_RD(sc, sizeof_port_stats);
59 /* prevent newer BC from causing buffer overflow */
60 if (res > sizeof(struct host_port_stats)) {
61 res = sizeof(struct host_port_stats);
66 * Older convention - all BCs support the port stats fields up until
67 * the 'not_used' field
70 res = (offsetof(struct host_port_stats, not_used) + 4);
72 /* if PFC stats are supported by the MFW, DMA them as well */
73 if (sc->devinfo.bc_ver >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) {
74 res += (offsetof(struct host_port_stats, pfc_frames_rx_lo) -
75 offsetof(struct host_port_stats, pfc_frames_tx_hi) + 4);
85 * Init service functions
89 * Post the next statistics ramrod. Protect it with the lock in
90 * order to ensure the strict order between statistics ramrods
91 * (each ramrod has a sequence number passed in a
92 * sc->fw_stats_req->hdr.drv_stats_counter and ramrods must be
96 bnx2x_storm_stats_post(struct bnx2x_softc *sc)
100 if (!sc->stats_pending) {
101 if (sc->stats_pending) {
105 sc->fw_stats_req->hdr.drv_stats_counter =
106 htole16(sc->stats_counter++);
109 "sending statistics ramrod %d",
110 le16toh(sc->fw_stats_req->hdr.drv_stats_counter));
112 /* adjust the ramrod to include VF queues statistics */
114 /* send FW stats ramrod */
115 rc = bnx2x_sp_post(sc, RAMROD_CMD_ID_COMMON_STAT_QUERY, 0,
116 U64_HI(sc->fw_stats_req_mapping),
117 U64_LO(sc->fw_stats_req_mapping),
118 NONE_CONNECTION_TYPE);
120 sc->stats_pending = 1;
126 bnx2x_hw_stats_post(struct bnx2x_softc *sc)
128 struct dmae_command *dmae = &sc->stats_dmae;
129 uint32_t *stats_comp = BNX2X_SP(sc, stats_comp);
133 *stats_comp = DMAE_COMP_VAL;
134 if (CHIP_REV_IS_SLOW(sc)) {
138 /* Update MCP's statistics if possible */
140 rte_memcpy(BNX2X_SP(sc, func_stats), &sc->func_stats,
141 sizeof(sc->func_stats));
145 if (sc->executer_idx) {
146 loader_idx = PMF_DMAE_C(sc);
147 opcode = bnx2x_dmae_opcode(sc, DMAE_SRC_PCI, DMAE_DST_GRC,
148 TRUE, DMAE_COMP_GRC);
149 opcode = bnx2x_dmae_opcode_clr_src_reset(opcode);
151 memset(dmae, 0, sizeof(struct dmae_command));
152 dmae->opcode = opcode;
153 dmae->src_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, dmae[0]));
154 dmae->src_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, dmae[0]));
155 dmae->dst_addr_lo = ((DMAE_REG_CMD_MEM +
156 sizeof(struct dmae_command) *
157 (loader_idx + 1)) >> 2);
158 dmae->dst_addr_hi = 0;
159 dmae->len = sizeof(struct dmae_command) >> 2;
160 dmae->comp_addr_lo = (dmae_reg_go_c[loader_idx + 1] >> 2);
161 dmae->comp_addr_hi = 0;
165 bnx2x_post_dmae(sc, dmae, loader_idx);
166 } else if (sc->func_stx) {
168 bnx2x_post_dmae(sc, dmae, INIT_DMAE_C(sc));
173 bnx2x_stats_comp(struct bnx2x_softc *sc)
175 uint32_t *stats_comp = BNX2X_SP(sc, stats_comp);
178 while (*stats_comp != DMAE_COMP_VAL) {
180 PMD_DRV_LOG(ERR, "Timeout waiting for stats finished");
192 * Statistics service functions
196 bnx2x_stats_pmf_update(struct bnx2x_softc *sc)
198 struct dmae_command *dmae;
200 int loader_idx = PMF_DMAE_C(sc);
201 uint32_t *stats_comp = BNX2X_SP(sc, stats_comp);
203 if (sc->devinfo.bc_ver <= 0x06001400) {
205 * Bootcode v6.0.21 fixed a GRC timeout that occurs when accessing
206 * BRB registers while the BRB block is in reset. The DMA transfer
207 * below triggers this issue resulting in the DMAE to stop
208 * functioning. Skip this initial stats transfer for old bootcode
209 * versions <= 6.0.20.
214 if (!sc->port.pmf || !sc->port.port_stx) {
215 PMD_DRV_LOG(ERR, "BUG!");
219 sc->executer_idx = 0;
221 opcode = bnx2x_dmae_opcode(sc, DMAE_SRC_GRC, DMAE_DST_PCI, FALSE, 0);
223 dmae = BNX2X_SP(sc, dmae[sc->executer_idx++]);
224 dmae->opcode = bnx2x_dmae_opcode_add_comp(opcode, DMAE_COMP_GRC);
225 dmae->src_addr_lo = (sc->port.port_stx >> 2);
226 dmae->src_addr_hi = 0;
227 dmae->dst_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, port_stats));
228 dmae->dst_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, port_stats));
229 dmae->len = DMAE_LEN32_RD_MAX;
230 dmae->comp_addr_lo = (dmae_reg_go_c[loader_idx] >> 2);
231 dmae->comp_addr_hi = 0;
234 dmae = BNX2X_SP(sc, dmae[sc->executer_idx++]);
235 dmae->opcode = bnx2x_dmae_opcode_add_comp(opcode, DMAE_COMP_PCI);
236 dmae->src_addr_lo = ((sc->port.port_stx >> 2) + DMAE_LEN32_RD_MAX);
237 dmae->src_addr_hi = 0;
238 dmae->dst_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, port_stats) +
239 DMAE_LEN32_RD_MAX * 4);
240 dmae->dst_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, port_stats) +
241 DMAE_LEN32_RD_MAX * 4);
242 dmae->len = (bnx2x_get_port_stats_dma_len(sc) - DMAE_LEN32_RD_MAX);
244 dmae->comp_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, stats_comp));
245 dmae->comp_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, stats_comp));
246 dmae->comp_val = DMAE_COMP_VAL;
249 bnx2x_hw_stats_post(sc);
250 bnx2x_stats_comp(sc);
254 bnx2x_port_stats_init(struct bnx2x_softc *sc)
256 struct dmae_command *dmae;
257 int port = SC_PORT(sc);
259 int loader_idx = PMF_DMAE_C(sc);
261 uint32_t *stats_comp = BNX2X_SP(sc, stats_comp);
264 if (!sc->link_vars.link_up || !sc->port.pmf) {
265 PMD_DRV_LOG(ERR, "BUG!");
269 sc->executer_idx = 0;
272 opcode = bnx2x_dmae_opcode(sc, DMAE_SRC_PCI, DMAE_DST_GRC,
273 TRUE, DMAE_COMP_GRC);
275 if (sc->port.port_stx) {
276 dmae = BNX2X_SP(sc, dmae[sc->executer_idx++]);
277 dmae->opcode = opcode;
278 dmae->src_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, port_stats));
279 dmae->src_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, port_stats));
280 dmae->dst_addr_lo = sc->port.port_stx >> 2;
281 dmae->dst_addr_hi = 0;
282 dmae->len = bnx2x_get_port_stats_dma_len(sc);
283 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
284 dmae->comp_addr_hi = 0;
289 dmae = BNX2X_SP(sc, dmae[sc->executer_idx++]);
290 dmae->opcode = opcode;
291 dmae->src_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, func_stats));
292 dmae->src_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, func_stats));
293 dmae->dst_addr_lo = (sc->func_stx >> 2);
294 dmae->dst_addr_hi = 0;
295 dmae->len = (sizeof(struct host_func_stats) >> 2);
296 dmae->comp_addr_lo = (dmae_reg_go_c[loader_idx] >> 2);
297 dmae->comp_addr_hi = 0;
302 opcode = bnx2x_dmae_opcode(sc, DMAE_SRC_GRC, DMAE_DST_PCI,
303 TRUE, DMAE_COMP_GRC);
305 /* EMAC is special */
306 if (sc->link_vars.mac_type == ELINK_MAC_TYPE_EMAC) {
307 mac_addr = (port ? GRCBASE_EMAC1 : GRCBASE_EMAC0);
309 /* EMAC_REG_EMAC_RX_STAT_AC (EMAC_REG_EMAC_RX_STAT_AC_COUNT)*/
310 dmae = BNX2X_SP(sc, dmae[sc->executer_idx++]);
311 dmae->opcode = opcode;
312 dmae->src_addr_lo = (mac_addr + EMAC_REG_EMAC_RX_STAT_AC) >> 2;
313 dmae->src_addr_hi = 0;
314 dmae->dst_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, mac_stats));
315 dmae->dst_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, mac_stats));
316 dmae->len = EMAC_REG_EMAC_RX_STAT_AC_COUNT;
317 dmae->comp_addr_lo = (dmae_reg_go_c[loader_idx] >> 2);
318 dmae->comp_addr_hi = 0;
321 /* EMAC_REG_EMAC_RX_STAT_AC_28 */
322 dmae = BNX2X_SP(sc, dmae[sc->executer_idx++]);
323 dmae->opcode = opcode;
324 dmae->src_addr_lo = ((mac_addr + EMAC_REG_EMAC_RX_STAT_AC_28) >> 2);
325 dmae->src_addr_hi = 0;
326 dmae->dst_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, mac_stats) +
327 offsetof(struct emac_stats,
328 rx_stat_falsecarriererrors));
329 dmae->dst_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, mac_stats) +
330 offsetof(struct emac_stats,
331 rx_stat_falsecarriererrors));
333 dmae->comp_addr_lo = (dmae_reg_go_c[loader_idx] >> 2);
334 dmae->comp_addr_hi = 0;
337 /* EMAC_REG_EMAC_TX_STAT_AC (EMAC_REG_EMAC_TX_STAT_AC_COUNT)*/
338 dmae = BNX2X_SP(sc, dmae[sc->executer_idx++]);
339 dmae->opcode = opcode;
340 dmae->src_addr_lo = ((mac_addr + EMAC_REG_EMAC_TX_STAT_AC) >> 2);
341 dmae->src_addr_hi = 0;
342 dmae->dst_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, mac_stats) +
343 offsetof(struct emac_stats,
344 tx_stat_ifhcoutoctets));
345 dmae->dst_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, mac_stats) +
346 offsetof(struct emac_stats,
347 tx_stat_ifhcoutoctets));
348 dmae->len = EMAC_REG_EMAC_TX_STAT_AC_COUNT;
349 dmae->comp_addr_lo = (dmae_reg_go_c[loader_idx] >> 2);
350 dmae->comp_addr_hi = 0;
353 uint32_t tx_src_addr_lo, rx_src_addr_lo;
354 uint16_t rx_len, tx_len;
356 /* configure the params according to MAC type */
357 switch (sc->link_vars.mac_type) {
358 case ELINK_MAC_TYPE_BMAC:
359 mac_addr = (port) ? NIG_REG_INGRESS_BMAC1_MEM :
360 NIG_REG_INGRESS_BMAC0_MEM;
362 /* BIGMAC_REGISTER_TX_STAT_GTPKT ..
363 BIGMAC_REGISTER_TX_STAT_GTBYT */
364 if (CHIP_IS_E1x(sc)) {
366 ((mac_addr + BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2);
367 tx_len = ((8 + BIGMAC_REGISTER_TX_STAT_GTBYT -
368 BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2);
370 ((mac_addr + BIGMAC_REGISTER_RX_STAT_GR64) >> 2);
371 rx_len = ((8 + BIGMAC_REGISTER_RX_STAT_GRIPJ -
372 BIGMAC_REGISTER_RX_STAT_GR64) >> 2);
375 ((mac_addr + BIGMAC2_REGISTER_TX_STAT_GTPOK) >> 2);
376 tx_len = ((8 + BIGMAC2_REGISTER_TX_STAT_GTBYT -
377 BIGMAC2_REGISTER_TX_STAT_GTPOK) >> 2);
379 ((mac_addr + BIGMAC2_REGISTER_RX_STAT_GR64) >> 2);
380 rx_len = ((8 + BIGMAC2_REGISTER_RX_STAT_GRIPJ -
381 BIGMAC2_REGISTER_RX_STAT_GR64) >> 2);
386 case ELINK_MAC_TYPE_UMAC: /* handled by MSTAT */
387 case ELINK_MAC_TYPE_XMAC: /* handled by MSTAT */
389 mac_addr = (port) ? GRCBASE_MSTAT1 : GRCBASE_MSTAT0;
390 tx_src_addr_lo = ((mac_addr + MSTAT_REG_TX_STAT_GTXPOK_LO) >> 2);
391 rx_src_addr_lo = ((mac_addr + MSTAT_REG_RX_STAT_GR64_LO) >> 2);
393 (sizeof(sc->sp->mac_stats.mstat_stats.stats_tx) >> 2);
395 (sizeof(sc->sp->mac_stats.mstat_stats.stats_rx) >> 2);
400 dmae = BNX2X_SP(sc, dmae[sc->executer_idx++]);
401 dmae->opcode = opcode;
402 dmae->src_addr_lo = tx_src_addr_lo;
403 dmae->src_addr_hi = 0;
405 dmae->dst_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, mac_stats));
406 dmae->dst_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, mac_stats));
407 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
408 dmae->comp_addr_hi = 0;
412 dmae = BNX2X_SP(sc, dmae[sc->executer_idx++]);
413 dmae->opcode = opcode;
414 dmae->src_addr_hi = 0;
415 dmae->src_addr_lo = rx_src_addr_lo;
417 U64_LO(BNX2X_SP_MAPPING(sc, mac_stats) + (tx_len << 2));
419 U64_HI(BNX2X_SP_MAPPING(sc, mac_stats) + (tx_len << 2));
421 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
422 dmae->comp_addr_hi = 0;
427 if (!CHIP_IS_E3(sc)) {
428 dmae = BNX2X_SP(sc, dmae[sc->executer_idx++]);
429 dmae->opcode = opcode;
431 (port ? NIG_REG_STAT1_EGRESS_MAC_PKT0 :
432 NIG_REG_STAT0_EGRESS_MAC_PKT0) >> 2;
433 dmae->src_addr_hi = 0;
434 dmae->dst_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, nig_stats) +
435 offsetof(struct nig_stats,
436 egress_mac_pkt0_lo));
437 dmae->dst_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, nig_stats) +
438 offsetof(struct nig_stats,
439 egress_mac_pkt0_lo));
440 dmae->len = ((2 * sizeof(uint32_t)) >> 2);
441 dmae->comp_addr_lo = (dmae_reg_go_c[loader_idx] >> 2);
442 dmae->comp_addr_hi = 0;
445 dmae = BNX2X_SP(sc, dmae[sc->executer_idx++]);
446 dmae->opcode = opcode;
448 (port ? NIG_REG_STAT1_EGRESS_MAC_PKT1 :
449 NIG_REG_STAT0_EGRESS_MAC_PKT1) >> 2;
450 dmae->src_addr_hi = 0;
451 dmae->dst_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, nig_stats) +
452 offsetof(struct nig_stats,
453 egress_mac_pkt1_lo));
454 dmae->dst_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, nig_stats) +
455 offsetof(struct nig_stats,
456 egress_mac_pkt1_lo));
457 dmae->len = ((2 * sizeof(uint32_t)) >> 2);
458 dmae->comp_addr_lo = (dmae_reg_go_c[loader_idx] >> 2);
459 dmae->comp_addr_hi = 0;
463 dmae = BNX2X_SP(sc, dmae[sc->executer_idx++]);
464 dmae->opcode = bnx2x_dmae_opcode(sc, DMAE_SRC_GRC, DMAE_DST_PCI,
465 TRUE, DMAE_COMP_PCI);
467 (port ? NIG_REG_STAT1_BRB_DISCARD :
468 NIG_REG_STAT0_BRB_DISCARD) >> 2;
469 dmae->src_addr_hi = 0;
470 dmae->dst_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, nig_stats));
471 dmae->dst_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, nig_stats));
472 dmae->len = (sizeof(struct nig_stats) - 4*sizeof(uint32_t)) >> 2;
474 dmae->comp_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, stats_comp));
475 dmae->comp_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, stats_comp));
476 dmae->comp_val = DMAE_COMP_VAL;
482 bnx2x_func_stats_init(struct bnx2x_softc *sc)
484 struct dmae_command *dmae = &sc->stats_dmae;
485 uint32_t *stats_comp = BNX2X_SP(sc, stats_comp);
489 PMD_DRV_LOG(ERR, "BUG!");
493 sc->executer_idx = 0;
494 memset(dmae, 0, sizeof(struct dmae_command));
496 dmae->opcode = bnx2x_dmae_opcode(sc, DMAE_SRC_PCI, DMAE_DST_GRC,
497 TRUE, DMAE_COMP_PCI);
498 dmae->src_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, func_stats));
499 dmae->src_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, func_stats));
500 dmae->dst_addr_lo = (sc->func_stx >> 2);
501 dmae->dst_addr_hi = 0;
502 dmae->len = (sizeof(struct host_func_stats) >> 2);
503 dmae->comp_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, stats_comp));
504 dmae->comp_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, stats_comp));
505 dmae->comp_val = DMAE_COMP_VAL;
511 bnx2x_stats_start(struct bnx2x_softc *sc)
514 * VFs travel through here as part of the statistics FSM, but no action
522 bnx2x_port_stats_init(sc);
525 else if (sc->func_stx) {
526 bnx2x_func_stats_init(sc);
529 bnx2x_hw_stats_post(sc);
530 bnx2x_storm_stats_post(sc);
534 bnx2x_stats_pmf_start(struct bnx2x_softc *sc)
536 bnx2x_stats_comp(sc);
537 bnx2x_stats_pmf_update(sc);
538 bnx2x_stats_start(sc);
542 bnx2x_stats_restart(struct bnx2x_softc *sc)
545 * VFs travel through here as part of the statistics FSM, but no action
552 bnx2x_stats_comp(sc);
553 bnx2x_stats_start(sc);
557 bnx2x_bmac_stats_update(struct bnx2x_softc *sc)
559 struct host_port_stats *pstats = BNX2X_SP(sc, port_stats);
560 struct bnx2x_eth_stats *estats = &sc->eth_stats;
566 if (CHIP_IS_E1x(sc)) {
567 struct bmac1_stats *new = BNX2X_SP(sc, mac_stats.bmac1_stats);
569 /* the macros below will use "bmac1_stats" type */
570 UPDATE_STAT64(rx_stat_grerb, rx_stat_ifhcinbadoctets);
571 UPDATE_STAT64(rx_stat_grfcs, rx_stat_dot3statsfcserrors);
572 UPDATE_STAT64(rx_stat_grund, rx_stat_etherstatsundersizepkts);
573 UPDATE_STAT64(rx_stat_grovr, rx_stat_dot3statsframestoolong);
574 UPDATE_STAT64(rx_stat_grfrg, rx_stat_etherstatsfragments);
575 UPDATE_STAT64(rx_stat_grjbr, rx_stat_etherstatsjabbers);
576 UPDATE_STAT64(rx_stat_grxcf, rx_stat_maccontrolframesreceived);
577 UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffstateentered);
578 UPDATE_STAT64(rx_stat_grxpf, rx_stat_mac_xpf);
580 UPDATE_STAT64(tx_stat_gtxpf, tx_stat_outxoffsent);
581 UPDATE_STAT64(tx_stat_gtxpf, tx_stat_flowcontroldone);
582 UPDATE_STAT64(tx_stat_gt64, tx_stat_etherstatspkts64octets);
583 UPDATE_STAT64(tx_stat_gt127,
584 tx_stat_etherstatspkts65octetsto127octets);
585 UPDATE_STAT64(tx_stat_gt255,
586 tx_stat_etherstatspkts128octetsto255octets);
587 UPDATE_STAT64(tx_stat_gt511,
588 tx_stat_etherstatspkts256octetsto511octets);
589 UPDATE_STAT64(tx_stat_gt1023,
590 tx_stat_etherstatspkts512octetsto1023octets);
591 UPDATE_STAT64(tx_stat_gt1518,
592 tx_stat_etherstatspkts1024octetsto1522octets);
593 UPDATE_STAT64(tx_stat_gt2047, tx_stat_mac_2047);
594 UPDATE_STAT64(tx_stat_gt4095, tx_stat_mac_4095);
595 UPDATE_STAT64(tx_stat_gt9216, tx_stat_mac_9216);
596 UPDATE_STAT64(tx_stat_gt16383, tx_stat_mac_16383);
597 UPDATE_STAT64(tx_stat_gterr,
598 tx_stat_dot3statsinternalmactransmiterrors);
599 UPDATE_STAT64(tx_stat_gtufl, tx_stat_mac_ufl);
601 struct bmac2_stats *new = BNX2X_SP(sc, mac_stats.bmac2_stats);
602 struct bnx2x_fw_port_stats_old *fwstats = &sc->fw_stats_old;
604 /* the macros below will use "bmac2_stats" type */
605 UPDATE_STAT64(rx_stat_grerb, rx_stat_ifhcinbadoctets);
606 UPDATE_STAT64(rx_stat_grfcs, rx_stat_dot3statsfcserrors);
607 UPDATE_STAT64(rx_stat_grund, rx_stat_etherstatsundersizepkts);
608 UPDATE_STAT64(rx_stat_grovr, rx_stat_dot3statsframestoolong);
609 UPDATE_STAT64(rx_stat_grfrg, rx_stat_etherstatsfragments);
610 UPDATE_STAT64(rx_stat_grjbr, rx_stat_etherstatsjabbers);
611 UPDATE_STAT64(rx_stat_grxcf, rx_stat_maccontrolframesreceived);
612 UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffstateentered);
613 UPDATE_STAT64(rx_stat_grxpf, rx_stat_mac_xpf);
614 UPDATE_STAT64(tx_stat_gtxpf, tx_stat_outxoffsent);
615 UPDATE_STAT64(tx_stat_gtxpf, tx_stat_flowcontroldone);
616 UPDATE_STAT64(tx_stat_gt64, tx_stat_etherstatspkts64octets);
617 UPDATE_STAT64(tx_stat_gt127,
618 tx_stat_etherstatspkts65octetsto127octets);
619 UPDATE_STAT64(tx_stat_gt255,
620 tx_stat_etherstatspkts128octetsto255octets);
621 UPDATE_STAT64(tx_stat_gt511,
622 tx_stat_etherstatspkts256octetsto511octets);
623 UPDATE_STAT64(tx_stat_gt1023,
624 tx_stat_etherstatspkts512octetsto1023octets);
625 UPDATE_STAT64(tx_stat_gt1518,
626 tx_stat_etherstatspkts1024octetsto1522octets);
627 UPDATE_STAT64(tx_stat_gt2047, tx_stat_mac_2047);
628 UPDATE_STAT64(tx_stat_gt4095, tx_stat_mac_4095);
629 UPDATE_STAT64(tx_stat_gt9216, tx_stat_mac_9216);
630 UPDATE_STAT64(tx_stat_gt16383, tx_stat_mac_16383);
631 UPDATE_STAT64(tx_stat_gterr,
632 tx_stat_dot3statsinternalmactransmiterrors);
633 UPDATE_STAT64(tx_stat_gtufl, tx_stat_mac_ufl);
635 /* collect PFC stats */
636 pstats->pfc_frames_tx_hi = new->tx_stat_gtpp_hi;
637 pstats->pfc_frames_tx_lo = new->tx_stat_gtpp_lo;
638 ADD_64(pstats->pfc_frames_tx_hi, fwstats->pfc_frames_tx_hi,
639 pstats->pfc_frames_tx_lo, fwstats->pfc_frames_tx_lo);
641 pstats->pfc_frames_rx_hi = new->rx_stat_grpp_hi;
642 pstats->pfc_frames_rx_lo = new->rx_stat_grpp_lo;
643 ADD_64(pstats->pfc_frames_rx_hi, fwstats->pfc_frames_rx_hi,
644 pstats->pfc_frames_rx_lo, fwstats->pfc_frames_rx_lo);
647 estats->pause_frames_received_hi = pstats->mac_stx[1].rx_stat_mac_xpf_hi;
648 estats->pause_frames_received_lo = pstats->mac_stx[1].rx_stat_mac_xpf_lo;
650 estats->pause_frames_sent_hi = pstats->mac_stx[1].tx_stat_outxoffsent_hi;
651 estats->pause_frames_sent_lo = pstats->mac_stx[1].tx_stat_outxoffsent_lo;
653 estats->pfc_frames_received_hi = pstats->pfc_frames_rx_hi;
654 estats->pfc_frames_received_lo = pstats->pfc_frames_rx_lo;
655 estats->pfc_frames_sent_hi = pstats->pfc_frames_tx_hi;
656 estats->pfc_frames_sent_lo = pstats->pfc_frames_tx_lo;
660 bnx2x_mstat_stats_update(struct bnx2x_softc *sc)
662 struct host_port_stats *pstats = BNX2X_SP(sc, port_stats);
663 struct bnx2x_eth_stats *estats = &sc->eth_stats;
664 struct mstat_stats *new = BNX2X_SP(sc, mac_stats.mstat_stats);
666 ADD_STAT64(stats_rx.rx_grerb, rx_stat_ifhcinbadoctets);
667 ADD_STAT64(stats_rx.rx_grfcs, rx_stat_dot3statsfcserrors);
668 ADD_STAT64(stats_rx.rx_grund, rx_stat_etherstatsundersizepkts);
669 ADD_STAT64(stats_rx.rx_grovr, rx_stat_dot3statsframestoolong);
670 ADD_STAT64(stats_rx.rx_grfrg, rx_stat_etherstatsfragments);
671 ADD_STAT64(stats_rx.rx_grxcf, rx_stat_maccontrolframesreceived);
672 ADD_STAT64(stats_rx.rx_grxpf, rx_stat_xoffstateentered);
673 ADD_STAT64(stats_rx.rx_grxpf, rx_stat_mac_xpf);
674 ADD_STAT64(stats_tx.tx_gtxpf, tx_stat_outxoffsent);
675 ADD_STAT64(stats_tx.tx_gtxpf, tx_stat_flowcontroldone);
677 /* collect pfc stats */
678 ADD_64(pstats->pfc_frames_tx_hi, new->stats_tx.tx_gtxpp_hi,
679 pstats->pfc_frames_tx_lo, new->stats_tx.tx_gtxpp_lo);
680 ADD_64(pstats->pfc_frames_rx_hi, new->stats_rx.rx_grxpp_hi,
681 pstats->pfc_frames_rx_lo, new->stats_rx.rx_grxpp_lo);
683 ADD_STAT64(stats_tx.tx_gt64, tx_stat_etherstatspkts64octets);
684 ADD_STAT64(stats_tx.tx_gt127, tx_stat_etherstatspkts65octetsto127octets);
685 ADD_STAT64(stats_tx.tx_gt255, tx_stat_etherstatspkts128octetsto255octets);
686 ADD_STAT64(stats_tx.tx_gt511, tx_stat_etherstatspkts256octetsto511octets);
687 ADD_STAT64(stats_tx.tx_gt1023,
688 tx_stat_etherstatspkts512octetsto1023octets);
689 ADD_STAT64(stats_tx.tx_gt1518,
690 tx_stat_etherstatspkts1024octetsto1522octets);
691 ADD_STAT64(stats_tx.tx_gt2047, tx_stat_mac_2047);
693 ADD_STAT64(stats_tx.tx_gt4095, tx_stat_mac_4095);
694 ADD_STAT64(stats_tx.tx_gt9216, tx_stat_mac_9216);
695 ADD_STAT64(stats_tx.tx_gt16383, tx_stat_mac_16383);
697 ADD_STAT64(stats_tx.tx_gterr, tx_stat_dot3statsinternalmactransmiterrors);
698 ADD_STAT64(stats_tx.tx_gtufl, tx_stat_mac_ufl);
700 estats->etherstatspkts1024octetsto1522octets_hi =
701 pstats->mac_stx[1].tx_stat_etherstatspkts1024octetsto1522octets_hi;
702 estats->etherstatspkts1024octetsto1522octets_lo =
703 pstats->mac_stx[1].tx_stat_etherstatspkts1024octetsto1522octets_lo;
705 estats->etherstatspktsover1522octets_hi =
706 pstats->mac_stx[1].tx_stat_mac_2047_hi;
707 estats->etherstatspktsover1522octets_lo =
708 pstats->mac_stx[1].tx_stat_mac_2047_lo;
710 ADD_64(estats->etherstatspktsover1522octets_hi,
711 pstats->mac_stx[1].tx_stat_mac_4095_hi,
712 estats->etherstatspktsover1522octets_lo,
713 pstats->mac_stx[1].tx_stat_mac_4095_lo);
715 ADD_64(estats->etherstatspktsover1522octets_hi,
716 pstats->mac_stx[1].tx_stat_mac_9216_hi,
717 estats->etherstatspktsover1522octets_lo,
718 pstats->mac_stx[1].tx_stat_mac_9216_lo);
720 ADD_64(estats->etherstatspktsover1522octets_hi,
721 pstats->mac_stx[1].tx_stat_mac_16383_hi,
722 estats->etherstatspktsover1522octets_lo,
723 pstats->mac_stx[1].tx_stat_mac_16383_lo);
725 estats->pause_frames_received_hi = pstats->mac_stx[1].rx_stat_mac_xpf_hi;
726 estats->pause_frames_received_lo = pstats->mac_stx[1].rx_stat_mac_xpf_lo;
728 estats->pause_frames_sent_hi = pstats->mac_stx[1].tx_stat_outxoffsent_hi;
729 estats->pause_frames_sent_lo = pstats->mac_stx[1].tx_stat_outxoffsent_lo;
731 estats->pfc_frames_received_hi = pstats->pfc_frames_rx_hi;
732 estats->pfc_frames_received_lo = pstats->pfc_frames_rx_lo;
733 estats->pfc_frames_sent_hi = pstats->pfc_frames_tx_hi;
734 estats->pfc_frames_sent_lo = pstats->pfc_frames_tx_lo;
738 bnx2x_emac_stats_update(struct bnx2x_softc *sc)
740 struct emac_stats *new = BNX2X_SP(sc, mac_stats.emac_stats);
741 struct host_port_stats *pstats = BNX2X_SP(sc, port_stats);
742 struct bnx2x_eth_stats *estats = &sc->eth_stats;
744 UPDATE_EXTEND_STAT(rx_stat_ifhcinbadoctets);
745 UPDATE_EXTEND_STAT(tx_stat_ifhcoutbadoctets);
746 UPDATE_EXTEND_STAT(rx_stat_dot3statsfcserrors);
747 UPDATE_EXTEND_STAT(rx_stat_dot3statsalignmenterrors);
748 UPDATE_EXTEND_STAT(rx_stat_dot3statscarriersenseerrors);
749 UPDATE_EXTEND_STAT(rx_stat_falsecarriererrors);
750 UPDATE_EXTEND_STAT(rx_stat_etherstatsundersizepkts);
751 UPDATE_EXTEND_STAT(rx_stat_dot3statsframestoolong);
752 UPDATE_EXTEND_STAT(rx_stat_etherstatsfragments);
753 UPDATE_EXTEND_STAT(rx_stat_etherstatsjabbers);
754 UPDATE_EXTEND_STAT(rx_stat_maccontrolframesreceived);
755 UPDATE_EXTEND_STAT(rx_stat_xoffstateentered);
756 UPDATE_EXTEND_STAT(rx_stat_xonpauseframesreceived);
757 UPDATE_EXTEND_STAT(rx_stat_xoffpauseframesreceived);
758 UPDATE_EXTEND_STAT(tx_stat_outxonsent);
759 UPDATE_EXTEND_STAT(tx_stat_outxoffsent);
760 UPDATE_EXTEND_STAT(tx_stat_flowcontroldone);
761 UPDATE_EXTEND_STAT(tx_stat_etherstatscollisions);
762 UPDATE_EXTEND_STAT(tx_stat_dot3statssinglecollisionframes);
763 UPDATE_EXTEND_STAT(tx_stat_dot3statsmultiplecollisionframes);
764 UPDATE_EXTEND_STAT(tx_stat_dot3statsdeferredtransmissions);
765 UPDATE_EXTEND_STAT(tx_stat_dot3statsexcessivecollisions);
766 UPDATE_EXTEND_STAT(tx_stat_dot3statslatecollisions);
767 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts64octets);
768 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts65octetsto127octets);
769 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts128octetsto255octets);
770 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts256octetsto511octets);
771 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts512octetsto1023octets);
772 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts1024octetsto1522octets);
773 UPDATE_EXTEND_STAT(tx_stat_etherstatspktsover1522octets);
774 UPDATE_EXTEND_STAT(tx_stat_dot3statsinternalmactransmiterrors);
776 estats->pause_frames_received_hi =
777 pstats->mac_stx[1].rx_stat_xonpauseframesreceived_hi;
778 estats->pause_frames_received_lo =
779 pstats->mac_stx[1].rx_stat_xonpauseframesreceived_lo;
780 ADD_64(estats->pause_frames_received_hi,
781 pstats->mac_stx[1].rx_stat_xoffpauseframesreceived_hi,
782 estats->pause_frames_received_lo,
783 pstats->mac_stx[1].rx_stat_xoffpauseframesreceived_lo);
785 estats->pause_frames_sent_hi =
786 pstats->mac_stx[1].tx_stat_outxonsent_hi;
787 estats->pause_frames_sent_lo =
788 pstats->mac_stx[1].tx_stat_outxonsent_lo;
789 ADD_64(estats->pause_frames_sent_hi,
790 pstats->mac_stx[1].tx_stat_outxoffsent_hi,
791 estats->pause_frames_sent_lo,
792 pstats->mac_stx[1].tx_stat_outxoffsent_lo);
796 bnx2x_hw_stats_update(struct bnx2x_softc *sc)
798 struct nig_stats *new = BNX2X_SP(sc, nig_stats);
799 struct nig_stats *old = &(sc->port.old_nig_stats);
800 struct host_port_stats *pstats = BNX2X_SP(sc, port_stats);
801 struct bnx2x_eth_stats *estats = &sc->eth_stats;
802 uint32_t lpi_reg, nig_timer_max;
808 switch (sc->link_vars.mac_type) {
809 case ELINK_MAC_TYPE_BMAC:
810 bnx2x_bmac_stats_update(sc);
813 case ELINK_MAC_TYPE_EMAC:
814 bnx2x_emac_stats_update(sc);
817 case ELINK_MAC_TYPE_UMAC:
818 case ELINK_MAC_TYPE_XMAC:
819 bnx2x_mstat_stats_update(sc);
822 case ELINK_MAC_TYPE_NONE: /* unreached */
824 "stats updated by DMAE but no MAC active");
827 default: /* unreached */
828 PMD_DRV_LOG(ERR, "stats update failed, unknown MAC type");
831 ADD_EXTEND_64(pstats->brb_drop_hi, pstats->brb_drop_lo,
832 new->brb_discard - old->brb_discard);
833 ADD_EXTEND_64(estats->brb_truncate_hi, estats->brb_truncate_lo,
834 new->brb_truncate - old->brb_truncate);
836 if (!CHIP_IS_E3(sc)) {
837 UPDATE_STAT64_NIG(egress_mac_pkt0,
838 etherstatspkts1024octetsto1522octets);
839 UPDATE_STAT64_NIG(egress_mac_pkt1,
840 etherstatspktsover1522octets);
843 rte_memcpy(old, new, sizeof(struct nig_stats));
845 rte_memcpy(&(estats->rx_stat_ifhcinbadoctets_hi), &(pstats->mac_stx[1]),
846 sizeof(struct mac_stx));
847 estats->brb_drop_hi = pstats->brb_drop_hi;
848 estats->brb_drop_lo = pstats->brb_drop_lo;
850 pstats->host_port_stats_counter++;
852 if (CHIP_IS_E3(sc)) {
853 lpi_reg = (SC_PORT(sc)) ?
854 MISC_REG_CPMU_LP_SM_ENT_CNT_P1 :
855 MISC_REG_CPMU_LP_SM_ENT_CNT_P0;
856 estats->eee_tx_lpi += REG_RD(sc, lpi_reg);
859 if (!BNX2X_NOMCP(sc)) {
860 nig_timer_max = SHMEM_RD(sc, port_mb[SC_PORT(sc)].stat_nig_timer);
861 if (nig_timer_max != estats->nig_timer_max) {
862 estats->nig_timer_max = nig_timer_max;
863 PMD_DRV_LOG(ERR, "invalid NIG timer max (%u)",
864 estats->nig_timer_max);
872 bnx2x_storm_stats_validate_counters(struct bnx2x_softc *sc)
874 struct stats_counter *counters = &sc->fw_stats_data->storm_counters;
875 uint16_t cur_stats_counter;
878 * Make sure we use the value of the counter
879 * used for sending the last stats ramrod.
881 cur_stats_counter = (sc->stats_counter - 1);
883 /* are storm stats valid? */
884 if (le16toh(counters->xstats_counter) != cur_stats_counter) {
886 "stats not updated by xstorm, "
887 "counter 0x%x != stats_counter 0x%x",
888 le16toh(counters->xstats_counter), sc->stats_counter);
892 if (le16toh(counters->ustats_counter) != cur_stats_counter) {
894 "stats not updated by ustorm, "
895 "counter 0x%x != stats_counter 0x%x",
896 le16toh(counters->ustats_counter), sc->stats_counter);
900 if (le16toh(counters->cstats_counter) != cur_stats_counter) {
902 "stats not updated by cstorm, "
903 "counter 0x%x != stats_counter 0x%x",
904 le16toh(counters->cstats_counter), sc->stats_counter);
908 if (le16toh(counters->tstats_counter) != cur_stats_counter) {
910 "stats not updated by tstorm, "
911 "counter 0x%x != stats_counter 0x%x",
912 le16toh(counters->tstats_counter), sc->stats_counter);
920 bnx2x_storm_stats_update(struct bnx2x_softc *sc)
922 struct tstorm_per_port_stats *tport =
923 &sc->fw_stats_data->port.tstorm_port_statistics;
924 struct tstorm_per_pf_stats *tfunc =
925 &sc->fw_stats_data->pf.tstorm_pf_statistics;
926 struct host_func_stats *fstats = &sc->func_stats;
927 struct bnx2x_eth_stats *estats = &sc->eth_stats;
928 struct bnx2x_eth_stats_old *estats_old = &sc->eth_stats_old;
931 /* vfs stat counter is managed by pf */
932 if (IS_PF(sc) && bnx2x_storm_stats_validate_counters(sc)) {
936 estats->error_bytes_received_hi = 0;
937 estats->error_bytes_received_lo = 0;
939 for (i = 0; i < sc->num_queues; i++) {
940 struct bnx2x_fastpath *fp = &sc->fp[i];
941 struct tstorm_per_queue_stats *tclient =
942 &sc->fw_stats_data->queue_stats[i].tstorm_queue_statistics;
943 struct tstorm_per_queue_stats *old_tclient = &fp->old_tclient;
944 struct ustorm_per_queue_stats *uclient =
945 &sc->fw_stats_data->queue_stats[i].ustorm_queue_statistics;
946 struct ustorm_per_queue_stats *old_uclient = &fp->old_uclient;
947 struct xstorm_per_queue_stats *xclient =
948 &sc->fw_stats_data->queue_stats[i].xstorm_queue_statistics;
949 struct xstorm_per_queue_stats *old_xclient = &fp->old_xclient;
950 struct bnx2x_eth_q_stats *qstats = &fp->eth_q_stats;
951 struct bnx2x_eth_q_stats_old *qstats_old = &fp->eth_q_stats_old;
955 /* PMD_DRV_LOG(DEBUG,
956 "queue[%d]: ucast_sent 0x%x bcast_sent 0x%x mcast_sent 0x%x",
957 i, xclient->ucast_pkts_sent, xclient->bcast_pkts_sent,
958 xclient->mcast_pkts_sent);
960 PMD_DRV_LOG(DEBUG, "---------------"); */
962 UPDATE_QSTAT(tclient->rcv_bcast_bytes,
963 total_broadcast_bytes_received);
964 UPDATE_QSTAT(tclient->rcv_mcast_bytes,
965 total_multicast_bytes_received);
966 UPDATE_QSTAT(tclient->rcv_ucast_bytes,
967 total_unicast_bytes_received);
970 * sum to total_bytes_received all
971 * unicast/multicast/broadcast
973 qstats->total_bytes_received_hi =
974 qstats->total_broadcast_bytes_received_hi;
975 qstats->total_bytes_received_lo =
976 qstats->total_broadcast_bytes_received_lo;
978 ADD_64(qstats->total_bytes_received_hi,
979 qstats->total_multicast_bytes_received_hi,
980 qstats->total_bytes_received_lo,
981 qstats->total_multicast_bytes_received_lo);
983 ADD_64(qstats->total_bytes_received_hi,
984 qstats->total_unicast_bytes_received_hi,
985 qstats->total_bytes_received_lo,
986 qstats->total_unicast_bytes_received_lo);
988 qstats->valid_bytes_received_hi = qstats->total_bytes_received_hi;
989 qstats->valid_bytes_received_lo = qstats->total_bytes_received_lo;
991 UPDATE_EXTEND_TSTAT(rcv_ucast_pkts, total_unicast_packets_received);
992 UPDATE_EXTEND_TSTAT(rcv_mcast_pkts, total_multicast_packets_received);
993 UPDATE_EXTEND_TSTAT(rcv_bcast_pkts, total_broadcast_packets_received);
994 UPDATE_EXTEND_E_TSTAT(pkts_too_big_discard,
995 etherstatsoverrsizepkts, 32);
996 UPDATE_EXTEND_E_TSTAT(no_buff_discard, no_buff_discard, 16);
998 SUB_EXTEND_USTAT(ucast_no_buff_pkts, total_unicast_packets_received);
999 SUB_EXTEND_USTAT(mcast_no_buff_pkts,
1000 total_multicast_packets_received);
1001 SUB_EXTEND_USTAT(bcast_no_buff_pkts,
1002 total_broadcast_packets_received);
1003 UPDATE_EXTEND_E_USTAT(ucast_no_buff_pkts, no_buff_discard);
1004 UPDATE_EXTEND_E_USTAT(mcast_no_buff_pkts, no_buff_discard);
1005 UPDATE_EXTEND_E_USTAT(bcast_no_buff_pkts, no_buff_discard);
1007 UPDATE_QSTAT(xclient->bcast_bytes_sent,
1008 total_broadcast_bytes_transmitted);
1009 UPDATE_QSTAT(xclient->mcast_bytes_sent,
1010 total_multicast_bytes_transmitted);
1011 UPDATE_QSTAT(xclient->ucast_bytes_sent,
1012 total_unicast_bytes_transmitted);
1015 * sum to total_bytes_transmitted all
1016 * unicast/multicast/broadcast
1018 qstats->total_bytes_transmitted_hi =
1019 qstats->total_unicast_bytes_transmitted_hi;
1020 qstats->total_bytes_transmitted_lo =
1021 qstats->total_unicast_bytes_transmitted_lo;
1023 ADD_64(qstats->total_bytes_transmitted_hi,
1024 qstats->total_broadcast_bytes_transmitted_hi,
1025 qstats->total_bytes_transmitted_lo,
1026 qstats->total_broadcast_bytes_transmitted_lo);
1028 ADD_64(qstats->total_bytes_transmitted_hi,
1029 qstats->total_multicast_bytes_transmitted_hi,
1030 qstats->total_bytes_transmitted_lo,
1031 qstats->total_multicast_bytes_transmitted_lo);
1033 UPDATE_EXTEND_XSTAT(ucast_pkts_sent,
1034 total_unicast_packets_transmitted);
1035 UPDATE_EXTEND_XSTAT(mcast_pkts_sent,
1036 total_multicast_packets_transmitted);
1037 UPDATE_EXTEND_XSTAT(bcast_pkts_sent,
1038 total_broadcast_packets_transmitted);
1040 UPDATE_EXTEND_TSTAT(checksum_discard,
1041 total_packets_received_checksum_discarded);
1042 UPDATE_EXTEND_TSTAT(ttl0_discard,
1043 total_packets_received_ttl0_discarded);
1045 UPDATE_EXTEND_XSTAT(error_drop_pkts,
1046 total_transmitted_dropped_packets_error);
1048 UPDATE_FSTAT_QSTAT(total_bytes_received);
1049 UPDATE_FSTAT_QSTAT(total_bytes_transmitted);
1050 UPDATE_FSTAT_QSTAT(total_unicast_packets_received);
1051 UPDATE_FSTAT_QSTAT(total_multicast_packets_received);
1052 UPDATE_FSTAT_QSTAT(total_broadcast_packets_received);
1053 UPDATE_FSTAT_QSTAT(total_unicast_packets_transmitted);
1054 UPDATE_FSTAT_QSTAT(total_multicast_packets_transmitted);
1055 UPDATE_FSTAT_QSTAT(total_broadcast_packets_transmitted);
1056 UPDATE_FSTAT_QSTAT(valid_bytes_received);
1059 ADD_64(estats->total_bytes_received_hi,
1060 estats->rx_stat_ifhcinbadoctets_hi,
1061 estats->total_bytes_received_lo,
1062 estats->rx_stat_ifhcinbadoctets_lo);
1064 ADD_64_LE(estats->total_bytes_received_hi,
1065 tfunc->rcv_error_bytes.hi,
1066 estats->total_bytes_received_lo,
1067 tfunc->rcv_error_bytes.lo);
1069 ADD_64_LE(estats->error_bytes_received_hi,
1070 tfunc->rcv_error_bytes.hi,
1071 estats->error_bytes_received_lo,
1072 tfunc->rcv_error_bytes.lo);
1074 UPDATE_ESTAT(etherstatsoverrsizepkts, rx_stat_dot3statsframestoolong);
1076 ADD_64(estats->error_bytes_received_hi,
1077 estats->rx_stat_ifhcinbadoctets_hi,
1078 estats->error_bytes_received_lo,
1079 estats->rx_stat_ifhcinbadoctets_lo);
1082 struct bnx2x_fw_port_stats_old *fwstats = &sc->fw_stats_old;
1083 UPDATE_FW_STAT(mac_filter_discard);
1084 UPDATE_FW_STAT(mf_tag_discard);
1085 UPDATE_FW_STAT(brb_truncate_discard);
1086 UPDATE_FW_STAT(mac_discard);
1089 fstats->host_func_stats_start = ++fstats->host_func_stats_end;
1091 sc->stats_pending = 0;
1097 bnx2x_drv_stats_update(struct bnx2x_softc *sc)
1099 struct bnx2x_eth_stats *estats = &sc->eth_stats;
1102 for (i = 0; i < sc->num_queues; i++) {
1103 struct bnx2x_eth_q_stats *qstats = &sc->fp[i].eth_q_stats;
1104 struct bnx2x_eth_q_stats_old *qstats_old = &sc->fp[i].eth_q_stats_old;
1106 UPDATE_ESTAT_QSTAT(rx_calls);
1107 UPDATE_ESTAT_QSTAT(rx_pkts);
1108 UPDATE_ESTAT_QSTAT(rx_soft_errors);
1109 UPDATE_ESTAT_QSTAT(rx_hw_csum_errors);
1110 UPDATE_ESTAT_QSTAT(rx_ofld_frames_csum_ip);
1111 UPDATE_ESTAT_QSTAT(rx_ofld_frames_csum_tcp_udp);
1112 UPDATE_ESTAT_QSTAT(rx_budget_reached);
1113 UPDATE_ESTAT_QSTAT(tx_pkts);
1114 UPDATE_ESTAT_QSTAT(tx_soft_errors);
1115 UPDATE_ESTAT_QSTAT(tx_ofld_frames_csum_ip);
1116 UPDATE_ESTAT_QSTAT(tx_ofld_frames_csum_tcp);
1117 UPDATE_ESTAT_QSTAT(tx_ofld_frames_csum_udp);
1118 UPDATE_ESTAT_QSTAT(tx_encap_failures);
1119 UPDATE_ESTAT_QSTAT(tx_hw_queue_full);
1120 UPDATE_ESTAT_QSTAT(tx_hw_max_queue_depth);
1121 UPDATE_ESTAT_QSTAT(tx_dma_mapping_failure);
1122 UPDATE_ESTAT_QSTAT(tx_max_drbr_queue_depth);
1123 UPDATE_ESTAT_QSTAT(tx_window_violation_std);
1124 UPDATE_ESTAT_QSTAT(tx_chain_lost_mbuf);
1125 UPDATE_ESTAT_QSTAT(tx_frames_deferred);
1126 UPDATE_ESTAT_QSTAT(tx_queue_xoff);
1128 /* mbuf driver statistics */
1129 UPDATE_ESTAT_QSTAT(mbuf_defrag_attempts);
1130 UPDATE_ESTAT_QSTAT(mbuf_defrag_failures);
1131 UPDATE_ESTAT_QSTAT(mbuf_rx_bd_alloc_failed);
1132 UPDATE_ESTAT_QSTAT(mbuf_rx_bd_mapping_failed);
1134 /* track the number of allocated mbufs */
1135 UPDATE_ESTAT_QSTAT(mbuf_alloc_tx);
1136 UPDATE_ESTAT_QSTAT(mbuf_alloc_rx);
1141 bnx2x_edebug_stats_stopped(struct bnx2x_softc *sc)
1145 if (SHMEM2_HAS(sc, edebug_driver_if[1])) {
1146 val = SHMEM2_RD(sc, edebug_driver_if[1]);
1148 if (val == EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT) {
1157 bnx2x_stats_update(struct bnx2x_softc *sc)
1159 uint32_t *stats_comp = BNX2X_SP(sc, stats_comp);
1161 if (bnx2x_edebug_stats_stopped(sc)) {
1167 bnx2x_storm_stats_update(sc);
1168 bnx2x_hw_stats_post(sc);
1169 bnx2x_storm_stats_post(sc);
1172 if (*stats_comp != DMAE_COMP_VAL) {
1177 bnx2x_hw_stats_update(sc);
1180 if (bnx2x_storm_stats_update(sc)) {
1181 if (sc->stats_pending++ == 3) {
1182 rte_panic("storm stats not updated for 3 times");
1188 * VF doesn't collect HW statistics, and doesn't get completions,
1189 * performs only update.
1191 bnx2x_storm_stats_update(sc);
1194 bnx2x_drv_stats_update(sc);
1198 bnx2x_port_stats_stop(struct bnx2x_softc *sc)
1200 struct dmae_command *dmae;
1202 int loader_idx = PMF_DMAE_C(sc);
1203 uint32_t *stats_comp = BNX2X_SP(sc, stats_comp);
1205 sc->executer_idx = 0;
1207 opcode = bnx2x_dmae_opcode(sc, DMAE_SRC_PCI, DMAE_DST_GRC, FALSE, 0);
1209 if (sc->port.port_stx) {
1210 dmae = BNX2X_SP(sc, dmae[sc->executer_idx++]);
1213 dmae->opcode = bnx2x_dmae_opcode_add_comp(opcode, DMAE_COMP_GRC);
1215 dmae->opcode = bnx2x_dmae_opcode_add_comp(opcode, DMAE_COMP_PCI);
1218 dmae->src_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, port_stats));
1219 dmae->src_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, port_stats));
1220 dmae->dst_addr_lo = sc->port.port_stx >> 2;
1221 dmae->dst_addr_hi = 0;
1222 dmae->len = bnx2x_get_port_stats_dma_len(sc);
1224 dmae->comp_addr_lo = (dmae_reg_go_c[loader_idx] >> 2);
1225 dmae->comp_addr_hi = 0;
1228 dmae->comp_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, stats_comp));
1229 dmae->comp_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, stats_comp));
1230 dmae->comp_val = DMAE_COMP_VAL;
1237 dmae = BNX2X_SP(sc, dmae[sc->executer_idx++]);
1238 dmae->opcode = bnx2x_dmae_opcode_add_comp(opcode, DMAE_COMP_PCI);
1239 dmae->src_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, func_stats));
1240 dmae->src_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, func_stats));
1241 dmae->dst_addr_lo = (sc->func_stx >> 2);
1242 dmae->dst_addr_hi = 0;
1243 dmae->len = (sizeof(struct host_func_stats) >> 2);
1244 dmae->comp_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, stats_comp));
1245 dmae->comp_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, stats_comp));
1246 dmae->comp_val = DMAE_COMP_VAL;
1253 bnx2x_stats_stop(struct bnx2x_softc *sc)
1255 uint8_t update = FALSE;
1257 bnx2x_stats_comp(sc);
1260 update = bnx2x_hw_stats_update(sc) == 0;
1263 update |= bnx2x_storm_stats_update(sc) == 0;
1268 bnx2x_port_stats_stop(sc);
1271 bnx2x_hw_stats_post(sc);
1272 bnx2x_stats_comp(sc);
1277 bnx2x_stats_do_nothing(__rte_unused struct bnx2x_softc *sc)
1282 static const struct {
1283 void (*action)(struct bnx2x_softc *sc);
1284 enum bnx2x_stats_state next_state;
1285 } bnx2x_stats_stm[STATS_STATE_MAX][STATS_EVENT_MAX] = {
1287 /* DISABLED PMF */ { bnx2x_stats_pmf_update, STATS_STATE_DISABLED },
1288 /* LINK_UP */ { bnx2x_stats_start, STATS_STATE_ENABLED },
1289 /* UPDATE */ { bnx2x_stats_do_nothing, STATS_STATE_DISABLED },
1290 /* STOP */ { bnx2x_stats_do_nothing, STATS_STATE_DISABLED }
1293 /* ENABLED PMF */ { bnx2x_stats_pmf_start, STATS_STATE_ENABLED },
1294 /* LINK_UP */ { bnx2x_stats_restart, STATS_STATE_ENABLED },
1295 /* UPDATE */ { bnx2x_stats_update, STATS_STATE_ENABLED },
1296 /* STOP */ { bnx2x_stats_stop, STATS_STATE_DISABLED }
1300 void bnx2x_stats_handle(struct bnx2x_softc *sc, enum bnx2x_stats_event event)
1302 enum bnx2x_stats_state state;
1304 if (unlikely(sc->panic)) {
1308 state = sc->stats_state;
1309 sc->stats_state = bnx2x_stats_stm[state][event].next_state;
1311 bnx2x_stats_stm[state][event].action(sc);
1313 if (event != STATS_EVENT_UPDATE) {
1315 "state %d -> event %d -> state %d",
1316 state, event, sc->stats_state);
1321 bnx2x_port_stats_base_init(struct bnx2x_softc *sc)
1323 struct dmae_command *dmae;
1324 uint32_t *stats_comp = BNX2X_SP(sc, stats_comp);
1327 if (!sc->port.pmf || !sc->port.port_stx) {
1328 PMD_DRV_LOG(ERR, "BUG!");
1332 sc->executer_idx = 0;
1334 dmae = BNX2X_SP(sc, dmae[sc->executer_idx++]);
1335 dmae->opcode = bnx2x_dmae_opcode(sc, DMAE_SRC_PCI, DMAE_DST_GRC,
1336 TRUE, DMAE_COMP_PCI);
1337 dmae->src_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, port_stats));
1338 dmae->src_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, port_stats));
1339 dmae->dst_addr_lo = (sc->port.port_stx >> 2);
1340 dmae->dst_addr_hi = 0;
1341 dmae->len = bnx2x_get_port_stats_dma_len(sc);
1342 dmae->comp_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, stats_comp));
1343 dmae->comp_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, stats_comp));
1344 dmae->comp_val = DMAE_COMP_VAL;
1347 bnx2x_hw_stats_post(sc);
1348 bnx2x_stats_comp(sc);
1352 * This function will prepare the statistics ramrod data the way
1353 * we will only have to increment the statistics counter and
1354 * send the ramrod each time we have to.
1357 bnx2x_prep_fw_stats_req(struct bnx2x_softc *sc)
1360 int first_queue_query_index;
1361 struct stats_query_header *stats_hdr = &sc->fw_stats_req->hdr;
1362 phys_addr_t cur_data_offset;
1363 struct stats_query_entry *cur_query_entry;
1365 stats_hdr->cmd_num = sc->fw_stats_num;
1366 stats_hdr->drv_stats_counter = 0;
1369 * The storm_counters struct contains the counters of completed
1370 * statistics requests per storm which are incremented by FW
1371 * each time it completes hadning a statistics ramrod. We will
1372 * check these counters in the timer handler and discard a
1373 * (statistics) ramrod completion.
1375 cur_data_offset = (sc->fw_stats_data_mapping +
1376 offsetof(struct bnx2x_fw_stats_data, storm_counters));
1378 stats_hdr->stats_counters_addrs.hi = htole32(U64_HI(cur_data_offset));
1379 stats_hdr->stats_counters_addrs.lo = htole32(U64_LO(cur_data_offset));
1382 * Prepare the first stats ramrod (will be completed with
1383 * the counters equal to zero) - init counters to somethig different.
1385 memset(&sc->fw_stats_data->storm_counters, 0xff,
1386 sizeof(struct stats_counter));
1388 /**** Port FW statistics data ****/
1389 cur_data_offset = (sc->fw_stats_data_mapping +
1390 offsetof(struct bnx2x_fw_stats_data, port));
1392 cur_query_entry = &sc->fw_stats_req->query[BNX2X_PORT_QUERY_IDX];
1394 cur_query_entry->kind = STATS_TYPE_PORT;
1395 /* For port query index is a DONT CARE */
1396 cur_query_entry->index = SC_PORT(sc);
1397 /* For port query funcID is a DONT CARE */
1398 cur_query_entry->funcID = htole16(SC_FUNC(sc));
1399 cur_query_entry->address.hi = htole32(U64_HI(cur_data_offset));
1400 cur_query_entry->address.lo = htole32(U64_LO(cur_data_offset));
1402 /**** PF FW statistics data ****/
1403 cur_data_offset = (sc->fw_stats_data_mapping +
1404 offsetof(struct bnx2x_fw_stats_data, pf));
1406 cur_query_entry = &sc->fw_stats_req->query[BNX2X_PF_QUERY_IDX];
1408 cur_query_entry->kind = STATS_TYPE_PF;
1409 /* For PF query index is a DONT CARE */
1410 cur_query_entry->index = SC_PORT(sc);
1411 cur_query_entry->funcID = htole16(SC_FUNC(sc));
1412 cur_query_entry->address.hi = htole32(U64_HI(cur_data_offset));
1413 cur_query_entry->address.lo = htole32(U64_LO(cur_data_offset));
1415 /**** Clients' queries ****/
1416 cur_data_offset = (sc->fw_stats_data_mapping +
1417 offsetof(struct bnx2x_fw_stats_data, queue_stats));
1420 * First queue query index depends whether FCoE offloaded request will
1421 * be included in the ramrod
1423 first_queue_query_index = (BNX2X_FIRST_QUEUE_QUERY_IDX - 1);
1425 for (i = 0; i < sc->num_queues; i++) {
1427 &sc->fw_stats_req->query[first_queue_query_index + i];
1429 cur_query_entry->kind = STATS_TYPE_QUEUE;
1430 cur_query_entry->index = bnx2x_stats_id(&sc->fp[i]);
1431 cur_query_entry->funcID = htole16(SC_FUNC(sc));
1432 cur_query_entry->address.hi = htole32(U64_HI(cur_data_offset));
1433 cur_query_entry->address.lo = htole32(U64_LO(cur_data_offset));
1435 cur_data_offset += sizeof(struct per_queue_stats);
1439 void bnx2x_memset_stats(struct bnx2x_softc *sc)
1443 /* function stats */
1444 for (i = 0; i < sc->num_queues; i++) {
1445 struct bnx2x_fastpath *fp = &sc->fp[i];
1447 memset(&fp->old_tclient, 0,
1448 sizeof(fp->old_tclient));
1449 memset(&fp->old_uclient, 0,
1450 sizeof(fp->old_uclient));
1451 memset(&fp->old_xclient, 0,
1452 sizeof(fp->old_xclient));
1453 if (sc->stats_init) {
1454 memset(&fp->eth_q_stats, 0,
1455 sizeof(fp->eth_q_stats));
1456 memset(&fp->eth_q_stats_old, 0,
1457 sizeof(fp->eth_q_stats_old));
1461 if (sc->stats_init) {
1462 memset(&sc->net_stats_old, 0, sizeof(sc->net_stats_old));
1463 memset(&sc->fw_stats_old, 0, sizeof(sc->fw_stats_old));
1464 memset(&sc->eth_stats_old, 0, sizeof(sc->eth_stats_old));
1465 memset(&sc->eth_stats, 0, sizeof(sc->eth_stats));
1466 memset(&sc->func_stats, 0, sizeof(sc->func_stats));
1469 sc->stats_state = STATS_STATE_DISABLED;
1471 if (sc->port.pmf && sc->port.port_stx)
1472 bnx2x_port_stats_base_init(sc);
1474 /* mark the end of statistics initializiation */
1475 sc->stats_init = false;
1479 bnx2x_stats_init(struct bnx2x_softc *sc)
1481 int /*abs*/port = SC_PORT(sc);
1482 int mb_idx = SC_FW_MB_IDX(sc);
1485 sc->stats_pending = 0;
1486 sc->executer_idx = 0;
1487 sc->stats_counter = 0;
1489 sc->stats_init = TRUE;
1491 /* port and func stats for management */
1492 if (!BNX2X_NOMCP(sc)) {
1493 sc->port.port_stx = SHMEM_RD(sc, port_mb[port].port_stx);
1494 sc->func_stx = SHMEM_RD(sc, func_mb[mb_idx].fw_mb_param);
1496 sc->port.port_stx = 0;
1500 PMD_DRV_LOG(DEBUG, "port_stx 0x%x func_stx 0x%x",
1501 sc->port.port_stx, sc->func_stx);
1503 /* pmf should retrieve port statistics from SP on a non-init*/
1504 if (!sc->stats_init && sc->port.pmf && sc->port.port_stx) {
1505 bnx2x_stats_handle(sc, STATS_EVENT_PMF);
1510 memset(&(sc->port.old_nig_stats), 0, sizeof(struct nig_stats));
1511 sc->port.old_nig_stats.brb_discard =
1512 REG_RD(sc, NIG_REG_STAT0_BRB_DISCARD + port*0x38);
1513 sc->port.old_nig_stats.brb_truncate =
1514 REG_RD(sc, NIG_REG_STAT0_BRB_TRUNCATE + port*0x38);
1515 if (!CHIP_IS_E3(sc)) {
1516 REG_RD_DMAE(sc, NIG_REG_STAT0_EGRESS_MAC_PKT0 + port*0x50,
1517 &(sc->port.old_nig_stats.egress_mac_pkt0_lo), 2);
1518 REG_RD_DMAE(sc, NIG_REG_STAT0_EGRESS_MAC_PKT1 + port*0x50,
1519 &(sc->port.old_nig_stats.egress_mac_pkt1_lo), 2);
1522 /* function stats */
1523 for (i = 0; i < sc->num_queues; i++) {
1524 memset(&sc->fp[i].old_tclient, 0, sizeof(sc->fp[i].old_tclient));
1525 memset(&sc->fp[i].old_uclient, 0, sizeof(sc->fp[i].old_uclient));
1526 memset(&sc->fp[i].old_xclient, 0, sizeof(sc->fp[i].old_xclient));
1527 if (sc->stats_init) {
1528 memset(&sc->fp[i].eth_q_stats, 0,
1529 sizeof(sc->fp[i].eth_q_stats));
1530 memset(&sc->fp[i].eth_q_stats_old, 0,
1531 sizeof(sc->fp[i].eth_q_stats_old));
1535 /* prepare statistics ramrod data */
1536 bnx2x_prep_fw_stats_req(sc);
1538 if (sc->stats_init) {
1539 memset(&sc->net_stats_old, 0, sizeof(sc->net_stats_old));
1540 memset(&sc->fw_stats_old, 0, sizeof(sc->fw_stats_old));
1541 memset(&sc->eth_stats_old, 0, sizeof(sc->eth_stats_old));
1542 memset(&sc->eth_stats, 0, sizeof(sc->eth_stats));
1543 memset(&sc->func_stats, 0, sizeof(sc->func_stats));
1545 /* Clean SP from previous statistics */
1547 memset(BNX2X_SP(sc, func_stats), 0, sizeof(struct host_func_stats));
1548 bnx2x_func_stats_init(sc);
1549 bnx2x_hw_stats_post(sc);
1550 bnx2x_stats_comp(sc);
1554 sc->stats_state = STATS_STATE_DISABLED;
1556 if (sc->port.pmf && sc->port.port_stx) {
1557 bnx2x_port_stats_base_init(sc);
1560 /* mark the end of statistics initializiation */
1561 sc->stats_init = FALSE;
1565 bnx2x_save_statistics(struct bnx2x_softc *sc)
1569 /* save queue statistics */
1570 for (i = 0; i < sc->num_queues; i++) {
1571 struct bnx2x_fastpath *fp = &sc->fp[i];
1572 struct bnx2x_eth_q_stats *qstats = &fp->eth_q_stats;
1573 struct bnx2x_eth_q_stats_old *qstats_old = &fp->eth_q_stats_old;
1575 UPDATE_QSTAT_OLD(total_unicast_bytes_received_hi);
1576 UPDATE_QSTAT_OLD(total_unicast_bytes_received_lo);
1577 UPDATE_QSTAT_OLD(total_broadcast_bytes_received_hi);
1578 UPDATE_QSTAT_OLD(total_broadcast_bytes_received_lo);
1579 UPDATE_QSTAT_OLD(total_multicast_bytes_received_hi);
1580 UPDATE_QSTAT_OLD(total_multicast_bytes_received_lo);
1581 UPDATE_QSTAT_OLD(total_unicast_bytes_transmitted_hi);
1582 UPDATE_QSTAT_OLD(total_unicast_bytes_transmitted_lo);
1583 UPDATE_QSTAT_OLD(total_broadcast_bytes_transmitted_hi);
1584 UPDATE_QSTAT_OLD(total_broadcast_bytes_transmitted_lo);
1585 UPDATE_QSTAT_OLD(total_multicast_bytes_transmitted_hi);
1586 UPDATE_QSTAT_OLD(total_multicast_bytes_transmitted_lo);
1589 /* store port firmware statistics */
1591 struct bnx2x_eth_stats *estats = &sc->eth_stats;
1592 struct bnx2x_fw_port_stats_old *fwstats = &sc->fw_stats_old;
1593 struct host_port_stats *pstats = BNX2X_SP(sc, port_stats);
1595 fwstats->pfc_frames_rx_hi = pstats->pfc_frames_rx_hi;
1596 fwstats->pfc_frames_rx_lo = pstats->pfc_frames_rx_lo;
1597 fwstats->pfc_frames_tx_hi = pstats->pfc_frames_tx_hi;
1598 fwstats->pfc_frames_tx_lo = pstats->pfc_frames_tx_lo;
1601 UPDATE_FW_STAT_OLD(mac_filter_discard);
1602 UPDATE_FW_STAT_OLD(mf_tag_discard);
1603 UPDATE_FW_STAT_OLD(brb_truncate_discard);
1604 UPDATE_FW_STAT_OLD(mac_discard);