2 * Copyright (c) 2007-2013 QLogic Corporation. All rights reserved.
4 * Eric Davis <edavis@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
6 * Gary Zambrano <zambrano@broadcom.com>
8 * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. Neither the name of Broadcom Corporation nor the name of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written consent.
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
34 * THE POSSIBILITY OF SUCH DAMAGE.
40 /* Init operation types and structures */
42 OP_RD = 0x1, /* read a single register */
43 OP_WR, /* write a single register */
44 OP_SW, /* copy a string to the device */
45 OP_ZR, /* clear memory */
46 OP_ZP, /* unzip then copy with DMAE */
47 OP_WR_64, /* write 64 bit pattern */
48 OP_WB, /* copy a string using DMAE */
49 OP_WB_ZR, /* Clear a string using DMAE or indirect-wr */
50 OP_IF_MODE_OR, /* Skip the following ops if all init modes don't match */
51 OP_IF_MODE_AND, /* Skip the following ops if any init modes don't match */
64 /* Returns the index of start or end of a specific block stage in ops array*/
65 #define BLOCK_OPS_IDX(block, stage, end) \
66 (2*(((block)*NUM_OF_INIT_PHASES) + (stage)) + (end))
69 /* structs for the various opcodes */
94 #else /* __LITTLE_ENDIAN */
108 uint32_t cmd_offset:24;
109 uint32_t mode_bit_map;
114 uint32_t cmd_offset:24;
115 uint32_t phase_bit_map;
120 uint32_t reserved:24;
126 struct op_write write;
127 struct op_arr_write arr_wr;
130 struct op_if_mode if_mode;
131 struct op_if_phase if_phase;
132 struct op_delay delay;
154 MODE_ASIC = 0x00000001,
155 MODE_FPGA = 0x00000002,
156 MODE_EMUL = 0x00000004,
157 MODE_E2 = 0x00000008,
158 MODE_E3 = 0x00000010,
159 MODE_PORT2 = 0x00000020,
160 MODE_PORT4 = 0x00000040,
161 MODE_SF = 0x00000080,
162 MODE_MF = 0x00000100,
163 MODE_MF_SD = 0x00000200,
164 MODE_MF_SI = 0x00000400,
165 MODE_MF_AFEX = 0x00000800,
166 MODE_E3_A0 = 0x00001000,
167 MODE_E3_B0 = 0x00002000,
168 MODE_COS3 = 0x00004000,
169 MODE_COS6 = 0x00008000,
170 MODE_LITTLE_ENDIAN = 0x00010000,
171 MODE_BIG_ENDIAN = 0x00020000,
221 #define ECORE_PORT2_MODE_NUM_VNICS 4
224 /* QM queue numbers */
225 #define ECORE_ETH_Q 0
226 #define ECORE_TOE_Q 3
227 #define ECORE_TOE_ACK_Q 6
228 #define ECORE_ISCSI_Q 9
229 #define ECORE_ISCSI_ACK_Q 11
230 #define ECORE_FCOE_Q 10
233 #define ECORE_PORT4_MODE_NUM_VNICS 2
235 /* COS offset for port1 in E3 B0 4port mode */
236 #define ECORE_E3B0_PORT1_COS_OFFSET 3
238 /* QM Register addresses */
239 #define ECORE_Q_VOQ_REG_ADDR(pf_q_num)\
240 (QM_REG_QVOQIDX_0 + 4 * (pf_q_num))
241 #define ECORE_VOQ_Q_REG_ADDR(cos, pf_q_num)\
242 (QM_REG_VOQQMASK_0_LSB + 4 * ((cos) * 2 + ((pf_q_num) >> 5)))
243 #define ECORE_Q_CMDQ_REG_ADDR(pf_q_num)\
244 (QM_REG_BYTECRDCMDQ_0 + 4 * ((pf_q_num) >> 4))
246 /* extracts the QM queue number for the specified port and vnic */
247 #define ECORE_PF_Q_NUM(q_num, port, vnic)\
248 ((((port) << 1) | (vnic)) * 16 + (q_num))
251 /* Maps the specified queue to the specified COS */
252 static inline void ecore_map_q_cos(struct bnx2x_softc *sc, uint32_t q_num, uint32_t new_cos)
254 /* find current COS mapping */
255 uint32_t curr_cos = REG_RD(sc, QM_REG_QVOQIDX_0 + q_num * 4);
257 /* check if queue->COS mapping has changed */
258 if (curr_cos != new_cos) {
259 uint32_t num_vnics = ECORE_PORT2_MODE_NUM_VNICS;
260 uint32_t reg_addr, reg_bit_map, vnic;
262 /* update parameters for 4port mode */
263 if (INIT_MODE_FLAGS(sc) & MODE_PORT4) {
264 num_vnics = ECORE_PORT4_MODE_NUM_VNICS;
266 curr_cos += ECORE_E3B0_PORT1_COS_OFFSET;
267 new_cos += ECORE_E3B0_PORT1_COS_OFFSET;
271 /* change queue mapping for each VNIC */
272 for (vnic = 0; vnic < num_vnics; vnic++) {
274 ECORE_PF_Q_NUM(q_num, PORT_ID(sc), vnic);
275 uint32_t q_bit_map = 1 << (pf_q_num & 0x1f);
277 /* overwrite queue->VOQ mapping */
278 REG_WR(sc, ECORE_Q_VOQ_REG_ADDR(pf_q_num), new_cos);
280 /* clear queue bit from current COS bit map */
281 reg_addr = ECORE_VOQ_Q_REG_ADDR(curr_cos, pf_q_num);
282 reg_bit_map = REG_RD(sc, reg_addr);
283 REG_WR(sc, reg_addr, reg_bit_map & (~q_bit_map));
285 /* set queue bit in new COS bit map */
286 reg_addr = ECORE_VOQ_Q_REG_ADDR(new_cos, pf_q_num);
287 reg_bit_map = REG_RD(sc, reg_addr);
288 REG_WR(sc, reg_addr, reg_bit_map | q_bit_map);
290 /* set/clear queue bit in command-queue bit map
291 (E2/E3A0 only, valid COS values are 0/1) */
292 if (!(INIT_MODE_FLAGS(sc) & MODE_E3_B0)) {
293 reg_addr = ECORE_Q_CMDQ_REG_ADDR(pf_q_num);
294 reg_bit_map = REG_RD(sc, reg_addr);
295 q_bit_map = 1 << (2 * (pf_q_num & 0xf));
296 reg_bit_map = new_cos ?
297 (reg_bit_map | q_bit_map) :
298 (reg_bit_map & (~q_bit_map));
299 REG_WR(sc, reg_addr, reg_bit_map);
305 /* Configures the QM according to the specified per-traffic-type COSes */
306 static inline void ecore_dcb_config_qm(struct bnx2x_softc *sc, enum cos_mode mode,
307 struct priority_cos *traffic_cos)
309 ecore_map_q_cos(sc, ECORE_FCOE_Q,
310 traffic_cos[LLFC_TRAFFIC_TYPE_FCOE].cos);
311 ecore_map_q_cos(sc, ECORE_ISCSI_Q,
312 traffic_cos[LLFC_TRAFFIC_TYPE_ISCSI].cos);
313 ecore_map_q_cos(sc, ECORE_ISCSI_ACK_Q,
314 traffic_cos[LLFC_TRAFFIC_TYPE_ISCSI].cos);
315 if (mode != STATIC_COS) {
316 /* required only in OVERRIDE_COS mode */
317 ecore_map_q_cos(sc, ECORE_ETH_Q,
318 traffic_cos[LLFC_TRAFFIC_TYPE_NW].cos);
319 ecore_map_q_cos(sc, ECORE_TOE_Q,
320 traffic_cos[LLFC_TRAFFIC_TYPE_NW].cos);
321 ecore_map_q_cos(sc, ECORE_TOE_ACK_Q,
322 traffic_cos[LLFC_TRAFFIC_TYPE_NW].cos);
328 * congestion managment port init api description
329 * the api works as follows:
330 * the driver should pass the cmng_init_input struct, the port_init function
331 * will prepare the required internal ram structure which will be passed back
332 * to the driver (cmng_init) that will write it into the internal ram.
335 * 1. the cmng_init struct does not represent the contiguous internal ram
336 * structure. the driver should use the XSTORM_CMNG_PERPORT_VARS_OFFSET
337 * offset in order to write the port sub struct and the
338 * PFID_FROM_PORT_AND_VNIC offset for writing the vnic sub struct (in other
339 * words - don't use memcpy!).
340 * 2. although the cmng_init struct is filled for the maximal vnic number
341 * possible, the driver should only write the valid vnics into the internal
342 * ram according to the appropriate port mode.
344 #define BITS_TO_BYTES(x) ((x)/8)
346 /* CMNG constants, as derived from system spec calculations */
348 /* default MIN rate in case VNIC min rate is configured to zero- 100Mbps */
349 #define DEF_MIN_RATE 100
351 /* resolution of the rate shaping timer - 400 usec */
352 #define RS_PERIODIC_TIMEOUT_USEC 400
355 * number of bytes in single QM arbitration cycle -
356 * coefficient for calculating the fairness timer
358 #define QM_ARB_BYTES 160000
360 /* resolution of Min algorithm 1:100 */
364 * how many bytes above threshold for
365 * the minimal credit of Min algorithm
367 #define MIN_ABOVE_THRESH 32768
370 * Fairness algorithm integration time coefficient -
371 * for calculating the actual Tfair
373 #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES)
375 /* Memory of fairness algorithm - 2 cycles */
377 #define SAFC_TIMEOUT_USEC 52
382 static inline void ecore_init_max(const struct cmng_init_input *input_data,
383 uint32_t r_param, struct cmng_init *ram_data)
386 struct cmng_vnic *vdata = &ram_data->vnic;
387 struct cmng_struct_per_port *pdata = &ram_data->port;
389 * rate shaping per-port variables
390 * 100 micro seconds in SDM ticks = 25
391 * since each tick is 4 microSeconds
394 pdata->rs_vars.rs_periodic_timeout =
395 RS_PERIODIC_TIMEOUT_USEC / SDM_TICKS;
397 /* this is the threshold below which no timer arming will occur.
398 * 1.25 coefficient is for the threshold to be a little bigger
399 * then the real time to compensate for timer in-accuracy
401 pdata->rs_vars.rs_threshold =
402 (5 * RS_PERIODIC_TIMEOUT_USEC * r_param)/4;
404 /* rate shaping per-vnic variables */
405 for (vnic = 0; vnic < ECORE_PORT2_MODE_NUM_VNICS; vnic++) {
406 /* global vnic counter */
407 vdata->vnic_max_rate[vnic].vn_counter.rate =
408 input_data->vnic_max_rate[vnic];
410 * maximal Mbps for this vnic
411 * the quota in each timer period - number of bytes
412 * transmitted in this period
414 vdata->vnic_max_rate[vnic].vn_counter.quota =
415 RS_PERIODIC_TIMEOUT_USEC *
416 (uint32_t)vdata->vnic_max_rate[vnic].vn_counter.rate / 8;
421 static inline void ecore_init_max_per_vn(uint16_t vnic_max_rate,
422 struct rate_shaping_vars_per_vn *ram_data)
424 /* global vnic counter */
425 ram_data->vn_counter.rate = vnic_max_rate;
428 * maximal Mbps for this vnic
429 * the quota in each timer period - number of bytes
430 * transmitted in this period
432 ram_data->vn_counter.quota =
433 RS_PERIODIC_TIMEOUT_USEC * (uint32_t)vnic_max_rate / 8;
436 static inline void ecore_init_min(const struct cmng_init_input *input_data,
437 uint32_t r_param, struct cmng_init *ram_data)
439 uint32_t vnic, fair_periodic_timeout_usec, vnicWeightSum, tFair;
440 struct cmng_vnic *vdata = &ram_data->vnic;
441 struct cmng_struct_per_port *pdata = &ram_data->port;
443 /* this is the resolution of the fairness timer */
444 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
447 * fairness per-port variables
448 * for 10G it is 1000usec. for 1G it is 10000usec.
450 tFair = T_FAIR_COEF / input_data->port_rate;
452 /* this is the threshold below which we won't arm the timer anymore */
453 pdata->fair_vars.fair_threshold = QM_ARB_BYTES;
456 * we multiply by 1e3/8 to get bytes/msec. We don't want the credits
457 * to pass a credit of the T_FAIR*FAIR_MEM (algorithm resolution)
459 pdata->fair_vars.upper_bound = r_param * tFair * FAIR_MEM;
461 /* since each tick is 4 microSeconds */
462 pdata->fair_vars.fairness_timeout =
463 fair_periodic_timeout_usec / SDM_TICKS;
465 /* calculate sum of weights */
468 for (vnic = 0; vnic < ECORE_PORT2_MODE_NUM_VNICS; vnic++)
469 vnicWeightSum += input_data->vnic_min_rate[vnic];
471 /* global vnic counter */
472 if (vnicWeightSum > 0) {
473 /* fairness per-vnic variables */
474 for (vnic = 0; vnic < ECORE_PORT2_MODE_NUM_VNICS; vnic++) {
476 * this is the credit for each period of the fairness
477 * algorithm - number of bytes in T_FAIR (this vnic
478 * share of the port rate)
480 vdata->vnic_min_rate[vnic].vn_credit_delta =
481 ((uint32_t)(input_data->vnic_min_rate[vnic]) * 100 *
482 (T_FAIR_COEF / (8 * 100 * vnicWeightSum)));
483 if (vdata->vnic_min_rate[vnic].vn_credit_delta <
484 pdata->fair_vars.fair_threshold +
486 vdata->vnic_min_rate[vnic].vn_credit_delta =
487 pdata->fair_vars.fair_threshold +
494 static inline void ecore_init_fw_wrr(const struct cmng_init_input *input_data,
495 struct cmng_init *ram_data)
498 uint32_t cosWeightSum = 0;
499 struct cmng_vnic *vdata = &ram_data->vnic;
500 struct cmng_struct_per_port *pdata = &ram_data->port;
502 for (cos = 0; cos < MAX_COS_NUMBER; cos++)
503 cosWeightSum += input_data->cos_min_rate[cos];
505 if (cosWeightSum > 0) {
507 for (vnic = 0; vnic < ECORE_PORT2_MODE_NUM_VNICS; vnic++) {
509 * Since cos and vnic shouldn't work together the rate
510 * to divide between the coses is the port rate.
512 uint32_t *ccd = vdata->vnic_min_rate[vnic].cos_credit_delta;
513 for (cos = 0; cos < MAX_COS_NUMBER; cos++) {
515 * this is the credit for each period of
516 * the fairness algorithm - number of bytes
517 * in T_FAIR (this cos share of the vnic rate)
520 ((uint32_t)input_data->cos_min_rate[cos] * 100 *
521 (T_FAIR_COEF / (8 * 100 * cosWeightSum)));
522 if (ccd[cos] < pdata->fair_vars.fair_threshold
523 + MIN_ABOVE_THRESH) {
525 pdata->fair_vars.fair_threshold +
533 static inline void ecore_init_safc(struct cmng_init *ram_data)
535 /* in microSeconds */
536 ram_data->port.safc_vars.safc_timeout_usec = SAFC_TIMEOUT_USEC;
539 /* Congestion management port init */
540 static inline void ecore_init_cmng(const struct cmng_init_input *input_data,
541 struct cmng_init *ram_data)
544 ECORE_MEMSET(ram_data, 0,sizeof(struct cmng_init));
546 ram_data->port.flags = input_data->flags;
549 * number of bytes transmitted in a rate of 10Gbps
550 * in one usec = 1.25KB.
552 r_param = BITS_TO_BYTES(input_data->port_rate);
553 ecore_init_max(input_data, r_param, ram_data);
554 ecore_init_min(input_data, r_param, ram_data);
555 ecore_init_fw_wrr(input_data, ram_data);
556 ecore_init_safc(ram_data);
562 /* Returns the index of start or end of a specific block stage in ops array*/
563 #define BLOCK_OPS_IDX(block, stage, end) \
564 (2*(((block)*NUM_OF_INIT_PHASES) + (stage)) + (end))
567 #define INITOP_SET 0 /* set the HW directly */
568 #define INITOP_CLEAR 1 /* clear the HW directly */
569 #define INITOP_INIT 2 /* set the init-value array */
571 /****************************************************************************
573 ****************************************************************************/
575 ecore_dma_addr_t page_mapping;
580 struct ilt_client_info {
586 #define ILT_CLIENT_SKIP_INIT 0x1
587 #define ILT_CLIENT_SKIP_MEM 0x2
592 struct ilt_line *lines;
593 struct ilt_client_info clients[4];
594 #define ILT_CLIENT_CDU 0
595 #define ILT_CLIENT_QM 1
596 #define ILT_CLIENT_SRC 2
597 #define ILT_CLIENT_TM 3
600 /****************************************************************************
602 ****************************************************************************/
608 /****************************************************************************
609 * Parity configuration
610 ****************************************************************************/
611 #define BLOCK_PRTY_INFO(block, en_mask, m1h, m2, m3) \
613 block##_REG_##block##_PRTY_MASK, \
614 block##_REG_##block##_PRTY_STS_CLR, \
615 en_mask, {m1h, m2, m3}, #block \
618 #define BLOCK_PRTY_INFO_0(block, en_mask, m1h, m2, m3) \
620 block##_REG_##block##_PRTY_MASK_0, \
621 block##_REG_##block##_PRTY_STS_CLR_0, \
622 en_mask, {m1h, m2, m3}, #block"_0" \
625 #define BLOCK_PRTY_INFO_1(block, en_mask, m1h, m2, m3) \
627 block##_REG_##block##_PRTY_MASK_1, \
628 block##_REG_##block##_PRTY_STS_CLR_1, \
629 en_mask, {m1h, m2, m3}, #block"_1" \
632 static const struct {
634 uint32_t sts_clr_addr;
635 uint32_t en_mask; /* Mask to enable parity attentions */
637 uint32_t e1h; /* 57711 */
638 uint32_t e2; /* 57712 */
639 uint32_t e3; /* 578xx */
640 } reg_mask; /* Register mask (all valid bits) */
641 char name[8]; /* Block's longest name is 7 characters long
644 } ecore_blocks_parity_data[] = {
646 /* REG_WR(bp, PXP_REG_PXP_PRTY_MASK, 0x80000); */
648 /* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_0, 0xfff40020); */
650 /* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_1, 0x20); */
651 /* REG_WR(bp, HC_REG_HC_PRTY_MASK, 0x0); */
652 /* REG_WR(bp, MISC_REG_MISC_PRTY_MASK, 0x0); */
654 /* Block IGU, MISC, PXP and PXP2 parity errors as long as we don't
655 * want to handle "system kill" flow at the moment.
657 BLOCK_PRTY_INFO(PXP, 0x7ffffff, 0x3ffffff, 0x7ffffff,
659 BLOCK_PRTY_INFO_0(PXP2, 0xffffffff, 0xffffffff, 0xffffffff,
661 BLOCK_PRTY_INFO_1(PXP2, 0x1ffffff, 0x7f, 0x7ff, 0x1ffffff),
662 BLOCK_PRTY_INFO(HC, 0x7, 0x7, 0, 0),
663 BLOCK_PRTY_INFO(NIG, 0xffffffff, 0xffffffff, 0, 0),
664 BLOCK_PRTY_INFO_0(NIG, 0xffffffff, 0, 0xffffffff, 0xffffffff),
665 BLOCK_PRTY_INFO_1(NIG, 0xffff, 0, 0xff, 0xffff),
666 BLOCK_PRTY_INFO(IGU, 0x7ff, 0, 0x7ff, 0x7ff),
667 BLOCK_PRTY_INFO(MISC, 0x1, 0x1, 0x1, 0x1),
668 BLOCK_PRTY_INFO(QM, 0, 0xfff, 0xfff, 0xfff),
669 BLOCK_PRTY_INFO(ATC, 0x1f, 0, 0x1f, 0x1f),
670 BLOCK_PRTY_INFO(PGLUE_B, 0x3, 0, 0x3, 0x3),
671 BLOCK_PRTY_INFO(DORQ, 0, 0x3, 0x3, 0x3),
672 {GRCBASE_UPB + PB_REG_PB_PRTY_MASK,
673 GRCBASE_UPB + PB_REG_PB_PRTY_STS_CLR, 0xf,
674 {0xf, 0xf, 0xf}, "UPB"},
675 {GRCBASE_XPB + PB_REG_PB_PRTY_MASK,
676 GRCBASE_XPB + PB_REG_PB_PRTY_STS_CLR, 0,
677 {0xf, 0xf, 0xf}, "XPB"},
678 BLOCK_PRTY_INFO(SRC, 0x4, 0x7, 0x7, 0x7),
679 BLOCK_PRTY_INFO(CDU, 0, 0x1f, 0x1f, 0x1f),
680 BLOCK_PRTY_INFO(CFC, 0, 0xf, 0xf, 0x3f),
681 BLOCK_PRTY_INFO(DBG, 0, 0x1, 0x1, 0x1),
682 BLOCK_PRTY_INFO(DMAE, 0, 0xf, 0xf, 0xf),
683 BLOCK_PRTY_INFO(BRB1, 0, 0xf, 0xf, 0xf),
684 BLOCK_PRTY_INFO(PRS, (1<<6), 0xff, 0xff, 0xff),
685 BLOCK_PRTY_INFO(PBF, 0, 0x3ffff, 0xfffff, 0xfffffff),
686 BLOCK_PRTY_INFO(TM, 0, 0x7f, 0x7f, 0x7f),
687 BLOCK_PRTY_INFO(TSDM, 0x18, 0x7ff, 0x7ff, 0x7ff),
688 BLOCK_PRTY_INFO(CSDM, 0x8, 0x7ff, 0x7ff, 0x7ff),
689 BLOCK_PRTY_INFO(USDM, 0x38, 0x7ff, 0x7ff, 0x7ff),
690 BLOCK_PRTY_INFO(XSDM, 0x8, 0x7ff, 0x7ff, 0x7ff),
691 BLOCK_PRTY_INFO(TCM, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
692 BLOCK_PRTY_INFO(CCM, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
693 BLOCK_PRTY_INFO(UCM, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
694 BLOCK_PRTY_INFO(XCM, 0, 0x3fffffff, 0x3fffffff, 0x3fffffff),
695 BLOCK_PRTY_INFO_0(TSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
696 BLOCK_PRTY_INFO_1(TSEM, 0, 0x1f, 0x3f, 0x3f),
697 BLOCK_PRTY_INFO_0(USEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
698 BLOCK_PRTY_INFO_1(USEM, 0, 0x1f, 0x1f, 0x1f),
699 BLOCK_PRTY_INFO_0(CSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
700 BLOCK_PRTY_INFO_1(CSEM, 0, 0x1f, 0x1f, 0x1f),
701 BLOCK_PRTY_INFO_0(XSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
702 BLOCK_PRTY_INFO_1(XSEM, 0, 0x1f, 0x3f, 0x3f),
706 /* [28] MCP Latched rom_parity
707 * [29] MCP Latched ump_rx_parity
708 * [30] MCP Latched ump_tx_parity
709 * [31] MCP Latched scpad_parity
711 #define MISC_AEU_ENABLE_MCP_PRTY_BITS \
712 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
713 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
714 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \
715 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
717 /* Below registers control the MCP parity attention output. When
718 * MISC_AEU_ENABLE_MCP_PRTY_BITS are set - attentions are
719 * enabled, when cleared - disabled.
721 static const uint32_t mcp_attn_ctl_regs[] = {
722 MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0,
723 MISC_REG_AEU_ENABLE4_NIG_0,
724 MISC_REG_AEU_ENABLE4_PXP_0,
725 MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0,
726 MISC_REG_AEU_ENABLE4_NIG_1,
727 MISC_REG_AEU_ENABLE4_PXP_1
730 static inline void ecore_set_mcp_parity(struct bnx2x_softc *sc, uint8_t enable)
735 for (i = 0; i < ARRSIZE(mcp_attn_ctl_regs); i++) {
736 reg_val = REG_RD(sc, mcp_attn_ctl_regs[i]);
739 reg_val |= MISC_AEU_ENABLE_MCP_PRTY_BITS;
741 reg_val &= ~MISC_AEU_ENABLE_MCP_PRTY_BITS;
743 REG_WR(sc, mcp_attn_ctl_regs[i], reg_val);
747 static inline uint32_t ecore_parity_reg_mask(struct bnx2x_softc *sc, int idx)
750 return ecore_blocks_parity_data[idx].reg_mask.e1h;
751 else if (CHIP_IS_E2(sc))
752 return ecore_blocks_parity_data[idx].reg_mask.e2;
753 else /* CHIP_IS_E3 */
754 return ecore_blocks_parity_data[idx].reg_mask.e3;
757 static inline void ecore_disable_blocks_parity(struct bnx2x_softc *sc)
761 for (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) {
762 uint32_t dis_mask = ecore_parity_reg_mask(sc, i);
765 REG_WR(sc, ecore_blocks_parity_data[i].mask_addr,
767 ECORE_MSG("Setting parity mask "
769 ecore_blocks_parity_data[i].name, dis_mask);
773 /* Disable MCP parity attentions */
774 ecore_set_mcp_parity(sc, FALSE);
778 * Clear the parity error status registers.
780 static inline void ecore_clear_blocks_parity(struct bnx2x_softc *sc)
783 uint32_t reg_val, mcp_aeu_bits =
784 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY |
785 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY |
786 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY |
787 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY;
789 /* Clear SEM_FAST parities */
790 REG_WR(sc, XSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
791 REG_WR(sc, TSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
792 REG_WR(sc, USEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
793 REG_WR(sc, CSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
795 for (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) {
796 uint32_t reg_mask = ecore_parity_reg_mask(sc, i);
799 reg_val = REG_RD(sc, ecore_blocks_parity_data[i].
801 if (reg_val & reg_mask)
803 "Parity errors in %s: 0x%x",
804 ecore_blocks_parity_data[i].name,
809 /* Check if there were parity attentions in MCP */
810 reg_val = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_MCP);
811 if (reg_val & mcp_aeu_bits)
812 ECORE_MSG("Parity error in MCP: 0x%x",
813 reg_val & mcp_aeu_bits);
815 /* Clear parity attentions in MCP:
816 * [7] clears Latched rom_parity
817 * [8] clears Latched ump_rx_parity
818 * [9] clears Latched ump_tx_parity
819 * [10] clears Latched scpad_parity (both ports)
821 REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x780);
824 static inline void ecore_enable_blocks_parity(struct bnx2x_softc *sc)
828 for (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) {
829 uint32_t reg_mask = ecore_parity_reg_mask(sc, i);
832 REG_WR(sc, ecore_blocks_parity_data[i].mask_addr,
833 ecore_blocks_parity_data[i].en_mask & reg_mask);
836 /* Enable MCP parity attentions */
837 ecore_set_mcp_parity(sc, TRUE);
841 #endif /* ECORE_INIT_H */