1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2007-2013 Broadcom Corporation.
4 * Eric Davis <edavis@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
6 * Gary Zambrano <zambrano@broadcom.com>
8 * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
9 * Copyright (c) 2015-2018 Cavium Inc.
10 * All rights reserved.
17 /* Init operation types and structures */
19 OP_RD = 0x1, /* read a single register */
20 OP_WR, /* write a single register */
21 OP_SW, /* copy a string to the device */
22 OP_ZR, /* clear memory */
23 OP_ZP, /* unzip then copy with DMAE */
24 OP_WR_64, /* write 64 bit pattern */
25 OP_WB, /* copy a string using DMAE */
26 OP_WB_ZR, /* Clear a string using DMAE or indirect-wr */
27 OP_IF_MODE_OR, /* Skip the following ops if all init modes don't match */
28 OP_IF_MODE_AND, /* Skip the following ops if any init modes don't match */
41 /* Returns the index of start or end of a specific block stage in ops array*/
42 #define BLOCK_OPS_IDX(block, stage, end) \
43 (2*(((block)*NUM_OF_INIT_PHASES) + (stage)) + (end))
46 /* structs for the various opcodes */
71 #else /* __LITTLE_ENDIAN */
85 uint32_t cmd_offset:24;
86 uint32_t mode_bit_map;
91 uint32_t cmd_offset:24;
92 uint32_t phase_bit_map;
103 struct op_write write;
104 struct op_arr_write arr_wr;
107 struct op_if_mode if_mode;
108 struct op_if_phase if_phase;
109 struct op_delay delay;
131 MODE_ASIC = 0x00000001,
132 MODE_FPGA = 0x00000002,
133 MODE_EMUL = 0x00000004,
134 MODE_E2 = 0x00000008,
135 MODE_E3 = 0x00000010,
136 MODE_PORT2 = 0x00000020,
137 MODE_PORT4 = 0x00000040,
138 MODE_SF = 0x00000080,
139 MODE_MF = 0x00000100,
140 MODE_MF_SD = 0x00000200,
141 MODE_MF_SI = 0x00000400,
142 MODE_MF_AFEX = 0x00000800,
143 MODE_E3_A0 = 0x00001000,
144 MODE_E3_B0 = 0x00002000,
145 MODE_COS3 = 0x00004000,
146 MODE_COS6 = 0x00008000,
147 MODE_LITTLE_ENDIAN = 0x00010000,
148 MODE_BIG_ENDIAN = 0x00020000,
198 #define ECORE_PORT2_MODE_NUM_VNICS 4
201 /* QM queue numbers */
202 #define ECORE_ETH_Q 0
203 #define ECORE_TOE_Q 3
204 #define ECORE_TOE_ACK_Q 6
205 #define ECORE_ISCSI_Q 9
206 #define ECORE_ISCSI_ACK_Q 11
207 #define ECORE_FCOE_Q 10
210 #define ECORE_PORT4_MODE_NUM_VNICS 2
212 /* COS offset for port1 in E3 B0 4port mode */
213 #define ECORE_E3B0_PORT1_COS_OFFSET 3
215 /* QM Register addresses */
216 #define ECORE_Q_VOQ_REG_ADDR(pf_q_num)\
217 (QM_REG_QVOQIDX_0 + 4 * (pf_q_num))
218 #define ECORE_VOQ_Q_REG_ADDR(cos, pf_q_num)\
219 (QM_REG_VOQQMASK_0_LSB + 4 * ((cos) * 2 + ((pf_q_num) >> 5)))
220 #define ECORE_Q_CMDQ_REG_ADDR(pf_q_num)\
221 (QM_REG_BYTECRDCMDQ_0 + 4 * ((pf_q_num) >> 4))
223 /* extracts the QM queue number for the specified port and vnic */
224 #define ECORE_PF_Q_NUM(q_num, port, vnic)\
225 ((((port) << 1) | (vnic)) * 16 + (q_num))
228 /* Maps the specified queue to the specified COS */
229 static inline void ecore_map_q_cos(struct bnx2x_softc *sc, uint32_t q_num, uint32_t new_cos)
231 /* find current COS mapping */
232 uint32_t curr_cos = REG_RD(sc, QM_REG_QVOQIDX_0 + q_num * 4);
234 /* check if queue->COS mapping has changed */
235 if (curr_cos != new_cos) {
236 uint32_t num_vnics = ECORE_PORT2_MODE_NUM_VNICS;
237 uint32_t reg_addr, reg_bit_map, vnic;
239 /* update parameters for 4port mode */
240 if (INIT_MODE_FLAGS(sc) & MODE_PORT4) {
241 num_vnics = ECORE_PORT4_MODE_NUM_VNICS;
243 curr_cos += ECORE_E3B0_PORT1_COS_OFFSET;
244 new_cos += ECORE_E3B0_PORT1_COS_OFFSET;
248 /* change queue mapping for each VNIC */
249 for (vnic = 0; vnic < num_vnics; vnic++) {
251 ECORE_PF_Q_NUM(q_num, PORT_ID(sc), vnic);
252 uint32_t q_bit_map = 1 << (pf_q_num & 0x1f);
254 /* overwrite queue->VOQ mapping */
255 REG_WR(sc, ECORE_Q_VOQ_REG_ADDR(pf_q_num), new_cos);
257 /* clear queue bit from current COS bit map */
258 reg_addr = ECORE_VOQ_Q_REG_ADDR(curr_cos, pf_q_num);
259 reg_bit_map = REG_RD(sc, reg_addr);
260 REG_WR(sc, reg_addr, reg_bit_map & (~q_bit_map));
262 /* set queue bit in new COS bit map */
263 reg_addr = ECORE_VOQ_Q_REG_ADDR(new_cos, pf_q_num);
264 reg_bit_map = REG_RD(sc, reg_addr);
265 REG_WR(sc, reg_addr, reg_bit_map | q_bit_map);
267 /* set/clear queue bit in command-queue bit map
268 (E2/E3A0 only, valid COS values are 0/1) */
269 if (!(INIT_MODE_FLAGS(sc) & MODE_E3_B0)) {
270 reg_addr = ECORE_Q_CMDQ_REG_ADDR(pf_q_num);
271 reg_bit_map = REG_RD(sc, reg_addr);
272 q_bit_map = 1 << (2 * (pf_q_num & 0xf));
273 reg_bit_map = new_cos ?
274 (reg_bit_map | q_bit_map) :
275 (reg_bit_map & (~q_bit_map));
276 REG_WR(sc, reg_addr, reg_bit_map);
282 /* Configures the QM according to the specified per-traffic-type COSes */
283 static inline void ecore_dcb_config_qm(struct bnx2x_softc *sc, enum cos_mode mode,
284 struct priority_cos *traffic_cos)
286 ecore_map_q_cos(sc, ECORE_FCOE_Q,
287 traffic_cos[LLFC_TRAFFIC_TYPE_FCOE].cos);
288 ecore_map_q_cos(sc, ECORE_ISCSI_Q,
289 traffic_cos[LLFC_TRAFFIC_TYPE_ISCSI].cos);
290 ecore_map_q_cos(sc, ECORE_ISCSI_ACK_Q,
291 traffic_cos[LLFC_TRAFFIC_TYPE_ISCSI].cos);
292 if (mode != STATIC_COS) {
293 /* required only in OVERRIDE_COS mode */
294 ecore_map_q_cos(sc, ECORE_ETH_Q,
295 traffic_cos[LLFC_TRAFFIC_TYPE_NW].cos);
296 ecore_map_q_cos(sc, ECORE_TOE_Q,
297 traffic_cos[LLFC_TRAFFIC_TYPE_NW].cos);
298 ecore_map_q_cos(sc, ECORE_TOE_ACK_Q,
299 traffic_cos[LLFC_TRAFFIC_TYPE_NW].cos);
305 * congestion management port init api description
306 * the api works as follows:
307 * the driver should pass the cmng_init_input struct, the port_init function
308 * will prepare the required internal ram structure which will be passed back
309 * to the driver (cmng_init) that will write it into the internal ram.
312 * 1. the cmng_init struct does not represent the contiguous internal ram
313 * structure. the driver should use the XSTORM_CMNG_PERPORT_VARS_OFFSET
314 * offset in order to write the port sub struct and the
315 * PFID_FROM_PORT_AND_VNIC offset for writing the vnic sub struct (in other
316 * words - don't use memcpy!).
317 * 2. although the cmng_init struct is filled for the maximal vnic number
318 * possible, the driver should only write the valid vnics into the internal
319 * ram according to the appropriate port mode.
321 #define BITS_TO_BYTES(x) ((x)/8)
323 /* CMNG constants, as derived from system spec calculations */
325 /* default MIN rate in case VNIC min rate is configured to zero- 100Mbps */
326 #define DEF_MIN_RATE 100
328 /* resolution of the rate shaping timer - 400 usec */
329 #define RS_PERIODIC_TIMEOUT_USEC 400
332 * number of bytes in single QM arbitration cycle -
333 * coefficient for calculating the fairness timer
335 #define QM_ARB_BYTES 160000
337 /* resolution of Min algorithm 1:100 */
341 * how many bytes above threshold for
342 * the minimal credit of Min algorithm
344 #define MIN_ABOVE_THRESH 32768
347 * Fairness algorithm integration time coefficient -
348 * for calculating the actual Tfair
350 #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES)
352 /* Memory of fairness algorithm - 2 cycles */
354 #define SAFC_TIMEOUT_USEC 52
359 static inline void ecore_init_max(const struct cmng_init_input *input_data,
360 uint32_t r_param, struct cmng_init *ram_data)
363 struct cmng_vnic *vdata = &ram_data->vnic;
364 struct cmng_struct_per_port *pdata = &ram_data->port;
366 * rate shaping per-port variables
367 * 100 micro seconds in SDM ticks = 25
368 * since each tick is 4 microSeconds
371 pdata->rs_vars.rs_periodic_timeout =
372 RS_PERIODIC_TIMEOUT_USEC / SDM_TICKS;
374 /* this is the threshold below which no timer arming will occur.
375 * 1.25 coefficient is for the threshold to be a little bigger
376 * then the real time to compensate for timer in-accuracy
378 pdata->rs_vars.rs_threshold =
379 (5 * RS_PERIODIC_TIMEOUT_USEC * r_param)/4;
381 /* rate shaping per-vnic variables */
382 for (vnic = 0; vnic < ECORE_PORT2_MODE_NUM_VNICS; vnic++) {
383 /* global vnic counter */
384 vdata->vnic_max_rate[vnic].vn_counter.rate =
385 input_data->vnic_max_rate[vnic];
387 * maximal Mbps for this vnic
388 * the quota in each timer period - number of bytes
389 * transmitted in this period
391 vdata->vnic_max_rate[vnic].vn_counter.quota =
392 RS_PERIODIC_TIMEOUT_USEC *
393 (uint32_t)vdata->vnic_max_rate[vnic].vn_counter.rate / 8;
398 static inline void ecore_init_max_per_vn(uint16_t vnic_max_rate,
399 struct rate_shaping_vars_per_vn *ram_data)
401 /* global vnic counter */
402 ram_data->vn_counter.rate = vnic_max_rate;
405 * maximal Mbps for this vnic
406 * the quota in each timer period - number of bytes
407 * transmitted in this period
409 ram_data->vn_counter.quota =
410 RS_PERIODIC_TIMEOUT_USEC * (uint32_t)vnic_max_rate / 8;
413 static inline void ecore_init_min(const struct cmng_init_input *input_data,
414 uint32_t r_param, struct cmng_init *ram_data)
416 uint32_t vnic, fair_periodic_timeout_usec, vnicWeightSum, tFair;
417 struct cmng_vnic *vdata = &ram_data->vnic;
418 struct cmng_struct_per_port *pdata = &ram_data->port;
420 /* this is the resolution of the fairness timer */
421 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
424 * fairness per-port variables
425 * for 10G it is 1000usec. for 1G it is 10000usec.
427 tFair = T_FAIR_COEF / input_data->port_rate;
429 /* this is the threshold below which we won't arm the timer anymore */
430 pdata->fair_vars.fair_threshold = QM_ARB_BYTES;
433 * we multiply by 1e3/8 to get bytes/msec. We don't want the credits
434 * to pass a credit of the T_FAIR*FAIR_MEM (algorithm resolution)
436 pdata->fair_vars.upper_bound = r_param * tFair * FAIR_MEM;
438 /* since each tick is 4 microSeconds */
439 pdata->fair_vars.fairness_timeout =
440 fair_periodic_timeout_usec / SDM_TICKS;
442 /* calculate sum of weights */
445 for (vnic = 0; vnic < ECORE_PORT2_MODE_NUM_VNICS; vnic++)
446 vnicWeightSum += input_data->vnic_min_rate[vnic];
448 /* global vnic counter */
449 if (vnicWeightSum > 0) {
450 /* fairness per-vnic variables */
451 for (vnic = 0; vnic < ECORE_PORT2_MODE_NUM_VNICS; vnic++) {
453 * this is the credit for each period of the fairness
454 * algorithm - number of bytes in T_FAIR (this vnic
455 * share of the port rate)
457 vdata->vnic_min_rate[vnic].vn_credit_delta =
458 ((uint32_t)(input_data->vnic_min_rate[vnic]) * 100 *
459 (T_FAIR_COEF / (8 * 100 * vnicWeightSum)));
460 if (vdata->vnic_min_rate[vnic].vn_credit_delta <
461 pdata->fair_vars.fair_threshold +
463 vdata->vnic_min_rate[vnic].vn_credit_delta =
464 pdata->fair_vars.fair_threshold +
471 static inline void ecore_init_fw_wrr(const struct cmng_init_input *input_data,
472 struct cmng_init *ram_data)
475 uint32_t cosWeightSum = 0;
476 struct cmng_vnic *vdata = &ram_data->vnic;
477 struct cmng_struct_per_port *pdata = &ram_data->port;
479 for (cos = 0; cos < MAX_COS_NUMBER; cos++)
480 cosWeightSum += input_data->cos_min_rate[cos];
482 if (cosWeightSum > 0) {
484 for (vnic = 0; vnic < ECORE_PORT2_MODE_NUM_VNICS; vnic++) {
486 * Since cos and vnic shouldn't work together the rate
487 * to divide between the coses is the port rate.
489 uint32_t *ccd = vdata->vnic_min_rate[vnic].cos_credit_delta;
490 for (cos = 0; cos < MAX_COS_NUMBER; cos++) {
492 * this is the credit for each period of
493 * the fairness algorithm - number of bytes
494 * in T_FAIR (this cos share of the vnic rate)
497 ((uint32_t)input_data->cos_min_rate[cos] * 100 *
498 (T_FAIR_COEF / (8 * 100 * cosWeightSum)));
499 if (ccd[cos] < pdata->fair_vars.fair_threshold
500 + MIN_ABOVE_THRESH) {
502 pdata->fair_vars.fair_threshold +
510 static inline void ecore_init_safc(struct cmng_init *ram_data)
512 /* in microSeconds */
513 ram_data->port.safc_vars.safc_timeout_usec = SAFC_TIMEOUT_USEC;
516 /* Congestion management port init */
517 static inline void ecore_init_cmng(const struct cmng_init_input *input_data,
518 struct cmng_init *ram_data)
521 ECORE_MEMSET(ram_data, 0,sizeof(struct cmng_init));
523 ram_data->port.flags = input_data->flags;
526 * number of bytes transmitted in a rate of 10Gbps
527 * in one usec = 1.25KB.
529 r_param = BITS_TO_BYTES(input_data->port_rate);
530 ecore_init_max(input_data, r_param, ram_data);
531 ecore_init_min(input_data, r_param, ram_data);
532 ecore_init_fw_wrr(input_data, ram_data);
533 ecore_init_safc(ram_data);
539 /* Returns the index of start or end of a specific block stage in ops array*/
540 #define BLOCK_OPS_IDX(block, stage, end) \
541 (2*(((block)*NUM_OF_INIT_PHASES) + (stage)) + (end))
544 #define INITOP_SET 0 /* set the HW directly */
545 #define INITOP_CLEAR 1 /* clear the HW directly */
546 #define INITOP_INIT 2 /* set the init-value array */
548 /****************************************************************************
550 ****************************************************************************/
552 ecore_dma_addr_t page_mapping;
557 struct ilt_client_info {
563 #define ILT_CLIENT_SKIP_INIT 0x1
564 #define ILT_CLIENT_SKIP_MEM 0x2
569 struct ilt_line *lines;
570 struct ilt_client_info clients[4];
571 #define ILT_CLIENT_CDU 0
572 #define ILT_CLIENT_QM 1
573 #define ILT_CLIENT_SRC 2
574 #define ILT_CLIENT_TM 3
577 /****************************************************************************
579 ****************************************************************************/
585 /****************************************************************************
586 * Parity configuration
587 ****************************************************************************/
588 #define BLOCK_PRTY_INFO(block, en_mask, m1h, m2, m3) \
590 block##_REG_##block##_PRTY_MASK, \
591 block##_REG_##block##_PRTY_STS_CLR, \
592 en_mask, {m1h, m2, m3}, #block \
595 #define BLOCK_PRTY_INFO_0(block, en_mask, m1h, m2, m3) \
597 block##_REG_##block##_PRTY_MASK_0, \
598 block##_REG_##block##_PRTY_STS_CLR_0, \
599 en_mask, {m1h, m2, m3}, #block"_0" \
602 #define BLOCK_PRTY_INFO_1(block, en_mask, m1h, m2, m3) \
604 block##_REG_##block##_PRTY_MASK_1, \
605 block##_REG_##block##_PRTY_STS_CLR_1, \
606 en_mask, {m1h, m2, m3}, #block"_1" \
609 static const struct {
611 uint32_t sts_clr_addr;
612 uint32_t en_mask; /* Mask to enable parity attentions */
614 uint32_t e1h; /* 57711 */
615 uint32_t e2; /* 57712 */
616 uint32_t e3; /* 578xx */
617 } reg_mask; /* Register mask (all valid bits) */
618 char name[8]; /* Block's longest name is 7 characters long
621 } ecore_blocks_parity_data[] = {
623 /* REG_WR(bp, PXP_REG_PXP_PRTY_MASK, 0x80000); */
625 /* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_0, 0xfff40020); */
627 /* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_1, 0x20); */
628 /* REG_WR(bp, HC_REG_HC_PRTY_MASK, 0x0); */
629 /* REG_WR(bp, MISC_REG_MISC_PRTY_MASK, 0x0); */
631 /* Block IGU, MISC, PXP and PXP2 parity errors as long as we don't
632 * want to handle "system kill" flow at the moment.
634 BLOCK_PRTY_INFO(PXP, 0x7ffffff, 0x3ffffff, 0x7ffffff,
636 BLOCK_PRTY_INFO_0(PXP2, 0xffffffff, 0xffffffff, 0xffffffff,
638 BLOCK_PRTY_INFO_1(PXP2, 0x1ffffff, 0x7f, 0x7ff, 0x1ffffff),
639 BLOCK_PRTY_INFO(HC, 0x7, 0x7, 0, 0),
640 BLOCK_PRTY_INFO(NIG, 0xffffffff, 0xffffffff, 0, 0),
641 BLOCK_PRTY_INFO_0(NIG, 0xffffffff, 0, 0xffffffff, 0xffffffff),
642 BLOCK_PRTY_INFO_1(NIG, 0xffff, 0, 0xff, 0xffff),
643 BLOCK_PRTY_INFO(IGU, 0x7ff, 0, 0x7ff, 0x7ff),
644 BLOCK_PRTY_INFO(MISC, 0x1, 0x1, 0x1, 0x1),
645 BLOCK_PRTY_INFO(QM, 0, 0xfff, 0xfff, 0xfff),
646 BLOCK_PRTY_INFO(ATC, 0x1f, 0, 0x1f, 0x1f),
647 BLOCK_PRTY_INFO(PGLUE_B, 0x3, 0, 0x3, 0x3),
648 BLOCK_PRTY_INFO(DORQ, 0, 0x3, 0x3, 0x3),
649 {GRCBASE_UPB + PB_REG_PB_PRTY_MASK,
650 GRCBASE_UPB + PB_REG_PB_PRTY_STS_CLR, 0xf,
651 {0xf, 0xf, 0xf}, "UPB"},
652 {GRCBASE_XPB + PB_REG_PB_PRTY_MASK,
653 GRCBASE_XPB + PB_REG_PB_PRTY_STS_CLR, 0,
654 {0xf, 0xf, 0xf}, "XPB"},
655 BLOCK_PRTY_INFO(SRC, 0x4, 0x7, 0x7, 0x7),
656 BLOCK_PRTY_INFO(CDU, 0, 0x1f, 0x1f, 0x1f),
657 BLOCK_PRTY_INFO(CFC, 0, 0xf, 0xf, 0x3f),
658 BLOCK_PRTY_INFO(DBG, 0, 0x1, 0x1, 0x1),
659 BLOCK_PRTY_INFO(DMAE, 0, 0xf, 0xf, 0xf),
660 BLOCK_PRTY_INFO(BRB1, 0, 0xf, 0xf, 0xf),
661 BLOCK_PRTY_INFO(PRS, (1<<6), 0xff, 0xff, 0xff),
662 BLOCK_PRTY_INFO(PBF, 0, 0x3ffff, 0xfffff, 0xfffffff),
663 BLOCK_PRTY_INFO(TM, 0, 0x7f, 0x7f, 0x7f),
664 BLOCK_PRTY_INFO(TSDM, 0x18, 0x7ff, 0x7ff, 0x7ff),
665 BLOCK_PRTY_INFO(CSDM, 0x8, 0x7ff, 0x7ff, 0x7ff),
666 BLOCK_PRTY_INFO(USDM, 0x38, 0x7ff, 0x7ff, 0x7ff),
667 BLOCK_PRTY_INFO(XSDM, 0x8, 0x7ff, 0x7ff, 0x7ff),
668 BLOCK_PRTY_INFO(TCM, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
669 BLOCK_PRTY_INFO(CCM, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
670 BLOCK_PRTY_INFO(UCM, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
671 BLOCK_PRTY_INFO(XCM, 0, 0x3fffffff, 0x3fffffff, 0x3fffffff),
672 BLOCK_PRTY_INFO_0(TSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
673 BLOCK_PRTY_INFO_1(TSEM, 0, 0x1f, 0x3f, 0x3f),
674 BLOCK_PRTY_INFO_0(USEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
675 BLOCK_PRTY_INFO_1(USEM, 0, 0x1f, 0x1f, 0x1f),
676 BLOCK_PRTY_INFO_0(CSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
677 BLOCK_PRTY_INFO_1(CSEM, 0, 0x1f, 0x1f, 0x1f),
678 BLOCK_PRTY_INFO_0(XSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
679 BLOCK_PRTY_INFO_1(XSEM, 0, 0x1f, 0x3f, 0x3f),
683 /* [28] MCP Latched rom_parity
684 * [29] MCP Latched ump_rx_parity
685 * [30] MCP Latched ump_tx_parity
686 * [31] MCP Latched scpad_parity
688 #define MISC_AEU_ENABLE_MCP_PRTY_BITS \
689 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
690 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
691 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \
692 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
694 /* Below registers control the MCP parity attention output. When
695 * MISC_AEU_ENABLE_MCP_PRTY_BITS are set - attentions are
696 * enabled, when cleared - disabled.
698 static const uint32_t mcp_attn_ctl_regs[] = {
699 MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0,
700 MISC_REG_AEU_ENABLE4_NIG_0,
701 MISC_REG_AEU_ENABLE4_PXP_0,
702 MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0,
703 MISC_REG_AEU_ENABLE4_NIG_1,
704 MISC_REG_AEU_ENABLE4_PXP_1
707 static inline void ecore_set_mcp_parity(struct bnx2x_softc *sc, uint8_t enable)
712 for (i = 0; i < ARRSIZE(mcp_attn_ctl_regs); i++) {
713 reg_val = REG_RD(sc, mcp_attn_ctl_regs[i]);
716 reg_val |= MISC_AEU_ENABLE_MCP_PRTY_BITS;
718 reg_val &= ~MISC_AEU_ENABLE_MCP_PRTY_BITS;
720 REG_WR(sc, mcp_attn_ctl_regs[i], reg_val);
724 static inline uint32_t ecore_parity_reg_mask(struct bnx2x_softc *sc, int idx)
727 return ecore_blocks_parity_data[idx].reg_mask.e1h;
728 else if (CHIP_IS_E2(sc))
729 return ecore_blocks_parity_data[idx].reg_mask.e2;
730 else /* CHIP_IS_E3 */
731 return ecore_blocks_parity_data[idx].reg_mask.e3;
734 static inline void ecore_disable_blocks_parity(struct bnx2x_softc *sc)
738 for (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) {
739 uint32_t dis_mask = ecore_parity_reg_mask(sc, i);
742 REG_WR(sc, ecore_blocks_parity_data[i].mask_addr,
744 ECORE_MSG(sc, "Setting parity mask "
746 ecore_blocks_parity_data[i].name, dis_mask);
750 /* Disable MCP parity attentions */
751 ecore_set_mcp_parity(sc, FALSE);
755 * Clear the parity error status registers.
757 static inline void ecore_clear_blocks_parity(struct bnx2x_softc *sc)
760 uint32_t reg_val, mcp_aeu_bits =
761 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY |
762 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY |
763 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY |
764 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY;
766 /* Clear SEM_FAST parities */
767 REG_WR(sc, XSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
768 REG_WR(sc, TSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
769 REG_WR(sc, USEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
770 REG_WR(sc, CSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
772 for (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) {
773 uint32_t reg_mask = ecore_parity_reg_mask(sc, i);
776 reg_val = REG_RD(sc, ecore_blocks_parity_data[i].
778 if (reg_val & reg_mask)
779 ECORE_MSG(sc, "Parity errors in %s: 0x%x",
780 ecore_blocks_parity_data[i].name,
785 /* Check if there were parity attentions in MCP */
786 reg_val = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_MCP);
787 if (reg_val & mcp_aeu_bits)
788 ECORE_MSG(sc, "Parity error in MCP: 0x%x",
789 reg_val & mcp_aeu_bits);
791 /* Clear parity attentions in MCP:
792 * [7] clears Latched rom_parity
793 * [8] clears Latched ump_rx_parity
794 * [9] clears Latched ump_tx_parity
795 * [10] clears Latched scpad_parity (both ports)
797 REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x780);
800 static inline void ecore_enable_blocks_parity(struct bnx2x_softc *sc)
804 for (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) {
805 uint32_t reg_mask = ecore_parity_reg_mask(sc, i);
808 REG_WR(sc, ecore_blocks_parity_data[i].mask_addr,
809 ecore_blocks_parity_data[i].en_mask & reg_mask);
812 /* Enable MCP parity attentions */
813 ecore_set_mcp_parity(sc, TRUE);
817 #endif /* ECORE_INIT_H */