2 * Copyright (c) 2007-2013 Cavium Inc. All rights reserved.
4 * Eric Davis <edavis@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
6 * Gary Zambrano <zambrano@broadcom.com>
8 * Copyright (c) 2014-2018 Cavium Inc.
12 * See LICENSE.bnx2x_pmd for copyright and licensing details.
19 #define ATC_ATC_INT_STS_REG_ADDRESS_ERROR \
21 #define ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS \
23 #define ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU \
25 #define ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT \
27 #define ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR \
29 #define ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND \
31 #define ATC_REG_ATC_INIT_DONE \
33 #define ATC_REG_ATC_INT_STS_CLR \
35 #define ATC_REG_ATC_PRTY_MASK \
37 #define ATC_REG_ATC_PRTY_STS_CLR \
39 #define BRB1_REG_BRB1_INT_MASK \
41 #define BRB1_REG_BRB1_PRTY_MASK \
43 #define BRB1_REG_BRB1_PRTY_STS_CLR \
45 #define BRB1_REG_MAC_GUARANTIED_0 \
47 #define BRB1_REG_MAC_GUARANTIED_1 \
49 #define BRB1_REG_NUM_OF_FULL_BLOCKS \
51 #define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 \
53 #define BRB1_REG_PAUSE_LOW_THRESHOLD_0 \
55 #define BRB1_REG_PORT_NUM_OCC_BLOCKS_0 \
57 #define CCM_REG_CCM_INT_MASK \
59 #define CCM_REG_CCM_PRTY_MASK \
61 #define CCM_REG_CCM_PRTY_STS_CLR \
63 #define CDU_REG_CDU_GLOBAL_PARAMS \
65 #define CDU_REG_CDU_INT_MASK \
67 #define CDU_REG_CDU_PRTY_MASK \
69 #define CDU_REG_CDU_PRTY_STS_CLR \
71 #define CFC_REG_AC_INIT_DONE \
73 #define CFC_REG_CAM_INIT_DONE \
75 #define CFC_REG_CFC_INT_MASK \
77 #define CFC_REG_CFC_INT_STS_CLR \
79 #define CFC_REG_CFC_PRTY_MASK \
81 #define CFC_REG_CFC_PRTY_STS_CLR \
83 #define CFC_REG_DEBUG0 \
85 #define CFC_REG_INIT_REG \
87 #define CFC_REG_LL_INIT_DONE \
89 #define CFC_REG_NUM_LCIDS_INSIDE_PF \
91 #define CFC_REG_STRONG_ENABLE_PF \
93 #define CFC_REG_WEAK_ENABLE_PF \
95 #define CSDM_REG_CSDM_INT_MASK_0 \
97 #define CSDM_REG_CSDM_INT_MASK_1 \
99 #define CSDM_REG_CSDM_PRTY_MASK \
101 #define CSDM_REG_CSDM_PRTY_STS_CLR \
103 #define CSEM_REG_CSEM_INT_MASK_0 \
105 #define CSEM_REG_CSEM_INT_MASK_1 \
107 #define CSEM_REG_CSEM_PRTY_MASK_0 \
109 #define CSEM_REG_CSEM_PRTY_MASK_1 \
111 #define CSEM_REG_CSEM_PRTY_STS_CLR_0 \
113 #define CSEM_REG_CSEM_PRTY_STS_CLR_1 \
115 #define CSEM_REG_FAST_MEMORY \
117 #define CSEM_REG_INT_TABLE \
119 #define CSEM_REG_PASSIVE_BUFFER \
121 #define CSEM_REG_PRAM \
123 #define CSEM_REG_VFPF_ERR_NUM \
125 #define DBG_REG_DBG_PRTY_MASK \
127 #define DBG_REG_DBG_PRTY_STS_CLR \
129 #define DMAE_REG_BACKWARD_COMP_EN \
131 #define DMAE_REG_CMD_MEM \
133 #define DMAE_REG_DMAE_INT_MASK \
135 #define DMAE_REG_DMAE_PRTY_MASK \
137 #define DMAE_REG_DMAE_PRTY_STS_CLR \
139 #define DMAE_REG_GO_C0 \
141 #define DMAE_REG_GO_C1 \
143 #define DMAE_REG_GO_C10 \
145 #define DMAE_REG_GO_C11 \
147 #define DMAE_REG_GO_C12 \
149 #define DMAE_REG_GO_C13 \
151 #define DMAE_REG_GO_C14 \
153 #define DMAE_REG_GO_C15 \
155 #define DMAE_REG_GO_C2 \
157 #define DMAE_REG_GO_C3 \
159 #define DMAE_REG_GO_C4 \
161 #define DMAE_REG_GO_C5 \
163 #define DMAE_REG_GO_C6 \
165 #define DMAE_REG_GO_C7 \
167 #define DMAE_REG_GO_C8 \
169 #define DMAE_REG_GO_C9 \
171 #define DORQ_REG_DORQ_INT_MASK \
173 #define DORQ_REG_DORQ_INT_STS_CLR \
175 #define DORQ_REG_DORQ_PRTY_MASK \
177 #define DORQ_REG_DORQ_PRTY_STS_CLR \
179 #define DORQ_REG_DPM_CID_OFST \
181 #define DORQ_REG_MAX_RVFID_SIZE \
183 #define DORQ_REG_NORM_CID_OFST \
185 #define DORQ_REG_PF_USAGE_CNT \
187 #define DORQ_REG_VF_NORM_CID_BASE \
189 #define DORQ_REG_VF_NORM_CID_OFST \
191 #define DORQ_REG_VF_NORM_CID_WND_SIZE \
193 #define DORQ_REG_VF_NORM_MAX_CID_COUNT \
195 #define DORQ_REG_VF_NORM_VF_BASE \
197 #define DORQ_REG_VF_TYPE_MASK_0 \
199 #define DORQ_REG_VF_TYPE_MAX_MCID_0 \
201 #define DORQ_REG_VF_TYPE_MIN_MCID_0 \
203 #define DORQ_REG_VF_TYPE_VALUE_0 \
205 #define DORQ_REG_VF_USAGE_CNT \
207 #define DORQ_REG_VF_USAGE_CT_LIMIT \
209 #define HC_CONFIG_0_REG_ATTN_BIT_EN_0 \
211 #define HC_CONFIG_0_REG_BLOCK_DISABLE_0 \
213 #define HC_CONFIG_0_REG_INT_LINE_EN_0 \
215 #define HC_CONFIG_0_REG_MSI_ATTN_EN_0 \
217 #define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 \
219 #define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 \
221 #define HC_CONFIG_1_REG_BLOCK_DISABLE_1 \
223 #define HC_REG_ATTN_MSG0_ADDR_L \
225 #define HC_REG_ATTN_MSG1_ADDR_L \
227 #define HC_REG_COMMAND_REG \
229 #define HC_REG_CONFIG_0 \
231 #define HC_REG_CONFIG_1 \
233 #define HC_REG_HC_PRTY_MASK \
235 #define HC_REG_HC_PRTY_STS_CLR \
237 #define HC_REG_INT_MASK \
239 #define HC_REG_LEADING_EDGE_0 \
241 #define HC_REG_MAIN_MEMORY \
243 #define HC_REG_MAIN_MEMORY_SIZE \
245 #define HC_REG_TRAILING_EDGE_0 \
247 #define IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN \
249 #define IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE \
251 #define IGU_REG_ATTENTION_ACK_BITS \
253 #define IGU_REG_ATTN_MSG_ADDR_H \
255 #define IGU_REG_ATTN_MSG_ADDR_L \
257 #define IGU_REG_BLOCK_CONFIGURATION \
259 #define IGU_REG_COMMAND_REG_32LSB_DATA \
261 #define IGU_REG_COMMAND_REG_CTRL \
263 #define IGU_REG_CSTORM_TYPE_0_SB_CLEANUP \
265 #define IGU_REG_IGU_PRTY_MASK \
267 #define IGU_REG_IGU_PRTY_STS_CLR \
269 #define IGU_REG_LEADING_EDGE_LATCH \
271 #define IGU_REG_MAPPING_MEMORY \
273 #define IGU_REG_MAPPING_MEMORY_SIZE \
275 #define IGU_REG_PBA_STATUS_LSB \
277 #define IGU_REG_PBA_STATUS_MSB \
279 #define IGU_REG_PCI_PF_MSIX_EN \
281 #define IGU_REG_PCI_PF_MSIX_FUNC_MASK \
283 #define IGU_REG_PCI_PF_MSI_EN \
285 #define IGU_REG_PENDING_BITS_STATUS \
287 #define IGU_REG_PF_CONFIGURATION \
289 #define IGU_REG_PROD_CONS_MEMORY \
291 #define IGU_REG_RESET_MEMORIES \
293 #define IGU_REG_SB_INT_BEFORE_MASK_LSB \
295 #define IGU_REG_SB_INT_BEFORE_MASK_MSB \
297 #define IGU_REG_SB_MASK_LSB \
299 #define IGU_REG_SB_MASK_MSB \
301 #define IGU_REG_STATISTIC_NUM_MESSAGE_SENT \
303 #define IGU_REG_TRAILING_EDGE_LATCH \
305 #define IGU_REG_VF_CONFIGURATION \
307 #define MCP_REG_MCPR_ACCESS_LOCK \
309 #define MCP_REG_MCPR_GP_INPUTS \
311 #define MCP_REG_MCPR_GP_OENABLE \
313 #define MCP_REG_MCPR_GP_OUTPUTS \
315 #define MCP_REG_MCPR_IMC_COMMAND \
317 #define MCP_REG_MCPR_IMC_DATAREG0 \
319 #define MCP_REG_MCPR_IMC_SLAVE_CONTROL \
321 #define MCP_REG_MCPR_NVM_ACCESS_ENABLE \
323 #define MCP_REG_MCPR_NVM_ADDR \
325 #define MCP_REG_MCPR_NVM_CFG4 \
327 #define MCP_REG_MCPR_NVM_COMMAND \
329 #define MCP_REG_MCPR_NVM_READ \
331 #define MCP_REG_MCPR_NVM_SW_ARB \
333 #define MCP_REG_MCPR_NVM_WRITE \
335 #define MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK \
337 #define MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK \
339 #define MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 \
341 #define MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 \
343 #define MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 \
345 #define MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 \
347 #define MISC_REG_AEU_AFTER_INVERT_4_MCP \
349 #define MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 \
351 #define MISC_REG_AEU_CLR_LATCH_SIGNAL \
353 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0 \
355 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1 \
357 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2 \
359 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 \
361 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 \
363 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 \
365 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 \
367 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 \
369 #define MISC_REG_AEU_ENABLE4_NIG_0 \
371 #define MISC_REG_AEU_ENABLE4_NIG_1 \
373 #define MISC_REG_AEU_ENABLE4_PXP_0 \
375 #define MISC_REG_AEU_ENABLE4_PXP_1 \
377 #define MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0 \
379 #define MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 \
381 #define MISC_REG_AEU_GENERAL_ATTN_0 \
383 #define MISC_REG_AEU_GENERAL_ATTN_1 \
385 #define MISC_REG_AEU_GENERAL_ATTN_10 \
387 #define MISC_REG_AEU_GENERAL_ATTN_11 \
389 #define MISC_REG_AEU_GENERAL_ATTN_12 \
391 #define MISC_REG_AEU_GENERAL_ATTN_2 \
393 #define MISC_REG_AEU_GENERAL_ATTN_3 \
395 #define MISC_REG_AEU_GENERAL_ATTN_4 \
397 #define MISC_REG_AEU_GENERAL_ATTN_5 \
399 #define MISC_REG_AEU_GENERAL_ATTN_6 \
401 #define MISC_REG_AEU_GENERAL_ATTN_7 \
403 #define MISC_REG_AEU_GENERAL_ATTN_8 \
405 #define MISC_REG_AEU_GENERAL_ATTN_9 \
407 #define MISC_REG_AEU_GENERAL_MASK \
409 #define MISC_REG_AEU_MASK_ATTN_FUNC_0 \
411 #define MISC_REG_AEU_MASK_ATTN_FUNC_1 \
413 #define MISC_REG_BOND_ID \
415 #define MISC_REG_CHIP_NUM \
417 #define MISC_REG_CHIP_REV \
419 #define MISC_REG_CHIP_TYPE \
421 #define MISC_REG_CHIP_TYPE_57811_MASK \
423 #define MISC_REG_CPMU_LP_DR_ENABLE \
425 #define MISC_REG_CPMU_LP_FW_ENABLE_P0 \
427 #define MISC_REG_CPMU_LP_IDLE_THR_P0 \
429 #define MISC_REG_CPMU_LP_MASK_ENT_P0 \
431 #define MISC_REG_CPMU_LP_MASK_EXT_P0 \
433 #define MISC_REG_CPMU_LP_SM_ENT_CNT_P0 \
435 #define MISC_REG_CPMU_LP_SM_ENT_CNT_P1 \
437 #define MISC_REG_DRIVER_CONTROL_1 \
439 #define MISC_REG_DRIVER_CONTROL_7 \
441 #define MISC_REG_FOUR_PORT_PATH_SWAP \
443 #define MISC_REG_FOUR_PORT_PATH_SWAP_OVWR \
445 #define MISC_REG_FOUR_PORT_PORT_SWAP \
447 #define MISC_REG_FOUR_PORT_PORT_SWAP_OVWR \
449 #define MISC_REG_GENERIC_CR_0 \
451 #define MISC_REG_GENERIC_CR_1 \
453 #define MISC_REG_GENERIC_POR_1 \
455 #define MISC_REG_GEN_PURP_HWG \
457 #define MISC_REG_GPIO \
459 #define MISC_REG_GPIO_EVENT_EN \
461 #define MISC_REG_GPIO_INT \
463 #define MISC_REG_GRC_RSV_ATTN \
465 #define MISC_REG_GRC_TIMEOUT_ATTN \
467 #define MISC_REG_LCPLL_E40_PWRDWN \
469 #define MISC_REG_LCPLL_E40_RESETB_ANA \
471 #define MISC_REG_LCPLL_E40_RESETB_DIG \
473 #define MISC_REG_MISC_INT_MASK \
475 #define MISC_REG_MISC_PRTY_MASK \
477 #define MISC_REG_MISC_PRTY_STS_CLR \
479 #define MISC_REG_PORT4MODE_EN \
481 #define MISC_REG_PORT4MODE_EN_OVWR \
483 #define MISC_REG_RESET_REG_1 \
485 #define MISC_REG_RESET_REG_2 \
487 #define MISC_REG_SHARED_MEM_ADDR \
489 #define MISC_REG_SPIO \
491 #define MISC_REG_SPIO_EVENT_EN \
493 #define MISC_REG_SPIO_INT \
495 #define MISC_REG_TWO_PORT_PATH_SWAP \
497 #define MISC_REG_TWO_PORT_PATH_SWAP_OVWR \
499 #define MISC_REG_UNPREPARED \
501 #define MISC_REG_WC0_CTRL_PHY_ADDR \
503 #define MISC_REG_WC0_RESET \
505 #define MISC_REG_XMAC_CORE_PORT_MODE \
507 #define MISC_REG_XMAC_PHY_PORT_MODE \
509 #define MSTAT_REG_RX_STAT_GR64_LO \
511 #define MSTAT_REG_TX_STAT_GTXPOK_LO \
513 #define NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN \
515 #define NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN \
517 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT \
519 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS \
521 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G \
523 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS \
525 #define NIG_REG_BMAC0_IN_EN \
527 #define NIG_REG_BMAC0_OUT_EN \
529 #define NIG_REG_BMAC0_PAUSE_OUT_EN \
531 #define NIG_REG_BMAC0_REGS_OUT_EN \
533 #define NIG_REG_BRB0_PAUSE_IN_EN \
535 #define NIG_REG_BRB1_PAUSE_IN_EN \
537 #define NIG_REG_DEBUG_PACKET_LB \
539 #define NIG_REG_EGRESS_DRAIN0_MODE \
541 #define NIG_REG_EGRESS_EMAC0_OUT_EN \
543 #define NIG_REG_EGRESS_EMAC0_PORT \
545 #define NIG_REG_EMAC0_IN_EN \
547 #define NIG_REG_EMAC0_PAUSE_OUT_EN \
549 #define NIG_REG_EMAC0_STATUS_MISC_MI_INT \
551 #define NIG_REG_INGRESS_BMAC0_MEM \
553 #define NIG_REG_INGRESS_BMAC1_MEM \
555 #define NIG_REG_INGRESS_EOP_LB_EMPTY \
557 #define NIG_REG_INGRESS_EOP_LB_FIFO \
559 #define NIG_REG_LATCH_BC_0 \
561 #define NIG_REG_LATCH_STATUS_0 \
563 #define NIG_REG_LED_10G_P0 \
565 #define NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 \
567 #define NIG_REG_LED_CONTROL_BLINK_RATE_P0 \
569 #define NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 \
571 #define NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 \
573 #define NIG_REG_LED_CONTROL_TRAFFIC_P0 \
575 #define NIG_REG_LED_MODE_P0 \
577 #define NIG_REG_LLFC_EGRESS_SRC_ENABLE_0 \
579 #define NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 \
581 #define NIG_REG_LLFC_ENABLE_0 \
583 #define NIG_REG_LLFC_ENABLE_1 \
585 #define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0 \
587 #define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 \
589 #define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0 \
591 #define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 \
593 #define NIG_REG_LLFC_OUT_EN_0 \
595 #define NIG_REG_LLFC_OUT_EN_1 \
597 #define NIG_REG_LLH0_BRB1_DRV_MASK \
599 #define NIG_REG_LLH0_BRB1_DRV_MASK_MF \
601 #define NIG_REG_LLH0_BRB1_NOT_MCP \
603 #define NIG_REG_LLH0_CLS_TYPE \
605 #define NIG_REG_LLH0_FUNC_EN \
607 #define NIG_REG_LLH0_FUNC_MEM \
609 #define NIG_REG_LLH0_FUNC_MEM_ENABLE \
611 #define NIG_REG_LLH0_FUNC_VLAN_ID \
613 #define NIG_REG_LLH0_XCM_MASK \
615 #define NIG_REG_LLH1_BRB1_NOT_MCP \
617 #define NIG_REG_LLH1_CLS_TYPE \
619 #define NIG_REG_LLH1_FUNC_MEM \
621 #define NIG_REG_LLH1_FUNC_MEM_ENABLE \
623 #define NIG_REG_LLH1_FUNC_MEM_SIZE \
625 #define NIG_REG_LLH1_MF_MODE \
627 #define NIG_REG_LLH1_XCM_MASK \
629 #define NIG_REG_LLH_E1HOV_MODE \
631 #define NIG_REG_LLH_MF_MODE \
633 #define NIG_REG_MASK_INTERRUPT_PORT0 \
635 #define NIG_REG_MASK_INTERRUPT_PORT1 \
637 #define NIG_REG_NIG_EMAC0_EN \
639 #define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC \
641 #define NIG_REG_NIG_INT_STS_CLR_0 \
643 #define NIG_REG_NIG_PRTY_MASK \
645 #define NIG_REG_NIG_PRTY_MASK_0 \
647 #define NIG_REG_NIG_PRTY_MASK_1 \
649 #define NIG_REG_NIG_PRTY_STS_CLR \
651 #define NIG_REG_NIG_PRTY_STS_CLR_0 \
653 #define NIG_REG_NIG_PRTY_STS_CLR_1 \
655 #define NIG_REG_P0_HDRS_AFTER_BASIC \
657 #define NIG_REG_P0_HWPFC_ENABLE \
659 #define NIG_REG_P0_LLH_FUNC_MEM2 \
661 #define NIG_REG_P0_MAC_IN_EN \
663 #define NIG_REG_P0_MAC_OUT_EN \
665 #define NIG_REG_P0_MAC_PAUSE_OUT_EN \
667 #define NIG_REG_P0_PKT_PRIORITY_TO_COS \
669 #define NIG_REG_P0_RX_COS0_PRIORITY_MASK \
671 #define NIG_REG_P0_RX_COS1_PRIORITY_MASK \
673 #define NIG_REG_P0_RX_COS2_PRIORITY_MASK \
675 #define NIG_REG_P0_RX_COS3_PRIORITY_MASK \
677 #define NIG_REG_P0_RX_COS4_PRIORITY_MASK \
679 #define NIG_REG_P0_RX_COS5_PRIORITY_MASK \
681 #define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP \
683 #define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB \
685 #define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB \
687 #define NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT \
689 #define NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ \
691 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0 \
693 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1 \
695 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2 \
697 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3 \
699 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4 \
701 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5 \
703 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6 \
705 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7 \
707 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8 \
709 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0 \
711 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1 \
713 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2 \
715 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3 \
717 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4 \
719 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5 \
721 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6 \
723 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7 \
725 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8 \
727 #define NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS \
729 #define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT \
731 #define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB \
733 #define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB \
735 #define NIG_REG_P1_HDRS_AFTER_BASIC \
737 #define NIG_REG_P1_HWPFC_ENABLE \
739 #define NIG_REG_P1_LLH_FUNC_MEM2 \
741 #define NIG_REG_P1_MAC_IN_EN \
743 #define NIG_REG_P1_MAC_OUT_EN \
745 #define NIG_REG_P1_MAC_PAUSE_OUT_EN \
747 #define NIG_REG_P1_PKT_PRIORITY_TO_COS \
749 #define NIG_REG_P1_RX_COS0_PRIORITY_MASK \
751 #define NIG_REG_P1_RX_COS1_PRIORITY_MASK \
753 #define NIG_REG_P1_RX_COS2_PRIORITY_MASK \
755 #define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB \
757 #define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB \
759 #define NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT \
761 #define NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ \
763 #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 \
765 #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 \
767 #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 \
769 #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 \
771 #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 \
773 #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 \
775 #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 \
777 #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 \
779 #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 \
781 #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 \
783 #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 \
785 #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 \
787 #define NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS \
789 #define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB \
791 #define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB \
793 #define NIG_REG_PAUSE_ENABLE_0 \
795 #define NIG_REG_PAUSE_ENABLE_1 \
797 #define NIG_REG_PORT_SWAP \
799 #define NIG_REG_PPP_ENABLE_0 \
801 #define NIG_REG_PPP_ENABLE_1 \
803 #define NIG_REG_PRS_REQ_IN_EN \
805 #define NIG_REG_SERDES0_CTRL_MD_DEVAD \
807 #define NIG_REG_SERDES0_CTRL_MD_ST \
809 #define NIG_REG_SERDES0_CTRL_PHY_ADDR \
811 #define NIG_REG_SERDES0_STATUS_LINK_STATUS \
813 #define NIG_REG_STAT0_BRB_DISCARD \
815 #define NIG_REG_STAT0_BRB_TRUNCATE \
817 #define NIG_REG_STAT0_EGRESS_MAC_PKT0 \
819 #define NIG_REG_STAT0_EGRESS_MAC_PKT1 \
821 #define NIG_REG_STAT1_BRB_DISCARD \
823 #define NIG_REG_STAT1_EGRESS_MAC_PKT0 \
825 #define NIG_REG_STAT1_EGRESS_MAC_PKT1 \
827 #define NIG_REG_STAT2_BRB_OCTET \
829 #define NIG_REG_STATUS_INTERRUPT_PORT0 \
831 #define NIG_REG_STRAP_OVERRIDE \
833 #define NIG_REG_XCM0_OUT_EN \
835 #define NIG_REG_XCM1_OUT_EN \
837 #define NIG_REG_XGXS0_CTRL_MD_DEVAD \
839 #define NIG_REG_XGXS0_CTRL_MD_ST \
841 #define NIG_REG_XGXS0_CTRL_PHY_ADDR \
843 #define NIG_REG_XGXS0_STATUS_LINK10G \
845 #define NIG_REG_XGXS0_STATUS_LINK_STATUS \
847 #define NIG_REG_XGXS_LANE_SEL_P0 \
849 #define NIG_REG_XGXS_SERDES0_MODE_SEL \
851 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT \
853 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS \
855 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G \
857 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS \
859 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE \
861 #define PBF_REG_COS0_UPPER_BOUND \
863 #define PBF_REG_COS0_UPPER_BOUND_P0 \
865 #define PBF_REG_COS0_UPPER_BOUND_P1 \
867 #define PBF_REG_COS0_WEIGHT \
869 #define PBF_REG_COS0_WEIGHT_P0 \
871 #define PBF_REG_COS0_WEIGHT_P1 \
873 #define PBF_REG_COS1_UPPER_BOUND \
875 #define PBF_REG_COS1_WEIGHT \
877 #define PBF_REG_COS1_WEIGHT_P0 \
879 #define PBF_REG_COS1_WEIGHT_P1 \
881 #define PBF_REG_COS2_WEIGHT_P0 \
883 #define PBF_REG_COS2_WEIGHT_P1 \
885 #define PBF_REG_COS3_WEIGHT_P0 \
887 #define PBF_REG_COS4_WEIGHT_P0 \
889 #define PBF_REG_COS5_WEIGHT_P0 \
891 #define PBF_REG_CREDIT_LB_Q \
893 #define PBF_REG_CREDIT_Q0 \
895 #define PBF_REG_CREDIT_Q1 \
897 #define PBF_REG_DISABLE_NEW_TASK_PROC_P0 \
899 #define PBF_REG_DISABLE_PF \
901 #define PBF_REG_DISABLE_VF \
903 #define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0 \
905 #define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1 \
907 #define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 \
909 #define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 \
911 #define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 \
913 #define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 \
915 #define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 \
917 #define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 \
919 #define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 \
921 #define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 \
923 #define PBF_REG_ETS_ENABLED \
925 #define PBF_REG_HDRS_AFTER_BASIC \
927 #define PBF_REG_HDRS_AFTER_TAG_0 \
929 #define PBF_REG_HIGH_PRIORITY_COS_NUM \
931 #define PBF_REG_INIT_CRD_LB_Q \
933 #define PBF_REG_INIT_CRD_Q0 \
935 #define PBF_REG_INIT_CRD_Q1 \
937 #define PBF_REG_INIT_P0 \
939 #define PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q \
941 #define PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 \
943 #define PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 \
945 #define PBF_REG_MUST_HAVE_HDRS \
947 #define PBF_REG_NUM_STRICT_ARB_SLOTS \
949 #define PBF_REG_P0_ARB_THRSH \
951 #define PBF_REG_P0_CREDIT \
953 #define PBF_REG_P0_INIT_CRD \
955 #define PBF_REG_P0_INTERNAL_CRD_FREED_CNT \
957 #define PBF_REG_P0_PAUSE_ENABLE \
959 #define PBF_REG_P0_TQ_LINES_FREED_CNT \
961 #define PBF_REG_P0_TQ_OCCUPANCY \
963 #define PBF_REG_P1_CREDIT \
965 #define PBF_REG_P1_INIT_CRD \
967 #define PBF_REG_P1_INTERNAL_CRD_FREED_CNT \
969 #define PBF_REG_P1_TQ_LINES_FREED_CNT \
971 #define PBF_REG_P1_TQ_OCCUPANCY \
973 #define PBF_REG_P4_CREDIT \
975 #define PBF_REG_P4_INIT_CRD \
977 #define PBF_REG_P4_INTERNAL_CRD_FREED_CNT \
979 #define PBF_REG_P4_TQ_LINES_FREED_CNT \
981 #define PBF_REG_P4_TQ_OCCUPANCY \
983 #define PBF_REG_PBF_INT_MASK \
985 #define PBF_REG_PBF_PRTY_MASK \
987 #define PBF_REG_PBF_PRTY_STS_CLR \
989 #define PBF_REG_TAG_ETHERTYPE_0 \
991 #define PBF_REG_TAG_LEN_0 \
993 #define PBF_REG_TQ_LINES_FREED_CNT_LB_Q \
995 #define PBF_REG_TQ_LINES_FREED_CNT_Q0 \
997 #define PBF_REG_TQ_LINES_FREED_CNT_Q1 \
999 #define PBF_REG_TQ_OCCUPANCY_LB_Q \
1001 #define PBF_REG_TQ_OCCUPANCY_Q0 \
1003 #define PBF_REG_TQ_OCCUPANCY_Q1 \
1005 #define PB_REG_PB_INT_MASK \
1007 #define PB_REG_PB_PRTY_MASK \
1009 #define PB_REG_PB_PRTY_STS_CLR \
1011 #define PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR \
1013 #define PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW \
1015 #define PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR \
1017 #define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN \
1019 #define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN \
1021 #define PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN \
1023 #define PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN \
1025 #define PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN \
1027 #define PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN \
1029 #define PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR \
1031 #define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR \
1033 #define PGLUE_B_REG_WAS_ERROR_VF_63_32_CLR \
1035 #define PGLUE_B_REG_WAS_ERROR_VF_95_64_CLR \
1037 #define PGLUE_B_REG_WAS_ERROR_VF_127_96_CLR \
1039 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER \
1041 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ \
1043 #define PGLUE_B_REG_INTERNAL_VFID_ENABLE \
1045 #define PGLUE_B_REG_PGLUE_B_INT_STS \
1047 #define PGLUE_B_REG_PGLUE_B_INT_STS_CLR \
1049 #define PGLUE_B_REG_PGLUE_B_PRTY_MASK \
1051 #define PGLUE_B_REG_PGLUE_B_PRTY_STS_CLR \
1053 #define PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR \
1055 #define PGLUE_B_REG_TAGS_63_32 \
1057 #define PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR \
1059 #define PRS_REG_A_PRSU_20 \
1061 #define PRS_REG_CFC_SEARCH_INITIAL_CREDIT \
1063 #define PRS_REG_E1HOV_MODE \
1065 #define PRS_REG_HDRS_AFTER_BASIC \
1067 #define PRS_REG_HDRS_AFTER_BASIC_PORT_0 \
1069 #define PRS_REG_HDRS_AFTER_BASIC_PORT_1 \
1071 #define PRS_REG_HDRS_AFTER_TAG_0 \
1073 #define PRS_REG_HDRS_AFTER_TAG_0_PORT_0 \
1075 #define PRS_REG_HDRS_AFTER_TAG_0_PORT_1 \
1077 #define PRS_REG_MUST_HAVE_HDRS \
1079 #define PRS_REG_MUST_HAVE_HDRS_PORT_0 \
1081 #define PRS_REG_MUST_HAVE_HDRS_PORT_1 \
1083 #define PRS_REG_NIC_MODE \
1085 #define PRS_REG_NUM_OF_PACKETS \
1087 #define PRS_REG_PRS_PRTY_MASK \
1089 #define PRS_REG_PRS_PRTY_STS_CLR \
1091 #define PRS_REG_TAG_ETHERTYPE_0 \
1093 #define PRS_REG_TAG_LEN_0 \
1095 #define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT \
1097 #define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF \
1099 #define PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN \
1101 #define PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED \
1103 #define PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED \
1105 #define PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR \
1107 #define PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR \
1109 #define PXP2_REG_PGL_ADDR_88_F0 \
1111 #define PXP2_REG_PGL_ADDR_88_F1 \
1113 #define PXP2_REG_PGL_ADDR_8C_F0 \
1115 #define PXP2_REG_PGL_ADDR_8C_F1 \
1117 #define PXP2_REG_PGL_ADDR_90_F0 \
1119 #define PXP2_REG_PGL_ADDR_90_F1 \
1121 #define PXP2_REG_PGL_ADDR_94_F0 \
1123 #define PXP2_REG_PGL_ADDR_94_F1 \
1125 #define PXP2_REG_PGL_EXP_ROM2 \
1127 #define PXP2_REG_PGL_PRETEND_FUNC_F0 \
1129 #define PXP2_REG_PGL_PRETEND_FUNC_F1 \
1131 #define PXP2_REG_PGL_TAGS_LIMIT \
1133 #define PXP2_REG_PSWRQ_BW_ADD1 \
1135 #define PXP2_REG_PSWRQ_BW_ADD10 \
1137 #define PXP2_REG_PSWRQ_BW_ADD11 \
1139 #define PXP2_REG_PSWRQ_BW_ADD2 \
1141 #define PXP2_REG_PSWRQ_BW_ADD28 \
1143 #define PXP2_REG_PSWRQ_BW_ADD3 \
1145 #define PXP2_REG_PSWRQ_BW_ADD6 \
1147 #define PXP2_REG_PSWRQ_BW_ADD7 \
1149 #define PXP2_REG_PSWRQ_BW_ADD8 \
1151 #define PXP2_REG_PSWRQ_BW_ADD9 \
1153 #define PXP2_REG_PSWRQ_BW_L1 \
1155 #define PXP2_REG_PSWRQ_BW_L10 \
1157 #define PXP2_REG_PSWRQ_BW_L11 \
1159 #define PXP2_REG_PSWRQ_BW_L2 \
1161 #define PXP2_REG_PSWRQ_BW_L28 \
1163 #define PXP2_REG_PSWRQ_BW_L3 \
1165 #define PXP2_REG_PSWRQ_BW_L6 \
1167 #define PXP2_REG_PSWRQ_BW_L7 \
1169 #define PXP2_REG_PSWRQ_BW_L8 \
1171 #define PXP2_REG_PSWRQ_BW_L9 \
1173 #define PXP2_REG_PSWRQ_BW_RD \
1175 #define PXP2_REG_PSWRQ_BW_UB1 \
1177 #define PXP2_REG_PSWRQ_BW_UB10 \
1179 #define PXP2_REG_PSWRQ_BW_UB11 \
1181 #define PXP2_REG_PSWRQ_BW_UB2 \
1183 #define PXP2_REG_PSWRQ_BW_UB28 \
1185 #define PXP2_REG_PSWRQ_BW_UB3 \
1187 #define PXP2_REG_PSWRQ_BW_UB6 \
1189 #define PXP2_REG_PSWRQ_BW_UB7 \
1191 #define PXP2_REG_PSWRQ_BW_UB8 \
1193 #define PXP2_REG_PSWRQ_BW_UB9 \
1195 #define PXP2_REG_PSWRQ_BW_WR \
1197 #define PXP2_REG_PSWRQ_CDU0_L2P \
1199 #define PXP2_REG_PSWRQ_QM0_L2P \
1201 #define PXP2_REG_PSWRQ_SRC0_L2P \
1203 #define PXP2_REG_PSWRQ_TM0_L2P \
1205 #define PXP2_REG_PXP2_INT_MASK_0 \
1207 #define PXP2_REG_PXP2_INT_MASK_1 \
1209 #define PXP2_REG_PXP2_INT_STS_0 \
1211 #define PXP2_REG_PXP2_INT_STS_1 \
1213 #define PXP2_REG_PXP2_INT_STS_CLR_0 \
1215 #define PXP2_REG_PXP2_PRTY_MASK_0 \
1217 #define PXP2_REG_PXP2_PRTY_MASK_1 \
1219 #define PXP2_REG_PXP2_PRTY_STS_CLR_0 \
1221 #define PXP2_REG_PXP2_PRTY_STS_CLR_1 \
1223 #define PXP2_REG_RD_BLK_CNT \
1225 #define PXP2_REG_RD_CDURD_SWAP_MODE \
1227 #define PXP2_REG_RD_DISABLE_INPUTS \
1229 #define PXP2_REG_RD_INIT_DONE \
1231 #define PXP2_REG_RD_PBF_SWAP_MODE \
1233 #define PXP2_REG_RD_PORT_IS_IDLE_0 \
1235 #define PXP2_REG_RD_PORT_IS_IDLE_1 \
1237 #define PXP2_REG_RD_QM_SWAP_MODE \
1239 #define PXP2_REG_RD_SRC_SWAP_MODE \
1241 #define PXP2_REG_RD_SR_CNT \
1243 #define PXP2_REG_RD_START_INIT \
1245 #define PXP2_REG_RD_TM_SWAP_MODE \
1247 #define PXP2_REG_RQ_BW_RD_ADD0 \
1249 #define PXP2_REG_RQ_BW_RD_ADD12 \
1251 #define PXP2_REG_RQ_BW_RD_ADD13 \
1253 #define PXP2_REG_RQ_BW_RD_ADD14 \
1255 #define PXP2_REG_RQ_BW_RD_ADD15 \
1257 #define PXP2_REG_RQ_BW_RD_ADD16 \
1259 #define PXP2_REG_RQ_BW_RD_ADD17 \
1261 #define PXP2_REG_RQ_BW_RD_ADD18 \
1263 #define PXP2_REG_RQ_BW_RD_ADD19 \
1265 #define PXP2_REG_RQ_BW_RD_ADD20 \
1267 #define PXP2_REG_RQ_BW_RD_ADD22 \
1269 #define PXP2_REG_RQ_BW_RD_ADD23 \
1271 #define PXP2_REG_RQ_BW_RD_ADD24 \
1273 #define PXP2_REG_RQ_BW_RD_ADD25 \
1275 #define PXP2_REG_RQ_BW_RD_ADD26 \
1277 #define PXP2_REG_RQ_BW_RD_ADD27 \
1279 #define PXP2_REG_RQ_BW_RD_ADD4 \
1281 #define PXP2_REG_RQ_BW_RD_ADD5 \
1283 #define PXP2_REG_RQ_BW_RD_L0 \
1285 #define PXP2_REG_RQ_BW_RD_L12 \
1287 #define PXP2_REG_RQ_BW_RD_L13 \
1289 #define PXP2_REG_RQ_BW_RD_L14 \
1291 #define PXP2_REG_RQ_BW_RD_L15 \
1293 #define PXP2_REG_RQ_BW_RD_L16 \
1295 #define PXP2_REG_RQ_BW_RD_L17 \
1297 #define PXP2_REG_RQ_BW_RD_L18 \
1299 #define PXP2_REG_RQ_BW_RD_L19 \
1301 #define PXP2_REG_RQ_BW_RD_L20 \
1303 #define PXP2_REG_RQ_BW_RD_L22 \
1305 #define PXP2_REG_RQ_BW_RD_L23 \
1307 #define PXP2_REG_RQ_BW_RD_L24 \
1309 #define PXP2_REG_RQ_BW_RD_L25 \
1311 #define PXP2_REG_RQ_BW_RD_L26 \
1313 #define PXP2_REG_RQ_BW_RD_L27 \
1315 #define PXP2_REG_RQ_BW_RD_L4 \
1317 #define PXP2_REG_RQ_BW_RD_L5 \
1319 #define PXP2_REG_RQ_BW_RD_UBOUND0 \
1321 #define PXP2_REG_RQ_BW_RD_UBOUND12 \
1323 #define PXP2_REG_RQ_BW_RD_UBOUND13 \
1325 #define PXP2_REG_RQ_BW_RD_UBOUND14 \
1327 #define PXP2_REG_RQ_BW_RD_UBOUND15 \
1329 #define PXP2_REG_RQ_BW_RD_UBOUND16 \
1331 #define PXP2_REG_RQ_BW_RD_UBOUND17 \
1333 #define PXP2_REG_RQ_BW_RD_UBOUND18 \
1335 #define PXP2_REG_RQ_BW_RD_UBOUND19 \
1337 #define PXP2_REG_RQ_BW_RD_UBOUND20 \
1339 #define PXP2_REG_RQ_BW_RD_UBOUND22 \
1341 #define PXP2_REG_RQ_BW_RD_UBOUND23 \
1343 #define PXP2_REG_RQ_BW_RD_UBOUND24 \
1345 #define PXP2_REG_RQ_BW_RD_UBOUND25 \
1347 #define PXP2_REG_RQ_BW_RD_UBOUND26 \
1349 #define PXP2_REG_RQ_BW_RD_UBOUND27 \
1351 #define PXP2_REG_RQ_BW_RD_UBOUND4 \
1353 #define PXP2_REG_RQ_BW_RD_UBOUND5 \
1355 #define PXP2_REG_RQ_BW_WR_ADD29 \
1357 #define PXP2_REG_RQ_BW_WR_ADD30 \
1359 #define PXP2_REG_RQ_BW_WR_L29 \
1361 #define PXP2_REG_RQ_BW_WR_L30 \
1363 #define PXP2_REG_RQ_BW_WR_UBOUND29 \
1365 #define PXP2_REG_RQ_BW_WR_UBOUND30 \
1367 #define PXP2_REG_RQ_CDU_ENDIAN_M \
1369 #define PXP2_REG_RQ_CDU_FIRST_ILT \
1371 #define PXP2_REG_RQ_CDU_LAST_ILT \
1373 #define PXP2_REG_RQ_CDU_P_SIZE \
1375 #define PXP2_REG_RQ_CFG_DONE \
1377 #define PXP2_REG_RQ_DBG_ENDIAN_M \
1379 #define PXP2_REG_RQ_DISABLE_INPUTS \
1381 #define PXP2_REG_RQ_DRAM_ALIGN \
1383 #define PXP2_REG_RQ_DRAM_ALIGN_RD \
1385 #define PXP2_REG_RQ_DRAM_ALIGN_SEL \
1387 #define PXP2_REG_RQ_HC_ENDIAN_M \
1389 #define PXP2_REG_RQ_ONCHIP_AT \
1391 #define PXP2_REG_RQ_ONCHIP_AT_B0 \
1393 #define PXP2_REG_RQ_PDR_LIMIT \
1395 #define PXP2_REG_RQ_QM_ENDIAN_M \
1397 #define PXP2_REG_RQ_QM_FIRST_ILT \
1399 #define PXP2_REG_RQ_QM_LAST_ILT \
1401 #define PXP2_REG_RQ_QM_P_SIZE \
1403 #define PXP2_REG_RQ_RBC_DONE \
1405 #define PXP2_REG_RQ_RD_MBS0 \
1407 #define PXP2_REG_RQ_RD_MBS1 \
1409 #define PXP2_REG_RQ_SRC_ENDIAN_M \
1411 #define PXP2_REG_RQ_SRC_FIRST_ILT \
1413 #define PXP2_REG_RQ_SRC_LAST_ILT \
1415 #define PXP2_REG_RQ_SRC_P_SIZE \
1417 #define PXP2_REG_RQ_TM_ENDIAN_M \
1419 #define PXP2_REG_RQ_TM_FIRST_ILT \
1421 #define PXP2_REG_RQ_TM_LAST_ILT \
1423 #define PXP2_REG_RQ_TM_P_SIZE \
1425 #define PXP2_REG_RQ_WR_MBS0 \
1427 #define PXP2_REG_RQ_WR_MBS1 \
1429 #define PXP2_REG_WR_CDU_MPS \
1431 #define PXP2_REG_WR_CSDM_MPS \
1433 #define PXP2_REG_WR_DBG_MPS \
1435 #define PXP2_REG_WR_DMAE_MPS \
1437 #define PXP2_REG_WR_HC_MPS \
1439 #define PXP2_REG_WR_QM_MPS \
1441 #define PXP2_REG_WR_SRC_MPS \
1443 #define PXP2_REG_WR_TM_MPS \
1445 #define PXP2_REG_WR_TSDM_MPS \
1447 #define PXP2_REG_WR_USDMDP_TH \
1449 #define PXP2_REG_WR_USDM_MPS \
1451 #define PXP2_REG_WR_XSDM_MPS \
1453 #define PXP_REG_HST_DISCARD_DOORBELLS \
1455 #define PXP_REG_HST_DISCARD_INTERNAL_WRITES \
1457 #define PXP_REG_HST_ZONE_PERMISSION_TABLE \
1459 #define PXP_REG_PXP_INT_MASK_0 \
1461 #define PXP_REG_PXP_INT_MASK_1 \
1463 #define PXP_REG_PXP_INT_STS_CLR_0 \
1465 #define PXP_REG_PXP_INT_STS_CLR_1 \
1467 #define PXP_REG_PXP_PRTY_MASK \
1469 #define PXP_REG_PXP_PRTY_STS_CLR \
1471 #define QM_REG_BASEADDR \
1473 #define QM_REG_BASEADDR_EXT_A \
1475 #define QM_REG_BYTECRDCMDQ_0 \
1477 #define QM_REG_CONNNUM_0 \
1479 #define QM_REG_PF_EN \
1481 #define QM_REG_PF_USG_CNT_0 \
1483 #define QM_REG_PTRTBL \
1485 #define QM_REG_PTRTBL_EXT_A \
1487 #define QM_REG_QM_INT_MASK \
1489 #define QM_REG_QM_PRTY_MASK \
1491 #define QM_REG_QM_PRTY_STS_CLR \
1493 #define QM_REG_QVOQIDX_0 \
1495 #define QM_REG_SOFT_RESET \
1497 #define QM_REG_VOQQMASK_0_LSB \
1499 #define SEM_FAST_REG_PARITY_RST \
1501 #define SRC_REG_COUNTFREE0 \
1503 #define SRC_REG_FIRSTFREE0 \
1505 #define SRC_REG_KEYSEARCH_0 \
1507 #define SRC_REG_KEYSEARCH_1 \
1509 #define SRC_REG_KEYSEARCH_2 \
1511 #define SRC_REG_KEYSEARCH_3 \
1513 #define SRC_REG_KEYSEARCH_4 \
1515 #define SRC_REG_KEYSEARCH_5 \
1517 #define SRC_REG_KEYSEARCH_6 \
1519 #define SRC_REG_KEYSEARCH_7 \
1521 #define SRC_REG_KEYSEARCH_8 \
1523 #define SRC_REG_KEYSEARCH_9 \
1525 #define SRC_REG_LASTFREE0 \
1527 #define SRC_REG_NUMBER_HASH_BITS0 \
1529 #define SRC_REG_SOFT_RST \
1531 #define SRC_REG_SRC_PRTY_MASK \
1533 #define SRC_REG_SRC_PRTY_STS_CLR \
1535 #define TCM_REG_PRS_IFEN \
1537 #define TCM_REG_TCM_INT_MASK \
1539 #define TCM_REG_TCM_PRTY_MASK \
1541 #define TCM_REG_TCM_PRTY_STS_CLR \
1543 #define TM_REG_EN_LINEAR0_TIMER \
1545 #define TM_REG_LIN0_MAX_ACTIVE_CID \
1547 #define TM_REG_LIN0_NUM_SCANS \
1549 #define TM_REG_LIN0_SCAN_ON \
1551 #define TM_REG_LIN0_SCAN_TIME \
1553 #define TM_REG_LIN0_VNIC_UC \
1555 #define TM_REG_TM_INT_MASK \
1557 #define TM_REG_TM_PRTY_MASK \
1559 #define TM_REG_TM_PRTY_STS_CLR \
1561 #define TSDM_REG_ENABLE_IN1 \
1563 #define TSDM_REG_TSDM_INT_MASK_0 \
1565 #define TSDM_REG_TSDM_INT_MASK_1 \
1567 #define TSDM_REG_TSDM_PRTY_MASK \
1569 #define TSDM_REG_TSDM_PRTY_STS_CLR \
1571 #define TSEM_REG_FAST_MEMORY \
1573 #define TSEM_REG_INT_TABLE \
1575 #define TSEM_REG_PASSIVE_BUFFER \
1577 #define TSEM_REG_PRAM \
1579 #define TSEM_REG_TSEM_INT_MASK_0 \
1581 #define TSEM_REG_TSEM_INT_MASK_1 \
1583 #define TSEM_REG_TSEM_PRTY_MASK_0 \
1585 #define TSEM_REG_TSEM_PRTY_MASK_1 \
1587 #define TSEM_REG_TSEM_PRTY_STS_CLR_0 \
1589 #define TSEM_REG_TSEM_PRTY_STS_CLR_1 \
1591 #define TSEM_REG_VFPF_ERR_NUM \
1593 #define UCM_REG_UCM_INT_MASK \
1595 #define UCM_REG_UCM_PRTY_MASK \
1597 #define UCM_REG_UCM_PRTY_STS_CLR \
1599 #define UMAC_COMMAND_CONFIG_REG_HD_ENA \
1601 #define UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE \
1603 #define UMAC_COMMAND_CONFIG_REG_LOOP_ENA \
1605 #define UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK \
1607 #define UMAC_COMMAND_CONFIG_REG_PAD_EN \
1609 #define UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE \
1611 #define UMAC_COMMAND_CONFIG_REG_PROMIS_EN \
1613 #define UMAC_COMMAND_CONFIG_REG_RX_ENA \
1615 #define UMAC_COMMAND_CONFIG_REG_SW_RESET \
1617 #define UMAC_COMMAND_CONFIG_REG_TX_ENA \
1619 #define UMAC_REG_COMMAND_CONFIG \
1621 #define UMAC_REG_EEE_WAKE_TIMER \
1623 #define UMAC_REG_MAC_ADDR0 \
1625 #define UMAC_REG_MAC_ADDR1 \
1627 #define UMAC_REG_MAXFR \
1629 #define UMAC_REG_UMAC_EEE_CTRL \
1631 #define UMAC_UMAC_EEE_CTRL_REG_EEE_EN \
1633 #define USDM_REG_USDM_INT_MASK_0 \
1635 #define USDM_REG_USDM_INT_MASK_1 \
1637 #define USDM_REG_USDM_PRTY_MASK \
1639 #define USDM_REG_USDM_PRTY_STS_CLR \
1641 #define USEM_REG_FAST_MEMORY \
1643 #define USEM_REG_INT_TABLE \
1645 #define USEM_REG_PASSIVE_BUFFER \
1647 #define USEM_REG_PRAM \
1649 #define USEM_REG_USEM_INT_MASK_0 \
1651 #define USEM_REG_USEM_INT_MASK_1 \
1653 #define USEM_REG_USEM_PRTY_MASK_0 \
1655 #define USEM_REG_USEM_PRTY_MASK_1 \
1657 #define USEM_REG_USEM_PRTY_STS_CLR_0 \
1659 #define USEM_REG_USEM_PRTY_STS_CLR_1 \
1661 #define USEM_REG_VFPF_ERR_NUM \
1663 #define VFC_MEMORIES_RST_REG_CAM_RST \
1665 #define VFC_MEMORIES_RST_REG_RAM_RST \
1667 #define VFC_REG_MEMORIES_RST \
1669 #define XCM_REG_XCM_INT_MASK \
1671 #define XCM_REG_XCM_PRTY_MASK \
1673 #define XCM_REG_XCM_PRTY_STS_CLR \
1675 #define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS \
1677 #define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS \
1679 #define XMAC_CTRL_REG_LINE_LOCAL_LPBK \
1681 #define XMAC_CTRL_REG_RX_EN \
1683 #define XMAC_CTRL_REG_SOFT_RESET \
1685 #define XMAC_CTRL_REG_TX_EN \
1687 #define XMAC_CTRL_REG_XLGMII_ALIGN_ENB \
1689 #define XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN \
1691 #define XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN \
1693 #define XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON \
1695 #define XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN \
1697 #define XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN \
1699 #define XMAC_PFC_CTRL_HI_REG_RX_PFC_EN \
1701 #define XMAC_PFC_CTRL_HI_REG_TX_PFC_EN \
1703 #define XMAC_REG_CLEAR_RX_LSS_STATUS \
1705 #define XMAC_REG_CTRL \
1707 #define XMAC_REG_CTRL_SA_HI \
1709 #define XMAC_REG_CTRL_SA_LO \
1711 #define XMAC_REG_EEE_CTRL \
1713 #define XMAC_REG_EEE_TIMERS_HI \
1715 #define XMAC_REG_PAUSE_CTRL \
1717 #define XMAC_REG_PFC_CTRL \
1719 #define XMAC_REG_PFC_CTRL_HI \
1721 #define XMAC_REG_RX_LSS_CTRL \
1723 #define XMAC_REG_RX_LSS_STATUS \
1725 #define XMAC_REG_RX_MAX_SIZE \
1727 #define XMAC_REG_TX_CTRL \
1729 #define XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE \
1731 #define XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE \
1733 #define XSDM_REG_OPERATION_GEN \
1735 #define XSDM_REG_XSDM_INT_MASK_0 \
1737 #define XSDM_REG_XSDM_INT_MASK_1 \
1739 #define XSDM_REG_XSDM_PRTY_MASK \
1741 #define XSDM_REG_XSDM_PRTY_STS_CLR \
1743 #define XSEM_REG_FAST_MEMORY \
1745 #define XSEM_REG_INT_TABLE \
1747 #define XSEM_REG_PASSIVE_BUFFER \
1749 #define XSEM_REG_PRAM \
1751 #define XSEM_REG_VFPF_ERR_NUM \
1753 #define XSEM_REG_XSEM_INT_MASK_0 \
1755 #define XSEM_REG_XSEM_INT_MASK_1 \
1757 #define XSEM_REG_XSEM_PRTY_MASK_0 \
1759 #define XSEM_REG_XSEM_PRTY_MASK_1 \
1761 #define XSEM_REG_XSEM_PRTY_STS_CLR_0 \
1763 #define XSEM_REG_XSEM_PRTY_STS_CLR_1 \
1765 #define MCPR_ACCESS_LOCK_LOCK (1L<<31)
1766 #define MCPR_IMC_COMMAND_ENABLE (1L<<31)
1767 #define MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT 16
1768 #define MCPR_IMC_COMMAND_OPERATION_BITSHIFT 28
1769 #define MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT 8
1770 #define MCPR_NVM_ACCESS_ENABLE_EN (1L<<0)
1771 #define MCPR_NVM_ACCESS_ENABLE_WR_EN (1L<<1)
1772 #define MCPR_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0)
1773 #define MCPR_NVM_CFG4_FLASH_SIZE (0x7L<<0)
1774 #define MCPR_NVM_COMMAND_DOIT (1L<<4)
1775 #define MCPR_NVM_COMMAND_DONE (1L<<3)
1776 #define MCPR_NVM_COMMAND_FIRST (1L<<7)
1777 #define MCPR_NVM_COMMAND_LAST (1L<<8)
1778 #define MCPR_NVM_COMMAND_WR (1L<<5)
1779 #define MCPR_NVM_SW_ARB_ARB_ARB1 (1L<<9)
1780 #define MCPR_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5)
1781 #define MCPR_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1)
1784 #define BIGMAC_REGISTER_BMAC_CONTROL (0x00<<3)
1785 #define BIGMAC_REGISTER_BMAC_XGXS_CONTROL (0x01<<3)
1786 #define BIGMAC_REGISTER_CNT_MAX_SIZE (0x05<<3)
1787 #define BIGMAC_REGISTER_RX_CONTROL (0x21<<3)
1788 #define BIGMAC_REGISTER_RX_LLFC_MSG_FLDS (0x46<<3)
1789 #define BIGMAC_REGISTER_RX_LSS_STATUS (0x43<<3)
1790 #define BIGMAC_REGISTER_RX_MAX_SIZE (0x23<<3)
1791 #define BIGMAC_REGISTER_RX_STAT_GR64 (0x26<<3)
1792 #define BIGMAC_REGISTER_RX_STAT_GRIPJ (0x42<<3)
1793 #define BIGMAC_REGISTER_TX_CONTROL (0x07<<3)
1794 #define BIGMAC_REGISTER_TX_MAX_SIZE (0x09<<3)
1795 #define BIGMAC_REGISTER_TX_PAUSE_THRESHOLD (0x0A<<3)
1796 #define BIGMAC_REGISTER_TX_SOURCE_ADDR (0x08<<3)
1797 #define BIGMAC_REGISTER_TX_STAT_GTBYT (0x20<<3)
1798 #define BIGMAC_REGISTER_TX_STAT_GTPKT (0x0C<<3)
1799 #define BIGMAC2_REGISTER_BMAC_CONTROL (0x00<<3)
1800 #define BIGMAC2_REGISTER_BMAC_XGXS_CONTROL (0x01<<3)
1801 #define BIGMAC2_REGISTER_CNT_MAX_SIZE (0x05<<3)
1802 #define BIGMAC2_REGISTER_PFC_CONTROL (0x06<<3)
1803 #define BIGMAC2_REGISTER_RX_CONTROL (0x3A<<3)
1804 #define BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS (0x62<<3)
1805 #define BIGMAC2_REGISTER_RX_LSS_STAT (0x3E<<3)
1806 #define BIGMAC2_REGISTER_RX_MAX_SIZE (0x3C<<3)
1807 #define BIGMAC2_REGISTER_RX_STAT_GR64 (0x40<<3)
1808 #define BIGMAC2_REGISTER_RX_STAT_GRIPJ (0x5f<<3)
1809 #define BIGMAC2_REGISTER_TX_CONTROL (0x1C<<3)
1810 #define BIGMAC2_REGISTER_TX_MAX_SIZE (0x1E<<3)
1811 #define BIGMAC2_REGISTER_TX_PAUSE_CONTROL (0x20<<3)
1812 #define BIGMAC2_REGISTER_TX_SOURCE_ADDR (0x1D<<3)
1813 #define BIGMAC2_REGISTER_TX_STAT_GTBYT (0x39<<3)
1814 #define BIGMAC2_REGISTER_TX_STAT_GTPOK (0x22<<3)
1817 #define EMAC_LED_1000MB_OVERRIDE (1L<<1)
1818 #define EMAC_LED_100MB_OVERRIDE (1L<<2)
1819 #define EMAC_LED_10MB_OVERRIDE (1L<<3)
1820 #define EMAC_LED_OVERRIDE (1L<<0)
1821 #define EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26)
1822 #define EMAC_MDIO_COMM_COMMAND_READ_22 (2L<<26)
1823 #define EMAC_MDIO_COMM_COMMAND_READ_45 (3L<<26)
1824 #define EMAC_MDIO_COMM_COMMAND_WRITE_22 (1L<<26)
1825 #define EMAC_MDIO_COMM_COMMAND_WRITE_45 (1L<<26)
1826 #define EMAC_MDIO_COMM_DATA (0xffffL<<0)
1827 #define EMAC_MDIO_COMM_START_BUSY (1L<<29)
1828 #define EMAC_MDIO_MODE_AUTO_POLL (1L<<4)
1829 #define EMAC_MDIO_MODE_CLAUSE_45 (1L<<31)
1830 #define EMAC_MDIO_MODE_CLOCK_CNT (0x3ffL<<16)
1831 #define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT 16
1832 #define EMAC_MDIO_STATUS_10MB (1L<<1)
1833 #define EMAC_MODE_25G_MODE (1L<<5)
1834 #define EMAC_MODE_HALF_DUPLEX (1L<<1)
1835 #define EMAC_MODE_PORT_GMII (2L<<2)
1836 #define EMAC_MODE_PORT_MII (1L<<2)
1837 #define EMAC_MODE_PORT_MII_10M (3L<<2)
1838 #define EMAC_MODE_RESET (1L<<0)
1839 #define EMAC_REG_EMAC_LED 0xc
1840 #define EMAC_REG_EMAC_MAC_MATCH 0x10
1841 #define EMAC_REG_EMAC_MDIO_COMM 0xac
1842 #define EMAC_REG_EMAC_MDIO_MODE 0xb4
1843 #define EMAC_REG_EMAC_MDIO_STATUS 0xb0
1844 #define EMAC_REG_EMAC_MODE 0x0
1845 #define EMAC_REG_EMAC_RX_MODE 0xc8
1846 #define EMAC_REG_EMAC_RX_MTU_SIZE 0x9c
1847 #define EMAC_REG_EMAC_RX_STAT_AC 0x180
1848 #define EMAC_REG_EMAC_RX_STAT_AC_28 0x1f4
1849 #define EMAC_REG_EMAC_RX_STAT_AC_COUNT 23
1850 #define EMAC_REG_EMAC_TX_MODE 0xbc
1851 #define EMAC_REG_EMAC_TX_STAT_AC 0x280
1852 #define EMAC_REG_EMAC_TX_STAT_AC_COUNT 22
1853 #define EMAC_REG_RX_PFC_MODE 0x320
1854 #define EMAC_REG_RX_PFC_MODE_PRIORITIES (1L<<2)
1855 #define EMAC_REG_RX_PFC_MODE_RX_EN (1L<<1)
1856 #define EMAC_REG_RX_PFC_MODE_TX_EN (1L<<0)
1857 #define EMAC_REG_RX_PFC_PARAM 0x324
1858 #define EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT 0
1859 #define EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT 16
1860 #define EMAC_REG_RX_PFC_STATS_XOFF_RCVD 0x328
1861 #define EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT (0xffff<<0)
1862 #define EMAC_REG_RX_PFC_STATS_XOFF_SENT 0x330
1863 #define EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT (0xffff<<0)
1864 #define EMAC_REG_RX_PFC_STATS_XON_RCVD 0x32c
1865 #define EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT (0xffff<<0)
1866 #define EMAC_REG_RX_PFC_STATS_XON_SENT 0x334
1867 #define EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT (0xffff<<0)
1868 #define EMAC_RX_MODE_FLOW_EN (1L<<2)
1869 #define EMAC_RX_MODE_KEEP_MAC_CONTROL (1L<<3)
1870 #define EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10)
1871 #define EMAC_RX_MODE_PROMISCUOUS (1L<<8)
1872 #define EMAC_RX_MODE_RESET (1L<<0)
1873 #define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31)
1874 #define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3)
1875 #define EMAC_TX_MODE_FLOW_EN (1L<<4)
1876 #define EMAC_TX_MODE_RESET (1L<<0)
1879 #define MISC_REGISTERS_GPIO_0 0
1880 #define MISC_REGISTERS_GPIO_1 1
1881 #define MISC_REGISTERS_GPIO_2 2
1882 #define MISC_REGISTERS_GPIO_3 3
1883 #define MISC_REGISTERS_GPIO_CLR_POS 16
1884 #define MISC_REGISTERS_GPIO_FLOAT (0xffL<<24)
1885 #define MISC_REGISTERS_GPIO_FLOAT_POS 24
1886 #define MISC_REGISTERS_GPIO_HIGH 1
1887 #define MISC_REGISTERS_GPIO_INPUT_HI_Z 2
1888 #define MISC_REGISTERS_GPIO_INT_CLR_POS 24
1889 #define MISC_REGISTERS_GPIO_INT_OUTPUT_CLR 0
1890 #define MISC_REGISTERS_GPIO_INT_OUTPUT_SET 1
1891 #define MISC_REGISTERS_GPIO_INT_SET_POS 16
1892 #define MISC_REGISTERS_GPIO_LOW 0
1893 #define MISC_REGISTERS_GPIO_OUTPUT_HIGH 1
1894 #define MISC_REGISTERS_GPIO_OUTPUT_LOW 0
1895 #define MISC_REGISTERS_GPIO_PORT_SHIFT 4
1896 #define MISC_REGISTERS_GPIO_SET_POS 8
1897 #define MISC_REGISTERS_RESET_REG_1_CLEAR 0x588
1898 #define MISC_REGISTERS_RESET_REG_1_RST_BRB1 (0x1<<0)
1899 #define MISC_REGISTERS_RESET_REG_1_RST_DORQ \
1901 #define MISC_REGISTERS_RESET_REG_1_RST_HC \
1903 #define MISC_REGISTERS_RESET_REG_1_RST_PXP \
1905 #define MISC_REGISTERS_RESET_REG_1_RST_PXPV \
1907 #define MISC_REGISTERS_RESET_REG_1_RST_QM \
1909 #define MISC_REGISTERS_RESET_REG_1_SET 0x584
1910 #define MISC_REGISTERS_RESET_REG_2_CLEAR 0x598
1911 #define MISC_REGISTERS_RESET_REG_2_MSTAT0 \
1913 #define MISC_REGISTERS_RESET_REG_2_MSTAT1 \
1915 #define MISC_REGISTERS_RESET_REG_2_PGLC \
1917 #define MISC_REGISTERS_RESET_REG_2_RST_ATC \
1919 #define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1<<0)
1920 #define MISC_REGISTERS_RESET_REG_2_RST_BMAC1 (0x1<<1)
1921 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC0 (0x1<<2)
1922 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE \
1924 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC1 (0x1<<3)
1925 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE \
1927 #define MISC_REGISTERS_RESET_REG_2_RST_GRC (0x1<<4)
1928 #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B (0x1<<6)
1929 #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE (0x1<<8)
1930 #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU (0x1<<7)
1931 #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE (0x1<<5)
1932 #define MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE \
1934 #define MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO \
1936 #define MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR \
1938 #define MISC_REGISTERS_RESET_REG_2_RST_RBCN (0x1<<9)
1939 #define MISC_REGISTERS_RESET_REG_2_SET 0x594
1940 #define MISC_REGISTERS_RESET_REG_2_UMAC0 \
1942 #define MISC_REGISTERS_RESET_REG_2_UMAC1 \
1944 #define MISC_REGISTERS_RESET_REG_2_XMAC \
1946 #define MISC_REGISTERS_RESET_REG_2_XMAC_SOFT \
1948 #define MISC_REGISTERS_RESET_REG_3_CLEAR 0x5a8
1949 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ (0x1<<1)
1950 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN (0x1<<2)
1951 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD (0x1<<3)
1952 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW (0x1<<0)
1953 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ (0x1<<5)
1954 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN (0x1<<6)
1955 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD (0x1<<7)
1956 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW (0x1<<4)
1957 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB (0x1<<8)
1958 #define MISC_REGISTERS_RESET_REG_3_SET 0x5a4
1959 #define MISC_SPIO_CLR_POS 16
1960 #define MISC_SPIO_FLOAT (0xffL<<24)
1961 #define MISC_SPIO_FLOAT_POS 24
1962 #define MISC_SPIO_INPUT_HI_Z 2
1963 #define MISC_SPIO_INT_OLD_SET_POS 16
1964 #define MISC_SPIO_OUTPUT_HIGH 1
1965 #define MISC_SPIO_OUTPUT_LOW 0
1966 #define MISC_SPIO_SET_POS 8
1967 #define MISC_SPIO_SPIO4 0x10
1968 #define MISC_SPIO_SPIO5 0x20
1969 #define HW_LOCK_MAX_RESOURCE_VALUE 31
1970 #define HW_LOCK_RESOURCE_DRV_FLAGS 10
1971 #define HW_LOCK_RESOURCE_GPIO 1
1972 #define HW_LOCK_RESOURCE_NVRAM 12
1973 #define HW_LOCK_RESOURCE_PORT0_ATT_MASK 3
1974 #define HW_LOCK_RESOURCE_RECOVERY_LEADER_0 8
1975 #define HW_LOCK_RESOURCE_RECOVERY_LEADER_1 9
1976 #define HW_LOCK_RESOURCE_RECOVERY_REG 11
1977 #define HW_LOCK_RESOURCE_RESET 5
1978 #define HW_LOCK_RESOURCE_SPIO 2
1981 #define AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT (0x1<<4)
1982 #define AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR (0x1<<5)
1983 #define AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT (0x1<<19)
1984 #define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (0x1<<18)
1985 #define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (0x1<<31)
1986 #define AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR (0x1<<30)
1987 #define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (0x1<<9)
1988 #define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR (0x1<<8)
1989 #define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT (0x1<<7)
1990 #define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR (0x1<<6)
1991 #define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT (0x1<<29)
1992 #define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR (0x1<<28)
1993 #define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT (0x1<<1)
1994 #define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR (0x1<<0)
1995 #define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR (0x1<<18)
1996 #define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT (0x1<<11)
1997 #define AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR (0x1<<10)
1998 #define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT (0x1<<13)
1999 #define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR (0x1<<12)
2000 #define AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 (0x1<<2)
2001 #define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR (0x1<<12)
2002 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY (0x1<<28)
2003 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY (0x1UL<<31)
2004 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY (0x1<<29)
2005 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY (0x1<<30)
2006 #define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT (0x1<<15)
2007 #define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR (0x1<<14)
2008 #define AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR (0x1<<14)
2009 #define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR (0x1<<20)
2010 #define AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT (0x1UL<<31)
2011 #define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR (0x1<<30)
2012 #define AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR (0x1<<0)
2013 #define AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT (0x1<<2)
2014 #define AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR (0x1<<3)
2015 #define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT (0x1<<5)
2016 #define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR (0x1<<4)
2017 #define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT (0x1<<3)
2018 #define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR (0x1<<2)
2019 #define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT (0x1<<3)
2020 #define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR (0x1<<2)
2021 #define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR (0x1<<22)
2022 #define AEU_INPUTS_ATTN_BITS_SPIO5 (0x1<<15)
2023 #define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT (0x1<<27)
2024 #define AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR (0x1<<26)
2025 #define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT (0x1<<5)
2026 #define AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR (0x1<<4)
2027 #define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT (0x1<<25)
2028 #define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR (0x1<<24)
2029 #define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT (0x1<<29)
2030 #define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR (0x1<<28)
2031 #define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT (0x1<<23)
2032 #define AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR (0x1<<22)
2033 #define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT (0x1<<27)
2034 #define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR (0x1<<26)
2035 #define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT (0x1<<21)
2036 #define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR (0x1<<20)
2037 #define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT (0x1<<25)
2038 #define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR (0x1<<24)
2039 #define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR (0x1<<16)
2040 #define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT (0x1<<9)
2041 #define AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR (0x1<<8)
2042 #define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT (0x1<<7)
2043 #define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR (0x1<<6)
2044 #define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT (0x1<<11)
2045 #define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR (0x1<<10)
2046 #define HW_PRTY_ASSERT_SET_0 \
2047 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR |\
2048 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR |\
2049 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR |\
2050 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
2051 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\
2052 AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\
2053 AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR)
2054 #define HW_PRTY_ASSERT_SET_1 \
2055 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\
2056 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR |\
2057 AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\
2058 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR |\
2059 AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\
2060 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR |\
2061 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
2062 AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\
2063 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
2064 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR |\
2065 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR |\
2066 AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\
2067 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR |\
2068 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR |\
2069 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\
2070 AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR)
2071 #define HW_PRTY_ASSERT_SET_2 \
2072 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR |\
2073 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR |\
2074 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
2075 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR |\
2076 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR |\
2077 AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\
2078 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR |\
2079 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
2080 #define HW_PRTY_ASSERT_SET_3 \
2081 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
2082 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
2083 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \
2084 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
2085 #define HW_PRTY_ASSERT_SET_4 \
2086 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |\
2087 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)
2088 #define HW_INTERRUT_ASSERT_SET_0 \
2089 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT |\
2090 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT |\
2091 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT |\
2092 AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT |\
2093 AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT)
2094 #define HW_INTERRUT_ASSERT_SET_1 \
2095 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT |\
2096 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT |\
2097 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT |\
2098 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT |\
2099 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT |\
2100 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT |\
2101 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT |\
2102 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT |\
2103 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT |\
2104 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT |\
2105 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
2106 #define HW_INTERRUT_ASSERT_SET_2 \
2107 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT |\
2108 AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT |\
2109 AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT |\
2110 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT |\
2111 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT |\
2112 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
2113 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
2116 #define RESERVED_GENERAL_ATTENTION_BIT_0 0
2118 #define EVEREST_GEN_ATTN_IN_USE_MASK 0x7ffe0
2119 #define EVEREST_LATCHED_ATTN_IN_USE_MASK 0xffe00000
2121 #define RESERVED_GENERAL_ATTENTION_BIT_6 6
2122 #define RESERVED_GENERAL_ATTENTION_BIT_7 7
2123 #define RESERVED_GENERAL_ATTENTION_BIT_8 8
2124 #define RESERVED_GENERAL_ATTENTION_BIT_9 9
2125 #define RESERVED_GENERAL_ATTENTION_BIT_10 10
2126 #define RESERVED_GENERAL_ATTENTION_BIT_11 11
2127 #define RESERVED_GENERAL_ATTENTION_BIT_12 12
2128 #define RESERVED_GENERAL_ATTENTION_BIT_13 13
2129 #define RESERVED_GENERAL_ATTENTION_BIT_14 14
2130 #define RESERVED_GENERAL_ATTENTION_BIT_15 15
2131 #define RESERVED_GENERAL_ATTENTION_BIT_16 16
2132 #define RESERVED_GENERAL_ATTENTION_BIT_17 17
2133 #define RESERVED_GENERAL_ATTENTION_BIT_18 18
2134 #define RESERVED_GENERAL_ATTENTION_BIT_19 19
2135 #define RESERVED_GENERAL_ATTENTION_BIT_20 20
2136 #define RESERVED_GENERAL_ATTENTION_BIT_21 21
2138 /* storm asserts attention bits */
2139 #define TSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_7
2140 #define USTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_8
2141 #define CSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_9
2142 #define XSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_10
2144 /* mcp error attention bit */
2145 #define MCP_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_11
2147 /*E1H NIG status sync attention mapped to group 4-7*/
2148 #define LINK_SYNC_ATTENTION_BIT_FUNC_0 RESERVED_GENERAL_ATTENTION_BIT_12
2149 #define LINK_SYNC_ATTENTION_BIT_FUNC_1 RESERVED_GENERAL_ATTENTION_BIT_13
2150 #define LINK_SYNC_ATTENTION_BIT_FUNC_2 RESERVED_GENERAL_ATTENTION_BIT_14
2151 #define LINK_SYNC_ATTENTION_BIT_FUNC_3 RESERVED_GENERAL_ATTENTION_BIT_15
2152 #define LINK_SYNC_ATTENTION_BIT_FUNC_4 RESERVED_GENERAL_ATTENTION_BIT_16
2153 #define LINK_SYNC_ATTENTION_BIT_FUNC_5 RESERVED_GENERAL_ATTENTION_BIT_17
2154 #define LINK_SYNC_ATTENTION_BIT_FUNC_6 RESERVED_GENERAL_ATTENTION_BIT_18
2155 #define LINK_SYNC_ATTENTION_BIT_FUNC_7 RESERVED_GENERAL_ATTENTION_BIT_19
2157 /* Used For Error Recovery: changing this will require more \
2158 changes in code that assume
2159 * error recovery uses general attn bit20 ! */
2160 #define ERROR_RECOVERY_ATTENTION_BIT \
2161 RESERVED_GENERAL_ATTENTION_BIT_20
2162 #define RESERVED_ATTENTION_BIT \
2163 RESERVED_GENERAL_ATTENTION_BIT_21
2165 #define LATCHED_ATTN_RBCR 23
2166 #define LATCHED_ATTN_RBCT 24
2167 #define LATCHED_ATTN_RBCN 25
2168 #define LATCHED_ATTN_RBCU 26
2169 #define LATCHED_ATTN_RBCP 27
2170 #define LATCHED_ATTN_TIMEOUT_GRC 28
2171 #define LATCHED_ATTN_RSVD_GRC 29
2172 #define LATCHED_ATTN_ROM_PARITY_MCP 30
2173 #define LATCHED_ATTN_UM_RX_PARITY_MCP 31
2174 #define LATCHED_ATTN_UM_TX_PARITY_MCP 32
2175 #define LATCHED_ATTN_SCPAD_PARITY_MCP 33
2177 #define GENERAL_ATTEN_WORD(atten_name) ((94 + atten_name) / 32)
2178 #define GENERAL_ATTEN_OFFSET(atten_name) (1UL << ((94 + atten_name) % 32))
2182 * This file defines GRC base address for every block.
2183 * This file is included by chipsim, asm microcode and cpp microcode.
2184 * These values are used in Design.xml on regBase attribute
2185 * Use the base with the generated offsets of specific registers.
2188 #define GRCBASE_PXPCS 0x000000
2189 #define GRCBASE_PCICONFIG 0x002000
2190 #define GRCBASE_PCIREG 0x002400
2191 #define GRCBASE_EMAC0 0x008000
2192 #define GRCBASE_EMAC1 0x008400
2193 #define GRCBASE_DBU 0x008800
2194 #define GRCBASE_PGLUE_B 0x009000
2195 #define GRCBASE_MISC 0x00A000
2196 #define GRCBASE_DBG 0x00C000
2197 #define GRCBASE_NIG 0x010000
2198 #define GRCBASE_XCM 0x020000
2199 #define GRCBASE_PRS 0x040000
2200 #define GRCBASE_SRCH 0x040400
2201 #define GRCBASE_TSDM 0x042000
2202 #define GRCBASE_TCM 0x050000
2203 #define GRCBASE_BRB1 0x060000
2204 #define GRCBASE_MCP 0x080000
2205 #define GRCBASE_UPB 0x0C1000
2206 #define GRCBASE_CSDM 0x0C2000
2207 #define GRCBASE_USDM 0x0C4000
2208 #define GRCBASE_CCM 0x0D0000
2209 #define GRCBASE_UCM 0x0E0000
2210 #define GRCBASE_CDU 0x101000
2211 #define GRCBASE_DMAE 0x102000
2212 #define GRCBASE_PXP 0x103000
2213 #define GRCBASE_CFC 0x104000
2214 #define GRCBASE_HC 0x108000
2215 #define GRCBASE_ATC 0x110000
2216 #define GRCBASE_PXP2 0x120000
2217 #define GRCBASE_IGU 0x130000
2218 #define GRCBASE_PBF 0x140000
2219 #define GRCBASE_UMAC0 0x160000
2220 #define GRCBASE_UMAC1 0x160400
2221 #define GRCBASE_XPB 0x161000
2222 #define GRCBASE_MSTAT0 0x162000
2223 #define GRCBASE_MSTAT1 0x162800
2224 #define GRCBASE_XMAC0 0x163000
2225 #define GRCBASE_XMAC1 0x163800
2226 #define GRCBASE_TIMERS 0x164000
2227 #define GRCBASE_XSDM 0x166000
2228 #define GRCBASE_QM 0x168000
2229 #define GRCBASE_QM_4PORT 0x168000
2230 #define GRCBASE_DQ 0x170000
2231 #define GRCBASE_TSEM 0x180000
2232 #define GRCBASE_CSEM 0x200000
2233 #define GRCBASE_XSEM 0x280000
2234 #define GRCBASE_XSEM_4PORT 0x280000
2235 #define GRCBASE_USEM 0x300000
2236 #define GRCBASE_MCP_A 0x380000
2237 #define GRCBASE_MISC_AEU GRCBASE_MISC
2238 #define GRCBASE_Tstorm GRCBASE_TSEM
2239 #define GRCBASE_Cstorm GRCBASE_CSEM
2240 #define GRCBASE_Xstorm GRCBASE_XSEM
2241 #define GRCBASE_Ustorm GRCBASE_USEM
2244 /* offset of configuration space in the pci core register */
2245 #define PCICFG_OFFSET 0x2000
2246 #define PCICFG_VENDOR_ID_OFFSET 0x00
2247 #define PCICFG_DEVICE_ID_OFFSET 0x02
2248 #define PCICFG_COMMAND_OFFSET 0x04
2249 #define PCICFG_COMMAND_IO_SPACE (1<<0)
2250 #define PCICFG_COMMAND_MEM_SPACE (1<<1)
2251 #define PCICFG_COMMAND_BUS_MASTER (1<<2)
2252 #define PCICFG_COMMAND_SPECIAL_CYCLES (1<<3)
2253 #define PCICFG_COMMAND_MWI_CYCLES (1<<4)
2254 #define PCICFG_COMMAND_VGA_SNOOP (1<<5)
2255 #define PCICFG_COMMAND_PERR_ENA (1<<6)
2256 #define PCICFG_COMMAND_STEPPING (1<<7)
2257 #define PCICFG_COMMAND_SERR_ENA (1<<8)
2258 #define PCICFG_COMMAND_FAST_B2B (1<<9)
2259 #define PCICFG_COMMAND_INT_DISABLE (1<<10)
2260 #define PCICFG_COMMAND_RESERVED (0x1f<<11)
2261 #define PCICFG_STATUS_OFFSET 0x06
2262 #define PCICFG_REVISION_ID_OFFSET 0x08
2263 #define PCICFG_REVESION_ID_MASK 0xff
2264 #define PCICFG_REVESION_ID_ERROR_VAL 0xff
2265 #define PCICFG_CACHE_LINE_SIZE 0x0c
2266 #define PCICFG_LATENCY_TIMER 0x0d
2267 #define PCICFG_HEADER_TYPE 0x0e
2268 #define PCICFG_HEADER_TYPE_NORMAL 0
2269 #define PCICFG_HEADER_TYPE_BRIDGE 1
2270 #define PCICFG_HEADER_TYPE_CARDBUS 2
2271 #define PCICFG_BAR_1_LOW 0x10
2272 #define PCICFG_BAR_1_HIGH 0x14
2273 #define PCICFG_BAR_2_LOW 0x18
2274 #define PCICFG_BAR_2_HIGH 0x1c
2275 #define PCICFG_BAR_3_LOW 0x20
2276 #define PCICFG_BAR_3_HIGH 0x24
2277 #define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2c
2278 #define PCICFG_SUBSYSTEM_ID_OFFSET 0x2e
2279 #define PCICFG_INT_LINE 0x3c
2280 #define PCICFG_INT_PIN 0x3d
2281 #define PCICFG_PM_CAPABILITY 0x48
2282 #define PCICFG_PM_CAPABILITY_VERSION (0x3<<16)
2283 #define PCICFG_PM_CAPABILITY_CLOCK (1<<19)
2284 #define PCICFG_PM_CAPABILITY_RESERVED (1<<20)
2285 #define PCICFG_PM_CAPABILITY_DSI (1<<21)
2286 #define PCICFG_PM_CAPABILITY_AUX_CURRENT (0x7<<22)
2287 #define PCICFG_PM_CAPABILITY_D1_SUPPORT (1<<25)
2288 #define PCICFG_PM_CAPABILITY_D2_SUPPORT (1<<26)
2289 #define PCICFG_PM_CAPABILITY_PME_IN_D0 (1<<27)
2290 #define PCICFG_PM_CAPABILITY_PME_IN_D1 (1<<28)
2291 #define PCICFG_PM_CAPABILITY_PME_IN_D2 (1<<29)
2292 #define PCICFG_PM_CAPABILITY_PME_IN_D3_HOT (1<<30)
2293 #define PCICFG_PM_CAPABILITY_PME_IN_D3_COLD (1<<31)
2294 #define PCICFG_PM_CSR_OFFSET 0x4c
2295 #define PCICFG_PM_CSR_STATE (0x3<<0)
2296 #define PCICFG_PM_CSR_PME_ENABLE (1<<8)
2297 #define PCICFG_PM_CSR_PME_STATUS (1<<15)
2298 #define PCICFG_VPD_FLAG_ADDR_OFFSET 0x50
2299 #define PCICFG_VPD_DATA_OFFSET 0x54
2300 #define PCICFG_MSI_CAP_ID_OFFSET 0x58
2301 #define PCICFG_MSI_CONTROL_ENABLE (0x1<<16)
2302 #define PCICFG_MSI_CONTROL_MCAP (0x7<<17)
2303 #define PCICFG_MSI_CONTROL_MENA (0x7<<20)
2304 #define PCICFG_MSI_CONTROL_64_BIT_ADDR_CAP (0x1<<23)
2305 #define PCICFG_MSI_CONTROL_MSI_PVMASK_CAPABLE (0x1<<24)
2306 #define PCICFG_MSI_ADDR_LOW_OFFSET 0x5c
2307 #define PCICFG_MSI_ADDR_HIGH_OFFSET 0x60
2308 #define PCICFG_MSI_DATA_OFFSET 0x64
2309 #define PCICFG_GRC_ADDRESS 0x78
2310 #define PCICFG_GRC_DATA 0x80
2311 #define PCICFG_ME_REGISTER 0x98
2312 #define PCICFG_MSIX_CAP_ID_OFFSET 0xa0
2313 #define PCICFG_MSIX_CONTROL_TABLE_SIZE (0x7ff<<16)
2314 #define PCICFG_MSIX_CONTROL_RESERVED (0x7<<27)
2315 #define PCICFG_MSIX_CONTROL_FUNC_MASK (0x1<<30)
2316 #define PCICFG_MSIX_CONTROL_MSIX_ENABLE (0x1<<31)
2318 #define PCICFG_DEVICE_CONTROL 0xb4
2319 #define PCICFG_DEVICE_CONTROL_NP_TRANSACTION_PEND (1<<21)
2320 #define PCICFG_DEVICE_STATUS 0xb6
2321 #define PCICFG_DEVICE_STATUS_CORR_ERR_DET (1<<0)
2322 #define PCICFG_DEVICE_STATUS_NON_FATAL_ERR_DET (1<<1)
2323 #define PCICFG_DEVICE_STATUS_FATAL_ERR_DET (1<<2)
2324 #define PCICFG_DEVICE_STATUS_UNSUP_REQ_DET (1<<3)
2325 #define PCICFG_DEVICE_STATUS_AUX_PWR_DET (1<<4)
2326 #define PCICFG_DEVICE_STATUS_NO_PEND (1<<5)
2327 #define PCICFG_LINK_CONTROL 0xbc
2330 /* config_2 offset */
2331 #define GRC_CONFIG_2_SIZE_REG 0x408
2332 #define PCI_CONFIG_2_BAR1_SIZE (0xfL<<0)
2333 #define PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0)
2334 #define PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0)
2335 #define PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0)
2336 #define PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0)
2337 #define PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0)
2338 #define PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0)
2339 #define PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0)
2340 #define PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0)
2341 #define PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0)
2342 #define PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0)
2343 #define PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0)
2344 #define PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0)
2345 #define PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0)
2346 #define PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0)
2347 #define PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0)
2348 #define PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0)
2349 #define PCI_CONFIG_2_BAR1_64ENA (1L<<4)
2350 #define PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5)
2351 #define PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6)
2352 #define PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7)
2353 #define PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8)
2354 #define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8)
2355 #define PCI_CONFIG_2_EXP_ROM_SIZE_2K (1L<<8)
2356 #define PCI_CONFIG_2_EXP_ROM_SIZE_4K (2L<<8)
2357 #define PCI_CONFIG_2_EXP_ROM_SIZE_8K (3L<<8)
2358 #define PCI_CONFIG_2_EXP_ROM_SIZE_16K (4L<<8)
2359 #define PCI_CONFIG_2_EXP_ROM_SIZE_32K (5L<<8)
2360 #define PCI_CONFIG_2_EXP_ROM_SIZE_64K (6L<<8)
2361 #define PCI_CONFIG_2_EXP_ROM_SIZE_128K (7L<<8)
2362 #define PCI_CONFIG_2_EXP_ROM_SIZE_256K (8L<<8)
2363 #define PCI_CONFIG_2_EXP_ROM_SIZE_512K (9L<<8)
2364 #define PCI_CONFIG_2_EXP_ROM_SIZE_1M (10L<<8)
2365 #define PCI_CONFIG_2_EXP_ROM_SIZE_2M (11L<<8)
2366 #define PCI_CONFIG_2_EXP_ROM_SIZE_4M (12L<<8)
2367 #define PCI_CONFIG_2_EXP_ROM_SIZE_8M (13L<<8)
2368 #define PCI_CONFIG_2_EXP_ROM_SIZE_16M (14L<<8)
2369 #define PCI_CONFIG_2_EXP_ROM_SIZE_32M (15L<<8)
2370 #define PCI_CONFIG_2_BAR_PREFETCH (1L<<16)
2371 #define PCI_CONFIG_2_RESERVED0 (0x7fffL<<17)
2373 /* config_3 offset */
2374 #define GRC_CONFIG_3_SIZE_REG 0x40c
2375 #define PCI_CONFIG_3_STICKY_BYTE (0xffL<<0)
2376 #define PCI_CONFIG_3_FORCE_PME (1L<<24)
2377 #define PCI_CONFIG_3_PME_STATUS (1L<<25)
2378 #define PCI_CONFIG_3_PME_ENABLE (1L<<26)
2379 #define PCI_CONFIG_3_PM_STATE (0x3L<<27)
2380 #define PCI_CONFIG_3_VAUX_PRESET (1L<<30)
2381 #define PCI_CONFIG_3_PCI_POWER (1L<<31)
2383 #define GRC_REG_DEVICE_CONTROL 0x4d8
2384 #define PCIE_SRIOV_DISABLE_IN_PROGRESS \
2385 (1 << 29) /*When VF Enable is cleared(after it was previously set),
2386 this register will read a value of 1, indicating that all the
2387 VFs that belong to this PF should be flushed.
2388 Software should clear this bit within 1 second of VF Enable
2389 being set by writing a 1 to it, so that VFs are visible to the system again.
2391 #define PCIE_FLR_IN_PROGRESS \
2392 (1 << 27) /*When FLR is initiated, this register will read a \
2393 value of 1 indicating that the
2394 Function is in FLR state. Func can be brought out of FLR state either by
2395 writing 1 to this register (at least 50 ms after FLR was initiated),
2396 or it can also be cleared automatically after 55 ms if auto_clear bit
2397 in private reg space is set. This bit also exists in VF register space
2400 #define GRC_BAR2_CONFIG 0x4e0
2401 #define PCI_CONFIG_2_BAR2_SIZE (0xfL<<0)
2402 #define PCI_CONFIG_2_BAR2_SIZE_DISABLED (0L<<0)
2403 #define PCI_CONFIG_2_BAR2_SIZE_64K (1L<<0)
2404 #define PCI_CONFIG_2_BAR2_SIZE_128K (2L<<0)
2405 #define PCI_CONFIG_2_BAR2_SIZE_256K (3L<<0)
2406 #define PCI_CONFIG_2_BAR2_SIZE_512K (4L<<0)
2407 #define PCI_CONFIG_2_BAR2_SIZE_1M (5L<<0)
2408 #define PCI_CONFIG_2_BAR2_SIZE_2M (6L<<0)
2409 #define PCI_CONFIG_2_BAR2_SIZE_4M (7L<<0)
2410 #define PCI_CONFIG_2_BAR2_SIZE_8M (8L<<0)
2411 #define PCI_CONFIG_2_BAR2_SIZE_16M (9L<<0)
2412 #define PCI_CONFIG_2_BAR2_SIZE_32M (10L<<0)
2413 #define PCI_CONFIG_2_BAR2_SIZE_64M (11L<<0)
2414 #define PCI_CONFIG_2_BAR2_SIZE_128M (12L<<0)
2415 #define PCI_CONFIG_2_BAR2_SIZE_256M (13L<<0)
2416 #define PCI_CONFIG_2_BAR2_SIZE_512M (14L<<0)
2417 #define PCI_CONFIG_2_BAR2_SIZE_1G (15L<<0)
2418 #define PCI_CONFIG_2_BAR2_64ENA (1L<<4)
2420 #define GRC_BAR3_CONFIG 0x4f4
2421 #define PCI_CONFIG_2_BAR3_SIZE (0xfL<<0)
2422 #define PCI_CONFIG_2_BAR3_SIZE_DISABLED (0L<<0)
2423 #define PCI_CONFIG_2_BAR3_SIZE_64K (1L<<0)
2424 #define PCI_CONFIG_2_BAR3_SIZE_128K (2L<<0)
2425 #define PCI_CONFIG_2_BAR3_SIZE_256K (3L<<0)
2426 #define PCI_CONFIG_2_BAR3_SIZE_512K (4L<<0)
2427 #define PCI_CONFIG_2_BAR3_SIZE_1M (5L<<0)
2428 #define PCI_CONFIG_2_BAR3_SIZE_2M (6L<<0)
2429 #define PCI_CONFIG_2_BAR3_SIZE_4M (7L<<0)
2430 #define PCI_CONFIG_2_BAR3_SIZE_8M (8L<<0)
2431 #define PCI_CONFIG_2_BAR3_SIZE_16M (9L<<0)
2432 #define PCI_CONFIG_2_BAR3_SIZE_32M (10L<<0)
2433 #define PCI_CONFIG_2_BAR3_SIZE_64M (11L<<0)
2434 #define PCI_CONFIG_2_BAR3_SIZE_128M (12L<<0)
2435 #define PCI_CONFIG_2_BAR3_SIZE_256M (13L<<0)
2436 #define PCI_CONFIG_2_BAR3_SIZE_512M (14L<<0)
2437 #define PCI_CONFIG_2_BAR3_SIZE_1G (15L<<0)
2438 #define PCI_CONFIG_2_BAR3_64ENA (1L<<4)
2440 #define PCI_PM_DATA_A 0x410
2441 #define PCI_PM_DATA_B 0x414
2442 #define PCI_ID_VAL1 0x434
2443 #define PCI_ID_VAL2 0x438
2444 #define PCI_ID_VAL3 0x43c
2445 #define PCI_ID_VAL3_REVISION_ID_ERROR (0xffL<<24)
2448 #define GRC_CONFIG_REG_VF_BAR_REG_1 0x608
2449 #define GRC_CONFIG_REG_VF_BAR_REG_BAR0_SIZE 0xf
2451 #define GRC_CONFIG_REG_VF_MSIX_CONTROL 0x61C
2452 #define GRC_CR_VF_MSIX_CTRL_VF_MSIX_TBL_SIZE_MASK \
2453 0x3F /*This field resides in VF only and does not exist in PF.
2454 This register controls the read value of the MSIX_CONTROL[10:0] register
2455 in the VF configuration space. A value of "00000000011" indicates
2456 a table size of 4. The value is controlled by IOV_MSIX_TBL_SIZ
2457 define in version.v */
2459 #define GRC_CONFIG_REG_PF_INIT_VF 0x624
2460 #define GRC_CR_PF_INIT_VF_PF_FIRST_VF_NUM_MASK \
2461 0xf /*First VF_NUM for PF is encoded in this register.
2462 The number of VFs assigned to a PF is assumed to be a multiple of 8.
2463 Software should program these bits based on Total Number of VFs \
2464 programmed for each PF.
2465 Since registers from 0x000-0x7ff are spilt across functions, each PF will have
2466 the same location for the same 4 bits*/
2468 #define PXPCS_TL_CONTROL_5 0x814
2469 #define PXPCS_TL_CONTROL_5_UNKNOWNTYPE_ERR_ATTN (1 << 29) /*WC*/
2470 #define PXPCS_TL_CONTROL_5_BOUNDARY4K_ERR_ATTN (1 << 28) /*WC*/
2471 #define PXPCS_TL_CONTROL_5_MRRS_ERR_ATTN (1 << 27) /*WC*/
2472 #define PXPCS_TL_CONTROL_5_MPS_ERR_ATTN (1 << 26) /*WC*/
2473 #define PXPCS_TL_CONTROL_5_TTX_BRIDGE_FORWARD_ERR (1 << 25) /*WC*/
2474 #define PXPCS_TL_CONTROL_5_TTX_TXINTF_OVERFLOW (1 << 24) /*WC*/
2475 #define PXPCS_TL_CONTROL_5_PHY_ERR_ATTN (1 << 23) /*RO*/
2476 #define PXPCS_TL_CONTROL_5_DL_ERR_ATTN (1 << 22) /*RO*/
2477 #define PXPCS_TL_CONTROL_5_TTX_ERR_NP_TAG_IN_USE (1 << 21) /*WC*/
2478 #define PXPCS_TL_CONTROL_5_TRX_ERR_UNEXP_RTAG (1 << 20) /*WC*/
2479 #define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT1 (1 << 19) /*WC*/
2480 #define PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 (1 << 18) /*WC*/
2481 #define PXPCS_TL_CONTROL_5_ERR_ECRC1 (1 << 17) /*WC*/
2482 #define PXPCS_TL_CONTROL_5_ERR_MALF_TLP1 (1 << 16) /*WC*/
2483 #define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW1 (1 << 15) /*WC*/
2484 #define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL1 (1 << 14) /*WC*/
2485 #define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT1 (1 << 13) /*WC*/
2486 #define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT1 (1 << 12) /*WC*/
2487 #define PXPCS_TL_CONTROL_5_ERR_FC_PRTL1 (1 << 11) /*WC*/
2488 #define PXPCS_TL_CONTROL_5_ERR_PSND_TLP1 (1 << 10) /*WC*/
2489 #define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT (1 << 9) /*WC*/
2490 #define PXPCS_TL_CONTROL_5_ERR_UNSPPORT (1 << 8) /*WC*/
2491 #define PXPCS_TL_CONTROL_5_ERR_ECRC (1 << 7) /*WC*/
2492 #define PXPCS_TL_CONTROL_5_ERR_MALF_TLP (1 << 6) /*WC*/
2493 #define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW (1 << 5) /*WC*/
2494 #define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL (1 << 4) /*WC*/
2495 #define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT (1 << 3) /*WC*/
2496 #define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT (1 << 2) /*WC*/
2497 #define PXPCS_TL_CONTROL_5_ERR_FC_PRTL (1 << 1) /*WC*/
2498 #define PXPCS_TL_CONTROL_5_ERR_PSND_TLP (1 << 0) /*WC*/
2501 #define PXPCS_TL_FUNC345_STAT 0x854
2502 #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT4 (1 << 29) /* WC */
2503 #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 \
2504 (1 << 28) /* Unsupported Request Error Status in function4, if \
2505 set, generate pcie_err_attn output when this error is seen. WC */
2506 #define PXPCS_TL_FUNC345_STAT_ERR_ECRC4 \
2507 (1 << 27) /* ECRC Error TLP Status Status in function 4, if set, \
2508 generate pcie_err_attn output when this error is seen.. WC */
2509 #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP4 \
2510 (1 << 26) /* Malformed TLP Status Status in function 4, if set, \
2511 generate pcie_err_attn output when this error is seen.. WC */
2512 #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW4 \
2513 (1 << 25) /* Receiver Overflow Status Status in function 4, if \
2514 set, generate pcie_err_attn output when this error is seen.. WC \
2516 #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL4 \
2517 (1 << 24) /* Unexpected Completion Status Status in function 4, \
2518 if set, generate pcie_err_attn output when this error is seen. WC \
2520 #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT4 \
2521 (1 << 23) /* Receive UR Statusin function 4. If set, generate \
2522 pcie_err_attn output when this error is seen. WC */
2523 #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT4 \
2524 (1 << 22) /* Completer Timeout Status Status in function 4, if \
2525 set, generate pcie_err_attn output when this error is seen. WC */
2526 #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL4 \
2527 (1 << 21) /* Flow Control Protocol Error Status Status in \
2528 function 4, if set, generate pcie_err_attn output when this error \
2530 #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP4 \
2531 (1 << 20) /* Poisoned Error Status Status in function 4, if set, \
2532 generate pcie_err_attn output when this error is seen.. WC */
2533 #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT3 (1 << 19) /* WC */
2534 #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 \
2535 (1 << 18) /* Unsupported Request Error Status in function3, if \
2536 set, generate pcie_err_attn output when this error is seen. WC */
2537 #define PXPCS_TL_FUNC345_STAT_ERR_ECRC3 \
2538 (1 << 17) /* ECRC Error TLP Status Status in function 3, if set, \
2539 generate pcie_err_attn output when this error is seen.. WC */
2540 #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP3 \
2541 (1 << 16) /* Malformed TLP Status Status in function 3, if set, \
2542 generate pcie_err_attn output when this error is seen.. WC */
2543 #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW3 \
2544 (1 << 15) /* Receiver Overflow Status Status in function 3, if \
2545 set, generate pcie_err_attn output when this error is seen.. WC \
2547 #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL3 \
2548 (1 << 14) /* Unexpected Completion Status Status in function 3, \
2549 if set, generate pcie_err_attn output when this error is seen. WC \
2551 #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT3 \
2552 (1 << 13) /* Receive UR Statusin function 3. If set, generate \
2553 pcie_err_attn output when this error is seen. WC */
2554 #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT3 \
2555 (1 << 12) /* Completer Timeout Status Status in function 3, if \
2556 set, generate pcie_err_attn output when this error is seen. WC */
2557 #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL3 \
2558 (1 << 11) /* Flow Control Protocol Error Status Status in \
2559 function 3, if set, generate pcie_err_attn output when this error \
2561 #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP3 \
2562 (1 << 10) /* Poisoned Error Status Status in function 3, if set, \
2563 generate pcie_err_attn output when this error is seen.. WC */
2564 #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT2 (1 << 9) /* WC */
2565 #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2 \
2566 (1 << 8) /* Unsupported Request Error Status for Function 2, if \
2567 set, generate pcie_err_attn output when this error is seen. WC */
2568 #define PXPCS_TL_FUNC345_STAT_ERR_ECRC2 \
2569 (1 << 7) /* ECRC Error TLP Status Status for Function 2, if set, \
2570 generate pcie_err_attn output when this error is seen.. WC */
2571 #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP2 \
2572 (1 << 6) /* Malformed TLP Status Status for Function 2, if set, \
2573 generate pcie_err_attn output when this error is seen.. WC */
2574 #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW2 \
2575 (1 << 5) /* Receiver Overflow Status Status for Function 2, if \
2576 set, generate pcie_err_attn output when this error is seen.. WC \
2578 #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL2 \
2579 (1 << 4) /* Unexpected Completion Status Status for Function 2, \
2580 if set, generate pcie_err_attn output when this error is seen. WC \
2582 #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT2 \
2583 (1 << 3) /* Receive UR Statusfor Function 2. If set, generate \
2584 pcie_err_attn output when this error is seen. WC */
2585 #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT2 \
2586 (1 << 2) /* Completer Timeout Status Status for Function 2, if \
2587 set, generate pcie_err_attn output when this error is seen. WC */
2588 #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL2 \
2589 (1 << 1) /* Flow Control Protocol Error Status Status for \
2590 Function 2, if set, generate pcie_err_attn output when this error \
2592 #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP2 \
2593 (1 << 0) /* Poisoned Error Status Status for Function 2, if set, \
2594 generate pcie_err_attn output when this error is seen.. WC */
2597 #define PXPCS_TL_FUNC678_STAT 0x85C
2598 #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT7 (1 << 29) /* WC */
2599 #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 \
2600 (1 << 28) /* Unsupported Request Error Status in function7, if \
2601 set, generate pcie_err_attn output when this error is seen. WC */
2602 #define PXPCS_TL_FUNC678_STAT_ERR_ECRC7 \
2603 (1 << 27) /* ECRC Error TLP Status Status in function 7, if set, \
2604 generate pcie_err_attn output when this error is seen.. WC */
2605 #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP7 \
2606 (1 << 26) /* Malformed TLP Status Status in function 7, if set, \
2607 generate pcie_err_attn output when this error is seen.. WC */
2608 #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW7 \
2609 (1 << 25) /* Receiver Overflow Status Status in function 7, if \
2610 set, generate pcie_err_attn output when this error is seen.. WC \
2612 #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL7 \
2613 (1 << 24) /* Unexpected Completion Status Status in function 7, \
2614 if set, generate pcie_err_attn output when this error is seen. WC \
2616 #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT7 \
2617 (1 << 23) /* Receive UR Statusin function 7. If set, generate \
2618 pcie_err_attn output when this error is seen. WC */
2619 #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT7 \
2620 (1 << 22) /* Completer Timeout Status Status in function 7, if \
2621 set, generate pcie_err_attn output when this error is seen. WC */
2622 #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL7 \
2623 (1 << 21) /* Flow Control Protocol Error Status Status in \
2624 function 7, if set, generate pcie_err_attn output when this error \
2626 #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP7 \
2627 (1 << 20) /* Poisoned Error Status Status in function 7, if set, \
2628 generate pcie_err_attn output when this error is seen.. WC */
2629 #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT6 (1 << 19) /* WC */
2630 #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 \
2631 (1 << 18) /* Unsupported Request Error Status in function6, if \
2632 set, generate pcie_err_attn output when this error is seen. WC */
2633 #define PXPCS_TL_FUNC678_STAT_ERR_ECRC6 \
2634 (1 << 17) /* ECRC Error TLP Status Status in function 6, if set, \
2635 generate pcie_err_attn output when this error is seen.. WC */
2636 #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP6 \
2637 (1 << 16) /* Malformed TLP Status Status in function 6, if set, \
2638 generate pcie_err_attn output when this error is seen.. WC */
2639 #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW6 \
2640 (1 << 15) /* Receiver Overflow Status Status in function 6, if \
2641 set, generate pcie_err_attn output when this error is seen.. WC \
2643 #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL6 \
2644 (1 << 14) /* Unexpected Completion Status Status in function 6, \
2645 if set, generate pcie_err_attn output when this error is seen. WC \
2647 #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT6 \
2648 (1 << 13) /* Receive UR Statusin function 6. If set, generate \
2649 pcie_err_attn output when this error is seen. WC */
2650 #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT6 \
2651 (1 << 12) /* Completer Timeout Status Status in function 6, if \
2652 set, generate pcie_err_attn output when this error is seen. WC */
2653 #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL6 \
2654 (1 << 11) /* Flow Control Protocol Error Status Status in \
2655 function 6, if set, generate pcie_err_attn output when this error \
2657 #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP6 \
2658 (1 << 10) /* Poisoned Error Status Status in function 6, if set, \
2659 generate pcie_err_attn output when this error is seen.. WC */
2660 #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT5 (1 << 9) /* WC */
2661 #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5 \
2662 (1 << 8) /* Unsupported Request Error Status for Function 5, if \
2663 set, generate pcie_err_attn output when this error is seen. WC */
2664 #define PXPCS_TL_FUNC678_STAT_ERR_ECRC5 \
2665 (1 << 7) /* ECRC Error TLP Status Status for Function 5, if set, \
2666 generate pcie_err_attn output when this error is seen.. WC */
2667 #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP5 \
2668 (1 << 6) /* Malformed TLP Status Status for Function 5, if set, \
2669 generate pcie_err_attn output when this error is seen.. WC */
2670 #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW5 \
2671 (1 << 5) /* Receiver Overflow Status Status for Function 5, if \
2672 set, generate pcie_err_attn output when this error is seen.. WC \
2674 #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL5 \
2675 (1 << 4) /* Unexpected Completion Status Status for Function 5, \
2676 if set, generate pcie_err_attn output when this error is seen. WC \
2678 #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT5 \
2679 (1 << 3) /* Receive UR Statusfor Function 5. If set, generate \
2680 pcie_err_attn output when this error is seen. WC */
2681 #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT5 \
2682 (1 << 2) /* Completer Timeout Status Status for Function 5, if \
2683 set, generate pcie_err_attn output when this error is seen. WC */
2684 #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL5 \
2685 (1 << 1) /* Flow Control Protocol Error Status Status for \
2686 Function 5, if set, generate pcie_err_attn output when this error \
2688 #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP5 \
2689 (1 << 0) /* Poisoned Error Status Status for Function 5, if set, \
2690 generate pcie_err_attn output when this error is seen.. WC */
2693 #define BAR_USTRORM_INTMEM 0x400000
2694 #define BAR_CSTRORM_INTMEM 0x410000
2695 #define BAR_XSTRORM_INTMEM 0x420000
2696 #define BAR_TSTRORM_INTMEM 0x430000
2698 /* for accessing the IGU in case of status block ACK */
2699 #define BAR_IGU_INTMEM 0x440000
2701 #define BAR_DOORBELL_OFFSET 0x800000
2703 #define BAR_ME_REGISTER 0x450000
2704 #define ME_REG_PF_NUM_SHIFT 0
2705 #define ME_REG_PF_NUM \
2706 (7L<<ME_REG_PF_NUM_SHIFT) /* Relative PF Num */
2707 #define ME_REG_VF_VALID (1<<8)
2708 #define ME_REG_VF_NUM_SHIFT 9
2709 #define ME_REG_VF_NUM_MASK (0x3f<<ME_REG_VF_NUM_SHIFT)
2710 #define VF_ID(x) ((x & ME_REG_VF_NUM_MASK) >> ME_REG_VF_NUM_SHIFT)
2711 #define ME_REG_VF_ERR (0x1<<3)
2712 #define ME_REG_ABS_PF_NUM_SHIFT 16
2713 #define ME_REG_ABS_PF_NUM \
2714 (7L<<ME_REG_ABS_PF_NUM_SHIFT) /* Absolute PF Num */
2717 #define PXP_VF_ADRR_NUM_QUEUES 136
2718 #define PXP_ADDR_QUEUE_SIZE 32
2719 #define PXP_ADDR_REG_SIZE 512
2722 #define PXP_VF_ADDR_IGU_START 0
2723 #define PXP_VF_ADDR_IGU_SIZE (0x3000)
2724 #define PXP_VF_ADDR_IGU_END \
2725 ((PXP_VF_ADDR_IGU_START) + (PXP_VF_ADDR_IGU_SIZE) - 1)
2727 #define PXP_VF_ADDR_USDM_QUEUES_START 0x3000
2728 #define PXP_VF_ADDR_USDM_QUEUES_SIZE \
2729 (PXP_VF_ADRR_NUM_QUEUES * PXP_ADDR_QUEUE_SIZE)
2730 #define PXP_VF_ADDR_USDM_QUEUES_END \
2731 ((PXP_VF_ADDR_USDM_QUEUES_START) + (PXP_VF_ADDR_USDM_QUEUES_SIZE) - 1)
2733 #define PXP_VF_ADDR_CSDM_QUEUES_START 0x4100
2734 #define PXP_VF_ADDR_CSDM_QUEUES_SIZE \
2735 (PXP_VF_ADRR_NUM_QUEUES * PXP_ADDR_QUEUE_SIZE)
2736 #define PXP_VF_ADDR_CSDM_QUEUES_END \
2737 ((PXP_VF_ADDR_CSDM_QUEUES_START) + (PXP_VF_ADDR_CSDM_QUEUES_SIZE) - 1)
2739 #define PXP_VF_ADDR_XSDM_QUEUES_START 0x5200
2740 #define PXP_VF_ADDR_XSDM_QUEUES_SIZE \
2741 (PXP_VF_ADRR_NUM_QUEUES * PXP_ADDR_QUEUE_SIZE)
2742 #define PXP_VF_ADDR_XSDM_QUEUES_END \
2743 ((PXP_VF_ADDR_XSDM_QUEUES_START) + (PXP_VF_ADDR_XSDM_QUEUES_SIZE) - 1)
2745 #define PXP_VF_ADDR_TSDM_QUEUES_START 0x6300
2746 #define PXP_VF_ADDR_TSDM_QUEUES_SIZE \
2747 (PXP_VF_ADRR_NUM_QUEUES * PXP_ADDR_QUEUE_SIZE)
2748 #define PXP_VF_ADDR_TSDM_QUEUES_END \
2749 ((PXP_VF_ADDR_TSDM_QUEUES_START) + (PXP_VF_ADDR_TSDM_QUEUES_SIZE) - 1)
2751 #define PXP_VF_ADDR_USDM_GLOBAL_START 0x7400
2752 #define PXP_VF_ADDR_USDM_GLOBAL_SIZE (PXP_ADDR_REG_SIZE)
2753 #define PXP_VF_ADDR_USDM_GLOBAL_END \
2754 ((PXP_VF_ADDR_USDM_GLOBAL_START) + (PXP_VF_ADDR_USDM_GLOBAL_SIZE) - 1)
2756 #define PXP_VF_ADDR_CSDM_GLOBAL_START 0x7600
2757 #define PXP_VF_ADDR_CSDM_GLOBAL_SIZE (PXP_ADDR_REG_SIZE)
2758 #define PXP_VF_ADDR_CSDM_GLOBAL_END \
2759 ((PXP_VF_ADDR_CSDM_GLOBAL_START) + (PXP_VF_ADDR_CSDM_GLOBAL_SIZE) - 1)
2761 #define PXP_VF_ADDR_XSDM_GLOBAL_START 0x7800
2762 #define PXP_VF_ADDR_XSDM_GLOBAL_SIZE (PXP_ADDR_REG_SIZE)
2763 #define PXP_VF_ADDR_XSDM_GLOBAL_END \
2764 ((PXP_VF_ADDR_XSDM_GLOBAL_START) + (PXP_VF_ADDR_XSDM_GLOBAL_SIZE) - 1)
2766 #define PXP_VF_ADDR_TSDM_GLOBAL_START 0x7a00
2767 #define PXP_VF_ADDR_TSDM_GLOBAL_SIZE (PXP_ADDR_REG_SIZE)
2768 #define PXP_VF_ADDR_TSDM_GLOBAL_END \
2769 ((PXP_VF_ADDR_TSDM_GLOBAL_START) + (PXP_VF_ADDR_TSDM_GLOBAL_SIZE) - 1)
2771 #define PXP_VF_ADDR_DB_START 0x7c00
2772 #define PXP_VF_ADDR_DB_SIZE (0x200)
2773 #define PXP_VF_ADDR_DB_END \
2774 ((PXP_VF_ADDR_DB_START) + (PXP_VF_ADDR_DB_SIZE) - 1)
2776 #define PXP_VF_ADDR_GRC_START 0x7e00
2777 #define PXP_VF_ADDR_GRC_SIZE (0x200)
2778 #define PXP_VF_ADDR_GRC_END \
2779 ((PXP_VF_ADDR_GRC_START) + (PXP_VF_ADDR_GRC_SIZE) - 1)
2781 #define PXP_VF_ADDR_DORQ_START (0x0)
2782 #define PXP_VF_ADDR_DORQ_SIZE (0xffffffff)
2783 #define PXP_VF_ADDR_DORQ_END (0xffffffff)
2785 #define PXP_BAR_GRC 0
2786 #define PXP_BAR_TSDM 0
2787 #define PXP_BAR_USDM 0
2788 #define PXP_BAR_XSDM 0
2789 #define PXP_BAR_CSDM 0
2790 #define PXP_BAR_IGU 0
2791 #define PXP_BAR_DQ 1
2793 #define PXP_VF_BAR_IGU 0
2794 #define PXP_VF_BAR_USDM_QUEUES 0
2795 #define PXP_VF_BAR_TSDM_QUEUES 0
2796 #define PXP_VF_BAR_XSDM_QUEUES 0
2797 #define PXP_VF_BAR_CSDM_QUEUES 0
2798 #define PXP_VF_BAR_USDM_GLOBAL 0
2799 #define PXP_VF_BAR_TSDM_GLOBAL 0
2800 #define PXP_VF_BAR_XSDM_GLOBAL 0
2801 #define PXP_VF_BAR_CSDM_GLOBAL 0
2802 #define PXP_VF_BAR_DB 0
2803 #define PXP_VF_BAR_GRC 0
2804 #define PXP_VF_BAR_DORQ 1
2806 /* PCI CAPABILITIES*/
2808 #define PCI_CAP_PCIE 0x10 /*PCIe capability ID*/
2810 #define PCIE_DEV_CAPS 0x04
2812 #define PCIE_DEV_CTRL 0x08
2813 #define PCIE_DEV_CTRL_FLR 0x8000;
2815 #define PCIE_DEV_STATUS 0x0A
2817 #define PCI_CAP_MSIX 0x11 /*MSI-X capability ID*/
2818 #define PCI_MSIX_CONTROL_SHIFT 16
2819 #define PCI_MSIX_TABLE_SIZE_MASK 0x07FF
2820 #define PCI_MSIX_TABLE_ENABLE_MASK 0x8000
2823 #define MDIO_REG_BANK_CL73_IEEEB0 0x0
2824 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0
2825 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200
2826 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000
2827 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000
2829 #define MDIO_REG_BANK_CL73_IEEEB1 0x10
2830 #define MDIO_CL73_IEEEB1_AN_ADV1 0x00
2831 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE 0x0400
2832 #define MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC 0x0800
2833 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH 0x0C00
2834 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK 0x0C00
2835 #define MDIO_CL73_IEEEB1_AN_ADV2 0x01
2836 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000
2837 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020
2838 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040
2839 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080
2840 #define MDIO_CL73_IEEEB1_AN_LP_ADV1 0x03
2841 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE 0x0400
2842 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC 0x0800
2843 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH 0x0C00
2844 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK 0x0C00
2845 #define MDIO_CL73_IEEEB1_AN_LP_ADV2 0x04
2847 #define MDIO_REG_BANK_RX0 0x80b0
2848 #define MDIO_RX0_RX_STATUS 0x10
2849 #define MDIO_RX0_RX_STATUS_SIGDET 0x8000
2850 #define MDIO_RX0_RX_STATUS_RX_SEQ_DONE 0x1000
2851 #define MDIO_RX0_RX_EQ_BOOST 0x1c
2852 #define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
2853 #define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10
2855 #define MDIO_REG_BANK_RX1 0x80c0
2856 #define MDIO_RX1_RX_EQ_BOOST 0x1c
2857 #define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
2858 #define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10
2860 #define MDIO_REG_BANK_RX2 0x80d0
2861 #define MDIO_RX2_RX_EQ_BOOST 0x1c
2862 #define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
2863 #define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10
2865 #define MDIO_REG_BANK_RX3 0x80e0
2866 #define MDIO_RX3_RX_EQ_BOOST 0x1c
2867 #define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
2868 #define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10
2870 #define MDIO_REG_BANK_RX_ALL 0x80f0
2871 #define MDIO_RX_ALL_RX_EQ_BOOST 0x1c
2872 #define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
2873 #define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10
2875 #define MDIO_REG_BANK_TX0 0x8060
2876 #define MDIO_TX0_TX_DRIVER 0x17
2877 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
2878 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
2879 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
2880 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
2881 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
2882 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
2883 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
2884 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
2885 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
2887 #define MDIO_REG_BANK_TX1 0x8070
2888 #define MDIO_TX1_TX_DRIVER 0x17
2889 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
2890 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
2891 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
2892 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
2893 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
2894 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
2895 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
2896 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
2897 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
2899 #define MDIO_REG_BANK_TX2 0x8080
2900 #define MDIO_TX2_TX_DRIVER 0x17
2901 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
2902 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
2903 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
2904 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
2905 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
2906 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
2907 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
2908 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
2909 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
2911 #define MDIO_REG_BANK_TX3 0x8090
2912 #define MDIO_TX3_TX_DRIVER 0x17
2913 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
2914 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
2915 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
2916 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
2917 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
2918 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
2919 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
2920 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
2921 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
2923 #define MDIO_REG_BANK_XGXS_BLOCK0 0x8000
2924 #define MDIO_BLOCK0_XGXS_CONTROL 0x10
2926 #define MDIO_REG_BANK_XGXS_BLOCK1 0x8010
2927 #define MDIO_BLOCK1_LANE_CTRL0 0x15
2928 #define MDIO_BLOCK1_LANE_CTRL1 0x16
2929 #define MDIO_BLOCK1_LANE_CTRL2 0x17
2930 #define MDIO_BLOCK1_LANE_PRBS 0x19
2932 #define MDIO_REG_BANK_XGXS_BLOCK2 0x8100
2933 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10
2934 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000
2935 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000
2936 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11
2937 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000
2938 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14
2939 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001
2940 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010
2941 #define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15
2943 #define MDIO_REG_BANK_GP_STATUS 0x8120
2944 #define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B
2945 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001
2946 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002
2947 #define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004
2948 #define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008
2949 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010
2950 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020
2951 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040
2952 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080
2953 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00
2954 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000
2955 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100
2956 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200
2957 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300
2958 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400
2959 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500
2960 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600
2961 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700
2962 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800
2963 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900
2964 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00
2965 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00
2966 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00
2967 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00
2968 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00
2969 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR 0x0F00
2970 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI 0x1B00
2971 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS 0x1E00
2972 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI 0x1F00
2973 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2 0x3900
2976 #define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130
2977 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS 0x10
2978 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK 0x8000
2979 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11
2980 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1
2981 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13
2982 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT (0xb71<<1)
2984 #define MDIO_REG_BANK_SERDES_DIGITAL 0x8300
2985 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 0x10
2986 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x0001
2987 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF 0x0002
2988 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN 0x0004
2989 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x0008
2990 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET 0x0010
2991 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE 0x0020
2992 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 0x11
2993 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001
2994 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040
2995 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14
2996 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SGMII 0x0001
2997 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_LINK 0x0002
2998 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004
2999 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018
3000 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3
3001 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G 0x0018
3002 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010
3003 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008
3004 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000
3005 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2 0x15
3006 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED 0x0002
3007 #define MDIO_SERDES_DIGITAL_MISC1 0x18
3008 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000
3009 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000
3010 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M 0x2000
3011 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M 0x4000
3012 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M 0x6000
3013 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M 0x8000
3014 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL 0x0010
3015 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK 0x000f
3016 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G 0x0000
3017 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G 0x0001
3018 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G 0x0002
3019 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG 0x0003
3020 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 0x0004
3021 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G 0x0005
3022 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G 0x0006
3023 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G 0x0007
3024 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G 0x0008
3025 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G 0x0009
3027 #define MDIO_REG_BANK_OVER_1G 0x8320
3028 #define MDIO_OVER_1G_DIGCTL_3_4 0x14
3029 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK 0xffe0
3030 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT 5
3031 #define MDIO_OVER_1G_UP1 0x19
3032 #define MDIO_OVER_1G_UP1_2_5G 0x0001
3033 #define MDIO_OVER_1G_UP1_5G 0x0002
3034 #define MDIO_OVER_1G_UP1_6G 0x0004
3035 #define MDIO_OVER_1G_UP1_10G 0x0010
3036 #define MDIO_OVER_1G_UP1_10GH 0x0008
3037 #define MDIO_OVER_1G_UP1_12G 0x0020
3038 #define MDIO_OVER_1G_UP1_12_5G 0x0040
3039 #define MDIO_OVER_1G_UP1_13G 0x0080
3040 #define MDIO_OVER_1G_UP1_15G 0x0100
3041 #define MDIO_OVER_1G_UP1_16G 0x0200
3042 #define MDIO_OVER_1G_UP2 0x1A
3043 #define MDIO_OVER_1G_UP2_IPREDRIVER_MASK 0x0007
3044 #define MDIO_OVER_1G_UP2_IDRIVER_MASK 0x0038
3045 #define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK 0x03C0
3046 #define MDIO_OVER_1G_UP3 0x1B
3047 #define MDIO_OVER_1G_UP3_HIGIG2 0x0001
3048 #define MDIO_OVER_1G_LP_UP1 0x1C
3049 #define MDIO_OVER_1G_LP_UP2 0x1D
3050 #define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK 0x03ff
3051 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK 0x0780
3052 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 7
3053 #define MDIO_OVER_1G_LP_UP3 0x1E
3055 #define MDIO_REG_BANK_REMOTE_PHY 0x8330
3056 #define MDIO_REMOTE_PHY_MISC_RX_STATUS 0x10
3057 #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG 0x0010
3058 #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG 0x0600
3060 #define MDIO_REG_BANK_BAM_NEXT_PAGE 0x8350
3061 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10
3062 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001
3063 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002
3065 #define MDIO_REG_BANK_CL73_USERB0 0x8370
3066 #define MDIO_CL73_USERB0_CL73_UCTRL 0x10
3067 #define MDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL 0x0002
3068 #define MDIO_CL73_USERB0_CL73_USTAT1 0x11
3069 #define MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK 0x0100
3070 #define MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37 0x0400
3071 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12
3072 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000
3073 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000
3074 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000
3075 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14
3076 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001
3078 #define MDIO_REG_BANK_AER_BLOCK 0xFFD0
3079 #define MDIO_AER_BLOCK_AER_REG 0x1E
3081 #define MDIO_REG_BANK_COMBO_IEEE0 0xFFE0
3082 #define MDIO_COMBO_IEEE0_MII_CONTROL 0x10
3083 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040
3084 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000
3085 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000
3086 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040
3087 #define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100
3088 #define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200
3089 #define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000
3090 #define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000
3091 #define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000
3092 #define MDIO_COMBO_IEEE0_MII_STATUS 0x11
3093 #define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004
3094 #define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020
3095 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV 0x14
3096 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020
3097 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040
3098 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180
3099 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000
3100 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080
3101 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100
3102 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180
3103 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000
3104 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15
3105 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000
3106 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000
3107 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180
3108 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE 0x0000
3109 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH 0x0180
3110 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040
3111 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020
3112 /*WhenthelinkpartnerisinSGMIImode(bit0=1), then
3113 bit15=link, bit12=duplex, bits11:10=speed, bit14=acknowledge.
3114 Theotherbitsarereservedandshouldbezero*/
3115 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001
3118 #define MDIO_PMA_DEVAD 0x1
3120 #define MDIO_PMA_REG_CTRL 0x0
3121 #define MDIO_PMA_REG_STATUS 0x1
3122 #define MDIO_PMA_REG_10G_CTRL2 0x7
3123 #define MDIO_PMA_REG_TX_DISABLE 0x0009
3124 #define MDIO_PMA_REG_RX_SD 0xa
3126 #define MDIO_PMA_REG_BNX2X_CTRL 0x0096
3127 #define MDIO_PMA_REG_FEC_CTRL 0x00ab
3128 #define MDIO_PMA_LASI_RXCTRL 0x9000
3129 #define MDIO_PMA_LASI_TXCTRL 0x9001
3130 #define MDIO_PMA_LASI_CTRL 0x9002
3131 #define MDIO_PMA_LASI_RXSTAT 0x9003
3132 #define MDIO_PMA_LASI_TXSTAT 0x9004
3133 #define MDIO_PMA_LASI_STAT 0x9005
3134 #define MDIO_PMA_REG_PHY_IDENTIFIER 0xc800
3135 #define MDIO_PMA_REG_DIGITAL_CTRL 0xc808
3136 #define MDIO_PMA_REG_DIGITAL_STATUS 0xc809
3137 #define MDIO_PMA_REG_TX_POWER_DOWN 0xca02
3138 #define MDIO_PMA_REG_CMU_PLL_BYPASS 0xca09
3139 #define MDIO_PMA_REG_MISC_CTRL 0xca0a
3140 #define MDIO_PMA_REG_GEN_CTRL 0xca10
3141 #define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188
3142 #define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a
3143 #define MDIO_PMA_REG_M8051_MSGIN_REG 0xca12
3144 #define MDIO_PMA_REG_M8051_MSGOUT_REG 0xca13
3145 #define MDIO_PMA_REG_ROM_VER1 0xca19
3146 #define MDIO_PMA_REG_ROM_VER2 0xca1a
3147 #define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b
3148 #define MDIO_PMA_REG_PLL_BANDWIDTH 0xca1d
3149 #define MDIO_PMA_REG_PLL_CTRL 0xca1e
3150 #define MDIO_PMA_REG_MISC_CTRL0 0xca23
3151 #define MDIO_PMA_REG_LRM_MODE 0xca3f
3152 #define MDIO_PMA_REG_CDR_BANDWIDTH 0xca46
3153 #define MDIO_PMA_REG_MISC_CTRL1 0xca85
3155 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL 0x8000
3156 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK 0x000c
3157 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE 0x0000
3158 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE 0x0004
3159 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS 0x0008
3160 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED 0x000c
3161 #define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT 0x8002
3162 #define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR 0x8003
3163 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF 0xc820
3164 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff
3165 #define MDIO_PMA_REG_8726_TX_CTRL1 0xca01
3166 #define MDIO_PMA_REG_8726_TX_CTRL2 0xca05
3168 #define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR 0x8005
3169 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF 0x8007
3170 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff
3171 #define MDIO_PMA_REG_8727_MISC_CTRL 0x8309
3172 #define MDIO_PMA_REG_8727_TX_CTRL1 0xca02
3173 #define MDIO_PMA_REG_8727_TX_CTRL2 0xca05
3174 #define MDIO_PMA_REG_8727_PCS_OPT_CTRL 0xc808
3175 #define MDIO_PMA_REG_8727_GPIO_CTRL 0xc80e
3176 #define MDIO_PMA_REG_8727_PCS_GP 0xc842
3177 #define MDIO_PMA_REG_8727_OPT_CFG_REG 0xc8e4
3179 #define MDIO_AN_REG_8727_MISC_CTRL 0x8309
3180 #define MDIO_PMA_REG_8073_CHIP_REV 0xc801
3181 #define MDIO_PMA_REG_8073_SPEED_LINK_STATUS 0xc820
3182 #define MDIO_PMA_REG_8073_XAUI_WA 0xc841
3183 #define MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL 0xcd08
3185 #define MDIO_PMA_REG_7101_RESET 0xc000
3186 #define MDIO_PMA_REG_7107_LED_CNTL 0xc007
3187 #define MDIO_PMA_REG_7107_LINK_LED_CNTL 0xc009
3188 #define MDIO_PMA_REG_7101_VER1 0xc026
3189 #define MDIO_PMA_REG_7101_VER2 0xc027
3191 #define MDIO_PMA_REG_8481_PMD_SIGNAL 0xa811
3192 #define MDIO_PMA_REG_8481_LED1_MASK 0xa82c
3193 #define MDIO_PMA_REG_8481_LED2_MASK 0xa82f
3194 #define MDIO_PMA_REG_8481_LED3_MASK 0xa832
3195 #define MDIO_PMA_REG_8481_LED3_BLINK 0xa834
3196 #define MDIO_PMA_REG_8481_LED5_MASK 0xa838
3197 #define MDIO_PMA_REG_8481_SIGNAL_MASK 0xa835
3198 #define MDIO_PMA_REG_8481_LINK_SIGNAL 0xa83b
3199 #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK 0x800
3200 #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT 11
3203 #define MDIO_WIS_DEVAD 0x2
3205 #define MDIO_WIS_REG_LASI_CNTL 0x9002
3206 #define MDIO_WIS_REG_LASI_STATUS 0x9005
3208 #define MDIO_PCS_DEVAD 0x3
3209 #define MDIO_PCS_REG_STATUS 0x0020
3210 #define MDIO_PCS_REG_LASI_STATUS 0x9005
3211 #define MDIO_PCS_REG_7101_DSP_ACCESS 0xD000
3212 #define MDIO_PCS_REG_7101_SPI_MUX 0xD008
3213 #define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A
3214 #define MDIO_PCS_REG_7101_SPI_RESET_BIT (5)
3215 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A
3216 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6)
3217 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD (0xC7)
3218 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2)
3219 #define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028
3222 #define MDIO_XS_DEVAD 0x4
3223 #define MDIO_XS_REG_STATUS 0x0001
3224 #define MDIO_XS_PLL_SEQUENCER 0x8000
3225 #define MDIO_XS_SFX7101_XGXS_TEST1 0xc00a
3227 #define MDIO_XS_8706_REG_BANK_RX0 0x80bc
3228 #define MDIO_XS_8706_REG_BANK_RX1 0x80cc
3229 #define MDIO_XS_8706_REG_BANK_RX2 0x80dc
3230 #define MDIO_XS_8706_REG_BANK_RX3 0x80ec
3231 #define MDIO_XS_8706_REG_BANK_RXA 0x80fc
3233 #define MDIO_XS_REG_8073_RX_CTRL_PCIE 0x80FA
3235 #define MDIO_AN_DEVAD 0x7
3237 #define MDIO_AN_REG_CTRL 0x0000
3238 #define MDIO_AN_REG_STATUS 0x0001
3239 #define MDIO_AN_REG_STATUS_AN_COMPLETE 0x0020
3240 #define MDIO_AN_REG_ADV_PAUSE 0x0010
3241 #define MDIO_AN_REG_ADV_PAUSE_PAUSE 0x0400
3242 #define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC 0x0800
3243 #define MDIO_AN_REG_ADV_PAUSE_BOTH 0x0C00
3244 #define MDIO_AN_REG_ADV_PAUSE_MASK 0x0C00
3245 #define MDIO_AN_REG_ADV 0x0011
3246 #define MDIO_AN_REG_ADV2 0x0012
3247 #define MDIO_AN_REG_LP_AUTO_NEG 0x0013
3248 #define MDIO_AN_REG_LP_AUTO_NEG2 0x0014
3249 #define MDIO_AN_REG_MASTER_STATUS 0x0021
3250 #define MDIO_AN_REG_EEE_ADV 0x003c
3251 #define MDIO_AN_REG_LP_EEE_ADV 0x003d
3253 #define MDIO_AN_REG_LINK_STATUS 0x8304
3254 #define MDIO_AN_REG_CL37_CL73 0x8370
3255 #define MDIO_AN_REG_CL37_AN 0xffe0
3256 #define MDIO_AN_REG_CL37_FC_LD 0xffe4
3257 #define MDIO_AN_REG_CL37_FC_LP 0xffe5
3258 #define MDIO_AN_REG_1000T_STATUS 0xffea
3260 #define MDIO_AN_REG_8073_2_5G 0x8329
3261 #define MDIO_AN_REG_8073_BAM 0x8350
3263 #define MDIO_AN_REG_8481_10GBASE_T_AN_CTRL 0x0020
3264 #define MDIO_AN_REG_8481_LEGACY_MII_CTRL 0xffe0
3265 #define MDIO_AN_REG_8481_MII_CTRL_FORCE_1G 0x40
3266 #define MDIO_AN_REG_8481_LEGACY_MII_STATUS 0xffe1
3267 #define MDIO_AN_REG_8481_LEGACY_AN_ADV 0xffe4
3268 #define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION 0xffe6
3269 #define MDIO_AN_REG_8481_1000T_CTRL 0xffe9
3270 #define MDIO_AN_REG_8481_1G_100T_EXT_CTRL 0xfff0
3271 #define MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF 0x0008
3272 #define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW 0xfff5
3273 #define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS 0xfff7
3274 #define MDIO_AN_REG_8481_AUX_CTRL 0xfff8
3275 #define MDIO_AN_REG_8481_LEGACY_SHADOW 0xfffc
3277 /* BNX2X84823 only */
3278 #define MDIO_CTL_DEVAD 0x1e
3279 #define MDIO_CTL_REG_84823_MEDIA 0x401a
3280 #define MDIO_CTL_REG_84823_MEDIA_MAC_MASK 0x0018
3281 /* These pins configure the BNX2X84823 interface to MAC after reset. */
3282 #define MDIO_CTL_REG_84823_CTRL_MAC_XFI 0x0008
3283 #define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M 0x0010
3284 /* These pins configure the BNX2X84823 interface to Line after reset. */
3285 #define MDIO_CTL_REG_84823_MEDIA_LINE_MASK 0x0060
3286 #define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L 0x0020
3287 #define MDIO_CTL_REG_84823_MEDIA_LINE_XFI 0x0040
3288 /* When this pin is active high during reset, 10GBASE-T core is power
3289 * down, When it is active low the 10GBASE-T is power up
3291 #define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN 0x0080
3292 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK 0x0100
3293 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER 0x0000
3294 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER 0x0100
3295 #define MDIO_CTL_REG_84823_MEDIA_FIBER_1G 0x1000
3296 #define MDIO_CTL_REG_84823_USER_CTRL_REG 0x4005
3297 #define MDIO_CTL_REG_84823_USER_CTRL_CMS 0x0080
3298 #define MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH 0xa82b
3299 #define MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ 0x2f
3300 #define MDIO_PMA_REG_84823_CTL_LED_CTL_1 0xa8e3
3301 #define MDIO_PMA_REG_84833_CTL_LED_CTL_1 0xa8ec
3302 #define MDIO_PMA_REG_84823_LED3_STRETCH_EN 0x0080
3304 /* BNX2X84833 only */
3305 #define MDIO_84833_TOP_CFG_FW_REV 0x400f
3306 #define MDIO_84833_TOP_CFG_FW_EEE 0x10b1
3307 #define MDIO_84833_TOP_CFG_FW_NO_EEE 0x1f81
3308 #define MDIO_84833_TOP_CFG_XGPHY_STRAP1 0x401a
3309 #define MDIO_84833_SUPER_ISOLATE 0x8000
3310 /* These are mailbox register set used by 84833. */
3311 #define MDIO_84833_TOP_CFG_SCRATCH_REG0 0x4005
3312 #define MDIO_84833_TOP_CFG_SCRATCH_REG1 0x4006
3313 #define MDIO_84833_TOP_CFG_SCRATCH_REG2 0x4007
3314 #define MDIO_84833_TOP_CFG_SCRATCH_REG3 0x4008
3315 #define MDIO_84833_TOP_CFG_SCRATCH_REG4 0x4009
3316 #define MDIO_84833_TOP_CFG_SCRATCH_REG26 0x4037
3317 #define MDIO_84833_TOP_CFG_SCRATCH_REG27 0x4038
3318 #define MDIO_84833_TOP_CFG_SCRATCH_REG28 0x4039
3319 #define MDIO_84833_TOP_CFG_SCRATCH_REG29 0x403a
3320 #define MDIO_84833_TOP_CFG_SCRATCH_REG30 0x403b
3321 #define MDIO_84833_TOP_CFG_SCRATCH_REG31 0x403c
3322 #define MDIO_84833_CMD_HDLR_COMMAND MDIO_84833_TOP_CFG_SCRATCH_REG0
3323 #define MDIO_84833_CMD_HDLR_STATUS MDIO_84833_TOP_CFG_SCRATCH_REG26
3324 #define MDIO_84833_CMD_HDLR_DATA1 MDIO_84833_TOP_CFG_SCRATCH_REG27
3325 #define MDIO_84833_CMD_HDLR_DATA2 MDIO_84833_TOP_CFG_SCRATCH_REG28
3326 #define MDIO_84833_CMD_HDLR_DATA3 MDIO_84833_TOP_CFG_SCRATCH_REG29
3327 #define MDIO_84833_CMD_HDLR_DATA4 MDIO_84833_TOP_CFG_SCRATCH_REG30
3328 #define MDIO_84833_CMD_HDLR_DATA5 MDIO_84833_TOP_CFG_SCRATCH_REG31
3330 /* Mailbox command set used by 84833. */
3331 #define PHY84833_CMD_SET_PAIR_SWAP 0x8001
3332 #define PHY84833_CMD_GET_EEE_MODE 0x8008
3333 #define PHY84833_CMD_SET_EEE_MODE 0x8009
3334 #define PHY84833_CMD_GET_CURRENT_TEMP 0x8031
3335 /* Mailbox status set used by 84833. */
3336 #define PHY84833_STATUS_CMD_RECEIVED 0x0001
3337 #define PHY84833_STATUS_CMD_IN_PROGRESS 0x0002
3338 #define PHY84833_STATUS_CMD_COMPLETE_PASS 0x0004
3339 #define PHY84833_STATUS_CMD_COMPLETE_ERROR 0x0008
3340 #define PHY84833_STATUS_CMD_OPEN_FOR_CMDS 0x0010
3341 #define PHY84833_STATUS_CMD_SYSTEM_BOOT 0x0020
3342 #define PHY84833_STATUS_CMD_NOT_OPEN_FOR_CMDS 0x0040
3343 #define PHY84833_STATUS_CMD_CLEAR_COMPLETE 0x0080
3344 #define PHY84833_STATUS_CMD_OPEN_OVERRIDE 0xa5a5
3347 /* Warpcore clause 45 addressing */
3348 #define MDIO_WC_DEVAD 0x3
3349 #define MDIO_WC_REG_IEEE0BLK_MIICNTL 0x0
3350 #define MDIO_WC_REG_IEEE0BLK_AUTONEGNP 0x7
3351 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT0 0x10
3352 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1 0x11
3353 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2 0x12
3354 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY 0x4000
3355 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ 0x8000
3356 #define MDIO_WC_REG_PCS_STATUS2 0x0021
3357 #define MDIO_WC_REG_PMD_KR_CONTROL 0x0096
3358 #define MDIO_WC_REG_XGXSBLK0_XGXSCONTROL 0x8000
3359 #define MDIO_WC_REG_XGXSBLK0_MISCCONTROL1 0x800e
3360 #define MDIO_WC_REG_XGXSBLK1_DESKEW 0x8010
3361 #define MDIO_WC_REG_XGXSBLK1_LANECTRL0 0x8015
3362 #define MDIO_WC_REG_XGXSBLK1_LANECTRL1 0x8016
3363 #define MDIO_WC_REG_XGXSBLK1_LANECTRL2 0x8017
3364 #define MDIO_WC_REG_XGXSBLK1_LANECTRL3 0x8018
3365 #define MDIO_WC_REG_XGXSBLK1_LANETEST0 0x801a
3366 #define MDIO_WC_REG_TX0_ANA_CTRL0 0x8061
3367 #define MDIO_WC_REG_TX1_ANA_CTRL0 0x8071
3368 #define MDIO_WC_REG_TX2_ANA_CTRL0 0x8081
3369 #define MDIO_WC_REG_TX3_ANA_CTRL0 0x8091
3370 #define MDIO_WC_REG_TX0_TX_DRIVER 0x8067
3371 #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET 0x04
3372 #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_MASK 0x00f0
3373 #define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET 0x08
3374 #define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
3375 #define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET 0x0c
3376 #define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_MASK 0x7000
3377 #define MDIO_WC_REG_TX1_TX_DRIVER 0x8077
3378 #define MDIO_WC_REG_TX2_TX_DRIVER 0x8087
3379 #define MDIO_WC_REG_TX3_TX_DRIVER 0x8097
3380 #define MDIO_WC_REG_RX0_ANARXCONTROL1G 0x80b9
3381 #define MDIO_WC_REG_RX2_ANARXCONTROL1G 0x80d9
3382 #define MDIO_WC_REG_RX0_PCI_CTRL 0x80ba
3383 #define MDIO_WC_REG_RX1_PCI_CTRL 0x80ca
3384 #define MDIO_WC_REG_RX2_PCI_CTRL 0x80da
3385 #define MDIO_WC_REG_RX3_PCI_CTRL 0x80ea
3386 #define MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G 0x8104
3387 #define MDIO_WC_REG_XGXS_STATUS3 0x8129
3388 #define MDIO_WC_REG_PAR_DET_10G_STATUS 0x8130
3389 #define MDIO_WC_REG_PAR_DET_10G_CTRL 0x8131
3390 #define MDIO_WC_REG_XGXS_STATUS4 0x813c
3391 #define MDIO_WC_REG_XGXS_X2_CONTROL2 0x8141
3392 #define MDIO_WC_REG_XGXS_X2_CONTROL3 0x8142
3393 #define MDIO_WC_REG_XGXS_RX_LN_SWAP1 0x816B
3394 #define MDIO_WC_REG_XGXS_TX_LN_SWAP1 0x8169
3395 #define MDIO_WC_REG_GP2_STATUS_GP_2_0 0x81d0
3396 #define MDIO_WC_REG_GP2_STATUS_GP_2_1 0x81d1
3397 #define MDIO_WC_REG_GP2_STATUS_GP_2_2 0x81d2
3398 #define MDIO_WC_REG_GP2_STATUS_GP_2_3 0x81d3
3399 #define MDIO_WC_REG_GP2_STATUS_GP_2_4 0x81d4
3400 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL 0x1000
3401 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CMPL 0x0100
3402 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP 0x0010
3403 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CAP 0x1
3404 #define MDIO_WC_REG_UC_INFO_B0_DEAD_TRAP 0x81EE
3405 #define MDIO_WC_REG_UC_INFO_B1_VERSION 0x81F0
3406 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE 0x81F2
3407 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE0_OFFSET 0x0
3408 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT 0x0
3409 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_OPT_LR 0x1
3410 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC 0x2
3411 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_XLAUI 0x3
3412 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_LONG_CH_6G 0x4
3413 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE1_OFFSET 0x4
3414 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE2_OFFSET 0x8
3415 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE3_OFFSET 0xc
3416 #define MDIO_WC_REG_UC_INFO_B1_CRC 0x81FE
3417 #define MDIO_WC_REG_DSC1B0_UC_CTRL 0x820e
3418 #define MDIO_WC_REG_DSC1B0_UC_CTRL_RDY4CMD (1<<7)
3419 #define MDIO_WC_REG_DSC_SMC 0x8213
3420 #define MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0 0x821e
3421 #define MDIO_WC_REG_TX_FIR_TAP 0x82e2
3422 #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET 0x00
3423 #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_MASK 0x000f
3424 #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET 0x04
3425 #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_MASK 0x03f0
3426 #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET 0x0a
3427 #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_MASK 0x7c00
3428 #define MDIO_WC_REG_TX_FIR_TAP_ENABLE 0x8000
3429 #define MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP 0x82e2
3430 #define MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL 0x82e3
3431 #define MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL 0x82e6
3432 #define MDIO_WC_REG_CL72_USERB0_CL72_BR_DEF_CTRL 0x82e7
3433 #define MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL 0x82e8
3434 #define MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL 0x82ec
3435 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1 0x8300
3436 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2 0x8301
3437 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3 0x8302
3438 #define MDIO_WC_REG_SERDESDIGITAL_STATUS1000X1 0x8304
3439 #define MDIO_WC_REG_SERDESDIGITAL_MISC1 0x8308
3440 #define MDIO_WC_REG_SERDESDIGITAL_MISC2 0x8309
3441 #define MDIO_WC_REG_DIGITAL3_UP1 0x8329
3442 #define MDIO_WC_REG_DIGITAL3_LP_UP1 0x832c
3443 #define MDIO_WC_REG_DIGITAL4_MISC3 0x833c
3444 #define MDIO_WC_REG_DIGITAL4_MISC5 0x833e
3445 #define MDIO_WC_REG_DIGITAL5_MISC6 0x8345
3446 #define MDIO_WC_REG_DIGITAL5_MISC7 0x8349
3447 #define MDIO_WC_REG_DIGITAL5_LINK_STATUS 0x834d
3448 #define MDIO_WC_REG_DIGITAL5_ACTUAL_SPEED 0x834e
3449 #define MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL 0x8350
3450 #define MDIO_WC_REG_CL49_USERB0_CTRL 0x8368
3451 #define MDIO_WC_REG_CL73_USERB0_CTRL 0x8370
3452 #define MDIO_WC_REG_CL73_USERB0_USTAT 0x8371
3453 #define MDIO_WC_REG_CL73_BAM_CTRL1 0x8372
3454 #define MDIO_WC_REG_CL73_BAM_CTRL2 0x8373
3455 #define MDIO_WC_REG_CL73_BAM_CTRL3 0x8374
3456 #define MDIO_WC_REG_CL73_BAM_CODE_FIELD 0x837b
3457 #define MDIO_WC_REG_EEE_COMBO_CONTROL0 0x8390
3458 #define MDIO_WC_REG_TX66_CONTROL 0x83b0
3459 #define MDIO_WC_REG_RX66_CONTROL 0x83c0
3460 #define MDIO_WC_REG_RX66_SCW0 0x83c2
3461 #define MDIO_WC_REG_RX66_SCW1 0x83c3
3462 #define MDIO_WC_REG_RX66_SCW2 0x83c4
3463 #define MDIO_WC_REG_RX66_SCW3 0x83c5
3464 #define MDIO_WC_REG_RX66_SCW0_MASK 0x83c6
3465 #define MDIO_WC_REG_RX66_SCW1_MASK 0x83c7
3466 #define MDIO_WC_REG_RX66_SCW2_MASK 0x83c8
3467 #define MDIO_WC_REG_RX66_SCW3_MASK 0x83c9
3468 #define MDIO_WC_REG_FX100_CTRL1 0x8400
3469 #define MDIO_WC_REG_FX100_CTRL3 0x8402
3470 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL5 0x8436
3471 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL6 0x8437
3472 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL7 0x8438
3473 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL9 0x8439
3474 #define MDIO_WC_REG_CL82_USERB1_RX_CTRL10 0x843a
3475 #define MDIO_WC_REG_CL82_USERB1_RX_CTRL11 0x843b
3476 #define MDIO_WC_REG_ETA_CL73_OUI1 0x8453
3477 #define MDIO_WC_REG_ETA_CL73_OUI2 0x8454
3478 #define MDIO_WC_REG_ETA_CL73_OUI3 0x8455
3479 #define MDIO_WC_REG_ETA_CL73_LD_BAM_CODE 0x8456
3480 #define MDIO_WC_REG_ETA_CL73_LD_UD_CODE 0x8457
3481 #define MDIO_WC_REG_MICROBLK_CMD 0xffc2
3482 #define MDIO_WC_REG_MICROBLK_DL_STATUS 0xffc5
3483 #define MDIO_WC_REG_MICROBLK_CMD3 0xffcc
3485 #define MDIO_WC_REG_AERBLK_AER 0xffde
3486 #define MDIO_WC_REG_COMBO_IEEE0_MIICTRL 0xffe0
3487 #define MDIO_WC_REG_COMBO_IEEE0_MIIISTAT 0xffe1
3489 #define MDIO_WC0_XGXS_BLK2_LANE_RESET 0x810A
3490 #define MDIO_WC0_XGXS_BLK2_LANE_RESET_RX_BITSHIFT 0
3491 #define MDIO_WC0_XGXS_BLK2_LANE_RESET_TX_BITSHIFT 4
3493 #define MDIO_WC0_XGXS_BLK6_XGXS_X2_CONTROL2 0x8141
3495 #define DIGITAL5_ACTUAL_SPEED_TX_MASK 0x003f
3498 #define MDIO_REG_GPHY_MII_STATUS 0x1
3499 #define MDIO_REG_GPHY_PHYID_LSB 0x3
3500 #define MDIO_REG_GPHY_CL45_ADDR_REG 0xd
3501 #define MDIO_REG_GPHY_CL45_REG_WRITE 0x4000
3502 #define MDIO_REG_GPHY_CL45_REG_READ 0xc000
3503 #define MDIO_REG_GPHY_CL45_DATA_REG 0xe
3504 #define MDIO_REG_GPHY_EEE_RESOLVED 0x803e
3505 #define MDIO_REG_GPHY_EXP_ACCESS_GATE 0x15
3506 #define MDIO_REG_GPHY_EXP_ACCESS 0x17
3507 #define MDIO_REG_GPHY_EXP_ACCESS_TOP 0xd00
3508 #define MDIO_REG_GPHY_EXP_TOP_2K_BUF 0x40
3509 #define MDIO_REG_GPHY_AUX_STATUS 0x19
3510 #define MDIO_REG_INTR_STATUS 0x1a
3511 #define MDIO_REG_INTR_MASK 0x1b
3512 #define MDIO_REG_INTR_MASK_LINK_STATUS (0x1 << 1)
3513 #define MDIO_REG_GPHY_SHADOW 0x1c
3514 #define MDIO_REG_GPHY_SHADOW_LED_SEL1 (0x0d << 10)
3515 #define MDIO_REG_GPHY_SHADOW_LED_SEL2 (0x0e << 10)
3516 #define MDIO_REG_GPHY_SHADOW_WR_ENA (0x1 << 15)
3517 #define MDIO_REG_GPHY_SHADOW_AUTO_DET_MED (0x1e << 10)
3518 #define MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD (0x1 << 8)
3521 #define IGU_FUNC_BASE 0x0400
3523 #define IGU_ADDR_MSIX 0x0000
3524 #define IGU_ADDR_INT_ACK 0x0200
3525 #define IGU_ADDR_PROD_UPD 0x0201
3526 #define IGU_ADDR_ATTN_BITS_UPD 0x0202
3527 #define IGU_ADDR_ATTN_BITS_SET 0x0203
3528 #define IGU_ADDR_ATTN_BITS_CLR 0x0204
3529 #define IGU_ADDR_COALESCE_NOW 0x0205
3530 #define IGU_ADDR_SIMD_MASK 0x0206
3531 #define IGU_ADDR_SIMD_NOMASK 0x0207
3532 #define IGU_ADDR_MSI_CTL 0x0210
3533 #define IGU_ADDR_MSI_ADDR_LO 0x0211
3534 #define IGU_ADDR_MSI_ADDR_HI 0x0212
3535 #define IGU_ADDR_MSI_DATA 0x0213
3538 #define IGU_USE_REGISTER_ustorm_type_0_sb_cleanup 0
3539 #define IGU_USE_REGISTER_ustorm_type_1_sb_cleanup 1
3540 #define IGU_USE_REGISTER_cstorm_type_0_sb_cleanup 2
3541 #define IGU_USE_REGISTER_cstorm_type_1_sb_cleanup 3
3543 #define COMMAND_REG_INT_ACK 0x0
3544 #define COMMAND_REG_PROD_UPD 0x4
3545 #define COMMAND_REG_ATTN_BITS_UPD 0x8
3546 #define COMMAND_REG_ATTN_BITS_SET 0xc
3547 #define COMMAND_REG_ATTN_BITS_CLR 0x10
3548 #define COMMAND_REG_COALESCE_NOW 0x14
3549 #define COMMAND_REG_SIMD_MASK 0x18
3550 #define COMMAND_REG_SIMD_NOMASK 0x1c
3553 #define IGU_MEM_BASE 0x0000
3555 #define IGU_MEM_MSIX_BASE 0x0000
3556 #define IGU_MEM_MSIX_UPPER 0x007f
3557 #define IGU_MEM_MSIX_RESERVED_UPPER 0x01ff
3559 #define IGU_MEM_PBA_MSIX_BASE 0x0200
3560 #define IGU_MEM_PBA_MSIX_UPPER 0x0200
3562 #define IGU_CMD_BACKWARD_COMP_PROD_UPD 0x0201
3563 #define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff
3565 #define IGU_CMD_INT_ACK_BASE 0x0400
3566 #define IGU_CMD_INT_ACK_UPPER \
3567 (IGU_CMD_INT_ACK_BASE + MAX_SB_PER_PATH - 1)
3568 #define IGU_CMD_INT_ACK_RESERVED_UPPER 0x04ff
3570 #define IGU_CMD_E2_PROD_UPD_BASE 0x0500
3571 #define IGU_CMD_E2_PROD_UPD_UPPER \
3572 (IGU_CMD_E2_PROD_UPD_BASE + MAX_SB_PER_PATH - 1)
3573 #define IGU_CMD_E2_PROD_UPD_RESERVED_UPPER 0x059f
3575 #define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05a0
3576 #define IGU_CMD_ATTN_BIT_SET_UPPER 0x05a1
3577 #define IGU_CMD_ATTN_BIT_CLR_UPPER 0x05a2
3579 #define IGU_REG_SISR_MDPC_WMASK_UPPER 0x05a3
3580 #define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER 0x05a4
3581 #define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER 0x05a5
3582 #define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05a6
3585 #define IGU_REG_RESERVED_UPPER 0x05ff
3587 #define IGU_SEG_IDX_ATTN 2
3588 #define IGU_SEG_IDX_DEFAULT 1
3589 /* Fields of IGU PF CONFIGRATION REGISTER */
3590 #define IGU_PF_CONF_FUNC_EN (0x1<<0) /* function enable */
3591 #define IGU_PF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */
3592 #define IGU_PF_CONF_INT_LINE_EN (0x1<<2) /* INT enable */
3593 #define IGU_PF_CONF_ATTN_BIT_EN (0x1<<3) /* attention enable */
3594 #define IGU_PF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */
3595 #define IGU_PF_CONF_SIMD_MODE (0x1<<5) /* simd all ones mode */
3597 /* Fields of IGU VF CONFIGRATION REGISTER */
3598 #define IGU_VF_CONF_FUNC_EN (0x1<<0) /* function enable */
3599 #define IGU_VF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */
3600 #define IGU_VF_CONF_PARENT_MASK (0x3<<2) /* Parent PF */
3601 #define IGU_VF_CONF_PARENT_SHIFT 2 /* Parent PF */
3602 #define IGU_VF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */
3605 #define IGU_BC_DSB_NUM_SEGS 5
3606 #define IGU_BC_NDSB_NUM_SEGS 2
3607 #define IGU_NORM_DSB_NUM_SEGS 2
3608 #define IGU_NORM_NDSB_NUM_SEGS 1
3609 #define IGU_BC_BASE_DSB_PROD 128
3610 #define IGU_NORM_BASE_DSB_PROD 136
3612 /* FID (if VF - [6] = 0; [5:0] = VF number; if PF - [6] = 1; \
3613 [5:2] = 0; [1:0] = PF number) */
3614 #define IGU_FID_ENCODE_IS_PF (0x1<<6)
3615 #define IGU_FID_ENCODE_IS_PF_SHIFT 6
3616 #define IGU_FID_VF_NUM_MASK (0x3f)
3617 #define IGU_FID_PF_NUM_MASK (0x7)
3619 #define IGU_REG_MAPPING_MEMORY_VALID (1<<0)
3620 #define IGU_REG_MAPPING_MEMORY_VECTOR_MASK (0x3F<<1)
3621 #define IGU_REG_MAPPING_MEMORY_VECTOR_SHIFT 1
3622 #define IGU_REG_MAPPING_MEMORY_FID_MASK (0x7F<<7)
3623 #define IGU_REG_MAPPING_MEMORY_FID_SHIFT 7
3626 #define CDU_REGION_NUMBER_XCM_AG 2
3627 #define CDU_REGION_NUMBER_UCM_AG 4
3630 /* String-to-compress [31:8] = CID (all 24 bits)
3631 * String-to-compress [7:4] = Region
3632 * String-to-compress [3:0] = Type
3634 #define CDU_VALID_DATA(_cid, _region, _type) \
3635 (((_cid) << 8) | (((_region)&0xf)<<4) | (((_type)&0xf)))
3636 #define CDU_CRC8(_cid, _region, _type) \
3637 (ecore_calc_crc8(CDU_VALID_DATA(_cid, _region, _type), 0xff))
3638 #define CDU_RSRVD_VALUE_TYPE_A(_cid, _region, _type) \
3639 (0x80 | ((CDU_CRC8(_cid, _region, _type)) & 0x7f))
3640 #define CDU_RSRVD_VALUE_TYPE_B(_crc, _type) \
3641 (0x80 | ((_type)&0xf << 3) | ((CDU_CRC8(_cid, _region, _type)) & 0x7))
3642 #define CDU_RSRVD_INVALIDATE_CONTEXT_VALUE(_val) ((_val) & ~0x80)
3644 #endif /* ECORE_REG_H */
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