2 * Copyright (c) 2007-2013 QLogic Corporation. All rights reserved.
4 * Eric Davis <edavis@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
6 * Gary Zambrano <zambrano@broadcom.com>
8 * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
9 * Copyright (c) 2015 QLogic Corporation.
10 * All rights reserved.
13 * See LICENSE.bnx2x_pmd for copyright and licensing details.
19 #if __BYTE_ORDER == __LITTLE_ENDIAN
23 #ifndef __LITTLE_ENDIAN
24 #define __LITTLE_ENDIAN
28 #else /* _BIG_ENDIAN */
36 #undef __LITTLE_ENDIAN
39 #include "ecore_mfw_req.h"
40 #include "ecore_fw_defs.h"
41 #include "ecore_hsi.h"
42 #include "ecore_reg.h"
45 typedef phys_addr_t ecore_dma_addr_t; /* expected to be 64 bit wide */
46 typedef volatile int ecore_atomic_t;
49 #define ETH_ALEN ETHER_ADDR_LEN /* 6 */
51 #define ECORE_SWCID_SHIFT 17
52 #define ECORE_SWCID_MASK ((0x1 << ECORE_SWCID_SHIFT) - 1)
54 #define ECORE_MC_HASH_SIZE 8
55 #define ECORE_MC_HASH_OFFSET(sc, i) \
56 (BAR_TSTRORM_INTMEM + \
57 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(FUNC_ID(sc)) + i*4)
59 #define ECORE_MAX_MULTICAST 64
60 #define ECORE_MAX_EMUL_MULTI 1
62 #define IRO sc->iro_array
64 typedef rte_spinlock_t ECORE_MUTEX;
65 #define ECORE_MUTEX_INIT(_mutex) rte_spinlock_init(_mutex)
66 #define ECORE_MUTEX_LOCK(_mutex) rte_spinlock_lock(_mutex)
67 #define ECORE_MUTEX_UNLOCK(_mutex) rte_spinlock_unlock(_mutex)
69 typedef rte_spinlock_t ECORE_MUTEX_SPIN;
70 #define ECORE_SPIN_LOCK_INIT(_spin, _sc) rte_spinlock_init(_spin)
71 #define ECORE_SPIN_LOCK_BH(_spin) rte_spinlock_lock(_spin) /* bh = bottom-half */
72 #define ECORE_SPIN_UNLOCK_BH(_spin) rte_spinlock_unlock(_spin) /* bh = bottom-half */
74 #define ECORE_SMP_MB_AFTER_CLEAR_BIT() mb()
75 #define ECORE_SMP_MB_BEFORE_CLEAR_BIT() mb()
76 #define ECORE_SMP_MB() mb()
77 #define ECORE_SMP_RMB() rmb()
78 #define ECORE_SMP_WMB() wmb()
79 #define ECORE_MMIOWB() wmb()
81 #define ECORE_SET_BIT_NA(bit, var) (*var |= (1 << bit))
82 #define ECORE_CLEAR_BIT_NA(bit, var) (*var &= ~(1 << bit))
84 #define ECORE_TEST_BIT(bit, var) bnx2x_test_bit(bit, var)
85 #define ECORE_SET_BIT(bit, var) bnx2x_set_bit(bit, var)
86 #define ECORE_CLEAR_BIT(bit, var) bnx2x_clear_bit(bit, var)
87 #define ECORE_TEST_AND_CLEAR_BIT(bit, var) bnx2x_test_and_clear_bit(bit, var)
89 #define atomic_load_acq_int (int)*
90 #define atomic_store_rel_int(a, v) (*a = v)
91 #define atomic_cmpset_acq_int(a, o, n) ((*a = (o & (n)) | (n)) ^ o)
93 #define atomic_load_acq_long (long)*
94 #define atomic_store_rel_long(a, v) (*a = v)
95 #define atomic_set_acq_long(a, v) (*a |= v)
96 #define atomic_clear_acq_long(a, v) (*a &= ~v)
97 #define atomic_cmpset_acq_long(a, o, n) ((*a = (o & (n)) | (n)) ^ o)
98 #define atomic_subtract_acq_long(a, v) (*a -= v)
99 #define atomic_add_acq_long(a, v) (*a += v)
101 #define ECORE_ATOMIC_READ(a) atomic_load_acq_int((volatile int *)a)
102 #define ECORE_ATOMIC_SET(a, v) atomic_store_rel_int((volatile int *)a, v)
103 #define ECORE_ATOMIC_CMPXCHG(a, o, n) bnx2x_cmpxchg((volatile int *)a, o, n)
105 #define ECORE_RET_PENDING(pending_bit, pending) \
106 (ECORE_TEST_BIT(pending_bit, pending) ? ECORE_PENDING : ECORE_SUCCESS)
108 #define ECORE_SET_FLAG(value, mask, flag) \
110 (value) &= ~(mask); \
111 (value) |= ((flag) << (mask##_SHIFT)); \
114 #define ECORE_GET_FLAG(value, mask) \
115 (((value) &= (mask)) >> (mask##_SHIFT))
117 #define ECORE_MIGHT_SLEEP()
119 #define ECORE_FCOE_CID(sc) ((sc)->fp[FCOE_IDX(sc)].cl_id)
121 #define ECORE_MEMCMP(_a, _b, _s) memcmp(_a, _b, _s)
122 #define ECORE_MEMCPY(_a, _b, _s) (void)rte_memcpy(_a, _b, _s)
123 #define ECORE_MEMSET(_a, _c, _s) memset(_a, _c, _s)
125 #define ECORE_CPU_TO_LE16(x) htole16(x)
126 #define ECORE_CPU_TO_LE32(x) htole32(x)
128 #define ECORE_WAIT(_s, _t) DELAY(1000)
129 #define ECORE_MSLEEP(_t) DELAY((_t) * 1000)
131 #define ECORE_LIKELY(x) likely(x)
132 #define ECORE_UNLIKELY(x) unlikely(x)
134 #define ECORE_ZALLOC(_size, _flags, _sc) \
135 rte_zmalloc("", _size, RTE_CACHE_LINE_SIZE)
137 #define ECORE_CALLOC(_len, _size, _flags, _sc) \
138 rte_calloc("", _len, _size, RTE_CACHE_LINE_SIZE)
140 #define ECORE_FREE(_s, _buf, _size) \
143 #define SC_ILT(sc) ((sc)->ilt)
144 #define ILOG2(x) bnx2x_ilog2(x)
146 #define ECORE_ILT_ZALLOC(x, y, size, str) \
148 x = rte_malloc("", sizeof(struct bnx2x_dma), RTE_CACHE_LINE_SIZE); \
150 if (bnx2x_dma_alloc((struct bnx2x_softc *)sc, \
151 size, (struct bnx2x_dma *)x, \
152 str, RTE_CACHE_LINE_SIZE) != 0) { \
157 *y = ((struct bnx2x_dma *)x)->paddr; \
162 #define ECORE_ILT_FREE(x, y, size) \
171 #define ECORE_IS_VALID_ETHER_ADDR(_mac) TRUE
173 #define ECORE_IS_MF_SD_MODE IS_MF_SD_MODE
174 #define ECORE_IS_MF_SI_MODE IS_MF_SI_MODE
175 #define ECORE_IS_MF_AFEX_MODE IS_MF_AFEX_MODE
177 #define ECORE_SET_CTX_VALIDATION bnx2x_set_ctx_validation
179 #define ECORE_UPDATE_COALESCE_SB_INDEX bnx2x_update_coalesce_sb_index
181 #define ECORE_ALIGN(x, a) ((((x) + (a) - 1) / (a)) * (a))
183 #define ECORE_REG_WR_DMAE_LEN REG_WR_DMAE_LEN
185 #define ECORE_PATH_ID SC_PATH
186 #define ECORE_PORT_ID SC_PORT
187 #define ECORE_FUNC_ID SC_FUNC
188 #define ECORE_ABS_FUNC_ID SC_ABS_FUNC
190 #define CRCPOLY_LE 0xedb88320
191 uint32_t ecore_calc_crc32(uint32_t crc, uint8_t const *p,
192 uint32_t len, uint32_t magic);
194 uint8_t ecore_calc_crc8(uint32_t data, uint8_t crc);
197 static inline uint32_t
198 ECORE_CRC32_LE(uint32_t seed, uint8_t *mac, uint32_t len)
200 return ecore_calc_crc32(seed, mac, len, CRCPOLY_LE);
203 #define ecore_sp_post(_sc, _a, _b, _c, _d) \
204 bnx2x_sp_post(_sc, _a, _b, U64_HI(_c), U64_LO(_c), _d)
206 #define ECORE_DBG_BREAK_IF(exp) \
208 if (unlikely(exp)) { \
209 rte_panic("ECORE"); \
213 #define ECORE_BUG() \
215 rte_panic("BUG (%s:%d)", __FILE__, __LINE__); \
218 #define ECORE_BUG_ON(exp) \
221 rte_panic("BUG_ON (%s:%d)", __FILE__, __LINE__); \
226 #define ECORE_MSG(m, ...) \
227 PMD_DRV_LOG(DEBUG, m, ##__VA_ARGS__)
229 typedef struct _ecore_list_entry_t
231 struct _ecore_list_entry_t *next, *prev;
232 } ecore_list_entry_t;
234 typedef struct ecore_list_t
236 ecore_list_entry_t *head, *tail;
240 /* initialize the list */
241 #define ECORE_LIST_INIT(_list) \
243 (_list)->head = NULL; \
244 (_list)->tail = NULL; \
248 /* return TRUE if the element is the last on the list */
249 #define ECORE_LIST_IS_LAST(_elem, _list) \
250 (_elem == (_list)->tail)
252 /* return TRUE if the list is empty */
253 #define ECORE_LIST_IS_EMPTY(_list) \
256 /* return the first element */
257 #define ECORE_LIST_FIRST_ENTRY(_list, cast, _link) \
258 (cast *)((_list)->head)
260 /* return the next element */
261 #define ECORE_LIST_NEXT(_elem, _link, cast) \
262 (cast *)((&((_elem)->_link))->next)
264 /* push an element on the head of the list */
265 #define ECORE_LIST_PUSH_HEAD(_elem, _list) \
267 (_elem)->prev = (ecore_list_entry_t *)0; \
268 (_elem)->next = (_list)->head; \
269 if ((_list)->tail == (ecore_list_entry_t *)0) { \
270 (_list)->tail = (_elem); \
272 (_list)->head->prev = (_elem); \
274 (_list)->head = (_elem); \
278 /* push an element on the tail of the list */
279 #define ECORE_LIST_PUSH_TAIL(_elem, _list) \
281 (_elem)->next = (ecore_list_entry_t *)0; \
282 (_elem)->prev = (_list)->tail; \
283 if ((_list)->tail) { \
284 (_list)->tail->next = (_elem); \
286 (_list)->head = (_elem); \
288 (_list)->tail = (_elem); \
292 /* push list1 on the head of list2 and return with list1 as empty */
293 #define ECORE_LIST_SPLICE_INIT(_list1, _list2) \
295 (_list1)->tail->next = (_list2)->head; \
296 if ((_list2)->head) { \
297 (_list2)->head->prev = (_list1)->tail; \
299 (_list2)->tail = (_list1)->tail; \
301 (_list2)->head = (_list1)->head; \
302 (_list2)->cnt += (_list1)->cnt; \
303 (_list1)->head = NULL; \
304 (_list1)->tail = NULL; \
308 /* remove an element from the list */
309 #define ECORE_LIST_REMOVE_ENTRY(_elem, _list) \
311 if ((_list)->head == (_elem)) { \
312 if ((_list)->head) { \
313 (_list)->head = (_list)->head->next; \
314 if ((_list)->head) { \
315 (_list)->head->prev = (ecore_list_entry_t *)0; \
317 (_list)->tail = (ecore_list_entry_t *)0; \
321 } else if ((_list)->tail == (_elem)) { \
322 if ((_list)->tail) { \
323 (_list)->tail = (_list)->tail->prev; \
324 if ((_list)->tail) { \
325 (_list)->tail->next = (ecore_list_entry_t *)0; \
327 (_list)->head = (ecore_list_entry_t *)0; \
332 (_elem)->prev->next = (_elem)->next; \
333 (_elem)->next->prev = (_elem)->prev; \
339 #define ECORE_LIST_FOR_EACH_ENTRY(pos, _list, _link, cast) \
340 for (pos = ECORE_LIST_FIRST_ENTRY(_list, cast, _link); \
342 pos = ECORE_LIST_NEXT(pos, _link, cast))
344 /* walk the list (safely) */
345 #define ECORE_LIST_FOR_EACH_ENTRY_SAFE(pos, n, _list, _link, cast) \
346 for (pos = ECORE_LIST_FIRST_ENTRY(_list, cast, _lint), \
347 n = (pos) ? ECORE_LIST_NEXT(pos, _link, cast) : NULL; \
350 n = (pos) ? ECORE_LIST_NEXT(pos, _link, cast) : NULL)
353 /* Manipulate a bit vector defined as an array of uint64_t */
355 /* Number of bits in one sge_mask array element */
356 #define BIT_VEC64_ELEM_SZ 64
357 #define BIT_VEC64_ELEM_SHIFT 6
358 #define BIT_VEC64_ELEM_MASK ((uint64_t)BIT_VEC64_ELEM_SZ - 1)
360 #define __BIT_VEC64_SET_BIT(el, bit) \
362 el = ((el) | ((uint64_t)0x1 << (bit))); \
365 #define __BIT_VEC64_CLEAR_BIT(el, bit) \
367 el = ((el) & (~((uint64_t)0x1 << (bit)))); \
370 #define BIT_VEC64_SET_BIT(vec64, idx) \
371 __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
372 (idx) & BIT_VEC64_ELEM_MASK)
374 #define BIT_VEC64_CLEAR_BIT(vec64, idx) \
375 __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
376 (idx) & BIT_VEC64_ELEM_MASK)
378 #define BIT_VEC64_TEST_BIT(vec64, idx) \
379 (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \
380 ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1)
383 * Creates a bitmask of all ones in less significant bits.
384 * idx - index of the most significant bit in the created mask
386 #define BIT_VEC64_ONES_MASK(idx) \
387 (((uint64_t)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1)
388 #define BIT_VEC64_ELEM_ONE_MASK ((uint64_t)(~0))
390 /* fill in a MAC address the way the FW likes it */
392 ecore_set_fw_mac_addr(uint16_t *fw_hi,
397 ((uint8_t *)fw_hi)[0] = mac[1];
398 ((uint8_t *)fw_hi)[1] = mac[0];
399 ((uint8_t *)fw_mid)[0] = mac[3];
400 ((uint8_t *)fw_mid)[1] = mac[2];
401 ((uint8_t *)fw_lo)[0] = mac[5];
402 ((uint8_t *)fw_lo)[1] = mac[4];
406 enum ecore_status_t {
414 /* PENDING is not an error and should be positive */
429 /* Bits representing general command's configuration */
433 /* Wait until all pending commands complete */
435 /* Don't send a ramrod, only update a registry */
437 /* Configure HW according to the current object state */
439 /* Execute the next command now */
441 /* Don't add a new command and continue execution of posponed
442 * commands. If not set a new command will be added to the
443 * pending commands list.
446 /* If there is another pending ramrod, wait until it finishes and
447 * re-try to submit this one. This flag can be set only in sleepable
448 * context, and should not be set from the context that completes the
449 * ramrods as deadlock will occur.
457 ECORE_OBJ_TYPE_RX_TX,
460 /* Public slow path states */
462 ECORE_FILTER_MAC_PENDING,
463 ECORE_FILTER_VLAN_PENDING,
464 ECORE_FILTER_VLAN_MAC_PENDING,
465 ECORE_FILTER_RX_MODE_PENDING,
466 ECORE_FILTER_RX_MODE_SCHED,
467 ECORE_FILTER_ISCSI_ETH_START_SCHED,
468 ECORE_FILTER_ISCSI_ETH_STOP_SCHED,
469 ECORE_FILTER_FCOE_ETH_START_SCHED,
470 ECORE_FILTER_FCOE_ETH_STOP_SCHED,
471 ECORE_FILTER_MCAST_PENDING,
472 ECORE_FILTER_MCAST_SCHED,
473 ECORE_FILTER_RSS_CONF_PENDING,
474 ECORE_AFEX_FCOE_Q_UPDATE_PENDING,
475 ECORE_AFEX_PENDING_VIFSET_MCP_ACK
478 struct ecore_raw_obj {
485 /* Ramrod data buffer params */
487 ecore_dma_addr_t rdata_mapping;
489 /* Ramrod state params */
490 int state; /* "ramrod is pending" state bit */
491 unsigned long *pstate; /* pointer to state buffer */
493 ecore_obj_type obj_type;
495 int (*wait_comp)(struct bnx2x_softc *sc,
496 struct ecore_raw_obj *o);
498 int (*check_pending)(struct ecore_raw_obj *o);
499 void (*clear_pending)(struct ecore_raw_obj *o);
500 void (*set_pending)(struct ecore_raw_obj *o);
503 /************************* VLAN-MAC commands related parameters ***************/
504 struct ecore_mac_ramrod_data {
505 uint8_t mac[ETH_ALEN];
506 uint8_t is_inner_mac;
509 struct ecore_vlan_ramrod_data {
513 struct ecore_vlan_mac_ramrod_data {
514 uint8_t mac[ETH_ALEN];
515 uint8_t is_inner_mac;
519 union ecore_classification_ramrod_data {
520 struct ecore_mac_ramrod_data mac;
521 struct ecore_vlan_ramrod_data vlan;
522 struct ecore_vlan_mac_ramrod_data vlan_mac;
525 /* VLAN_MAC commands */
526 enum ecore_vlan_mac_cmd {
532 struct ecore_vlan_mac_data {
533 /* Requested command: ECORE_VLAN_MAC_XX */
534 enum ecore_vlan_mac_cmd cmd;
535 /* used to contain the data related vlan_mac_flags bits from
538 unsigned long vlan_mac_flags;
540 /* Needed for MOVE command */
541 struct ecore_vlan_mac_obj *target_obj;
543 union ecore_classification_ramrod_data u;
546 /*************************** Exe Queue obj ************************************/
547 union ecore_exe_queue_cmd_data {
548 struct ecore_vlan_mac_data vlan_mac;
554 struct ecore_exeq_elem {
555 ecore_list_entry_t link;
557 /* Length of this element in the exe_chunk. */
560 union ecore_exe_queue_cmd_data cmd_data;
563 union ecore_qable_obj;
565 union ecore_exeq_comp_elem {
566 union event_ring_elem *elem;
569 struct ecore_exe_queue_obj;
571 typedef int (*exe_q_validate)(struct bnx2x_softc *sc,
572 union ecore_qable_obj *o,
573 struct ecore_exeq_elem *elem);
575 typedef int (*exe_q_remove)(struct bnx2x_softc *sc,
576 union ecore_qable_obj *o,
577 struct ecore_exeq_elem *elem);
579 /* Return positive if entry was optimized, 0 - if not, negative
580 * in case of an error.
582 typedef int (*exe_q_optimize)(struct bnx2x_softc *sc,
583 union ecore_qable_obj *o,
584 struct ecore_exeq_elem *elem);
585 typedef int (*exe_q_execute)(struct bnx2x_softc *sc,
586 union ecore_qable_obj *o,
587 ecore_list_t *exe_chunk,
588 unsigned long *ramrod_flags);
589 typedef struct ecore_exeq_elem *
590 (*exe_q_get)(struct ecore_exe_queue_obj *o,
591 struct ecore_exeq_elem *elem);
593 struct ecore_exe_queue_obj {
594 /* Commands pending for an execution. */
595 ecore_list_t exe_queue;
597 /* Commands pending for an completion. */
598 ecore_list_t pending_comp;
600 ECORE_MUTEX_SPIN lock;
602 /* Maximum length of commands' list for one execution */
605 union ecore_qable_obj *owner;
607 /****** Virtual functions ******/
609 * Called before commands execution for commands that are really
610 * going to be executed (after 'optimize').
612 * Must run under exe_queue->lock
614 exe_q_validate validate;
617 * Called before removing pending commands, cleaning allocated
618 * resources (e.g., credits from validate)
623 * This will try to cancel the current pending commands list
624 * considering the new command.
626 * Returns the number of optimized commands or a negative error code
628 * Must run under exe_queue->lock
630 exe_q_optimize optimize;
633 * Run the next commands chunk (owner specific).
635 exe_q_execute execute;
638 * Return the exe_queue element containing the specific command
639 * if any. Otherwise return NULL.
643 /***************** Classification verbs: Set/Del MAC/VLAN/VLAN-MAC ************/
645 * Element in the VLAN_MAC registry list having all current configured
648 struct ecore_vlan_mac_registry_elem {
649 ecore_list_entry_t link;
651 /* Used to store the cam offset used for the mac/vlan/vlan-mac.
652 * Relevant for 57711 only. VLANs and MACs share the
653 * same CAM for these chips.
657 /* Needed for DEL and RESTORE flows */
658 unsigned long vlan_mac_flags;
660 union ecore_classification_ramrod_data u;
663 /* Bits representing VLAN_MAC commands specific flags */
669 ECORE_DONT_CONSUME_CAM_CREDIT,
670 ECORE_DONT_CONSUME_CAM_CREDIT_DEST,
673 struct ecore_vlan_mac_ramrod_params {
674 /* Object to run the command from */
675 struct ecore_vlan_mac_obj *vlan_mac_obj;
677 /* General command flags: COMP_WAIT, etc. */
678 unsigned long ramrod_flags;
680 /* Command specific configuration request */
681 struct ecore_vlan_mac_data user_req;
684 struct ecore_vlan_mac_obj {
685 struct ecore_raw_obj raw;
687 /* Bookkeeping list: will prevent the addition of already existing
691 /* Implement a simple reader/writer lock on the head list.
692 * all these fields should only be accessed under the exe_queue lock
694 uint8_t head_reader; /* Num. of readers accessing head list */
695 int head_exe_request; /* Pending execution request. */
696 unsigned long saved_ramrod_flags; /* Ramrods of pending execution */
698 /* Execution queue interface instance */
699 struct ecore_exe_queue_obj exe_queue;
701 /* MACs credit pool */
702 struct ecore_credit_pool_obj *macs_pool;
704 /* VLANs credit pool */
705 struct ecore_credit_pool_obj *vlans_pool;
707 /* RAMROD command to be used */
710 /* copy first n elements onto preallocated buffer
712 * @param n number of elements to get
713 * @param buf buffer preallocated by caller into which elements
714 * will be copied. Note elements are 4-byte aligned
715 * so buffer size must be able to accommodate the
718 * @return number of copied bytes
721 int (*get_n_elements)(struct bnx2x_softc *sc,
722 struct ecore_vlan_mac_obj *o, int n, uint8_t *base,
723 uint8_t stride, uint8_t size);
726 * Checks if ADD-ramrod with the given params may be performed.
728 * @return zero if the element may be added
731 int (*check_add)(struct bnx2x_softc *sc,
732 struct ecore_vlan_mac_obj *o,
733 union ecore_classification_ramrod_data *data);
736 * Checks if DEL-ramrod with the given params may be performed.
738 * @return TRUE if the element may be deleted
740 struct ecore_vlan_mac_registry_elem *
741 (*check_del)(struct bnx2x_softc *sc,
742 struct ecore_vlan_mac_obj *o,
743 union ecore_classification_ramrod_data *data);
746 * Checks if DEL-ramrod with the given params may be performed.
748 * @return TRUE if the element may be deleted
750 int (*check_move)(struct bnx2x_softc *sc,
751 struct ecore_vlan_mac_obj *src_o,
752 struct ecore_vlan_mac_obj *dst_o,
753 union ecore_classification_ramrod_data *data);
756 * Update the relevant credit object(s) (consume/return
759 int (*get_credit)(struct ecore_vlan_mac_obj *o);
760 int (*put_credit)(struct ecore_vlan_mac_obj *o);
761 int (*get_cam_offset)(struct ecore_vlan_mac_obj *o, int *offset);
762 int (*put_cam_offset)(struct ecore_vlan_mac_obj *o, int offset);
765 * Configures one rule in the ramrod data buffer.
767 void (*set_one_rule)(struct bnx2x_softc *sc,
768 struct ecore_vlan_mac_obj *o,
769 struct ecore_exeq_elem *elem, int rule_idx,
773 * Delete all configured elements having the given
774 * vlan_mac_flags specification. Assumes no pending for
775 * execution commands. Will schedule all all currently
776 * configured MACs/VLANs/VLAN-MACs matching the vlan_mac_flags
777 * specification for deletion and will use the given
778 * ramrod_flags for the last DEL operation.
782 * @param ramrod_flags RAMROD_XX flags
784 * @return 0 if the last operation has completed successfully
785 * and there are no more elements left, positive value
786 * if there are pending for completion commands,
787 * negative value in case of failure.
789 int (*delete_all)(struct bnx2x_softc *sc,
790 struct ecore_vlan_mac_obj *o,
791 unsigned long *vlan_mac_flags,
792 unsigned long *ramrod_flags);
795 * Reconfigures the next MAC/VLAN/VLAN-MAC element from the previously
796 * configured elements list.
799 * @param p Command parameters (RAMROD_COMP_WAIT bit in
800 * ramrod_flags is only taken into an account)
801 * @param ppos a pointer to the cookie that should be given back in the
802 * next call to make function handle the next element. If
803 * *ppos is set to NULL it will restart the iterator.
804 * If returned *ppos == NULL this means that the last
805 * element has been handled.
809 int (*restore)(struct bnx2x_softc *sc,
810 struct ecore_vlan_mac_ramrod_params *p,
811 struct ecore_vlan_mac_registry_elem **ppos);
814 * Should be called on a completion arrival.
818 * @param cqe Completion element we are handling
819 * @param ramrod_flags if RAMROD_CONT is set the next bulk of
820 * pending commands will be executed.
821 * RAMROD_DRV_CLR_ONLY and RAMROD_RESTORE
822 * may also be set if needed.
824 * @return 0 if there are neither pending nor waiting for
825 * completion commands. Positive value if there are
826 * pending for execution or for completion commands.
827 * Negative value in case of an error (including an
830 int (*complete)(struct bnx2x_softc *sc, struct ecore_vlan_mac_obj *o,
831 union event_ring_elem *cqe,
832 unsigned long *ramrod_flags);
835 * Wait for completion of all commands. Don't schedule new ones,
836 * just wait. It assumes that the completion code will schedule
839 int (*wait)(struct bnx2x_softc *sc, struct ecore_vlan_mac_obj *o);
843 ECORE_LLH_CAM_ISCSI_ETH_LINE = 0,
844 ECORE_LLH_CAM_ETH_LINE,
845 ECORE_LLH_CAM_MAX_PF_LINE = NIG_REG_LLH1_FUNC_MEM_SIZE / 2
848 /** RX_MODE verbs:DROP_ALL/ACCEPT_ALL/ACCEPT_ALL_MULTI/ACCEPT_ALL_VLAN/NORMAL */
850 /* RX_MODE ramrod special flags: set in rx_mode_flags field in
851 * a ecore_rx_mode_ramrod_params.
854 ECORE_RX_MODE_FCOE_ETH,
855 ECORE_RX_MODE_ISCSI_ETH,
859 ECORE_ACCEPT_UNICAST,
860 ECORE_ACCEPT_MULTICAST,
861 ECORE_ACCEPT_ALL_UNICAST,
862 ECORE_ACCEPT_ALL_MULTICAST,
863 ECORE_ACCEPT_BROADCAST,
864 ECORE_ACCEPT_UNMATCHED,
865 ECORE_ACCEPT_ANY_VLAN
868 struct ecore_rx_mode_ramrod_params {
869 struct ecore_rx_mode_obj *rx_mode_obj;
870 unsigned long *pstate;
875 unsigned long ramrod_flags;
876 unsigned long rx_mode_flags;
878 /* rdata is either a pointer to eth_filter_rules_ramrod_data(e2) or to
879 * a tstorm_eth_mac_filter_config (e1x).
882 ecore_dma_addr_t rdata_mapping;
884 /* Rx mode settings */
885 unsigned long rx_accept_flags;
887 /* internal switching settings */
888 unsigned long tx_accept_flags;
891 struct ecore_rx_mode_obj {
892 int (*config_rx_mode)(struct bnx2x_softc *sc,
893 struct ecore_rx_mode_ramrod_params *p);
895 int (*wait_comp)(struct bnx2x_softc *sc,
896 struct ecore_rx_mode_ramrod_params *p);
899 /********************** Set multicast group ***********************************/
901 struct ecore_mcast_list_elem {
902 ecore_list_entry_t link;
906 union ecore_mcast_config_data {
908 uint8_t bin; /* used in a RESTORE flow */
911 struct ecore_mcast_ramrod_params {
912 struct ecore_mcast_obj *mcast_obj;
914 /* Relevant options are RAMROD_COMP_WAIT and RAMROD_DRV_CLR_ONLY */
915 unsigned long ramrod_flags;
917 ecore_list_t mcast_list; /* list of struct ecore_mcast_list_elem */
921 enum ecore_mcast_cmd {
923 ECORE_MCAST_CMD_CONT,
925 ECORE_MCAST_CMD_RESTORE,
928 struct ecore_mcast_obj {
929 struct ecore_raw_obj raw;
933 #define ECORE_MCAST_BINS_NUM 256
934 #define ECORE_MCAST_VEC_SZ (ECORE_MCAST_BINS_NUM / 64)
935 uint64_t vec[ECORE_MCAST_VEC_SZ];
937 /** Number of BINs to clear. Should be updated
938 * immediately when a command arrives in order to
939 * properly create DEL commands.
950 /* Pending commands */
951 ecore_list_t pending_cmds_head;
953 /* A state that is set in raw.pstate, when there are pending commands */
956 /* Maximal number of mcast MACs configured in one command */
959 /* Total number of currently pending MACs to configure: both
960 * in the pending commands list and in the current command.
962 int total_pending_num;
967 * @param cmd command to execute (ECORE_MCAST_CMD_X, see above)
969 int (*config_mcast)(struct bnx2x_softc *sc,
970 struct ecore_mcast_ramrod_params *p,
971 enum ecore_mcast_cmd cmd);
974 * Fills the ramrod data during the RESTORE flow.
978 * @param start_idx Registry index to start from
979 * @param rdata_idx Index in the ramrod data to start from
981 * @return -1 if we handled the whole registry or index of the last
982 * handled registry element.
984 int (*hdl_restore)(struct bnx2x_softc *sc, struct ecore_mcast_obj *o,
985 int start_bin, int *rdata_idx);
987 int (*enqueue_cmd)(struct bnx2x_softc *sc, struct ecore_mcast_obj *o,
988 struct ecore_mcast_ramrod_params *p,
989 enum ecore_mcast_cmd cmd);
991 void (*set_one_rule)(struct bnx2x_softc *sc,
992 struct ecore_mcast_obj *o, int idx,
993 union ecore_mcast_config_data *cfg_data,
994 enum ecore_mcast_cmd cmd);
996 /** Checks if there are more mcast MACs to be set or a previous
997 * command is still pending.
999 int (*check_pending)(struct ecore_mcast_obj *o);
1002 * Set/Clear/Check SCHEDULED state of the object
1004 void (*set_sched)(struct ecore_mcast_obj *o);
1005 void (*clear_sched)(struct ecore_mcast_obj *o);
1006 int (*check_sched)(struct ecore_mcast_obj *o);
1008 /* Wait until all pending commands complete */
1009 int (*wait_comp)(struct bnx2x_softc *sc, struct ecore_mcast_obj *o);
1012 * Handle the internal object counters needed for proper
1013 * commands handling. Checks that the provided parameters are
1016 int (*validate)(struct bnx2x_softc *sc,
1017 struct ecore_mcast_ramrod_params *p,
1018 enum ecore_mcast_cmd cmd);
1021 * Restore the values of internal counters in case of a failure.
1023 void (*revert)(struct bnx2x_softc *sc,
1024 struct ecore_mcast_ramrod_params *p,
1027 int (*get_registry_size)(struct ecore_mcast_obj *o);
1028 void (*set_registry_size)(struct ecore_mcast_obj *o, int n);
1031 /*************************** Credit handling **********************************/
1032 struct ecore_credit_pool_obj {
1034 /* Current amount of credit in the pool */
1035 ecore_atomic_t credit;
1037 /* Maximum allowed credit. put() will check against it. */
1040 /* Allocate a pool table statically.
1042 * Currently the maximum allowed size is MAX_MAC_CREDIT_E2(272)
1044 * The set bit in the table will mean that the entry is available.
1046 #define ECORE_POOL_VEC_SIZE (MAX_MAC_CREDIT_E2 / 64)
1047 uint64_t pool_mirror[ECORE_POOL_VEC_SIZE];
1049 /* Base pool offset (initialized differently */
1050 int base_pool_offset;
1053 * Get the next free pool entry.
1055 * @return TRUE if there was a free entry in the pool
1057 int (*get_entry)(struct ecore_credit_pool_obj *o, int *entry);
1060 * Return the entry back to the pool.
1062 * @return TRUE if entry is legal and has been successfully
1063 * returned to the pool.
1065 int (*put_entry)(struct ecore_credit_pool_obj *o, int entry);
1068 * Get the requested amount of credit from the pool.
1070 * @param cnt Amount of requested credit
1071 * @return TRUE if the operation is successful
1073 int (*get)(struct ecore_credit_pool_obj *o, int cnt);
1076 * Returns the credit to the pool.
1078 * @param cnt Amount of credit to return
1079 * @return TRUE if the operation is successful
1081 int (*put)(struct ecore_credit_pool_obj *o, int cnt);
1084 * Reads the current amount of credit.
1086 int (*check)(struct ecore_credit_pool_obj *o);
1089 /*************************** RSS configuration ********************************/
1091 /* RSS_MODE bits are mutually exclusive */
1092 ECORE_RSS_MODE_DISABLED,
1093 ECORE_RSS_MODE_REGULAR,
1095 ECORE_RSS_SET_SRCH, /* Setup searcher, E1x specific flag */
1104 ECORE_RSS_TUNNELING,
1107 struct ecore_config_rss_params {
1108 struct ecore_rss_config_obj *rss_obj;
1110 /* may have RAMROD_COMP_WAIT set only */
1111 unsigned long ramrod_flags;
1113 /* ECORE_RSS_X bits */
1114 unsigned long rss_flags;
1116 /* Number hash bits to take into an account */
1117 uint8_t rss_result_mask;
1119 /* Indirection table */
1120 uint8_t ind_table[T_ETH_INDIRECTION_TABLE_SIZE];
1122 /* RSS hash values */
1123 uint32_t rss_key[10];
1125 /* valid only iff ECORE_RSS_UPDATE_TOE is set */
1126 uint16_t toe_rss_bitmap;
1128 /* valid iff ECORE_RSS_TUNNELING is set */
1129 uint16_t tunnel_value;
1130 uint16_t tunnel_mask;
1133 struct ecore_rss_config_obj {
1134 struct ecore_raw_obj raw;
1136 /* RSS engine to use */
1139 /* Last configured indirection table */
1140 uint8_t ind_table[T_ETH_INDIRECTION_TABLE_SIZE];
1142 /* flags for enabling 4-tupple hash on UDP */
1146 int (*config_rss)(struct bnx2x_softc *sc,
1147 struct ecore_config_rss_params *p);
1150 /*********************** Queue state update ***********************************/
1152 /* UPDATE command options */
1154 ECORE_Q_UPDATE_IN_VLAN_REM,
1155 ECORE_Q_UPDATE_IN_VLAN_REM_CHNG,
1156 ECORE_Q_UPDATE_OUT_VLAN_REM,
1157 ECORE_Q_UPDATE_OUT_VLAN_REM_CHNG,
1158 ECORE_Q_UPDATE_ANTI_SPOOF,
1159 ECORE_Q_UPDATE_ANTI_SPOOF_CHNG,
1160 ECORE_Q_UPDATE_ACTIVATE,
1161 ECORE_Q_UPDATE_ACTIVATE_CHNG,
1162 ECORE_Q_UPDATE_DEF_VLAN_EN,
1163 ECORE_Q_UPDATE_DEF_VLAN_EN_CHNG,
1164 ECORE_Q_UPDATE_SILENT_VLAN_REM_CHNG,
1165 ECORE_Q_UPDATE_SILENT_VLAN_REM,
1166 ECORE_Q_UPDATE_TX_SWITCHING_CHNG,
1167 ECORE_Q_UPDATE_TX_SWITCHING,
1170 /* Allowed Queue states */
1171 enum ecore_q_state {
1172 ECORE_Q_STATE_RESET,
1173 ECORE_Q_STATE_INITIALIZED,
1174 ECORE_Q_STATE_ACTIVE,
1175 ECORE_Q_STATE_MULTI_COS,
1176 ECORE_Q_STATE_MCOS_TERMINATED,
1177 ECORE_Q_STATE_INACTIVE,
1178 ECORE_Q_STATE_STOPPED,
1179 ECORE_Q_STATE_TERMINATED,
1180 ECORE_Q_STATE_FLRED,
1184 /* Allowed Queue states */
1185 enum ecore_q_logical_state {
1186 ECORE_Q_LOGICAL_STATE_ACTIVE,
1187 ECORE_Q_LOGICAL_STATE_STOPPED,
1190 /* Allowed commands */
1191 enum ecore_queue_cmd {
1194 ECORE_Q_CMD_SETUP_TX_ONLY,
1195 ECORE_Q_CMD_DEACTIVATE,
1196 ECORE_Q_CMD_ACTIVATE,
1198 ECORE_Q_CMD_UPDATE_TPA,
1200 ECORE_Q_CMD_CFC_DEL,
1201 ECORE_Q_CMD_TERMINATE,
1206 /* queue SETUP + INIT flags */
1209 ECORE_Q_FLG_TPA_IPV6,
1210 ECORE_Q_FLG_TPA_GRO,
1212 ECORE_Q_FLG_ZERO_STATS,
1222 ECORE_Q_FLG_LEADING_RSS,
1224 ECORE_Q_FLG_DEF_VLAN,
1225 ECORE_Q_FLG_TX_SWITCH,
1227 ECORE_Q_FLG_ANTI_SPOOF,
1228 ECORE_Q_FLG_SILENT_VLAN_REM,
1229 ECORE_Q_FLG_FORCE_DEFAULT_PRI,
1230 ECORE_Q_FLG_REFUSE_OUTBAND_VLAN,
1231 ECORE_Q_FLG_PCSUM_ON_PKT,
1232 ECORE_Q_FLG_TUN_INC_INNER_IP_ID
1235 /* Queue type options: queue type may be a combination of below. */
1238 ECORE_Q_TYPE_HAS_RX,
1239 ECORE_Q_TYPE_HAS_TX,
1242 #define ECORE_PRIMARY_CID_INDEX 0
1243 #define ECORE_MULTI_TX_COS_E1X 3 /* QM only */
1244 #define ECORE_MULTI_TX_COS_E2_E3A0 2
1245 #define ECORE_MULTI_TX_COS_E3B0 3
1246 #define ECORE_MULTI_TX_COS 3 /* Maximum possible */
1247 #define MAC_PAD (ECORE_ALIGN(ETH_ALEN, sizeof(uint32_t)) - ETH_ALEN)
1249 struct ecore_queue_init_params {
1251 unsigned long flags;
1254 uint8_t sb_cq_index;
1258 unsigned long flags;
1261 uint8_t sb_cq_index;
1264 /* CID context in the host memory */
1265 struct eth_context *cxts[ECORE_MULTI_TX_COS];
1267 /* maximum number of cos supported by hardware */
1271 struct ecore_queue_terminate_params {
1272 /* index within the tx_only cids of this queue object */
1276 struct ecore_queue_cfc_del_params {
1277 /* index within the tx_only cids of this queue object */
1281 struct ecore_queue_update_params {
1282 unsigned long update_flags; /* ECORE_Q_UPDATE_XX bits */
1284 uint16_t silent_removal_value;
1285 uint16_t silent_removal_mask;
1286 /* index within the tx_only cids of this queue object */
1290 struct rxq_pause_params {
1295 uint16_t sge_th_lo; /* valid iff ECORE_Q_FLG_TPA */
1296 uint16_t sge_th_hi; /* valid iff ECORE_Q_FLG_TPA */
1301 struct ecore_general_setup_params {
1302 /* valid iff ECORE_Q_FLG_STATS */
1310 struct ecore_rxq_setup_params {
1312 ecore_dma_addr_t dscr_map;
1313 ecore_dma_addr_t rcq_map;
1314 ecore_dma_addr_t rcq_np_map;
1316 uint16_t drop_flags;
1319 uint8_t cl_qzone_id;
1321 /* valid iff ECORE_Q_FLG_TPA */
1322 uint16_t tpa_agg_sz;
1323 uint8_t max_tpa_queues;
1324 uint8_t rss_engine_id;
1326 /* valid iff ECORE_Q_FLG_MCAST */
1327 uint8_t mcast_engine_id;
1329 uint8_t cache_line_log;
1331 uint8_t sb_cq_index;
1333 /* valid iff BXN2X_Q_FLG_SILENT_VLAN_REM */
1334 uint16_t silent_removal_value;
1335 uint16_t silent_removal_mask;
1338 struct ecore_txq_setup_params {
1340 ecore_dma_addr_t dscr_map;
1343 uint8_t sb_cq_index;
1344 uint8_t cos; /* valid iff ECORE_Q_FLG_COS */
1345 uint16_t traffic_type;
1346 /* equals to the leading rss client id, used for TX classification*/
1347 uint8_t tss_leading_cl_id;
1349 /* valid iff ECORE_Q_FLG_DEF_VLAN */
1350 uint16_t default_vlan;
1353 struct ecore_queue_setup_params {
1354 struct ecore_general_setup_params gen_params;
1355 struct ecore_txq_setup_params txq_params;
1356 struct ecore_rxq_setup_params rxq_params;
1357 struct rxq_pause_params pause_params;
1358 unsigned long flags;
1361 struct ecore_queue_setup_tx_only_params {
1362 struct ecore_general_setup_params gen_params;
1363 struct ecore_txq_setup_params txq_params;
1364 unsigned long flags;
1365 /* index within the tx_only cids of this queue object */
1369 struct ecore_queue_state_params {
1370 struct ecore_queue_sp_obj *q_obj;
1372 /* Current command */
1373 enum ecore_queue_cmd cmd;
1375 /* may have RAMROD_COMP_WAIT set only */
1376 unsigned long ramrod_flags;
1378 /* Params according to the current command */
1380 struct ecore_queue_update_params update;
1381 struct ecore_queue_setup_params setup;
1382 struct ecore_queue_init_params init;
1383 struct ecore_queue_setup_tx_only_params tx_only;
1384 struct ecore_queue_terminate_params terminate;
1385 struct ecore_queue_cfc_del_params cfc_del;
1389 struct ecore_viflist_params {
1391 uint8_t func_bit_map_res;
1394 struct ecore_queue_sp_obj {
1395 uint32_t cids[ECORE_MULTI_TX_COS];
1399 /* number of traffic classes supported by queue.
1400 * The primary connection of the queue supports the first traffic
1401 * class. Any further traffic class is supported by a tx-only
1404 * Therefore max_cos is also a number of valid entries in the cids
1408 uint8_t num_tx_only, next_tx_only;
1410 enum ecore_q_state state, next_state;
1412 /* bits from enum ecore_q_type */
1415 /* ECORE_Q_CMD_XX bits. This object implements "one
1416 * pending" paradigm but for debug and tracing purposes it's
1417 * more convenient to have different bits for different
1420 unsigned long pending;
1422 /* Buffer to use as a ramrod data and its mapping */
1424 ecore_dma_addr_t rdata_mapping;
1427 * Performs one state change according to the given parameters.
1429 * @return 0 in case of success and negative value otherwise.
1431 int (*send_cmd)(struct bnx2x_softc *sc,
1432 struct ecore_queue_state_params *params);
1435 * Sets the pending bit according to the requested transition.
1437 int (*set_pending)(struct ecore_queue_sp_obj *o,
1438 struct ecore_queue_state_params *params);
1441 * Checks that the requested state transition is legal.
1443 int (*check_transition)(struct bnx2x_softc *sc,
1444 struct ecore_queue_sp_obj *o,
1445 struct ecore_queue_state_params *params);
1448 * Completes the pending command.
1450 int (*complete_cmd)(struct bnx2x_softc *sc,
1451 struct ecore_queue_sp_obj *o,
1452 enum ecore_queue_cmd);
1454 int (*wait_comp)(struct bnx2x_softc *sc,
1455 struct ecore_queue_sp_obj *o,
1456 enum ecore_queue_cmd cmd);
1459 /********************** Function state update *********************************/
1460 /* Allowed Function states */
1461 enum ecore_func_state {
1462 ECORE_F_STATE_RESET,
1463 ECORE_F_STATE_INITIALIZED,
1464 ECORE_F_STATE_STARTED,
1465 ECORE_F_STATE_TX_STOPPED,
1469 /* Allowed Function commands */
1470 enum ecore_func_cmd {
1471 ECORE_F_CMD_HW_INIT,
1474 ECORE_F_CMD_HW_RESET,
1475 ECORE_F_CMD_AFEX_UPDATE,
1476 ECORE_F_CMD_AFEX_VIFLISTS,
1477 ECORE_F_CMD_TX_STOP,
1478 ECORE_F_CMD_TX_START,
1479 ECORE_F_CMD_SWITCH_UPDATE,
1483 struct ecore_func_hw_init_params {
1484 /* A load phase returned by MCP.
1487 * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP
1488 * FW_MSG_CODE_DRV_LOAD_COMMON
1489 * FW_MSG_CODE_DRV_LOAD_PORT
1490 * FW_MSG_CODE_DRV_LOAD_FUNCTION
1492 uint32_t load_phase;
1495 struct ecore_func_hw_reset_params {
1496 /* A load phase returned by MCP.
1499 * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP
1500 * FW_MSG_CODE_DRV_LOAD_COMMON
1501 * FW_MSG_CODE_DRV_LOAD_PORT
1502 * FW_MSG_CODE_DRV_LOAD_FUNCTION
1504 uint32_t reset_phase;
1507 struct ecore_func_start_params {
1508 /* Multi Function mode:
1510 * - Switch Dependent
1511 * - Switch Independent
1515 /* Switch Dependent mode outer VLAN tag */
1516 uint16_t sd_vlan_tag;
1518 /* Function cos mode */
1519 uint8_t network_cos_mode;
1521 /* NVGRE classification enablement */
1522 uint8_t nvgre_clss_en;
1524 /* NO_GRE_TUNNEL/NVGRE_TUNNEL/L2GRE_TUNNEL/IPGRE_TUNNEL */
1525 uint8_t gre_tunnel_mode;
1527 /* GRE_OUTER_HEADERS_RSS/GRE_INNER_HEADERS_RSS/NVGRE_KEY_ENTROPY_RSS */
1528 uint8_t gre_tunnel_rss;
1532 struct ecore_func_switch_update_params {
1536 struct ecore_func_afex_update_params {
1538 uint16_t afex_default_vlan;
1539 uint8_t allowed_priorities;
1542 struct ecore_func_afex_viflists_params {
1543 uint16_t vif_list_index;
1544 uint8_t func_bit_map;
1545 uint8_t afex_vif_list_command;
1546 uint8_t func_to_clear;
1548 struct ecore_func_tx_start_params {
1549 struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES];
1550 uint8_t dcb_enabled;
1551 uint8_t dcb_version;
1552 uint8_t dont_add_pri_0;
1555 struct ecore_func_state_params {
1556 struct ecore_func_sp_obj *f_obj;
1558 /* Current command */
1559 enum ecore_func_cmd cmd;
1561 /* may have RAMROD_COMP_WAIT set only */
1562 unsigned long ramrod_flags;
1564 /* Params according to the current command */
1566 struct ecore_func_hw_init_params hw_init;
1567 struct ecore_func_hw_reset_params hw_reset;
1568 struct ecore_func_start_params start;
1569 struct ecore_func_switch_update_params switch_update;
1570 struct ecore_func_afex_update_params afex_update;
1571 struct ecore_func_afex_viflists_params afex_viflists;
1572 struct ecore_func_tx_start_params tx_start;
1576 struct ecore_func_sp_drv_ops {
1577 /* Init tool + runtime initialization:
1579 * - Common (per Path)
1583 int (*init_hw_cmn_chip)(struct bnx2x_softc *sc);
1584 int (*init_hw_cmn)(struct bnx2x_softc *sc);
1585 int (*init_hw_port)(struct bnx2x_softc *sc);
1586 int (*init_hw_func)(struct bnx2x_softc *sc);
1588 /* Reset Function HW: Common, Port, Function phases. */
1589 void (*reset_hw_cmn)(struct bnx2x_softc *sc);
1590 void (*reset_hw_port)(struct bnx2x_softc *sc);
1591 void (*reset_hw_func)(struct bnx2x_softc *sc);
1593 /* Prepare/Release FW resources */
1594 int (*init_fw)(struct bnx2x_softc *sc);
1595 void (*release_fw)(struct bnx2x_softc *sc);
1598 struct ecore_func_sp_obj {
1599 enum ecore_func_state state, next_state;
1601 /* ECORE_FUNC_CMD_XX bits. This object implements "one
1602 * pending" paradigm but for debug and tracing purposes it's
1603 * more convenient to have different bits for different
1606 unsigned long pending;
1608 /* Buffer to use as a ramrod data and its mapping */
1610 ecore_dma_addr_t rdata_mapping;
1612 /* Buffer to use as a afex ramrod data and its mapping.
1613 * This can't be same rdata as above because afex ramrod requests
1614 * can arrive to the object in parallel to other ramrod requests.
1617 ecore_dma_addr_t afex_rdata_mapping;
1619 /* this mutex validates that when pending flag is taken, the next
1620 * ramrod to be sent will be the one set the pending bit
1622 ECORE_MUTEX one_pending_mutex;
1624 /* Driver interface */
1625 struct ecore_func_sp_drv_ops *drv;
1628 * Performs one state change according to the given parameters.
1630 * @return 0 in case of success and negative value otherwise.
1632 int (*send_cmd)(struct bnx2x_softc *sc,
1633 struct ecore_func_state_params *params);
1636 * Checks that the requested state transition is legal.
1638 int (*check_transition)(struct bnx2x_softc *sc,
1639 struct ecore_func_sp_obj *o,
1640 struct ecore_func_state_params *params);
1643 * Completes the pending command.
1645 int (*complete_cmd)(struct bnx2x_softc *sc,
1646 struct ecore_func_sp_obj *o,
1647 enum ecore_func_cmd cmd);
1649 int (*wait_comp)(struct bnx2x_softc *sc, struct ecore_func_sp_obj *o,
1650 enum ecore_func_cmd cmd);
1653 /********************** Interfaces ********************************************/
1654 /* Queueable objects set */
1655 union ecore_qable_obj {
1656 struct ecore_vlan_mac_obj vlan_mac;
1658 /************** Function state update *********/
1659 void ecore_init_func_obj(struct bnx2x_softc *sc,
1660 struct ecore_func_sp_obj *obj,
1661 void *rdata, ecore_dma_addr_t rdata_mapping,
1662 void *afex_rdata, ecore_dma_addr_t afex_rdata_mapping,
1663 struct ecore_func_sp_drv_ops *drv_iface);
1665 int ecore_func_state_change(struct bnx2x_softc *sc,
1666 struct ecore_func_state_params *params);
1668 enum ecore_func_state ecore_func_get_state(struct bnx2x_softc *sc,
1669 struct ecore_func_sp_obj *o);
1670 /******************* Queue State **************/
1671 void ecore_init_queue_obj(struct bnx2x_softc *sc,
1672 struct ecore_queue_sp_obj *obj, uint8_t cl_id, uint32_t *cids,
1673 uint8_t cid_cnt, uint8_t func_id, void *rdata,
1674 ecore_dma_addr_t rdata_mapping, unsigned long type);
1676 int ecore_queue_state_change(struct bnx2x_softc *sc,
1677 struct ecore_queue_state_params *params);
1679 /********************* VLAN-MAC ****************/
1680 void ecore_init_mac_obj(struct bnx2x_softc *sc,
1681 struct ecore_vlan_mac_obj *mac_obj,
1682 uint8_t cl_id, uint32_t cid, uint8_t func_id, void *rdata,
1683 ecore_dma_addr_t rdata_mapping, int state,
1684 unsigned long *pstate, ecore_obj_type type,
1685 struct ecore_credit_pool_obj *macs_pool);
1687 void ecore_vlan_mac_h_read_unlock(struct bnx2x_softc *sc,
1688 struct ecore_vlan_mac_obj *o);
1689 int ecore_vlan_mac_h_write_lock(struct bnx2x_softc *sc,
1690 struct ecore_vlan_mac_obj *o);
1691 void ecore_vlan_mac_h_write_unlock(struct bnx2x_softc *sc,
1692 struct ecore_vlan_mac_obj *o);
1693 int ecore_config_vlan_mac(struct bnx2x_softc *sc,
1694 struct ecore_vlan_mac_ramrod_params *p);
1696 int ecore_vlan_mac_move(struct bnx2x_softc *sc,
1697 struct ecore_vlan_mac_ramrod_params *p,
1698 struct ecore_vlan_mac_obj *dest_o);
1700 /********************* RX MODE ****************/
1702 void ecore_init_rx_mode_obj(struct bnx2x_softc *sc,
1703 struct ecore_rx_mode_obj *o);
1706 * ecore_config_rx_mode - Send and RX_MODE ramrod according to the provided parameters.
1708 * @p: Command parameters
1710 * Return: 0 - if operation was successful and there is no pending completions,
1711 * positive number - if there are pending completions,
1712 * negative - if there were errors
1714 int ecore_config_rx_mode(struct bnx2x_softc *sc,
1715 struct ecore_rx_mode_ramrod_params *p);
1717 /****************** MULTICASTS ****************/
1719 void ecore_init_mcast_obj(struct bnx2x_softc *sc,
1720 struct ecore_mcast_obj *mcast_obj,
1721 uint8_t mcast_cl_id, uint32_t mcast_cid, uint8_t func_id,
1722 uint8_t engine_id, void *rdata, ecore_dma_addr_t rdata_mapping,
1723 int state, unsigned long *pstate,
1724 ecore_obj_type type);
1727 * ecore_config_mcast - Configure multicast MACs list.
1729 * @cmd: command to execute: BNX2X_MCAST_CMD_X
1731 * May configure a new list
1732 * provided in p->mcast_list (ECORE_MCAST_CMD_ADD), clean up
1733 * (ECORE_MCAST_CMD_DEL) or restore (ECORE_MCAST_CMD_RESTORE) a current
1734 * configuration, continue to execute the pending commands
1735 * (ECORE_MCAST_CMD_CONT).
1737 * If previous command is still pending or if number of MACs to
1738 * configure is more that maximum number of MACs in one command,
1739 * the current command will be enqueued to the tail of the
1740 * pending commands list.
1742 * Return: 0 is operation was successfull and there are no pending completions,
1743 * negative if there were errors, positive if there are pending
1746 int ecore_config_mcast(struct bnx2x_softc *sc,
1747 struct ecore_mcast_ramrod_params *p,
1748 enum ecore_mcast_cmd cmd);
1750 /****************** CREDIT POOL ****************/
1751 void ecore_init_mac_credit_pool(struct bnx2x_softc *sc,
1752 struct ecore_credit_pool_obj *p, uint8_t func_id,
1754 void ecore_init_vlan_credit_pool(struct bnx2x_softc *sc,
1755 struct ecore_credit_pool_obj *p, uint8_t func_id,
1758 /****************** RSS CONFIGURATION ****************/
1759 void ecore_init_rss_config_obj(struct ecore_rss_config_obj *rss_obj,
1760 uint8_t cl_id, uint32_t cid, uint8_t func_id, uint8_t engine_id,
1761 void *rdata, ecore_dma_addr_t rdata_mapping,
1762 int state, unsigned long *pstate,
1763 ecore_obj_type type);
1766 * ecore_config_rss - Updates RSS configuration according to provided parameters
1768 * Return: 0 in case of success
1770 int ecore_config_rss(struct bnx2x_softc *sc,
1771 struct ecore_config_rss_params *p);
1774 #endif /* ECORE_SP_H */