1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2007-2013 Broadcom Corporation.
4 * Eric Davis <edavis@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
6 * Gary Zambrano <zambrano@broadcom.com>
8 * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
9 * Copyright (c) 2015-2018 Cavium Inc.
10 * All rights reserved.
16 #include "ecore_mfw_req.h"
17 #include "ecore_fw_defs.h"
18 #include "ecore_hsi.h"
19 #include "ecore_reg.h"
21 static elink_status_t elink_link_reset(struct elink_params *params,
22 struct elink_vars *vars,
23 uint8_t reset_ext_phy);
24 static elink_status_t elink_check_half_open_conn(struct elink_params *params,
25 struct elink_vars *vars,
27 static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
28 struct elink_params *params);
30 #define MDIO_REG_BANK_CL73_IEEEB0 0x0
31 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0
32 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200
33 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000
34 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000
36 #define MDIO_REG_BANK_CL73_IEEEB1 0x10
37 #define MDIO_CL73_IEEEB1_AN_ADV1 0x00
38 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE 0x0400
39 #define MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC 0x0800
40 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH 0x0C00
41 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK 0x0C00
42 #define MDIO_CL73_IEEEB1_AN_ADV2 0x01
43 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000
44 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020
45 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040
46 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080
47 #define MDIO_CL73_IEEEB1_AN_LP_ADV1 0x03
48 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE 0x0400
49 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC 0x0800
50 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH 0x0C00
51 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK 0x0C00
52 #define MDIO_CL73_IEEEB1_AN_LP_ADV2 0x04
54 #define MDIO_REG_BANK_RX0 0x80b0
55 #define MDIO_RX0_RX_STATUS 0x10
56 #define MDIO_RX0_RX_STATUS_SIGDET 0x8000
57 #define MDIO_RX0_RX_STATUS_RX_SEQ_DONE 0x1000
58 #define MDIO_RX0_RX_EQ_BOOST 0x1c
59 #define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
60 #define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10
62 #define MDIO_REG_BANK_RX1 0x80c0
63 #define MDIO_RX1_RX_EQ_BOOST 0x1c
64 #define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
65 #define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10
67 #define MDIO_REG_BANK_RX2 0x80d0
68 #define MDIO_RX2_RX_EQ_BOOST 0x1c
69 #define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
70 #define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10
72 #define MDIO_REG_BANK_RX3 0x80e0
73 #define MDIO_RX3_RX_EQ_BOOST 0x1c
74 #define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
75 #define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10
77 #define MDIO_REG_BANK_RX_ALL 0x80f0
78 #define MDIO_RX_ALL_RX_EQ_BOOST 0x1c
79 #define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
80 #define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10
82 #define MDIO_REG_BANK_TX0 0x8060
83 #define MDIO_TX0_TX_DRIVER 0x17
84 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
85 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
86 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
87 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
88 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
89 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
90 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
91 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
92 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
94 #define MDIO_REG_BANK_TX1 0x8070
95 #define MDIO_TX1_TX_DRIVER 0x17
96 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
97 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
98 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
99 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
100 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
101 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
102 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
103 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
104 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
106 #define MDIO_REG_BANK_TX2 0x8080
107 #define MDIO_TX2_TX_DRIVER 0x17
108 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
109 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
110 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
111 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
112 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
113 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
114 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
115 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
116 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
118 #define MDIO_REG_BANK_TX3 0x8090
119 #define MDIO_TX3_TX_DRIVER 0x17
120 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
121 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
122 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
123 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
124 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
125 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
126 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
127 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
128 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
130 #define MDIO_REG_BANK_XGXS_BLOCK0 0x8000
131 #define MDIO_BLOCK0_XGXS_CONTROL 0x10
133 #define MDIO_REG_BANK_XGXS_BLOCK1 0x8010
134 #define MDIO_BLOCK1_LANE_CTRL0 0x15
135 #define MDIO_BLOCK1_LANE_CTRL1 0x16
136 #define MDIO_BLOCK1_LANE_CTRL2 0x17
137 #define MDIO_BLOCK1_LANE_PRBS 0x19
139 #define MDIO_REG_BANK_XGXS_BLOCK2 0x8100
140 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10
141 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000
142 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000
143 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11
144 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000
145 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14
146 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001
147 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010
148 #define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15
150 #define MDIO_REG_BANK_GP_STATUS 0x8120
151 #define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B
152 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001
153 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002
154 #define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004
155 #define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008
156 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010
157 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020
158 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040
159 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080
160 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00
161 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000
162 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100
163 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200
164 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300
165 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400
166 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500
167 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600
168 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700
169 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800
170 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900
171 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00
172 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00
173 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00
174 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00
175 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00
176 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR 0x0F00
177 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI 0x1B00
178 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS 0x1E00
179 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI 0x1F00
180 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2 0x3900
182 #define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130
183 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS 0x10
184 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK 0x8000
185 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11
186 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1
187 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13
188 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT (0xb71<<1)
190 #define MDIO_REG_BANK_SERDES_DIGITAL 0x8300
191 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 0x10
192 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x0001
193 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF 0x0002
194 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN 0x0004
195 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x0008
196 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET 0x0010
197 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE 0x0020
198 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 0x11
199 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001
200 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040
201 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14
202 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SGMII 0x0001
203 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_LINK 0x0002
204 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004
205 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018
206 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3
207 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G 0x0018
208 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010
209 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008
210 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000
211 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2 0x15
212 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED 0x0002
213 #define MDIO_SERDES_DIGITAL_MISC1 0x18
214 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000
215 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000
216 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M 0x2000
217 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M 0x4000
218 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M 0x6000
219 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M 0x8000
220 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL 0x0010
221 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK 0x000f
222 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G 0x0000
223 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G 0x0001
224 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G 0x0002
225 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG 0x0003
226 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 0x0004
227 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G 0x0005
228 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G 0x0006
229 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G 0x0007
230 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G 0x0008
231 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G 0x0009
233 #define MDIO_REG_BANK_OVER_1G 0x8320
234 #define MDIO_OVER_1G_DIGCTL_3_4 0x14
235 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK 0xffe0
236 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT 5
237 #define MDIO_OVER_1G_UP1 0x19
238 #define MDIO_OVER_1G_UP1_2_5G 0x0001
239 #define MDIO_OVER_1G_UP1_5G 0x0002
240 #define MDIO_OVER_1G_UP1_6G 0x0004
241 #define MDIO_OVER_1G_UP1_10G 0x0010
242 #define MDIO_OVER_1G_UP1_10GH 0x0008
243 #define MDIO_OVER_1G_UP1_12G 0x0020
244 #define MDIO_OVER_1G_UP1_12_5G 0x0040
245 #define MDIO_OVER_1G_UP1_13G 0x0080
246 #define MDIO_OVER_1G_UP1_15G 0x0100
247 #define MDIO_OVER_1G_UP1_16G 0x0200
248 #define MDIO_OVER_1G_UP2 0x1A
249 #define MDIO_OVER_1G_UP2_IPREDRIVER_MASK 0x0007
250 #define MDIO_OVER_1G_UP2_IDRIVER_MASK 0x0038
251 #define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK 0x03C0
252 #define MDIO_OVER_1G_UP3 0x1B
253 #define MDIO_OVER_1G_UP3_HIGIG2 0x0001
254 #define MDIO_OVER_1G_LP_UP1 0x1C
255 #define MDIO_OVER_1G_LP_UP2 0x1D
256 #define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK 0x03ff
257 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK 0x0780
258 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 7
259 #define MDIO_OVER_1G_LP_UP3 0x1E
261 #define MDIO_REG_BANK_REMOTE_PHY 0x8330
262 #define MDIO_REMOTE_PHY_MISC_RX_STATUS 0x10
263 #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG 0x0010
264 #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG 0x0600
266 #define MDIO_REG_BANK_BAM_NEXT_PAGE 0x8350
267 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10
268 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001
269 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002
271 #define MDIO_REG_BANK_CL73_USERB0 0x8370
272 #define MDIO_CL73_USERB0_CL73_UCTRL 0x10
273 #define MDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL 0x0002
274 #define MDIO_CL73_USERB0_CL73_USTAT1 0x11
275 #define MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK 0x0100
276 #define MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37 0x0400
277 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12
278 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000
279 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000
280 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000
281 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14
282 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001
284 #define MDIO_REG_BANK_AER_BLOCK 0xFFD0
285 #define MDIO_AER_BLOCK_AER_REG 0x1E
287 #define MDIO_REG_BANK_COMBO_IEEE0 0xFFE0
288 #define MDIO_COMBO_IEEE0_MII_CONTROL 0x10
289 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040
290 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000
291 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000
292 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040
293 #define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100
294 #define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200
295 #define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000
296 #define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000
297 #define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000
298 #define MDIO_COMBO_IEEE0_MII_STATUS 0x11
299 #define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004
300 #define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020
301 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV 0x14
302 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020
303 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040
304 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180
305 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000
306 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080
307 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100
308 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180
309 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000
310 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15
311 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000
312 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000
313 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180
314 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE 0x0000
315 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH 0x0180
316 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040
317 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020
318 /*WhenthelinkpartnerisinSGMIImode(bit0=1),then
319 bit15=link,bit12=duplex,bits11:10=speed,bit14=acknowledge.
320 Theotherbitsarereservedandshouldbezero*/
321 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001
323 #define MDIO_PMA_DEVAD 0x1
325 #define MDIO_PMA_REG_CTRL 0x0
326 #define MDIO_PMA_REG_STATUS 0x1
327 #define MDIO_PMA_REG_10G_CTRL2 0x7
328 #define MDIO_PMA_REG_TX_DISABLE 0x0009
329 #define MDIO_PMA_REG_RX_SD 0xa
331 #define MDIO_PMA_REG_BNX2X_CTRL 0x0096
332 #define MDIO_PMA_REG_FEC_CTRL 0x00ab
333 #define MDIO_PMA_LASI_RXCTRL 0x9000
334 #define MDIO_PMA_LASI_TXCTRL 0x9001
335 #define MDIO_PMA_LASI_CTRL 0x9002
336 #define MDIO_PMA_LASI_RXSTAT 0x9003
337 #define MDIO_PMA_LASI_TXSTAT 0x9004
338 #define MDIO_PMA_LASI_STAT 0x9005
339 #define MDIO_PMA_REG_PHY_IDENTIFIER 0xc800
340 #define MDIO_PMA_REG_DIGITAL_CTRL 0xc808
341 #define MDIO_PMA_REG_DIGITAL_STATUS 0xc809
342 #define MDIO_PMA_REG_TX_POWER_DOWN 0xca02
343 #define MDIO_PMA_REG_CMU_PLL_BYPASS 0xca09
344 #define MDIO_PMA_REG_MISC_CTRL 0xca0a
345 #define MDIO_PMA_REG_GEN_CTRL 0xca10
346 #define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188
347 #define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a
348 #define MDIO_PMA_REG_M8051_MSGIN_REG 0xca12
349 #define MDIO_PMA_REG_M8051_MSGOUT_REG 0xca13
350 #define MDIO_PMA_REG_ROM_VER1 0xca19
351 #define MDIO_PMA_REG_ROM_VER2 0xca1a
352 #define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b
353 #define MDIO_PMA_REG_PLL_BANDWIDTH 0xca1d
354 #define MDIO_PMA_REG_PLL_CTRL 0xca1e
355 #define MDIO_PMA_REG_MISC_CTRL0 0xca23
356 #define MDIO_PMA_REG_LRM_MODE 0xca3f
357 #define MDIO_PMA_REG_CDR_BANDWIDTH 0xca46
358 #define MDIO_PMA_REG_MISC_CTRL1 0xca85
360 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL 0x8000
361 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK 0x000c
362 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE 0x0000
363 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE 0x0004
364 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS 0x0008
365 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED 0x000c
366 #define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT 0x8002
367 #define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR 0x8003
368 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF 0xc820
369 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff
370 #define MDIO_PMA_REG_8726_TX_CTRL1 0xca01
371 #define MDIO_PMA_REG_8726_TX_CTRL2 0xca05
373 #define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR 0x8005
374 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF 0x8007
375 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff
376 #define MDIO_PMA_REG_8727_MISC_CTRL 0x8309
377 #define MDIO_PMA_REG_8727_TX_CTRL1 0xca02
378 #define MDIO_PMA_REG_8727_TX_CTRL2 0xca05
379 #define MDIO_PMA_REG_8727_PCS_OPT_CTRL 0xc808
380 #define MDIO_PMA_REG_8727_GPIO_CTRL 0xc80e
381 #define MDIO_PMA_REG_8727_PCS_GP 0xc842
382 #define MDIO_PMA_REG_8727_OPT_CFG_REG 0xc8e4
384 #define MDIO_AN_REG_8727_MISC_CTRL 0x8309
385 #define MDIO_PMA_REG_8073_CHIP_REV 0xc801
386 #define MDIO_PMA_REG_8073_SPEED_LINK_STATUS 0xc820
387 #define MDIO_PMA_REG_8073_XAUI_WA 0xc841
388 #define MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL 0xcd08
390 #define MDIO_PMA_REG_7101_RESET 0xc000
391 #define MDIO_PMA_REG_7107_LED_CNTL 0xc007
392 #define MDIO_PMA_REG_7107_LINK_LED_CNTL 0xc009
393 #define MDIO_PMA_REG_7101_VER1 0xc026
394 #define MDIO_PMA_REG_7101_VER2 0xc027
396 #define MDIO_PMA_REG_8481_PMD_SIGNAL 0xa811
397 #define MDIO_PMA_REG_8481_LED1_MASK 0xa82c
398 #define MDIO_PMA_REG_8481_LED2_MASK 0xa82f
399 #define MDIO_PMA_REG_8481_LED3_MASK 0xa832
400 #define MDIO_PMA_REG_8481_LED3_BLINK 0xa834
401 #define MDIO_PMA_REG_8481_LED5_MASK 0xa838
402 #define MDIO_PMA_REG_8481_SIGNAL_MASK 0xa835
403 #define MDIO_PMA_REG_8481_LINK_SIGNAL 0xa83b
404 #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK 0x800
405 #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT 11
407 #define MDIO_WIS_DEVAD 0x2
409 #define MDIO_WIS_REG_LASI_CNTL 0x9002
410 #define MDIO_WIS_REG_LASI_STATUS 0x9005
412 #define MDIO_PCS_DEVAD 0x3
413 #define MDIO_PCS_REG_STATUS 0x0020
414 #define MDIO_PCS_REG_LASI_STATUS 0x9005
415 #define MDIO_PCS_REG_7101_DSP_ACCESS 0xD000
416 #define MDIO_PCS_REG_7101_SPI_MUX 0xD008
417 #define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A
418 #define MDIO_PCS_REG_7101_SPI_RESET_BIT (5)
419 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A
420 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6)
421 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD (0xC7)
422 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2)
423 #define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028
425 #define MDIO_XS_DEVAD 0x4
426 #define MDIO_XS_REG_STATUS 0x0001
427 #define MDIO_XS_PLL_SEQUENCER 0x8000
428 #define MDIO_XS_SFX7101_XGXS_TEST1 0xc00a
430 #define MDIO_XS_8706_REG_BANK_RX0 0x80bc
431 #define MDIO_XS_8706_REG_BANK_RX1 0x80cc
432 #define MDIO_XS_8706_REG_BANK_RX2 0x80dc
433 #define MDIO_XS_8706_REG_BANK_RX3 0x80ec
434 #define MDIO_XS_8706_REG_BANK_RXA 0x80fc
436 #define MDIO_XS_REG_8073_RX_CTRL_PCIE 0x80FA
438 #define MDIO_AN_DEVAD 0x7
440 #define MDIO_AN_REG_CTRL 0x0000
441 #define MDIO_AN_REG_STATUS 0x0001
442 #define MDIO_AN_REG_STATUS_AN_COMPLETE 0x0020
443 #define MDIO_AN_REG_ADV_PAUSE 0x0010
444 #define MDIO_AN_REG_ADV_PAUSE_PAUSE 0x0400
445 #define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC 0x0800
446 #define MDIO_AN_REG_ADV_PAUSE_BOTH 0x0C00
447 #define MDIO_AN_REG_ADV_PAUSE_MASK 0x0C00
448 #define MDIO_AN_REG_ADV 0x0011
449 #define MDIO_AN_REG_ADV2 0x0012
450 #define MDIO_AN_REG_LP_AUTO_NEG 0x0013
451 #define MDIO_AN_REG_LP_AUTO_NEG2 0x0014
452 #define MDIO_AN_REG_MASTER_STATUS 0x0021
453 #define MDIO_AN_REG_EEE_ADV 0x003c
454 #define MDIO_AN_REG_LP_EEE_ADV 0x003d
456 #define MDIO_AN_REG_LINK_STATUS 0x8304
457 #define MDIO_AN_REG_CL37_CL73 0x8370
458 #define MDIO_AN_REG_CL37_AN 0xffe0
459 #define MDIO_AN_REG_CL37_FC_LD 0xffe4
460 #define MDIO_AN_REG_CL37_FC_LP 0xffe5
461 #define MDIO_AN_REG_1000T_STATUS 0xffea
463 #define MDIO_AN_REG_8073_2_5G 0x8329
464 #define MDIO_AN_REG_8073_BAM 0x8350
466 #define MDIO_AN_REG_8481_10GBASE_T_AN_CTRL 0x0020
467 #define MDIO_AN_REG_8481_LEGACY_MII_CTRL 0xffe0
468 #define MDIO_AN_REG_8481_MII_CTRL_FORCE_1G 0x40
469 #define MDIO_AN_REG_8481_LEGACY_MII_STATUS 0xffe1
470 #define MDIO_AN_REG_8481_LEGACY_AN_ADV 0xffe4
471 #define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION 0xffe6
472 #define MDIO_AN_REG_8481_1000T_CTRL 0xffe9
473 #define MDIO_AN_REG_8481_1G_100T_EXT_CTRL 0xfff0
474 #define MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF 0x0008
475 #define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW 0xfff5
476 #define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS 0xfff7
477 #define MDIO_AN_REG_8481_AUX_CTRL 0xfff8
478 #define MDIO_AN_REG_8481_LEGACY_SHADOW 0xfffc
480 /* BNX2X84823 only */
481 #define MDIO_CTL_DEVAD 0x1e
482 #define MDIO_CTL_REG_84823_MEDIA 0x401a
483 #define MDIO_CTL_REG_84823_MEDIA_MAC_MASK 0x0018
484 /* These pins configure the BNX2X84823 interface to MAC after reset. */
485 #define MDIO_CTL_REG_84823_CTRL_MAC_XFI 0x0008
486 #define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M 0x0010
487 /* These pins configure the BNX2X84823 interface to Line after reset. */
488 #define MDIO_CTL_REG_84823_MEDIA_LINE_MASK 0x0060
489 #define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L 0x0020
490 #define MDIO_CTL_REG_84823_MEDIA_LINE_XFI 0x0040
491 /* When this pin is active high during reset, 10GBASE-T core is power
492 * down, When it is active low the 10GBASE-T is power up
494 #define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN 0x0080
495 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK 0x0100
496 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER 0x0000
497 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER 0x0100
498 #define MDIO_CTL_REG_84823_MEDIA_FIBER_1G 0x1000
499 #define MDIO_CTL_REG_84823_USER_CTRL_REG 0x4005
500 #define MDIO_CTL_REG_84823_USER_CTRL_CMS 0x0080
501 #define MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH 0xa82b
502 #define MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ 0x2f
503 #define MDIO_PMA_REG_84823_CTL_LED_CTL_1 0xa8e3
504 #define MDIO_PMA_REG_84833_CTL_LED_CTL_1 0xa8ec
505 #define MDIO_PMA_REG_84823_LED3_STRETCH_EN 0x0080
507 /* BNX2X84833 only */
508 #define MDIO_84833_TOP_CFG_FW_REV 0x400f
509 #define MDIO_84833_TOP_CFG_FW_EEE 0x10b1
510 #define MDIO_84833_TOP_CFG_FW_NO_EEE 0x1f81
511 #define MDIO_84833_TOP_CFG_XGPHY_STRAP1 0x401a
512 #define MDIO_84833_SUPER_ISOLATE 0x8000
513 /* These are mailbox register set used by 84833. */
514 #define MDIO_84833_TOP_CFG_SCRATCH_REG0 0x4005
515 #define MDIO_84833_TOP_CFG_SCRATCH_REG1 0x4006
516 #define MDIO_84833_TOP_CFG_SCRATCH_REG2 0x4007
517 #define MDIO_84833_TOP_CFG_SCRATCH_REG3 0x4008
518 #define MDIO_84833_TOP_CFG_SCRATCH_REG4 0x4009
519 #define MDIO_84833_TOP_CFG_SCRATCH_REG26 0x4037
520 #define MDIO_84833_TOP_CFG_SCRATCH_REG27 0x4038
521 #define MDIO_84833_TOP_CFG_SCRATCH_REG28 0x4039
522 #define MDIO_84833_TOP_CFG_SCRATCH_REG29 0x403a
523 #define MDIO_84833_TOP_CFG_SCRATCH_REG30 0x403b
524 #define MDIO_84833_TOP_CFG_SCRATCH_REG31 0x403c
525 #define MDIO_84833_CMD_HDLR_COMMAND MDIO_84833_TOP_CFG_SCRATCH_REG0
526 #define MDIO_84833_CMD_HDLR_STATUS MDIO_84833_TOP_CFG_SCRATCH_REG26
527 #define MDIO_84833_CMD_HDLR_DATA1 MDIO_84833_TOP_CFG_SCRATCH_REG27
528 #define MDIO_84833_CMD_HDLR_DATA2 MDIO_84833_TOP_CFG_SCRATCH_REG28
529 #define MDIO_84833_CMD_HDLR_DATA3 MDIO_84833_TOP_CFG_SCRATCH_REG29
530 #define MDIO_84833_CMD_HDLR_DATA4 MDIO_84833_TOP_CFG_SCRATCH_REG30
531 #define MDIO_84833_CMD_HDLR_DATA5 MDIO_84833_TOP_CFG_SCRATCH_REG31
533 /* Mailbox command set used by 84833. */
534 #define PHY84833_CMD_SET_PAIR_SWAP 0x8001
535 #define PHY84833_CMD_GET_EEE_MODE 0x8008
536 #define PHY84833_CMD_SET_EEE_MODE 0x8009
537 #define PHY84833_CMD_GET_CURRENT_TEMP 0x8031
538 /* Mailbox status set used by 84833. */
539 #define PHY84833_STATUS_CMD_RECEIVED 0x0001
540 #define PHY84833_STATUS_CMD_IN_PROGRESS 0x0002
541 #define PHY84833_STATUS_CMD_COMPLETE_PASS 0x0004
542 #define PHY84833_STATUS_CMD_COMPLETE_ERROR 0x0008
543 #define PHY84833_STATUS_CMD_OPEN_FOR_CMDS 0x0010
544 #define PHY84833_STATUS_CMD_SYSTEM_BOOT 0x0020
545 #define PHY84833_STATUS_CMD_NOT_OPEN_FOR_CMDS 0x0040
546 #define PHY84833_STATUS_CMD_CLEAR_COMPLETE 0x0080
547 #define PHY84833_STATUS_CMD_OPEN_OVERRIDE 0xa5a5
549 /* Warpcore clause 45 addressing */
550 #define MDIO_WC_DEVAD 0x3
551 #define MDIO_WC_REG_IEEE0BLK_MIICNTL 0x0
552 #define MDIO_WC_REG_IEEE0BLK_AUTONEGNP 0x7
553 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT0 0x10
554 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1 0x11
555 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2 0x12
556 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY 0x4000
557 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ 0x8000
558 #define MDIO_WC_REG_PCS_STATUS2 0x0021
559 #define MDIO_WC_REG_PMD_KR_CONTROL 0x0096
560 #define MDIO_WC_REG_XGXSBLK0_XGXSCONTROL 0x8000
561 #define MDIO_WC_REG_XGXSBLK0_MISCCONTROL1 0x800e
562 #define MDIO_WC_REG_XGXSBLK1_DESKEW 0x8010
563 #define MDIO_WC_REG_XGXSBLK1_LANECTRL0 0x8015
564 #define MDIO_WC_REG_XGXSBLK1_LANECTRL1 0x8016
565 #define MDIO_WC_REG_XGXSBLK1_LANECTRL2 0x8017
566 #define MDIO_WC_REG_XGXSBLK1_LANECTRL3 0x8018
567 #define MDIO_WC_REG_XGXSBLK1_LANETEST0 0x801a
568 #define MDIO_WC_REG_TX0_ANA_CTRL0 0x8061
569 #define MDIO_WC_REG_TX1_ANA_CTRL0 0x8071
570 #define MDIO_WC_REG_TX2_ANA_CTRL0 0x8081
571 #define MDIO_WC_REG_TX3_ANA_CTRL0 0x8091
572 #define MDIO_WC_REG_TX0_TX_DRIVER 0x8067
573 #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET 0x04
574 #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_MASK 0x00f0
575 #define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET 0x08
576 #define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
577 #define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET 0x0c
578 #define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_MASK 0x7000
579 #define MDIO_WC_REG_TX1_TX_DRIVER 0x8077
580 #define MDIO_WC_REG_TX2_TX_DRIVER 0x8087
581 #define MDIO_WC_REG_TX3_TX_DRIVER 0x8097
582 #define MDIO_WC_REG_RX0_ANARXCONTROL1G 0x80b9
583 #define MDIO_WC_REG_RX2_ANARXCONTROL1G 0x80d9
584 #define MDIO_WC_REG_RX0_PCI_CTRL 0x80ba
585 #define MDIO_WC_REG_RX1_PCI_CTRL 0x80ca
586 #define MDIO_WC_REG_RX2_PCI_CTRL 0x80da
587 #define MDIO_WC_REG_RX3_PCI_CTRL 0x80ea
588 #define MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G 0x8104
589 #define MDIO_WC_REG_XGXS_STATUS3 0x8129
590 #define MDIO_WC_REG_PAR_DET_10G_STATUS 0x8130
591 #define MDIO_WC_REG_PAR_DET_10G_CTRL 0x8131
592 #define MDIO_WC_REG_XGXS_STATUS4 0x813c
593 #define MDIO_WC_REG_XGXS_X2_CONTROL2 0x8141
594 #define MDIO_WC_REG_XGXS_X2_CONTROL3 0x8142
595 #define MDIO_WC_REG_XGXS_RX_LN_SWAP1 0x816B
596 #define MDIO_WC_REG_XGXS_TX_LN_SWAP1 0x8169
597 #define MDIO_WC_REG_GP2_STATUS_GP_2_0 0x81d0
598 #define MDIO_WC_REG_GP2_STATUS_GP_2_1 0x81d1
599 #define MDIO_WC_REG_GP2_STATUS_GP_2_2 0x81d2
600 #define MDIO_WC_REG_GP2_STATUS_GP_2_3 0x81d3
601 #define MDIO_WC_REG_GP2_STATUS_GP_2_4 0x81d4
602 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL 0x1000
603 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CMPL 0x0100
604 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP 0x0010
605 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CAP 0x1
606 #define MDIO_WC_REG_UC_INFO_B0_DEAD_TRAP 0x81EE
607 #define MDIO_WC_REG_UC_INFO_B1_VERSION 0x81F0
608 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE 0x81F2
609 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE0_OFFSET 0x0
610 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT 0x0
611 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_OPT_LR 0x1
612 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC 0x2
613 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_XLAUI 0x3
614 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_LONG_CH_6G 0x4
615 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE1_OFFSET 0x4
616 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE2_OFFSET 0x8
617 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE3_OFFSET 0xc
618 #define MDIO_WC_REG_UC_INFO_B1_CRC 0x81FE
619 #define MDIO_WC_REG_DSC1B0_UC_CTRL 0x820e
620 #define MDIO_WC_REG_DSC1B0_UC_CTRL_RDY4CMD (1<<7)
621 #define MDIO_WC_REG_DSC_SMC 0x8213
622 #define MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0 0x821e
623 #define MDIO_WC_REG_TX_FIR_TAP 0x82e2
624 #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET 0x00
625 #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_MASK 0x000f
626 #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET 0x04
627 #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_MASK 0x03f0
628 #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET 0x0a
629 #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_MASK 0x7c00
630 #define MDIO_WC_REG_TX_FIR_TAP_ENABLE 0x8000
631 #define MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP 0x82e2
632 #define MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL 0x82e3
633 #define MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL 0x82e6
634 #define MDIO_WC_REG_CL72_USERB0_CL72_BR_DEF_CTRL 0x82e7
635 #define MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL 0x82e8
636 #define MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL 0x82ec
637 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1 0x8300
638 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2 0x8301
639 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3 0x8302
640 #define MDIO_WC_REG_SERDESDIGITAL_STATUS1000X1 0x8304
641 #define MDIO_WC_REG_SERDESDIGITAL_MISC1 0x8308
642 #define MDIO_WC_REG_SERDESDIGITAL_MISC2 0x8309
643 #define MDIO_WC_REG_DIGITAL3_UP1 0x8329
644 #define MDIO_WC_REG_DIGITAL3_LP_UP1 0x832c
645 #define MDIO_WC_REG_DIGITAL4_MISC3 0x833c
646 #define MDIO_WC_REG_DIGITAL4_MISC5 0x833e
647 #define MDIO_WC_REG_DIGITAL5_MISC6 0x8345
648 #define MDIO_WC_REG_DIGITAL5_MISC7 0x8349
649 #define MDIO_WC_REG_DIGITAL5_LINK_STATUS 0x834d
650 #define MDIO_WC_REG_DIGITAL5_ACTUAL_SPEED 0x834e
651 #define MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL 0x8350
652 #define MDIO_WC_REG_CL49_USERB0_CTRL 0x8368
653 #define MDIO_WC_REG_CL73_USERB0_CTRL 0x8370
654 #define MDIO_WC_REG_CL73_USERB0_USTAT 0x8371
655 #define MDIO_WC_REG_CL73_BAM_CTRL1 0x8372
656 #define MDIO_WC_REG_CL73_BAM_CTRL2 0x8373
657 #define MDIO_WC_REG_CL73_BAM_CTRL3 0x8374
658 #define MDIO_WC_REG_CL73_BAM_CODE_FIELD 0x837b
659 #define MDIO_WC_REG_EEE_COMBO_CONTROL0 0x8390
660 #define MDIO_WC_REG_TX66_CONTROL 0x83b0
661 #define MDIO_WC_REG_RX66_CONTROL 0x83c0
662 #define MDIO_WC_REG_RX66_SCW0 0x83c2
663 #define MDIO_WC_REG_RX66_SCW1 0x83c3
664 #define MDIO_WC_REG_RX66_SCW2 0x83c4
665 #define MDIO_WC_REG_RX66_SCW3 0x83c5
666 #define MDIO_WC_REG_RX66_SCW0_MASK 0x83c6
667 #define MDIO_WC_REG_RX66_SCW1_MASK 0x83c7
668 #define MDIO_WC_REG_RX66_SCW2_MASK 0x83c8
669 #define MDIO_WC_REG_RX66_SCW3_MASK 0x83c9
670 #define MDIO_WC_REG_FX100_CTRL1 0x8400
671 #define MDIO_WC_REG_FX100_CTRL3 0x8402
672 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL5 0x8436
673 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL6 0x8437
674 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL7 0x8438
675 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL9 0x8439
676 #define MDIO_WC_REG_CL82_USERB1_RX_CTRL10 0x843a
677 #define MDIO_WC_REG_CL82_USERB1_RX_CTRL11 0x843b
678 #define MDIO_WC_REG_ETA_CL73_OUI1 0x8453
679 #define MDIO_WC_REG_ETA_CL73_OUI2 0x8454
680 #define MDIO_WC_REG_ETA_CL73_OUI3 0x8455
681 #define MDIO_WC_REG_ETA_CL73_LD_BAM_CODE 0x8456
682 #define MDIO_WC_REG_ETA_CL73_LD_UD_CODE 0x8457
683 #define MDIO_WC_REG_MICROBLK_CMD 0xffc2
684 #define MDIO_WC_REG_MICROBLK_DL_STATUS 0xffc5
685 #define MDIO_WC_REG_MICROBLK_CMD3 0xffcc
687 #define MDIO_WC_REG_AERBLK_AER 0xffde
688 #define MDIO_WC_REG_COMBO_IEEE0_MIICTRL 0xffe0
689 #define MDIO_WC_REG_COMBO_IEEE0_MIIISTAT 0xffe1
691 #define MDIO_WC0_XGXS_BLK2_LANE_RESET 0x810A
692 #define MDIO_WC0_XGXS_BLK2_LANE_RESET_RX_BITSHIFT 0
693 #define MDIO_WC0_XGXS_BLK2_LANE_RESET_TX_BITSHIFT 4
695 #define MDIO_WC0_XGXS_BLK6_XGXS_X2_CONTROL2 0x8141
697 #define DIGITAL5_ACTUAL_SPEED_TX_MASK 0x003f
700 #define MDIO_REG_GPHY_MII_STATUS 0x1
701 #define MDIO_REG_GPHY_PHYID_LSB 0x3
702 #define MDIO_REG_GPHY_CL45_ADDR_REG 0xd
703 #define MDIO_REG_GPHY_CL45_REG_WRITE 0x4000
704 #define MDIO_REG_GPHY_CL45_REG_READ 0xc000
705 #define MDIO_REG_GPHY_CL45_DATA_REG 0xe
706 #define MDIO_REG_GPHY_EEE_RESOLVED 0x803e
707 #define MDIO_REG_GPHY_EXP_ACCESS_GATE 0x15
708 #define MDIO_REG_GPHY_EXP_ACCESS 0x17
709 #define MDIO_REG_GPHY_EXP_ACCESS_TOP 0xd00
710 #define MDIO_REG_GPHY_EXP_TOP_2K_BUF 0x40
711 #define MDIO_REG_GPHY_AUX_STATUS 0x19
712 #define MDIO_REG_INTR_STATUS 0x1a
713 #define MDIO_REG_INTR_MASK 0x1b
714 #define MDIO_REG_INTR_MASK_LINK_STATUS (0x1 << 1)
715 #define MDIO_REG_GPHY_SHADOW 0x1c
716 #define MDIO_REG_GPHY_SHADOW_LED_SEL1 (0x0d << 10)
717 #define MDIO_REG_GPHY_SHADOW_LED_SEL2 (0x0e << 10)
718 #define MDIO_REG_GPHY_SHADOW_WR_ENA (0x1 << 15)
719 #define MDIO_REG_GPHY_SHADOW_AUTO_DET_MED (0x1e << 10)
720 #define MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD (0x1 << 8)
722 typedef elink_status_t(*read_sfp_module_eeprom_func_p) (struct elink_phy * phy,
723 struct elink_params *
730 /********************************************************/
731 #define ELINK_ETH_HLEN 14
732 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
733 #define ELINK_ETH_OVREHEAD (ELINK_ETH_HLEN + 8 + 8)
734 #define ELINK_ETH_MIN_PACKET_SIZE 60
735 #define ELINK_ETH_MAX_PACKET_SIZE 1500
736 #define ELINK_ETH_MAX_JUMBO_PACKET_SIZE 9600
737 #define ELINK_MDIO_ACCESS_TIMEOUT 1000
738 #define WC_LANE_MAX 4
739 #define I2C_SWITCH_WIDTH 2
742 #define I2C_WA_RETRY_CNT 3
743 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1)
744 #define MCPR_IMC_COMMAND_READ_OP 1
745 #define MCPR_IMC_COMMAND_WRITE_OP 2
747 /* LED Blink rate that will achieve ~15.9Hz */
748 #define LED_BLINK_RATE_VAL_E3 354
749 #define LED_BLINK_RATE_VAL_E1X_E2 480
750 /***********************************************************/
751 /* Shortcut definitions */
752 /***********************************************************/
754 #define ELINK_NIG_LATCH_BC_ENABLE_MI_INT 0
756 #define ELINK_NIG_STATUS_EMAC0_MI_INT \
757 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
758 #define ELINK_NIG_STATUS_XGXS0_LINK10G \
759 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
760 #define ELINK_NIG_STATUS_XGXS0_LINK_STATUS \
761 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
762 #define ELINK_NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
763 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
764 #define ELINK_NIG_STATUS_SERDES0_LINK_STATUS \
765 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
766 #define ELINK_NIG_MASK_MI_INT \
767 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
768 #define ELINK_NIG_MASK_XGXS0_LINK10G \
769 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
770 #define ELINK_NIG_MASK_XGXS0_LINK_STATUS \
771 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
772 #define ELINK_NIG_MASK_SERDES0_LINK_STATUS \
773 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
775 #define ELINK_MDIO_AN_CL73_OR_37_COMPLETE \
776 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
777 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
779 #define ELINK_XGXS_RESET_BITS \
780 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
781 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
782 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
783 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
784 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
786 #define ELINK_SERDES_RESET_BITS \
787 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
788 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
789 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
790 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
792 #define ELINK_AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
793 #define ELINK_AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
794 #define ELINK_AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
795 #define ELINK_AUTONEG_PARALLEL \
796 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
797 #define ELINK_AUTONEG_SGMII_FIBER_AUTODET \
798 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
799 #define ELINK_AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
801 #define ELINK_GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
802 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
803 #define ELINK_GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
804 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
805 #define ELINK_GP_STATUS_SPEED_MASK \
806 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
807 #define ELINK_GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
808 #define ELINK_GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
809 #define ELINK_GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
810 #define ELINK_GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
811 #define ELINK_GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
812 #define ELINK_GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
813 #define ELINK_GP_STATUS_10G_HIG \
814 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
815 #define ELINK_GP_STATUS_10G_CX4 \
816 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
817 #define ELINK_GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
818 #define ELINK_GP_STATUS_10G_KX4 \
819 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
820 #define ELINK_GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR
821 #define ELINK_GP_STATUS_10G_XFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI
822 #define ELINK_GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS
823 #define ELINK_GP_STATUS_10G_SFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI
824 #define ELINK_GP_STATUS_20G_KR2 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2
825 #define ELINK_LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
826 #define ELINK_LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
827 #define ELINK_LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
828 #define ELINK_LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
829 #define ELINK_LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
830 #define ELINK_LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
831 #define ELINK_LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
832 #define ELINK_LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
833 #define ELINK_LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
834 #define ELINK_LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
835 #define ELINK_LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
836 #define ELINK_LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
837 #define ELINK_LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
838 #define ELINK_LINK_20GTFD LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
839 #define ELINK_LINK_20GXFD LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
841 #define ELINK_LINK_UPDATE_MASK \
842 (LINK_STATUS_SPEED_AND_DUPLEX_MASK | \
843 LINK_STATUS_LINK_UP | \
844 LINK_STATUS_PHYSICAL_LINK_FLAG | \
845 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE | \
846 LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK | \
847 LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK | \
848 LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK | \
849 LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE | \
850 LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
852 #define ELINK_SFP_EEPROM_CON_TYPE_ADDR 0x2
853 #define ELINK_SFP_EEPROM_CON_TYPE_VAL_LC 0x7
854 #define ELINK_SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
855 #define ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45 0x22
857 #define ELINK_SFP_EEPROM_COMP_CODE_ADDR 0x3
858 #define ELINK_SFP_EEPROM_COMP_CODE_SR_MASK (1<<4)
859 #define ELINK_SFP_EEPROM_COMP_CODE_LR_MASK (1<<5)
860 #define ELINK_SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6)
862 #define ELINK_SFP_EEPROM_FC_TX_TECH_ADDR 0x8
863 #define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
864 #define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
866 #define ELINK_SFP_EEPROM_OPTIONS_ADDR 0x40
867 #define ELINK_SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
868 #define ELINK_SFP_EEPROM_OPTIONS_SIZE 2
870 #define ELINK_EDC_MODE_LINEAR 0x0022
871 #define ELINK_EDC_MODE_LIMITING 0x0044
872 #define ELINK_EDC_MODE_PASSIVE_DAC 0x0055
873 #define ELINK_EDC_MODE_ACTIVE_DAC 0x0066
876 #define DCBX_INVALID_COS (0xFF)
878 #define ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000)
879 #define ELINK_ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000)
880 #define ELINK_ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS (1360)
881 #define ELINK_ETS_E3B0_NIG_MIN_W_VAL_20GBPS (2720)
882 #define ELINK_ETS_E3B0_PBF_MIN_W_VAL (10000)
884 #define ELINK_MAX_PACKET_SIZE (9700)
885 #define MAX_KR_LINK_RETRY 4
887 /**********************************************************/
889 /**********************************************************/
891 #define CL22_WR_OVER_CL45(_sc, _phy, _bank, _addr, _val) \
892 elink_cl45_write(_sc, _phy, \
893 (_phy)->def_md_devad, \
894 (_bank + (_addr & 0xf)), \
897 #define CL22_RD_OVER_CL45(_sc, _phy, _bank, _addr, _val) \
898 elink_cl45_read(_sc, _phy, \
899 (_phy)->def_md_devad, \
900 (_bank + (_addr & 0xf)), \
903 static uint32_t elink_bits_en(struct bnx2x_softc *sc, uint32_t reg, uint32_t bits)
905 uint32_t val = REG_RD(sc, reg);
908 REG_WR(sc, reg, val);
912 static uint32_t elink_bits_dis(struct bnx2x_softc *sc, uint32_t reg,
915 uint32_t val = REG_RD(sc, reg);
918 REG_WR(sc, reg, val);
923 * elink_check_lfa - This function checks if link reinitialization is required,
924 * or link flap can be avoided.
926 * @params: link parameters
927 * Returns 0 if Link Flap Avoidance conditions are met otherwise, the failed
930 static int elink_check_lfa(struct elink_params *params)
932 uint32_t link_status, cfg_idx, lfa_mask, cfg_size;
933 uint32_t cur_speed_cap_mask, cur_req_fc_auto_adv, additional_config;
934 uint32_t saved_val, req_val, eee_status;
935 struct bnx2x_softc *sc = params->sc;
938 REG_RD(sc, params->lfa_base +
939 offsetof(struct shmem_lfa, additional_config));
941 /* NOTE: must be first condition checked -
942 * to verify DCC bit is cleared in any case!
944 if (additional_config & NO_LFA_DUE_TO_DCC_MASK) {
945 PMD_DRV_LOG(DEBUG, sc, "No LFA due to DCC flap after clp exit");
946 REG_WR(sc, params->lfa_base +
947 offsetof(struct shmem_lfa, additional_config),
948 additional_config & ~NO_LFA_DUE_TO_DCC_MASK);
949 return LFA_DCC_LFA_DISABLED;
952 /* Verify that link is up */
953 link_status = REG_RD(sc, params->shmem_base +
954 offsetof(struct shmem_region,
955 port_mb[params->port].link_status));
956 if (!(link_status & LINK_STATUS_LINK_UP))
957 return LFA_LINK_DOWN;
959 /* if loaded after BOOT from SAN, don't flap the link in any case and
960 * rely on link set by preboot driver
962 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_BOOT_FROM_SAN)
965 /* Verify that loopback mode is not set */
966 if (params->loopback_mode)
967 return LFA_LOOPBACK_ENABLED;
969 /* Verify that MFW supports LFA */
970 if (!params->lfa_base)
971 return LFA_MFW_IS_TOO_OLD;
973 if (params->num_phys == 3) {
975 lfa_mask = 0xffffffff;
982 saved_val = REG_RD(sc, params->lfa_base +
983 offsetof(struct shmem_lfa, req_duplex));
984 req_val = params->req_duplex[0] | (params->req_duplex[1] << 16);
985 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
986 PMD_DRV_LOG(INFO, sc, "Duplex mismatch %x vs. %x",
987 (saved_val & lfa_mask), (req_val & lfa_mask));
988 return LFA_DUPLEX_MISMATCH;
990 /* Compare Flow Control */
991 saved_val = REG_RD(sc, params->lfa_base +
992 offsetof(struct shmem_lfa, req_flow_ctrl));
993 req_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16);
994 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
995 PMD_DRV_LOG(DEBUG, sc, "Flow control mismatch %x vs. %x",
996 (saved_val & lfa_mask), (req_val & lfa_mask));
997 return LFA_FLOW_CTRL_MISMATCH;
999 /* Compare Link Speed */
1000 saved_val = REG_RD(sc, params->lfa_base +
1001 offsetof(struct shmem_lfa, req_line_speed));
1002 req_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16);
1003 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
1004 PMD_DRV_LOG(DEBUG, sc, "Link speed mismatch %x vs. %x",
1005 (saved_val & lfa_mask), (req_val & lfa_mask));
1006 return LFA_LINK_SPEED_MISMATCH;
1009 for (cfg_idx = 0; cfg_idx < cfg_size; cfg_idx++) {
1010 cur_speed_cap_mask = REG_RD(sc, params->lfa_base +
1011 offsetof(struct shmem_lfa,
1012 speed_cap_mask[cfg_idx]));
1014 if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) {
1015 PMD_DRV_LOG(DEBUG, sc, "Speed Cap mismatch %x vs. %x",
1017 params->speed_cap_mask[cfg_idx]);
1018 return LFA_SPEED_CAP_MISMATCH;
1022 cur_req_fc_auto_adv =
1023 REG_RD(sc, params->lfa_base +
1024 offsetof(struct shmem_lfa, additional_config)) &
1025 REQ_FC_AUTO_ADV_MASK;
1027 if ((uint16_t) cur_req_fc_auto_adv != params->req_fc_auto_adv) {
1028 PMD_DRV_LOG(DEBUG, sc, "Flow Ctrl AN mismatch %x vs. %x",
1029 cur_req_fc_auto_adv, params->req_fc_auto_adv);
1030 return LFA_FLOW_CTRL_MISMATCH;
1033 eee_status = REG_RD(sc, params->shmem2_base +
1034 offsetof(struct shmem2_region,
1035 eee_status[params->port]));
1037 if (((eee_status & SHMEM_EEE_LPI_REQUESTED_BIT) ^
1038 (params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI)) ||
1039 ((eee_status & SHMEM_EEE_REQUESTED_BIT) ^
1040 (params->eee_mode & ELINK_EEE_MODE_ADV_LPI))) {
1041 PMD_DRV_LOG(DEBUG, sc,
1042 "EEE mismatch %x vs. %x", params->eee_mode,
1044 return LFA_EEE_MISMATCH;
1047 /* LFA conditions are met */
1051 /******************************************************************/
1052 /* EPIO/GPIO section */
1053 /******************************************************************/
1054 static void elink_get_epio(struct bnx2x_softc *sc, uint32_t epio_pin,
1057 uint32_t epio_mask, gp_oenable;
1060 if (epio_pin > 31) {
1061 PMD_DRV_LOG(DEBUG, sc, "Invalid EPIO pin %d to get", epio_pin);
1065 epio_mask = 1 << epio_pin;
1066 /* Set this EPIO to output */
1067 gp_oenable = REG_RD(sc, MCP_REG_MCPR_GP_OENABLE);
1068 REG_WR(sc, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask);
1070 *en = (REG_RD(sc, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;
1073 static void elink_set_epio(struct bnx2x_softc *sc, uint32_t epio_pin, uint32_t en)
1075 uint32_t epio_mask, gp_output, gp_oenable;
1078 if (epio_pin > 31) {
1079 PMD_DRV_LOG(DEBUG, sc, "Invalid EPIO pin %d to set", epio_pin);
1082 PMD_DRV_LOG(DEBUG, sc, "Setting EPIO pin %d to %d", epio_pin, en);
1083 epio_mask = 1 << epio_pin;
1084 /* Set this EPIO to output */
1085 gp_output = REG_RD(sc, MCP_REG_MCPR_GP_OUTPUTS);
1087 gp_output |= epio_mask;
1089 gp_output &= ~epio_mask;
1091 REG_WR(sc, MCP_REG_MCPR_GP_OUTPUTS, gp_output);
1093 /* Set the value for this EPIO */
1094 gp_oenable = REG_RD(sc, MCP_REG_MCPR_GP_OENABLE);
1095 REG_WR(sc, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask);
1098 static void elink_set_cfg_pin(struct bnx2x_softc *sc, uint32_t pin_cfg,
1101 if (pin_cfg == PIN_CFG_NA)
1103 if (pin_cfg >= PIN_CFG_EPIO0) {
1104 elink_set_epio(sc, pin_cfg - PIN_CFG_EPIO0, val);
1106 uint8_t gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
1107 uint8_t gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
1108 elink_cb_gpio_write(sc, gpio_num, (uint8_t) val, gpio_port);
1112 static uint32_t elink_get_cfg_pin(struct bnx2x_softc *sc, uint32_t pin_cfg,
1115 if (pin_cfg == PIN_CFG_NA)
1116 return ELINK_STATUS_ERROR;
1117 if (pin_cfg >= PIN_CFG_EPIO0) {
1118 elink_get_epio(sc, pin_cfg - PIN_CFG_EPIO0, val);
1120 uint8_t gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
1121 uint8_t gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
1122 *val = elink_cb_gpio_read(sc, gpio_num, gpio_port);
1124 return ELINK_STATUS_OK;
1128 /******************************************************************/
1130 /******************************************************************/
1131 static void elink_update_pfc_xmac(struct elink_params *params,
1132 struct elink_vars *vars)
1134 struct bnx2x_softc *sc = params->sc;
1136 uint32_t pause_val, pfc0_val, pfc1_val;
1138 /* XMAC base adrr */
1139 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1141 /* Initialize pause and pfc registers */
1142 pause_val = 0x18000;
1143 pfc0_val = 0xFFFF8000;
1146 /* No PFC support */
1147 if (!(params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)) {
1149 /* RX flow control - Process pause frame in receive direction
1151 if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)
1152 pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN;
1154 /* TX flow control - Send pause packet when buffer is full */
1155 if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)
1156 pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;
1157 } else { /* PFC support */
1158 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN |
1159 XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
1160 XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
1161 XMAC_PFC_CTRL_HI_REG_TX_PFC_EN |
1162 XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1163 /* Write pause and PFC registers */
1164 REG_WR(sc, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1165 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1166 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1167 pfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1171 /* Write pause and PFC registers */
1172 REG_WR(sc, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1173 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1174 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1176 /* Set MAC address for source TX Pause/PFC frames */
1177 REG_WR(sc, xmac_base + XMAC_REG_CTRL_SA_LO,
1178 ((params->mac_addr[2] << 24) |
1179 (params->mac_addr[3] << 16) |
1180 (params->mac_addr[4] << 8) | (params->mac_addr[5])));
1181 REG_WR(sc, xmac_base + XMAC_REG_CTRL_SA_HI,
1182 ((params->mac_addr[0] << 8) | (params->mac_addr[1])));
1187 /******************************************************************/
1188 /* MAC/PBF section */
1189 /******************************************************************/
1190 static void elink_set_mdio_clk(struct bnx2x_softc *sc, uint32_t emac_base)
1192 uint32_t new_mode, cur_mode;
1194 /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1195 * (a value of 49==0x31) and make sure that the AUTO poll is off
1197 cur_mode = REG_RD(sc, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1199 if (USES_WARPCORE(sc))
1200 clc_cnt = 74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
1202 clc_cnt = 49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
1204 if (((cur_mode & EMAC_MDIO_MODE_CLOCK_CNT) == clc_cnt) &&
1205 (cur_mode & (EMAC_MDIO_MODE_CLAUSE_45)))
1208 new_mode = cur_mode &
1209 ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT);
1210 new_mode |= clc_cnt;
1211 new_mode |= (EMAC_MDIO_MODE_CLAUSE_45);
1213 PMD_DRV_LOG(DEBUG, sc, "Changing emac_mode from 0x%x to 0x%x",
1214 cur_mode, new_mode);
1215 REG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode);
1219 static void elink_set_mdio_emac_per_phy(struct bnx2x_softc *sc,
1220 struct elink_params *params)
1223 /* Set mdio clock per phy */
1224 for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys;
1226 elink_set_mdio_clk(sc, params->phy[phy_index].mdio_ctrl);
1229 static uint8_t elink_is_4_port_mode(struct bnx2x_softc *sc)
1231 uint32_t port4mode_ovwr_val;
1232 /* Check 4-port override enabled */
1233 port4mode_ovwr_val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);
1234 if (port4mode_ovwr_val & (1 << 0)) {
1235 /* Return 4-port mode override value */
1236 return (port4mode_ovwr_val & (1 << 1)) == (1 << 1);
1238 /* Return 4-port mode from input pin */
1239 return (uint8_t) REG_RD(sc, MISC_REG_PORT4MODE_EN);
1242 static void elink_emac_init(struct elink_params *params)
1244 /* reset and unreset the emac core */
1245 struct bnx2x_softc *sc = params->sc;
1246 uint8_t port = params->port;
1247 uint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1251 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1252 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1254 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1255 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1257 /* init emac - use read-modify-write */
1258 /* self clear reset */
1259 val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);
1260 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MODE,
1261 (val | EMAC_MODE_RESET));
1265 val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);
1266 PMD_DRV_LOG(DEBUG, sc, "EMAC reset reg is %u", val);
1268 PMD_DRV_LOG(DEBUG, sc, "EMAC timeout!");
1272 } while (val & EMAC_MODE_RESET);
1274 elink_set_mdio_emac_per_phy(sc, params);
1275 /* Set mac address */
1276 val = ((params->mac_addr[0] << 8) | params->mac_addr[1]);
1277 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MAC_MATCH, val);
1279 val = ((params->mac_addr[2] << 24) |
1280 (params->mac_addr[3] << 16) |
1281 (params->mac_addr[4] << 8) | params->mac_addr[5]);
1282 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MAC_MATCH + 4, val);
1285 static void elink_set_xumac_nig(struct elink_params *params,
1286 uint16_t tx_pause_en, uint8_t enable)
1288 struct bnx2x_softc *sc = params->sc;
1290 REG_WR(sc, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
1292 REG_WR(sc, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
1294 REG_WR(sc, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
1295 NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en);
1298 static void elink_set_umac_rxtx(struct elink_params *params, uint8_t en)
1300 uint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1302 struct bnx2x_softc *sc = params->sc;
1303 if (!(REG_RD(sc, MISC_REG_RESET_REG_2) &
1304 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)))
1306 val = REG_RD(sc, umac_base + UMAC_REG_COMMAND_CONFIG);
1308 val |= (UMAC_COMMAND_CONFIG_REG_TX_ENA |
1309 UMAC_COMMAND_CONFIG_REG_RX_ENA);
1311 val &= ~(UMAC_COMMAND_CONFIG_REG_TX_ENA |
1312 UMAC_COMMAND_CONFIG_REG_RX_ENA);
1313 /* Disable RX and TX */
1314 REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1317 static void elink_umac_enable(struct elink_params *params,
1318 struct elink_vars *vars, uint8_t lb)
1321 uint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1322 struct bnx2x_softc *sc = params->sc;
1324 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1325 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1328 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1329 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1331 PMD_DRV_LOG(DEBUG, sc, "enabling UMAC");
1333 /* This register opens the gate for the UMAC despite its name */
1334 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port * 4, 1);
1336 val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN |
1337 UMAC_COMMAND_CONFIG_REG_PAD_EN |
1338 UMAC_COMMAND_CONFIG_REG_SW_RESET |
1339 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
1340 switch (vars->line_speed) {
1341 case ELINK_SPEED_10:
1344 case ELINK_SPEED_100:
1347 case ELINK_SPEED_1000:
1350 case ELINK_SPEED_2500:
1354 PMD_DRV_LOG(DEBUG, sc, "Invalid speed for UMAC %d",
1358 if (!(vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
1359 val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE;
1361 if (!(vars->flow_ctrl & ELINK_FLOW_CTRL_RX))
1362 val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE;
1364 if (vars->duplex == DUPLEX_HALF)
1365 val |= UMAC_COMMAND_CONFIG_REG_HD_ENA;
1367 REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1370 /* Configure UMAC for EEE */
1371 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
1372 PMD_DRV_LOG(DEBUG, sc, "configured UMAC for EEE");
1373 REG_WR(sc, umac_base + UMAC_REG_UMAC_EEE_CTRL,
1374 UMAC_UMAC_EEE_CTRL_REG_EEE_EN);
1375 REG_WR(sc, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11);
1377 REG_WR(sc, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0);
1380 /* Set MAC address for source TX Pause/PFC frames (under SW reset) */
1381 REG_WR(sc, umac_base + UMAC_REG_MAC_ADDR0,
1382 ((params->mac_addr[2] << 24) |
1383 (params->mac_addr[3] << 16) |
1384 (params->mac_addr[4] << 8) | (params->mac_addr[5])));
1385 REG_WR(sc, umac_base + UMAC_REG_MAC_ADDR1,
1386 ((params->mac_addr[0] << 8) | (params->mac_addr[1])));
1388 /* Enable RX and TX */
1389 val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN;
1390 val |= UMAC_COMMAND_CONFIG_REG_TX_ENA | UMAC_COMMAND_CONFIG_REG_RX_ENA;
1391 REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1394 /* Remove SW Reset */
1395 val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET;
1397 /* Check loopback mode */
1399 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA;
1400 REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1402 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
1403 * length used by the MAC receive logic to check frames.
1405 REG_WR(sc, umac_base + UMAC_REG_MAXFR, 0x2710);
1406 elink_set_xumac_nig(params,
1407 ((vars->flow_ctrl & ELINK_FLOW_CTRL_TX) != 0), 1);
1408 vars->mac_type = ELINK_MAC_TYPE_UMAC;
1412 /* Define the XMAC mode */
1413 static void elink_xmac_init(struct elink_params *params, uint32_t max_speed)
1415 struct bnx2x_softc *sc = params->sc;
1416 uint32_t is_port4mode = elink_is_4_port_mode(sc);
1418 /* In 4-port mode, need to set the mode only once, so if XMAC is
1419 * already out of reset, it means the mode has already been set,
1420 * and it must not* reset the XMAC again, since it controls both
1424 if (((CHIP_NUM(sc) == CHIP_NUM_57840_4_10) ||
1425 (CHIP_NUM(sc) == CHIP_NUM_57840_2_20) ||
1426 (CHIP_NUM(sc) == CHIP_NUM_57840_OBS)) &&
1428 (REG_RD(sc, MISC_REG_RESET_REG_2) &
1429 MISC_REGISTERS_RESET_REG_2_XMAC)) {
1430 PMD_DRV_LOG(DEBUG, sc, "XMAC already out of reset in 4-port mode");
1435 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1436 MISC_REGISTERS_RESET_REG_2_XMAC);
1439 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1440 MISC_REGISTERS_RESET_REG_2_XMAC);
1442 PMD_DRV_LOG(DEBUG, sc, "Init XMAC to 2 ports x 10G per path");
1444 /* Set the number of ports on the system side to up to 2 */
1445 REG_WR(sc, MISC_REG_XMAC_CORE_PORT_MODE, 1);
1447 /* Set the number of ports on the Warp Core to 10G */
1448 REG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1450 /* Set the number of ports on the system side to 1 */
1451 REG_WR(sc, MISC_REG_XMAC_CORE_PORT_MODE, 0);
1452 if (max_speed == ELINK_SPEED_10000) {
1453 PMD_DRV_LOG(DEBUG, sc,
1454 "Init XMAC to 10G x 1 port per path");
1455 /* Set the number of ports on the Warp Core to 10G */
1456 REG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1458 PMD_DRV_LOG(DEBUG, sc,
1459 "Init XMAC to 20G x 2 ports per path");
1460 /* Set the number of ports on the Warp Core to 20G */
1461 REG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 1);
1465 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1466 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1469 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1470 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1474 static void elink_set_xmac_rxtx(struct elink_params *params, uint8_t en)
1476 uint8_t port = params->port;
1477 struct bnx2x_softc *sc = params->sc;
1478 uint32_t pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1481 if (REG_RD(sc, MISC_REG_RESET_REG_2) & MISC_REGISTERS_RESET_REG_2_XMAC) {
1482 /* Send an indication to change the state in the NIG back to XON
1483 * Clearing this bit enables the next set of this bit to get
1486 pfc_ctrl = REG_RD(sc, xmac_base + XMAC_REG_PFC_CTRL_HI);
1487 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI,
1488 (pfc_ctrl & ~(1 << 1)));
1489 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI,
1490 (pfc_ctrl | (1 << 1)));
1491 PMD_DRV_LOG(DEBUG, sc, "Disable XMAC on port %x", port);
1492 val = REG_RD(sc, xmac_base + XMAC_REG_CTRL);
1494 val |= (XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
1496 val &= ~(XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
1497 REG_WR(sc, xmac_base + XMAC_REG_CTRL, val);
1501 static elink_status_t elink_xmac_enable(struct elink_params *params,
1502 struct elink_vars *vars, uint8_t lb)
1504 uint32_t val, xmac_base;
1505 struct bnx2x_softc *sc = params->sc;
1506 PMD_DRV_LOG(DEBUG, sc, "enabling XMAC");
1508 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1510 elink_xmac_init(params, vars->line_speed);
1512 /* This register determines on which events the MAC will assert
1513 * error on the i/f to the NIG along w/ EOP.
1516 /* This register tells the NIG whether to send traffic to UMAC
1519 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port * 4, 0);
1521 /* When XMAC is in XLGMII mode, disable sending idles for fault
1524 if (!(params->phy[ELINK_INT_PHY].flags & ELINK_FLAGS_TX_ERROR_CHECK)) {
1525 REG_WR(sc, xmac_base + XMAC_REG_RX_LSS_CTRL,
1526 (XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE |
1527 XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE));
1528 REG_WR(sc, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
1529 REG_WR(sc, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
1530 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
1531 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
1533 /* Set Max packet size */
1534 REG_WR(sc, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);
1536 /* CRC append for Tx packets */
1537 REG_WR(sc, xmac_base + XMAC_REG_TX_CTRL, 0xC800);
1540 elink_update_pfc_xmac(params, vars);
1542 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
1543 PMD_DRV_LOG(DEBUG, sc, "Setting XMAC for EEE");
1544 REG_WR(sc, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008);
1545 REG_WR(sc, xmac_base + XMAC_REG_EEE_CTRL, 0x1);
1547 REG_WR(sc, xmac_base + XMAC_REG_EEE_CTRL, 0x0);
1550 /* Enable TX and RX */
1551 val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN;
1553 /* Set MAC in XLGMII mode for dual-mode */
1554 if ((vars->line_speed == ELINK_SPEED_20000) &&
1555 (params->phy[ELINK_INT_PHY].supported &
1556 ELINK_SUPPORTED_20000baseKR2_Full))
1557 val |= XMAC_CTRL_REG_XLGMII_ALIGN_ENB;
1559 /* Check loopback mode */
1561 val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK;
1562 REG_WR(sc, xmac_base + XMAC_REG_CTRL, val);
1563 elink_set_xumac_nig(params,
1564 ((vars->flow_ctrl & ELINK_FLOW_CTRL_TX) != 0), 1);
1566 vars->mac_type = ELINK_MAC_TYPE_XMAC;
1568 return ELINK_STATUS_OK;
1571 static elink_status_t elink_emac_enable(struct elink_params *params,
1572 struct elink_vars *vars, uint8_t lb)
1574 struct bnx2x_softc *sc = params->sc;
1575 uint8_t port = params->port;
1576 uint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1579 PMD_DRV_LOG(DEBUG, sc, "enabling EMAC");
1582 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1583 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1585 /* enable emac and not bmac */
1586 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + port * 4, 1);
1588 if (vars->phy_flags & PHY_XGXS_FLAG) {
1589 uint32_t ser_lane = ((params->lane_config &
1590 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1591 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1593 PMD_DRV_LOG(DEBUG, sc, "XGXS");
1594 /* select the master lanes (out of 0-3) */
1595 REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port * 4, ser_lane);
1597 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1);
1599 } else { /* SerDes */
1600 PMD_DRV_LOG(DEBUG, sc, "SerDes");
1602 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 0);
1605 elink_bits_en(sc, emac_base + EMAC_REG_EMAC_RX_MODE,
1606 EMAC_RX_MODE_RESET);
1607 elink_bits_en(sc, emac_base + EMAC_REG_EMAC_TX_MODE,
1608 EMAC_TX_MODE_RESET);
1610 /* pause enable/disable */
1611 elink_bits_dis(sc, emac_base + EMAC_REG_EMAC_RX_MODE,
1612 EMAC_RX_MODE_FLOW_EN);
1614 elink_bits_dis(sc, emac_base + EMAC_REG_EMAC_TX_MODE,
1615 (EMAC_TX_MODE_EXT_PAUSE_EN |
1616 EMAC_TX_MODE_FLOW_EN));
1617 if (!(params->feature_config_flags &
1618 ELINK_FEATURE_CONFIG_PFC_ENABLED)) {
1619 if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)
1620 elink_bits_en(sc, emac_base +
1621 EMAC_REG_EMAC_RX_MODE,
1622 EMAC_RX_MODE_FLOW_EN);
1624 if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)
1625 elink_bits_en(sc, emac_base +
1626 EMAC_REG_EMAC_TX_MODE,
1627 (EMAC_TX_MODE_EXT_PAUSE_EN |
1628 EMAC_TX_MODE_FLOW_EN));
1630 elink_bits_en(sc, emac_base + EMAC_REG_EMAC_TX_MODE,
1631 EMAC_TX_MODE_FLOW_EN);
1633 /* KEEP_VLAN_TAG, promiscuous */
1634 val = REG_RD(sc, emac_base + EMAC_REG_EMAC_RX_MODE);
1635 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
1637 /* Setting this bit causes MAC control frames (except for pause
1638 * frames) to be passed on for processing. This setting has no
1639 * affect on the operation of the pause frames. This bit effects
1640 * all packets regardless of RX Parser packet sorting logic.
1641 * Turn the PFC off to make sure we are in Xon state before
1644 elink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_MODE, 0);
1645 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) {
1646 PMD_DRV_LOG(DEBUG, sc, "PFC is enabled");
1647 /* Enable PFC again */
1648 elink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_MODE,
1649 EMAC_REG_RX_PFC_MODE_RX_EN |
1650 EMAC_REG_RX_PFC_MODE_TX_EN |
1651 EMAC_REG_RX_PFC_MODE_PRIORITIES);
1653 elink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_PARAM,
1655 EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
1657 EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
1658 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
1660 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_RX_MODE, val);
1663 val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);
1668 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MODE, val);
1671 REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port * 4, 1);
1673 /* Enable emac for jumbo packets */
1674 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_RX_MTU_SIZE,
1675 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
1676 (ELINK_ETH_MAX_JUMBO_PACKET_SIZE +
1677 ELINK_ETH_OVREHEAD)));
1680 REG_WR(sc, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port * 4, 0x1);
1682 /* Disable the NIG in/out to the bmac */
1683 REG_WR(sc, NIG_REG_BMAC0_IN_EN + port * 4, 0x0);
1684 REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + port * 4, 0x0);
1685 REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port * 4, 0x0);
1687 /* Enable the NIG in/out to the emac */
1688 REG_WR(sc, NIG_REG_EMAC0_IN_EN + port * 4, 0x1);
1690 if ((params->feature_config_flags &
1691 ELINK_FEATURE_CONFIG_PFC_ENABLED) ||
1692 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
1695 REG_WR(sc, NIG_REG_EMAC0_PAUSE_OUT_EN + port * 4, val);
1696 REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port * 4, 0x1);
1698 REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4, 0x0);
1700 vars->mac_type = ELINK_MAC_TYPE_EMAC;
1701 return ELINK_STATUS_OK;
1704 static void elink_update_pfc_bmac1(struct elink_params *params,
1705 struct elink_vars *vars)
1707 uint32_t wb_data[2];
1708 struct bnx2x_softc *sc = params->sc;
1709 uint32_t bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1710 NIG_REG_INGRESS_BMAC0_MEM;
1712 uint32_t val = 0x14;
1713 if ((!(params->feature_config_flags &
1714 ELINK_FEATURE_CONFIG_PFC_ENABLED)) &&
1715 (vars->flow_ctrl & ELINK_FLOW_CTRL_RX))
1716 /* Enable BigMAC to react on received Pause packets */
1720 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
1724 if (!(params->feature_config_flags &
1725 ELINK_FEATURE_CONFIG_PFC_ENABLED) &&
1726 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
1730 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
1733 static void elink_update_pfc_bmac2(struct elink_params *params,
1734 struct elink_vars *vars, uint8_t is_lb)
1736 /* Set rx control: Strip CRC and enable BigMAC to relay
1737 * control packets to the system as well
1739 uint32_t wb_data[2];
1740 struct bnx2x_softc *sc = params->sc;
1741 uint32_t bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1742 NIG_REG_INGRESS_BMAC0_MEM;
1743 uint32_t val = 0x14;
1745 if ((!(params->feature_config_flags &
1746 ELINK_FEATURE_CONFIG_PFC_ENABLED)) &&
1747 (vars->flow_ctrl & ELINK_FLOW_CTRL_RX))
1748 /* Enable BigMAC to react on received Pause packets */
1752 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
1757 if (!(params->feature_config_flags &
1758 ELINK_FEATURE_CONFIG_PFC_ENABLED) &&
1759 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
1763 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
1765 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) {
1766 PMD_DRV_LOG(DEBUG, sc, "PFC is enabled");
1767 /* Enable PFC RX & TX & STATS and set 8 COS */
1769 wb_data[0] |= (1 << 0); /* RX */
1770 wb_data[0] |= (1 << 1); /* TX */
1771 wb_data[0] |= (1 << 2); /* Force initial Xon */
1772 wb_data[0] |= (1 << 3); /* 8 cos */
1773 wb_data[0] |= (1 << 5); /* STATS */
1775 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
1777 /* Clear the force Xon */
1778 wb_data[0] &= ~(1 << 2);
1780 PMD_DRV_LOG(DEBUG, sc, "PFC is disabled");
1781 /* Disable PFC RX & TX & STATS and set 8 COS */
1786 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
1788 /* Set Time (based unit is 512 bit time) between automatic
1789 * re-sending of PP packets amd enable automatic re-send of
1790 * Per-Priroity Packet as long as pp_gen is asserted and
1791 * pp_disable is low.
1794 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
1795 val |= (1 << 16); /* enable automatic re-send */
1799 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
1803 val = 0x3; /* Enable RX and TX */
1805 val |= 0x4; /* Local loopback */
1806 PMD_DRV_LOG(DEBUG, sc, "enable bmac loopback");
1808 /* When PFC enabled, Pass pause frames towards the NIG. */
1809 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
1810 val |= ((1 << 6) | (1 << 5));
1814 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
1817 /******************************************************************************
1819 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are
1820 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
1821 ******************************************************************************/
1822 static elink_status_t elink_pfc_nig_rx_priority_mask(struct bnx2x_softc *sc,
1824 uint32_t priority_mask,
1827 uint32_t nig_reg_rx_priority_mask_add = 0;
1829 switch (cos_entry) {
1831 nig_reg_rx_priority_mask_add = (port) ?
1832 NIG_REG_P1_RX_COS0_PRIORITY_MASK :
1833 NIG_REG_P0_RX_COS0_PRIORITY_MASK;
1836 nig_reg_rx_priority_mask_add = (port) ?
1837 NIG_REG_P1_RX_COS1_PRIORITY_MASK :
1838 NIG_REG_P0_RX_COS1_PRIORITY_MASK;
1841 nig_reg_rx_priority_mask_add = (port) ?
1842 NIG_REG_P1_RX_COS2_PRIORITY_MASK :
1843 NIG_REG_P0_RX_COS2_PRIORITY_MASK;
1847 return ELINK_STATUS_ERROR;
1848 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;
1852 return ELINK_STATUS_ERROR;
1853 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;
1857 return ELINK_STATUS_ERROR;
1858 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;
1862 REG_WR(sc, nig_reg_rx_priority_mask_add, priority_mask);
1864 return ELINK_STATUS_OK;
1867 static void elink_update_mng(struct elink_params *params, uint32_t link_status)
1869 struct bnx2x_softc *sc = params->sc;
1871 REG_WR(sc, params->shmem_base +
1872 offsetof(struct shmem_region,
1873 port_mb[params->port].link_status), link_status);
1876 static void elink_update_link_attr(struct elink_params *params,
1879 struct bnx2x_softc *sc = params->sc;
1881 if (SHMEM2_HAS(sc, link_attr_sync))
1882 REG_WR(sc, params->shmem2_base +
1883 offsetof(struct shmem2_region,
1884 link_attr_sync[params->port]), link_attr);
1887 static void elink_update_pfc_nig(struct elink_params *params,
1888 struct elink_nig_brb_pfc_port_params
1891 uint32_t xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en =
1893 uint32_t llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0;
1894 uint32_t pkt_priority_to_cos = 0;
1895 struct bnx2x_softc *sc = params->sc;
1896 uint8_t port = params->port;
1898 int set_pfc = params->feature_config_flags &
1899 ELINK_FEATURE_CONFIG_PFC_ENABLED;
1900 PMD_DRV_LOG(DEBUG, sc, "updating pfc nig parameters");
1902 /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
1903 * MAC control frames (that are not pause packets)
1904 * will be forwarded to the XCM.
1906 xcm_mask = REG_RD(sc, port ? NIG_REG_LLH1_XCM_MASK :
1907 NIG_REG_LLH0_XCM_MASK);
1908 /* NIG params will override non PFC params, since it's possible to
1909 * do transition from PFC to SAFC
1919 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
1920 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
1925 llfc_out_en = nig_params->llfc_out_en;
1926 llfc_enable = nig_params->llfc_enable;
1927 pause_enable = nig_params->pause_enable;
1928 } else /* Default non PFC mode - PAUSE */
1931 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
1932 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
1937 REG_WR(sc, port ? NIG_REG_BRB1_PAUSE_IN_EN :
1938 NIG_REG_BRB0_PAUSE_IN_EN, pause_enable);
1939 REG_WR(sc, port ? NIG_REG_LLFC_OUT_EN_1 :
1940 NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
1941 REG_WR(sc, port ? NIG_REG_LLFC_ENABLE_1 :
1942 NIG_REG_LLFC_ENABLE_0, llfc_enable);
1943 REG_WR(sc, port ? NIG_REG_PAUSE_ENABLE_1 :
1944 NIG_REG_PAUSE_ENABLE_0, pause_enable);
1946 REG_WR(sc, port ? NIG_REG_PPP_ENABLE_1 :
1947 NIG_REG_PPP_ENABLE_0, ppp_enable);
1949 REG_WR(sc, port ? NIG_REG_LLH1_XCM_MASK :
1950 NIG_REG_LLH0_XCM_MASK, xcm_mask);
1952 REG_WR(sc, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 :
1953 NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
1955 /* Output enable for RX_XCM # IF */
1956 REG_WR(sc, port ? NIG_REG_XCM1_OUT_EN :
1957 NIG_REG_XCM0_OUT_EN, xcm_out_en);
1959 /* HW PFC TX enable */
1960 REG_WR(sc, port ? NIG_REG_P1_HWPFC_ENABLE :
1961 NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable);
1965 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
1967 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++)
1968 elink_pfc_nig_rx_priority_mask(sc, i,
1970 rx_cos_priority_mask[i],
1973 REG_WR(sc, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
1974 NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
1975 nig_params->llfc_high_priority_classes);
1977 REG_WR(sc, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
1978 NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
1979 nig_params->llfc_low_priority_classes);
1981 REG_WR(sc, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
1982 NIG_REG_P0_PKT_PRIORITY_TO_COS, pkt_priority_to_cos);
1985 elink_status_t elink_update_pfc(struct elink_params *params,
1986 struct elink_vars *vars,
1987 struct elink_nig_brb_pfc_port_params
1990 /* The PFC and pause are orthogonal to one another, meaning when
1991 * PFC is enabled, the pause are disabled, and when PFC is
1992 * disabled, pause are set according to the pause result.
1995 struct bnx2x_softc *sc = params->sc;
1996 elink_status_t elink_status = ELINK_STATUS_OK;
1997 uint8_t bmac_loopback = (params->loopback_mode == ELINK_LOOPBACK_BMAC);
1999 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
2000 vars->link_status |= LINK_STATUS_PFC_ENABLED;
2002 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
2004 elink_update_mng(params, vars->link_status);
2006 /* Update NIG params */
2007 elink_update_pfc_nig(params, pfc_params);
2010 return elink_status;
2012 PMD_DRV_LOG(DEBUG, sc, "About to update PFC in BMAC");
2014 if (CHIP_IS_E3(sc)) {
2015 if (vars->mac_type == ELINK_MAC_TYPE_XMAC)
2016 elink_update_pfc_xmac(params, vars);
2018 val = REG_RD(sc, MISC_REG_RESET_REG_2);
2020 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
2022 PMD_DRV_LOG(DEBUG, sc, "About to update PFC in EMAC");
2023 elink_emac_enable(params, vars, 0);
2024 return elink_status;
2027 elink_update_pfc_bmac2(params, vars, bmac_loopback);
2029 elink_update_pfc_bmac1(params, vars);
2032 if ((params->feature_config_flags &
2033 ELINK_FEATURE_CONFIG_PFC_ENABLED) ||
2034 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
2036 REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port * 4, val);
2038 return elink_status;
2041 static elink_status_t elink_bmac1_enable(struct elink_params *params,
2042 struct elink_vars *vars, uint8_t is_lb)
2044 struct bnx2x_softc *sc = params->sc;
2045 uint8_t port = params->port;
2046 uint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2047 NIG_REG_INGRESS_BMAC0_MEM;
2048 uint32_t wb_data[2];
2051 PMD_DRV_LOG(DEBUG, sc, "Enabling BigMAC1");
2056 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
2060 wb_data[0] = ((params->mac_addr[2] << 24) |
2061 (params->mac_addr[3] << 16) |
2062 (params->mac_addr[4] << 8) | params->mac_addr[5]);
2063 wb_data[1] = ((params->mac_addr[0] << 8) | params->mac_addr[1]);
2064 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
2070 PMD_DRV_LOG(DEBUG, sc, "enable bmac loopback");
2074 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
2077 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
2079 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
2081 elink_update_pfc_bmac1(params, vars);
2084 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
2086 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
2088 /* Set cnt max size */
2089 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
2091 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2093 /* Configure SAFC */
2094 wb_data[0] = 0x1000200;
2096 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
2099 return ELINK_STATUS_OK;
2102 static elink_status_t elink_bmac2_enable(struct elink_params *params,
2103 struct elink_vars *vars, uint8_t is_lb)
2105 struct bnx2x_softc *sc = params->sc;
2106 uint8_t port = params->port;
2107 uint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2108 NIG_REG_INGRESS_BMAC0_MEM;
2109 uint32_t wb_data[2];
2111 PMD_DRV_LOG(DEBUG, sc, "Enabling BigMAC2");
2115 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2118 /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
2121 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
2127 wb_data[0] = ((params->mac_addr[2] << 24) |
2128 (params->mac_addr[3] << 16) |
2129 (params->mac_addr[4] << 8) | params->mac_addr[5]);
2130 wb_data[1] = ((params->mac_addr[0] << 8) | params->mac_addr[1]);
2131 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
2136 /* Configure SAFC */
2137 wb_data[0] = 0x1000200;
2139 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
2144 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
2146 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
2150 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
2152 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
2154 /* Set cnt max size */
2155 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD - 2;
2157 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2159 elink_update_pfc_bmac2(params, vars, is_lb);
2161 return ELINK_STATUS_OK;
2164 static elink_status_t elink_bmac_enable(struct elink_params *params,
2165 struct elink_vars *vars,
2166 uint8_t is_lb, uint8_t reset_bmac)
2168 elink_status_t rc = ELINK_STATUS_OK;
2169 uint8_t port = params->port;
2170 struct bnx2x_softc *sc = params->sc;
2172 /* Reset and unreset the BigMac */
2174 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2175 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2179 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2180 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2182 /* Enable access for bmac registers */
2183 REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4, 0x1);
2185 /* Enable BMAC according to BMAC type */
2187 rc = elink_bmac2_enable(params, vars, is_lb);
2189 rc = elink_bmac1_enable(params, vars, is_lb);
2190 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 0x1);
2191 REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port * 4, 0x0);
2192 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + port * 4, 0x0);
2194 if ((params->feature_config_flags &
2195 ELINK_FEATURE_CONFIG_PFC_ENABLED) ||
2196 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
2198 REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + port * 4, val);
2199 REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port * 4, 0x0);
2200 REG_WR(sc, NIG_REG_EMAC0_IN_EN + port * 4, 0x0);
2201 REG_WR(sc, NIG_REG_EMAC0_PAUSE_OUT_EN + port * 4, 0x0);
2202 REG_WR(sc, NIG_REG_BMAC0_IN_EN + port * 4, 0x1);
2203 REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port * 4, 0x1);
2205 vars->mac_type = ELINK_MAC_TYPE_BMAC;
2209 static void elink_set_bmac_rx(struct bnx2x_softc *sc, uint8_t port, uint8_t en)
2211 uint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2212 NIG_REG_INGRESS_BMAC0_MEM;
2213 uint32_t wb_data[2];
2214 uint32_t nig_bmac_enable =
2215 REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
2218 bmac_addr += BIGMAC2_REGISTER_BMAC_CONTROL;
2220 bmac_addr += BIGMAC_REGISTER_BMAC_CONTROL;
2221 /* Only if the bmac is out of reset */
2222 if (REG_RD(sc, MISC_REG_RESET_REG_2) &
2223 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) && nig_bmac_enable) {
2224 /* Clear Rx Enable bit in BMAC_CONTROL register */
2225 REG_RD_DMAE(sc, bmac_addr, wb_data, 2);
2227 wb_data[0] |= ELINK_BMAC_CONTROL_RX_ENABLE;
2229 wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE;
2230 REG_WR_DMAE(sc, bmac_addr, wb_data, 2);
2235 static elink_status_t elink_pbf_update(struct elink_params *params,
2236 uint32_t flow_ctrl, uint32_t line_speed)
2238 struct bnx2x_softc *sc = params->sc;
2239 uint8_t port = params->port;
2240 uint32_t init_crd, crd;
2241 uint32_t count = 1000;
2244 REG_WR(sc, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port * 4, 0x1);
2246 /* Wait for init credit */
2247 init_crd = REG_RD(sc, PBF_REG_P0_INIT_CRD + port * 4);
2248 crd = REG_RD(sc, PBF_REG_P0_CREDIT + port * 8);
2249 PMD_DRV_LOG(DEBUG, sc, "init_crd 0x%x crd 0x%x", init_crd, crd);
2251 while ((init_crd != crd) && count) {
2253 crd = REG_RD(sc, PBF_REG_P0_CREDIT + port * 8);
2256 crd = REG_RD(sc, PBF_REG_P0_CREDIT + port * 8);
2257 if (init_crd != crd) {
2258 PMD_DRV_LOG(DEBUG, sc, "BUG! init_crd 0x%x != crd 0x%x",
2260 return ELINK_STATUS_ERROR;
2263 if (flow_ctrl & ELINK_FLOW_CTRL_RX ||
2264 line_speed == ELINK_SPEED_10 ||
2265 line_speed == ELINK_SPEED_100 ||
2266 line_speed == ELINK_SPEED_1000 || line_speed == ELINK_SPEED_2500) {
2267 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 1);
2268 /* Update threshold */
2269 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, 0);
2270 /* Update init credit */
2271 init_crd = 778; /* (800-18-4) */
2274 uint32_t thresh = (ELINK_ETH_MAX_JUMBO_PACKET_SIZE +
2275 ELINK_ETH_OVREHEAD) / 16;
2276 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 0);
2277 /* Update threshold */
2278 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, thresh);
2279 /* Update init credit */
2280 switch (line_speed) {
2281 case ELINK_SPEED_10000:
2282 init_crd = thresh + 553 - 22;
2285 PMD_DRV_LOG(DEBUG, sc, "Invalid line_speed 0x%x",
2287 return ELINK_STATUS_ERROR;
2290 REG_WR(sc, PBF_REG_P0_INIT_CRD + port * 4, init_crd);
2291 PMD_DRV_LOG(DEBUG, sc, "PBF updated to speed %d credit %d",
2292 line_speed, init_crd);
2294 /* Probe the credit changes */
2295 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0x1);
2297 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0x0);
2300 REG_WR(sc, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port * 4, 0x0);
2301 return ELINK_STATUS_OK;
2305 * elink_get_emac_base - retrive emac base address
2307 * @bp: driver handle
2308 * @mdc_mdio_access: access type
2311 * This function selects the MDC/MDIO access (through emac0 or
2312 * emac1) depend on the mdc_mdio_access, port, port swapped. Each
2313 * phy has a default access mode, which could also be overridden
2314 * by nvram configuration. This parameter, whether this is the
2315 * default phy configuration, or the nvram overrun
2316 * configuration, is passed here as mdc_mdio_access and selects
2317 * the emac_base for the CL45 read/writes operations
2319 static uint32_t elink_get_emac_base(struct bnx2x_softc *sc,
2320 uint32_t mdc_mdio_access, uint8_t port)
2322 uint32_t emac_base = 0;
2323 switch (mdc_mdio_access) {
2324 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
2326 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
2327 if (REG_RD(sc, NIG_REG_PORT_SWAP))
2328 emac_base = GRCBASE_EMAC1;
2330 emac_base = GRCBASE_EMAC0;
2332 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
2333 if (REG_RD(sc, NIG_REG_PORT_SWAP))
2334 emac_base = GRCBASE_EMAC0;
2336 emac_base = GRCBASE_EMAC1;
2338 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
2339 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2341 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
2342 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
2351 /******************************************************************/
2352 /* CL22 access functions */
2353 /******************************************************************/
2354 static elink_status_t elink_cl22_write(struct bnx2x_softc *sc,
2355 struct elink_phy *phy,
2356 uint16_t reg, uint16_t val)
2360 elink_status_t rc = ELINK_STATUS_OK;
2361 /* Switch to CL22 */
2362 mode = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2363 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2364 mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2367 tmp = ((phy->addr << 21) | (reg << 16) | val |
2368 EMAC_MDIO_COMM_COMMAND_WRITE_22 | EMAC_MDIO_COMM_START_BUSY);
2369 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2371 for (i = 0; i < 50; i++) {
2374 tmp = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2375 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2380 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2381 PMD_DRV_LOG(DEBUG, sc, "write phy register failed");
2382 rc = ELINK_STATUS_TIMEOUT;
2384 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2388 static elink_status_t elink_cl22_read(struct bnx2x_softc *sc,
2389 struct elink_phy *phy,
2390 uint16_t reg, uint16_t * ret_val)
2394 elink_status_t rc = ELINK_STATUS_OK;
2396 /* Switch to CL22 */
2397 mode = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2398 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2399 mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2402 val = ((phy->addr << 21) | (reg << 16) |
2403 EMAC_MDIO_COMM_COMMAND_READ_22 | EMAC_MDIO_COMM_START_BUSY);
2404 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2406 for (i = 0; i < 50; i++) {
2409 val = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2410 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2411 *ret_val = (uint16_t) (val & EMAC_MDIO_COMM_DATA);
2416 if (val & EMAC_MDIO_COMM_START_BUSY) {
2417 PMD_DRV_LOG(DEBUG, sc, "read phy register failed");
2420 rc = ELINK_STATUS_TIMEOUT;
2422 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2426 /******************************************************************/
2427 /* CL45 access functions */
2428 /******************************************************************/
2429 static elink_status_t elink_cl45_read(struct bnx2x_softc *sc,
2430 struct elink_phy *phy, uint8_t devad,
2431 uint16_t reg, uint16_t * ret_val)
2435 elink_status_t rc = ELINK_STATUS_OK;
2436 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_G) {
2437 elink_set_mdio_clk(sc, phy->mdio_ctrl);
2440 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)
2441 elink_bits_en(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2442 EMAC_MDIO_STATUS_10MB);
2444 val = ((phy->addr << 21) | (devad << 16) | reg |
2445 EMAC_MDIO_COMM_COMMAND_ADDRESS | EMAC_MDIO_COMM_START_BUSY);
2446 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2448 for (i = 0; i < 50; i++) {
2451 val = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2452 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2457 if (val & EMAC_MDIO_COMM_START_BUSY) {
2458 PMD_DRV_LOG(DEBUG, sc, "read phy register failed");
2459 elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout"
2462 rc = ELINK_STATUS_TIMEOUT;
2465 val = ((phy->addr << 21) | (devad << 16) |
2466 EMAC_MDIO_COMM_COMMAND_READ_45 |
2467 EMAC_MDIO_COMM_START_BUSY);
2468 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2470 for (i = 0; i < 50; i++) {
2473 val = REG_RD(sc, phy->mdio_ctrl +
2474 EMAC_REG_EMAC_MDIO_COMM);
2475 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2477 (uint16_t) (val & EMAC_MDIO_COMM_DATA);
2481 if (val & EMAC_MDIO_COMM_START_BUSY) {
2482 PMD_DRV_LOG(DEBUG, sc, "read phy register failed");
2483 elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout"
2486 rc = ELINK_STATUS_TIMEOUT;
2489 /* Work around for E3 A0 */
2490 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA) {
2491 phy->flags ^= ELINK_FLAGS_DUMMY_READ;
2492 if (phy->flags & ELINK_FLAGS_DUMMY_READ) {
2494 elink_cl45_read(sc, phy, devad, 0xf, &temp_val);
2498 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)
2499 elink_bits_dis(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2500 EMAC_MDIO_STATUS_10MB);
2504 static elink_status_t elink_cl45_write(struct bnx2x_softc *sc,
2505 struct elink_phy *phy, uint8_t devad,
2506 uint16_t reg, uint16_t val)
2510 elink_status_t rc = ELINK_STATUS_OK;
2511 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_G) {
2512 elink_set_mdio_clk(sc, phy->mdio_ctrl);
2515 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)
2516 elink_bits_en(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2517 EMAC_MDIO_STATUS_10MB);
2520 tmp = ((phy->addr << 21) | (devad << 16) | reg |
2521 EMAC_MDIO_COMM_COMMAND_ADDRESS | EMAC_MDIO_COMM_START_BUSY);
2522 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2524 for (i = 0; i < 50; i++) {
2527 tmp = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2528 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2533 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2534 PMD_DRV_LOG(DEBUG, sc, "write phy register failed");
2535 elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout"
2537 rc = ELINK_STATUS_TIMEOUT;
2540 tmp = ((phy->addr << 21) | (devad << 16) | val |
2541 EMAC_MDIO_COMM_COMMAND_WRITE_45 |
2542 EMAC_MDIO_COMM_START_BUSY);
2543 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2545 for (i = 0; i < 50; i++) {
2548 tmp = REG_RD(sc, phy->mdio_ctrl +
2549 EMAC_REG_EMAC_MDIO_COMM);
2550 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2555 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2556 PMD_DRV_LOG(DEBUG, sc, "write phy register failed");
2557 elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout"
2559 rc = ELINK_STATUS_TIMEOUT;
2562 /* Work around for E3 A0 */
2563 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA) {
2564 phy->flags ^= ELINK_FLAGS_DUMMY_READ;
2565 if (phy->flags & ELINK_FLAGS_DUMMY_READ) {
2567 elink_cl45_read(sc, phy, devad, 0xf, &temp_val);
2570 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)
2571 elink_bits_dis(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2572 EMAC_MDIO_STATUS_10MB);
2576 /******************************************************************/
2578 /******************************************************************/
2579 static uint8_t elink_eee_has_cap(struct elink_params *params)
2581 struct bnx2x_softc *sc = params->sc;
2583 if (REG_RD(sc, params->shmem2_base) <=
2584 offsetof(struct shmem2_region, eee_status[params->port]))
2590 static elink_status_t elink_eee_nvram_to_time(uint32_t nvram_mode,
2591 uint32_t * idle_timer)
2593 switch (nvram_mode) {
2594 case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED:
2595 *idle_timer = ELINK_EEE_MODE_NVRAM_BALANCED_TIME;
2597 case PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE:
2598 *idle_timer = ELINK_EEE_MODE_NVRAM_AGGRESSIVE_TIME;
2600 case PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY:
2601 *idle_timer = ELINK_EEE_MODE_NVRAM_LATENCY_TIME;
2608 return ELINK_STATUS_OK;
2611 static elink_status_t elink_eee_time_to_nvram(uint32_t idle_timer,
2612 uint32_t * nvram_mode)
2614 switch (idle_timer) {
2615 case ELINK_EEE_MODE_NVRAM_BALANCED_TIME:
2616 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED;
2618 case ELINK_EEE_MODE_NVRAM_AGGRESSIVE_TIME:
2619 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE;
2621 case ELINK_EEE_MODE_NVRAM_LATENCY_TIME:
2622 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY;
2625 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED;
2629 return ELINK_STATUS_OK;
2632 static uint32_t elink_eee_calc_timer(struct elink_params *params)
2634 uint32_t eee_mode, eee_idle;
2635 struct bnx2x_softc *sc = params->sc;
2637 if (params->eee_mode & ELINK_EEE_MODE_OVERRIDE_NVRAM) {
2638 if (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME) {
2639 /* time value in eee_mode --> used directly */
2640 eee_idle = params->eee_mode & ELINK_EEE_MODE_TIMER_MASK;
2642 /* hsi value in eee_mode --> time */
2643 if (elink_eee_nvram_to_time(params->eee_mode &
2644 ELINK_EEE_MODE_NVRAM_MASK,
2649 /* hsi values in nvram --> time */
2650 eee_mode = ((REG_RD(sc, params->shmem_base +
2651 offsetof(struct shmem_region,
2652 dev_info.port_feature_config
2654 port].eee_power_mode)) &
2655 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
2656 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
2658 if (elink_eee_nvram_to_time(eee_mode, &eee_idle))
2665 static elink_status_t elink_eee_set_timers(struct elink_params *params,
2666 struct elink_vars *vars)
2668 uint32_t eee_idle = 0, eee_mode;
2669 struct bnx2x_softc *sc = params->sc;
2671 eee_idle = elink_eee_calc_timer(params);
2674 REG_WR(sc, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2),
2676 } else if ((params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI) &&
2677 (params->eee_mode & ELINK_EEE_MODE_OVERRIDE_NVRAM) &&
2678 (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME)) {
2679 PMD_DRV_LOG(DEBUG, sc, "Error: Tx LPI is enabled with timer 0");
2680 return ELINK_STATUS_ERROR;
2683 vars->eee_status &= ~(SHMEM_EEE_TIMER_MASK | SHMEM_EEE_TIME_OUTPUT_BIT);
2684 if (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME) {
2685 /* eee_idle in 1u --> eee_status in 16u */
2687 vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) |
2688 SHMEM_EEE_TIME_OUTPUT_BIT;
2690 if (elink_eee_time_to_nvram(eee_idle, &eee_mode))
2691 return ELINK_STATUS_ERROR;
2692 vars->eee_status |= eee_mode;
2695 return ELINK_STATUS_OK;
2698 static elink_status_t elink_eee_initial_config(struct elink_params *params,
2699 struct elink_vars *vars,
2702 vars->eee_status |= ((uint32_t) mode) << SHMEM_EEE_SUPPORTED_SHIFT;
2704 /* Propagate params' bits --> vars (for migration exposure) */
2705 if (params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI)
2706 vars->eee_status |= SHMEM_EEE_LPI_REQUESTED_BIT;
2708 vars->eee_status &= ~SHMEM_EEE_LPI_REQUESTED_BIT;
2710 if (params->eee_mode & ELINK_EEE_MODE_ADV_LPI)
2711 vars->eee_status |= SHMEM_EEE_REQUESTED_BIT;
2713 vars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT;
2715 return elink_eee_set_timers(params, vars);
2718 static elink_status_t elink_eee_disable(struct elink_phy *phy,
2719 struct elink_params *params,
2720 struct elink_vars *vars)
2722 struct bnx2x_softc *sc = params->sc;
2724 /* Make Certain LPI is disabled */
2725 REG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0);
2727 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0);
2729 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
2731 return ELINK_STATUS_OK;
2734 static elink_status_t elink_eee_advertise(struct elink_phy *phy,
2735 struct elink_params *params,
2736 struct elink_vars *vars,
2739 struct bnx2x_softc *sc = params->sc;
2742 /* Mask events preventing LPI generation */
2743 REG_WR(sc, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20);
2745 if (modes & SHMEM_EEE_10G_ADV) {
2746 PMD_DRV_LOG(DEBUG, sc, "Advertise 10GBase-T EEE");
2749 if (modes & SHMEM_EEE_1G_ADV) {
2750 PMD_DRV_LOG(DEBUG, sc, "Advertise 1GBase-T EEE");
2754 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val);
2756 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
2757 vars->eee_status |= (modes << SHMEM_EEE_ADV_STATUS_SHIFT);
2759 return ELINK_STATUS_OK;
2762 static void elink_update_mng_eee(struct elink_params *params,
2763 uint32_t eee_status)
2765 struct bnx2x_softc *sc = params->sc;
2767 if (elink_eee_has_cap(params))
2768 REG_WR(sc, params->shmem2_base +
2769 offsetof(struct shmem2_region,
2770 eee_status[params->port]), eee_status);
2773 static void elink_eee_an_resolve(struct elink_phy *phy,
2774 struct elink_params *params,
2775 struct elink_vars *vars)
2777 struct bnx2x_softc *sc = params->sc;
2778 uint16_t adv = 0, lp = 0;
2779 uint32_t lp_adv = 0;
2782 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv);
2783 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp);
2786 lp_adv |= SHMEM_EEE_100M_ADV;
2788 if (vars->line_speed == ELINK_SPEED_100)
2790 PMD_DRV_LOG(DEBUG, sc, "EEE negotiated - 100M");
2794 lp_adv |= SHMEM_EEE_1G_ADV;
2796 if (vars->line_speed == ELINK_SPEED_1000)
2798 PMD_DRV_LOG(DEBUG, sc, "EEE negotiated - 1G");
2802 lp_adv |= SHMEM_EEE_10G_ADV;
2804 if (vars->line_speed == ELINK_SPEED_10000)
2806 PMD_DRV_LOG(DEBUG, sc, "EEE negotiated - 10G");
2810 vars->eee_status &= ~SHMEM_EEE_LP_ADV_STATUS_MASK;
2811 vars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT);
2814 PMD_DRV_LOG(DEBUG, sc, "EEE is active");
2815 vars->eee_status |= SHMEM_EEE_ACTIVE_BIT;
2819 /******************************************************************/
2820 /* BSC access functions from E3 */
2821 /******************************************************************/
2822 static void elink_bsc_module_sel(struct elink_params *params)
2825 uint32_t board_cfg, sfp_ctrl;
2826 uint32_t i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH];
2827 struct bnx2x_softc *sc = params->sc;
2828 uint8_t port = params->port;
2829 /* Read I2C output PINs */
2830 board_cfg = REG_RD(sc, params->shmem_base +
2831 offsetof(struct shmem_region,
2832 dev_info.shared_hw_config.board));
2833 i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK;
2834 i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >>
2835 SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;
2837 /* Read I2C output value */
2838 sfp_ctrl = REG_RD(sc, params->shmem_base +
2839 offsetof(struct shmem_region,
2840 dev_info.port_hw_config[port].
2842 i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0;
2843 i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0;
2844 PMD_DRV_LOG(DEBUG, sc, "Setting BSC switch");
2845 for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++)
2846 elink_set_cfg_pin(sc, i2c_pins[idx], i2c_val[idx]);
2849 static elink_status_t elink_bsc_read(struct elink_params *params,
2850 struct bnx2x_softc *sc,
2854 uint8_t xfer_cnt, uint32_t * data_array)
2857 elink_status_t rc = ELINK_STATUS_OK;
2859 if (xfer_cnt > 16) {
2860 PMD_DRV_LOG(DEBUG, sc, "invalid xfer_cnt %d. Max is 16 bytes",
2862 return ELINK_STATUS_ERROR;
2865 elink_bsc_module_sel(params);
2867 xfer_cnt = 16 - lc_addr;
2869 /* Enable the engine */
2870 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
2871 val |= MCPR_IMC_COMMAND_ENABLE;
2872 REG_WR(sc, MCP_REG_MCPR_IMC_COMMAND, val);
2874 /* Program slave device ID */
2875 val = (sl_devid << 16) | sl_addr;
2876 REG_WR(sc, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);
2878 /* Start xfer with 0 byte to update the address pointer ??? */
2879 val = (MCPR_IMC_COMMAND_ENABLE) |
2880 (MCPR_IMC_COMMAND_WRITE_OP <<
2881 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
2882 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);
2883 REG_WR(sc, MCP_REG_MCPR_IMC_COMMAND, val);
2885 /* Poll for completion */
2887 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
2888 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
2890 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
2892 PMD_DRV_LOG(DEBUG, sc, "wr 0 byte timed out after %d try",
2894 rc = ELINK_STATUS_TIMEOUT;
2898 if (rc == ELINK_STATUS_TIMEOUT)
2901 /* Start xfer with read op */
2902 val = (MCPR_IMC_COMMAND_ENABLE) |
2903 (MCPR_IMC_COMMAND_READ_OP <<
2904 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
2905 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) |
2907 REG_WR(sc, MCP_REG_MCPR_IMC_COMMAND, val);
2909 /* Poll for completion */
2911 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
2912 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
2914 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
2916 PMD_DRV_LOG(DEBUG, sc,
2917 "rd op timed out after %d try", i);
2918 rc = ELINK_STATUS_TIMEOUT;
2922 if (rc == ELINK_STATUS_TIMEOUT)
2925 for (i = (lc_addr >> 2); i < 4; i++) {
2926 data_array[i] = REG_RD(sc, (MCP_REG_MCPR_IMC_DATAREG0 + i * 4));
2928 data_array[i] = ((data_array[i] & 0x000000ff) << 24) |
2929 ((data_array[i] & 0x0000ff00) << 8) |
2930 ((data_array[i] & 0x00ff0000) >> 8) |
2931 ((data_array[i] & 0xff000000) >> 24);
2937 static void elink_cl45_read_or_write(struct bnx2x_softc *sc,
2938 struct elink_phy *phy, uint8_t devad,
2939 uint16_t reg, uint16_t or_val)
2942 elink_cl45_read(sc, phy, devad, reg, &val);
2943 elink_cl45_write(sc, phy, devad, reg, val | or_val);
2946 static void elink_cl45_read_and_write(struct bnx2x_softc *sc,
2947 struct elink_phy *phy,
2948 uint8_t devad, uint16_t reg,
2952 elink_cl45_read(sc, phy, devad, reg, &val);
2953 elink_cl45_write(sc, phy, devad, reg, val & and_val);
2956 static uint8_t elink_get_warpcore_lane(struct elink_params *params)
2959 struct bnx2x_softc *sc = params->sc;
2960 uint32_t path_swap, path_swap_ovr;
2964 port = params->port;
2966 if (elink_is_4_port_mode(sc)) {
2967 uint32_t port_swap, port_swap_ovr;
2969 /* Figure out path swap value */
2970 path_swap_ovr = REG_RD(sc, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);
2971 if (path_swap_ovr & 0x1)
2972 path_swap = (path_swap_ovr & 0x2);
2974 path_swap = REG_RD(sc, MISC_REG_FOUR_PORT_PATH_SWAP);
2979 /* Figure out port swap value */
2980 port_swap_ovr = REG_RD(sc, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);
2981 if (port_swap_ovr & 0x1)
2982 port_swap = (port_swap_ovr & 0x2);
2984 port_swap = REG_RD(sc, MISC_REG_FOUR_PORT_PORT_SWAP);
2989 lane = (port << 1) + path;
2990 } else { /* Two port mode - no port swap */
2992 /* Figure out path swap value */
2993 path_swap_ovr = REG_RD(sc, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
2994 if (path_swap_ovr & 0x1) {
2995 path_swap = (path_swap_ovr & 0x2);
2997 path_swap = REG_RD(sc, MISC_REG_TWO_PORT_PATH_SWAP);
3007 static void elink_set_aer_mmd(struct elink_params *params,
3008 struct elink_phy *phy)
3011 uint16_t offset, aer_val;
3012 struct bnx2x_softc *sc = params->sc;
3013 ser_lane = ((params->lane_config &
3014 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
3015 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
3017 offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
3018 (phy->addr + ser_lane) : 0;
3020 if (USES_WARPCORE(sc)) {
3021 aer_val = elink_get_warpcore_lane(params);
3022 /* In Dual-lane mode, two lanes are joined together,
3023 * so in order to configure them, the AER broadcast method is
3025 * 0x200 is the broadcast address for lanes 0,1
3026 * 0x201 is the broadcast address for lanes 2,3
3028 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)
3029 aer_val = (aer_val >> 1) | 0x200;
3030 } else if (CHIP_IS_E2(sc))
3031 aer_val = 0x3800 + offset - 1;
3033 aer_val = 0x3800 + offset;
3035 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
3036 MDIO_AER_BLOCK_AER_REG, aer_val);
3040 /******************************************************************/
3041 /* Internal phy section */
3042 /******************************************************************/
3044 static void elink_set_serdes_access(struct bnx2x_softc *sc, uint8_t port)
3046 uint32_t emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3049 REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_ST + port * 0x10, 1);
3050 REG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
3052 REG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
3055 REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_ST + port * 0x10, 0);
3058 static void elink_serdes_deassert(struct bnx2x_softc *sc, uint8_t port)
3062 PMD_DRV_LOG(DEBUG, sc, "elink_serdes_deassert");
3064 val = ELINK_SERDES_RESET_BITS << (port * 16);
3066 /* Reset and unreset the SerDes/XGXS */
3067 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3069 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3071 elink_set_serdes_access(sc, port);
3073 REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_DEVAD + port * 0x10,
3074 ELINK_DEFAULT_PHY_DEV_ADDR);
3077 static void elink_xgxs_specific_func(struct elink_phy *phy,
3078 struct elink_params *params,
3081 struct bnx2x_softc *sc = params->sc;
3083 case ELINK_PHY_INIT:
3084 /* Set correct devad */
3085 REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_ST + params->port * 0x18, 0);
3086 REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port * 0x18,
3092 static void elink_xgxs_deassert(struct elink_params *params)
3094 struct bnx2x_softc *sc = params->sc;
3097 PMD_DRV_LOG(DEBUG, sc, "elink_xgxs_deassert");
3098 port = params->port;
3100 val = ELINK_XGXS_RESET_BITS << (port * 16);
3102 /* Reset and unreset the SerDes/XGXS */
3103 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3105 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3106 elink_xgxs_specific_func(¶ms->phy[ELINK_INT_PHY], params,
3110 static void elink_calc_ieee_aneg_adv(struct elink_phy *phy,
3111 struct elink_params *params,
3114 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
3115 /* Resolve pause mode and advertisement Please refer to Table
3116 * 28B-3 of the 802.3ab-1999 spec
3119 switch (phy->req_flow_ctrl) {
3120 case ELINK_FLOW_CTRL_AUTO:
3121 switch (params->req_fc_auto_adv) {
3122 case ELINK_FLOW_CTRL_BOTH:
3123 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3125 case ELINK_FLOW_CTRL_RX:
3126 case ELINK_FLOW_CTRL_TX:
3128 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3134 case ELINK_FLOW_CTRL_TX:
3135 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3138 case ELINK_FLOW_CTRL_RX:
3139 case ELINK_FLOW_CTRL_BOTH:
3140 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3143 case ELINK_FLOW_CTRL_NONE:
3145 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3148 PMD_DRV_LOG(DEBUG, params->sc, "ieee_fc = 0x%x", *ieee_fc);
3151 static void set_phy_vars(struct elink_params *params, struct elink_vars *vars)
3153 uint8_t actual_phy_idx, phy_index, link_cfg_idx;
3154 uint8_t phy_config_swapped = params->multi_phy_config &
3155 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
3156 for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys;
3158 link_cfg_idx = ELINK_LINK_CONFIG_IDX(phy_index);
3159 actual_phy_idx = phy_index;
3160 if (phy_config_swapped) {
3161 if (phy_index == ELINK_EXT_PHY1)
3162 actual_phy_idx = ELINK_EXT_PHY2;
3163 else if (phy_index == ELINK_EXT_PHY2)
3164 actual_phy_idx = ELINK_EXT_PHY1;
3166 params->phy[actual_phy_idx].req_flow_ctrl =
3167 params->req_flow_ctrl[link_cfg_idx];
3169 params->phy[actual_phy_idx].req_line_speed =
3170 params->req_line_speed[link_cfg_idx];
3172 params->phy[actual_phy_idx].speed_cap_mask =
3173 params->speed_cap_mask[link_cfg_idx];
3175 params->phy[actual_phy_idx].req_duplex =
3176 params->req_duplex[link_cfg_idx];
3178 if (params->req_line_speed[link_cfg_idx] ==
3179 ELINK_SPEED_AUTO_NEG)
3180 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
3182 PMD_DRV_LOG(DEBUG, params->sc, "req_flow_ctrl %x, req_line_speed %x,"
3183 " speed_cap_mask %x",
3184 params->phy[actual_phy_idx].req_flow_ctrl,
3185 params->phy[actual_phy_idx].req_line_speed,
3186 params->phy[actual_phy_idx].speed_cap_mask);
3190 static void elink_ext_phy_set_pause(struct elink_params *params,
3191 struct elink_phy *phy,
3192 struct elink_vars *vars)
3195 struct bnx2x_softc *sc = params->sc;
3196 /* Read modify write pause advertizing */
3197 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
3199 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
3201 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3202 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3203 if ((vars->ieee_fc &
3204 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3205 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3206 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3208 if ((vars->ieee_fc &
3209 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3210 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3211 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
3213 PMD_DRV_LOG(DEBUG, sc, "Ext phy AN advertize 0x%x", val);
3214 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
3217 static void elink_pause_resolve(struct elink_vars *vars, uint32_t pause_result)
3219 switch (pause_result) { /* ASYM P ASYM P */
3220 case 0xb: /* 1 0 1 1 */
3221 vars->flow_ctrl = ELINK_FLOW_CTRL_TX;
3224 case 0xe: /* 1 1 1 0 */
3225 vars->flow_ctrl = ELINK_FLOW_CTRL_RX;
3228 case 0x5: /* 0 1 0 1 */
3229 case 0x7: /* 0 1 1 1 */
3230 case 0xd: /* 1 1 0 1 */
3231 case 0xf: /* 1 1 1 1 */
3232 vars->flow_ctrl = ELINK_FLOW_CTRL_BOTH;
3238 if (pause_result & (1 << 0))
3239 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
3240 if (pause_result & (1 << 1))
3241 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
3245 static void elink_ext_phy_update_adv_fc(struct elink_phy *phy,
3246 struct elink_params *params,
3247 struct elink_vars *vars)
3249 uint16_t ld_pause; /* local */
3250 uint16_t lp_pause; /* link partner */
3251 uint16_t pause_result;
3252 struct bnx2x_softc *sc = params->sc;
3253 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE) {
3254 elink_cl22_read(sc, phy, 0x4, &ld_pause);
3255 elink_cl22_read(sc, phy, 0x5, &lp_pause);
3256 } else if (CHIP_IS_E3(sc) && ELINK_SINGLE_MEDIA_DIRECT(params)) {
3257 uint8_t lane = elink_get_warpcore_lane(params);
3258 uint16_t gp_status, gp_mask;
3259 elink_cl45_read(sc, phy,
3260 MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4,
3262 gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL |
3263 MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) <<
3265 if ((gp_status & gp_mask) == gp_mask) {
3266 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
3267 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3268 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
3269 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3271 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
3272 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
3273 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
3274 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
3275 ld_pause = ((ld_pause &
3276 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3278 lp_pause = ((lp_pause &
3279 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3283 elink_cl45_read(sc, phy,
3285 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3286 elink_cl45_read(sc, phy,
3288 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3290 pause_result = (ld_pause & MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
3291 pause_result |= (lp_pause & MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
3292 PMD_DRV_LOG(DEBUG, sc, "Ext PHY pause result 0x%x", pause_result);
3293 elink_pause_resolve(vars, pause_result);
3297 static uint8_t elink_ext_phy_resolve_fc(struct elink_phy *phy,
3298 struct elink_params *params,
3299 struct elink_vars *vars)
3302 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
3303 if (phy->req_flow_ctrl != ELINK_FLOW_CTRL_AUTO) {
3304 /* Update the advertised flow-controled of LD/LP in AN */
3305 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)
3306 elink_ext_phy_update_adv_fc(phy, params, vars);
3307 /* But set the flow-control result as the requested one */
3308 vars->flow_ctrl = phy->req_flow_ctrl;
3309 } else if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG)
3310 vars->flow_ctrl = params->req_fc_auto_adv;
3311 else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
3313 elink_ext_phy_update_adv_fc(phy, params, vars);
3318 /******************************************************************/
3319 /* Warpcore section */
3320 /******************************************************************/
3321 /* The init_internal_warpcore should mirror the xgxs,
3322 * i.e. reset the lane (if needed), set aer for the
3323 * init configuration, and set/clear SGMII flag. Internal
3324 * phy init is done purely in phy_init stage.
3326 #define WC_TX_DRIVER(post2, idriver, ipre) \
3327 ((post2 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | \
3328 (idriver << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | \
3329 (ipre << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET))
3331 #define WC_TX_FIR(post, main, pre) \
3332 ((post << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | \
3333 (main << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | \
3334 (pre << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET))
3336 static void elink_warpcore_enable_AN_KR2(struct elink_phy *phy,
3337 struct elink_params *params,
3338 struct elink_vars *vars)
3340 struct bnx2x_softc *sc = params->sc;
3342 static struct elink_reg_set reg_set[] = {
3343 /* Step 1 - Program the TX/RX alignment markers */
3344 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0xa157},
3345 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xcbe2},
3346 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0x7537},
3347 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0xa157},
3348 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xcbe2},
3349 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0x7537},
3350 /* Step 2 - Configure the NP registers */
3351 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000a},
3352 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6400},
3353 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0620},
3354 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0157},
3355 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x6464},
3356 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x3150},
3357 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x3150},
3358 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0157},
3359 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0620}
3361 PMD_DRV_LOG(DEBUG, sc, "Enabling 20G-KR2");
3363 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3364 MDIO_WC_REG_CL49_USERB0_CTRL, (3 << 6));
3366 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3367 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
3370 /* Start KR2 work-around timer which handles BNX2X8073 link-parner */
3371 vars->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE;
3372 elink_update_link_attr(params, vars->link_attr_sync);
3375 static void elink_disable_kr2(struct elink_params *params,
3376 struct elink_vars *vars, struct elink_phy *phy)
3378 struct bnx2x_softc *sc = params->sc;
3380 static struct elink_reg_set reg_set[] = {
3381 /* Step 1 - Program the TX/RX alignment markers */
3382 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0x7690},
3383 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xe647},
3384 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0xc4f0},
3385 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0x7690},
3386 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xe647},
3387 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0xc4f0},
3388 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000c},
3389 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6000},
3390 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0000},
3391 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0002},
3392 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x0000},
3393 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x0af7},
3394 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x0af7},
3395 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0002},
3396 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0000}
3398 PMD_DRV_LOG(DEBUG, sc, "Disabling 20G-KR2");
3400 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3401 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
3403 vars->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE;
3404 elink_update_link_attr(params, vars->link_attr_sync);
3406 vars->check_kr2_recovery_cnt = ELINK_CHECK_KR2_RECOVERY_CNT;
3409 static void elink_warpcore_set_lpi_passthrough(struct elink_phy *phy,
3410 struct elink_params *params)
3412 struct bnx2x_softc *sc = params->sc;
3414 PMD_DRV_LOG(DEBUG, sc, "Configure WC for LPI pass through");
3415 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3416 MDIO_WC_REG_EEE_COMBO_CONTROL0, 0x7c);
3417 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3418 MDIO_WC_REG_DIGITAL4_MISC5, 0xc000);
3421 static void elink_warpcore_restart_AN_KR(struct elink_phy *phy,
3422 struct elink_params *params)
3424 /* Restart autoneg on the leading lane only */
3425 struct bnx2x_softc *sc = params->sc;
3426 uint16_t lane = elink_get_warpcore_lane(params);
3427 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
3428 MDIO_AER_BLOCK_AER_REG, lane);
3429 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
3430 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
3433 elink_set_aer_mmd(params, phy);
3436 static void elink_warpcore_enable_AN_KR(struct elink_phy *phy,
3437 struct elink_params *params,
3438 struct elink_vars *vars)
3440 uint16_t lane, i, cl72_ctrl, an_adv = 0;
3441 struct bnx2x_softc *sc = params->sc;
3442 static struct elink_reg_set reg_set[] = {
3443 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
3444 {MDIO_PMA_DEVAD, MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0},
3445 {MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415},
3446 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190},
3447 /* Disable Autoneg: re-enable it after adv is done. */
3448 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0},
3449 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2},
3450 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0},
3452 PMD_DRV_LOG(DEBUG, sc, "Enable Auto Negotiation for KR");
3453 /* Set to default registers that may be overridden by 10G force */
3454 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3455 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
3458 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3459 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &cl72_ctrl);
3460 cl72_ctrl &= 0x08ff;
3461 cl72_ctrl |= 0x3800;
3462 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3463 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, cl72_ctrl);
3465 /* Check adding advertisement for 1G KX */
3466 if (((vars->line_speed == ELINK_SPEED_AUTO_NEG) &&
3467 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
3468 (vars->line_speed == ELINK_SPEED_1000)) {
3469 uint16_t addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2;
3472 /* Enable CL37 1G Parallel Detect */
3473 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, addr, 0x1);
3474 PMD_DRV_LOG(DEBUG, sc, "Advertize 1G");
3476 if (((vars->line_speed == ELINK_SPEED_AUTO_NEG) &&
3477 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
3478 (vars->line_speed == ELINK_SPEED_10000)) {
3479 /* Check adding advertisement for 10G KR */
3481 /* Enable 10G Parallel Detect */
3482 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
3483 MDIO_AER_BLOCK_AER_REG, 0);
3485 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
3486 MDIO_WC_REG_PAR_DET_10G_CTRL, 1);
3487 elink_set_aer_mmd(params, phy);
3488 PMD_DRV_LOG(DEBUG, sc, "Advertize 10G");
3491 /* Set Transmit PMD settings */
3492 lane = elink_get_warpcore_lane(params);
3493 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3494 MDIO_WC_REG_TX0_TX_DRIVER + 0x10 * lane,
3495 WC_TX_DRIVER(0x02, 0x06, 0x09));
3496 /* Configure the next lane if dual mode */
3497 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)
3498 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3499 MDIO_WC_REG_TX0_TX_DRIVER + 0x10 * (lane + 1),
3500 WC_TX_DRIVER(0x02, 0x06, 0x09));
3501 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3502 MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL, 0x03f0);
3503 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3504 MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL, 0x03f0);
3506 /* Advertised speeds */
3507 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
3508 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, an_adv);
3510 /* Advertised and set FEC (Forward Error Correction) */
3511 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
3512 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2,
3513 (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY |
3514 MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ));
3516 /* Enable CL37 BAM */
3517 if (REG_RD(sc, params->shmem_base +
3518 offsetof(struct shmem_region,
3519 dev_info.port_hw_config[params->port].
3521 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
3522 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3523 MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL,
3525 PMD_DRV_LOG(DEBUG, sc, "Enable CL37 BAM on KR");
3528 /* Advertise pause */
3529 elink_ext_phy_set_pause(params, phy, vars);
3530 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
3531 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3532 MDIO_WC_REG_DIGITAL5_MISC7, 0x100);
3534 /* Over 1G - AN local device user page 1 */
3535 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3536 MDIO_WC_REG_DIGITAL3_UP1, 0x1f);
3538 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
3539 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) ||
3540 (phy->req_line_speed == ELINK_SPEED_20000)) {
3542 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
3543 MDIO_AER_BLOCK_AER_REG, lane);
3545 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3546 MDIO_WC_REG_RX1_PCI_CTRL +
3547 (0x10 * lane), (1 << 11));
3549 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3550 MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7);
3551 elink_set_aer_mmd(params, phy);
3553 elink_warpcore_enable_AN_KR2(phy, params, vars);
3555 elink_disable_kr2(params, vars, phy);
3558 /* Enable Autoneg: only on the main lane */
3559 elink_warpcore_restart_AN_KR(phy, params);
3562 static void elink_warpcore_set_10G_KR(struct elink_phy *phy,
3563 struct elink_params *params)
3565 struct bnx2x_softc *sc = params->sc;
3566 uint16_t val16, i, lane;
3567 static struct elink_reg_set reg_set[] = {
3568 /* Disable Autoneg */
3569 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
3570 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3572 {MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0},
3573 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0},
3574 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1},
3575 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa},
3576 /* Leave cl72 training enable, needed for KR */
3577 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2}
3580 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3581 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
3584 lane = elink_get_warpcore_lane(params);
3585 /* Global registers */
3586 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
3587 MDIO_AER_BLOCK_AER_REG, 0);
3588 /* Disable CL36 PCS Tx */
3589 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3590 MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
3591 val16 &= ~(0x0011 << lane);
3592 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3593 MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);
3595 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3596 MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);
3597 val16 |= (0x0303 << (lane << 1));
3598 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3599 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);
3601 elink_set_aer_mmd(params, phy);
3602 /* Set speed via PMA/PMD register */
3603 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD,
3604 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
3606 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD,
3607 MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB);
3609 /* Enable encoded forced speed */
3610 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3611 MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30);
3613 /* Turn TX scramble payload only the 64/66 scrambler */
3614 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_TX66_CONTROL, 0x9);
3616 /* Turn RX scramble payload only the 64/66 scrambler */
3617 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3618 MDIO_WC_REG_RX66_CONTROL, 0xF9);
3620 /* Set and clear loopback to cause a reset to 64/66 decoder */
3621 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3622 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000);
3623 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3624 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3628 static void elink_warpcore_set_10G_XFI(struct elink_phy *phy,
3629 struct elink_params *params,
3632 struct bnx2x_softc *sc = params->sc;
3633 uint16_t misc1_val, tap_val, tx_driver_val, lane, val;
3634 uint32_t cfg_tap_val, tx_drv_brdct, tx_equal;
3636 /* Hold rxSeqStart */
3637 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3638 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000);
3640 /* Hold tx_fifo_reset */
3641 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3642 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x1);
3644 /* Disable CL73 AN */
3645 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
3647 /* Disable 100FX Enable and Auto-Detect */
3648 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
3649 MDIO_WC_REG_FX100_CTRL1, 0xFFFA);
3651 /* Disable 100FX Idle detect */
3652 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3653 MDIO_WC_REG_FX100_CTRL3, 0x0080);
3655 /* Set Block address to Remote PHY & Clear forced_speed[5] */
3656 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
3657 MDIO_WC_REG_DIGITAL4_MISC3, 0xFF7F);
3659 /* Turn off auto-detect & fiber mode */
3660 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
3661 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3664 /* Set filter_force_link, disable_false_link and parallel_detect */
3665 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3666 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val);
3667 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3668 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3669 ((val | 0x0006) & 0xFFFE));
3672 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3673 MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val);
3675 misc1_val &= ~(0x1f);
3679 tap_val = WC_TX_FIR(0x08, 0x37, 0x00);
3680 tx_driver_val = WC_TX_DRIVER(0x00, 0x02, 0x03);
3682 cfg_tap_val = REG_RD(sc, params->shmem_base +
3683 offsetof(struct shmem_region,
3684 dev_info.port_hw_config[params->
3685 port].sfi_tap_values));
3687 tx_equal = cfg_tap_val & PORT_HW_CFG_TX_EQUALIZATION_MASK;
3689 tx_drv_brdct = (cfg_tap_val &
3690 PORT_HW_CFG_TX_DRV_BROADCAST_MASK) >>
3691 PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT;
3695 /* TAP values are controlled by nvram, if value there isn't 0 */
3697 tap_val = (uint16_t) tx_equal;
3699 tap_val = WC_TX_FIR(0x0f, 0x2b, 0x02);
3703 WC_TX_DRIVER(0x03, (uint16_t) tx_drv_brdct, 0x06);
3705 tx_driver_val = WC_TX_DRIVER(0x03, 0x02, 0x06);
3707 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3708 MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val);
3710 /* Set Transmit PMD settings */
3711 lane = elink_get_warpcore_lane(params);
3712 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3713 MDIO_WC_REG_TX_FIR_TAP,
3714 tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE);
3715 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3716 MDIO_WC_REG_TX0_TX_DRIVER + 0x10 * lane,
3719 /* Enable fiber mode, enable and invert sig_det */
3720 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3721 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0xd);
3723 /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */
3724 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3725 MDIO_WC_REG_DIGITAL4_MISC3, 0x8080);
3727 elink_warpcore_set_lpi_passthrough(phy, params);
3729 /* 10G XFI Full Duplex */
3730 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3731 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100);
3733 /* Release tx_fifo_reset */
3734 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
3735 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
3737 /* Release rxSeqStart */
3738 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
3739 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x7FFF);
3742 static void elink_warpcore_set_20G_force_KR2(struct elink_phy *phy,
3743 struct elink_params *params)
3746 struct bnx2x_softc *sc = params->sc;
3747 /* Set global registers, so set AER lane to 0 */
3748 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
3749 MDIO_AER_BLOCK_AER_REG, 0);
3751 /* Disable sequencer */
3752 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
3753 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~(1 << 13));
3755 elink_set_aer_mmd(params, phy);
3757 elink_cl45_read_and_write(sc, phy, MDIO_PMA_DEVAD,
3758 MDIO_WC_REG_PMD_KR_CONTROL, ~(1 << 1));
3759 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
3761 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3762 MDIO_WC_REG_CL73_USERB0_CTRL, &val);
3765 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3766 MDIO_WC_REG_CL73_USERB0_CTRL, val);
3768 /* Set 20G KR2 force speed */
3769 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3770 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x1f);
3772 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3773 MDIO_WC_REG_DIGITAL4_MISC3, (1 << 7));
3775 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3776 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &val);
3779 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3780 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, val);
3781 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3782 MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0x835A);
3784 /* Enable sequencer (over lane 0) */
3785 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
3786 MDIO_AER_BLOCK_AER_REG, 0);
3788 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3789 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, (1 << 13));
3791 elink_set_aer_mmd(params, phy);
3794 static void elink_warpcore_set_20G_DXGXS(struct bnx2x_softc *sc,
3795 struct elink_phy *phy, uint16_t lane)
3797 /* Rx0 anaRxControl1G */
3798 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3799 MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90);
3801 /* Rx2 anaRxControl1G */
3802 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3803 MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90);
3805 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_RX66_SCW0, 0xE070);
3807 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_RX66_SCW1, 0xC0D0);
3809 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_RX66_SCW2, 0xA0B0);
3811 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_RX66_SCW3, 0x8090);
3813 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3814 MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0);
3816 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3817 MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0);
3819 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3820 MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0);
3822 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3823 MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0);
3825 /* Serdes Digital Misc1 */
3826 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3827 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008);
3829 /* Serdes Digital4 Misc3 */
3830 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3831 MDIO_WC_REG_DIGITAL4_MISC3, 0x8088);
3833 /* Set Transmit PMD settings */
3834 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3835 MDIO_WC_REG_TX_FIR_TAP,
3836 (WC_TX_FIR(0x12, 0x2d, 0x00) |
3837 MDIO_WC_REG_TX_FIR_TAP_ENABLE));
3838 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3839 MDIO_WC_REG_TX0_TX_DRIVER + 0x10 * lane,
3840 WC_TX_DRIVER(0x02, 0x02, 0x02));
3843 static void elink_warpcore_set_sgmii_speed(struct elink_phy *phy,
3844 struct elink_params *params,
3846 uint8_t always_autoneg)
3848 struct bnx2x_softc *sc = params->sc;
3849 uint16_t val16, digctrl_kx1, digctrl_kx2;
3851 /* Clear XFI clock comp in non-10G single lane mode. */
3852 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
3853 MDIO_WC_REG_RX66_CONTROL, ~(3 << 13));
3855 elink_warpcore_set_lpi_passthrough(phy, params);
3857 if (always_autoneg || phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {
3859 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3860 MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
3862 PMD_DRV_LOG(DEBUG, sc, "set SGMII AUTONEG");
3864 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3865 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
3867 switch (phy->req_line_speed) {
3868 case ELINK_SPEED_10:
3870 case ELINK_SPEED_100:
3873 case ELINK_SPEED_1000:
3877 PMD_DRV_LOG(DEBUG, sc,
3878 "Speed not supported: 0x%x",
3879 phy->req_line_speed);
3883 if (phy->req_duplex == DUPLEX_FULL)
3886 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3887 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);
3889 PMD_DRV_LOG(DEBUG, sc, "set SGMII force speed %d",
3890 phy->req_line_speed);
3891 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3892 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
3893 PMD_DRV_LOG(DEBUG, sc, " (readback) %x", val16);
3896 /* SGMII Slave mode and disable signal detect */
3897 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3898 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1);
3902 digctrl_kx1 &= 0xff4a;
3904 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3905 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, digctrl_kx1);
3907 /* Turn off parallel detect */
3908 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3909 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2);
3910 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3911 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3912 (digctrl_kx2 & ~(1 << 2)));
3914 /* Re-enable parallel detect */
3915 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3916 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3917 (digctrl_kx2 | (1 << 2)));
3919 /* Enable autodet */
3920 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3921 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3922 (digctrl_kx1 | 0x10));
3925 static void elink_warpcore_reset_lane(struct bnx2x_softc *sc,
3926 struct elink_phy *phy, uint8_t reset)
3929 /* Take lane out of reset after configuration is finished */
3930 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3931 MDIO_WC_REG_DIGITAL5_MISC6, &val);
3936 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3937 MDIO_WC_REG_DIGITAL5_MISC6, val);
3938 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3939 MDIO_WC_REG_DIGITAL5_MISC6, &val);
3942 /* Clear SFI/XFI link settings registers */
3943 static void elink_warpcore_clear_regs(struct elink_phy *phy,
3944 struct elink_params *params,
3947 struct bnx2x_softc *sc = params->sc;
3949 static struct elink_reg_set wc_regs[] = {
3950 {MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0},
3951 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL1, 0x014a},
3952 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800},
3953 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008},
3954 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3956 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3958 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
3960 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000},
3961 {MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000},
3962 {MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040},
3963 {MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140}
3965 /* Set XFI clock comp as default. */
3966 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3967 MDIO_WC_REG_RX66_CONTROL, (3 << 13));
3969 for (i = 0; i < ARRAY_SIZE(wc_regs); i++)
3970 elink_cl45_write(sc, phy, wc_regs[i].devad, wc_regs[i].reg,
3973 lane = elink_get_warpcore_lane(params);
3974 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3975 MDIO_WC_REG_TX0_TX_DRIVER + 0x10 * lane, 0x0990);
3979 static elink_status_t elink_get_mod_abs_int_cfg(struct bnx2x_softc *sc,
3980 uint32_t shmem_base,
3983 uint8_t * gpio_port)
3988 if (CHIP_IS_E3(sc)) {
3989 cfg_pin = (REG_RD(sc, shmem_base +
3990 offsetof(struct shmem_region,
3991 dev_info.port_hw_config[port].
3993 PORT_HW_CFG_E3_MOD_ABS_MASK) >>
3994 PORT_HW_CFG_E3_MOD_ABS_SHIFT;
3996 /* Should not happen. This function called upon interrupt
3997 * triggered by GPIO ( since EPIO can only generate interrupts
3999 * So if this function was called and none of the GPIOs was set,
4000 * it means the shit hit the fan.
4002 if ((cfg_pin < PIN_CFG_GPIO0_P0) ||
4003 (cfg_pin > PIN_CFG_GPIO3_P1)) {
4004 PMD_DRV_LOG(DEBUG, sc,
4005 "No cfg pin %x for module detect indication",
4007 return ELINK_STATUS_ERROR;
4010 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3;
4011 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2;
4013 *gpio_num = MISC_REGISTERS_GPIO_3;
4017 return ELINK_STATUS_OK;
4020 static int elink_is_sfp_module_plugged(struct elink_params *params)
4022 struct bnx2x_softc *sc = params->sc;
4023 uint8_t gpio_num, gpio_port;
4025 if (elink_get_mod_abs_int_cfg(sc,
4026 params->shmem_base, params->port,
4027 &gpio_num, &gpio_port) != ELINK_STATUS_OK)
4029 gpio_val = elink_cb_gpio_read(sc, gpio_num, gpio_port);
4031 /* Call the handling function in case module is detected */
4038 static int elink_warpcore_get_sigdet(struct elink_phy *phy,
4039 struct elink_params *params)
4041 uint16_t gp2_status_reg0, lane;
4042 struct bnx2x_softc *sc = params->sc;
4044 lane = elink_get_warpcore_lane(params);
4046 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0,
4049 return (gp2_status_reg0 >> (8 + lane)) & 0x1;
4052 static void elink_warpcore_config_runtime(struct elink_phy *phy,
4053 struct elink_params *params,
4054 struct elink_vars *vars)
4056 struct bnx2x_softc *sc = params->sc;
4057 uint32_t serdes_net_if;
4058 uint16_t gp_status1 = 0, lnkup = 0, lnkup_kr = 0;
4060 vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1;
4062 if (!vars->turn_to_run_wc_rt)
4065 if (vars->rx_tx_asic_rst) {
4066 uint16_t lane = elink_get_warpcore_lane(params);
4067 serdes_net_if = (REG_RD(sc, params->shmem_base +
4068 offsetof(struct shmem_region,
4069 dev_info.port_hw_config
4072 PORT_HW_CFG_NET_SERDES_IF_MASK);
4074 switch (serdes_net_if) {
4075 case PORT_HW_CFG_NET_SERDES_IF_KR:
4076 /* Do we get link yet? */
4077 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 0x81d1,
4079 lnkup = (gp_status1 >> (8 + lane)) & 0x1; /* 1G */
4081 lnkup_kr = (gp_status1 >> (12 + lane)) & 0x1;
4083 if (lnkup_kr || lnkup) {
4084 vars->rx_tx_asic_rst = 0;
4086 /* Reset the lane to see if link comes up. */
4087 elink_warpcore_reset_lane(sc, phy, 1);
4088 elink_warpcore_reset_lane(sc, phy, 0);
4090 /* Restart Autoneg */
4091 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
4092 MDIO_WC_REG_IEEE0BLK_MIICNTL,
4095 vars->rx_tx_asic_rst--;
4096 PMD_DRV_LOG(DEBUG, sc, "0x%x retry left",
4097 vars->rx_tx_asic_rst);
4106 /*params->rx_tx_asic_rst */
4109 static void elink_warpcore_config_sfi(struct elink_phy *phy,
4110 struct elink_params *params)
4112 uint16_t lane = elink_get_warpcore_lane(params);
4114 elink_warpcore_clear_regs(phy, params, lane);
4115 if ((params->req_line_speed[ELINK_LINK_CONFIG_IDX(ELINK_INT_PHY)] ==
4116 ELINK_SPEED_10000) &&
4117 (phy->media_type != ELINK_ETH_PHY_SFP_1G_FIBER)) {
4118 PMD_DRV_LOG(DEBUG, params->sc, "Setting 10G SFI");
4119 elink_warpcore_set_10G_XFI(phy, params, 0);
4121 PMD_DRV_LOG(DEBUG, params->sc, "Setting 1G Fiber");
4122 elink_warpcore_set_sgmii_speed(phy, params, 1, 0);
4126 static void elink_sfp_e3_set_transmitter(struct elink_params *params,
4127 struct elink_phy *phy, uint8_t tx_en)
4129 struct bnx2x_softc *sc = params->sc;
4131 uint8_t port = params->port;
4133 cfg_pin = REG_RD(sc, params->shmem_base +
4134 offsetof(struct shmem_region,
4135 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4136 PORT_HW_CFG_E3_TX_LASER_MASK;
4137 /* Set the !tx_en since this pin is DISABLE_TX_LASER */
4138 PMD_DRV_LOG(DEBUG, sc, "Setting WC TX to %d", tx_en);
4140 /* For 20G, the expected pin to be used is 3 pins after the current */
4141 elink_set_cfg_pin(sc, cfg_pin, tx_en ^ 1);
4142 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
4143 elink_set_cfg_pin(sc, cfg_pin + 3, tx_en ^ 1);
4146 static uint8_t elink_warpcore_config_init(struct elink_phy *phy,
4147 struct elink_params *params,
4148 struct elink_vars *vars)
4150 struct bnx2x_softc *sc = params->sc;
4151 uint32_t serdes_net_if;
4153 uint16_t lane = elink_get_warpcore_lane(params);
4154 serdes_net_if = (REG_RD(sc, params->shmem_base +
4155 offsetof(struct shmem_region,
4156 dev_info.port_hw_config[params->port].
4158 PORT_HW_CFG_NET_SERDES_IF_MASK);
4159 PMD_DRV_LOG(DEBUG, sc,
4160 "Begin Warpcore init, link_speed %d, "
4161 "serdes_net_if = 0x%x", vars->line_speed, serdes_net_if);
4162 elink_set_aer_mmd(params, phy);
4163 elink_warpcore_reset_lane(sc, phy, 1);
4164 vars->phy_flags |= PHY_XGXS_FLAG;
4165 if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) ||
4166 (phy->req_line_speed &&
4167 ((phy->req_line_speed == ELINK_SPEED_100) ||
4168 (phy->req_line_speed == ELINK_SPEED_10)))) {
4169 vars->phy_flags |= PHY_SGMII_FLAG;
4170 PMD_DRV_LOG(DEBUG, sc, "Setting SGMII mode");
4171 elink_warpcore_clear_regs(phy, params, lane);
4172 elink_warpcore_set_sgmii_speed(phy, params, 0, 1);
4174 switch (serdes_net_if) {
4175 case PORT_HW_CFG_NET_SERDES_IF_KR:
4176 /* Enable KR Auto Neg */
4177 if (params->loopback_mode != ELINK_LOOPBACK_EXT)
4178 elink_warpcore_enable_AN_KR(phy, params, vars);
4180 PMD_DRV_LOG(DEBUG, sc, "Setting KR 10G-Force");
4181 elink_warpcore_set_10G_KR(phy, params);
4185 case PORT_HW_CFG_NET_SERDES_IF_XFI:
4186 elink_warpcore_clear_regs(phy, params, lane);
4187 if (vars->line_speed == ELINK_SPEED_10000) {
4188 PMD_DRV_LOG(DEBUG, sc, "Setting 10G XFI");
4189 elink_warpcore_set_10G_XFI(phy, params, 1);
4191 if (ELINK_SINGLE_MEDIA_DIRECT(params)) {
4192 PMD_DRV_LOG(DEBUG, sc, "1G Fiber");
4195 PMD_DRV_LOG(DEBUG, sc, "10/100/1G SGMII");
4198 elink_warpcore_set_sgmii_speed(phy,
4205 case PORT_HW_CFG_NET_SERDES_IF_SFI:
4206 /* Issue Module detection if module is plugged, or
4207 * enabled transmitter to avoid current leakage in case
4208 * no module is connected
4210 if ((params->loopback_mode == ELINK_LOOPBACK_NONE) ||
4211 (params->loopback_mode == ELINK_LOOPBACK_EXT)) {
4212 if (elink_is_sfp_module_plugged(params))
4213 elink_sfp_module_detection(phy, params);
4215 elink_sfp_e3_set_transmitter(params,
4219 elink_warpcore_config_sfi(phy, params);
4222 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
4223 if (vars->line_speed != ELINK_SPEED_20000) {
4224 PMD_DRV_LOG(DEBUG, sc, "Speed not supported yet");
4227 PMD_DRV_LOG(DEBUG, sc, "Setting 20G DXGXS");
4228 elink_warpcore_set_20G_DXGXS(sc, phy, lane);
4229 /* Issue Module detection */
4231 elink_sfp_module_detection(phy, params);
4233 case PORT_HW_CFG_NET_SERDES_IF_KR2:
4234 if (!params->loopback_mode) {
4235 elink_warpcore_enable_AN_KR(phy, params, vars);
4237 PMD_DRV_LOG(DEBUG, sc, "Setting KR 20G-Force");
4238 elink_warpcore_set_20G_force_KR2(phy, params);
4242 PMD_DRV_LOG(DEBUG, sc,
4243 "Unsupported Serdes Net Interface 0x%x",
4249 /* Take lane out of reset after configuration is finished */
4250 elink_warpcore_reset_lane(sc, phy, 0);
4251 PMD_DRV_LOG(DEBUG, sc, "Exit config init");
4256 static void elink_warpcore_link_reset(struct elink_phy *phy,
4257 struct elink_params *params)
4259 struct bnx2x_softc *sc = params->sc;
4260 uint16_t val16, lane;
4261 elink_sfp_e3_set_transmitter(params, phy, 0);
4262 elink_set_mdio_emac_per_phy(sc, params);
4263 elink_set_aer_mmd(params, phy);
4264 /* Global register */
4265 elink_warpcore_reset_lane(sc, phy, 1);
4267 /* Clear loopback settings (if any) */
4269 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4270 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0xBFFF);
4272 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4273 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0xfffe);
4275 /* Update those 1-copy registers */
4276 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
4277 MDIO_AER_BLOCK_AER_REG, 0);
4278 /* Enable 1G MDIO (1-copy) */
4279 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4280 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~0x10);
4282 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4283 MDIO_WC_REG_XGXSBLK1_LANECTRL2, 0xff00);
4284 lane = elink_get_warpcore_lane(params);
4285 /* Disable CL36 PCS Tx */
4286 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4287 MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
4288 val16 |= (0x11 << lane);
4289 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)
4290 val16 |= (0x22 << lane);
4291 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4292 MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);
4294 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4295 MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);
4296 val16 &= ~(0x0303 << (lane << 1));
4297 val16 |= (0x0101 << (lane << 1));
4298 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE) {
4299 val16 &= ~(0x0c0c << (lane << 1));
4300 val16 |= (0x0404 << (lane << 1));
4303 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4304 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);
4306 elink_set_aer_mmd(params, phy);
4310 static void elink_set_warpcore_loopback(struct elink_phy *phy,
4311 struct elink_params *params)
4313 struct bnx2x_softc *sc = params->sc;
4316 PMD_DRV_LOG(DEBUG, sc, "Setting Warpcore loopback type %x, speed %d",
4317 params->loopback_mode, phy->req_line_speed);
4319 if (phy->req_line_speed < ELINK_SPEED_10000 ||
4320 phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) {
4321 /* 10/100/1000/20G-KR2 */
4323 /* Update those 1-copy registers */
4324 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
4325 MDIO_AER_BLOCK_AER_REG, 0);
4326 /* Enable 1G MDIO (1-copy) */
4327 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4328 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4330 /* Set 1G loopback based on lane (1-copy) */
4331 lane = elink_get_warpcore_lane(params);
4332 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4333 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4334 val16 |= (1 << lane);
4335 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)
4336 val16 |= (2 << lane);
4337 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4338 MDIO_WC_REG_XGXSBLK1_LANECTRL2, val16);
4340 /* Switch back to 4-copy registers */
4341 elink_set_aer_mmd(params, phy);
4343 /* 10G / 20G-DXGXS */
4344 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4345 MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4347 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4348 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1);
4352 static void elink_sync_link(struct elink_params *params,
4353 struct elink_vars *vars)
4355 struct bnx2x_softc *sc = params->sc;
4356 uint8_t link_10g_plus;
4357 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4358 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
4359 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
4360 if (vars->link_up) {
4361 PMD_DRV_LOG(DEBUG, sc, "phy link up");
4363 vars->phy_link_up = 1;
4364 vars->duplex = DUPLEX_FULL;
4365 switch (vars->link_status & LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
4366 case ELINK_LINK_10THD:
4367 vars->duplex = DUPLEX_HALF;
4369 case ELINK_LINK_10TFD:
4370 vars->line_speed = ELINK_SPEED_10;
4373 case ELINK_LINK_100TXHD:
4374 vars->duplex = DUPLEX_HALF;
4376 case ELINK_LINK_100T4:
4377 case ELINK_LINK_100TXFD:
4378 vars->line_speed = ELINK_SPEED_100;
4381 case ELINK_LINK_1000THD:
4382 vars->duplex = DUPLEX_HALF;
4384 case ELINK_LINK_1000TFD:
4385 vars->line_speed = ELINK_SPEED_1000;
4388 case ELINK_LINK_2500THD:
4389 vars->duplex = DUPLEX_HALF;
4391 case ELINK_LINK_2500TFD:
4392 vars->line_speed = ELINK_SPEED_2500;
4395 case ELINK_LINK_10GTFD:
4396 vars->line_speed = ELINK_SPEED_10000;
4398 case ELINK_LINK_20GTFD:
4399 vars->line_speed = ELINK_SPEED_20000;
4404 vars->flow_ctrl = 0;
4405 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
4406 vars->flow_ctrl |= ELINK_FLOW_CTRL_TX;
4408 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
4409 vars->flow_ctrl |= ELINK_FLOW_CTRL_RX;
4411 if (!vars->flow_ctrl)
4412 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
4414 if (vars->line_speed &&
4415 ((vars->line_speed == ELINK_SPEED_10) ||
4416 (vars->line_speed == ELINK_SPEED_100))) {
4417 vars->phy_flags |= PHY_SGMII_FLAG;
4419 vars->phy_flags &= ~PHY_SGMII_FLAG;
4421 if (vars->line_speed &&
4422 USES_WARPCORE(sc) && (vars->line_speed == ELINK_SPEED_1000))
4423 vars->phy_flags |= PHY_SGMII_FLAG;
4424 /* Anything 10 and over uses the bmac */
4425 link_10g_plus = (vars->line_speed >= ELINK_SPEED_10000);
4427 if (link_10g_plus) {
4428 if (USES_WARPCORE(sc))
4429 vars->mac_type = ELINK_MAC_TYPE_XMAC;
4431 vars->mac_type = ELINK_MAC_TYPE_BMAC;
4433 if (USES_WARPCORE(sc))
4434 vars->mac_type = ELINK_MAC_TYPE_UMAC;
4436 vars->mac_type = ELINK_MAC_TYPE_EMAC;
4438 } else { /* Link down */
4439 PMD_DRV_LOG(DEBUG, sc, "phy link down");
4441 vars->phy_link_up = 0;
4443 vars->line_speed = 0;
4444 vars->duplex = DUPLEX_FULL;
4445 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
4447 /* Indicate no mac active */
4448 vars->mac_type = ELINK_MAC_TYPE_NONE;
4449 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4450 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
4451 if (vars->link_status & LINK_STATUS_SFP_TX_FAULT)
4452 vars->phy_flags |= PHY_SFP_TX_FAULT_FLAG;
4456 void elink_link_status_update(struct elink_params *params,
4457 struct elink_vars *vars)
4459 struct bnx2x_softc *sc = params->sc;
4460 uint8_t port = params->port;
4461 uint32_t sync_offset, media_types;
4462 /* Update PHY configuration */
4463 set_phy_vars(params, vars);
4465 vars->link_status = REG_RD(sc, params->shmem_base +
4466 offsetof(struct shmem_region,
4467 port_mb[port].link_status));
4469 /* Force link UP in non LOOPBACK_EXT loopback mode(s) */
4470 if (params->loopback_mode != ELINK_LOOPBACK_NONE &&
4471 params->loopback_mode != ELINK_LOOPBACK_EXT)
4472 vars->link_status |= LINK_STATUS_LINK_UP;
4474 if (elink_eee_has_cap(params))
4475 vars->eee_status = REG_RD(sc, params->shmem2_base +
4476 offsetof(struct shmem2_region,
4477 eee_status[params->port]));
4479 vars->phy_flags = PHY_XGXS_FLAG;
4480 elink_sync_link(params, vars);
4481 /* Sync media type */
4482 sync_offset = params->shmem_base +
4483 offsetof(struct shmem_region,
4484 dev_info.port_hw_config[port].media_type);
4485 media_types = REG_RD(sc, sync_offset);
4487 params->phy[ELINK_INT_PHY].media_type =
4488 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
4489 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
4490 params->phy[ELINK_EXT_PHY1].media_type =
4491 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
4492 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
4493 params->phy[ELINK_EXT_PHY2].media_type =
4494 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
4495 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
4496 PMD_DRV_LOG(DEBUG, sc, "media_types = 0x%x", media_types);
4498 /* Sync AEU offset */
4499 sync_offset = params->shmem_base +
4500 offsetof(struct shmem_region,
4501 dev_info.port_hw_config[port].aeu_int_mask);
4503 vars->aeu_int_mask = REG_RD(sc, sync_offset);
4505 /* Sync PFC status */
4506 if (vars->link_status & LINK_STATUS_PFC_ENABLED)
4507 params->feature_config_flags |=
4508 ELINK_FEATURE_CONFIG_PFC_ENABLED;
4510 params->feature_config_flags &=
4511 ~ELINK_FEATURE_CONFIG_PFC_ENABLED;
4513 if (SHMEM2_HAS(sc, link_attr_sync))
4514 vars->link_attr_sync = SHMEM2_RD(sc,
4515 link_attr_sync[params->port]);
4517 PMD_DRV_LOG(DEBUG, sc, "link_status 0x%x phy_link_up %x int_mask 0x%x",
4518 vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
4519 PMD_DRV_LOG(DEBUG, sc, "line_speed %x duplex %x flow_ctrl 0x%x",
4520 vars->line_speed, vars->duplex, vars->flow_ctrl);
4523 static void elink_set_master_ln(struct elink_params *params,
4524 struct elink_phy *phy)
4526 struct bnx2x_softc *sc = params->sc;
4527 uint16_t new_master_ln, ser_lane;
4528 ser_lane = ((params->lane_config &
4529 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4530 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4532 /* Set the master_ln for AN */
4533 CL22_RD_OVER_CL45(sc, phy,
4534 MDIO_REG_BANK_XGXS_BLOCK2,
4535 MDIO_XGXS_BLOCK2_TEST_MODE_LANE, &new_master_ln);
4537 CL22_WR_OVER_CL45(sc, phy,
4538 MDIO_REG_BANK_XGXS_BLOCK2,
4539 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4540 (new_master_ln | ser_lane));
4543 static elink_status_t elink_reset_unicore(struct elink_params *params,
4544 struct elink_phy *phy,
4547 struct bnx2x_softc *sc = params->sc;
4548 uint16_t mii_control;
4550 CL22_RD_OVER_CL45(sc, phy,
4551 MDIO_REG_BANK_COMBO_IEEE0,
4552 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
4554 /* Reset the unicore */
4555 CL22_WR_OVER_CL45(sc, phy,
4556 MDIO_REG_BANK_COMBO_IEEE0,
4557 MDIO_COMBO_IEEE0_MII_CONTROL,
4558 (mii_control | MDIO_COMBO_IEEO_MII_CONTROL_RESET));
4560 elink_set_serdes_access(sc, params->port);
4562 /* Wait for the reset to self clear */
4563 for (i = 0; i < ELINK_MDIO_ACCESS_TIMEOUT; i++) {
4566 /* The reset erased the previous bank value */
4567 CL22_RD_OVER_CL45(sc, phy,
4568 MDIO_REG_BANK_COMBO_IEEE0,
4569 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
4571 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
4573 return ELINK_STATUS_OK;
4577 elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, params->port); // "Warning: PHY was not initialized,"
4580 PMD_DRV_LOG(DEBUG, sc, "BUG! XGXS is still in reset!");
4581 return ELINK_STATUS_ERROR;
4585 static void elink_set_swap_lanes(struct elink_params *params,
4586 struct elink_phy *phy)
4588 struct bnx2x_softc *sc = params->sc;
4589 /* Each two bits represents a lane number:
4590 * No swap is 0123 => 0x1b no need to enable the swap
4592 uint16_t rx_lane_swap, tx_lane_swap;
4594 rx_lane_swap = ((params->lane_config &
4595 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
4596 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
4597 tx_lane_swap = ((params->lane_config &
4598 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
4599 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
4601 if (rx_lane_swap != 0x1b) {
4602 CL22_WR_OVER_CL45(sc, phy,
4603 MDIO_REG_BANK_XGXS_BLOCK2,
4604 MDIO_XGXS_BLOCK2_RX_LN_SWAP,
4606 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
4607 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
4609 CL22_WR_OVER_CL45(sc, phy,
4610 MDIO_REG_BANK_XGXS_BLOCK2,
4611 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
4614 if (tx_lane_swap != 0x1b) {
4615 CL22_WR_OVER_CL45(sc, phy,
4616 MDIO_REG_BANK_XGXS_BLOCK2,
4617 MDIO_XGXS_BLOCK2_TX_LN_SWAP,
4619 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
4621 CL22_WR_OVER_CL45(sc, phy,
4622 MDIO_REG_BANK_XGXS_BLOCK2,
4623 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
4627 static void elink_set_parallel_detection(struct elink_phy *phy,
4628 struct elink_params *params)
4630 struct bnx2x_softc *sc = params->sc;
4632 CL22_RD_OVER_CL45(sc, phy,
4633 MDIO_REG_BANK_SERDES_DIGITAL,
4634 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, &control2);
4635 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4636 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4638 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4639 PMD_DRV_LOG(DEBUG, sc, "phy->speed_cap_mask = 0x%x, control2 = 0x%x",
4640 phy->speed_cap_mask, control2);
4641 CL22_WR_OVER_CL45(sc, phy,
4642 MDIO_REG_BANK_SERDES_DIGITAL,
4643 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, control2);
4645 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
4646 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
4647 PMD_DRV_LOG(DEBUG, sc, "XGXS");
4649 CL22_WR_OVER_CL45(sc, phy,
4650 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4651 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
4652 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
4654 CL22_RD_OVER_CL45(sc, phy,
4655 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4656 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4660 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
4662 CL22_WR_OVER_CL45(sc, phy,
4663 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4664 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4667 /* Disable parallel detection of HiG */
4668 CL22_WR_OVER_CL45(sc, phy,
4669 MDIO_REG_BANK_XGXS_BLOCK2,
4670 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
4671 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
4672 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
4676 static void elink_set_autoneg(struct elink_phy *phy,
4677 struct elink_params *params,
4678 struct elink_vars *vars, uint8_t enable_cl73)
4680 struct bnx2x_softc *sc = params->sc;
4684 CL22_RD_OVER_CL45(sc, phy,
4685 MDIO_REG_BANK_COMBO_IEEE0,
4686 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val);
4688 /* CL37 Autoneg Enabled */
4689 if (vars->line_speed == ELINK_SPEED_AUTO_NEG)
4690 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
4691 else /* CL37 Autoneg Disabled */
4692 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4693 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
4695 CL22_WR_OVER_CL45(sc, phy,
4696 MDIO_REG_BANK_COMBO_IEEE0,
4697 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
4699 /* Enable/Disable Autodetection */
4701 CL22_RD_OVER_CL45(sc, phy,
4702 MDIO_REG_BANK_SERDES_DIGITAL,
4703 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, ®_val);
4704 reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
4705 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
4706 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
4707 if (vars->line_speed == ELINK_SPEED_AUTO_NEG)
4708 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
4710 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
4712 CL22_WR_OVER_CL45(sc, phy,
4713 MDIO_REG_BANK_SERDES_DIGITAL,
4714 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
4716 /* Enable TetonII and BAM autoneg */
4717 CL22_RD_OVER_CL45(sc, phy,
4718 MDIO_REG_BANK_BAM_NEXT_PAGE,
4719 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, ®_val);
4720 if (vars->line_speed == ELINK_SPEED_AUTO_NEG) {
4721 /* Enable BAM aneg Mode and TetonII aneg Mode */
4722 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
4723 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
4725 /* TetonII and BAM Autoneg Disabled */
4726 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
4727 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
4729 CL22_WR_OVER_CL45(sc, phy,
4730 MDIO_REG_BANK_BAM_NEXT_PAGE,
4731 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, reg_val);
4734 /* Enable Cl73 FSM status bits */
4735 CL22_WR_OVER_CL45(sc, phy,
4736 MDIO_REG_BANK_CL73_USERB0,
4737 MDIO_CL73_USERB0_CL73_UCTRL, 0xe);
4739 /* Enable BAM Station Manager */
4740 CL22_WR_OVER_CL45(sc, phy,
4741 MDIO_REG_BANK_CL73_USERB0,
4742 MDIO_CL73_USERB0_CL73_BAM_CTRL1,
4743 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
4744 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN
4746 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
4748 /* Advertise CL73 link speeds */
4749 CL22_RD_OVER_CL45(sc, phy,
4750 MDIO_REG_BANK_CL73_IEEEB1,
4751 MDIO_CL73_IEEEB1_AN_ADV2, ®_val);
4752 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
4753 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
4754 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4755 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
4757 CL22_WR_OVER_CL45(sc, phy,
4758 MDIO_REG_BANK_CL73_IEEEB1,
4759 MDIO_CL73_IEEEB1_AN_ADV2, reg_val);
4761 /* CL73 Autoneg Enabled */
4762 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
4764 } else /* CL73 Autoneg Disabled */
4767 CL22_WR_OVER_CL45(sc, phy,
4768 MDIO_REG_BANK_CL73_IEEEB0,
4769 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
4772 /* Program SerDes, forced speed */
4773 static void elink_program_serdes(struct elink_phy *phy,
4774 struct elink_params *params,
4775 struct elink_vars *vars)
4777 struct bnx2x_softc *sc = params->sc;
4780 /* Program duplex, disable autoneg and sgmii */
4781 CL22_RD_OVER_CL45(sc, phy,
4782 MDIO_REG_BANK_COMBO_IEEE0,
4783 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val);
4784 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
4785 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4786 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
4787 if (phy->req_duplex == DUPLEX_FULL)
4788 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
4789 CL22_WR_OVER_CL45(sc, phy,
4790 MDIO_REG_BANK_COMBO_IEEE0,
4791 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
4794 * - needed only if the speed is greater than 1G (2.5G or 10G)
4796 CL22_RD_OVER_CL45(sc, phy,
4797 MDIO_REG_BANK_SERDES_DIGITAL,
4798 MDIO_SERDES_DIGITAL_MISC1, ®_val);
4799 /* Clearing the speed value before setting the right speed */
4800 PMD_DRV_LOG(DEBUG, sc, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x", reg_val);
4802 reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
4803 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
4805 if (!((vars->line_speed == ELINK_SPEED_1000) ||
4806 (vars->line_speed == ELINK_SPEED_100) ||
4807 (vars->line_speed == ELINK_SPEED_10))) {
4809 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
4810 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
4811 if (vars->line_speed == ELINK_SPEED_10000)
4813 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
4816 CL22_WR_OVER_CL45(sc, phy,
4817 MDIO_REG_BANK_SERDES_DIGITAL,
4818 MDIO_SERDES_DIGITAL_MISC1, reg_val);
4822 static void elink_set_brcm_cl37_advertisement(struct elink_phy *phy,
4823 struct elink_params *params)
4825 struct bnx2x_softc *sc = params->sc;
4828 /* Set extended capabilities */
4829 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
4830 val |= MDIO_OVER_1G_UP1_2_5G;
4831 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
4832 val |= MDIO_OVER_1G_UP1_10G;
4833 CL22_WR_OVER_CL45(sc, phy,
4834 MDIO_REG_BANK_OVER_1G, MDIO_OVER_1G_UP1, val);
4836 CL22_WR_OVER_CL45(sc, phy,
4837 MDIO_REG_BANK_OVER_1G, MDIO_OVER_1G_UP3, 0x400);
4840 static void elink_set_ieee_aneg_advertisement(struct elink_phy *phy,
4841 struct elink_params *params,
4844 struct bnx2x_softc *sc = params->sc;
4846 /* For AN, we are always publishing full duplex */
4848 CL22_WR_OVER_CL45(sc, phy,
4849 MDIO_REG_BANK_COMBO_IEEE0,
4850 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
4851 CL22_RD_OVER_CL45(sc, phy,
4852 MDIO_REG_BANK_CL73_IEEEB1,
4853 MDIO_CL73_IEEEB1_AN_ADV1, &val);
4854 val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
4855 val |= ((ieee_fc << 3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
4856 CL22_WR_OVER_CL45(sc, phy,
4857 MDIO_REG_BANK_CL73_IEEEB1,
4858 MDIO_CL73_IEEEB1_AN_ADV1, val);
4861 static void elink_restart_autoneg(struct elink_phy *phy,
4862 struct elink_params *params,
4863 uint8_t enable_cl73)
4865 struct bnx2x_softc *sc = params->sc;
4866 uint16_t mii_control;
4868 PMD_DRV_LOG(DEBUG, sc, "elink_restart_autoneg");
4869 /* Enable and restart BAM/CL37 aneg */
4872 CL22_RD_OVER_CL45(sc, phy,
4873 MDIO_REG_BANK_CL73_IEEEB0,
4874 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
4877 CL22_WR_OVER_CL45(sc, phy,
4878 MDIO_REG_BANK_CL73_IEEEB0,
4879 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
4881 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
4882 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
4885 CL22_RD_OVER_CL45(sc, phy,
4886 MDIO_REG_BANK_COMBO_IEEE0,
4887 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
4888 PMD_DRV_LOG(DEBUG, sc,
4889 "elink_restart_autoneg mii_control before = 0x%x",
4891 CL22_WR_OVER_CL45(sc, phy,
4892 MDIO_REG_BANK_COMBO_IEEE0,
4893 MDIO_COMBO_IEEE0_MII_CONTROL,
4895 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4896 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
4900 static void elink_initialize_sgmii_process(struct elink_phy *phy,
4901 struct elink_params *params,
4902 struct elink_vars *vars)
4904 struct bnx2x_softc *sc = params->sc;
4907 /* In SGMII mode, the unicore is always slave */
4909 CL22_RD_OVER_CL45(sc, phy,
4910 MDIO_REG_BANK_SERDES_DIGITAL,
4911 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &control1);
4912 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
4913 /* Set sgmii mode (and not fiber) */
4914 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
4915 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
4916 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
4917 CL22_WR_OVER_CL45(sc, phy,
4918 MDIO_REG_BANK_SERDES_DIGITAL,
4919 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, control1);
4921 /* If forced speed */
4922 if (!(vars->line_speed == ELINK_SPEED_AUTO_NEG)) {
4923 /* Set speed, disable autoneg */
4924 uint16_t mii_control;
4926 CL22_RD_OVER_CL45(sc, phy,
4927 MDIO_REG_BANK_COMBO_IEEE0,
4928 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
4929 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4930 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK |
4931 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
4933 switch (vars->line_speed) {
4934 case ELINK_SPEED_100:
4936 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
4938 case ELINK_SPEED_1000:
4940 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
4942 case ELINK_SPEED_10:
4943 /* There is nothing to set for 10M */
4946 /* Invalid speed for SGMII */
4947 PMD_DRV_LOG(DEBUG, sc, "Invalid line_speed 0x%x",
4952 /* Setting the full duplex */
4953 if (phy->req_duplex == DUPLEX_FULL)
4954 mii_control |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
4955 CL22_WR_OVER_CL45(sc, phy,
4956 MDIO_REG_BANK_COMBO_IEEE0,
4957 MDIO_COMBO_IEEE0_MII_CONTROL, mii_control);
4959 } else { /* AN mode */
4960 /* Enable and restart AN */
4961 elink_restart_autoneg(phy, params, 0);
4967 static elink_status_t elink_direct_parallel_detect_used(struct elink_phy *phy,
4971 struct bnx2x_softc *sc = params->sc;
4972 uint16_t pd_10g, status2_1000x;
4973 if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG)
4974 return ELINK_STATUS_OK;
4975 CL22_RD_OVER_CL45(sc, phy,
4976 MDIO_REG_BANK_SERDES_DIGITAL,
4977 MDIO_SERDES_DIGITAL_A_1000X_STATUS2, &status2_1000x);
4978 CL22_RD_OVER_CL45(sc, phy,
4979 MDIO_REG_BANK_SERDES_DIGITAL,
4980 MDIO_SERDES_DIGITAL_A_1000X_STATUS2, &status2_1000x);
4981 if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
4982 PMD_DRV_LOG(DEBUG, sc, "1G parallel detect link on port %d",
4984 return ELINK_STATUS_ERROR;
4987 CL22_RD_OVER_CL45(sc, phy,
4988 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4989 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS, &pd_10g);
4991 if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
4992 PMD_DRV_LOG(DEBUG, sc, "10G parallel detect link on port %d",
4994 return ELINK_STATUS_ERROR;
4996 return ELINK_STATUS_OK;
4999 static void elink_update_adv_fc(struct elink_phy *phy,
5000 struct elink_params *params,
5001 struct elink_vars *vars, uint32_t gp_status)
5003 uint16_t ld_pause; /* local driver */
5004 uint16_t lp_pause; /* link partner */
5005 uint16_t pause_result;
5006 struct bnx2x_softc *sc = params->sc;
5008 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5009 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
5010 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5011 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
5013 CL22_RD_OVER_CL45(sc, phy,
5014 MDIO_REG_BANK_CL73_IEEEB1,
5015 MDIO_CL73_IEEEB1_AN_ADV1, &ld_pause);
5016 CL22_RD_OVER_CL45(sc, phy,
5017 MDIO_REG_BANK_CL73_IEEEB1,
5018 MDIO_CL73_IEEEB1_AN_LP_ADV1, &lp_pause);
5019 pause_result = (ld_pause &
5020 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8;
5021 pause_result |= (lp_pause &
5022 MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10;
5023 PMD_DRV_LOG(DEBUG, sc, "pause_result CL73 0x%x", pause_result);
5025 CL22_RD_OVER_CL45(sc, phy,
5026 MDIO_REG_BANK_COMBO_IEEE0,
5027 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, &ld_pause);
5028 CL22_RD_OVER_CL45(sc, phy,
5029 MDIO_REG_BANK_COMBO_IEEE0,
5030 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
5032 pause_result = (ld_pause &
5033 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) >> 5;
5034 pause_result |= (lp_pause &
5035 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) >> 7;
5036 PMD_DRV_LOG(DEBUG, sc, "pause_result CL37 0x%x", pause_result);
5038 elink_pause_resolve(vars, pause_result);
5042 static void elink_flow_ctrl_resolve(struct elink_phy *phy,
5043 struct elink_params *params,
5044 struct elink_vars *vars, uint32_t gp_status)
5046 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
5048 /* Resolve from gp_status in case of AN complete and not sgmii */
5049 if (phy->req_flow_ctrl != ELINK_FLOW_CTRL_AUTO) {
5050 /* Update the advertised flow-controled of LD/LP in AN */
5051 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)
5052 elink_update_adv_fc(phy, params, vars, gp_status);
5053 /* But set the flow-control result as the requested one */
5054 vars->flow_ctrl = phy->req_flow_ctrl;
5055 } else if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG)
5056 vars->flow_ctrl = params->req_fc_auto_adv;
5057 else if ((gp_status & ELINK_MDIO_AN_CL73_OR_37_COMPLETE) &&
5058 (!(vars->phy_flags & PHY_SGMII_FLAG))) {
5059 if (elink_direct_parallel_detect_used(phy, params)) {
5060 vars->flow_ctrl = params->req_fc_auto_adv;
5063 elink_update_adv_fc(phy, params, vars, gp_status);
5065 PMD_DRV_LOG(DEBUG, params->sc, "flow_ctrl 0x%x", vars->flow_ctrl);
5068 static void elink_check_fallback_to_cl37(struct elink_phy *phy,
5069 struct elink_params *params)
5071 struct bnx2x_softc *sc = params->sc;
5072 uint16_t rx_status, ustat_val, cl37_fsm_received;
5073 PMD_DRV_LOG(DEBUG, sc, "elink_check_fallback_to_cl37");
5074 /* Step 1: Make sure signal is detected */
5075 CL22_RD_OVER_CL45(sc, phy,
5076 MDIO_REG_BANK_RX0, MDIO_RX0_RX_STATUS, &rx_status);
5077 if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
5078 (MDIO_RX0_RX_STATUS_SIGDET)) {
5079 PMD_DRV_LOG(DEBUG, sc, "Signal is not detected. Restoring CL73."
5080 "rx_status(0x80b0) = 0x%x", rx_status);
5081 CL22_WR_OVER_CL45(sc, phy,
5082 MDIO_REG_BANK_CL73_IEEEB0,
5083 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5084 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
5087 /* Step 2: Check CL73 state machine */
5088 CL22_RD_OVER_CL45(sc, phy,
5089 MDIO_REG_BANK_CL73_USERB0,
5090 MDIO_CL73_USERB0_CL73_USTAT1, &ustat_val);
5092 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5093 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
5094 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5095 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
5096 PMD_DRV_LOG(DEBUG, sc, "CL73 state-machine is not stable. "
5097 "ustat_val(0x8371) = 0x%x", ustat_val);
5100 /* Step 3: Check CL37 Message Pages received to indicate LP
5101 * supports only CL37
5103 CL22_RD_OVER_CL45(sc, phy,
5104 MDIO_REG_BANK_REMOTE_PHY,
5105 MDIO_REMOTE_PHY_MISC_RX_STATUS, &cl37_fsm_received);
5106 if ((cl37_fsm_received &
5107 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5108 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
5109 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5110 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
5111 PMD_DRV_LOG(DEBUG, sc, "No CL37 FSM were received. "
5112 "misc_rx_status(0x8330) = 0x%x", cl37_fsm_received);
5115 /* The combined cl37/cl73 fsm state information indicating that
5116 * we are connected to a device which does not support cl73, but
5117 * does support cl37 BAM. In this case we disable cl73 and
5118 * restart cl37 auto-neg
5122 CL22_WR_OVER_CL45(sc, phy,
5123 MDIO_REG_BANK_CL73_IEEEB0,
5124 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 0);
5125 /* Restart CL37 autoneg */
5126 elink_restart_autoneg(phy, params, 0);
5127 PMD_DRV_LOG(DEBUG, sc, "Disabling CL73, and restarting CL37 autoneg");
5130 static void elink_xgxs_an_resolve(struct elink_phy *phy,
5131 struct elink_params *params,
5132 struct elink_vars *vars, uint32_t gp_status)
5134 if (gp_status & ELINK_MDIO_AN_CL73_OR_37_COMPLETE)
5135 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5137 if (elink_direct_parallel_detect_used(phy, params))
5138 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
5141 static elink_status_t elink_get_link_speed_duplex(struct elink_phy *phy,
5142 struct elink_params *params __rte_unused,
5143 struct elink_vars *vars,
5144 uint16_t is_link_up,
5145 uint16_t speed_mask,
5148 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)
5149 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
5151 PMD_DRV_LOG(DEBUG, params->sc, "phy link up");
5153 vars->phy_link_up = 1;
5154 vars->link_status |= LINK_STATUS_LINK_UP;
5156 switch (speed_mask) {
5157 case ELINK_GP_STATUS_10M:
5158 vars->line_speed = ELINK_SPEED_10;
5159 if (is_duplex == DUPLEX_FULL)
5160 vars->link_status |= ELINK_LINK_10TFD;
5162 vars->link_status |= ELINK_LINK_10THD;
5165 case ELINK_GP_STATUS_100M:
5166 vars->line_speed = ELINK_SPEED_100;
5167 if (is_duplex == DUPLEX_FULL)
5168 vars->link_status |= ELINK_LINK_100TXFD;
5170 vars->link_status |= ELINK_LINK_100TXHD;
5173 case ELINK_GP_STATUS_1G:
5174 case ELINK_GP_STATUS_1G_KX:
5175 vars->line_speed = ELINK_SPEED_1000;
5176 if (is_duplex == DUPLEX_FULL)
5177 vars->link_status |= ELINK_LINK_1000TFD;
5179 vars->link_status |= ELINK_LINK_1000THD;
5182 case ELINK_GP_STATUS_2_5G:
5183 vars->line_speed = ELINK_SPEED_2500;
5184 if (is_duplex == DUPLEX_FULL)
5185 vars->link_status |= ELINK_LINK_2500TFD;
5187 vars->link_status |= ELINK_LINK_2500THD;
5190 case ELINK_GP_STATUS_5G:
5191 case ELINK_GP_STATUS_6G:
5192 PMD_DRV_LOG(DEBUG, params->sc,
5193 "link speed unsupported gp_status 0x%x",
5195 return ELINK_STATUS_ERROR;
5197 case ELINK_GP_STATUS_10G_KX4:
5198 case ELINK_GP_STATUS_10G_HIG:
5199 case ELINK_GP_STATUS_10G_CX4:
5200 case ELINK_GP_STATUS_10G_KR:
5201 case ELINK_GP_STATUS_10G_SFI:
5202 case ELINK_GP_STATUS_10G_XFI:
5203 vars->line_speed = ELINK_SPEED_10000;
5204 vars->link_status |= ELINK_LINK_10GTFD;
5206 case ELINK_GP_STATUS_20G_DXGXS:
5207 case ELINK_GP_STATUS_20G_KR2:
5208 vars->line_speed = ELINK_SPEED_20000;
5209 vars->link_status |= ELINK_LINK_20GTFD;
5212 PMD_DRV_LOG(DEBUG, params->sc,
5213 "link speed unsupported gp_status 0x%x",
5215 return ELINK_STATUS_ERROR;
5217 } else { /* link_down */
5218 PMD_DRV_LOG(DEBUG, params->sc, "phy link down");
5220 vars->phy_link_up = 0;
5222 vars->duplex = DUPLEX_FULL;
5223 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
5224 vars->mac_type = ELINK_MAC_TYPE_NONE;
5226 PMD_DRV_LOG(DEBUG, params->sc, " phy_link_up %x line_speed %d",
5227 vars->phy_link_up, vars->line_speed);
5228 return ELINK_STATUS_OK;
5231 static uint8_t elink_link_settings_status(struct elink_phy *phy,
5232 struct elink_params *params,
5233 struct elink_vars *vars)
5235 struct bnx2x_softc *sc = params->sc;
5237 uint16_t gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask;
5238 elink_status_t rc = ELINK_STATUS_OK;
5240 /* Read gp_status */
5241 CL22_RD_OVER_CL45(sc, phy,
5242 MDIO_REG_BANK_GP_STATUS,
5243 MDIO_GP_STATUS_TOP_AN_STATUS1, &gp_status);
5244 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
5245 duplex = DUPLEX_FULL;
5246 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)
5248 speed_mask = gp_status & ELINK_GP_STATUS_SPEED_MASK;
5249 PMD_DRV_LOG(DEBUG, sc, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x",
5250 gp_status, link_up, speed_mask);
5251 rc = elink_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,
5253 if (rc == ELINK_STATUS_ERROR)
5256 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
5257 if (ELINK_SINGLE_MEDIA_DIRECT(params)) {
5258 vars->duplex = duplex;
5259 elink_flow_ctrl_resolve(phy, params, vars, gp_status);
5260 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)
5261 elink_xgxs_an_resolve(phy, params, vars,
5264 } else { /* Link_down */
5265 if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
5266 ELINK_SINGLE_MEDIA_DIRECT(params)) {
5267 /* Check signal is detected */
5268 elink_check_fallback_to_cl37(phy, params);
5272 /* Read LP advertised speeds */
5273 if (ELINK_SINGLE_MEDIA_DIRECT(params) &&
5274 (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) {
5277 CL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_CL73_IEEEB1,
5278 MDIO_CL73_IEEEB1_AN_LP_ADV2, &val);
5280 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5281 vars->link_status |=
5282 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5283 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5284 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5285 vars->link_status |=
5286 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5288 CL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_OVER_1G,
5289 MDIO_OVER_1G_LP_UP1, &val);
5291 if (val & MDIO_OVER_1G_UP1_2_5G)
5292 vars->link_status |=
5293 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5294 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5295 vars->link_status |=
5296 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5299 PMD_DRV_LOG(DEBUG, sc, "duplex %x flow_ctrl 0x%x link_status 0x%x",
5300 vars->duplex, vars->flow_ctrl, vars->link_status);
5304 static uint8_t elink_warpcore_read_status(struct elink_phy *phy,
5305 struct elink_params *params,
5306 struct elink_vars *vars)
5308 struct bnx2x_softc *sc = params->sc;
5310 uint16_t gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL;
5311 elink_status_t rc = ELINK_STATUS_OK;
5312 lane = elink_get_warpcore_lane(params);
5313 /* Read gp_status */
5314 if ((params->loopback_mode) && (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)) {
5315 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5316 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
5317 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5318 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
5320 } else if ((phy->req_line_speed > ELINK_SPEED_10000) &&
5321 (phy->supported & ELINK_SUPPORTED_20000baseMLD2_Full)) {
5322 uint16_t temp_link_up;
5323 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 1, &temp_link_up);
5324 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 1, &link_up);
5325 PMD_DRV_LOG(DEBUG, sc, "PCS RX link status = 0x%x-->0x%x",
5326 temp_link_up, link_up);
5327 link_up &= (1 << 2);
5329 elink_ext_phy_resolve_fc(phy, params, vars);
5331 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5332 MDIO_WC_REG_GP2_STATUS_GP_2_1, &gp_status1);
5333 PMD_DRV_LOG(DEBUG, sc, "0x81d1 = 0x%x", gp_status1);
5334 /* Check for either KR, 1G, or AN up. */
5335 link_up = ((gp_status1 >> 8) |
5336 (gp_status1 >> 12) | (gp_status1)) & (1 << lane);
5337 if (phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) {
5339 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
5340 MDIO_AN_REG_STATUS, &an_link);
5341 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
5342 MDIO_AN_REG_STATUS, &an_link);
5343 link_up |= (an_link & (1 << 2));
5345 if (link_up && ELINK_SINGLE_MEDIA_DIRECT(params)) {
5346 uint16_t pd, gp_status4;
5347 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {
5348 /* Check Autoneg complete */
5349 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5350 MDIO_WC_REG_GP2_STATUS_GP_2_4,
5352 if (gp_status4 & ((1 << 12) << lane))
5353 vars->link_status |=
5354 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5356 /* Check parallel detect used */
5357 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5358 MDIO_WC_REG_PAR_DET_10G_STATUS,
5361 vars->link_status |=
5362 LINK_STATUS_PARALLEL_DETECTION_USED;
5364 elink_ext_phy_resolve_fc(phy, params, vars);
5365 vars->duplex = duplex;
5369 if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) &&
5370 ELINK_SINGLE_MEDIA_DIRECT(params)) {
5373 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
5374 MDIO_AN_REG_LP_AUTO_NEG2, &val);
5376 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5377 vars->link_status |=
5378 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5379 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5380 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5381 vars->link_status |=
5382 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5384 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5385 MDIO_WC_REG_DIGITAL3_LP_UP1, &val);
5387 if (val & MDIO_OVER_1G_UP1_2_5G)
5388 vars->link_status |=
5389 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5390 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5391 vars->link_status |=
5392 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5397 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5398 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed);
5400 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5401 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed);
5403 PMD_DRV_LOG(DEBUG, sc, "lane %d gp_speed 0x%x", lane, gp_speed);
5405 if ((lane & 1) == 0)
5408 link_up = ! !link_up;
5410 /* Reset the TX FIFO to fix SGMII issue */
5411 rc = elink_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,
5414 /* In case of KR link down, start up the recovering procedure */
5415 if ((!link_up) && (phy->media_type == ELINK_ETH_PHY_KR) &&
5416 (!(phy->flags & ELINK_FLAGS_WC_DUAL_MODE)))
5417 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
5419 PMD_DRV_LOG(DEBUG, sc, "duplex %x flow_ctrl 0x%x link_status 0x%x",
5420 vars->duplex, vars->flow_ctrl, vars->link_status);
5424 static void elink_set_gmii_tx_driver(struct elink_params *params)
5426 struct bnx2x_softc *sc = params->sc;
5427 struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY];
5433 CL22_RD_OVER_CL45(sc, phy,
5434 MDIO_REG_BANK_OVER_1G, MDIO_OVER_1G_LP_UP2, &lp_up2);
5436 /* Bits [10:7] at lp_up2, positioned at [15:12] */
5437 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
5438 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
5439 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
5444 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
5445 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
5446 CL22_RD_OVER_CL45(sc, phy,
5447 bank, MDIO_TX0_TX_DRIVER, &tx_driver);
5449 /* Replace tx_driver bits [15:12] */
5450 if (lp_up2 != (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
5451 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
5452 tx_driver |= lp_up2;
5453 CL22_WR_OVER_CL45(sc, phy,
5454 bank, MDIO_TX0_TX_DRIVER, tx_driver);
5459 static elink_status_t elink_emac_program(struct elink_params *params,
5460 struct elink_vars *vars)
5462 struct bnx2x_softc *sc = params->sc;
5463 uint8_t port = params->port;
5466 PMD_DRV_LOG(DEBUG, sc, "setting link speed & duplex");
5467 elink_bits_dis(sc, GRCBASE_EMAC0 + port * 0x400 +
5469 (EMAC_MODE_25G_MODE |
5470 EMAC_MODE_PORT_MII_10M | EMAC_MODE_HALF_DUPLEX));
5471 switch (vars->line_speed) {
5472 case ELINK_SPEED_10:
5473 mode |= EMAC_MODE_PORT_MII_10M;
5476 case ELINK_SPEED_100:
5477 mode |= EMAC_MODE_PORT_MII;
5480 case ELINK_SPEED_1000:
5481 mode |= EMAC_MODE_PORT_GMII;
5484 case ELINK_SPEED_2500:
5485 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
5489 /* 10G not valid for EMAC */
5490 PMD_DRV_LOG(DEBUG, sc,
5491 "Invalid line_speed 0x%x", vars->line_speed);
5492 return ELINK_STATUS_ERROR;
5495 if (vars->duplex == DUPLEX_HALF)
5496 mode |= EMAC_MODE_HALF_DUPLEX;
5498 GRCBASE_EMAC0 + port * 0x400 + EMAC_REG_EMAC_MODE, mode);
5500 elink_set_led(params, vars, ELINK_LED_MODE_OPER, vars->line_speed);
5501 return ELINK_STATUS_OK;
5504 static void elink_set_preemphasis(struct elink_phy *phy,
5505 struct elink_params *params)
5508 uint16_t bank, i = 0;
5509 struct bnx2x_softc *sc = params->sc;
5511 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
5512 bank += (MDIO_REG_BANK_RX1 - MDIO_REG_BANK_RX0), i++) {
5513 CL22_WR_OVER_CL45(sc, phy,
5515 MDIO_RX0_RX_EQ_BOOST, phy->rx_preemphasis[i]);
5518 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
5519 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
5520 CL22_WR_OVER_CL45(sc, phy,
5522 MDIO_TX0_TX_DRIVER, phy->tx_preemphasis[i]);
5526 static uint8_t elink_xgxs_config_init(struct elink_phy *phy,
5527 struct elink_params *params,
5528 struct elink_vars *vars)
5530 uint8_t enable_cl73 = (ELINK_SINGLE_MEDIA_DIRECT(params) ||
5531 (params->loopback_mode == ELINK_LOOPBACK_XGXS));
5533 if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
5534 if (ELINK_SINGLE_MEDIA_DIRECT(params) &&
5535 (params->feature_config_flags &
5536 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
5537 elink_set_preemphasis(phy, params);
5539 /* Forced speed requested? */
5540 if (vars->line_speed != ELINK_SPEED_AUTO_NEG ||
5541 (ELINK_SINGLE_MEDIA_DIRECT(params) &&
5542 params->loopback_mode == ELINK_LOOPBACK_EXT)) {
5543 PMD_DRV_LOG(DEBUG, params->sc, "not SGMII, no AN");
5545 /* Disable autoneg */
5546 elink_set_autoneg(phy, params, vars, 0);
5548 /* Program speed and duplex */
5549 elink_program_serdes(phy, params, vars);
5551 } else { /* AN_mode */
5552 PMD_DRV_LOG(DEBUG, params->sc, "not SGMII, AN");
5555 elink_set_brcm_cl37_advertisement(phy, params);
5557 /* Program duplex & pause advertisement (for aneg) */
5558 elink_set_ieee_aneg_advertisement(phy, params,
5561 /* Enable autoneg */
5562 elink_set_autoneg(phy, params, vars, enable_cl73);
5564 /* Enable and restart AN */
5565 elink_restart_autoneg(phy, params, enable_cl73);
5568 } else { /* SGMII mode */
5569 PMD_DRV_LOG(DEBUG, params->sc, "SGMII");
5571 elink_initialize_sgmii_process(phy, params, vars);
5577 static elink_status_t elink_prepare_xgxs(struct elink_phy *phy,
5578 struct elink_params *params,
5579 struct elink_vars *vars)
5582 vars->phy_flags |= PHY_XGXS_FLAG;
5583 if ((phy->req_line_speed &&
5584 ((phy->req_line_speed == ELINK_SPEED_100) ||
5585 (phy->req_line_speed == ELINK_SPEED_10))) ||
5586 (!phy->req_line_speed &&
5587 (phy->speed_cap_mask >=
5588 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
5589 (phy->speed_cap_mask <
5590 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
5591 (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))
5592 vars->phy_flags |= PHY_SGMII_FLAG;
5594 vars->phy_flags &= ~PHY_SGMII_FLAG;
5596 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
5597 elink_set_aer_mmd(params, phy);
5598 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
5599 elink_set_master_ln(params, phy);
5601 rc = elink_reset_unicore(params, phy, 0);
5602 /* Reset the SerDes and wait for reset bit return low */
5603 if (rc != ELINK_STATUS_OK)
5606 elink_set_aer_mmd(params, phy);
5607 /* Setting the masterLn_def again after the reset */
5608 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
5609 elink_set_master_ln(params, phy);
5610 elink_set_swap_lanes(params, phy);
5616 static uint16_t elink_wait_reset_complete(struct bnx2x_softc *sc,
5617 struct elink_phy *phy,
5618 struct elink_params *params)
5621 /* Wait for soft reset to get cleared up to 1 sec */
5622 for (cnt = 0; cnt < 1000; cnt++) {
5623 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE)
5624 elink_cl22_read(sc, phy, MDIO_PMA_REG_CTRL, &ctrl);
5626 elink_cl45_read(sc, phy,
5628 MDIO_PMA_REG_CTRL, &ctrl);
5629 if (!(ctrl & (1 << 15)))
5635 elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, params->port); // "Warning: PHY was not initialized,"
5638 PMD_DRV_LOG(DEBUG, sc, "control reg 0x%x (after %d ms)", ctrl, cnt);
5642 static void elink_link_int_enable(struct elink_params *params)
5644 uint8_t port = params->port;
5646 struct bnx2x_softc *sc = params->sc;
5648 /* Setting the status to report on link up for either XGXS or SerDes */
5649 if (CHIP_IS_E3(sc)) {
5650 mask = ELINK_NIG_MASK_XGXS0_LINK_STATUS;
5651 if (!(ELINK_SINGLE_MEDIA_DIRECT(params)))
5652 mask |= ELINK_NIG_MASK_MI_INT;
5653 } else if (params->switch_cfg == ELINK_SWITCH_CFG_10G) {
5654 mask = (ELINK_NIG_MASK_XGXS0_LINK10G |
5655 ELINK_NIG_MASK_XGXS0_LINK_STATUS);
5656 PMD_DRV_LOG(DEBUG, sc, "enabled XGXS interrupt");
5657 if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) &&
5658 params->phy[ELINK_INT_PHY].type !=
5659 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
5660 mask |= ELINK_NIG_MASK_MI_INT;
5661 PMD_DRV_LOG(DEBUG, sc, "enabled external phy int");
5664 } else { /* SerDes */
5665 mask = ELINK_NIG_MASK_SERDES0_LINK_STATUS;
5666 PMD_DRV_LOG(DEBUG, sc, "enabled SerDes interrupt");
5667 if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) &&
5668 params->phy[ELINK_INT_PHY].type !=
5669 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
5670 mask |= ELINK_NIG_MASK_MI_INT;
5671 PMD_DRV_LOG(DEBUG, sc, "enabled external phy int");
5674 elink_bits_en(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, mask);
5676 PMD_DRV_LOG(DEBUG, sc, "port %x, is_xgxs %x, int_status 0x%x", port,
5677 (params->switch_cfg == ELINK_SWITCH_CFG_10G),
5678 REG_RD(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4));
5679 PMD_DRV_LOG(DEBUG, sc, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x",
5680 REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4),
5681 REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port * 0x18),
5683 NIG_REG_SERDES0_STATUS_LINK_STATUS + port * 0x3c));
5684 PMD_DRV_LOG(DEBUG, sc, " 10G %x, XGXS_LINK %x",
5685 REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port * 0x68),
5686 REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port * 0x68));
5689 static void elink_rearm_latch_signal(struct bnx2x_softc *sc, uint8_t port,
5692 uint32_t latch_status = 0;
5694 /* Disable the MI INT ( external phy int ) by writing 1 to the
5695 * status register. Link down indication is high-active-signal,
5696 * so in this case we need to write the status to clear the XOR
5698 /* Read Latched signals */
5699 latch_status = REG_RD(sc, NIG_REG_LATCH_STATUS_0 + port * 8);
5700 PMD_DRV_LOG(DEBUG, sc, "latch_status = 0x%x", latch_status);
5701 /* Handle only those with latched-signal=up. */
5704 NIG_REG_STATUS_INTERRUPT_PORT0
5705 + port * 4, ELINK_NIG_STATUS_EMAC0_MI_INT);
5708 NIG_REG_STATUS_INTERRUPT_PORT0
5709 + port * 4, ELINK_NIG_STATUS_EMAC0_MI_INT);
5711 if (latch_status & 1) {
5713 /* For all latched-signal=up : Re-Arm Latch signals */
5714 REG_WR(sc, NIG_REG_LATCH_STATUS_0 + port * 8,
5715 (latch_status & 0xfffe) | (latch_status & 1));
5717 /* For all latched-signal=up,Write original_signal to status */
5720 static void elink_link_int_ack(struct elink_params *params,
5721 struct elink_vars *vars, uint8_t is_10g_plus)
5723 struct bnx2x_softc *sc = params->sc;
5724 uint8_t port = params->port;
5726 /* First reset all status we assume only one line will be
5729 elink_bits_dis(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4,
5730 (ELINK_NIG_STATUS_XGXS0_LINK10G |
5731 ELINK_NIG_STATUS_XGXS0_LINK_STATUS |
5732 ELINK_NIG_STATUS_SERDES0_LINK_STATUS));
5733 if (vars->phy_link_up) {
5734 if (USES_WARPCORE(sc))
5735 mask = ELINK_NIG_STATUS_XGXS0_LINK_STATUS;
5738 mask = ELINK_NIG_STATUS_XGXS0_LINK10G;
5739 else if (params->switch_cfg == ELINK_SWITCH_CFG_10G) {
5740 /* Disable the link interrupt by writing 1 to
5741 * the relevant lane in the status register
5744 ((params->lane_config &
5745 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
5746 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
5747 mask = ((1 << ser_lane) <<
5748 ELINK_NIG_STATUS_XGXS0_LINK_STATUS_SIZE);
5750 mask = ELINK_NIG_STATUS_SERDES0_LINK_STATUS;
5752 PMD_DRV_LOG(DEBUG, sc, "Ack link up interrupt with mask 0x%x",
5755 NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4, mask);
5759 static uint8_t elink_format_ver(uint32_t num, uint8_t * str,
5762 uint8_t *str_ptr = str;
5763 uint32_t mask = 0xf0000000;
5764 uint8_t shift = 8 * 4;
5766 uint8_t remove_leading_zeros = 1;
5768 /* Need more than 10chars for this format */
5771 return ELINK_STATUS_ERROR;
5776 digit = ((num & mask) >> shift);
5777 if (digit == 0 && remove_leading_zeros) {
5780 } else if (digit < 0xa)
5781 *str_ptr = digit + '0';
5783 *str_ptr = digit - 0xa + 'a';
5784 remove_leading_zeros = 0;
5788 if (shift == 4 * 4) {
5792 remove_leading_zeros = 1;
5795 return ELINK_STATUS_OK;
5798 static uint8_t elink_null_format_ver(__rte_unused uint32_t spirom_ver,
5799 uint8_t * str, uint16_t * len)
5803 return ELINK_STATUS_OK;
5806 static void elink_set_xgxs_loopback(struct elink_phy *phy,
5807 struct elink_params *params)
5809 uint8_t port = params->port;
5810 struct bnx2x_softc *sc = params->sc;
5812 if (phy->req_line_speed != ELINK_SPEED_1000) {
5813 uint32_t md_devad = 0;
5815 PMD_DRV_LOG(DEBUG, sc, "XGXS 10G loopback enable");
5817 if (!CHIP_IS_E3(sc)) {
5818 /* Change the uni_phy_addr in the nig */
5819 md_devad = REG_RD(sc, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
5822 REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + port * 0x18,
5826 elink_cl45_write(sc, phy,
5828 (MDIO_REG_BANK_AER_BLOCK +
5829 (MDIO_AER_BLOCK_AER_REG & 0xf)), 0x2800);
5831 elink_cl45_write(sc, phy,
5833 (MDIO_REG_BANK_CL73_IEEEB0 +
5834 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
5837 /* Set aer mmd back */
5838 elink_set_aer_mmd(params, phy);
5840 if (!CHIP_IS_E3(sc)) {
5842 REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + port * 0x18,
5847 PMD_DRV_LOG(DEBUG, sc, "XGXS 1G loopback enable");
5848 elink_cl45_read(sc, phy, 5,
5849 (MDIO_REG_BANK_COMBO_IEEE0 +
5850 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
5852 elink_cl45_write(sc, phy, 5,
5853 (MDIO_REG_BANK_COMBO_IEEE0 +
5854 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
5856 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
5860 elink_status_t elink_set_led(struct elink_params *params,
5861 struct elink_vars *vars, uint8_t mode,
5864 uint8_t port = params->port;
5865 uint16_t hw_led_mode = params->hw_led_mode;
5866 elink_status_t rc = ELINK_STATUS_OK;
5869 uint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
5870 struct bnx2x_softc *sc = params->sc;
5871 PMD_DRV_LOG(DEBUG, sc, "elink_set_led: port %x, mode %d", port, mode);
5872 PMD_DRV_LOG(DEBUG, sc,
5873 "speed 0x%x, hw_led_mode 0x%x", speed, hw_led_mode);
5875 for (phy_idx = ELINK_EXT_PHY1; phy_idx < ELINK_MAX_PHYS; phy_idx++) {
5876 if (params->phy[phy_idx].set_link_led) {
5877 params->phy[phy_idx].set_link_led(¶ms->phy[phy_idx],
5883 case ELINK_LED_MODE_FRONT_PANEL_OFF:
5884 case ELINK_LED_MODE_OFF:
5885 REG_WR(sc, NIG_REG_LED_10G_P0 + port * 4, 0);
5886 REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4,
5887 SHARED_HW_CFG_LED_MAC1);
5889 tmp = elink_cb_reg_read(sc, emac_base + EMAC_REG_EMAC_LED);
5890 if (params->phy[ELINK_EXT_PHY1].type ==
5891 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE)
5892 tmp &= ~(EMAC_LED_1000MB_OVERRIDE |
5893 EMAC_LED_100MB_OVERRIDE |
5894 EMAC_LED_10MB_OVERRIDE);
5896 tmp |= EMAC_LED_OVERRIDE;
5898 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED, tmp);
5901 case ELINK_LED_MODE_OPER:
5902 /* For all other phys, OPER mode is same as ON, so in case
5903 * link is down, do nothing
5908 case ELINK_LED_MODE_ON:
5909 if (((params->phy[ELINK_EXT_PHY1].type ==
5910 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727) ||
5911 (params->phy[ELINK_EXT_PHY1].type ==
5912 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722)) &&
5913 CHIP_IS_E2(sc) && params->num_phys == 2) {
5914 /* This is a work-around for E2+8727 Configurations */
5915 if (mode == ELINK_LED_MODE_ON ||
5916 speed == ELINK_SPEED_10000) {
5917 REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4, 0);
5918 REG_WR(sc, NIG_REG_LED_10G_P0 + port * 4, 1);
5921 elink_cb_reg_read(sc,
5924 elink_cb_reg_write(sc,
5927 (tmp | EMAC_LED_OVERRIDE));
5928 /* Return here without enabling traffic
5929 * LED blink and setting rate in ON mode.
5930 * In oper mode, enabling LED blink
5931 * and setting rate is needed.
5933 if (mode == ELINK_LED_MODE_ON)
5936 } else if (ELINK_SINGLE_MEDIA_DIRECT(params)) {
5937 /* This is a work-around for HW issue found when link
5940 if ((!CHIP_IS_E3(sc)) ||
5941 (CHIP_IS_E3(sc) && mode == ELINK_LED_MODE_ON))
5942 REG_WR(sc, NIG_REG_LED_10G_P0 + port * 4, 1);
5944 if (CHIP_IS_E1x(sc) ||
5945 CHIP_IS_E2(sc) || (mode == ELINK_LED_MODE_ON))
5946 REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4, 0);
5948 REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4,
5950 } else if ((params->phy[ELINK_EXT_PHY1].type ==
5951 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE) &&
5952 (mode == ELINK_LED_MODE_ON)) {
5953 REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4, 0);
5955 elink_cb_reg_read(sc,
5956 emac_base + EMAC_REG_EMAC_LED);
5957 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED,
5958 tmp | EMAC_LED_OVERRIDE |
5959 EMAC_LED_1000MB_OVERRIDE);
5960 /* Break here; otherwise, it'll disable the
5961 * intended override.
5965 uint32_t nig_led_mode = ((params->hw_led_mode <<
5966 SHARED_HW_CFG_LED_MODE_SHIFT)
5968 SHARED_HW_CFG_LED_EXTPHY2)
5969 ? (SHARED_HW_CFG_LED_PHY1 >>
5970 SHARED_HW_CFG_LED_MODE_SHIFT) : hw_led_mode;
5971 REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4,
5975 REG_WR(sc, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port * 4,
5977 /* Set blinking rate to ~15.9Hz */
5979 REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port * 4,
5980 LED_BLINK_RATE_VAL_E3);
5982 REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port * 4,
5983 LED_BLINK_RATE_VAL_E1X_E2);
5984 REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 + port * 4, 1);
5985 tmp = elink_cb_reg_read(sc, emac_base + EMAC_REG_EMAC_LED);
5986 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED,
5987 (tmp & (~EMAC_LED_OVERRIDE)));
5992 rc = ELINK_STATUS_ERROR;
5993 PMD_DRV_LOG(DEBUG, sc,
5994 "elink_set_led: Invalid led mode %d", mode);
6001 static elink_status_t elink_link_initialize(struct elink_params *params,
6002 struct elink_vars *vars)
6004 elink_status_t rc = ELINK_STATUS_OK;
6005 uint8_t phy_index, non_ext_phy;
6006 struct bnx2x_softc *sc = params->sc;
6007 /* In case of external phy existence, the line speed would be the
6008 * line speed linked up by the external phy. In case it is direct
6009 * only, then the line_speed during initialization will be
6010 * equal to the req_line_speed
6012 vars->line_speed = params->phy[ELINK_INT_PHY].req_line_speed;
6014 /* Initialize the internal phy in case this is a direct board
6015 * (no external phys), or this board has external phy which requires
6018 if (!USES_WARPCORE(sc))
6019 elink_prepare_xgxs(¶ms->phy[ELINK_INT_PHY], params, vars);
6020 /* init ext phy and enable link state int */
6021 non_ext_phy = (ELINK_SINGLE_MEDIA_DIRECT(params) ||
6022 (params->loopback_mode == ELINK_LOOPBACK_XGXS));
6025 (params->phy[ELINK_EXT_PHY1].flags & ELINK_FLAGS_INIT_XGXS_FIRST) ||
6026 (params->loopback_mode == ELINK_LOOPBACK_EXT_PHY)) {
6027 struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY];
6028 if (vars->line_speed == ELINK_SPEED_AUTO_NEG &&
6029 (CHIP_IS_E1x(sc) || CHIP_IS_E2(sc)))
6030 elink_set_parallel_detection(phy, params);
6031 if (params->phy[ELINK_INT_PHY].config_init)
6032 params->phy[ELINK_INT_PHY].config_init(phy,
6036 /* Re-read this value in case it was changed inside config_init due to
6037 * limitations of optic module
6039 vars->line_speed = params->phy[ELINK_INT_PHY].req_line_speed;
6041 /* Init external phy */
6043 if (params->phy[ELINK_INT_PHY].supported &
6044 ELINK_SUPPORTED_FIBRE)
6045 vars->link_status |= LINK_STATUS_SERDES_LINK;
6047 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
6049 /* No need to initialize second phy in case of first
6050 * phy only selection. In case of second phy, we do
6051 * need to initialize the first phy, since they are
6054 if (params->phy[phy_index].supported &
6055 ELINK_SUPPORTED_FIBRE)
6056 vars->link_status |= LINK_STATUS_SERDES_LINK;
6058 if (phy_index == ELINK_EXT_PHY2 &&
6059 (elink_phy_selection(params) ==
6060 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
6061 PMD_DRV_LOG(DEBUG, sc,
6062 "Not initializing second phy");
6065 params->phy[phy_index].config_init(¶ms->
6070 /* Reset the interrupt indication after phy was initialized */
6071 elink_bits_dis(sc, NIG_REG_STATUS_INTERRUPT_PORT0 +
6073 (ELINK_NIG_STATUS_XGXS0_LINK10G |
6074 ELINK_NIG_STATUS_XGXS0_LINK_STATUS |
6075 ELINK_NIG_STATUS_SERDES0_LINK_STATUS |
6076 ELINK_NIG_MASK_MI_INT));
6080 static void elink_int_link_reset(__rte_unused struct elink_phy *phy,
6081 struct elink_params *params)
6083 /* Reset the SerDes/XGXS */
6084 REG_WR(params->sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
6085 (0x1ff << (params->port * 16)));
6088 static void elink_common_ext_link_reset(__rte_unused struct elink_phy *phy,
6089 struct elink_params *params)
6091 struct bnx2x_softc *sc = params->sc;
6095 gpio_port = SC_PATH(sc);
6097 gpio_port = params->port;
6098 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
6099 MISC_REGISTERS_GPIO_OUTPUT_LOW, gpio_port);
6100 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
6101 MISC_REGISTERS_GPIO_OUTPUT_LOW, gpio_port);
6102 PMD_DRV_LOG(DEBUG, sc, "reset external PHY");
6105 static elink_status_t elink_update_link_down(struct elink_params *params,
6106 struct elink_vars *vars)
6108 struct bnx2x_softc *sc = params->sc;
6109 uint8_t port = params->port;
6111 PMD_DRV_LOG(DEBUG, sc, "Port %x: Link is down", port);
6112 elink_set_led(params, vars, ELINK_LED_MODE_OFF, 0);
6113 vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;
6114 /* Indicate no mac active */
6115 vars->mac_type = ELINK_MAC_TYPE_NONE;
6117 /* Update shared memory */
6118 vars->link_status &= ~ELINK_LINK_UPDATE_MASK;
6119 vars->line_speed = 0;
6120 elink_update_mng(params, vars->link_status);
6122 /* Activate nig drain */
6123 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + port * 4, 1);
6126 if (!CHIP_IS_E3(sc))
6127 REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port * 4, 0);
6130 /* Reset BigMac/Xmac */
6131 if (CHIP_IS_E1x(sc) || CHIP_IS_E2(sc))
6132 elink_set_bmac_rx(sc, params->port, 0);
6134 if (CHIP_IS_E3(sc)) {
6135 /* Prevent LPI Generation by chip */
6136 REG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2),
6138 REG_WR(sc, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2),
6140 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
6141 SHMEM_EEE_ACTIVE_BIT);
6143 elink_update_mng_eee(params, vars->eee_status);
6144 elink_set_xmac_rxtx(params, 0);
6145 elink_set_umac_rxtx(params, 0);
6148 return ELINK_STATUS_OK;
6151 static elink_status_t elink_update_link_up(struct elink_params *params,
6152 struct elink_vars *vars,
6155 struct bnx2x_softc *sc = params->sc;
6156 uint8_t phy_idx, port = params->port;
6157 elink_status_t rc = ELINK_STATUS_OK;
6159 vars->link_status |= (LINK_STATUS_LINK_UP |
6160 LINK_STATUS_PHYSICAL_LINK_FLAG);
6161 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
6163 if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)
6164 vars->link_status |= LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
6166 if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)
6167 vars->link_status |= LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
6168 if (USES_WARPCORE(sc)) {
6170 if (elink_xmac_enable(params, vars, 0) ==
6171 ELINK_STATUS_NO_LINK) {
6172 PMD_DRV_LOG(DEBUG, sc, "Found errors on XMAC");
6174 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6175 vars->link_status &= ~LINK_STATUS_LINK_UP;
6178 elink_umac_enable(params, vars, 0);
6179 elink_set_led(params, vars,
6180 ELINK_LED_MODE_OPER, vars->line_speed);
6182 if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) &&
6183 (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) {
6184 PMD_DRV_LOG(DEBUG, sc, "Enabling LPI assertion");
6185 REG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 +
6186 (params->port << 2), 1);
6187 REG_WR(sc, MISC_REG_CPMU_LP_DR_ENABLE, 1);
6188 REG_WR(sc, MISC_REG_CPMU_LP_MASK_ENT_P0 +
6189 (params->port << 2), 0xfc20);
6192 if ((CHIP_IS_E1x(sc) || CHIP_IS_E2(sc))) {
6194 if (elink_bmac_enable(params, vars, 0, 1) ==
6195 ELINK_STATUS_NO_LINK) {
6196 PMD_DRV_LOG(DEBUG, sc, "Found errors on BMAC");
6198 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6199 vars->link_status &= ~LINK_STATUS_LINK_UP;
6202 elink_set_led(params, vars,
6203 ELINK_LED_MODE_OPER, ELINK_SPEED_10000);
6205 rc = elink_emac_program(params, vars);
6206 elink_emac_enable(params, vars, 0);
6209 if ((vars->link_status &
6210 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
6211 && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
6212 ELINK_SINGLE_MEDIA_DIRECT(params))
6213 elink_set_gmii_tx_driver(params);
6218 if (CHIP_IS_E1x(sc))
6219 rc |= elink_pbf_update(params, vars->flow_ctrl,
6223 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + port * 4, 0);
6225 /* Update shared memory */
6226 elink_update_mng(params, vars->link_status);
6227 elink_update_mng_eee(params, vars->eee_status);
6228 /* Check remote fault */
6229 for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) {
6230 if (params->phy[phy_idx].flags & ELINK_FLAGS_TX_ERROR_CHECK) {
6231 elink_check_half_open_conn(params, vars, 0);
6239 /* The elink_link_update function should be called upon link
6241 * Link is considered up as follows:
6242 * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
6244 * - SINGLE_MEDIA - The link between the 577xx and the external
6245 * phy (XGXS) need to up as well as the external link of the
6247 * - DUAL_MEDIA - The link between the 577xx and the first
6248 * external phy needs to be up, and at least one of the 2
6249 * external phy link must be up.
6251 elink_status_t elink_link_update(struct elink_params * params,
6252 struct elink_vars * vars)
6254 struct bnx2x_softc *sc = params->sc;
6255 struct elink_vars phy_vars[ELINK_MAX_PHYS];
6256 uint8_t port = params->port;
6257 uint8_t link_10g_plus, phy_index;
6258 uint8_t ext_phy_link_up = 0, cur_link_up;
6259 elink_status_t rc = ELINK_STATUS_OK;
6260 __rte_unused uint8_t is_mi_int = 0;
6261 uint16_t ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
6262 uint8_t active_external_phy = ELINK_INT_PHY;
6263 vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
6264 vars->link_status &= ~ELINK_LINK_UPDATE_MASK;
6265 for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys;
6267 phy_vars[phy_index].flow_ctrl = 0;
6268 phy_vars[phy_index].link_status = ETH_LINK_DOWN;
6269 phy_vars[phy_index].line_speed = 0;
6270 phy_vars[phy_index].duplex = DUPLEX_FULL;
6271 phy_vars[phy_index].phy_link_up = 0;
6272 phy_vars[phy_index].link_up = 0;
6273 phy_vars[phy_index].fault_detected = 0;
6274 /* different consideration, since vars holds inner state */
6275 phy_vars[phy_index].eee_status = vars->eee_status;
6278 if (USES_WARPCORE(sc))
6279 elink_set_aer_mmd(params, ¶ms->phy[ELINK_INT_PHY]);
6281 PMD_DRV_LOG(DEBUG, sc, "port %x, XGXS?%x, int_status 0x%x",
6282 port, (vars->phy_flags & PHY_XGXS_FLAG),
6283 REG_RD(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4));
6285 is_mi_int = (uint8_t) (REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
6287 PMD_DRV_LOG(DEBUG, sc, "int_mask 0x%x MI_INT %x, SERDES_LINK %x",
6288 REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4),
6291 NIG_REG_SERDES0_STATUS_LINK_STATUS + port * 0x3c));
6293 PMD_DRV_LOG(DEBUG, sc, " 10G %x, XGXS_LINK %x",
6294 REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port * 0x68),
6295 REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port * 0x68));
6298 if (!CHIP_IS_E3(sc))
6299 REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port * 4, 0);
6302 * Check external link change only for external phys, and apply
6303 * priority selection between them in case the link on both phys
6304 * is up. Note that instead of the common vars, a temporary
6305 * vars argument is used since each phy may have different link/
6306 * speed/duplex result
6308 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
6310 struct elink_phy *phy = ¶ms->phy[phy_index];
6311 if (!phy->read_status)
6313 /* Read link status and params of this ext phy */
6314 cur_link_up = phy->read_status(phy, params,
6315 &phy_vars[phy_index]);
6317 PMD_DRV_LOG(DEBUG, sc, "phy in index %d link is up",
6320 PMD_DRV_LOG(DEBUG, sc, "phy in index %d link is down",
6325 if (!ext_phy_link_up) {
6326 ext_phy_link_up = 1;
6327 active_external_phy = phy_index;
6329 switch (elink_phy_selection(params)) {
6330 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6331 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6332 /* In this option, the first PHY makes sure to pass the
6333 * traffic through itself only.
6334 * Its not clear how to reset the link on the second phy
6336 active_external_phy = ELINK_EXT_PHY1;
6338 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6339 /* In this option, the first PHY makes sure to pass the
6340 * traffic through the second PHY.
6342 active_external_phy = ELINK_EXT_PHY2;
6345 /* Link indication on both PHYs with the following cases
6347 * - FIRST_PHY means that second phy wasn't initialized,
6348 * hence its link is expected to be down
6349 * - SECOND_PHY means that first phy should not be able
6350 * to link up by itself (using configuration)
6351 * - DEFAULT should be overridden during initialization
6353 PMD_DRV_LOG(DEBUG, sc, "Invalid link indication"
6354 "mpc=0x%x. DISABLING LINK !!!",
6355 params->multi_phy_config);
6356 ext_phy_link_up = 0;
6361 prev_line_speed = vars->line_speed;
6363 * Read the status of the internal phy. In case of
6364 * DIRECT_SINGLE_MEDIA board, this link is the external link,
6365 * otherwise this is the link between the 577xx and the first
6368 if (params->phy[ELINK_INT_PHY].read_status)
6369 params->phy[ELINK_INT_PHY].read_status(¶ms->
6372 /* The INT_PHY flow control reside in the vars. This include the
6373 * case where the speed or flow control are not set to AUTO.
6374 * Otherwise, the active external phy flow control result is set
6375 * to the vars. The ext_phy_line_speed is needed to check if the
6376 * speed is different between the internal phy and external phy.
6377 * This case may be result of intermediate link speed change.
6379 if (active_external_phy > ELINK_INT_PHY) {
6380 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
6381 /* Link speed is taken from the XGXS. AN and FC result from
6384 vars->link_status |= phy_vars[active_external_phy].link_status;
6386 /* if active_external_phy is first PHY and link is up - disable
6387 * disable TX on second external PHY
6389 if (active_external_phy == ELINK_EXT_PHY1) {
6390 if (params->phy[ELINK_EXT_PHY2].phy_specific_func) {
6391 PMD_DRV_LOG(DEBUG, sc, "Disabling TX on EXT_PHY2");
6392 params->phy[ELINK_EXT_PHY2].
6393 phy_specific_func(¶ms->
6394 phy[ELINK_EXT_PHY2],
6395 params, ELINK_DISABLE_TX);
6399 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
6400 vars->duplex = phy_vars[active_external_phy].duplex;
6401 if (params->phy[active_external_phy].supported &
6402 ELINK_SUPPORTED_FIBRE)
6403 vars->link_status |= LINK_STATUS_SERDES_LINK;
6405 vars->link_status &= ~LINK_STATUS_SERDES_LINK;
6407 vars->eee_status = phy_vars[active_external_phy].eee_status;
6409 PMD_DRV_LOG(DEBUG, sc, "Active external phy selected: %x",
6410 active_external_phy);
6413 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
6415 if (params->phy[phy_index].flags &
6416 ELINK_FLAGS_REARM_LATCH_SIGNAL) {
6417 elink_rearm_latch_signal(sc, port,
6419 active_external_phy);
6423 PMD_DRV_LOG(DEBUG, sc, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
6424 " ext_phy_line_speed = %d", vars->flow_ctrl,
6425 vars->link_status, ext_phy_line_speed);
6426 /* Upon link speed change set the NIG into drain mode. Comes to
6427 * deals with possible FIFO glitch due to clk change when speed
6428 * is decreased without link down indicator
6431 if (vars->phy_link_up) {
6432 if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
6433 (ext_phy_line_speed != vars->line_speed)) {
6434 PMD_DRV_LOG(DEBUG, sc, "Internal link speed %d is"
6435 " different than the external"
6436 " link speed %d", vars->line_speed,
6437 ext_phy_line_speed);
6438 vars->phy_link_up = 0;
6439 } else if (prev_line_speed != vars->line_speed) {
6441 NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4,
6447 /* Anything 10 and over uses the bmac */
6448 link_10g_plus = (vars->line_speed >= ELINK_SPEED_10000);
6450 elink_link_int_ack(params, vars, link_10g_plus);
6452 /* In case external phy link is up, and internal link is down
6453 * (not initialized yet probably after link initialization, it
6454 * needs to be initialized.
6455 * Note that after link down-up as result of cable plug, the xgxs
6456 * link would probably become up again without the need
6459 if (!(ELINK_SINGLE_MEDIA_DIRECT(params))) {
6460 PMD_DRV_LOG(DEBUG, sc, "ext_phy_link_up = %d, int_link_up = %d,"
6461 " init_preceding = %d", ext_phy_link_up,
6463 params->phy[ELINK_EXT_PHY1].flags &
6464 ELINK_FLAGS_INIT_XGXS_FIRST);
6465 if (!(params->phy[ELINK_EXT_PHY1].flags &
6466 ELINK_FLAGS_INIT_XGXS_FIRST)
6467 && ext_phy_link_up && !vars->phy_link_up) {
6468 vars->line_speed = ext_phy_line_speed;
6469 if (vars->line_speed < ELINK_SPEED_1000)
6470 vars->phy_flags |= PHY_SGMII_FLAG;
6472 vars->phy_flags &= ~PHY_SGMII_FLAG;
6474 if (params->phy[ELINK_INT_PHY].config_init)
6475 params->phy[ELINK_INT_PHY].config_init(¶ms->
6482 /* Link is up only if both local phy and external phy (in case of
6483 * non-direct board) are up and no fault detected on active PHY.
6485 vars->link_up = (vars->phy_link_up &&
6487 ELINK_SINGLE_MEDIA_DIRECT(params)) &&
6488 (phy_vars[active_external_phy].fault_detected == 0));
6490 /* Update the PFC configuration in case it was changed */
6491 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
6492 vars->link_status |= LINK_STATUS_PFC_ENABLED;
6494 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
6497 rc = elink_update_link_up(params, vars, link_10g_plus);
6499 rc = elink_update_link_down(params, vars);
6501 /* Update MCP link status was changed */
6503 feature_config_flags & ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX)
6504 elink_cb_fw_command(sc, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0);
6509 /*****************************************************************************/
6510 /* External Phy section */
6511 /*****************************************************************************/
6512 static void elink_ext_phy_hw_reset(struct bnx2x_softc *sc, uint8_t port)
6514 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
6515 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
6517 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
6518 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
6521 static void elink_save_spirom_version(struct bnx2x_softc *sc,
6522 __rte_unused uint8_t port,
6523 uint32_t spirom_ver, uint32_t ver_addr)
6525 PMD_DRV_LOG(DEBUG, sc, "FW version 0x%x:0x%x for port %d",
6526 (uint16_t) (spirom_ver >> 16), (uint16_t) spirom_ver, port);
6529 REG_WR(sc, ver_addr, spirom_ver);
6532 static void elink_save_bnx2x_spirom_ver(struct bnx2x_softc *sc,
6533 struct elink_phy *phy, uint8_t port)
6535 uint16_t fw_ver1, fw_ver2;
6537 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
6538 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6539 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
6540 MDIO_PMA_REG_ROM_VER2, &fw_ver2);
6541 elink_save_spirom_version(sc, port,
6542 (uint32_t) (fw_ver1 << 16 | fw_ver2),
6546 static void elink_ext_phy_10G_an_resolve(struct bnx2x_softc *sc,
6547 struct elink_phy *phy,
6548 struct elink_vars *vars)
6551 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_STATUS, &val);
6552 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_STATUS, &val);
6554 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
6555 if ((val & (1 << 0)) == 0)
6556 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
6559 /******************************************************************/
6560 /* common BNX2X8073/BNX2X8727 PHY SECTION */
6561 /******************************************************************/
6562 static void elink_8073_resolve_fc(struct elink_phy *phy,
6563 struct elink_params *params,
6564 struct elink_vars *vars)
6566 struct bnx2x_softc *sc = params->sc;
6567 if (phy->req_line_speed == ELINK_SPEED_10 ||
6568 phy->req_line_speed == ELINK_SPEED_100) {
6569 vars->flow_ctrl = phy->req_flow_ctrl;
6573 if (elink_ext_phy_resolve_fc(phy, params, vars) &&
6574 (vars->flow_ctrl == ELINK_FLOW_CTRL_NONE)) {
6575 uint16_t pause_result;
6576 uint16_t ld_pause; /* local */
6577 uint16_t lp_pause; /* link partner */
6578 elink_cl45_read(sc, phy,
6580 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
6582 elink_cl45_read(sc, phy,
6584 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
6585 pause_result = (ld_pause &
6586 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
6587 pause_result |= (lp_pause &
6588 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
6590 elink_pause_resolve(vars, pause_result);
6591 PMD_DRV_LOG(DEBUG, sc, "Ext PHY CL37 pause result 0x%x",
6596 static elink_status_t elink_8073_8727_external_rom_boot(struct bnx2x_softc *sc,
6597 struct elink_phy *phy,
6601 uint16_t fw_ver1 = 0, fw_msgout;
6602 elink_status_t rc = ELINK_STATUS_OK;
6604 /* Boot port from external ROM */
6606 elink_cl45_write(sc, phy,
6607 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
6609 /* Ucode reboot and rst */
6610 elink_cl45_write(sc, phy,
6611 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x008c);
6613 elink_cl45_write(sc, phy,
6614 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL1, 0x0001);
6616 /* Reset internal microprocessor */
6617 elink_cl45_write(sc, phy,
6619 MDIO_PMA_REG_GEN_CTRL,
6620 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
6622 /* Release srst bit */
6623 elink_cl45_write(sc, phy,
6625 MDIO_PMA_REG_GEN_CTRL,
6626 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
6628 /* Delay 100ms per the PHY specifications */
6631 /* 8073 sometimes taking longer to download */
6635 PMD_DRV_LOG(DEBUG, sc,
6636 "elink_8073_8727_external_rom_boot port %x:"
6637 "Download failed. fw version = 0x%x",
6639 rc = ELINK_STATUS_ERROR;
6643 elink_cl45_read(sc, phy,
6645 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6646 elink_cl45_read(sc, phy,
6648 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
6651 } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
6652 ((fw_msgout & 0xff) != 0x03 && (phy->type ==
6653 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073)));
6655 /* Clear ser_boot_ctl bit */
6656 elink_cl45_write(sc, phy,
6657 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL1, 0x0000);
6658 elink_save_bnx2x_spirom_ver(sc, phy, port);
6660 PMD_DRV_LOG(DEBUG, sc,
6661 "elink_8073_8727_external_rom_boot port %x:"
6662 "Download complete. fw version = 0x%x", port, fw_ver1);
6667 /******************************************************************/
6668 /* BNX2X8073 PHY SECTION */
6669 /******************************************************************/
6670 static elink_status_t elink_8073_is_snr_needed(struct bnx2x_softc *sc,
6671 struct elink_phy *phy)
6673 /* This is only required for 8073A1, version 102 only */
6676 /* Read 8073 HW revision */
6677 elink_cl45_read(sc, phy,
6678 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, &val);
6681 /* No need to workaround in 8073 A1 */
6682 return ELINK_STATUS_OK;
6685 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER2, &val);
6687 /* SNR should be applied only for version 0x102 */
6689 return ELINK_STATUS_OK;
6691 return ELINK_STATUS_ERROR;
6694 static elink_status_t elink_8073_xaui_wa(struct bnx2x_softc *sc,
6695 struct elink_phy *phy)
6697 uint16_t val, cnt, cnt1;
6699 elink_cl45_read(sc, phy,
6700 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, &val);
6703 /* No need to workaround in 8073 A1 */
6704 return ELINK_STATUS_OK;
6706 /* XAUI workaround in 8073 A0: */
6708 /* After loading the boot ROM and restarting Autoneg, poll
6712 for (cnt = 0; cnt < 1000; cnt++) {
6713 elink_cl45_read(sc, phy,
6715 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &val);
6716 /* If bit [14] = 0 or bit [13] = 0, continue on with
6717 * system initialization (XAUI work-around not required, as
6718 * these bits indicate 2.5G or 1G link up).
6720 if (!(val & (1 << 14)) || !(val & (1 << 13))) {
6721 PMD_DRV_LOG(DEBUG, sc, "XAUI work-around not required");
6722 return ELINK_STATUS_OK;
6723 } else if (!(val & (1 << 15))) {
6724 PMD_DRV_LOG(DEBUG, sc, "bit 15 went off");
6725 /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's
6726 * MSB (bit15) goes to 1 (indicating that the XAUI
6727 * workaround has completed), then continue on with
6728 * system initialization.
6730 for (cnt1 = 0; cnt1 < 1000; cnt1++) {
6731 elink_cl45_read(sc, phy,
6733 MDIO_PMA_REG_8073_XAUI_WA,
6735 if (val & (1 << 15)) {
6736 PMD_DRV_LOG(DEBUG, sc,
6737 "XAUI workaround has completed");
6738 return ELINK_STATUS_OK;
6746 PMD_DRV_LOG(DEBUG, sc, "Warning: XAUI work-around timeout !!!");
6747 return ELINK_STATUS_ERROR;
6750 static void elink_807x_force_10G(struct bnx2x_softc *sc, struct elink_phy *phy)
6752 /* Force KR or KX */
6753 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
6754 elink_cl45_write(sc, phy,
6755 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
6756 elink_cl45_write(sc, phy,
6757 MDIO_PMA_DEVAD, MDIO_PMA_REG_BNX2X_CTRL, 0x0000);
6758 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
6761 static void elink_8073_set_pause_cl37(struct elink_params *params,
6762 struct elink_phy *phy,
6763 struct elink_vars *vars)
6766 struct bnx2x_softc *sc = params->sc;
6767 elink_cl45_read(sc, phy,
6768 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
6770 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
6771 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
6772 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
6773 if ((vars->ieee_fc &
6774 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
6775 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
6776 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
6778 if ((vars->ieee_fc &
6779 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
6780 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
6781 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
6783 if ((vars->ieee_fc &
6784 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
6785 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
6786 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
6788 PMD_DRV_LOG(DEBUG, sc, "Ext phy AN advertize cl37 0x%x", cl37_val);
6790 elink_cl45_write(sc, phy,
6791 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
6795 static void elink_8073_specific_func(struct elink_phy *phy,
6796 struct elink_params *params,
6799 struct bnx2x_softc *sc = params->sc;
6801 case ELINK_PHY_INIT:
6803 elink_cl45_write(sc, phy,
6804 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
6806 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
6812 static uint8_t elink_8073_config_init(struct elink_phy *phy,
6813 struct elink_params *params,
6814 struct elink_vars *vars)
6816 struct bnx2x_softc *sc = params->sc;
6817 uint16_t val = 0, tmp1;
6819 PMD_DRV_LOG(DEBUG, sc, "Init 8073");
6822 gpio_port = SC_PATH(sc);
6824 gpio_port = params->port;
6825 /* Restore normal power mode */
6826 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
6827 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
6829 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
6830 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
6832 elink_8073_specific_func(phy, params, ELINK_PHY_INIT);
6833 elink_8073_set_pause_cl37(params, phy, vars);
6835 elink_cl45_read(sc, phy,
6836 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
6838 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
6840 PMD_DRV_LOG(DEBUG, sc, "Before rom RX_ALARM(port1): 0x%x", tmp1);
6842 /* Swap polarity if required - Must be done only in non-1G mode */
6843 if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
6844 /* Configure the 8073 to swap _P and _N of the KR lines */
6845 PMD_DRV_LOG(DEBUG, sc, "Swapping polarity for the 8073");
6846 /* 10G Rx/Tx and 1G Tx signal polarity swap */
6847 elink_cl45_read(sc, phy,
6849 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
6850 elink_cl45_write(sc, phy,
6852 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
6856 /* Enable CL37 BAM */
6857 if (REG_RD(sc, params->shmem_base +
6858 offsetof(struct shmem_region,
6859 dev_info.port_hw_config[params->port].
6861 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
6863 elink_cl45_read(sc, phy,
6864 MDIO_AN_DEVAD, MDIO_AN_REG_8073_BAM, &val);
6865 elink_cl45_write(sc, phy,
6866 MDIO_AN_DEVAD, MDIO_AN_REG_8073_BAM, val | 1);
6867 PMD_DRV_LOG(DEBUG, sc, "Enable CL37 BAM on KR");
6869 if (params->loopback_mode == ELINK_LOOPBACK_EXT) {
6870 elink_807x_force_10G(sc, phy);
6871 PMD_DRV_LOG(DEBUG, sc, "Forced speed 10G on 807X");
6872 return ELINK_STATUS_OK;
6874 elink_cl45_write(sc, phy,
6875 MDIO_PMA_DEVAD, MDIO_PMA_REG_BNX2X_CTRL, 0x0002);
6877 if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG) {
6878 if (phy->req_line_speed == ELINK_SPEED_10000) {
6880 } else if (phy->req_line_speed == ELINK_SPEED_2500) {
6882 /* Note that 2.5G works only when used with 1G
6889 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
6892 /* Note that 2.5G works only when used with 1G advertisement */
6893 if (phy->speed_cap_mask &
6894 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
6895 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
6897 PMD_DRV_LOG(DEBUG, sc, "807x autoneg val = 0x%x", val);
6900 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
6901 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
6903 if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
6904 (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)) ||
6905 (phy->req_line_speed == ELINK_SPEED_2500)) {
6907 /* Allow 2.5G for A1 and above */
6908 elink_cl45_read(sc, phy,
6909 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
6911 PMD_DRV_LOG(DEBUG, sc, "Add 2.5G");
6917 PMD_DRV_LOG(DEBUG, sc, "Disable 2.5G");
6921 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
6922 /* Add support for CL37 (passive mode) II */
6924 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
6925 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
6926 (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
6929 /* Add support for CL37 (passive mode) III */
6930 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
6932 /* The SNR will improve about 2db by changing BW and FEE main
6933 * tap. Rest commands are executed after link is up
6934 * Change FFE main cursor to 5 in EDC register
6936 if (elink_8073_is_snr_needed(sc, phy))
6937 elink_cl45_write(sc, phy,
6938 MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
6941 /* Enable FEC (Forware Error Correction) Request in the AN */
6942 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
6944 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
6946 elink_ext_phy_set_pause(params, phy, vars);
6948 /* Restart autoneg */
6950 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
6951 PMD_DRV_LOG(DEBUG, sc, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x",
6952 ((val & (1 << 5)) > 0), ((val & (1 << 7)) > 0));
6953 return ELINK_STATUS_OK;
6956 static uint8_t elink_8073_read_status(struct elink_phy *phy,
6957 struct elink_params *params,
6958 struct elink_vars *vars)
6960 struct bnx2x_softc *sc = params->sc;
6961 uint8_t link_up = 0;
6962 uint16_t val1, val2;
6963 uint16_t link_status = 0;
6964 uint16_t an1000_status = 0;
6966 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
6968 PMD_DRV_LOG(DEBUG, sc, "8703 LASI status 0x%x", val1);
6970 /* Clear the interrupt LASI status register */
6971 elink_cl45_read(sc, phy, MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
6972 elink_cl45_read(sc, phy, MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
6973 PMD_DRV_LOG(DEBUG, sc, "807x PCS status 0x%x->0x%x", val2, val1);
6975 elink_cl45_read(sc, phy,
6976 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
6978 /* Check the LASI */
6979 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
6981 PMD_DRV_LOG(DEBUG, sc, "KR 0x9003 0x%x", val2);
6983 /* Check the link status */
6984 elink_cl45_read(sc, phy, MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
6985 PMD_DRV_LOG(DEBUG, sc, "KR PCS status 0x%x", val2);
6987 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
6988 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
6989 link_up = ((val1 & 4) == 4);
6990 PMD_DRV_LOG(DEBUG, sc, "PMA_REG_STATUS=0x%x", val1);
6992 if (link_up && ((phy->req_line_speed != ELINK_SPEED_10000))) {
6993 if (elink_8073_xaui_wa(sc, phy) != 0)
6996 elink_cl45_read(sc, phy,
6997 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
6998 elink_cl45_read(sc, phy,
6999 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7001 /* Check the link status on 1.1.2 */
7002 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7003 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7004 PMD_DRV_LOG(DEBUG, sc, "KR PMA status 0x%x->0x%x,"
7005 "an_link_status=0x%x", val2, val1, an1000_status);
7007 link_up = (((val1 & 4) == 4) || (an1000_status & (1 << 1)));
7008 if (link_up && elink_8073_is_snr_needed(sc, phy)) {
7009 /* The SNR will improve about 2dbby changing the BW and FEE main
7010 * tap. The 1st write to change FFE main tap is set before
7011 * restart AN. Change PLL Bandwidth in EDC register
7013 elink_cl45_write(sc, phy,
7014 MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
7017 /* Change CDR Bandwidth in EDC register */
7018 elink_cl45_write(sc, phy,
7019 MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
7022 elink_cl45_read(sc, phy,
7023 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7026 /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
7027 if ((link_status & (1 << 2)) && (!(link_status & (1 << 15)))) {
7029 vars->line_speed = ELINK_SPEED_10000;
7030 PMD_DRV_LOG(DEBUG, sc, "port %x: External link up in 10G",
7032 } else if ((link_status & (1 << 1)) && (!(link_status & (1 << 14)))) {
7034 vars->line_speed = ELINK_SPEED_2500;
7035 PMD_DRV_LOG(DEBUG, sc, "port %x: External link up in 2.5G",
7037 } else if ((link_status & (1 << 0)) && (!(link_status & (1 << 13)))) {
7039 vars->line_speed = ELINK_SPEED_1000;
7040 PMD_DRV_LOG(DEBUG, sc, "port %x: External link up in 1G",
7044 PMD_DRV_LOG(DEBUG, sc, "port %x: External link is down",
7049 /* Swap polarity if required */
7050 if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7051 /* Configure the 8073 to swap P and N of the KR lines */
7052 elink_cl45_read(sc, phy,
7054 MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
7055 /* Set bit 3 to invert Rx in 1G mode and clear this bit
7056 * when it`s in 10G mode.
7058 if (vars->line_speed == ELINK_SPEED_1000) {
7059 PMD_DRV_LOG(DEBUG, sc, "Swapping 1G polarity for"
7065 elink_cl45_write(sc, phy,
7067 MDIO_XS_REG_8073_RX_CTRL_PCIE, val1);
7069 elink_ext_phy_10G_an_resolve(sc, phy, vars);
7070 elink_8073_resolve_fc(phy, params, vars);
7071 vars->duplex = DUPLEX_FULL;
7074 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
7075 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
7076 MDIO_AN_REG_LP_AUTO_NEG2, &val1);
7078 if (val1 & (1 << 5))
7079 vars->link_status |=
7080 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
7081 if (val1 & (1 << 7))
7082 vars->link_status |=
7083 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
7089 static void elink_8073_link_reset(__rte_unused struct elink_phy *phy,
7090 struct elink_params *params)
7092 struct bnx2x_softc *sc = params->sc;
7095 gpio_port = SC_PATH(sc);
7097 gpio_port = params->port;
7098 PMD_DRV_LOG(DEBUG, sc, "Setting 8073 port %d into low power mode",
7100 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
7101 MISC_REGISTERS_GPIO_OUTPUT_LOW, gpio_port);
7104 /******************************************************************/
7105 /* BNX2X8705 PHY SECTION */
7106 /******************************************************************/
7107 static uint8_t elink_8705_config_init(struct elink_phy *phy,
7108 struct elink_params *params,
7109 __rte_unused struct elink_vars
7112 struct bnx2x_softc *sc = params->sc;
7113 PMD_DRV_LOG(DEBUG, sc, "init 8705");
7114 /* Restore normal power mode */
7115 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
7116 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
7118 elink_ext_phy_hw_reset(sc, params->port);
7119 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
7120 elink_wait_reset_complete(sc, phy, params);
7122 elink_cl45_write(sc, phy,
7123 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
7124 elink_cl45_write(sc, phy,
7125 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
7126 elink_cl45_write(sc, phy,
7127 MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
7128 elink_cl45_write(sc, phy, MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
7129 /* BNX2X8705 doesn't have microcode, hence the 0 */
7130 elink_save_spirom_version(sc, params->port, params->shmem_base, 0);
7131 return ELINK_STATUS_OK;
7134 static uint8_t elink_8705_read_status(struct elink_phy *phy,
7135 struct elink_params *params,
7136 struct elink_vars *vars)
7138 uint8_t link_up = 0;
7139 uint16_t val1, rx_sd;
7140 struct bnx2x_softc *sc = params->sc;
7141 PMD_DRV_LOG(DEBUG, sc, "read status 8705");
7142 elink_cl45_read(sc, phy,
7143 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7144 PMD_DRV_LOG(DEBUG, sc, "8705 LASI status 0x%x", val1);
7146 elink_cl45_read(sc, phy,
7147 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7148 PMD_DRV_LOG(DEBUG, sc, "8705 LASI status 0x%x", val1);
7150 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
7152 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xc809, &val1);
7153 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xc809, &val1);
7155 PMD_DRV_LOG(DEBUG, sc, "8705 1.c809 val=0x%x", val1);
7156 link_up = ((rx_sd & 0x1) && (val1 & (1 << 9))
7157 && ((val1 & (1 << 8)) == 0));
7159 vars->line_speed = ELINK_SPEED_10000;
7160 elink_ext_phy_resolve_fc(phy, params, vars);
7165 /******************************************************************/
7166 /* SFP+ module Section */
7167 /******************************************************************/
7168 static void elink_set_disable_pmd_transmit(struct elink_params *params,
7169 struct elink_phy *phy,
7172 struct bnx2x_softc *sc = params->sc;
7173 /* Disable transmitter only for bootcodes which can enable it afterwards
7177 if (params->feature_config_flags &
7178 ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED) {
7179 PMD_DRV_LOG(DEBUG, sc, "Disabling PMD transmitter");
7181 PMD_DRV_LOG(DEBUG, sc, "NOT disabling PMD transmitter");
7185 PMD_DRV_LOG(DEBUG, sc, "Enabling PMD transmitter");
7187 elink_cl45_write(sc, phy,
7188 MDIO_PMA_DEVAD, MDIO_PMA_REG_TX_DISABLE, pmd_dis);
7191 static uint8_t elink_get_gpio_port(struct elink_params *params)
7194 uint32_t swap_val, swap_override;
7195 struct bnx2x_softc *sc = params->sc;
7196 if (CHIP_IS_E2(sc)) {
7197 gpio_port = SC_PATH(sc);
7199 gpio_port = params->port;
7201 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
7202 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
7203 return gpio_port ^ (swap_val && swap_override);
7206 static void elink_sfp_e1e2_set_transmitter(struct elink_params *params,
7207 struct elink_phy *phy, uint8_t tx_en)
7210 uint8_t port = params->port;
7211 struct bnx2x_softc *sc = params->sc;
7212 uint32_t tx_en_mode;
7214 /* Disable/Enable transmitter ( TX laser of the SFP+ module.) */
7215 tx_en_mode = REG_RD(sc, params->shmem_base +
7216 offsetof(struct shmem_region,
7217 dev_info.port_hw_config[port].sfp_ctrl)) &
7218 PORT_HW_CFG_TX_LASER_MASK;
7219 PMD_DRV_LOG(DEBUG, sc, "Setting transmitter tx_en=%x for port %x "
7220 "mode = %x", tx_en, port, tx_en_mode);
7221 switch (tx_en_mode) {
7222 case PORT_HW_CFG_TX_LASER_MDIO:
7224 elink_cl45_read(sc, phy,
7226 MDIO_PMA_REG_PHY_IDENTIFIER, &val);
7233 elink_cl45_write(sc, phy,
7235 MDIO_PMA_REG_PHY_IDENTIFIER, val);
7237 case PORT_HW_CFG_TX_LASER_GPIO0:
7238 case PORT_HW_CFG_TX_LASER_GPIO1:
7239 case PORT_HW_CFG_TX_LASER_GPIO2:
7240 case PORT_HW_CFG_TX_LASER_GPIO3:
7243 uint8_t gpio_port, gpio_mode;
7245 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
7247 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
7249 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
7250 gpio_port = elink_get_gpio_port(params);
7251 elink_cb_gpio_write(sc, gpio_pin, gpio_mode, gpio_port);
7255 PMD_DRV_LOG(DEBUG, sc,
7256 "Invalid TX_LASER_MDIO 0x%x", tx_en_mode);
7261 static void elink_sfp_set_transmitter(struct elink_params *params,
7262 struct elink_phy *phy, uint8_t tx_en)
7264 struct bnx2x_softc *sc = params->sc;
7265 PMD_DRV_LOG(DEBUG, sc, "Setting SFP+ transmitter to %d", tx_en);
7267 elink_sfp_e3_set_transmitter(params, phy, tx_en);
7269 elink_sfp_e1e2_set_transmitter(params, phy, tx_en);
7272 static elink_status_t elink_8726_read_sfp_module_eeprom(struct elink_phy *phy,
7279 __rte_unused uint8_t
7282 struct bnx2x_softc *sc = params->sc;
7285 if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) {
7286 PMD_DRV_LOG(DEBUG, sc, "Reading from eeprom is limited to 0xf");
7287 return ELINK_STATUS_ERROR;
7289 /* Set the read command byte count */
7290 elink_cl45_write(sc, phy,
7291 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7292 (byte_cnt | (dev_addr << 8)));
7294 /* Set the read command address */
7295 elink_cl45_write(sc, phy,
7296 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7299 /* Activate read command */
7300 elink_cl45_write(sc, phy,
7301 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7304 /* Wait up to 500us for command complete status */
7305 for (i = 0; i < 100; i++) {
7306 elink_cl45_read(sc, phy,
7308 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7309 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7310 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7315 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7316 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7317 PMD_DRV_LOG(DEBUG, sc,
7318 "Got bad status 0x%x when reading from SFP+ EEPROM",
7319 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7320 return ELINK_STATUS_ERROR;
7323 /* Read the buffer */
7324 for (i = 0; i < byte_cnt; i++) {
7325 elink_cl45_read(sc, phy,
7327 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
7329 (uint8_t) (val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
7332 for (i = 0; i < 100; i++) {
7333 elink_cl45_read(sc, phy,
7335 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7336 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7337 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7338 return ELINK_STATUS_OK;
7341 return ELINK_STATUS_ERROR;
7344 static void elink_warpcore_power_module(struct elink_params *params,
7348 struct bnx2x_softc *sc = params->sc;
7350 pin_cfg = (REG_RD(sc, params->shmem_base +
7351 offsetof(struct shmem_region,
7352 dev_info.port_hw_config[params->port].
7353 e3_sfp_ctrl)) & PORT_HW_CFG_E3_PWR_DIS_MASK)
7354 >> PORT_HW_CFG_E3_PWR_DIS_SHIFT;
7356 if (pin_cfg == PIN_CFG_NA)
7358 PMD_DRV_LOG(DEBUG, sc, "Setting SFP+ module power to %d using pin cfg %d",
7360 /* Low ==> corresponding SFP+ module is powered
7361 * high ==> the SFP+ module is powered down
7363 elink_set_cfg_pin(sc, pin_cfg, power ^ 1);
7366 static elink_status_t elink_warpcore_read_sfp_module_eeprom(__rte_unused struct
7376 elink_status_t rc = ELINK_STATUS_OK;
7377 uint8_t i, j = 0, cnt = 0;
7378 uint32_t data_array[4];
7380 struct bnx2x_softc *sc = params->sc;
7382 if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) {
7383 PMD_DRV_LOG(DEBUG, sc,
7384 "Reading from eeprom is limited to 16 bytes");
7385 return ELINK_STATUS_ERROR;
7388 /* 4 byte aligned address */
7389 addr32 = addr & (~0x3);
7391 if ((!is_init) && (cnt == I2C_WA_PWR_ITER)) {
7392 elink_warpcore_power_module(params, 0);
7393 /* Note that 100us are not enough here */
7395 elink_warpcore_power_module(params, 1);
7397 rc = elink_bsc_read(params, sc, dev_addr, addr32, 0, byte_cnt,
7399 } while ((rc != ELINK_STATUS_OK) && (++cnt < I2C_WA_RETRY_CNT));
7401 if (rc == ELINK_STATUS_OK) {
7402 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) {
7403 o_buf[j] = *((uint8_t *) data_array + i);
7411 static elink_status_t elink_8727_read_sfp_module_eeprom(struct elink_phy *phy,
7418 __rte_unused uint8_t
7421 struct bnx2x_softc *sc = params->sc;
7424 if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) {
7425 PMD_DRV_LOG(DEBUG, sc, "Reading from eeprom is limited to 0xf");
7426 return ELINK_STATUS_ERROR;
7429 /* Set 2-wire transfer rate of SFP+ module EEPROM
7430 * to 100Khz since some DACs(direct attached cables) do
7431 * not work at 400Khz.
7433 elink_cl45_write(sc, phy,
7435 MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
7436 ((dev_addr << 8) | 1));
7438 /* Need to read from 1.8000 to clear it */
7439 elink_cl45_read(sc, phy,
7440 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7442 /* Set the read command byte count */
7443 elink_cl45_write(sc, phy,
7445 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7446 ((byte_cnt < 2) ? 2 : byte_cnt));
7448 /* Set the read command address */
7449 elink_cl45_write(sc, phy,
7451 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, addr);
7452 /* Set the destination address */
7453 elink_cl45_write(sc, phy,
7455 0x8004, MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
7457 /* Activate read command */
7458 elink_cl45_write(sc, phy,
7460 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, 0x8002);
7461 /* Wait appropriate time for two-wire command to finish before
7462 * polling the status register
7466 /* Wait up to 500us for command complete status */
7467 for (i = 0; i < 100; i++) {
7468 elink_cl45_read(sc, phy,
7470 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7471 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7472 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7477 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7478 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7479 PMD_DRV_LOG(DEBUG, sc,
7480 "Got bad status 0x%x when reading from SFP+ EEPROM",
7481 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7482 return ELINK_STATUS_TIMEOUT;
7485 /* Read the buffer */
7486 for (i = 0; i < byte_cnt; i++) {
7487 elink_cl45_read(sc, phy,
7489 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
7491 (uint8_t) (val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
7494 for (i = 0; i < 100; i++) {
7495 elink_cl45_read(sc, phy,
7497 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7498 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7499 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7500 return ELINK_STATUS_OK;
7504 return ELINK_STATUS_ERROR;
7507 static elink_status_t elink_read_sfp_module_eeprom(struct elink_phy *phy,
7508 struct elink_params *params,
7514 elink_status_t rc = ELINK_STATUS_OK;
7516 uint8_t *user_data = o_buf;
7517 read_sfp_module_eeprom_func_p read_func;
7519 if ((dev_addr != 0xa0) && (dev_addr != 0xa2)) {
7520 PMD_DRV_LOG(DEBUG, params->sc,
7521 "invalid dev_addr 0x%x", dev_addr);
7522 return ELINK_STATUS_ERROR;
7525 switch (phy->type) {
7526 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726:
7527 read_func = elink_8726_read_sfp_module_eeprom;
7529 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727:
7530 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722:
7531 read_func = elink_8727_read_sfp_module_eeprom;
7533 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
7534 read_func = elink_warpcore_read_sfp_module_eeprom;
7537 return ELINK_OP_NOT_SUPPORTED;
7540 while (!rc && (byte_cnt > 0)) {
7541 xfer_size = (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) ?
7542 ELINK_SFP_EEPROM_PAGE_SIZE : byte_cnt;
7543 rc = read_func(phy, params, dev_addr, addr, xfer_size,
7545 byte_cnt -= xfer_size;
7546 user_data += xfer_size;
7552 static elink_status_t elink_get_edc_mode(struct elink_phy *phy,
7553 struct elink_params *params,
7554 uint16_t * edc_mode)
7556 struct bnx2x_softc *sc = params->sc;
7557 uint32_t sync_offset = 0, phy_idx, media_types;
7558 uint8_t gport, val[2], check_limiting_mode = 0;
7559 *edc_mode = ELINK_EDC_MODE_LIMITING;
7560 phy->media_type = ELINK_ETH_PHY_UNSPECIFIED;
7561 /* First check for copper cable */
7562 if (elink_read_sfp_module_eeprom(phy,
7564 ELINK_I2C_DEV_ADDR_A0,
7565 ELINK_SFP_EEPROM_CON_TYPE_ADDR,
7566 2, (uint8_t *) val) != 0) {
7567 PMD_DRV_LOG(DEBUG, sc, "Failed to read from SFP+ module EEPROM");
7568 return ELINK_STATUS_ERROR;
7572 case ELINK_SFP_EEPROM_CON_TYPE_VAL_COPPER:
7574 uint8_t copper_module_type;
7575 phy->media_type = ELINK_ETH_PHY_DA_TWINAX;
7576 /* Check if its active cable (includes SFP+ module)
7579 if (elink_read_sfp_module_eeprom(phy,
7581 ELINK_I2C_DEV_ADDR_A0,
7582 ELINK_SFP_EEPROM_FC_TX_TECH_ADDR,
7584 &copper_module_type) !=
7586 PMD_DRV_LOG(DEBUG, sc,
7587 "Failed to read copper-cable-type"
7588 " from SFP+ EEPROM");
7589 return ELINK_STATUS_ERROR;
7592 if (copper_module_type &
7593 ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
7594 PMD_DRV_LOG(DEBUG, sc,
7595 "Active Copper cable detected");
7597 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
7598 *edc_mode = ELINK_EDC_MODE_ACTIVE_DAC;
7600 check_limiting_mode = 1;
7601 } else if (copper_module_type &
7602 ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE)
7604 PMD_DRV_LOG(DEBUG, sc,
7605 "Passive Copper cable detected");
7606 *edc_mode = ELINK_EDC_MODE_PASSIVE_DAC;
7608 PMD_DRV_LOG(DEBUG, sc,
7609 "Unknown copper-cable-type 0x%x !!!",
7610 copper_module_type);
7611 return ELINK_STATUS_ERROR;
7615 case ELINK_SFP_EEPROM_CON_TYPE_VAL_LC:
7616 case ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45:
7617 check_limiting_mode = 1;
7618 if ((val[1] & (ELINK_SFP_EEPROM_COMP_CODE_SR_MASK |
7619 ELINK_SFP_EEPROM_COMP_CODE_LR_MASK |
7620 ELINK_SFP_EEPROM_COMP_CODE_LRM_MASK)) == 0) {
7621 PMD_DRV_LOG(DEBUG, sc, "1G SFP module detected");
7622 gport = params->port;
7623 phy->media_type = ELINK_ETH_PHY_SFP_1G_FIBER;
7624 if (phy->req_line_speed != ELINK_SPEED_1000) {
7625 phy->req_line_speed = ELINK_SPEED_1000;
7626 if (!CHIP_IS_E1x(sc)) {
7627 gport = SC_PATH(sc) +
7628 (params->port << 1);
7630 elink_cb_event_log(sc, ELINK_LOG_ID_NON_10G_MODULE, gport); //"Warning: Link speed was forced to 1000Mbps."
7631 // " Current SFP module in port %d is not"
7632 // " compliant with 10G Ethernet",
7636 int idx, cfg_idx = 0;
7637 PMD_DRV_LOG(DEBUG, sc, "10G Optic module detected");
7638 for (idx = ELINK_INT_PHY; idx < ELINK_MAX_PHYS; idx++) {
7639 if (params->phy[idx].type == phy->type) {
7640 cfg_idx = ELINK_LINK_CONFIG_IDX(idx);
7644 phy->media_type = ELINK_ETH_PHY_SFPP_10G_FIBER;
7645 phy->req_line_speed = params->req_line_speed[cfg_idx];
7649 PMD_DRV_LOG(DEBUG, sc, "Unable to determine module type 0x%x !!!",
7651 return ELINK_STATUS_ERROR;
7653 sync_offset = params->shmem_base +
7654 offsetof(struct shmem_region,
7655 dev_info.port_hw_config[params->port].media_type);
7656 media_types = REG_RD(sc, sync_offset);
7657 /* Update media type for non-PMF sync */
7658 for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) {
7659 if (&(params->phy[phy_idx]) == phy) {
7660 media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
7661 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
7665 media_type & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
7666 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
7670 REG_WR(sc, sync_offset, media_types);
7671 if (check_limiting_mode) {
7672 uint8_t options[ELINK_SFP_EEPROM_OPTIONS_SIZE];
7673 if (elink_read_sfp_module_eeprom(phy,
7675 ELINK_I2C_DEV_ADDR_A0,
7676 ELINK_SFP_EEPROM_OPTIONS_ADDR,
7677 ELINK_SFP_EEPROM_OPTIONS_SIZE,
7679 PMD_DRV_LOG(DEBUG, sc,
7680 "Failed to read Option field from module EEPROM");
7681 return ELINK_STATUS_ERROR;
7683 if ((options[0] & ELINK_SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
7684 *edc_mode = ELINK_EDC_MODE_LINEAR;
7686 *edc_mode = ELINK_EDC_MODE_LIMITING;
7688 PMD_DRV_LOG(DEBUG, sc, "EDC mode is set to 0x%x", *edc_mode);
7689 return ELINK_STATUS_OK;
7692 /* This function read the relevant field from the module (SFP+), and verify it
7693 * is compliant with this board
7695 static elink_status_t elink_verify_sfp_module(struct elink_phy *phy,
7696 struct elink_params *params)
7698 struct bnx2x_softc *sc = params->sc;
7700 uint32_t fw_resp, fw_cmd_param;
7701 char vendor_name[ELINK_SFP_EEPROM_VENDOR_NAME_SIZE + 1];
7702 char vendor_pn[ELINK_SFP_EEPROM_PART_NO_SIZE + 1];
7703 phy->flags &= ~ELINK_FLAGS_SFP_NOT_APPROVED;
7704 val = REG_RD(sc, params->shmem_base +
7705 offsetof(struct shmem_region,
7706 dev_info.port_feature_config[params->port].
7708 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
7709 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
7710 PMD_DRV_LOG(DEBUG, sc, "NOT enforcing module verification");
7711 return ELINK_STATUS_OK;
7714 if (params->feature_config_flags &
7715 ELINK_FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
7716 /* Use specific phy request */
7717 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
7718 } else if (params->feature_config_flags &
7719 ELINK_FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
7720 /* Use first phy request only in case of non-dual media */
7721 if (ELINK_DUAL_MEDIA(params)) {
7722 PMD_DRV_LOG(DEBUG, sc,
7723 "FW does not support OPT MDL verification");
7724 return ELINK_STATUS_ERROR;
7726 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
7728 /* No support in OPT MDL detection */
7729 PMD_DRV_LOG(DEBUG, sc, "FW does not support OPT MDL verification");
7730 return ELINK_STATUS_ERROR;
7733 fw_cmd_param = ELINK_FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
7734 fw_resp = elink_cb_fw_command(sc, cmd, fw_cmd_param);
7735 if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
7736 PMD_DRV_LOG(DEBUG, sc, "Approved module");
7737 return ELINK_STATUS_OK;
7740 /* Format the warning message */
7741 if (elink_read_sfp_module_eeprom(phy,
7743 ELINK_I2C_DEV_ADDR_A0,
7744 ELINK_SFP_EEPROM_VENDOR_NAME_ADDR,
7745 ELINK_SFP_EEPROM_VENDOR_NAME_SIZE,
7746 (uint8_t *) vendor_name))
7747 vendor_name[0] = '\0';
7749 vendor_name[ELINK_SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
7750 if (elink_read_sfp_module_eeprom(phy,
7752 ELINK_I2C_DEV_ADDR_A0,
7753 ELINK_SFP_EEPROM_PART_NO_ADDR,
7754 ELINK_SFP_EEPROM_PART_NO_SIZE,
7755 (uint8_t *) vendor_pn))
7756 vendor_pn[0] = '\0';
7758 vendor_pn[ELINK_SFP_EEPROM_PART_NO_SIZE] = '\0';
7760 elink_cb_event_log(sc, ELINK_LOG_ID_UNQUAL_IO_MODULE, params->port, vendor_name, vendor_pn); // "Warning: Unqualified SFP+ module detected,"
7761 // " Port %d from %s part number %s",
7763 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
7764 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG)
7765 phy->flags |= ELINK_FLAGS_SFP_NOT_APPROVED;
7766 return ELINK_STATUS_ERROR;
7769 static elink_status_t elink_wait_for_sfp_module_initialized(struct elink_phy
7777 /* Initialization time after hot-plug may take up to 300ms for
7778 * some phys type ( e.g. JDSU )
7781 for (timeout = 0; timeout < 60; timeout++) {
7782 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
7783 rc = elink_warpcore_read_sfp_module_eeprom(phy, params,
7784 ELINK_I2C_DEV_ADDR_A0,
7788 rc = elink_read_sfp_module_eeprom(phy, params,
7789 ELINK_I2C_DEV_ADDR_A0,
7792 PMD_DRV_LOG(DEBUG, params->sc,
7793 "SFP+ module initialization took %d ms",
7795 return ELINK_STATUS_OK;
7799 rc = elink_read_sfp_module_eeprom(phy, params, ELINK_I2C_DEV_ADDR_A0,
7804 static void elink_8727_power_module(struct bnx2x_softc *sc,
7805 struct elink_phy *phy, uint8_t is_power_up)
7807 /* Make sure GPIOs are not using for LED mode */
7809 /* In the GPIO register, bit 4 is use to determine if the GPIOs are
7810 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
7812 * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
7813 * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1
7814 * where the 1st bit is the over-current(only input), and 2nd bit is
7815 * for power( only output )
7817 * In case of NOC feature is disabled and power is up, set GPIO control
7818 * as input to enable listening of over-current indication
7820 if (phy->flags & ELINK_FLAGS_NOC)
7825 /* Set GPIO control to OUTPUT, and set the power bit
7826 * to according to the is_power_up
7830 elink_cl45_write(sc, phy,
7831 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, val);
7834 static elink_status_t elink_8726_set_limiting_mode(struct bnx2x_softc *sc,
7835 struct elink_phy *phy,
7838 uint16_t cur_limiting_mode;
7840 elink_cl45_read(sc, phy,
7842 MDIO_PMA_REG_ROM_VER2, &cur_limiting_mode);
7843 PMD_DRV_LOG(DEBUG, sc,
7844 "Current Limiting mode is 0x%x", cur_limiting_mode);
7846 if (edc_mode == ELINK_EDC_MODE_LIMITING) {
7847 PMD_DRV_LOG(DEBUG, sc, "Setting LIMITING MODE");
7848 elink_cl45_write(sc, phy,
7850 MDIO_PMA_REG_ROM_VER2,
7851 ELINK_EDC_MODE_LIMITING);
7852 } else { /* LRM mode ( default ) */
7854 PMD_DRV_LOG(DEBUG, sc, "Setting LRM MODE");
7856 /* Changing to LRM mode takes quite few seconds. So do it only
7857 * if current mode is limiting (default is LRM)
7859 if (cur_limiting_mode != ELINK_EDC_MODE_LIMITING)
7860 return ELINK_STATUS_OK;
7862 elink_cl45_write(sc, phy,
7863 MDIO_PMA_DEVAD, MDIO_PMA_REG_LRM_MODE, 0);
7864 elink_cl45_write(sc, phy,
7865 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER2, 0x128);
7866 elink_cl45_write(sc, phy,
7868 MDIO_PMA_REG_MISC_CTRL0, 0x4008);
7869 elink_cl45_write(sc, phy,
7870 MDIO_PMA_DEVAD, MDIO_PMA_REG_LRM_MODE, 0xaaaa);
7872 return ELINK_STATUS_OK;
7875 static elink_status_t elink_8727_set_limiting_mode(struct bnx2x_softc *sc,
7876 struct elink_phy *phy,
7879 uint16_t phy_identifier;
7880 uint16_t rom_ver2_val;
7881 elink_cl45_read(sc, phy,
7883 MDIO_PMA_REG_PHY_IDENTIFIER, &phy_identifier);
7885 elink_cl45_write(sc, phy,
7887 MDIO_PMA_REG_PHY_IDENTIFIER,
7888 (phy_identifier & ~(1 << 9)));
7890 elink_cl45_read(sc, phy,
7891 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER2, &rom_ver2_val);
7892 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
7893 elink_cl45_write(sc, phy,
7895 MDIO_PMA_REG_ROM_VER2,
7896 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
7898 elink_cl45_write(sc, phy,
7900 MDIO_PMA_REG_PHY_IDENTIFIER,
7901 (phy_identifier | (1 << 9)));
7903 return ELINK_STATUS_OK;
7906 static void elink_8727_specific_func(struct elink_phy *phy,
7907 struct elink_params *params,
7910 struct bnx2x_softc *sc = params->sc;
7913 case ELINK_DISABLE_TX:
7914 elink_sfp_set_transmitter(params, phy, 0);
7916 case ELINK_ENABLE_TX:
7917 if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED))
7918 elink_sfp_set_transmitter(params, phy, 1);
7920 case ELINK_PHY_INIT:
7921 elink_cl45_write(sc, phy,
7922 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
7923 (1 << 2) | (1 << 5));
7924 elink_cl45_write(sc, phy,
7925 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, 0);
7926 elink_cl45_write(sc, phy,
7927 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0006);
7928 /* Make MOD_ABS give interrupt on change */
7929 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
7930 MDIO_PMA_REG_8727_PCS_OPT_CTRL, &val);
7932 if (phy->flags & ELINK_FLAGS_NOC)
7934 /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
7935 * status which reflect SFP+ module over-current
7937 if (!(phy->flags & ELINK_FLAGS_NOC))
7938 val &= 0xff8f; /* Reset bits 4-6 */
7939 elink_cl45_write(sc, phy,
7940 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
7944 PMD_DRV_LOG(DEBUG, sc, "Function 0x%x not supported by 8727",
7950 static void elink_set_e1e2_module_fault_led(struct elink_params *params,
7953 struct bnx2x_softc *sc = params->sc;
7955 uint32_t fault_led_gpio = REG_RD(sc, params->shmem_base +
7956 offsetof(struct shmem_region,
7958 port_hw_config[params->port].
7960 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
7961 switch (fault_led_gpio) {
7962 case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
7964 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:
7965 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
7966 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
7967 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
7969 uint8_t gpio_port = elink_get_gpio_port(params);
7970 uint16_t gpio_pin = fault_led_gpio -
7971 PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
7972 PMD_DRV_LOG(DEBUG, sc, "Set fault module-detected led "
7973 "pin %x port %x mode %x",
7974 gpio_pin, gpio_port, gpio_mode);
7975 elink_cb_gpio_write(sc, gpio_pin, gpio_mode, gpio_port);
7979 PMD_DRV_LOG(DEBUG, sc, "Error: Invalid fault led mode 0x%x",
7984 static void elink_set_e3_module_fault_led(struct elink_params *params,
7988 uint8_t port = params->port;
7989 struct bnx2x_softc *sc = params->sc;
7990 pin_cfg = (REG_RD(sc, params->shmem_base +
7991 offsetof(struct shmem_region,
7992 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
7993 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
7994 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
7995 PMD_DRV_LOG(DEBUG, sc, "Setting Fault LED to %d using pin cfg %d",
7996 gpio_mode, pin_cfg);
7997 elink_set_cfg_pin(sc, pin_cfg, gpio_mode);
8000 static void elink_set_sfp_module_fault_led(struct elink_params *params,
8003 struct bnx2x_softc *sc = params->sc;
8004 PMD_DRV_LOG(DEBUG, sc,
8005 "Setting SFP+ module fault LED to %d", gpio_mode);
8006 if (CHIP_IS_E3(sc)) {
8007 /* Low ==> if SFP+ module is supported otherwise
8008 * High ==> if SFP+ module is not on the approved vendor list
8010 elink_set_e3_module_fault_led(params, gpio_mode);
8012 elink_set_e1e2_module_fault_led(params, gpio_mode);
8015 static void elink_warpcore_hw_reset(__rte_unused struct elink_phy *phy,
8016 struct elink_params *params)
8018 struct bnx2x_softc *sc = params->sc;
8019 elink_warpcore_power_module(params, 0);
8020 /* Put Warpcore in low power mode */
8021 REG_WR(sc, MISC_REG_WC0_RESET, 0x0c0e);
8023 /* Put LCPLL in low power mode */
8024 REG_WR(sc, MISC_REG_LCPLL_E40_PWRDWN, 1);
8025 REG_WR(sc, MISC_REG_LCPLL_E40_RESETB_ANA, 0);
8026 REG_WR(sc, MISC_REG_LCPLL_E40_RESETB_DIG, 0);
8029 static void elink_power_sfp_module(struct elink_params *params,
8030 struct elink_phy *phy, uint8_t power)
8032 PMD_DRV_LOG(DEBUG, params->sc, "Setting SFP+ power to %x", power);
8034 switch (phy->type) {
8035 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727:
8036 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722:
8037 elink_8727_power_module(params->sc, phy, power);
8039 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8040 elink_warpcore_power_module(params, power);
8047 static void elink_warpcore_set_limiting_mode(struct elink_params *params,
8048 struct elink_phy *phy,
8052 uint16_t mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8053 struct bnx2x_softc *sc = params->sc;
8055 uint8_t lane = elink_get_warpcore_lane(params);
8056 /* This is a global register which controls all lanes */
8057 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
8058 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8059 val &= ~(0xf << (lane << 2));
8062 case ELINK_EDC_MODE_LINEAR:
8063 case ELINK_EDC_MODE_LIMITING:
8064 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8066 case ELINK_EDC_MODE_PASSIVE_DAC:
8067 case ELINK_EDC_MODE_ACTIVE_DAC:
8068 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC;
8074 val |= (mode << (lane << 2));
8075 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
8076 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val);
8078 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
8079 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8081 /* Restart microcode to re-read the new mode */
8082 elink_warpcore_reset_lane(sc, phy, 1);
8083 elink_warpcore_reset_lane(sc, phy, 0);
8087 static void elink_set_limiting_mode(struct elink_params *params,
8088 struct elink_phy *phy, uint16_t edc_mode)
8090 switch (phy->type) {
8091 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726:
8092 elink_8726_set_limiting_mode(params->sc, phy, edc_mode);
8094 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727:
8095 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722:
8096 elink_8727_set_limiting_mode(params->sc, phy, edc_mode);
8098 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8099 elink_warpcore_set_limiting_mode(params, phy, edc_mode);
8104 static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
8105 struct elink_params *params)
8107 struct bnx2x_softc *sc = params->sc;
8109 elink_status_t rc = ELINK_STATUS_OK;
8111 uint32_t val = REG_RD(sc, params->shmem_base +
8112 offsetof(struct shmem_region,
8113 dev_info.port_feature_config[params->
8116 /* Enabled transmitter by default */
8117 elink_sfp_set_transmitter(params, phy, 1);
8118 PMD_DRV_LOG(DEBUG, sc, "SFP+ module plugged in/out detected on port %d",
8120 /* Power up module */
8121 elink_power_sfp_module(params, phy, 1);
8122 if (elink_get_edc_mode(phy, params, &edc_mode) != 0) {
8123 PMD_DRV_LOG(DEBUG, sc, "Failed to get valid module type");
8124 return ELINK_STATUS_ERROR;
8125 } else if (elink_verify_sfp_module(phy, params) != 0) {
8126 /* Check SFP+ module compatibility */
8127 PMD_DRV_LOG(DEBUG, sc, "Module verification failed!!");
8128 rc = ELINK_STATUS_ERROR;
8129 /* Turn on fault module-detected led */
8130 elink_set_sfp_module_fault_led(params,
8131 MISC_REGISTERS_GPIO_HIGH);
8133 /* Check if need to power down the SFP+ module */
8134 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8135 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
8136 PMD_DRV_LOG(DEBUG, sc, "Shutdown SFP+ module!!");
8137 elink_power_sfp_module(params, phy, 0);
8141 /* Turn off fault module-detected led */
8142 elink_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
8145 /* Check and set limiting mode / LRM mode on 8726. On 8727 it
8146 * is done automatically
8148 elink_set_limiting_mode(params, phy, edc_mode);
8150 /* Disable transmit for this module if the module is not approved, and
8151 * laser needs to be disabled.
8154 ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8155 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER))
8156 elink_sfp_set_transmitter(params, phy, 0);
8161 void elink_handle_module_detect_int(struct elink_params *params)
8163 struct bnx2x_softc *sc = params->sc;
8164 struct elink_phy *phy;
8166 uint8_t gpio_num, gpio_port;
8167 if (CHIP_IS_E3(sc)) {
8168 phy = ¶ms->phy[ELINK_INT_PHY];
8169 /* Always enable TX laser,will be disabled in case of fault */
8170 elink_sfp_set_transmitter(params, phy, 1);
8172 phy = ¶ms->phy[ELINK_EXT_PHY1];
8174 if (elink_get_mod_abs_int_cfg(sc, params->shmem_base,
8175 params->port, &gpio_num, &gpio_port) ==
8176 ELINK_STATUS_ERROR) {
8177 PMD_DRV_LOG(DEBUG, sc, "Failed to get MOD_ABS interrupt config");
8181 /* Set valid module led off */
8182 elink_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
8184 /* Get current gpio val reflecting module plugged in / out */
8185 gpio_val = elink_cb_gpio_read(sc, gpio_num, gpio_port);
8187 /* Call the handling function in case module is detected */
8188 if (gpio_val == 0) {
8189 elink_set_mdio_emac_per_phy(sc, params);
8190 elink_set_aer_mmd(params, phy);
8192 elink_power_sfp_module(params, phy, 1);
8193 elink_cb_gpio_int_write(sc, gpio_num,
8194 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
8196 if (elink_wait_for_sfp_module_initialized(phy, params) == 0) {
8197 elink_sfp_module_detection(phy, params);
8198 if (CHIP_IS_E3(sc)) {
8199 uint16_t rx_tx_in_reset;
8200 /* In case WC is out of reset, reconfigure the
8201 * link speed while taking into account 1G
8202 * module limitation.
8204 elink_cl45_read(sc, phy,
8206 MDIO_WC_REG_DIGITAL5_MISC6,
8208 if ((!rx_tx_in_reset) &&
8209 (params->link_flags &
8210 ELINK_PHY_INITIALIZED)) {
8211 elink_warpcore_reset_lane(sc, phy, 1);
8212 elink_warpcore_config_sfi(phy, params);
8213 elink_warpcore_reset_lane(sc, phy, 0);
8217 PMD_DRV_LOG(DEBUG, sc, "SFP+ module is not initialized");
8220 elink_cb_gpio_int_write(sc, gpio_num,
8221 MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
8223 /* Module was plugged out.
8224 * Disable transmit for this module
8226 phy->media_type = ELINK_ETH_PHY_NOT_PRESENT;
8230 /******************************************************************/
8231 /* Used by 8706 and 8727 */
8232 /******************************************************************/
8233 static void elink_sfp_mask_fault(struct bnx2x_softc *sc,
8234 struct elink_phy *phy,
8235 uint16_t alarm_status_offset,
8236 uint16_t alarm_ctrl_offset)
8238 uint16_t alarm_status, val;
8239 elink_cl45_read(sc, phy,
8240 MDIO_PMA_DEVAD, alarm_status_offset, &alarm_status);
8241 elink_cl45_read(sc, phy,
8242 MDIO_PMA_DEVAD, alarm_status_offset, &alarm_status);
8243 /* Mask or enable the fault event. */
8244 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
8245 if (alarm_status & (1 << 0))
8249 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
8252 /******************************************************************/
8253 /* common BNX2X8706/BNX2X8726 PHY SECTION */
8254 /******************************************************************/
8255 static uint8_t elink_8706_8726_read_status(struct elink_phy *phy,
8256 struct elink_params *params,
8257 struct elink_vars *vars)
8259 uint8_t link_up = 0;
8260 uint16_t val1, val2, rx_sd, pcs_status;
8261 struct bnx2x_softc *sc = params->sc;
8262 PMD_DRV_LOG(DEBUG, sc, "XGXS 8706/8726");
8263 /* Clear RX Alarm */
8264 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
8266 elink_sfp_mask_fault(sc, phy, MDIO_PMA_LASI_TXSTAT,
8267 MDIO_PMA_LASI_TXCTRL);
8269 /* Clear LASI indication */
8270 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8271 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
8272 PMD_DRV_LOG(DEBUG, sc,
8273 "8706/8726 LASI status 0x%x--> 0x%x", val1, val2);
8275 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
8276 elink_cl45_read(sc, phy,
8277 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
8278 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8279 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8281 PMD_DRV_LOG(DEBUG, sc, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
8282 " link_status 0x%x", rx_sd, pcs_status, val2);
8283 /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
8284 * are set, or if the autoneg bit 1 is set
8286 link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1 << 1)));
8288 if (val2 & (1 << 1))
8289 vars->line_speed = ELINK_SPEED_1000;
8291 vars->line_speed = ELINK_SPEED_10000;
8292 elink_ext_phy_resolve_fc(phy, params, vars);
8293 vars->duplex = DUPLEX_FULL;
8296 /* Capture 10G link fault. Read twice to clear stale value. */
8297 if (vars->line_speed == ELINK_SPEED_10000) {
8298 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
8299 MDIO_PMA_LASI_TXSTAT, &val1);
8300 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
8301 MDIO_PMA_LASI_TXSTAT, &val1);
8302 if (val1 & (1 << 0))
8303 vars->fault_detected = 1;
8309 /******************************************************************/
8310 /* BNX2X8706 PHY SECTION */
8311 /******************************************************************/
8312 static uint8_t elink_8706_config_init(struct elink_phy *phy,
8313 struct elink_params *params,
8314 __rte_unused struct elink_vars *vars)
8316 uint32_t tx_en_mode;
8317 uint16_t cnt, val, tmp1;
8318 struct bnx2x_softc *sc = params->sc;
8320 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
8321 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
8323 elink_ext_phy_hw_reset(sc, params->port);
8324 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
8325 elink_wait_reset_complete(sc, phy, params);
8327 /* Wait until fw is loaded */
8328 for (cnt = 0; cnt < 100; cnt++) {
8329 elink_cl45_read(sc, phy,
8330 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
8335 PMD_DRV_LOG(DEBUG, sc, "XGXS 8706 is initialized after %d ms", cnt);
8336 if ((params->feature_config_flags &
8337 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8340 for (i = 0; i < 4; i++) {
8341 reg = MDIO_XS_8706_REG_BANK_RX0 +
8342 i * (MDIO_XS_8706_REG_BANK_RX1 -
8343 MDIO_XS_8706_REG_BANK_RX0);
8344 elink_cl45_read(sc, phy, MDIO_XS_DEVAD, reg, &val);
8345 /* Clear first 3 bits of the control */
8347 /* Set control bits according to configuration */
8348 val |= (phy->rx_preemphasis[i] & 0x7);
8349 PMD_DRV_LOG(DEBUG, sc, "Setting RX Equalizer to BNX2X8706"
8350 " reg 0x%x <-- val 0x%x", reg, val);
8351 elink_cl45_write(sc, phy, MDIO_XS_DEVAD, reg, val);
8355 if (phy->req_line_speed == ELINK_SPEED_10000) {
8356 PMD_DRV_LOG(DEBUG, sc, "XGXS 8706 force 10Gbps");
8358 elink_cl45_write(sc, phy,
8360 MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
8361 elink_cl45_write(sc, phy,
8362 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, 0);
8363 /* Arm LASI for link and Tx fault. */
8364 elink_cl45_write(sc, phy,
8365 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3);
8367 /* Force 1Gbps using autoneg with 1G advertisement */
8369 /* Allow CL37 through CL73 */
8370 PMD_DRV_LOG(DEBUG, sc, "XGXS 8706 AutoNeg");
8371 elink_cl45_write(sc, phy,
8372 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8374 /* Enable Full-Duplex advertisement on CL37 */
8375 elink_cl45_write(sc, phy,
8376 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
8377 /* Enable CL37 AN */
8378 elink_cl45_write(sc, phy,
8379 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8381 elink_cl45_write(sc, phy,
8382 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1 << 5));
8384 /* Enable clause 73 AN */
8385 elink_cl45_write(sc, phy,
8386 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8387 elink_cl45_write(sc, phy,
8388 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 0x0400);
8389 elink_cl45_write(sc, phy,
8390 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0004);
8392 elink_save_bnx2x_spirom_ver(sc, phy, params->port);
8394 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
8395 * power mode, if TX Laser is disabled
8398 tx_en_mode = REG_RD(sc, params->shmem_base +
8399 offsetof(struct shmem_region,
8400 dev_info.port_hw_config[params->port].
8402 & PORT_HW_CFG_TX_LASER_MASK;
8404 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8405 PMD_DRV_LOG(DEBUG, sc, "Enabling TXONOFF_PWRDN_DIS");
8406 elink_cl45_read(sc, phy,
8407 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL,
8410 elink_cl45_write(sc, phy,
8411 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL,
8415 return ELINK_STATUS_OK;
8418 static uint8_t elink_8706_read_status(struct elink_phy *phy,
8419 struct elink_params *params,
8420 struct elink_vars *vars)
8422 return elink_8706_8726_read_status(phy, params, vars);
8425 /******************************************************************/
8426 /* BNX2X8726 PHY SECTION */
8427 /******************************************************************/
8428 static void elink_8726_config_loopback(struct elink_phy *phy,
8429 struct elink_params *params)
8431 struct bnx2x_softc *sc = params->sc;
8432 PMD_DRV_LOG(DEBUG, sc, "PMA/PMD ext_phy_loopback: 8726");
8433 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
8436 static void elink_8726_external_rom_boot(struct elink_phy *phy,
8437 struct elink_params *params)
8439 struct bnx2x_softc *sc = params->sc;
8440 /* Need to wait 100ms after reset */
8443 /* Micro controller re-boot */
8444 elink_cl45_write(sc, phy,
8445 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
8447 /* Set soft reset */
8448 elink_cl45_write(sc, phy,
8450 MDIO_PMA_REG_GEN_CTRL,
8451 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
8453 elink_cl45_write(sc, phy,
8454 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL1, 0x0001);
8456 elink_cl45_write(sc, phy,
8458 MDIO_PMA_REG_GEN_CTRL,
8459 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
8461 /* Wait for 150ms for microcode load */
8464 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
8465 elink_cl45_write(sc, phy,
8466 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL1, 0x0000);
8469 elink_save_bnx2x_spirom_ver(sc, phy, params->port);
8472 static uint8_t elink_8726_read_status(struct elink_phy *phy,
8473 struct elink_params *params,
8474 struct elink_vars *vars)
8476 struct bnx2x_softc *sc = params->sc;
8478 uint8_t link_up = elink_8706_8726_read_status(phy, params, vars);
8480 elink_cl45_read(sc, phy,
8481 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
8483 if (val1 & (1 << 15)) {
8484 PMD_DRV_LOG(DEBUG, sc, "Tx is disabled");
8486 vars->line_speed = 0;
8492 static uint8_t elink_8726_config_init(struct elink_phy *phy,
8493 struct elink_params *params,
8494 struct elink_vars *vars)
8496 struct bnx2x_softc *sc = params->sc;
8497 PMD_DRV_LOG(DEBUG, sc, "Initializing BNX2X8726");
8499 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1 << 15);
8500 elink_wait_reset_complete(sc, phy, params);
8502 elink_8726_external_rom_boot(phy, params);
8504 /* Need to call module detected on initialization since the module
8505 * detection triggered by actual module insertion might occur before
8506 * driver is loaded, and when driver is loaded, it reset all
8507 * registers, including the transmitter
8509 elink_sfp_module_detection(phy, params);
8511 if (phy->req_line_speed == ELINK_SPEED_1000) {
8512 PMD_DRV_LOG(DEBUG, sc, "Setting 1G force");
8513 elink_cl45_write(sc, phy,
8514 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
8515 elink_cl45_write(sc, phy,
8516 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
8517 elink_cl45_write(sc, phy,
8518 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5);
8519 elink_cl45_write(sc, phy,
8520 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 0x400);
8521 } else if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
8522 (phy->speed_cap_mask &
8523 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
8524 ((phy->speed_cap_mask &
8525 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
8526 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8527 PMD_DRV_LOG(DEBUG, sc, "Setting 1G clause37");
8528 /* Set Flow control */
8529 elink_ext_phy_set_pause(params, phy, vars);
8530 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
8531 elink_cl45_write(sc, phy,
8532 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8533 elink_cl45_write(sc, phy,
8534 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
8535 elink_cl45_write(sc, phy,
8536 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8537 elink_cl45_write(sc, phy,
8538 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8539 /* Enable RX-ALARM control to receive interrupt for 1G speed
8542 elink_cl45_write(sc, phy,
8543 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4);
8544 elink_cl45_write(sc, phy,
8545 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 0x400);
8547 } else { /* Default 10G. Set only LASI control */
8548 elink_cl45_write(sc, phy,
8549 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1);
8552 /* Set TX PreEmphasis if needed */
8553 if ((params->feature_config_flags &
8554 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8555 PMD_DRV_LOG(DEBUG, sc,
8556 "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x",
8557 phy->tx_preemphasis[0], phy->tx_preemphasis[1]);
8558 elink_cl45_write(sc, phy,
8560 MDIO_PMA_REG_8726_TX_CTRL1,
8561 phy->tx_preemphasis[0]);
8563 elink_cl45_write(sc, phy,
8565 MDIO_PMA_REG_8726_TX_CTRL2,
8566 phy->tx_preemphasis[1]);
8569 return ELINK_STATUS_OK;
8573 static void elink_8726_link_reset(struct elink_phy *phy,
8574 struct elink_params *params)
8576 struct bnx2x_softc *sc = params->sc;
8577 PMD_DRV_LOG(DEBUG, sc, "elink_8726_link_reset port %d", params->port);
8578 /* Set serial boot control for external load */
8579 elink_cl45_write(sc, phy,
8580 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
8583 /******************************************************************/
8584 /* BNX2X8727 PHY SECTION */
8585 /******************************************************************/
8587 static void elink_8727_set_link_led(struct elink_phy *phy,
8588 struct elink_params *params, uint8_t mode)
8590 struct bnx2x_softc *sc = params->sc;
8591 uint16_t led_mode_bitmask = 0;
8592 uint16_t gpio_pins_bitmask = 0;
8594 /* Only NOC flavor requires to set the LED specifically */
8595 if (!(phy->flags & ELINK_FLAGS_NOC))
8598 case ELINK_LED_MODE_FRONT_PANEL_OFF:
8599 case ELINK_LED_MODE_OFF:
8600 led_mode_bitmask = 0;
8601 gpio_pins_bitmask = 0x03;
8603 case ELINK_LED_MODE_ON:
8604 led_mode_bitmask = 0;
8605 gpio_pins_bitmask = 0x02;
8607 case ELINK_LED_MODE_OPER:
8608 led_mode_bitmask = 0x60;
8609 gpio_pins_bitmask = 0x11;
8612 elink_cl45_read(sc, phy,
8613 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, &val);
8615 val |= led_mode_bitmask;
8616 elink_cl45_write(sc, phy,
8617 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val);
8618 elink_cl45_read(sc, phy,
8619 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, &val);
8621 val |= gpio_pins_bitmask;
8622 elink_cl45_write(sc, phy,
8623 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, val);
8626 static void elink_8727_hw_reset(__rte_unused struct elink_phy *phy,
8627 struct elink_params *params)
8629 uint32_t swap_val, swap_override;
8631 /* The PHY reset is controlled by GPIO 1. Fake the port number
8632 * to cancel the swap done in set_gpio()
8634 struct bnx2x_softc *sc = params->sc;
8635 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
8636 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
8637 port = (swap_val && swap_override) ^ 1;
8638 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
8639 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
8642 static void elink_8727_config_speed(struct elink_phy *phy,
8643 struct elink_params *params)
8645 struct bnx2x_softc *sc = params->sc;
8647 /* Set option 1G speed */
8648 if ((phy->req_line_speed == ELINK_SPEED_1000) ||
8649 (phy->media_type == ELINK_ETH_PHY_SFP_1G_FIBER)) {
8650 PMD_DRV_LOG(DEBUG, sc, "Setting 1G force");
8651 elink_cl45_write(sc, phy,
8652 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
8653 elink_cl45_write(sc, phy,
8654 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
8655 elink_cl45_read(sc, phy,
8656 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
8657 PMD_DRV_LOG(DEBUG, sc, "1.7 = 0x%x", tmp1);
8658 /* Power down the XAUI until link is up in case of dual-media
8661 if (ELINK_DUAL_MEDIA(params)) {
8662 elink_cl45_read(sc, phy,
8664 MDIO_PMA_REG_8727_PCS_GP, &val);
8666 elink_cl45_write(sc, phy,
8668 MDIO_PMA_REG_8727_PCS_GP, val);
8670 } else if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
8671 ((phy->speed_cap_mask &
8672 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
8673 ((phy->speed_cap_mask &
8674 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
8675 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8677 PMD_DRV_LOG(DEBUG, sc, "Setting 1G clause37");
8678 elink_cl45_write(sc, phy,
8679 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
8680 elink_cl45_write(sc, phy,
8681 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
8683 /* Since the 8727 has only single reset pin, need to set the 10G
8684 * registers although it is default
8686 elink_cl45_write(sc, phy,
8687 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
8689 elink_cl45_write(sc, phy,
8690 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
8691 elink_cl45_write(sc, phy,
8692 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
8693 elink_cl45_write(sc, phy,
8694 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
8699 static uint8_t elink_8727_config_init(struct elink_phy *phy,
8700 struct elink_params *params,
8701 __rte_unused struct elink_vars
8704 uint32_t tx_en_mode;
8705 uint16_t tmp1, mod_abs, tmp2;
8706 struct bnx2x_softc *sc = params->sc;
8707 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
8709 elink_wait_reset_complete(sc, phy, params);
8711 PMD_DRV_LOG(DEBUG, sc, "Initializing BNX2X8727");
8713 elink_8727_specific_func(phy, params, ELINK_PHY_INIT);
8714 /* Initially configure MOD_ABS to interrupt when module is
8717 elink_cl45_read(sc, phy,
8718 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
8719 /* Set EDC off by setting OPTXLOS signal input to low (bit 9).
8720 * When the EDC is off it locks onto a reference clock and avoids
8723 mod_abs &= ~(1 << 8);
8724 if (!(phy->flags & ELINK_FLAGS_NOC))
8725 mod_abs &= ~(1 << 9);
8726 elink_cl45_write(sc, phy,
8727 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
8729 /* Enable/Disable PHY transmitter output */
8730 elink_set_disable_pmd_transmit(params, phy, 0);
8732 elink_8727_power_module(sc, phy, 1);
8734 elink_cl45_read(sc, phy,
8735 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
8737 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
8739 elink_8727_config_speed(phy, params);
8741 /* Set TX PreEmphasis if needed */
8742 if ((params->feature_config_flags &
8743 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8744 PMD_DRV_LOG(DEBUG, sc, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x",
8745 phy->tx_preemphasis[0], phy->tx_preemphasis[1]);
8746 elink_cl45_write(sc, phy,
8747 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
8748 phy->tx_preemphasis[0]);
8750 elink_cl45_write(sc, phy,
8751 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
8752 phy->tx_preemphasis[1]);
8755 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
8756 * power mode, if TX Laser is disabled
8758 tx_en_mode = REG_RD(sc, params->shmem_base +
8759 offsetof(struct shmem_region,
8760 dev_info.port_hw_config[params->port].
8762 & PORT_HW_CFG_TX_LASER_MASK;
8764 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8766 PMD_DRV_LOG(DEBUG, sc, "Enabling TXONOFF_PWRDN_DIS");
8767 elink_cl45_read(sc, phy,
8768 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG,
8772 elink_cl45_write(sc, phy,
8773 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG,
8775 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
8776 MDIO_PMA_REG_PHY_IDENTIFIER, &tmp2);
8777 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD,
8778 MDIO_PMA_REG_PHY_IDENTIFIER, (tmp2 & 0x7fff));
8781 return ELINK_STATUS_OK;
8784 static void elink_8727_handle_mod_abs(struct elink_phy *phy,
8785 struct elink_params *params)
8787 struct bnx2x_softc *sc = params->sc;
8788 uint16_t mod_abs, rx_alarm_status;
8789 uint32_t val = REG_RD(sc, params->shmem_base +
8790 offsetof(struct shmem_region,
8791 dev_info.port_feature_config[params->
8793 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
8795 if (mod_abs & (1 << 8)) {
8797 /* Module is absent */
8798 PMD_DRV_LOG(DEBUG, sc, "MOD_ABS indication show module is absent");
8799 phy->media_type = ELINK_ETH_PHY_NOT_PRESENT;
8800 /* 1. Set mod_abs to detect next module
8802 * 2. Set EDC off by setting OPTXLOS signal input to low
8804 * When the EDC is off it locks onto a reference clock and
8805 * avoids becoming 'lost'.
8807 mod_abs &= ~(1 << 8);
8808 if (!(phy->flags & ELINK_FLAGS_NOC))
8809 mod_abs &= ~(1 << 9);
8810 elink_cl45_write(sc, phy,
8812 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
8814 /* Clear RX alarm since it stays up as long as
8815 * the mod_abs wasn't changed
8817 elink_cl45_read(sc, phy,
8819 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
8822 /* Module is present */
8823 PMD_DRV_LOG(DEBUG, sc, "MOD_ABS indication show module is present");
8824 /* First disable transmitter, and if the module is ok, the
8825 * module_detection will enable it
8826 * 1. Set mod_abs to detect next module absent event ( bit 8)
8827 * 2. Restore the default polarity of the OPRXLOS signal and
8828 * this signal will then correctly indicate the presence or
8829 * absence of the Rx signal. (bit 9)
8831 mod_abs |= (1 << 8);
8832 if (!(phy->flags & ELINK_FLAGS_NOC))
8833 mod_abs |= (1 << 9);
8834 elink_cl45_write(sc, phy,
8836 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
8838 /* Clear RX alarm since it stays up as long as the mod_abs
8839 * wasn't changed. This is need to be done before calling the
8840 * module detection, otherwise it will clear* the link update
8843 elink_cl45_read(sc, phy,
8845 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
8847 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8848 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
8849 elink_sfp_set_transmitter(params, phy, 0);
8851 if (elink_wait_for_sfp_module_initialized(phy, params) == 0) {
8852 elink_sfp_module_detection(phy, params);
8854 PMD_DRV_LOG(DEBUG, sc, "SFP+ module is not initialized");
8857 /* Reconfigure link speed based on module type limitations */
8858 elink_8727_config_speed(phy, params);
8861 PMD_DRV_LOG(DEBUG, sc, "8727 RX_ALARM_STATUS 0x%x", rx_alarm_status);
8862 /* No need to check link status in case of module plugged in/out */
8865 static uint8_t elink_8727_read_status(struct elink_phy *phy,
8866 struct elink_params *params,
8867 struct elink_vars *vars)
8869 struct bnx2x_softc *sc = params->sc;
8870 uint8_t link_up = 0, oc_port = params->port;
8871 uint16_t link_status = 0;
8872 uint16_t rx_alarm_status, lasi_ctrl, val1;
8874 /* If PHY is not initialized, do not check link status */
8875 elink_cl45_read(sc, phy,
8876 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, &lasi_ctrl);
8880 /* Check the LASI on Rx */
8881 elink_cl45_read(sc, phy,
8882 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
8883 vars->line_speed = 0;
8884 PMD_DRV_LOG(DEBUG, sc, "8727 RX_ALARM_STATUS 0x%x", rx_alarm_status);
8886 elink_sfp_mask_fault(sc, phy, MDIO_PMA_LASI_TXSTAT,
8887 MDIO_PMA_LASI_TXCTRL);
8889 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8891 PMD_DRV_LOG(DEBUG, sc, "8727 LASI status 0x%x", val1);
8894 elink_cl45_read(sc, phy,
8895 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
8897 /* If a module is present and there is need to check
8900 if (!(phy->flags & ELINK_FLAGS_NOC) && !(rx_alarm_status & (1 << 5))) {
8901 /* Check over-current using 8727 GPIO0 input */
8902 elink_cl45_read(sc, phy,
8903 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
8906 if ((val1 & (1 << 8)) == 0) {
8907 if (!CHIP_IS_E1x(sc))
8908 oc_port = SC_PATH(sc) + (params->port << 1);
8909 PMD_DRV_LOG(DEBUG, sc,
8910 "8727 Power fault has been detected on port %d",
8912 elink_cb_event_log(sc, ELINK_LOG_ID_OVER_CURRENT, oc_port); //"Error: Power fault on Port %d has "
8913 // "been detected and the power to "
8914 // "that SFP+ module has been removed "
8915 // "to prevent failure of the card. "
8916 // "Please remove the SFP+ module and "
8917 // "restart the system to clear this "
8919 /* Disable all RX_ALARMs except for mod_abs */
8920 elink_cl45_write(sc, phy,
8922 MDIO_PMA_LASI_RXCTRL, (1 << 5));
8924 elink_cl45_read(sc, phy,
8926 MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
8927 /* Wait for module_absent_event */
8929 elink_cl45_write(sc, phy,
8931 MDIO_PMA_REG_PHY_IDENTIFIER, val1);
8932 /* Clear RX alarm */
8933 elink_cl45_read(sc, phy,
8935 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
8936 elink_8727_power_module(params->sc, phy, 0);
8941 /* Over current check */
8942 /* When module absent bit is set, check module */
8943 if (rx_alarm_status & (1 << 5)) {
8944 elink_8727_handle_mod_abs(phy, params);
8945 /* Enable all mod_abs and link detection bits */
8946 elink_cl45_write(sc, phy,
8947 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8948 ((1 << 5) | (1 << 2)));
8951 if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) {
8952 PMD_DRV_LOG(DEBUG, sc, "Enabling 8727 TX laser");
8953 elink_sfp_set_transmitter(params, phy, 1);
8955 PMD_DRV_LOG(DEBUG, sc, "Tx is disabled");
8959 elink_cl45_read(sc, phy,
8961 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
8963 /* Bits 0..2 --> speed detected,
8964 * Bits 13..15--> link is down
8966 if ((link_status & (1 << 2)) && (!(link_status & (1 << 15)))) {
8968 vars->line_speed = ELINK_SPEED_10000;
8969 PMD_DRV_LOG(DEBUG, sc, "port %x: External link up in 10G",
8971 } else if ((link_status & (1 << 0)) && (!(link_status & (1 << 13)))) {
8973 vars->line_speed = ELINK_SPEED_1000;
8974 PMD_DRV_LOG(DEBUG, sc, "port %x: External link up in 1G",
8978 PMD_DRV_LOG(DEBUG, sc, "port %x: External link is down",
8982 /* Capture 10G link fault. */
8983 if (vars->line_speed == ELINK_SPEED_10000) {
8984 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
8985 MDIO_PMA_LASI_TXSTAT, &val1);
8987 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
8988 MDIO_PMA_LASI_TXSTAT, &val1);
8990 if (val1 & (1 << 0)) {
8991 vars->fault_detected = 1;
8996 elink_ext_phy_resolve_fc(phy, params, vars);
8997 vars->duplex = DUPLEX_FULL;
8998 PMD_DRV_LOG(DEBUG, sc, "duplex = 0x%x", vars->duplex);
9001 if ((ELINK_DUAL_MEDIA(params)) &&
9002 (phy->req_line_speed == ELINK_SPEED_1000)) {
9003 elink_cl45_read(sc, phy,
9005 MDIO_PMA_REG_8727_PCS_GP, &val1);
9006 /* In case of dual-media board and 1G, power up the XAUI side,
9007 * otherwise power it down. For 10G it is done automatically
9013 elink_cl45_write(sc, phy,
9015 MDIO_PMA_REG_8727_PCS_GP, val1);
9020 static void elink_8727_link_reset(struct elink_phy *phy,
9021 struct elink_params *params)
9023 struct bnx2x_softc *sc = params->sc;
9025 /* Enable/Disable PHY transmitter output */
9026 elink_set_disable_pmd_transmit(params, phy, 1);
9028 /* Disable Transmitter */
9029 elink_sfp_set_transmitter(params, phy, 0);
9031 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0);
9035 /******************************************************************/
9036 /* BNX2X8481/BNX2X84823/BNX2X84833 PHY SECTION */
9037 /******************************************************************/
9038 static void elink_save_848xx_spirom_version(struct elink_phy *phy,
9039 struct bnx2x_softc *sc, uint8_t port)
9041 uint16_t val, fw_ver2, cnt, i;
9042 static struct elink_reg_set reg_set[] = {
9043 {MDIO_PMA_DEVAD, 0xA819, 0x0014},
9044 {MDIO_PMA_DEVAD, 0xA81A, 0xc200},
9045 {MDIO_PMA_DEVAD, 0xA81B, 0x0000},
9046 {MDIO_PMA_DEVAD, 0xA81C, 0x0300},
9047 {MDIO_PMA_DEVAD, 0xA817, 0x0009}
9051 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||
9052 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) {
9053 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1);
9054 elink_save_spirom_version(sc, port, fw_ver1 & 0xfff,
9057 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */
9058 /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
9059 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
9060 elink_cl45_write(sc, phy, reg_set[i].devad,
9061 reg_set[i].reg, reg_set[i].val);
9063 for (cnt = 0; cnt < 100; cnt++) {
9064 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9070 PMD_DRV_LOG(DEBUG, sc, "Unable to read 848xx "
9071 "phy fw version(1)");
9072 elink_save_spirom_version(sc, port, 0, phy->ver_addr);
9076 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
9077 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
9078 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9079 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
9080 for (cnt = 0; cnt < 100; cnt++) {
9081 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9087 PMD_DRV_LOG(DEBUG, sc, "Unable to read 848xx phy fw "
9089 elink_save_spirom_version(sc, port, 0, phy->ver_addr);
9093 /* lower 16 bits of the register SPI_FW_STATUS */
9094 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
9095 /* upper 16 bits of register SPI_FW_STATUS */
9096 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
9098 elink_save_spirom_version(sc, port, (fw_ver2 << 16) | fw_ver1,
9104 static void elink_848xx_set_led(struct bnx2x_softc *sc, struct elink_phy *phy)
9106 uint16_t val, offset, i;
9107 static struct elink_reg_set reg_set[] = {
9108 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED1_MASK, 0x0080},
9109 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED2_MASK, 0x0018},
9110 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_MASK, 0x0006},
9111 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_BLINK, 0x0000},
9112 {MDIO_PMA_DEVAD, MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH,
9113 MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ},
9114 {MDIO_AN_DEVAD, 0xFFFB, 0xFFFD}
9116 /* PHYC_CTL_LED_CTL */
9117 elink_cl45_read(sc, phy,
9118 MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
9122 elink_cl45_write(sc, phy,
9123 MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LINK_SIGNAL, val);
9125 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
9126 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
9129 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||
9130 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834))
9131 offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1;
9133 offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1;
9135 /* stretch_en for LED3 */
9136 elink_cl45_read_or_write(sc, phy,
9137 MDIO_PMA_DEVAD, offset,
9138 MDIO_PMA_REG_84823_LED3_STRETCH_EN);
9141 static void elink_848xx_specific_func(struct elink_phy *phy,
9142 struct elink_params *params,
9145 struct bnx2x_softc *sc = params->sc;
9147 case ELINK_PHY_INIT:
9148 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) &&
9149 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) {
9150 /* Save spirom version */
9151 elink_save_848xx_spirom_version(phy, sc, params->port);
9153 /* This phy uses the NIG latch mechanism since link indication
9154 * arrives through its LED4 and not via its LASI signal, so we
9155 * get steady signal instead of clear on read
9157 elink_bits_en(sc, NIG_REG_LATCH_BC_0 + params->port * 4,
9158 1 << ELINK_NIG_LATCH_BC_ENABLE_MI_INT);
9160 elink_848xx_set_led(sc, phy);
9165 static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy,
9166 struct elink_params *params,
9167 struct elink_vars *vars)
9169 struct bnx2x_softc *sc = params->sc;
9170 uint16_t autoneg_val, an_1000_val, an_10_100_val;
9172 elink_848xx_specific_func(phy, params, ELINK_PHY_INIT);
9173 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
9175 /* set 1000 speed advertisement */
9176 elink_cl45_read(sc, phy,
9177 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9180 elink_ext_phy_set_pause(params, phy, vars);
9181 elink_cl45_read(sc, phy,
9183 MDIO_AN_REG_8481_LEGACY_AN_ADV, &an_10_100_val);
9184 elink_cl45_read(sc, phy,
9185 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9187 /* Disable forced speed */
9189 ~((1 << 6) | (1 << 8) | (1 << 9) | (1 << 12) | (1 << 13));
9190 an_10_100_val &= ~((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8));
9192 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
9193 (phy->speed_cap_mask &
9194 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
9195 (phy->req_line_speed == ELINK_SPEED_1000)) {
9196 an_1000_val |= (1 << 8);
9197 autoneg_val |= (1 << 9 | 1 << 12);
9198 if (phy->req_duplex == DUPLEX_FULL)
9199 an_1000_val |= (1 << 9);
9200 PMD_DRV_LOG(DEBUG, sc, "Advertising 1G");
9202 an_1000_val &= ~((1 << 8) | (1 << 9));
9204 elink_cl45_write(sc, phy,
9205 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9208 /* Set 10/100 speed advertisement */
9209 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {
9210 if (phy->speed_cap_mask &
9211 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) {
9212 /* Enable autoneg and restart autoneg for legacy speeds
9214 autoneg_val |= (1 << 9 | 1 << 12);
9215 an_10_100_val |= (1 << 8);
9216 PMD_DRV_LOG(DEBUG, sc, "Advertising 100M-FD");
9219 if (phy->speed_cap_mask &
9220 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) {
9221 /* Enable autoneg and restart autoneg for legacy speeds
9223 autoneg_val |= (1 << 9 | 1 << 12);
9224 an_10_100_val |= (1 << 7);
9225 PMD_DRV_LOG(DEBUG, sc, "Advertising 100M-HD");
9228 if ((phy->speed_cap_mask &
9229 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
9230 (phy->supported & ELINK_SUPPORTED_10baseT_Full)) {
9231 an_10_100_val |= (1 << 6);
9232 autoneg_val |= (1 << 9 | 1 << 12);
9233 PMD_DRV_LOG(DEBUG, sc, "Advertising 10M-FD");
9236 if ((phy->speed_cap_mask &
9237 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) &&
9238 (phy->supported & ELINK_SUPPORTED_10baseT_Half)) {
9239 an_10_100_val |= (1 << 5);
9240 autoneg_val |= (1 << 9 | 1 << 12);
9241 PMD_DRV_LOG(DEBUG, sc, "Advertising 10M-HD");
9245 /* Only 10/100 are allowed to work in FORCE mode */
9246 if ((phy->req_line_speed == ELINK_SPEED_100) &&
9248 (ELINK_SUPPORTED_100baseT_Half | ELINK_SUPPORTED_100baseT_Full))) {
9249 autoneg_val |= (1 << 13);
9250 /* Enabled AUTO-MDIX when autoneg is disabled */
9251 elink_cl45_write(sc, phy,
9252 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9253 (1 << 15 | 1 << 9 | 7 << 0));
9254 /* The PHY needs this set even for forced link. */
9255 an_10_100_val |= (1 << 8) | (1 << 7);
9256 PMD_DRV_LOG(DEBUG, sc, "Setting 100M force");
9258 if ((phy->req_line_speed == ELINK_SPEED_10) &&
9260 (ELINK_SUPPORTED_10baseT_Half | ELINK_SUPPORTED_10baseT_Full))) {
9261 /* Enabled AUTO-MDIX when autoneg is disabled */
9262 elink_cl45_write(sc, phy,
9263 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9264 (1 << 15 | 1 << 9 | 7 << 0));
9265 PMD_DRV_LOG(DEBUG, sc, "Setting 10M force");
9268 elink_cl45_write(sc, phy,
9269 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
9272 if (phy->req_duplex == DUPLEX_FULL)
9273 autoneg_val |= (1 << 8);
9275 /* Always write this if this is not 84833/4.
9276 * For 84833/4, write it only when it's a forced speed.
9278 if (((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) &&
9279 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) ||
9280 ((autoneg_val & (1 << 12)) == 0))
9281 elink_cl45_write(sc, phy,
9283 MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
9285 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
9286 (phy->speed_cap_mask &
9287 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
9288 (phy->req_line_speed == ELINK_SPEED_10000)) {
9289 PMD_DRV_LOG(DEBUG, sc, "Advertising 10G");
9290 /* Restart autoneg for 10G */
9292 elink_cl45_read_or_write(sc, phy,
9294 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9296 elink_cl45_write(sc, phy,
9297 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x3200);
9299 elink_cl45_write(sc, phy,
9301 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, 1);
9303 return ELINK_STATUS_OK;
9306 static uint8_t elink_8481_config_init(struct elink_phy *phy,
9307 struct elink_params *params,
9308 struct elink_vars *vars)
9310 struct bnx2x_softc *sc = params->sc;
9311 /* Restore normal power mode */
9312 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
9313 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
9316 elink_ext_phy_hw_reset(sc, params->port);
9317 elink_wait_reset_complete(sc, phy, params);
9319 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1 << 15);
9320 return elink_848xx_cmn_config_init(phy, params, vars);
9323 #define PHY84833_CMDHDLR_WAIT 300
9324 #define PHY84833_CMDHDLR_MAX_ARGS 5
9325 static elink_status_t elink_84833_cmd_hdlr(struct elink_phy *phy,
9326 struct elink_params *params,
9327 uint16_t fw_cmd, uint16_t cmd_args[],
9332 struct bnx2x_softc *sc = params->sc;
9333 /* Write CMD_OPEN_OVERRIDE to STATUS reg */
9334 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
9335 MDIO_84833_CMD_HDLR_STATUS,
9336 PHY84833_STATUS_CMD_OPEN_OVERRIDE);
9337 for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
9338 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
9339 MDIO_84833_CMD_HDLR_STATUS, &val);
9340 if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS)
9344 if (idx >= PHY84833_CMDHDLR_WAIT) {
9345 PMD_DRV_LOG(DEBUG, sc, "FW cmd: FW not ready.");
9346 return ELINK_STATUS_ERROR;
9349 /* Prepare argument(s) and issue command */
9350 for (idx = 0; idx < argc; idx++) {
9351 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
9352 MDIO_84833_CMD_HDLR_DATA1 + idx,
9355 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
9356 MDIO_84833_CMD_HDLR_COMMAND, fw_cmd);
9357 for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
9358 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
9359 MDIO_84833_CMD_HDLR_STATUS, &val);
9360 if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) ||
9361 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR))
9365 if ((idx >= PHY84833_CMDHDLR_WAIT) ||
9366 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) {
9367 PMD_DRV_LOG(DEBUG, sc, "FW cmd failed.");
9368 return ELINK_STATUS_ERROR;
9370 /* Gather returning data */
9371 for (idx = 0; idx < argc; idx++) {
9372 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
9373 MDIO_84833_CMD_HDLR_DATA1 + idx,
9376 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
9377 MDIO_84833_CMD_HDLR_STATUS,
9378 PHY84833_STATUS_CMD_CLEAR_COMPLETE);
9379 return ELINK_STATUS_OK;
9382 static elink_status_t elink_84833_pair_swap_cfg(struct elink_phy *phy,
9383 struct elink_params *params,
9384 __rte_unused struct elink_vars
9388 uint16_t data[PHY84833_CMDHDLR_MAX_ARGS];
9389 elink_status_t status;
9390 struct bnx2x_softc *sc = params->sc;
9392 /* Check for configuration. */
9393 pair_swap = REG_RD(sc, params->shmem_base +
9394 offsetof(struct shmem_region,
9395 dev_info.port_hw_config[params->port].
9397 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;
9400 return ELINK_STATUS_OK;
9402 /* Only the second argument is used for this command */
9403 data[1] = (uint16_t) pair_swap;
9405 status = elink_84833_cmd_hdlr(phy, params,
9406 PHY84833_CMD_SET_PAIR_SWAP, data,
9407 PHY84833_CMDHDLR_MAX_ARGS);
9408 if (status == ELINK_STATUS_OK) {
9409 PMD_DRV_LOG(DEBUG, sc, "Pairswap OK, val=0x%x", data[1]);
9415 static uint8_t elink_84833_get_reset_gpios(struct bnx2x_softc *sc,
9416 uint32_t shmem_base_path[],
9417 __rte_unused uint32_t chip_id)
9419 uint32_t reset_pin[2];
9421 uint8_t reset_gpios;
9422 if (CHIP_IS_E3(sc)) {
9423 /* Assume that these will be GPIOs, not EPIOs. */
9424 for (idx = 0; idx < 2; idx++) {
9425 /* Map config param to register bit. */
9426 reset_pin[idx] = REG_RD(sc, shmem_base_path[idx] +
9427 offsetof(struct shmem_region,
9432 (reset_pin[idx] & PORT_HW_CFG_E3_PHY_RESET_MASK) >>
9433 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
9434 reset_pin[idx] -= PIN_CFG_GPIO0_P0;
9435 reset_pin[idx] = (1 << reset_pin[idx]);
9437 reset_gpios = (uint8_t) (reset_pin[0] | reset_pin[1]);
9439 /* E2, look from diff place of shmem. */
9440 for (idx = 0; idx < 2; idx++) {
9441 reset_pin[idx] = REG_RD(sc, shmem_base_path[idx] +
9442 offsetof(struct shmem_region,
9446 reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK;
9447 reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0;
9448 reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT;
9449 reset_pin[idx] = (1 << reset_pin[idx]);
9451 reset_gpios = (uint8_t) (reset_pin[0] | reset_pin[1]);
9457 static void elink_84833_hw_reset_phy(struct elink_phy *phy,
9458 struct elink_params *params)
9460 struct bnx2x_softc *sc = params->sc;
9461 uint8_t reset_gpios;
9462 uint32_t other_shmem_base_addr = REG_RD(sc, params->shmem2_base +
9463 offsetof(struct shmem2_region,
9464 other_shmem_base_addr));
9466 uint32_t shmem_base_path[2];
9468 /* Work around for 84833 LED failure inside RESET status */
9469 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
9470 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9471 MDIO_AN_REG_8481_MII_CTRL_FORCE_1G);
9472 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
9473 MDIO_AN_REG_8481_1G_100T_EXT_CTRL,
9474 MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF);
9476 shmem_base_path[0] = params->shmem_base;
9477 shmem_base_path[1] = other_shmem_base_addr;
9479 reset_gpios = elink_84833_get_reset_gpios(sc, shmem_base_path,
9482 elink_cb_gpio_mult_write(sc, reset_gpios,
9483 MISC_REGISTERS_GPIO_OUTPUT_LOW);
9485 PMD_DRV_LOG(DEBUG, sc,
9486 "84833 hw reset on pin values 0x%x", reset_gpios);
9489 static elink_status_t elink_8483x_disable_eee(struct elink_phy *phy,
9490 struct elink_params *params,
9491 struct elink_vars *vars)
9494 uint16_t cmd_args = 0;
9496 PMD_DRV_LOG(DEBUG, params->sc, "Don't Advertise 10GBase-T EEE");
9498 /* Prevent Phy from working in EEE and advertising it */
9499 rc = elink_84833_cmd_hdlr(phy, params,
9500 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
9501 if (rc != ELINK_STATUS_OK) {
9502 PMD_DRV_LOG(DEBUG, params->sc, "EEE disable failed.");
9506 return elink_eee_disable(phy, params, vars);
9509 static elink_status_t elink_8483x_enable_eee(struct elink_phy *phy,
9510 struct elink_params *params,
9511 struct elink_vars *vars)
9514 uint16_t cmd_args = 1;
9516 rc = elink_84833_cmd_hdlr(phy, params,
9517 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
9518 if (rc != ELINK_STATUS_OK) {
9519 PMD_DRV_LOG(DEBUG, params->sc, "EEE enable failed.");
9523 return elink_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV);
9526 #define PHY84833_CONSTANT_LATENCY 1193
9527 static uint8_t elink_848x3_config_init(struct elink_phy *phy,
9528 struct elink_params *params,
9529 struct elink_vars *vars)
9531 struct bnx2x_softc *sc = params->sc;
9532 uint8_t port, initialize = 1;
9534 uint32_t actual_phy_selection;
9535 uint16_t cmd_args[PHY84833_CMDHDLR_MAX_ARGS];
9536 elink_status_t rc = ELINK_STATUS_OK;
9540 if (!(CHIP_IS_E1x(sc)))
9543 port = params->port;
9545 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823) {
9546 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_3,
9547 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
9550 elink_cl45_write(sc, phy,
9551 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x8000);
9554 elink_wait_reset_complete(sc, phy, params);
9556 /* Wait for GPHY to come out of reset */
9558 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) &&
9559 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) {
9560 /* BNX2X84823 requires that XGXS links up first @ 10G for normal
9564 temp = vars->line_speed;
9565 vars->line_speed = ELINK_SPEED_10000;
9566 elink_set_autoneg(¶ms->phy[ELINK_INT_PHY], params, vars, 0);
9567 elink_program_serdes(¶ms->phy[ELINK_INT_PHY], params, vars);
9568 vars->line_speed = temp;
9571 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
9572 MDIO_CTL_REG_84823_MEDIA, &val);
9573 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
9574 MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
9575 MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
9576 MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
9577 MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
9579 if (CHIP_IS_E3(sc)) {
9580 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
9581 MDIO_CTL_REG_84823_MEDIA_LINE_MASK);
9583 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI |
9584 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L);
9587 actual_phy_selection = elink_phy_selection(params);
9589 switch (actual_phy_selection) {
9590 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
9591 /* Do nothing. Essentially this is like the priority copper */
9593 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
9594 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
9596 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
9597 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
9599 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
9600 /* Do nothing here. The first PHY won't be initialized at all */
9602 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
9603 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
9607 if (params->phy[ELINK_EXT_PHY2].req_line_speed == ELINK_SPEED_1000)
9608 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
9610 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
9611 MDIO_CTL_REG_84823_MEDIA, val);
9612 PMD_DRV_LOG(DEBUG, sc, "Multi_phy config = 0x%x, Media control = 0x%x",
9613 params->multi_phy_config, val);
9615 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||
9616 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) {
9617 elink_84833_pair_swap_cfg(phy, params, vars);
9619 /* Keep AutogrEEEn disabled. */
9622 cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1;
9623 cmd_args[3] = PHY84833_CONSTANT_LATENCY;
9624 rc = elink_84833_cmd_hdlr(phy, params,
9625 PHY84833_CMD_SET_EEE_MODE, cmd_args,
9626 PHY84833_CMDHDLR_MAX_ARGS);
9627 if (rc != ELINK_STATUS_OK) {
9628 PMD_DRV_LOG(DEBUG, sc, "Cfg AutogrEEEn failed.");
9632 rc = elink_848xx_cmn_config_init(phy, params, vars);
9634 elink_save_848xx_spirom_version(phy, sc, params->port);
9636 /* 84833 PHY has a better feature and doesn't need to support this. */
9637 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823) {
9638 uint32_t cms_enable = REG_RD(sc, params->shmem_base +
9639 offsetof(struct shmem_region,
9641 port_hw_config[params->
9644 PORT_HW_CFG_ENABLE_CMS_MASK;
9646 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
9647 MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
9649 val |= MDIO_CTL_REG_84823_USER_CTRL_CMS;
9651 val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS;
9652 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
9653 MDIO_CTL_REG_84823_USER_CTRL_REG, val);
9656 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
9657 MDIO_84833_TOP_CFG_FW_REV, &val);
9659 /* Configure EEE support */
9660 if ((val >= MDIO_84833_TOP_CFG_FW_EEE) &&
9661 (val != MDIO_84833_TOP_CFG_FW_NO_EEE) &&
9662 elink_eee_has_cap(params)) {
9663 rc = elink_eee_initial_config(params, vars, SHMEM_EEE_10G_ADV);
9664 if (rc != ELINK_STATUS_OK) {
9665 PMD_DRV_LOG(DEBUG, sc, "Failed to configure EEE timers");
9666 elink_8483x_disable_eee(phy, params, vars);
9670 if ((phy->req_duplex == DUPLEX_FULL) &&
9671 (params->eee_mode & ELINK_EEE_MODE_ADV_LPI) &&
9672 (elink_eee_calc_timer(params) ||
9673 !(params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI)))
9674 rc = elink_8483x_enable_eee(phy, params, vars);
9676 rc = elink_8483x_disable_eee(phy, params, vars);
9677 if (rc != ELINK_STATUS_OK) {
9678 PMD_DRV_LOG(DEBUG, sc, "Failed to set EEE advertisement");
9682 vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK;
9685 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||
9686 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) {
9687 /* Bring PHY out of super isolate mode as the final step. */
9688 elink_cl45_read_and_write(sc, phy,
9690 MDIO_84833_TOP_CFG_XGPHY_STRAP1,
9692 MDIO_84833_SUPER_ISOLATE);
9697 static uint8_t elink_848xx_read_status(struct elink_phy *phy,
9698 struct elink_params *params,
9699 struct elink_vars *vars)
9701 struct bnx2x_softc *sc = params->sc;
9702 uint16_t val, val1, val2;
9703 uint8_t link_up = 0;
9705 /* Check 10G-BaseT link status */
9706 /* Check PMD signal ok */
9707 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, 0xFFFA, &val1);
9708 elink_cl45_read(sc, phy,
9709 MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL, &val2);
9710 PMD_DRV_LOG(DEBUG, sc, "BNX2X848xx: PMD_SIGNAL 1.a811 = 0x%x", val2);
9712 /* Check link 10G */
9713 if (val2 & (1 << 11)) {
9714 vars->line_speed = ELINK_SPEED_10000;
9715 vars->duplex = DUPLEX_FULL;
9717 elink_ext_phy_10G_an_resolve(sc, phy, vars);
9718 } else { /* Check Legacy speed link */
9719 uint16_t legacy_status, legacy_speed, mii_ctrl;
9721 /* Enable expansion register 0x42 (Operation mode status) */
9722 elink_cl45_write(sc, phy,
9724 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
9726 /* Get legacy speed operation status */
9727 elink_cl45_read(sc, phy,
9729 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
9732 PMD_DRV_LOG(DEBUG, sc,
9733 "Legacy speed status = 0x%x", legacy_status);
9734 link_up = ((legacy_status & (1 << 11)) == (1 << 11));
9735 legacy_speed = (legacy_status & (3 << 9));
9736 if (legacy_speed == (0 << 9))
9737 vars->line_speed = ELINK_SPEED_10;
9738 else if (legacy_speed == (1 << 9))
9739 vars->line_speed = ELINK_SPEED_100;
9740 else if (legacy_speed == (2 << 9))
9741 vars->line_speed = ELINK_SPEED_1000;
9742 else { /* Should not happen: Treat as link down */
9743 vars->line_speed = 0;
9747 if (params->feature_config_flags &
9748 ELINK_FEATURE_CONFIG_IEEE_PHY_TEST) {
9749 elink_cl45_read(sc, phy,
9751 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9753 /* For IEEE testing, check for a fake link. */
9754 link_up |= ((mii_ctrl & 0x3040) == 0x40);
9758 if (legacy_status & (1 << 8))
9759 vars->duplex = DUPLEX_FULL;
9761 vars->duplex = DUPLEX_HALF;
9763 PMD_DRV_LOG(DEBUG, sc,
9764 "Link is up in %dMbps, is_duplex_full= %d",
9766 (vars->duplex == DUPLEX_FULL));
9767 /* Check legacy speed AN resolution */
9768 elink_cl45_read(sc, phy,
9770 MDIO_AN_REG_8481_LEGACY_MII_STATUS,
9773 vars->link_status |=
9774 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
9775 elink_cl45_read(sc, phy,
9777 MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
9779 if ((val & (1 << 0)) == 0)
9780 vars->link_status |=
9781 LINK_STATUS_PARALLEL_DETECTION_USED;
9785 PMD_DRV_LOG(DEBUG, sc, "BNX2X848x3: link speed is %d",
9787 elink_ext_phy_resolve_fc(phy, params, vars);
9789 /* Read LP advertised speeds */
9790 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
9791 MDIO_AN_REG_CL37_FC_LP, &val);
9793 vars->link_status |=
9794 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
9796 vars->link_status |=
9797 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
9799 vars->link_status |=
9800 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
9802 vars->link_status |=
9803 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
9805 vars->link_status |=
9806 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
9808 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
9809 MDIO_AN_REG_1000T_STATUS, &val);
9811 if (val & (1 << 10))
9812 vars->link_status |=
9813 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
9814 if (val & (1 << 11))
9815 vars->link_status |=
9816 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
9818 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
9819 MDIO_AN_REG_MASTER_STATUS, &val);
9821 if (val & (1 << 11))
9822 vars->link_status |=
9823 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
9825 /* Determine if EEE was negotiated */
9826 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||
9827 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834))
9828 elink_eee_an_resolve(phy, params, vars);
9834 static uint8_t elink_848xx_format_ver(uint32_t raw_ver, uint8_t * str,
9837 elink_status_t status = ELINK_STATUS_OK;
9838 uint32_t spirom_ver;
9839 spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
9840 status = elink_format_ver(spirom_ver, str, len);
9844 static void elink_8481_hw_reset(__rte_unused struct elink_phy *phy,
9845 struct elink_params *params)
9847 elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1,
9848 MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
9849 elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1,
9850 MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
9853 static void elink_8481_link_reset(struct elink_phy *phy,
9854 struct elink_params *params)
9856 elink_cl45_write(params->sc, phy,
9857 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
9858 elink_cl45_write(params->sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
9861 static void elink_848x3_link_reset(struct elink_phy *phy,
9862 struct elink_params *params)
9864 struct bnx2x_softc *sc = params->sc;
9868 if (!(CHIP_IS_E1x(sc)))
9871 port = params->port;
9873 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823) {
9874 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_3,
9875 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
9877 elink_cl45_read(sc, phy,
9879 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16);
9880 val16 |= MDIO_84833_SUPER_ISOLATE;
9881 elink_cl45_write(sc, phy,
9883 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16);
9887 static void elink_848xx_set_link_led(struct elink_phy *phy,
9888 struct elink_params *params, uint8_t mode)
9890 struct bnx2x_softc *sc = params->sc;
9892 __rte_unused uint8_t port;
9894 if (!(CHIP_IS_E1x(sc)))
9897 port = params->port;
9900 case ELINK_LED_MODE_OFF:
9902 PMD_DRV_LOG(DEBUG, sc, "Port 0x%x: LED MODE OFF", port);
9904 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9905 SHARED_HW_CFG_LED_EXTPHY1) {
9908 elink_cl45_write(sc, phy,
9910 MDIO_PMA_REG_8481_LED1_MASK, 0x0);
9912 elink_cl45_write(sc, phy,
9914 MDIO_PMA_REG_8481_LED2_MASK, 0x0);
9916 elink_cl45_write(sc, phy,
9918 MDIO_PMA_REG_8481_LED3_MASK, 0x0);
9920 elink_cl45_write(sc, phy,
9922 MDIO_PMA_REG_8481_LED5_MASK, 0x0);
9925 elink_cl45_write(sc, phy,
9927 MDIO_PMA_REG_8481_LED1_MASK, 0x0);
9930 case ELINK_LED_MODE_FRONT_PANEL_OFF:
9932 PMD_DRV_LOG(DEBUG, sc,
9933 "Port 0x%x: LED MODE FRONT PANEL OFF", port);
9935 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9936 SHARED_HW_CFG_LED_EXTPHY1) {
9939 elink_cl45_write(sc, phy,
9941 MDIO_PMA_REG_8481_LED1_MASK, 0x0);
9943 elink_cl45_write(sc, phy,
9945 MDIO_PMA_REG_8481_LED2_MASK, 0x0);
9947 elink_cl45_write(sc, phy,
9949 MDIO_PMA_REG_8481_LED3_MASK, 0x0);
9951 elink_cl45_write(sc, phy,
9953 MDIO_PMA_REG_8481_LED5_MASK, 0x20);
9956 elink_cl45_write(sc, phy,
9958 MDIO_PMA_REG_8481_LED1_MASK, 0x0);
9959 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834) {
9960 /* Disable MI_INT interrupt before setting LED4
9961 * source to constant off.
9963 if (REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 +
9965 ELINK_NIG_MASK_MI_INT) {
9966 params->link_flags |=
9967 ELINK_LINK_FLAGS_INT_DISABLED;
9970 NIG_REG_MASK_INTERRUPT_PORT0
9972 ELINK_NIG_MASK_MI_INT);
9974 elink_cl45_write(sc, phy,
9976 MDIO_PMA_REG_8481_SIGNAL_MASK,
9981 case ELINK_LED_MODE_ON:
9983 PMD_DRV_LOG(DEBUG, sc, "Port 0x%x: LED MODE ON", port);
9985 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9986 SHARED_HW_CFG_LED_EXTPHY1) {
9987 /* Set control reg */
9988 elink_cl45_read(sc, phy,
9990 MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
9994 elink_cl45_write(sc, phy,
9996 MDIO_PMA_REG_8481_LINK_SIGNAL, val);
9999 elink_cl45_write(sc, phy,
10001 MDIO_PMA_REG_8481_LED1_MASK, 0x0);
10003 elink_cl45_write(sc, phy,
10005 MDIO_PMA_REG_8481_LED2_MASK, 0x20);
10007 elink_cl45_write(sc, phy,
10009 MDIO_PMA_REG_8481_LED3_MASK, 0x20);
10011 elink_cl45_write(sc, phy,
10013 MDIO_PMA_REG_8481_LED5_MASK, 0x0);
10015 elink_cl45_write(sc, phy,
10017 MDIO_PMA_REG_8481_LED1_MASK, 0x20);
10018 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834) {
10019 /* Disable MI_INT interrupt before setting LED4
10020 * source to constant on.
10022 if (REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 +
10023 params->port * 4) &
10024 ELINK_NIG_MASK_MI_INT) {
10025 params->link_flags |=
10026 ELINK_LINK_FLAGS_INT_DISABLED;
10029 NIG_REG_MASK_INTERRUPT_PORT0
10030 + params->port * 4,
10031 ELINK_NIG_MASK_MI_INT);
10033 elink_cl45_write(sc, phy,
10035 MDIO_PMA_REG_8481_SIGNAL_MASK,
10041 case ELINK_LED_MODE_OPER:
10043 PMD_DRV_LOG(DEBUG, sc, "Port 0x%x: LED MODE OPER", port);
10045 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10046 SHARED_HW_CFG_LED_EXTPHY1) {
10048 /* Set control reg */
10049 elink_cl45_read(sc, phy,
10051 MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
10054 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
10056 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT))
10058 PMD_DRV_LOG(DEBUG, sc, "Setting LINK_SIGNAL");
10059 elink_cl45_write(sc, phy,
10061 MDIO_PMA_REG_8481_LINK_SIGNAL,
10065 /* Set LED masks */
10066 elink_cl45_write(sc, phy,
10068 MDIO_PMA_REG_8481_LED1_MASK, 0x10);
10070 elink_cl45_write(sc, phy,
10072 MDIO_PMA_REG_8481_LED2_MASK, 0x80);
10074 elink_cl45_write(sc, phy,
10076 MDIO_PMA_REG_8481_LED3_MASK, 0x98);
10078 elink_cl45_write(sc, phy,
10080 MDIO_PMA_REG_8481_LED5_MASK, 0x40);
10083 /* EXTPHY2 LED mode indicate that the 100M/1G/10G LED
10084 * sources are all wired through LED1, rather than only
10085 * 10G in other modes.
10087 val = ((params->hw_led_mode <<
10088 SHARED_HW_CFG_LED_MODE_SHIFT) ==
10089 SHARED_HW_CFG_LED_EXTPHY2) ? 0x98 : 0x80;
10091 elink_cl45_write(sc, phy,
10093 MDIO_PMA_REG_8481_LED1_MASK, val);
10095 /* Tell LED3 to blink on source */
10096 elink_cl45_read(sc, phy,
10098 MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
10100 val |= (1 << 6); /* A83B[8:6]= 1 */
10101 elink_cl45_write(sc, phy,
10103 MDIO_PMA_REG_8481_LINK_SIGNAL, val);
10104 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834) {
10105 /* Restore LED4 source to external link,
10106 * and re-enable interrupts.
10108 elink_cl45_write(sc, phy,
10110 MDIO_PMA_REG_8481_SIGNAL_MASK,
10112 if (params->link_flags &
10113 ELINK_LINK_FLAGS_INT_DISABLED) {
10114 elink_link_int_enable(params);
10115 params->link_flags &=
10116 ~ELINK_LINK_FLAGS_INT_DISABLED;
10123 /* This is a workaround for E3+84833 until autoneg
10124 * restart is fixed in f/w
10126 if (CHIP_IS_E3(sc)) {
10127 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
10128 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val);
10132 /******************************************************************/
10133 /* 54618SE PHY SECTION */
10134 /******************************************************************/
10135 static void elink_54618se_specific_func(struct elink_phy *phy,
10136 struct elink_params *params,
10139 struct bnx2x_softc *sc = params->sc;
10142 case ELINK_PHY_INIT:
10143 /* Configure LED4: set to INTR (0x6). */
10144 /* Accessing shadow register 0xe. */
10145 elink_cl22_write(sc, phy,
10146 MDIO_REG_GPHY_SHADOW,
10147 MDIO_REG_GPHY_SHADOW_LED_SEL2);
10148 elink_cl22_read(sc, phy, MDIO_REG_GPHY_SHADOW, &temp);
10149 temp &= ~(0xf << 4);
10150 temp |= (0x6 << 4);
10151 elink_cl22_write(sc, phy,
10152 MDIO_REG_GPHY_SHADOW,
10153 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10154 /* Configure INTR based on link status change. */
10155 elink_cl22_write(sc, phy,
10156 MDIO_REG_INTR_MASK,
10157 ~MDIO_REG_INTR_MASK_LINK_STATUS);
10162 static uint8_t elink_54618se_config_init(struct elink_phy *phy,
10163 struct elink_params *params,
10164 struct elink_vars *vars)
10166 struct bnx2x_softc *sc = params->sc;
10168 uint16_t autoneg_val, an_1000_val, an_10_100_val, fc_val, temp;
10171 PMD_DRV_LOG(DEBUG, sc, "54618SE cfg init");
10174 /* This works with E3 only, no need to check the chip
10175 * before determining the port.
10177 port = params->port;
10179 cfg_pin = (REG_RD(sc, params->shmem_base +
10180 offsetof(struct shmem_region,
10181 dev_info.port_hw_config[port].
10183 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10184 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10186 /* Drive pin high to bring the GPHY out of reset. */
10187 elink_set_cfg_pin(sc, cfg_pin, 1);
10189 /* wait for GPHY to reset */
10193 elink_cl22_write(sc, phy, MDIO_PMA_REG_CTRL, 0x8000);
10194 elink_wait_reset_complete(sc, phy, params);
10196 /* Wait for GPHY to reset */
10199 elink_54618se_specific_func(phy, params, ELINK_PHY_INIT);
10200 /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
10201 elink_cl22_write(sc, phy,
10202 MDIO_REG_GPHY_SHADOW,
10203 MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
10204 elink_cl22_read(sc, phy, MDIO_REG_GPHY_SHADOW, &temp);
10205 temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD;
10206 elink_cl22_write(sc, phy,
10207 MDIO_REG_GPHY_SHADOW,
10208 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10211 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
10212 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
10214 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
10215 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
10216 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
10218 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
10219 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
10220 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
10222 /* Read all advertisement */
10223 elink_cl22_read(sc, phy, 0x09, &an_1000_val);
10225 elink_cl22_read(sc, phy, 0x04, &an_10_100_val);
10227 elink_cl22_read(sc, phy, MDIO_PMA_REG_CTRL, &autoneg_val);
10229 /* Disable forced speed */
10231 ~((1 << 6) | (1 << 8) | (1 << 9) | (1 << 12) | (1 << 13));
10233 ~((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 10) |
10236 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
10237 (phy->speed_cap_mask &
10238 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
10239 (phy->req_line_speed == ELINK_SPEED_1000)) {
10240 an_1000_val |= (1 << 8);
10241 autoneg_val |= (1 << 9 | 1 << 12);
10242 if (phy->req_duplex == DUPLEX_FULL)
10243 an_1000_val |= (1 << 9);
10244 PMD_DRV_LOG(DEBUG, sc, "Advertising 1G");
10246 an_1000_val &= ~((1 << 8) | (1 << 9));
10248 elink_cl22_write(sc, phy, 0x09, an_1000_val);
10249 elink_cl22_read(sc, phy, 0x09, &an_1000_val);
10251 /* Advertise 10/100 link speed */
10252 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {
10253 if (phy->speed_cap_mask &
10254 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) {
10255 an_10_100_val |= (1 << 5);
10256 autoneg_val |= (1 << 9 | 1 << 12);
10257 PMD_DRV_LOG(DEBUG, sc, "Advertising 10M-HD");
10259 if (phy->speed_cap_mask &
10260 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) {
10261 an_10_100_val |= (1 << 6);
10262 autoneg_val |= (1 << 9 | 1 << 12);
10263 PMD_DRV_LOG(DEBUG, sc, "Advertising 10M-FD");
10265 if (phy->speed_cap_mask &
10266 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) {
10267 an_10_100_val |= (1 << 7);
10268 autoneg_val |= (1 << 9 | 1 << 12);
10269 PMD_DRV_LOG(DEBUG, sc, "Advertising 100M-HD");
10271 if (phy->speed_cap_mask &
10272 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) {
10273 an_10_100_val |= (1 << 8);
10274 autoneg_val |= (1 << 9 | 1 << 12);
10275 PMD_DRV_LOG(DEBUG, sc, "Advertising 100M-FD");
10279 /* Only 10/100 are allowed to work in FORCE mode */
10280 if (phy->req_line_speed == ELINK_SPEED_100) {
10281 autoneg_val |= (1 << 13);
10282 /* Enabled AUTO-MDIX when autoneg is disabled */
10283 elink_cl22_write(sc, phy, 0x18, (1 << 15 | 1 << 9 | 7 << 0));
10284 PMD_DRV_LOG(DEBUG, sc, "Setting 100M force");
10286 if (phy->req_line_speed == ELINK_SPEED_10) {
10287 /* Enabled AUTO-MDIX when autoneg is disabled */
10288 elink_cl22_write(sc, phy, 0x18, (1 << 15 | 1 << 9 | 7 << 0));
10289 PMD_DRV_LOG(DEBUG, sc, "Setting 10M force");
10292 if ((phy->flags & ELINK_FLAGS_EEE) && elink_eee_has_cap(params)) {
10295 elink_cl22_write(sc, phy, MDIO_REG_GPHY_EXP_ACCESS,
10296 MDIO_REG_GPHY_EXP_ACCESS_TOP |
10297 MDIO_REG_GPHY_EXP_TOP_2K_BUF);
10298 elink_cl22_read(sc, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp);
10300 elink_cl22_write(sc, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp);
10302 rc = elink_eee_initial_config(params, vars, SHMEM_EEE_1G_ADV);
10303 if (rc != ELINK_STATUS_OK) {
10304 PMD_DRV_LOG(DEBUG, sc, "Failed to configure EEE timers");
10305 elink_eee_disable(phy, params, vars);
10306 } else if ((params->eee_mode & ELINK_EEE_MODE_ADV_LPI) &&
10307 (phy->req_duplex == DUPLEX_FULL) &&
10308 (elink_eee_calc_timer(params) ||
10309 !(params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI))) {
10310 /* Need to advertise EEE only when requested,
10311 * and either no LPI assertion was requested,
10312 * or it was requested and a valid timer was set.
10313 * Also notice full duplex is required for EEE.
10315 elink_eee_advertise(phy, params, vars,
10318 PMD_DRV_LOG(DEBUG, sc, "Don't Advertise 1GBase-T EEE");
10319 elink_eee_disable(phy, params, vars);
10322 vars->eee_status &= ~SHMEM_EEE_1G_ADV <<
10323 SHMEM_EEE_SUPPORTED_SHIFT;
10325 if (phy->flags & ELINK_FLAGS_EEE) {
10326 /* Handle legacy auto-grEEEn */
10327 if (params->feature_config_flags &
10328 ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
10330 PMD_DRV_LOG(DEBUG, sc, "Enabling Auto-GrEEEn");
10333 PMD_DRV_LOG(DEBUG, sc, "Don't Adv. EEE");
10335 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
10336 MDIO_AN_REG_EEE_ADV, temp);
10340 elink_cl22_write(sc, phy, 0x04, an_10_100_val | fc_val);
10342 if (phy->req_duplex == DUPLEX_FULL)
10343 autoneg_val |= (1 << 8);
10345 elink_cl22_write(sc, phy, MDIO_PMA_REG_CTRL, autoneg_val);
10347 return ELINK_STATUS_OK;
10350 static void elink_5461x_set_link_led(struct elink_phy *phy,
10351 struct elink_params *params, uint8_t mode)
10353 struct bnx2x_softc *sc = params->sc;
10356 elink_cl22_write(sc, phy,
10357 MDIO_REG_GPHY_SHADOW, MDIO_REG_GPHY_SHADOW_LED_SEL1);
10358 elink_cl22_read(sc, phy, MDIO_REG_GPHY_SHADOW, &temp);
10361 PMD_DRV_LOG(DEBUG, sc, "54618x set link led (mode=%x)", mode);
10363 case ELINK_LED_MODE_FRONT_PANEL_OFF:
10364 case ELINK_LED_MODE_OFF:
10367 case ELINK_LED_MODE_OPER:
10370 case ELINK_LED_MODE_ON:
10376 elink_cl22_write(sc, phy,
10377 MDIO_REG_GPHY_SHADOW,
10378 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10382 static void elink_54618se_link_reset(struct elink_phy *phy,
10383 struct elink_params *params)
10385 struct bnx2x_softc *sc = params->sc;
10389 /* In case of no EPIO routed to reset the GPHY, put it
10390 * in low power mode.
10392 elink_cl22_write(sc, phy, MDIO_PMA_REG_CTRL, 0x800);
10393 /* This works with E3 only, no need to check the chip
10394 * before determining the port.
10396 port = params->port;
10397 cfg_pin = (REG_RD(sc, params->shmem_base +
10398 offsetof(struct shmem_region,
10399 dev_info.port_hw_config[port].
10401 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10402 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10404 /* Drive pin low to put GPHY in reset. */
10405 elink_set_cfg_pin(sc, cfg_pin, 0);
10408 static uint8_t elink_54618se_read_status(struct elink_phy *phy,
10409 struct elink_params *params,
10410 struct elink_vars *vars)
10412 struct bnx2x_softc *sc = params->sc;
10414 uint8_t link_up = 0;
10415 uint16_t legacy_status, legacy_speed;
10417 /* Get speed operation status */
10418 elink_cl22_read(sc, phy, MDIO_REG_GPHY_AUX_STATUS, &legacy_status);
10419 PMD_DRV_LOG(DEBUG, sc, "54618SE read_status: 0x%x", legacy_status);
10421 /* Read status to clear the PHY interrupt. */
10422 elink_cl22_read(sc, phy, MDIO_REG_INTR_STATUS, &val);
10424 link_up = ((legacy_status & (1 << 2)) == (1 << 2));
10427 legacy_speed = (legacy_status & (7 << 8));
10428 if (legacy_speed == (7 << 8)) {
10429 vars->line_speed = ELINK_SPEED_1000;
10430 vars->duplex = DUPLEX_FULL;
10431 } else if (legacy_speed == (6 << 8)) {
10432 vars->line_speed = ELINK_SPEED_1000;
10433 vars->duplex = DUPLEX_HALF;
10434 } else if (legacy_speed == (5 << 8)) {
10435 vars->line_speed = ELINK_SPEED_100;
10436 vars->duplex = DUPLEX_FULL;
10438 /* Omitting 100Base-T4 for now */
10439 else if (legacy_speed == (3 << 8)) {
10440 vars->line_speed = ELINK_SPEED_100;
10441 vars->duplex = DUPLEX_HALF;
10442 } else if (legacy_speed == (2 << 8)) {
10443 vars->line_speed = ELINK_SPEED_10;
10444 vars->duplex = DUPLEX_FULL;
10445 } else if (legacy_speed == (1 << 8)) {
10446 vars->line_speed = ELINK_SPEED_10;
10447 vars->duplex = DUPLEX_HALF;
10448 } else /* Should not happen */
10449 vars->line_speed = 0;
10451 PMD_DRV_LOG(DEBUG, sc,
10452 "Link is up in %dMbps, is_duplex_full= %d",
10453 vars->line_speed, (vars->duplex == DUPLEX_FULL));
10455 /* Check legacy speed AN resolution */
10456 elink_cl22_read(sc, phy, 0x01, &val);
10457 if (val & (1 << 5))
10458 vars->link_status |=
10459 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10460 elink_cl22_read(sc, phy, 0x06, &val);
10461 if ((val & (1 << 0)) == 0)
10462 vars->link_status |=
10463 LINK_STATUS_PARALLEL_DETECTION_USED;
10465 PMD_DRV_LOG(DEBUG, sc, "BNX2X54618SE: link speed is %d",
10468 elink_ext_phy_resolve_fc(phy, params, vars);
10470 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
10471 /* Report LP advertised speeds */
10472 elink_cl22_read(sc, phy, 0x5, &val);
10474 if (val & (1 << 5))
10475 vars->link_status |=
10476 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
10477 if (val & (1 << 6))
10478 vars->link_status |=
10479 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
10480 if (val & (1 << 7))
10481 vars->link_status |=
10482 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
10483 if (val & (1 << 8))
10484 vars->link_status |=
10485 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
10486 if (val & (1 << 9))
10487 vars->link_status |=
10488 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
10490 elink_cl22_read(sc, phy, 0xa, &val);
10491 if (val & (1 << 10))
10492 vars->link_status |=
10493 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
10494 if (val & (1 << 11))
10495 vars->link_status |=
10496 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
10498 if ((phy->flags & ELINK_FLAGS_EEE) &&
10499 elink_eee_has_cap(params))
10500 elink_eee_an_resolve(phy, params, vars);
10506 static void elink_54618se_config_loopback(struct elink_phy *phy,
10507 struct elink_params *params)
10509 struct bnx2x_softc *sc = params->sc;
10511 uint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
10513 PMD_DRV_LOG(DEBUG, sc, "2PMA/PMD ext_phy_loopback: 54618se");
10515 /* Enable master/slave manual mmode and set to master */
10516 /* mii write 9 [bits set 11 12] */
10517 elink_cl22_write(sc, phy, 0x09, 3 << 11);
10519 /* forced 1G and disable autoneg */
10520 /* set val [mii read 0] */
10521 /* set val [expr $val & [bits clear 6 12 13]] */
10522 /* set val [expr $val | [bits set 6 8]] */
10523 /* mii write 0 $val */
10524 elink_cl22_read(sc, phy, 0x00, &val);
10525 val &= ~((1 << 6) | (1 << 12) | (1 << 13));
10526 val |= (1 << 6) | (1 << 8);
10527 elink_cl22_write(sc, phy, 0x00, val);
10529 /* Set external loopback and Tx using 6dB coding */
10530 /* mii write 0x18 7 */
10531 /* set val [mii read 0x18] */
10532 /* mii write 0x18 [expr $val | [bits set 10 15]] */
10533 elink_cl22_write(sc, phy, 0x18, 7);
10534 elink_cl22_read(sc, phy, 0x18, &val);
10535 elink_cl22_write(sc, phy, 0x18, val | (1 << 10) | (1 << 15));
10537 /* This register opens the gate for the UMAC despite its name */
10538 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port * 4, 1);
10540 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
10541 * length used by the MAC receive logic to check frames.
10543 REG_WR(sc, umac_base + UMAC_REG_MAXFR, 0x2710);
10546 /******************************************************************/
10547 /* SFX7101 PHY SECTION */
10548 /******************************************************************/
10549 static void elink_7101_config_loopback(struct elink_phy *phy,
10550 struct elink_params *params)
10552 struct bnx2x_softc *sc = params->sc;
10553 /* SFX7101_XGXS_TEST1 */
10554 elink_cl45_write(sc, phy,
10555 MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
10558 static uint8_t elink_7101_config_init(struct elink_phy *phy,
10559 struct elink_params *params,
10560 struct elink_vars *vars)
10562 uint16_t fw_ver1, fw_ver2, val;
10563 struct bnx2x_softc *sc = params->sc;
10564 PMD_DRV_LOG(DEBUG, sc, "Setting the SFX7101 LASI indication");
10566 /* Restore normal power mode */
10567 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
10568 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
10570 elink_ext_phy_hw_reset(sc, params->port);
10571 elink_wait_reset_complete(sc, phy, params);
10573 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1);
10574 PMD_DRV_LOG(DEBUG, sc, "Setting the SFX7101 LED to blink on traffic");
10575 elink_cl45_write(sc, phy,
10576 MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1 << 3));
10578 elink_ext_phy_set_pause(params, phy, vars);
10579 /* Restart autoneg */
10580 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
10582 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
10584 /* Save spirom version */
10585 elink_cl45_read(sc, phy,
10586 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
10588 elink_cl45_read(sc, phy,
10589 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
10590 elink_save_spirom_version(sc, params->port,
10591 (uint32_t) (fw_ver1 << 16 | fw_ver2),
10593 return ELINK_STATUS_OK;
10596 static uint8_t elink_7101_read_status(struct elink_phy *phy,
10597 struct elink_params *params,
10598 struct elink_vars *vars)
10600 struct bnx2x_softc *sc = params->sc;
10602 uint16_t val1, val2;
10603 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
10604 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
10605 PMD_DRV_LOG(DEBUG, sc, "10G-base-T LASI status 0x%x->0x%x", val2, val1);
10606 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
10607 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
10608 PMD_DRV_LOG(DEBUG, sc, "10G-base-T PMA status 0x%x->0x%x", val2, val1);
10609 link_up = ((val1 & 4) == 4);
10610 /* If link is up print the AN outcome of the SFX7101 PHY */
10612 elink_cl45_read(sc, phy,
10613 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
10615 vars->line_speed = ELINK_SPEED_10000;
10616 vars->duplex = DUPLEX_FULL;
10617 PMD_DRV_LOG(DEBUG, sc, "SFX7101 AN status 0x%x->Master=%x",
10618 val2, (val2 & (1 << 14)));
10619 elink_ext_phy_10G_an_resolve(sc, phy, vars);
10620 elink_ext_phy_resolve_fc(phy, params, vars);
10622 /* Read LP advertised speeds */
10623 if (val2 & (1 << 11))
10624 vars->link_status |=
10625 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
10630 static uint8_t elink_7101_format_ver(uint32_t spirom_ver, uint8_t * str,
10634 return ELINK_STATUS_ERROR;
10635 str[0] = (spirom_ver & 0xFF);
10636 str[1] = (spirom_ver & 0xFF00) >> 8;
10637 str[2] = (spirom_ver & 0xFF0000) >> 16;
10638 str[3] = (spirom_ver & 0xFF000000) >> 24;
10641 return ELINK_STATUS_OK;
10644 static void elink_7101_hw_reset(__rte_unused struct elink_phy *phy,
10645 struct elink_params *params)
10647 /* Low power mode is controlled by GPIO 2 */
10648 elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_2,
10649 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
10650 /* The PHY reset is controlled by GPIO 1 */
10651 elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1,
10652 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
10655 static void elink_7101_set_link_led(struct elink_phy *phy,
10656 struct elink_params *params, uint8_t mode)
10659 struct bnx2x_softc *sc = params->sc;
10661 case ELINK_LED_MODE_FRONT_PANEL_OFF:
10662 case ELINK_LED_MODE_OFF:
10665 case ELINK_LED_MODE_ON:
10668 case ELINK_LED_MODE_OPER:
10672 elink_cl45_write(sc, phy,
10673 MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LINK_LED_CNTL, val);
10676 /******************************************************************/
10677 /* STATIC PHY DECLARATION */
10678 /******************************************************************/
10680 static const struct elink_phy phy_null = {
10681 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
10684 .flags = ELINK_FLAGS_INIT_XGXS_FIRST,
10685 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10686 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10689 .media_type = ELINK_ETH_PHY_NOT_PRESENT,
10691 .req_flow_ctrl = 0,
10692 .req_line_speed = 0,
10693 .speed_cap_mask = 0,
10696 .config_init = NULL,
10697 .read_status = NULL,
10698 .link_reset = NULL,
10699 .config_loopback = NULL,
10700 .format_fw_ver = NULL,
10702 .set_link_led = NULL,
10703 .phy_specific_func = NULL
10706 static const struct elink_phy phy_serdes = {
10707 .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
10711 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10712 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10714 .supported = (ELINK_SUPPORTED_10baseT_Half |
10715 ELINK_SUPPORTED_10baseT_Full |
10716 ELINK_SUPPORTED_100baseT_Half |
10717 ELINK_SUPPORTED_100baseT_Full |
10718 ELINK_SUPPORTED_1000baseT_Full |
10719 ELINK_SUPPORTED_2500baseX_Full |
10720 ELINK_SUPPORTED_TP |
10721 ELINK_SUPPORTED_Autoneg |
10722 ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
10723 .media_type = ELINK_ETH_PHY_BASE_T,
10725 .req_flow_ctrl = 0,
10726 .req_line_speed = 0,
10727 .speed_cap_mask = 0,
10730 .config_init = elink_xgxs_config_init,
10731 .read_status = elink_link_settings_status,
10732 .link_reset = elink_int_link_reset,
10733 .config_loopback = NULL,
10734 .format_fw_ver = NULL,
10736 .set_link_led = NULL,
10737 .phy_specific_func = NULL
10740 static const struct elink_phy phy_xgxs = {
10741 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
10745 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10746 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10748 .supported = (ELINK_SUPPORTED_10baseT_Half |
10749 ELINK_SUPPORTED_10baseT_Full |
10750 ELINK_SUPPORTED_100baseT_Half |
10751 ELINK_SUPPORTED_100baseT_Full |
10752 ELINK_SUPPORTED_1000baseT_Full |
10753 ELINK_SUPPORTED_2500baseX_Full |
10754 ELINK_SUPPORTED_10000baseT_Full |
10755 ELINK_SUPPORTED_FIBRE |
10756 ELINK_SUPPORTED_Autoneg |
10757 ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
10758 .media_type = ELINK_ETH_PHY_CX4,
10760 .req_flow_ctrl = 0,
10761 .req_line_speed = 0,
10762 .speed_cap_mask = 0,
10765 .config_init = elink_xgxs_config_init,
10766 .read_status = elink_link_settings_status,
10767 .link_reset = elink_int_link_reset,
10768 .config_loopback = elink_set_xgxs_loopback,
10769 .format_fw_ver = NULL,
10771 .set_link_led = NULL,
10772 .phy_specific_func = elink_xgxs_specific_func
10775 static const struct elink_phy phy_warpcore = {
10776 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
10779 .flags = ELINK_FLAGS_TX_ERROR_CHECK,
10780 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10781 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10783 .supported = (ELINK_SUPPORTED_10baseT_Half |
10784 ELINK_SUPPORTED_10baseT_Full |
10785 ELINK_SUPPORTED_100baseT_Half |
10786 ELINK_SUPPORTED_100baseT_Full |
10787 ELINK_SUPPORTED_1000baseT_Full |
10788 ELINK_SUPPORTED_10000baseT_Full |
10789 ELINK_SUPPORTED_20000baseKR2_Full |
10790 ELINK_SUPPORTED_20000baseMLD2_Full |
10791 ELINK_SUPPORTED_FIBRE |
10792 ELINK_SUPPORTED_Autoneg |
10793 ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
10794 .media_type = ELINK_ETH_PHY_UNSPECIFIED,
10796 .req_flow_ctrl = 0,
10797 .req_line_speed = 0,
10798 .speed_cap_mask = 0,
10799 /* req_duplex = */ 0,
10801 .config_init = elink_warpcore_config_init,
10802 .read_status = elink_warpcore_read_status,
10803 .link_reset = elink_warpcore_link_reset,
10804 .config_loopback = elink_set_warpcore_loopback,
10805 .format_fw_ver = NULL,
10806 .hw_reset = elink_warpcore_hw_reset,
10807 .set_link_led = NULL,
10808 .phy_specific_func = NULL
10811 static const struct elink_phy phy_7101 = {
10812 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
10815 .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ,
10816 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10817 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10819 .supported = (ELINK_SUPPORTED_10000baseT_Full |
10820 ELINK_SUPPORTED_TP |
10821 ELINK_SUPPORTED_Autoneg |
10822 ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
10823 .media_type = ELINK_ETH_PHY_BASE_T,
10825 .req_flow_ctrl = 0,
10826 .req_line_speed = 0,
10827 .speed_cap_mask = 0,
10830 .config_init = elink_7101_config_init,
10831 .read_status = elink_7101_read_status,
10832 .link_reset = elink_common_ext_link_reset,
10833 .config_loopback = elink_7101_config_loopback,
10834 .format_fw_ver = elink_7101_format_ver,
10835 .hw_reset = elink_7101_hw_reset,
10836 .set_link_led = elink_7101_set_link_led,
10837 .phy_specific_func = NULL
10840 static const struct elink_phy phy_8073 = {
10841 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073,
10845 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10846 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10848 .supported = (ELINK_SUPPORTED_10000baseT_Full |
10849 ELINK_SUPPORTED_2500baseX_Full |
10850 ELINK_SUPPORTED_1000baseT_Full |
10851 ELINK_SUPPORTED_FIBRE |
10852 ELINK_SUPPORTED_Autoneg |
10853 ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
10854 .media_type = ELINK_ETH_PHY_KR,
10856 .req_flow_ctrl = 0,
10857 .req_line_speed = 0,
10858 .speed_cap_mask = 0,
10861 .config_init = elink_8073_config_init,
10862 .read_status = elink_8073_read_status,
10863 .link_reset = elink_8073_link_reset,
10864 .config_loopback = NULL,
10865 .format_fw_ver = elink_format_ver,
10867 .set_link_led = NULL,
10868 .phy_specific_func = elink_8073_specific_func
10871 static const struct elink_phy phy_8705 = {
10872 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8705,
10875 .flags = ELINK_FLAGS_INIT_XGXS_FIRST,
10876 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10877 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10879 .supported = (ELINK_SUPPORTED_10000baseT_Full |
10880 ELINK_SUPPORTED_FIBRE |
10881 ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
10882 .media_type = ELINK_ETH_PHY_XFP_FIBER,
10884 .req_flow_ctrl = 0,
10885 .req_line_speed = 0,
10886 .speed_cap_mask = 0,
10889 .config_init = elink_8705_config_init,
10890 .read_status = elink_8705_read_status,
10891 .link_reset = elink_common_ext_link_reset,
10892 .config_loopback = NULL,
10893 .format_fw_ver = elink_null_format_ver,
10895 .set_link_led = NULL,
10896 .phy_specific_func = NULL
10899 static const struct elink_phy phy_8706 = {
10900 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8706,
10903 .flags = ELINK_FLAGS_INIT_XGXS_FIRST,
10904 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10905 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10907 .supported = (ELINK_SUPPORTED_10000baseT_Full |
10908 ELINK_SUPPORTED_1000baseT_Full |
10909 ELINK_SUPPORTED_FIBRE |
10910 ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
10911 .media_type = ELINK_ETH_PHY_SFPP_10G_FIBER,
10913 .req_flow_ctrl = 0,
10914 .req_line_speed = 0,
10915 .speed_cap_mask = 0,
10918 .config_init = elink_8706_config_init,
10919 .read_status = elink_8706_read_status,
10920 .link_reset = elink_common_ext_link_reset,
10921 .config_loopback = NULL,
10922 .format_fw_ver = elink_format_ver,
10924 .set_link_led = NULL,
10925 .phy_specific_func = NULL
10928 static const struct elink_phy phy_8726 = {
10929 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726,
10932 .flags = (ELINK_FLAGS_INIT_XGXS_FIRST | ELINK_FLAGS_TX_ERROR_CHECK),
10933 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10934 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10936 .supported = (ELINK_SUPPORTED_10000baseT_Full |
10937 ELINK_SUPPORTED_1000baseT_Full |
10938 ELINK_SUPPORTED_Autoneg |
10939 ELINK_SUPPORTED_FIBRE |
10940 ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
10941 .media_type = ELINK_ETH_PHY_NOT_PRESENT,
10943 .req_flow_ctrl = 0,
10944 .req_line_speed = 0,
10945 .speed_cap_mask = 0,
10948 .config_init = elink_8726_config_init,
10949 .read_status = elink_8726_read_status,
10950 .link_reset = elink_8726_link_reset,
10951 .config_loopback = elink_8726_config_loopback,
10952 .format_fw_ver = elink_format_ver,
10954 .set_link_led = NULL,
10955 .phy_specific_func = NULL
10958 static const struct elink_phy phy_8727 = {
10959 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727,
10962 .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ | ELINK_FLAGS_TX_ERROR_CHECK),
10963 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10964 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10966 .supported = (ELINK_SUPPORTED_10000baseT_Full |
10967 ELINK_SUPPORTED_1000baseT_Full |
10968 ELINK_SUPPORTED_FIBRE |
10969 ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
10970 .media_type = ELINK_ETH_PHY_NOT_PRESENT,
10972 .req_flow_ctrl = 0,
10973 .req_line_speed = 0,
10974 .speed_cap_mask = 0,
10977 .config_init = elink_8727_config_init,
10978 .read_status = elink_8727_read_status,
10979 .link_reset = elink_8727_link_reset,
10980 .config_loopback = NULL,
10981 .format_fw_ver = elink_format_ver,
10982 .hw_reset = elink_8727_hw_reset,
10983 .set_link_led = elink_8727_set_link_led,
10984 .phy_specific_func = elink_8727_specific_func
10987 static const struct elink_phy phy_8481 = {
10988 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8481,
10991 .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ |
10992 ELINK_FLAGS_REARM_LATCH_SIGNAL,
10993 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10994 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10996 .supported = (ELINK_SUPPORTED_10baseT_Half |
10997 ELINK_SUPPORTED_10baseT_Full |
10998 ELINK_SUPPORTED_100baseT_Half |
10999 ELINK_SUPPORTED_100baseT_Full |
11000 ELINK_SUPPORTED_1000baseT_Full |
11001 ELINK_SUPPORTED_10000baseT_Full |
11002 ELINK_SUPPORTED_TP |
11003 ELINK_SUPPORTED_Autoneg |
11004 ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
11005 .media_type = ELINK_ETH_PHY_BASE_T,
11007 .req_flow_ctrl = 0,
11008 .req_line_speed = 0,
11009 .speed_cap_mask = 0,
11012 .config_init = elink_8481_config_init,
11013 .read_status = elink_848xx_read_status,
11014 .link_reset = elink_8481_link_reset,
11015 .config_loopback = NULL,
11016 .format_fw_ver = elink_848xx_format_ver,
11017 .hw_reset = elink_8481_hw_reset,
11018 .set_link_led = elink_848xx_set_link_led,
11019 .phy_specific_func = NULL
11022 static const struct elink_phy phy_84823 = {
11023 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823,
11026 .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ |
11027 ELINK_FLAGS_REARM_LATCH_SIGNAL | ELINK_FLAGS_TX_ERROR_CHECK),
11028 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11029 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11031 .supported = (ELINK_SUPPORTED_10baseT_Half |
11032 ELINK_SUPPORTED_10baseT_Full |
11033 ELINK_SUPPORTED_100baseT_Half |
11034 ELINK_SUPPORTED_100baseT_Full |
11035 ELINK_SUPPORTED_1000baseT_Full |
11036 ELINK_SUPPORTED_10000baseT_Full |
11037 ELINK_SUPPORTED_TP |
11038 ELINK_SUPPORTED_Autoneg |
11039 ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
11040 .media_type = ELINK_ETH_PHY_BASE_T,
11042 .req_flow_ctrl = 0,
11043 .req_line_speed = 0,
11044 .speed_cap_mask = 0,
11047 .config_init = elink_848x3_config_init,
11048 .read_status = elink_848xx_read_status,
11049 .link_reset = elink_848x3_link_reset,
11050 .config_loopback = NULL,
11051 .format_fw_ver = elink_848xx_format_ver,
11053 .set_link_led = elink_848xx_set_link_led,
11054 .phy_specific_func = elink_848xx_specific_func
11057 static const struct elink_phy phy_84833 = {
11058 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833,
11061 .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ |
11062 ELINK_FLAGS_REARM_LATCH_SIGNAL |
11063 ELINK_FLAGS_TX_ERROR_CHECK | ELINK_FLAGS_TEMPERATURE),
11064 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11065 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11067 .supported = (ELINK_SUPPORTED_100baseT_Half |
11068 ELINK_SUPPORTED_100baseT_Full |
11069 ELINK_SUPPORTED_1000baseT_Full |
11070 ELINK_SUPPORTED_10000baseT_Full |
11071 ELINK_SUPPORTED_TP |
11072 ELINK_SUPPORTED_Autoneg |
11073 ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
11074 .media_type = ELINK_ETH_PHY_BASE_T,
11076 .req_flow_ctrl = 0,
11077 .req_line_speed = 0,
11078 .speed_cap_mask = 0,
11081 .config_init = elink_848x3_config_init,
11082 .read_status = elink_848xx_read_status,
11083 .link_reset = elink_848x3_link_reset,
11084 .config_loopback = NULL,
11085 .format_fw_ver = elink_848xx_format_ver,
11086 .hw_reset = elink_84833_hw_reset_phy,
11087 .set_link_led = elink_848xx_set_link_led,
11088 .phy_specific_func = elink_848xx_specific_func
11091 static const struct elink_phy phy_84834 = {
11092 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834,
11095 .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ |
11096 ELINK_FLAGS_REARM_LATCH_SIGNAL,
11097 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11098 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11100 .supported = (ELINK_SUPPORTED_100baseT_Half |
11101 ELINK_SUPPORTED_100baseT_Full |
11102 ELINK_SUPPORTED_1000baseT_Full |
11103 ELINK_SUPPORTED_10000baseT_Full |
11104 ELINK_SUPPORTED_TP |
11105 ELINK_SUPPORTED_Autoneg |
11106 ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
11107 .media_type = ELINK_ETH_PHY_BASE_T,
11109 .req_flow_ctrl = 0,
11110 .req_line_speed = 0,
11111 .speed_cap_mask = 0,
11114 .config_init = elink_848x3_config_init,
11115 .read_status = elink_848xx_read_status,
11116 .link_reset = elink_848x3_link_reset,
11117 .config_loopback = NULL,
11118 .format_fw_ver = elink_848xx_format_ver,
11119 .hw_reset = elink_84833_hw_reset_phy,
11120 .set_link_led = elink_848xx_set_link_led,
11121 .phy_specific_func = elink_848xx_specific_func
11124 static const struct elink_phy phy_54618se = {
11125 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE,
11128 .flags = ELINK_FLAGS_INIT_XGXS_FIRST,
11129 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11130 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11132 .supported = (ELINK_SUPPORTED_10baseT_Half |
11133 ELINK_SUPPORTED_10baseT_Full |
11134 ELINK_SUPPORTED_100baseT_Half |
11135 ELINK_SUPPORTED_100baseT_Full |
11136 ELINK_SUPPORTED_1000baseT_Full |
11137 ELINK_SUPPORTED_TP |
11138 ELINK_SUPPORTED_Autoneg |
11139 ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
11140 .media_type = ELINK_ETH_PHY_BASE_T,
11142 .req_flow_ctrl = 0,
11143 .req_line_speed = 0,
11144 .speed_cap_mask = 0,
11145 /* req_duplex = */ 0,
11147 .config_init = elink_54618se_config_init,
11148 .read_status = elink_54618se_read_status,
11149 .link_reset = elink_54618se_link_reset,
11150 .config_loopback = elink_54618se_config_loopback,
11151 .format_fw_ver = NULL,
11153 .set_link_led = elink_5461x_set_link_led,
11154 .phy_specific_func = elink_54618se_specific_func
11157 /*****************************************************************/
11159 /* Populate the phy according. Main function: elink_populate_phy */
11161 /*****************************************************************/
11163 static void elink_populate_preemphasis(struct bnx2x_softc *sc,
11164 uint32_t shmem_base,
11165 struct elink_phy *phy, uint8_t port,
11168 /* Get the 4 lanes xgxs config rx and tx */
11169 uint32_t rx = 0, tx = 0, i;
11170 for (i = 0; i < 2; i++) {
11171 /* INT_PHY and ELINK_EXT_PHY1 share the same value location in
11172 * the shmem. When num_phys is greater than 1, than this value
11173 * applies only to ELINK_EXT_PHY1
11175 if (phy_index == ELINK_INT_PHY || phy_index == ELINK_EXT_PHY1) {
11176 rx = REG_RD(sc, shmem_base +
11177 offsetof(struct shmem_region,
11178 dev_info.port_hw_config[port].
11179 xgxs_config_rx[i << 1]));
11181 tx = REG_RD(sc, shmem_base +
11182 offsetof(struct shmem_region,
11183 dev_info.port_hw_config[port].
11184 xgxs_config_tx[i << 1]));
11186 rx = REG_RD(sc, shmem_base +
11187 offsetof(struct shmem_region,
11188 dev_info.port_hw_config[port].
11189 xgxs_config2_rx[i << 1]));
11191 tx = REG_RD(sc, shmem_base +
11192 offsetof(struct shmem_region,
11193 dev_info.port_hw_config[port].
11194 xgxs_config2_rx[i << 1]));
11197 phy->rx_preemphasis[i << 1] = ((rx >> 16) & 0xffff);
11198 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
11200 phy->tx_preemphasis[i << 1] = ((tx >> 16) & 0xffff);
11201 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
11205 static uint32_t elink_get_ext_phy_config(struct bnx2x_softc *sc,
11206 uint32_t shmem_base, uint8_t phy_index,
11209 uint32_t ext_phy_config = 0;
11210 switch (phy_index) {
11211 case ELINK_EXT_PHY1:
11212 ext_phy_config = REG_RD(sc, shmem_base +
11213 offsetof(struct shmem_region,
11214 dev_info.port_hw_config[port].
11215 external_phy_config));
11217 case ELINK_EXT_PHY2:
11218 ext_phy_config = REG_RD(sc, shmem_base +
11219 offsetof(struct shmem_region,
11220 dev_info.port_hw_config[port].
11221 external_phy_config2));
11224 PMD_DRV_LOG(DEBUG, sc, "Invalid phy_index %d", phy_index);
11225 return ELINK_STATUS_ERROR;
11228 return ext_phy_config;
11231 static elink_status_t elink_populate_int_phy(struct bnx2x_softc *sc,
11232 uint32_t shmem_base, uint8_t port,
11233 struct elink_phy *phy)
11236 __rte_unused uint32_t chip_id;
11237 uint32_t switch_cfg = (REG_RD(sc, shmem_base +
11238 offsetof(struct shmem_region,
11240 port_feature_config[port].
11242 PORT_FEATURE_CONNECTED_SWITCH_MASK);
11244 (REG_RD(sc, MISC_REG_CHIP_NUM) << 16) |
11245 ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12);
11247 PMD_DRV_LOG(DEBUG, sc, ":chip_id = 0x%x", chip_id);
11248 if (USES_WARPCORE(sc)) {
11249 uint32_t serdes_net_if;
11250 phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR);
11251 *phy = phy_warpcore;
11252 if (REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)
11253 phy->flags |= ELINK_FLAGS_4_PORT_MODE;
11255 phy->flags &= ~ELINK_FLAGS_4_PORT_MODE;
11256 /* Check Dual mode */
11257 serdes_net_if = (REG_RD(sc, shmem_base +
11258 offsetof(struct shmem_region,
11259 dev_info.port_hw_config[port].
11261 PORT_HW_CFG_NET_SERDES_IF_MASK);
11262 /* Set the appropriate supported and flags indications per
11263 * interface type of the chip
11265 switch (serdes_net_if) {
11266 case PORT_HW_CFG_NET_SERDES_IF_SGMII:
11267 phy->supported &= (ELINK_SUPPORTED_10baseT_Half |
11268 ELINK_SUPPORTED_10baseT_Full |
11269 ELINK_SUPPORTED_100baseT_Half |
11270 ELINK_SUPPORTED_100baseT_Full |
11271 ELINK_SUPPORTED_1000baseT_Full |
11272 ELINK_SUPPORTED_FIBRE |
11273 ELINK_SUPPORTED_Autoneg |
11274 ELINK_SUPPORTED_Pause |
11275 ELINK_SUPPORTED_Asym_Pause);
11276 phy->media_type = ELINK_ETH_PHY_BASE_T;
11278 case PORT_HW_CFG_NET_SERDES_IF_XFI:
11279 phy->supported &= (ELINK_SUPPORTED_1000baseT_Full |
11280 ELINK_SUPPORTED_10000baseT_Full |
11281 ELINK_SUPPORTED_FIBRE |
11282 ELINK_SUPPORTED_Pause |
11283 ELINK_SUPPORTED_Asym_Pause);
11284 phy->media_type = ELINK_ETH_PHY_XFP_FIBER;
11286 case PORT_HW_CFG_NET_SERDES_IF_SFI:
11287 phy->supported &= (ELINK_SUPPORTED_1000baseT_Full |
11288 ELINK_SUPPORTED_10000baseT_Full |
11289 ELINK_SUPPORTED_FIBRE |
11290 ELINK_SUPPORTED_Pause |
11291 ELINK_SUPPORTED_Asym_Pause);
11292 phy->media_type = ELINK_ETH_PHY_SFPP_10G_FIBER;
11294 case PORT_HW_CFG_NET_SERDES_IF_KR:
11295 phy->media_type = ELINK_ETH_PHY_KR;
11296 phy->supported &= (ELINK_SUPPORTED_1000baseT_Full |
11297 ELINK_SUPPORTED_10000baseT_Full |
11298 ELINK_SUPPORTED_FIBRE |
11299 ELINK_SUPPORTED_Autoneg |
11300 ELINK_SUPPORTED_Pause |
11301 ELINK_SUPPORTED_Asym_Pause);
11303 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
11304 phy->media_type = ELINK_ETH_PHY_KR;
11305 phy->flags |= ELINK_FLAGS_WC_DUAL_MODE;
11306 phy->supported &= (ELINK_SUPPORTED_20000baseMLD2_Full |
11307 ELINK_SUPPORTED_FIBRE |
11308 ELINK_SUPPORTED_Pause |
11309 ELINK_SUPPORTED_Asym_Pause);
11311 case PORT_HW_CFG_NET_SERDES_IF_KR2:
11312 phy->media_type = ELINK_ETH_PHY_KR;
11313 phy->flags |= ELINK_FLAGS_WC_DUAL_MODE;
11314 phy->supported &= (ELINK_SUPPORTED_20000baseKR2_Full |
11315 ELINK_SUPPORTED_10000baseT_Full |
11316 ELINK_SUPPORTED_1000baseT_Full |
11317 ELINK_SUPPORTED_Autoneg |
11318 ELINK_SUPPORTED_FIBRE |
11319 ELINK_SUPPORTED_Pause |
11320 ELINK_SUPPORTED_Asym_Pause);
11321 phy->flags &= ~ELINK_FLAGS_TX_ERROR_CHECK;
11324 PMD_DRV_LOG(DEBUG, sc, "Unknown WC interface type 0x%x",
11329 /* Enable MDC/MDIO work-around for E3 A0 since free running MDC
11330 * was not set as expected. For B0, ECO will be enabled so there
11331 * won't be an issue there
11333 if (CHIP_REV(sc) == CHIP_REV_Ax)
11334 phy->flags |= ELINK_FLAGS_MDC_MDIO_WA;
11336 phy->flags |= ELINK_FLAGS_MDC_MDIO_WA_B0;
11338 switch (switch_cfg) {
11339 case ELINK_SWITCH_CFG_1G:
11340 phy_addr = REG_RD(sc,
11341 NIG_REG_SERDES0_CTRL_PHY_ADDR +
11345 case ELINK_SWITCH_CFG_10G:
11346 phy_addr = REG_RD(sc,
11347 NIG_REG_XGXS0_CTRL_PHY_ADDR +
11352 PMD_DRV_LOG(DEBUG, sc, "Invalid switch_cfg");
11353 return ELINK_STATUS_ERROR;
11356 phy->addr = (uint8_t) phy_addr;
11357 phy->mdio_ctrl = elink_get_emac_base(sc,
11358 SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
11360 if (CHIP_IS_E2(sc))
11361 phy->def_md_devad = ELINK_E2_DEFAULT_PHY_DEV_ADDR;
11363 phy->def_md_devad = ELINK_DEFAULT_PHY_DEV_ADDR;
11365 PMD_DRV_LOG(DEBUG, sc, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x",
11366 port, phy->addr, phy->mdio_ctrl);
11368 elink_populate_preemphasis(sc, shmem_base, phy, port, ELINK_INT_PHY);
11369 return ELINK_STATUS_OK;
11372 static elink_status_t elink_populate_ext_phy(struct bnx2x_softc *sc,
11374 uint32_t shmem_base,
11375 uint32_t shmem2_base,
11377 struct elink_phy *phy)
11379 uint32_t ext_phy_config, phy_type, config2;
11380 uint32_t mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
11381 ext_phy_config = elink_get_ext_phy_config(sc, shmem_base,
11383 phy_type = ELINK_XGXS_EXT_PHY_TYPE(ext_phy_config);
11384 /* Select the phy type */
11385 switch (phy_type) {
11386 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073:
11387 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
11390 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8705:
11393 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8706:
11396 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726:
11397 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11400 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727_NOC:
11401 /* BNX2X8727_NOC => BNX2X8727 no over current */
11402 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11404 phy->flags |= ELINK_FLAGS_NOC;
11406 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722:
11407 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727:
11408 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11411 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8481:
11414 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823:
11417 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833:
11420 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834:
11423 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54616:
11424 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE:
11425 *phy = phy_54618se;
11426 if (phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE)
11427 phy->flags |= ELINK_FLAGS_EEE;
11429 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
11432 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
11434 return ELINK_STATUS_ERROR;
11437 /* In case external PHY wasn't found */
11438 if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
11439 (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
11440 return ELINK_STATUS_ERROR;
11441 return ELINK_STATUS_OK;
11444 phy->addr = ELINK_XGXS_EXT_PHY_ADDR(ext_phy_config);
11445 elink_populate_preemphasis(sc, shmem_base, phy, port, phy_index);
11447 /* The shmem address of the phy version is located on different
11448 * structures. In case this structure is too old, do not set
11451 config2 = REG_RD(sc, shmem_base + offsetof(struct shmem_region,
11452 dev_info.shared_hw_config.
11454 if (phy_index == ELINK_EXT_PHY1) {
11455 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
11457 ext_phy_fw_version);
11459 /* Check specific mdc mdio settings */
11460 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
11461 mdc_mdio_access = config2 &
11462 SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
11464 uint32_t size = REG_RD(sc, shmem2_base);
11466 if (size > offsetof(struct shmem2_region, ext_phy_fw_version2)) {
11467 phy->ver_addr = shmem2_base +
11468 offsetof(struct shmem2_region,
11469 ext_phy_fw_version2[port]);
11471 /* Check specific mdc mdio settings */
11472 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
11473 mdc_mdio_access = (config2 &
11474 SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
11475 >> (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
11476 SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
11478 phy->mdio_ctrl = elink_get_emac_base(sc, mdc_mdio_access, port);
11480 if (((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||
11481 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) &&
11483 /* Remove 100Mb link supported for BNX2X84833/4 when phy fw
11484 * version lower than or equal to 1.39
11486 uint32_t raw_ver = REG_RD(sc, phy->ver_addr);
11487 if (((raw_ver & 0x7F) <= 39) && (((raw_ver & 0xF80) >> 7) <= 1))
11488 phy->supported &= ~(ELINK_SUPPORTED_100baseT_Half |
11489 ELINK_SUPPORTED_100baseT_Full);
11492 PMD_DRV_LOG(DEBUG, sc, "phy_type 0x%x port %d found in index %d",
11493 phy_type, port, phy_index);
11494 PMD_DRV_LOG(DEBUG, sc, " addr=0x%x, mdio_ctl=0x%x",
11495 phy->addr, phy->mdio_ctrl);
11496 return ELINK_STATUS_OK;
11499 static elink_status_t elink_populate_phy(struct bnx2x_softc *sc,
11500 uint8_t phy_index, uint32_t shmem_base,
11501 uint32_t shmem2_base, uint8_t port,
11502 struct elink_phy *phy)
11504 elink_status_t status = ELINK_STATUS_OK;
11505 phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
11506 if (phy_index == ELINK_INT_PHY)
11507 return elink_populate_int_phy(sc, shmem_base, port, phy);
11508 status = elink_populate_ext_phy(sc, phy_index, shmem_base, shmem2_base,
11513 static void elink_phy_def_cfg(struct elink_params *params,
11514 struct elink_phy *phy, uint8_t phy_index)
11516 struct bnx2x_softc *sc = params->sc;
11517 uint32_t link_config;
11518 /* Populate the default phy configuration for MF mode */
11519 if (phy_index == ELINK_EXT_PHY2) {
11520 link_config = REG_RD(sc, params->shmem_base +
11521 offsetof(struct shmem_region,
11522 dev_info.port_feature_config
11523 [params->port].link_config2));
11524 phy->speed_cap_mask =
11526 params->shmem_base + offsetof(struct shmem_region,
11527 dev_info.port_hw_config
11529 speed_capability_mask2));
11531 link_config = REG_RD(sc, params->shmem_base +
11532 offsetof(struct shmem_region,
11533 dev_info.port_feature_config
11534 [params->port].link_config));
11535 phy->speed_cap_mask =
11537 params->shmem_base + offsetof(struct shmem_region,
11538 dev_info.port_hw_config
11540 speed_capability_mask));
11543 PMD_DRV_LOG(DEBUG, sc,
11544 "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x",
11545 phy_index, link_config, phy->speed_cap_mask);
11547 phy->req_duplex = DUPLEX_FULL;
11548 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
11549 case PORT_FEATURE_LINK_SPEED_10M_HALF:
11550 phy->req_duplex = DUPLEX_HALF;
11552 case PORT_FEATURE_LINK_SPEED_10M_FULL:
11553 phy->req_line_speed = ELINK_SPEED_10;
11555 case PORT_FEATURE_LINK_SPEED_100M_HALF:
11556 phy->req_duplex = DUPLEX_HALF;
11558 case PORT_FEATURE_LINK_SPEED_100M_FULL:
11559 phy->req_line_speed = ELINK_SPEED_100;
11561 case PORT_FEATURE_LINK_SPEED_1G:
11562 phy->req_line_speed = ELINK_SPEED_1000;
11564 case PORT_FEATURE_LINK_SPEED_2_5G:
11565 phy->req_line_speed = ELINK_SPEED_2500;
11567 case PORT_FEATURE_LINK_SPEED_10G_CX4:
11568 phy->req_line_speed = ELINK_SPEED_10000;
11571 phy->req_line_speed = ELINK_SPEED_AUTO_NEG;
11575 switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) {
11576 case PORT_FEATURE_FLOW_CONTROL_AUTO:
11577 phy->req_flow_ctrl = ELINK_FLOW_CTRL_AUTO;
11579 case PORT_FEATURE_FLOW_CONTROL_TX:
11580 phy->req_flow_ctrl = ELINK_FLOW_CTRL_TX;
11582 case PORT_FEATURE_FLOW_CONTROL_RX:
11583 phy->req_flow_ctrl = ELINK_FLOW_CTRL_RX;
11585 case PORT_FEATURE_FLOW_CONTROL_BOTH:
11586 phy->req_flow_ctrl = ELINK_FLOW_CTRL_BOTH;
11589 phy->req_flow_ctrl = ELINK_FLOW_CTRL_NONE;
11594 uint32_t elink_phy_selection(struct elink_params *params)
11596 uint32_t phy_config_swapped, prio_cfg;
11597 uint32_t return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
11599 phy_config_swapped = params->multi_phy_config &
11600 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
11602 prio_cfg = params->multi_phy_config & PORT_HW_CFG_PHY_SELECTION_MASK;
11604 if (phy_config_swapped) {
11605 switch (prio_cfg) {
11606 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
11608 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
11610 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
11612 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
11614 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
11615 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
11617 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
11618 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
11622 return_cfg = prio_cfg;
11627 elink_status_t elink_phy_probe(struct elink_params * params)
11629 uint8_t phy_index, actual_phy_idx;
11630 uint32_t phy_config_swapped, sync_offset, media_types;
11631 struct bnx2x_softc *sc = params->sc;
11632 struct elink_phy *phy;
11633 params->num_phys = 0;
11634 PMD_DRV_LOG(DEBUG, sc, "Begin phy probe");
11636 phy_config_swapped = params->multi_phy_config &
11637 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
11639 for (phy_index = ELINK_INT_PHY; phy_index < ELINK_MAX_PHYS; phy_index++) {
11640 actual_phy_idx = phy_index;
11641 if (phy_config_swapped) {
11642 if (phy_index == ELINK_EXT_PHY1)
11643 actual_phy_idx = ELINK_EXT_PHY2;
11644 else if (phy_index == ELINK_EXT_PHY2)
11645 actual_phy_idx = ELINK_EXT_PHY1;
11647 PMD_DRV_LOG(DEBUG, sc, "phy_config_swapped %x, phy_index %x,"
11648 " actual_phy_idx %x", phy_config_swapped,
11649 phy_index, actual_phy_idx);
11650 phy = ¶ms->phy[actual_phy_idx];
11651 if (elink_populate_phy(sc, phy_index, params->shmem_base,
11652 params->shmem2_base, params->port,
11653 phy) != ELINK_STATUS_OK) {
11654 params->num_phys = 0;
11655 PMD_DRV_LOG(DEBUG, sc, "phy probe failed in phy index %d",
11657 for (phy_index = ELINK_INT_PHY;
11658 phy_index < ELINK_MAX_PHYS; phy_index++)
11660 return ELINK_STATUS_ERROR;
11662 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
11665 if (params->feature_config_flags &
11666 ELINK_FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET)
11667 phy->flags &= ~ELINK_FLAGS_TX_ERROR_CHECK;
11669 if (!(params->feature_config_flags &
11670 ELINK_FEATURE_CONFIG_MT_SUPPORT))
11671 phy->flags |= ELINK_FLAGS_MDC_MDIO_WA_G;
11673 sync_offset = params->shmem_base +
11674 offsetof(struct shmem_region,
11675 dev_info.port_hw_config[params->port].media_type);
11676 media_types = REG_RD(sc, sync_offset);
11678 /* Update media type for non-PMF sync only for the first time
11679 * In case the media type changes afterwards, it will be updated
11680 * using the update_status function
11682 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
11683 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
11684 actual_phy_idx))) == 0) {
11685 media_types |= ((phy->media_type &
11686 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
11687 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
11690 REG_WR(sc, sync_offset, media_types);
11692 elink_phy_def_cfg(params, phy, phy_index);
11693 params->num_phys++;
11696 PMD_DRV_LOG(DEBUG, sc,
11697 "End phy probe. #phys found %x", params->num_phys);
11698 return ELINK_STATUS_OK;
11701 static void elink_init_bmac_loopback(struct elink_params *params,
11702 struct elink_vars *vars)
11704 struct bnx2x_softc *sc = params->sc;
11706 vars->line_speed = ELINK_SPEED_10000;
11707 vars->duplex = DUPLEX_FULL;
11708 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
11709 vars->mac_type = ELINK_MAC_TYPE_BMAC;
11711 vars->phy_flags = PHY_XGXS_FLAG;
11713 elink_xgxs_deassert(params);
11715 /* Set bmac loopback */
11716 elink_bmac_enable(params, vars, 1, 1);
11718 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
11721 static void elink_init_emac_loopback(struct elink_params *params,
11722 struct elink_vars *vars)
11724 struct bnx2x_softc *sc = params->sc;
11726 vars->line_speed = ELINK_SPEED_1000;
11727 vars->duplex = DUPLEX_FULL;
11728 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
11729 vars->mac_type = ELINK_MAC_TYPE_EMAC;
11731 vars->phy_flags = PHY_XGXS_FLAG;
11733 elink_xgxs_deassert(params);
11734 /* Set bmac loopback */
11735 elink_emac_enable(params, vars, 1);
11736 elink_emac_program(params, vars);
11737 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
11740 static void elink_init_xmac_loopback(struct elink_params *params,
11741 struct elink_vars *vars)
11743 struct bnx2x_softc *sc = params->sc;
11745 if (!params->req_line_speed[0])
11746 vars->line_speed = ELINK_SPEED_10000;
11748 vars->line_speed = params->req_line_speed[0];
11749 vars->duplex = DUPLEX_FULL;
11750 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
11751 vars->mac_type = ELINK_MAC_TYPE_XMAC;
11752 vars->phy_flags = PHY_XGXS_FLAG;
11753 /* Set WC to loopback mode since link is required to provide clock
11754 * to the XMAC in 20G mode
11756 elink_set_aer_mmd(params, ¶ms->phy[0]);
11757 elink_warpcore_reset_lane(sc, ¶ms->phy[0], 0);
11758 params->phy[ELINK_INT_PHY].config_loopback(¶ms->phy[ELINK_INT_PHY],
11761 elink_xmac_enable(params, vars, 1);
11762 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
11765 static void elink_init_umac_loopback(struct elink_params *params,
11766 struct elink_vars *vars)
11768 struct bnx2x_softc *sc = params->sc;
11770 vars->line_speed = ELINK_SPEED_1000;
11771 vars->duplex = DUPLEX_FULL;
11772 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
11773 vars->mac_type = ELINK_MAC_TYPE_UMAC;
11774 vars->phy_flags = PHY_XGXS_FLAG;
11775 elink_umac_enable(params, vars, 1);
11777 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
11780 static void elink_init_xgxs_loopback(struct elink_params *params,
11781 struct elink_vars *vars)
11783 struct bnx2x_softc *sc = params->sc;
11784 struct elink_phy *int_phy = ¶ms->phy[ELINK_INT_PHY];
11786 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
11787 vars->duplex = DUPLEX_FULL;
11788 if (params->req_line_speed[0] == ELINK_SPEED_1000)
11789 vars->line_speed = ELINK_SPEED_1000;
11790 else if ((params->req_line_speed[0] == ELINK_SPEED_20000) ||
11791 (int_phy->flags & ELINK_FLAGS_WC_DUAL_MODE))
11792 vars->line_speed = ELINK_SPEED_20000;
11794 vars->line_speed = ELINK_SPEED_10000;
11796 if (!USES_WARPCORE(sc))
11797 elink_xgxs_deassert(params);
11798 elink_link_initialize(params, vars);
11800 if (params->req_line_speed[0] == ELINK_SPEED_1000) {
11801 if (USES_WARPCORE(sc))
11802 elink_umac_enable(params, vars, 0);
11804 elink_emac_program(params, vars);
11805 elink_emac_enable(params, vars, 0);
11808 if (USES_WARPCORE(sc))
11809 elink_xmac_enable(params, vars, 0);
11811 elink_bmac_enable(params, vars, 0, 1);
11814 if (params->loopback_mode == ELINK_LOOPBACK_XGXS) {
11815 /* Set 10G XGXS loopback */
11816 int_phy->config_loopback(int_phy, params);
11818 /* Set external phy loopback */
11820 for (phy_index = ELINK_EXT_PHY1;
11821 phy_index < params->num_phys; phy_index++)
11822 if (params->phy[phy_index].config_loopback)
11823 params->phy[phy_index].config_loopback(¶ms->
11828 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
11830 elink_set_led(params, vars, ELINK_LED_MODE_OPER, vars->line_speed);
11833 void elink_set_rx_filter(struct elink_params *params, uint8_t en)
11835 struct bnx2x_softc *sc = params->sc;
11836 uint8_t val = en * 0x1F;
11838 /* Open / close the gate between the NIG and the BRB */
11839 if (!CHIP_IS_E1x(sc))
11841 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + params->port * 4, val);
11843 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port * 4, en * 0x3);
11845 REG_WR(sc, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP :
11846 NIG_REG_LLH0_BRB1_NOT_MCP), en);
11849 static elink_status_t elink_avoid_link_flap(struct elink_params *params,
11850 struct elink_vars *vars)
11853 uint32_t dont_clear_stat, lfa_sts;
11854 struct bnx2x_softc *sc = params->sc;
11856 /* Sync the link parameters */
11857 elink_link_status_update(params, vars);
11860 * The module verification was already done by previous link owner,
11861 * so this call is meant only to get warning message
11864 for (phy_idx = ELINK_INT_PHY; phy_idx < params->num_phys; phy_idx++) {
11865 struct elink_phy *phy = ¶ms->phy[phy_idx];
11866 if (phy->phy_specific_func) {
11867 PMD_DRV_LOG(DEBUG, sc, "Calling PHY specific func");
11868 phy->phy_specific_func(phy, params, ELINK_PHY_INIT);
11870 if ((phy->media_type == ELINK_ETH_PHY_SFPP_10G_FIBER) ||
11871 (phy->media_type == ELINK_ETH_PHY_SFP_1G_FIBER) ||
11872 (phy->media_type == ELINK_ETH_PHY_DA_TWINAX))
11873 elink_verify_sfp_module(phy, params);
11875 lfa_sts = REG_RD(sc, params->lfa_base +
11876 offsetof(struct shmem_lfa, lfa_sts));
11878 dont_clear_stat = lfa_sts & SHMEM_LFA_DONT_CLEAR_STAT;
11880 /* Re-enable the NIG/MAC */
11881 if (CHIP_IS_E3(sc)) {
11882 if (!dont_clear_stat) {
11883 REG_WR(sc, GRCBASE_MISC +
11884 MISC_REGISTERS_RESET_REG_2_CLEAR,
11885 (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<
11887 REG_WR(sc, GRCBASE_MISC +
11888 MISC_REGISTERS_RESET_REG_2_SET,
11889 (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<
11892 if (vars->line_speed < ELINK_SPEED_10000)
11893 elink_umac_enable(params, vars, 0);
11895 elink_xmac_enable(params, vars, 0);
11897 if (vars->line_speed < ELINK_SPEED_10000)
11898 elink_emac_enable(params, vars, 0);
11900 elink_bmac_enable(params, vars, 0, !dont_clear_stat);
11903 /* Increment LFA count */
11904 lfa_sts = ((lfa_sts & ~LINK_FLAP_AVOIDANCE_COUNT_MASK) |
11905 (((((lfa_sts & LINK_FLAP_AVOIDANCE_COUNT_MASK) >>
11906 LINK_FLAP_AVOIDANCE_COUNT_OFFSET) + 1) & 0xff)
11907 << LINK_FLAP_AVOIDANCE_COUNT_OFFSET));
11908 /* Clear link flap reason */
11909 lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;
11911 REG_WR(sc, params->lfa_base +
11912 offsetof(struct shmem_lfa, lfa_sts), lfa_sts);
11914 /* Disable NIG DRAIN */
11915 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
11917 /* Enable interrupts */
11918 elink_link_int_enable(params);
11919 return ELINK_STATUS_OK;
11922 static void elink_cannot_avoid_link_flap(struct elink_params *params,
11923 struct elink_vars *vars,
11926 uint32_t lfa_sts, cfg_idx, tmp_val;
11927 struct bnx2x_softc *sc = params->sc;
11929 elink_link_reset(params, vars, 1);
11931 if (!params->lfa_base)
11933 /* Store the new link parameters */
11934 REG_WR(sc, params->lfa_base +
11935 offsetof(struct shmem_lfa, req_duplex),
11936 params->req_duplex[0] | (params->req_duplex[1] << 16));
11938 REG_WR(sc, params->lfa_base +
11939 offsetof(struct shmem_lfa, req_flow_ctrl),
11940 params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16));
11942 REG_WR(sc, params->lfa_base +
11943 offsetof(struct shmem_lfa, req_line_speed),
11944 params->req_line_speed[0] | (params->req_line_speed[1] << 16));
11946 for (cfg_idx = 0; cfg_idx < SHMEM_LINK_CONFIG_SIZE; cfg_idx++) {
11947 REG_WR(sc, params->lfa_base +
11948 offsetof(struct shmem_lfa,
11949 speed_cap_mask[cfg_idx]),
11950 params->speed_cap_mask[cfg_idx]);
11953 tmp_val = REG_RD(sc, params->lfa_base +
11954 offsetof(struct shmem_lfa, additional_config));
11955 tmp_val &= ~REQ_FC_AUTO_ADV_MASK;
11956 tmp_val |= params->req_fc_auto_adv;
11958 REG_WR(sc, params->lfa_base +
11959 offsetof(struct shmem_lfa, additional_config), tmp_val);
11961 lfa_sts = REG_RD(sc, params->lfa_base +
11962 offsetof(struct shmem_lfa, lfa_sts));
11964 /* Clear the "Don't Clear Statistics" bit, and set reason */
11965 lfa_sts &= ~SHMEM_LFA_DONT_CLEAR_STAT;
11967 /* Set link flap reason */
11968 lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;
11969 lfa_sts |= ((lfa_status & LFA_LINK_FLAP_REASON_MASK) <<
11970 LFA_LINK_FLAP_REASON_OFFSET);
11972 /* Increment link flap counter */
11973 lfa_sts = ((lfa_sts & ~LINK_FLAP_COUNT_MASK) |
11974 (((((lfa_sts & LINK_FLAP_COUNT_MASK) >>
11975 LINK_FLAP_COUNT_OFFSET) + 1) & 0xff)
11976 << LINK_FLAP_COUNT_OFFSET));
11977 REG_WR(sc, params->lfa_base +
11978 offsetof(struct shmem_lfa, lfa_sts), lfa_sts);
11979 /* Proceed with regular link initialization */
11982 elink_status_t elink_phy_init(struct elink_params *params,
11983 struct elink_vars *vars)
11986 struct bnx2x_softc *sc = params->sc;
11987 PMD_DRV_LOG(DEBUG, sc, "Phy Initialization started");
11988 PMD_DRV_LOG(DEBUG, sc, "(1) req_speed %d, req_flowctrl %d",
11989 params->req_line_speed[0], params->req_flow_ctrl[0]);
11990 PMD_DRV_LOG(DEBUG, sc, "(2) req_speed %d, req_flowctrl %d",
11991 params->req_line_speed[1], params->req_flow_ctrl[1]);
11992 PMD_DRV_LOG(DEBUG, sc,
11993 "req_adv_flow_ctrl 0x%x", params->req_fc_auto_adv);
11994 vars->link_status = 0;
11995 vars->phy_link_up = 0;
11997 vars->line_speed = 0;
11998 vars->duplex = DUPLEX_FULL;
11999 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
12000 vars->mac_type = ELINK_MAC_TYPE_NONE;
12001 vars->phy_flags = 0;
12002 vars->check_kr2_recovery_cnt = 0;
12003 params->link_flags = ELINK_PHY_INITIALIZED;
12004 /* Driver opens NIG-BRB filters */
12005 elink_set_rx_filter(params, 1);
12006 /* Check if link flap can be avoided */
12007 lfa_status = elink_check_lfa(params);
12009 if (lfa_status == 0) {
12010 PMD_DRV_LOG(DEBUG, sc,
12011 "Link Flap Avoidance in progress");
12012 return elink_avoid_link_flap(params, vars);
12015 PMD_DRV_LOG(DEBUG, sc,
12016 "Cannot avoid link flap lfa_sta=0x%x", lfa_status);
12017 elink_cannot_avoid_link_flap(params, vars, lfa_status);
12019 /* Disable attentions */
12020 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + params->port * 4,
12021 (ELINK_NIG_MASK_XGXS0_LINK_STATUS |
12022 ELINK_NIG_MASK_XGXS0_LINK10G |
12023 ELINK_NIG_MASK_SERDES0_LINK_STATUS |
12024 ELINK_NIG_MASK_MI_INT));
12026 elink_emac_init(params);
12028 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
12029 vars->link_status |= LINK_STATUS_PFC_ENABLED;
12031 if ((params->num_phys == 0) && !CHIP_REV_IS_SLOW(sc)) {
12032 PMD_DRV_LOG(DEBUG, sc, "No phy found for initialization !!");
12033 return ELINK_STATUS_ERROR;
12035 set_phy_vars(params, vars);
12037 PMD_DRV_LOG(DEBUG, sc, "Num of phys on board: %d", params->num_phys);
12039 switch (params->loopback_mode) {
12040 case ELINK_LOOPBACK_BMAC:
12041 elink_init_bmac_loopback(params, vars);
12043 case ELINK_LOOPBACK_EMAC:
12044 elink_init_emac_loopback(params, vars);
12046 case ELINK_LOOPBACK_XMAC:
12047 elink_init_xmac_loopback(params, vars);
12049 case ELINK_LOOPBACK_UMAC:
12050 elink_init_umac_loopback(params, vars);
12052 case ELINK_LOOPBACK_XGXS:
12053 case ELINK_LOOPBACK_EXT_PHY:
12054 elink_init_xgxs_loopback(params, vars);
12057 if (!CHIP_IS_E3(sc)) {
12058 if (params->switch_cfg == ELINK_SWITCH_CFG_10G)
12059 elink_xgxs_deassert(params);
12061 elink_serdes_deassert(sc, params->port);
12063 elink_link_initialize(params, vars);
12065 elink_link_int_enable(params);
12068 elink_update_mng(params, vars->link_status);
12070 elink_update_mng_eee(params, vars->eee_status);
12071 return ELINK_STATUS_OK;
12074 static elink_status_t elink_link_reset(struct elink_params *params,
12075 struct elink_vars *vars,
12076 uint8_t reset_ext_phy)
12078 struct bnx2x_softc *sc = params->sc;
12079 uint8_t phy_index, port = params->port, clear_latch_ind = 0;
12080 PMD_DRV_LOG(DEBUG, sc, "Resetting the link of port %d", port);
12081 /* Disable attentions */
12082 vars->link_status = 0;
12083 elink_update_mng(params, vars->link_status);
12084 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
12085 SHMEM_EEE_ACTIVE_BIT);
12086 elink_update_mng_eee(params, vars->eee_status);
12087 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4,
12088 (ELINK_NIG_MASK_XGXS0_LINK_STATUS |
12089 ELINK_NIG_MASK_XGXS0_LINK10G |
12090 ELINK_NIG_MASK_SERDES0_LINK_STATUS |
12091 ELINK_NIG_MASK_MI_INT));
12093 /* Activate nig drain */
12094 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + port * 4, 1);
12096 /* Disable nig egress interface */
12097 if (!CHIP_IS_E3(sc)) {
12098 REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port * 4, 0);
12099 REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port * 4, 0);
12101 if (!CHIP_IS_E3(sc))
12102 elink_set_bmac_rx(sc, port, 0);
12103 if (CHIP_IS_E3(sc) && !CHIP_REV_IS_FPGA(sc)) {
12104 elink_set_xmac_rxtx(params, 0);
12105 elink_set_umac_rxtx(params, 0);
12108 if (!CHIP_IS_E3(sc))
12109 REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port * 4, 0);
12112 /* The PHY reset is controlled by GPIO 1
12113 * Hold it as vars low
12115 /* Clear link led */
12116 elink_set_mdio_emac_per_phy(sc, params);
12117 elink_set_led(params, vars, ELINK_LED_MODE_OFF, 0);
12119 if (reset_ext_phy && (!CHIP_REV_IS_SLOW(sc))) {
12120 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
12122 if (params->phy[phy_index].link_reset) {
12123 elink_set_aer_mmd(params,
12124 ¶ms->phy[phy_index]);
12125 params->phy[phy_index].link_reset(¶ms->
12130 if (params->phy[phy_index].flags &
12131 ELINK_FLAGS_REARM_LATCH_SIGNAL)
12132 clear_latch_ind = 1;
12136 if (clear_latch_ind) {
12137 /* Clear latching indication */
12138 elink_rearm_latch_signal(sc, port, 0);
12139 elink_bits_dis(sc, NIG_REG_LATCH_BC_0 + port * 4,
12140 1 << ELINK_NIG_LATCH_BC_ENABLE_MI_INT);
12142 if (params->phy[ELINK_INT_PHY].link_reset)
12143 params->phy[ELINK_INT_PHY].link_reset(¶ms->
12148 /* Disable nig ingress interface */
12149 if (!CHIP_IS_E3(sc)) {
12151 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
12152 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
12153 REG_WR(sc, NIG_REG_BMAC0_IN_EN + port * 4, 0);
12154 REG_WR(sc, NIG_REG_EMAC0_IN_EN + port * 4, 0);
12156 uint32_t xmac_base =
12157 (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
12158 elink_set_xumac_nig(params, 0, 0);
12159 if (REG_RD(sc, MISC_REG_RESET_REG_2) &
12160 MISC_REGISTERS_RESET_REG_2_XMAC)
12161 REG_WR(sc, xmac_base + XMAC_REG_CTRL,
12162 XMAC_CTRL_REG_SOFT_RESET);
12165 vars->phy_flags = 0;
12166 return ELINK_STATUS_OK;
12169 elink_status_t elink_lfa_reset(struct elink_params * params,
12170 struct elink_vars * vars)
12172 struct bnx2x_softc *sc = params->sc;
12174 vars->phy_flags = 0;
12175 params->link_flags &= ~ELINK_PHY_INITIALIZED;
12176 if (!params->lfa_base)
12177 return elink_link_reset(params, vars, 1);
12179 * Activate NIG drain so that during this time the device won't send
12180 * anything while it is unable to response.
12182 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 1);
12185 * Close gracefully the gate from BMAC to NIG such that no half packets
12188 if (!CHIP_IS_E3(sc))
12189 elink_set_bmac_rx(sc, params->port, 0);
12191 if (CHIP_IS_E3(sc)) {
12192 elink_set_xmac_rxtx(params, 0);
12193 elink_set_umac_rxtx(params, 0);
12195 /* Wait 10ms for the pipe to clean up */
12198 /* Clean the NIG-BRB using the network filters in a way that will
12199 * not cut a packet in the middle.
12201 elink_set_rx_filter(params, 0);
12204 * Re-open the gate between the BMAC and the NIG, after verifying the
12205 * gate to the BRB is closed, otherwise packets may arrive to the
12206 * firmware before driver had initialized it. The target is to achieve
12207 * minimum management protocol down time.
12209 if (!CHIP_IS_E3(sc))
12210 elink_set_bmac_rx(sc, params->port, 1);
12212 if (CHIP_IS_E3(sc)) {
12213 elink_set_xmac_rxtx(params, 1);
12214 elink_set_umac_rxtx(params, 1);
12216 /* Disable NIG drain */
12217 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
12218 return ELINK_STATUS_OK;
12221 /****************************************************************************/
12222 /* Common function */
12223 /****************************************************************************/
12224 static elink_status_t elink_8073_common_init_phy(struct bnx2x_softc *sc,
12225 uint32_t shmem_base_path[],
12226 uint32_t shmem2_base_path[],
12228 __rte_unused uint32_t chip_id)
12230 struct elink_phy phy[PORT_MAX];
12231 struct elink_phy *phy_blk[PORT_MAX];
12234 int8_t port_of_path = 0;
12235 uint32_t swap_val, swap_override;
12236 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
12237 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
12238 port ^= (swap_val && swap_override);
12239 elink_ext_phy_hw_reset(sc, port);
12240 /* PART1 - Reset both phys */
12241 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12242 uint32_t shmem_base, shmem2_base;
12243 /* In E2, same phy is using for port0 of the two paths */
12244 if (CHIP_IS_E1x(sc)) {
12245 shmem_base = shmem_base_path[0];
12246 shmem2_base = shmem2_base_path[0];
12247 port_of_path = port;
12249 shmem_base = shmem_base_path[port];
12250 shmem2_base = shmem2_base_path[port];
12254 /* Extract the ext phy address for the port */
12255 if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,
12256 port_of_path, &phy[port]) !=
12258 PMD_DRV_LOG(DEBUG, sc, "populate_phy failed");
12259 return ELINK_STATUS_ERROR;
12261 /* Disable attentions */
12262 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 +
12264 (ELINK_NIG_MASK_XGXS0_LINK_STATUS |
12265 ELINK_NIG_MASK_XGXS0_LINK10G |
12266 ELINK_NIG_MASK_SERDES0_LINK_STATUS |
12267 ELINK_NIG_MASK_MI_INT));
12269 /* Need to take the phy out of low power mode in order
12270 * to write to access its registers
12272 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
12273 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
12275 /* Reset the phy */
12276 elink_cl45_write(sc, &phy[port],
12277 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1 << 15);
12280 /* Add delay of 150ms after reset */
12283 if (phy[PORT_0].addr & 0x1) {
12284 phy_blk[PORT_0] = &(phy[PORT_1]);
12285 phy_blk[PORT_1] = &(phy[PORT_0]);
12287 phy_blk[PORT_0] = &(phy[PORT_0]);
12288 phy_blk[PORT_1] = &(phy[PORT_1]);
12291 /* PART2 - Download firmware to both phys */
12292 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12293 if (CHIP_IS_E1x(sc))
12294 port_of_path = port;
12298 PMD_DRV_LOG(DEBUG, sc, "Loading spirom for phy address 0x%x",
12299 phy_blk[port]->addr);
12300 if (elink_8073_8727_external_rom_boot(sc, phy_blk[port],
12302 return ELINK_STATUS_ERROR;
12304 /* Only set bit 10 = 1 (Tx power down) */
12305 elink_cl45_read(sc, phy_blk[port],
12307 MDIO_PMA_REG_TX_POWER_DOWN, &val);
12309 /* Phase1 of TX_POWER_DOWN reset */
12310 elink_cl45_write(sc, phy_blk[port],
12312 MDIO_PMA_REG_TX_POWER_DOWN, (val | 1 << 10));
12315 /* Toggle Transmitter: Power down and then up with 600ms delay
12320 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
12321 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12322 /* Phase2 of POWER_DOWN_RESET */
12323 /* Release bit 10 (Release Tx power down) */
12324 elink_cl45_read(sc, phy_blk[port],
12326 MDIO_PMA_REG_TX_POWER_DOWN, &val);
12328 elink_cl45_write(sc, phy_blk[port],
12330 MDIO_PMA_REG_TX_POWER_DOWN,
12331 (val & (~(1 << 10))));
12334 /* Read modify write the SPI-ROM version select register */
12335 elink_cl45_read(sc, phy_blk[port],
12337 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
12338 elink_cl45_write(sc, phy_blk[port],
12340 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1 << 12)));
12342 /* set GPIO2 back to LOW */
12343 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
12344 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
12346 return ELINK_STATUS_OK;
12349 static elink_status_t elink_8726_common_init_phy(struct bnx2x_softc *sc,
12350 uint32_t shmem_base_path[],
12351 uint32_t shmem2_base_path[],
12353 __rte_unused uint32_t chip_id)
12357 struct elink_phy phy;
12358 /* Use port1 because of the static port-swap */
12359 /* Enable the module detection interrupt */
12360 val = REG_RD(sc, MISC_REG_GPIO_EVENT_EN);
12361 val |= ((1 << MISC_REGISTERS_GPIO_3) |
12363 (MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
12364 REG_WR(sc, MISC_REG_GPIO_EVENT_EN, val);
12366 elink_ext_phy_hw_reset(sc, 0);
12368 for (port = 0; port < PORT_MAX; port++) {
12369 uint32_t shmem_base, shmem2_base;
12371 /* In E2, same phy is using for port0 of the two paths */
12372 if (CHIP_IS_E1x(sc)) {
12373 shmem_base = shmem_base_path[0];
12374 shmem2_base = shmem2_base_path[0];
12376 shmem_base = shmem_base_path[port];
12377 shmem2_base = shmem2_base_path[port];
12379 /* Extract the ext phy address for the port */
12380 if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,
12381 port, &phy) != ELINK_STATUS_OK) {
12382 PMD_DRV_LOG(DEBUG, sc, "populate phy failed");
12383 return ELINK_STATUS_ERROR;
12387 elink_cl45_write(sc, &phy,
12388 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
12390 /* Set fault module detected LED on */
12391 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_0,
12392 MISC_REGISTERS_GPIO_HIGH, port);
12395 return ELINK_STATUS_OK;
12398 static void elink_get_ext_phy_reset_gpio(struct bnx2x_softc *sc,
12399 uint32_t shmem_base, uint8_t * io_gpio,
12403 uint32_t phy_gpio_reset = REG_RD(sc, shmem_base +
12404 offsetof(struct shmem_region,
12406 port_hw_config[PORT_0].
12408 switch (phy_gpio_reset) {
12409 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
12413 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:
12417 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:
12421 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:
12425 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:
12429 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:
12433 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:
12437 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:
12442 /* Don't override the io_gpio and io_port */
12447 static elink_status_t elink_8727_common_init_phy(struct bnx2x_softc *sc,
12448 uint32_t shmem_base_path[],
12449 uint32_t shmem2_base_path[],
12451 __rte_unused uint32_t chip_id)
12453 int8_t port, reset_gpio;
12454 uint32_t swap_val, swap_override;
12455 struct elink_phy phy[PORT_MAX];
12456 struct elink_phy *phy_blk[PORT_MAX];
12457 int8_t port_of_path;
12458 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
12459 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
12461 reset_gpio = MISC_REGISTERS_GPIO_1;
12464 /* Retrieve the reset gpio/port which control the reset.
12465 * Default is GPIO1, PORT1
12467 elink_get_ext_phy_reset_gpio(sc, shmem_base_path[0],
12468 (uint8_t *) & reset_gpio,
12469 (uint8_t *) & port);
12471 /* Calculate the port based on port swap */
12472 port ^= (swap_val && swap_override);
12474 /* Initiate PHY reset */
12475 elink_cb_gpio_write(sc, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
12478 elink_cb_gpio_write(sc, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
12483 /* PART1 - Reset both phys */
12484 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12485 uint32_t shmem_base, shmem2_base;
12487 /* In E2, same phy is using for port0 of the two paths */
12488 if (CHIP_IS_E1x(sc)) {
12489 shmem_base = shmem_base_path[0];
12490 shmem2_base = shmem2_base_path[0];
12491 port_of_path = port;
12493 shmem_base = shmem_base_path[port];
12494 shmem2_base = shmem2_base_path[port];
12498 /* Extract the ext phy address for the port */
12499 if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,
12500 port_of_path, &phy[port]) !=
12502 PMD_DRV_LOG(DEBUG, sc, "populate phy failed");
12503 return ELINK_STATUS_ERROR;
12505 /* disable attentions */
12506 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 +
12508 (ELINK_NIG_MASK_XGXS0_LINK_STATUS |
12509 ELINK_NIG_MASK_XGXS0_LINK10G |
12510 ELINK_NIG_MASK_SERDES0_LINK_STATUS |
12511 ELINK_NIG_MASK_MI_INT));
12513 /* Reset the phy */
12514 elink_cl45_write(sc, &phy[port],
12515 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1 << 15);
12518 /* Add delay of 150ms after reset */
12520 if (phy[PORT_0].addr & 0x1) {
12521 phy_blk[PORT_0] = &(phy[PORT_1]);
12522 phy_blk[PORT_1] = &(phy[PORT_0]);
12524 phy_blk[PORT_0] = &(phy[PORT_0]);
12525 phy_blk[PORT_1] = &(phy[PORT_1]);
12527 /* PART2 - Download firmware to both phys */
12528 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12529 if (CHIP_IS_E1x(sc))
12530 port_of_path = port;
12533 PMD_DRV_LOG(DEBUG, sc, "Loading spirom for phy address 0x%x",
12534 phy_blk[port]->addr);
12535 if (elink_8073_8727_external_rom_boot(sc, phy_blk[port],
12537 return ELINK_STATUS_ERROR;
12538 /* Disable PHY transmitter output */
12539 elink_cl45_write(sc, phy_blk[port],
12540 MDIO_PMA_DEVAD, MDIO_PMA_REG_TX_DISABLE, 1);
12543 return ELINK_STATUS_OK;
12546 static elink_status_t elink_84833_common_init_phy(struct bnx2x_softc *sc,
12547 uint32_t shmem_base_path[],
12548 __rte_unused uint32_t
12549 shmem2_base_path[],
12550 __rte_unused uint8_t
12551 phy_index, uint32_t chip_id)
12553 uint8_t reset_gpios;
12554 reset_gpios = elink_84833_get_reset_gpios(sc, shmem_base_path, chip_id);
12555 elink_cb_gpio_mult_write(sc, reset_gpios,
12556 MISC_REGISTERS_GPIO_OUTPUT_LOW);
12558 elink_cb_gpio_mult_write(sc, reset_gpios,
12559 MISC_REGISTERS_GPIO_OUTPUT_HIGH);
12560 PMD_DRV_LOG(DEBUG, sc,
12561 "84833 reset pulse on pin values 0x%x", reset_gpios);
12562 return ELINK_STATUS_OK;
12565 static elink_status_t elink_ext_phy_common_init(struct bnx2x_softc *sc,
12566 uint32_t shmem_base_path[],
12567 uint32_t shmem2_base_path[],
12569 uint32_t ext_phy_type,
12572 elink_status_t rc = ELINK_STATUS_OK;
12574 switch (ext_phy_type) {
12575 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073:
12576 rc = elink_8073_common_init_phy(sc, shmem_base_path,
12578 phy_index, chip_id);
12580 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722:
12581 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727:
12582 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727_NOC:
12583 rc = elink_8727_common_init_phy(sc, shmem_base_path,
12585 phy_index, chip_id);
12588 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726:
12589 /* GPIO1 affects both ports, so there's need to pull
12590 * it for single port alone
12592 rc = elink_8726_common_init_phy(sc, shmem_base_path,
12594 phy_index, chip_id);
12596 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833:
12597 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834:
12598 /* GPIO3's are linked, and so both need to be toggled
12599 * to obtain required 2us pulse.
12601 rc = elink_84833_common_init_phy(sc, shmem_base_path,
12603 phy_index, chip_id);
12605 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
12606 rc = ELINK_STATUS_ERROR;
12609 PMD_DRV_LOG(DEBUG, sc,
12610 "ext_phy 0x%x common init not required",
12615 if (rc != ELINK_STATUS_OK)
12616 elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, 0); // "Warning: PHY was not initialized,"
12622 elink_status_t elink_common_init_phy(struct bnx2x_softc * sc,
12623 uint32_t shmem_base_path[],
12624 uint32_t shmem2_base_path[],
12626 __rte_unused uint8_t one_port_enabled)
12628 elink_status_t rc = ELINK_STATUS_OK;
12629 uint32_t phy_ver, val;
12630 uint8_t phy_index = 0;
12631 uint32_t ext_phy_type, ext_phy_config;
12633 elink_set_mdio_clk(sc, GRCBASE_EMAC0);
12634 elink_set_mdio_clk(sc, GRCBASE_EMAC1);
12635 PMD_DRV_LOG(DEBUG, sc, "Begin common phy init");
12636 if (CHIP_IS_E3(sc)) {
12638 val = REG_RD(sc, MISC_REG_GEN_PURP_HWG);
12639 REG_WR(sc, MISC_REG_GEN_PURP_HWG, val | 1);
12641 /* Check if common init was already done */
12642 phy_ver = REG_RD(sc, shmem_base_path[0] +
12643 offsetof(struct shmem_region,
12644 port_mb[PORT_0].ext_phy_fw_version));
12646 PMD_DRV_LOG(DEBUG, sc, "Not doing common init; phy ver is 0x%x",
12648 return ELINK_STATUS_OK;
12651 /* Read the ext_phy_type for arbitrary port(0) */
12652 for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS;
12654 ext_phy_config = elink_get_ext_phy_config(sc,
12655 shmem_base_path[0],
12657 ext_phy_type = ELINK_XGXS_EXT_PHY_TYPE(ext_phy_config);
12658 rc |= elink_ext_phy_common_init(sc, shmem_base_path,
12660 phy_index, ext_phy_type,
12666 static void elink_check_over_curr(struct elink_params *params,
12667 struct elink_vars *vars)
12669 struct bnx2x_softc *sc = params->sc;
12671 uint8_t port = params->port;
12674 cfg_pin = (REG_RD(sc, params->shmem_base +
12675 offsetof(struct shmem_region,
12676 dev_info.port_hw_config[port].
12677 e3_cmn_pin_cfg1)) &
12678 PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>
12679 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;
12681 /* Ignore check if no external input PIN available */
12682 if (elink_get_cfg_pin(sc, cfg_pin, &pin_val) != ELINK_STATUS_OK)
12686 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) {
12687 elink_cb_event_log(sc, ELINK_LOG_ID_OVER_CURRENT, params->port); //"Error: Power fault on Port %d has"
12688 // " been detected and the power to "
12689 // "that SFP+ module has been removed"
12690 // " to prevent failure of the card."
12691 // " Please remove the SFP+ module and"
12692 // " restart the system to clear this"
12694 vars->phy_flags |= PHY_OVER_CURRENT_FLAG;
12695 elink_warpcore_power_module(params, 0);
12698 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG;
12701 /* Returns 0 if no change occurred since last check; 1 otherwise. */
12702 static uint8_t elink_analyze_link_error(struct elink_params *params,
12703 struct elink_vars *vars,
12704 uint32_t status, uint32_t phy_flag,
12705 uint32_t link_flag, uint8_t notify)
12707 struct bnx2x_softc *sc = params->sc;
12708 /* Compare new value with previous value */
12710 uint32_t old_status = (vars->phy_flags & phy_flag) ? 1 : 0;
12712 if ((status ^ old_status) == 0)
12715 /* If values differ */
12716 switch (phy_flag) {
12717 case PHY_HALF_OPEN_CONN_FLAG:
12718 PMD_DRV_LOG(DEBUG, sc, "Analyze Remote Fault");
12720 case PHY_SFP_TX_FAULT_FLAG:
12721 PMD_DRV_LOG(DEBUG, sc, "Analyze TX Fault");
12724 PMD_DRV_LOG(DEBUG, sc, "Analyze UNKNOWN");
12726 PMD_DRV_LOG(DEBUG, sc, "Link changed:[%x %x]->%x", vars->link_up,
12727 old_status, status);
12729 /* a. Update shmem->link_status accordingly
12730 * b. Update elink_vars->link_up
12733 vars->link_status &= ~LINK_STATUS_LINK_UP;
12734 vars->link_status |= link_flag;
12736 vars->phy_flags |= phy_flag;
12738 /* activate nig drain */
12739 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 1);
12740 /* Set LED mode to off since the PHY doesn't know about these
12743 led_mode = ELINK_LED_MODE_OFF;
12745 vars->link_status |= LINK_STATUS_LINK_UP;
12746 vars->link_status &= ~link_flag;
12748 vars->phy_flags &= ~phy_flag;
12749 led_mode = ELINK_LED_MODE_OPER;
12751 /* Clear nig drain */
12752 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
12754 elink_sync_link(params, vars);
12755 /* Update the LED according to the link state */
12756 elink_set_led(params, vars, led_mode, ELINK_SPEED_10000);
12758 /* Update link status in the shared memory */
12759 elink_update_mng(params, vars->link_status);
12761 /* C. Trigger General Attention */
12762 vars->periodic_flags |= ELINK_PERIODIC_FLAGS_LINK_EVENT;
12764 elink_cb_notify_link_changed(sc);
12769 /******************************************************************************
12771 * This function checks for half opened connection change indication.
12772 * When such change occurs, it calls the elink_analyze_link_error
12773 * to check if Remote Fault is set or cleared. Reception of remote fault
12774 * status message in the MAC indicates that the peer's MAC has detected
12775 * a fault, for example, due to break in the TX side of fiber.
12777 ******************************************************************************/
12778 static elink_status_t elink_check_half_open_conn(struct elink_params *params,
12779 struct elink_vars *vars,
12782 struct bnx2x_softc *sc = params->sc;
12783 uint32_t lss_status = 0;
12785 /* In case link status is physically up @ 10G do */
12786 if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) ||
12787 (REG_RD(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port * 4)))
12788 return ELINK_STATUS_OK;
12790 if (CHIP_IS_E3(sc) &&
12791 (REG_RD(sc, MISC_REG_RESET_REG_2) &
12792 (MISC_REGISTERS_RESET_REG_2_XMAC))) {
12793 /* Check E3 XMAC */
12794 /* Note that link speed cannot be queried here, since it may be
12795 * zero while link is down. In case UMAC is active, LSS will
12796 * simply not be set
12798 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
12800 /* Clear stick bits (Requires rising edge) */
12801 REG_WR(sc, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
12802 REG_WR(sc, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
12803 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
12804 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
12805 if (REG_RD(sc, mac_base + XMAC_REG_RX_LSS_STATUS))
12808 elink_analyze_link_error(params, vars, lss_status,
12809 PHY_HALF_OPEN_CONN_FLAG,
12810 LINK_STATUS_NONE, notify);
12811 } else if (REG_RD(sc, MISC_REG_RESET_REG_2) &
12812 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) {
12813 /* Check E1X / E2 BMAC */
12814 uint32_t lss_status_reg;
12815 uint32_t wb_data[2];
12816 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
12817 NIG_REG_INGRESS_BMAC0_MEM;
12818 /* Read BIGMAC_REGISTER_RX_LSS_STATUS */
12819 if (CHIP_IS_E2(sc))
12820 lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT;
12822 lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS;
12824 REG_RD_DMAE(sc, mac_base + lss_status_reg, wb_data, 2);
12825 lss_status = (wb_data[0] > 0);
12827 elink_analyze_link_error(params, vars, lss_status,
12828 PHY_HALF_OPEN_CONN_FLAG,
12829 LINK_STATUS_NONE, notify);
12831 return ELINK_STATUS_OK;
12834 static void elink_sfp_tx_fault_detection(struct elink_phy *phy,
12835 struct elink_params *params,
12836 struct elink_vars *vars)
12838 struct bnx2x_softc *sc = params->sc;
12839 uint32_t cfg_pin, value = 0;
12840 uint8_t led_change, port = params->port;
12842 /* Get The SFP+ TX_Fault controlling pin ([eg]pio) */
12843 cfg_pin = (REG_RD(sc, params->shmem_base + offsetof(struct shmem_region,
12848 PORT_HW_CFG_E3_TX_FAULT_MASK) >>
12849 PORT_HW_CFG_E3_TX_FAULT_SHIFT;
12851 if (elink_get_cfg_pin(sc, cfg_pin, &value)) {
12852 PMD_DRV_LOG(DEBUG, sc, "Failed to read pin 0x%02x", cfg_pin);
12856 led_change = elink_analyze_link_error(params, vars, value,
12857 PHY_SFP_TX_FAULT_FLAG,
12858 LINK_STATUS_SFP_TX_FAULT, 1);
12861 /* Change TX_Fault led, set link status for further syncs */
12864 if (vars->phy_flags & PHY_SFP_TX_FAULT_FLAG) {
12865 led_mode = MISC_REGISTERS_GPIO_HIGH;
12866 vars->link_status |= LINK_STATUS_SFP_TX_FAULT;
12868 led_mode = MISC_REGISTERS_GPIO_LOW;
12869 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
12872 /* If module is unapproved, led should be on regardless */
12873 if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) {
12874 PMD_DRV_LOG(DEBUG, sc, "Change TX_Fault LED: ->%x",
12876 elink_set_e3_module_fault_led(params, led_mode);
12881 static void elink_kr2_recovery(struct elink_params *params,
12882 struct elink_vars *vars, struct elink_phy *phy)
12884 PMD_DRV_LOG(DEBUG, params->sc, "KR2 recovery");
12886 elink_warpcore_enable_AN_KR2(phy, params, vars);
12887 elink_warpcore_restart_AN_KR(phy, params);
12890 static void elink_check_kr2_wa(struct elink_params *params,
12891 struct elink_vars *vars, struct elink_phy *phy)
12893 struct bnx2x_softc *sc = params->sc;
12894 uint16_t base_page, next_page, not_kr2_device, lane;
12897 /* Once KR2 was disabled, wait 5 seconds before checking KR2 recovery
12898 * Since some switches tend to reinit the AN process and clear the
12899 * the advertised BP/NP after ~2 seconds causing the KR2 to be disabled
12900 * and recovered many times
12902 if (vars->check_kr2_recovery_cnt > 0) {
12903 vars->check_kr2_recovery_cnt--;
12907 sigdet = elink_warpcore_get_sigdet(phy, params);
12909 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
12910 elink_kr2_recovery(params, vars, phy);
12911 PMD_DRV_LOG(DEBUG, sc, "No sigdet");
12916 lane = elink_get_warpcore_lane(params);
12917 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
12918 MDIO_AER_BLOCK_AER_REG, lane);
12919 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
12920 MDIO_AN_REG_LP_AUTO_NEG, &base_page);
12921 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
12922 MDIO_AN_REG_LP_AUTO_NEG2, &next_page);
12923 elink_set_aer_mmd(params, phy);
12925 /* CL73 has not begun yet */
12926 if (base_page == 0) {
12927 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
12928 elink_kr2_recovery(params, vars, phy);
12929 PMD_DRV_LOG(DEBUG, sc, "No BP");
12934 /* In case NP bit is not set in the BasePage, or it is set,
12935 * but only KX is advertised, declare this link partner as non-KR2
12938 not_kr2_device = (((base_page & 0x8000) == 0) ||
12939 (((base_page & 0x8000) &&
12940 ((next_page & 0xe0) == 0x20))));
12942 /* In case KR2 is already disabled, check if we need to re-enable it */
12943 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
12944 if (!not_kr2_device) {
12945 PMD_DRV_LOG(DEBUG, sc, "BP=0x%x, NP=0x%x", base_page,
12947 elink_kr2_recovery(params, vars, phy);
12951 /* KR2 is enabled, but not KR2 device */
12952 if (not_kr2_device) {
12953 /* Disable KR2 on both lanes */
12954 PMD_DRV_LOG(DEBUG, sc,
12955 "BP=0x%x, NP=0x%x", base_page, next_page);
12956 elink_disable_kr2(params, vars, phy);
12957 /* Restart AN on leading lane */
12958 elink_warpcore_restart_AN_KR(phy, params);
12963 void elink_period_func(struct elink_params *params, struct elink_vars *vars)
12966 struct bnx2x_softc *sc = params->sc;
12967 for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) {
12968 if (params->phy[phy_idx].flags & ELINK_FLAGS_TX_ERROR_CHECK) {
12969 elink_set_aer_mmd(params, ¶ms->phy[phy_idx]);
12970 if (elink_check_half_open_conn(params, vars, 1) !=
12972 PMD_DRV_LOG(DEBUG, sc, "Fault detection failed");
12978 if (CHIP_IS_E3(sc)) {
12979 struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY];
12980 elink_set_aer_mmd(params, phy);
12981 if ((phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) &&
12982 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
12983 elink_check_kr2_wa(params, vars, phy);
12984 elink_check_over_curr(params, vars);
12985 if (vars->rx_tx_asic_rst)
12986 elink_warpcore_config_runtime(phy, params, vars);
12988 if ((REG_RD(sc, params->shmem_base +
12989 offsetof(struct shmem_region,
12990 dev_info.port_hw_config[params->port].
12992 & PORT_HW_CFG_NET_SERDES_IF_MASK) ==
12993 PORT_HW_CFG_NET_SERDES_IF_SFI) {
12994 if (elink_is_sfp_module_plugged(params)) {
12995 elink_sfp_tx_fault_detection(phy, params, vars);
12996 } else if (vars->link_status & LINK_STATUS_SFP_TX_FAULT) {
12997 /* Clean trail, interrupt corrects the leds */
12998 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
12999 vars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG;
13000 /* Update link status in the shared memory */
13001 elink_update_mng(params, vars->link_status);
13007 uint8_t elink_fan_failure_det_req(struct bnx2x_softc *sc,
13008 uint32_t shmem_base,
13009 uint32_t shmem2_base, uint8_t port)
13011 uint8_t phy_index, fan_failure_det_req = 0;
13012 struct elink_phy phy;
13013 for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS;
13015 if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,
13017 != ELINK_STATUS_OK) {
13018 PMD_DRV_LOG(DEBUG, sc, "populate phy failed");
13021 fan_failure_det_req |= (phy.flags &
13022 ELINK_FLAGS_FAN_FAILURE_DET_REQ);
13024 return fan_failure_det_req;
13027 void elink_hw_reset_phy(struct elink_params *params)
13030 struct bnx2x_softc *sc = params->sc;
13031 elink_update_mng(params, 0);
13032 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + params->port * 4,
13033 (ELINK_NIG_MASK_XGXS0_LINK_STATUS |
13034 ELINK_NIG_MASK_XGXS0_LINK10G |
13035 ELINK_NIG_MASK_SERDES0_LINK_STATUS |
13036 ELINK_NIG_MASK_MI_INT));
13038 for (phy_index = ELINK_INT_PHY; phy_index < ELINK_MAX_PHYS; phy_index++) {
13039 if (params->phy[phy_index].hw_reset) {
13040 params->phy[phy_index].hw_reset(¶ms->phy[phy_index],
13042 params->phy[phy_index] = phy_null;
13047 void elink_init_mod_abs_int(struct bnx2x_softc *sc, struct elink_vars *vars,
13048 __rte_unused uint32_t chip_id, uint32_t shmem_base,
13049 uint32_t shmem2_base, uint8_t port)
13051 uint8_t gpio_num = 0xff, gpio_port = 0xff, phy_index;
13053 uint32_t offset, aeu_mask, swap_val, swap_override, sync_offset;
13054 if (CHIP_IS_E3(sc)) {
13055 if (elink_get_mod_abs_int_cfg(sc,
13059 &gpio_port) != ELINK_STATUS_OK)
13062 struct elink_phy phy;
13063 for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS;
13065 if (elink_populate_phy(sc, phy_index, shmem_base,
13066 shmem2_base, port, &phy)
13067 != ELINK_STATUS_OK) {
13068 PMD_DRV_LOG(DEBUG, sc, "populate phy failed");
13071 if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726) {
13072 gpio_num = MISC_REGISTERS_GPIO_3;
13079 if (gpio_num == 0xff)
13082 /* Set GPIO3 to trigger SFP+ module insertion/removal */
13083 elink_cb_gpio_write(sc, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z,
13086 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
13087 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
13088 gpio_port ^= (swap_val && swap_override);
13090 vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<
13091 (gpio_num + (gpio_port << 2));
13093 sync_offset = shmem_base +
13094 offsetof(struct shmem_region,
13095 dev_info.port_hw_config[port].aeu_int_mask);
13096 REG_WR(sc, sync_offset, vars->aeu_int_mask);
13098 PMD_DRV_LOG(DEBUG, sc, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x",
13099 gpio_num, gpio_port, vars->aeu_int_mask);
13102 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
13104 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
13106 /* Open appropriate AEU for interrupts */
13107 aeu_mask = REG_RD(sc, offset);
13108 aeu_mask |= vars->aeu_int_mask;
13109 REG_WR(sc, offset, aeu_mask);
13111 /* Enable the GPIO to trigger interrupt */
13112 val = REG_RD(sc, MISC_REG_GPIO_EVENT_EN);
13113 val |= 1 << (gpio_num + (gpio_port << 2));
13114 REG_WR(sc, MISC_REG_GPIO_EVENT_EN, val);