2 * Copyright (c) 2007-2013 QLogic Corporation. All rights reserved.
4 * Eric Davis <edavis@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
6 * Gary Zambrano <zambrano@broadcom.com>
8 * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. Neither the name of Broadcom Corporation nor the name of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written consent.
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
34 * THE POSSIBILITY OF SUCH DAMAGE.
39 #include "ecore_mfw_req.h"
40 #include "ecore_fw_defs.h"
41 #include "ecore_hsi.h"
42 #include "ecore_reg.h"
44 static elink_status_t elink_link_reset(struct elink_params *params,
45 struct elink_vars *vars,
46 uint8_t reset_ext_phy);
47 static elink_status_t elink_check_half_open_conn(struct elink_params *params,
48 struct elink_vars *vars,
50 static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
51 struct elink_params *params);
53 #define MDIO_REG_BANK_CL73_IEEEB0 0x0
54 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0
55 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200
56 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000
57 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000
59 #define MDIO_REG_BANK_CL73_IEEEB1 0x10
60 #define MDIO_CL73_IEEEB1_AN_ADV1 0x00
61 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE 0x0400
62 #define MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC 0x0800
63 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH 0x0C00
64 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK 0x0C00
65 #define MDIO_CL73_IEEEB1_AN_ADV2 0x01
66 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000
67 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020
68 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040
69 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080
70 #define MDIO_CL73_IEEEB1_AN_LP_ADV1 0x03
71 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE 0x0400
72 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC 0x0800
73 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH 0x0C00
74 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK 0x0C00
75 #define MDIO_CL73_IEEEB1_AN_LP_ADV2 0x04
77 #define MDIO_REG_BANK_RX0 0x80b0
78 #define MDIO_RX0_RX_STATUS 0x10
79 #define MDIO_RX0_RX_STATUS_SIGDET 0x8000
80 #define MDIO_RX0_RX_STATUS_RX_SEQ_DONE 0x1000
81 #define MDIO_RX0_RX_EQ_BOOST 0x1c
82 #define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
83 #define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10
85 #define MDIO_REG_BANK_RX1 0x80c0
86 #define MDIO_RX1_RX_EQ_BOOST 0x1c
87 #define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
88 #define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10
90 #define MDIO_REG_BANK_RX2 0x80d0
91 #define MDIO_RX2_RX_EQ_BOOST 0x1c
92 #define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
93 #define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10
95 #define MDIO_REG_BANK_RX3 0x80e0
96 #define MDIO_RX3_RX_EQ_BOOST 0x1c
97 #define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
98 #define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10
100 #define MDIO_REG_BANK_RX_ALL 0x80f0
101 #define MDIO_RX_ALL_RX_EQ_BOOST 0x1c
102 #define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
103 #define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10
105 #define MDIO_REG_BANK_TX0 0x8060
106 #define MDIO_TX0_TX_DRIVER 0x17
107 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
108 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
109 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
110 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
111 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
112 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
113 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
114 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
115 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
117 #define MDIO_REG_BANK_TX1 0x8070
118 #define MDIO_TX1_TX_DRIVER 0x17
119 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
120 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
121 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
122 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
123 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
124 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
125 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
126 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
127 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
129 #define MDIO_REG_BANK_TX2 0x8080
130 #define MDIO_TX2_TX_DRIVER 0x17
131 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
132 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
133 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
134 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
135 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
136 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
137 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
138 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
139 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
141 #define MDIO_REG_BANK_TX3 0x8090
142 #define MDIO_TX3_TX_DRIVER 0x17
143 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
144 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
145 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
146 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
147 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
148 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
149 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
150 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
151 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
153 #define MDIO_REG_BANK_XGXS_BLOCK0 0x8000
154 #define MDIO_BLOCK0_XGXS_CONTROL 0x10
156 #define MDIO_REG_BANK_XGXS_BLOCK1 0x8010
157 #define MDIO_BLOCK1_LANE_CTRL0 0x15
158 #define MDIO_BLOCK1_LANE_CTRL1 0x16
159 #define MDIO_BLOCK1_LANE_CTRL2 0x17
160 #define MDIO_BLOCK1_LANE_PRBS 0x19
162 #define MDIO_REG_BANK_XGXS_BLOCK2 0x8100
163 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10
164 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000
165 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000
166 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11
167 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000
168 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14
169 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001
170 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010
171 #define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15
173 #define MDIO_REG_BANK_GP_STATUS 0x8120
174 #define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B
175 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001
176 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002
177 #define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004
178 #define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008
179 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010
180 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020
181 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040
182 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080
183 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00
184 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000
185 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100
186 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200
187 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300
188 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400
189 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500
190 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600
191 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700
192 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800
193 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900
194 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00
195 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00
196 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00
197 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00
198 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00
199 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR 0x0F00
200 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI 0x1B00
201 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS 0x1E00
202 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI 0x1F00
203 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2 0x3900
205 #define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130
206 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS 0x10
207 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK 0x8000
208 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11
209 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1
210 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13
211 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT (0xb71<<1)
213 #define MDIO_REG_BANK_SERDES_DIGITAL 0x8300
214 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 0x10
215 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x0001
216 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF 0x0002
217 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN 0x0004
218 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x0008
219 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET 0x0010
220 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE 0x0020
221 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 0x11
222 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001
223 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040
224 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14
225 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SGMII 0x0001
226 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_LINK 0x0002
227 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004
228 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018
229 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3
230 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G 0x0018
231 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010
232 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008
233 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000
234 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2 0x15
235 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED 0x0002
236 #define MDIO_SERDES_DIGITAL_MISC1 0x18
237 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000
238 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000
239 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M 0x2000
240 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M 0x4000
241 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M 0x6000
242 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M 0x8000
243 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL 0x0010
244 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK 0x000f
245 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G 0x0000
246 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G 0x0001
247 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G 0x0002
248 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG 0x0003
249 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 0x0004
250 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G 0x0005
251 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G 0x0006
252 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G 0x0007
253 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G 0x0008
254 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G 0x0009
256 #define MDIO_REG_BANK_OVER_1G 0x8320
257 #define MDIO_OVER_1G_DIGCTL_3_4 0x14
258 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK 0xffe0
259 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT 5
260 #define MDIO_OVER_1G_UP1 0x19
261 #define MDIO_OVER_1G_UP1_2_5G 0x0001
262 #define MDIO_OVER_1G_UP1_5G 0x0002
263 #define MDIO_OVER_1G_UP1_6G 0x0004
264 #define MDIO_OVER_1G_UP1_10G 0x0010
265 #define MDIO_OVER_1G_UP1_10GH 0x0008
266 #define MDIO_OVER_1G_UP1_12G 0x0020
267 #define MDIO_OVER_1G_UP1_12_5G 0x0040
268 #define MDIO_OVER_1G_UP1_13G 0x0080
269 #define MDIO_OVER_1G_UP1_15G 0x0100
270 #define MDIO_OVER_1G_UP1_16G 0x0200
271 #define MDIO_OVER_1G_UP2 0x1A
272 #define MDIO_OVER_1G_UP2_IPREDRIVER_MASK 0x0007
273 #define MDIO_OVER_1G_UP2_IDRIVER_MASK 0x0038
274 #define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK 0x03C0
275 #define MDIO_OVER_1G_UP3 0x1B
276 #define MDIO_OVER_1G_UP3_HIGIG2 0x0001
277 #define MDIO_OVER_1G_LP_UP1 0x1C
278 #define MDIO_OVER_1G_LP_UP2 0x1D
279 #define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK 0x03ff
280 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK 0x0780
281 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 7
282 #define MDIO_OVER_1G_LP_UP3 0x1E
284 #define MDIO_REG_BANK_REMOTE_PHY 0x8330
285 #define MDIO_REMOTE_PHY_MISC_RX_STATUS 0x10
286 #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG 0x0010
287 #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG 0x0600
289 #define MDIO_REG_BANK_BAM_NEXT_PAGE 0x8350
290 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10
291 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001
292 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002
294 #define MDIO_REG_BANK_CL73_USERB0 0x8370
295 #define MDIO_CL73_USERB0_CL73_UCTRL 0x10
296 #define MDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL 0x0002
297 #define MDIO_CL73_USERB0_CL73_USTAT1 0x11
298 #define MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK 0x0100
299 #define MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37 0x0400
300 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12
301 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000
302 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000
303 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000
304 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14
305 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001
307 #define MDIO_REG_BANK_AER_BLOCK 0xFFD0
308 #define MDIO_AER_BLOCK_AER_REG 0x1E
310 #define MDIO_REG_BANK_COMBO_IEEE0 0xFFE0
311 #define MDIO_COMBO_IEEE0_MII_CONTROL 0x10
312 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040
313 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000
314 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000
315 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040
316 #define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100
317 #define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200
318 #define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000
319 #define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000
320 #define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000
321 #define MDIO_COMBO_IEEE0_MII_STATUS 0x11
322 #define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004
323 #define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020
324 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV 0x14
325 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020
326 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040
327 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180
328 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000
329 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080
330 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100
331 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180
332 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000
333 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15
334 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000
335 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000
336 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180
337 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE 0x0000
338 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH 0x0180
339 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040
340 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020
341 /*WhenthelinkpartnerisinSGMIImode(bit0=1),then
342 bit15=link,bit12=duplex,bits11:10=speed,bit14=acknowledge.
343 Theotherbitsarereservedandshouldbezero*/
344 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001
346 #define MDIO_PMA_DEVAD 0x1
348 #define MDIO_PMA_REG_CTRL 0x0
349 #define MDIO_PMA_REG_STATUS 0x1
350 #define MDIO_PMA_REG_10G_CTRL2 0x7
351 #define MDIO_PMA_REG_TX_DISABLE 0x0009
352 #define MDIO_PMA_REG_RX_SD 0xa
354 #define MDIO_PMA_REG_BNX2X_CTRL 0x0096
355 #define MDIO_PMA_REG_FEC_CTRL 0x00ab
356 #define MDIO_PMA_LASI_RXCTRL 0x9000
357 #define MDIO_PMA_LASI_TXCTRL 0x9001
358 #define MDIO_PMA_LASI_CTRL 0x9002
359 #define MDIO_PMA_LASI_RXSTAT 0x9003
360 #define MDIO_PMA_LASI_TXSTAT 0x9004
361 #define MDIO_PMA_LASI_STAT 0x9005
362 #define MDIO_PMA_REG_PHY_IDENTIFIER 0xc800
363 #define MDIO_PMA_REG_DIGITAL_CTRL 0xc808
364 #define MDIO_PMA_REG_DIGITAL_STATUS 0xc809
365 #define MDIO_PMA_REG_TX_POWER_DOWN 0xca02
366 #define MDIO_PMA_REG_CMU_PLL_BYPASS 0xca09
367 #define MDIO_PMA_REG_MISC_CTRL 0xca0a
368 #define MDIO_PMA_REG_GEN_CTRL 0xca10
369 #define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188
370 #define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a
371 #define MDIO_PMA_REG_M8051_MSGIN_REG 0xca12
372 #define MDIO_PMA_REG_M8051_MSGOUT_REG 0xca13
373 #define MDIO_PMA_REG_ROM_VER1 0xca19
374 #define MDIO_PMA_REG_ROM_VER2 0xca1a
375 #define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b
376 #define MDIO_PMA_REG_PLL_BANDWIDTH 0xca1d
377 #define MDIO_PMA_REG_PLL_CTRL 0xca1e
378 #define MDIO_PMA_REG_MISC_CTRL0 0xca23
379 #define MDIO_PMA_REG_LRM_MODE 0xca3f
380 #define MDIO_PMA_REG_CDR_BANDWIDTH 0xca46
381 #define MDIO_PMA_REG_MISC_CTRL1 0xca85
383 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL 0x8000
384 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK 0x000c
385 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE 0x0000
386 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE 0x0004
387 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS 0x0008
388 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED 0x000c
389 #define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT 0x8002
390 #define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR 0x8003
391 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF 0xc820
392 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff
393 #define MDIO_PMA_REG_8726_TX_CTRL1 0xca01
394 #define MDIO_PMA_REG_8726_TX_CTRL2 0xca05
396 #define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR 0x8005
397 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF 0x8007
398 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff
399 #define MDIO_PMA_REG_8727_MISC_CTRL 0x8309
400 #define MDIO_PMA_REG_8727_TX_CTRL1 0xca02
401 #define MDIO_PMA_REG_8727_TX_CTRL2 0xca05
402 #define MDIO_PMA_REG_8727_PCS_OPT_CTRL 0xc808
403 #define MDIO_PMA_REG_8727_GPIO_CTRL 0xc80e
404 #define MDIO_PMA_REG_8727_PCS_GP 0xc842
405 #define MDIO_PMA_REG_8727_OPT_CFG_REG 0xc8e4
407 #define MDIO_AN_REG_8727_MISC_CTRL 0x8309
408 #define MDIO_PMA_REG_8073_CHIP_REV 0xc801
409 #define MDIO_PMA_REG_8073_SPEED_LINK_STATUS 0xc820
410 #define MDIO_PMA_REG_8073_XAUI_WA 0xc841
411 #define MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL 0xcd08
413 #define MDIO_PMA_REG_7101_RESET 0xc000
414 #define MDIO_PMA_REG_7107_LED_CNTL 0xc007
415 #define MDIO_PMA_REG_7107_LINK_LED_CNTL 0xc009
416 #define MDIO_PMA_REG_7101_VER1 0xc026
417 #define MDIO_PMA_REG_7101_VER2 0xc027
419 #define MDIO_PMA_REG_8481_PMD_SIGNAL 0xa811
420 #define MDIO_PMA_REG_8481_LED1_MASK 0xa82c
421 #define MDIO_PMA_REG_8481_LED2_MASK 0xa82f
422 #define MDIO_PMA_REG_8481_LED3_MASK 0xa832
423 #define MDIO_PMA_REG_8481_LED3_BLINK 0xa834
424 #define MDIO_PMA_REG_8481_LED5_MASK 0xa838
425 #define MDIO_PMA_REG_8481_SIGNAL_MASK 0xa835
426 #define MDIO_PMA_REG_8481_LINK_SIGNAL 0xa83b
427 #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK 0x800
428 #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT 11
430 #define MDIO_WIS_DEVAD 0x2
432 #define MDIO_WIS_REG_LASI_CNTL 0x9002
433 #define MDIO_WIS_REG_LASI_STATUS 0x9005
435 #define MDIO_PCS_DEVAD 0x3
436 #define MDIO_PCS_REG_STATUS 0x0020
437 #define MDIO_PCS_REG_LASI_STATUS 0x9005
438 #define MDIO_PCS_REG_7101_DSP_ACCESS 0xD000
439 #define MDIO_PCS_REG_7101_SPI_MUX 0xD008
440 #define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A
441 #define MDIO_PCS_REG_7101_SPI_RESET_BIT (5)
442 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A
443 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6)
444 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD (0xC7)
445 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2)
446 #define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028
448 #define MDIO_XS_DEVAD 0x4
449 #define MDIO_XS_REG_STATUS 0x0001
450 #define MDIO_XS_PLL_SEQUENCER 0x8000
451 #define MDIO_XS_SFX7101_XGXS_TEST1 0xc00a
453 #define MDIO_XS_8706_REG_BANK_RX0 0x80bc
454 #define MDIO_XS_8706_REG_BANK_RX1 0x80cc
455 #define MDIO_XS_8706_REG_BANK_RX2 0x80dc
456 #define MDIO_XS_8706_REG_BANK_RX3 0x80ec
457 #define MDIO_XS_8706_REG_BANK_RXA 0x80fc
459 #define MDIO_XS_REG_8073_RX_CTRL_PCIE 0x80FA
461 #define MDIO_AN_DEVAD 0x7
463 #define MDIO_AN_REG_CTRL 0x0000
464 #define MDIO_AN_REG_STATUS 0x0001
465 #define MDIO_AN_REG_STATUS_AN_COMPLETE 0x0020
466 #define MDIO_AN_REG_ADV_PAUSE 0x0010
467 #define MDIO_AN_REG_ADV_PAUSE_PAUSE 0x0400
468 #define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC 0x0800
469 #define MDIO_AN_REG_ADV_PAUSE_BOTH 0x0C00
470 #define MDIO_AN_REG_ADV_PAUSE_MASK 0x0C00
471 #define MDIO_AN_REG_ADV 0x0011
472 #define MDIO_AN_REG_ADV2 0x0012
473 #define MDIO_AN_REG_LP_AUTO_NEG 0x0013
474 #define MDIO_AN_REG_LP_AUTO_NEG2 0x0014
475 #define MDIO_AN_REG_MASTER_STATUS 0x0021
476 #define MDIO_AN_REG_EEE_ADV 0x003c
477 #define MDIO_AN_REG_LP_EEE_ADV 0x003d
479 #define MDIO_AN_REG_LINK_STATUS 0x8304
480 #define MDIO_AN_REG_CL37_CL73 0x8370
481 #define MDIO_AN_REG_CL37_AN 0xffe0
482 #define MDIO_AN_REG_CL37_FC_LD 0xffe4
483 #define MDIO_AN_REG_CL37_FC_LP 0xffe5
484 #define MDIO_AN_REG_1000T_STATUS 0xffea
486 #define MDIO_AN_REG_8073_2_5G 0x8329
487 #define MDIO_AN_REG_8073_BAM 0x8350
489 #define MDIO_AN_REG_8481_10GBASE_T_AN_CTRL 0x0020
490 #define MDIO_AN_REG_8481_LEGACY_MII_CTRL 0xffe0
491 #define MDIO_AN_REG_8481_MII_CTRL_FORCE_1G 0x40
492 #define MDIO_AN_REG_8481_LEGACY_MII_STATUS 0xffe1
493 #define MDIO_AN_REG_8481_LEGACY_AN_ADV 0xffe4
494 #define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION 0xffe6
495 #define MDIO_AN_REG_8481_1000T_CTRL 0xffe9
496 #define MDIO_AN_REG_8481_1G_100T_EXT_CTRL 0xfff0
497 #define MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF 0x0008
498 #define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW 0xfff5
499 #define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS 0xfff7
500 #define MDIO_AN_REG_8481_AUX_CTRL 0xfff8
501 #define MDIO_AN_REG_8481_LEGACY_SHADOW 0xfffc
503 /* BNX2X84823 only */
504 #define MDIO_CTL_DEVAD 0x1e
505 #define MDIO_CTL_REG_84823_MEDIA 0x401a
506 #define MDIO_CTL_REG_84823_MEDIA_MAC_MASK 0x0018
507 /* These pins configure the BNX2X84823 interface to MAC after reset. */
508 #define MDIO_CTL_REG_84823_CTRL_MAC_XFI 0x0008
509 #define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M 0x0010
510 /* These pins configure the BNX2X84823 interface to Line after reset. */
511 #define MDIO_CTL_REG_84823_MEDIA_LINE_MASK 0x0060
512 #define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L 0x0020
513 #define MDIO_CTL_REG_84823_MEDIA_LINE_XFI 0x0040
514 /* When this pin is active high during reset, 10GBASE-T core is power
515 * down, When it is active low the 10GBASE-T is power up
517 #define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN 0x0080
518 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK 0x0100
519 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER 0x0000
520 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER 0x0100
521 #define MDIO_CTL_REG_84823_MEDIA_FIBER_1G 0x1000
522 #define MDIO_CTL_REG_84823_USER_CTRL_REG 0x4005
523 #define MDIO_CTL_REG_84823_USER_CTRL_CMS 0x0080
524 #define MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH 0xa82b
525 #define MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ 0x2f
526 #define MDIO_PMA_REG_84823_CTL_LED_CTL_1 0xa8e3
527 #define MDIO_PMA_REG_84833_CTL_LED_CTL_1 0xa8ec
528 #define MDIO_PMA_REG_84823_LED3_STRETCH_EN 0x0080
530 /* BNX2X84833 only */
531 #define MDIO_84833_TOP_CFG_FW_REV 0x400f
532 #define MDIO_84833_TOP_CFG_FW_EEE 0x10b1
533 #define MDIO_84833_TOP_CFG_FW_NO_EEE 0x1f81
534 #define MDIO_84833_TOP_CFG_XGPHY_STRAP1 0x401a
535 #define MDIO_84833_SUPER_ISOLATE 0x8000
536 /* These are mailbox register set used by 84833. */
537 #define MDIO_84833_TOP_CFG_SCRATCH_REG0 0x4005
538 #define MDIO_84833_TOP_CFG_SCRATCH_REG1 0x4006
539 #define MDIO_84833_TOP_CFG_SCRATCH_REG2 0x4007
540 #define MDIO_84833_TOP_CFG_SCRATCH_REG3 0x4008
541 #define MDIO_84833_TOP_CFG_SCRATCH_REG4 0x4009
542 #define MDIO_84833_TOP_CFG_SCRATCH_REG26 0x4037
543 #define MDIO_84833_TOP_CFG_SCRATCH_REG27 0x4038
544 #define MDIO_84833_TOP_CFG_SCRATCH_REG28 0x4039
545 #define MDIO_84833_TOP_CFG_SCRATCH_REG29 0x403a
546 #define MDIO_84833_TOP_CFG_SCRATCH_REG30 0x403b
547 #define MDIO_84833_TOP_CFG_SCRATCH_REG31 0x403c
548 #define MDIO_84833_CMD_HDLR_COMMAND MDIO_84833_TOP_CFG_SCRATCH_REG0
549 #define MDIO_84833_CMD_HDLR_STATUS MDIO_84833_TOP_CFG_SCRATCH_REG26
550 #define MDIO_84833_CMD_HDLR_DATA1 MDIO_84833_TOP_CFG_SCRATCH_REG27
551 #define MDIO_84833_CMD_HDLR_DATA2 MDIO_84833_TOP_CFG_SCRATCH_REG28
552 #define MDIO_84833_CMD_HDLR_DATA3 MDIO_84833_TOP_CFG_SCRATCH_REG29
553 #define MDIO_84833_CMD_HDLR_DATA4 MDIO_84833_TOP_CFG_SCRATCH_REG30
554 #define MDIO_84833_CMD_HDLR_DATA5 MDIO_84833_TOP_CFG_SCRATCH_REG31
556 /* Mailbox command set used by 84833. */
557 #define PHY84833_CMD_SET_PAIR_SWAP 0x8001
558 #define PHY84833_CMD_GET_EEE_MODE 0x8008
559 #define PHY84833_CMD_SET_EEE_MODE 0x8009
560 #define PHY84833_CMD_GET_CURRENT_TEMP 0x8031
561 /* Mailbox status set used by 84833. */
562 #define PHY84833_STATUS_CMD_RECEIVED 0x0001
563 #define PHY84833_STATUS_CMD_IN_PROGRESS 0x0002
564 #define PHY84833_STATUS_CMD_COMPLETE_PASS 0x0004
565 #define PHY84833_STATUS_CMD_COMPLETE_ERROR 0x0008
566 #define PHY84833_STATUS_CMD_OPEN_FOR_CMDS 0x0010
567 #define PHY84833_STATUS_CMD_SYSTEM_BOOT 0x0020
568 #define PHY84833_STATUS_CMD_NOT_OPEN_FOR_CMDS 0x0040
569 #define PHY84833_STATUS_CMD_CLEAR_COMPLETE 0x0080
570 #define PHY84833_STATUS_CMD_OPEN_OVERRIDE 0xa5a5
572 /* Warpcore clause 45 addressing */
573 #define MDIO_WC_DEVAD 0x3
574 #define MDIO_WC_REG_IEEE0BLK_MIICNTL 0x0
575 #define MDIO_WC_REG_IEEE0BLK_AUTONEGNP 0x7
576 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT0 0x10
577 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1 0x11
578 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2 0x12
579 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY 0x4000
580 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ 0x8000
581 #define MDIO_WC_REG_PCS_STATUS2 0x0021
582 #define MDIO_WC_REG_PMD_KR_CONTROL 0x0096
583 #define MDIO_WC_REG_XGXSBLK0_XGXSCONTROL 0x8000
584 #define MDIO_WC_REG_XGXSBLK0_MISCCONTROL1 0x800e
585 #define MDIO_WC_REG_XGXSBLK1_DESKEW 0x8010
586 #define MDIO_WC_REG_XGXSBLK1_LANECTRL0 0x8015
587 #define MDIO_WC_REG_XGXSBLK1_LANECTRL1 0x8016
588 #define MDIO_WC_REG_XGXSBLK1_LANECTRL2 0x8017
589 #define MDIO_WC_REG_XGXSBLK1_LANECTRL3 0x8018
590 #define MDIO_WC_REG_XGXSBLK1_LANETEST0 0x801a
591 #define MDIO_WC_REG_TX0_ANA_CTRL0 0x8061
592 #define MDIO_WC_REG_TX1_ANA_CTRL0 0x8071
593 #define MDIO_WC_REG_TX2_ANA_CTRL0 0x8081
594 #define MDIO_WC_REG_TX3_ANA_CTRL0 0x8091
595 #define MDIO_WC_REG_TX0_TX_DRIVER 0x8067
596 #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET 0x04
597 #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_MASK 0x00f0
598 #define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET 0x08
599 #define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
600 #define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET 0x0c
601 #define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_MASK 0x7000
602 #define MDIO_WC_REG_TX1_TX_DRIVER 0x8077
603 #define MDIO_WC_REG_TX2_TX_DRIVER 0x8087
604 #define MDIO_WC_REG_TX3_TX_DRIVER 0x8097
605 #define MDIO_WC_REG_RX0_ANARXCONTROL1G 0x80b9
606 #define MDIO_WC_REG_RX2_ANARXCONTROL1G 0x80d9
607 #define MDIO_WC_REG_RX0_PCI_CTRL 0x80ba
608 #define MDIO_WC_REG_RX1_PCI_CTRL 0x80ca
609 #define MDIO_WC_REG_RX2_PCI_CTRL 0x80da
610 #define MDIO_WC_REG_RX3_PCI_CTRL 0x80ea
611 #define MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G 0x8104
612 #define MDIO_WC_REG_XGXS_STATUS3 0x8129
613 #define MDIO_WC_REG_PAR_DET_10G_STATUS 0x8130
614 #define MDIO_WC_REG_PAR_DET_10G_CTRL 0x8131
615 #define MDIO_WC_REG_XGXS_STATUS4 0x813c
616 #define MDIO_WC_REG_XGXS_X2_CONTROL2 0x8141
617 #define MDIO_WC_REG_XGXS_X2_CONTROL3 0x8142
618 #define MDIO_WC_REG_XGXS_RX_LN_SWAP1 0x816B
619 #define MDIO_WC_REG_XGXS_TX_LN_SWAP1 0x8169
620 #define MDIO_WC_REG_GP2_STATUS_GP_2_0 0x81d0
621 #define MDIO_WC_REG_GP2_STATUS_GP_2_1 0x81d1
622 #define MDIO_WC_REG_GP2_STATUS_GP_2_2 0x81d2
623 #define MDIO_WC_REG_GP2_STATUS_GP_2_3 0x81d3
624 #define MDIO_WC_REG_GP2_STATUS_GP_2_4 0x81d4
625 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL 0x1000
626 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CMPL 0x0100
627 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP 0x0010
628 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CAP 0x1
629 #define MDIO_WC_REG_UC_INFO_B0_DEAD_TRAP 0x81EE
630 #define MDIO_WC_REG_UC_INFO_B1_VERSION 0x81F0
631 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE 0x81F2
632 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE0_OFFSET 0x0
633 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT 0x0
634 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_OPT_LR 0x1
635 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC 0x2
636 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_XLAUI 0x3
637 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_LONG_CH_6G 0x4
638 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE1_OFFSET 0x4
639 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE2_OFFSET 0x8
640 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE3_OFFSET 0xc
641 #define MDIO_WC_REG_UC_INFO_B1_CRC 0x81FE
642 #define MDIO_WC_REG_DSC1B0_UC_CTRL 0x820e
643 #define MDIO_WC_REG_DSC1B0_UC_CTRL_RDY4CMD (1<<7)
644 #define MDIO_WC_REG_DSC_SMC 0x8213
645 #define MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0 0x821e
646 #define MDIO_WC_REG_TX_FIR_TAP 0x82e2
647 #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET 0x00
648 #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_MASK 0x000f
649 #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET 0x04
650 #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_MASK 0x03f0
651 #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET 0x0a
652 #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_MASK 0x7c00
653 #define MDIO_WC_REG_TX_FIR_TAP_ENABLE 0x8000
654 #define MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP 0x82e2
655 #define MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL 0x82e3
656 #define MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL 0x82e6
657 #define MDIO_WC_REG_CL72_USERB0_CL72_BR_DEF_CTRL 0x82e7
658 #define MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL 0x82e8
659 #define MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL 0x82ec
660 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1 0x8300
661 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2 0x8301
662 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3 0x8302
663 #define MDIO_WC_REG_SERDESDIGITAL_STATUS1000X1 0x8304
664 #define MDIO_WC_REG_SERDESDIGITAL_MISC1 0x8308
665 #define MDIO_WC_REG_SERDESDIGITAL_MISC2 0x8309
666 #define MDIO_WC_REG_DIGITAL3_UP1 0x8329
667 #define MDIO_WC_REG_DIGITAL3_LP_UP1 0x832c
668 #define MDIO_WC_REG_DIGITAL4_MISC3 0x833c
669 #define MDIO_WC_REG_DIGITAL4_MISC5 0x833e
670 #define MDIO_WC_REG_DIGITAL5_MISC6 0x8345
671 #define MDIO_WC_REG_DIGITAL5_MISC7 0x8349
672 #define MDIO_WC_REG_DIGITAL5_LINK_STATUS 0x834d
673 #define MDIO_WC_REG_DIGITAL5_ACTUAL_SPEED 0x834e
674 #define MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL 0x8350
675 #define MDIO_WC_REG_CL49_USERB0_CTRL 0x8368
676 #define MDIO_WC_REG_CL73_USERB0_CTRL 0x8370
677 #define MDIO_WC_REG_CL73_USERB0_USTAT 0x8371
678 #define MDIO_WC_REG_CL73_BAM_CTRL1 0x8372
679 #define MDIO_WC_REG_CL73_BAM_CTRL2 0x8373
680 #define MDIO_WC_REG_CL73_BAM_CTRL3 0x8374
681 #define MDIO_WC_REG_CL73_BAM_CODE_FIELD 0x837b
682 #define MDIO_WC_REG_EEE_COMBO_CONTROL0 0x8390
683 #define MDIO_WC_REG_TX66_CONTROL 0x83b0
684 #define MDIO_WC_REG_RX66_CONTROL 0x83c0
685 #define MDIO_WC_REG_RX66_SCW0 0x83c2
686 #define MDIO_WC_REG_RX66_SCW1 0x83c3
687 #define MDIO_WC_REG_RX66_SCW2 0x83c4
688 #define MDIO_WC_REG_RX66_SCW3 0x83c5
689 #define MDIO_WC_REG_RX66_SCW0_MASK 0x83c6
690 #define MDIO_WC_REG_RX66_SCW1_MASK 0x83c7
691 #define MDIO_WC_REG_RX66_SCW2_MASK 0x83c8
692 #define MDIO_WC_REG_RX66_SCW3_MASK 0x83c9
693 #define MDIO_WC_REG_FX100_CTRL1 0x8400
694 #define MDIO_WC_REG_FX100_CTRL3 0x8402
695 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL5 0x8436
696 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL6 0x8437
697 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL7 0x8438
698 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL9 0x8439
699 #define MDIO_WC_REG_CL82_USERB1_RX_CTRL10 0x843a
700 #define MDIO_WC_REG_CL82_USERB1_RX_CTRL11 0x843b
701 #define MDIO_WC_REG_ETA_CL73_OUI1 0x8453
702 #define MDIO_WC_REG_ETA_CL73_OUI2 0x8454
703 #define MDIO_WC_REG_ETA_CL73_OUI3 0x8455
704 #define MDIO_WC_REG_ETA_CL73_LD_BAM_CODE 0x8456
705 #define MDIO_WC_REG_ETA_CL73_LD_UD_CODE 0x8457
706 #define MDIO_WC_REG_MICROBLK_CMD 0xffc2
707 #define MDIO_WC_REG_MICROBLK_DL_STATUS 0xffc5
708 #define MDIO_WC_REG_MICROBLK_CMD3 0xffcc
710 #define MDIO_WC_REG_AERBLK_AER 0xffde
711 #define MDIO_WC_REG_COMBO_IEEE0_MIICTRL 0xffe0
712 #define MDIO_WC_REG_COMBO_IEEE0_MIIISTAT 0xffe1
714 #define MDIO_WC0_XGXS_BLK2_LANE_RESET 0x810A
715 #define MDIO_WC0_XGXS_BLK2_LANE_RESET_RX_BITSHIFT 0
716 #define MDIO_WC0_XGXS_BLK2_LANE_RESET_TX_BITSHIFT 4
718 #define MDIO_WC0_XGXS_BLK6_XGXS_X2_CONTROL2 0x8141
720 #define DIGITAL5_ACTUAL_SPEED_TX_MASK 0x003f
723 #define MDIO_REG_GPHY_MII_STATUS 0x1
724 #define MDIO_REG_GPHY_PHYID_LSB 0x3
725 #define MDIO_REG_GPHY_CL45_ADDR_REG 0xd
726 #define MDIO_REG_GPHY_CL45_REG_WRITE 0x4000
727 #define MDIO_REG_GPHY_CL45_REG_READ 0xc000
728 #define MDIO_REG_GPHY_CL45_DATA_REG 0xe
729 #define MDIO_REG_GPHY_EEE_RESOLVED 0x803e
730 #define MDIO_REG_GPHY_EXP_ACCESS_GATE 0x15
731 #define MDIO_REG_GPHY_EXP_ACCESS 0x17
732 #define MDIO_REG_GPHY_EXP_ACCESS_TOP 0xd00
733 #define MDIO_REG_GPHY_EXP_TOP_2K_BUF 0x40
734 #define MDIO_REG_GPHY_AUX_STATUS 0x19
735 #define MDIO_REG_INTR_STATUS 0x1a
736 #define MDIO_REG_INTR_MASK 0x1b
737 #define MDIO_REG_INTR_MASK_LINK_STATUS (0x1 << 1)
738 #define MDIO_REG_GPHY_SHADOW 0x1c
739 #define MDIO_REG_GPHY_SHADOW_LED_SEL1 (0x0d << 10)
740 #define MDIO_REG_GPHY_SHADOW_LED_SEL2 (0x0e << 10)
741 #define MDIO_REG_GPHY_SHADOW_WR_ENA (0x1 << 15)
742 #define MDIO_REG_GPHY_SHADOW_AUTO_DET_MED (0x1e << 10)
743 #define MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD (0x1 << 8)
745 typedef elink_status_t(*read_sfp_module_eeprom_func_p) (struct elink_phy * phy,
746 struct elink_params *
753 /********************************************************/
754 #define ELINK_ETH_HLEN 14
755 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
756 #define ELINK_ETH_OVREHEAD (ELINK_ETH_HLEN + 8 + 8)
757 #define ELINK_ETH_MIN_PACKET_SIZE 60
758 #define ELINK_ETH_MAX_PACKET_SIZE 1500
759 #define ELINK_ETH_MAX_JUMBO_PACKET_SIZE 9600
760 #define ELINK_MDIO_ACCESS_TIMEOUT 1000
761 #define WC_LANE_MAX 4
762 #define I2C_SWITCH_WIDTH 2
765 #define I2C_WA_RETRY_CNT 3
766 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1)
767 #define MCPR_IMC_COMMAND_READ_OP 1
768 #define MCPR_IMC_COMMAND_WRITE_OP 2
770 /* LED Blink rate that will achieve ~15.9Hz */
771 #define LED_BLINK_RATE_VAL_E3 354
772 #define LED_BLINK_RATE_VAL_E1X_E2 480
773 /***********************************************************/
774 /* Shortcut definitions */
775 /***********************************************************/
777 #define ELINK_NIG_LATCH_BC_ENABLE_MI_INT 0
779 #define ELINK_NIG_STATUS_EMAC0_MI_INT \
780 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
781 #define ELINK_NIG_STATUS_XGXS0_LINK10G \
782 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
783 #define ELINK_NIG_STATUS_XGXS0_LINK_STATUS \
784 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
785 #define ELINK_NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
786 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
787 #define ELINK_NIG_STATUS_SERDES0_LINK_STATUS \
788 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
789 #define ELINK_NIG_MASK_MI_INT \
790 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
791 #define ELINK_NIG_MASK_XGXS0_LINK10G \
792 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
793 #define ELINK_NIG_MASK_XGXS0_LINK_STATUS \
794 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
795 #define ELINK_NIG_MASK_SERDES0_LINK_STATUS \
796 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
798 #define ELINK_MDIO_AN_CL73_OR_37_COMPLETE \
799 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
800 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
802 #define ELINK_XGXS_RESET_BITS \
803 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
804 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
805 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
806 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
807 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
809 #define ELINK_SERDES_RESET_BITS \
810 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
811 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
812 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
813 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
815 #define ELINK_AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
816 #define ELINK_AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
817 #define ELINK_AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
818 #define ELINK_AUTONEG_PARALLEL \
819 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
820 #define ELINK_AUTONEG_SGMII_FIBER_AUTODET \
821 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
822 #define ELINK_AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
824 #define ELINK_GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
825 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
826 #define ELINK_GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
827 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
828 #define ELINK_GP_STATUS_SPEED_MASK \
829 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
830 #define ELINK_GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
831 #define ELINK_GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
832 #define ELINK_GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
833 #define ELINK_GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
834 #define ELINK_GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
835 #define ELINK_GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
836 #define ELINK_GP_STATUS_10G_HIG \
837 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
838 #define ELINK_GP_STATUS_10G_CX4 \
839 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
840 #define ELINK_GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
841 #define ELINK_GP_STATUS_10G_KX4 \
842 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
843 #define ELINK_GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR
844 #define ELINK_GP_STATUS_10G_XFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI
845 #define ELINK_GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS
846 #define ELINK_GP_STATUS_10G_SFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI
847 #define ELINK_GP_STATUS_20G_KR2 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2
848 #define ELINK_LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
849 #define ELINK_LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
850 #define ELINK_LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
851 #define ELINK_LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
852 #define ELINK_LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
853 #define ELINK_LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
854 #define ELINK_LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
855 #define ELINK_LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
856 #define ELINK_LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
857 #define ELINK_LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
858 #define ELINK_LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
859 #define ELINK_LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
860 #define ELINK_LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
861 #define ELINK_LINK_20GTFD LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
862 #define ELINK_LINK_20GXFD LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
864 #define ELINK_LINK_UPDATE_MASK \
865 (LINK_STATUS_SPEED_AND_DUPLEX_MASK | \
866 LINK_STATUS_LINK_UP | \
867 LINK_STATUS_PHYSICAL_LINK_FLAG | \
868 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE | \
869 LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK | \
870 LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK | \
871 LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK | \
872 LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE | \
873 LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
875 #define ELINK_SFP_EEPROM_CON_TYPE_ADDR 0x2
876 #define ELINK_SFP_EEPROM_CON_TYPE_VAL_LC 0x7
877 #define ELINK_SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
878 #define ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45 0x22
880 #define ELINK_SFP_EEPROM_COMP_CODE_ADDR 0x3
881 #define ELINK_SFP_EEPROM_COMP_CODE_SR_MASK (1<<4)
882 #define ELINK_SFP_EEPROM_COMP_CODE_LR_MASK (1<<5)
883 #define ELINK_SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6)
885 #define ELINK_SFP_EEPROM_FC_TX_TECH_ADDR 0x8
886 #define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
887 #define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
889 #define ELINK_SFP_EEPROM_OPTIONS_ADDR 0x40
890 #define ELINK_SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
891 #define ELINK_SFP_EEPROM_OPTIONS_SIZE 2
893 #define ELINK_EDC_MODE_LINEAR 0x0022
894 #define ELINK_EDC_MODE_LIMITING 0x0044
895 #define ELINK_EDC_MODE_PASSIVE_DAC 0x0055
896 #define ELINK_EDC_MODE_ACTIVE_DAC 0x0066
899 #define DCBX_INVALID_COS (0xFF)
901 #define ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000)
902 #define ELINK_ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000)
903 #define ELINK_ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS (1360)
904 #define ELINK_ETS_E3B0_NIG_MIN_W_VAL_20GBPS (2720)
905 #define ELINK_ETS_E3B0_PBF_MIN_W_VAL (10000)
907 #define ELINK_MAX_PACKET_SIZE (9700)
908 #define MAX_KR_LINK_RETRY 4
910 /**********************************************************/
912 /**********************************************************/
914 #define CL22_WR_OVER_CL45(_sc, _phy, _bank, _addr, _val) \
915 elink_cl45_write(_sc, _phy, \
916 (_phy)->def_md_devad, \
917 (_bank + (_addr & 0xf)), \
920 #define CL22_RD_OVER_CL45(_sc, _phy, _bank, _addr, _val) \
921 elink_cl45_read(_sc, _phy, \
922 (_phy)->def_md_devad, \
923 (_bank + (_addr & 0xf)), \
926 static uint32_t elink_bits_en(struct bnx2x_softc *sc, uint32_t reg, uint32_t bits)
928 uint32_t val = REG_RD(sc, reg);
931 REG_WR(sc, reg, val);
935 static uint32_t elink_bits_dis(struct bnx2x_softc *sc, uint32_t reg,
938 uint32_t val = REG_RD(sc, reg);
941 REG_WR(sc, reg, val);
946 * elink_check_lfa - This function checks if link reinitialization is required,
947 * or link flap can be avoided.
949 * @params: link parameters
950 * Returns 0 if Link Flap Avoidance conditions are met otherwise, the failed
953 static int elink_check_lfa(struct elink_params *params)
955 uint32_t link_status, cfg_idx, lfa_mask, cfg_size;
956 uint32_t cur_speed_cap_mask, cur_req_fc_auto_adv, additional_config;
957 uint32_t saved_val, req_val, eee_status;
958 struct bnx2x_softc *sc = params->sc;
961 REG_RD(sc, params->lfa_base +
962 offsetof(struct shmem_lfa, additional_config));
964 /* NOTE: must be first condition checked -
965 * to verify DCC bit is cleared in any case!
967 if (additional_config & NO_LFA_DUE_TO_DCC_MASK) {
968 PMD_DRV_LOG(DEBUG, "No LFA due to DCC flap after clp exit");
969 REG_WR(sc, params->lfa_base +
970 offsetof(struct shmem_lfa, additional_config),
971 additional_config & ~NO_LFA_DUE_TO_DCC_MASK);
972 return LFA_DCC_LFA_DISABLED;
975 /* Verify that link is up */
976 link_status = REG_RD(sc, params->shmem_base +
977 offsetof(struct shmem_region,
978 port_mb[params->port].link_status));
979 if (!(link_status & LINK_STATUS_LINK_UP))
980 return LFA_LINK_DOWN;
982 /* if loaded after BOOT from SAN, don't flap the link in any case and
983 * rely on link set by preboot driver
985 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_BOOT_FROM_SAN)
988 /* Verify that loopback mode is not set */
989 if (params->loopback_mode)
990 return LFA_LOOPBACK_ENABLED;
992 /* Verify that MFW supports LFA */
993 if (!params->lfa_base)
994 return LFA_MFW_IS_TOO_OLD;
996 if (params->num_phys == 3) {
998 lfa_mask = 0xffffffff;
1004 /* Compare Duplex */
1005 saved_val = REG_RD(sc, params->lfa_base +
1006 offsetof(struct shmem_lfa, req_duplex));
1007 req_val = params->req_duplex[0] | (params->req_duplex[1] << 16);
1008 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
1009 PMD_DRV_LOG(INFO, "Duplex mismatch %x vs. %x",
1010 (saved_val & lfa_mask), (req_val & lfa_mask));
1011 return LFA_DUPLEX_MISMATCH;
1013 /* Compare Flow Control */
1014 saved_val = REG_RD(sc, params->lfa_base +
1015 offsetof(struct shmem_lfa, req_flow_ctrl));
1016 req_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16);
1017 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
1018 PMD_DRV_LOG(DEBUG, "Flow control mismatch %x vs. %x",
1019 (saved_val & lfa_mask), (req_val & lfa_mask));
1020 return LFA_FLOW_CTRL_MISMATCH;
1022 /* Compare Link Speed */
1023 saved_val = REG_RD(sc, params->lfa_base +
1024 offsetof(struct shmem_lfa, req_line_speed));
1025 req_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16);
1026 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
1027 PMD_DRV_LOG(DEBUG, "Link speed mismatch %x vs. %x",
1028 (saved_val & lfa_mask), (req_val & lfa_mask));
1029 return LFA_LINK_SPEED_MISMATCH;
1032 for (cfg_idx = 0; cfg_idx < cfg_size; cfg_idx++) {
1033 cur_speed_cap_mask = REG_RD(sc, params->lfa_base +
1034 offsetof(struct shmem_lfa,
1035 speed_cap_mask[cfg_idx]));
1037 if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) {
1038 PMD_DRV_LOG(DEBUG, "Speed Cap mismatch %x vs. %x",
1040 params->speed_cap_mask[cfg_idx]);
1041 return LFA_SPEED_CAP_MISMATCH;
1045 cur_req_fc_auto_adv =
1046 REG_RD(sc, params->lfa_base +
1047 offsetof(struct shmem_lfa, additional_config)) &
1048 REQ_FC_AUTO_ADV_MASK;
1050 if ((uint16_t) cur_req_fc_auto_adv != params->req_fc_auto_adv) {
1051 PMD_DRV_LOG(DEBUG, "Flow Ctrl AN mismatch %x vs. %x",
1052 cur_req_fc_auto_adv, params->req_fc_auto_adv);
1053 return LFA_FLOW_CTRL_MISMATCH;
1056 eee_status = REG_RD(sc, params->shmem2_base +
1057 offsetof(struct shmem2_region,
1058 eee_status[params->port]));
1060 if (((eee_status & SHMEM_EEE_LPI_REQUESTED_BIT) ^
1061 (params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI)) ||
1062 ((eee_status & SHMEM_EEE_REQUESTED_BIT) ^
1063 (params->eee_mode & ELINK_EEE_MODE_ADV_LPI))) {
1064 PMD_DRV_LOG(DEBUG, "EEE mismatch %x vs. %x", params->eee_mode,
1066 return LFA_EEE_MISMATCH;
1069 /* LFA conditions are met */
1073 /******************************************************************/
1074 /* EPIO/GPIO section */
1075 /******************************************************************/
1076 static void elink_get_epio(struct bnx2x_softc *sc, uint32_t epio_pin,
1079 uint32_t epio_mask, gp_oenable;
1082 if (epio_pin > 31) {
1083 PMD_DRV_LOG(DEBUG, "Invalid EPIO pin %d to get", epio_pin);
1087 epio_mask = 1 << epio_pin;
1088 /* Set this EPIO to output */
1089 gp_oenable = REG_RD(sc, MCP_REG_MCPR_GP_OENABLE);
1090 REG_WR(sc, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask);
1092 *en = (REG_RD(sc, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;
1095 static void elink_set_epio(struct bnx2x_softc *sc, uint32_t epio_pin, uint32_t en)
1097 uint32_t epio_mask, gp_output, gp_oenable;
1100 if (epio_pin > 31) {
1101 PMD_DRV_LOG(DEBUG, "Invalid EPIO pin %d to set", epio_pin);
1104 PMD_DRV_LOG(DEBUG, "Setting EPIO pin %d to %d", epio_pin, en);
1105 epio_mask = 1 << epio_pin;
1106 /* Set this EPIO to output */
1107 gp_output = REG_RD(sc, MCP_REG_MCPR_GP_OUTPUTS);
1109 gp_output |= epio_mask;
1111 gp_output &= ~epio_mask;
1113 REG_WR(sc, MCP_REG_MCPR_GP_OUTPUTS, gp_output);
1115 /* Set the value for this EPIO */
1116 gp_oenable = REG_RD(sc, MCP_REG_MCPR_GP_OENABLE);
1117 REG_WR(sc, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask);
1120 static void elink_set_cfg_pin(struct bnx2x_softc *sc, uint32_t pin_cfg,
1123 if (pin_cfg == PIN_CFG_NA)
1125 if (pin_cfg >= PIN_CFG_EPIO0) {
1126 elink_set_epio(sc, pin_cfg - PIN_CFG_EPIO0, val);
1128 uint8_t gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
1129 uint8_t gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
1130 elink_cb_gpio_write(sc, gpio_num, (uint8_t) val, gpio_port);
1134 static uint32_t elink_get_cfg_pin(struct bnx2x_softc *sc, uint32_t pin_cfg,
1137 if (pin_cfg == PIN_CFG_NA)
1138 return ELINK_STATUS_ERROR;
1139 if (pin_cfg >= PIN_CFG_EPIO0) {
1140 elink_get_epio(sc, pin_cfg - PIN_CFG_EPIO0, val);
1142 uint8_t gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
1143 uint8_t gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
1144 *val = elink_cb_gpio_read(sc, gpio_num, gpio_port);
1146 return ELINK_STATUS_OK;
1150 /******************************************************************/
1152 /******************************************************************/
1153 static void elink_update_pfc_xmac(struct elink_params *params,
1154 struct elink_vars *vars)
1156 struct bnx2x_softc *sc = params->sc;
1158 uint32_t pause_val, pfc0_val, pfc1_val;
1160 /* XMAC base adrr */
1161 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1163 /* Initialize pause and pfc registers */
1164 pause_val = 0x18000;
1165 pfc0_val = 0xFFFF8000;
1168 /* No PFC support */
1169 if (!(params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)) {
1171 /* RX flow control - Process pause frame in receive direction
1173 if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)
1174 pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN;
1176 /* TX flow control - Send pause packet when buffer is full */
1177 if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)
1178 pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;
1179 } else { /* PFC support */
1180 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN |
1181 XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
1182 XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
1183 XMAC_PFC_CTRL_HI_REG_TX_PFC_EN |
1184 XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1185 /* Write pause and PFC registers */
1186 REG_WR(sc, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1187 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1188 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1189 pfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1193 /* Write pause and PFC registers */
1194 REG_WR(sc, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1195 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1196 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1198 /* Set MAC address for source TX Pause/PFC frames */
1199 REG_WR(sc, xmac_base + XMAC_REG_CTRL_SA_LO,
1200 ((params->mac_addr[2] << 24) |
1201 (params->mac_addr[3] << 16) |
1202 (params->mac_addr[4] << 8) | (params->mac_addr[5])));
1203 REG_WR(sc, xmac_base + XMAC_REG_CTRL_SA_HI,
1204 ((params->mac_addr[0] << 8) | (params->mac_addr[1])));
1209 /******************************************************************/
1210 /* MAC/PBF section */
1211 /******************************************************************/
1212 static void elink_set_mdio_clk(struct bnx2x_softc *sc, uint32_t emac_base)
1214 uint32_t new_mode, cur_mode;
1216 /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1217 * (a value of 49==0x31) and make sure that the AUTO poll is off
1219 cur_mode = REG_RD(sc, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1221 if (USES_WARPCORE(sc))
1222 clc_cnt = 74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
1224 clc_cnt = 49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
1226 if (((cur_mode & EMAC_MDIO_MODE_CLOCK_CNT) == clc_cnt) &&
1227 (cur_mode & (EMAC_MDIO_MODE_CLAUSE_45)))
1230 new_mode = cur_mode &
1231 ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT);
1232 new_mode |= clc_cnt;
1233 new_mode |= (EMAC_MDIO_MODE_CLAUSE_45);
1235 PMD_DRV_LOG(DEBUG, "Changing emac_mode from 0x%x to 0x%x",
1236 cur_mode, new_mode);
1237 REG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode);
1241 static void elink_set_mdio_emac_per_phy(struct bnx2x_softc *sc,
1242 struct elink_params *params)
1245 /* Set mdio clock per phy */
1246 for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys;
1248 elink_set_mdio_clk(sc, params->phy[phy_index].mdio_ctrl);
1251 static uint8_t elink_is_4_port_mode(struct bnx2x_softc *sc)
1253 uint32_t port4mode_ovwr_val;
1254 /* Check 4-port override enabled */
1255 port4mode_ovwr_val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);
1256 if (port4mode_ovwr_val & (1 << 0)) {
1257 /* Return 4-port mode override value */
1258 return ((port4mode_ovwr_val & (1 << 1)) == (1 << 1));
1260 /* Return 4-port mode from input pin */
1261 return (uint8_t) REG_RD(sc, MISC_REG_PORT4MODE_EN);
1264 static void elink_emac_init(struct elink_params *params)
1266 /* reset and unreset the emac core */
1267 struct bnx2x_softc *sc = params->sc;
1268 uint8_t port = params->port;
1269 uint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1273 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1274 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1276 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1277 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1279 /* init emac - use read-modify-write */
1280 /* self clear reset */
1281 val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);
1282 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MODE,
1283 (val | EMAC_MODE_RESET));
1287 val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);
1288 PMD_DRV_LOG(DEBUG, "EMAC reset reg is %u", val);
1290 PMD_DRV_LOG(DEBUG, "EMAC timeout!");
1294 } while (val & EMAC_MODE_RESET);
1296 elink_set_mdio_emac_per_phy(sc, params);
1297 /* Set mac address */
1298 val = ((params->mac_addr[0] << 8) | params->mac_addr[1]);
1299 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MAC_MATCH, val);
1301 val = ((params->mac_addr[2] << 24) |
1302 (params->mac_addr[3] << 16) |
1303 (params->mac_addr[4] << 8) | params->mac_addr[5]);
1304 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MAC_MATCH + 4, val);
1307 static void elink_set_xumac_nig(struct elink_params *params,
1308 uint16_t tx_pause_en, uint8_t enable)
1310 struct bnx2x_softc *sc = params->sc;
1312 REG_WR(sc, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
1314 REG_WR(sc, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
1316 REG_WR(sc, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
1317 NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en);
1320 static void elink_set_umac_rxtx(struct elink_params *params, uint8_t en)
1322 uint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1324 struct bnx2x_softc *sc = params->sc;
1325 if (!(REG_RD(sc, MISC_REG_RESET_REG_2) &
1326 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)))
1328 val = REG_RD(sc, umac_base + UMAC_REG_COMMAND_CONFIG);
1330 val |= (UMAC_COMMAND_CONFIG_REG_TX_ENA |
1331 UMAC_COMMAND_CONFIG_REG_RX_ENA);
1333 val &= ~(UMAC_COMMAND_CONFIG_REG_TX_ENA |
1334 UMAC_COMMAND_CONFIG_REG_RX_ENA);
1335 /* Disable RX and TX */
1336 REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1339 static void elink_umac_enable(struct elink_params *params,
1340 struct elink_vars *vars, uint8_t lb)
1343 uint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1344 struct bnx2x_softc *sc = params->sc;
1346 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1347 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1350 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1351 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1353 PMD_DRV_LOG(DEBUG, "enabling UMAC");
1355 /* This register opens the gate for the UMAC despite its name */
1356 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port * 4, 1);
1358 val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN |
1359 UMAC_COMMAND_CONFIG_REG_PAD_EN |
1360 UMAC_COMMAND_CONFIG_REG_SW_RESET |
1361 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
1362 switch (vars->line_speed) {
1363 case ELINK_SPEED_10:
1366 case ELINK_SPEED_100:
1369 case ELINK_SPEED_1000:
1372 case ELINK_SPEED_2500:
1376 PMD_DRV_LOG(DEBUG, "Invalid speed for UMAC %d",
1380 if (!(vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
1381 val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE;
1383 if (!(vars->flow_ctrl & ELINK_FLOW_CTRL_RX))
1384 val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE;
1386 if (vars->duplex == DUPLEX_HALF)
1387 val |= UMAC_COMMAND_CONFIG_REG_HD_ENA;
1389 REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1392 /* Configure UMAC for EEE */
1393 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
1394 PMD_DRV_LOG(DEBUG, "configured UMAC for EEE");
1395 REG_WR(sc, umac_base + UMAC_REG_UMAC_EEE_CTRL,
1396 UMAC_UMAC_EEE_CTRL_REG_EEE_EN);
1397 REG_WR(sc, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11);
1399 REG_WR(sc, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0);
1402 /* Set MAC address for source TX Pause/PFC frames (under SW reset) */
1403 REG_WR(sc, umac_base + UMAC_REG_MAC_ADDR0,
1404 ((params->mac_addr[2] << 24) |
1405 (params->mac_addr[3] << 16) |
1406 (params->mac_addr[4] << 8) | (params->mac_addr[5])));
1407 REG_WR(sc, umac_base + UMAC_REG_MAC_ADDR1,
1408 ((params->mac_addr[0] << 8) | (params->mac_addr[1])));
1410 /* Enable RX and TX */
1411 val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN;
1412 val |= UMAC_COMMAND_CONFIG_REG_TX_ENA | UMAC_COMMAND_CONFIG_REG_RX_ENA;
1413 REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1416 /* Remove SW Reset */
1417 val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET;
1419 /* Check loopback mode */
1421 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA;
1422 REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1424 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
1425 * length used by the MAC receive logic to check frames.
1427 REG_WR(sc, umac_base + UMAC_REG_MAXFR, 0x2710);
1428 elink_set_xumac_nig(params,
1429 ((vars->flow_ctrl & ELINK_FLOW_CTRL_TX) != 0), 1);
1430 vars->mac_type = ELINK_MAC_TYPE_UMAC;
1434 /* Define the XMAC mode */
1435 static void elink_xmac_init(struct elink_params *params, uint32_t max_speed)
1437 struct bnx2x_softc *sc = params->sc;
1438 uint32_t is_port4mode = elink_is_4_port_mode(sc);
1440 /* In 4-port mode, need to set the mode only once, so if XMAC is
1441 * already out of reset, it means the mode has already been set,
1442 * and it must not* reset the XMAC again, since it controls both
1446 if (((CHIP_NUM(sc) == CHIP_NUM_57840_4_10) ||
1447 (CHIP_NUM(sc) == CHIP_NUM_57840_2_20) ||
1448 (CHIP_NUM(sc) == CHIP_NUM_57840_OBS)) &&
1450 (REG_RD(sc, MISC_REG_RESET_REG_2) &
1451 MISC_REGISTERS_RESET_REG_2_XMAC)) {
1452 PMD_DRV_LOG(DEBUG, "XMAC already out of reset in 4-port mode");
1457 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1458 MISC_REGISTERS_RESET_REG_2_XMAC);
1461 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1462 MISC_REGISTERS_RESET_REG_2_XMAC);
1464 PMD_DRV_LOG(DEBUG, "Init XMAC to 2 ports x 10G per path");
1466 /* Set the number of ports on the system side to up to 2 */
1467 REG_WR(sc, MISC_REG_XMAC_CORE_PORT_MODE, 1);
1469 /* Set the number of ports on the Warp Core to 10G */
1470 REG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1472 /* Set the number of ports on the system side to 1 */
1473 REG_WR(sc, MISC_REG_XMAC_CORE_PORT_MODE, 0);
1474 if (max_speed == ELINK_SPEED_10000) {
1476 "Init XMAC to 10G x 1 port per path");
1477 /* Set the number of ports on the Warp Core to 10G */
1478 REG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1481 "Init XMAC to 20G x 2 ports per path");
1482 /* Set the number of ports on the Warp Core to 20G */
1483 REG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 1);
1487 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1488 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1491 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1492 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1496 static void elink_set_xmac_rxtx(struct elink_params *params, uint8_t en)
1498 uint8_t port = params->port;
1499 struct bnx2x_softc *sc = params->sc;
1500 uint32_t pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1503 if (REG_RD(sc, MISC_REG_RESET_REG_2) & MISC_REGISTERS_RESET_REG_2_XMAC) {
1504 /* Send an indication to change the state in the NIG back to XON
1505 * Clearing this bit enables the next set of this bit to get
1508 pfc_ctrl = REG_RD(sc, xmac_base + XMAC_REG_PFC_CTRL_HI);
1509 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI,
1510 (pfc_ctrl & ~(1 << 1)));
1511 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI,
1512 (pfc_ctrl | (1 << 1)));
1513 PMD_DRV_LOG(DEBUG, "Disable XMAC on port %x", port);
1514 val = REG_RD(sc, xmac_base + XMAC_REG_CTRL);
1516 val |= (XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
1518 val &= ~(XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
1519 REG_WR(sc, xmac_base + XMAC_REG_CTRL, val);
1523 static elink_status_t elink_xmac_enable(struct elink_params *params,
1524 struct elink_vars *vars, uint8_t lb)
1526 uint32_t val, xmac_base;
1527 struct bnx2x_softc *sc = params->sc;
1528 PMD_DRV_LOG(DEBUG, "enabling XMAC");
1530 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1532 elink_xmac_init(params, vars->line_speed);
1534 /* This register determines on which events the MAC will assert
1535 * error on the i/f to the NIG along w/ EOP.
1538 /* This register tells the NIG whether to send traffic to UMAC
1541 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port * 4, 0);
1543 /* When XMAC is in XLGMII mode, disable sending idles for fault
1546 if (!(params->phy[ELINK_INT_PHY].flags & ELINK_FLAGS_TX_ERROR_CHECK)) {
1547 REG_WR(sc, xmac_base + XMAC_REG_RX_LSS_CTRL,
1548 (XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE |
1549 XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE));
1550 REG_WR(sc, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
1551 REG_WR(sc, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
1552 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
1553 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
1555 /* Set Max packet size */
1556 REG_WR(sc, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);
1558 /* CRC append for Tx packets */
1559 REG_WR(sc, xmac_base + XMAC_REG_TX_CTRL, 0xC800);
1562 elink_update_pfc_xmac(params, vars);
1564 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
1565 PMD_DRV_LOG(DEBUG, "Setting XMAC for EEE");
1566 REG_WR(sc, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008);
1567 REG_WR(sc, xmac_base + XMAC_REG_EEE_CTRL, 0x1);
1569 REG_WR(sc, xmac_base + XMAC_REG_EEE_CTRL, 0x0);
1572 /* Enable TX and RX */
1573 val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN;
1575 /* Set MAC in XLGMII mode for dual-mode */
1576 if ((vars->line_speed == ELINK_SPEED_20000) &&
1577 (params->phy[ELINK_INT_PHY].supported &
1578 ELINK_SUPPORTED_20000baseKR2_Full))
1579 val |= XMAC_CTRL_REG_XLGMII_ALIGN_ENB;
1581 /* Check loopback mode */
1583 val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK;
1584 REG_WR(sc, xmac_base + XMAC_REG_CTRL, val);
1585 elink_set_xumac_nig(params,
1586 ((vars->flow_ctrl & ELINK_FLOW_CTRL_TX) != 0), 1);
1588 vars->mac_type = ELINK_MAC_TYPE_XMAC;
1590 return ELINK_STATUS_OK;
1593 static elink_status_t elink_emac_enable(struct elink_params *params,
1594 struct elink_vars *vars, uint8_t lb)
1596 struct bnx2x_softc *sc = params->sc;
1597 uint8_t port = params->port;
1598 uint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1601 PMD_DRV_LOG(DEBUG, "enabling EMAC");
1604 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1605 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1607 /* enable emac and not bmac */
1608 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + port * 4, 1);
1610 #ifdef ELINK_INCLUDE_EMUL
1612 if (CHIP_REV_IS_EMUL(sc)) {
1613 /* Use lane 1 (of lanes 0-3) */
1614 REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port * 4, 1);
1615 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1);
1620 #ifdef ELINK_INCLUDE_FPGA
1621 if (CHIP_REV_IS_FPGA(sc)) {
1622 /* Use lane 1 (of lanes 0-3) */
1623 PMD_DRV_LOG(DEBUG, "elink_emac_enable: Setting FPGA");
1625 REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port * 4, 1);
1626 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 0);
1630 if (vars->phy_flags & PHY_XGXS_FLAG) {
1631 uint32_t ser_lane = ((params->lane_config &
1632 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1633 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1635 PMD_DRV_LOG(DEBUG, "XGXS");
1636 /* select the master lanes (out of 0-3) */
1637 REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port * 4, ser_lane);
1639 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1);
1641 } else { /* SerDes */
1642 PMD_DRV_LOG(DEBUG, "SerDes");
1644 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 0);
1647 elink_bits_en(sc, emac_base + EMAC_REG_EMAC_RX_MODE,
1648 EMAC_RX_MODE_RESET);
1649 elink_bits_en(sc, emac_base + EMAC_REG_EMAC_TX_MODE,
1650 EMAC_TX_MODE_RESET);
1652 #if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA)
1653 if (CHIP_REV_IS_SLOW(sc)) {
1654 /* config GMII mode */
1655 val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);
1656 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MODE,
1657 (val | EMAC_MODE_PORT_GMII));
1660 /* pause enable/disable */
1661 elink_bits_dis(sc, emac_base + EMAC_REG_EMAC_RX_MODE,
1662 EMAC_RX_MODE_FLOW_EN);
1664 elink_bits_dis(sc, emac_base + EMAC_REG_EMAC_TX_MODE,
1665 (EMAC_TX_MODE_EXT_PAUSE_EN |
1666 EMAC_TX_MODE_FLOW_EN));
1667 if (!(params->feature_config_flags &
1668 ELINK_FEATURE_CONFIG_PFC_ENABLED)) {
1669 if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)
1670 elink_bits_en(sc, emac_base +
1671 EMAC_REG_EMAC_RX_MODE,
1672 EMAC_RX_MODE_FLOW_EN);
1674 if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)
1675 elink_bits_en(sc, emac_base +
1676 EMAC_REG_EMAC_TX_MODE,
1677 (EMAC_TX_MODE_EXT_PAUSE_EN |
1678 EMAC_TX_MODE_FLOW_EN));
1680 elink_bits_en(sc, emac_base + EMAC_REG_EMAC_TX_MODE,
1681 EMAC_TX_MODE_FLOW_EN);
1682 #if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA)
1686 /* KEEP_VLAN_TAG, promiscuous */
1687 val = REG_RD(sc, emac_base + EMAC_REG_EMAC_RX_MODE);
1688 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
1690 /* Setting this bit causes MAC control frames (except for pause
1691 * frames) to be passed on for processing. This setting has no
1692 * affect on the operation of the pause frames. This bit effects
1693 * all packets regardless of RX Parser packet sorting logic.
1694 * Turn the PFC off to make sure we are in Xon state before
1697 elink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_MODE, 0);
1698 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) {
1699 PMD_DRV_LOG(DEBUG, "PFC is enabled");
1700 /* Enable PFC again */
1701 elink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_MODE,
1702 EMAC_REG_RX_PFC_MODE_RX_EN |
1703 EMAC_REG_RX_PFC_MODE_TX_EN |
1704 EMAC_REG_RX_PFC_MODE_PRIORITIES);
1706 elink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_PARAM,
1708 EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
1710 EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
1711 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
1713 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_RX_MODE, val);
1716 val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);
1721 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MODE, val);
1724 REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port * 4, 1);
1726 /* Enable emac for jumbo packets */
1727 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_RX_MTU_SIZE,
1728 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
1729 (ELINK_ETH_MAX_JUMBO_PACKET_SIZE +
1730 ELINK_ETH_OVREHEAD)));
1733 REG_WR(sc, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port * 4, 0x1);
1735 /* Disable the NIG in/out to the bmac */
1736 REG_WR(sc, NIG_REG_BMAC0_IN_EN + port * 4, 0x0);
1737 REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + port * 4, 0x0);
1738 REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port * 4, 0x0);
1740 /* Enable the NIG in/out to the emac */
1741 REG_WR(sc, NIG_REG_EMAC0_IN_EN + port * 4, 0x1);
1743 if ((params->feature_config_flags &
1744 ELINK_FEATURE_CONFIG_PFC_ENABLED) ||
1745 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
1748 REG_WR(sc, NIG_REG_EMAC0_PAUSE_OUT_EN + port * 4, val);
1749 REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port * 4, 0x1);
1751 #ifdef ELINK_INCLUDE_EMUL
1752 if (CHIP_REV_IS_EMUL(sc)) {
1753 /* Take the BigMac out of reset */
1754 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1755 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1757 /* Enable access for bmac registers */
1758 REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4, 0x1);
1761 REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4, 0x0);
1763 vars->mac_type = ELINK_MAC_TYPE_EMAC;
1764 return ELINK_STATUS_OK;
1767 static void elink_update_pfc_bmac1(struct elink_params *params,
1768 struct elink_vars *vars)
1770 uint32_t wb_data[2];
1771 struct bnx2x_softc *sc = params->sc;
1772 uint32_t bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1773 NIG_REG_INGRESS_BMAC0_MEM;
1775 uint32_t val = 0x14;
1776 if ((!(params->feature_config_flags &
1777 ELINK_FEATURE_CONFIG_PFC_ENABLED)) &&
1778 (vars->flow_ctrl & ELINK_FLOW_CTRL_RX))
1779 /* Enable BigMAC to react on received Pause packets */
1783 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
1787 if (!(params->feature_config_flags &
1788 ELINK_FEATURE_CONFIG_PFC_ENABLED) &&
1789 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
1793 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
1796 static void elink_update_pfc_bmac2(struct elink_params *params,
1797 struct elink_vars *vars, uint8_t is_lb)
1799 /* Set rx control: Strip CRC and enable BigMAC to relay
1800 * control packets to the system as well
1802 uint32_t wb_data[2];
1803 struct bnx2x_softc *sc = params->sc;
1804 uint32_t bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1805 NIG_REG_INGRESS_BMAC0_MEM;
1806 uint32_t val = 0x14;
1808 if ((!(params->feature_config_flags &
1809 ELINK_FEATURE_CONFIG_PFC_ENABLED)) &&
1810 (vars->flow_ctrl & ELINK_FLOW_CTRL_RX))
1811 /* Enable BigMAC to react on received Pause packets */
1815 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
1820 if (!(params->feature_config_flags &
1821 ELINK_FEATURE_CONFIG_PFC_ENABLED) &&
1822 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
1826 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
1828 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) {
1829 PMD_DRV_LOG(DEBUG, "PFC is enabled");
1830 /* Enable PFC RX & TX & STATS and set 8 COS */
1832 wb_data[0] |= (1 << 0); /* RX */
1833 wb_data[0] |= (1 << 1); /* TX */
1834 wb_data[0] |= (1 << 2); /* Force initial Xon */
1835 wb_data[0] |= (1 << 3); /* 8 cos */
1836 wb_data[0] |= (1 << 5); /* STATS */
1838 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
1840 /* Clear the force Xon */
1841 wb_data[0] &= ~(1 << 2);
1843 PMD_DRV_LOG(DEBUG, "PFC is disabled");
1844 /* Disable PFC RX & TX & STATS and set 8 COS */
1849 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
1851 /* Set Time (based unit is 512 bit time) between automatic
1852 * re-sending of PP packets amd enable automatic re-send of
1853 * Per-Priroity Packet as long as pp_gen is asserted and
1854 * pp_disable is low.
1857 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
1858 val |= (1 << 16); /* enable automatic re-send */
1862 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
1866 val = 0x3; /* Enable RX and TX */
1868 val |= 0x4; /* Local loopback */
1869 PMD_DRV_LOG(DEBUG, "enable bmac loopback");
1871 /* When PFC enabled, Pass pause frames towards the NIG. */
1872 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
1873 val |= ((1 << 6) | (1 << 5));
1877 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
1880 /******************************************************************************
1882 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are
1883 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
1884 ******************************************************************************/
1885 static elink_status_t elink_pfc_nig_rx_priority_mask(struct bnx2x_softc *sc,
1887 uint32_t priority_mask,
1890 uint32_t nig_reg_rx_priority_mask_add = 0;
1892 switch (cos_entry) {
1894 nig_reg_rx_priority_mask_add = (port) ?
1895 NIG_REG_P1_RX_COS0_PRIORITY_MASK :
1896 NIG_REG_P0_RX_COS0_PRIORITY_MASK;
1899 nig_reg_rx_priority_mask_add = (port) ?
1900 NIG_REG_P1_RX_COS1_PRIORITY_MASK :
1901 NIG_REG_P0_RX_COS1_PRIORITY_MASK;
1904 nig_reg_rx_priority_mask_add = (port) ?
1905 NIG_REG_P1_RX_COS2_PRIORITY_MASK :
1906 NIG_REG_P0_RX_COS2_PRIORITY_MASK;
1910 return ELINK_STATUS_ERROR;
1911 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;
1915 return ELINK_STATUS_ERROR;
1916 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;
1920 return ELINK_STATUS_ERROR;
1921 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;
1925 REG_WR(sc, nig_reg_rx_priority_mask_add, priority_mask);
1927 return ELINK_STATUS_OK;
1930 static void elink_update_mng(struct elink_params *params, uint32_t link_status)
1932 struct bnx2x_softc *sc = params->sc;
1934 REG_WR(sc, params->shmem_base +
1935 offsetof(struct shmem_region,
1936 port_mb[params->port].link_status), link_status);
1939 static void elink_update_link_attr(struct elink_params *params,
1942 struct bnx2x_softc *sc = params->sc;
1944 if (SHMEM2_HAS(sc, link_attr_sync))
1945 REG_WR(sc, params->shmem2_base +
1946 offsetof(struct shmem2_region,
1947 link_attr_sync[params->port]), link_attr);
1950 static void elink_update_pfc_nig(struct elink_params *params,
1951 struct elink_nig_brb_pfc_port_params
1954 uint32_t xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en =
1956 uint32_t llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0;
1957 uint32_t pkt_priority_to_cos = 0;
1958 struct bnx2x_softc *sc = params->sc;
1959 uint8_t port = params->port;
1961 int set_pfc = params->feature_config_flags &
1962 ELINK_FEATURE_CONFIG_PFC_ENABLED;
1963 PMD_DRV_LOG(DEBUG, "updating pfc nig parameters");
1965 /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
1966 * MAC control frames (that are not pause packets)
1967 * will be forwarded to the XCM.
1969 xcm_mask = REG_RD(sc, port ? NIG_REG_LLH1_XCM_MASK :
1970 NIG_REG_LLH0_XCM_MASK);
1971 /* NIG params will override non PFC params, since it's possible to
1972 * do transition from PFC to SAFC
1982 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
1983 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
1988 llfc_out_en = nig_params->llfc_out_en;
1989 llfc_enable = nig_params->llfc_enable;
1990 pause_enable = nig_params->pause_enable;
1991 } else /* Default non PFC mode - PAUSE */
1994 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
1995 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2000 REG_WR(sc, port ? NIG_REG_BRB1_PAUSE_IN_EN :
2001 NIG_REG_BRB0_PAUSE_IN_EN, pause_enable);
2002 REG_WR(sc, port ? NIG_REG_LLFC_OUT_EN_1 :
2003 NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
2004 REG_WR(sc, port ? NIG_REG_LLFC_ENABLE_1 :
2005 NIG_REG_LLFC_ENABLE_0, llfc_enable);
2006 REG_WR(sc, port ? NIG_REG_PAUSE_ENABLE_1 :
2007 NIG_REG_PAUSE_ENABLE_0, pause_enable);
2009 REG_WR(sc, port ? NIG_REG_PPP_ENABLE_1 :
2010 NIG_REG_PPP_ENABLE_0, ppp_enable);
2012 REG_WR(sc, port ? NIG_REG_LLH1_XCM_MASK :
2013 NIG_REG_LLH0_XCM_MASK, xcm_mask);
2015 REG_WR(sc, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 :
2016 NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
2018 /* Output enable for RX_XCM # IF */
2019 REG_WR(sc, port ? NIG_REG_XCM1_OUT_EN :
2020 NIG_REG_XCM0_OUT_EN, xcm_out_en);
2022 /* HW PFC TX enable */
2023 REG_WR(sc, port ? NIG_REG_P1_HWPFC_ENABLE :
2024 NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable);
2028 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
2030 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++)
2031 elink_pfc_nig_rx_priority_mask(sc, i,
2033 rx_cos_priority_mask[i],
2036 REG_WR(sc, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
2037 NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
2038 nig_params->llfc_high_priority_classes);
2040 REG_WR(sc, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
2041 NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
2042 nig_params->llfc_low_priority_classes);
2044 REG_WR(sc, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
2045 NIG_REG_P0_PKT_PRIORITY_TO_COS, pkt_priority_to_cos);
2048 elink_status_t elink_update_pfc(struct elink_params *params,
2049 struct elink_vars *vars,
2050 struct elink_nig_brb_pfc_port_params
2053 /* The PFC and pause are orthogonal to one another, meaning when
2054 * PFC is enabled, the pause are disabled, and when PFC is
2055 * disabled, pause are set according to the pause result.
2058 struct bnx2x_softc *sc = params->sc;
2059 elink_status_t elink_status = ELINK_STATUS_OK;
2060 uint8_t bmac_loopback = (params->loopback_mode == ELINK_LOOPBACK_BMAC);
2062 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
2063 vars->link_status |= LINK_STATUS_PFC_ENABLED;
2065 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
2067 elink_update_mng(params, vars->link_status);
2069 /* Update NIG params */
2070 elink_update_pfc_nig(params, pfc_params);
2073 return elink_status;
2075 PMD_DRV_LOG(DEBUG, "About to update PFC in BMAC");
2077 if (CHIP_IS_E3(sc)) {
2078 if (vars->mac_type == ELINK_MAC_TYPE_XMAC)
2079 elink_update_pfc_xmac(params, vars);
2081 val = REG_RD(sc, MISC_REG_RESET_REG_2);
2083 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
2085 PMD_DRV_LOG(DEBUG, "About to update PFC in EMAC");
2086 elink_emac_enable(params, vars, 0);
2087 return elink_status;
2090 elink_update_pfc_bmac2(params, vars, bmac_loopback);
2092 elink_update_pfc_bmac1(params, vars);
2095 if ((params->feature_config_flags &
2096 ELINK_FEATURE_CONFIG_PFC_ENABLED) ||
2097 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
2099 REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port * 4, val);
2101 return elink_status;
2104 static elink_status_t elink_bmac1_enable(struct elink_params *params,
2105 struct elink_vars *vars, uint8_t is_lb)
2107 struct bnx2x_softc *sc = params->sc;
2108 uint8_t port = params->port;
2109 uint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2110 NIG_REG_INGRESS_BMAC0_MEM;
2111 uint32_t wb_data[2];
2114 PMD_DRV_LOG(DEBUG, "Enabling BigMAC1");
2119 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
2123 wb_data[0] = ((params->mac_addr[2] << 24) |
2124 (params->mac_addr[3] << 16) |
2125 (params->mac_addr[4] << 8) | params->mac_addr[5]);
2126 wb_data[1] = ((params->mac_addr[0] << 8) | params->mac_addr[1]);
2127 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
2133 PMD_DRV_LOG(DEBUG, "enable bmac loopback");
2137 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
2140 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
2142 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
2144 elink_update_pfc_bmac1(params, vars);
2147 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
2149 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
2151 /* Set cnt max size */
2152 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
2154 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2156 /* Configure SAFC */
2157 wb_data[0] = 0x1000200;
2159 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
2161 #ifdef ELINK_INCLUDE_EMUL
2162 /* Fix for emulation */
2163 if (CHIP_REV_IS_EMUL(sc)) {
2164 wb_data[0] = 0xf000;
2166 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_PAUSE_THRESHOLD,
2171 return ELINK_STATUS_OK;
2174 static elink_status_t elink_bmac2_enable(struct elink_params *params,
2175 struct elink_vars *vars, uint8_t is_lb)
2177 struct bnx2x_softc *sc = params->sc;
2178 uint8_t port = params->port;
2179 uint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2180 NIG_REG_INGRESS_BMAC0_MEM;
2181 uint32_t wb_data[2];
2183 PMD_DRV_LOG(DEBUG, "Enabling BigMAC2");
2187 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2190 /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
2193 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
2199 wb_data[0] = ((params->mac_addr[2] << 24) |
2200 (params->mac_addr[3] << 16) |
2201 (params->mac_addr[4] << 8) | params->mac_addr[5]);
2202 wb_data[1] = ((params->mac_addr[0] << 8) | params->mac_addr[1]);
2203 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
2208 /* Configure SAFC */
2209 wb_data[0] = 0x1000200;
2211 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
2216 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
2218 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
2222 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
2224 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
2226 /* Set cnt max size */
2227 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD - 2;
2229 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2231 elink_update_pfc_bmac2(params, vars, is_lb);
2233 return ELINK_STATUS_OK;
2236 static elink_status_t elink_bmac_enable(struct elink_params *params,
2237 struct elink_vars *vars,
2238 uint8_t is_lb, uint8_t reset_bmac)
2240 elink_status_t rc = ELINK_STATUS_OK;
2241 uint8_t port = params->port;
2242 struct bnx2x_softc *sc = params->sc;
2244 /* Reset and unreset the BigMac */
2246 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2247 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2251 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2252 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2254 /* Enable access for bmac registers */
2255 REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4, 0x1);
2257 /* Enable BMAC according to BMAC type */
2259 rc = elink_bmac2_enable(params, vars, is_lb);
2261 rc = elink_bmac1_enable(params, vars, is_lb);
2262 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 0x1);
2263 REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port * 4, 0x0);
2264 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + port * 4, 0x0);
2266 if ((params->feature_config_flags &
2267 ELINK_FEATURE_CONFIG_PFC_ENABLED) ||
2268 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
2270 REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + port * 4, val);
2271 REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port * 4, 0x0);
2272 REG_WR(sc, NIG_REG_EMAC0_IN_EN + port * 4, 0x0);
2273 REG_WR(sc, NIG_REG_EMAC0_PAUSE_OUT_EN + port * 4, 0x0);
2274 REG_WR(sc, NIG_REG_BMAC0_IN_EN + port * 4, 0x1);
2275 REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port * 4, 0x1);
2277 vars->mac_type = ELINK_MAC_TYPE_BMAC;
2281 static void elink_set_bmac_rx(struct bnx2x_softc *sc, uint8_t port, uint8_t en)
2283 uint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2284 NIG_REG_INGRESS_BMAC0_MEM;
2285 uint32_t wb_data[2];
2286 uint32_t nig_bmac_enable =
2287 REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
2290 bmac_addr += BIGMAC2_REGISTER_BMAC_CONTROL;
2292 bmac_addr += BIGMAC_REGISTER_BMAC_CONTROL;
2293 /* Only if the bmac is out of reset */
2294 if (REG_RD(sc, MISC_REG_RESET_REG_2) &
2295 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) && nig_bmac_enable) {
2296 /* Clear Rx Enable bit in BMAC_CONTROL register */
2297 REG_RD_DMAE(sc, bmac_addr, wb_data, 2);
2299 wb_data[0] |= ELINK_BMAC_CONTROL_RX_ENABLE;
2301 wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE;
2302 REG_WR_DMAE(sc, bmac_addr, wb_data, 2);
2307 static elink_status_t elink_pbf_update(struct elink_params *params,
2308 uint32_t flow_ctrl, uint32_t line_speed)
2310 struct bnx2x_softc *sc = params->sc;
2311 uint8_t port = params->port;
2312 uint32_t init_crd, crd;
2313 uint32_t count = 1000;
2316 REG_WR(sc, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port * 4, 0x1);
2318 /* Wait for init credit */
2319 init_crd = REG_RD(sc, PBF_REG_P0_INIT_CRD + port * 4);
2320 crd = REG_RD(sc, PBF_REG_P0_CREDIT + port * 8);
2321 PMD_DRV_LOG(DEBUG, "init_crd 0x%x crd 0x%x", init_crd, crd);
2323 while ((init_crd != crd) && count) {
2325 crd = REG_RD(sc, PBF_REG_P0_CREDIT + port * 8);
2328 crd = REG_RD(sc, PBF_REG_P0_CREDIT + port * 8);
2329 if (init_crd != crd) {
2330 PMD_DRV_LOG(DEBUG, "BUG! init_crd 0x%x != crd 0x%x",
2332 return ELINK_STATUS_ERROR;
2335 if (flow_ctrl & ELINK_FLOW_CTRL_RX ||
2336 line_speed == ELINK_SPEED_10 ||
2337 line_speed == ELINK_SPEED_100 ||
2338 line_speed == ELINK_SPEED_1000 || line_speed == ELINK_SPEED_2500) {
2339 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 1);
2340 /* Update threshold */
2341 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, 0);
2342 /* Update init credit */
2343 init_crd = 778; /* (800-18-4) */
2346 uint32_t thresh = (ELINK_ETH_MAX_JUMBO_PACKET_SIZE +
2347 ELINK_ETH_OVREHEAD) / 16;
2348 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 0);
2349 /* Update threshold */
2350 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, thresh);
2351 /* Update init credit */
2352 switch (line_speed) {
2353 case ELINK_SPEED_10000:
2354 init_crd = thresh + 553 - 22;
2357 PMD_DRV_LOG(DEBUG, "Invalid line_speed 0x%x",
2359 return ELINK_STATUS_ERROR;
2362 REG_WR(sc, PBF_REG_P0_INIT_CRD + port * 4, init_crd);
2363 PMD_DRV_LOG(DEBUG, "PBF updated to speed %d credit %d",
2364 line_speed, init_crd);
2366 /* Probe the credit changes */
2367 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0x1);
2369 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0x0);
2372 REG_WR(sc, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port * 4, 0x0);
2373 return ELINK_STATUS_OK;
2377 * elink_get_emac_base - retrive emac base address
2379 * @bp: driver handle
2380 * @mdc_mdio_access: access type
2383 * This function selects the MDC/MDIO access (through emac0 or
2384 * emac1) depend on the mdc_mdio_access, port, port swapped. Each
2385 * phy has a default access mode, which could also be overridden
2386 * by nvram configuration. This parameter, whether this is the
2387 * default phy configuration, or the nvram overrun
2388 * configuration, is passed here as mdc_mdio_access and selects
2389 * the emac_base for the CL45 read/writes operations
2391 static uint32_t elink_get_emac_base(struct bnx2x_softc *sc,
2392 uint32_t mdc_mdio_access, uint8_t port)
2394 uint32_t emac_base = 0;
2395 switch (mdc_mdio_access) {
2396 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
2398 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
2399 if (REG_RD(sc, NIG_REG_PORT_SWAP))
2400 emac_base = GRCBASE_EMAC1;
2402 emac_base = GRCBASE_EMAC0;
2404 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
2405 if (REG_RD(sc, NIG_REG_PORT_SWAP))
2406 emac_base = GRCBASE_EMAC0;
2408 emac_base = GRCBASE_EMAC1;
2410 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
2411 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2413 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
2414 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
2423 /******************************************************************/
2424 /* CL22 access functions */
2425 /******************************************************************/
2426 static elink_status_t elink_cl22_write(struct bnx2x_softc *sc,
2427 struct elink_phy *phy,
2428 uint16_t reg, uint16_t val)
2432 elink_status_t rc = ELINK_STATUS_OK;
2433 /* Switch to CL22 */
2434 mode = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2435 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2436 mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2439 tmp = ((phy->addr << 21) | (reg << 16) | val |
2440 EMAC_MDIO_COMM_COMMAND_WRITE_22 | EMAC_MDIO_COMM_START_BUSY);
2441 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2443 for (i = 0; i < 50; i++) {
2446 tmp = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2447 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2452 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2453 PMD_DRV_LOG(DEBUG, "write phy register failed");
2454 rc = ELINK_STATUS_TIMEOUT;
2456 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2460 static elink_status_t elink_cl22_read(struct bnx2x_softc *sc,
2461 struct elink_phy *phy,
2462 uint16_t reg, uint16_t * ret_val)
2466 elink_status_t rc = ELINK_STATUS_OK;
2468 /* Switch to CL22 */
2469 mode = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2470 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2471 mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2474 val = ((phy->addr << 21) | (reg << 16) |
2475 EMAC_MDIO_COMM_COMMAND_READ_22 | EMAC_MDIO_COMM_START_BUSY);
2476 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2478 for (i = 0; i < 50; i++) {
2481 val = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2482 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2483 *ret_val = (uint16_t) (val & EMAC_MDIO_COMM_DATA);
2488 if (val & EMAC_MDIO_COMM_START_BUSY) {
2489 PMD_DRV_LOG(DEBUG, "read phy register failed");
2492 rc = ELINK_STATUS_TIMEOUT;
2494 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2498 /******************************************************************/
2499 /* CL45 access functions */
2500 /******************************************************************/
2501 static elink_status_t elink_cl45_read(struct bnx2x_softc *sc,
2502 struct elink_phy *phy, uint8_t devad,
2503 uint16_t reg, uint16_t * ret_val)
2507 elink_status_t rc = ELINK_STATUS_OK;
2508 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_G) {
2509 elink_set_mdio_clk(sc, phy->mdio_ctrl);
2512 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)
2513 elink_bits_en(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2514 EMAC_MDIO_STATUS_10MB);
2516 val = ((phy->addr << 21) | (devad << 16) | reg |
2517 EMAC_MDIO_COMM_COMMAND_ADDRESS | EMAC_MDIO_COMM_START_BUSY);
2518 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2520 for (i = 0; i < 50; i++) {
2523 val = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2524 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2529 if (val & EMAC_MDIO_COMM_START_BUSY) {
2530 PMD_DRV_LOG(DEBUG, "read phy register failed");
2531 elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout"
2534 rc = ELINK_STATUS_TIMEOUT;
2537 val = ((phy->addr << 21) | (devad << 16) |
2538 EMAC_MDIO_COMM_COMMAND_READ_45 |
2539 EMAC_MDIO_COMM_START_BUSY);
2540 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2542 for (i = 0; i < 50; i++) {
2545 val = REG_RD(sc, phy->mdio_ctrl +
2546 EMAC_REG_EMAC_MDIO_COMM);
2547 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2549 (uint16_t) (val & EMAC_MDIO_COMM_DATA);
2553 if (val & EMAC_MDIO_COMM_START_BUSY) {
2554 PMD_DRV_LOG(DEBUG, "read phy register failed");
2555 elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout"
2558 rc = ELINK_STATUS_TIMEOUT;
2561 /* Work around for E3 A0 */
2562 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA) {
2563 phy->flags ^= ELINK_FLAGS_DUMMY_READ;
2564 if (phy->flags & ELINK_FLAGS_DUMMY_READ) {
2566 elink_cl45_read(sc, phy, devad, 0xf, &temp_val);
2570 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)
2571 elink_bits_dis(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2572 EMAC_MDIO_STATUS_10MB);
2576 static elink_status_t elink_cl45_write(struct bnx2x_softc *sc,
2577 struct elink_phy *phy, uint8_t devad,
2578 uint16_t reg, uint16_t val)
2582 elink_status_t rc = ELINK_STATUS_OK;
2583 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_G) {
2584 elink_set_mdio_clk(sc, phy->mdio_ctrl);
2587 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)
2588 elink_bits_en(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2589 EMAC_MDIO_STATUS_10MB);
2592 tmp = ((phy->addr << 21) | (devad << 16) | reg |
2593 EMAC_MDIO_COMM_COMMAND_ADDRESS | EMAC_MDIO_COMM_START_BUSY);
2594 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2596 for (i = 0; i < 50; i++) {
2599 tmp = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2600 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2605 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2606 PMD_DRV_LOG(DEBUG, "write phy register failed");
2607 elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout"
2609 rc = ELINK_STATUS_TIMEOUT;
2612 tmp = ((phy->addr << 21) | (devad << 16) | val |
2613 EMAC_MDIO_COMM_COMMAND_WRITE_45 |
2614 EMAC_MDIO_COMM_START_BUSY);
2615 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2617 for (i = 0; i < 50; i++) {
2620 tmp = REG_RD(sc, phy->mdio_ctrl +
2621 EMAC_REG_EMAC_MDIO_COMM);
2622 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2627 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2628 PMD_DRV_LOG(DEBUG, "write phy register failed");
2629 elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout"
2631 rc = ELINK_STATUS_TIMEOUT;
2634 /* Work around for E3 A0 */
2635 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA) {
2636 phy->flags ^= ELINK_FLAGS_DUMMY_READ;
2637 if (phy->flags & ELINK_FLAGS_DUMMY_READ) {
2639 elink_cl45_read(sc, phy, devad, 0xf, &temp_val);
2642 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)
2643 elink_bits_dis(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2644 EMAC_MDIO_STATUS_10MB);
2648 /******************************************************************/
2650 /******************************************************************/
2651 static uint8_t elink_eee_has_cap(struct elink_params *params)
2653 struct bnx2x_softc *sc = params->sc;
2655 if (REG_RD(sc, params->shmem2_base) <=
2656 offsetof(struct shmem2_region, eee_status[params->port]))
2662 static elink_status_t elink_eee_nvram_to_time(uint32_t nvram_mode,
2663 uint32_t * idle_timer)
2665 switch (nvram_mode) {
2666 case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED:
2667 *idle_timer = ELINK_EEE_MODE_NVRAM_BALANCED_TIME;
2669 case PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE:
2670 *idle_timer = ELINK_EEE_MODE_NVRAM_AGGRESSIVE_TIME;
2672 case PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY:
2673 *idle_timer = ELINK_EEE_MODE_NVRAM_LATENCY_TIME;
2680 return ELINK_STATUS_OK;
2683 static elink_status_t elink_eee_time_to_nvram(uint32_t idle_timer,
2684 uint32_t * nvram_mode)
2686 switch (idle_timer) {
2687 case ELINK_EEE_MODE_NVRAM_BALANCED_TIME:
2688 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED;
2690 case ELINK_EEE_MODE_NVRAM_AGGRESSIVE_TIME:
2691 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE;
2693 case ELINK_EEE_MODE_NVRAM_LATENCY_TIME:
2694 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY;
2697 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED;
2701 return ELINK_STATUS_OK;
2704 static uint32_t elink_eee_calc_timer(struct elink_params *params)
2706 uint32_t eee_mode, eee_idle;
2707 struct bnx2x_softc *sc = params->sc;
2709 if (params->eee_mode & ELINK_EEE_MODE_OVERRIDE_NVRAM) {
2710 if (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME) {
2711 /* time value in eee_mode --> used directly */
2712 eee_idle = params->eee_mode & ELINK_EEE_MODE_TIMER_MASK;
2714 /* hsi value in eee_mode --> time */
2715 if (elink_eee_nvram_to_time(params->eee_mode &
2716 ELINK_EEE_MODE_NVRAM_MASK,
2721 /* hsi values in nvram --> time */
2722 eee_mode = ((REG_RD(sc, params->shmem_base +
2723 offsetof(struct shmem_region,
2724 dev_info.port_feature_config
2726 port].eee_power_mode)) &
2727 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
2728 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
2730 if (elink_eee_nvram_to_time(eee_mode, &eee_idle))
2737 static elink_status_t elink_eee_set_timers(struct elink_params *params,
2738 struct elink_vars *vars)
2740 uint32_t eee_idle = 0, eee_mode;
2741 struct bnx2x_softc *sc = params->sc;
2743 eee_idle = elink_eee_calc_timer(params);
2746 REG_WR(sc, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2),
2748 } else if ((params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI) &&
2749 (params->eee_mode & ELINK_EEE_MODE_OVERRIDE_NVRAM) &&
2750 (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME)) {
2751 PMD_DRV_LOG(DEBUG, "Error: Tx LPI is enabled with timer 0");
2752 return ELINK_STATUS_ERROR;
2755 vars->eee_status &= ~(SHMEM_EEE_TIMER_MASK | SHMEM_EEE_TIME_OUTPUT_BIT);
2756 if (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME) {
2757 /* eee_idle in 1u --> eee_status in 16u */
2759 vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) |
2760 SHMEM_EEE_TIME_OUTPUT_BIT;
2762 if (elink_eee_time_to_nvram(eee_idle, &eee_mode))
2763 return ELINK_STATUS_ERROR;
2764 vars->eee_status |= eee_mode;
2767 return ELINK_STATUS_OK;
2770 static elink_status_t elink_eee_initial_config(struct elink_params *params,
2771 struct elink_vars *vars,
2774 vars->eee_status |= ((uint32_t) mode) << SHMEM_EEE_SUPPORTED_SHIFT;
2776 /* Propogate params' bits --> vars (for migration exposure) */
2777 if (params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI)
2778 vars->eee_status |= SHMEM_EEE_LPI_REQUESTED_BIT;
2780 vars->eee_status &= ~SHMEM_EEE_LPI_REQUESTED_BIT;
2782 if (params->eee_mode & ELINK_EEE_MODE_ADV_LPI)
2783 vars->eee_status |= SHMEM_EEE_REQUESTED_BIT;
2785 vars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT;
2787 return elink_eee_set_timers(params, vars);
2790 static elink_status_t elink_eee_disable(struct elink_phy *phy,
2791 struct elink_params *params,
2792 struct elink_vars *vars)
2794 struct bnx2x_softc *sc = params->sc;
2796 /* Make Certain LPI is disabled */
2797 REG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0);
2799 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0);
2801 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
2803 return ELINK_STATUS_OK;
2806 static elink_status_t elink_eee_advertise(struct elink_phy *phy,
2807 struct elink_params *params,
2808 struct elink_vars *vars,
2811 struct bnx2x_softc *sc = params->sc;
2814 /* Mask events preventing LPI generation */
2815 REG_WR(sc, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20);
2817 if (modes & SHMEM_EEE_10G_ADV) {
2818 PMD_DRV_LOG(DEBUG, "Advertise 10GBase-T EEE");
2821 if (modes & SHMEM_EEE_1G_ADV) {
2822 PMD_DRV_LOG(DEBUG, "Advertise 1GBase-T EEE");
2826 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val);
2828 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
2829 vars->eee_status |= (modes << SHMEM_EEE_ADV_STATUS_SHIFT);
2831 return ELINK_STATUS_OK;
2834 static void elink_update_mng_eee(struct elink_params *params,
2835 uint32_t eee_status)
2837 struct bnx2x_softc *sc = params->sc;
2839 if (elink_eee_has_cap(params))
2840 REG_WR(sc, params->shmem2_base +
2841 offsetof(struct shmem2_region,
2842 eee_status[params->port]), eee_status);
2845 static void elink_eee_an_resolve(struct elink_phy *phy,
2846 struct elink_params *params,
2847 struct elink_vars *vars)
2849 struct bnx2x_softc *sc = params->sc;
2850 uint16_t adv = 0, lp = 0;
2851 uint32_t lp_adv = 0;
2854 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv);
2855 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp);
2858 lp_adv |= SHMEM_EEE_100M_ADV;
2860 if (vars->line_speed == ELINK_SPEED_100)
2862 PMD_DRV_LOG(DEBUG, "EEE negotiated - 100M");
2866 lp_adv |= SHMEM_EEE_1G_ADV;
2868 if (vars->line_speed == ELINK_SPEED_1000)
2870 PMD_DRV_LOG(DEBUG, "EEE negotiated - 1G");
2874 lp_adv |= SHMEM_EEE_10G_ADV;
2876 if (vars->line_speed == ELINK_SPEED_10000)
2878 PMD_DRV_LOG(DEBUG, "EEE negotiated - 10G");
2882 vars->eee_status &= ~SHMEM_EEE_LP_ADV_STATUS_MASK;
2883 vars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT);
2886 PMD_DRV_LOG(DEBUG, "EEE is active");
2887 vars->eee_status |= SHMEM_EEE_ACTIVE_BIT;
2891 /******************************************************************/
2892 /* BSC access functions from E3 */
2893 /******************************************************************/
2894 static void elink_bsc_module_sel(struct elink_params *params)
2897 uint32_t board_cfg, sfp_ctrl;
2898 uint32_t i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH];
2899 struct bnx2x_softc *sc = params->sc;
2900 uint8_t port = params->port;
2901 /* Read I2C output PINs */
2902 board_cfg = REG_RD(sc, params->shmem_base +
2903 offsetof(struct shmem_region,
2904 dev_info.shared_hw_config.board));
2905 i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK;
2906 i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >>
2907 SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;
2909 /* Read I2C output value */
2910 sfp_ctrl = REG_RD(sc, params->shmem_base +
2911 offsetof(struct shmem_region,
2912 dev_info.port_hw_config[port].
2914 i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0;
2915 i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0;
2916 PMD_DRV_LOG(DEBUG, "Setting BSC switch");
2917 for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++)
2918 elink_set_cfg_pin(sc, i2c_pins[idx], i2c_val[idx]);
2921 static elink_status_t elink_bsc_read(struct elink_params *params,
2922 struct bnx2x_softc *sc,
2926 uint8_t xfer_cnt, uint32_t * data_array)
2929 elink_status_t rc = ELINK_STATUS_OK;
2931 if (xfer_cnt > 16) {
2932 PMD_DRV_LOG(DEBUG, "invalid xfer_cnt %d. Max is 16 bytes",
2934 return ELINK_STATUS_ERROR;
2937 elink_bsc_module_sel(params);
2939 xfer_cnt = 16 - lc_addr;
2941 /* Enable the engine */
2942 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
2943 val |= MCPR_IMC_COMMAND_ENABLE;
2944 REG_WR(sc, MCP_REG_MCPR_IMC_COMMAND, val);
2946 /* Program slave device ID */
2947 val = (sl_devid << 16) | sl_addr;
2948 REG_WR(sc, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);
2950 /* Start xfer with 0 byte to update the address pointer ??? */
2951 val = (MCPR_IMC_COMMAND_ENABLE) |
2952 (MCPR_IMC_COMMAND_WRITE_OP <<
2953 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
2954 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);
2955 REG_WR(sc, MCP_REG_MCPR_IMC_COMMAND, val);
2957 /* Poll for completion */
2959 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
2960 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
2962 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
2964 PMD_DRV_LOG(DEBUG, "wr 0 byte timed out after %d try",
2966 rc = ELINK_STATUS_TIMEOUT;
2970 if (rc == ELINK_STATUS_TIMEOUT)
2973 /* Start xfer with read op */
2974 val = (MCPR_IMC_COMMAND_ENABLE) |
2975 (MCPR_IMC_COMMAND_READ_OP <<
2976 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
2977 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) |
2979 REG_WR(sc, MCP_REG_MCPR_IMC_COMMAND, val);
2981 /* Poll for completion */
2983 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
2984 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
2986 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
2988 PMD_DRV_LOG(DEBUG, "rd op timed out after %d try", i);
2989 rc = ELINK_STATUS_TIMEOUT;
2993 if (rc == ELINK_STATUS_TIMEOUT)
2996 for (i = (lc_addr >> 2); i < 4; i++) {
2997 data_array[i] = REG_RD(sc, (MCP_REG_MCPR_IMC_DATAREG0 + i * 4));
2999 data_array[i] = ((data_array[i] & 0x000000ff) << 24) |
3000 ((data_array[i] & 0x0000ff00) << 8) |
3001 ((data_array[i] & 0x00ff0000) >> 8) |
3002 ((data_array[i] & 0xff000000) >> 24);
3008 static void elink_cl45_read_or_write(struct bnx2x_softc *sc,
3009 struct elink_phy *phy, uint8_t devad,
3010 uint16_t reg, uint16_t or_val)
3013 elink_cl45_read(sc, phy, devad, reg, &val);
3014 elink_cl45_write(sc, phy, devad, reg, val | or_val);
3017 static void elink_cl45_read_and_write(struct bnx2x_softc *sc,
3018 struct elink_phy *phy,
3019 uint8_t devad, uint16_t reg,
3023 elink_cl45_read(sc, phy, devad, reg, &val);
3024 elink_cl45_write(sc, phy, devad, reg, val & and_val);
3027 static uint8_t elink_get_warpcore_lane(struct elink_params *params)
3030 struct bnx2x_softc *sc = params->sc;
3031 uint32_t path_swap, path_swap_ovr;
3035 port = params->port;
3037 if (elink_is_4_port_mode(sc)) {
3038 uint32_t port_swap, port_swap_ovr;
3040 /* Figure out path swap value */
3041 path_swap_ovr = REG_RD(sc, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);
3042 if (path_swap_ovr & 0x1)
3043 path_swap = (path_swap_ovr & 0x2);
3045 path_swap = REG_RD(sc, MISC_REG_FOUR_PORT_PATH_SWAP);
3050 /* Figure out port swap value */
3051 port_swap_ovr = REG_RD(sc, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);
3052 if (port_swap_ovr & 0x1)
3053 port_swap = (port_swap_ovr & 0x2);
3055 port_swap = REG_RD(sc, MISC_REG_FOUR_PORT_PORT_SWAP);
3060 lane = (port << 1) + path;
3061 } else { /* Two port mode - no port swap */
3063 /* Figure out path swap value */
3064 path_swap_ovr = REG_RD(sc, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
3065 if (path_swap_ovr & 0x1) {
3066 path_swap = (path_swap_ovr & 0x2);
3068 path_swap = REG_RD(sc, MISC_REG_TWO_PORT_PATH_SWAP);
3078 static void elink_set_aer_mmd(struct elink_params *params,
3079 struct elink_phy *phy)
3082 uint16_t offset, aer_val;
3083 struct bnx2x_softc *sc = params->sc;
3084 ser_lane = ((params->lane_config &
3085 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
3086 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
3088 offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
3089 (phy->addr + ser_lane) : 0;
3091 if (USES_WARPCORE(sc)) {
3092 aer_val = elink_get_warpcore_lane(params);
3093 /* In Dual-lane mode, two lanes are joined together,
3094 * so in order to configure them, the AER broadcast method is
3096 * 0x200 is the broadcast address for lanes 0,1
3097 * 0x201 is the broadcast address for lanes 2,3
3099 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)
3100 aer_val = (aer_val >> 1) | 0x200;
3101 } else if (CHIP_IS_E2(sc))
3102 aer_val = 0x3800 + offset - 1;
3104 aer_val = 0x3800 + offset;
3106 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
3107 MDIO_AER_BLOCK_AER_REG, aer_val);
3111 /******************************************************************/
3112 /* Internal phy section */
3113 /******************************************************************/
3115 static void elink_set_serdes_access(struct bnx2x_softc *sc, uint8_t port)
3117 uint32_t emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3120 REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_ST + port * 0x10, 1);
3121 REG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
3123 REG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
3126 REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_ST + port * 0x10, 0);
3129 static void elink_serdes_deassert(struct bnx2x_softc *sc, uint8_t port)
3133 PMD_DRV_LOG(DEBUG, "elink_serdes_deassert");
3135 val = ELINK_SERDES_RESET_BITS << (port * 16);
3137 /* Reset and unreset the SerDes/XGXS */
3138 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3140 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3142 elink_set_serdes_access(sc, port);
3144 REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_DEVAD + port * 0x10,
3145 ELINK_DEFAULT_PHY_DEV_ADDR);
3148 static void elink_xgxs_specific_func(struct elink_phy *phy,
3149 struct elink_params *params,
3152 struct bnx2x_softc *sc = params->sc;
3154 case ELINK_PHY_INIT:
3155 /* Set correct devad */
3156 REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_ST + params->port * 0x18, 0);
3157 REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port * 0x18,
3163 static void elink_xgxs_deassert(struct elink_params *params)
3165 struct bnx2x_softc *sc = params->sc;
3168 PMD_DRV_LOG(DEBUG, "elink_xgxs_deassert");
3169 port = params->port;
3171 val = ELINK_XGXS_RESET_BITS << (port * 16);
3173 /* Reset and unreset the SerDes/XGXS */
3174 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3176 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3177 elink_xgxs_specific_func(¶ms->phy[ELINK_INT_PHY], params,
3181 static void elink_calc_ieee_aneg_adv(struct elink_phy *phy,
3182 struct elink_params *params,
3185 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
3186 /* Resolve pause mode and advertisement Please refer to Table
3187 * 28B-3 of the 802.3ab-1999 spec
3190 switch (phy->req_flow_ctrl) {
3191 case ELINK_FLOW_CTRL_AUTO:
3192 switch (params->req_fc_auto_adv) {
3193 case ELINK_FLOW_CTRL_BOTH:
3194 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3196 case ELINK_FLOW_CTRL_RX:
3197 case ELINK_FLOW_CTRL_TX:
3199 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3205 case ELINK_FLOW_CTRL_TX:
3206 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3209 case ELINK_FLOW_CTRL_RX:
3210 case ELINK_FLOW_CTRL_BOTH:
3211 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3214 case ELINK_FLOW_CTRL_NONE:
3216 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3219 PMD_DRV_LOG(DEBUG, "ieee_fc = 0x%x", *ieee_fc);
3222 static void set_phy_vars(struct elink_params *params, struct elink_vars *vars)
3224 uint8_t actual_phy_idx, phy_index, link_cfg_idx;
3225 uint8_t phy_config_swapped = params->multi_phy_config &
3226 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
3227 for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys;
3229 link_cfg_idx = ELINK_LINK_CONFIG_IDX(phy_index);
3230 actual_phy_idx = phy_index;
3231 if (phy_config_swapped) {
3232 if (phy_index == ELINK_EXT_PHY1)
3233 actual_phy_idx = ELINK_EXT_PHY2;
3234 else if (phy_index == ELINK_EXT_PHY2)
3235 actual_phy_idx = ELINK_EXT_PHY1;
3237 params->phy[actual_phy_idx].req_flow_ctrl =
3238 params->req_flow_ctrl[link_cfg_idx];
3240 params->phy[actual_phy_idx].req_line_speed =
3241 params->req_line_speed[link_cfg_idx];
3243 params->phy[actual_phy_idx].speed_cap_mask =
3244 params->speed_cap_mask[link_cfg_idx];
3246 params->phy[actual_phy_idx].req_duplex =
3247 params->req_duplex[link_cfg_idx];
3249 if (params->req_line_speed[link_cfg_idx] ==
3250 ELINK_SPEED_AUTO_NEG)
3251 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
3253 PMD_DRV_LOG(DEBUG, "req_flow_ctrl %x, req_line_speed %x,"
3254 " speed_cap_mask %x",
3255 params->phy[actual_phy_idx].req_flow_ctrl,
3256 params->phy[actual_phy_idx].req_line_speed,
3257 params->phy[actual_phy_idx].speed_cap_mask);
3261 static void elink_ext_phy_set_pause(struct elink_params *params,
3262 struct elink_phy *phy,
3263 struct elink_vars *vars)
3266 struct bnx2x_softc *sc = params->sc;
3267 /* Read modify write pause advertizing */
3268 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
3270 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
3272 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3273 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3274 if ((vars->ieee_fc &
3275 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3276 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3277 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3279 if ((vars->ieee_fc &
3280 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3281 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3282 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
3284 PMD_DRV_LOG(DEBUG, "Ext phy AN advertize 0x%x", val);
3285 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
3288 static void elink_pause_resolve(struct elink_vars *vars, uint32_t pause_result)
3290 switch (pause_result) { /* ASYM P ASYM P */
3291 case 0xb: /* 1 0 1 1 */
3292 vars->flow_ctrl = ELINK_FLOW_CTRL_TX;
3295 case 0xe: /* 1 1 1 0 */
3296 vars->flow_ctrl = ELINK_FLOW_CTRL_RX;
3299 case 0x5: /* 0 1 0 1 */
3300 case 0x7: /* 0 1 1 1 */
3301 case 0xd: /* 1 1 0 1 */
3302 case 0xf: /* 1 1 1 1 */
3303 vars->flow_ctrl = ELINK_FLOW_CTRL_BOTH;
3309 if (pause_result & (1 << 0))
3310 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
3311 if (pause_result & (1 << 1))
3312 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
3316 static void elink_ext_phy_update_adv_fc(struct elink_phy *phy,
3317 struct elink_params *params,
3318 struct elink_vars *vars)
3320 uint16_t ld_pause; /* local */
3321 uint16_t lp_pause; /* link partner */
3322 uint16_t pause_result;
3323 struct bnx2x_softc *sc = params->sc;
3324 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE) {
3325 elink_cl22_read(sc, phy, 0x4, &ld_pause);
3326 elink_cl22_read(sc, phy, 0x5, &lp_pause);
3327 } else if (CHIP_IS_E3(sc) && ELINK_SINGLE_MEDIA_DIRECT(params)) {
3328 uint8_t lane = elink_get_warpcore_lane(params);
3329 uint16_t gp_status, gp_mask;
3330 elink_cl45_read(sc, phy,
3331 MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4,
3333 gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL |
3334 MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) <<
3336 if ((gp_status & gp_mask) == gp_mask) {
3337 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
3338 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3339 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
3340 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3342 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
3343 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
3344 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
3345 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
3346 ld_pause = ((ld_pause &
3347 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3349 lp_pause = ((lp_pause &
3350 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3354 elink_cl45_read(sc, phy,
3356 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3357 elink_cl45_read(sc, phy,
3359 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3361 pause_result = (ld_pause & MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
3362 pause_result |= (lp_pause & MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
3363 PMD_DRV_LOG(DEBUG, "Ext PHY pause result 0x%x", pause_result);
3364 elink_pause_resolve(vars, pause_result);
3368 static uint8_t elink_ext_phy_resolve_fc(struct elink_phy *phy,
3369 struct elink_params *params,
3370 struct elink_vars *vars)
3373 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
3374 if (phy->req_flow_ctrl != ELINK_FLOW_CTRL_AUTO) {
3375 /* Update the advertised flow-controled of LD/LP in AN */
3376 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)
3377 elink_ext_phy_update_adv_fc(phy, params, vars);
3378 /* But set the flow-control result as the requested one */
3379 vars->flow_ctrl = phy->req_flow_ctrl;
3380 } else if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG)
3381 vars->flow_ctrl = params->req_fc_auto_adv;
3382 else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
3384 elink_ext_phy_update_adv_fc(phy, params, vars);
3389 /******************************************************************/
3390 /* Warpcore section */
3391 /******************************************************************/
3392 /* The init_internal_warpcore should mirror the xgxs,
3393 * i.e. reset the lane (if needed), set aer for the
3394 * init configuration, and set/clear SGMII flag. Internal
3395 * phy init is done purely in phy_init stage.
3397 #define WC_TX_DRIVER(post2, idriver, ipre) \
3398 ((post2 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | \
3399 (idriver << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | \
3400 (ipre << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET))
3402 #define WC_TX_FIR(post, main, pre) \
3403 ((post << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | \
3404 (main << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | \
3405 (pre << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET))
3407 static void elink_warpcore_enable_AN_KR2(struct elink_phy *phy,
3408 struct elink_params *params,
3409 struct elink_vars *vars)
3411 struct bnx2x_softc *sc = params->sc;
3413 static struct elink_reg_set reg_set[] = {
3414 /* Step 1 - Program the TX/RX alignment markers */
3415 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0xa157},
3416 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xcbe2},
3417 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0x7537},
3418 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0xa157},
3419 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xcbe2},
3420 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0x7537},
3421 /* Step 2 - Configure the NP registers */
3422 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000a},
3423 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6400},
3424 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0620},
3425 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0157},
3426 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x6464},
3427 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x3150},
3428 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x3150},
3429 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0157},
3430 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0620}
3432 PMD_DRV_LOG(DEBUG, "Enabling 20G-KR2");
3434 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3435 MDIO_WC_REG_CL49_USERB0_CTRL, (3 << 6));
3437 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3438 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
3441 /* Start KR2 work-around timer which handles BNX2X8073 link-parner */
3442 vars->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE;
3443 elink_update_link_attr(params, vars->link_attr_sync);
3446 static void elink_disable_kr2(struct elink_params *params,
3447 struct elink_vars *vars, struct elink_phy *phy)
3449 struct bnx2x_softc *sc = params->sc;
3451 static struct elink_reg_set reg_set[] = {
3452 /* Step 1 - Program the TX/RX alignment markers */
3453 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0x7690},
3454 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xe647},
3455 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0xc4f0},
3456 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0x7690},
3457 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xe647},
3458 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0xc4f0},
3459 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000c},
3460 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6000},
3461 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0000},
3462 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0002},
3463 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x0000},
3464 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x0af7},
3465 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x0af7},
3466 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0002},
3467 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0000}
3469 PMD_DRV_LOG(DEBUG, "Disabling 20G-KR2");
3471 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3472 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
3474 vars->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE;
3475 elink_update_link_attr(params, vars->link_attr_sync);
3477 vars->check_kr2_recovery_cnt = ELINK_CHECK_KR2_RECOVERY_CNT;
3480 static void elink_warpcore_set_lpi_passthrough(struct elink_phy *phy,
3481 struct elink_params *params)
3483 struct bnx2x_softc *sc = params->sc;
3485 PMD_DRV_LOG(DEBUG, "Configure WC for LPI pass through");
3486 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3487 MDIO_WC_REG_EEE_COMBO_CONTROL0, 0x7c);
3488 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3489 MDIO_WC_REG_DIGITAL4_MISC5, 0xc000);
3492 static void elink_warpcore_restart_AN_KR(struct elink_phy *phy,
3493 struct elink_params *params)
3495 /* Restart autoneg on the leading lane only */
3496 struct bnx2x_softc *sc = params->sc;
3497 uint16_t lane = elink_get_warpcore_lane(params);
3498 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
3499 MDIO_AER_BLOCK_AER_REG, lane);
3500 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
3501 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
3504 elink_set_aer_mmd(params, phy);
3507 static void elink_warpcore_enable_AN_KR(struct elink_phy *phy,
3508 struct elink_params *params,
3509 struct elink_vars *vars)
3511 uint16_t lane, i, cl72_ctrl, an_adv = 0;
3512 struct bnx2x_softc *sc = params->sc;
3513 static struct elink_reg_set reg_set[] = {
3514 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
3515 {MDIO_PMA_DEVAD, MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0},
3516 {MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415},
3517 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190},
3518 /* Disable Autoneg: re-enable it after adv is done. */
3519 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0},
3520 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2},
3521 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0},
3523 PMD_DRV_LOG(DEBUG, "Enable Auto Negotiation for KR");
3524 /* Set to default registers that may be overriden by 10G force */
3525 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3526 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
3529 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3530 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &cl72_ctrl);
3531 cl72_ctrl &= 0x08ff;
3532 cl72_ctrl |= 0x3800;
3533 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3534 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, cl72_ctrl);
3536 /* Check adding advertisement for 1G KX */
3537 if (((vars->line_speed == ELINK_SPEED_AUTO_NEG) &&
3538 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
3539 (vars->line_speed == ELINK_SPEED_1000)) {
3540 uint16_t addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2;
3543 /* Enable CL37 1G Parallel Detect */
3544 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, addr, 0x1);
3545 PMD_DRV_LOG(DEBUG, "Advertize 1G");
3547 if (((vars->line_speed == ELINK_SPEED_AUTO_NEG) &&
3548 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
3549 (vars->line_speed == ELINK_SPEED_10000)) {
3550 /* Check adding advertisement for 10G KR */
3552 /* Enable 10G Parallel Detect */
3553 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
3554 MDIO_AER_BLOCK_AER_REG, 0);
3556 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
3557 MDIO_WC_REG_PAR_DET_10G_CTRL, 1);
3558 elink_set_aer_mmd(params, phy);
3559 PMD_DRV_LOG(DEBUG, "Advertize 10G");
3562 /* Set Transmit PMD settings */
3563 lane = elink_get_warpcore_lane(params);
3564 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3565 MDIO_WC_REG_TX0_TX_DRIVER + 0x10 * lane,
3566 WC_TX_DRIVER(0x02, 0x06, 0x09));
3567 /* Configure the next lane if dual mode */
3568 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)
3569 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3570 MDIO_WC_REG_TX0_TX_DRIVER + 0x10 * (lane + 1),
3571 WC_TX_DRIVER(0x02, 0x06, 0x09));
3572 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3573 MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL, 0x03f0);
3574 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3575 MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL, 0x03f0);
3577 /* Advertised speeds */
3578 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
3579 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, an_adv);
3581 /* Advertised and set FEC (Forward Error Correction) */
3582 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
3583 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2,
3584 (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY |
3585 MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ));
3587 /* Enable CL37 BAM */
3588 if (REG_RD(sc, params->shmem_base +
3589 offsetof(struct shmem_region,
3590 dev_info.port_hw_config[params->port].
3592 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
3593 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3594 MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL,
3596 PMD_DRV_LOG(DEBUG, "Enable CL37 BAM on KR");
3599 /* Advertise pause */
3600 elink_ext_phy_set_pause(params, phy, vars);
3601 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
3602 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3603 MDIO_WC_REG_DIGITAL5_MISC7, 0x100);
3605 /* Over 1G - AN local device user page 1 */
3606 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3607 MDIO_WC_REG_DIGITAL3_UP1, 0x1f);
3609 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
3610 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) ||
3611 (phy->req_line_speed == ELINK_SPEED_20000)) {
3613 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
3614 MDIO_AER_BLOCK_AER_REG, lane);
3616 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3617 MDIO_WC_REG_RX1_PCI_CTRL +
3618 (0x10 * lane), (1 << 11));
3620 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3621 MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7);
3622 elink_set_aer_mmd(params, phy);
3624 elink_warpcore_enable_AN_KR2(phy, params, vars);
3626 elink_disable_kr2(params, vars, phy);
3629 /* Enable Autoneg: only on the main lane */
3630 elink_warpcore_restart_AN_KR(phy, params);
3633 static void elink_warpcore_set_10G_KR(struct elink_phy *phy,
3634 struct elink_params *params)
3636 struct bnx2x_softc *sc = params->sc;
3637 uint16_t val16, i, lane;
3638 static struct elink_reg_set reg_set[] = {
3639 /* Disable Autoneg */
3640 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
3641 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3643 {MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0},
3644 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0},
3645 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1},
3646 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa},
3647 /* Leave cl72 training enable, needed for KR */
3648 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2}
3651 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3652 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
3655 lane = elink_get_warpcore_lane(params);
3656 /* Global registers */
3657 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
3658 MDIO_AER_BLOCK_AER_REG, 0);
3659 /* Disable CL36 PCS Tx */
3660 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3661 MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
3662 val16 &= ~(0x0011 << lane);
3663 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3664 MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);
3666 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3667 MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);
3668 val16 |= (0x0303 << (lane << 1));
3669 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3670 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);
3672 elink_set_aer_mmd(params, phy);
3673 /* Set speed via PMA/PMD register */
3674 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD,
3675 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
3677 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD,
3678 MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB);
3680 /* Enable encoded forced speed */
3681 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3682 MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30);
3684 /* Turn TX scramble payload only the 64/66 scrambler */
3685 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_TX66_CONTROL, 0x9);
3687 /* Turn RX scramble payload only the 64/66 scrambler */
3688 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3689 MDIO_WC_REG_RX66_CONTROL, 0xF9);
3691 /* Set and clear loopback to cause a reset to 64/66 decoder */
3692 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3693 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000);
3694 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3695 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3699 static void elink_warpcore_set_10G_XFI(struct elink_phy *phy,
3700 struct elink_params *params,
3703 struct bnx2x_softc *sc = params->sc;
3704 uint16_t misc1_val, tap_val, tx_driver_val, lane, val;
3705 uint32_t cfg_tap_val, tx_drv_brdct, tx_equal;
3707 /* Hold rxSeqStart */
3708 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3709 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000);
3711 /* Hold tx_fifo_reset */
3712 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3713 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x1);
3715 /* Disable CL73 AN */
3716 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
3718 /* Disable 100FX Enable and Auto-Detect */
3719 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
3720 MDIO_WC_REG_FX100_CTRL1, 0xFFFA);
3722 /* Disable 100FX Idle detect */
3723 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3724 MDIO_WC_REG_FX100_CTRL3, 0x0080);
3726 /* Set Block address to Remote PHY & Clear forced_speed[5] */
3727 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
3728 MDIO_WC_REG_DIGITAL4_MISC3, 0xFF7F);
3730 /* Turn off auto-detect & fiber mode */
3731 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
3732 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3735 /* Set filter_force_link, disable_false_link and parallel_detect */
3736 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3737 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val);
3738 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3739 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3740 ((val | 0x0006) & 0xFFFE));
3743 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3744 MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val);
3746 misc1_val &= ~(0x1f);
3750 tap_val = WC_TX_FIR(0x08, 0x37, 0x00);
3751 tx_driver_val = WC_TX_DRIVER(0x00, 0x02, 0x03);
3753 cfg_tap_val = REG_RD(sc, params->shmem_base +
3754 offsetof(struct shmem_region,
3755 dev_info.port_hw_config[params->
3756 port].sfi_tap_values));
3758 tx_equal = cfg_tap_val & PORT_HW_CFG_TX_EQUALIZATION_MASK;
3760 tx_drv_brdct = (cfg_tap_val &
3761 PORT_HW_CFG_TX_DRV_BROADCAST_MASK) >>
3762 PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT;
3766 /* TAP values are controlled by nvram, if value there isn't 0 */
3768 tap_val = (uint16_t) tx_equal;
3770 tap_val = WC_TX_FIR(0x0f, 0x2b, 0x02);
3774 WC_TX_DRIVER(0x03, (uint16_t) tx_drv_brdct, 0x06);
3776 tx_driver_val = WC_TX_DRIVER(0x03, 0x02, 0x06);
3778 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3779 MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val);
3781 /* Set Transmit PMD settings */
3782 lane = elink_get_warpcore_lane(params);
3783 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3784 MDIO_WC_REG_TX_FIR_TAP,
3785 tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE);
3786 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3787 MDIO_WC_REG_TX0_TX_DRIVER + 0x10 * lane,
3790 /* Enable fiber mode, enable and invert sig_det */
3791 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3792 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0xd);
3794 /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */
3795 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3796 MDIO_WC_REG_DIGITAL4_MISC3, 0x8080);
3798 elink_warpcore_set_lpi_passthrough(phy, params);
3800 /* 10G XFI Full Duplex */
3801 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3802 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100);
3804 /* Release tx_fifo_reset */
3805 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
3806 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
3808 /* Release rxSeqStart */
3809 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
3810 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x7FFF);
3813 static void elink_warpcore_set_20G_force_KR2(struct elink_phy *phy,
3814 struct elink_params *params)
3817 struct bnx2x_softc *sc = params->sc;
3818 /* Set global registers, so set AER lane to 0 */
3819 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
3820 MDIO_AER_BLOCK_AER_REG, 0);
3822 /* Disable sequencer */
3823 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
3824 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~(1 << 13));
3826 elink_set_aer_mmd(params, phy);
3828 elink_cl45_read_and_write(sc, phy, MDIO_PMA_DEVAD,
3829 MDIO_WC_REG_PMD_KR_CONTROL, ~(1 << 1));
3830 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
3832 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3833 MDIO_WC_REG_CL73_USERB0_CTRL, &val);
3836 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3837 MDIO_WC_REG_CL73_USERB0_CTRL, val);
3839 /* Set 20G KR2 force speed */
3840 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3841 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x1f);
3843 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3844 MDIO_WC_REG_DIGITAL4_MISC3, (1 << 7));
3846 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3847 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &val);
3850 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3851 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, val);
3852 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3853 MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0x835A);
3855 /* Enable sequencer (over lane 0) */
3856 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
3857 MDIO_AER_BLOCK_AER_REG, 0);
3859 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3860 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, (1 << 13));
3862 elink_set_aer_mmd(params, phy);
3865 static void elink_warpcore_set_20G_DXGXS(struct bnx2x_softc *sc,
3866 struct elink_phy *phy, uint16_t lane)
3868 /* Rx0 anaRxControl1G */
3869 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3870 MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90);
3872 /* Rx2 anaRxControl1G */
3873 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3874 MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90);
3876 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_RX66_SCW0, 0xE070);
3878 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_RX66_SCW1, 0xC0D0);
3880 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_RX66_SCW2, 0xA0B0);
3882 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_RX66_SCW3, 0x8090);
3884 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3885 MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0);
3887 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3888 MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0);
3890 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3891 MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0);
3893 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3894 MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0);
3896 /* Serdes Digital Misc1 */
3897 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3898 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008);
3900 /* Serdes Digital4 Misc3 */
3901 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3902 MDIO_WC_REG_DIGITAL4_MISC3, 0x8088);
3904 /* Set Transmit PMD settings */
3905 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3906 MDIO_WC_REG_TX_FIR_TAP,
3907 (WC_TX_FIR(0x12, 0x2d, 0x00) |
3908 MDIO_WC_REG_TX_FIR_TAP_ENABLE));
3909 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3910 MDIO_WC_REG_TX0_TX_DRIVER + 0x10 * lane,
3911 WC_TX_DRIVER(0x02, 0x02, 0x02));
3914 static void elink_warpcore_set_sgmii_speed(struct elink_phy *phy,
3915 struct elink_params *params,
3917 uint8_t always_autoneg)
3919 struct bnx2x_softc *sc = params->sc;
3920 uint16_t val16, digctrl_kx1, digctrl_kx2;
3922 /* Clear XFI clock comp in non-10G single lane mode. */
3923 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
3924 MDIO_WC_REG_RX66_CONTROL, ~(3 << 13));
3926 elink_warpcore_set_lpi_passthrough(phy, params);
3928 if (always_autoneg || phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {
3930 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3931 MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
3933 PMD_DRV_LOG(DEBUG, "set SGMII AUTONEG");
3935 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3936 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
3938 switch (phy->req_line_speed) {
3939 case ELINK_SPEED_10:
3941 case ELINK_SPEED_100:
3944 case ELINK_SPEED_1000:
3949 "Speed not supported: 0x%x",
3950 phy->req_line_speed);
3954 if (phy->req_duplex == DUPLEX_FULL)
3957 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3958 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);
3960 PMD_DRV_LOG(DEBUG, "set SGMII force speed %d",
3961 phy->req_line_speed);
3962 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3963 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
3964 PMD_DRV_LOG(DEBUG, " (readback) %x", val16);
3967 /* SGMII Slave mode and disable signal detect */
3968 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3969 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1);
3973 digctrl_kx1 &= 0xff4a;
3975 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3976 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, digctrl_kx1);
3978 /* Turn off parallel detect */
3979 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3980 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2);
3981 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3982 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3983 (digctrl_kx2 & ~(1 << 2)));
3985 /* Re-enable parallel detect */
3986 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3987 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3988 (digctrl_kx2 | (1 << 2)));
3990 /* Enable autodet */
3991 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3992 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3993 (digctrl_kx1 | 0x10));
3996 static void elink_warpcore_reset_lane(struct bnx2x_softc *sc,
3997 struct elink_phy *phy, uint8_t reset)
4000 /* Take lane out of reset after configuration is finished */
4001 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4002 MDIO_WC_REG_DIGITAL5_MISC6, &val);
4007 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4008 MDIO_WC_REG_DIGITAL5_MISC6, val);
4009 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4010 MDIO_WC_REG_DIGITAL5_MISC6, &val);
4013 /* Clear SFI/XFI link settings registers */
4014 static void elink_warpcore_clear_regs(struct elink_phy *phy,
4015 struct elink_params *params,
4018 struct bnx2x_softc *sc = params->sc;
4020 static struct elink_reg_set wc_regs[] = {
4021 {MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0},
4022 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL1, 0x014a},
4023 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800},
4024 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008},
4025 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4027 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4029 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
4031 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000},
4032 {MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000},
4033 {MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040},
4034 {MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140}
4036 /* Set XFI clock comp as default. */
4037 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4038 MDIO_WC_REG_RX66_CONTROL, (3 << 13));
4040 for (i = 0; i < ARRAY_SIZE(wc_regs); i++)
4041 elink_cl45_write(sc, phy, wc_regs[i].devad, wc_regs[i].reg,
4044 lane = elink_get_warpcore_lane(params);
4045 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4046 MDIO_WC_REG_TX0_TX_DRIVER + 0x10 * lane, 0x0990);
4050 static elink_status_t elink_get_mod_abs_int_cfg(struct bnx2x_softc *sc,
4051 uint32_t shmem_base,
4054 uint8_t * gpio_port)
4059 if (CHIP_IS_E3(sc)) {
4060 cfg_pin = (REG_RD(sc, shmem_base +
4061 offsetof(struct shmem_region,
4062 dev_info.port_hw_config[port].
4064 PORT_HW_CFG_E3_MOD_ABS_MASK) >>
4065 PORT_HW_CFG_E3_MOD_ABS_SHIFT;
4067 /* Should not happen. This function called upon interrupt
4068 * triggered by GPIO ( since EPIO can only generate interrupts
4070 * So if this function was called and none of the GPIOs was set,
4071 * it means the shit hit the fan.
4073 if ((cfg_pin < PIN_CFG_GPIO0_P0) ||
4074 (cfg_pin > PIN_CFG_GPIO3_P1)) {
4076 "No cfg pin %x for module detect indication",
4078 return ELINK_STATUS_ERROR;
4081 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3;
4082 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2;
4084 *gpio_num = MISC_REGISTERS_GPIO_3;
4088 return ELINK_STATUS_OK;
4091 static int elink_is_sfp_module_plugged(struct elink_params *params)
4093 struct bnx2x_softc *sc = params->sc;
4094 uint8_t gpio_num, gpio_port;
4096 if (elink_get_mod_abs_int_cfg(sc,
4097 params->shmem_base, params->port,
4098 &gpio_num, &gpio_port) != ELINK_STATUS_OK)
4100 gpio_val = elink_cb_gpio_read(sc, gpio_num, gpio_port);
4102 /* Call the handling function in case module is detected */
4109 static int elink_warpcore_get_sigdet(struct elink_phy *phy,
4110 struct elink_params *params)
4112 uint16_t gp2_status_reg0, lane;
4113 struct bnx2x_softc *sc = params->sc;
4115 lane = elink_get_warpcore_lane(params);
4117 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0,
4120 return (gp2_status_reg0 >> (8 + lane)) & 0x1;
4123 static void elink_warpcore_config_runtime(struct elink_phy *phy,
4124 struct elink_params *params,
4125 struct elink_vars *vars)
4127 struct bnx2x_softc *sc = params->sc;
4128 uint32_t serdes_net_if;
4129 uint16_t gp_status1 = 0, lnkup = 0, lnkup_kr = 0;
4131 vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1;
4133 if (!vars->turn_to_run_wc_rt)
4136 if (vars->rx_tx_asic_rst) {
4137 uint16_t lane = elink_get_warpcore_lane(params);
4138 serdes_net_if = (REG_RD(sc, params->shmem_base +
4139 offsetof(struct shmem_region,
4140 dev_info.port_hw_config
4143 PORT_HW_CFG_NET_SERDES_IF_MASK);
4145 switch (serdes_net_if) {
4146 case PORT_HW_CFG_NET_SERDES_IF_KR:
4147 /* Do we get link yet? */
4148 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 0x81d1,
4150 lnkup = (gp_status1 >> (8 + lane)) & 0x1; /* 1G */
4152 lnkup_kr = (gp_status1 >> (12 + lane)) & 0x1;
4154 if (lnkup_kr || lnkup) {
4155 vars->rx_tx_asic_rst = 0;
4157 /* Reset the lane to see if link comes up. */
4158 elink_warpcore_reset_lane(sc, phy, 1);
4159 elink_warpcore_reset_lane(sc, phy, 0);
4161 /* Restart Autoneg */
4162 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
4163 MDIO_WC_REG_IEEE0BLK_MIICNTL,
4166 vars->rx_tx_asic_rst--;
4167 PMD_DRV_LOG(DEBUG, "0x%x retry left",
4168 vars->rx_tx_asic_rst);
4177 /*params->rx_tx_asic_rst */
4180 static void elink_warpcore_config_sfi(struct elink_phy *phy,
4181 struct elink_params *params)
4183 uint16_t lane = elink_get_warpcore_lane(params);
4185 elink_warpcore_clear_regs(phy, params, lane);
4186 if ((params->req_line_speed[ELINK_LINK_CONFIG_IDX(ELINK_INT_PHY)] ==
4187 ELINK_SPEED_10000) &&
4188 (phy->media_type != ELINK_ETH_PHY_SFP_1G_FIBER)) {
4189 PMD_DRV_LOG(DEBUG, "Setting 10G SFI");
4190 elink_warpcore_set_10G_XFI(phy, params, 0);
4192 PMD_DRV_LOG(DEBUG, "Setting 1G Fiber");
4193 elink_warpcore_set_sgmii_speed(phy, params, 1, 0);
4197 static void elink_sfp_e3_set_transmitter(struct elink_params *params,
4198 struct elink_phy *phy, uint8_t tx_en)
4200 struct bnx2x_softc *sc = params->sc;
4202 uint8_t port = params->port;
4204 cfg_pin = REG_RD(sc, params->shmem_base +
4205 offsetof(struct shmem_region,
4206 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4207 PORT_HW_CFG_E3_TX_LASER_MASK;
4208 /* Set the !tx_en since this pin is DISABLE_TX_LASER */
4209 PMD_DRV_LOG(DEBUG, "Setting WC TX to %d", tx_en);
4211 /* For 20G, the expected pin to be used is 3 pins after the current */
4212 elink_set_cfg_pin(sc, cfg_pin, tx_en ^ 1);
4213 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
4214 elink_set_cfg_pin(sc, cfg_pin + 3, tx_en ^ 1);
4217 static void elink_warpcore_config_init(struct elink_phy *phy,
4218 struct elink_params *params,
4219 struct elink_vars *vars)
4221 struct bnx2x_softc *sc = params->sc;
4222 uint32_t serdes_net_if;
4224 uint16_t lane = elink_get_warpcore_lane(params);
4225 serdes_net_if = (REG_RD(sc, params->shmem_base +
4226 offsetof(struct shmem_region,
4227 dev_info.port_hw_config[params->port].
4229 PORT_HW_CFG_NET_SERDES_IF_MASK);
4231 "Begin Warpcore init, link_speed %d, "
4232 "serdes_net_if = 0x%x", vars->line_speed, serdes_net_if);
4233 elink_set_aer_mmd(params, phy);
4234 elink_warpcore_reset_lane(sc, phy, 1);
4235 vars->phy_flags |= PHY_XGXS_FLAG;
4236 if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) ||
4237 (phy->req_line_speed &&
4238 ((phy->req_line_speed == ELINK_SPEED_100) ||
4239 (phy->req_line_speed == ELINK_SPEED_10)))) {
4240 vars->phy_flags |= PHY_SGMII_FLAG;
4241 PMD_DRV_LOG(DEBUG, "Setting SGMII mode");
4242 elink_warpcore_clear_regs(phy, params, lane);
4243 elink_warpcore_set_sgmii_speed(phy, params, 0, 1);
4245 switch (serdes_net_if) {
4246 case PORT_HW_CFG_NET_SERDES_IF_KR:
4247 /* Enable KR Auto Neg */
4248 if (params->loopback_mode != ELINK_LOOPBACK_EXT)
4249 elink_warpcore_enable_AN_KR(phy, params, vars);
4251 PMD_DRV_LOG(DEBUG, "Setting KR 10G-Force");
4252 elink_warpcore_set_10G_KR(phy, params);
4256 case PORT_HW_CFG_NET_SERDES_IF_XFI:
4257 elink_warpcore_clear_regs(phy, params, lane);
4258 if (vars->line_speed == ELINK_SPEED_10000) {
4259 PMD_DRV_LOG(DEBUG, "Setting 10G XFI");
4260 elink_warpcore_set_10G_XFI(phy, params, 1);
4262 if (ELINK_SINGLE_MEDIA_DIRECT(params)) {
4263 PMD_DRV_LOG(DEBUG, "1G Fiber");
4266 PMD_DRV_LOG(DEBUG, "10/100/1G SGMII");
4269 elink_warpcore_set_sgmii_speed(phy,
4276 case PORT_HW_CFG_NET_SERDES_IF_SFI:
4277 /* Issue Module detection if module is plugged, or
4278 * enabled transmitter to avoid current leakage in case
4279 * no module is connected
4281 if ((params->loopback_mode == ELINK_LOOPBACK_NONE) ||
4282 (params->loopback_mode == ELINK_LOOPBACK_EXT)) {
4283 if (elink_is_sfp_module_plugged(params))
4284 elink_sfp_module_detection(phy, params);
4286 elink_sfp_e3_set_transmitter(params,
4290 elink_warpcore_config_sfi(phy, params);
4293 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
4294 if (vars->line_speed != ELINK_SPEED_20000) {
4295 PMD_DRV_LOG(DEBUG, "Speed not supported yet");
4298 PMD_DRV_LOG(DEBUG, "Setting 20G DXGXS");
4299 elink_warpcore_set_20G_DXGXS(sc, phy, lane);
4300 /* Issue Module detection */
4302 elink_sfp_module_detection(phy, params);
4304 case PORT_HW_CFG_NET_SERDES_IF_KR2:
4305 if (!params->loopback_mode) {
4306 elink_warpcore_enable_AN_KR(phy, params, vars);
4308 PMD_DRV_LOG(DEBUG, "Setting KR 20G-Force");
4309 elink_warpcore_set_20G_force_KR2(phy, params);
4314 "Unsupported Serdes Net Interface 0x%x",
4320 /* Take lane out of reset after configuration is finished */
4321 elink_warpcore_reset_lane(sc, phy, 0);
4322 PMD_DRV_LOG(DEBUG, "Exit config init");
4325 static void elink_warpcore_link_reset(struct elink_phy *phy,
4326 struct elink_params *params)
4328 struct bnx2x_softc *sc = params->sc;
4329 uint16_t val16, lane;
4330 elink_sfp_e3_set_transmitter(params, phy, 0);
4331 elink_set_mdio_emac_per_phy(sc, params);
4332 elink_set_aer_mmd(params, phy);
4333 /* Global register */
4334 elink_warpcore_reset_lane(sc, phy, 1);
4336 /* Clear loopback settings (if any) */
4338 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4339 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0xBFFF);
4341 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4342 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0xfffe);
4344 /* Update those 1-copy registers */
4345 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
4346 MDIO_AER_BLOCK_AER_REG, 0);
4347 /* Enable 1G MDIO (1-copy) */
4348 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4349 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~0x10);
4351 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4352 MDIO_WC_REG_XGXSBLK1_LANECTRL2, 0xff00);
4353 lane = elink_get_warpcore_lane(params);
4354 /* Disable CL36 PCS Tx */
4355 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4356 MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
4357 val16 |= (0x11 << lane);
4358 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)
4359 val16 |= (0x22 << lane);
4360 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4361 MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);
4363 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4364 MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);
4365 val16 &= ~(0x0303 << (lane << 1));
4366 val16 |= (0x0101 << (lane << 1));
4367 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE) {
4368 val16 &= ~(0x0c0c << (lane << 1));
4369 val16 |= (0x0404 << (lane << 1));
4372 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4373 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);
4375 elink_set_aer_mmd(params, phy);
4379 static void elink_set_warpcore_loopback(struct elink_phy *phy,
4380 struct elink_params *params)
4382 struct bnx2x_softc *sc = params->sc;
4385 PMD_DRV_LOG(DEBUG, "Setting Warpcore loopback type %x, speed %d",
4386 params->loopback_mode, phy->req_line_speed);
4388 if (phy->req_line_speed < ELINK_SPEED_10000 ||
4389 phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) {
4390 /* 10/100/1000/20G-KR2 */
4392 /* Update those 1-copy registers */
4393 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
4394 MDIO_AER_BLOCK_AER_REG, 0);
4395 /* Enable 1G MDIO (1-copy) */
4396 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4397 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4399 /* Set 1G loopback based on lane (1-copy) */
4400 lane = elink_get_warpcore_lane(params);
4401 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4402 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4403 val16 |= (1 << lane);
4404 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)
4405 val16 |= (2 << lane);
4406 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4407 MDIO_WC_REG_XGXSBLK1_LANECTRL2, val16);
4409 /* Switch back to 4-copy registers */
4410 elink_set_aer_mmd(params, phy);
4412 /* 10G / 20G-DXGXS */
4413 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4414 MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4416 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4417 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1);
4421 static void elink_sync_link(struct elink_params *params,
4422 struct elink_vars *vars)
4424 struct bnx2x_softc *sc = params->sc;
4425 uint8_t link_10g_plus;
4426 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4427 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
4428 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
4429 if (vars->link_up) {
4430 PMD_DRV_LOG(DEBUG, "phy link up");
4432 vars->phy_link_up = 1;
4433 vars->duplex = DUPLEX_FULL;
4434 switch (vars->link_status & LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
4435 case ELINK_LINK_10THD:
4436 vars->duplex = DUPLEX_HALF;
4438 case ELINK_LINK_10TFD:
4439 vars->line_speed = ELINK_SPEED_10;
4442 case ELINK_LINK_100TXHD:
4443 vars->duplex = DUPLEX_HALF;
4445 case ELINK_LINK_100T4:
4446 case ELINK_LINK_100TXFD:
4447 vars->line_speed = ELINK_SPEED_100;
4450 case ELINK_LINK_1000THD:
4451 vars->duplex = DUPLEX_HALF;
4453 case ELINK_LINK_1000TFD:
4454 vars->line_speed = ELINK_SPEED_1000;
4457 case ELINK_LINK_2500THD:
4458 vars->duplex = DUPLEX_HALF;
4460 case ELINK_LINK_2500TFD:
4461 vars->line_speed = ELINK_SPEED_2500;
4464 case ELINK_LINK_10GTFD:
4465 vars->line_speed = ELINK_SPEED_10000;
4467 case ELINK_LINK_20GTFD:
4468 vars->line_speed = ELINK_SPEED_20000;
4473 vars->flow_ctrl = 0;
4474 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
4475 vars->flow_ctrl |= ELINK_FLOW_CTRL_TX;
4477 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
4478 vars->flow_ctrl |= ELINK_FLOW_CTRL_RX;
4480 if (!vars->flow_ctrl)
4481 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
4483 if (vars->line_speed &&
4484 ((vars->line_speed == ELINK_SPEED_10) ||
4485 (vars->line_speed == ELINK_SPEED_100))) {
4486 vars->phy_flags |= PHY_SGMII_FLAG;
4488 vars->phy_flags &= ~PHY_SGMII_FLAG;
4490 if (vars->line_speed &&
4491 USES_WARPCORE(sc) && (vars->line_speed == ELINK_SPEED_1000))
4492 vars->phy_flags |= PHY_SGMII_FLAG;
4493 /* Anything 10 and over uses the bmac */
4494 link_10g_plus = (vars->line_speed >= ELINK_SPEED_10000);
4496 if (link_10g_plus) {
4497 if (USES_WARPCORE(sc))
4498 vars->mac_type = ELINK_MAC_TYPE_XMAC;
4500 vars->mac_type = ELINK_MAC_TYPE_BMAC;
4502 if (USES_WARPCORE(sc))
4503 vars->mac_type = ELINK_MAC_TYPE_UMAC;
4505 vars->mac_type = ELINK_MAC_TYPE_EMAC;
4507 } else { /* Link down */
4508 PMD_DRV_LOG(DEBUG, "phy link down");
4510 vars->phy_link_up = 0;
4512 vars->line_speed = 0;
4513 vars->duplex = DUPLEX_FULL;
4514 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
4516 /* Indicate no mac active */
4517 vars->mac_type = ELINK_MAC_TYPE_NONE;
4518 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4519 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
4520 if (vars->link_status & LINK_STATUS_SFP_TX_FAULT)
4521 vars->phy_flags |= PHY_SFP_TX_FAULT_FLAG;
4525 void elink_link_status_update(struct elink_params *params,
4526 struct elink_vars *vars)
4528 struct bnx2x_softc *sc = params->sc;
4529 uint8_t port = params->port;
4530 uint32_t sync_offset, media_types;
4531 /* Update PHY configuration */
4532 set_phy_vars(params, vars);
4534 vars->link_status = REG_RD(sc, params->shmem_base +
4535 offsetof(struct shmem_region,
4536 port_mb[port].link_status));
4538 /* Force link UP in non LOOPBACK_EXT loopback mode(s) */
4539 if (params->loopback_mode != ELINK_LOOPBACK_NONE &&
4540 params->loopback_mode != ELINK_LOOPBACK_EXT)
4541 vars->link_status |= LINK_STATUS_LINK_UP;
4543 if (elink_eee_has_cap(params))
4544 vars->eee_status = REG_RD(sc, params->shmem2_base +
4545 offsetof(struct shmem2_region,
4546 eee_status[params->port]));
4548 vars->phy_flags = PHY_XGXS_FLAG;
4549 elink_sync_link(params, vars);
4550 /* Sync media type */
4551 sync_offset = params->shmem_base +
4552 offsetof(struct shmem_region,
4553 dev_info.port_hw_config[port].media_type);
4554 media_types = REG_RD(sc, sync_offset);
4556 params->phy[ELINK_INT_PHY].media_type =
4557 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
4558 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
4559 params->phy[ELINK_EXT_PHY1].media_type =
4560 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
4561 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
4562 params->phy[ELINK_EXT_PHY2].media_type =
4563 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
4564 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
4565 PMD_DRV_LOG(DEBUG, "media_types = 0x%x", media_types);
4567 /* Sync AEU offset */
4568 sync_offset = params->shmem_base +
4569 offsetof(struct shmem_region,
4570 dev_info.port_hw_config[port].aeu_int_mask);
4572 vars->aeu_int_mask = REG_RD(sc, sync_offset);
4574 /* Sync PFC status */
4575 if (vars->link_status & LINK_STATUS_PFC_ENABLED)
4576 params->feature_config_flags |=
4577 ELINK_FEATURE_CONFIG_PFC_ENABLED;
4579 params->feature_config_flags &=
4580 ~ELINK_FEATURE_CONFIG_PFC_ENABLED;
4582 if (SHMEM2_HAS(sc, link_attr_sync))
4583 vars->link_attr_sync = SHMEM2_RD(sc,
4584 link_attr_sync[params->port]);
4586 PMD_DRV_LOG(DEBUG, "link_status 0x%x phy_link_up %x int_mask 0x%x",
4587 vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
4588 PMD_DRV_LOG(DEBUG, "line_speed %x duplex %x flow_ctrl 0x%x",
4589 vars->line_speed, vars->duplex, vars->flow_ctrl);
4592 static void elink_set_master_ln(struct elink_params *params,
4593 struct elink_phy *phy)
4595 struct bnx2x_softc *sc = params->sc;
4596 uint16_t new_master_ln, ser_lane;
4597 ser_lane = ((params->lane_config &
4598 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4599 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4601 /* Set the master_ln for AN */
4602 CL22_RD_OVER_CL45(sc, phy,
4603 MDIO_REG_BANK_XGXS_BLOCK2,
4604 MDIO_XGXS_BLOCK2_TEST_MODE_LANE, &new_master_ln);
4606 CL22_WR_OVER_CL45(sc, phy,
4607 MDIO_REG_BANK_XGXS_BLOCK2,
4608 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4609 (new_master_ln | ser_lane));
4612 static elink_status_t elink_reset_unicore(struct elink_params *params,
4613 struct elink_phy *phy,
4616 struct bnx2x_softc *sc = params->sc;
4617 uint16_t mii_control;
4619 CL22_RD_OVER_CL45(sc, phy,
4620 MDIO_REG_BANK_COMBO_IEEE0,
4621 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
4623 /* Reset the unicore */
4624 CL22_WR_OVER_CL45(sc, phy,
4625 MDIO_REG_BANK_COMBO_IEEE0,
4626 MDIO_COMBO_IEEE0_MII_CONTROL,
4627 (mii_control | MDIO_COMBO_IEEO_MII_CONTROL_RESET));
4629 elink_set_serdes_access(sc, params->port);
4631 /* Wait for the reset to self clear */
4632 for (i = 0; i < ELINK_MDIO_ACCESS_TIMEOUT; i++) {
4635 /* The reset erased the previous bank value */
4636 CL22_RD_OVER_CL45(sc, phy,
4637 MDIO_REG_BANK_COMBO_IEEE0,
4638 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
4640 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
4642 return ELINK_STATUS_OK;
4646 elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, params->port); // "Warning: PHY was not initialized,"
4649 PMD_DRV_LOG(DEBUG, "BUG! XGXS is still in reset!");
4650 return ELINK_STATUS_ERROR;
4654 static void elink_set_swap_lanes(struct elink_params *params,
4655 struct elink_phy *phy)
4657 struct bnx2x_softc *sc = params->sc;
4658 /* Each two bits represents a lane number:
4659 * No swap is 0123 => 0x1b no need to enable the swap
4661 uint16_t rx_lane_swap, tx_lane_swap;
4663 rx_lane_swap = ((params->lane_config &
4664 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
4665 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
4666 tx_lane_swap = ((params->lane_config &
4667 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
4668 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
4670 if (rx_lane_swap != 0x1b) {
4671 CL22_WR_OVER_CL45(sc, phy,
4672 MDIO_REG_BANK_XGXS_BLOCK2,
4673 MDIO_XGXS_BLOCK2_RX_LN_SWAP,
4675 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
4676 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
4678 CL22_WR_OVER_CL45(sc, phy,
4679 MDIO_REG_BANK_XGXS_BLOCK2,
4680 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
4683 if (tx_lane_swap != 0x1b) {
4684 CL22_WR_OVER_CL45(sc, phy,
4685 MDIO_REG_BANK_XGXS_BLOCK2,
4686 MDIO_XGXS_BLOCK2_TX_LN_SWAP,
4688 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
4690 CL22_WR_OVER_CL45(sc, phy,
4691 MDIO_REG_BANK_XGXS_BLOCK2,
4692 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
4696 static void elink_set_parallel_detection(struct elink_phy *phy,
4697 struct elink_params *params)
4699 struct bnx2x_softc *sc = params->sc;
4701 CL22_RD_OVER_CL45(sc, phy,
4702 MDIO_REG_BANK_SERDES_DIGITAL,
4703 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, &control2);
4704 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4705 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4707 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4708 PMD_DRV_LOG(DEBUG, "phy->speed_cap_mask = 0x%x, control2 = 0x%x",
4709 phy->speed_cap_mask, control2);
4710 CL22_WR_OVER_CL45(sc, phy,
4711 MDIO_REG_BANK_SERDES_DIGITAL,
4712 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, control2);
4714 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
4715 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
4716 PMD_DRV_LOG(DEBUG, "XGXS");
4718 CL22_WR_OVER_CL45(sc, phy,
4719 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4720 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
4721 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
4723 CL22_RD_OVER_CL45(sc, phy,
4724 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4725 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4729 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
4731 CL22_WR_OVER_CL45(sc, phy,
4732 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4733 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4736 /* Disable parallel detection of HiG */
4737 CL22_WR_OVER_CL45(sc, phy,
4738 MDIO_REG_BANK_XGXS_BLOCK2,
4739 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
4740 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
4741 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
4745 static void elink_set_autoneg(struct elink_phy *phy,
4746 struct elink_params *params,
4747 struct elink_vars *vars, uint8_t enable_cl73)
4749 struct bnx2x_softc *sc = params->sc;
4753 CL22_RD_OVER_CL45(sc, phy,
4754 MDIO_REG_BANK_COMBO_IEEE0,
4755 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val);
4757 /* CL37 Autoneg Enabled */
4758 if (vars->line_speed == ELINK_SPEED_AUTO_NEG)
4759 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
4760 else /* CL37 Autoneg Disabled */
4761 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4762 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
4764 CL22_WR_OVER_CL45(sc, phy,
4765 MDIO_REG_BANK_COMBO_IEEE0,
4766 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
4768 /* Enable/Disable Autodetection */
4770 CL22_RD_OVER_CL45(sc, phy,
4771 MDIO_REG_BANK_SERDES_DIGITAL,
4772 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, ®_val);
4773 reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
4774 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
4775 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
4776 if (vars->line_speed == ELINK_SPEED_AUTO_NEG)
4777 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
4779 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
4781 CL22_WR_OVER_CL45(sc, phy,
4782 MDIO_REG_BANK_SERDES_DIGITAL,
4783 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
4785 /* Enable TetonII and BAM autoneg */
4786 CL22_RD_OVER_CL45(sc, phy,
4787 MDIO_REG_BANK_BAM_NEXT_PAGE,
4788 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, ®_val);
4789 if (vars->line_speed == ELINK_SPEED_AUTO_NEG) {
4790 /* Enable BAM aneg Mode and TetonII aneg Mode */
4791 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
4792 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
4794 /* TetonII and BAM Autoneg Disabled */
4795 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
4796 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
4798 CL22_WR_OVER_CL45(sc, phy,
4799 MDIO_REG_BANK_BAM_NEXT_PAGE,
4800 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, reg_val);
4803 /* Enable Cl73 FSM status bits */
4804 CL22_WR_OVER_CL45(sc, phy,
4805 MDIO_REG_BANK_CL73_USERB0,
4806 MDIO_CL73_USERB0_CL73_UCTRL, 0xe);
4808 /* Enable BAM Station Manager */
4809 CL22_WR_OVER_CL45(sc, phy,
4810 MDIO_REG_BANK_CL73_USERB0,
4811 MDIO_CL73_USERB0_CL73_BAM_CTRL1,
4812 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
4813 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN
4815 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
4817 /* Advertise CL73 link speeds */
4818 CL22_RD_OVER_CL45(sc, phy,
4819 MDIO_REG_BANK_CL73_IEEEB1,
4820 MDIO_CL73_IEEEB1_AN_ADV2, ®_val);
4821 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
4822 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
4823 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4824 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
4826 CL22_WR_OVER_CL45(sc, phy,
4827 MDIO_REG_BANK_CL73_IEEEB1,
4828 MDIO_CL73_IEEEB1_AN_ADV2, reg_val);
4830 /* CL73 Autoneg Enabled */
4831 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
4833 } else /* CL73 Autoneg Disabled */
4836 CL22_WR_OVER_CL45(sc, phy,
4837 MDIO_REG_BANK_CL73_IEEEB0,
4838 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
4841 /* Program SerDes, forced speed */
4842 static void elink_program_serdes(struct elink_phy *phy,
4843 struct elink_params *params,
4844 struct elink_vars *vars)
4846 struct bnx2x_softc *sc = params->sc;
4849 /* Program duplex, disable autoneg and sgmii */
4850 CL22_RD_OVER_CL45(sc, phy,
4851 MDIO_REG_BANK_COMBO_IEEE0,
4852 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val);
4853 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
4854 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4855 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
4856 if (phy->req_duplex == DUPLEX_FULL)
4857 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
4858 CL22_WR_OVER_CL45(sc, phy,
4859 MDIO_REG_BANK_COMBO_IEEE0,
4860 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
4863 * - needed only if the speed is greater than 1G (2.5G or 10G)
4865 CL22_RD_OVER_CL45(sc, phy,
4866 MDIO_REG_BANK_SERDES_DIGITAL,
4867 MDIO_SERDES_DIGITAL_MISC1, ®_val);
4868 /* Clearing the speed value before setting the right speed */
4869 PMD_DRV_LOG(DEBUG, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x", reg_val);
4871 reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
4872 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
4874 if (!((vars->line_speed == ELINK_SPEED_1000) ||
4875 (vars->line_speed == ELINK_SPEED_100) ||
4876 (vars->line_speed == ELINK_SPEED_10))) {
4878 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
4879 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
4880 if (vars->line_speed == ELINK_SPEED_10000)
4882 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
4885 CL22_WR_OVER_CL45(sc, phy,
4886 MDIO_REG_BANK_SERDES_DIGITAL,
4887 MDIO_SERDES_DIGITAL_MISC1, reg_val);
4891 static void elink_set_brcm_cl37_advertisement(struct elink_phy *phy,
4892 struct elink_params *params)
4894 struct bnx2x_softc *sc = params->sc;
4897 /* Set extended capabilities */
4898 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
4899 val |= MDIO_OVER_1G_UP1_2_5G;
4900 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
4901 val |= MDIO_OVER_1G_UP1_10G;
4902 CL22_WR_OVER_CL45(sc, phy,
4903 MDIO_REG_BANK_OVER_1G, MDIO_OVER_1G_UP1, val);
4905 CL22_WR_OVER_CL45(sc, phy,
4906 MDIO_REG_BANK_OVER_1G, MDIO_OVER_1G_UP3, 0x400);
4909 static void elink_set_ieee_aneg_advertisement(struct elink_phy *phy,
4910 struct elink_params *params,
4913 struct bnx2x_softc *sc = params->sc;
4915 /* For AN, we are always publishing full duplex */
4917 CL22_WR_OVER_CL45(sc, phy,
4918 MDIO_REG_BANK_COMBO_IEEE0,
4919 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
4920 CL22_RD_OVER_CL45(sc, phy,
4921 MDIO_REG_BANK_CL73_IEEEB1,
4922 MDIO_CL73_IEEEB1_AN_ADV1, &val);
4923 val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
4924 val |= ((ieee_fc << 3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
4925 CL22_WR_OVER_CL45(sc, phy,
4926 MDIO_REG_BANK_CL73_IEEEB1,
4927 MDIO_CL73_IEEEB1_AN_ADV1, val);
4930 static void elink_restart_autoneg(struct elink_phy *phy,
4931 struct elink_params *params,
4932 uint8_t enable_cl73)
4934 struct bnx2x_softc *sc = params->sc;
4935 uint16_t mii_control;
4937 PMD_DRV_LOG(DEBUG, "elink_restart_autoneg");
4938 /* Enable and restart BAM/CL37 aneg */
4941 CL22_RD_OVER_CL45(sc, phy,
4942 MDIO_REG_BANK_CL73_IEEEB0,
4943 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
4946 CL22_WR_OVER_CL45(sc, phy,
4947 MDIO_REG_BANK_CL73_IEEEB0,
4948 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
4950 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
4951 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
4954 CL22_RD_OVER_CL45(sc, phy,
4955 MDIO_REG_BANK_COMBO_IEEE0,
4956 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
4958 "elink_restart_autoneg mii_control before = 0x%x",
4960 CL22_WR_OVER_CL45(sc, phy,
4961 MDIO_REG_BANK_COMBO_IEEE0,
4962 MDIO_COMBO_IEEE0_MII_CONTROL,
4964 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4965 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
4969 static void elink_initialize_sgmii_process(struct elink_phy *phy,
4970 struct elink_params *params,
4971 struct elink_vars *vars)
4973 struct bnx2x_softc *sc = params->sc;
4976 /* In SGMII mode, the unicore is always slave */
4978 CL22_RD_OVER_CL45(sc, phy,
4979 MDIO_REG_BANK_SERDES_DIGITAL,
4980 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &control1);
4981 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
4982 /* Set sgmii mode (and not fiber) */
4983 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
4984 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
4985 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
4986 CL22_WR_OVER_CL45(sc, phy,
4987 MDIO_REG_BANK_SERDES_DIGITAL,
4988 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, control1);
4990 /* If forced speed */
4991 if (!(vars->line_speed == ELINK_SPEED_AUTO_NEG)) {
4992 /* Set speed, disable autoneg */
4993 uint16_t mii_control;
4995 CL22_RD_OVER_CL45(sc, phy,
4996 MDIO_REG_BANK_COMBO_IEEE0,
4997 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
4998 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4999 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK |
5000 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
5002 switch (vars->line_speed) {
5003 case ELINK_SPEED_100:
5005 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
5007 case ELINK_SPEED_1000:
5009 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
5011 case ELINK_SPEED_10:
5012 /* There is nothing to set for 10M */
5015 /* Invalid speed for SGMII */
5016 PMD_DRV_LOG(DEBUG, "Invalid line_speed 0x%x",
5021 /* Setting the full duplex */
5022 if (phy->req_duplex == DUPLEX_FULL)
5023 mii_control |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
5024 CL22_WR_OVER_CL45(sc, phy,
5025 MDIO_REG_BANK_COMBO_IEEE0,
5026 MDIO_COMBO_IEEE0_MII_CONTROL, mii_control);
5028 } else { /* AN mode */
5029 /* Enable and restart AN */
5030 elink_restart_autoneg(phy, params, 0);
5036 static elink_status_t elink_direct_parallel_detect_used(struct elink_phy *phy,
5040 struct bnx2x_softc *sc = params->sc;
5041 uint16_t pd_10g, status2_1000x;
5042 if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG)
5043 return ELINK_STATUS_OK;
5044 CL22_RD_OVER_CL45(sc, phy,
5045 MDIO_REG_BANK_SERDES_DIGITAL,
5046 MDIO_SERDES_DIGITAL_A_1000X_STATUS2, &status2_1000x);
5047 CL22_RD_OVER_CL45(sc, phy,
5048 MDIO_REG_BANK_SERDES_DIGITAL,
5049 MDIO_SERDES_DIGITAL_A_1000X_STATUS2, &status2_1000x);
5050 if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
5051 PMD_DRV_LOG(DEBUG, "1G parallel detect link on port %d",
5056 CL22_RD_OVER_CL45(sc, phy,
5057 MDIO_REG_BANK_10G_PARALLEL_DETECT,
5058 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS, &pd_10g);
5060 if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
5061 PMD_DRV_LOG(DEBUG, "10G parallel detect link on port %d",
5065 return ELINK_STATUS_OK;
5068 static void elink_update_adv_fc(struct elink_phy *phy,
5069 struct elink_params *params,
5070 struct elink_vars *vars, uint32_t gp_status)
5072 uint16_t ld_pause; /* local driver */
5073 uint16_t lp_pause; /* link partner */
5074 uint16_t pause_result;
5075 struct bnx2x_softc *sc = params->sc;
5077 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5078 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
5079 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5080 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
5082 CL22_RD_OVER_CL45(sc, phy,
5083 MDIO_REG_BANK_CL73_IEEEB1,
5084 MDIO_CL73_IEEEB1_AN_ADV1, &ld_pause);
5085 CL22_RD_OVER_CL45(sc, phy,
5086 MDIO_REG_BANK_CL73_IEEEB1,
5087 MDIO_CL73_IEEEB1_AN_LP_ADV1, &lp_pause);
5088 pause_result = (ld_pause &
5089 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8;
5090 pause_result |= (lp_pause &
5091 MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10;
5092 PMD_DRV_LOG(DEBUG, "pause_result CL73 0x%x", pause_result);
5094 CL22_RD_OVER_CL45(sc, phy,
5095 MDIO_REG_BANK_COMBO_IEEE0,
5096 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, &ld_pause);
5097 CL22_RD_OVER_CL45(sc, phy,
5098 MDIO_REG_BANK_COMBO_IEEE0,
5099 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
5101 pause_result = (ld_pause &
5102 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) >> 5;
5103 pause_result |= (lp_pause &
5104 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) >> 7;
5105 PMD_DRV_LOG(DEBUG, "pause_result CL37 0x%x", pause_result);
5107 elink_pause_resolve(vars, pause_result);
5111 static void elink_flow_ctrl_resolve(struct elink_phy *phy,
5112 struct elink_params *params,
5113 struct elink_vars *vars, uint32_t gp_status)
5115 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
5117 /* Resolve from gp_status in case of AN complete and not sgmii */
5118 if (phy->req_flow_ctrl != ELINK_FLOW_CTRL_AUTO) {
5119 /* Update the advertised flow-controled of LD/LP in AN */
5120 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)
5121 elink_update_adv_fc(phy, params, vars, gp_status);
5122 /* But set the flow-control result as the requested one */
5123 vars->flow_ctrl = phy->req_flow_ctrl;
5124 } else if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG)
5125 vars->flow_ctrl = params->req_fc_auto_adv;
5126 else if ((gp_status & ELINK_MDIO_AN_CL73_OR_37_COMPLETE) &&
5127 (!(vars->phy_flags & PHY_SGMII_FLAG))) {
5128 if (elink_direct_parallel_detect_used(phy, params)) {
5129 vars->flow_ctrl = params->req_fc_auto_adv;
5132 elink_update_adv_fc(phy, params, vars, gp_status);
5134 PMD_DRV_LOG(DEBUG, "flow_ctrl 0x%x", vars->flow_ctrl);
5137 static void elink_check_fallback_to_cl37(struct elink_phy *phy,
5138 struct elink_params *params)
5140 struct bnx2x_softc *sc = params->sc;
5141 uint16_t rx_status, ustat_val, cl37_fsm_received;
5142 PMD_DRV_LOG(DEBUG, "elink_check_fallback_to_cl37");
5143 /* Step 1: Make sure signal is detected */
5144 CL22_RD_OVER_CL45(sc, phy,
5145 MDIO_REG_BANK_RX0, MDIO_RX0_RX_STATUS, &rx_status);
5146 if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
5147 (MDIO_RX0_RX_STATUS_SIGDET)) {
5148 PMD_DRV_LOG(DEBUG, "Signal is not detected. Restoring CL73."
5149 "rx_status(0x80b0) = 0x%x", rx_status);
5150 CL22_WR_OVER_CL45(sc, phy,
5151 MDIO_REG_BANK_CL73_IEEEB0,
5152 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5153 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
5156 /* Step 2: Check CL73 state machine */
5157 CL22_RD_OVER_CL45(sc, phy,
5158 MDIO_REG_BANK_CL73_USERB0,
5159 MDIO_CL73_USERB0_CL73_USTAT1, &ustat_val);
5161 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5162 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
5163 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5164 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
5165 PMD_DRV_LOG(DEBUG, "CL73 state-machine is not stable. "
5166 "ustat_val(0x8371) = 0x%x", ustat_val);
5169 /* Step 3: Check CL37 Message Pages received to indicate LP
5170 * supports only CL37
5172 CL22_RD_OVER_CL45(sc, phy,
5173 MDIO_REG_BANK_REMOTE_PHY,
5174 MDIO_REMOTE_PHY_MISC_RX_STATUS, &cl37_fsm_received);
5175 if ((cl37_fsm_received &
5176 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5177 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
5178 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5179 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
5180 PMD_DRV_LOG(DEBUG, "No CL37 FSM were received. "
5181 "misc_rx_status(0x8330) = 0x%x", cl37_fsm_received);
5184 /* The combined cl37/cl73 fsm state information indicating that
5185 * we are connected to a device which does not support cl73, but
5186 * does support cl37 BAM. In this case we disable cl73 and
5187 * restart cl37 auto-neg
5191 CL22_WR_OVER_CL45(sc, phy,
5192 MDIO_REG_BANK_CL73_IEEEB0,
5193 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 0);
5194 /* Restart CL37 autoneg */
5195 elink_restart_autoneg(phy, params, 0);
5196 PMD_DRV_LOG(DEBUG, "Disabling CL73, and restarting CL37 autoneg");
5199 static void elink_xgxs_an_resolve(struct elink_phy *phy,
5200 struct elink_params *params,
5201 struct elink_vars *vars, uint32_t gp_status)
5203 if (gp_status & ELINK_MDIO_AN_CL73_OR_37_COMPLETE)
5204 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5206 if (elink_direct_parallel_detect_used(phy, params))
5207 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
5210 static elink_status_t elink_get_link_speed_duplex(struct elink_phy *phy,
5211 struct elink_params *params __rte_unused,
5212 struct elink_vars *vars,
5213 uint16_t is_link_up,
5214 uint16_t speed_mask,
5217 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)
5218 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
5220 PMD_DRV_LOG(DEBUG, "phy link up");
5222 vars->phy_link_up = 1;
5223 vars->link_status |= LINK_STATUS_LINK_UP;
5225 switch (speed_mask) {
5226 case ELINK_GP_STATUS_10M:
5227 vars->line_speed = ELINK_SPEED_10;
5228 if (is_duplex == DUPLEX_FULL)
5229 vars->link_status |= ELINK_LINK_10TFD;
5231 vars->link_status |= ELINK_LINK_10THD;
5234 case ELINK_GP_STATUS_100M:
5235 vars->line_speed = ELINK_SPEED_100;
5236 if (is_duplex == DUPLEX_FULL)
5237 vars->link_status |= ELINK_LINK_100TXFD;
5239 vars->link_status |= ELINK_LINK_100TXHD;
5242 case ELINK_GP_STATUS_1G:
5243 case ELINK_GP_STATUS_1G_KX:
5244 vars->line_speed = ELINK_SPEED_1000;
5245 if (is_duplex == DUPLEX_FULL)
5246 vars->link_status |= ELINK_LINK_1000TFD;
5248 vars->link_status |= ELINK_LINK_1000THD;
5251 case ELINK_GP_STATUS_2_5G:
5252 vars->line_speed = ELINK_SPEED_2500;
5253 if (is_duplex == DUPLEX_FULL)
5254 vars->link_status |= ELINK_LINK_2500TFD;
5256 vars->link_status |= ELINK_LINK_2500THD;
5259 case ELINK_GP_STATUS_5G:
5260 case ELINK_GP_STATUS_6G:
5262 "link speed unsupported gp_status 0x%x",
5264 return ELINK_STATUS_ERROR;
5266 case ELINK_GP_STATUS_10G_KX4:
5267 case ELINK_GP_STATUS_10G_HIG:
5268 case ELINK_GP_STATUS_10G_CX4:
5269 case ELINK_GP_STATUS_10G_KR:
5270 case ELINK_GP_STATUS_10G_SFI:
5271 case ELINK_GP_STATUS_10G_XFI:
5272 vars->line_speed = ELINK_SPEED_10000;
5273 vars->link_status |= ELINK_LINK_10GTFD;
5275 case ELINK_GP_STATUS_20G_DXGXS:
5276 case ELINK_GP_STATUS_20G_KR2:
5277 vars->line_speed = ELINK_SPEED_20000;
5278 vars->link_status |= ELINK_LINK_20GTFD;
5282 "link speed unsupported gp_status 0x%x",
5284 return ELINK_STATUS_ERROR;
5286 } else { /* link_down */
5287 PMD_DRV_LOG(DEBUG, "phy link down");
5289 vars->phy_link_up = 0;
5291 vars->duplex = DUPLEX_FULL;
5292 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
5293 vars->mac_type = ELINK_MAC_TYPE_NONE;
5295 PMD_DRV_LOG(DEBUG, " phy_link_up %x line_speed %d",
5296 vars->phy_link_up, vars->line_speed);
5297 return ELINK_STATUS_OK;
5300 static elink_status_t elink_link_settings_status(struct elink_phy *phy,
5301 struct elink_params *params,
5302 struct elink_vars *vars)
5304 struct bnx2x_softc *sc = params->sc;
5306 uint16_t gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask;
5307 elink_status_t rc = ELINK_STATUS_OK;
5309 /* Read gp_status */
5310 CL22_RD_OVER_CL45(sc, phy,
5311 MDIO_REG_BANK_GP_STATUS,
5312 MDIO_GP_STATUS_TOP_AN_STATUS1, &gp_status);
5313 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
5314 duplex = DUPLEX_FULL;
5315 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)
5317 speed_mask = gp_status & ELINK_GP_STATUS_SPEED_MASK;
5318 PMD_DRV_LOG(DEBUG, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x",
5319 gp_status, link_up, speed_mask);
5320 rc = elink_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,
5322 if (rc == ELINK_STATUS_ERROR)
5325 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
5326 if (ELINK_SINGLE_MEDIA_DIRECT(params)) {
5327 vars->duplex = duplex;
5328 elink_flow_ctrl_resolve(phy, params, vars, gp_status);
5329 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)
5330 elink_xgxs_an_resolve(phy, params, vars,
5333 } else { /* Link_down */
5334 if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
5335 ELINK_SINGLE_MEDIA_DIRECT(params)) {
5336 /* Check signal is detected */
5337 elink_check_fallback_to_cl37(phy, params);
5341 /* Read LP advertised speeds */
5342 if (ELINK_SINGLE_MEDIA_DIRECT(params) &&
5343 (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) {
5346 CL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_CL73_IEEEB1,
5347 MDIO_CL73_IEEEB1_AN_LP_ADV2, &val);
5349 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5350 vars->link_status |=
5351 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5352 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5353 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5354 vars->link_status |=
5355 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5357 CL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_OVER_1G,
5358 MDIO_OVER_1G_LP_UP1, &val);
5360 if (val & MDIO_OVER_1G_UP1_2_5G)
5361 vars->link_status |=
5362 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5363 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5364 vars->link_status |=
5365 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5368 PMD_DRV_LOG(DEBUG, "duplex %x flow_ctrl 0x%x link_status 0x%x",
5369 vars->duplex, vars->flow_ctrl, vars->link_status);
5373 static elink_status_t elink_warpcore_read_status(struct elink_phy *phy,
5374 struct elink_params *params,
5375 struct elink_vars *vars)
5377 struct bnx2x_softc *sc = params->sc;
5379 uint16_t gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL;
5380 elink_status_t rc = ELINK_STATUS_OK;
5381 lane = elink_get_warpcore_lane(params);
5382 /* Read gp_status */
5383 if ((params->loopback_mode) && (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)) {
5384 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5385 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
5386 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5387 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
5389 } else if ((phy->req_line_speed > ELINK_SPEED_10000) &&
5390 (phy->supported & ELINK_SUPPORTED_20000baseMLD2_Full)) {
5391 uint16_t temp_link_up;
5392 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 1, &temp_link_up);
5393 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 1, &link_up);
5394 PMD_DRV_LOG(DEBUG, "PCS RX link status = 0x%x-->0x%x",
5395 temp_link_up, link_up);
5396 link_up &= (1 << 2);
5398 elink_ext_phy_resolve_fc(phy, params, vars);
5400 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5401 MDIO_WC_REG_GP2_STATUS_GP_2_1, &gp_status1);
5402 PMD_DRV_LOG(DEBUG, "0x81d1 = 0x%x", gp_status1);
5403 /* Check for either KR, 1G, or AN up. */
5404 link_up = ((gp_status1 >> 8) |
5405 (gp_status1 >> 12) | (gp_status1)) & (1 << lane);
5406 if (phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) {
5408 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
5409 MDIO_AN_REG_STATUS, &an_link);
5410 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
5411 MDIO_AN_REG_STATUS, &an_link);
5412 link_up |= (an_link & (1 << 2));
5414 if (link_up && ELINK_SINGLE_MEDIA_DIRECT(params)) {
5415 uint16_t pd, gp_status4;
5416 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {
5417 /* Check Autoneg complete */
5418 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5419 MDIO_WC_REG_GP2_STATUS_GP_2_4,
5421 if (gp_status4 & ((1 << 12) << lane))
5422 vars->link_status |=
5423 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5425 /* Check parallel detect used */
5426 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5427 MDIO_WC_REG_PAR_DET_10G_STATUS,
5430 vars->link_status |=
5431 LINK_STATUS_PARALLEL_DETECTION_USED;
5433 elink_ext_phy_resolve_fc(phy, params, vars);
5434 vars->duplex = duplex;
5438 if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) &&
5439 ELINK_SINGLE_MEDIA_DIRECT(params)) {
5442 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
5443 MDIO_AN_REG_LP_AUTO_NEG2, &val);
5445 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5446 vars->link_status |=
5447 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5448 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5449 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5450 vars->link_status |=
5451 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5453 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5454 MDIO_WC_REG_DIGITAL3_LP_UP1, &val);
5456 if (val & MDIO_OVER_1G_UP1_2_5G)
5457 vars->link_status |=
5458 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5459 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5460 vars->link_status |=
5461 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5466 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5467 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed);
5469 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5470 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed);
5472 PMD_DRV_LOG(DEBUG, "lane %d gp_speed 0x%x", lane, gp_speed);
5474 if ((lane & 1) == 0)
5477 link_up = ! !link_up;
5479 /* Reset the TX FIFO to fix SGMII issue */
5480 rc = elink_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,
5483 /* In case of KR link down, start up the recovering procedure */
5484 if ((!link_up) && (phy->media_type == ELINK_ETH_PHY_KR) &&
5485 (!(phy->flags & ELINK_FLAGS_WC_DUAL_MODE)))
5486 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
5488 PMD_DRV_LOG(DEBUG, "duplex %x flow_ctrl 0x%x link_status 0x%x",
5489 vars->duplex, vars->flow_ctrl, vars->link_status);
5493 static void elink_set_gmii_tx_driver(struct elink_params *params)
5495 struct bnx2x_softc *sc = params->sc;
5496 struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY];
5502 CL22_RD_OVER_CL45(sc, phy,
5503 MDIO_REG_BANK_OVER_1G, MDIO_OVER_1G_LP_UP2, &lp_up2);
5505 /* Bits [10:7] at lp_up2, positioned at [15:12] */
5506 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
5507 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
5508 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
5513 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
5514 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
5515 CL22_RD_OVER_CL45(sc, phy,
5516 bank, MDIO_TX0_TX_DRIVER, &tx_driver);
5518 /* Replace tx_driver bits [15:12] */
5519 if (lp_up2 != (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
5520 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
5521 tx_driver |= lp_up2;
5522 CL22_WR_OVER_CL45(sc, phy,
5523 bank, MDIO_TX0_TX_DRIVER, tx_driver);
5528 static elink_status_t elink_emac_program(struct elink_params *params,
5529 struct elink_vars *vars)
5531 struct bnx2x_softc *sc = params->sc;
5532 uint8_t port = params->port;
5535 PMD_DRV_LOG(DEBUG, "setting link speed & duplex");
5536 elink_bits_dis(sc, GRCBASE_EMAC0 + port * 0x400 +
5538 (EMAC_MODE_25G_MODE |
5539 EMAC_MODE_PORT_MII_10M | EMAC_MODE_HALF_DUPLEX));
5540 switch (vars->line_speed) {
5541 case ELINK_SPEED_10:
5542 mode |= EMAC_MODE_PORT_MII_10M;
5545 case ELINK_SPEED_100:
5546 mode |= EMAC_MODE_PORT_MII;
5549 case ELINK_SPEED_1000:
5550 mode |= EMAC_MODE_PORT_GMII;
5553 case ELINK_SPEED_2500:
5554 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
5558 /* 10G not valid for EMAC */
5559 PMD_DRV_LOG(DEBUG, "Invalid line_speed 0x%x", vars->line_speed);
5560 return ELINK_STATUS_ERROR;
5563 if (vars->duplex == DUPLEX_HALF)
5564 mode |= EMAC_MODE_HALF_DUPLEX;
5566 GRCBASE_EMAC0 + port * 0x400 + EMAC_REG_EMAC_MODE, mode);
5568 elink_set_led(params, vars, ELINK_LED_MODE_OPER, vars->line_speed);
5569 return ELINK_STATUS_OK;
5572 static void elink_set_preemphasis(struct elink_phy *phy,
5573 struct elink_params *params)
5576 uint16_t bank, i = 0;
5577 struct bnx2x_softc *sc = params->sc;
5579 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
5580 bank += (MDIO_REG_BANK_RX1 - MDIO_REG_BANK_RX0), i++) {
5581 CL22_WR_OVER_CL45(sc, phy,
5583 MDIO_RX0_RX_EQ_BOOST, phy->rx_preemphasis[i]);
5586 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
5587 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
5588 CL22_WR_OVER_CL45(sc, phy,
5590 MDIO_TX0_TX_DRIVER, phy->tx_preemphasis[i]);
5594 static void elink_xgxs_config_init(struct elink_phy *phy,
5595 struct elink_params *params,
5596 struct elink_vars *vars)
5598 uint8_t enable_cl73 = (ELINK_SINGLE_MEDIA_DIRECT(params) ||
5599 (params->loopback_mode == ELINK_LOOPBACK_XGXS));
5601 if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
5602 if (ELINK_SINGLE_MEDIA_DIRECT(params) &&
5603 (params->feature_config_flags &
5604 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
5605 elink_set_preemphasis(phy, params);
5607 /* Forced speed requested? */
5608 if (vars->line_speed != ELINK_SPEED_AUTO_NEG ||
5609 (ELINK_SINGLE_MEDIA_DIRECT(params) &&
5610 params->loopback_mode == ELINK_LOOPBACK_EXT)) {
5611 PMD_DRV_LOG(DEBUG, "not SGMII, no AN");
5613 /* Disable autoneg */
5614 elink_set_autoneg(phy, params, vars, 0);
5616 /* Program speed and duplex */
5617 elink_program_serdes(phy, params, vars);
5619 } else { /* AN_mode */
5620 PMD_DRV_LOG(DEBUG, "not SGMII, AN");
5623 elink_set_brcm_cl37_advertisement(phy, params);
5625 /* Program duplex & pause advertisement (for aneg) */
5626 elink_set_ieee_aneg_advertisement(phy, params,
5629 /* Enable autoneg */
5630 elink_set_autoneg(phy, params, vars, enable_cl73);
5632 /* Enable and restart AN */
5633 elink_restart_autoneg(phy, params, enable_cl73);
5636 } else { /* SGMII mode */
5637 PMD_DRV_LOG(DEBUG, "SGMII");
5639 elink_initialize_sgmii_process(phy, params, vars);
5643 static elink_status_t elink_prepare_xgxs(struct elink_phy *phy,
5644 struct elink_params *params,
5645 struct elink_vars *vars)
5648 vars->phy_flags |= PHY_XGXS_FLAG;
5649 if ((phy->req_line_speed &&
5650 ((phy->req_line_speed == ELINK_SPEED_100) ||
5651 (phy->req_line_speed == ELINK_SPEED_10))) ||
5652 (!phy->req_line_speed &&
5653 (phy->speed_cap_mask >=
5654 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
5655 (phy->speed_cap_mask <
5656 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
5657 (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))
5658 vars->phy_flags |= PHY_SGMII_FLAG;
5660 vars->phy_flags &= ~PHY_SGMII_FLAG;
5662 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
5663 elink_set_aer_mmd(params, phy);
5664 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
5665 elink_set_master_ln(params, phy);
5667 rc = elink_reset_unicore(params, phy, 0);
5668 /* Reset the SerDes and wait for reset bit return low */
5669 if (rc != ELINK_STATUS_OK)
5672 elink_set_aer_mmd(params, phy);
5673 /* Setting the masterLn_def again after the reset */
5674 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
5675 elink_set_master_ln(params, phy);
5676 elink_set_swap_lanes(params, phy);
5682 static uint16_t elink_wait_reset_complete(struct bnx2x_softc *sc,
5683 struct elink_phy *phy,
5684 struct elink_params *params)
5687 /* Wait for soft reset to get cleared up to 1 sec */
5688 for (cnt = 0; cnt < 1000; cnt++) {
5689 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE)
5690 elink_cl22_read(sc, phy, MDIO_PMA_REG_CTRL, &ctrl);
5692 elink_cl45_read(sc, phy,
5694 MDIO_PMA_REG_CTRL, &ctrl);
5695 if (!(ctrl & (1 << 15)))
5701 elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, params->port); // "Warning: PHY was not initialized,"
5704 PMD_DRV_LOG(DEBUG, "control reg 0x%x (after %d ms)", ctrl, cnt);
5708 static void elink_link_int_enable(struct elink_params *params)
5710 uint8_t port = params->port;
5712 struct bnx2x_softc *sc = params->sc;
5714 /* Setting the status to report on link up for either XGXS or SerDes */
5715 if (CHIP_IS_E3(sc)) {
5716 mask = ELINK_NIG_MASK_XGXS0_LINK_STATUS;
5717 if (!(ELINK_SINGLE_MEDIA_DIRECT(params)))
5718 mask |= ELINK_NIG_MASK_MI_INT;
5719 } else if (params->switch_cfg == ELINK_SWITCH_CFG_10G) {
5720 mask = (ELINK_NIG_MASK_XGXS0_LINK10G |
5721 ELINK_NIG_MASK_XGXS0_LINK_STATUS);
5722 PMD_DRV_LOG(DEBUG, "enabled XGXS interrupt");
5723 if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) &&
5724 params->phy[ELINK_INT_PHY].type !=
5725 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
5726 mask |= ELINK_NIG_MASK_MI_INT;
5727 PMD_DRV_LOG(DEBUG, "enabled external phy int");
5730 } else { /* SerDes */
5731 mask = ELINK_NIG_MASK_SERDES0_LINK_STATUS;
5732 PMD_DRV_LOG(DEBUG, "enabled SerDes interrupt");
5733 if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) &&
5734 params->phy[ELINK_INT_PHY].type !=
5735 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
5736 mask |= ELINK_NIG_MASK_MI_INT;
5737 PMD_DRV_LOG(DEBUG, "enabled external phy int");
5740 elink_bits_en(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, mask);
5742 PMD_DRV_LOG(DEBUG, "port %x, is_xgxs %x, int_status 0x%x", port,
5743 (params->switch_cfg == ELINK_SWITCH_CFG_10G),
5744 REG_RD(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4));
5745 PMD_DRV_LOG(DEBUG, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x",
5746 REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4),
5747 REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port * 0x18),
5749 NIG_REG_SERDES0_STATUS_LINK_STATUS + port * 0x3c));
5750 PMD_DRV_LOG(DEBUG, " 10G %x, XGXS_LINK %x",
5751 REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port * 0x68),
5752 REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port * 0x68));
5755 static void elink_rearm_latch_signal(struct bnx2x_softc *sc, uint8_t port,
5758 uint32_t latch_status = 0;
5760 /* Disable the MI INT ( external phy int ) by writing 1 to the
5761 * status register. Link down indication is high-active-signal,
5762 * so in this case we need to write the status to clear the XOR
5764 /* Read Latched signals */
5765 latch_status = REG_RD(sc, NIG_REG_LATCH_STATUS_0 + port * 8);
5766 PMD_DRV_LOG(DEBUG, "latch_status = 0x%x", latch_status);
5767 /* Handle only those with latched-signal=up. */
5770 NIG_REG_STATUS_INTERRUPT_PORT0
5771 + port * 4, ELINK_NIG_STATUS_EMAC0_MI_INT);
5774 NIG_REG_STATUS_INTERRUPT_PORT0
5775 + port * 4, ELINK_NIG_STATUS_EMAC0_MI_INT);
5777 if (latch_status & 1) {
5779 /* For all latched-signal=up : Re-Arm Latch signals */
5780 REG_WR(sc, NIG_REG_LATCH_STATUS_0 + port * 8,
5781 (latch_status & 0xfffe) | (latch_status & 1));
5783 /* For all latched-signal=up,Write original_signal to status */
5786 static void elink_link_int_ack(struct elink_params *params,
5787 struct elink_vars *vars, uint8_t is_10g_plus)
5789 struct bnx2x_softc *sc = params->sc;
5790 uint8_t port = params->port;
5792 /* First reset all status we assume only one line will be
5795 elink_bits_dis(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4,
5796 (ELINK_NIG_STATUS_XGXS0_LINK10G |
5797 ELINK_NIG_STATUS_XGXS0_LINK_STATUS |
5798 ELINK_NIG_STATUS_SERDES0_LINK_STATUS));
5799 if (vars->phy_link_up) {
5800 if (USES_WARPCORE(sc))
5801 mask = ELINK_NIG_STATUS_XGXS0_LINK_STATUS;
5804 mask = ELINK_NIG_STATUS_XGXS0_LINK10G;
5805 else if (params->switch_cfg == ELINK_SWITCH_CFG_10G) {
5806 /* Disable the link interrupt by writing 1 to
5807 * the relevant lane in the status register
5810 ((params->lane_config &
5811 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
5812 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
5813 mask = ((1 << ser_lane) <<
5814 ELINK_NIG_STATUS_XGXS0_LINK_STATUS_SIZE);
5816 mask = ELINK_NIG_STATUS_SERDES0_LINK_STATUS;
5818 PMD_DRV_LOG(DEBUG, "Ack link up interrupt with mask 0x%x",
5821 NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4, mask);
5825 static elink_status_t elink_format_ver(uint32_t num, uint8_t * str,
5828 uint8_t *str_ptr = str;
5829 uint32_t mask = 0xf0000000;
5830 uint8_t shift = 8 * 4;
5832 uint8_t remove_leading_zeros = 1;
5834 /* Need more than 10chars for this format */
5837 return ELINK_STATUS_ERROR;
5842 digit = ((num & mask) >> shift);
5843 if (digit == 0 && remove_leading_zeros) {
5846 } else if (digit < 0xa)
5847 *str_ptr = digit + '0';
5849 *str_ptr = digit - 0xa + 'a';
5850 remove_leading_zeros = 0;
5854 if (shift == 4 * 4) {
5858 remove_leading_zeros = 1;
5861 return ELINK_STATUS_OK;
5864 static elink_status_t elink_null_format_ver(__rte_unused uint32_t spirom_ver,
5865 uint8_t * str, uint16_t * len)
5869 return ELINK_STATUS_OK;
5872 static void elink_set_xgxs_loopback(struct elink_phy *phy,
5873 struct elink_params *params)
5875 uint8_t port = params->port;
5876 struct bnx2x_softc *sc = params->sc;
5878 if (phy->req_line_speed != ELINK_SPEED_1000) {
5879 uint32_t md_devad = 0;
5881 PMD_DRV_LOG(DEBUG, "XGXS 10G loopback enable");
5883 if (!CHIP_IS_E3(sc)) {
5884 /* Change the uni_phy_addr in the nig */
5885 md_devad = REG_RD(sc, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
5888 REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + port * 0x18,
5892 elink_cl45_write(sc, phy,
5894 (MDIO_REG_BANK_AER_BLOCK +
5895 (MDIO_AER_BLOCK_AER_REG & 0xf)), 0x2800);
5897 elink_cl45_write(sc, phy,
5899 (MDIO_REG_BANK_CL73_IEEEB0 +
5900 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
5903 /* Set aer mmd back */
5904 elink_set_aer_mmd(params, phy);
5906 if (!CHIP_IS_E3(sc)) {
5908 REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + port * 0x18,
5913 PMD_DRV_LOG(DEBUG, "XGXS 1G loopback enable");
5914 elink_cl45_read(sc, phy, 5,
5915 (MDIO_REG_BANK_COMBO_IEEE0 +
5916 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
5918 elink_cl45_write(sc, phy, 5,
5919 (MDIO_REG_BANK_COMBO_IEEE0 +
5920 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
5922 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
5926 elink_status_t elink_set_led(struct elink_params *params,
5927 struct elink_vars *vars, uint8_t mode,
5930 uint8_t port = params->port;
5931 uint16_t hw_led_mode = params->hw_led_mode;
5932 elink_status_t rc = ELINK_STATUS_OK;
5935 uint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
5936 struct bnx2x_softc *sc = params->sc;
5937 PMD_DRV_LOG(DEBUG, "elink_set_led: port %x, mode %d", port, mode);
5938 PMD_DRV_LOG(DEBUG, "speed 0x%x, hw_led_mode 0x%x", speed, hw_led_mode);
5940 for (phy_idx = ELINK_EXT_PHY1; phy_idx < ELINK_MAX_PHYS; phy_idx++) {
5941 if (params->phy[phy_idx].set_link_led) {
5942 params->phy[phy_idx].set_link_led(¶ms->phy[phy_idx],
5946 #ifdef ELINK_INCLUDE_EMUL
5947 if (params->feature_config_flags &
5948 ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC)
5953 case ELINK_LED_MODE_FRONT_PANEL_OFF:
5954 case ELINK_LED_MODE_OFF:
5955 REG_WR(sc, NIG_REG_LED_10G_P0 + port * 4, 0);
5956 REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4,
5957 SHARED_HW_CFG_LED_MAC1);
5959 tmp = elink_cb_reg_read(sc, emac_base + EMAC_REG_EMAC_LED);
5960 if (params->phy[ELINK_EXT_PHY1].type ==
5961 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE)
5962 tmp &= ~(EMAC_LED_1000MB_OVERRIDE |
5963 EMAC_LED_100MB_OVERRIDE |
5964 EMAC_LED_10MB_OVERRIDE);
5966 tmp |= EMAC_LED_OVERRIDE;
5968 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED, tmp);
5971 case ELINK_LED_MODE_OPER:
5972 /* For all other phys, OPER mode is same as ON, so in case
5973 * link is down, do nothing
5977 case ELINK_LED_MODE_ON:
5978 if (((params->phy[ELINK_EXT_PHY1].type ==
5979 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727) ||
5980 (params->phy[ELINK_EXT_PHY1].type ==
5981 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722)) &&
5982 CHIP_IS_E2(sc) && params->num_phys == 2) {
5983 /* This is a work-around for E2+8727 Configurations */
5984 if (mode == ELINK_LED_MODE_ON ||
5985 speed == ELINK_SPEED_10000) {
5986 REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4, 0);
5987 REG_WR(sc, NIG_REG_LED_10G_P0 + port * 4, 1);
5990 elink_cb_reg_read(sc,
5993 elink_cb_reg_write(sc,
5996 (tmp | EMAC_LED_OVERRIDE));
5997 /* Return here without enabling traffic
5998 * LED blink and setting rate in ON mode.
5999 * In oper mode, enabling LED blink
6000 * and setting rate is needed.
6002 if (mode == ELINK_LED_MODE_ON)
6005 } else if (ELINK_SINGLE_MEDIA_DIRECT(params)) {
6006 /* This is a work-around for HW issue found when link
6009 if ((!CHIP_IS_E3(sc)) ||
6010 (CHIP_IS_E3(sc) && mode == ELINK_LED_MODE_ON))
6011 REG_WR(sc, NIG_REG_LED_10G_P0 + port * 4, 1);
6013 if (CHIP_IS_E1x(sc) ||
6014 CHIP_IS_E2(sc) || (mode == ELINK_LED_MODE_ON))
6015 REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4, 0);
6017 REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4,
6019 } else if ((params->phy[ELINK_EXT_PHY1].type ==
6020 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE) &&
6021 (mode == ELINK_LED_MODE_ON)) {
6022 REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4, 0);
6024 elink_cb_reg_read(sc,
6025 emac_base + EMAC_REG_EMAC_LED);
6026 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED,
6027 tmp | EMAC_LED_OVERRIDE |
6028 EMAC_LED_1000MB_OVERRIDE);
6029 /* Break here; otherwise, it'll disable the
6030 * intended override.
6034 uint32_t nig_led_mode = ((params->hw_led_mode <<
6035 SHARED_HW_CFG_LED_MODE_SHIFT)
6037 SHARED_HW_CFG_LED_EXTPHY2)
6038 ? (SHARED_HW_CFG_LED_PHY1 >>
6039 SHARED_HW_CFG_LED_MODE_SHIFT) : hw_led_mode;
6040 REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4,
6044 REG_WR(sc, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port * 4,
6046 /* Set blinking rate to ~15.9Hz */
6048 REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port * 4,
6049 LED_BLINK_RATE_VAL_E3);
6051 REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port * 4,
6052 LED_BLINK_RATE_VAL_E1X_E2);
6053 REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 + port * 4, 1);
6054 tmp = elink_cb_reg_read(sc, emac_base + EMAC_REG_EMAC_LED);
6055 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED,
6056 (tmp & (~EMAC_LED_OVERRIDE)));
6061 rc = ELINK_STATUS_ERROR;
6062 PMD_DRV_LOG(DEBUG, "elink_set_led: Invalid led mode %d", mode);
6069 static elink_status_t elink_link_initialize(struct elink_params *params,
6070 struct elink_vars *vars)
6072 elink_status_t rc = ELINK_STATUS_OK;
6073 uint8_t phy_index, non_ext_phy;
6074 struct bnx2x_softc *sc = params->sc;
6075 /* In case of external phy existence, the line speed would be the
6076 * line speed linked up by the external phy. In case it is direct
6077 * only, then the line_speed during initialization will be
6078 * equal to the req_line_speed
6080 vars->line_speed = params->phy[ELINK_INT_PHY].req_line_speed;
6082 /* Initialize the internal phy in case this is a direct board
6083 * (no external phys), or this board has external phy which requires
6086 if (!USES_WARPCORE(sc))
6087 elink_prepare_xgxs(¶ms->phy[ELINK_INT_PHY], params, vars);
6088 /* init ext phy and enable link state int */
6089 non_ext_phy = (ELINK_SINGLE_MEDIA_DIRECT(params) ||
6090 (params->loopback_mode == ELINK_LOOPBACK_XGXS));
6093 (params->phy[ELINK_EXT_PHY1].flags & ELINK_FLAGS_INIT_XGXS_FIRST) ||
6094 (params->loopback_mode == ELINK_LOOPBACK_EXT_PHY)) {
6095 struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY];
6096 if (vars->line_speed == ELINK_SPEED_AUTO_NEG &&
6097 (CHIP_IS_E1x(sc) || CHIP_IS_E2(sc)))
6098 elink_set_parallel_detection(phy, params);
6099 if (params->phy[ELINK_INT_PHY].config_init)
6100 params->phy[ELINK_INT_PHY].config_init(phy,
6104 /* Re-read this value in case it was changed inside config_init due to
6105 * limitations of optic module
6107 vars->line_speed = params->phy[ELINK_INT_PHY].req_line_speed;
6109 /* Init external phy */
6111 if (params->phy[ELINK_INT_PHY].supported &
6112 ELINK_SUPPORTED_FIBRE)
6113 vars->link_status |= LINK_STATUS_SERDES_LINK;
6115 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
6117 /* No need to initialize second phy in case of first
6118 * phy only selection. In case of second phy, we do
6119 * need to initialize the first phy, since they are
6122 if (params->phy[phy_index].supported &
6123 ELINK_SUPPORTED_FIBRE)
6124 vars->link_status |= LINK_STATUS_SERDES_LINK;
6126 if (phy_index == ELINK_EXT_PHY2 &&
6127 (elink_phy_selection(params) ==
6128 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
6130 "Not initializing second phy");
6133 params->phy[phy_index].config_init(¶ms->
6138 /* Reset the interrupt indication after phy was initialized */
6139 elink_bits_dis(sc, NIG_REG_STATUS_INTERRUPT_PORT0 +
6141 (ELINK_NIG_STATUS_XGXS0_LINK10G |
6142 ELINK_NIG_STATUS_XGXS0_LINK_STATUS |
6143 ELINK_NIG_STATUS_SERDES0_LINK_STATUS |
6144 ELINK_NIG_MASK_MI_INT));
6148 static void elink_int_link_reset(__rte_unused struct elink_phy *phy,
6149 struct elink_params *params)
6151 /* Reset the SerDes/XGXS */
6152 REG_WR(params->sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
6153 (0x1ff << (params->port * 16)));
6156 static void elink_common_ext_link_reset(__rte_unused struct elink_phy *phy,
6157 struct elink_params *params)
6159 struct bnx2x_softc *sc = params->sc;
6163 gpio_port = SC_PATH(sc);
6165 gpio_port = params->port;
6166 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
6167 MISC_REGISTERS_GPIO_OUTPUT_LOW, gpio_port);
6168 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
6169 MISC_REGISTERS_GPIO_OUTPUT_LOW, gpio_port);
6170 PMD_DRV_LOG(DEBUG, "reset external PHY");
6173 static elink_status_t elink_update_link_down(struct elink_params *params,
6174 struct elink_vars *vars)
6176 struct bnx2x_softc *sc = params->sc;
6177 uint8_t port = params->port;
6179 PMD_DRV_LOG(DEBUG, "Port %x: Link is down", port);
6180 elink_set_led(params, vars, ELINK_LED_MODE_OFF, 0);
6181 vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;
6182 /* Indicate no mac active */
6183 vars->mac_type = ELINK_MAC_TYPE_NONE;
6185 /* Update shared memory */
6186 vars->link_status &= ~ELINK_LINK_UPDATE_MASK;
6187 vars->line_speed = 0;
6188 elink_update_mng(params, vars->link_status);
6190 /* Activate nig drain */
6191 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + port * 4, 1);
6194 if (!CHIP_IS_E3(sc))
6195 REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port * 4, 0);
6198 /* Reset BigMac/Xmac */
6199 if (CHIP_IS_E1x(sc) || CHIP_IS_E2(sc))
6200 elink_set_bmac_rx(sc, params->port, 0);
6202 if (CHIP_IS_E3(sc)) {
6203 /* Prevent LPI Generation by chip */
6204 REG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2),
6206 REG_WR(sc, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2),
6208 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
6209 SHMEM_EEE_ACTIVE_BIT);
6211 elink_update_mng_eee(params, vars->eee_status);
6212 elink_set_xmac_rxtx(params, 0);
6213 elink_set_umac_rxtx(params, 0);
6216 return ELINK_STATUS_OK;
6219 static elink_status_t elink_update_link_up(struct elink_params *params,
6220 struct elink_vars *vars,
6223 struct bnx2x_softc *sc = params->sc;
6224 uint8_t phy_idx, port = params->port;
6225 elink_status_t rc = ELINK_STATUS_OK;
6227 vars->link_status |= (LINK_STATUS_LINK_UP |
6228 LINK_STATUS_PHYSICAL_LINK_FLAG);
6229 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
6231 if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)
6232 vars->link_status |= LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
6234 if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)
6235 vars->link_status |= LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
6236 if (USES_WARPCORE(sc)) {
6238 if (elink_xmac_enable(params, vars, 0) ==
6239 ELINK_STATUS_NO_LINK) {
6240 PMD_DRV_LOG(DEBUG, "Found errors on XMAC");
6242 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6243 vars->link_status &= ~LINK_STATUS_LINK_UP;
6246 elink_umac_enable(params, vars, 0);
6247 elink_set_led(params, vars,
6248 ELINK_LED_MODE_OPER, vars->line_speed);
6250 if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) &&
6251 (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) {
6252 PMD_DRV_LOG(DEBUG, "Enabling LPI assertion");
6253 REG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 +
6254 (params->port << 2), 1);
6255 REG_WR(sc, MISC_REG_CPMU_LP_DR_ENABLE, 1);
6256 REG_WR(sc, MISC_REG_CPMU_LP_MASK_ENT_P0 +
6257 (params->port << 2), 0xfc20);
6260 if ((CHIP_IS_E1x(sc) || CHIP_IS_E2(sc))) {
6262 if (elink_bmac_enable(params, vars, 0, 1) ==
6263 ELINK_STATUS_NO_LINK) {
6264 PMD_DRV_LOG(DEBUG, "Found errors on BMAC");
6266 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6267 vars->link_status &= ~LINK_STATUS_LINK_UP;
6270 elink_set_led(params, vars,
6271 ELINK_LED_MODE_OPER, ELINK_SPEED_10000);
6273 rc = elink_emac_program(params, vars);
6274 elink_emac_enable(params, vars, 0);
6277 if ((vars->link_status &
6278 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
6279 && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
6280 ELINK_SINGLE_MEDIA_DIRECT(params))
6281 elink_set_gmii_tx_driver(params);
6286 if (CHIP_IS_E1x(sc))
6287 rc |= elink_pbf_update(params, vars->flow_ctrl,
6291 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + port * 4, 0);
6293 /* Update shared memory */
6294 elink_update_mng(params, vars->link_status);
6295 elink_update_mng_eee(params, vars->eee_status);
6296 /* Check remote fault */
6297 for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) {
6298 if (params->phy[phy_idx].flags & ELINK_FLAGS_TX_ERROR_CHECK) {
6299 elink_check_half_open_conn(params, vars, 0);
6307 /* The elink_link_update function should be called upon link
6309 * Link is considered up as follows:
6310 * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
6312 * - SINGLE_MEDIA - The link between the 577xx and the external
6313 * phy (XGXS) need to up as well as the external link of the
6315 * - DUAL_MEDIA - The link between the 577xx and the first
6316 * external phy needs to be up, and at least one of the 2
6317 * external phy link must be up.
6319 elink_status_t elink_link_update(struct elink_params * params,
6320 struct elink_vars * vars)
6322 struct bnx2x_softc *sc = params->sc;
6323 struct elink_vars phy_vars[ELINK_MAX_PHYS];
6324 uint8_t port = params->port;
6325 uint8_t link_10g_plus, phy_index;
6326 uint8_t ext_phy_link_up = 0, cur_link_up;
6327 elink_status_t rc = ELINK_STATUS_OK;
6328 __rte_unused uint8_t is_mi_int = 0;
6329 uint16_t ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
6330 uint8_t active_external_phy = ELINK_INT_PHY;
6331 vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
6332 vars->link_status &= ~ELINK_LINK_UPDATE_MASK;
6333 for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys;
6335 phy_vars[phy_index].flow_ctrl = 0;
6336 phy_vars[phy_index].link_status = 0;
6337 phy_vars[phy_index].line_speed = 0;
6338 phy_vars[phy_index].duplex = DUPLEX_FULL;
6339 phy_vars[phy_index].phy_link_up = 0;
6340 phy_vars[phy_index].link_up = 0;
6341 phy_vars[phy_index].fault_detected = 0;
6342 /* different consideration, since vars holds inner state */
6343 phy_vars[phy_index].eee_status = vars->eee_status;
6346 if (USES_WARPCORE(sc))
6347 elink_set_aer_mmd(params, ¶ms->phy[ELINK_INT_PHY]);
6349 PMD_DRV_LOG(DEBUG, "port %x, XGXS?%x, int_status 0x%x",
6350 port, (vars->phy_flags & PHY_XGXS_FLAG),
6351 REG_RD(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4));
6353 is_mi_int = (uint8_t) (REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
6355 PMD_DRV_LOG(DEBUG, "int_mask 0x%x MI_INT %x, SERDES_LINK %x",
6356 REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4),
6359 NIG_REG_SERDES0_STATUS_LINK_STATUS + port * 0x3c));
6361 PMD_DRV_LOG(DEBUG, " 10G %x, XGXS_LINK %x",
6362 REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port * 0x68),
6363 REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port * 0x68));
6366 if (!CHIP_IS_E3(sc))
6367 REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port * 4, 0);
6370 * Check external link change only for external phys, and apply
6371 * priority selection between them in case the link on both phys
6372 * is up. Note that instead of the common vars, a temporary
6373 * vars argument is used since each phy may have different link/
6374 * speed/duplex result
6376 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
6378 struct elink_phy *phy = ¶ms->phy[phy_index];
6379 if (!phy->read_status)
6381 /* Read link status and params of this ext phy */
6382 cur_link_up = phy->read_status(phy, params,
6383 &phy_vars[phy_index]);
6385 PMD_DRV_LOG(DEBUG, "phy in index %d link is up",
6388 PMD_DRV_LOG(DEBUG, "phy in index %d link is down",
6393 if (!ext_phy_link_up) {
6394 ext_phy_link_up = 1;
6395 active_external_phy = phy_index;
6397 switch (elink_phy_selection(params)) {
6398 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6399 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6400 /* In this option, the first PHY makes sure to pass the
6401 * traffic through itself only.
6402 * Its not clear how to reset the link on the second phy
6404 active_external_phy = ELINK_EXT_PHY1;
6406 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6407 /* In this option, the first PHY makes sure to pass the
6408 * traffic through the second PHY.
6410 active_external_phy = ELINK_EXT_PHY2;
6413 /* Link indication on both PHYs with the following cases
6415 * - FIRST_PHY means that second phy wasn't initialized,
6416 * hence its link is expected to be down
6417 * - SECOND_PHY means that first phy should not be able
6418 * to link up by itself (using configuration)
6419 * - DEFAULT should be overriden during initialiazation
6421 PMD_DRV_LOG(DEBUG, "Invalid link indication"
6422 "mpc=0x%x. DISABLING LINK !!!",
6423 params->multi_phy_config);
6424 ext_phy_link_up = 0;
6429 prev_line_speed = vars->line_speed;
6431 * Read the status of the internal phy. In case of
6432 * DIRECT_SINGLE_MEDIA board, this link is the external link,
6433 * otherwise this is the link between the 577xx and the first
6436 if (params->phy[ELINK_INT_PHY].read_status)
6437 params->phy[ELINK_INT_PHY].read_status(¶ms->
6440 /* The INT_PHY flow control reside in the vars. This include the
6441 * case where the speed or flow control are not set to AUTO.
6442 * Otherwise, the active external phy flow control result is set
6443 * to the vars. The ext_phy_line_speed is needed to check if the
6444 * speed is different between the internal phy and external phy.
6445 * This case may be result of intermediate link speed change.
6447 if (active_external_phy > ELINK_INT_PHY) {
6448 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
6449 /* Link speed is taken from the XGXS. AN and FC result from
6452 vars->link_status |= phy_vars[active_external_phy].link_status;
6454 /* if active_external_phy is first PHY and link is up - disable
6455 * disable TX on second external PHY
6457 if (active_external_phy == ELINK_EXT_PHY1) {
6458 if (params->phy[ELINK_EXT_PHY2].phy_specific_func) {
6459 PMD_DRV_LOG(DEBUG, "Disabling TX on EXT_PHY2");
6460 params->phy[ELINK_EXT_PHY2].
6461 phy_specific_func(¶ms->
6462 phy[ELINK_EXT_PHY2],
6463 params, ELINK_DISABLE_TX);
6467 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
6468 vars->duplex = phy_vars[active_external_phy].duplex;
6469 if (params->phy[active_external_phy].supported &
6470 ELINK_SUPPORTED_FIBRE)
6471 vars->link_status |= LINK_STATUS_SERDES_LINK;
6473 vars->link_status &= ~LINK_STATUS_SERDES_LINK;
6475 vars->eee_status = phy_vars[active_external_phy].eee_status;
6477 PMD_DRV_LOG(DEBUG, "Active external phy selected: %x",
6478 active_external_phy);
6481 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
6483 if (params->phy[phy_index].flags &
6484 ELINK_FLAGS_REARM_LATCH_SIGNAL) {
6485 elink_rearm_latch_signal(sc, port,
6487 active_external_phy);
6491 PMD_DRV_LOG(DEBUG, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
6492 " ext_phy_line_speed = %d", vars->flow_ctrl,
6493 vars->link_status, ext_phy_line_speed);
6494 /* Upon link speed change set the NIG into drain mode. Comes to
6495 * deals with possible FIFO glitch due to clk change when speed
6496 * is decreased without link down indicator
6499 if (vars->phy_link_up) {
6500 if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
6501 (ext_phy_line_speed != vars->line_speed)) {
6502 PMD_DRV_LOG(DEBUG, "Internal link speed %d is"
6503 " different than the external"
6504 " link speed %d", vars->line_speed,
6505 ext_phy_line_speed);
6506 vars->phy_link_up = 0;
6507 } else if (prev_line_speed != vars->line_speed) {
6509 NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4,
6515 /* Anything 10 and over uses the bmac */
6516 link_10g_plus = (vars->line_speed >= ELINK_SPEED_10000);
6518 elink_link_int_ack(params, vars, link_10g_plus);
6520 /* In case external phy link is up, and internal link is down
6521 * (not initialized yet probably after link initialization, it
6522 * needs to be initialized.
6523 * Note that after link down-up as result of cable plug, the xgxs
6524 * link would probably become up again without the need
6527 if (!(ELINK_SINGLE_MEDIA_DIRECT(params))) {
6528 PMD_DRV_LOG(DEBUG, "ext_phy_link_up = %d, int_link_up = %d,"
6529 " init_preceding = %d", ext_phy_link_up,
6531 params->phy[ELINK_EXT_PHY1].flags &
6532 ELINK_FLAGS_INIT_XGXS_FIRST);
6533 if (!(params->phy[ELINK_EXT_PHY1].flags &
6534 ELINK_FLAGS_INIT_XGXS_FIRST)
6535 && ext_phy_link_up && !vars->phy_link_up) {
6536 vars->line_speed = ext_phy_line_speed;
6537 if (vars->line_speed < ELINK_SPEED_1000)
6538 vars->phy_flags |= PHY_SGMII_FLAG;
6540 vars->phy_flags &= ~PHY_SGMII_FLAG;
6542 if (params->phy[ELINK_INT_PHY].config_init)
6543 params->phy[ELINK_INT_PHY].config_init(¶ms->
6550 /* Link is up only if both local phy and external phy (in case of
6551 * non-direct board) are up and no fault detected on active PHY.
6553 vars->link_up = (vars->phy_link_up &&
6555 ELINK_SINGLE_MEDIA_DIRECT(params)) &&
6556 (phy_vars[active_external_phy].fault_detected == 0));
6558 /* Update the PFC configuration in case it was changed */
6559 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
6560 vars->link_status |= LINK_STATUS_PFC_ENABLED;
6562 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
6565 rc = elink_update_link_up(params, vars, link_10g_plus);
6567 rc = elink_update_link_down(params, vars);
6569 /* Update MCP link status was changed */
6571 feature_config_flags & ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX)
6572 elink_cb_fw_command(sc, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0);
6577 /*****************************************************************************/
6578 /* External Phy section */
6579 /*****************************************************************************/
6580 static void elink_ext_phy_hw_reset(struct bnx2x_softc *sc, uint8_t port)
6582 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
6583 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
6585 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
6586 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
6589 static void elink_save_spirom_version(struct bnx2x_softc *sc,
6590 __rte_unused uint8_t port,
6591 uint32_t spirom_ver, uint32_t ver_addr)
6593 PMD_DRV_LOG(DEBUG, "FW version 0x%x:0x%x for port %d",
6594 (uint16_t) (spirom_ver >> 16), (uint16_t) spirom_ver, port);
6597 REG_WR(sc, ver_addr, spirom_ver);
6600 static void elink_save_bnx2x_spirom_ver(struct bnx2x_softc *sc,
6601 struct elink_phy *phy, uint8_t port)
6603 uint16_t fw_ver1, fw_ver2;
6605 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
6606 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6607 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
6608 MDIO_PMA_REG_ROM_VER2, &fw_ver2);
6609 elink_save_spirom_version(sc, port,
6610 (uint32_t) (fw_ver1 << 16 | fw_ver2),
6614 static void elink_ext_phy_10G_an_resolve(struct bnx2x_softc *sc,
6615 struct elink_phy *phy,
6616 struct elink_vars *vars)
6619 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_STATUS, &val);
6620 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_STATUS, &val);
6622 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
6623 if ((val & (1 << 0)) == 0)
6624 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
6627 /******************************************************************/
6628 /* common BNX2X8073/BNX2X8727 PHY SECTION */
6629 /******************************************************************/
6630 static void elink_8073_resolve_fc(struct elink_phy *phy,
6631 struct elink_params *params,
6632 struct elink_vars *vars)
6634 struct bnx2x_softc *sc = params->sc;
6635 if (phy->req_line_speed == ELINK_SPEED_10 ||
6636 phy->req_line_speed == ELINK_SPEED_100) {
6637 vars->flow_ctrl = phy->req_flow_ctrl;
6641 if (elink_ext_phy_resolve_fc(phy, params, vars) &&
6642 (vars->flow_ctrl == ELINK_FLOW_CTRL_NONE)) {
6643 uint16_t pause_result;
6644 uint16_t ld_pause; /* local */
6645 uint16_t lp_pause; /* link partner */
6646 elink_cl45_read(sc, phy,
6648 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
6650 elink_cl45_read(sc, phy,
6652 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
6653 pause_result = (ld_pause &
6654 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
6655 pause_result |= (lp_pause &
6656 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
6658 elink_pause_resolve(vars, pause_result);
6659 PMD_DRV_LOG(DEBUG, "Ext PHY CL37 pause result 0x%x",
6664 static elink_status_t elink_8073_8727_external_rom_boot(struct bnx2x_softc *sc,
6665 struct elink_phy *phy,
6669 uint16_t fw_ver1, fw_msgout;
6670 elink_status_t rc = ELINK_STATUS_OK;
6672 /* Boot port from external ROM */
6674 elink_cl45_write(sc, phy,
6675 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
6677 /* Ucode reboot and rst */
6678 elink_cl45_write(sc, phy,
6679 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x008c);
6681 elink_cl45_write(sc, phy,
6682 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL1, 0x0001);
6684 /* Reset internal microprocessor */
6685 elink_cl45_write(sc, phy,
6687 MDIO_PMA_REG_GEN_CTRL,
6688 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
6690 /* Release srst bit */
6691 elink_cl45_write(sc, phy,
6693 MDIO_PMA_REG_GEN_CTRL,
6694 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
6696 /* Delay 100ms per the PHY specifications */
6699 /* 8073 sometimes taking longer to download */
6704 "elink_8073_8727_external_rom_boot port %x:"
6705 "Download failed. fw version = 0x%x",
6707 rc = ELINK_STATUS_ERROR;
6711 elink_cl45_read(sc, phy,
6713 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6714 elink_cl45_read(sc, phy,
6716 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
6719 } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
6720 ((fw_msgout & 0xff) != 0x03 && (phy->type ==
6721 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073)));
6723 /* Clear ser_boot_ctl bit */
6724 elink_cl45_write(sc, phy,
6725 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL1, 0x0000);
6726 elink_save_bnx2x_spirom_ver(sc, phy, port);
6729 "elink_8073_8727_external_rom_boot port %x:"
6730 "Download complete. fw version = 0x%x", port, fw_ver1);
6735 /******************************************************************/
6736 /* BNX2X8073 PHY SECTION */
6737 /******************************************************************/
6738 static elink_status_t elink_8073_is_snr_needed(struct bnx2x_softc *sc,
6739 struct elink_phy *phy)
6741 /* This is only required for 8073A1, version 102 only */
6744 /* Read 8073 HW revision */
6745 elink_cl45_read(sc, phy,
6746 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, &val);
6749 /* No need to workaround in 8073 A1 */
6750 return ELINK_STATUS_OK;
6753 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER2, &val);
6755 /* SNR should be applied only for version 0x102 */
6757 return ELINK_STATUS_OK;
6762 static elink_status_t elink_8073_xaui_wa(struct bnx2x_softc *sc,
6763 struct elink_phy *phy)
6765 uint16_t val, cnt, cnt1;
6767 elink_cl45_read(sc, phy,
6768 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, &val);
6771 /* No need to workaround in 8073 A1 */
6772 return ELINK_STATUS_OK;
6774 /* XAUI workaround in 8073 A0: */
6776 /* After loading the boot ROM and restarting Autoneg, poll
6780 for (cnt = 0; cnt < 1000; cnt++) {
6781 elink_cl45_read(sc, phy,
6783 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &val);
6784 /* If bit [14] = 0 or bit [13] = 0, continue on with
6785 * system initialization (XAUI work-around not required, as
6786 * these bits indicate 2.5G or 1G link up).
6788 if (!(val & (1 << 14)) || !(val & (1 << 13))) {
6789 PMD_DRV_LOG(DEBUG, "XAUI work-around not required");
6790 return ELINK_STATUS_OK;
6791 } else if (!(val & (1 << 15))) {
6792 PMD_DRV_LOG(DEBUG, "bit 15 went off");
6793 /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's
6794 * MSB (bit15) goes to 1 (indicating that the XAUI
6795 * workaround has completed), then continue on with
6796 * system initialization.
6798 for (cnt1 = 0; cnt1 < 1000; cnt1++) {
6799 elink_cl45_read(sc, phy,
6801 MDIO_PMA_REG_8073_XAUI_WA,
6803 if (val & (1 << 15)) {
6805 "XAUI workaround has completed");
6806 return ELINK_STATUS_OK;
6814 PMD_DRV_LOG(DEBUG, "Warning: XAUI work-around timeout !!!");
6815 return ELINK_STATUS_ERROR;
6818 static void elink_807x_force_10G(struct bnx2x_softc *sc, struct elink_phy *phy)
6820 /* Force KR or KX */
6821 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
6822 elink_cl45_write(sc, phy,
6823 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
6824 elink_cl45_write(sc, phy,
6825 MDIO_PMA_DEVAD, MDIO_PMA_REG_BNX2X_CTRL, 0x0000);
6826 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
6829 static void elink_8073_set_pause_cl37(struct elink_params *params,
6830 struct elink_phy *phy,
6831 struct elink_vars *vars)
6834 struct bnx2x_softc *sc = params->sc;
6835 elink_cl45_read(sc, phy,
6836 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
6838 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
6839 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
6840 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
6841 if ((vars->ieee_fc &
6842 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
6843 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
6844 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
6846 if ((vars->ieee_fc &
6847 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
6848 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
6849 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
6851 if ((vars->ieee_fc &
6852 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
6853 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
6854 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
6856 PMD_DRV_LOG(DEBUG, "Ext phy AN advertize cl37 0x%x", cl37_val);
6858 elink_cl45_write(sc, phy,
6859 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
6863 static void elink_8073_specific_func(struct elink_phy *phy,
6864 struct elink_params *params,
6867 struct bnx2x_softc *sc = params->sc;
6869 case ELINK_PHY_INIT:
6871 elink_cl45_write(sc, phy,
6872 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
6874 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
6880 static elink_status_t elink_8073_config_init(struct elink_phy *phy,
6881 struct elink_params *params,
6882 struct elink_vars *vars)
6884 struct bnx2x_softc *sc = params->sc;
6885 uint16_t val = 0, tmp1;
6887 PMD_DRV_LOG(DEBUG, "Init 8073");
6890 gpio_port = SC_PATH(sc);
6892 gpio_port = params->port;
6893 /* Restore normal power mode */
6894 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
6895 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
6897 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
6898 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
6900 elink_8073_specific_func(phy, params, ELINK_PHY_INIT);
6901 elink_8073_set_pause_cl37(params, phy, vars);
6903 elink_cl45_read(sc, phy,
6904 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
6906 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
6908 PMD_DRV_LOG(DEBUG, "Before rom RX_ALARM(port1): 0x%x", tmp1);
6910 /* Swap polarity if required - Must be done only in non-1G mode */
6911 if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
6912 /* Configure the 8073 to swap _P and _N of the KR lines */
6913 PMD_DRV_LOG(DEBUG, "Swapping polarity for the 8073");
6914 /* 10G Rx/Tx and 1G Tx signal polarity swap */
6915 elink_cl45_read(sc, phy,
6917 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
6918 elink_cl45_write(sc, phy,
6920 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
6924 /* Enable CL37 BAM */
6925 if (REG_RD(sc, params->shmem_base +
6926 offsetof(struct shmem_region,
6927 dev_info.port_hw_config[params->port].
6929 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
6931 elink_cl45_read(sc, phy,
6932 MDIO_AN_DEVAD, MDIO_AN_REG_8073_BAM, &val);
6933 elink_cl45_write(sc, phy,
6934 MDIO_AN_DEVAD, MDIO_AN_REG_8073_BAM, val | 1);
6935 PMD_DRV_LOG(DEBUG, "Enable CL37 BAM on KR");
6937 if (params->loopback_mode == ELINK_LOOPBACK_EXT) {
6938 elink_807x_force_10G(sc, phy);
6939 PMD_DRV_LOG(DEBUG, "Forced speed 10G on 807X");
6940 return ELINK_STATUS_OK;
6942 elink_cl45_write(sc, phy,
6943 MDIO_PMA_DEVAD, MDIO_PMA_REG_BNX2X_CTRL, 0x0002);
6945 if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG) {
6946 if (phy->req_line_speed == ELINK_SPEED_10000) {
6948 } else if (phy->req_line_speed == ELINK_SPEED_2500) {
6950 /* Note that 2.5G works only when used with 1G
6957 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
6960 /* Note that 2.5G works only when used with 1G advertisement */
6961 if (phy->speed_cap_mask &
6962 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
6963 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
6965 PMD_DRV_LOG(DEBUG, "807x autoneg val = 0x%x", val);
6968 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
6969 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
6971 if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
6972 (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)) ||
6973 (phy->req_line_speed == ELINK_SPEED_2500)) {
6975 /* Allow 2.5G for A1 and above */
6976 elink_cl45_read(sc, phy,
6977 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
6979 PMD_DRV_LOG(DEBUG, "Add 2.5G");
6985 PMD_DRV_LOG(DEBUG, "Disable 2.5G");
6989 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
6990 /* Add support for CL37 (passive mode) II */
6992 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
6993 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
6994 (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
6997 /* Add support for CL37 (passive mode) III */
6998 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
7000 /* The SNR will improve about 2db by changing BW and FEE main
7001 * tap. Rest commands are executed after link is up
7002 * Change FFE main cursor to 5 in EDC register
7004 if (elink_8073_is_snr_needed(sc, phy))
7005 elink_cl45_write(sc, phy,
7006 MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
7009 /* Enable FEC (Forware Error Correction) Request in the AN */
7010 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
7012 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
7014 elink_ext_phy_set_pause(params, phy, vars);
7016 /* Restart autoneg */
7018 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
7019 PMD_DRV_LOG(DEBUG, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x",
7020 ((val & (1 << 5)) > 0), ((val & (1 << 7)) > 0));
7021 return ELINK_STATUS_OK;
7024 static uint8_t elink_8073_read_status(struct elink_phy *phy,
7025 struct elink_params *params,
7026 struct elink_vars *vars)
7028 struct bnx2x_softc *sc = params->sc;
7029 uint8_t link_up = 0;
7030 uint16_t val1, val2;
7031 uint16_t link_status = 0;
7032 uint16_t an1000_status = 0;
7034 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
7036 PMD_DRV_LOG(DEBUG, "8703 LASI status 0x%x", val1);
7038 /* Clear the interrupt LASI status register */
7039 elink_cl45_read(sc, phy, MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7040 elink_cl45_read(sc, phy, MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
7041 PMD_DRV_LOG(DEBUG, "807x PCS status 0x%x->0x%x", val2, val1);
7043 elink_cl45_read(sc, phy,
7044 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
7046 /* Check the LASI */
7047 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
7049 PMD_DRV_LOG(DEBUG, "KR 0x9003 0x%x", val2);
7051 /* Check the link status */
7052 elink_cl45_read(sc, phy, MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7053 PMD_DRV_LOG(DEBUG, "KR PCS status 0x%x", val2);
7055 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7056 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7057 link_up = ((val1 & 4) == 4);
7058 PMD_DRV_LOG(DEBUG, "PMA_REG_STATUS=0x%x", val1);
7060 if (link_up && ((phy->req_line_speed != ELINK_SPEED_10000))) {
7061 if (elink_8073_xaui_wa(sc, phy) != 0)
7064 elink_cl45_read(sc, phy,
7065 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7066 elink_cl45_read(sc, phy,
7067 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7069 /* Check the link status on 1.1.2 */
7070 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7071 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7072 PMD_DRV_LOG(DEBUG, "KR PMA status 0x%x->0x%x,"
7073 "an_link_status=0x%x", val2, val1, an1000_status);
7075 link_up = (((val1 & 4) == 4) || (an1000_status & (1 << 1)));
7076 if (link_up && elink_8073_is_snr_needed(sc, phy)) {
7077 /* The SNR will improve about 2dbby changing the BW and FEE main
7078 * tap. The 1st write to change FFE main tap is set before
7079 * restart AN. Change PLL Bandwidth in EDC register
7081 elink_cl45_write(sc, phy,
7082 MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
7085 /* Change CDR Bandwidth in EDC register */
7086 elink_cl45_write(sc, phy,
7087 MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
7090 elink_cl45_read(sc, phy,
7091 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7094 /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
7095 if ((link_status & (1 << 2)) && (!(link_status & (1 << 15)))) {
7097 vars->line_speed = ELINK_SPEED_10000;
7098 PMD_DRV_LOG(DEBUG, "port %x: External link up in 10G",
7100 } else if ((link_status & (1 << 1)) && (!(link_status & (1 << 14)))) {
7102 vars->line_speed = ELINK_SPEED_2500;
7103 PMD_DRV_LOG(DEBUG, "port %x: External link up in 2.5G",
7105 } else if ((link_status & (1 << 0)) && (!(link_status & (1 << 13)))) {
7107 vars->line_speed = ELINK_SPEED_1000;
7108 PMD_DRV_LOG(DEBUG, "port %x: External link up in 1G",
7112 PMD_DRV_LOG(DEBUG, "port %x: External link is down",
7117 /* Swap polarity if required */
7118 if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7119 /* Configure the 8073 to swap P and N of the KR lines */
7120 elink_cl45_read(sc, phy,
7122 MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
7123 /* Set bit 3 to invert Rx in 1G mode and clear this bit
7124 * when it`s in 10G mode.
7126 if (vars->line_speed == ELINK_SPEED_1000) {
7127 PMD_DRV_LOG(DEBUG, "Swapping 1G polarity for"
7133 elink_cl45_write(sc, phy,
7135 MDIO_XS_REG_8073_RX_CTRL_PCIE, val1);
7137 elink_ext_phy_10G_an_resolve(sc, phy, vars);
7138 elink_8073_resolve_fc(phy, params, vars);
7139 vars->duplex = DUPLEX_FULL;
7142 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
7143 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
7144 MDIO_AN_REG_LP_AUTO_NEG2, &val1);
7146 if (val1 & (1 << 5))
7147 vars->link_status |=
7148 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
7149 if (val1 & (1 << 7))
7150 vars->link_status |=
7151 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
7157 static void elink_8073_link_reset(__rte_unused struct elink_phy *phy,
7158 struct elink_params *params)
7160 struct bnx2x_softc *sc = params->sc;
7163 gpio_port = SC_PATH(sc);
7165 gpio_port = params->port;
7166 PMD_DRV_LOG(DEBUG, "Setting 8073 port %d into low power mode",
7168 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
7169 MISC_REGISTERS_GPIO_OUTPUT_LOW, gpio_port);
7172 /******************************************************************/
7173 /* BNX2X8705 PHY SECTION */
7174 /******************************************************************/
7175 static elink_status_t elink_8705_config_init(struct elink_phy *phy,
7176 struct elink_params *params,
7177 __rte_unused struct elink_vars
7180 struct bnx2x_softc *sc = params->sc;
7181 PMD_DRV_LOG(DEBUG, "init 8705");
7182 /* Restore normal power mode */
7183 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
7184 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
7186 elink_ext_phy_hw_reset(sc, params->port);
7187 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
7188 elink_wait_reset_complete(sc, phy, params);
7190 elink_cl45_write(sc, phy,
7191 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
7192 elink_cl45_write(sc, phy,
7193 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
7194 elink_cl45_write(sc, phy,
7195 MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
7196 elink_cl45_write(sc, phy, MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
7197 /* BNX2X8705 doesn't have microcode, hence the 0 */
7198 elink_save_spirom_version(sc, params->port, params->shmem_base, 0);
7199 return ELINK_STATUS_OK;
7202 static uint8_t elink_8705_read_status(struct elink_phy *phy,
7203 struct elink_params *params,
7204 struct elink_vars *vars)
7206 uint8_t link_up = 0;
7207 uint16_t val1, rx_sd;
7208 struct bnx2x_softc *sc = params->sc;
7209 PMD_DRV_LOG(DEBUG, "read status 8705");
7210 elink_cl45_read(sc, phy,
7211 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7212 PMD_DRV_LOG(DEBUG, "8705 LASI status 0x%x", val1);
7214 elink_cl45_read(sc, phy,
7215 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7216 PMD_DRV_LOG(DEBUG, "8705 LASI status 0x%x", val1);
7218 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
7220 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xc809, &val1);
7221 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xc809, &val1);
7223 PMD_DRV_LOG(DEBUG, "8705 1.c809 val=0x%x", val1);
7224 link_up = ((rx_sd & 0x1) && (val1 & (1 << 9))
7225 && ((val1 & (1 << 8)) == 0));
7227 vars->line_speed = ELINK_SPEED_10000;
7228 elink_ext_phy_resolve_fc(phy, params, vars);
7233 /******************************************************************/
7234 /* SFP+ module Section */
7235 /******************************************************************/
7236 static void elink_set_disable_pmd_transmit(struct elink_params *params,
7237 struct elink_phy *phy,
7240 struct bnx2x_softc *sc = params->sc;
7241 /* Disable transmitter only for bootcodes which can enable it afterwards
7245 if (params->feature_config_flags &
7246 ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED) {
7247 PMD_DRV_LOG(DEBUG, "Disabling PMD transmitter");
7249 PMD_DRV_LOG(DEBUG, "NOT disabling PMD transmitter");
7253 PMD_DRV_LOG(DEBUG, "Enabling PMD transmitter");
7255 elink_cl45_write(sc, phy,
7256 MDIO_PMA_DEVAD, MDIO_PMA_REG_TX_DISABLE, pmd_dis);
7259 static uint8_t elink_get_gpio_port(struct elink_params *params)
7262 uint32_t swap_val, swap_override;
7263 struct bnx2x_softc *sc = params->sc;
7264 if (CHIP_IS_E2(sc)) {
7265 gpio_port = SC_PATH(sc);
7267 gpio_port = params->port;
7269 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
7270 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
7271 return gpio_port ^ (swap_val && swap_override);
7274 static void elink_sfp_e1e2_set_transmitter(struct elink_params *params,
7275 struct elink_phy *phy, uint8_t tx_en)
7278 uint8_t port = params->port;
7279 struct bnx2x_softc *sc = params->sc;
7280 uint32_t tx_en_mode;
7282 /* Disable/Enable transmitter ( TX laser of the SFP+ module.) */
7283 tx_en_mode = REG_RD(sc, params->shmem_base +
7284 offsetof(struct shmem_region,
7285 dev_info.port_hw_config[port].sfp_ctrl)) &
7286 PORT_HW_CFG_TX_LASER_MASK;
7287 PMD_DRV_LOG(DEBUG, "Setting transmitter tx_en=%x for port %x "
7288 "mode = %x", tx_en, port, tx_en_mode);
7289 switch (tx_en_mode) {
7290 case PORT_HW_CFG_TX_LASER_MDIO:
7292 elink_cl45_read(sc, phy,
7294 MDIO_PMA_REG_PHY_IDENTIFIER, &val);
7301 elink_cl45_write(sc, phy,
7303 MDIO_PMA_REG_PHY_IDENTIFIER, val);
7305 case PORT_HW_CFG_TX_LASER_GPIO0:
7306 case PORT_HW_CFG_TX_LASER_GPIO1:
7307 case PORT_HW_CFG_TX_LASER_GPIO2:
7308 case PORT_HW_CFG_TX_LASER_GPIO3:
7311 uint8_t gpio_port, gpio_mode;
7313 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
7315 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
7317 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
7318 gpio_port = elink_get_gpio_port(params);
7319 elink_cb_gpio_write(sc, gpio_pin, gpio_mode, gpio_port);
7323 PMD_DRV_LOG(DEBUG, "Invalid TX_LASER_MDIO 0x%x", tx_en_mode);
7328 static void elink_sfp_set_transmitter(struct elink_params *params,
7329 struct elink_phy *phy, uint8_t tx_en)
7331 struct bnx2x_softc *sc = params->sc;
7332 PMD_DRV_LOG(DEBUG, "Setting SFP+ transmitter to %d", tx_en);
7334 elink_sfp_e3_set_transmitter(params, phy, tx_en);
7336 elink_sfp_e1e2_set_transmitter(params, phy, tx_en);
7339 static elink_status_t elink_8726_read_sfp_module_eeprom(struct elink_phy *phy,
7346 __rte_unused uint8_t
7349 struct bnx2x_softc *sc = params->sc;
7352 if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) {
7353 PMD_DRV_LOG(DEBUG, "Reading from eeprom is limited to 0xf");
7354 return ELINK_STATUS_ERROR;
7356 /* Set the read command byte count */
7357 elink_cl45_write(sc, phy,
7358 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7359 (byte_cnt | (dev_addr << 8)));
7361 /* Set the read command address */
7362 elink_cl45_write(sc, phy,
7363 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7366 /* Activate read command */
7367 elink_cl45_write(sc, phy,
7368 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7371 /* Wait up to 500us for command complete status */
7372 for (i = 0; i < 100; i++) {
7373 elink_cl45_read(sc, phy,
7375 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7376 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7377 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7382 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7383 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7385 "Got bad status 0x%x when reading from SFP+ EEPROM",
7386 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7387 return ELINK_STATUS_ERROR;
7390 /* Read the buffer */
7391 for (i = 0; i < byte_cnt; i++) {
7392 elink_cl45_read(sc, phy,
7394 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
7396 (uint8_t) (val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
7399 for (i = 0; i < 100; i++) {
7400 elink_cl45_read(sc, phy,
7402 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7403 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7404 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7405 return ELINK_STATUS_OK;
7408 return ELINK_STATUS_ERROR;
7411 static void elink_warpcore_power_module(struct elink_params *params,
7415 struct bnx2x_softc *sc = params->sc;
7417 pin_cfg = (REG_RD(sc, params->shmem_base +
7418 offsetof(struct shmem_region,
7419 dev_info.port_hw_config[params->port].
7420 e3_sfp_ctrl)) & PORT_HW_CFG_E3_PWR_DIS_MASK)
7421 >> PORT_HW_CFG_E3_PWR_DIS_SHIFT;
7423 if (pin_cfg == PIN_CFG_NA)
7425 PMD_DRV_LOG(DEBUG, "Setting SFP+ module power to %d using pin cfg %d",
7427 /* Low ==> corresponding SFP+ module is powered
7428 * high ==> the SFP+ module is powered down
7430 elink_set_cfg_pin(sc, pin_cfg, power ^ 1);
7433 static elink_status_t elink_warpcore_read_sfp_module_eeprom(__rte_unused struct
7443 elink_status_t rc = ELINK_STATUS_OK;
7444 uint8_t i, j = 0, cnt = 0;
7445 uint32_t data_array[4];
7447 struct bnx2x_softc *sc = params->sc;
7449 if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) {
7451 "Reading from eeprom is limited to 16 bytes");
7452 return ELINK_STATUS_ERROR;
7455 /* 4 byte aligned address */
7456 addr32 = addr & (~0x3);
7458 if ((!is_init) && (cnt == I2C_WA_PWR_ITER)) {
7459 elink_warpcore_power_module(params, 0);
7460 /* Note that 100us are not enough here */
7462 elink_warpcore_power_module(params, 1);
7464 rc = elink_bsc_read(params, sc, dev_addr, addr32, 0, byte_cnt,
7466 } while ((rc != ELINK_STATUS_OK) && (++cnt < I2C_WA_RETRY_CNT));
7468 if (rc == ELINK_STATUS_OK) {
7469 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) {
7470 o_buf[j] = *((uint8_t *) data_array + i);
7478 static elink_status_t elink_8727_read_sfp_module_eeprom(struct elink_phy *phy,
7485 __rte_unused uint8_t
7488 struct bnx2x_softc *sc = params->sc;
7491 if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) {
7492 PMD_DRV_LOG(DEBUG, "Reading from eeprom is limited to 0xf");
7493 return ELINK_STATUS_ERROR;
7496 /* Set 2-wire transfer rate of SFP+ module EEPROM
7497 * to 100Khz since some DACs(direct attached cables) do
7498 * not work at 400Khz.
7500 elink_cl45_write(sc, phy,
7502 MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
7503 ((dev_addr << 8) | 1));
7505 /* Need to read from 1.8000 to clear it */
7506 elink_cl45_read(sc, phy,
7507 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7509 /* Set the read command byte count */
7510 elink_cl45_write(sc, phy,
7512 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7513 ((byte_cnt < 2) ? 2 : byte_cnt));
7515 /* Set the read command address */
7516 elink_cl45_write(sc, phy,
7518 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, addr);
7519 /* Set the destination address */
7520 elink_cl45_write(sc, phy,
7522 0x8004, MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
7524 /* Activate read command */
7525 elink_cl45_write(sc, phy,
7527 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, 0x8002);
7528 /* Wait appropriate time for two-wire command to finish before
7529 * polling the status register
7533 /* Wait up to 500us for command complete status */
7534 for (i = 0; i < 100; i++) {
7535 elink_cl45_read(sc, phy,
7537 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7538 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7539 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7544 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7545 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7547 "Got bad status 0x%x when reading from SFP+ EEPROM",
7548 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7549 return ELINK_STATUS_TIMEOUT;
7552 /* Read the buffer */
7553 for (i = 0; i < byte_cnt; i++) {
7554 elink_cl45_read(sc, phy,
7556 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
7558 (uint8_t) (val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
7561 for (i = 0; i < 100; i++) {
7562 elink_cl45_read(sc, phy,
7564 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7565 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7566 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7567 return ELINK_STATUS_OK;
7571 return ELINK_STATUS_ERROR;
7574 static elink_status_t elink_read_sfp_module_eeprom(struct elink_phy *phy,
7575 struct elink_params *params,
7581 elink_status_t rc = 0;
7583 uint8_t *user_data = o_buf;
7584 read_sfp_module_eeprom_func_p read_func;
7586 if ((dev_addr != 0xa0) && (dev_addr != 0xa2)) {
7587 PMD_DRV_LOG(DEBUG, "invalid dev_addr 0x%x", dev_addr);
7588 return ELINK_STATUS_ERROR;
7591 switch (phy->type) {
7592 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726:
7593 read_func = elink_8726_read_sfp_module_eeprom;
7595 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727:
7596 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722:
7597 read_func = elink_8727_read_sfp_module_eeprom;
7599 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
7600 read_func = elink_warpcore_read_sfp_module_eeprom;
7603 return ELINK_OP_NOT_SUPPORTED;
7606 while (!rc && (byte_cnt > 0)) {
7607 xfer_size = (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) ?
7608 ELINK_SFP_EEPROM_PAGE_SIZE : byte_cnt;
7609 rc = read_func(phy, params, dev_addr, addr, xfer_size,
7611 byte_cnt -= xfer_size;
7612 user_data += xfer_size;
7618 static elink_status_t elink_get_edc_mode(struct elink_phy *phy,
7619 struct elink_params *params,
7620 uint16_t * edc_mode)
7622 struct bnx2x_softc *sc = params->sc;
7623 uint32_t sync_offset = 0, phy_idx, media_types;
7624 uint8_t gport, val[2], check_limiting_mode = 0;
7625 *edc_mode = ELINK_EDC_MODE_LIMITING;
7626 phy->media_type = ELINK_ETH_PHY_UNSPECIFIED;
7627 /* First check for copper cable */
7628 if (elink_read_sfp_module_eeprom(phy,
7630 ELINK_I2C_DEV_ADDR_A0,
7631 ELINK_SFP_EEPROM_CON_TYPE_ADDR,
7632 2, (uint8_t *) val) != 0) {
7633 PMD_DRV_LOG(DEBUG, "Failed to read from SFP+ module EEPROM");
7634 return ELINK_STATUS_ERROR;
7638 case ELINK_SFP_EEPROM_CON_TYPE_VAL_COPPER:
7640 uint8_t copper_module_type;
7641 phy->media_type = ELINK_ETH_PHY_DA_TWINAX;
7642 /* Check if its active cable (includes SFP+ module)
7645 if (elink_read_sfp_module_eeprom(phy,
7647 ELINK_I2C_DEV_ADDR_A0,
7648 ELINK_SFP_EEPROM_FC_TX_TECH_ADDR,
7650 &copper_module_type) !=
7653 "Failed to read copper-cable-type"
7654 " from SFP+ EEPROM");
7655 return ELINK_STATUS_ERROR;
7658 if (copper_module_type &
7659 ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
7661 "Active Copper cable detected");
7663 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
7664 *edc_mode = ELINK_EDC_MODE_ACTIVE_DAC;
7666 check_limiting_mode = 1;
7667 } else if (copper_module_type &
7668 ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE)
7671 "Passive Copper cable detected");
7672 *edc_mode = ELINK_EDC_MODE_PASSIVE_DAC;
7675 "Unknown copper-cable-type 0x%x !!!",
7676 copper_module_type);
7677 return ELINK_STATUS_ERROR;
7681 case ELINK_SFP_EEPROM_CON_TYPE_VAL_LC:
7682 case ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45:
7683 check_limiting_mode = 1;
7684 if ((val[1] & (ELINK_SFP_EEPROM_COMP_CODE_SR_MASK |
7685 ELINK_SFP_EEPROM_COMP_CODE_LR_MASK |
7686 ELINK_SFP_EEPROM_COMP_CODE_LRM_MASK)) == 0) {
7687 PMD_DRV_LOG(DEBUG, "1G SFP module detected");
7688 gport = params->port;
7689 phy->media_type = ELINK_ETH_PHY_SFP_1G_FIBER;
7690 if (phy->req_line_speed != ELINK_SPEED_1000) {
7691 phy->req_line_speed = ELINK_SPEED_1000;
7692 if (!CHIP_IS_E1x(sc)) {
7693 gport = SC_PATH(sc) +
7694 (params->port << 1);
7696 elink_cb_event_log(sc, ELINK_LOG_ID_NON_10G_MODULE, gport); //"Warning: Link speed was forced to 1000Mbps."
7697 // " Current SFP module in port %d is not"
7698 // " compliant with 10G Ethernet",
7702 int idx, cfg_idx = 0;
7703 PMD_DRV_LOG(DEBUG, "10G Optic module detected");
7704 for (idx = ELINK_INT_PHY; idx < ELINK_MAX_PHYS; idx++) {
7705 if (params->phy[idx].type == phy->type) {
7706 cfg_idx = ELINK_LINK_CONFIG_IDX(idx);
7710 phy->media_type = ELINK_ETH_PHY_SFPP_10G_FIBER;
7711 phy->req_line_speed = params->req_line_speed[cfg_idx];
7715 PMD_DRV_LOG(DEBUG, "Unable to determine module type 0x%x !!!",
7717 return ELINK_STATUS_ERROR;
7719 sync_offset = params->shmem_base +
7720 offsetof(struct shmem_region,
7721 dev_info.port_hw_config[params->port].media_type);
7722 media_types = REG_RD(sc, sync_offset);
7723 /* Update media type for non-PMF sync */
7724 for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) {
7725 if (&(params->phy[phy_idx]) == phy) {
7726 media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
7727 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
7731 media_type & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
7732 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
7736 REG_WR(sc, sync_offset, media_types);
7737 if (check_limiting_mode) {
7738 uint8_t options[ELINK_SFP_EEPROM_OPTIONS_SIZE];
7739 if (elink_read_sfp_module_eeprom(phy,
7741 ELINK_I2C_DEV_ADDR_A0,
7742 ELINK_SFP_EEPROM_OPTIONS_ADDR,
7743 ELINK_SFP_EEPROM_OPTIONS_SIZE,
7746 "Failed to read Option field from module EEPROM");
7747 return ELINK_STATUS_ERROR;
7749 if ((options[0] & ELINK_SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
7750 *edc_mode = ELINK_EDC_MODE_LINEAR;
7752 *edc_mode = ELINK_EDC_MODE_LIMITING;
7754 PMD_DRV_LOG(DEBUG, "EDC mode is set to 0x%x", *edc_mode);
7755 return ELINK_STATUS_OK;
7758 /* This function read the relevant field from the module (SFP+), and verify it
7759 * is compliant with this board
7761 static elink_status_t elink_verify_sfp_module(struct elink_phy *phy,
7762 struct elink_params *params)
7764 struct bnx2x_softc *sc = params->sc;
7766 uint32_t fw_resp, fw_cmd_param;
7767 char vendor_name[ELINK_SFP_EEPROM_VENDOR_NAME_SIZE + 1];
7768 char vendor_pn[ELINK_SFP_EEPROM_PART_NO_SIZE + 1];
7769 phy->flags &= ~ELINK_FLAGS_SFP_NOT_APPROVED;
7770 val = REG_RD(sc, params->shmem_base +
7771 offsetof(struct shmem_region,
7772 dev_info.port_feature_config[params->port].
7774 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
7775 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
7776 PMD_DRV_LOG(DEBUG, "NOT enforcing module verification");
7777 return ELINK_STATUS_OK;
7780 if (params->feature_config_flags &
7781 ELINK_FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
7782 /* Use specific phy request */
7783 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
7784 } else if (params->feature_config_flags &
7785 ELINK_FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
7786 /* Use first phy request only in case of non-dual media */
7787 if (ELINK_DUAL_MEDIA(params)) {
7789 "FW does not support OPT MDL verification");
7790 return ELINK_STATUS_ERROR;
7792 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
7794 /* No support in OPT MDL detection */
7795 PMD_DRV_LOG(DEBUG, "FW does not support OPT MDL verification");
7796 return ELINK_STATUS_ERROR;
7799 fw_cmd_param = ELINK_FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
7800 fw_resp = elink_cb_fw_command(sc, cmd, fw_cmd_param);
7801 if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
7802 PMD_DRV_LOG(DEBUG, "Approved module");
7803 return ELINK_STATUS_OK;
7806 /* Format the warning message */
7807 if (elink_read_sfp_module_eeprom(phy,
7809 ELINK_I2C_DEV_ADDR_A0,
7810 ELINK_SFP_EEPROM_VENDOR_NAME_ADDR,
7811 ELINK_SFP_EEPROM_VENDOR_NAME_SIZE,
7812 (uint8_t *) vendor_name))
7813 vendor_name[0] = '\0';
7815 vendor_name[ELINK_SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
7816 if (elink_read_sfp_module_eeprom(phy,
7818 ELINK_I2C_DEV_ADDR_A0,
7819 ELINK_SFP_EEPROM_PART_NO_ADDR,
7820 ELINK_SFP_EEPROM_PART_NO_SIZE,
7821 (uint8_t *) vendor_pn))
7822 vendor_pn[0] = '\0';
7824 vendor_pn[ELINK_SFP_EEPROM_PART_NO_SIZE] = '\0';
7826 elink_cb_event_log(sc, ELINK_LOG_ID_UNQUAL_IO_MODULE, params->port, vendor_name, vendor_pn); // "Warning: Unqualified SFP+ module detected,"
7827 // " Port %d from %s part number %s",
7829 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
7830 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG)
7831 phy->flags |= ELINK_FLAGS_SFP_NOT_APPROVED;
7832 return ELINK_STATUS_ERROR;
7835 static elink_status_t elink_wait_for_sfp_module_initialized(struct elink_phy
7843 /* Initialization time after hot-plug may take up to 300ms for
7844 * some phys type ( e.g. JDSU )
7847 for (timeout = 0; timeout < 60; timeout++) {
7848 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
7849 rc = elink_warpcore_read_sfp_module_eeprom(phy, params,
7850 ELINK_I2C_DEV_ADDR_A0,
7854 rc = elink_read_sfp_module_eeprom(phy, params,
7855 ELINK_I2C_DEV_ADDR_A0,
7859 "SFP+ module initialization took %d ms",
7861 return ELINK_STATUS_OK;
7865 rc = elink_read_sfp_module_eeprom(phy, params, ELINK_I2C_DEV_ADDR_A0,
7870 static void elink_8727_power_module(struct bnx2x_softc *sc,
7871 struct elink_phy *phy, uint8_t is_power_up)
7873 /* Make sure GPIOs are not using for LED mode */
7875 /* In the GPIO register, bit 4 is use to determine if the GPIOs are
7876 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
7878 * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
7879 * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1
7880 * where the 1st bit is the over-current(only input), and 2nd bit is
7881 * for power( only output )
7883 * In case of NOC feature is disabled and power is up, set GPIO control
7884 * as input to enable listening of over-current indication
7886 if (phy->flags & ELINK_FLAGS_NOC)
7891 /* Set GPIO control to OUTPUT, and set the power bit
7892 * to according to the is_power_up
7896 elink_cl45_write(sc, phy,
7897 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, val);
7900 static elink_status_t elink_8726_set_limiting_mode(struct bnx2x_softc *sc,
7901 struct elink_phy *phy,
7904 uint16_t cur_limiting_mode;
7906 elink_cl45_read(sc, phy,
7908 MDIO_PMA_REG_ROM_VER2, &cur_limiting_mode);
7909 PMD_DRV_LOG(DEBUG, "Current Limiting mode is 0x%x", cur_limiting_mode);
7911 if (edc_mode == ELINK_EDC_MODE_LIMITING) {
7912 PMD_DRV_LOG(DEBUG, "Setting LIMITING MODE");
7913 elink_cl45_write(sc, phy,
7915 MDIO_PMA_REG_ROM_VER2,
7916 ELINK_EDC_MODE_LIMITING);
7917 } else { /* LRM mode ( default ) */
7919 PMD_DRV_LOG(DEBUG, "Setting LRM MODE");
7921 /* Changing to LRM mode takes quite few seconds. So do it only
7922 * if current mode is limiting (default is LRM)
7924 if (cur_limiting_mode != ELINK_EDC_MODE_LIMITING)
7925 return ELINK_STATUS_OK;
7927 elink_cl45_write(sc, phy,
7928 MDIO_PMA_DEVAD, MDIO_PMA_REG_LRM_MODE, 0);
7929 elink_cl45_write(sc, phy,
7930 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER2, 0x128);
7931 elink_cl45_write(sc, phy,
7933 MDIO_PMA_REG_MISC_CTRL0, 0x4008);
7934 elink_cl45_write(sc, phy,
7935 MDIO_PMA_DEVAD, MDIO_PMA_REG_LRM_MODE, 0xaaaa);
7937 return ELINK_STATUS_OK;
7940 static elink_status_t elink_8727_set_limiting_mode(struct bnx2x_softc *sc,
7941 struct elink_phy *phy,
7944 uint16_t phy_identifier;
7945 uint16_t rom_ver2_val;
7946 elink_cl45_read(sc, phy,
7948 MDIO_PMA_REG_PHY_IDENTIFIER, &phy_identifier);
7950 elink_cl45_write(sc, phy,
7952 MDIO_PMA_REG_PHY_IDENTIFIER,
7953 (phy_identifier & ~(1 << 9)));
7955 elink_cl45_read(sc, phy,
7956 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER2, &rom_ver2_val);
7957 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
7958 elink_cl45_write(sc, phy,
7960 MDIO_PMA_REG_ROM_VER2,
7961 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
7963 elink_cl45_write(sc, phy,
7965 MDIO_PMA_REG_PHY_IDENTIFIER,
7966 (phy_identifier | (1 << 9)));
7968 return ELINK_STATUS_OK;
7971 static void elink_8727_specific_func(struct elink_phy *phy,
7972 struct elink_params *params,
7975 struct bnx2x_softc *sc = params->sc;
7978 case ELINK_DISABLE_TX:
7979 elink_sfp_set_transmitter(params, phy, 0);
7981 case ELINK_ENABLE_TX:
7982 if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED))
7983 elink_sfp_set_transmitter(params, phy, 1);
7985 case ELINK_PHY_INIT:
7986 elink_cl45_write(sc, phy,
7987 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
7988 (1 << 2) | (1 << 5));
7989 elink_cl45_write(sc, phy,
7990 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, 0);
7991 elink_cl45_write(sc, phy,
7992 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0006);
7993 /* Make MOD_ABS give interrupt on change */
7994 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
7995 MDIO_PMA_REG_8727_PCS_OPT_CTRL, &val);
7997 if (phy->flags & ELINK_FLAGS_NOC)
7999 /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
8000 * status which reflect SFP+ module over-current
8002 if (!(phy->flags & ELINK_FLAGS_NOC))
8003 val &= 0xff8f; /* Reset bits 4-6 */
8004 elink_cl45_write(sc, phy,
8005 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8009 PMD_DRV_LOG(DEBUG, "Function 0x%x not supported by 8727",
8015 static void elink_set_e1e2_module_fault_led(struct elink_params *params,
8018 struct bnx2x_softc *sc = params->sc;
8020 uint32_t fault_led_gpio = REG_RD(sc, params->shmem_base +
8021 offsetof(struct shmem_region,
8023 port_hw_config[params->port].
8025 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
8026 switch (fault_led_gpio) {
8027 case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
8029 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:
8030 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
8031 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
8032 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
8034 uint8_t gpio_port = elink_get_gpio_port(params);
8035 uint16_t gpio_pin = fault_led_gpio -
8036 PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
8037 PMD_DRV_LOG(DEBUG, "Set fault module-detected led "
8038 "pin %x port %x mode %x",
8039 gpio_pin, gpio_port, gpio_mode);
8040 elink_cb_gpio_write(sc, gpio_pin, gpio_mode, gpio_port);
8044 PMD_DRV_LOG(DEBUG, "Error: Invalid fault led mode 0x%x",
8049 static void elink_set_e3_module_fault_led(struct elink_params *params,
8053 uint8_t port = params->port;
8054 struct bnx2x_softc *sc = params->sc;
8055 pin_cfg = (REG_RD(sc, params->shmem_base +
8056 offsetof(struct shmem_region,
8057 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
8058 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
8059 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
8060 PMD_DRV_LOG(DEBUG, "Setting Fault LED to %d using pin cfg %d",
8061 gpio_mode, pin_cfg);
8062 elink_set_cfg_pin(sc, pin_cfg, gpio_mode);
8065 static void elink_set_sfp_module_fault_led(struct elink_params *params,
8068 struct bnx2x_softc *sc = params->sc;
8069 PMD_DRV_LOG(DEBUG, "Setting SFP+ module fault LED to %d", gpio_mode);
8070 if (CHIP_IS_E3(sc)) {
8071 /* Low ==> if SFP+ module is supported otherwise
8072 * High ==> if SFP+ module is not on the approved vendor list
8074 elink_set_e3_module_fault_led(params, gpio_mode);
8076 elink_set_e1e2_module_fault_led(params, gpio_mode);
8079 static void elink_warpcore_hw_reset(__rte_unused struct elink_phy *phy,
8080 struct elink_params *params)
8082 struct bnx2x_softc *sc = params->sc;
8083 elink_warpcore_power_module(params, 0);
8084 /* Put Warpcore in low power mode */
8085 REG_WR(sc, MISC_REG_WC0_RESET, 0x0c0e);
8087 /* Put LCPLL in low power mode */
8088 REG_WR(sc, MISC_REG_LCPLL_E40_PWRDWN, 1);
8089 REG_WR(sc, MISC_REG_LCPLL_E40_RESETB_ANA, 0);
8090 REG_WR(sc, MISC_REG_LCPLL_E40_RESETB_DIG, 0);
8093 static void elink_power_sfp_module(struct elink_params *params,
8094 struct elink_phy *phy, uint8_t power)
8096 PMD_DRV_LOG(DEBUG, "Setting SFP+ power to %x", power);
8098 switch (phy->type) {
8099 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727:
8100 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722:
8101 elink_8727_power_module(params->sc, phy, power);
8103 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8104 elink_warpcore_power_module(params, power);
8111 static void elink_warpcore_set_limiting_mode(struct elink_params *params,
8112 struct elink_phy *phy,
8116 uint16_t mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8117 struct bnx2x_softc *sc = params->sc;
8119 uint8_t lane = elink_get_warpcore_lane(params);
8120 /* This is a global register which controls all lanes */
8121 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
8122 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8123 val &= ~(0xf << (lane << 2));
8126 case ELINK_EDC_MODE_LINEAR:
8127 case ELINK_EDC_MODE_LIMITING:
8128 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8130 case ELINK_EDC_MODE_PASSIVE_DAC:
8131 case ELINK_EDC_MODE_ACTIVE_DAC:
8132 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC;
8138 val |= (mode << (lane << 2));
8139 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
8140 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val);
8142 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
8143 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8145 /* Restart microcode to re-read the new mode */
8146 elink_warpcore_reset_lane(sc, phy, 1);
8147 elink_warpcore_reset_lane(sc, phy, 0);
8151 static void elink_set_limiting_mode(struct elink_params *params,
8152 struct elink_phy *phy, uint16_t edc_mode)
8154 switch (phy->type) {
8155 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726:
8156 elink_8726_set_limiting_mode(params->sc, phy, edc_mode);
8158 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727:
8159 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722:
8160 elink_8727_set_limiting_mode(params->sc, phy, edc_mode);
8162 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8163 elink_warpcore_set_limiting_mode(params, phy, edc_mode);
8168 static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
8169 struct elink_params *params)
8171 struct bnx2x_softc *sc = params->sc;
8173 elink_status_t rc = ELINK_STATUS_OK;
8175 uint32_t val = REG_RD(sc, params->shmem_base +
8176 offsetof(struct shmem_region,
8177 dev_info.port_feature_config[params->
8180 /* Enabled transmitter by default */
8181 elink_sfp_set_transmitter(params, phy, 1);
8182 PMD_DRV_LOG(DEBUG, "SFP+ module plugged in/out detected on port %d",
8184 /* Power up module */
8185 elink_power_sfp_module(params, phy, 1);
8186 if (elink_get_edc_mode(phy, params, &edc_mode) != 0) {
8187 PMD_DRV_LOG(DEBUG, "Failed to get valid module type");
8188 return ELINK_STATUS_ERROR;
8189 } else if (elink_verify_sfp_module(phy, params) != 0) {
8190 /* Check SFP+ module compatibility */
8191 PMD_DRV_LOG(DEBUG, "Module verification failed!!");
8192 rc = ELINK_STATUS_ERROR;
8193 /* Turn on fault module-detected led */
8194 elink_set_sfp_module_fault_led(params,
8195 MISC_REGISTERS_GPIO_HIGH);
8197 /* Check if need to power down the SFP+ module */
8198 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8199 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
8200 PMD_DRV_LOG(DEBUG, "Shutdown SFP+ module!!");
8201 elink_power_sfp_module(params, phy, 0);
8205 /* Turn off fault module-detected led */
8206 elink_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
8209 /* Check and set limiting mode / LRM mode on 8726. On 8727 it
8210 * is done automatically
8212 elink_set_limiting_mode(params, phy, edc_mode);
8214 /* Disable transmit for this module if the module is not approved, and
8215 * laser needs to be disabled.
8218 ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8219 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER))
8220 elink_sfp_set_transmitter(params, phy, 0);
8225 void elink_handle_module_detect_int(struct elink_params *params)
8227 struct bnx2x_softc *sc = params->sc;
8228 struct elink_phy *phy;
8230 uint8_t gpio_num, gpio_port;
8231 if (CHIP_IS_E3(sc)) {
8232 phy = ¶ms->phy[ELINK_INT_PHY];
8233 /* Always enable TX laser,will be disabled in case of fault */
8234 elink_sfp_set_transmitter(params, phy, 1);
8236 phy = ¶ms->phy[ELINK_EXT_PHY1];
8238 if (elink_get_mod_abs_int_cfg(sc, params->shmem_base,
8239 params->port, &gpio_num, &gpio_port) ==
8240 ELINK_STATUS_ERROR) {
8241 PMD_DRV_LOG(DEBUG, "Failed to get MOD_ABS interrupt config");
8245 /* Set valid module led off */
8246 elink_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
8248 /* Get current gpio val reflecting module plugged in / out */
8249 gpio_val = elink_cb_gpio_read(sc, gpio_num, gpio_port);
8251 /* Call the handling function in case module is detected */
8252 if (gpio_val == 0) {
8253 elink_set_mdio_emac_per_phy(sc, params);
8254 elink_set_aer_mmd(params, phy);
8256 elink_power_sfp_module(params, phy, 1);
8257 elink_cb_gpio_int_write(sc, gpio_num,
8258 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
8260 if (elink_wait_for_sfp_module_initialized(phy, params) == 0) {
8261 elink_sfp_module_detection(phy, params);
8262 if (CHIP_IS_E3(sc)) {
8263 uint16_t rx_tx_in_reset;
8264 /* In case WC is out of reset, reconfigure the
8265 * link speed while taking into account 1G
8266 * module limitation.
8268 elink_cl45_read(sc, phy,
8270 MDIO_WC_REG_DIGITAL5_MISC6,
8272 if ((!rx_tx_in_reset) &&
8273 (params->link_flags &
8274 ELINK_PHY_INITIALIZED)) {
8275 elink_warpcore_reset_lane(sc, phy, 1);
8276 elink_warpcore_config_sfi(phy, params);
8277 elink_warpcore_reset_lane(sc, phy, 0);
8281 PMD_DRV_LOG(DEBUG, "SFP+ module is not initialized");
8284 elink_cb_gpio_int_write(sc, gpio_num,
8285 MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
8287 /* Module was plugged out.
8288 * Disable transmit for this module
8290 phy->media_type = ELINK_ETH_PHY_NOT_PRESENT;
8294 /******************************************************************/
8295 /* Used by 8706 and 8727 */
8296 /******************************************************************/
8297 static void elink_sfp_mask_fault(struct bnx2x_softc *sc,
8298 struct elink_phy *phy,
8299 uint16_t alarm_status_offset,
8300 uint16_t alarm_ctrl_offset)
8302 uint16_t alarm_status, val;
8303 elink_cl45_read(sc, phy,
8304 MDIO_PMA_DEVAD, alarm_status_offset, &alarm_status);
8305 elink_cl45_read(sc, phy,
8306 MDIO_PMA_DEVAD, alarm_status_offset, &alarm_status);
8307 /* Mask or enable the fault event. */
8308 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
8309 if (alarm_status & (1 << 0))
8313 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
8316 /******************************************************************/
8317 /* common BNX2X8706/BNX2X8726 PHY SECTION */
8318 /******************************************************************/
8319 static uint8_t elink_8706_8726_read_status(struct elink_phy *phy,
8320 struct elink_params *params,
8321 struct elink_vars *vars)
8323 uint8_t link_up = 0;
8324 uint16_t val1, val2, rx_sd, pcs_status;
8325 struct bnx2x_softc *sc = params->sc;
8326 PMD_DRV_LOG(DEBUG, "XGXS 8706/8726");
8327 /* Clear RX Alarm */
8328 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
8330 elink_sfp_mask_fault(sc, phy, MDIO_PMA_LASI_TXSTAT,
8331 MDIO_PMA_LASI_TXCTRL);
8333 /* Clear LASI indication */
8334 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8335 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
8336 PMD_DRV_LOG(DEBUG, "8706/8726 LASI status 0x%x--> 0x%x", val1, val2);
8338 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
8339 elink_cl45_read(sc, phy,
8340 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
8341 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8342 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8344 PMD_DRV_LOG(DEBUG, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
8345 " link_status 0x%x", rx_sd, pcs_status, val2);
8346 /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
8347 * are set, or if the autoneg bit 1 is set
8349 link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1 << 1)));
8351 if (val2 & (1 << 1))
8352 vars->line_speed = ELINK_SPEED_1000;
8354 vars->line_speed = ELINK_SPEED_10000;
8355 elink_ext_phy_resolve_fc(phy, params, vars);
8356 vars->duplex = DUPLEX_FULL;
8359 /* Capture 10G link fault. Read twice to clear stale value. */
8360 if (vars->line_speed == ELINK_SPEED_10000) {
8361 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
8362 MDIO_PMA_LASI_TXSTAT, &val1);
8363 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
8364 MDIO_PMA_LASI_TXSTAT, &val1);
8365 if (val1 & (1 << 0))
8366 vars->fault_detected = 1;
8372 /******************************************************************/
8373 /* BNX2X8706 PHY SECTION */
8374 /******************************************************************/
8375 static uint8_t elink_8706_config_init(struct elink_phy *phy,
8376 struct elink_params *params,
8377 __rte_unused struct elink_vars *vars)
8379 uint32_t tx_en_mode;
8380 uint16_t cnt, val, tmp1;
8381 struct bnx2x_softc *sc = params->sc;
8383 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
8384 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
8386 elink_ext_phy_hw_reset(sc, params->port);
8387 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
8388 elink_wait_reset_complete(sc, phy, params);
8390 /* Wait until fw is loaded */
8391 for (cnt = 0; cnt < 100; cnt++) {
8392 elink_cl45_read(sc, phy,
8393 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
8398 PMD_DRV_LOG(DEBUG, "XGXS 8706 is initialized after %d ms", cnt);
8399 if ((params->feature_config_flags &
8400 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8403 for (i = 0; i < 4; i++) {
8404 reg = MDIO_XS_8706_REG_BANK_RX0 +
8405 i * (MDIO_XS_8706_REG_BANK_RX1 -
8406 MDIO_XS_8706_REG_BANK_RX0);
8407 elink_cl45_read(sc, phy, MDIO_XS_DEVAD, reg, &val);
8408 /* Clear first 3 bits of the control */
8410 /* Set control bits according to configuration */
8411 val |= (phy->rx_preemphasis[i] & 0x7);
8412 PMD_DRV_LOG(DEBUG, "Setting RX Equalizer to BNX2X8706"
8413 " reg 0x%x <-- val 0x%x", reg, val);
8414 elink_cl45_write(sc, phy, MDIO_XS_DEVAD, reg, val);
8418 if (phy->req_line_speed == ELINK_SPEED_10000) {
8419 PMD_DRV_LOG(DEBUG, "XGXS 8706 force 10Gbps");
8421 elink_cl45_write(sc, phy,
8423 MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
8424 elink_cl45_write(sc, phy,
8425 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, 0);
8426 /* Arm LASI for link and Tx fault. */
8427 elink_cl45_write(sc, phy,
8428 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3);
8430 /* Force 1Gbps using autoneg with 1G advertisement */
8432 /* Allow CL37 through CL73 */
8433 PMD_DRV_LOG(DEBUG, "XGXS 8706 AutoNeg");
8434 elink_cl45_write(sc, phy,
8435 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8437 /* Enable Full-Duplex advertisement on CL37 */
8438 elink_cl45_write(sc, phy,
8439 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
8440 /* Enable CL37 AN */
8441 elink_cl45_write(sc, phy,
8442 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8444 elink_cl45_write(sc, phy,
8445 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1 << 5));
8447 /* Enable clause 73 AN */
8448 elink_cl45_write(sc, phy,
8449 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8450 elink_cl45_write(sc, phy,
8451 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 0x0400);
8452 elink_cl45_write(sc, phy,
8453 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0004);
8455 elink_save_bnx2x_spirom_ver(sc, phy, params->port);
8457 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
8458 * power mode, if TX Laser is disabled
8461 tx_en_mode = REG_RD(sc, params->shmem_base +
8462 offsetof(struct shmem_region,
8463 dev_info.port_hw_config[params->port].
8465 & PORT_HW_CFG_TX_LASER_MASK;
8467 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8468 PMD_DRV_LOG(DEBUG, "Enabling TXONOFF_PWRDN_DIS");
8469 elink_cl45_read(sc, phy,
8470 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL,
8473 elink_cl45_write(sc, phy,
8474 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL,
8478 return ELINK_STATUS_OK;
8481 static elink_status_t elink_8706_read_status(struct elink_phy *phy,
8482 struct elink_params *params,
8483 struct elink_vars *vars)
8485 return elink_8706_8726_read_status(phy, params, vars);
8488 /******************************************************************/
8489 /* BNX2X8726 PHY SECTION */
8490 /******************************************************************/
8491 static void elink_8726_config_loopback(struct elink_phy *phy,
8492 struct elink_params *params)
8494 struct bnx2x_softc *sc = params->sc;
8495 PMD_DRV_LOG(DEBUG, "PMA/PMD ext_phy_loopback: 8726");
8496 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
8499 static void elink_8726_external_rom_boot(struct elink_phy *phy,
8500 struct elink_params *params)
8502 struct bnx2x_softc *sc = params->sc;
8503 /* Need to wait 100ms after reset */
8506 /* Micro controller re-boot */
8507 elink_cl45_write(sc, phy,
8508 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
8510 /* Set soft reset */
8511 elink_cl45_write(sc, phy,
8513 MDIO_PMA_REG_GEN_CTRL,
8514 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
8516 elink_cl45_write(sc, phy,
8517 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL1, 0x0001);
8519 elink_cl45_write(sc, phy,
8521 MDIO_PMA_REG_GEN_CTRL,
8522 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
8524 /* Wait for 150ms for microcode load */
8527 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
8528 elink_cl45_write(sc, phy,
8529 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL1, 0x0000);
8532 elink_save_bnx2x_spirom_ver(sc, phy, params->port);
8535 static uint8_t elink_8726_read_status(struct elink_phy *phy,
8536 struct elink_params *params,
8537 struct elink_vars *vars)
8539 struct bnx2x_softc *sc = params->sc;
8541 uint8_t link_up = elink_8706_8726_read_status(phy, params, vars);
8543 elink_cl45_read(sc, phy,
8544 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
8546 if (val1 & (1 << 15)) {
8547 PMD_DRV_LOG(DEBUG, "Tx is disabled");
8549 vars->line_speed = 0;
8555 static elink_status_t elink_8726_config_init(struct elink_phy *phy,
8556 struct elink_params *params,
8557 struct elink_vars *vars)
8559 struct bnx2x_softc *sc = params->sc;
8560 PMD_DRV_LOG(DEBUG, "Initializing BNX2X8726");
8562 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1 << 15);
8563 elink_wait_reset_complete(sc, phy, params);
8565 elink_8726_external_rom_boot(phy, params);
8567 /* Need to call module detected on initialization since the module
8568 * detection triggered by actual module insertion might occur before
8569 * driver is loaded, and when driver is loaded, it reset all
8570 * registers, including the transmitter
8572 elink_sfp_module_detection(phy, params);
8574 if (phy->req_line_speed == ELINK_SPEED_1000) {
8575 PMD_DRV_LOG(DEBUG, "Setting 1G force");
8576 elink_cl45_write(sc, phy,
8577 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
8578 elink_cl45_write(sc, phy,
8579 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
8580 elink_cl45_write(sc, phy,
8581 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5);
8582 elink_cl45_write(sc, phy,
8583 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 0x400);
8584 } else if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
8585 (phy->speed_cap_mask &
8586 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
8587 ((phy->speed_cap_mask &
8588 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
8589 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8590 PMD_DRV_LOG(DEBUG, "Setting 1G clause37");
8591 /* Set Flow control */
8592 elink_ext_phy_set_pause(params, phy, vars);
8593 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
8594 elink_cl45_write(sc, phy,
8595 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8596 elink_cl45_write(sc, phy,
8597 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
8598 elink_cl45_write(sc, phy,
8599 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8600 elink_cl45_write(sc, phy,
8601 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8602 /* Enable RX-ALARM control to receive interrupt for 1G speed
8605 elink_cl45_write(sc, phy,
8606 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4);
8607 elink_cl45_write(sc, phy,
8608 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 0x400);
8610 } else { /* Default 10G. Set only LASI control */
8611 elink_cl45_write(sc, phy,
8612 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1);
8615 /* Set TX PreEmphasis if needed */
8616 if ((params->feature_config_flags &
8617 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8619 "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x",
8620 phy->tx_preemphasis[0], phy->tx_preemphasis[1]);
8621 elink_cl45_write(sc, phy,
8623 MDIO_PMA_REG_8726_TX_CTRL1,
8624 phy->tx_preemphasis[0]);
8626 elink_cl45_write(sc, phy,
8628 MDIO_PMA_REG_8726_TX_CTRL2,
8629 phy->tx_preemphasis[1]);
8632 return ELINK_STATUS_OK;
8636 static void elink_8726_link_reset(struct elink_phy *phy,
8637 struct elink_params *params)
8639 struct bnx2x_softc *sc = params->sc;
8640 PMD_DRV_LOG(DEBUG, "elink_8726_link_reset port %d", params->port);
8641 /* Set serial boot control for external load */
8642 elink_cl45_write(sc, phy,
8643 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
8646 /******************************************************************/
8647 /* BNX2X8727 PHY SECTION */
8648 /******************************************************************/
8650 static void elink_8727_set_link_led(struct elink_phy *phy,
8651 struct elink_params *params, uint8_t mode)
8653 struct bnx2x_softc *sc = params->sc;
8654 uint16_t led_mode_bitmask = 0;
8655 uint16_t gpio_pins_bitmask = 0;
8657 /* Only NOC flavor requires to set the LED specifically */
8658 if (!(phy->flags & ELINK_FLAGS_NOC))
8661 case ELINK_LED_MODE_FRONT_PANEL_OFF:
8662 case ELINK_LED_MODE_OFF:
8663 led_mode_bitmask = 0;
8664 gpio_pins_bitmask = 0x03;
8666 case ELINK_LED_MODE_ON:
8667 led_mode_bitmask = 0;
8668 gpio_pins_bitmask = 0x02;
8670 case ELINK_LED_MODE_OPER:
8671 led_mode_bitmask = 0x60;
8672 gpio_pins_bitmask = 0x11;
8675 elink_cl45_read(sc, phy,
8676 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, &val);
8678 val |= led_mode_bitmask;
8679 elink_cl45_write(sc, phy,
8680 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val);
8681 elink_cl45_read(sc, phy,
8682 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, &val);
8684 val |= gpio_pins_bitmask;
8685 elink_cl45_write(sc, phy,
8686 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, val);
8689 static void elink_8727_hw_reset(__rte_unused struct elink_phy *phy,
8690 struct elink_params *params)
8692 uint32_t swap_val, swap_override;
8694 /* The PHY reset is controlled by GPIO 1. Fake the port number
8695 * to cancel the swap done in set_gpio()
8697 struct bnx2x_softc *sc = params->sc;
8698 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
8699 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
8700 port = (swap_val && swap_override) ^ 1;
8701 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
8702 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
8705 static void elink_8727_config_speed(struct elink_phy *phy,
8706 struct elink_params *params)
8708 struct bnx2x_softc *sc = params->sc;
8710 /* Set option 1G speed */
8711 if ((phy->req_line_speed == ELINK_SPEED_1000) ||
8712 (phy->media_type == ELINK_ETH_PHY_SFP_1G_FIBER)) {
8713 PMD_DRV_LOG(DEBUG, "Setting 1G force");
8714 elink_cl45_write(sc, phy,
8715 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
8716 elink_cl45_write(sc, phy,
8717 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
8718 elink_cl45_read(sc, phy,
8719 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
8720 PMD_DRV_LOG(DEBUG, "1.7 = 0x%x", tmp1);
8721 /* Power down the XAUI until link is up in case of dual-media
8724 if (ELINK_DUAL_MEDIA(params)) {
8725 elink_cl45_read(sc, phy,
8727 MDIO_PMA_REG_8727_PCS_GP, &val);
8729 elink_cl45_write(sc, phy,
8731 MDIO_PMA_REG_8727_PCS_GP, val);
8733 } else if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
8734 ((phy->speed_cap_mask &
8735 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
8736 ((phy->speed_cap_mask &
8737 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
8738 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8740 PMD_DRV_LOG(DEBUG, "Setting 1G clause37");
8741 elink_cl45_write(sc, phy,
8742 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
8743 elink_cl45_write(sc, phy,
8744 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
8746 /* Since the 8727 has only single reset pin, need to set the 10G
8747 * registers although it is default
8749 elink_cl45_write(sc, phy,
8750 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
8752 elink_cl45_write(sc, phy,
8753 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
8754 elink_cl45_write(sc, phy,
8755 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
8756 elink_cl45_write(sc, phy,
8757 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
8762 static elink_status_t elink_8727_config_init(struct elink_phy *phy,
8763 struct elink_params *params,
8764 __rte_unused struct elink_vars
8767 uint32_t tx_en_mode;
8768 uint16_t tmp1, mod_abs, tmp2;
8769 struct bnx2x_softc *sc = params->sc;
8770 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
8772 elink_wait_reset_complete(sc, phy, params);
8774 PMD_DRV_LOG(DEBUG, "Initializing BNX2X8727");
8776 elink_8727_specific_func(phy, params, ELINK_PHY_INIT);
8777 /* Initially configure MOD_ABS to interrupt when module is
8780 elink_cl45_read(sc, phy,
8781 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
8782 /* Set EDC off by setting OPTXLOS signal input to low (bit 9).
8783 * When the EDC is off it locks onto a reference clock and avoids
8786 mod_abs &= ~(1 << 8);
8787 if (!(phy->flags & ELINK_FLAGS_NOC))
8788 mod_abs &= ~(1 << 9);
8789 elink_cl45_write(sc, phy,
8790 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
8792 /* Enable/Disable PHY transmitter output */
8793 elink_set_disable_pmd_transmit(params, phy, 0);
8795 elink_8727_power_module(sc, phy, 1);
8797 elink_cl45_read(sc, phy,
8798 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
8800 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
8802 elink_8727_config_speed(phy, params);
8804 /* Set TX PreEmphasis if needed */
8805 if ((params->feature_config_flags &
8806 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8807 PMD_DRV_LOG(DEBUG, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x",
8808 phy->tx_preemphasis[0], phy->tx_preemphasis[1]);
8809 elink_cl45_write(sc, phy,
8810 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
8811 phy->tx_preemphasis[0]);
8813 elink_cl45_write(sc, phy,
8814 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
8815 phy->tx_preemphasis[1]);
8818 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
8819 * power mode, if TX Laser is disabled
8821 tx_en_mode = REG_RD(sc, params->shmem_base +
8822 offsetof(struct shmem_region,
8823 dev_info.port_hw_config[params->port].
8825 & PORT_HW_CFG_TX_LASER_MASK;
8827 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8829 PMD_DRV_LOG(DEBUG, "Enabling TXONOFF_PWRDN_DIS");
8830 elink_cl45_read(sc, phy,
8831 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG,
8835 elink_cl45_write(sc, phy,
8836 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG,
8838 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
8839 MDIO_PMA_REG_PHY_IDENTIFIER, &tmp2);
8840 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD,
8841 MDIO_PMA_REG_PHY_IDENTIFIER, (tmp2 & 0x7fff));
8844 return ELINK_STATUS_OK;
8847 static void elink_8727_handle_mod_abs(struct elink_phy *phy,
8848 struct elink_params *params)
8850 struct bnx2x_softc *sc = params->sc;
8851 uint16_t mod_abs, rx_alarm_status;
8852 uint32_t val = REG_RD(sc, params->shmem_base +
8853 offsetof(struct shmem_region,
8854 dev_info.port_feature_config[params->
8856 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
8858 if (mod_abs & (1 << 8)) {
8860 /* Module is absent */
8861 PMD_DRV_LOG(DEBUG, "MOD_ABS indication show module is absent");
8862 phy->media_type = ELINK_ETH_PHY_NOT_PRESENT;
8863 /* 1. Set mod_abs to detect next module
8865 * 2. Set EDC off by setting OPTXLOS signal input to low
8867 * When the EDC is off it locks onto a reference clock and
8868 * avoids becoming 'lost'.
8870 mod_abs &= ~(1 << 8);
8871 if (!(phy->flags & ELINK_FLAGS_NOC))
8872 mod_abs &= ~(1 << 9);
8873 elink_cl45_write(sc, phy,
8875 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
8877 /* Clear RX alarm since it stays up as long as
8878 * the mod_abs wasn't changed
8880 elink_cl45_read(sc, phy,
8882 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
8885 /* Module is present */
8886 PMD_DRV_LOG(DEBUG, "MOD_ABS indication show module is present");
8887 /* First disable transmitter, and if the module is ok, the
8888 * module_detection will enable it
8889 * 1. Set mod_abs to detect next module absent event ( bit 8)
8890 * 2. Restore the default polarity of the OPRXLOS signal and
8891 * this signal will then correctly indicate the presence or
8892 * absence of the Rx signal. (bit 9)
8894 mod_abs |= (1 << 8);
8895 if (!(phy->flags & ELINK_FLAGS_NOC))
8896 mod_abs |= (1 << 9);
8897 elink_cl45_write(sc, phy,
8899 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
8901 /* Clear RX alarm since it stays up as long as the mod_abs
8902 * wasn't changed. This is need to be done before calling the
8903 * module detection, otherwise it will clear* the link update
8906 elink_cl45_read(sc, phy,
8908 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
8910 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8911 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
8912 elink_sfp_set_transmitter(params, phy, 0);
8914 if (elink_wait_for_sfp_module_initialized(phy, params) == 0) {
8915 elink_sfp_module_detection(phy, params);
8917 PMD_DRV_LOG(DEBUG, "SFP+ module is not initialized");
8920 /* Reconfigure link speed based on module type limitations */
8921 elink_8727_config_speed(phy, params);
8924 PMD_DRV_LOG(DEBUG, "8727 RX_ALARM_STATUS 0x%x", rx_alarm_status);
8925 /* No need to check link status in case of module plugged in/out */
8928 static uint8_t elink_8727_read_status(struct elink_phy *phy,
8929 struct elink_params *params,
8930 struct elink_vars *vars)
8932 struct bnx2x_softc *sc = params->sc;
8933 uint8_t link_up = 0, oc_port = params->port;
8934 uint16_t link_status = 0;
8935 uint16_t rx_alarm_status, lasi_ctrl, val1;
8937 /* If PHY is not initialized, do not check link status */
8938 elink_cl45_read(sc, phy,
8939 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, &lasi_ctrl);
8943 /* Check the LASI on Rx */
8944 elink_cl45_read(sc, phy,
8945 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
8946 vars->line_speed = 0;
8947 PMD_DRV_LOG(DEBUG, "8727 RX_ALARM_STATUS 0x%x", rx_alarm_status);
8949 elink_sfp_mask_fault(sc, phy, MDIO_PMA_LASI_TXSTAT,
8950 MDIO_PMA_LASI_TXCTRL);
8952 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8954 PMD_DRV_LOG(DEBUG, "8727 LASI status 0x%x", val1);
8957 elink_cl45_read(sc, phy,
8958 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
8960 /* If a module is present and there is need to check
8963 if (!(phy->flags & ELINK_FLAGS_NOC) && !(rx_alarm_status & (1 << 5))) {
8964 /* Check over-current using 8727 GPIO0 input */
8965 elink_cl45_read(sc, phy,
8966 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
8969 if ((val1 & (1 << 8)) == 0) {
8970 if (!CHIP_IS_E1x(sc))
8971 oc_port = SC_PATH(sc) + (params->port << 1);
8973 "8727 Power fault has been detected on port %d",
8975 elink_cb_event_log(sc, ELINK_LOG_ID_OVER_CURRENT, oc_port); //"Error: Power fault on Port %d has "
8976 // "been detected and the power to "
8977 // "that SFP+ module has been removed "
8978 // "to prevent failure of the card. "
8979 // "Please remove the SFP+ module and "
8980 // "restart the system to clear this "
8982 /* Disable all RX_ALARMs except for mod_abs */
8983 elink_cl45_write(sc, phy,
8985 MDIO_PMA_LASI_RXCTRL, (1 << 5));
8987 elink_cl45_read(sc, phy,
8989 MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
8990 /* Wait for module_absent_event */
8992 elink_cl45_write(sc, phy,
8994 MDIO_PMA_REG_PHY_IDENTIFIER, val1);
8995 /* Clear RX alarm */
8996 elink_cl45_read(sc, phy,
8998 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
8999 elink_8727_power_module(params->sc, phy, 0);
9004 /* Over current check */
9005 /* When module absent bit is set, check module */
9006 if (rx_alarm_status & (1 << 5)) {
9007 elink_8727_handle_mod_abs(phy, params);
9008 /* Enable all mod_abs and link detection bits */
9009 elink_cl45_write(sc, phy,
9010 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9011 ((1 << 5) | (1 << 2)));
9014 if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) {
9015 PMD_DRV_LOG(DEBUG, "Enabling 8727 TX laser");
9016 elink_sfp_set_transmitter(params, phy, 1);
9018 PMD_DRV_LOG(DEBUG, "Tx is disabled");
9022 elink_cl45_read(sc, phy,
9024 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
9026 /* Bits 0..2 --> speed detected,
9027 * Bits 13..15--> link is down
9029 if ((link_status & (1 << 2)) && (!(link_status & (1 << 15)))) {
9031 vars->line_speed = ELINK_SPEED_10000;
9032 PMD_DRV_LOG(DEBUG, "port %x: External link up in 10G",
9034 } else if ((link_status & (1 << 0)) && (!(link_status & (1 << 13)))) {
9036 vars->line_speed = ELINK_SPEED_1000;
9037 PMD_DRV_LOG(DEBUG, "port %x: External link up in 1G",
9041 PMD_DRV_LOG(DEBUG, "port %x: External link is down",
9045 /* Capture 10G link fault. */
9046 if (vars->line_speed == ELINK_SPEED_10000) {
9047 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
9048 MDIO_PMA_LASI_TXSTAT, &val1);
9050 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
9051 MDIO_PMA_LASI_TXSTAT, &val1);
9053 if (val1 & (1 << 0)) {
9054 vars->fault_detected = 1;
9059 elink_ext_phy_resolve_fc(phy, params, vars);
9060 vars->duplex = DUPLEX_FULL;
9061 PMD_DRV_LOG(DEBUG, "duplex = 0x%x", vars->duplex);
9064 if ((ELINK_DUAL_MEDIA(params)) &&
9065 (phy->req_line_speed == ELINK_SPEED_1000)) {
9066 elink_cl45_read(sc, phy,
9068 MDIO_PMA_REG_8727_PCS_GP, &val1);
9069 /* In case of dual-media board and 1G, power up the XAUI side,
9070 * otherwise power it down. For 10G it is done automatically
9076 elink_cl45_write(sc, phy,
9078 MDIO_PMA_REG_8727_PCS_GP, val1);
9083 static void elink_8727_link_reset(struct elink_phy *phy,
9084 struct elink_params *params)
9086 struct bnx2x_softc *sc = params->sc;
9088 /* Enable/Disable PHY transmitter output */
9089 elink_set_disable_pmd_transmit(params, phy, 1);
9091 /* Disable Transmitter */
9092 elink_sfp_set_transmitter(params, phy, 0);
9094 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0);
9098 /******************************************************************/
9099 /* BNX2X8481/BNX2X84823/BNX2X84833 PHY SECTION */
9100 /******************************************************************/
9101 static void elink_save_848xx_spirom_version(struct elink_phy *phy,
9102 struct bnx2x_softc *sc, uint8_t port)
9104 uint16_t val, fw_ver2, cnt, i;
9105 static struct elink_reg_set reg_set[] = {
9106 {MDIO_PMA_DEVAD, 0xA819, 0x0014},
9107 {MDIO_PMA_DEVAD, 0xA81A, 0xc200},
9108 {MDIO_PMA_DEVAD, 0xA81B, 0x0000},
9109 {MDIO_PMA_DEVAD, 0xA81C, 0x0300},
9110 {MDIO_PMA_DEVAD, 0xA817, 0x0009}
9114 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||
9115 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) {
9116 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1);
9117 elink_save_spirom_version(sc, port, fw_ver1 & 0xfff,
9120 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */
9121 /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
9122 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
9123 elink_cl45_write(sc, phy, reg_set[i].devad,
9124 reg_set[i].reg, reg_set[i].val);
9126 for (cnt = 0; cnt < 100; cnt++) {
9127 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9133 PMD_DRV_LOG(DEBUG, "Unable to read 848xx "
9134 "phy fw version(1)");
9135 elink_save_spirom_version(sc, port, 0, phy->ver_addr);
9139 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
9140 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
9141 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9142 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
9143 for (cnt = 0; cnt < 100; cnt++) {
9144 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9150 PMD_DRV_LOG(DEBUG, "Unable to read 848xx phy fw "
9152 elink_save_spirom_version(sc, port, 0, phy->ver_addr);
9156 /* lower 16 bits of the register SPI_FW_STATUS */
9157 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
9158 /* upper 16 bits of register SPI_FW_STATUS */
9159 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
9161 elink_save_spirom_version(sc, port, (fw_ver2 << 16) | fw_ver1,
9167 static void elink_848xx_set_led(struct bnx2x_softc *sc, struct elink_phy *phy)
9169 uint16_t val, offset, i;
9170 static struct elink_reg_set reg_set[] = {
9171 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED1_MASK, 0x0080},
9172 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED2_MASK, 0x0018},
9173 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_MASK, 0x0006},
9174 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_BLINK, 0x0000},
9175 {MDIO_PMA_DEVAD, MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH,
9176 MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ},
9177 {MDIO_AN_DEVAD, 0xFFFB, 0xFFFD}
9179 /* PHYC_CTL_LED_CTL */
9180 elink_cl45_read(sc, phy,
9181 MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
9185 elink_cl45_write(sc, phy,
9186 MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LINK_SIGNAL, val);
9188 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
9189 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
9192 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||
9193 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834))
9194 offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1;
9196 offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1;
9198 /* stretch_en for LED3 */
9199 elink_cl45_read_or_write(sc, phy,
9200 MDIO_PMA_DEVAD, offset,
9201 MDIO_PMA_REG_84823_LED3_STRETCH_EN);
9204 static void elink_848xx_specific_func(struct elink_phy *phy,
9205 struct elink_params *params,
9208 struct bnx2x_softc *sc = params->sc;
9210 case ELINK_PHY_INIT:
9211 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) &&
9212 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) {
9213 /* Save spirom version */
9214 elink_save_848xx_spirom_version(phy, sc, params->port);
9216 /* This phy uses the NIG latch mechanism since link indication
9217 * arrives through its LED4 and not via its LASI signal, so we
9218 * get steady signal instead of clear on read
9220 elink_bits_en(sc, NIG_REG_LATCH_BC_0 + params->port * 4,
9221 1 << ELINK_NIG_LATCH_BC_ENABLE_MI_INT);
9223 elink_848xx_set_led(sc, phy);
9228 static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy,
9229 struct elink_params *params,
9230 struct elink_vars *vars)
9232 struct bnx2x_softc *sc = params->sc;
9233 uint16_t autoneg_val, an_1000_val, an_10_100_val;
9235 elink_848xx_specific_func(phy, params, ELINK_PHY_INIT);
9236 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
9238 /* set 1000 speed advertisement */
9239 elink_cl45_read(sc, phy,
9240 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9243 elink_ext_phy_set_pause(params, phy, vars);
9244 elink_cl45_read(sc, phy,
9246 MDIO_AN_REG_8481_LEGACY_AN_ADV, &an_10_100_val);
9247 elink_cl45_read(sc, phy,
9248 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9250 /* Disable forced speed */
9252 ~((1 << 6) | (1 << 8) | (1 << 9) | (1 << 12) | (1 << 13));
9253 an_10_100_val &= ~((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8));
9255 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
9256 (phy->speed_cap_mask &
9257 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
9258 (phy->req_line_speed == ELINK_SPEED_1000)) {
9259 an_1000_val |= (1 << 8);
9260 autoneg_val |= (1 << 9 | 1 << 12);
9261 if (phy->req_duplex == DUPLEX_FULL)
9262 an_1000_val |= (1 << 9);
9263 PMD_DRV_LOG(DEBUG, "Advertising 1G");
9265 an_1000_val &= ~((1 << 8) | (1 << 9));
9267 elink_cl45_write(sc, phy,
9268 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9271 /* Set 10/100 speed advertisement */
9272 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {
9273 if (phy->speed_cap_mask &
9274 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) {
9275 /* Enable autoneg and restart autoneg for legacy speeds
9277 autoneg_val |= (1 << 9 | 1 << 12);
9278 an_10_100_val |= (1 << 8);
9279 PMD_DRV_LOG(DEBUG, "Advertising 100M-FD");
9282 if (phy->speed_cap_mask &
9283 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) {
9284 /* Enable autoneg and restart autoneg for legacy speeds
9286 autoneg_val |= (1 << 9 | 1 << 12);
9287 an_10_100_val |= (1 << 7);
9288 PMD_DRV_LOG(DEBUG, "Advertising 100M-HD");
9291 if ((phy->speed_cap_mask &
9292 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
9293 (phy->supported & ELINK_SUPPORTED_10baseT_Full)) {
9294 an_10_100_val |= (1 << 6);
9295 autoneg_val |= (1 << 9 | 1 << 12);
9296 PMD_DRV_LOG(DEBUG, "Advertising 10M-FD");
9299 if ((phy->speed_cap_mask &
9300 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) &&
9301 (phy->supported & ELINK_SUPPORTED_10baseT_Half)) {
9302 an_10_100_val |= (1 << 5);
9303 autoneg_val |= (1 << 9 | 1 << 12);
9304 PMD_DRV_LOG(DEBUG, "Advertising 10M-HD");
9308 /* Only 10/100 are allowed to work in FORCE mode */
9309 if ((phy->req_line_speed == ELINK_SPEED_100) &&
9311 (ELINK_SUPPORTED_100baseT_Half | ELINK_SUPPORTED_100baseT_Full))) {
9312 autoneg_val |= (1 << 13);
9313 /* Enabled AUTO-MDIX when autoneg is disabled */
9314 elink_cl45_write(sc, phy,
9315 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9316 (1 << 15 | 1 << 9 | 7 << 0));
9317 /* The PHY needs this set even for forced link. */
9318 an_10_100_val |= (1 << 8) | (1 << 7);
9319 PMD_DRV_LOG(DEBUG, "Setting 100M force");
9321 if ((phy->req_line_speed == ELINK_SPEED_10) &&
9323 (ELINK_SUPPORTED_10baseT_Half | ELINK_SUPPORTED_10baseT_Full))) {
9324 /* Enabled AUTO-MDIX when autoneg is disabled */
9325 elink_cl45_write(sc, phy,
9326 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9327 (1 << 15 | 1 << 9 | 7 << 0));
9328 PMD_DRV_LOG(DEBUG, "Setting 10M force");
9331 elink_cl45_write(sc, phy,
9332 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
9335 if (phy->req_duplex == DUPLEX_FULL)
9336 autoneg_val |= (1 << 8);
9338 /* Always write this if this is not 84833/4.
9339 * For 84833/4, write it only when it's a forced speed.
9341 if (((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) &&
9342 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) ||
9343 ((autoneg_val & (1 << 12)) == 0))
9344 elink_cl45_write(sc, phy,
9346 MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
9348 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
9349 (phy->speed_cap_mask &
9350 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
9351 (phy->req_line_speed == ELINK_SPEED_10000)) {
9352 PMD_DRV_LOG(DEBUG, "Advertising 10G");
9353 /* Restart autoneg for 10G */
9355 elink_cl45_read_or_write(sc, phy,
9357 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9359 elink_cl45_write(sc, phy,
9360 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x3200);
9362 elink_cl45_write(sc, phy,
9364 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, 1);
9366 return ELINK_STATUS_OK;
9369 static elink_status_t elink_8481_config_init(struct elink_phy *phy,
9370 struct elink_params *params,
9371 struct elink_vars *vars)
9373 struct bnx2x_softc *sc = params->sc;
9374 /* Restore normal power mode */
9375 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
9376 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
9379 elink_ext_phy_hw_reset(sc, params->port);
9380 elink_wait_reset_complete(sc, phy, params);
9382 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1 << 15);
9383 return elink_848xx_cmn_config_init(phy, params, vars);
9386 #define PHY84833_CMDHDLR_WAIT 300
9387 #define PHY84833_CMDHDLR_MAX_ARGS 5
9388 static elink_status_t elink_84833_cmd_hdlr(struct elink_phy *phy,
9389 struct elink_params *params,
9390 uint16_t fw_cmd, uint16_t cmd_args[],
9395 struct bnx2x_softc *sc = params->sc;
9396 /* Write CMD_OPEN_OVERRIDE to STATUS reg */
9397 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
9398 MDIO_84833_CMD_HDLR_STATUS,
9399 PHY84833_STATUS_CMD_OPEN_OVERRIDE);
9400 for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
9401 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
9402 MDIO_84833_CMD_HDLR_STATUS, &val);
9403 if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS)
9407 if (idx >= PHY84833_CMDHDLR_WAIT) {
9408 PMD_DRV_LOG(DEBUG, "FW cmd: FW not ready.");
9409 return ELINK_STATUS_ERROR;
9412 /* Prepare argument(s) and issue command */
9413 for (idx = 0; idx < argc; idx++) {
9414 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
9415 MDIO_84833_CMD_HDLR_DATA1 + idx,
9418 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
9419 MDIO_84833_CMD_HDLR_COMMAND, fw_cmd);
9420 for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
9421 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
9422 MDIO_84833_CMD_HDLR_STATUS, &val);
9423 if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) ||
9424 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR))
9428 if ((idx >= PHY84833_CMDHDLR_WAIT) ||
9429 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) {
9430 PMD_DRV_LOG(DEBUG, "FW cmd failed.");
9431 return ELINK_STATUS_ERROR;
9433 /* Gather returning data */
9434 for (idx = 0; idx < argc; idx++) {
9435 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
9436 MDIO_84833_CMD_HDLR_DATA1 + idx,
9439 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
9440 MDIO_84833_CMD_HDLR_STATUS,
9441 PHY84833_STATUS_CMD_CLEAR_COMPLETE);
9442 return ELINK_STATUS_OK;
9445 static elink_status_t elink_84833_pair_swap_cfg(struct elink_phy *phy,
9446 struct elink_params *params,
9447 __rte_unused struct elink_vars
9451 uint16_t data[PHY84833_CMDHDLR_MAX_ARGS];
9452 elink_status_t status;
9453 struct bnx2x_softc *sc = params->sc;
9455 /* Check for configuration. */
9456 pair_swap = REG_RD(sc, params->shmem_base +
9457 offsetof(struct shmem_region,
9458 dev_info.port_hw_config[params->port].
9460 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;
9463 return ELINK_STATUS_OK;
9465 /* Only the second argument is used for this command */
9466 data[1] = (uint16_t) pair_swap;
9468 status = elink_84833_cmd_hdlr(phy, params,
9469 PHY84833_CMD_SET_PAIR_SWAP, data,
9470 PHY84833_CMDHDLR_MAX_ARGS);
9471 if (status == ELINK_STATUS_OK) {
9472 PMD_DRV_LOG(DEBUG, "Pairswap OK, val=0x%x", data[1]);
9478 static uint8_t elink_84833_get_reset_gpios(struct bnx2x_softc *sc,
9479 uint32_t shmem_base_path[],
9480 __rte_unused uint32_t chip_id)
9482 uint32_t reset_pin[2];
9484 uint8_t reset_gpios;
9485 if (CHIP_IS_E3(sc)) {
9486 /* Assume that these will be GPIOs, not EPIOs. */
9487 for (idx = 0; idx < 2; idx++) {
9488 /* Map config param to register bit. */
9489 reset_pin[idx] = REG_RD(sc, shmem_base_path[idx] +
9490 offsetof(struct shmem_region,
9495 (reset_pin[idx] & PORT_HW_CFG_E3_PHY_RESET_MASK) >>
9496 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
9497 reset_pin[idx] -= PIN_CFG_GPIO0_P0;
9498 reset_pin[idx] = (1 << reset_pin[idx]);
9500 reset_gpios = (uint8_t) (reset_pin[0] | reset_pin[1]);
9502 /* E2, look from diff place of shmem. */
9503 for (idx = 0; idx < 2; idx++) {
9504 reset_pin[idx] = REG_RD(sc, shmem_base_path[idx] +
9505 offsetof(struct shmem_region,
9509 reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK;
9510 reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0;
9511 reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT;
9512 reset_pin[idx] = (1 << reset_pin[idx]);
9514 reset_gpios = (uint8_t) (reset_pin[0] | reset_pin[1]);
9520 static elink_status_t elink_84833_hw_reset_phy(struct elink_phy *phy,
9521 struct elink_params *params)
9523 struct bnx2x_softc *sc = params->sc;
9524 uint8_t reset_gpios;
9525 uint32_t other_shmem_base_addr = REG_RD(sc, params->shmem2_base +
9526 offsetof(struct shmem2_region,
9527 other_shmem_base_addr));
9529 uint32_t shmem_base_path[2];
9531 /* Work around for 84833 LED failure inside RESET status */
9532 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
9533 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9534 MDIO_AN_REG_8481_MII_CTRL_FORCE_1G);
9535 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
9536 MDIO_AN_REG_8481_1G_100T_EXT_CTRL,
9537 MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF);
9539 shmem_base_path[0] = params->shmem_base;
9540 shmem_base_path[1] = other_shmem_base_addr;
9542 reset_gpios = elink_84833_get_reset_gpios(sc, shmem_base_path,
9545 elink_cb_gpio_mult_write(sc, reset_gpios,
9546 MISC_REGISTERS_GPIO_OUTPUT_LOW);
9548 PMD_DRV_LOG(DEBUG, "84833 hw reset on pin values 0x%x", reset_gpios);
9550 return ELINK_STATUS_OK;
9553 static elink_status_t elink_8483x_disable_eee(struct elink_phy *phy,
9554 struct elink_params *params,
9555 struct elink_vars *vars)
9558 uint16_t cmd_args = 0;
9560 PMD_DRV_LOG(DEBUG, "Don't Advertise 10GBase-T EEE");
9562 /* Prevent Phy from working in EEE and advertising it */
9563 rc = elink_84833_cmd_hdlr(phy, params,
9564 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
9565 if (rc != ELINK_STATUS_OK) {
9566 PMD_DRV_LOG(DEBUG, "EEE disable failed.");
9570 return elink_eee_disable(phy, params, vars);
9573 static elink_status_t elink_8483x_enable_eee(struct elink_phy *phy,
9574 struct elink_params *params,
9575 struct elink_vars *vars)
9578 uint16_t cmd_args = 1;
9580 rc = elink_84833_cmd_hdlr(phy, params,
9581 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
9582 if (rc != ELINK_STATUS_OK) {
9583 PMD_DRV_LOG(DEBUG, "EEE enable failed.");
9587 return elink_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV);
9590 #define PHY84833_CONSTANT_LATENCY 1193
9591 static elink_status_t elink_848x3_config_init(struct elink_phy *phy,
9592 struct elink_params *params,
9593 struct elink_vars *vars)
9595 struct bnx2x_softc *sc = params->sc;
9596 uint8_t port, initialize = 1;
9598 uint32_t actual_phy_selection;
9599 uint16_t cmd_args[PHY84833_CMDHDLR_MAX_ARGS];
9600 elink_status_t rc = ELINK_STATUS_OK;
9604 if (!(CHIP_IS_E1x(sc)))
9607 port = params->port;
9609 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823) {
9610 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_3,
9611 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
9614 elink_cl45_write(sc, phy,
9615 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x8000);
9618 elink_wait_reset_complete(sc, phy, params);
9620 /* Wait for GPHY to come out of reset */
9622 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) &&
9623 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) {
9624 /* BNX2X84823 requires that XGXS links up first @ 10G for normal
9628 temp = vars->line_speed;
9629 vars->line_speed = ELINK_SPEED_10000;
9630 elink_set_autoneg(¶ms->phy[ELINK_INT_PHY], params, vars, 0);
9631 elink_program_serdes(¶ms->phy[ELINK_INT_PHY], params, vars);
9632 vars->line_speed = temp;
9635 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
9636 MDIO_CTL_REG_84823_MEDIA, &val);
9637 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
9638 MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
9639 MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
9640 MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
9641 MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
9643 if (CHIP_IS_E3(sc)) {
9644 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
9645 MDIO_CTL_REG_84823_MEDIA_LINE_MASK);
9647 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI |
9648 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L);
9651 actual_phy_selection = elink_phy_selection(params);
9653 switch (actual_phy_selection) {
9654 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
9655 /* Do nothing. Essentially this is like the priority copper */
9657 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
9658 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
9660 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
9661 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
9663 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
9664 /* Do nothing here. The first PHY won't be initialized at all */
9666 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
9667 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
9671 if (params->phy[ELINK_EXT_PHY2].req_line_speed == ELINK_SPEED_1000)
9672 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
9674 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
9675 MDIO_CTL_REG_84823_MEDIA, val);
9676 PMD_DRV_LOG(DEBUG, "Multi_phy config = 0x%x, Media control = 0x%x",
9677 params->multi_phy_config, val);
9679 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||
9680 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) {
9681 elink_84833_pair_swap_cfg(phy, params, vars);
9683 /* Keep AutogrEEEn disabled. */
9686 cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1;
9687 cmd_args[3] = PHY84833_CONSTANT_LATENCY;
9688 rc = elink_84833_cmd_hdlr(phy, params,
9689 PHY84833_CMD_SET_EEE_MODE, cmd_args,
9690 PHY84833_CMDHDLR_MAX_ARGS);
9691 if (rc != ELINK_STATUS_OK) {
9692 PMD_DRV_LOG(DEBUG, "Cfg AutogrEEEn failed.");
9696 rc = elink_848xx_cmn_config_init(phy, params, vars);
9698 elink_save_848xx_spirom_version(phy, sc, params->port);
9700 /* 84833 PHY has a better feature and doesn't need to support this. */
9701 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823) {
9702 uint32_t cms_enable = REG_RD(sc, params->shmem_base +
9703 offsetof(struct shmem_region,
9705 port_hw_config[params->
9708 PORT_HW_CFG_ENABLE_CMS_MASK;
9710 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
9711 MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
9713 val |= MDIO_CTL_REG_84823_USER_CTRL_CMS;
9715 val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS;
9716 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
9717 MDIO_CTL_REG_84823_USER_CTRL_REG, val);
9720 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
9721 MDIO_84833_TOP_CFG_FW_REV, &val);
9723 /* Configure EEE support */
9724 if ((val >= MDIO_84833_TOP_CFG_FW_EEE) &&
9725 (val != MDIO_84833_TOP_CFG_FW_NO_EEE) &&
9726 elink_eee_has_cap(params)) {
9727 rc = elink_eee_initial_config(params, vars, SHMEM_EEE_10G_ADV);
9728 if (rc != ELINK_STATUS_OK) {
9729 PMD_DRV_LOG(DEBUG, "Failed to configure EEE timers");
9730 elink_8483x_disable_eee(phy, params, vars);
9734 if ((phy->req_duplex == DUPLEX_FULL) &&
9735 (params->eee_mode & ELINK_EEE_MODE_ADV_LPI) &&
9736 (elink_eee_calc_timer(params) ||
9737 !(params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI)))
9738 rc = elink_8483x_enable_eee(phy, params, vars);
9740 rc = elink_8483x_disable_eee(phy, params, vars);
9741 if (rc != ELINK_STATUS_OK) {
9742 PMD_DRV_LOG(DEBUG, "Failed to set EEE advertisement");
9746 vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK;
9749 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||
9750 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) {
9751 /* Bring PHY out of super isolate mode as the final step. */
9752 elink_cl45_read_and_write(sc, phy,
9754 MDIO_84833_TOP_CFG_XGPHY_STRAP1,
9756 MDIO_84833_SUPER_ISOLATE);
9761 static uint8_t elink_848xx_read_status(struct elink_phy *phy,
9762 struct elink_params *params,
9763 struct elink_vars *vars)
9765 struct bnx2x_softc *sc = params->sc;
9766 uint16_t val, val1, val2;
9767 uint8_t link_up = 0;
9769 /* Check 10G-BaseT link status */
9770 /* Check PMD signal ok */
9771 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, 0xFFFA, &val1);
9772 elink_cl45_read(sc, phy,
9773 MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL, &val2);
9774 PMD_DRV_LOG(DEBUG, "BNX2X848xx: PMD_SIGNAL 1.a811 = 0x%x", val2);
9776 /* Check link 10G */
9777 if (val2 & (1 << 11)) {
9778 vars->line_speed = ELINK_SPEED_10000;
9779 vars->duplex = DUPLEX_FULL;
9781 elink_ext_phy_10G_an_resolve(sc, phy, vars);
9782 } else { /* Check Legacy speed link */
9783 uint16_t legacy_status, legacy_speed, mii_ctrl;
9785 /* Enable expansion register 0x42 (Operation mode status) */
9786 elink_cl45_write(sc, phy,
9788 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
9790 /* Get legacy speed operation status */
9791 elink_cl45_read(sc, phy,
9793 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
9796 PMD_DRV_LOG(DEBUG, "Legacy speed status = 0x%x", legacy_status);
9797 link_up = ((legacy_status & (1 << 11)) == (1 << 11));
9798 legacy_speed = (legacy_status & (3 << 9));
9799 if (legacy_speed == (0 << 9))
9800 vars->line_speed = ELINK_SPEED_10;
9801 else if (legacy_speed == (1 << 9))
9802 vars->line_speed = ELINK_SPEED_100;
9803 else if (legacy_speed == (2 << 9))
9804 vars->line_speed = ELINK_SPEED_1000;
9805 else { /* Should not happen: Treat as link down */
9806 vars->line_speed = 0;
9810 if (params->feature_config_flags &
9811 ELINK_FEATURE_CONFIG_IEEE_PHY_TEST) {
9812 elink_cl45_read(sc, phy,
9814 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9816 /* For IEEE testing, check for a fake link. */
9817 link_up |= ((mii_ctrl & 0x3040) == 0x40);
9821 if (legacy_status & (1 << 8))
9822 vars->duplex = DUPLEX_FULL;
9824 vars->duplex = DUPLEX_HALF;
9827 "Link is up in %dMbps, is_duplex_full= %d",
9829 (vars->duplex == DUPLEX_FULL));
9830 /* Check legacy speed AN resolution */
9831 elink_cl45_read(sc, phy,
9833 MDIO_AN_REG_8481_LEGACY_MII_STATUS,
9836 vars->link_status |=
9837 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
9838 elink_cl45_read(sc, phy,
9840 MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
9842 if ((val & (1 << 0)) == 0)
9843 vars->link_status |=
9844 LINK_STATUS_PARALLEL_DETECTION_USED;
9848 PMD_DRV_LOG(DEBUG, "BNX2X848x3: link speed is %d",
9850 elink_ext_phy_resolve_fc(phy, params, vars);
9852 /* Read LP advertised speeds */
9853 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
9854 MDIO_AN_REG_CL37_FC_LP, &val);
9856 vars->link_status |=
9857 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
9859 vars->link_status |=
9860 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
9862 vars->link_status |=
9863 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
9865 vars->link_status |=
9866 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
9868 vars->link_status |=
9869 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
9871 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
9872 MDIO_AN_REG_1000T_STATUS, &val);
9874 if (val & (1 << 10))
9875 vars->link_status |=
9876 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
9877 if (val & (1 << 11))
9878 vars->link_status |=
9879 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
9881 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
9882 MDIO_AN_REG_MASTER_STATUS, &val);
9884 if (val & (1 << 11))
9885 vars->link_status |=
9886 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
9888 /* Determine if EEE was negotiated */
9889 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||
9890 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834))
9891 elink_eee_an_resolve(phy, params, vars);
9897 static elink_status_t elink_848xx_format_ver(uint32_t raw_ver, uint8_t * str,
9900 elink_status_t status = ELINK_STATUS_OK;
9901 uint32_t spirom_ver;
9902 spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
9903 status = elink_format_ver(spirom_ver, str, len);
9907 static void elink_8481_hw_reset(__rte_unused struct elink_phy *phy,
9908 struct elink_params *params)
9910 elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1,
9911 MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
9912 elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1,
9913 MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
9916 static void elink_8481_link_reset(struct elink_phy *phy,
9917 struct elink_params *params)
9919 elink_cl45_write(params->sc, phy,
9920 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
9921 elink_cl45_write(params->sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
9924 static void elink_848x3_link_reset(struct elink_phy *phy,
9925 struct elink_params *params)
9927 struct bnx2x_softc *sc = params->sc;
9931 if (!(CHIP_IS_E1x(sc)))
9934 port = params->port;
9936 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823) {
9937 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_3,
9938 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
9940 elink_cl45_read(sc, phy,
9942 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16);
9943 val16 |= MDIO_84833_SUPER_ISOLATE;
9944 elink_cl45_write(sc, phy,
9946 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16);
9950 static void elink_848xx_set_link_led(struct elink_phy *phy,
9951 struct elink_params *params, uint8_t mode)
9953 struct bnx2x_softc *sc = params->sc;
9955 __rte_unused uint8_t port;
9957 if (!(CHIP_IS_E1x(sc)))
9960 port = params->port;
9963 case ELINK_LED_MODE_OFF:
9965 PMD_DRV_LOG(DEBUG, "Port 0x%x: LED MODE OFF", port);
9967 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9968 SHARED_HW_CFG_LED_EXTPHY1) {
9971 elink_cl45_write(sc, phy,
9973 MDIO_PMA_REG_8481_LED1_MASK, 0x0);
9975 elink_cl45_write(sc, phy,
9977 MDIO_PMA_REG_8481_LED2_MASK, 0x0);
9979 elink_cl45_write(sc, phy,
9981 MDIO_PMA_REG_8481_LED3_MASK, 0x0);
9983 elink_cl45_write(sc, phy,
9985 MDIO_PMA_REG_8481_LED5_MASK, 0x0);
9988 elink_cl45_write(sc, phy,
9990 MDIO_PMA_REG_8481_LED1_MASK, 0x0);
9993 case ELINK_LED_MODE_FRONT_PANEL_OFF:
9995 PMD_DRV_LOG(DEBUG, "Port 0x%x: LED MODE FRONT PANEL OFF", port);
9997 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9998 SHARED_HW_CFG_LED_EXTPHY1) {
10000 /* Set LED masks */
10001 elink_cl45_write(sc, phy,
10003 MDIO_PMA_REG_8481_LED1_MASK, 0x0);
10005 elink_cl45_write(sc, phy,
10007 MDIO_PMA_REG_8481_LED2_MASK, 0x0);
10009 elink_cl45_write(sc, phy,
10011 MDIO_PMA_REG_8481_LED3_MASK, 0x0);
10013 elink_cl45_write(sc, phy,
10015 MDIO_PMA_REG_8481_LED5_MASK, 0x20);
10018 elink_cl45_write(sc, phy,
10020 MDIO_PMA_REG_8481_LED1_MASK, 0x0);
10021 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834) {
10022 /* Disable MI_INT interrupt before setting LED4
10023 * source to constant off.
10025 if (REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 +
10026 params->port * 4) &
10027 ELINK_NIG_MASK_MI_INT) {
10028 params->link_flags |=
10029 ELINK_LINK_FLAGS_INT_DISABLED;
10032 NIG_REG_MASK_INTERRUPT_PORT0
10033 + params->port * 4,
10034 ELINK_NIG_MASK_MI_INT);
10036 elink_cl45_write(sc, phy,
10038 MDIO_PMA_REG_8481_SIGNAL_MASK,
10043 case ELINK_LED_MODE_ON:
10045 PMD_DRV_LOG(DEBUG, "Port 0x%x: LED MODE ON", port);
10047 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10048 SHARED_HW_CFG_LED_EXTPHY1) {
10049 /* Set control reg */
10050 elink_cl45_read(sc, phy,
10052 MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
10056 elink_cl45_write(sc, phy,
10058 MDIO_PMA_REG_8481_LINK_SIGNAL, val);
10060 /* Set LED masks */
10061 elink_cl45_write(sc, phy,
10063 MDIO_PMA_REG_8481_LED1_MASK, 0x0);
10065 elink_cl45_write(sc, phy,
10067 MDIO_PMA_REG_8481_LED2_MASK, 0x20);
10069 elink_cl45_write(sc, phy,
10071 MDIO_PMA_REG_8481_LED3_MASK, 0x20);
10073 elink_cl45_write(sc, phy,
10075 MDIO_PMA_REG_8481_LED5_MASK, 0x0);
10077 elink_cl45_write(sc, phy,
10079 MDIO_PMA_REG_8481_LED1_MASK, 0x20);
10080 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834) {
10081 /* Disable MI_INT interrupt before setting LED4
10082 * source to constant on.
10084 if (REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 +
10085 params->port * 4) &
10086 ELINK_NIG_MASK_MI_INT) {
10087 params->link_flags |=
10088 ELINK_LINK_FLAGS_INT_DISABLED;
10091 NIG_REG_MASK_INTERRUPT_PORT0
10092 + params->port * 4,
10093 ELINK_NIG_MASK_MI_INT);
10095 elink_cl45_write(sc, phy,
10097 MDIO_PMA_REG_8481_SIGNAL_MASK,
10103 case ELINK_LED_MODE_OPER:
10105 PMD_DRV_LOG(DEBUG, "Port 0x%x: LED MODE OPER", port);
10107 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10108 SHARED_HW_CFG_LED_EXTPHY1) {
10110 /* Set control reg */
10111 elink_cl45_read(sc, phy,
10113 MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
10116 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
10118 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT))
10120 PMD_DRV_LOG(DEBUG, "Setting LINK_SIGNAL");
10121 elink_cl45_write(sc, phy,
10123 MDIO_PMA_REG_8481_LINK_SIGNAL,
10127 /* Set LED masks */
10128 elink_cl45_write(sc, phy,
10130 MDIO_PMA_REG_8481_LED1_MASK, 0x10);
10132 elink_cl45_write(sc, phy,
10134 MDIO_PMA_REG_8481_LED2_MASK, 0x80);
10136 elink_cl45_write(sc, phy,
10138 MDIO_PMA_REG_8481_LED3_MASK, 0x98);
10140 elink_cl45_write(sc, phy,
10142 MDIO_PMA_REG_8481_LED5_MASK, 0x40);
10145 /* EXTPHY2 LED mode indicate that the 100M/1G/10G LED
10146 * sources are all wired through LED1, rather than only
10147 * 10G in other modes.
10149 val = ((params->hw_led_mode <<
10150 SHARED_HW_CFG_LED_MODE_SHIFT) ==
10151 SHARED_HW_CFG_LED_EXTPHY2) ? 0x98 : 0x80;
10153 elink_cl45_write(sc, phy,
10155 MDIO_PMA_REG_8481_LED1_MASK, val);
10157 /* Tell LED3 to blink on source */
10158 elink_cl45_read(sc, phy,
10160 MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
10162 val |= (1 << 6); /* A83B[8:6]= 1 */
10163 elink_cl45_write(sc, phy,
10165 MDIO_PMA_REG_8481_LINK_SIGNAL, val);
10166 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834) {
10167 /* Restore LED4 source to external link,
10168 * and re-enable interrupts.
10170 elink_cl45_write(sc, phy,
10172 MDIO_PMA_REG_8481_SIGNAL_MASK,
10174 if (params->link_flags &
10175 ELINK_LINK_FLAGS_INT_DISABLED) {
10176 elink_link_int_enable(params);
10177 params->link_flags &=
10178 ~ELINK_LINK_FLAGS_INT_DISABLED;
10185 /* This is a workaround for E3+84833 until autoneg
10186 * restart is fixed in f/w
10188 if (CHIP_IS_E3(sc)) {
10189 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
10190 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val);
10194 /******************************************************************/
10195 /* 54618SE PHY SECTION */
10196 /******************************************************************/
10197 static void elink_54618se_specific_func(struct elink_phy *phy,
10198 struct elink_params *params,
10201 struct bnx2x_softc *sc = params->sc;
10204 case ELINK_PHY_INIT:
10205 /* Configure LED4: set to INTR (0x6). */
10206 /* Accessing shadow register 0xe. */
10207 elink_cl22_write(sc, phy,
10208 MDIO_REG_GPHY_SHADOW,
10209 MDIO_REG_GPHY_SHADOW_LED_SEL2);
10210 elink_cl22_read(sc, phy, MDIO_REG_GPHY_SHADOW, &temp);
10211 temp &= ~(0xf << 4);
10212 temp |= (0x6 << 4);
10213 elink_cl22_write(sc, phy,
10214 MDIO_REG_GPHY_SHADOW,
10215 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10216 /* Configure INTR based on link status change. */
10217 elink_cl22_write(sc, phy,
10218 MDIO_REG_INTR_MASK,
10219 ~MDIO_REG_INTR_MASK_LINK_STATUS);
10224 static elink_status_t elink_54618se_config_init(struct elink_phy *phy,
10225 struct elink_params *params,
10226 struct elink_vars *vars)
10228 struct bnx2x_softc *sc = params->sc;
10230 uint16_t autoneg_val, an_1000_val, an_10_100_val, fc_val, temp;
10233 PMD_DRV_LOG(DEBUG, "54618SE cfg init");
10236 /* This works with E3 only, no need to check the chip
10237 * before determining the port.
10239 port = params->port;
10241 cfg_pin = (REG_RD(sc, params->shmem_base +
10242 offsetof(struct shmem_region,
10243 dev_info.port_hw_config[port].
10245 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10246 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10248 /* Drive pin high to bring the GPHY out of reset. */
10249 elink_set_cfg_pin(sc, cfg_pin, 1);
10251 /* wait for GPHY to reset */
10255 elink_cl22_write(sc, phy, MDIO_PMA_REG_CTRL, 0x8000);
10256 elink_wait_reset_complete(sc, phy, params);
10258 /* Wait for GPHY to reset */
10261 elink_54618se_specific_func(phy, params, ELINK_PHY_INIT);
10262 /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
10263 elink_cl22_write(sc, phy,
10264 MDIO_REG_GPHY_SHADOW,
10265 MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
10266 elink_cl22_read(sc, phy, MDIO_REG_GPHY_SHADOW, &temp);
10267 temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD;
10268 elink_cl22_write(sc, phy,
10269 MDIO_REG_GPHY_SHADOW,
10270 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10273 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
10274 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
10276 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
10277 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
10278 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
10280 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
10281 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
10282 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
10284 /* Read all advertisement */
10285 elink_cl22_read(sc, phy, 0x09, &an_1000_val);
10287 elink_cl22_read(sc, phy, 0x04, &an_10_100_val);
10289 elink_cl22_read(sc, phy, MDIO_PMA_REG_CTRL, &autoneg_val);
10291 /* Disable forced speed */
10293 ~((1 << 6) | (1 << 8) | (1 << 9) | (1 << 12) | (1 << 13));
10295 ~((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 10) |
10298 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
10299 (phy->speed_cap_mask &
10300 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
10301 (phy->req_line_speed == ELINK_SPEED_1000)) {
10302 an_1000_val |= (1 << 8);
10303 autoneg_val |= (1 << 9 | 1 << 12);
10304 if (phy->req_duplex == DUPLEX_FULL)
10305 an_1000_val |= (1 << 9);
10306 PMD_DRV_LOG(DEBUG, "Advertising 1G");
10308 an_1000_val &= ~((1 << 8) | (1 << 9));
10310 elink_cl22_write(sc, phy, 0x09, an_1000_val);
10311 elink_cl22_read(sc, phy, 0x09, &an_1000_val);
10313 /* Advertise 10/100 link speed */
10314 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {
10315 if (phy->speed_cap_mask &
10316 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) {
10317 an_10_100_val |= (1 << 5);
10318 autoneg_val |= (1 << 9 | 1 << 12);
10319 PMD_DRV_LOG(DEBUG, "Advertising 10M-HD");
10321 if (phy->speed_cap_mask &
10322 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) {
10323 an_10_100_val |= (1 << 6);
10324 autoneg_val |= (1 << 9 | 1 << 12);
10325 PMD_DRV_LOG(DEBUG, "Advertising 10M-FD");
10327 if (phy->speed_cap_mask &
10328 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) {
10329 an_10_100_val |= (1 << 7);
10330 autoneg_val |= (1 << 9 | 1 << 12);
10331 PMD_DRV_LOG(DEBUG, "Advertising 100M-HD");
10333 if (phy->speed_cap_mask &
10334 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) {
10335 an_10_100_val |= (1 << 8);
10336 autoneg_val |= (1 << 9 | 1 << 12);
10337 PMD_DRV_LOG(DEBUG, "Advertising 100M-FD");
10341 /* Only 10/100 are allowed to work in FORCE mode */
10342 if (phy->req_line_speed == ELINK_SPEED_100) {
10343 autoneg_val |= (1 << 13);
10344 /* Enabled AUTO-MDIX when autoneg is disabled */
10345 elink_cl22_write(sc, phy, 0x18, (1 << 15 | 1 << 9 | 7 << 0));
10346 PMD_DRV_LOG(DEBUG, "Setting 100M force");
10348 if (phy->req_line_speed == ELINK_SPEED_10) {
10349 /* Enabled AUTO-MDIX when autoneg is disabled */
10350 elink_cl22_write(sc, phy, 0x18, (1 << 15 | 1 << 9 | 7 << 0));
10351 PMD_DRV_LOG(DEBUG, "Setting 10M force");
10354 if ((phy->flags & ELINK_FLAGS_EEE) && elink_eee_has_cap(params)) {
10357 elink_cl22_write(sc, phy, MDIO_REG_GPHY_EXP_ACCESS,
10358 MDIO_REG_GPHY_EXP_ACCESS_TOP |
10359 MDIO_REG_GPHY_EXP_TOP_2K_BUF);
10360 elink_cl22_read(sc, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp);
10362 elink_cl22_write(sc, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp);
10364 rc = elink_eee_initial_config(params, vars, SHMEM_EEE_1G_ADV);
10365 if (rc != ELINK_STATUS_OK) {
10366 PMD_DRV_LOG(DEBUG, "Failed to configure EEE timers");
10367 elink_eee_disable(phy, params, vars);
10368 } else if ((params->eee_mode & ELINK_EEE_MODE_ADV_LPI) &&
10369 (phy->req_duplex == DUPLEX_FULL) &&
10370 (elink_eee_calc_timer(params) ||
10371 !(params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI))) {
10372 /* Need to advertise EEE only when requested,
10373 * and either no LPI assertion was requested,
10374 * or it was requested and a valid timer was set.
10375 * Also notice full duplex is required for EEE.
10377 elink_eee_advertise(phy, params, vars,
10380 PMD_DRV_LOG(DEBUG, "Don't Advertise 1GBase-T EEE");
10381 elink_eee_disable(phy, params, vars);
10384 vars->eee_status &= ~SHMEM_EEE_1G_ADV <<
10385 SHMEM_EEE_SUPPORTED_SHIFT;
10387 if (phy->flags & ELINK_FLAGS_EEE) {
10388 /* Handle legacy auto-grEEEn */
10389 if (params->feature_config_flags &
10390 ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
10392 PMD_DRV_LOG(DEBUG, "Enabling Auto-GrEEEn");
10395 PMD_DRV_LOG(DEBUG, "Don't Adv. EEE");
10397 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
10398 MDIO_AN_REG_EEE_ADV, temp);
10402 elink_cl22_write(sc, phy, 0x04, an_10_100_val | fc_val);
10404 if (phy->req_duplex == DUPLEX_FULL)
10405 autoneg_val |= (1 << 8);
10407 elink_cl22_write(sc, phy, MDIO_PMA_REG_CTRL, autoneg_val);
10409 return ELINK_STATUS_OK;
10412 static void elink_5461x_set_link_led(struct elink_phy *phy,
10413 struct elink_params *params, uint8_t mode)
10415 struct bnx2x_softc *sc = params->sc;
10418 elink_cl22_write(sc, phy,
10419 MDIO_REG_GPHY_SHADOW, MDIO_REG_GPHY_SHADOW_LED_SEL1);
10420 elink_cl22_read(sc, phy, MDIO_REG_GPHY_SHADOW, &temp);
10423 PMD_DRV_LOG(DEBUG, "54618x set link led (mode=%x)", mode);
10425 case ELINK_LED_MODE_FRONT_PANEL_OFF:
10426 case ELINK_LED_MODE_OFF:
10429 case ELINK_LED_MODE_OPER:
10432 case ELINK_LED_MODE_ON:
10438 elink_cl22_write(sc, phy,
10439 MDIO_REG_GPHY_SHADOW,
10440 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10444 static void elink_54618se_link_reset(struct elink_phy *phy,
10445 struct elink_params *params)
10447 struct bnx2x_softc *sc = params->sc;
10451 /* In case of no EPIO routed to reset the GPHY, put it
10452 * in low power mode.
10454 elink_cl22_write(sc, phy, MDIO_PMA_REG_CTRL, 0x800);
10455 /* This works with E3 only, no need to check the chip
10456 * before determining the port.
10458 port = params->port;
10459 cfg_pin = (REG_RD(sc, params->shmem_base +
10460 offsetof(struct shmem_region,
10461 dev_info.port_hw_config[port].
10463 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10464 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10466 /* Drive pin low to put GPHY in reset. */
10467 elink_set_cfg_pin(sc, cfg_pin, 0);
10470 static uint8_t elink_54618se_read_status(struct elink_phy *phy,
10471 struct elink_params *params,
10472 struct elink_vars *vars)
10474 struct bnx2x_softc *sc = params->sc;
10476 uint8_t link_up = 0;
10477 uint16_t legacy_status, legacy_speed;
10479 /* Get speed operation status */
10480 elink_cl22_read(sc, phy, MDIO_REG_GPHY_AUX_STATUS, &legacy_status);
10481 PMD_DRV_LOG(DEBUG, "54618SE read_status: 0x%x", legacy_status);
10483 /* Read status to clear the PHY interrupt. */
10484 elink_cl22_read(sc, phy, MDIO_REG_INTR_STATUS, &val);
10486 link_up = ((legacy_status & (1 << 2)) == (1 << 2));
10489 legacy_speed = (legacy_status & (7 << 8));
10490 if (legacy_speed == (7 << 8)) {
10491 vars->line_speed = ELINK_SPEED_1000;
10492 vars->duplex = DUPLEX_FULL;
10493 } else if (legacy_speed == (6 << 8)) {
10494 vars->line_speed = ELINK_SPEED_1000;
10495 vars->duplex = DUPLEX_HALF;
10496 } else if (legacy_speed == (5 << 8)) {
10497 vars->line_speed = ELINK_SPEED_100;
10498 vars->duplex = DUPLEX_FULL;
10500 /* Omitting 100Base-T4 for now */
10501 else if (legacy_speed == (3 << 8)) {
10502 vars->line_speed = ELINK_SPEED_100;
10503 vars->duplex = DUPLEX_HALF;
10504 } else if (legacy_speed == (2 << 8)) {
10505 vars->line_speed = ELINK_SPEED_10;
10506 vars->duplex = DUPLEX_FULL;
10507 } else if (legacy_speed == (1 << 8)) {
10508 vars->line_speed = ELINK_SPEED_10;
10509 vars->duplex = DUPLEX_HALF;
10510 } else /* Should not happen */
10511 vars->line_speed = 0;
10514 "Link is up in %dMbps, is_duplex_full= %d",
10515 vars->line_speed, (vars->duplex == DUPLEX_FULL));
10517 /* Check legacy speed AN resolution */
10518 elink_cl22_read(sc, phy, 0x01, &val);
10519 if (val & (1 << 5))
10520 vars->link_status |=
10521 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10522 elink_cl22_read(sc, phy, 0x06, &val);
10523 if ((val & (1 << 0)) == 0)
10524 vars->link_status |=
10525 LINK_STATUS_PARALLEL_DETECTION_USED;
10527 PMD_DRV_LOG(DEBUG, "BNX2X54618SE: link speed is %d",
10530 elink_ext_phy_resolve_fc(phy, params, vars);
10532 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
10533 /* Report LP advertised speeds */
10534 elink_cl22_read(sc, phy, 0x5, &val);
10536 if (val & (1 << 5))
10537 vars->link_status |=
10538 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
10539 if (val & (1 << 6))
10540 vars->link_status |=
10541 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
10542 if (val & (1 << 7))
10543 vars->link_status |=
10544 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
10545 if (val & (1 << 8))
10546 vars->link_status |=
10547 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
10548 if (val & (1 << 9))
10549 vars->link_status |=
10550 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
10552 elink_cl22_read(sc, phy, 0xa, &val);
10553 if (val & (1 << 10))
10554 vars->link_status |=
10555 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
10556 if (val & (1 << 11))
10557 vars->link_status |=
10558 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
10560 if ((phy->flags & ELINK_FLAGS_EEE) &&
10561 elink_eee_has_cap(params))
10562 elink_eee_an_resolve(phy, params, vars);
10568 static void elink_54618se_config_loopback(struct elink_phy *phy,
10569 struct elink_params *params)
10571 struct bnx2x_softc *sc = params->sc;
10573 uint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
10575 PMD_DRV_LOG(DEBUG, "2PMA/PMD ext_phy_loopback: 54618se");
10577 /* Enable master/slave manual mmode and set to master */
10578 /* mii write 9 [bits set 11 12] */
10579 elink_cl22_write(sc, phy, 0x09, 3 << 11);
10581 /* forced 1G and disable autoneg */
10582 /* set val [mii read 0] */
10583 /* set val [expr $val & [bits clear 6 12 13]] */
10584 /* set val [expr $val | [bits set 6 8]] */
10585 /* mii write 0 $val */
10586 elink_cl22_read(sc, phy, 0x00, &val);
10587 val &= ~((1 << 6) | (1 << 12) | (1 << 13));
10588 val |= (1 << 6) | (1 << 8);
10589 elink_cl22_write(sc, phy, 0x00, val);
10591 /* Set external loopback and Tx using 6dB coding */
10592 /* mii write 0x18 7 */
10593 /* set val [mii read 0x18] */
10594 /* mii write 0x18 [expr $val | [bits set 10 15]] */
10595 elink_cl22_write(sc, phy, 0x18, 7);
10596 elink_cl22_read(sc, phy, 0x18, &val);
10597 elink_cl22_write(sc, phy, 0x18, val | (1 << 10) | (1 << 15));
10599 /* This register opens the gate for the UMAC despite its name */
10600 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port * 4, 1);
10602 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
10603 * length used by the MAC receive logic to check frames.
10605 REG_WR(sc, umac_base + UMAC_REG_MAXFR, 0x2710);
10608 /******************************************************************/
10609 /* SFX7101 PHY SECTION */
10610 /******************************************************************/
10611 static void elink_7101_config_loopback(struct elink_phy *phy,
10612 struct elink_params *params)
10614 struct bnx2x_softc *sc = params->sc;
10615 /* SFX7101_XGXS_TEST1 */
10616 elink_cl45_write(sc, phy,
10617 MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
10620 static elink_status_t elink_7101_config_init(struct elink_phy *phy,
10621 struct elink_params *params,
10622 struct elink_vars *vars)
10624 uint16_t fw_ver1, fw_ver2, val;
10625 struct bnx2x_softc *sc = params->sc;
10626 PMD_DRV_LOG(DEBUG, "Setting the SFX7101 LASI indication");
10628 /* Restore normal power mode */
10629 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
10630 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
10632 elink_ext_phy_hw_reset(sc, params->port);
10633 elink_wait_reset_complete(sc, phy, params);
10635 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1);
10636 PMD_DRV_LOG(DEBUG, "Setting the SFX7101 LED to blink on traffic");
10637 elink_cl45_write(sc, phy,
10638 MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1 << 3));
10640 elink_ext_phy_set_pause(params, phy, vars);
10641 /* Restart autoneg */
10642 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
10644 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
10646 /* Save spirom version */
10647 elink_cl45_read(sc, phy,
10648 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
10650 elink_cl45_read(sc, phy,
10651 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
10652 elink_save_spirom_version(sc, params->port,
10653 (uint32_t) (fw_ver1 << 16 | fw_ver2),
10655 return ELINK_STATUS_OK;
10658 static uint8_t elink_7101_read_status(struct elink_phy *phy,
10659 struct elink_params *params,
10660 struct elink_vars *vars)
10662 struct bnx2x_softc *sc = params->sc;
10664 uint16_t val1, val2;
10665 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
10666 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
10667 PMD_DRV_LOG(DEBUG, "10G-base-T LASI status 0x%x->0x%x", val2, val1);
10668 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
10669 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
10670 PMD_DRV_LOG(DEBUG, "10G-base-T PMA status 0x%x->0x%x", val2, val1);
10671 link_up = ((val1 & 4) == 4);
10672 /* If link is up print the AN outcome of the SFX7101 PHY */
10674 elink_cl45_read(sc, phy,
10675 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
10677 vars->line_speed = ELINK_SPEED_10000;
10678 vars->duplex = DUPLEX_FULL;
10679 PMD_DRV_LOG(DEBUG, "SFX7101 AN status 0x%x->Master=%x",
10680 val2, (val2 & (1 << 14)));
10681 elink_ext_phy_10G_an_resolve(sc, phy, vars);
10682 elink_ext_phy_resolve_fc(phy, params, vars);
10684 /* Read LP advertised speeds */
10685 if (val2 & (1 << 11))
10686 vars->link_status |=
10687 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
10692 static elink_status_t elink_7101_format_ver(uint32_t spirom_ver, uint8_t * str,
10696 return ELINK_STATUS_ERROR;
10697 str[0] = (spirom_ver & 0xFF);
10698 str[1] = (spirom_ver & 0xFF00) >> 8;
10699 str[2] = (spirom_ver & 0xFF0000) >> 16;
10700 str[3] = (spirom_ver & 0xFF000000) >> 24;
10703 return ELINK_STATUS_OK;
10706 static void elink_7101_hw_reset(__rte_unused struct elink_phy *phy,
10707 struct elink_params *params)
10709 /* Low power mode is controlled by GPIO 2 */
10710 elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_2,
10711 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
10712 /* The PHY reset is controlled by GPIO 1 */
10713 elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1,
10714 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
10717 static void elink_7101_set_link_led(struct elink_phy *phy,
10718 struct elink_params *params, uint8_t mode)
10721 struct bnx2x_softc *sc = params->sc;
10723 case ELINK_LED_MODE_FRONT_PANEL_OFF:
10724 case ELINK_LED_MODE_OFF:
10727 case ELINK_LED_MODE_ON:
10730 case ELINK_LED_MODE_OPER:
10734 elink_cl45_write(sc, phy,
10735 MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LINK_LED_CNTL, val);
10738 /******************************************************************/
10739 /* STATIC PHY DECLARATION */
10740 /******************************************************************/
10742 static const struct elink_phy phy_null = {
10743 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
10746 .flags = ELINK_FLAGS_INIT_XGXS_FIRST,
10747 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10748 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10751 .media_type = ELINK_ETH_PHY_NOT_PRESENT,
10753 .req_flow_ctrl = 0,
10754 .req_line_speed = 0,
10755 .speed_cap_mask = 0,
10758 .config_init = (config_init_t) NULL,
10759 .read_status = (read_status_t) NULL,
10760 .link_reset = (link_reset_t) NULL,
10761 .config_loopback = (config_loopback_t) NULL,
10762 .format_fw_ver = (format_fw_ver_t) NULL,
10763 .hw_reset = (hw_reset_t) NULL,
10764 .set_link_led = (set_link_led_t) NULL,
10765 .phy_specific_func = (phy_specific_func_t) NULL
10768 static const struct elink_phy phy_serdes = {
10769 .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
10773 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10774 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10776 .supported = (ELINK_SUPPORTED_10baseT_Half |
10777 ELINK_SUPPORTED_10baseT_Full |
10778 ELINK_SUPPORTED_100baseT_Half |
10779 ELINK_SUPPORTED_100baseT_Full |
10780 ELINK_SUPPORTED_1000baseT_Full |
10781 ELINK_SUPPORTED_2500baseX_Full |
10782 ELINK_SUPPORTED_TP |
10783 ELINK_SUPPORTED_Autoneg |
10784 ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
10785 .media_type = ELINK_ETH_PHY_BASE_T,
10787 .req_flow_ctrl = 0,
10788 .req_line_speed = 0,
10789 .speed_cap_mask = 0,
10792 .config_init = (config_init_t) elink_xgxs_config_init,
10793 .read_status = (read_status_t) elink_link_settings_status,
10794 .link_reset = (link_reset_t) elink_int_link_reset,
10795 .config_loopback = (config_loopback_t) NULL,
10796 .format_fw_ver = (format_fw_ver_t) NULL,
10797 .hw_reset = (hw_reset_t) NULL,
10798 .set_link_led = (set_link_led_t) NULL,
10799 .phy_specific_func = (phy_specific_func_t) NULL
10802 static const struct elink_phy phy_xgxs = {
10803 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
10807 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10808 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10810 .supported = (ELINK_SUPPORTED_10baseT_Half |
10811 ELINK_SUPPORTED_10baseT_Full |
10812 ELINK_SUPPORTED_100baseT_Half |
10813 ELINK_SUPPORTED_100baseT_Full |
10814 ELINK_SUPPORTED_1000baseT_Full |
10815 ELINK_SUPPORTED_2500baseX_Full |
10816 ELINK_SUPPORTED_10000baseT_Full |
10817 ELINK_SUPPORTED_FIBRE |
10818 ELINK_SUPPORTED_Autoneg |
10819 ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
10820 .media_type = ELINK_ETH_PHY_CX4,
10822 .req_flow_ctrl = 0,
10823 .req_line_speed = 0,
10824 .speed_cap_mask = 0,
10827 .config_init = (config_init_t) elink_xgxs_config_init,
10828 .read_status = (read_status_t) elink_link_settings_status,
10829 .link_reset = (link_reset_t) elink_int_link_reset,
10830 .config_loopback = (config_loopback_t) elink_set_xgxs_loopback,
10831 .format_fw_ver = (format_fw_ver_t) NULL,
10832 .hw_reset = (hw_reset_t) NULL,
10833 .set_link_led = (set_link_led_t) NULL,
10834 .phy_specific_func = (phy_specific_func_t) elink_xgxs_specific_func
10837 static const struct elink_phy phy_warpcore = {
10838 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
10841 .flags = ELINK_FLAGS_TX_ERROR_CHECK,
10842 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10843 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10845 .supported = (ELINK_SUPPORTED_10baseT_Half |
10846 ELINK_SUPPORTED_10baseT_Full |
10847 ELINK_SUPPORTED_100baseT_Half |
10848 ELINK_SUPPORTED_100baseT_Full |
10849 ELINK_SUPPORTED_1000baseT_Full |
10850 ELINK_SUPPORTED_10000baseT_Full |
10851 ELINK_SUPPORTED_20000baseKR2_Full |
10852 ELINK_SUPPORTED_20000baseMLD2_Full |
10853 ELINK_SUPPORTED_FIBRE |
10854 ELINK_SUPPORTED_Autoneg |
10855 ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
10856 .media_type = ELINK_ETH_PHY_UNSPECIFIED,
10858 .req_flow_ctrl = 0,
10859 .req_line_speed = 0,
10860 .speed_cap_mask = 0,
10861 /* req_duplex = */ 0,
10863 .config_init = (config_init_t) elink_warpcore_config_init,
10864 .read_status = (read_status_t) elink_warpcore_read_status,
10865 .link_reset = (link_reset_t) elink_warpcore_link_reset,
10866 .config_loopback = (config_loopback_t) elink_set_warpcore_loopback,
10867 .format_fw_ver = (format_fw_ver_t) NULL,
10868 .hw_reset = (hw_reset_t) elink_warpcore_hw_reset,
10869 .set_link_led = (set_link_led_t) NULL,
10870 .phy_specific_func = (phy_specific_func_t) NULL
10873 static const struct elink_phy phy_7101 = {
10874 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
10877 .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ,
10878 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10879 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10881 .supported = (ELINK_SUPPORTED_10000baseT_Full |
10882 ELINK_SUPPORTED_TP |
10883 ELINK_SUPPORTED_Autoneg |
10884 ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
10885 .media_type = ELINK_ETH_PHY_BASE_T,
10887 .req_flow_ctrl = 0,
10888 .req_line_speed = 0,
10889 .speed_cap_mask = 0,
10892 .config_init = (config_init_t) elink_7101_config_init,
10893 .read_status = (read_status_t) elink_7101_read_status,
10894 .link_reset = (link_reset_t) elink_common_ext_link_reset,
10895 .config_loopback = (config_loopback_t) elink_7101_config_loopback,
10896 .format_fw_ver = (format_fw_ver_t) elink_7101_format_ver,
10897 .hw_reset = (hw_reset_t) elink_7101_hw_reset,
10898 .set_link_led = (set_link_led_t) elink_7101_set_link_led,
10899 .phy_specific_func = (phy_specific_func_t) NULL
10902 static const struct elink_phy phy_8073 = {
10903 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073,
10907 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10908 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10910 .supported = (ELINK_SUPPORTED_10000baseT_Full |
10911 ELINK_SUPPORTED_2500baseX_Full |
10912 ELINK_SUPPORTED_1000baseT_Full |
10913 ELINK_SUPPORTED_FIBRE |
10914 ELINK_SUPPORTED_Autoneg |
10915 ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
10916 .media_type = ELINK_ETH_PHY_KR,
10918 .req_flow_ctrl = 0,
10919 .req_line_speed = 0,
10920 .speed_cap_mask = 0,
10923 .config_init = (config_init_t) elink_8073_config_init,
10924 .read_status = (read_status_t) elink_8073_read_status,
10925 .link_reset = (link_reset_t) elink_8073_link_reset,
10926 .config_loopback = (config_loopback_t) NULL,
10927 .format_fw_ver = (format_fw_ver_t) elink_format_ver,
10928 .hw_reset = (hw_reset_t) NULL,
10929 .set_link_led = (set_link_led_t) NULL,
10930 .phy_specific_func = (phy_specific_func_t) elink_8073_specific_func
10933 static const struct elink_phy phy_8705 = {
10934 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8705,
10937 .flags = ELINK_FLAGS_INIT_XGXS_FIRST,
10938 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10939 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10941 .supported = (ELINK_SUPPORTED_10000baseT_Full |
10942 ELINK_SUPPORTED_FIBRE |
10943 ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
10944 .media_type = ELINK_ETH_PHY_XFP_FIBER,
10946 .req_flow_ctrl = 0,
10947 .req_line_speed = 0,
10948 .speed_cap_mask = 0,
10951 .config_init = (config_init_t) elink_8705_config_init,
10952 .read_status = (read_status_t) elink_8705_read_status,
10953 .link_reset = (link_reset_t) elink_common_ext_link_reset,
10954 .config_loopback = (config_loopback_t) NULL,
10955 .format_fw_ver = (format_fw_ver_t) elink_null_format_ver,
10956 .hw_reset = (hw_reset_t) NULL,
10957 .set_link_led = (set_link_led_t) NULL,
10958 .phy_specific_func = (phy_specific_func_t) NULL
10961 static const struct elink_phy phy_8706 = {
10962 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8706,
10965 .flags = ELINK_FLAGS_INIT_XGXS_FIRST,
10966 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10967 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10969 .supported = (ELINK_SUPPORTED_10000baseT_Full |
10970 ELINK_SUPPORTED_1000baseT_Full |
10971 ELINK_SUPPORTED_FIBRE |
10972 ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
10973 .media_type = ELINK_ETH_PHY_SFPP_10G_FIBER,
10975 .req_flow_ctrl = 0,
10976 .req_line_speed = 0,
10977 .speed_cap_mask = 0,
10980 .config_init = (config_init_t) elink_8706_config_init,
10981 .read_status = (read_status_t) elink_8706_read_status,
10982 .link_reset = (link_reset_t) elink_common_ext_link_reset,
10983 .config_loopback = (config_loopback_t) NULL,
10984 .format_fw_ver = (format_fw_ver_t) elink_format_ver,
10985 .hw_reset = (hw_reset_t) NULL,
10986 .set_link_led = (set_link_led_t) NULL,
10987 .phy_specific_func = (phy_specific_func_t) NULL
10990 static const struct elink_phy phy_8726 = {
10991 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726,
10994 .flags = (ELINK_FLAGS_INIT_XGXS_FIRST | ELINK_FLAGS_TX_ERROR_CHECK),
10995 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10996 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10998 .supported = (ELINK_SUPPORTED_10000baseT_Full |
10999 ELINK_SUPPORTED_1000baseT_Full |
11000 ELINK_SUPPORTED_Autoneg |
11001 ELINK_SUPPORTED_FIBRE |
11002 ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
11003 .media_type = ELINK_ETH_PHY_NOT_PRESENT,
11005 .req_flow_ctrl = 0,
11006 .req_line_speed = 0,
11007 .speed_cap_mask = 0,
11010 .config_init = (config_init_t) elink_8726_config_init,
11011 .read_status = (read_status_t) elink_8726_read_status,
11012 .link_reset = (link_reset_t) elink_8726_link_reset,
11013 .config_loopback = (config_loopback_t) elink_8726_config_loopback,
11014 .format_fw_ver = (format_fw_ver_t) elink_format_ver,
11015 .hw_reset = (hw_reset_t) NULL,
11016 .set_link_led = (set_link_led_t) NULL,
11017 .phy_specific_func = (phy_specific_func_t) NULL
11020 static const struct elink_phy phy_8727 = {
11021 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727,
11024 .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ | ELINK_FLAGS_TX_ERROR_CHECK),
11025 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11026 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11028 .supported = (ELINK_SUPPORTED_10000baseT_Full |
11029 ELINK_SUPPORTED_1000baseT_Full |
11030 ELINK_SUPPORTED_FIBRE |
11031 ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
11032 .media_type = ELINK_ETH_PHY_NOT_PRESENT,
11034 .req_flow_ctrl = 0,
11035 .req_line_speed = 0,
11036 .speed_cap_mask = 0,
11039 .config_init = (config_init_t) elink_8727_config_init,
11040 .read_status = (read_status_t) elink_8727_read_status,
11041 .link_reset = (link_reset_t) elink_8727_link_reset,
11042 .config_loopback = (config_loopback_t) NULL,
11043 .format_fw_ver = (format_fw_ver_t) elink_format_ver,
11044 .hw_reset = (hw_reset_t) elink_8727_hw_reset,
11045 .set_link_led = (set_link_led_t) elink_8727_set_link_led,
11046 .phy_specific_func = (phy_specific_func_t) elink_8727_specific_func
11049 static const struct elink_phy phy_8481 = {
11050 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8481,
11053 .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ |
11054 ELINK_FLAGS_REARM_LATCH_SIGNAL,
11055 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11056 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11058 .supported = (ELINK_SUPPORTED_10baseT_Half |
11059 ELINK_SUPPORTED_10baseT_Full |
11060 ELINK_SUPPORTED_100baseT_Half |
11061 ELINK_SUPPORTED_100baseT_Full |
11062 ELINK_SUPPORTED_1000baseT_Full |
11063 ELINK_SUPPORTED_10000baseT_Full |
11064 ELINK_SUPPORTED_TP |
11065 ELINK_SUPPORTED_Autoneg |
11066 ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
11067 .media_type = ELINK_ETH_PHY_BASE_T,
11069 .req_flow_ctrl = 0,
11070 .req_line_speed = 0,
11071 .speed_cap_mask = 0,
11074 .config_init = (config_init_t) elink_8481_config_init,
11075 .read_status = (read_status_t) elink_848xx_read_status,
11076 .link_reset = (link_reset_t) elink_8481_link_reset,
11077 .config_loopback = (config_loopback_t) NULL,
11078 .format_fw_ver = (format_fw_ver_t) elink_848xx_format_ver,
11079 .hw_reset = (hw_reset_t) elink_8481_hw_reset,
11080 .set_link_led = (set_link_led_t) elink_848xx_set_link_led,
11081 .phy_specific_func = (phy_specific_func_t) NULL
11084 static const struct elink_phy phy_84823 = {
11085 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823,
11088 .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ |
11089 ELINK_FLAGS_REARM_LATCH_SIGNAL | ELINK_FLAGS_TX_ERROR_CHECK),
11090 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11091 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11093 .supported = (ELINK_SUPPORTED_10baseT_Half |
11094 ELINK_SUPPORTED_10baseT_Full |
11095 ELINK_SUPPORTED_100baseT_Half |
11096 ELINK_SUPPORTED_100baseT_Full |
11097 ELINK_SUPPORTED_1000baseT_Full |
11098 ELINK_SUPPORTED_10000baseT_Full |
11099 ELINK_SUPPORTED_TP |
11100 ELINK_SUPPORTED_Autoneg |
11101 ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
11102 .media_type = ELINK_ETH_PHY_BASE_T,
11104 .req_flow_ctrl = 0,
11105 .req_line_speed = 0,
11106 .speed_cap_mask = 0,
11109 .config_init = (config_init_t) elink_848x3_config_init,
11110 .read_status = (read_status_t) elink_848xx_read_status,
11111 .link_reset = (link_reset_t) elink_848x3_link_reset,
11112 .config_loopback = (config_loopback_t) NULL,
11113 .format_fw_ver = (format_fw_ver_t) elink_848xx_format_ver,
11114 .hw_reset = (hw_reset_t) NULL,
11115 .set_link_led = (set_link_led_t) elink_848xx_set_link_led,
11116 .phy_specific_func = (phy_specific_func_t) elink_848xx_specific_func
11119 static const struct elink_phy phy_84833 = {
11120 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833,
11123 .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ |
11124 ELINK_FLAGS_REARM_LATCH_SIGNAL |
11125 ELINK_FLAGS_TX_ERROR_CHECK | ELINK_FLAGS_TEMPERATURE),
11126 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11127 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11129 .supported = (ELINK_SUPPORTED_100baseT_Half |
11130 ELINK_SUPPORTED_100baseT_Full |
11131 ELINK_SUPPORTED_1000baseT_Full |
11132 ELINK_SUPPORTED_10000baseT_Full |
11133 ELINK_SUPPORTED_TP |
11134 ELINK_SUPPORTED_Autoneg |
11135 ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
11136 .media_type = ELINK_ETH_PHY_BASE_T,
11138 .req_flow_ctrl = 0,
11139 .req_line_speed = 0,
11140 .speed_cap_mask = 0,
11143 .config_init = (config_init_t) elink_848x3_config_init,
11144 .read_status = (read_status_t) elink_848xx_read_status,
11145 .link_reset = (link_reset_t) elink_848x3_link_reset,
11146 .config_loopback = (config_loopback_t) NULL,
11147 .format_fw_ver = (format_fw_ver_t) elink_848xx_format_ver,
11148 .hw_reset = (hw_reset_t) elink_84833_hw_reset_phy,
11149 .set_link_led = (set_link_led_t) elink_848xx_set_link_led,
11150 .phy_specific_func = (phy_specific_func_t) elink_848xx_specific_func
11153 static const struct elink_phy phy_84834 = {
11154 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834,
11157 .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ |
11158 ELINK_FLAGS_REARM_LATCH_SIGNAL,
11159 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11160 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11162 .supported = (ELINK_SUPPORTED_100baseT_Half |
11163 ELINK_SUPPORTED_100baseT_Full |
11164 ELINK_SUPPORTED_1000baseT_Full |
11165 ELINK_SUPPORTED_10000baseT_Full |
11166 ELINK_SUPPORTED_TP |
11167 ELINK_SUPPORTED_Autoneg |
11168 ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
11169 .media_type = ELINK_ETH_PHY_BASE_T,
11171 .req_flow_ctrl = 0,
11172 .req_line_speed = 0,
11173 .speed_cap_mask = 0,
11176 .config_init = (config_init_t) elink_848x3_config_init,
11177 .read_status = (read_status_t) elink_848xx_read_status,
11178 .link_reset = (link_reset_t) elink_848x3_link_reset,
11179 .config_loopback = (config_loopback_t) NULL,
11180 .format_fw_ver = (format_fw_ver_t) elink_848xx_format_ver,
11181 .hw_reset = (hw_reset_t) elink_84833_hw_reset_phy,
11182 .set_link_led = (set_link_led_t) elink_848xx_set_link_led,
11183 .phy_specific_func = (phy_specific_func_t) elink_848xx_specific_func
11186 static const struct elink_phy phy_54618se = {
11187 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE,
11190 .flags = ELINK_FLAGS_INIT_XGXS_FIRST,
11191 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11192 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11194 .supported = (ELINK_SUPPORTED_10baseT_Half |
11195 ELINK_SUPPORTED_10baseT_Full |
11196 ELINK_SUPPORTED_100baseT_Half |
11197 ELINK_SUPPORTED_100baseT_Full |
11198 ELINK_SUPPORTED_1000baseT_Full |
11199 ELINK_SUPPORTED_TP |
11200 ELINK_SUPPORTED_Autoneg |
11201 ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
11202 .media_type = ELINK_ETH_PHY_BASE_T,
11204 .req_flow_ctrl = 0,
11205 .req_line_speed = 0,
11206 .speed_cap_mask = 0,
11207 /* req_duplex = */ 0,
11209 .config_init = (config_init_t) elink_54618se_config_init,
11210 .read_status = (read_status_t) elink_54618se_read_status,
11211 .link_reset = (link_reset_t) elink_54618se_link_reset,
11212 .config_loopback = (config_loopback_t) elink_54618se_config_loopback,
11213 .format_fw_ver = (format_fw_ver_t) NULL,
11214 .hw_reset = (hw_reset_t) NULL,
11215 .set_link_led = (set_link_led_t) elink_5461x_set_link_led,
11216 .phy_specific_func = (phy_specific_func_t) elink_54618se_specific_func
11219 /*****************************************************************/
11221 /* Populate the phy according. Main function: elink_populate_phy */
11223 /*****************************************************************/
11225 static void elink_populate_preemphasis(struct bnx2x_softc *sc,
11226 uint32_t shmem_base,
11227 struct elink_phy *phy, uint8_t port,
11230 /* Get the 4 lanes xgxs config rx and tx */
11231 uint32_t rx = 0, tx = 0, i;
11232 for (i = 0; i < 2; i++) {
11233 /* INT_PHY and ELINK_EXT_PHY1 share the same value location in
11234 * the shmem. When num_phys is greater than 1, than this value
11235 * applies only to ELINK_EXT_PHY1
11237 if (phy_index == ELINK_INT_PHY || phy_index == ELINK_EXT_PHY1) {
11238 rx = REG_RD(sc, shmem_base +
11239 offsetof(struct shmem_region,
11240 dev_info.port_hw_config[port].
11241 xgxs_config_rx[i << 1]));
11243 tx = REG_RD(sc, shmem_base +
11244 offsetof(struct shmem_region,
11245 dev_info.port_hw_config[port].
11246 xgxs_config_tx[i << 1]));
11248 rx = REG_RD(sc, shmem_base +
11249 offsetof(struct shmem_region,
11250 dev_info.port_hw_config[port].
11251 xgxs_config2_rx[i << 1]));
11253 tx = REG_RD(sc, shmem_base +
11254 offsetof(struct shmem_region,
11255 dev_info.port_hw_config[port].
11256 xgxs_config2_rx[i << 1]));
11259 phy->rx_preemphasis[i << 1] = ((rx >> 16) & 0xffff);
11260 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
11262 phy->tx_preemphasis[i << 1] = ((tx >> 16) & 0xffff);
11263 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
11267 static uint32_t elink_get_ext_phy_config(struct bnx2x_softc *sc,
11268 uint32_t shmem_base, uint8_t phy_index,
11271 uint32_t ext_phy_config = 0;
11272 switch (phy_index) {
11273 case ELINK_EXT_PHY1:
11274 ext_phy_config = REG_RD(sc, shmem_base +
11275 offsetof(struct shmem_region,
11276 dev_info.port_hw_config[port].
11277 external_phy_config));
11279 case ELINK_EXT_PHY2:
11280 ext_phy_config = REG_RD(sc, shmem_base +
11281 offsetof(struct shmem_region,
11282 dev_info.port_hw_config[port].
11283 external_phy_config2));
11286 PMD_DRV_LOG(DEBUG, "Invalid phy_index %d", phy_index);
11287 return ELINK_STATUS_ERROR;
11290 return ext_phy_config;
11293 static elink_status_t elink_populate_int_phy(struct bnx2x_softc *sc,
11294 uint32_t shmem_base, uint8_t port,
11295 struct elink_phy *phy)
11298 __rte_unused uint32_t chip_id;
11299 uint32_t switch_cfg = (REG_RD(sc, shmem_base +
11300 offsetof(struct shmem_region,
11302 port_feature_config[port].
11304 PORT_FEATURE_CONNECTED_SWITCH_MASK);
11306 (REG_RD(sc, MISC_REG_CHIP_NUM) << 16) |
11307 ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12);
11309 PMD_DRV_LOG(DEBUG, ":chip_id = 0x%x", chip_id);
11310 if (USES_WARPCORE(sc)) {
11311 uint32_t serdes_net_if;
11312 phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR);
11313 *phy = phy_warpcore;
11314 if (REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)
11315 phy->flags |= ELINK_FLAGS_4_PORT_MODE;
11317 phy->flags &= ~ELINK_FLAGS_4_PORT_MODE;
11318 /* Check Dual mode */
11319 serdes_net_if = (REG_RD(sc, shmem_base +
11320 offsetof(struct shmem_region,
11321 dev_info.port_hw_config[port].
11323 PORT_HW_CFG_NET_SERDES_IF_MASK);
11324 /* Set the appropriate supported and flags indications per
11325 * interface type of the chip
11327 switch (serdes_net_if) {
11328 case PORT_HW_CFG_NET_SERDES_IF_SGMII:
11329 phy->supported &= (ELINK_SUPPORTED_10baseT_Half |
11330 ELINK_SUPPORTED_10baseT_Full |
11331 ELINK_SUPPORTED_100baseT_Half |
11332 ELINK_SUPPORTED_100baseT_Full |
11333 ELINK_SUPPORTED_1000baseT_Full |
11334 ELINK_SUPPORTED_FIBRE |
11335 ELINK_SUPPORTED_Autoneg |
11336 ELINK_SUPPORTED_Pause |
11337 ELINK_SUPPORTED_Asym_Pause);
11338 phy->media_type = ELINK_ETH_PHY_BASE_T;
11340 case PORT_HW_CFG_NET_SERDES_IF_XFI:
11341 phy->supported &= (ELINK_SUPPORTED_1000baseT_Full |
11342 ELINK_SUPPORTED_10000baseT_Full |
11343 ELINK_SUPPORTED_FIBRE |
11344 ELINK_SUPPORTED_Pause |
11345 ELINK_SUPPORTED_Asym_Pause);
11346 phy->media_type = ELINK_ETH_PHY_XFP_FIBER;
11348 case PORT_HW_CFG_NET_SERDES_IF_SFI:
11349 phy->supported &= (ELINK_SUPPORTED_1000baseT_Full |
11350 ELINK_SUPPORTED_10000baseT_Full |
11351 ELINK_SUPPORTED_FIBRE |
11352 ELINK_SUPPORTED_Pause |
11353 ELINK_SUPPORTED_Asym_Pause);
11354 phy->media_type = ELINK_ETH_PHY_SFPP_10G_FIBER;
11356 case PORT_HW_CFG_NET_SERDES_IF_KR:
11357 phy->media_type = ELINK_ETH_PHY_KR;
11358 phy->supported &= (ELINK_SUPPORTED_1000baseT_Full |
11359 ELINK_SUPPORTED_10000baseT_Full |
11360 ELINK_SUPPORTED_FIBRE |
11361 ELINK_SUPPORTED_Autoneg |
11362 ELINK_SUPPORTED_Pause |
11363 ELINK_SUPPORTED_Asym_Pause);
11365 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
11366 phy->media_type = ELINK_ETH_PHY_KR;
11367 phy->flags |= ELINK_FLAGS_WC_DUAL_MODE;
11368 phy->supported &= (ELINK_SUPPORTED_20000baseMLD2_Full |
11369 ELINK_SUPPORTED_FIBRE |
11370 ELINK_SUPPORTED_Pause |
11371 ELINK_SUPPORTED_Asym_Pause);
11373 case PORT_HW_CFG_NET_SERDES_IF_KR2:
11374 phy->media_type = ELINK_ETH_PHY_KR;
11375 phy->flags |= ELINK_FLAGS_WC_DUAL_MODE;
11376 phy->supported &= (ELINK_SUPPORTED_20000baseKR2_Full |
11377 ELINK_SUPPORTED_10000baseT_Full |
11378 ELINK_SUPPORTED_1000baseT_Full |
11379 ELINK_SUPPORTED_Autoneg |
11380 ELINK_SUPPORTED_FIBRE |
11381 ELINK_SUPPORTED_Pause |
11382 ELINK_SUPPORTED_Asym_Pause);
11383 phy->flags &= ~ELINK_FLAGS_TX_ERROR_CHECK;
11386 PMD_DRV_LOG(DEBUG, "Unknown WC interface type 0x%x",
11391 /* Enable MDC/MDIO work-around for E3 A0 since free running MDC
11392 * was not set as expected. For B0, ECO will be enabled so there
11393 * won't be an issue there
11395 if (CHIP_REV(sc) == CHIP_REV_Ax)
11396 phy->flags |= ELINK_FLAGS_MDC_MDIO_WA;
11398 phy->flags |= ELINK_FLAGS_MDC_MDIO_WA_B0;
11400 switch (switch_cfg) {
11401 case ELINK_SWITCH_CFG_1G:
11402 phy_addr = REG_RD(sc,
11403 NIG_REG_SERDES0_CTRL_PHY_ADDR +
11407 case ELINK_SWITCH_CFG_10G:
11408 phy_addr = REG_RD(sc,
11409 NIG_REG_XGXS0_CTRL_PHY_ADDR +
11414 PMD_DRV_LOG(DEBUG, "Invalid switch_cfg");
11415 return ELINK_STATUS_ERROR;
11418 phy->addr = (uint8_t) phy_addr;
11419 phy->mdio_ctrl = elink_get_emac_base(sc,
11420 SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
11422 if (CHIP_IS_E2(sc))
11423 phy->def_md_devad = ELINK_E2_DEFAULT_PHY_DEV_ADDR;
11425 phy->def_md_devad = ELINK_DEFAULT_PHY_DEV_ADDR;
11427 PMD_DRV_LOG(DEBUG, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x",
11428 port, phy->addr, phy->mdio_ctrl);
11430 elink_populate_preemphasis(sc, shmem_base, phy, port, ELINK_INT_PHY);
11431 return ELINK_STATUS_OK;
11434 static elink_status_t elink_populate_ext_phy(struct bnx2x_softc *sc,
11436 uint32_t shmem_base,
11437 uint32_t shmem2_base,
11439 struct elink_phy *phy)
11441 uint32_t ext_phy_config, phy_type, config2;
11442 uint32_t mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
11443 ext_phy_config = elink_get_ext_phy_config(sc, shmem_base,
11445 phy_type = ELINK_XGXS_EXT_PHY_TYPE(ext_phy_config);
11446 /* Select the phy type */
11447 switch (phy_type) {
11448 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073:
11449 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
11452 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8705:
11455 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8706:
11458 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726:
11459 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11462 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727_NOC:
11463 /* BNX2X8727_NOC => BNX2X8727 no over current */
11464 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11466 phy->flags |= ELINK_FLAGS_NOC;
11468 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722:
11469 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727:
11470 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11473 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8481:
11476 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823:
11479 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833:
11482 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834:
11485 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54616:
11486 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE:
11487 *phy = phy_54618se;
11488 if (phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE)
11489 phy->flags |= ELINK_FLAGS_EEE;
11491 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
11494 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
11496 return ELINK_STATUS_ERROR;
11499 /* In case external PHY wasn't found */
11500 if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
11501 (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
11502 return ELINK_STATUS_ERROR;
11503 return ELINK_STATUS_OK;
11506 phy->addr = ELINK_XGXS_EXT_PHY_ADDR(ext_phy_config);
11507 elink_populate_preemphasis(sc, shmem_base, phy, port, phy_index);
11509 /* The shmem address of the phy version is located on different
11510 * structures. In case this structure is too old, do not set
11513 config2 = REG_RD(sc, shmem_base + offsetof(struct shmem_region,
11514 dev_info.shared_hw_config.
11516 if (phy_index == ELINK_EXT_PHY1) {
11517 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
11519 ext_phy_fw_version);
11521 /* Check specific mdc mdio settings */
11522 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
11523 mdc_mdio_access = config2 &
11524 SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
11526 uint32_t size = REG_RD(sc, shmem2_base);
11528 if (size > offsetof(struct shmem2_region, ext_phy_fw_version2)) {
11529 phy->ver_addr = shmem2_base +
11530 offsetof(struct shmem2_region,
11531 ext_phy_fw_version2[port]);
11533 /* Check specific mdc mdio settings */
11534 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
11535 mdc_mdio_access = (config2 &
11536 SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
11537 >> (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
11538 SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
11540 phy->mdio_ctrl = elink_get_emac_base(sc, mdc_mdio_access, port);
11542 if (((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||
11543 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) &&
11545 /* Remove 100Mb link supported for BNX2X84833/4 when phy fw
11546 * version lower than or equal to 1.39
11548 uint32_t raw_ver = REG_RD(sc, phy->ver_addr);
11549 if (((raw_ver & 0x7F) <= 39) && (((raw_ver & 0xF80) >> 7) <= 1))
11550 phy->supported &= ~(ELINK_SUPPORTED_100baseT_Half |
11551 ELINK_SUPPORTED_100baseT_Full);
11554 PMD_DRV_LOG(DEBUG, "phy_type 0x%x port %d found in index %d",
11555 phy_type, port, phy_index);
11556 PMD_DRV_LOG(DEBUG, " addr=0x%x, mdio_ctl=0x%x",
11557 phy->addr, phy->mdio_ctrl);
11558 return ELINK_STATUS_OK;
11561 static elink_status_t elink_populate_phy(struct bnx2x_softc *sc,
11562 uint8_t phy_index, uint32_t shmem_base,
11563 uint32_t shmem2_base, uint8_t port,
11564 struct elink_phy *phy)
11566 elink_status_t status = ELINK_STATUS_OK;
11567 phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
11568 if (phy_index == ELINK_INT_PHY)
11569 return elink_populate_int_phy(sc, shmem_base, port, phy);
11570 status = elink_populate_ext_phy(sc, phy_index, shmem_base, shmem2_base,
11575 static void elink_phy_def_cfg(struct elink_params *params,
11576 struct elink_phy *phy, uint8_t phy_index)
11578 struct bnx2x_softc *sc = params->sc;
11579 uint32_t link_config;
11580 /* Populate the default phy configuration for MF mode */
11581 if (phy_index == ELINK_EXT_PHY2) {
11582 link_config = REG_RD(sc, params->shmem_base +
11583 offsetof(struct shmem_region,
11584 dev_info.port_feature_config
11585 [params->port].link_config2));
11586 phy->speed_cap_mask =
11588 params->shmem_base + offsetof(struct shmem_region,
11589 dev_info.port_hw_config
11591 speed_capability_mask2));
11593 link_config = REG_RD(sc, params->shmem_base +
11594 offsetof(struct shmem_region,
11595 dev_info.port_feature_config
11596 [params->port].link_config));
11597 phy->speed_cap_mask =
11599 params->shmem_base + offsetof(struct shmem_region,
11600 dev_info.port_hw_config
11602 speed_capability_mask));
11606 "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x",
11607 phy_index, link_config, phy->speed_cap_mask);
11609 phy->req_duplex = DUPLEX_FULL;
11610 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
11611 case PORT_FEATURE_LINK_SPEED_10M_HALF:
11612 phy->req_duplex = DUPLEX_HALF;
11613 case PORT_FEATURE_LINK_SPEED_10M_FULL:
11614 phy->req_line_speed = ELINK_SPEED_10;
11616 case PORT_FEATURE_LINK_SPEED_100M_HALF:
11617 phy->req_duplex = DUPLEX_HALF;
11618 case PORT_FEATURE_LINK_SPEED_100M_FULL:
11619 phy->req_line_speed = ELINK_SPEED_100;
11621 case PORT_FEATURE_LINK_SPEED_1G:
11622 phy->req_line_speed = ELINK_SPEED_1000;
11624 case PORT_FEATURE_LINK_SPEED_2_5G:
11625 phy->req_line_speed = ELINK_SPEED_2500;
11627 case PORT_FEATURE_LINK_SPEED_10G_CX4:
11628 phy->req_line_speed = ELINK_SPEED_10000;
11631 phy->req_line_speed = ELINK_SPEED_AUTO_NEG;
11635 switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) {
11636 case PORT_FEATURE_FLOW_CONTROL_AUTO:
11637 phy->req_flow_ctrl = ELINK_FLOW_CTRL_AUTO;
11639 case PORT_FEATURE_FLOW_CONTROL_TX:
11640 phy->req_flow_ctrl = ELINK_FLOW_CTRL_TX;
11642 case PORT_FEATURE_FLOW_CONTROL_RX:
11643 phy->req_flow_ctrl = ELINK_FLOW_CTRL_RX;
11645 case PORT_FEATURE_FLOW_CONTROL_BOTH:
11646 phy->req_flow_ctrl = ELINK_FLOW_CTRL_BOTH;
11649 phy->req_flow_ctrl = ELINK_FLOW_CTRL_NONE;
11654 uint32_t elink_phy_selection(struct elink_params *params)
11656 uint32_t phy_config_swapped, prio_cfg;
11657 uint32_t return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
11659 phy_config_swapped = params->multi_phy_config &
11660 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
11662 prio_cfg = params->multi_phy_config & PORT_HW_CFG_PHY_SELECTION_MASK;
11664 if (phy_config_swapped) {
11665 switch (prio_cfg) {
11666 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
11668 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
11670 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
11672 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
11674 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
11675 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
11677 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
11678 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
11682 return_cfg = prio_cfg;
11687 elink_status_t elink_phy_probe(struct elink_params * params)
11689 uint8_t phy_index, actual_phy_idx;
11690 uint32_t phy_config_swapped, sync_offset, media_types;
11691 struct bnx2x_softc *sc = params->sc;
11692 struct elink_phy *phy;
11693 params->num_phys = 0;
11694 PMD_DRV_LOG(DEBUG, "Begin phy probe");
11695 #ifdef ELINK_INCLUDE_EMUL
11696 if (CHIP_REV_IS_EMUL(sc))
11697 return ELINK_STATUS_OK;
11699 phy_config_swapped = params->multi_phy_config &
11700 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
11702 for (phy_index = ELINK_INT_PHY; phy_index < ELINK_MAX_PHYS; phy_index++) {
11703 actual_phy_idx = phy_index;
11704 if (phy_config_swapped) {
11705 if (phy_index == ELINK_EXT_PHY1)
11706 actual_phy_idx = ELINK_EXT_PHY2;
11707 else if (phy_index == ELINK_EXT_PHY2)
11708 actual_phy_idx = ELINK_EXT_PHY1;
11710 PMD_DRV_LOG(DEBUG, "phy_config_swapped %x, phy_index %x,"
11711 " actual_phy_idx %x", phy_config_swapped,
11712 phy_index, actual_phy_idx);
11713 phy = ¶ms->phy[actual_phy_idx];
11714 if (elink_populate_phy(sc, phy_index, params->shmem_base,
11715 params->shmem2_base, params->port,
11716 phy) != ELINK_STATUS_OK) {
11717 params->num_phys = 0;
11718 PMD_DRV_LOG(DEBUG, "phy probe failed in phy index %d",
11720 for (phy_index = ELINK_INT_PHY;
11721 phy_index < ELINK_MAX_PHYS; phy_index++)
11723 return ELINK_STATUS_ERROR;
11725 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
11728 if (params->feature_config_flags &
11729 ELINK_FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET)
11730 phy->flags &= ~ELINK_FLAGS_TX_ERROR_CHECK;
11732 if (!(params->feature_config_flags &
11733 ELINK_FEATURE_CONFIG_MT_SUPPORT))
11734 phy->flags |= ELINK_FLAGS_MDC_MDIO_WA_G;
11736 sync_offset = params->shmem_base +
11737 offsetof(struct shmem_region,
11738 dev_info.port_hw_config[params->port].media_type);
11739 media_types = REG_RD(sc, sync_offset);
11741 /* Update media type for non-PMF sync only for the first time
11742 * In case the media type changes afterwards, it will be updated
11743 * using the update_status function
11745 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
11746 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
11747 actual_phy_idx))) == 0) {
11748 media_types |= ((phy->media_type &
11749 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
11750 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
11753 REG_WR(sc, sync_offset, media_types);
11755 elink_phy_def_cfg(params, phy, phy_index);
11756 params->num_phys++;
11759 PMD_DRV_LOG(DEBUG, "End phy probe. #phys found %x", params->num_phys);
11760 return ELINK_STATUS_OK;
11763 #ifdef ELINK_INCLUDE_EMUL
11764 static elink_status_t elink_init_e3_emul_mac(struct elink_params *params,
11765 struct elink_vars *vars)
11767 struct bnx2x_softc *sc = params->sc;
11768 vars->line_speed = params->req_line_speed[0];
11769 /* In case link speed is auto, set speed the highest as possible */
11770 if (params->req_line_speed[0] == ELINK_SPEED_AUTO_NEG) {
11771 if (params->feature_config_flags &
11772 ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC)
11773 vars->line_speed = ELINK_SPEED_2500;
11774 else if (elink_is_4_port_mode(sc))
11775 vars->line_speed = ELINK_SPEED_10000;
11777 vars->line_speed = ELINK_SPEED_20000;
11779 if (vars->line_speed < ELINK_SPEED_10000) {
11780 if ((params->feature_config_flags &
11781 ELINK_FEATURE_CONFIG_EMUL_DISABLE_UMAC)) {
11782 PMD_DRV_LOG(DEBUG, "Invalid line speed %d while UMAC is"
11783 " disabled!", params->req_line_speed[0]);
11784 return ELINK_STATUS_ERROR;
11786 switch (vars->line_speed) {
11787 case ELINK_SPEED_10:
11788 vars->link_status = ELINK_LINK_10TFD;
11790 case ELINK_SPEED_100:
11791 vars->link_status = ELINK_LINK_100TXFD;
11793 case ELINK_SPEED_1000:
11794 vars->link_status = ELINK_LINK_1000TFD;
11796 case ELINK_SPEED_2500:
11797 vars->link_status = ELINK_LINK_2500TFD;
11800 PMD_DRV_LOG(DEBUG, "Invalid line speed %d for UMAC",
11802 return ELINK_STATUS_ERROR;
11804 vars->link_status |= LINK_STATUS_LINK_UP;
11806 if (params->loopback_mode == ELINK_LOOPBACK_UMAC)
11807 elink_umac_enable(params, vars, 1);
11809 elink_umac_enable(params, vars, 0);
11811 /* Link speed >= 10000 requires XMAC enabled */
11812 if (params->feature_config_flags &
11813 ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC) {
11814 PMD_DRV_LOG(DEBUG, "Invalid line speed %d while XMAC is"
11815 " disabled!", params->req_line_speed[0]);
11816 return ELINK_STATUS_ERROR;
11818 /* Check link speed */
11819 switch (vars->line_speed) {
11820 case ELINK_SPEED_10000:
11821 vars->link_status = ELINK_LINK_10GTFD;
11823 case ELINK_SPEED_20000:
11824 vars->link_status = ELINK_LINK_20GTFD;
11827 PMD_DRV_LOG(DEBUG, "Invalid line speed %d for XMAC",
11829 return ELINK_STATUS_ERROR;
11831 vars->link_status |= LINK_STATUS_LINK_UP;
11832 if (params->loopback_mode == ELINK_LOOPBACK_XMAC)
11833 elink_xmac_enable(params, vars, 1);
11835 elink_xmac_enable(params, vars, 0);
11837 return ELINK_STATUS_OK;
11840 static elink_status_t elink_init_emul(struct elink_params *params,
11841 struct elink_vars *vars)
11843 struct bnx2x_softc *sc = params->sc;
11844 if (CHIP_IS_E3(sc)) {
11845 if (elink_init_e3_emul_mac(params, vars) != ELINK_STATUS_OK)
11846 return ELINK_STATUS_ERROR;
11848 if (params->feature_config_flags &
11849 ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC) {
11850 vars->line_speed = ELINK_SPEED_1000;
11851 vars->link_status = (LINK_STATUS_LINK_UP |
11852 ELINK_LINK_1000XFD);
11853 if (params->loopback_mode == ELINK_LOOPBACK_EMAC)
11854 elink_emac_enable(params, vars, 1);
11856 elink_emac_enable(params, vars, 0);
11858 vars->line_speed = ELINK_SPEED_10000;
11859 vars->link_status = (LINK_STATUS_LINK_UP |
11860 ELINK_LINK_10GTFD);
11861 if (params->loopback_mode == ELINK_LOOPBACK_BMAC)
11862 elink_bmac_enable(params, vars, 1, 1);
11864 elink_bmac_enable(params, vars, 0, 1);
11868 vars->duplex = DUPLEX_FULL;
11869 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
11871 if (CHIP_IS_E1x(sc))
11872 elink_pbf_update(params, vars->flow_ctrl, vars->line_speed);
11873 /* Disable drain */
11874 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
11876 /* update shared memory */
11877 elink_update_mng(params, vars->link_status);
11878 return ELINK_STATUS_OK;
11881 #ifdef ELINK_INCLUDE_FPGA
11882 static elink_status_t elink_init_fpga(struct elink_params *params,
11883 struct elink_vars *vars)
11885 /* Enable on E1.5 FPGA */
11886 struct bnx2x_softc *sc = params->sc;
11887 vars->duplex = DUPLEX_FULL;
11888 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
11889 vars->flow_ctrl = (ELINK_FLOW_CTRL_TX | ELINK_FLOW_CTRL_RX);
11890 vars->link_status |= (LINK_STATUS_TX_FLOW_CONTROL_ENABLED |
11891 LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
11892 if (CHIP_IS_E3(sc)) {
11893 vars->line_speed = params->req_line_speed[0];
11894 switch (vars->line_speed) {
11895 case ELINK_SPEED_AUTO_NEG:
11896 vars->line_speed = ELINK_SPEED_2500;
11897 case ELINK_SPEED_2500:
11898 vars->link_status = ELINK_LINK_2500TFD;
11900 case ELINK_SPEED_1000:
11901 vars->link_status = ELINK_LINK_1000XFD;
11903 case ELINK_SPEED_100:
11904 vars->link_status = ELINK_LINK_100TXFD;
11906 case ELINK_SPEED_10:
11907 vars->link_status = ELINK_LINK_10TFD;
11910 PMD_DRV_LOG(DEBUG, "Invalid link speed %d",
11911 params->req_line_speed[0]);
11912 return ELINK_STATUS_ERROR;
11914 vars->link_status |= LINK_STATUS_LINK_UP;
11915 if (params->loopback_mode == ELINK_LOOPBACK_UMAC)
11916 elink_umac_enable(params, vars, 1);
11918 elink_umac_enable(params, vars, 0);
11920 vars->line_speed = ELINK_SPEED_10000;
11921 vars->link_status = (LINK_STATUS_LINK_UP | ELINK_LINK_10GTFD);
11922 if (params->loopback_mode == ELINK_LOOPBACK_EMAC)
11923 elink_emac_enable(params, vars, 1);
11925 elink_emac_enable(params, vars, 0);
11929 if (CHIP_IS_E1x(sc))
11930 elink_pbf_update(params, vars->flow_ctrl, vars->line_speed);
11931 /* Disable drain */
11932 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
11934 /* Update shared memory */
11935 elink_update_mng(params, vars->link_status);
11936 return ELINK_STATUS_OK;
11939 static void elink_init_bmac_loopback(struct elink_params *params,
11940 struct elink_vars *vars)
11942 struct bnx2x_softc *sc = params->sc;
11944 vars->line_speed = ELINK_SPEED_10000;
11945 vars->duplex = DUPLEX_FULL;
11946 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
11947 vars->mac_type = ELINK_MAC_TYPE_BMAC;
11949 vars->phy_flags = PHY_XGXS_FLAG;
11951 elink_xgxs_deassert(params);
11953 /* Set bmac loopback */
11954 elink_bmac_enable(params, vars, 1, 1);
11956 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
11959 static void elink_init_emac_loopback(struct elink_params *params,
11960 struct elink_vars *vars)
11962 struct bnx2x_softc *sc = params->sc;
11964 vars->line_speed = ELINK_SPEED_1000;
11965 vars->duplex = DUPLEX_FULL;
11966 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
11967 vars->mac_type = ELINK_MAC_TYPE_EMAC;
11969 vars->phy_flags = PHY_XGXS_FLAG;
11971 elink_xgxs_deassert(params);
11972 /* Set bmac loopback */
11973 elink_emac_enable(params, vars, 1);
11974 elink_emac_program(params, vars);
11975 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
11978 static void elink_init_xmac_loopback(struct elink_params *params,
11979 struct elink_vars *vars)
11981 struct bnx2x_softc *sc = params->sc;
11983 if (!params->req_line_speed[0])
11984 vars->line_speed = ELINK_SPEED_10000;
11986 vars->line_speed = params->req_line_speed[0];
11987 vars->duplex = DUPLEX_FULL;
11988 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
11989 vars->mac_type = ELINK_MAC_TYPE_XMAC;
11990 vars->phy_flags = PHY_XGXS_FLAG;
11991 /* Set WC to loopback mode since link is required to provide clock
11992 * to the XMAC in 20G mode
11994 elink_set_aer_mmd(params, ¶ms->phy[0]);
11995 elink_warpcore_reset_lane(sc, ¶ms->phy[0], 0);
11996 params->phy[ELINK_INT_PHY].config_loopback(¶ms->phy[ELINK_INT_PHY],
11999 elink_xmac_enable(params, vars, 1);
12000 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
12003 static void elink_init_umac_loopback(struct elink_params *params,
12004 struct elink_vars *vars)
12006 struct bnx2x_softc *sc = params->sc;
12008 vars->line_speed = ELINK_SPEED_1000;
12009 vars->duplex = DUPLEX_FULL;
12010 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
12011 vars->mac_type = ELINK_MAC_TYPE_UMAC;
12012 vars->phy_flags = PHY_XGXS_FLAG;
12013 elink_umac_enable(params, vars, 1);
12015 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
12018 static void elink_init_xgxs_loopback(struct elink_params *params,
12019 struct elink_vars *vars)
12021 struct bnx2x_softc *sc = params->sc;
12022 struct elink_phy *int_phy = ¶ms->phy[ELINK_INT_PHY];
12024 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
12025 vars->duplex = DUPLEX_FULL;
12026 if (params->req_line_speed[0] == ELINK_SPEED_1000)
12027 vars->line_speed = ELINK_SPEED_1000;
12028 else if ((params->req_line_speed[0] == ELINK_SPEED_20000) ||
12029 (int_phy->flags & ELINK_FLAGS_WC_DUAL_MODE))
12030 vars->line_speed = ELINK_SPEED_20000;
12032 vars->line_speed = ELINK_SPEED_10000;
12034 if (!USES_WARPCORE(sc))
12035 elink_xgxs_deassert(params);
12036 elink_link_initialize(params, vars);
12038 if (params->req_line_speed[0] == ELINK_SPEED_1000) {
12039 if (USES_WARPCORE(sc))
12040 elink_umac_enable(params, vars, 0);
12042 elink_emac_program(params, vars);
12043 elink_emac_enable(params, vars, 0);
12046 if (USES_WARPCORE(sc))
12047 elink_xmac_enable(params, vars, 0);
12049 elink_bmac_enable(params, vars, 0, 1);
12052 if (params->loopback_mode == ELINK_LOOPBACK_XGXS) {
12053 /* Set 10G XGXS loopback */
12054 int_phy->config_loopback(int_phy, params);
12056 /* Set external phy loopback */
12058 for (phy_index = ELINK_EXT_PHY1;
12059 phy_index < params->num_phys; phy_index++)
12060 if (params->phy[phy_index].config_loopback)
12061 params->phy[phy_index].config_loopback(¶ms->
12066 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
12068 elink_set_led(params, vars, ELINK_LED_MODE_OPER, vars->line_speed);
12071 void elink_set_rx_filter(struct elink_params *params, uint8_t en)
12073 struct bnx2x_softc *sc = params->sc;
12074 uint8_t val = en * 0x1F;
12076 /* Open / close the gate between the NIG and the BRB */
12077 if (!CHIP_IS_E1x(sc))
12079 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + params->port * 4, val);
12081 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port * 4, en * 0x3);
12083 REG_WR(sc, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP :
12084 NIG_REG_LLH0_BRB1_NOT_MCP), en);
12087 static elink_status_t elink_avoid_link_flap(struct elink_params *params,
12088 struct elink_vars *vars)
12091 uint32_t dont_clear_stat, lfa_sts;
12092 struct bnx2x_softc *sc = params->sc;
12094 /* Sync the link parameters */
12095 elink_link_status_update(params, vars);
12098 * The module verification was already done by previous link owner,
12099 * so this call is meant only to get warning message
12102 for (phy_idx = ELINK_INT_PHY; phy_idx < params->num_phys; phy_idx++) {
12103 struct elink_phy *phy = ¶ms->phy[phy_idx];
12104 if (phy->phy_specific_func) {
12105 PMD_DRV_LOG(DEBUG, "Calling PHY specific func");
12106 phy->phy_specific_func(phy, params, ELINK_PHY_INIT);
12108 if ((phy->media_type == ELINK_ETH_PHY_SFPP_10G_FIBER) ||
12109 (phy->media_type == ELINK_ETH_PHY_SFP_1G_FIBER) ||
12110 (phy->media_type == ELINK_ETH_PHY_DA_TWINAX))
12111 elink_verify_sfp_module(phy, params);
12113 lfa_sts = REG_RD(sc, params->lfa_base +
12114 offsetof(struct shmem_lfa, lfa_sts));
12116 dont_clear_stat = lfa_sts & SHMEM_LFA_DONT_CLEAR_STAT;
12118 /* Re-enable the NIG/MAC */
12119 if (CHIP_IS_E3(sc)) {
12120 if (!dont_clear_stat) {
12121 REG_WR(sc, GRCBASE_MISC +
12122 MISC_REGISTERS_RESET_REG_2_CLEAR,
12123 (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<
12125 REG_WR(sc, GRCBASE_MISC +
12126 MISC_REGISTERS_RESET_REG_2_SET,
12127 (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<
12130 if (vars->line_speed < ELINK_SPEED_10000)
12131 elink_umac_enable(params, vars, 0);
12133 elink_xmac_enable(params, vars, 0);
12135 if (vars->line_speed < ELINK_SPEED_10000)
12136 elink_emac_enable(params, vars, 0);
12138 elink_bmac_enable(params, vars, 0, !dont_clear_stat);
12141 /* Increment LFA count */
12142 lfa_sts = ((lfa_sts & ~LINK_FLAP_AVOIDANCE_COUNT_MASK) |
12143 (((((lfa_sts & LINK_FLAP_AVOIDANCE_COUNT_MASK) >>
12144 LINK_FLAP_AVOIDANCE_COUNT_OFFSET) + 1) & 0xff)
12145 << LINK_FLAP_AVOIDANCE_COUNT_OFFSET));
12146 /* Clear link flap reason */
12147 lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;
12149 REG_WR(sc, params->lfa_base +
12150 offsetof(struct shmem_lfa, lfa_sts), lfa_sts);
12152 /* Disable NIG DRAIN */
12153 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
12155 /* Enable interrupts */
12156 elink_link_int_enable(params);
12157 return ELINK_STATUS_OK;
12160 static void elink_cannot_avoid_link_flap(struct elink_params *params,
12161 struct elink_vars *vars,
12164 uint32_t lfa_sts, cfg_idx, tmp_val;
12165 struct bnx2x_softc *sc = params->sc;
12167 elink_link_reset(params, vars, 1);
12169 if (!params->lfa_base)
12171 /* Store the new link parameters */
12172 REG_WR(sc, params->lfa_base +
12173 offsetof(struct shmem_lfa, req_duplex),
12174 params->req_duplex[0] | (params->req_duplex[1] << 16));
12176 REG_WR(sc, params->lfa_base +
12177 offsetof(struct shmem_lfa, req_flow_ctrl),
12178 params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16));
12180 REG_WR(sc, params->lfa_base +
12181 offsetof(struct shmem_lfa, req_line_speed),
12182 params->req_line_speed[0] | (params->req_line_speed[1] << 16));
12184 for (cfg_idx = 0; cfg_idx < SHMEM_LINK_CONFIG_SIZE; cfg_idx++) {
12185 REG_WR(sc, params->lfa_base +
12186 offsetof(struct shmem_lfa,
12187 speed_cap_mask[cfg_idx]),
12188 params->speed_cap_mask[cfg_idx]);
12191 tmp_val = REG_RD(sc, params->lfa_base +
12192 offsetof(struct shmem_lfa, additional_config));
12193 tmp_val &= ~REQ_FC_AUTO_ADV_MASK;
12194 tmp_val |= params->req_fc_auto_adv;
12196 REG_WR(sc, params->lfa_base +
12197 offsetof(struct shmem_lfa, additional_config), tmp_val);
12199 lfa_sts = REG_RD(sc, params->lfa_base +
12200 offsetof(struct shmem_lfa, lfa_sts));
12202 /* Clear the "Don't Clear Statistics" bit, and set reason */
12203 lfa_sts &= ~SHMEM_LFA_DONT_CLEAR_STAT;
12205 /* Set link flap reason */
12206 lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;
12207 lfa_sts |= ((lfa_status & LFA_LINK_FLAP_REASON_MASK) <<
12208 LFA_LINK_FLAP_REASON_OFFSET);
12210 /* Increment link flap counter */
12211 lfa_sts = ((lfa_sts & ~LINK_FLAP_COUNT_MASK) |
12212 (((((lfa_sts & LINK_FLAP_COUNT_MASK) >>
12213 LINK_FLAP_COUNT_OFFSET) + 1) & 0xff)
12214 << LINK_FLAP_COUNT_OFFSET));
12215 REG_WR(sc, params->lfa_base +
12216 offsetof(struct shmem_lfa, lfa_sts), lfa_sts);
12217 /* Proceed with regular link initialization */
12220 elink_status_t elink_phy_init(struct elink_params *params,
12221 struct elink_vars *vars)
12224 struct bnx2x_softc *sc = params->sc;
12225 PMD_DRV_LOG(DEBUG, "Phy Initialization started");
12226 PMD_DRV_LOG(DEBUG, "(1) req_speed %d, req_flowctrl %d",
12227 params->req_line_speed[0], params->req_flow_ctrl[0]);
12228 PMD_DRV_LOG(DEBUG, "(2) req_speed %d, req_flowctrl %d",
12229 params->req_line_speed[1], params->req_flow_ctrl[1]);
12230 PMD_DRV_LOG(DEBUG, "req_adv_flow_ctrl 0x%x", params->req_fc_auto_adv);
12231 vars->link_status = 0;
12232 vars->phy_link_up = 0;
12234 vars->line_speed = 0;
12235 vars->duplex = DUPLEX_FULL;
12236 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
12237 vars->mac_type = ELINK_MAC_TYPE_NONE;
12238 vars->phy_flags = 0;
12239 vars->check_kr2_recovery_cnt = 0;
12240 params->link_flags = ELINK_PHY_INITIALIZED;
12241 /* Driver opens NIG-BRB filters */
12242 elink_set_rx_filter(params, 1);
12243 /* Check if link flap can be avoided */
12244 lfa_status = elink_check_lfa(params);
12246 if (lfa_status == 0) {
12247 PMD_DRV_LOG(DEBUG, "Link Flap Avoidance in progress");
12248 return elink_avoid_link_flap(params, vars);
12251 PMD_DRV_LOG(DEBUG, "Cannot avoid link flap lfa_sta=0x%x", lfa_status);
12252 elink_cannot_avoid_link_flap(params, vars, lfa_status);
12254 /* Disable attentions */
12255 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + params->port * 4,
12256 (ELINK_NIG_MASK_XGXS0_LINK_STATUS |
12257 ELINK_NIG_MASK_XGXS0_LINK10G |
12258 ELINK_NIG_MASK_SERDES0_LINK_STATUS |
12259 ELINK_NIG_MASK_MI_INT));
12260 #ifdef ELINK_INCLUDE_EMUL
12261 if (!(params->feature_config_flags &
12262 ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC))
12265 elink_emac_init(params);
12267 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
12268 vars->link_status |= LINK_STATUS_PFC_ENABLED;
12270 if ((params->num_phys == 0) && !CHIP_REV_IS_SLOW(sc)) {
12271 PMD_DRV_LOG(DEBUG, "No phy found for initialization !!");
12272 return ELINK_STATUS_ERROR;
12274 set_phy_vars(params, vars);
12276 PMD_DRV_LOG(DEBUG, "Num of phys on board: %d", params->num_phys);
12277 #ifdef ELINK_INCLUDE_FPGA
12278 if (CHIP_REV_IS_FPGA(sc)) {
12279 return elink_init_fpga(params, vars);
12282 #ifdef ELINK_INCLUDE_EMUL
12283 if (CHIP_REV_IS_EMUL(sc)) {
12284 return elink_init_emul(params, vars);
12287 switch (params->loopback_mode) {
12288 case ELINK_LOOPBACK_BMAC:
12289 elink_init_bmac_loopback(params, vars);
12291 case ELINK_LOOPBACK_EMAC:
12292 elink_init_emac_loopback(params, vars);
12294 case ELINK_LOOPBACK_XMAC:
12295 elink_init_xmac_loopback(params, vars);
12297 case ELINK_LOOPBACK_UMAC:
12298 elink_init_umac_loopback(params, vars);
12300 case ELINK_LOOPBACK_XGXS:
12301 case ELINK_LOOPBACK_EXT_PHY:
12302 elink_init_xgxs_loopback(params, vars);
12305 if (!CHIP_IS_E3(sc)) {
12306 if (params->switch_cfg == ELINK_SWITCH_CFG_10G)
12307 elink_xgxs_deassert(params);
12309 elink_serdes_deassert(sc, params->port);
12311 elink_link_initialize(params, vars);
12313 elink_link_int_enable(params);
12316 elink_update_mng(params, vars->link_status);
12318 elink_update_mng_eee(params, vars->eee_status);
12319 return ELINK_STATUS_OK;
12322 static elink_status_t elink_link_reset(struct elink_params *params,
12323 struct elink_vars *vars,
12324 uint8_t reset_ext_phy)
12326 struct bnx2x_softc *sc = params->sc;
12327 uint8_t phy_index, port = params->port, clear_latch_ind = 0;
12328 PMD_DRV_LOG(DEBUG, "Resetting the link of port %d", port);
12329 /* Disable attentions */
12330 vars->link_status = 0;
12331 elink_update_mng(params, vars->link_status);
12332 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
12333 SHMEM_EEE_ACTIVE_BIT);
12334 elink_update_mng_eee(params, vars->eee_status);
12335 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4,
12336 (ELINK_NIG_MASK_XGXS0_LINK_STATUS |
12337 ELINK_NIG_MASK_XGXS0_LINK10G |
12338 ELINK_NIG_MASK_SERDES0_LINK_STATUS |
12339 ELINK_NIG_MASK_MI_INT));
12341 /* Activate nig drain */
12342 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + port * 4, 1);
12344 /* Disable nig egress interface */
12345 if (!CHIP_IS_E3(sc)) {
12346 REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port * 4, 0);
12347 REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port * 4, 0);
12349 #ifdef ELINK_INCLUDE_EMUL
12350 /* Stop BigMac rx */
12351 if (!(params->feature_config_flags &
12352 ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC))
12354 if (!CHIP_IS_E3(sc))
12355 elink_set_bmac_rx(sc, port, 0);
12356 #ifdef ELINK_INCLUDE_EMUL
12357 /* Stop XMAC/UMAC rx */
12358 if (!(params->feature_config_flags &
12359 ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC))
12361 if (CHIP_IS_E3(sc) && !CHIP_REV_IS_FPGA(sc)) {
12362 elink_set_xmac_rxtx(params, 0);
12363 elink_set_umac_rxtx(params, 0);
12366 if (!CHIP_IS_E3(sc))
12367 REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port * 4, 0);
12370 /* The PHY reset is controlled by GPIO 1
12371 * Hold it as vars low
12373 /* Clear link led */
12374 elink_set_mdio_emac_per_phy(sc, params);
12375 elink_set_led(params, vars, ELINK_LED_MODE_OFF, 0);
12377 if (reset_ext_phy && (!CHIP_REV_IS_SLOW(sc))) {
12378 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
12380 if (params->phy[phy_index].link_reset) {
12381 elink_set_aer_mmd(params,
12382 ¶ms->phy[phy_index]);
12383 params->phy[phy_index].link_reset(¶ms->
12388 if (params->phy[phy_index].flags &
12389 ELINK_FLAGS_REARM_LATCH_SIGNAL)
12390 clear_latch_ind = 1;
12394 if (clear_latch_ind) {
12395 /* Clear latching indication */
12396 elink_rearm_latch_signal(sc, port, 0);
12397 elink_bits_dis(sc, NIG_REG_LATCH_BC_0 + port * 4,
12398 1 << ELINK_NIG_LATCH_BC_ENABLE_MI_INT);
12400 #if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA)
12401 if (!CHIP_REV_IS_SLOW(sc))
12403 if (params->phy[ELINK_INT_PHY].link_reset)
12404 params->phy[ELINK_INT_PHY].link_reset(¶ms->
12409 /* Disable nig ingress interface */
12410 if (!CHIP_IS_E3(sc)) {
12412 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
12413 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
12414 REG_WR(sc, NIG_REG_BMAC0_IN_EN + port * 4, 0);
12415 REG_WR(sc, NIG_REG_EMAC0_IN_EN + port * 4, 0);
12417 uint32_t xmac_base =
12418 (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
12419 elink_set_xumac_nig(params, 0, 0);
12420 if (REG_RD(sc, MISC_REG_RESET_REG_2) &
12421 MISC_REGISTERS_RESET_REG_2_XMAC)
12422 REG_WR(sc, xmac_base + XMAC_REG_CTRL,
12423 XMAC_CTRL_REG_SOFT_RESET);
12426 vars->phy_flags = 0;
12427 return ELINK_STATUS_OK;
12430 elink_status_t elink_lfa_reset(struct elink_params * params,
12431 struct elink_vars * vars)
12433 struct bnx2x_softc *sc = params->sc;
12435 vars->phy_flags = 0;
12436 params->link_flags &= ~ELINK_PHY_INITIALIZED;
12437 if (!params->lfa_base)
12438 return elink_link_reset(params, vars, 1);
12440 * Activate NIG drain so that during this time the device won't send
12441 * anything while it is unable to response.
12443 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 1);
12446 * Close gracefully the gate from BMAC to NIG such that no half packets
12449 if (!CHIP_IS_E3(sc))
12450 elink_set_bmac_rx(sc, params->port, 0);
12452 if (CHIP_IS_E3(sc)) {
12453 elink_set_xmac_rxtx(params, 0);
12454 elink_set_umac_rxtx(params, 0);
12456 /* Wait 10ms for the pipe to clean up */
12459 /* Clean the NIG-BRB using the network filters in a way that will
12460 * not cut a packet in the middle.
12462 elink_set_rx_filter(params, 0);
12465 * Re-open the gate between the BMAC and the NIG, after verifying the
12466 * gate to the BRB is closed, otherwise packets may arrive to the
12467 * firmware before driver had initialized it. The target is to achieve
12468 * minimum management protocol down time.
12470 if (!CHIP_IS_E3(sc))
12471 elink_set_bmac_rx(sc, params->port, 1);
12473 if (CHIP_IS_E3(sc)) {
12474 elink_set_xmac_rxtx(params, 1);
12475 elink_set_umac_rxtx(params, 1);
12477 /* Disable NIG drain */
12478 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
12479 return ELINK_STATUS_OK;
12482 /****************************************************************************/
12483 /* Common function */
12484 /****************************************************************************/
12485 static elink_status_t elink_8073_common_init_phy(struct bnx2x_softc *sc,
12486 uint32_t shmem_base_path[],
12487 uint32_t shmem2_base_path[],
12489 __rte_unused uint32_t chip_id)
12491 struct elink_phy phy[PORT_MAX];
12492 struct elink_phy *phy_blk[PORT_MAX];
12495 int8_t port_of_path = 0;
12496 uint32_t swap_val, swap_override;
12497 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
12498 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
12499 port ^= (swap_val && swap_override);
12500 elink_ext_phy_hw_reset(sc, port);
12501 /* PART1 - Reset both phys */
12502 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12503 uint32_t shmem_base, shmem2_base;
12504 /* In E2, same phy is using for port0 of the two paths */
12505 if (CHIP_IS_E1x(sc)) {
12506 shmem_base = shmem_base_path[0];
12507 shmem2_base = shmem2_base_path[0];
12508 port_of_path = port;
12510 shmem_base = shmem_base_path[port];
12511 shmem2_base = shmem2_base_path[port];
12515 /* Extract the ext phy address for the port */
12516 if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,
12517 port_of_path, &phy[port]) !=
12519 PMD_DRV_LOG(DEBUG, "populate_phy failed");
12520 return ELINK_STATUS_ERROR;
12522 /* Disable attentions */
12523 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 +
12525 (ELINK_NIG_MASK_XGXS0_LINK_STATUS |
12526 ELINK_NIG_MASK_XGXS0_LINK10G |
12527 ELINK_NIG_MASK_SERDES0_LINK_STATUS |
12528 ELINK_NIG_MASK_MI_INT));
12530 /* Need to take the phy out of low power mode in order
12531 * to write to access its registers
12533 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
12534 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
12536 /* Reset the phy */
12537 elink_cl45_write(sc, &phy[port],
12538 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1 << 15);
12541 /* Add delay of 150ms after reset */
12544 if (phy[PORT_0].addr & 0x1) {
12545 phy_blk[PORT_0] = &(phy[PORT_1]);
12546 phy_blk[PORT_1] = &(phy[PORT_0]);
12548 phy_blk[PORT_0] = &(phy[PORT_0]);
12549 phy_blk[PORT_1] = &(phy[PORT_1]);
12552 /* PART2 - Download firmware to both phys */
12553 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12554 if (CHIP_IS_E1x(sc))
12555 port_of_path = port;
12559 PMD_DRV_LOG(DEBUG, "Loading spirom for phy address 0x%x",
12560 phy_blk[port]->addr);
12561 if (elink_8073_8727_external_rom_boot(sc, phy_blk[port],
12563 return ELINK_STATUS_ERROR;
12565 /* Only set bit 10 = 1 (Tx power down) */
12566 elink_cl45_read(sc, phy_blk[port],
12568 MDIO_PMA_REG_TX_POWER_DOWN, &val);
12570 /* Phase1 of TX_POWER_DOWN reset */
12571 elink_cl45_write(sc, phy_blk[port],
12573 MDIO_PMA_REG_TX_POWER_DOWN, (val | 1 << 10));
12576 /* Toggle Transmitter: Power down and then up with 600ms delay
12581 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
12582 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12583 /* Phase2 of POWER_DOWN_RESET */
12584 /* Release bit 10 (Release Tx power down) */
12585 elink_cl45_read(sc, phy_blk[port],
12587 MDIO_PMA_REG_TX_POWER_DOWN, &val);
12589 elink_cl45_write(sc, phy_blk[port],
12591 MDIO_PMA_REG_TX_POWER_DOWN,
12592 (val & (~(1 << 10))));
12595 /* Read modify write the SPI-ROM version select register */
12596 elink_cl45_read(sc, phy_blk[port],
12598 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
12599 elink_cl45_write(sc, phy_blk[port],
12601 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1 << 12)));
12603 /* set GPIO2 back to LOW */
12604 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
12605 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
12607 return ELINK_STATUS_OK;
12610 static elink_status_t elink_8726_common_init_phy(struct bnx2x_softc *sc,
12611 uint32_t shmem_base_path[],
12612 uint32_t shmem2_base_path[],
12614 __rte_unused uint32_t chip_id)
12618 struct elink_phy phy;
12619 /* Use port1 because of the static port-swap */
12620 /* Enable the module detection interrupt */
12621 val = REG_RD(sc, MISC_REG_GPIO_EVENT_EN);
12622 val |= ((1 << MISC_REGISTERS_GPIO_3) |
12624 (MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
12625 REG_WR(sc, MISC_REG_GPIO_EVENT_EN, val);
12627 elink_ext_phy_hw_reset(sc, 0);
12629 for (port = 0; port < PORT_MAX; port++) {
12630 uint32_t shmem_base, shmem2_base;
12632 /* In E2, same phy is using for port0 of the two paths */
12633 if (CHIP_IS_E1x(sc)) {
12634 shmem_base = shmem_base_path[0];
12635 shmem2_base = shmem2_base_path[0];
12637 shmem_base = shmem_base_path[port];
12638 shmem2_base = shmem2_base_path[port];
12640 /* Extract the ext phy address for the port */
12641 if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,
12642 port, &phy) != ELINK_STATUS_OK) {
12643 PMD_DRV_LOG(DEBUG, "populate phy failed");
12644 return ELINK_STATUS_ERROR;
12648 elink_cl45_write(sc, &phy,
12649 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
12651 /* Set fault module detected LED on */
12652 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_0,
12653 MISC_REGISTERS_GPIO_HIGH, port);
12656 return ELINK_STATUS_OK;
12659 static void elink_get_ext_phy_reset_gpio(struct bnx2x_softc *sc,
12660 uint32_t shmem_base, uint8_t * io_gpio,
12664 uint32_t phy_gpio_reset = REG_RD(sc, shmem_base +
12665 offsetof(struct shmem_region,
12667 port_hw_config[PORT_0].
12669 switch (phy_gpio_reset) {
12670 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
12674 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:
12678 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:
12682 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:
12686 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:
12690 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:
12694 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:
12698 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:
12703 /* Don't override the io_gpio and io_port */
12708 static elink_status_t elink_8727_common_init_phy(struct bnx2x_softc *sc,
12709 uint32_t shmem_base_path[],
12710 uint32_t shmem2_base_path[],
12712 __rte_unused uint32_t chip_id)
12714 int8_t port, reset_gpio;
12715 uint32_t swap_val, swap_override;
12716 struct elink_phy phy[PORT_MAX];
12717 struct elink_phy *phy_blk[PORT_MAX];
12718 int8_t port_of_path;
12719 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
12720 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
12722 reset_gpio = MISC_REGISTERS_GPIO_1;
12725 /* Retrieve the reset gpio/port which control the reset.
12726 * Default is GPIO1, PORT1
12728 elink_get_ext_phy_reset_gpio(sc, shmem_base_path[0],
12729 (uint8_t *) & reset_gpio,
12730 (uint8_t *) & port);
12732 /* Calculate the port based on port swap */
12733 port ^= (swap_val && swap_override);
12735 /* Initiate PHY reset */
12736 elink_cb_gpio_write(sc, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
12739 elink_cb_gpio_write(sc, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
12744 /* PART1 - Reset both phys */
12745 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12746 uint32_t shmem_base, shmem2_base;
12748 /* In E2, same phy is using for port0 of the two paths */
12749 if (CHIP_IS_E1x(sc)) {
12750 shmem_base = shmem_base_path[0];
12751 shmem2_base = shmem2_base_path[0];
12752 port_of_path = port;
12754 shmem_base = shmem_base_path[port];
12755 shmem2_base = shmem2_base_path[port];
12759 /* Extract the ext phy address for the port */
12760 if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,
12761 port_of_path, &phy[port]) !=
12763 PMD_DRV_LOG(DEBUG, "populate phy failed");
12764 return ELINK_STATUS_ERROR;
12766 /* disable attentions */
12767 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 +
12769 (ELINK_NIG_MASK_XGXS0_LINK_STATUS |
12770 ELINK_NIG_MASK_XGXS0_LINK10G |
12771 ELINK_NIG_MASK_SERDES0_LINK_STATUS |
12772 ELINK_NIG_MASK_MI_INT));
12774 /* Reset the phy */
12775 elink_cl45_write(sc, &phy[port],
12776 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1 << 15);
12779 /* Add delay of 150ms after reset */
12781 if (phy[PORT_0].addr & 0x1) {
12782 phy_blk[PORT_0] = &(phy[PORT_1]);
12783 phy_blk[PORT_1] = &(phy[PORT_0]);
12785 phy_blk[PORT_0] = &(phy[PORT_0]);
12786 phy_blk[PORT_1] = &(phy[PORT_1]);
12788 /* PART2 - Download firmware to both phys */
12789 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12790 if (CHIP_IS_E1x(sc))
12791 port_of_path = port;
12794 PMD_DRV_LOG(DEBUG, "Loading spirom for phy address 0x%x",
12795 phy_blk[port]->addr);
12796 if (elink_8073_8727_external_rom_boot(sc, phy_blk[port],
12798 return ELINK_STATUS_ERROR;
12799 /* Disable PHY transmitter output */
12800 elink_cl45_write(sc, phy_blk[port],
12801 MDIO_PMA_DEVAD, MDIO_PMA_REG_TX_DISABLE, 1);
12804 return ELINK_STATUS_OK;
12807 static elink_status_t elink_84833_common_init_phy(struct bnx2x_softc *sc,
12808 uint32_t shmem_base_path[],
12809 __rte_unused uint32_t
12810 shmem2_base_path[],
12811 __rte_unused uint8_t
12812 phy_index, uint32_t chip_id)
12814 uint8_t reset_gpios;
12815 reset_gpios = elink_84833_get_reset_gpios(sc, shmem_base_path, chip_id);
12816 elink_cb_gpio_mult_write(sc, reset_gpios,
12817 MISC_REGISTERS_GPIO_OUTPUT_LOW);
12819 elink_cb_gpio_mult_write(sc, reset_gpios,
12820 MISC_REGISTERS_GPIO_OUTPUT_HIGH);
12821 PMD_DRV_LOG(DEBUG, "84833 reset pulse on pin values 0x%x", reset_gpios);
12822 return ELINK_STATUS_OK;
12825 static elink_status_t elink_ext_phy_common_init(struct bnx2x_softc *sc,
12826 uint32_t shmem_base_path[],
12827 uint32_t shmem2_base_path[],
12829 uint32_t ext_phy_type,
12832 elink_status_t rc = ELINK_STATUS_OK;
12834 switch (ext_phy_type) {
12835 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073:
12836 rc = elink_8073_common_init_phy(sc, shmem_base_path,
12838 phy_index, chip_id);
12840 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722:
12841 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727:
12842 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727_NOC:
12843 rc = elink_8727_common_init_phy(sc, shmem_base_path,
12845 phy_index, chip_id);
12848 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726:
12849 /* GPIO1 affects both ports, so there's need to pull
12850 * it for single port alone
12852 rc = elink_8726_common_init_phy(sc, shmem_base_path,
12854 phy_index, chip_id);
12856 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833:
12857 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834:
12858 /* GPIO3's are linked, and so both need to be toggled
12859 * to obtain required 2us pulse.
12861 rc = elink_84833_common_init_phy(sc, shmem_base_path,
12863 phy_index, chip_id);
12865 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
12866 rc = ELINK_STATUS_ERROR;
12870 "ext_phy 0x%x common init not required",
12875 if (rc != ELINK_STATUS_OK)
12876 elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, 0); // "Warning: PHY was not initialized,"
12882 elink_status_t elink_common_init_phy(struct bnx2x_softc * sc,
12883 uint32_t shmem_base_path[],
12884 uint32_t shmem2_base_path[],
12886 __rte_unused uint8_t one_port_enabled)
12888 elink_status_t rc = ELINK_STATUS_OK;
12889 uint32_t phy_ver, val;
12890 uint8_t phy_index = 0;
12891 uint32_t ext_phy_type, ext_phy_config;
12892 #if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA)
12893 if (CHIP_REV_IS_EMUL(sc) || CHIP_REV_IS_FPGA(sc))
12894 return ELINK_STATUS_OK;
12897 elink_set_mdio_clk(sc, GRCBASE_EMAC0);
12898 elink_set_mdio_clk(sc, GRCBASE_EMAC1);
12899 PMD_DRV_LOG(DEBUG, "Begin common phy init");
12900 if (CHIP_IS_E3(sc)) {
12902 val = REG_RD(sc, MISC_REG_GEN_PURP_HWG);
12903 REG_WR(sc, MISC_REG_GEN_PURP_HWG, val | 1);
12905 /* Check if common init was already done */
12906 phy_ver = REG_RD(sc, shmem_base_path[0] +
12907 offsetof(struct shmem_region,
12908 port_mb[PORT_0].ext_phy_fw_version));
12910 PMD_DRV_LOG(DEBUG, "Not doing common init; phy ver is 0x%x",
12912 return ELINK_STATUS_OK;
12915 /* Read the ext_phy_type for arbitrary port(0) */
12916 for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS;
12918 ext_phy_config = elink_get_ext_phy_config(sc,
12919 shmem_base_path[0],
12921 ext_phy_type = ELINK_XGXS_EXT_PHY_TYPE(ext_phy_config);
12922 rc |= elink_ext_phy_common_init(sc, shmem_base_path,
12924 phy_index, ext_phy_type,
12930 static void elink_check_over_curr(struct elink_params *params,
12931 struct elink_vars *vars)
12933 struct bnx2x_softc *sc = params->sc;
12935 uint8_t port = params->port;
12938 cfg_pin = (REG_RD(sc, params->shmem_base +
12939 offsetof(struct shmem_region,
12940 dev_info.port_hw_config[port].
12941 e3_cmn_pin_cfg1)) &
12942 PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>
12943 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;
12945 /* Ignore check if no external input PIN available */
12946 if (elink_get_cfg_pin(sc, cfg_pin, &pin_val) != ELINK_STATUS_OK)
12950 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) {
12951 elink_cb_event_log(sc, ELINK_LOG_ID_OVER_CURRENT, params->port); //"Error: Power fault on Port %d has"
12952 // " been detected and the power to "
12953 // "that SFP+ module has been removed"
12954 // " to prevent failure of the card."
12955 // " Please remove the SFP+ module and"
12956 // " restart the system to clear this"
12958 vars->phy_flags |= PHY_OVER_CURRENT_FLAG;
12959 elink_warpcore_power_module(params, 0);
12962 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG;
12965 /* Returns 0 if no change occured since last check; 1 otherwise. */
12966 static uint8_t elink_analyze_link_error(struct elink_params *params,
12967 struct elink_vars *vars,
12968 uint32_t status, uint32_t phy_flag,
12969 uint32_t link_flag, uint8_t notify)
12971 struct bnx2x_softc *sc = params->sc;
12972 /* Compare new value with previous value */
12974 uint32_t old_status = (vars->phy_flags & phy_flag) ? 1 : 0;
12976 if ((status ^ old_status) == 0)
12979 /* If values differ */
12980 switch (phy_flag) {
12981 case PHY_HALF_OPEN_CONN_FLAG:
12982 PMD_DRV_LOG(DEBUG, "Analyze Remote Fault");
12984 case PHY_SFP_TX_FAULT_FLAG:
12985 PMD_DRV_LOG(DEBUG, "Analyze TX Fault");
12988 PMD_DRV_LOG(DEBUG, "Analyze UNKNOWN");
12990 PMD_DRV_LOG(DEBUG, "Link changed:[%x %x]->%x", vars->link_up,
12991 old_status, status);
12993 /* a. Update shmem->link_status accordingly
12994 * b. Update elink_vars->link_up
12997 vars->link_status &= ~LINK_STATUS_LINK_UP;
12998 vars->link_status |= link_flag;
13000 vars->phy_flags |= phy_flag;
13002 /* activate nig drain */
13003 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 1);
13004 /* Set LED mode to off since the PHY doesn't know about these
13007 led_mode = ELINK_LED_MODE_OFF;
13009 vars->link_status |= LINK_STATUS_LINK_UP;
13010 vars->link_status &= ~link_flag;
13012 vars->phy_flags &= ~phy_flag;
13013 led_mode = ELINK_LED_MODE_OPER;
13015 /* Clear nig drain */
13016 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
13018 elink_sync_link(params, vars);
13019 /* Update the LED according to the link state */
13020 elink_set_led(params, vars, led_mode, ELINK_SPEED_10000);
13022 /* Update link status in the shared memory */
13023 elink_update_mng(params, vars->link_status);
13025 /* C. Trigger General Attention */
13026 vars->periodic_flags |= ELINK_PERIODIC_FLAGS_LINK_EVENT;
13028 elink_cb_notify_link_changed(sc);
13033 /******************************************************************************
13035 * This function checks for half opened connection change indication.
13036 * When such change occurs, it calls the elink_analyze_link_error
13037 * to check if Remote Fault is set or cleared. Reception of remote fault
13038 * status message in the MAC indicates that the peer's MAC has detected
13039 * a fault, for example, due to break in the TX side of fiber.
13041 ******************************************************************************/
13042 static elink_status_t elink_check_half_open_conn(struct elink_params *params,
13043 struct elink_vars *vars,
13046 struct bnx2x_softc *sc = params->sc;
13047 uint32_t lss_status = 0;
13049 /* In case link status is physically up @ 10G do */
13050 if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) ||
13051 (REG_RD(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port * 4)))
13052 return ELINK_STATUS_OK;
13054 if (CHIP_IS_E3(sc) &&
13055 (REG_RD(sc, MISC_REG_RESET_REG_2) &
13056 (MISC_REGISTERS_RESET_REG_2_XMAC))) {
13057 /* Check E3 XMAC */
13058 /* Note that link speed cannot be queried here, since it may be
13059 * zero while link is down. In case UMAC is active, LSS will
13060 * simply not be set
13062 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
13064 /* Clear stick bits (Requires rising edge) */
13065 REG_WR(sc, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
13066 REG_WR(sc, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
13067 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
13068 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
13069 if (REG_RD(sc, mac_base + XMAC_REG_RX_LSS_STATUS))
13072 elink_analyze_link_error(params, vars, lss_status,
13073 PHY_HALF_OPEN_CONN_FLAG,
13074 LINK_STATUS_NONE, notify);
13075 } else if (REG_RD(sc, MISC_REG_RESET_REG_2) &
13076 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) {
13077 /* Check E1X / E2 BMAC */
13078 uint32_t lss_status_reg;
13079 uint32_t wb_data[2];
13080 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
13081 NIG_REG_INGRESS_BMAC0_MEM;
13082 /* Read BIGMAC_REGISTER_RX_LSS_STATUS */
13083 if (CHIP_IS_E2(sc))
13084 lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT;
13086 lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS;
13088 REG_RD_DMAE(sc, mac_base + lss_status_reg, wb_data, 2);
13089 lss_status = (wb_data[0] > 0);
13091 elink_analyze_link_error(params, vars, lss_status,
13092 PHY_HALF_OPEN_CONN_FLAG,
13093 LINK_STATUS_NONE, notify);
13095 return ELINK_STATUS_OK;
13098 static void elink_sfp_tx_fault_detection(struct elink_phy *phy,
13099 struct elink_params *params,
13100 struct elink_vars *vars)
13102 struct bnx2x_softc *sc = params->sc;
13103 uint32_t cfg_pin, value = 0;
13104 uint8_t led_change, port = params->port;
13106 /* Get The SFP+ TX_Fault controlling pin ([eg]pio) */
13107 cfg_pin = (REG_RD(sc, params->shmem_base + offsetof(struct shmem_region,
13112 PORT_HW_CFG_E3_TX_FAULT_MASK) >>
13113 PORT_HW_CFG_E3_TX_FAULT_SHIFT;
13115 if (elink_get_cfg_pin(sc, cfg_pin, &value)) {
13116 PMD_DRV_LOG(DEBUG, "Failed to read pin 0x%02x", cfg_pin);
13120 led_change = elink_analyze_link_error(params, vars, value,
13121 PHY_SFP_TX_FAULT_FLAG,
13122 LINK_STATUS_SFP_TX_FAULT, 1);
13125 /* Change TX_Fault led, set link status for further syncs */
13128 if (vars->phy_flags & PHY_SFP_TX_FAULT_FLAG) {
13129 led_mode = MISC_REGISTERS_GPIO_HIGH;
13130 vars->link_status |= LINK_STATUS_SFP_TX_FAULT;
13132 led_mode = MISC_REGISTERS_GPIO_LOW;
13133 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
13136 /* If module is unapproved, led should be on regardless */
13137 if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) {
13138 PMD_DRV_LOG(DEBUG, "Change TX_Fault LED: ->%x",
13140 elink_set_e3_module_fault_led(params, led_mode);
13145 static void elink_kr2_recovery(struct elink_params *params,
13146 struct elink_vars *vars, struct elink_phy *phy)
13148 PMD_DRV_LOG(DEBUG, "KR2 recovery");
13150 elink_warpcore_enable_AN_KR2(phy, params, vars);
13151 elink_warpcore_restart_AN_KR(phy, params);
13154 static void elink_check_kr2_wa(struct elink_params *params,
13155 struct elink_vars *vars, struct elink_phy *phy)
13157 struct bnx2x_softc *sc = params->sc;
13158 uint16_t base_page, next_page, not_kr2_device, lane;
13161 /* Once KR2 was disabled, wait 5 seconds before checking KR2 recovery
13162 * Since some switches tend to reinit the AN process and clear the
13163 * the advertised BP/NP after ~2 seconds causing the KR2 to be disabled
13164 * and recovered many times
13166 if (vars->check_kr2_recovery_cnt > 0) {
13167 vars->check_kr2_recovery_cnt--;
13171 sigdet = elink_warpcore_get_sigdet(phy, params);
13173 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
13174 elink_kr2_recovery(params, vars, phy);
13175 PMD_DRV_LOG(DEBUG, "No sigdet");
13180 lane = elink_get_warpcore_lane(params);
13181 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
13182 MDIO_AER_BLOCK_AER_REG, lane);
13183 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
13184 MDIO_AN_REG_LP_AUTO_NEG, &base_page);
13185 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
13186 MDIO_AN_REG_LP_AUTO_NEG2, &next_page);
13187 elink_set_aer_mmd(params, phy);
13189 /* CL73 has not begun yet */
13190 if (base_page == 0) {
13191 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
13192 elink_kr2_recovery(params, vars, phy);
13193 PMD_DRV_LOG(DEBUG, "No BP");
13198 /* In case NP bit is not set in the BasePage, or it is set,
13199 * but only KX is advertised, declare this link partner as non-KR2
13202 not_kr2_device = (((base_page & 0x8000) == 0) ||
13203 (((base_page & 0x8000) &&
13204 ((next_page & 0xe0) == 0x2))));
13206 /* In case KR2 is already disabled, check if we need to re-enable it */
13207 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
13208 if (!not_kr2_device) {
13209 PMD_DRV_LOG(DEBUG, "BP=0x%x, NP=0x%x", base_page,
13211 elink_kr2_recovery(params, vars, phy);
13215 /* KR2 is enabled, but not KR2 device */
13216 if (not_kr2_device) {
13217 /* Disable KR2 on both lanes */
13218 PMD_DRV_LOG(DEBUG, "BP=0x%x, NP=0x%x", base_page, next_page);
13219 elink_disable_kr2(params, vars, phy);
13220 /* Restart AN on leading lane */
13221 elink_warpcore_restart_AN_KR(phy, params);
13226 void elink_period_func(struct elink_params *params, struct elink_vars *vars)
13229 struct bnx2x_softc *sc = params->sc;
13230 for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) {
13231 if (params->phy[phy_idx].flags & ELINK_FLAGS_TX_ERROR_CHECK) {
13232 elink_set_aer_mmd(params, ¶ms->phy[phy_idx]);
13233 if (elink_check_half_open_conn(params, vars, 1) !=
13235 PMD_DRV_LOG(DEBUG, "Fault detection failed");
13241 if (CHIP_IS_E3(sc)) {
13242 struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY];
13243 elink_set_aer_mmd(params, phy);
13244 if ((phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) &&
13245 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
13246 elink_check_kr2_wa(params, vars, phy);
13247 elink_check_over_curr(params, vars);
13248 if (vars->rx_tx_asic_rst)
13249 elink_warpcore_config_runtime(phy, params, vars);
13251 if ((REG_RD(sc, params->shmem_base +
13252 offsetof(struct shmem_region,
13253 dev_info.port_hw_config[params->port].
13255 & PORT_HW_CFG_NET_SERDES_IF_MASK) ==
13256 PORT_HW_CFG_NET_SERDES_IF_SFI) {
13257 if (elink_is_sfp_module_plugged(params)) {
13258 elink_sfp_tx_fault_detection(phy, params, vars);
13259 } else if (vars->link_status & LINK_STATUS_SFP_TX_FAULT) {
13260 /* Clean trail, interrupt corrects the leds */
13261 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
13262 vars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG;
13263 /* Update link status in the shared memory */
13264 elink_update_mng(params, vars->link_status);
13270 uint8_t elink_fan_failure_det_req(struct bnx2x_softc *sc,
13271 uint32_t shmem_base,
13272 uint32_t shmem2_base, uint8_t port)
13274 uint8_t phy_index, fan_failure_det_req = 0;
13275 struct elink_phy phy;
13276 for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS;
13278 if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,
13280 != ELINK_STATUS_OK) {
13281 PMD_DRV_LOG(DEBUG, "populate phy failed");
13284 fan_failure_det_req |= (phy.flags &
13285 ELINK_FLAGS_FAN_FAILURE_DET_REQ);
13287 return fan_failure_det_req;
13290 void elink_hw_reset_phy(struct elink_params *params)
13293 struct bnx2x_softc *sc = params->sc;
13294 elink_update_mng(params, 0);
13295 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + params->port * 4,
13296 (ELINK_NIG_MASK_XGXS0_LINK_STATUS |
13297 ELINK_NIG_MASK_XGXS0_LINK10G |
13298 ELINK_NIG_MASK_SERDES0_LINK_STATUS |
13299 ELINK_NIG_MASK_MI_INT));
13301 for (phy_index = ELINK_INT_PHY; phy_index < ELINK_MAX_PHYS; phy_index++) {
13302 if (params->phy[phy_index].hw_reset) {
13303 params->phy[phy_index].hw_reset(¶ms->phy[phy_index],
13305 params->phy[phy_index] = phy_null;
13310 void elink_init_mod_abs_int(struct bnx2x_softc *sc, struct elink_vars *vars,
13311 __rte_unused uint32_t chip_id, uint32_t shmem_base,
13312 uint32_t shmem2_base, uint8_t port)
13314 uint8_t gpio_num = 0xff, gpio_port = 0xff, phy_index;
13316 uint32_t offset, aeu_mask, swap_val, swap_override, sync_offset;
13317 if (CHIP_IS_E3(sc)) {
13318 if (elink_get_mod_abs_int_cfg(sc,
13322 &gpio_port) != ELINK_STATUS_OK)
13325 struct elink_phy phy;
13326 for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS;
13328 if (elink_populate_phy(sc, phy_index, shmem_base,
13329 shmem2_base, port, &phy)
13330 != ELINK_STATUS_OK) {
13331 PMD_DRV_LOG(DEBUG, "populate phy failed");
13334 if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726) {
13335 gpio_num = MISC_REGISTERS_GPIO_3;
13342 if (gpio_num == 0xff)
13345 /* Set GPIO3 to trigger SFP+ module insertion/removal */
13346 elink_cb_gpio_write(sc, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z,
13349 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
13350 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
13351 gpio_port ^= (swap_val && swap_override);
13353 vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<
13354 (gpio_num + (gpio_port << 2));
13356 sync_offset = shmem_base +
13357 offsetof(struct shmem_region,
13358 dev_info.port_hw_config[port].aeu_int_mask);
13359 REG_WR(sc, sync_offset, vars->aeu_int_mask);
13361 PMD_DRV_LOG(DEBUG, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x",
13362 gpio_num, gpio_port, vars->aeu_int_mask);
13365 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
13367 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
13369 /* Open appropriate AEU for interrupts */
13370 aeu_mask = REG_RD(sc, offset);
13371 aeu_mask |= vars->aeu_int_mask;
13372 REG_WR(sc, offset, aeu_mask);
13374 /* Enable the GPIO to trigger interrupt */
13375 val = REG_RD(sc, MISC_REG_GPIO_EVENT_EN);
13376 val |= 1 << (gpio_num + (gpio_port << 2));
13377 REG_WR(sc, MISC_REG_GPIO_EVENT_EN, val);