1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2007-2013 Broadcom Corporation.
4 * Eric Davis <edavis@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
6 * Gary Zambrano <zambrano@broadcom.com>
8 * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
9 * Copyright (c) 2015-2018 Cavium Inc.
10 * All rights reserved.
24 /***********************************************************/
25 /* CLC Call backs functions */
26 /***********************************************************/
27 /* CLC device structure */
30 extern uint32_t elink_cb_reg_read(struct bnx2x_softc *sc, uint32_t reg_addr);
31 extern void elink_cb_reg_write(struct bnx2x_softc *sc, uint32_t reg_addr, uint32_t val);
33 /* mode - 0( LOW ) /1(HIGH)*/
34 extern uint8_t elink_cb_gpio_write(struct bnx2x_softc *sc,
36 uint8_t mode, uint8_t port);
37 extern uint8_t elink_cb_gpio_mult_write(struct bnx2x_softc *sc,
41 extern uint32_t elink_cb_gpio_read(struct bnx2x_softc *sc, uint16_t gpio_num, uint8_t port);
42 extern uint8_t elink_cb_gpio_int_write(struct bnx2x_softc *sc,
44 uint8_t mode, uint8_t port);
46 extern uint32_t elink_cb_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param);
48 /* This function is called every 1024 bytes downloading of phy firmware.
49 Driver can use it to print to screen indication for download progress */
50 extern void elink_cb_download_progress(struct bnx2x_softc *sc, uint32_t cur, uint32_t total);
52 /* Each log type has its own parameters */
53 typedef enum elink_log_id {
54 ELINK_LOG_ID_UNQUAL_IO_MODULE = 0, /* uint8_t port, const char* vendor_name, const char* vendor_pn */
55 ELINK_LOG_ID_OVER_CURRENT = 1, /* uint8_t port */
56 ELINK_LOG_ID_PHY_UNINITIALIZED = 2, /* uint8_t port */
57 ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT= 3, /* No params */
58 ELINK_LOG_ID_NON_10G_MODULE = 4, /* uint8_t port */
61 typedef enum elink_status {
66 ELINK_STATUS_INVALID_IMAGE,
67 ELINK_OP_NOT_SUPPORTED = 122
69 extern void elink_cb_event_log(struct bnx2x_softc *sc, const elink_log_id_t log_id, ...);
70 extern void elink_cb_load_warpcore_microcode(void);
72 extern void elink_cb_notify_link_changed(struct bnx2x_softc *sc);
74 #define ELINK_EVENT_LOG_LEVEL_ERROR 1
75 #define ELINK_EVENT_LOG_LEVEL_WARNING 2
76 #define ELINK_EVENT_ID_SFP_UNQUALIFIED_MODULE 1
77 #define ELINK_EVENT_ID_SFP_POWER_FAULT 2
79 #define ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0]))
82 /***********************************************************/
84 /***********************************************************/
85 #define ELINK_DEFAULT_PHY_DEV_ADDR 3
86 #define ELINK_E2_DEFAULT_PHY_DEV_ADDR 5
92 #define ELINK_FLOW_CTRL_AUTO PORT_FEATURE_FLOW_CONTROL_AUTO
93 #define ELINK_FLOW_CTRL_TX PORT_FEATURE_FLOW_CONTROL_TX
94 #define ELINK_FLOW_CTRL_RX PORT_FEATURE_FLOW_CONTROL_RX
95 #define ELINK_FLOW_CTRL_BOTH PORT_FEATURE_FLOW_CONTROL_BOTH
96 #define ELINK_FLOW_CTRL_NONE PORT_FEATURE_FLOW_CONTROL_NONE
98 #define ELINK_NET_SERDES_IF_XFI 1
99 #define ELINK_NET_SERDES_IF_SFI 2
100 #define ELINK_NET_SERDES_IF_KR 3
101 #define ELINK_NET_SERDES_IF_DXGXS 4
103 #define ELINK_SPEED_AUTO_NEG 0
104 #define ELINK_SPEED_10 10
105 #define ELINK_SPEED_100 100
106 #define ELINK_SPEED_1000 1000
107 #define ELINK_SPEED_2500 2500
108 #define ELINK_SPEED_10000 10000
109 #define ELINK_SPEED_20000 20000
111 #define ELINK_I2C_DEV_ADDR_A0 0xa0
112 #define ELINK_I2C_DEV_ADDR_A2 0xa2
114 #define ELINK_SFP_EEPROM_PAGE_SIZE 16
115 #define ELINK_SFP_EEPROM_VENDOR_NAME_ADDR 0x14
116 #define ELINK_SFP_EEPROM_VENDOR_NAME_SIZE 16
117 #define ELINK_SFP_EEPROM_VENDOR_OUI_ADDR 0x25
118 #define ELINK_SFP_EEPROM_VENDOR_OUI_SIZE 3
119 #define ELINK_SFP_EEPROM_PART_NO_ADDR 0x28
120 #define ELINK_SFP_EEPROM_PART_NO_SIZE 16
121 #define ELINK_SFP_EEPROM_REVISION_ADDR 0x38
122 #define ELINK_SFP_EEPROM_REVISION_SIZE 4
123 #define ELINK_SFP_EEPROM_SERIAL_ADDR 0x44
124 #define ELINK_SFP_EEPROM_SERIAL_SIZE 16
125 #define ELINK_SFP_EEPROM_DATE_ADDR 0x54 /* ASCII YYMMDD */
126 #define ELINK_SFP_EEPROM_DATE_SIZE 6
127 #define ELINK_SFP_EEPROM_DIAG_TYPE_ADDR 0x5c
128 #define ELINK_SFP_EEPROM_DIAG_TYPE_SIZE 1
129 #define ELINK_SFP_EEPROM_DIAG_ADDR_CHANGE_REQ (1<<2)
130 #define ELINK_SFP_EEPROM_SFF_8472_COMP_ADDR 0x5e
131 #define ELINK_SFP_EEPROM_SFF_8472_COMP_SIZE 1
133 #define ELINK_SFP_EEPROM_A2_CHECKSUM_RANGE 0x5e
134 #define ELINK_SFP_EEPROM_A2_CC_DMI_ADDR 0x5f
136 #define ELINK_PWR_FLT_ERR_MSG_LEN 250
138 #define ELINK_XGXS_EXT_PHY_TYPE(ext_phy_config) \
139 ((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK)
140 #define ELINK_XGXS_EXT_PHY_ADDR(ext_phy_config) \
141 (((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> \
142 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT)
143 #define ELINK_SERDES_EXT_PHY_TYPE(ext_phy_config) \
144 ((ext_phy_config) & PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK)
146 /* Single Media Direct board is the plain 577xx board with CX4/RJ45 jacks */
147 #define ELINK_SINGLE_MEDIA_DIRECT(params) (params->num_phys == 1)
148 /* Single Media board contains single external phy */
149 #define ELINK_SINGLE_MEDIA(params) (params->num_phys == 2)
150 /* Dual Media board contains two external phy with different media */
151 #define ELINK_DUAL_MEDIA(params) (params->num_phys == 3)
153 #define ELINK_FW_PARAM_PHY_ADDR_MASK 0x000000FF
154 #define ELINK_FW_PARAM_PHY_TYPE_MASK 0x0000FF00
155 #define ELINK_FW_PARAM_MDIO_CTRL_MASK 0xFFFF0000
156 #define ELINK_FW_PARAM_MDIO_CTRL_OFFSET 16
157 #define ELINK_FW_PARAM_PHY_ADDR(fw_param) (fw_param & \
158 ELINK_FW_PARAM_PHY_ADDR_MASK)
159 #define ELINK_FW_PARAM_PHY_TYPE(fw_param) (fw_param & \
160 ELINK_FW_PARAM_PHY_TYPE_MASK)
161 #define ELINK_FW_PARAM_MDIO_CTRL(fw_param) ((fw_param & \
162 ELINK_FW_PARAM_MDIO_CTRL_MASK) >> \
163 ELINK_FW_PARAM_MDIO_CTRL_OFFSET)
164 #define ELINK_FW_PARAM_SET(phy_addr, phy_type, mdio_access) \
165 (phy_addr | phy_type | mdio_access << ELINK_FW_PARAM_MDIO_CTRL_OFFSET)
168 #define ELINK_PFC_BRB_FULL_LB_XOFF_THRESHOLD 170
169 #define ELINK_PFC_BRB_FULL_LB_XON_THRESHOLD 250
171 #define ELINK_MAXVAL(a, b) (((a) > (b)) ? (a) : (b))
173 #define ELINK_BMAC_CONTROL_RX_ENABLE 2
174 /***********************************************************/
176 /***********************************************************/
177 #define ELINK_INT_PHY 0
178 #define ELINK_EXT_PHY1 1
179 #define ELINK_EXT_PHY2 2
180 #define ELINK_MAX_PHYS 3
182 /* Same configuration is shared between the XGXS and the first external phy */
183 #define ELINK_LINK_CONFIG_SIZE (ELINK_MAX_PHYS - 1)
184 #define ELINK_LINK_CONFIG_IDX(_phy_idx) ((_phy_idx == ELINK_INT_PHY) ? \
186 /***********************************************************/
187 /* elink_phy struct */
188 /* Defines the required arguments and function per phy */
189 /***********************************************************/
194 typedef uint8_t (*config_init_t)(struct elink_phy *phy, struct elink_params *params,
195 struct elink_vars *vars);
196 typedef uint8_t (*read_status_t)(struct elink_phy *phy, struct elink_params *params,
197 struct elink_vars *vars);
198 typedef void (*link_reset_t)(struct elink_phy *phy,
199 struct elink_params *params);
200 typedef void (*config_loopback_t)(struct elink_phy *phy,
201 struct elink_params *params);
202 typedef uint8_t (*format_fw_ver_t)(uint32_t raw, uint8_t *str, uint16_t *len);
203 typedef void (*hw_reset_t)(struct elink_phy *phy, struct elink_params *params);
204 typedef void (*set_link_led_t)(struct elink_phy *phy,
205 struct elink_params *params, uint8_t mode);
206 typedef void (*phy_specific_func_t)(struct elink_phy *phy,
207 struct elink_params *params, uint32_t action);
208 struct elink_reg_set {
217 /* Loaded during init */
219 uint8_t def_md_devad;
221 /* No Over-Current detection */
222 #define ELINK_FLAGS_NOC (1<<1)
223 /* Fan failure detection required */
224 #define ELINK_FLAGS_FAN_FAILURE_DET_REQ (1<<2)
225 /* Initialize first the XGXS and only then the phy itself */
226 #define ELINK_FLAGS_INIT_XGXS_FIRST (1<<3)
227 #define ELINK_FLAGS_WC_DUAL_MODE (1<<4)
228 #define ELINK_FLAGS_4_PORT_MODE (1<<5)
229 #define ELINK_FLAGS_REARM_LATCH_SIGNAL (1<<6)
230 #define ELINK_FLAGS_SFP_NOT_APPROVED (1<<7)
231 #define ELINK_FLAGS_MDC_MDIO_WA (1<<8)
232 #define ELINK_FLAGS_DUMMY_READ (1<<9)
233 #define ELINK_FLAGS_MDC_MDIO_WA_B0 (1<<10)
234 #define ELINK_FLAGS_SFP_MODULE_PLUGGED_IN_WC (1<<11)
235 #define ELINK_FLAGS_TX_ERROR_CHECK (1<<12)
236 #define ELINK_FLAGS_EEE (1<<13)
237 #define ELINK_FLAGS_TEMPERATURE (1<<14)
238 #define ELINK_FLAGS_MDC_MDIO_WA_G (1<<15)
240 /* preemphasis values for the rx side */
241 uint16_t rx_preemphasis[4];
243 /* preemphasis values for the tx side */
244 uint16_t tx_preemphasis[4];
246 /* EMAC address for access MDIO */
250 #define ELINK_SUPPORTED_10baseT_Half (1<<0)
251 #define ELINK_SUPPORTED_10baseT_Full (1<<1)
252 #define ELINK_SUPPORTED_100baseT_Half (1<<2)
253 #define ELINK_SUPPORTED_100baseT_Full (1<<3)
254 #define ELINK_SUPPORTED_1000baseT_Full (1<<4)
255 #define ELINK_SUPPORTED_2500baseX_Full (1<<5)
256 #define ELINK_SUPPORTED_10000baseT_Full (1<<6)
257 #define ELINK_SUPPORTED_TP (1<<7)
258 #define ELINK_SUPPORTED_FIBRE (1<<8)
259 #define ELINK_SUPPORTED_Autoneg (1<<9)
260 #define ELINK_SUPPORTED_Pause (1<<10)
261 #define ELINK_SUPPORTED_Asym_Pause (1<<11)
262 #define ELINK_SUPPORTED_20000baseMLD2_Full (1<<21)
263 #define ELINK_SUPPORTED_20000baseKR2_Full (1<<22)
266 #define ELINK_ETH_PHY_UNSPECIFIED 0x0
267 #define ELINK_ETH_PHY_SFPP_10G_FIBER 0x1
268 #define ELINK_ETH_PHY_XFP_FIBER 0x2
269 #define ELINK_ETH_PHY_DA_TWINAX 0x3
270 #define ELINK_ETH_PHY_BASE_T 0x4
271 #define ELINK_ETH_PHY_SFP_1G_FIBER 0x5
272 #define ELINK_ETH_PHY_KR 0xf0
273 #define ELINK_ETH_PHY_CX4 0xf1
274 #define ELINK_ETH_PHY_NOT_PRESENT 0xff
276 /* The address in which version is located*/
279 uint16_t req_flow_ctrl;
281 uint16_t req_line_speed;
283 uint32_t speed_cap_mask;
287 /* Called per phy/port init, and it configures LASI, speed, autoneg,
288 duplex, flow control negotiation, etc. */
289 config_init_t config_init;
291 /* Called due to interrupt. It determines the link, speed */
292 read_status_t read_status;
294 /* Called when driver is unloading. Should reset the phy */
295 link_reset_t link_reset;
297 /* Set the loopback configuration for the phy */
298 config_loopback_t config_loopback;
300 /* Format the given raw number into str up to len */
301 format_fw_ver_t format_fw_ver;
303 /* Reset the phy (both ports) */
306 /* Set link led mode (on/off/oper)*/
307 set_link_led_t set_link_led;
309 /* PHY Specific tasks */
310 phy_specific_func_t phy_specific_func;
311 #define ELINK_DISABLE_TX 1
312 #define ELINK_ENABLE_TX 2
313 #define ELINK_PHY_INIT 3
316 /* Inputs parameters to the CLC */
317 struct elink_params {
321 /* Default / User Configuration */
322 uint8_t loopback_mode;
323 #define ELINK_LOOPBACK_NONE 0
324 #define ELINK_LOOPBACK_EMAC 1
325 #define ELINK_LOOPBACK_BMAC 2
326 #define ELINK_LOOPBACK_XGXS 3
327 #define ELINK_LOOPBACK_EXT_PHY 4
328 #define ELINK_LOOPBACK_EXT 5
329 #define ELINK_LOOPBACK_UMAC 6
330 #define ELINK_LOOPBACK_XMAC 7
332 /* Device parameters */
335 uint16_t req_duplex[ELINK_LINK_CONFIG_SIZE];
336 uint16_t req_flow_ctrl[ELINK_LINK_CONFIG_SIZE];
338 uint16_t req_line_speed[ELINK_LINK_CONFIG_SIZE]; /* Also determine AutoNeg */
340 /* shmem parameters */
342 uint32_t shmem2_base;
343 uint32_t speed_cap_mask[ELINK_LINK_CONFIG_SIZE];
345 #define ELINK_SWITCH_CFG_1G PORT_FEATURE_CON_SWITCH_1G_SWITCH
346 #define ELINK_SWITCH_CFG_10G PORT_FEATURE_CON_SWITCH_10G_SWITCH
347 #define ELINK_SWITCH_CFG_AUTO_DETECT PORT_FEATURE_CON_SWITCH_AUTO_DETECT
349 uint32_t lane_config;
351 /* Phy register parameter */
355 uint32_t feature_config_flags;
356 #define ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0)
357 #define ELINK_FEATURE_CONFIG_PFC_ENABLED (1<<1)
358 #define ELINK_FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY (1<<2)
359 #define ELINK_FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY (1<<3)
360 #define ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX (1<<8)
361 #define ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED (1<<9)
362 #define ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED (1<<10)
363 #define ELINK_FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET (1<<11)
364 #define ELINK_FEATURE_CONFIG_IEEE_PHY_TEST (1<<12)
365 #define ELINK_FEATURE_CONFIG_MT_SUPPORT (1<<13)
366 #define ELINK_FEATURE_CONFIG_BOOT_FROM_SAN (1<<14)
368 /* Will be populated during common init */
369 struct elink_phy phy[ELINK_MAX_PHYS];
371 /* Will be populated during common init */
376 /* Used to configure the EEE Tx LPI timer, has several modes of
377 * operation, according to bits 29:28 -
378 * 2'b00: Timer will be configured by nvram, output will be the value
380 * 2'b01: Timer will be configured by nvram, output will be in
382 * 2'b10: bits 1:0 contain an nvram value which will be used instead
383 * of the one located in the nvram. Output will be that value.
384 * 2'b11: bits 19:0 contain the idle timer in microseconds; output
385 * will be in microseconds.
386 * Bits 31:30 should be 2'b11 in order for EEE to be enabled.
389 #define ELINK_EEE_MODE_NVRAM_BALANCED_TIME (0xa00)
390 #define ELINK_EEE_MODE_NVRAM_AGGRESSIVE_TIME (0x100)
391 #define ELINK_EEE_MODE_NVRAM_LATENCY_TIME (0x6000)
392 #define ELINK_EEE_MODE_NVRAM_MASK (0x3)
393 #define ELINK_EEE_MODE_TIMER_MASK (0xfffff)
394 #define ELINK_EEE_MODE_OUTPUT_TIME (1<<28)
395 #define ELINK_EEE_MODE_OVERRIDE_NVRAM (1<<29)
396 #define ELINK_EEE_MODE_ENABLE_LPI (1<<30)
397 #define ELINK_EEE_MODE_ADV_LPI (1<<31)
399 uint16_t hw_led_mode; /* part of the hw_config read from the shmem */
400 uint32_t multi_phy_config;
402 /* Device pointer passed to all callback functions */
403 struct bnx2x_softc *sc;
404 uint16_t req_fc_auto_adv; /* Should be set to TX / BOTH when
405 req_flow_ctrl is set to AUTO */
407 #define ELINK_LINK_FLAGS_INT_DISABLED (1<<0)
408 #define ELINK_PHY_INITIALIZED (1<<1)
412 /* Output parameters */
415 #define PHY_XGXS_FLAG (1<<0)
416 #define PHY_SGMII_FLAG (1<<1)
417 #define PHY_PHYSICAL_LINK_FLAG (1<<2)
418 #define PHY_HALF_OPEN_CONN_FLAG (1<<3)
419 #define PHY_OVER_CURRENT_FLAG (1<<4)
420 #define PHY_SFP_TX_FAULT_FLAG (1<<5)
423 #define ELINK_MAC_TYPE_NONE 0
424 #define ELINK_MAC_TYPE_EMAC 1
425 #define ELINK_MAC_TYPE_BMAC 2
426 #define ELINK_MAC_TYPE_UMAC 3
427 #define ELINK_MAC_TYPE_XMAC 4
429 uint8_t phy_link_up; /* internal phy link indication */
438 /* The same definitions as the shmem parameter */
439 uint32_t link_status;
441 uint8_t fault_detected;
442 uint8_t check_kr2_recovery_cnt;
443 #define ELINK_CHECK_KR2_RECOVERY_CNT 5
444 uint16_t periodic_flags;
445 #define ELINK_PERIODIC_FLAGS_LINK_EVENT 0x0001
447 uint32_t aeu_int_mask;
448 uint8_t rx_tx_asic_rst;
449 uint8_t turn_to_run_wc_rt;
451 /* The same definitions as the shmem2 parameter */
452 uint32_t link_attr_sync;
455 /***********************************************************/
457 /***********************************************************/
458 elink_status_t elink_phy_init(struct elink_params *params, struct elink_vars *vars);
460 /* Reset the link. Should be called when driver or interface goes down
461 Before calling phy firmware upgrade, the reset_ext_phy should be set
463 elink_status_t elink_lfa_reset(struct elink_params *params, struct elink_vars *vars);
464 /* elink_link_update should be called upon link interrupt */
465 elink_status_t elink_link_update(struct elink_params *params, struct elink_vars *vars);
467 /* Reads the link_status from the shmem,
468 and update the link vars accordingly */
469 void elink_link_status_update(struct elink_params *input,
470 struct elink_vars *output);
473 Basically, the CLC takes care of the led for the link, but in case one needs
474 to set/unset the led unnaturally, set the "mode" to ELINK_LED_MODE_OPER to
475 blink the led, and ELINK_LED_MODE_OFF to set the led off.*/
476 elink_status_t elink_set_led(struct elink_params *params,
477 struct elink_vars *vars, uint8_t mode, uint32_t speed);
478 #define ELINK_LED_MODE_OFF 0
479 #define ELINK_LED_MODE_ON 1
480 #define ELINK_LED_MODE_OPER 2
481 #define ELINK_LED_MODE_FRONT_PANEL_OFF 3
483 /* elink_handle_module_detect_int should be called upon module detection
485 void elink_handle_module_detect_int(struct elink_params *params);
487 /* One-time initialization for external phy after power up */
488 elink_status_t elink_common_init_phy(struct bnx2x_softc *sc, uint32_t shmem_base_path[],
489 uint32_t shmem2_base_path[], uint32_t chip_id, uint8_t one_port_enabled);
491 void elink_hw_reset_phy(struct elink_params *params);
493 /* Check swap bit and adjust PHY order */
494 uint32_t elink_phy_selection(struct elink_params *params);
496 /* Probe the phys on board, and populate them in "params" */
497 elink_status_t elink_phy_probe(struct elink_params *params);
499 /* Checks if fan failure detection is required on one of the phys on board */
500 uint8_t elink_fan_failure_det_req(struct bnx2x_softc *sc, uint32_t shmem_base,
501 uint32_t shmem2_base, uint8_t port);
503 /* Open / close the gate between the NIG and the BRB */
504 void elink_set_rx_filter(struct elink_params *params, uint8_t en);
508 /* Number of maximum COS per chip */
509 #define ELINK_DCBX_E2E3_MAX_NUM_COS (2)
510 #define ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0 (6)
511 #define ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1 (3)
512 #define ELINK_DCBX_E3B0_MAX_NUM_COS ( \
513 ELINK_MAXVAL(ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0, \
514 ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1))
516 #define ELINK_DCBX_MAX_NUM_COS ( \
517 ELINK_MAXVAL(ELINK_DCBX_E3B0_MAX_NUM_COS, \
518 ELINK_DCBX_E2E3_MAX_NUM_COS))
520 /* PFC port configuration params */
521 struct elink_nig_brb_pfc_port_params {
523 uint32_t pause_enable;
524 uint32_t llfc_out_en;
525 uint32_t llfc_enable;
526 uint32_t pkt_priority_to_cos;
527 uint8_t num_of_rx_cos_priority_mask;
528 uint32_t rx_cos_priority_mask[ELINK_DCBX_MAX_NUM_COS];
529 uint32_t llfc_high_priority_classes;
530 uint32_t llfc_low_priority_classes;
534 /* ETS port configuration params */
535 struct elink_ets_bw_params {
539 struct elink_ets_sp_params {
541 * valid values are 0 - 5. 0 is highest strict priority.
542 * There can't be two COS's with the same pri.
547 enum elink_cos_state {
548 elink_cos_state_strict = 0,
549 elink_cos_state_bw = 1,
552 struct elink_ets_cos_params {
553 enum elink_cos_state state ;
555 struct elink_ets_bw_params bw_params;
556 struct elink_ets_sp_params sp_params;
560 struct elink_ets_params {
561 uint8_t num_of_cos; /* Number of valid COS entries*/
562 struct elink_ets_cos_params cos[ELINK_DCBX_MAX_NUM_COS];
565 /* Used to update the PFC attributes in EMAC, BMAC, NIG and BRB
566 * when link is already up
568 elink_status_t elink_update_pfc(struct elink_params *params,
569 struct elink_vars *vars,
570 struct elink_nig_brb_pfc_port_params *pfc_params);
572 void elink_init_mod_abs_int(struct bnx2x_softc *sc, struct elink_vars *vars,
573 uint32_t chip_id, uint32_t shmem_base, uint32_t shmem2_base,
576 void elink_period_func(struct elink_params *params, struct elink_vars *vars);
578 void elink_enable_pmd_tx(struct elink_params *params);