1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
11 #include <sys/queue.h>
14 #include <rte_bus_pci.h>
15 #include <rte_ethdev_driver.h>
16 #include <rte_memory.h>
17 #include <rte_lcore.h>
18 #include <rte_spinlock.h>
23 #define BNXT_MAX_MTU 9574
24 #define VLAN_TAG_SIZE 4
25 #define BNXT_VF_RSV_NUM_RSS_CTX 1
26 #define BNXT_VF_RSV_NUM_L2_CTX 4
27 /* TODO: For now, do not support VMDq/RFS on VFs. */
28 #define BNXT_VF_RSV_NUM_VNIC 1
29 #define BNXT_MAX_LED 4
30 #define BNXT_NUM_VLANS 2
31 #define BNXT_MIN_RING_DESC 16
32 #define BNXT_MAX_TX_RING_DESC 4096
33 #define BNXT_MAX_RX_RING_DESC 8192
34 #define BNXT_DB_SIZE 0x80
36 /* Chimp Communication Channel */
37 #define GRCPF_REG_CHIMP_CHANNEL_OFFSET 0x0
38 #define GRCPF_REG_CHIMP_COMM_TRIGGER 0x100
39 /* Kong Communication Channel */
40 #define GRCPF_REG_KONG_CHANNEL_OFFSET 0xA00
41 #define GRCPF_REG_KONG_COMM_TRIGGER 0xB00
43 #define BNXT_INT_LAT_TMR_MIN 75
44 #define BNXT_INT_LAT_TMR_MAX 150
45 #define BNXT_NUM_CMPL_AGGR_INT 36
46 #define BNXT_CMPL_AGGR_DMA_TMR 37
47 #define BNXT_NUM_CMPL_DMA_AGGR 36
48 #define BNXT_CMPL_AGGR_DMA_TMR_DURING_INT 50
49 #define BNXT_NUM_CMPL_DMA_AGGR_DURING_INT 12
51 struct bnxt_led_info {
56 uint16_t led_state_caps;
57 #define BNXT_LED_ALT_BLINK_CAP(x) ((x) & \
58 rte_cpu_to_le_16(HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT))
60 uint16_t led_color_caps;
68 uint16_t led_blink_on;
69 uint16_t led_blink_off;
74 #define BNXT_LED_DFLT_ENA \
75 (HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID | \
76 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE | \
77 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON | \
78 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF | \
79 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID)
81 #define BNXT_LED_DFLT_ENA_SHIFT 6
83 #define BNXT_LED_DFLT_ENABLES(x) \
84 rte_cpu_to_le_32(BNXT_LED_DFLT_ENA << (BNXT_LED_DFLT_ENA_SHIFT * (x)))
86 enum bnxt_hw_context {
88 HW_CONTEXT_IS_RSS = 1,
89 HW_CONTEXT_IS_COS = 2,
93 struct bnxt_vlan_table_entry {
96 } __attribute__((packed));
98 struct bnxt_vlan_antispoof_table_entry {
102 } __attribute__((packed));
104 struct bnxt_child_vf_info {
106 struct bnxt_vlan_table_entry *vlan_table;
107 struct bnxt_vlan_antispoof_table_entry *vlan_as_table;
108 STAILQ_HEAD(, bnxt_filter_info) filter;
109 uint32_t func_cfg_flags;
112 uint16_t max_tx_rate;
115 uint8_t mac_spoof_en;
116 uint8_t vlan_spoof_en;
121 struct bnxt_pf_info {
122 #define BNXT_FIRST_PF_FID 1
123 #define BNXT_MAX_VFS(bp) (bp->pf.max_vfs)
124 #define BNXT_TOTAL_VFS(bp) ((bp)->pf.total_vfs)
125 #define BNXT_FIRST_VF_FID 128
126 #define BNXT_PF_RINGS_USED(bp) bnxt_get_num_queues(bp)
127 #define BNXT_PF_RINGS_AVAIL(bp) (bp->pf.max_cp_rings - BNXT_PF_RINGS_USED(bp))
129 uint16_t first_vf_id;
132 uint16_t total_vfs; /* Total VFs possible.
133 * Not necessarily enabled.
135 uint32_t func_cfg_flags;
137 rte_iova_t vf_req_buf_dma_addr;
138 uint32_t vf_req_fwd[8];
139 uint16_t total_vnics;
140 struct bnxt_child_vf_info *vf_info;
141 #define BNXT_EVB_MODE_NONE 0
142 #define BNXT_EVB_MODE_VEB 1
143 #define BNXT_EVB_MODE_VEPA 2
147 /* Max wait time is 10 * 100ms = 1s */
148 #define BNXT_LINK_WAIT_CNT 10
149 #define BNXT_LINK_WAIT_INTERVAL 100
150 struct bnxt_link_info {
153 uint8_t phy_link_status;
161 #define PHY_VER_LEN 3
162 uint8_t phy_ver[PHY_VER_LEN];
164 uint16_t support_speeds;
165 uint16_t auto_link_speed;
166 uint16_t force_link_speed;
167 uint16_t auto_link_speed_mask;
168 uint32_t preemphasis;
173 #define BNXT_COS_QUEUE_COUNT 8
174 struct bnxt_cos_queue_info {
180 STAILQ_ENTRY(rte_flow) next;
181 struct bnxt_filter_info *filter;
182 struct bnxt_vnic_info *vnic;
185 struct bnxt_ptp_cfg {
186 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400
187 #define BNXT_GRCPF_REG_SYNC_TIME 0x480
188 #define BNXT_CYCLECOUNTER_MASK 0xffffffffffffffffULL
189 struct rte_timecounter tc;
190 struct rte_timecounter tx_tstamp_tc;
191 struct rte_timecounter rx_tstamp_tc;
193 #define BNXT_MAX_TX_TS 1
195 #define BNXT_PTP_MSG_SYNC (1 << 0)
196 #define BNXT_PTP_MSG_DELAY_REQ (1 << 1)
197 #define BNXT_PTP_MSG_PDELAY_REQ (1 << 2)
198 #define BNXT_PTP_MSG_PDELAY_RESP (1 << 3)
199 #define BNXT_PTP_MSG_FOLLOW_UP (1 << 8)
200 #define BNXT_PTP_MSG_DELAY_RESP (1 << 9)
201 #define BNXT_PTP_MSG_PDELAY_RESP_FOLLOW_UP (1 << 10)
202 #define BNXT_PTP_MSG_ANNOUNCE (1 << 11)
203 #define BNXT_PTP_MSG_SIGNALING (1 << 12)
204 #define BNXT_PTP_MSG_MANAGEMENT (1 << 13)
205 #define BNXT_PTP_MSG_EVENTS (BNXT_PTP_MSG_SYNC | \
206 BNXT_PTP_MSG_DELAY_REQ | \
207 BNXT_PTP_MSG_PDELAY_REQ | \
208 BNXT_PTP_MSG_PDELAY_RESP)
209 uint8_t tx_tstamp_en:1;
212 #define BNXT_PTP_RX_TS_L 0
213 #define BNXT_PTP_RX_TS_H 1
214 #define BNXT_PTP_RX_SEQ 2
215 #define BNXT_PTP_RX_FIFO 3
216 #define BNXT_PTP_RX_FIFO_PENDING 0x1
217 #define BNXT_PTP_RX_FIFO_ADV 4
218 #define BNXT_PTP_RX_REGS 5
220 #define BNXT_PTP_TX_TS_L 0
221 #define BNXT_PTP_TX_TS_H 1
222 #define BNXT_PTP_TX_SEQ 2
223 #define BNXT_PTP_TX_FIFO 3
224 #define BNXT_PTP_TX_FIFO_EMPTY 0x2
225 #define BNXT_PTP_TX_REGS 4
226 uint32_t rx_regs[BNXT_PTP_RX_REGS];
227 uint32_t rx_mapped_regs[BNXT_PTP_RX_REGS];
228 uint32_t tx_regs[BNXT_PTP_TX_REGS];
229 uint32_t tx_mapped_regs[BNXT_PTP_TX_REGS];
233 uint16_t num_cmpl_aggr_int;
234 uint16_t num_cmpl_dma_aggr;
235 uint16_t num_cmpl_dma_aggr_during_int;
236 uint16_t int_lat_tmr_max;
237 uint16_t int_lat_tmr_min;
238 uint16_t cmpl_aggr_dma_tmr;
239 uint16_t cmpl_aggr_dma_tmr_during_int;
242 /* 64-bit doorbell */
243 #define DBR_XID_SFT 32
244 #define DBR_PATH_L2 (0x1ULL << 56)
245 #define DBR_TYPE_SQ (0x0ULL << 60)
246 #define DBR_TYPE_SRQ (0x2ULL << 60)
247 #define DBR_TYPE_CQ (0x4ULL << 60)
248 #define DBR_TYPE_NQ (0xaULL << 60)
250 #define BNXT_RSS_TBL_SIZE_THOR 512
251 #define BNXT_RSS_ENTRIES_PER_CTX_THOR 64
252 #define BNXT_MAX_RSS_CTXTS_THOR \
253 (BNXT_RSS_TBL_SIZE_THOR / BNXT_RSS_ENTRIES_PER_CTX_THOR)
255 #define BNXT_MAX_TC 8
256 #define BNXT_MAX_QUEUE 8
257 #define BNXT_MAX_TC_Q (BNXT_MAX_TC + 1)
258 #define BNXT_MAX_Q (bp->max_q + 1)
259 #define BNXT_PAGE_SHFT 12
260 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHFT)
261 #define MAX_CTX_PAGES (BNXT_PAGE_SIZE / 8)
263 #define PTU_PTE_VALID 0x1UL
264 #define PTU_PTE_LAST 0x2UL
265 #define PTU_PTE_NEXT_TO_LAST 0x4UL
267 struct bnxt_ring_mem_info {
271 #define BNXT_RMEM_VALID_PTE_FLAG 1
272 #define BNXT_RMEM_RING_PTE_FLAG 2
276 const struct rte_memzone *mz;
279 rte_iova_t pg_tbl_map;
280 const struct rte_memzone *pg_tbl_mz;
286 struct bnxt_ctx_pg_info {
288 void *ctx_pg_arr[MAX_CTX_PAGES];
289 rte_iova_t ctx_dma_arr[MAX_CTX_PAGES];
290 struct bnxt_ring_mem_info ring_mem;
293 struct bnxt_ctx_mem_info {
294 uint32_t qp_max_entries;
295 uint16_t qp_min_qp1_entries;
296 uint16_t qp_max_l2_entries;
297 uint16_t qp_entry_size;
298 uint16_t srq_max_l2_entries;
299 uint32_t srq_max_entries;
300 uint16_t srq_entry_size;
301 uint16_t cq_max_l2_entries;
302 uint32_t cq_max_entries;
303 uint16_t cq_entry_size;
304 uint16_t vnic_max_vnic_entries;
305 uint16_t vnic_max_ring_table_entries;
306 uint16_t vnic_entry_size;
307 uint32_t stat_max_entries;
308 uint16_t stat_entry_size;
309 uint16_t tqm_entry_size;
310 uint32_t tqm_min_entries_per_ring;
311 uint32_t tqm_max_entries_per_ring;
312 uint32_t mrav_max_entries;
313 uint16_t mrav_entry_size;
314 uint16_t tim_entry_size;
315 uint32_t tim_max_entries;
316 uint8_t tqm_entries_multiple;
319 #define BNXT_CTX_FLAG_INITED 0x01
321 struct bnxt_ctx_pg_info qp_mem;
322 struct bnxt_ctx_pg_info srq_mem;
323 struct bnxt_ctx_pg_info cq_mem;
324 struct bnxt_ctx_pg_info vnic_mem;
325 struct bnxt_ctx_pg_info stat_mem;
326 struct bnxt_ctx_pg_info *tqm_mem[BNXT_MAX_TC_Q];
329 #define BNXT_HWRM_SHORT_REQ_LEN sizeof(struct hwrm_short_input)
333 struct rte_eth_dev *eth_dev;
334 struct rte_eth_rss_conf rss_conf;
335 struct rte_pci_device *pdev;
339 #define BNXT_FLAG_REGISTERED (1 << 0)
340 #define BNXT_FLAG_VF (1 << 1)
341 #define BNXT_FLAG_PORT_STATS (1 << 2)
342 #define BNXT_FLAG_JUMBO (1 << 3)
343 #define BNXT_FLAG_SHORT_CMD (1 << 4)
344 #define BNXT_FLAG_UPDATE_HASH (1 << 5)
345 #define BNXT_FLAG_PTP_SUPPORTED (1 << 6)
346 #define BNXT_FLAG_MULTI_HOST (1 << 7)
347 #define BNXT_FLAG_EXT_RX_PORT_STATS (1 << 8)
348 #define BNXT_FLAG_EXT_TX_PORT_STATS (1 << 9)
349 #define BNXT_FLAG_KONG_MB_EN (1 << 10)
350 #define BNXT_FLAG_TRUSTED_VF_EN (1 << 11)
351 #define BNXT_FLAG_DFLT_VNIC_SET (1 << 12)
352 #define BNXT_FLAG_THOR_CHIP (1 << 13)
353 #define BNXT_FLAG_EXT_STATS_SUPPORTED (1 << 29)
354 #define BNXT_FLAG_NEW_RM (1 << 30)
355 #define BNXT_FLAG_INIT_DONE (1U << 31)
356 #define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF))
357 #define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF)
358 #define BNXT_NPAR(bp) ((bp)->port_partition_type)
359 #define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST)
360 #define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
361 #define BNXT_USE_CHIMP_MB 0 //For non-CFA commands, everything uses Chimp.
362 #define BNXT_USE_KONG(bp) ((bp)->flags & BNXT_FLAG_KONG_MB_EN)
363 #define BNXT_VF_IS_TRUSTED(bp) ((bp)->flags & BNXT_FLAG_TRUSTED_VF_EN)
364 #define BNXT_CHIP_THOR(bp) ((bp)->flags & BNXT_FLAG_THOR_CHIP)
365 #define BNXT_HAS_NQ(bp) BNXT_CHIP_THOR(bp)
366 #define BNXT_HAS_RING_GRPS(bp) (!BNXT_CHIP_THOR(bp))
368 unsigned int rx_nr_rings;
369 unsigned int rx_cp_nr_rings;
370 struct bnxt_rx_queue **rx_queues;
371 const void *rx_mem_zone;
372 struct rx_port_stats *hw_rx_port_stats;
373 rte_iova_t hw_rx_port_stats_map;
374 struct rx_port_stats_ext *hw_rx_port_stats_ext;
375 rte_iova_t hw_rx_port_stats_ext_map;
376 uint16_t fw_rx_port_stats_ext_size;
378 unsigned int tx_nr_rings;
379 unsigned int tx_cp_nr_rings;
380 struct bnxt_tx_queue **tx_queues;
381 const void *tx_mem_zone;
382 struct tx_port_stats *hw_tx_port_stats;
383 rte_iova_t hw_tx_port_stats_map;
384 struct tx_port_stats_ext *hw_tx_port_stats_ext;
385 rte_iova_t hw_tx_port_stats_ext_map;
386 uint16_t fw_tx_port_stats_ext_size;
388 /* Default completion ring */
389 struct bnxt_cp_ring_info *def_cp_ring;
390 uint32_t max_ring_grps;
391 struct bnxt_ring_grp_info *grp_info;
393 unsigned int nr_vnics;
395 struct bnxt_vnic_info *vnic_info;
396 STAILQ_HEAD(, bnxt_vnic_info) free_vnic_list;
398 struct bnxt_filter_info *filter_info;
399 STAILQ_HEAD(, bnxt_filter_info) free_filter_list;
401 struct bnxt_irq *irq_tbl;
403 #define MAX_NUM_MAC_ADDR 32
404 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
406 uint16_t hwrm_cmd_seq;
407 uint16_t kong_cmd_seq;
408 void *hwrm_cmd_resp_addr;
409 rte_iova_t hwrm_cmd_resp_dma_addr;
410 void *hwrm_short_cmd_req_addr;
411 rte_iova_t hwrm_short_cmd_req_dma_addr;
412 rte_spinlock_t hwrm_lock;
413 uint16_t max_req_len;
414 uint16_t max_resp_len;
415 uint16_t hwrm_max_ext_req_len;
417 struct bnxt_link_info link_info;
418 struct bnxt_cos_queue_info cos_queue[BNXT_COS_QUEUE_COUNT];
425 uint8_t dflt_mac_addr[RTE_ETHER_ADDR_LEN];
426 uint16_t max_rsscos_ctx;
427 uint16_t max_cp_rings;
428 uint16_t max_tx_rings;
429 uint16_t max_rx_rings;
430 uint16_t max_nq_rings;
433 uint16_t max_stat_ctx;
434 uint16_t first_vf_id;
436 struct bnxt_pf_info pf;
437 uint8_t port_partition_type;
439 uint8_t vxlan_port_cnt;
440 uint8_t geneve_port_cnt;
442 uint16_t geneve_port;
443 uint16_t vxlan_fw_dst_port_id;
444 uint16_t geneve_fw_dst_port_id;
446 uint32_t hwrm_spec_code;
448 struct bnxt_led_info leds[BNXT_MAX_LED];
450 struct bnxt_ptp_cfg *ptp_cfg;
451 uint16_t vf_resv_strategy;
452 struct bnxt_ctx_mem_info *ctx;
455 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete);
456 int bnxt_rcv_msg_from_vf(struct bnxt *bp, uint16_t vf_id, void *msg);
458 bool is_bnxt_supported(struct rte_eth_dev *dev);
459 bool bnxt_stratus_device(struct bnxt *bp);
460 extern const struct rte_flow_ops bnxt_flow_ops;
462 extern int bnxt_logtype_driver;
463 #define PMD_DRV_LOG_RAW(level, fmt, args...) \
464 rte_log(RTE_LOG_ ## level, bnxt_logtype_driver, "%s(): " fmt, \
467 #define PMD_DRV_LOG(level, fmt, args...) \
468 PMD_DRV_LOG_RAW(level, fmt, ## args)