drivers/net/bnxt/bnxt.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2021 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #ifndef _BNXT_H_
   7 #define _BNXT_H_
   8
   9 #include <inttypes.h>
  10 #include <stdbool.h>
  11 #include <sys/queue.h>
  12
  13 #include <rte_pci.h>
  14 #include <rte_bus_pci.h>
  15 #include <ethdev_driver.h>
  16 #include <rte_memory.h>
  17 #include <rte_lcore.h>
  18 #include <rte_spinlock.h>
  19 #include <rte_time.h>
  20
  21 #include "bnxt_cpr.h"
  22 #include "bnxt_util.h"
  23
  24 #include "tf_core.h"
  25 #include "bnxt_ulp.h"
  26 #include "bnxt_tf_common.h"
  27
  28 /* Vendor ID */
  29 #define PCI_VENDOR_ID_BROADCOM          0x14E4
  30
  31 /* Device IDs */
  32 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
  33 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
  34 #define BROADCOM_DEV_ID_STRATUS_NIC     0x1614
  35 #define BROADCOM_DEV_ID_57414_VF        0x16c1
  36 #define BROADCOM_DEV_ID_57304_VF        0x16cb
  37 #define BROADCOM_DEV_ID_57417_MF        0x16cc
  38 #define BROADCOM_DEV_ID_NS2             0x16cd
  39 #define BROADCOM_DEV_ID_57406_VF        0x16d3
  40 #define BROADCOM_DEV_ID_57412           0x16d6
  41 #define BROADCOM_DEV_ID_57414           0x16d7
  42 #define BROADCOM_DEV_ID_57416_RJ45      0x16d8
  43 #define BROADCOM_DEV_ID_57417_RJ45      0x16d9
  44 #define BROADCOM_DEV_ID_5741X_VF        0x16dc
  45 #define BROADCOM_DEV_ID_57412_MF        0x16de
  46 #define BROADCOM_DEV_ID_57317_RJ45      0x16e0
  47 #define BROADCOM_DEV_ID_5731X_VF        0x16e1
  48 #define BROADCOM_DEV_ID_57417_SFP       0x16e2
  49 #define BROADCOM_DEV_ID_57416_SFP       0x16e3
  50 #define BROADCOM_DEV_ID_57317_SFP       0x16e4
  51 #define BROADCOM_DEV_ID_57407_MF        0x16ea
  52 #define BROADCOM_DEV_ID_57414_MF        0x16ec
  53 #define BROADCOM_DEV_ID_57416_MF        0x16ee
  54 #define BROADCOM_DEV_ID_57508           0x1750
  55 #define BROADCOM_DEV_ID_57504           0x1751
  56 #define BROADCOM_DEV_ID_57502           0x1752
  57 #define BROADCOM_DEV_ID_57508_MF1       0x1800
  58 #define BROADCOM_DEV_ID_57504_MF1       0x1801
  59 #define BROADCOM_DEV_ID_57502_MF1       0x1802
  60 #define BROADCOM_DEV_ID_57508_MF2       0x1803
  61 #define BROADCOM_DEV_ID_57504_MF2       0x1804
  62 #define BROADCOM_DEV_ID_57502_MF2       0x1805
  63 #define BROADCOM_DEV_ID_57500_VF1       0x1806
  64 #define BROADCOM_DEV_ID_57500_VF2       0x1807
  65 #define BROADCOM_DEV_ID_58802           0xd802
  66 #define BROADCOM_DEV_ID_58804           0xd804
  67 #define BROADCOM_DEV_ID_58808           0x16f0
  68 #define BROADCOM_DEV_ID_58802_VF        0xd800
  69 #define BROADCOM_DEV_ID_58812           0xd812
  70 #define BROADCOM_DEV_ID_58814           0xd814
  71 #define BROADCOM_DEV_ID_58818           0xd818
  72 #define BROADCOM_DEV_ID_58818_VF        0xd82e
  73
  74 #define BROADCOM_DEV_957508_N2100       0x5208
  75 #define IS_BNXT_DEV_957508_N2100(bp)    \
  76         ((bp)->pdev->id.subsystem_device_id == BROADCOM_DEV_957508_N2100)
  77
  78 #define BNXT_MAX_MTU            9574
  79 #define VLAN_TAG_SIZE           4
  80 #define BNXT_NUM_VLANS          2
  81 #define BNXT_MAX_PKT_LEN        (BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +\
  82                                  RTE_ETHER_CRC_LEN +\
  83                                  (BNXT_NUM_VLANS * VLAN_TAG_SIZE))
  84 /* FW adds extra 4 bytes for FCS */
  85 #define BNXT_VNIC_MRU(mtu)\
  86         ((mtu) + RTE_ETHER_HDR_LEN + VLAN_TAG_SIZE * BNXT_NUM_VLANS)
  87 #define BNXT_VF_RSV_NUM_RSS_CTX 1
  88 #define BNXT_VF_RSV_NUM_L2_CTX  4
  89 /* TODO: For now, do not support VMDq/RFS on VFs. */
  90 #define BNXT_VF_RSV_NUM_VNIC    1
  91 #define BNXT_MAX_LED            4
  92 #define BNXT_MIN_RING_DESC      16
  93 #define BNXT_MAX_TX_RING_DESC   4096
  94 #define BNXT_MAX_RX_RING_DESC   8192
  95 #define BNXT_DB_SIZE            0x80
  96
  97 #define TPA_MAX_AGGS            64
  98 #define TPA_MAX_AGGS_TH         1024
  99
 100 #define TPA_MAX_NUM_SEGS        32
 101 #define TPA_MAX_SEGS_TH         8 /* 32 segments in 4-segment units */
 102 #define TPA_MAX_SEGS            5 /* 32 segments in log2 units */
 103
 104 #define BNXT_TPA_MAX_AGGS(bp) \
 105         (BNXT_CHIP_P5(bp) ? TPA_MAX_AGGS_TH : \
 106                              TPA_MAX_AGGS)
 107
 108 #define BNXT_TPA_MAX_SEGS(bp) \
 109         (BNXT_CHIP_P5(bp) ? TPA_MAX_SEGS_TH : \
 110                               TPA_MAX_SEGS)
 111
 112 /*
 113  * Define the number of async completion rings to be used. Set to zero for
 114  * configurations in which the maximum number of packet completion rings
 115  * for packet completions is desired or when async completion handling
 116  * cannot be interrupt-driven.
 117  */
 118 #ifdef RTE_EXEC_ENV_FREEBSD
 119 /* In FreeBSD OS, nic_uio driver does not support interrupts */
 120 #define BNXT_NUM_ASYNC_CPR(bp) 0U
 121 #else
 122 #define BNXT_NUM_ASYNC_CPR(bp) 1U
 123 #endif
 124
 125 #define BNXT_MISC_VEC_ID               RTE_INTR_VEC_ZERO_OFFSET
 126 #define BNXT_RX_VEC_START              RTE_INTR_VEC_RXTX_OFFSET
 127
 128 /* Chimp Communication Channel */
 129 #define GRCPF_REG_CHIMP_CHANNEL_OFFSET          0x0
 130 #define GRCPF_REG_CHIMP_COMM_TRIGGER            0x100
 131 /* Kong Communication Channel */
 132 #define GRCPF_REG_KONG_CHANNEL_OFFSET           0xA00
 133 #define GRCPF_REG_KONG_COMM_TRIGGER             0xB00
 134
 135 #define BNXT_INT_LAT_TMR_MIN                    75
 136 #define BNXT_INT_LAT_TMR_MAX                    150
 137 #define BNXT_NUM_CMPL_AGGR_INT                  36
 138 #define BNXT_CMPL_AGGR_DMA_TMR                  37
 139 #define BNXT_NUM_CMPL_DMA_AGGR                  36
 140 #define BNXT_CMPL_AGGR_DMA_TMR_DURING_INT       50
 141 #define BNXT_NUM_CMPL_DMA_AGGR_DURING_INT       12
 142
 143 #define BNXT_DEFAULT_VNIC_STATE_MASK                    \
 144         HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK
 145 #define BNXT_DEFAULT_VNIC_STATE_SFT                     \
 146         HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT
 147 #define BNXT_DEFAULT_VNIC_ALLOC                         \
 148         HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC
 149 #define BNXT_DEFAULT_VNIC_FREE                          \
 150         HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE
 151 #define BNXT_DEFAULT_VNIC_CHANGE_PF_ID_MASK             \
 152         HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK
 153 #define BNXT_DEFAULT_VNIC_CHANGE_PF_ID_SFT              \
 154         HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT
 155 #define BNXT_DEFAULT_VNIC_CHANGE_VF_ID_MASK             \
 156         HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK
 157 #define BNXT_DEFAULT_VNIC_CHANGE_VF_ID_SFT              \
 158         HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT
 159
 160 #define BNXT_HWRM_CMD_TO_FORWARD(cmd)   \
 161                 (bp->pf->vf_req_fwd[(cmd) / 32] |= (1 << ((cmd) % 32)))
 162
 163 struct bnxt_led_info {
 164         uint8_t      num_leds;
 165         uint8_t      led_id;
 166         uint8_t      led_type;
 167         uint8_t      led_group_id;
 168         uint8_t      unused;
 169         uint16_t  led_state_caps;
 170 #define BNXT_LED_ALT_BLINK_CAP(x)       ((x) &  \
 171         rte_cpu_to_le_16(HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT))
 172
 173         uint16_t  led_color_caps;
 174 };
 175
 176 struct bnxt_led_cfg {
 177         uint8_t led_id;
 178         uint8_t led_state;
 179         uint8_t led_color;
 180         uint8_t unused;
 181         uint16_t led_blink_on;
 182         uint16_t led_blink_off;
 183         uint8_t led_group_id;
 184         uint8_t rsvd;
 185 };
 186
 187 #define BNXT_LED_DFLT_ENA                               \
 188         (HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID |             \
 189          HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE |          \
 190          HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON |       \
 191          HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF |      \
 192          HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID)
 193
 194 #define BNXT_LED_DFLT_ENA_SHIFT         6
 195
 196 #define BNXT_LED_DFLT_ENABLES(x)                        \
 197         rte_cpu_to_le_32(BNXT_LED_DFLT_ENA << (BNXT_LED_DFLT_ENA_SHIFT * (x)))
 198
 199 struct bnxt_vlan_table_entry {
 200         uint16_t                tpid;
 201         uint16_t                vid;
 202 } __rte_packed;
 203
 204 struct bnxt_vlan_antispoof_table_entry {
 205         uint16_t                tpid;
 206         uint16_t                vid;
 207         uint16_t                mask;
 208 } __rte_packed;
 209
 210 struct bnxt_child_vf_info {
 211         void                    *req_buf;
 212         struct bnxt_vlan_table_entry    *vlan_table;
 213         struct bnxt_vlan_antispoof_table_entry  *vlan_as_table;
 214         STAILQ_HEAD(, bnxt_filter_info) filter;
 215         uint32_t                func_cfg_flags;
 216         uint32_t                l2_rx_mask;
 217         uint16_t                fid;
 218         uint16_t                max_tx_rate;
 219         uint16_t                dflt_vlan;
 220         uint16_t                vlan_count;
 221         uint8_t                 mac_spoof_en;
 222         uint8_t                 vlan_spoof_en;
 223         bool                    random_mac;
 224         bool                    persist_stats;
 225 };
 226
 227 struct bnxt_parent_info {
 228 #define BNXT_PF_FID_INVALID     0xFFFF
 229         uint16_t                fid;
 230         uint16_t                vnic;
 231         uint16_t                port_id;
 232         uint8_t                 mac_addr[RTE_ETHER_ADDR_LEN];
 233 };
 234
 235 struct bnxt_pf_info {
 236 #define BNXT_FIRST_PF_FID       1
 237 #define BNXT_MAX_VFS(bp)        ((bp)->pf->max_vfs)
 238 #define BNXT_MAX_VF_REPS        64
 239 #define BNXT_TOTAL_VFS(bp)      ((bp)->pf->total_vfs)
 240 #define BNXT_FIRST_VF_FID       128
 241 #define BNXT_PF_RINGS_USED(bp)  bnxt_get_num_queues(bp)
 242 #define BNXT_PF_RINGS_AVAIL(bp) ((bp)->pf->max_cp_rings - \
 243                                  BNXT_PF_RINGS_USED(bp))
 244         uint16_t                port_id;
 245         uint16_t                first_vf_id;
 246         uint16_t                active_vfs;
 247         uint16_t                max_vfs;
 248         uint16_t                total_vfs; /* Total VFs possible.
 249                                             * Not necessarily enabled.
 250                                             */
 251         uint32_t                func_cfg_flags;
 252         void                    *vf_req_buf;
 253         rte_iova_t              vf_req_buf_dma_addr;
 254         uint32_t                vf_req_fwd[8];
 255         uint16_t                total_vnics;
 256         struct bnxt_child_vf_info       *vf_info;
 257 #define BNXT_EVB_MODE_NONE      0
 258 #define BNXT_EVB_MODE_VEB       1
 259 #define BNXT_EVB_MODE_VEPA      2
 260         uint8_t                 evb_mode;
 261 };
 262
 263 /* Max wait time for link up is 10s and link down is 500ms */
 264 #define BNXT_MAX_LINK_WAIT_CNT  200
 265 #define BNXT_MIN_LINK_WAIT_CNT  10
 266 #define BNXT_LINK_WAIT_INTERVAL 50
 267 struct bnxt_link_info {
 268         uint32_t                phy_flags;
 269         uint8_t                 mac_type;
 270         uint8_t                 phy_link_status;
 271         uint8_t                 loop_back;
 272         uint8_t                 link_up;
 273         uint8_t                 duplex;
 274         uint8_t                 pause;
 275         uint8_t                 force_pause;
 276         uint8_t                 auto_pause;
 277         uint8_t                 auto_mode;
 278 #define PHY_VER_LEN             3
 279         uint8_t                 phy_ver[PHY_VER_LEN];
 280         uint16_t                link_speed;
 281         uint16_t                support_speeds;
 282         uint16_t                auto_link_speed;
 283         uint16_t                force_link_speed;
 284         uint16_t                auto_link_speed_mask;
 285         uint32_t                preemphasis;
 286         uint8_t                 phy_type;
 287         uint8_t                 media_type;
 288         uint16_t                support_auto_speeds;
 289         uint8_t                 link_signal_mode;
 290         uint16_t                force_pam4_link_speed;
 291         uint16_t                support_pam4_speeds;
 292         uint16_t                auto_pam4_link_speeds;
 293         uint16_t                support_pam4_auto_speeds;
 294         uint8_t                 req_signal_mode;
 295         uint8_t                 module_status;
 296 };
 297
 298 #define BNXT_COS_QUEUE_COUNT    8
 299 struct bnxt_cos_queue_info {
 300         uint8_t id;
 301         uint8_t profile;
 302 };
 303
 304 struct rte_flow {
 305         STAILQ_ENTRY(rte_flow) next;
 306         struct bnxt_filter_info *filter;
 307         struct bnxt_vnic_info   *vnic;
 308 };
 309
 310 #define BNXT_PTP_RX_PND_CNT             10
 311 #define BNXT_PTP_FLAGS_PATH_TX          0x0
 312 #define BNXT_PTP_FLAGS_PATH_RX          0x1
 313 #define BNXT_PTP_FLAGS_CURRENT_TIME     0x2
 314 #define BNXT_PTP_CURRENT_TIME_MASK      0xFFFF00000000ULL
 315
 316 struct bnxt_ptp_cfg {
 317 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT  0x400
 318 #define BNXT_GRCPF_REG_SYNC_TIME        0x480
 319 #define BNXT_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 320         struct rte_timecounter      tc;
 321         struct rte_timecounter      tx_tstamp_tc;
 322         struct rte_timecounter      rx_tstamp_tc;
 323         struct bnxt             *bp;
 324 #define BNXT_MAX_TX_TS  1
 325         uint16_t                        rxctl;
 326 #define BNXT_PTP_MSG_SYNC                       BIT(0)
 327 #define BNXT_PTP_MSG_DELAY_REQ                  BIT(1)
 328 #define BNXT_PTP_MSG_PDELAY_REQ                 BIT(2)
 329 #define BNXT_PTP_MSG_PDELAY_RESP                BIT(3)
 330 #define BNXT_PTP_MSG_FOLLOW_UP                  BIT(8)
 331 #define BNXT_PTP_MSG_DELAY_RESP                 BIT(9)
 332 #define BNXT_PTP_MSG_PDELAY_RESP_FOLLOW_UP      BIT(10)
 333 #define BNXT_PTP_MSG_ANNOUNCE                   BIT(11)
 334 #define BNXT_PTP_MSG_SIGNALING                  BIT(12)
 335 #define BNXT_PTP_MSG_MANAGEMENT                 BIT(13)
 336 #define BNXT_PTP_MSG_EVENTS             (BNXT_PTP_MSG_SYNC |            \
 337                                          BNXT_PTP_MSG_DELAY_REQ |       \
 338                                          BNXT_PTP_MSG_PDELAY_REQ |      \
 339                                          BNXT_PTP_MSG_PDELAY_RESP)
 340         uint8_t                 tx_tstamp_en:1;
 341         int                     rx_filter;
 342
 343 #define BNXT_PTP_RX_TS_L        0
 344 #define BNXT_PTP_RX_TS_H        1
 345 #define BNXT_PTP_RX_SEQ         2
 346 #define BNXT_PTP_RX_FIFO        3
 347 #define BNXT_PTP_RX_FIFO_PENDING 0x1
 348 #define BNXT_PTP_RX_FIFO_ADV    4
 349 #define BNXT_PTP_RX_REGS        5
 350
 351 #define BNXT_PTP_TX_TS_L        0
 352 #define BNXT_PTP_TX_TS_H        1
 353 #define BNXT_PTP_TX_SEQ         2
 354 #define BNXT_PTP_TX_FIFO        3
 355 #define BNXT_PTP_TX_FIFO_EMPTY   0x2
 356 #define BNXT_PTP_TX_REGS        4
 357         uint32_t                        rx_regs[BNXT_PTP_RX_REGS];
 358         uint32_t                        rx_mapped_regs[BNXT_PTP_RX_REGS];
 359         uint32_t                        tx_regs[BNXT_PTP_TX_REGS];
 360         uint32_t                        tx_mapped_regs[BNXT_PTP_TX_REGS];
 361
 362         /* On Thor, the Rx timestamp is present in the Rx completion record */
 363         uint64_t                        rx_timestamp;
 364         uint64_t                        current_time;
 365 };
 366
 367 struct bnxt_coal {
 368         uint16_t                        num_cmpl_aggr_int;
 369         uint16_t                        num_cmpl_dma_aggr;
 370         uint16_t                        num_cmpl_dma_aggr_during_int;
 371         uint16_t                        int_lat_tmr_max;
 372         uint16_t                        int_lat_tmr_min;
 373         uint16_t                        cmpl_aggr_dma_tmr;
 374         uint16_t                        cmpl_aggr_dma_tmr_during_int;
 375 };
 376
 377 /* 64-bit doorbell */
 378 #define DBR_EPOCH_MASK                          0x01000000UL
 379 #define DBR_EPOCH_SFT                           24
 380 #define DBR_XID_SFT                             32
 381 #define DBR_PATH_L2                             (0x1ULL << 56)
 382 #define DBR_VALID                               (0x1ULL << 58)
 383 #define DBR_TYPE_SQ                             (0x0ULL << 60)
 384 #define DBR_TYPE_SRQ                            (0x2ULL << 60)
 385 #define DBR_TYPE_CQ                             (0x4ULL << 60)
 386 #define DBR_TYPE_NQ                             (0xaULL << 60)
 387 #define DBR_TYPE_NQ_ARM                         (0xbULL << 60)
 388
 389 #define DB_PF_OFFSET                    0x10000
 390 #define DB_VF_OFFSET                    0x4000
 391
 392 #define BNXT_RSS_TBL_SIZE_P5            512U
 393 #define BNXT_RSS_ENTRIES_PER_CTX_P5     64
 394 #define BNXT_MAX_RSS_CTXTS_P5 \
 395         (BNXT_RSS_TBL_SIZE_P5 / BNXT_RSS_ENTRIES_PER_CTX_P5)
 396
 397 #define BNXT_MAX_QUEUE                  8
 398 #define BNXT_MAX_TQM_SP_RINGS           1
 399 #define BNXT_MAX_TQM_FP_LEGACY_RINGS    8
 400 #define BNXT_MAX_TQM_FP_RINGS           9
 401 #define BNXT_MAX_TQM_LEGACY_RINGS       \
 402         (BNXT_MAX_TQM_SP_RINGS + BNXT_MAX_TQM_FP_LEGACY_RINGS)
 403 #define BNXT_MAX_TQM_RINGS              \
 404         (BNXT_MAX_TQM_SP_RINGS + BNXT_MAX_TQM_FP_RINGS)
 405 #define BNXT_BACKING_STORE_CFG_LEGACY_LEN       256
 406 #define BNXT_BACKING_STORE_CFG_LEN      \
 407         sizeof(struct hwrm_func_backing_store_cfg_input)
 408 #define BNXT_PAGE_SHFT 12
 409 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHFT)
 410 #define MAX_CTX_PAGES  (BNXT_PAGE_SIZE / 8)
 411
 412 #define PTU_PTE_VALID             0x1UL
 413 #define PTU_PTE_LAST              0x2UL
 414 #define PTU_PTE_NEXT_TO_LAST      0x4UL
 415
 416 struct bnxt_ring_mem_info {
 417         int                             nr_pages;
 418         int                             page_size;
 419         uint32_t                        flags;
 420 #define BNXT_RMEM_VALID_PTE_FLAG        1
 421 #define BNXT_RMEM_RING_PTE_FLAG         2
 422
 423         void                            **pg_arr;
 424         rte_iova_t                      *dma_arr;
 425         const struct rte_memzone        *mz;
 426
 427         uint64_t                        *pg_tbl;
 428         rte_iova_t                      pg_tbl_map;
 429         const struct rte_memzone        *pg_tbl_mz;
 430
 431         int                             vmem_size;
 432         void                            **vmem;
 433 };
 434
 435 struct bnxt_ctx_pg_info {
 436         uint32_t        entries;
 437         void            *ctx_pg_arr[MAX_CTX_PAGES];
 438         rte_iova_t      ctx_dma_arr[MAX_CTX_PAGES];
 439         struct bnxt_ring_mem_info ring_mem;
 440 };
 441
 442 struct bnxt_ctx_mem_info {
 443         uint32_t        qp_max_entries;
 444         uint16_t        qp_min_qp1_entries;
 445         uint16_t        qp_max_l2_entries;
 446         uint16_t        qp_entry_size;
 447         uint16_t        srq_max_l2_entries;
 448         uint32_t        srq_max_entries;
 449         uint16_t        srq_entry_size;
 450         uint16_t        cq_max_l2_entries;
 451         uint32_t        cq_max_entries;
 452         uint16_t        cq_entry_size;
 453         uint16_t        vnic_max_vnic_entries;
 454         uint16_t        vnic_max_ring_table_entries;
 455         uint16_t        vnic_entry_size;
 456         uint32_t        stat_max_entries;
 457         uint16_t        stat_entry_size;
 458         uint16_t        tqm_entry_size;
 459         uint32_t        tqm_min_entries_per_ring;
 460         uint32_t        tqm_max_entries_per_ring;
 461         uint32_t        mrav_max_entries;
 462         uint16_t        mrav_entry_size;
 463         uint16_t        tim_entry_size;
 464         uint32_t        tim_max_entries;
 465         uint8_t         tqm_entries_multiple;
 466         uint8_t         tqm_fp_rings_count;
 467
 468         uint32_t        flags;
 469 #define BNXT_CTX_FLAG_INITED    0x01
 470
 471         struct bnxt_ctx_pg_info qp_mem;
 472         struct bnxt_ctx_pg_info srq_mem;
 473         struct bnxt_ctx_pg_info cq_mem;
 474         struct bnxt_ctx_pg_info vnic_mem;
 475         struct bnxt_ctx_pg_info stat_mem;
 476         struct bnxt_ctx_pg_info *tqm_mem[BNXT_MAX_TQM_RINGS];
 477 };
 478
 479 struct bnxt_ctx_mem_buf_info {
 480         void            *va;
 481         rte_iova_t      dma;
 482         uint16_t        ctx_id;
 483         size_t          size;
 484 };
 485
 486 /* Maximum Firmware Reset bail out value in milliseconds */
 487 #define BNXT_MAX_FW_RESET_TIMEOUT       6000
 488 /* Minimum time required for the firmware readiness in milliseconds */
 489 #define BNXT_MIN_FW_READY_TIMEOUT       2000
 490 /* Frequency for the firmware readiness check in milliseconds */
 491 #define BNXT_FW_READY_WAIT_INTERVAL     100
 492
 493 #define US_PER_MS                       1000
 494 #define NS_PER_US                       1000
 495
 496 struct bnxt_error_recovery_info {
 497         /* All units in milliseconds */
 498         uint32_t        driver_polling_freq;
 499         uint32_t        master_func_wait_period;
 500         uint32_t        normal_func_wait_period;
 501         uint32_t        master_func_wait_period_after_reset;
 502         uint32_t        max_bailout_time_after_reset;
 503 #define BNXT_FW_STATUS_REG              0
 504 #define BNXT_FW_HEARTBEAT_CNT_REG       1
 505 #define BNXT_FW_RECOVERY_CNT_REG        2
 506 #define BNXT_FW_RESET_INPROG_REG        3
 507 #define BNXT_FW_STATUS_REG_CNT          4
 508         uint32_t        status_regs[BNXT_FW_STATUS_REG_CNT];
 509         uint32_t        mapped_status_regs[BNXT_FW_STATUS_REG_CNT];
 510         uint32_t        reset_inprogress_reg_mask;
 511 #define BNXT_NUM_RESET_REG      16
 512         uint8_t         reg_array_cnt;
 513         uint32_t        reset_reg[BNXT_NUM_RESET_REG];
 514         uint32_t        reset_reg_val[BNXT_NUM_RESET_REG];
 515         uint8_t         delay_after_reset[BNXT_NUM_RESET_REG];
 516 #define BNXT_FLAG_ERROR_RECOVERY_HOST   BIT(0)
 517 #define BNXT_FLAG_ERROR_RECOVERY_CO_CPU BIT(1)
 518 #define BNXT_FLAG_MASTER_FUNC           BIT(2)
 519 #define BNXT_FLAG_RECOVERY_ENABLED      BIT(3)
 520         uint32_t        flags;
 521
 522         uint32_t        last_heart_beat;
 523         uint32_t        last_reset_counter;
 524 };
 525
 526 /* Frequency for the FUNC_DRV_IF_CHANGE retry in milliseconds */
 527 #define BNXT_IF_CHANGE_RETRY_INTERVAL   50
 528 /* Maximum retry count for FUNC_DRV_IF_CHANGE */
 529 #define BNXT_IF_CHANGE_RETRY_COUNT      40
 530
 531 struct bnxt_mark_info {
 532         uint32_t        mark_id;
 533         bool            valid;
 534 };
 535
 536 struct bnxt_rep_info {
 537         struct rte_eth_dev      *vfr_eth_dev;
 538         pthread_mutex_t         vfr_lock;
 539         pthread_mutex_t         vfr_start_lock;
 540         bool                    conduit_valid;
 541 };
 542
 543 /* address space location of register */
 544 #define BNXT_FW_STATUS_REG_TYPE_MASK    3
 545 /* register is located in PCIe config space */
 546 #define BNXT_FW_STATUS_REG_TYPE_CFG     0
 547 /* register is located in GRC address space */
 548 #define BNXT_FW_STATUS_REG_TYPE_GRC     1
 549 /* register is located in BAR0  */
 550 #define BNXT_FW_STATUS_REG_TYPE_BAR0    2
 551 /* register is located in BAR1  */
 552 #define BNXT_FW_STATUS_REG_TYPE_BAR1    3
 553
 554 #define BNXT_FW_STATUS_REG_TYPE(reg)    ((reg) & BNXT_FW_STATUS_REG_TYPE_MASK)
 555 #define BNXT_FW_STATUS_REG_OFF(reg)     ((reg) & ~BNXT_FW_STATUS_REG_TYPE_MASK)
 556
 557 #define BNXT_GRCP_WINDOW_2_BASE         0x2000
 558 #define BNXT_GRCP_WINDOW_3_BASE         0x3000
 559
 560 #define BNXT_GRCP_BASE_MASK             0xfffff000
 561 #define BNXT_GRCP_OFFSET_MASK           0x00000ffc
 562
 563 #define BNXT_FW_STATUS_HEALTHY          0x8000
 564 #define BNXT_FW_STATUS_SHUTDOWN         0x100000
 565
 566 #define BNXT_ETH_RSS_SUPPORT (  \
 567         ETH_RSS_IPV4 |          \
 568         ETH_RSS_NONFRAG_IPV4_TCP |      \
 569         ETH_RSS_NONFRAG_IPV4_UDP |      \
 570         ETH_RSS_IPV6 |          \
 571         ETH_RSS_NONFRAG_IPV6_TCP |      \
 572         ETH_RSS_NONFRAG_IPV6_UDP |      \
 573         ETH_RSS_LEVEL_MASK)
 574
 575 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 576                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 577                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 578                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 579                                      DEV_TX_OFFLOAD_TCP_TSO | \
 580                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 581                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 582                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 583                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 584                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 585                                      DEV_TX_OFFLOAD_QINQ_INSERT | \
 586                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 587
 588 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 589                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 590                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 591                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 592                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 593                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 594                                      DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | \
 595                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 596                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 597                                      DEV_RX_OFFLOAD_VLAN_EXTEND | \
 598                                      DEV_RX_OFFLOAD_TCP_LRO | \
 599                                      DEV_RX_OFFLOAD_SCATTER | \
 600                                      DEV_RX_OFFLOAD_RSS_HASH)
 601
 602 #define BNXT_HWRM_SHORT_REQ_LEN         sizeof(struct hwrm_short_input)
 603
 604 struct bnxt_flow_stat_info {
 605         uint16_t                max_fc;
 606         uint16_t                flow_count;
 607         struct bnxt_ctx_mem_buf_info rx_fc_in_tbl;
 608         struct bnxt_ctx_mem_buf_info rx_fc_out_tbl;
 609         struct bnxt_ctx_mem_buf_info tx_fc_in_tbl;
 610         struct bnxt_ctx_mem_buf_info tx_fc_out_tbl;
 611 };
 612
 613 struct bnxt_ring_stats {
 614         /* Number of transmitted unicast packets */
 615         uint64_t        tx_ucast_pkts;
 616         /* Number of transmitted multicast packets */
 617         uint64_t        tx_mcast_pkts;
 618         /* Number of transmitted broadcast packets */
 619         uint64_t        tx_bcast_pkts;
 620         /* Number of packets discarded in transmit path */
 621         uint64_t        tx_discard_pkts;
 622         /* Number of packets in transmit path with error */
 623         uint64_t        tx_error_pkts;
 624         /* Number of transmitted bytes for unicast traffic */
 625         uint64_t        tx_ucast_bytes;
 626         /* Number of transmitted bytes for multicast traffic */
 627         uint64_t        tx_mcast_bytes;
 628         /* Number of transmitted bytes for broadcast traffic */
 629         uint64_t        tx_bcast_bytes;
 630         /* Number of received unicast packets */
 631         uint64_t        rx_ucast_pkts;
 632         /* Number of received multicast packets */
 633         uint64_t        rx_mcast_pkts;
 634         /* Number of received broadcast packets */
 635         uint64_t        rx_bcast_pkts;
 636         /* Number of packets discarded in receive path */
 637         uint64_t        rx_discard_pkts;
 638         /* Number of packets in receive path with errors */
 639         uint64_t        rx_error_pkts;
 640         /* Number of received bytes for unicast traffic */
 641         uint64_t        rx_ucast_bytes;
 642         /* Number of received bytes for multicast traffic */
 643         uint64_t        rx_mcast_bytes;
 644         /* Number of received bytes for broadcast traffic */
 645         uint64_t        rx_bcast_bytes;
 646         /* Number of aggregated unicast packets */
 647         uint64_t        rx_agg_pkts;
 648         /* Number of aggregated unicast bytes */
 649         uint64_t        rx_agg_bytes;
 650         /* Number of aggregation events */
 651         uint64_t        rx_agg_events;
 652         /* Number of aborted aggregations */
 653         uint64_t        rx_agg_aborts;
 654 };
 655
 656 struct bnxt {
 657         void                            *bar0;
 658
 659         struct rte_eth_dev              *eth_dev;
 660         struct rte_pci_device           *pdev;
 661         void                            *doorbell_base;
 662         int                             legacy_db_size;
 663
 664         uint32_t                flags;
 665 #define BNXT_FLAG_REGISTERED            BIT(0)
 666 #define BNXT_FLAG_VF                    BIT(1)
 667 #define BNXT_FLAG_PORT_STATS            BIT(2)
 668 #define BNXT_FLAG_JUMBO                 BIT(3)
 669 #define BNXT_FLAG_SHORT_CMD             BIT(4)
 670 #define BNXT_FLAG_UPDATE_HASH           BIT(5)
 671 #define BNXT_FLAG_PTP_SUPPORTED         BIT(6)
 672 #define BNXT_FLAG_MULTI_HOST            BIT(7)
 673 #define BNXT_FLAG_EXT_RX_PORT_STATS     BIT(8)
 674 #define BNXT_FLAG_EXT_TX_PORT_STATS     BIT(9)
 675 #define BNXT_FLAG_KONG_MB_EN            BIT(10)
 676 #define BNXT_FLAG_TRUSTED_VF_EN         BIT(11)
 677 #define BNXT_FLAG_DFLT_VNIC_SET         BIT(12)
 678 #define BNXT_FLAG_CHIP_P5               BIT(13)
 679 #define BNXT_FLAG_STINGRAY              BIT(14)
 680 #define BNXT_FLAG_FW_RESET              BIT(15)
 681 #define BNXT_FLAG_FATAL_ERROR           BIT(16)
 682 #define BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE   BIT(17)
 683 #define BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED     BIT(18)
 684 #define BNXT_FLAG_EXT_STATS_SUPPORTED           BIT(19)
 685 #define BNXT_FLAG_NEW_RM                        BIT(20)
 686 #define BNXT_FLAG_NPAR_PF                       BIT(21)
 687 #define BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS         BIT(22)
 688 #define BNXT_FLAG_FC_THREAD                     BIT(23)
 689 #define BNXT_FLAG_RX_VECTOR_PKT_MODE            BIT(24)
 690 #define BNXT_FLAG_FLOW_XSTATS_EN                BIT(25)
 691 #define BNXT_FLAG_DFLT_MAC_SET                  BIT(26)
 692 #define BNXT_FLAG_GFID_ENABLE                   BIT(27)
 693 #define BNXT_FLAG_RFS_NEEDS_VNIC                BIT(28)
 694 #define BNXT_FLAG_FLOW_CFA_RFS_RING_TBL_IDX_V2  BIT(29)
 695 #define BNXT_RFS_NEEDS_VNIC(bp) ((bp)->flags & BNXT_FLAG_RFS_NEEDS_VNIC)
 696 #define BNXT_PF(bp)             (!((bp)->flags & BNXT_FLAG_VF))
 697 #define BNXT_VF(bp)             ((bp)->flags & BNXT_FLAG_VF)
 698 #define BNXT_NPAR(bp)           ((bp)->flags & BNXT_FLAG_NPAR_PF)
 699 #define BNXT_MH(bp)             ((bp)->flags & BNXT_FLAG_MULTI_HOST)
 700 #define BNXT_SINGLE_PF(bp)      (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
 701 #define BNXT_USE_CHIMP_MB       0 //For non-CFA commands, everything uses Chimp.
 702 #define BNXT_USE_KONG(bp)       ((bp)->flags & BNXT_FLAG_KONG_MB_EN)
 703 #define BNXT_VF_IS_TRUSTED(bp)  ((bp)->flags & BNXT_FLAG_TRUSTED_VF_EN)
 704 #define BNXT_CHIP_P5(bp)        ((bp)->flags & BNXT_FLAG_CHIP_P5)
 705 #define BNXT_STINGRAY(bp)       ((bp)->flags & BNXT_FLAG_STINGRAY)
 706 #define BNXT_HAS_NQ(bp)         BNXT_CHIP_P5(bp)
 707 #define BNXT_HAS_RING_GRPS(bp)  (!BNXT_CHIP_P5(bp))
 708 #define BNXT_FLOW_XSTATS_EN(bp) ((bp)->flags & BNXT_FLAG_FLOW_XSTATS_EN)
 709 #define BNXT_HAS_DFLT_MAC_SET(bp)      ((bp)->flags & BNXT_FLAG_DFLT_MAC_SET)
 710 #define BNXT_GFID_ENABLED(bp)   ((bp)->flags & BNXT_FLAG_GFID_ENABLE)
 711
 712         uint32_t                        flags2;
 713 #define BNXT_FLAGS2_PTP_TIMESYNC_ENABLED        BIT(0)
 714 #define BNXT_FLAGS2_PTP_ALARM_SCHEDULED         BIT(1)
 715 #define BNXT_FLAGS2_ACCUM_STATS_EN              BIT(2)
 716 #define BNXT_P5_PTP_TIMESYNC_ENABLED(bp)        \
 717         ((bp)->flags2 & BNXT_FLAGS2_PTP_TIMESYNC_ENABLED)
 718 #define BNXT_ACCUM_STATS_EN(bp)                 \
 719         ((bp)->flags2 & BNXT_FLAGS2_ACCUM_STATS_EN)
 720
 721         uint16_t                chip_num;
 722 #define CHIP_NUM_58818          0xd818
 723 #define BNXT_CHIP_SR2(bp)       ((bp)->chip_num == CHIP_NUM_58818)
 724
 725         uint32_t                fw_cap;
 726 #define BNXT_FW_CAP_HOT_RESET           BIT(0)
 727 #define BNXT_FW_CAP_IF_CHANGE           BIT(1)
 728 #define BNXT_FW_CAP_ERROR_RECOVERY      BIT(2)
 729 #define BNXT_FW_CAP_ERR_RECOVER_RELOAD  BIT(3)
 730 #define BNXT_FW_CAP_HCOMM_FW_STATUS     BIT(4)
 731 #define BNXT_FW_CAP_ADV_FLOW_MGMT       BIT(5)
 732 #define BNXT_FW_CAP_ADV_FLOW_COUNTERS   BIT(6)
 733 #define BNXT_FW_CAP_LINK_ADMIN          BIT(7)
 734 #define BNXT_FW_CAP_TRUFLOW_EN          BIT(8)
 735 #define BNXT_TRUFLOW_EN(bp)     ((bp)->fw_cap & BNXT_FW_CAP_TRUFLOW_EN)
 736
 737         pthread_mutex_t         flow_lock;
 738
 739         uint32_t                vnic_cap_flags;
 740 #define BNXT_VNIC_CAP_COS_CLASSIFY      BIT(0)
 741 #define BNXT_VNIC_CAP_OUTER_RSS         BIT(1)
 742 #define BNXT_VNIC_CAP_RX_CMPL_V2        BIT(2)
 743         unsigned int            rx_nr_rings;
 744         unsigned int            rx_cp_nr_rings;
 745         unsigned int            rx_num_qs_per_vnic;
 746         struct bnxt_rx_queue **rx_queues;
 747         const void              *rx_mem_zone;
 748         struct rx_port_stats    *hw_rx_port_stats;
 749         rte_iova_t              hw_rx_port_stats_map;
 750         struct rx_port_stats_ext    *hw_rx_port_stats_ext;
 751         rte_iova_t              hw_rx_port_stats_ext_map;
 752         uint16_t                fw_rx_port_stats_ext_size;
 753
 754         unsigned int            tx_nr_rings;
 755         unsigned int            tx_cp_nr_rings;
 756         struct bnxt_tx_queue **tx_queues;
 757         const void              *tx_mem_zone;
 758         struct tx_port_stats    *hw_tx_port_stats;
 759         rte_iova_t              hw_tx_port_stats_map;
 760         struct tx_port_stats_ext    *hw_tx_port_stats_ext;
 761         rte_iova_t              hw_tx_port_stats_ext_map;
 762         uint16_t                fw_tx_port_stats_ext_size;
 763
 764         /* Default completion ring */
 765         struct bnxt_cp_ring_info        *async_cp_ring;
 766         struct bnxt_cp_ring_info        *rxtx_nq_ring;
 767         uint32_t                max_ring_grps;
 768         struct bnxt_ring_grp_info       *grp_info;
 769
 770         uint16_t                        nr_vnics;
 771
 772 #define BNXT_GET_DEFAULT_VNIC(bp)       (&(bp)->vnic_info[0])
 773         struct bnxt_vnic_info   *vnic_info;
 774         STAILQ_HEAD(, bnxt_vnic_info)   free_vnic_list;
 775
 776         struct bnxt_filter_info *filter_info;
 777         STAILQ_HEAD(, bnxt_filter_info) free_filter_list;
 778
 779         struct bnxt_irq         *irq_tbl;
 780
 781         uint8_t                 mac_addr[RTE_ETHER_ADDR_LEN];
 782
 783         uint16_t                        chimp_cmd_seq;
 784         uint16_t                        kong_cmd_seq;
 785         void                            *hwrm_cmd_resp_addr;
 786         rte_iova_t                      hwrm_cmd_resp_dma_addr;
 787         void                            *hwrm_short_cmd_req_addr;
 788         rte_iova_t                      hwrm_short_cmd_req_dma_addr;
 789         rte_spinlock_t                  hwrm_lock;
 790         /* synchronize between dev_configure_op and int handler */
 791         pthread_mutex_t                 def_cp_lock;
 792         /* synchronize between dev_start_op and async evt handler
 793          * Locking sequence in async evt handler will be
 794          * def_cp_lock
 795          * health_check_lock
 796          */
 797         pthread_mutex_t                 health_check_lock;
 798         /* synchronize between dev_stop/dev_close_op and
 799          * error recovery thread triggered as part of
 800          * HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY
 801          */
 802         pthread_mutex_t                 err_recovery_lock;
 803         uint16_t                        max_req_len;
 804         uint16_t                        max_resp_len;
 805         uint16_t                        hwrm_max_ext_req_len;
 806
 807          /* default command timeout value of 500ms */
 808 #define DFLT_HWRM_CMD_TIMEOUT           500000
 809          /* short command timeout value of 50ms */
 810 #define SHORT_HWRM_CMD_TIMEOUT          50000
 811         /* default HWRM request timeout value */
 812         uint32_t                        hwrm_cmd_timeout;
 813
 814         struct bnxt_link_info           *link_info;
 815         struct bnxt_cos_queue_info      *rx_cos_queue;
 816         struct bnxt_cos_queue_info      *tx_cos_queue;
 817         uint8_t                 tx_cosq_id[BNXT_COS_QUEUE_COUNT];
 818         uint8_t                 rx_cosq_cnt;
 819         uint8_t                 max_tc;
 820         uint8_t                 max_lltc;
 821         uint8_t                 max_q;
 822
 823         uint16_t                fw_fid;
 824         uint16_t                max_rsscos_ctx;
 825         uint16_t                max_cp_rings;
 826         uint16_t                max_tx_rings;
 827         uint16_t                max_rx_rings;
 828 #define MAX_STINGRAY_RINGS              236U
 829 #define BNXT_MAX_VF_REP_RINGS   8
 830
 831         uint16_t                max_nq_rings;
 832         uint16_t                max_l2_ctx;
 833         uint16_t                max_rx_em_flows;
 834         uint16_t                max_vnics;
 835         uint16_t                max_stat_ctx;
 836         uint16_t                max_tpa_v2;
 837         uint16_t                first_vf_id;
 838         uint16_t                vlan;
 839 #define BNXT_OUTER_TPID_MASK    0x0000ffff
 840 #define BNXT_OUTER_TPID_BD_MASK 0xffff0000
 841 #define BNXT_OUTER_TPID_BD_SHFT 16
 842         uint32_t                outer_tpid_bd;
 843         struct bnxt_pf_info     *pf;
 844         struct bnxt_parent_info *parent;
 845         uint8_t                 port_cnt;
 846         uint8_t                 vxlan_port_cnt;
 847         uint8_t                 geneve_port_cnt;
 848         uint16_t                vxlan_port;
 849         uint16_t                geneve_port;
 850         uint16_t                vxlan_fw_dst_port_id;
 851         uint16_t                geneve_fw_dst_port_id;
 852         uint32_t                fw_ver;
 853         uint32_t                hwrm_spec_code;
 854
 855         struct bnxt_led_info    *leds;
 856         struct bnxt_ptp_cfg     *ptp_cfg;
 857         uint16_t                vf_resv_strategy;
 858         struct bnxt_ctx_mem_info        *ctx;
 859
 860         uint16_t                fw_reset_min_msecs;
 861         uint16_t                fw_reset_max_msecs;
 862         uint16_t                switch_domain_id;
 863         uint16_t                num_reps;
 864         struct bnxt_rep_info    *rep_info;
 865         uint16_t                *cfa_code_map;
 866         /* Struct to hold adapter error recovery related info */
 867         struct bnxt_error_recovery_info *recovery_info;
 868 #define BNXT_MARK_TABLE_SZ      (sizeof(struct bnxt_mark_info)  * 64 * 1024)
 869 /* TCAM and EM should be 16-bit only. Other modes not supported. */
 870 #define BNXT_FLOW_ID_MASK       0x0000ffff
 871         struct bnxt_mark_info   *mark_table;
 872
 873 #define BNXT_SVIF_INVALID       0xFFFF
 874         uint16_t                func_svif;
 875         uint16_t                port_svif;
 876
 877         struct tf               tfp;
 878         struct tf               tfp_shared;
 879         struct bnxt_ulp_context *ulp_ctx;
 880         struct bnxt_flow_stat_info *flow_stat;
 881         uint16_t                max_num_kflows;
 882         uint8_t                 app_id;
 883         uint16_t                tx_cfa_action;
 884         struct bnxt_ring_stats  *prev_rx_ring_stats;
 885         struct bnxt_ring_stats  *prev_tx_ring_stats;
 886 };
 887
 888 static
 889 inline uint16_t bnxt_max_rings(struct bnxt *bp)
 890 {
 891         uint16_t max_tx_rings = bp->max_tx_rings;
 892         uint16_t max_rx_rings = bp->max_rx_rings;
 893         uint16_t max_cp_rings = bp->max_cp_rings;
 894         uint16_t max_rings;
 895
 896         /* For the sake of symmetry:
 897          * max Tx rings == max Rx rings, one stat ctx for each.
 898          */
 899         if (BNXT_STINGRAY(bp)) {
 900                 max_rx_rings = RTE_MIN(RTE_MIN(max_rx_rings / 2U,
 901                                                MAX_STINGRAY_RINGS),
 902                                        bp->max_stat_ctx / 2U);
 903         } else {
 904                 max_rx_rings = RTE_MIN(max_rx_rings / 2U,
 905                                        bp->max_stat_ctx / 2U);
 906         }
 907
 908         /*
 909          * RSS table size in Thor is 512.
 910          * Cap max Rx rings to the same value for RSS.
 911          */
 912         if (BNXT_CHIP_P5(bp))
 913                 max_rx_rings = RTE_MIN(max_rx_rings, BNXT_RSS_TBL_SIZE_P5);
 914
 915         max_tx_rings = RTE_MIN(max_tx_rings, max_rx_rings);
 916         if (max_cp_rings > BNXT_NUM_ASYNC_CPR(bp))
 917                 max_cp_rings -= BNXT_NUM_ASYNC_CPR(bp);
 918         max_rings = RTE_MIN(max_cp_rings / 2U, max_tx_rings);
 919
 920         return max_rings;
 921 }
 922
 923 #define BNXT_FC_TIMER   1 /* Timer freq in Sec Flow Counters */
 924
 925 /**
 926  * Structure to store private data for each VF representor instance
 927  */
 928 struct bnxt_representor {
 929         uint16_t                switch_domain_id;
 930         uint16_t                vf_id;
 931 #define BNXT_REP_IS_PF          BIT(0)
 932 #define BNXT_REP_Q_R2F_VALID            BIT(1)
 933 #define BNXT_REP_Q_F2R_VALID            BIT(2)
 934 #define BNXT_REP_FC_R2F_VALID           BIT(3)
 935 #define BNXT_REP_FC_F2R_VALID           BIT(4)
 936 #define BNXT_REP_BASED_PF_VALID         BIT(5)
 937         uint32_t                flags;
 938         uint16_t                fw_fid;
 939 #define BNXT_DFLT_VNIC_ID_INVALID       0xFFFF
 940         uint16_t                dflt_vnic_id;
 941         uint16_t                svif;
 942         uint16_t                vfr_tx_cfa_action;
 943         uint8_t                 parent_pf_idx; /* Logical PF index */
 944         uint32_t                dpdk_port_id;
 945         uint32_t                rep_based_pf;
 946         uint8_t                 rep_q_r2f;
 947         uint8_t                 rep_q_f2r;
 948         uint8_t                 rep_fc_r2f;
 949         uint8_t                 rep_fc_f2r;
 950         /* Private data store of associated PF/Trusted VF */
 951         struct rte_eth_dev      *parent_dev;
 952         uint8_t                 mac_addr[RTE_ETHER_ADDR_LEN];
 953         uint8_t                 dflt_mac_addr[RTE_ETHER_ADDR_LEN];
 954         struct bnxt_rx_queue    **rx_queues;
 955         unsigned int            rx_nr_rings;
 956         unsigned int            tx_nr_rings;
 957         uint64_t                tx_pkts[BNXT_MAX_VF_REP_RINGS];
 958         uint64_t                tx_bytes[BNXT_MAX_VF_REP_RINGS];
 959         uint64_t                rx_pkts[BNXT_MAX_VF_REP_RINGS];
 960         uint64_t                rx_bytes[BNXT_MAX_VF_REP_RINGS];
 961         uint64_t                rx_drop_pkts[BNXT_MAX_VF_REP_RINGS];
 962         uint64_t                rx_drop_bytes[BNXT_MAX_VF_REP_RINGS];
 963 };
 964
 965 #define BNXT_REP_PF(vfr_bp)             ((vfr_bp)->flags & BNXT_REP_IS_PF)
 966 #define BNXT_REP_BASED_PF(vfr_bp)       \
 967                 ((vfr_bp)->flags & BNXT_REP_BASED_PF_VALID)
 968
 969 struct bnxt_vf_rep_tx_queue {
 970         struct bnxt_tx_queue *txq;
 971         struct bnxt_representor *bp;
 972 };
 973
 974 #define I2C_DEV_ADDR_A0                 0xa0
 975 #define I2C_DEV_ADDR_A2                 0xa2
 976 #define SFF_DIAG_SUPPORT_OFFSET         0x5c
 977 #define SFF_MODULE_ID_SFP               0x3
 978 #define SFF_MODULE_ID_QSFP              0xc
 979 #define SFF_MODULE_ID_QSFP_PLUS         0xd
 980 #define SFF_MODULE_ID_QSFP28            0x11
 981 #define SFF8636_FLATMEM_OFFSET          0x2
 982 #define SFF8636_FLATMEM_MASK            0x4
 983 #define SFF8636_OPT_PAGES_OFFSET        0xc3
 984 #define SFF8636_PAGE1_MASK              0x40
 985 #define SFF8636_PAGE2_MASK              0x80
 986 #define BNXT_MAX_PHY_I2C_RESP_SIZE      64
 987
 988 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
 989 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
 990                      bool exp_link_status);
 991 int bnxt_rcv_msg_from_vf(struct bnxt *bp, uint16_t vf_id, void *msg);
 992 int is_bnxt_in_error(struct bnxt *bp);
 993
 994 int bnxt_map_fw_health_status_regs(struct bnxt *bp);
 995 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index);
 996 void bnxt_schedule_fw_health_check(struct bnxt *bp);
 997
 998 bool is_bnxt_supported(struct rte_eth_dev *dev);
 999 bool bnxt_stratus_device(struct bnxt *bp);
1000 void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
1001 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp);
1002 int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1003                         int wait_to_complete);
1004 uint16_t bnxt_dummy_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1005                               uint16_t nb_pkts);
1006 uint16_t bnxt_dummy_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
1007                               uint16_t nb_pkts);
1008
1009 extern const struct rte_flow_ops bnxt_flow_ops;
1010
1011 #define bnxt_acquire_flow_lock(bp) \
1012         pthread_mutex_lock(&(bp)->flow_lock)
1013
1014 #define bnxt_release_flow_lock(bp) \
1015         pthread_mutex_unlock(&(bp)->flow_lock)
1016
1017 #define BNXT_VALID_VNIC_OR_RET(bp, vnic_id) do { \
1018         if ((vnic_id) >= (bp)->max_vnics) { \
1019                 rte_flow_error_set(error, \
1020                                 EINVAL, \
1021                                 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, \
1022                                 NULL, \
1023                                 "Group id is invalid!"); \
1024                 rc = -rte_errno; \
1025                 goto ret; \
1026         } \
1027 } while (0)
1028
1029 #define BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)    \
1030                 ((eth_dev)->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1031
1032 extern int bnxt_logtype_driver;
1033 #define PMD_DRV_LOG_RAW(level, fmt, args...) \
1034         rte_log(RTE_LOG_ ## level, bnxt_logtype_driver, "%s(): " fmt, \
1035                 __func__, ## args)
1036
1037 #define PMD_DRV_LOG(level, fmt, args...) \
1038           PMD_DRV_LOG_RAW(level, fmt, ## args)
1039
1040 extern const struct rte_flow_ops bnxt_ulp_rte_flow_ops;
1041 int32_t bnxt_ulp_port_init(struct bnxt *bp);
1042 void bnxt_ulp_port_deinit(struct bnxt *bp);
1043 int32_t bnxt_ulp_create_df_rules(struct bnxt *bp);
1044 void bnxt_ulp_destroy_df_rules(struct bnxt *bp, bool global);
1045 int32_t
1046 bnxt_ulp_create_vfr_default_rules(struct rte_eth_dev *vfr_ethdev);
1047 int32_t
1048 bnxt_ulp_delete_vfr_default_rules(struct bnxt_representor *vfr);
1049 void bnxt_get_iface_mac(uint16_t port, enum bnxt_ulp_intf_type type,
1050                         uint8_t *mac, uint8_t *parent_mac);
1051 uint16_t bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type);
1052 uint16_t bnxt_get_parent_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type);
1053 struct bnxt *bnxt_get_bp(uint16_t port);
1054 uint16_t bnxt_get_svif(uint16_t port_id, bool func_svif,
1055                        enum bnxt_ulp_intf_type type);
1056 uint16_t bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type);
1057 uint16_t bnxt_get_parif(uint16_t port, enum bnxt_ulp_intf_type type);
1058 uint16_t bnxt_get_phy_port_id(uint16_t port);
1059 uint16_t bnxt_get_vport(uint16_t port);
1060 enum bnxt_ulp_intf_type
1061 bnxt_get_interface_type(uint16_t port);
1062 int bnxt_rep_dev_start_op(struct rte_eth_dev *eth_dev);
1063
1064 void bnxt_cancel_fc_thread(struct bnxt *bp);
1065 void bnxt_flow_cnt_alarm_cb(void *arg);
1066 int bnxt_flow_stats_req(struct bnxt *bp);
1067 int bnxt_flow_stats_cnt(struct bnxt *bp);
1068 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp);
1069 int bnxt_flow_ops_get_op(struct rte_eth_dev *dev,
1070                          const struct rte_flow_ops **ops);
1071
1072 #endif