1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
11 #include <sys/queue.h>
14 #include <rte_bus_pci.h>
15 #include <rte_ethdev_driver.h>
16 #include <rte_memory.h>
17 #include <rte_lcore.h>
18 #include <rte_spinlock.h>
22 #include "bnxt_util.h"
26 #include "bnxt_tf_common.h"
29 #define PCI_VENDOR_ID_BROADCOM 0x14E4
32 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
33 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
34 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
35 #define BROADCOM_DEV_ID_57414_VF 0x16c1
36 #define BROADCOM_DEV_ID_57301 0x16c8
37 #define BROADCOM_DEV_ID_57302 0x16c9
38 #define BROADCOM_DEV_ID_57304_PF 0x16ca
39 #define BROADCOM_DEV_ID_57304_VF 0x16cb
40 #define BROADCOM_DEV_ID_57417_MF 0x16cc
41 #define BROADCOM_DEV_ID_NS2 0x16cd
42 #define BROADCOM_DEV_ID_57311 0x16ce
43 #define BROADCOM_DEV_ID_57312 0x16cf
44 #define BROADCOM_DEV_ID_57402 0x16d0
45 #define BROADCOM_DEV_ID_57404 0x16d1
46 #define BROADCOM_DEV_ID_57406_PF 0x16d2
47 #define BROADCOM_DEV_ID_57406_VF 0x16d3
48 #define BROADCOM_DEV_ID_57402_MF 0x16d4
49 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
50 #define BROADCOM_DEV_ID_57412 0x16d6
51 #define BROADCOM_DEV_ID_57414 0x16d7
52 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
53 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
54 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
55 #define BROADCOM_DEV_ID_57412_MF 0x16de
56 #define BROADCOM_DEV_ID_57314 0x16df
57 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
58 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
59 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
60 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
61 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
62 #define BROADCOM_DEV_ID_57404_MF 0x16e7
63 #define BROADCOM_DEV_ID_57406_MF 0x16e8
64 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
65 #define BROADCOM_DEV_ID_57407_MF 0x16ea
66 #define BROADCOM_DEV_ID_57414_MF 0x16ec
67 #define BROADCOM_DEV_ID_57416_MF 0x16ee
68 #define BROADCOM_DEV_ID_57508 0x1750
69 #define BROADCOM_DEV_ID_57504 0x1751
70 #define BROADCOM_DEV_ID_57502 0x1752
71 #define BROADCOM_DEV_ID_57508_MF1 0x1800
72 #define BROADCOM_DEV_ID_57504_MF1 0x1801
73 #define BROADCOM_DEV_ID_57502_MF1 0x1802
74 #define BROADCOM_DEV_ID_57508_MF2 0x1803
75 #define BROADCOM_DEV_ID_57504_MF2 0x1804
76 #define BROADCOM_DEV_ID_57502_MF2 0x1805
77 #define BROADCOM_DEV_ID_57500_VF1 0x1806
78 #define BROADCOM_DEV_ID_57500_VF2 0x1807
79 #define BROADCOM_DEV_ID_58802 0xd802
80 #define BROADCOM_DEV_ID_58804 0xd804
81 #define BROADCOM_DEV_ID_58808 0x16f0
82 #define BROADCOM_DEV_ID_58802_VF 0xd800
84 #define BNXT_MAX_MTU 9574
85 #define VLAN_TAG_SIZE 4
86 #define BNXT_NUM_VLANS 2
87 #define BNXT_MAX_PKT_LEN (BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +\
89 (BNXT_NUM_VLANS * VLAN_TAG_SIZE))
90 /* FW adds extra 4 bytes for FCS */
91 #define BNXT_VNIC_MRU(mtu)\
92 ((mtu) + RTE_ETHER_HDR_LEN + VLAN_TAG_SIZE * BNXT_NUM_VLANS)
93 #define BNXT_VF_RSV_NUM_RSS_CTX 1
94 #define BNXT_VF_RSV_NUM_L2_CTX 4
95 /* TODO: For now, do not support VMDq/RFS on VFs. */
96 #define BNXT_VF_RSV_NUM_VNIC 1
97 #define BNXT_MAX_LED 4
98 #define BNXT_MIN_RING_DESC 16
99 #define BNXT_MAX_TX_RING_DESC 4096
100 #define BNXT_MAX_RX_RING_DESC 8192
101 #define BNXT_DB_SIZE 0x80
103 #define TPA_MAX_AGGS 64
104 #define TPA_MAX_AGGS_TH 1024
106 #define TPA_MAX_NUM_SEGS 32
107 #define TPA_MAX_SEGS_TH 8 /* 32 segments in 4-segment units */
108 #define TPA_MAX_SEGS 5 /* 32 segments in log2 units */
110 #define BNXT_TPA_MAX_AGGS(bp) \
111 (BNXT_CHIP_THOR(bp) ? TPA_MAX_AGGS_TH : \
114 #define BNXT_TPA_MAX_SEGS(bp) \
115 (BNXT_CHIP_THOR(bp) ? TPA_MAX_SEGS_TH : \
118 #ifdef RTE_ARCH_ARM64
119 #define BNXT_NUM_ASYNC_CPR(bp) (BNXT_STINGRAY(bp) ? 0 : 1)
121 #define BNXT_NUM_ASYNC_CPR(bp) 1
124 /* In FreeBSD OS, nic_uio driver does not support interrupts */
125 #ifdef RTE_EXEC_ENV_FREEBSD
126 #ifdef BNXT_NUM_ASYNC_CPR
127 #undef BNXT_NUM_ASYNC_CPR
129 #define BNXT_NUM_ASYNC_CPR(bp) 0
132 #define BNXT_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
133 #define BNXT_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
135 /* Chimp Communication Channel */
136 #define GRCPF_REG_CHIMP_CHANNEL_OFFSET 0x0
137 #define GRCPF_REG_CHIMP_COMM_TRIGGER 0x100
138 /* Kong Communication Channel */
139 #define GRCPF_REG_KONG_CHANNEL_OFFSET 0xA00
140 #define GRCPF_REG_KONG_COMM_TRIGGER 0xB00
142 #define BNXT_INT_LAT_TMR_MIN 75
143 #define BNXT_INT_LAT_TMR_MAX 150
144 #define BNXT_NUM_CMPL_AGGR_INT 36
145 #define BNXT_CMPL_AGGR_DMA_TMR 37
146 #define BNXT_NUM_CMPL_DMA_AGGR 36
147 #define BNXT_CMPL_AGGR_DMA_TMR_DURING_INT 50
148 #define BNXT_NUM_CMPL_DMA_AGGR_DURING_INT 12
150 #define BNXT_DEFAULT_VNIC_STATE_MASK \
151 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK
152 #define BNXT_DEFAULT_VNIC_STATE_SFT \
153 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT
154 #define BNXT_DEFAULT_VNIC_ALLOC \
155 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC
156 #define BNXT_DEFAULT_VNIC_FREE \
157 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE
158 #define BNXT_DEFAULT_VNIC_CHANGE_PF_ID_MASK \
159 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK
160 #define BNXT_DEFAULT_VNIC_CHANGE_PF_ID_SFT \
161 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT
162 #define BNXT_DEFAULT_VNIC_CHANGE_VF_ID_MASK \
163 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK
164 #define BNXT_DEFAULT_VNIC_CHANGE_VF_ID_SFT \
165 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT
167 struct bnxt_led_info {
171 uint8_t led_group_id;
173 uint16_t led_state_caps;
174 #define BNXT_LED_ALT_BLINK_CAP(x) ((x) & \
175 rte_cpu_to_le_16(HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT))
177 uint16_t led_color_caps;
180 struct bnxt_led_cfg {
185 uint16_t led_blink_on;
186 uint16_t led_blink_off;
187 uint8_t led_group_id;
191 #define BNXT_LED_DFLT_ENA \
192 (HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID | \
193 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE | \
194 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON | \
195 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF | \
196 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID)
198 #define BNXT_LED_DFLT_ENA_SHIFT 6
200 #define BNXT_LED_DFLT_ENABLES(x) \
201 rte_cpu_to_le_32(BNXT_LED_DFLT_ENA << (BNXT_LED_DFLT_ENA_SHIFT * (x)))
203 struct bnxt_vlan_table_entry {
208 struct bnxt_vlan_antispoof_table_entry {
214 struct bnxt_child_vf_info {
216 struct bnxt_vlan_table_entry *vlan_table;
217 struct bnxt_vlan_antispoof_table_entry *vlan_as_table;
218 STAILQ_HEAD(, bnxt_filter_info) filter;
219 uint32_t func_cfg_flags;
222 uint16_t max_tx_rate;
225 uint8_t mac_spoof_en;
226 uint8_t vlan_spoof_en;
231 struct bnxt_parent_info {
232 #define BNXT_PF_FID_INVALID 0xFFFF
236 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
239 struct bnxt_pf_info {
240 #define BNXT_FIRST_PF_FID 1
241 #define BNXT_MAX_VFS(bp) ((bp)->pf->max_vfs)
242 #define BNXT_MAX_VF_REPS 64
243 #define BNXT_TOTAL_VFS(bp) ((bp)->pf->total_vfs)
244 #define BNXT_FIRST_VF_FID 128
245 #define BNXT_PF_RINGS_USED(bp) bnxt_get_num_queues(bp)
246 #define BNXT_PF_RINGS_AVAIL(bp) ((bp)->pf->max_cp_rings - \
247 BNXT_PF_RINGS_USED(bp))
249 uint16_t first_vf_id;
252 uint16_t total_vfs; /* Total VFs possible.
253 * Not necessarily enabled.
255 uint32_t func_cfg_flags;
257 rte_iova_t vf_req_buf_dma_addr;
258 uint32_t vf_req_fwd[8];
259 uint16_t total_vnics;
260 struct bnxt_child_vf_info *vf_info;
261 #define BNXT_EVB_MODE_NONE 0
262 #define BNXT_EVB_MODE_VEB 1
263 #define BNXT_EVB_MODE_VEPA 2
267 /* Max wait time for link up is 10s and link down is 500ms */
268 #define BNXT_LINK_UP_WAIT_CNT 200
269 #define BNXT_LINK_DOWN_WAIT_CNT 10
270 #define BNXT_LINK_WAIT_INTERVAL 50
271 struct bnxt_link_info {
274 uint8_t phy_link_status;
282 #define PHY_VER_LEN 3
283 uint8_t phy_ver[PHY_VER_LEN];
285 uint16_t support_speeds;
286 uint16_t auto_link_speed;
287 uint16_t force_link_speed;
288 uint16_t auto_link_speed_mask;
289 uint32_t preemphasis;
294 #define BNXT_COS_QUEUE_COUNT 8
295 struct bnxt_cos_queue_info {
301 STAILQ_ENTRY(rte_flow) next;
302 struct bnxt_filter_info *filter;
303 struct bnxt_vnic_info *vnic;
306 #define BNXT_PTP_FLAGS_PATH_TX 0x0
307 #define BNXT_PTP_FLAGS_PATH_RX 0x1
308 #define BNXT_PTP_FLAGS_CURRENT_TIME 0x2
310 struct bnxt_ptp_cfg {
311 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400
312 #define BNXT_GRCPF_REG_SYNC_TIME 0x480
313 #define BNXT_CYCLECOUNTER_MASK 0xffffffffffffffffULL
314 struct rte_timecounter tc;
315 struct rte_timecounter tx_tstamp_tc;
316 struct rte_timecounter rx_tstamp_tc;
318 #define BNXT_MAX_TX_TS 1
320 #define BNXT_PTP_MSG_SYNC BIT(0)
321 #define BNXT_PTP_MSG_DELAY_REQ BIT(1)
322 #define BNXT_PTP_MSG_PDELAY_REQ BIT(2)
323 #define BNXT_PTP_MSG_PDELAY_RESP BIT(3)
324 #define BNXT_PTP_MSG_FOLLOW_UP BIT(8)
325 #define BNXT_PTP_MSG_DELAY_RESP BIT(9)
326 #define BNXT_PTP_MSG_PDELAY_RESP_FOLLOW_UP BIT(10)
327 #define BNXT_PTP_MSG_ANNOUNCE BIT(11)
328 #define BNXT_PTP_MSG_SIGNALING BIT(12)
329 #define BNXT_PTP_MSG_MANAGEMENT BIT(13)
330 #define BNXT_PTP_MSG_EVENTS (BNXT_PTP_MSG_SYNC | \
331 BNXT_PTP_MSG_DELAY_REQ | \
332 BNXT_PTP_MSG_PDELAY_REQ | \
333 BNXT_PTP_MSG_PDELAY_RESP)
334 uint8_t tx_tstamp_en:1;
337 #define BNXT_PTP_RX_TS_L 0
338 #define BNXT_PTP_RX_TS_H 1
339 #define BNXT_PTP_RX_SEQ 2
340 #define BNXT_PTP_RX_FIFO 3
341 #define BNXT_PTP_RX_FIFO_PENDING 0x1
342 #define BNXT_PTP_RX_FIFO_ADV 4
343 #define BNXT_PTP_RX_REGS 5
345 #define BNXT_PTP_TX_TS_L 0
346 #define BNXT_PTP_TX_TS_H 1
347 #define BNXT_PTP_TX_SEQ 2
348 #define BNXT_PTP_TX_FIFO 3
349 #define BNXT_PTP_TX_FIFO_EMPTY 0x2
350 #define BNXT_PTP_TX_REGS 4
351 uint32_t rx_regs[BNXT_PTP_RX_REGS];
352 uint32_t rx_mapped_regs[BNXT_PTP_RX_REGS];
353 uint32_t tx_regs[BNXT_PTP_TX_REGS];
354 uint32_t tx_mapped_regs[BNXT_PTP_TX_REGS];
356 /* On Thor, the Rx timestamp is present in the Rx completion record */
357 uint64_t rx_timestamp;
361 uint16_t num_cmpl_aggr_int;
362 uint16_t num_cmpl_dma_aggr;
363 uint16_t num_cmpl_dma_aggr_during_int;
364 uint16_t int_lat_tmr_max;
365 uint16_t int_lat_tmr_min;
366 uint16_t cmpl_aggr_dma_tmr;
367 uint16_t cmpl_aggr_dma_tmr_during_int;
370 /* 64-bit doorbell */
371 #define DBR_XID_SFT 32
372 #define DBR_PATH_L2 (0x1ULL << 56)
373 #define DBR_TYPE_SQ (0x0ULL << 60)
374 #define DBR_TYPE_SRQ (0x2ULL << 60)
375 #define DBR_TYPE_CQ (0x4ULL << 60)
376 #define DBR_TYPE_NQ (0xaULL << 60)
377 #define DBR_TYPE_NQ_ARM (0xbULL << 60)
379 #define BNXT_RSS_TBL_SIZE_THOR 512
380 #define BNXT_RSS_ENTRIES_PER_CTX_THOR 64
381 #define BNXT_MAX_RSS_CTXTS_THOR \
382 (BNXT_RSS_TBL_SIZE_THOR / BNXT_RSS_ENTRIES_PER_CTX_THOR)
384 #define BNXT_MAX_TC 8
385 #define BNXT_MAX_QUEUE 8
386 #define BNXT_MAX_TC_Q (BNXT_MAX_TC + 1)
387 #define BNXT_PAGE_SHFT 12
388 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHFT)
389 #define MAX_CTX_PAGES (BNXT_PAGE_SIZE / 8)
391 #define PTU_PTE_VALID 0x1UL
392 #define PTU_PTE_LAST 0x2UL
393 #define PTU_PTE_NEXT_TO_LAST 0x4UL
395 struct bnxt_ring_mem_info {
399 #define BNXT_RMEM_VALID_PTE_FLAG 1
400 #define BNXT_RMEM_RING_PTE_FLAG 2
404 const struct rte_memzone *mz;
407 rte_iova_t pg_tbl_map;
408 const struct rte_memzone *pg_tbl_mz;
414 struct bnxt_ctx_pg_info {
416 void *ctx_pg_arr[MAX_CTX_PAGES];
417 rte_iova_t ctx_dma_arr[MAX_CTX_PAGES];
418 struct bnxt_ring_mem_info ring_mem;
421 struct bnxt_ctx_mem_info {
422 uint32_t qp_max_entries;
423 uint16_t qp_min_qp1_entries;
424 uint16_t qp_max_l2_entries;
425 uint16_t qp_entry_size;
426 uint16_t srq_max_l2_entries;
427 uint32_t srq_max_entries;
428 uint16_t srq_entry_size;
429 uint16_t cq_max_l2_entries;
430 uint32_t cq_max_entries;
431 uint16_t cq_entry_size;
432 uint16_t vnic_max_vnic_entries;
433 uint16_t vnic_max_ring_table_entries;
434 uint16_t vnic_entry_size;
435 uint32_t stat_max_entries;
436 uint16_t stat_entry_size;
437 uint16_t tqm_entry_size;
438 uint32_t tqm_min_entries_per_ring;
439 uint32_t tqm_max_entries_per_ring;
440 uint32_t mrav_max_entries;
441 uint16_t mrav_entry_size;
442 uint16_t tim_entry_size;
443 uint32_t tim_max_entries;
444 uint8_t tqm_entries_multiple;
445 uint8_t tqm_fp_rings_count;
448 #define BNXT_CTX_FLAG_INITED 0x01
450 struct bnxt_ctx_pg_info qp_mem;
451 struct bnxt_ctx_pg_info srq_mem;
452 struct bnxt_ctx_pg_info cq_mem;
453 struct bnxt_ctx_pg_info vnic_mem;
454 struct bnxt_ctx_pg_info stat_mem;
455 struct bnxt_ctx_pg_info *tqm_mem[BNXT_MAX_TC_Q];
458 struct bnxt_ctx_mem_buf_info {
465 /* Maximum Firmware Reset bail out value in milliseconds */
466 #define BNXT_MAX_FW_RESET_TIMEOUT 6000
467 /* Minimum time required for the firmware readiness in milliseconds */
468 #define BNXT_MIN_FW_READY_TIMEOUT 2000
469 /* Frequency for the firmware readiness check in milliseconds */
470 #define BNXT_FW_READY_WAIT_INTERVAL 100
472 #define US_PER_MS 1000
473 #define NS_PER_US 1000
475 struct bnxt_error_recovery_info {
476 /* All units in milliseconds */
477 uint32_t driver_polling_freq;
478 uint32_t master_func_wait_period;
479 uint32_t normal_func_wait_period;
480 uint32_t master_func_wait_period_after_reset;
481 uint32_t max_bailout_time_after_reset;
482 #define BNXT_FW_STATUS_REG 0
483 #define BNXT_FW_HEARTBEAT_CNT_REG 1
484 #define BNXT_FW_RECOVERY_CNT_REG 2
485 #define BNXT_FW_RESET_INPROG_REG 3
486 #define BNXT_FW_STATUS_REG_CNT 4
487 uint32_t status_regs[BNXT_FW_STATUS_REG_CNT];
488 uint32_t mapped_status_regs[BNXT_FW_STATUS_REG_CNT];
489 uint32_t reset_inprogress_reg_mask;
490 #define BNXT_NUM_RESET_REG 16
491 uint8_t reg_array_cnt;
492 uint32_t reset_reg[BNXT_NUM_RESET_REG];
493 uint32_t reset_reg_val[BNXT_NUM_RESET_REG];
494 uint8_t delay_after_reset[BNXT_NUM_RESET_REG];
495 #define BNXT_FLAG_ERROR_RECOVERY_HOST BIT(0)
496 #define BNXT_FLAG_ERROR_RECOVERY_CO_CPU BIT(1)
497 #define BNXT_FLAG_MASTER_FUNC BIT(2)
498 #define BNXT_FLAG_RECOVERY_ENABLED BIT(3)
501 uint32_t last_heart_beat;
502 uint32_t last_reset_counter;
505 /* Frequency for the FUNC_DRV_IF_CHANGE retry in milliseconds */
506 #define BNXT_IF_CHANGE_RETRY_INTERVAL 50
507 /* Maximum retry count for FUNC_DRV_IF_CHANGE */
508 #define BNXT_IF_CHANGE_RETRY_COUNT 40
510 struct bnxt_mark_info {
515 struct bnxt_rep_info {
516 struct rte_eth_dev *vfr_eth_dev;
517 pthread_mutex_t vfr_lock;
518 pthread_mutex_t vfr_start_lock;
522 /* address space location of register */
523 #define BNXT_FW_STATUS_REG_TYPE_MASK 3
524 /* register is located in PCIe config space */
525 #define BNXT_FW_STATUS_REG_TYPE_CFG 0
526 /* register is located in GRC address space */
527 #define BNXT_FW_STATUS_REG_TYPE_GRC 1
528 /* register is located in BAR0 */
529 #define BNXT_FW_STATUS_REG_TYPE_BAR0 2
530 /* register is located in BAR1 */
531 #define BNXT_FW_STATUS_REG_TYPE_BAR1 3
533 #define BNXT_FW_STATUS_REG_TYPE(reg) ((reg) & BNXT_FW_STATUS_REG_TYPE_MASK)
534 #define BNXT_FW_STATUS_REG_OFF(reg) ((reg) & ~BNXT_FW_STATUS_REG_TYPE_MASK)
536 #define BNXT_GRCP_WINDOW_2_BASE 0x2000
537 #define BNXT_GRCP_WINDOW_3_BASE 0x3000
539 #define BNXT_GRCP_BASE_MASK 0xfffff000
540 #define BNXT_GRCP_OFFSET_MASK 0x00000ffc
542 #define BNXT_FW_STATUS_HEALTHY 0x8000
543 #define BNXT_FW_STATUS_SHUTDOWN 0x100000
545 #define BNXT_ETH_RSS_SUPPORT ( \
547 ETH_RSS_NONFRAG_IPV4_TCP | \
548 ETH_RSS_NONFRAG_IPV4_UDP | \
550 ETH_RSS_NONFRAG_IPV6_TCP | \
551 ETH_RSS_NONFRAG_IPV6_UDP)
553 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
554 DEV_TX_OFFLOAD_IPV4_CKSUM | \
555 DEV_TX_OFFLOAD_TCP_CKSUM | \
556 DEV_TX_OFFLOAD_UDP_CKSUM | \
557 DEV_TX_OFFLOAD_TCP_TSO | \
558 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
559 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
560 DEV_TX_OFFLOAD_GRE_TNL_TSO | \
561 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
562 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
563 DEV_TX_OFFLOAD_QINQ_INSERT | \
564 DEV_TX_OFFLOAD_MULTI_SEGS)
566 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
567 DEV_RX_OFFLOAD_VLAN_STRIP | \
568 DEV_RX_OFFLOAD_IPV4_CKSUM | \
569 DEV_RX_OFFLOAD_UDP_CKSUM | \
570 DEV_RX_OFFLOAD_TCP_CKSUM | \
571 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
572 DEV_RX_OFFLOAD_JUMBO_FRAME | \
573 DEV_RX_OFFLOAD_KEEP_CRC | \
574 DEV_RX_OFFLOAD_VLAN_EXTEND | \
575 DEV_RX_OFFLOAD_TCP_LRO | \
576 DEV_RX_OFFLOAD_SCATTER | \
577 DEV_RX_OFFLOAD_RSS_HASH)
579 #define MAX_TABLE_SUPPORT 4
580 #define MAX_DIR_SUPPORT 2
581 struct bnxt_dmabuf_info {
583 int fd[MAX_DIR_SUPPORT][MAX_TABLE_SUPPORT];
586 #define BNXT_HWRM_SHORT_REQ_LEN sizeof(struct hwrm_short_input)
588 struct bnxt_flow_stat_info {
591 struct bnxt_ctx_mem_buf_info rx_fc_in_tbl;
592 struct bnxt_ctx_mem_buf_info rx_fc_out_tbl;
593 struct bnxt_ctx_mem_buf_info tx_fc_in_tbl;
594 struct bnxt_ctx_mem_buf_info tx_fc_out_tbl;
600 struct rte_eth_dev *eth_dev;
601 struct rte_pci_device *pdev;
605 #define BNXT_FLAG_REGISTERED BIT(0)
606 #define BNXT_FLAG_VF BIT(1)
607 #define BNXT_FLAG_PORT_STATS BIT(2)
608 #define BNXT_FLAG_JUMBO BIT(3)
609 #define BNXT_FLAG_SHORT_CMD BIT(4)
610 #define BNXT_FLAG_UPDATE_HASH BIT(5)
611 #define BNXT_FLAG_PTP_SUPPORTED BIT(6)
612 #define BNXT_FLAG_MULTI_HOST BIT(7)
613 #define BNXT_FLAG_EXT_RX_PORT_STATS BIT(8)
614 #define BNXT_FLAG_EXT_TX_PORT_STATS BIT(9)
615 #define BNXT_FLAG_KONG_MB_EN BIT(10)
616 #define BNXT_FLAG_TRUSTED_VF_EN BIT(11)
617 #define BNXT_FLAG_DFLT_VNIC_SET BIT(12)
618 #define BNXT_FLAG_THOR_CHIP BIT(13)
619 #define BNXT_FLAG_STINGRAY BIT(14)
620 #define BNXT_FLAG_FW_RESET BIT(15)
621 #define BNXT_FLAG_FATAL_ERROR BIT(16)
622 #define BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE BIT(17)
623 #define BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED BIT(18)
624 #define BNXT_FLAG_EXT_STATS_SUPPORTED BIT(19)
625 #define BNXT_FLAG_NEW_RM BIT(20)
626 #define BNXT_FLAG_NPAR_PF BIT(21)
627 #define BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS BIT(22)
628 #define BNXT_FLAG_FC_THREAD BIT(23)
629 #define BNXT_FLAG_RX_VECTOR_PKT_MODE BIT(24)
630 #define BNXT_FLAG_FLOW_XSTATS_EN BIT(25)
631 #define BNXT_FLAG_DFLT_MAC_SET BIT(26)
632 #define BNXT_FLAG_TRUFLOW_EN BIT(27)
633 #define BNXT_FLAG_GFID_ENABLE BIT(28)
634 #define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF))
635 #define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF)
636 #define BNXT_NPAR(bp) ((bp)->flags & BNXT_FLAG_NPAR_PF)
637 #define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST)
638 #define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
639 #define BNXT_USE_CHIMP_MB 0 //For non-CFA commands, everything uses Chimp.
640 #define BNXT_USE_KONG(bp) ((bp)->flags & BNXT_FLAG_KONG_MB_EN)
641 #define BNXT_VF_IS_TRUSTED(bp) ((bp)->flags & BNXT_FLAG_TRUSTED_VF_EN)
642 #define BNXT_CHIP_THOR(bp) ((bp)->flags & BNXT_FLAG_THOR_CHIP)
643 #define BNXT_STINGRAY(bp) ((bp)->flags & BNXT_FLAG_STINGRAY)
644 #define BNXT_HAS_NQ(bp) BNXT_CHIP_THOR(bp)
645 #define BNXT_HAS_RING_GRPS(bp) (!BNXT_CHIP_THOR(bp))
646 #define BNXT_FLOW_XSTATS_EN(bp) ((bp)->flags & BNXT_FLAG_FLOW_XSTATS_EN)
647 #define BNXT_HAS_DFLT_MAC_SET(bp) ((bp)->flags & BNXT_FLAG_DFLT_MAC_SET)
648 #define BNXT_TRUFLOW_EN(bp) ((bp)->flags & BNXT_FLAG_TRUFLOW_EN)
649 #define BNXT_GFID_ENABLED(bp) ((bp)->flags & BNXT_FLAG_GFID_ENABLE)
652 #define BNXT_FW_CAP_HOT_RESET BIT(0)
653 #define BNXT_FW_CAP_IF_CHANGE BIT(1)
654 #define BNXT_FW_CAP_ERROR_RECOVERY BIT(2)
655 #define BNXT_FW_CAP_ERR_RECOVER_RELOAD BIT(3)
656 #define BNXT_FW_CAP_ADV_FLOW_MGMT BIT(5)
657 #define BNXT_FW_CAP_ADV_FLOW_COUNTERS BIT(6)
658 #define BNXT_FW_CAP_HCOMM_FW_STATUS BIT(7)
660 pthread_mutex_t flow_lock;
662 uint32_t vnic_cap_flags;
663 #define BNXT_VNIC_CAP_COS_CLASSIFY BIT(0)
664 unsigned int rx_nr_rings;
665 unsigned int rx_cp_nr_rings;
666 unsigned int rx_num_qs_per_vnic;
667 struct bnxt_rx_queue **rx_queues;
668 const void *rx_mem_zone;
669 struct rx_port_stats *hw_rx_port_stats;
670 rte_iova_t hw_rx_port_stats_map;
671 struct rx_port_stats_ext *hw_rx_port_stats_ext;
672 rte_iova_t hw_rx_port_stats_ext_map;
673 uint16_t fw_rx_port_stats_ext_size;
675 unsigned int tx_nr_rings;
676 unsigned int tx_cp_nr_rings;
677 struct bnxt_tx_queue **tx_queues;
678 const void *tx_mem_zone;
679 struct tx_port_stats *hw_tx_port_stats;
680 rte_iova_t hw_tx_port_stats_map;
681 struct tx_port_stats_ext *hw_tx_port_stats_ext;
682 rte_iova_t hw_tx_port_stats_ext_map;
683 uint16_t fw_tx_port_stats_ext_size;
685 /* Default completion ring */
686 struct bnxt_cp_ring_info *async_cp_ring;
687 struct bnxt_cp_ring_info *rxtx_nq_ring;
688 uint32_t max_ring_grps;
689 struct bnxt_ring_grp_info *grp_info;
691 unsigned int nr_vnics;
693 #define BNXT_GET_DEFAULT_VNIC(bp) (&(bp)->vnic_info[0])
694 struct bnxt_vnic_info *vnic_info;
695 STAILQ_HEAD(, bnxt_vnic_info) free_vnic_list;
697 struct bnxt_filter_info *filter_info;
698 STAILQ_HEAD(, bnxt_filter_info) free_filter_list;
700 struct bnxt_irq *irq_tbl;
702 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
704 uint16_t chimp_cmd_seq;
705 uint16_t kong_cmd_seq;
706 void *hwrm_cmd_resp_addr;
707 rte_iova_t hwrm_cmd_resp_dma_addr;
708 void *hwrm_short_cmd_req_addr;
709 rte_iova_t hwrm_short_cmd_req_dma_addr;
710 rte_spinlock_t hwrm_lock;
711 pthread_mutex_t def_cp_lock;
712 uint16_t max_req_len;
713 uint16_t max_resp_len;
714 uint16_t hwrm_max_ext_req_len;
716 /* default command timeout value of 500ms */
717 #define DFLT_HWRM_CMD_TIMEOUT 500000
718 /* short command timeout value of 50ms */
719 #define SHORT_HWRM_CMD_TIMEOUT 50000
720 /* default HWRM request timeout value */
721 uint32_t hwrm_cmd_timeout;
723 struct bnxt_link_info *link_info;
724 struct bnxt_cos_queue_info *rx_cos_queue;
725 struct bnxt_cos_queue_info *tx_cos_queue;
726 uint8_t tx_cosq_id[BNXT_COS_QUEUE_COUNT];
733 uint16_t max_rsscos_ctx;
734 uint16_t max_cp_rings;
735 uint16_t max_tx_rings;
736 uint16_t max_rx_rings;
737 #define MAX_STINGRAY_RINGS 128U
738 /* For sake of symmetry, max Tx rings == max Rx rings, one stat ctx for each */
739 #define BNXT_MAX_RX_RINGS(bp) \
740 (BNXT_STINGRAY(bp) ? RTE_MIN(RTE_MIN(bp->max_rx_rings / 2U, \
741 MAX_STINGRAY_RINGS), \
742 bp->max_stat_ctx / 2U) : \
743 RTE_MIN(bp->max_rx_rings / 2U, \
744 bp->max_stat_ctx / 2U))
745 #define BNXT_MAX_TX_RINGS(bp) \
746 (RTE_MIN((bp)->max_tx_rings, BNXT_MAX_RX_RINGS(bp)))
748 #define BNXT_MAX_RINGS(bp) \
749 (RTE_MIN((((bp)->max_cp_rings - BNXT_NUM_ASYNC_CPR(bp)) / 2U), \
750 BNXT_MAX_TX_RINGS(bp)))
752 #define BNXT_MAX_VF_REP_RINGS 8
754 uint16_t max_nq_rings;
756 uint16_t max_rx_em_flows;
758 uint16_t max_stat_ctx;
760 uint16_t first_vf_id;
762 #define BNXT_OUTER_TPID_MASK 0x0000ffff
763 #define BNXT_OUTER_TPID_BD_MASK 0xffff0000
764 #define BNXT_OUTER_TPID_BD_SHFT 16
765 uint32_t outer_tpid_bd;
766 struct bnxt_pf_info *pf;
767 struct bnxt_parent_info *parent;
769 uint8_t vxlan_port_cnt;
770 uint8_t geneve_port_cnt;
772 uint16_t geneve_port;
773 uint16_t vxlan_fw_dst_port_id;
774 uint16_t geneve_fw_dst_port_id;
776 uint32_t hwrm_spec_code;
778 struct bnxt_led_info *leds;
779 struct bnxt_ptp_cfg *ptp_cfg;
780 uint16_t vf_resv_strategy;
781 struct bnxt_ctx_mem_info *ctx;
783 uint16_t fw_reset_min_msecs;
784 uint16_t fw_reset_max_msecs;
785 uint16_t switch_domain_id;
787 struct bnxt_rep_info *rep_info;
788 uint16_t *cfa_code_map;
789 /* Struct to hold adapter error recovery related info */
790 struct bnxt_error_recovery_info *recovery_info;
791 #define BNXT_MARK_TABLE_SZ (sizeof(struct bnxt_mark_info) * 64 * 1024)
792 /* TCAM and EM should be 16-bit only. Other modes not supported. */
793 #define BNXT_FLOW_ID_MASK 0x0000ffff
794 struct bnxt_mark_info *mark_table;
796 #define BNXT_SVIF_INVALID 0xFFFF
801 struct bnxt_dmabuf_info dmabuf;
802 struct bnxt_ulp_context *ulp_ctx;
803 struct bnxt_flow_stat_info *flow_stat;
805 uint16_t max_num_kflows;
806 uint16_t tx_cfa_action;
809 #define BNXT_FC_TIMER 1 /* Timer freq in Sec Flow Counters */
812 * Structure to store private data for each VF representor instance
814 struct bnxt_vf_representor {
815 uint16_t switch_domain_id;
818 #define BNXT_DFLT_VNIC_ID_INVALID 0xFFFF
819 uint16_t dflt_vnic_id;
821 uint16_t vfr_tx_cfa_action;
822 uint32_t rep2vf_flow_id;
823 uint32_t vf2rep_flow_id;
824 /* Private data store of associated PF/Trusted VF */
825 struct rte_eth_dev *parent_dev;
826 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
827 uint8_t dflt_mac_addr[RTE_ETHER_ADDR_LEN];
828 struct bnxt_rx_queue **rx_queues;
829 unsigned int rx_nr_rings;
830 unsigned int tx_nr_rings;
831 uint64_t tx_pkts[BNXT_MAX_VF_REP_RINGS];
832 uint64_t tx_bytes[BNXT_MAX_VF_REP_RINGS];
833 uint64_t rx_pkts[BNXT_MAX_VF_REP_RINGS];
834 uint64_t rx_bytes[BNXT_MAX_VF_REP_RINGS];
835 uint64_t rx_drop_pkts[BNXT_MAX_VF_REP_RINGS];
836 uint64_t rx_drop_bytes[BNXT_MAX_VF_REP_RINGS];
839 struct bnxt_vf_rep_tx_queue {
840 struct bnxt_tx_queue *txq;
841 struct bnxt_vf_representor *bp;
844 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
845 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
846 bool exp_link_status);
847 int bnxt_rcv_msg_from_vf(struct bnxt *bp, uint16_t vf_id, void *msg);
848 int is_bnxt_in_error(struct bnxt *bp);
850 int bnxt_map_fw_health_status_regs(struct bnxt *bp);
851 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index);
852 void bnxt_schedule_fw_health_check(struct bnxt *bp);
854 bool is_bnxt_supported(struct rte_eth_dev *dev);
855 bool bnxt_stratus_device(struct bnxt *bp);
856 void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
857 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp);
858 int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
859 int wait_to_complete);
861 extern const struct rte_flow_ops bnxt_flow_ops;
863 #define bnxt_acquire_flow_lock(bp) \
864 pthread_mutex_lock(&(bp)->flow_lock)
866 #define bnxt_release_flow_lock(bp) \
867 pthread_mutex_unlock(&(bp)->flow_lock)
869 #define BNXT_VALID_VNIC_OR_RET(bp, vnic_id) do { \
870 if ((vnic_id) >= (bp)->max_vnics) { \
871 rte_flow_error_set(error, \
873 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, \
875 "Group id is invalid!"); \
881 #define BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev) \
882 ((eth_dev)->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
884 extern int bnxt_logtype_driver;
885 #define PMD_DRV_LOG_RAW(level, fmt, args...) \
886 rte_log(RTE_LOG_ ## level, bnxt_logtype_driver, "%s(): " fmt, \
889 #define PMD_DRV_LOG(level, fmt, args...) \
890 PMD_DRV_LOG_RAW(level, fmt, ## args)
892 extern const struct rte_flow_ops bnxt_ulp_rte_flow_ops;
893 int32_t bnxt_ulp_init(struct bnxt *bp);
894 void bnxt_ulp_deinit(struct bnxt *bp);
895 int32_t bnxt_ulp_create_df_rules(struct bnxt *bp);
896 void bnxt_ulp_destroy_df_rules(struct bnxt *bp, bool global);
898 uint16_t bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type);
899 uint16_t bnxt_get_svif(uint16_t port_id, bool func_svif,
900 enum bnxt_ulp_intf_type type);
901 uint16_t bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type);
902 uint16_t bnxt_get_parif(uint16_t port, enum bnxt_ulp_intf_type type);
903 uint16_t bnxt_get_phy_port_id(uint16_t port);
904 uint16_t bnxt_get_vport(uint16_t port);
905 enum bnxt_ulp_intf_type
906 bnxt_get_interface_type(uint16_t port);
907 int bnxt_vf_rep_dev_start_op(struct rte_eth_dev *eth_dev);
909 void bnxt_cancel_fc_thread(struct bnxt *bp);
910 void bnxt_flow_cnt_alarm_cb(void *arg);
911 int bnxt_flow_stats_req(struct bnxt *bp);
912 int bnxt_flow_stats_cnt(struct bnxt *bp);
913 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp);
916 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
917 enum rte_filter_type filter_type,
918 enum rte_filter_op filter_op, void *arg);