4 * Copyright(c) Broadcom Limited.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Broadcom Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 #include <sys/queue.h>
42 #include <rte_bus_pci.h>
43 #include <rte_ethdev.h>
44 #include <rte_memory.h>
45 #include <rte_lcore.h>
46 #include <rte_spinlock.h>
51 #define BNXT_MAX_MTU 9500
52 #define VLAN_TAG_SIZE 4
53 #define BNXT_MAX_LED 4
55 struct bnxt_led_info {
60 uint16_t led_state_caps;
61 #define BNXT_LED_ALT_BLINK_CAP(x) ((x) & \
62 rte_cpu_to_le_16(HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT))
64 uint16_t led_color_caps;
72 uint16_t led_blink_on;
73 uint16_t led_blink_off;
78 #define BNXT_LED_DFLT_ENA \
79 (HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID | \
80 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE | \
81 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON | \
82 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF | \
83 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID)
85 #define BNXT_LED_DFLT_ENA_SHIFT 6
87 #define BNXT_LED_DFLT_ENABLES(x) \
88 rte_cpu_to_le_32(BNXT_LED_DFLT_ENA << (BNXT_LED_DFLT_ENA_SHIFT * (x)))
90 enum bnxt_hw_context {
92 HW_CONTEXT_IS_RSS = 1,
93 HW_CONTEXT_IS_COS = 2,
97 struct bnxt_vlan_table_entry {
100 } __attribute__((packed));
102 struct bnxt_vlan_antispoof_table_entry {
106 } __attribute__((packed));
108 struct bnxt_child_vf_info {
110 struct bnxt_vlan_table_entry *vlan_table;
111 struct bnxt_vlan_antispoof_table_entry *vlan_as_table;
112 STAILQ_HEAD(, bnxt_filter_info) filter;
113 uint32_t func_cfg_flags;
116 uint16_t max_tx_rate;
119 uint8_t mac_spoof_en;
120 uint8_t vlan_spoof_en;
125 struct bnxt_pf_info {
126 #define BNXT_FIRST_PF_FID 1
127 #define BNXT_MAX_VFS(bp) (bp->pf.max_vfs)
128 #define BNXT_FIRST_VF_FID 128
129 #define BNXT_PF_RINGS_USED(bp) bnxt_get_num_queues(bp)
130 #define BNXT_PF_RINGS_AVAIL(bp) (bp->pf.max_cp_rings - BNXT_PF_RINGS_USED(bp))
132 uint16_t first_vf_id;
135 uint32_t func_cfg_flags;
137 rte_iova_t vf_req_buf_dma_addr;
138 uint32_t vf_req_fwd[8];
139 uint16_t total_vnics;
140 struct bnxt_child_vf_info *vf_info;
141 #define BNXT_EVB_MODE_NONE 0
142 #define BNXT_EVB_MODE_VEB 1
143 #define BNXT_EVB_MODE_VEPA 2
147 /* Max wait time is 10 * 100ms = 1s */
148 #define BNXT_LINK_WAIT_CNT 10
149 #define BNXT_LINK_WAIT_INTERVAL 100
150 struct bnxt_link_info {
153 uint8_t phy_link_status;
161 #define PHY_VER_LEN 3
162 uint8_t phy_ver[PHY_VER_LEN];
164 uint16_t support_speeds;
165 uint16_t auto_link_speed;
166 uint16_t auto_link_speed_mask;
167 uint32_t preemphasis;
172 #define BNXT_COS_QUEUE_COUNT 8
173 struct bnxt_cos_queue_info {
179 STAILQ_ENTRY(rte_flow) next;
180 struct bnxt_filter_info *filter;
181 struct bnxt_vnic_info *vnic;
184 struct bnxt_ptp_cfg {
185 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400
186 #define BNXT_GRCPF_REG_SYNC_TIME 0x480
187 #define BNXT_CYCLECOUNTER_MASK 0xffffffffffffffffULL
188 struct rte_timecounter tc;
189 struct rte_timecounter tx_tstamp_tc;
190 struct rte_timecounter rx_tstamp_tc;
192 #define BNXT_MAX_TX_TS 1
194 #define BNXT_PTP_MSG_SYNC (1 << 0)
195 #define BNXT_PTP_MSG_DELAY_REQ (1 << 1)
196 #define BNXT_PTP_MSG_PDELAY_REQ (1 << 2)
197 #define BNXT_PTP_MSG_PDELAY_RESP (1 << 3)
198 #define BNXT_PTP_MSG_FOLLOW_UP (1 << 8)
199 #define BNXT_PTP_MSG_DELAY_RESP (1 << 9)
200 #define BNXT_PTP_MSG_PDELAY_RESP_FOLLOW_UP (1 << 10)
201 #define BNXT_PTP_MSG_ANNOUNCE (1 << 11)
202 #define BNXT_PTP_MSG_SIGNALING (1 << 12)
203 #define BNXT_PTP_MSG_MANAGEMENT (1 << 13)
204 #define BNXT_PTP_MSG_EVENTS (BNXT_PTP_MSG_SYNC | \
205 BNXT_PTP_MSG_DELAY_REQ | \
206 BNXT_PTP_MSG_PDELAY_REQ | \
207 BNXT_PTP_MSG_PDELAY_RESP)
208 uint8_t tx_tstamp_en:1;
211 #define BNXT_PTP_RX_TS_L 0
212 #define BNXT_PTP_RX_TS_H 1
213 #define BNXT_PTP_RX_SEQ 2
214 #define BNXT_PTP_RX_FIFO 3
215 #define BNXT_PTP_RX_FIFO_PENDING 0x1
216 #define BNXT_PTP_RX_FIFO_ADV 4
217 #define BNXT_PTP_RX_REGS 5
219 #define BNXT_PTP_TX_TS_L 0
220 #define BNXT_PTP_TX_TS_H 1
221 #define BNXT_PTP_TX_SEQ 2
222 #define BNXT_PTP_TX_FIFO 3
223 #define BNXT_PTP_TX_FIFO_EMPTY 0x2
224 #define BNXT_PTP_TX_REGS 4
225 uint32_t rx_regs[BNXT_PTP_RX_REGS];
226 uint32_t rx_mapped_regs[BNXT_PTP_RX_REGS];
227 uint32_t tx_regs[BNXT_PTP_TX_REGS];
228 uint32_t tx_mapped_regs[BNXT_PTP_TX_REGS];
231 #define BNXT_HWRM_SHORT_REQ_LEN sizeof(struct hwrm_short_input)
235 struct rte_eth_dev *eth_dev;
236 struct rte_eth_rss_conf rss_conf;
237 struct rte_pci_device *pdev;
240 #define BNXT_FLAG_REGISTERED (1 << 0)
241 #define BNXT_FLAG_VF (1 << 1)
242 #define BNXT_FLAG_PORT_STATS (1 << 2)
243 #define BNXT_FLAG_JUMBO (1 << 3)
244 #define BNXT_FLAG_SHORT_CMD (1 << 4)
245 #define BNXT_FLAG_UPDATE_HASH (1 << 5)
246 #define BNXT_FLAG_PTP_SUPPORTED (1 << 6)
247 #define BNXT_FLAG_MULTI_HOST (1 << 7)
248 #define BNXT_FLAG_INIT_DONE (1 << 31)
249 #define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF))
250 #define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF)
251 #define BNXT_NPAR(bp) ((bp)->port_partition_type)
252 #define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST)
253 #define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
255 unsigned int rx_nr_rings;
256 unsigned int rx_cp_nr_rings;
257 struct bnxt_rx_queue **rx_queues;
258 const void *rx_mem_zone;
259 struct rx_port_stats *hw_rx_port_stats;
260 rte_iova_t hw_rx_port_stats_map;
262 unsigned int tx_nr_rings;
263 unsigned int tx_cp_nr_rings;
264 struct bnxt_tx_queue **tx_queues;
265 const void *tx_mem_zone;
266 struct tx_port_stats *hw_tx_port_stats;
267 rte_iova_t hw_tx_port_stats_map;
269 /* Default completion ring */
270 struct bnxt_cp_ring_info *def_cp_ring;
271 uint32_t max_ring_grps;
272 struct bnxt_ring_grp_info *grp_info;
274 unsigned int nr_vnics;
276 struct bnxt_vnic_info *vnic_info;
277 STAILQ_HEAD(, bnxt_vnic_info) free_vnic_list;
279 struct bnxt_filter_info *filter_info;
280 STAILQ_HEAD(, bnxt_filter_info) free_filter_list;
282 /* VNIC pointer for flow filter (VMDq) pools */
283 #define MAX_FF_POOLS 256
284 STAILQ_HEAD(, bnxt_vnic_info) ff_pool[MAX_FF_POOLS];
286 struct bnxt_irq *irq_tbl;
288 #define MAX_NUM_MAC_ADDR 32
289 uint8_t mac_addr[ETHER_ADDR_LEN];
291 uint16_t hwrm_cmd_seq;
292 void *hwrm_cmd_resp_addr;
293 rte_iova_t hwrm_cmd_resp_dma_addr;
294 void *hwrm_short_cmd_req_addr;
295 rte_iova_t hwrm_short_cmd_req_dma_addr;
296 rte_spinlock_t hwrm_lock;
297 uint16_t max_req_len;
298 uint16_t max_resp_len;
300 struct bnxt_link_info link_info;
301 struct bnxt_cos_queue_info cos_queue[BNXT_COS_QUEUE_COUNT];
304 uint8_t dflt_mac_addr[ETHER_ADDR_LEN];
305 uint16_t max_rsscos_ctx;
306 uint16_t max_cp_rings;
307 uint16_t max_tx_rings;
308 uint16_t max_rx_rings;
311 uint16_t max_stat_ctx;
313 struct bnxt_pf_info pf;
314 uint8_t port_partition_type;
316 uint8_t vxlan_port_cnt;
317 uint8_t geneve_port_cnt;
319 uint16_t geneve_port;
320 uint16_t vxlan_fw_dst_port_id;
321 uint16_t geneve_fw_dst_port_id;
323 rte_atomic64_t rx_mbuf_alloc_fail;
325 struct bnxt_led_info leds[BNXT_MAX_LED];
327 struct bnxt_ptp_cfg *ptp_cfg;
330 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete);
331 int bnxt_rcv_msg_from_vf(struct bnxt *bp, uint16_t vf_id, void *msg);
333 #define RX_PROD_AGG_BD_TYPE_RX_PROD_AGG 0x6
335 bool is_bnxt_supported(struct rte_eth_dev *dev);
336 extern const struct rte_flow_ops bnxt_flow_ops;