drivers/net/bnxt/bnxt.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #ifndef _BNXT_H_
   7 #define _BNXT_H_
   8
   9 #include <inttypes.h>
  10 #include <stdbool.h>
  11 #include <sys/queue.h>
  12
  13 #include <rte_pci.h>
  14 #include <rte_bus_pci.h>
  15 #include <rte_ethdev_driver.h>
  16 #include <rte_memory.h>
  17 #include <rte_lcore.h>
  18 #include <rte_spinlock.h>
  19 #include <rte_time.h>
  20
  21 #include "bnxt_cpr.h"
  22 #include "bnxt_util.h"
  23
  24 #include "tf_core.h"
  25 #include "bnxt_ulp.h"
  26 #include "bnxt_tf_common.h"
  27
  28 /* Vendor ID */
  29 #define PCI_VENDOR_ID_BROADCOM          0x14E4
  30
  31 /* Device IDs */
  32 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
  33 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
  34 #define BROADCOM_DEV_ID_STRATUS_NIC     0x1614
  35 #define BROADCOM_DEV_ID_57414_VF        0x16c1
  36 #define BROADCOM_DEV_ID_57301           0x16c8
  37 #define BROADCOM_DEV_ID_57302           0x16c9
  38 #define BROADCOM_DEV_ID_57304_PF        0x16ca
  39 #define BROADCOM_DEV_ID_57304_VF        0x16cb
  40 #define BROADCOM_DEV_ID_57417_MF        0x16cc
  41 #define BROADCOM_DEV_ID_NS2             0x16cd
  42 #define BROADCOM_DEV_ID_57311           0x16ce
  43 #define BROADCOM_DEV_ID_57312           0x16cf
  44 #define BROADCOM_DEV_ID_57402           0x16d0
  45 #define BROADCOM_DEV_ID_57404           0x16d1
  46 #define BROADCOM_DEV_ID_57406_PF        0x16d2
  47 #define BROADCOM_DEV_ID_57406_VF        0x16d3
  48 #define BROADCOM_DEV_ID_57402_MF        0x16d4
  49 #define BROADCOM_DEV_ID_57407_RJ45      0x16d5
  50 #define BROADCOM_DEV_ID_57412           0x16d6
  51 #define BROADCOM_DEV_ID_57414           0x16d7
  52 #define BROADCOM_DEV_ID_57416_RJ45      0x16d8
  53 #define BROADCOM_DEV_ID_57417_RJ45      0x16d9
  54 #define BROADCOM_DEV_ID_5741X_VF        0x16dc
  55 #define BROADCOM_DEV_ID_57412_MF        0x16de
  56 #define BROADCOM_DEV_ID_57314           0x16df
  57 #define BROADCOM_DEV_ID_57317_RJ45      0x16e0
  58 #define BROADCOM_DEV_ID_5731X_VF        0x16e1
  59 #define BROADCOM_DEV_ID_57417_SFP       0x16e2
  60 #define BROADCOM_DEV_ID_57416_SFP       0x16e3
  61 #define BROADCOM_DEV_ID_57317_SFP       0x16e4
  62 #define BROADCOM_DEV_ID_57404_MF        0x16e7
  63 #define BROADCOM_DEV_ID_57406_MF        0x16e8
  64 #define BROADCOM_DEV_ID_57407_SFP       0x16e9
  65 #define BROADCOM_DEV_ID_57407_MF        0x16ea
  66 #define BROADCOM_DEV_ID_57414_MF        0x16ec
  67 #define BROADCOM_DEV_ID_57416_MF        0x16ee
  68 #define BROADCOM_DEV_ID_57508           0x1750
  69 #define BROADCOM_DEV_ID_57504           0x1751
  70 #define BROADCOM_DEV_ID_57502           0x1752
  71 #define BROADCOM_DEV_ID_57508_MF1       0x1800
  72 #define BROADCOM_DEV_ID_57504_MF1       0x1801
  73 #define BROADCOM_DEV_ID_57502_MF1       0x1802
  74 #define BROADCOM_DEV_ID_57508_MF2       0x1803
  75 #define BROADCOM_DEV_ID_57504_MF2       0x1804
  76 #define BROADCOM_DEV_ID_57502_MF2       0x1805
  77 #define BROADCOM_DEV_ID_57500_VF1       0x1806
  78 #define BROADCOM_DEV_ID_57500_VF2       0x1807
  79 #define BROADCOM_DEV_ID_58802           0xd802
  80 #define BROADCOM_DEV_ID_58804           0xd804
  81 #define BROADCOM_DEV_ID_58808           0x16f0
  82 #define BROADCOM_DEV_ID_58802_VF        0xd800
  83
  84 #define BROADCOM_DEV_957508_N2100       0x5208
  85 #define IS_BNXT_DEV_957508_N2100(bp)    \
  86         ((bp)->pdev->id.subsystem_device_id == BROADCOM_DEV_957508_N2100)
  87
  88 #define BNXT_MAX_MTU            9574
  89 #define VLAN_TAG_SIZE           4
  90 #define BNXT_NUM_VLANS          2
  91 #define BNXT_MAX_PKT_LEN        (BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +\
  92                                  RTE_ETHER_CRC_LEN +\
  93                                  (BNXT_NUM_VLANS * VLAN_TAG_SIZE))
  94 /* FW adds extra 4 bytes for FCS */
  95 #define BNXT_VNIC_MRU(mtu)\
  96         ((mtu) + RTE_ETHER_HDR_LEN + VLAN_TAG_SIZE * BNXT_NUM_VLANS)
  97 #define BNXT_VF_RSV_NUM_RSS_CTX 1
  98 #define BNXT_VF_RSV_NUM_L2_CTX  4
  99 /* TODO: For now, do not support VMDq/RFS on VFs. */
 100 #define BNXT_VF_RSV_NUM_VNIC    1
 101 #define BNXT_MAX_LED            4
 102 #define BNXT_MIN_RING_DESC      16
 103 #define BNXT_MAX_TX_RING_DESC   4096
 104 #define BNXT_MAX_RX_RING_DESC   8192
 105 #define BNXT_DB_SIZE            0x80
 106
 107 #define TPA_MAX_AGGS            64
 108 #define TPA_MAX_AGGS_TH         1024
 109
 110 #define TPA_MAX_NUM_SEGS        32
 111 #define TPA_MAX_SEGS_TH         8 /* 32 segments in 4-segment units */
 112 #define TPA_MAX_SEGS            5 /* 32 segments in log2 units */
 113
 114 #define BNXT_TPA_MAX_AGGS(bp) \
 115         (BNXT_CHIP_THOR(bp) ? TPA_MAX_AGGS_TH : \
 116                              TPA_MAX_AGGS)
 117
 118 #define BNXT_TPA_MAX_SEGS(bp) \
 119         (BNXT_CHIP_THOR(bp) ? TPA_MAX_SEGS_TH : \
 120                               TPA_MAX_SEGS)
 121
 122 #ifdef RTE_ARCH_ARM64
 123 #define BNXT_NUM_ASYNC_CPR(bp) (BNXT_STINGRAY(bp) ? 0 : 1)
 124 #else
 125 #define BNXT_NUM_ASYNC_CPR(bp) 1
 126 #endif
 127
 128 /* In FreeBSD OS, nic_uio driver does not support interrupts */
 129 #ifdef RTE_EXEC_ENV_FREEBSD
 130 #ifdef BNXT_NUM_ASYNC_CPR
 131 #undef BNXT_NUM_ASYNC_CPR
 132 #endif
 133 #define BNXT_NUM_ASYNC_CPR(bp)  0
 134 #endif
 135
 136 #define BNXT_MISC_VEC_ID               RTE_INTR_VEC_ZERO_OFFSET
 137 #define BNXT_RX_VEC_START              RTE_INTR_VEC_RXTX_OFFSET
 138
 139 /* Chimp Communication Channel */
 140 #define GRCPF_REG_CHIMP_CHANNEL_OFFSET          0x0
 141 #define GRCPF_REG_CHIMP_COMM_TRIGGER            0x100
 142 /* Kong Communication Channel */
 143 #define GRCPF_REG_KONG_CHANNEL_OFFSET           0xA00
 144 #define GRCPF_REG_KONG_COMM_TRIGGER             0xB00
 145
 146 #define BNXT_INT_LAT_TMR_MIN                    75
 147 #define BNXT_INT_LAT_TMR_MAX                    150
 148 #define BNXT_NUM_CMPL_AGGR_INT                  36
 149 #define BNXT_CMPL_AGGR_DMA_TMR                  37
 150 #define BNXT_NUM_CMPL_DMA_AGGR                  36
 151 #define BNXT_CMPL_AGGR_DMA_TMR_DURING_INT       50
 152 #define BNXT_NUM_CMPL_DMA_AGGR_DURING_INT       12
 153
 154 #define BNXT_DEFAULT_VNIC_STATE_MASK                    \
 155         HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK
 156 #define BNXT_DEFAULT_VNIC_STATE_SFT                     \
 157         HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT
 158 #define BNXT_DEFAULT_VNIC_ALLOC                         \
 159         HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC
 160 #define BNXT_DEFAULT_VNIC_FREE                          \
 161         HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE
 162 #define BNXT_DEFAULT_VNIC_CHANGE_PF_ID_MASK             \
 163         HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK
 164 #define BNXT_DEFAULT_VNIC_CHANGE_PF_ID_SFT              \
 165         HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT
 166 #define BNXT_DEFAULT_VNIC_CHANGE_VF_ID_MASK             \
 167         HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK
 168 #define BNXT_DEFAULT_VNIC_CHANGE_VF_ID_SFT              \
 169         HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT
 170
 171 struct bnxt_led_info {
 172         uint8_t      num_leds;
 173         uint8_t      led_id;
 174         uint8_t      led_type;
 175         uint8_t      led_group_id;
 176         uint8_t      unused;
 177         uint16_t  led_state_caps;
 178 #define BNXT_LED_ALT_BLINK_CAP(x)       ((x) &  \
 179         rte_cpu_to_le_16(HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT))
 180
 181         uint16_t  led_color_caps;
 182 };
 183
 184 struct bnxt_led_cfg {
 185         uint8_t led_id;
 186         uint8_t led_state;
 187         uint8_t led_color;
 188         uint8_t unused;
 189         uint16_t led_blink_on;
 190         uint16_t led_blink_off;
 191         uint8_t led_group_id;
 192         uint8_t rsvd;
 193 };
 194
 195 #define BNXT_LED_DFLT_ENA                               \
 196         (HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID |             \
 197          HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE |          \
 198          HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON |       \
 199          HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF |      \
 200          HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID)
 201
 202 #define BNXT_LED_DFLT_ENA_SHIFT         6
 203
 204 #define BNXT_LED_DFLT_ENABLES(x)                        \
 205         rte_cpu_to_le_32(BNXT_LED_DFLT_ENA << (BNXT_LED_DFLT_ENA_SHIFT * (x)))
 206
 207 struct bnxt_vlan_table_entry {
 208         uint16_t                tpid;
 209         uint16_t                vid;
 210 } __rte_packed;
 211
 212 struct bnxt_vlan_antispoof_table_entry {
 213         uint16_t                tpid;
 214         uint16_t                vid;
 215         uint16_t                mask;
 216 } __rte_packed;
 217
 218 struct bnxt_child_vf_info {
 219         void                    *req_buf;
 220         struct bnxt_vlan_table_entry    *vlan_table;
 221         struct bnxt_vlan_antispoof_table_entry  *vlan_as_table;
 222         STAILQ_HEAD(, bnxt_filter_info) filter;
 223         uint32_t                func_cfg_flags;
 224         uint32_t                l2_rx_mask;
 225         uint16_t                fid;
 226         uint16_t                max_tx_rate;
 227         uint16_t                dflt_vlan;
 228         uint16_t                vlan_count;
 229         uint8_t                 mac_spoof_en;
 230         uint8_t                 vlan_spoof_en;
 231         bool                    random_mac;
 232         bool                    persist_stats;
 233 };
 234
 235 struct bnxt_parent_info {
 236 #define BNXT_PF_FID_INVALID     0xFFFF
 237         uint16_t                fid;
 238         uint16_t                vnic;
 239         uint16_t                port_id;
 240         uint8_t                 mac_addr[RTE_ETHER_ADDR_LEN];
 241 };
 242
 243 struct bnxt_pf_info {
 244 #define BNXT_FIRST_PF_FID       1
 245 #define BNXT_MAX_VFS(bp)        ((bp)->pf->max_vfs)
 246 #define BNXT_MAX_VF_REPS        64
 247 #define BNXT_TOTAL_VFS(bp)      ((bp)->pf->total_vfs)
 248 #define BNXT_FIRST_VF_FID       128
 249 #define BNXT_PF_RINGS_USED(bp)  bnxt_get_num_queues(bp)
 250 #define BNXT_PF_RINGS_AVAIL(bp) ((bp)->pf->max_cp_rings - \
 251                                  BNXT_PF_RINGS_USED(bp))
 252         uint16_t                port_id;
 253         uint16_t                first_vf_id;
 254         uint16_t                active_vfs;
 255         uint16_t                max_vfs;
 256         uint16_t                total_vfs; /* Total VFs possible.
 257                                             * Not necessarily enabled.
 258                                             */
 259         uint32_t                func_cfg_flags;
 260         void                    *vf_req_buf;
 261         rte_iova_t              vf_req_buf_dma_addr;
 262         uint32_t                vf_req_fwd[8];
 263         uint16_t                total_vnics;
 264         struct bnxt_child_vf_info       *vf_info;
 265 #define BNXT_EVB_MODE_NONE      0
 266 #define BNXT_EVB_MODE_VEB       1
 267 #define BNXT_EVB_MODE_VEPA      2
 268         uint8_t                 evb_mode;
 269 };
 270
 271 /* Max wait time for link up is 10s and link down is 500ms */
 272 #define BNXT_LINK_UP_WAIT_CNT   200
 273 #define BNXT_LINK_DOWN_WAIT_CNT 10
 274 #define BNXT_LINK_WAIT_INTERVAL 50
 275 struct bnxt_link_info {
 276         uint32_t                phy_flags;
 277         uint8_t                 mac_type;
 278         uint8_t                 phy_link_status;
 279         uint8_t                 loop_back;
 280         uint8_t                 link_up;
 281         uint8_t                 duplex;
 282         uint8_t                 pause;
 283         uint8_t                 force_pause;
 284         uint8_t                 auto_pause;
 285         uint8_t                 auto_mode;
 286 #define PHY_VER_LEN             3
 287         uint8_t                 phy_ver[PHY_VER_LEN];
 288         uint16_t                link_speed;
 289         uint16_t                support_speeds;
 290         uint16_t                auto_link_speed;
 291         uint16_t                force_link_speed;
 292         uint16_t                auto_link_speed_mask;
 293         uint32_t                preemphasis;
 294         uint8_t                 phy_type;
 295         uint8_t                 media_type;
 296 };
 297
 298 #define BNXT_COS_QUEUE_COUNT    8
 299 struct bnxt_cos_queue_info {
 300         uint8_t id;
 301         uint8_t profile;
 302 };
 303
 304 struct rte_flow {
 305         STAILQ_ENTRY(rte_flow) next;
 306         struct bnxt_filter_info *filter;
 307         struct bnxt_vnic_info   *vnic;
 308 };
 309
 310 #define BNXT_PTP_FLAGS_PATH_TX          0x0
 311 #define BNXT_PTP_FLAGS_PATH_RX          0x1
 312 #define BNXT_PTP_FLAGS_CURRENT_TIME     0x2
 313
 314 struct bnxt_ptp_cfg {
 315 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT  0x400
 316 #define BNXT_GRCPF_REG_SYNC_TIME        0x480
 317 #define BNXT_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 318         struct rte_timecounter      tc;
 319         struct rte_timecounter      tx_tstamp_tc;
 320         struct rte_timecounter      rx_tstamp_tc;
 321         struct bnxt             *bp;
 322 #define BNXT_MAX_TX_TS  1
 323         uint16_t                        rxctl;
 324 #define BNXT_PTP_MSG_SYNC                       BIT(0)
 325 #define BNXT_PTP_MSG_DELAY_REQ                  BIT(1)
 326 #define BNXT_PTP_MSG_PDELAY_REQ                 BIT(2)
 327 #define BNXT_PTP_MSG_PDELAY_RESP                BIT(3)
 328 #define BNXT_PTP_MSG_FOLLOW_UP                  BIT(8)
 329 #define BNXT_PTP_MSG_DELAY_RESP                 BIT(9)
 330 #define BNXT_PTP_MSG_PDELAY_RESP_FOLLOW_UP      BIT(10)
 331 #define BNXT_PTP_MSG_ANNOUNCE                   BIT(11)
 332 #define BNXT_PTP_MSG_SIGNALING                  BIT(12)
 333 #define BNXT_PTP_MSG_MANAGEMENT                 BIT(13)
 334 #define BNXT_PTP_MSG_EVENTS             (BNXT_PTP_MSG_SYNC |            \
 335                                          BNXT_PTP_MSG_DELAY_REQ |       \
 336                                          BNXT_PTP_MSG_PDELAY_REQ |      \
 337                                          BNXT_PTP_MSG_PDELAY_RESP)
 338         uint8_t                 tx_tstamp_en:1;
 339         int                     rx_filter;
 340
 341 #define BNXT_PTP_RX_TS_L        0
 342 #define BNXT_PTP_RX_TS_H        1
 343 #define BNXT_PTP_RX_SEQ         2
 344 #define BNXT_PTP_RX_FIFO        3
 345 #define BNXT_PTP_RX_FIFO_PENDING 0x1
 346 #define BNXT_PTP_RX_FIFO_ADV    4
 347 #define BNXT_PTP_RX_REGS        5
 348
 349 #define BNXT_PTP_TX_TS_L        0
 350 #define BNXT_PTP_TX_TS_H        1
 351 #define BNXT_PTP_TX_SEQ         2
 352 #define BNXT_PTP_TX_FIFO        3
 353 #define BNXT_PTP_TX_FIFO_EMPTY   0x2
 354 #define BNXT_PTP_TX_REGS        4
 355         uint32_t                        rx_regs[BNXT_PTP_RX_REGS];
 356         uint32_t                        rx_mapped_regs[BNXT_PTP_RX_REGS];
 357         uint32_t                        tx_regs[BNXT_PTP_TX_REGS];
 358         uint32_t                        tx_mapped_regs[BNXT_PTP_TX_REGS];
 359
 360         /* On Thor, the Rx timestamp is present in the Rx completion record */
 361         uint64_t                        rx_timestamp;
 362 };
 363
 364 struct bnxt_coal {
 365         uint16_t                        num_cmpl_aggr_int;
 366         uint16_t                        num_cmpl_dma_aggr;
 367         uint16_t                        num_cmpl_dma_aggr_during_int;
 368         uint16_t                        int_lat_tmr_max;
 369         uint16_t                        int_lat_tmr_min;
 370         uint16_t                        cmpl_aggr_dma_tmr;
 371         uint16_t                        cmpl_aggr_dma_tmr_during_int;
 372 };
 373
 374 /* 64-bit doorbell */
 375 #define DBR_XID_SFT                             32
 376 #define DBR_PATH_L2                             (0x1ULL << 56)
 377 #define DBR_TYPE_SQ                             (0x0ULL << 60)
 378 #define DBR_TYPE_SRQ                            (0x2ULL << 60)
 379 #define DBR_TYPE_CQ                             (0x4ULL << 60)
 380 #define DBR_TYPE_NQ                             (0xaULL << 60)
 381 #define DBR_TYPE_NQ_ARM                         (0xbULL << 60)
 382
 383 #define BNXT_RSS_TBL_SIZE_THOR          512
 384 #define BNXT_RSS_ENTRIES_PER_CTX_THOR   64
 385 #define BNXT_MAX_RSS_CTXTS_THOR \
 386         (BNXT_RSS_TBL_SIZE_THOR / BNXT_RSS_ENTRIES_PER_CTX_THOR)
 387
 388 #define BNXT_MAX_TC    8
 389 #define BNXT_MAX_QUEUE 8
 390 #define BNXT_MAX_TC_Q  (BNXT_MAX_TC + 1)
 391 #define BNXT_PAGE_SHFT 12
 392 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHFT)
 393 #define MAX_CTX_PAGES  (BNXT_PAGE_SIZE / 8)
 394
 395 #define PTU_PTE_VALID             0x1UL
 396 #define PTU_PTE_LAST              0x2UL
 397 #define PTU_PTE_NEXT_TO_LAST      0x4UL
 398
 399 struct bnxt_ring_mem_info {
 400         int                             nr_pages;
 401         int                             page_size;
 402         uint32_t                        flags;
 403 #define BNXT_RMEM_VALID_PTE_FLAG        1
 404 #define BNXT_RMEM_RING_PTE_FLAG         2
 405
 406         void                            **pg_arr;
 407         rte_iova_t                      *dma_arr;
 408         const struct rte_memzone        *mz;
 409
 410         uint64_t                        *pg_tbl;
 411         rte_iova_t                      pg_tbl_map;
 412         const struct rte_memzone        *pg_tbl_mz;
 413
 414         int                             vmem_size;
 415         void                            **vmem;
 416 };
 417
 418 struct bnxt_ctx_pg_info {
 419         uint32_t        entries;
 420         void            *ctx_pg_arr[MAX_CTX_PAGES];
 421         rte_iova_t      ctx_dma_arr[MAX_CTX_PAGES];
 422         struct bnxt_ring_mem_info ring_mem;
 423 };
 424
 425 struct bnxt_ctx_mem_info {
 426         uint32_t        qp_max_entries;
 427         uint16_t        qp_min_qp1_entries;
 428         uint16_t        qp_max_l2_entries;
 429         uint16_t        qp_entry_size;
 430         uint16_t        srq_max_l2_entries;
 431         uint32_t        srq_max_entries;
 432         uint16_t        srq_entry_size;
 433         uint16_t        cq_max_l2_entries;
 434         uint32_t        cq_max_entries;
 435         uint16_t        cq_entry_size;
 436         uint16_t        vnic_max_vnic_entries;
 437         uint16_t        vnic_max_ring_table_entries;
 438         uint16_t        vnic_entry_size;
 439         uint32_t        stat_max_entries;
 440         uint16_t        stat_entry_size;
 441         uint16_t        tqm_entry_size;
 442         uint32_t        tqm_min_entries_per_ring;
 443         uint32_t        tqm_max_entries_per_ring;
 444         uint32_t        mrav_max_entries;
 445         uint16_t        mrav_entry_size;
 446         uint16_t        tim_entry_size;
 447         uint32_t        tim_max_entries;
 448         uint8_t         tqm_entries_multiple;
 449         uint8_t         tqm_fp_rings_count;
 450
 451         uint32_t        flags;
 452 #define BNXT_CTX_FLAG_INITED    0x01
 453
 454         struct bnxt_ctx_pg_info qp_mem;
 455         struct bnxt_ctx_pg_info srq_mem;
 456         struct bnxt_ctx_pg_info cq_mem;
 457         struct bnxt_ctx_pg_info vnic_mem;
 458         struct bnxt_ctx_pg_info stat_mem;
 459         struct bnxt_ctx_pg_info *tqm_mem[BNXT_MAX_TC_Q];
 460 };
 461
 462 struct bnxt_ctx_mem_buf_info {
 463         void            *va;
 464         rte_iova_t      dma;
 465         uint16_t        ctx_id;
 466         size_t          size;
 467 };
 468
 469 /* Maximum Firmware Reset bail out value in milliseconds */
 470 #define BNXT_MAX_FW_RESET_TIMEOUT       6000
 471 /* Minimum time required for the firmware readiness in milliseconds */
 472 #define BNXT_MIN_FW_READY_TIMEOUT       2000
 473 /* Frequency for the firmware readiness check in milliseconds */
 474 #define BNXT_FW_READY_WAIT_INTERVAL     100
 475
 476 #define US_PER_MS                       1000
 477 #define NS_PER_US                       1000
 478
 479 struct bnxt_error_recovery_info {
 480         /* All units in milliseconds */
 481         uint32_t        driver_polling_freq;
 482         uint32_t        master_func_wait_period;
 483         uint32_t        normal_func_wait_period;
 484         uint32_t        master_func_wait_period_after_reset;
 485         uint32_t        max_bailout_time_after_reset;
 486 #define BNXT_FW_STATUS_REG              0
 487 #define BNXT_FW_HEARTBEAT_CNT_REG       1
 488 #define BNXT_FW_RECOVERY_CNT_REG        2
 489 #define BNXT_FW_RESET_INPROG_REG        3
 490 #define BNXT_FW_STATUS_REG_CNT          4
 491         uint32_t        status_regs[BNXT_FW_STATUS_REG_CNT];
 492         uint32_t        mapped_status_regs[BNXT_FW_STATUS_REG_CNT];
 493         uint32_t        reset_inprogress_reg_mask;
 494 #define BNXT_NUM_RESET_REG      16
 495         uint8_t         reg_array_cnt;
 496         uint32_t        reset_reg[BNXT_NUM_RESET_REG];
 497         uint32_t        reset_reg_val[BNXT_NUM_RESET_REG];
 498         uint8_t         delay_after_reset[BNXT_NUM_RESET_REG];
 499 #define BNXT_FLAG_ERROR_RECOVERY_HOST   BIT(0)
 500 #define BNXT_FLAG_ERROR_RECOVERY_CO_CPU BIT(1)
 501 #define BNXT_FLAG_MASTER_FUNC           BIT(2)
 502 #define BNXT_FLAG_RECOVERY_ENABLED      BIT(3)
 503         uint32_t        flags;
 504
 505         uint32_t        last_heart_beat;
 506         uint32_t        last_reset_counter;
 507 };
 508
 509 /* Frequency for the FUNC_DRV_IF_CHANGE retry in milliseconds */
 510 #define BNXT_IF_CHANGE_RETRY_INTERVAL   50
 511 /* Maximum retry count for FUNC_DRV_IF_CHANGE */
 512 #define BNXT_IF_CHANGE_RETRY_COUNT      40
 513
 514 struct bnxt_mark_info {
 515         uint32_t        mark_id;
 516         bool            valid;
 517 };
 518
 519 struct bnxt_rep_info {
 520         struct rte_eth_dev      *vfr_eth_dev;
 521         pthread_mutex_t         vfr_lock;
 522         pthread_mutex_t         vfr_start_lock;
 523         bool                    conduit_valid;
 524 };
 525
 526 /* address space location of register */
 527 #define BNXT_FW_STATUS_REG_TYPE_MASK    3
 528 /* register is located in PCIe config space */
 529 #define BNXT_FW_STATUS_REG_TYPE_CFG     0
 530 /* register is located in GRC address space */
 531 #define BNXT_FW_STATUS_REG_TYPE_GRC     1
 532 /* register is located in BAR0  */
 533 #define BNXT_FW_STATUS_REG_TYPE_BAR0    2
 534 /* register is located in BAR1  */
 535 #define BNXT_FW_STATUS_REG_TYPE_BAR1    3
 536
 537 #define BNXT_FW_STATUS_REG_TYPE(reg)    ((reg) & BNXT_FW_STATUS_REG_TYPE_MASK)
 538 #define BNXT_FW_STATUS_REG_OFF(reg)     ((reg) & ~BNXT_FW_STATUS_REG_TYPE_MASK)
 539
 540 #define BNXT_GRCP_WINDOW_2_BASE         0x2000
 541 #define BNXT_GRCP_WINDOW_3_BASE         0x3000
 542
 543 #define BNXT_GRCP_BASE_MASK             0xfffff000
 544 #define BNXT_GRCP_OFFSET_MASK           0x00000ffc
 545
 546 #define BNXT_FW_STATUS_HEALTHY          0x8000
 547 #define BNXT_FW_STATUS_SHUTDOWN         0x100000
 548
 549 #define BNXT_ETH_RSS_SUPPORT (  \
 550         ETH_RSS_IPV4 |          \
 551         ETH_RSS_NONFRAG_IPV4_TCP |      \
 552         ETH_RSS_NONFRAG_IPV4_UDP |      \
 553         ETH_RSS_IPV6 |          \
 554         ETH_RSS_NONFRAG_IPV6_TCP |      \
 555         ETH_RSS_NONFRAG_IPV6_UDP)
 556
 557 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 558                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 559                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 560                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 561                                      DEV_TX_OFFLOAD_TCP_TSO | \
 562                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 563                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 564                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 565                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 566                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 567                                      DEV_TX_OFFLOAD_QINQ_INSERT | \
 568                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 569
 570 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 571                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 572                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 573                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 574                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 575                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 576                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 577                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 578                                      DEV_RX_OFFLOAD_VLAN_EXTEND | \
 579                                      DEV_RX_OFFLOAD_TCP_LRO | \
 580                                      DEV_RX_OFFLOAD_SCATTER | \
 581                                      DEV_RX_OFFLOAD_RSS_HASH)
 582
 583 #define  MAX_TABLE_SUPPORT 4
 584 #define  MAX_DIR_SUPPORT   2
 585 struct bnxt_dmabuf_info {
 586         uint32_t entry_num;
 587         int      fd[MAX_DIR_SUPPORT][MAX_TABLE_SUPPORT];
 588 };
 589
 590 #define BNXT_HWRM_SHORT_REQ_LEN         sizeof(struct hwrm_short_input)
 591
 592 struct bnxt_flow_stat_info {
 593         uint16_t                max_fc;
 594         uint16_t                flow_count;
 595         struct bnxt_ctx_mem_buf_info rx_fc_in_tbl;
 596         struct bnxt_ctx_mem_buf_info rx_fc_out_tbl;
 597         struct bnxt_ctx_mem_buf_info tx_fc_in_tbl;
 598         struct bnxt_ctx_mem_buf_info tx_fc_out_tbl;
 599 };
 600
 601 struct bnxt {
 602         void                            *bar0;
 603
 604         struct rte_eth_dev              *eth_dev;
 605         struct rte_pci_device           *pdev;
 606         void                            *doorbell_base;
 607
 608         uint32_t                flags;
 609 #define BNXT_FLAG_REGISTERED            BIT(0)
 610 #define BNXT_FLAG_VF                    BIT(1)
 611 #define BNXT_FLAG_PORT_STATS            BIT(2)
 612 #define BNXT_FLAG_JUMBO                 BIT(3)
 613 #define BNXT_FLAG_SHORT_CMD             BIT(4)
 614 #define BNXT_FLAG_UPDATE_HASH           BIT(5)
 615 #define BNXT_FLAG_PTP_SUPPORTED         BIT(6)
 616 #define BNXT_FLAG_MULTI_HOST            BIT(7)
 617 #define BNXT_FLAG_EXT_RX_PORT_STATS     BIT(8)
 618 #define BNXT_FLAG_EXT_TX_PORT_STATS     BIT(9)
 619 #define BNXT_FLAG_KONG_MB_EN            BIT(10)
 620 #define BNXT_FLAG_TRUSTED_VF_EN         BIT(11)
 621 #define BNXT_FLAG_DFLT_VNIC_SET         BIT(12)
 622 #define BNXT_FLAG_THOR_CHIP             BIT(13)
 623 #define BNXT_FLAG_STINGRAY              BIT(14)
 624 #define BNXT_FLAG_FW_RESET              BIT(15)
 625 #define BNXT_FLAG_FATAL_ERROR           BIT(16)
 626 #define BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE   BIT(17)
 627 #define BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED     BIT(18)
 628 #define BNXT_FLAG_EXT_STATS_SUPPORTED           BIT(19)
 629 #define BNXT_FLAG_NEW_RM                        BIT(20)
 630 #define BNXT_FLAG_NPAR_PF                       BIT(21)
 631 #define BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS         BIT(22)
 632 #define BNXT_FLAG_FC_THREAD                     BIT(23)
 633 #define BNXT_FLAG_RX_VECTOR_PKT_MODE            BIT(24)
 634 #define BNXT_FLAG_FLOW_XSTATS_EN                BIT(25)
 635 #define BNXT_FLAG_DFLT_MAC_SET                  BIT(26)
 636 #define BNXT_FLAG_TRUFLOW_EN                    BIT(27)
 637 #define BNXT_FLAG_GFID_ENABLE                   BIT(28)
 638 #define BNXT_PF(bp)             (!((bp)->flags & BNXT_FLAG_VF))
 639 #define BNXT_VF(bp)             ((bp)->flags & BNXT_FLAG_VF)
 640 #define BNXT_NPAR(bp)           ((bp)->flags & BNXT_FLAG_NPAR_PF)
 641 #define BNXT_MH(bp)             ((bp)->flags & BNXT_FLAG_MULTI_HOST)
 642 #define BNXT_SINGLE_PF(bp)      (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
 643 #define BNXT_USE_CHIMP_MB       0 //For non-CFA commands, everything uses Chimp.
 644 #define BNXT_USE_KONG(bp)       ((bp)->flags & BNXT_FLAG_KONG_MB_EN)
 645 #define BNXT_VF_IS_TRUSTED(bp)  ((bp)->flags & BNXT_FLAG_TRUSTED_VF_EN)
 646 #define BNXT_CHIP_THOR(bp)      ((bp)->flags & BNXT_FLAG_THOR_CHIP)
 647 #define BNXT_STINGRAY(bp)       ((bp)->flags & BNXT_FLAG_STINGRAY)
 648 #define BNXT_HAS_NQ(bp)         BNXT_CHIP_THOR(bp)
 649 #define BNXT_HAS_RING_GRPS(bp)  (!BNXT_CHIP_THOR(bp))
 650 #define BNXT_FLOW_XSTATS_EN(bp) ((bp)->flags & BNXT_FLAG_FLOW_XSTATS_EN)
 651 #define BNXT_HAS_DFLT_MAC_SET(bp)      ((bp)->flags & BNXT_FLAG_DFLT_MAC_SET)
 652 #define BNXT_TRUFLOW_EN(bp)     ((bp)->flags & BNXT_FLAG_TRUFLOW_EN)
 653 #define BNXT_GFID_ENABLED(bp)   ((bp)->flags & BNXT_FLAG_GFID_ENABLE)
 654
 655         uint32_t                fw_cap;
 656 #define BNXT_FW_CAP_HOT_RESET           BIT(0)
 657 #define BNXT_FW_CAP_IF_CHANGE           BIT(1)
 658 #define BNXT_FW_CAP_ERROR_RECOVERY      BIT(2)
 659 #define BNXT_FW_CAP_ERR_RECOVER_RELOAD  BIT(3)
 660 #define BNXT_FW_CAP_ADV_FLOW_MGMT       BIT(5)
 661 #define BNXT_FW_CAP_ADV_FLOW_COUNTERS   BIT(6)
 662 #define BNXT_FW_CAP_HCOMM_FW_STATUS     BIT(7)
 663
 664         pthread_mutex_t         flow_lock;
 665
 666         uint32_t                vnic_cap_flags;
 667 #define BNXT_VNIC_CAP_COS_CLASSIFY      BIT(0)
 668         unsigned int            rx_nr_rings;
 669         unsigned int            rx_cp_nr_rings;
 670         unsigned int            rx_num_qs_per_vnic;
 671         struct bnxt_rx_queue **rx_queues;
 672         const void              *rx_mem_zone;
 673         struct rx_port_stats    *hw_rx_port_stats;
 674         rte_iova_t              hw_rx_port_stats_map;
 675         struct rx_port_stats_ext    *hw_rx_port_stats_ext;
 676         rte_iova_t              hw_rx_port_stats_ext_map;
 677         uint16_t                fw_rx_port_stats_ext_size;
 678
 679         unsigned int            tx_nr_rings;
 680         unsigned int            tx_cp_nr_rings;
 681         struct bnxt_tx_queue **tx_queues;
 682         const void              *tx_mem_zone;
 683         struct tx_port_stats    *hw_tx_port_stats;
 684         rte_iova_t              hw_tx_port_stats_map;
 685         struct tx_port_stats_ext    *hw_tx_port_stats_ext;
 686         rte_iova_t              hw_tx_port_stats_ext_map;
 687         uint16_t                fw_tx_port_stats_ext_size;
 688
 689         /* Default completion ring */
 690         struct bnxt_cp_ring_info        *async_cp_ring;
 691         struct bnxt_cp_ring_info        *rxtx_nq_ring;
 692         uint32_t                max_ring_grps;
 693         struct bnxt_ring_grp_info       *grp_info;
 694
 695         unsigned int            nr_vnics;
 696
 697 #define BNXT_GET_DEFAULT_VNIC(bp)       (&(bp)->vnic_info[0])
 698         struct bnxt_vnic_info   *vnic_info;
 699         STAILQ_HEAD(, bnxt_vnic_info)   free_vnic_list;
 700
 701         struct bnxt_filter_info *filter_info;
 702         STAILQ_HEAD(, bnxt_filter_info) free_filter_list;
 703
 704         struct bnxt_irq         *irq_tbl;
 705
 706         uint8_t                 mac_addr[RTE_ETHER_ADDR_LEN];
 707
 708         uint16_t                        chimp_cmd_seq;
 709         uint16_t                        kong_cmd_seq;
 710         void                            *hwrm_cmd_resp_addr;
 711         rte_iova_t                      hwrm_cmd_resp_dma_addr;
 712         void                            *hwrm_short_cmd_req_addr;
 713         rte_iova_t                      hwrm_short_cmd_req_dma_addr;
 714         rte_spinlock_t                  hwrm_lock;
 715         pthread_mutex_t                 def_cp_lock;
 716         uint16_t                        max_req_len;
 717         uint16_t                        max_resp_len;
 718         uint16_t                        hwrm_max_ext_req_len;
 719
 720          /* default command timeout value of 500ms */
 721 #define DFLT_HWRM_CMD_TIMEOUT           500000
 722          /* short command timeout value of 50ms */
 723 #define SHORT_HWRM_CMD_TIMEOUT          50000
 724         /* default HWRM request timeout value */
 725         uint32_t                        hwrm_cmd_timeout;
 726
 727         struct bnxt_link_info           *link_info;
 728         struct bnxt_cos_queue_info      *rx_cos_queue;
 729         struct bnxt_cos_queue_info      *tx_cos_queue;
 730         uint8_t                 tx_cosq_id[BNXT_COS_QUEUE_COUNT];
 731         uint8_t                 rx_cosq_cnt;
 732         uint8_t                 max_tc;
 733         uint8_t                 max_lltc;
 734         uint8_t                 max_q;
 735
 736         uint16_t                fw_fid;
 737         uint16_t                max_rsscos_ctx;
 738         uint16_t                max_cp_rings;
 739         uint16_t                max_tx_rings;
 740         uint16_t                max_rx_rings;
 741 #define MAX_STINGRAY_RINGS              128U
 742 /* For sake of symmetry, max Tx rings == max Rx rings, one stat ctx for each */
 743 #define BNXT_MAX_RX_RINGS(bp) \
 744         (BNXT_STINGRAY(bp) ? RTE_MIN(RTE_MIN(bp->max_rx_rings / 2U, \
 745                                              MAX_STINGRAY_RINGS), \
 746                                      bp->max_stat_ctx / 2U) : \
 747                                 RTE_MIN(bp->max_rx_rings / 2U, \
 748                                         bp->max_stat_ctx / 2U))
 749 #define BNXT_MAX_TX_RINGS(bp) \
 750         (RTE_MIN((bp)->max_tx_rings, BNXT_MAX_RX_RINGS(bp)))
 751
 752 #define BNXT_MAX_RINGS(bp) \
 753         (RTE_MIN((((bp)->max_cp_rings - BNXT_NUM_ASYNC_CPR(bp)) / 2U), \
 754                  BNXT_MAX_TX_RINGS(bp)))
 755
 756 #define BNXT_MAX_VF_REP_RINGS   8
 757
 758         uint16_t                max_nq_rings;
 759         uint16_t                max_l2_ctx;
 760         uint16_t                max_rx_em_flows;
 761         uint16_t                max_vnics;
 762         uint16_t                max_stat_ctx;
 763         uint16_t                max_tpa_v2;
 764         uint16_t                first_vf_id;
 765         uint16_t                vlan;
 766 #define BNXT_OUTER_TPID_MASK    0x0000ffff
 767 #define BNXT_OUTER_TPID_BD_MASK 0xffff0000
 768 #define BNXT_OUTER_TPID_BD_SHFT 16
 769         uint32_t                outer_tpid_bd;
 770         struct bnxt_pf_info     *pf;
 771         struct bnxt_parent_info *parent;
 772         uint8_t                 port_cnt;
 773         uint8_t                 vxlan_port_cnt;
 774         uint8_t                 geneve_port_cnt;
 775         uint16_t                vxlan_port;
 776         uint16_t                geneve_port;
 777         uint16_t                vxlan_fw_dst_port_id;
 778         uint16_t                geneve_fw_dst_port_id;
 779         uint32_t                fw_ver;
 780         uint32_t                hwrm_spec_code;
 781
 782         struct bnxt_led_info    *leds;
 783         struct bnxt_ptp_cfg     *ptp_cfg;
 784         uint16_t                vf_resv_strategy;
 785         struct bnxt_ctx_mem_info        *ctx;
 786
 787         uint16_t                fw_reset_min_msecs;
 788         uint16_t                fw_reset_max_msecs;
 789         uint16_t                switch_domain_id;
 790         uint16_t                num_reps;
 791         struct bnxt_rep_info    *rep_info;
 792         uint16_t                *cfa_code_map;
 793         /* Struct to hold adapter error recovery related info */
 794         struct bnxt_error_recovery_info *recovery_info;
 795 #define BNXT_MARK_TABLE_SZ      (sizeof(struct bnxt_mark_info)  * 64 * 1024)
 796 /* TCAM and EM should be 16-bit only. Other modes not supported. */
 797 #define BNXT_FLOW_ID_MASK       0x0000ffff
 798         struct bnxt_mark_info   *mark_table;
 799
 800 #define BNXT_SVIF_INVALID       0xFFFF
 801         uint16_t                func_svif;
 802         uint16_t                port_svif;
 803
 804         struct tf               tfp;
 805         struct bnxt_dmabuf_info dmabuf;
 806         struct bnxt_ulp_context *ulp_ctx;
 807         struct bnxt_flow_stat_info *flow_stat;
 808         uint8_t                 flow_xstat;
 809         uint16_t                max_num_kflows;
 810         uint16_t                tx_cfa_action;
 811 };
 812
 813 #define BNXT_FC_TIMER   1 /* Timer freq in Sec Flow Counters */
 814
 815 /**
 816  * Structure to store private data for each VF representor instance
 817  */
 818 struct bnxt_vf_representor {
 819         uint16_t                switch_domain_id;
 820         uint16_t                vf_id;
 821         uint16_t                fw_fid;
 822 #define BNXT_DFLT_VNIC_ID_INVALID       0xFFFF
 823         uint16_t                dflt_vnic_id;
 824         uint16_t                svif;
 825         uint16_t                vfr_tx_cfa_action;
 826         uint32_t                rep2vf_flow_id;
 827         uint32_t                vf2rep_flow_id;
 828         /* Private data store of associated PF/Trusted VF */
 829         struct rte_eth_dev      *parent_dev;
 830         uint8_t                 mac_addr[RTE_ETHER_ADDR_LEN];
 831         uint8_t                 dflt_mac_addr[RTE_ETHER_ADDR_LEN];
 832         struct bnxt_rx_queue    **rx_queues;
 833         unsigned int            rx_nr_rings;
 834         unsigned int            tx_nr_rings;
 835         uint64_t                tx_pkts[BNXT_MAX_VF_REP_RINGS];
 836         uint64_t                tx_bytes[BNXT_MAX_VF_REP_RINGS];
 837         uint64_t                rx_pkts[BNXT_MAX_VF_REP_RINGS];
 838         uint64_t                rx_bytes[BNXT_MAX_VF_REP_RINGS];
 839         uint64_t                rx_drop_pkts[BNXT_MAX_VF_REP_RINGS];
 840         uint64_t                rx_drop_bytes[BNXT_MAX_VF_REP_RINGS];
 841 };
 842
 843 struct bnxt_vf_rep_tx_queue {
 844         struct bnxt_tx_queue *txq;
 845         struct bnxt_vf_representor *bp;
 846 };
 847
 848 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
 849 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
 850                      bool exp_link_status);
 851 int bnxt_rcv_msg_from_vf(struct bnxt *bp, uint16_t vf_id, void *msg);
 852 int is_bnxt_in_error(struct bnxt *bp);
 853
 854 int bnxt_map_fw_health_status_regs(struct bnxt *bp);
 855 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index);
 856 void bnxt_schedule_fw_health_check(struct bnxt *bp);
 857
 858 bool is_bnxt_supported(struct rte_eth_dev *dev);
 859 bool bnxt_stratus_device(struct bnxt *bp);
 860 void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 861 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp);
 862 int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
 863                         int wait_to_complete);
 864
 865 extern const struct rte_flow_ops bnxt_flow_ops;
 866
 867 #define bnxt_acquire_flow_lock(bp) \
 868         pthread_mutex_lock(&(bp)->flow_lock)
 869
 870 #define bnxt_release_flow_lock(bp) \
 871         pthread_mutex_unlock(&(bp)->flow_lock)
 872
 873 #define BNXT_VALID_VNIC_OR_RET(bp, vnic_id) do { \
 874         if ((vnic_id) >= (bp)->max_vnics) { \
 875                 rte_flow_error_set(error, \
 876                                 EINVAL, \
 877                                 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, \
 878                                 NULL, \
 879                                 "Group id is invalid!"); \
 880                 rc = -rte_errno; \
 881                 goto ret; \
 882         } \
 883 } while (0)
 884
 885 #define BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)    \
 886                 ((eth_dev)->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
 887
 888 extern int bnxt_logtype_driver;
 889 #define PMD_DRV_LOG_RAW(level, fmt, args...) \
 890         rte_log(RTE_LOG_ ## level, bnxt_logtype_driver, "%s(): " fmt, \
 891                 __func__, ## args)
 892
 893 #define PMD_DRV_LOG(level, fmt, args...) \
 894           PMD_DRV_LOG_RAW(level, fmt, ## args)
 895
 896 extern const struct rte_flow_ops bnxt_ulp_rte_flow_ops;
 897 int32_t bnxt_ulp_init(struct bnxt *bp);
 898 void bnxt_ulp_deinit(struct bnxt *bp);
 899 int32_t bnxt_ulp_create_df_rules(struct bnxt *bp);
 900 void bnxt_ulp_destroy_df_rules(struct bnxt *bp, bool global);
 901
 902 uint16_t bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type);
 903 uint16_t bnxt_get_svif(uint16_t port_id, bool func_svif,
 904                        enum bnxt_ulp_intf_type type);
 905 uint16_t bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type);
 906 uint16_t bnxt_get_parif(uint16_t port, enum bnxt_ulp_intf_type type);
 907 uint16_t bnxt_get_phy_port_id(uint16_t port);
 908 uint16_t bnxt_get_vport(uint16_t port);
 909 enum bnxt_ulp_intf_type
 910 bnxt_get_interface_type(uint16_t port);
 911 int bnxt_vf_rep_dev_start_op(struct rte_eth_dev *eth_dev);
 912
 913 void bnxt_cancel_fc_thread(struct bnxt *bp);
 914 void bnxt_flow_cnt_alarm_cb(void *arg);
 915 int bnxt_flow_stats_req(struct bnxt *bp);
 916 int bnxt_flow_stats_cnt(struct bnxt *bp);
 917 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp);
 918
 919 int
 920 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
 921                     enum rte_filter_type filter_type,
 922                     enum rte_filter_op filter_op, void *arg);
 923 #endif