1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
11 #include <sys/queue.h>
14 #include <rte_bus_pci.h>
15 #include <rte_ethdev_driver.h>
16 #include <rte_memory.h>
17 #include <rte_lcore.h>
18 #include <rte_spinlock.h>
22 #include "bnxt_util.h"
26 #include "bnxt_tf_common.h"
29 #define PCI_VENDOR_ID_BROADCOM 0x14E4
32 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
33 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
34 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
35 #define BROADCOM_DEV_ID_57414_VF 0x16c1
36 #define BROADCOM_DEV_ID_57301 0x16c8
37 #define BROADCOM_DEV_ID_57302 0x16c9
38 #define BROADCOM_DEV_ID_57304_PF 0x16ca
39 #define BROADCOM_DEV_ID_57304_VF 0x16cb
40 #define BROADCOM_DEV_ID_57417_MF 0x16cc
41 #define BROADCOM_DEV_ID_NS2 0x16cd
42 #define BROADCOM_DEV_ID_57311 0x16ce
43 #define BROADCOM_DEV_ID_57312 0x16cf
44 #define BROADCOM_DEV_ID_57402 0x16d0
45 #define BROADCOM_DEV_ID_57404 0x16d1
46 #define BROADCOM_DEV_ID_57406_PF 0x16d2
47 #define BROADCOM_DEV_ID_57406_VF 0x16d3
48 #define BROADCOM_DEV_ID_57402_MF 0x16d4
49 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
50 #define BROADCOM_DEV_ID_57412 0x16d6
51 #define BROADCOM_DEV_ID_57414 0x16d7
52 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
53 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
54 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
55 #define BROADCOM_DEV_ID_57412_MF 0x16de
56 #define BROADCOM_DEV_ID_57314 0x16df
57 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
58 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
59 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
60 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
61 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
62 #define BROADCOM_DEV_ID_57404_MF 0x16e7
63 #define BROADCOM_DEV_ID_57406_MF 0x16e8
64 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
65 #define BROADCOM_DEV_ID_57407_MF 0x16ea
66 #define BROADCOM_DEV_ID_57414_MF 0x16ec
67 #define BROADCOM_DEV_ID_57416_MF 0x16ee
68 #define BROADCOM_DEV_ID_57508 0x1750
69 #define BROADCOM_DEV_ID_57504 0x1751
70 #define BROADCOM_DEV_ID_57502 0x1752
71 #define BROADCOM_DEV_ID_57508_MF1 0x1800
72 #define BROADCOM_DEV_ID_57504_MF1 0x1801
73 #define BROADCOM_DEV_ID_57502_MF1 0x1802
74 #define BROADCOM_DEV_ID_57508_MF2 0x1803
75 #define BROADCOM_DEV_ID_57504_MF2 0x1804
76 #define BROADCOM_DEV_ID_57502_MF2 0x1805
77 #define BROADCOM_DEV_ID_57500_VF1 0x1806
78 #define BROADCOM_DEV_ID_57500_VF2 0x1807
79 #define BROADCOM_DEV_ID_58802 0xd802
80 #define BROADCOM_DEV_ID_58804 0xd804
81 #define BROADCOM_DEV_ID_58808 0x16f0
82 #define BROADCOM_DEV_ID_58802_VF 0xd800
84 #define BROADCOM_DEV_957508_N2100 0x5208
85 #define IS_BNXT_DEV_957508_N2100(bp) \
86 ((bp)->pdev->id.subsystem_device_id == BROADCOM_DEV_957508_N2100)
88 #define BNXT_MAX_MTU 9574
89 #define VLAN_TAG_SIZE 4
90 #define BNXT_NUM_VLANS 2
91 #define BNXT_MAX_PKT_LEN (BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +\
93 (BNXT_NUM_VLANS * VLAN_TAG_SIZE))
94 /* FW adds extra 4 bytes for FCS */
95 #define BNXT_VNIC_MRU(mtu)\
96 ((mtu) + RTE_ETHER_HDR_LEN + VLAN_TAG_SIZE * BNXT_NUM_VLANS)
97 #define BNXT_VF_RSV_NUM_RSS_CTX 1
98 #define BNXT_VF_RSV_NUM_L2_CTX 4
99 /* TODO: For now, do not support VMDq/RFS on VFs. */
100 #define BNXT_VF_RSV_NUM_VNIC 1
101 #define BNXT_MAX_LED 4
102 #define BNXT_MIN_RING_DESC 16
103 #define BNXT_MAX_TX_RING_DESC 4096
104 #define BNXT_MAX_RX_RING_DESC 8192
105 #define BNXT_DB_SIZE 0x80
107 #define TPA_MAX_AGGS 64
108 #define TPA_MAX_AGGS_TH 1024
110 #define TPA_MAX_NUM_SEGS 32
111 #define TPA_MAX_SEGS_TH 8 /* 32 segments in 4-segment units */
112 #define TPA_MAX_SEGS 5 /* 32 segments in log2 units */
114 #define BNXT_TPA_MAX_AGGS(bp) \
115 (BNXT_CHIP_THOR(bp) ? TPA_MAX_AGGS_TH : \
118 #define BNXT_TPA_MAX_SEGS(bp) \
119 (BNXT_CHIP_THOR(bp) ? TPA_MAX_SEGS_TH : \
123 * Define the number of async completion rings to be used. Set to zero for
124 * configurations in which the maximum number of packet completion rings
125 * for packet completions is desired or when async completion handling
126 * cannot be interrupt-driven.
128 #ifdef RTE_EXEC_ENV_FREEBSD
129 /* In FreeBSD OS, nic_uio driver does not support interrupts */
130 #define BNXT_NUM_ASYNC_CPR(bp) 0
132 #define BNXT_NUM_ASYNC_CPR(bp) 1
135 #define BNXT_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
136 #define BNXT_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
138 /* Chimp Communication Channel */
139 #define GRCPF_REG_CHIMP_CHANNEL_OFFSET 0x0
140 #define GRCPF_REG_CHIMP_COMM_TRIGGER 0x100
141 /* Kong Communication Channel */
142 #define GRCPF_REG_KONG_CHANNEL_OFFSET 0xA00
143 #define GRCPF_REG_KONG_COMM_TRIGGER 0xB00
145 #define BNXT_INT_LAT_TMR_MIN 75
146 #define BNXT_INT_LAT_TMR_MAX 150
147 #define BNXT_NUM_CMPL_AGGR_INT 36
148 #define BNXT_CMPL_AGGR_DMA_TMR 37
149 #define BNXT_NUM_CMPL_DMA_AGGR 36
150 #define BNXT_CMPL_AGGR_DMA_TMR_DURING_INT 50
151 #define BNXT_NUM_CMPL_DMA_AGGR_DURING_INT 12
153 #define BNXT_DEFAULT_VNIC_STATE_MASK \
154 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK
155 #define BNXT_DEFAULT_VNIC_STATE_SFT \
156 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT
157 #define BNXT_DEFAULT_VNIC_ALLOC \
158 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC
159 #define BNXT_DEFAULT_VNIC_FREE \
160 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE
161 #define BNXT_DEFAULT_VNIC_CHANGE_PF_ID_MASK \
162 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK
163 #define BNXT_DEFAULT_VNIC_CHANGE_PF_ID_SFT \
164 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT
165 #define BNXT_DEFAULT_VNIC_CHANGE_VF_ID_MASK \
166 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK
167 #define BNXT_DEFAULT_VNIC_CHANGE_VF_ID_SFT \
168 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT
170 #define BNXT_HWRM_CMD_TO_FORWARD(cmd) \
171 (bp->pf->vf_req_fwd[(cmd) / 32] |= (1 << ((cmd) % 32)))
173 struct bnxt_led_info {
177 uint8_t led_group_id;
179 uint16_t led_state_caps;
180 #define BNXT_LED_ALT_BLINK_CAP(x) ((x) & \
181 rte_cpu_to_le_16(HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT))
183 uint16_t led_color_caps;
186 struct bnxt_led_cfg {
191 uint16_t led_blink_on;
192 uint16_t led_blink_off;
193 uint8_t led_group_id;
197 #define BNXT_LED_DFLT_ENA \
198 (HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID | \
199 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE | \
200 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON | \
201 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF | \
202 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID)
204 #define BNXT_LED_DFLT_ENA_SHIFT 6
206 #define BNXT_LED_DFLT_ENABLES(x) \
207 rte_cpu_to_le_32(BNXT_LED_DFLT_ENA << (BNXT_LED_DFLT_ENA_SHIFT * (x)))
209 struct bnxt_vlan_table_entry {
214 struct bnxt_vlan_antispoof_table_entry {
220 struct bnxt_child_vf_info {
222 struct bnxt_vlan_table_entry *vlan_table;
223 struct bnxt_vlan_antispoof_table_entry *vlan_as_table;
224 STAILQ_HEAD(, bnxt_filter_info) filter;
225 uint32_t func_cfg_flags;
228 uint16_t max_tx_rate;
231 uint8_t mac_spoof_en;
232 uint8_t vlan_spoof_en;
237 struct bnxt_parent_info {
238 #define BNXT_PF_FID_INVALID 0xFFFF
242 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
245 struct bnxt_pf_info {
246 #define BNXT_FIRST_PF_FID 1
247 #define BNXT_MAX_VFS(bp) ((bp)->pf->max_vfs)
248 #define BNXT_MAX_VF_REPS 64
249 #define BNXT_TOTAL_VFS(bp) ((bp)->pf->total_vfs)
250 #define BNXT_FIRST_VF_FID 128
251 #define BNXT_PF_RINGS_USED(bp) bnxt_get_num_queues(bp)
252 #define BNXT_PF_RINGS_AVAIL(bp) ((bp)->pf->max_cp_rings - \
253 BNXT_PF_RINGS_USED(bp))
255 uint16_t first_vf_id;
258 uint16_t total_vfs; /* Total VFs possible.
259 * Not necessarily enabled.
261 uint32_t func_cfg_flags;
263 rte_iova_t vf_req_buf_dma_addr;
264 uint32_t vf_req_fwd[8];
265 uint16_t total_vnics;
266 struct bnxt_child_vf_info *vf_info;
267 #define BNXT_EVB_MODE_NONE 0
268 #define BNXT_EVB_MODE_VEB 1
269 #define BNXT_EVB_MODE_VEPA 2
273 /* Max wait time for link up is 10s and link down is 500ms */
274 #define BNXT_MAX_LINK_WAIT_CNT 200
275 #define BNXT_MIN_LINK_WAIT_CNT 10
276 #define BNXT_LINK_WAIT_INTERVAL 50
277 struct bnxt_link_info {
280 uint8_t phy_link_status;
288 #define PHY_VER_LEN 3
289 uint8_t phy_ver[PHY_VER_LEN];
291 uint16_t support_speeds;
292 uint16_t auto_link_speed;
293 uint16_t force_link_speed;
294 uint16_t auto_link_speed_mask;
295 uint32_t preemphasis;
298 uint16_t support_auto_speeds;
299 uint8_t link_signal_mode;
300 uint16_t force_pam4_link_speed;
301 uint16_t support_pam4_speeds;
302 uint16_t auto_pam4_link_speeds;
303 uint16_t support_pam4_auto_speeds;
304 uint8_t req_signal_mode;
307 #define BNXT_COS_QUEUE_COUNT 8
308 struct bnxt_cos_queue_info {
314 STAILQ_ENTRY(rte_flow) next;
315 struct bnxt_filter_info *filter;
316 struct bnxt_vnic_info *vnic;
319 #define BNXT_PTP_FLAGS_PATH_TX 0x0
320 #define BNXT_PTP_FLAGS_PATH_RX 0x1
321 #define BNXT_PTP_FLAGS_CURRENT_TIME 0x2
323 struct bnxt_ptp_cfg {
324 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400
325 #define BNXT_GRCPF_REG_SYNC_TIME 0x480
326 #define BNXT_CYCLECOUNTER_MASK 0xffffffffffffffffULL
327 struct rte_timecounter tc;
328 struct rte_timecounter tx_tstamp_tc;
329 struct rte_timecounter rx_tstamp_tc;
331 #define BNXT_MAX_TX_TS 1
333 #define BNXT_PTP_MSG_SYNC BIT(0)
334 #define BNXT_PTP_MSG_DELAY_REQ BIT(1)
335 #define BNXT_PTP_MSG_PDELAY_REQ BIT(2)
336 #define BNXT_PTP_MSG_PDELAY_RESP BIT(3)
337 #define BNXT_PTP_MSG_FOLLOW_UP BIT(8)
338 #define BNXT_PTP_MSG_DELAY_RESP BIT(9)
339 #define BNXT_PTP_MSG_PDELAY_RESP_FOLLOW_UP BIT(10)
340 #define BNXT_PTP_MSG_ANNOUNCE BIT(11)
341 #define BNXT_PTP_MSG_SIGNALING BIT(12)
342 #define BNXT_PTP_MSG_MANAGEMENT BIT(13)
343 #define BNXT_PTP_MSG_EVENTS (BNXT_PTP_MSG_SYNC | \
344 BNXT_PTP_MSG_DELAY_REQ | \
345 BNXT_PTP_MSG_PDELAY_REQ | \
346 BNXT_PTP_MSG_PDELAY_RESP)
347 uint8_t tx_tstamp_en:1;
350 #define BNXT_PTP_RX_TS_L 0
351 #define BNXT_PTP_RX_TS_H 1
352 #define BNXT_PTP_RX_SEQ 2
353 #define BNXT_PTP_RX_FIFO 3
354 #define BNXT_PTP_RX_FIFO_PENDING 0x1
355 #define BNXT_PTP_RX_FIFO_ADV 4
356 #define BNXT_PTP_RX_REGS 5
358 #define BNXT_PTP_TX_TS_L 0
359 #define BNXT_PTP_TX_TS_H 1
360 #define BNXT_PTP_TX_SEQ 2
361 #define BNXT_PTP_TX_FIFO 3
362 #define BNXT_PTP_TX_FIFO_EMPTY 0x2
363 #define BNXT_PTP_TX_REGS 4
364 uint32_t rx_regs[BNXT_PTP_RX_REGS];
365 uint32_t rx_mapped_regs[BNXT_PTP_RX_REGS];
366 uint32_t tx_regs[BNXT_PTP_TX_REGS];
367 uint32_t tx_mapped_regs[BNXT_PTP_TX_REGS];
369 /* On Thor, the Rx timestamp is present in the Rx completion record */
370 uint64_t rx_timestamp;
374 uint16_t num_cmpl_aggr_int;
375 uint16_t num_cmpl_dma_aggr;
376 uint16_t num_cmpl_dma_aggr_during_int;
377 uint16_t int_lat_tmr_max;
378 uint16_t int_lat_tmr_min;
379 uint16_t cmpl_aggr_dma_tmr;
380 uint16_t cmpl_aggr_dma_tmr_during_int;
383 /* 64-bit doorbell */
384 #define DBR_XID_SFT 32
385 #define DBR_PATH_L2 (0x1ULL << 56)
386 #define DBR_TYPE_SQ (0x0ULL << 60)
387 #define DBR_TYPE_SRQ (0x2ULL << 60)
388 #define DBR_TYPE_CQ (0x4ULL << 60)
389 #define DBR_TYPE_NQ (0xaULL << 60)
390 #define DBR_TYPE_NQ_ARM (0xbULL << 60)
392 #define BNXT_RSS_TBL_SIZE_THOR 512
393 #define BNXT_RSS_ENTRIES_PER_CTX_THOR 64
394 #define BNXT_MAX_RSS_CTXTS_THOR \
395 (BNXT_RSS_TBL_SIZE_THOR / BNXT_RSS_ENTRIES_PER_CTX_THOR)
397 #define BNXT_MAX_TC 8
398 #define BNXT_MAX_QUEUE 8
399 #define BNXT_MAX_TC_Q (BNXT_MAX_TC + 1)
400 #define BNXT_PAGE_SHFT 12
401 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHFT)
402 #define MAX_CTX_PAGES (BNXT_PAGE_SIZE / 8)
404 #define PTU_PTE_VALID 0x1UL
405 #define PTU_PTE_LAST 0x2UL
406 #define PTU_PTE_NEXT_TO_LAST 0x4UL
408 struct bnxt_ring_mem_info {
412 #define BNXT_RMEM_VALID_PTE_FLAG 1
413 #define BNXT_RMEM_RING_PTE_FLAG 2
417 const struct rte_memzone *mz;
420 rte_iova_t pg_tbl_map;
421 const struct rte_memzone *pg_tbl_mz;
427 struct bnxt_ctx_pg_info {
429 void *ctx_pg_arr[MAX_CTX_PAGES];
430 rte_iova_t ctx_dma_arr[MAX_CTX_PAGES];
431 struct bnxt_ring_mem_info ring_mem;
434 struct bnxt_ctx_mem_info {
435 uint32_t qp_max_entries;
436 uint16_t qp_min_qp1_entries;
437 uint16_t qp_max_l2_entries;
438 uint16_t qp_entry_size;
439 uint16_t srq_max_l2_entries;
440 uint32_t srq_max_entries;
441 uint16_t srq_entry_size;
442 uint16_t cq_max_l2_entries;
443 uint32_t cq_max_entries;
444 uint16_t cq_entry_size;
445 uint16_t vnic_max_vnic_entries;
446 uint16_t vnic_max_ring_table_entries;
447 uint16_t vnic_entry_size;
448 uint32_t stat_max_entries;
449 uint16_t stat_entry_size;
450 uint16_t tqm_entry_size;
451 uint32_t tqm_min_entries_per_ring;
452 uint32_t tqm_max_entries_per_ring;
453 uint32_t mrav_max_entries;
454 uint16_t mrav_entry_size;
455 uint16_t tim_entry_size;
456 uint32_t tim_max_entries;
457 uint8_t tqm_entries_multiple;
458 uint8_t tqm_fp_rings_count;
461 #define BNXT_CTX_FLAG_INITED 0x01
463 struct bnxt_ctx_pg_info qp_mem;
464 struct bnxt_ctx_pg_info srq_mem;
465 struct bnxt_ctx_pg_info cq_mem;
466 struct bnxt_ctx_pg_info vnic_mem;
467 struct bnxt_ctx_pg_info stat_mem;
468 struct bnxt_ctx_pg_info *tqm_mem[BNXT_MAX_TC_Q];
471 struct bnxt_ctx_mem_buf_info {
478 /* Maximum Firmware Reset bail out value in milliseconds */
479 #define BNXT_MAX_FW_RESET_TIMEOUT 6000
480 /* Minimum time required for the firmware readiness in milliseconds */
481 #define BNXT_MIN_FW_READY_TIMEOUT 2000
482 /* Frequency for the firmware readiness check in milliseconds */
483 #define BNXT_FW_READY_WAIT_INTERVAL 100
485 #define US_PER_MS 1000
486 #define NS_PER_US 1000
488 struct bnxt_error_recovery_info {
489 /* All units in milliseconds */
490 uint32_t driver_polling_freq;
491 uint32_t master_func_wait_period;
492 uint32_t normal_func_wait_period;
493 uint32_t master_func_wait_period_after_reset;
494 uint32_t max_bailout_time_after_reset;
495 #define BNXT_FW_STATUS_REG 0
496 #define BNXT_FW_HEARTBEAT_CNT_REG 1
497 #define BNXT_FW_RECOVERY_CNT_REG 2
498 #define BNXT_FW_RESET_INPROG_REG 3
499 #define BNXT_FW_STATUS_REG_CNT 4
500 uint32_t status_regs[BNXT_FW_STATUS_REG_CNT];
501 uint32_t mapped_status_regs[BNXT_FW_STATUS_REG_CNT];
502 uint32_t reset_inprogress_reg_mask;
503 #define BNXT_NUM_RESET_REG 16
504 uint8_t reg_array_cnt;
505 uint32_t reset_reg[BNXT_NUM_RESET_REG];
506 uint32_t reset_reg_val[BNXT_NUM_RESET_REG];
507 uint8_t delay_after_reset[BNXT_NUM_RESET_REG];
508 #define BNXT_FLAG_ERROR_RECOVERY_HOST BIT(0)
509 #define BNXT_FLAG_ERROR_RECOVERY_CO_CPU BIT(1)
510 #define BNXT_FLAG_MASTER_FUNC BIT(2)
511 #define BNXT_FLAG_RECOVERY_ENABLED BIT(3)
514 uint32_t last_heart_beat;
515 uint32_t last_reset_counter;
518 /* Frequency for the FUNC_DRV_IF_CHANGE retry in milliseconds */
519 #define BNXT_IF_CHANGE_RETRY_INTERVAL 50
520 /* Maximum retry count for FUNC_DRV_IF_CHANGE */
521 #define BNXT_IF_CHANGE_RETRY_COUNT 40
523 struct bnxt_mark_info {
528 struct bnxt_rep_info {
529 struct rte_eth_dev *vfr_eth_dev;
530 pthread_mutex_t vfr_lock;
531 pthread_mutex_t vfr_start_lock;
535 /* address space location of register */
536 #define BNXT_FW_STATUS_REG_TYPE_MASK 3
537 /* register is located in PCIe config space */
538 #define BNXT_FW_STATUS_REG_TYPE_CFG 0
539 /* register is located in GRC address space */
540 #define BNXT_FW_STATUS_REG_TYPE_GRC 1
541 /* register is located in BAR0 */
542 #define BNXT_FW_STATUS_REG_TYPE_BAR0 2
543 /* register is located in BAR1 */
544 #define BNXT_FW_STATUS_REG_TYPE_BAR1 3
546 #define BNXT_FW_STATUS_REG_TYPE(reg) ((reg) & BNXT_FW_STATUS_REG_TYPE_MASK)
547 #define BNXT_FW_STATUS_REG_OFF(reg) ((reg) & ~BNXT_FW_STATUS_REG_TYPE_MASK)
549 #define BNXT_GRCP_WINDOW_2_BASE 0x2000
550 #define BNXT_GRCP_WINDOW_3_BASE 0x3000
552 #define BNXT_GRCP_BASE_MASK 0xfffff000
553 #define BNXT_GRCP_OFFSET_MASK 0x00000ffc
555 #define BNXT_FW_STATUS_HEALTHY 0x8000
556 #define BNXT_FW_STATUS_SHUTDOWN 0x100000
558 #define BNXT_ETH_RSS_SUPPORT ( \
560 ETH_RSS_NONFRAG_IPV4_TCP | \
561 ETH_RSS_NONFRAG_IPV4_UDP | \
563 ETH_RSS_NONFRAG_IPV6_TCP | \
564 ETH_RSS_NONFRAG_IPV6_UDP | \
567 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
568 DEV_TX_OFFLOAD_IPV4_CKSUM | \
569 DEV_TX_OFFLOAD_TCP_CKSUM | \
570 DEV_TX_OFFLOAD_UDP_CKSUM | \
571 DEV_TX_OFFLOAD_TCP_TSO | \
572 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
573 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
574 DEV_TX_OFFLOAD_GRE_TNL_TSO | \
575 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
576 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
577 DEV_TX_OFFLOAD_QINQ_INSERT | \
578 DEV_TX_OFFLOAD_MULTI_SEGS)
580 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
581 DEV_RX_OFFLOAD_VLAN_STRIP | \
582 DEV_RX_OFFLOAD_IPV4_CKSUM | \
583 DEV_RX_OFFLOAD_UDP_CKSUM | \
584 DEV_RX_OFFLOAD_TCP_CKSUM | \
585 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
586 DEV_RX_OFFLOAD_JUMBO_FRAME | \
587 DEV_RX_OFFLOAD_KEEP_CRC | \
588 DEV_RX_OFFLOAD_VLAN_EXTEND | \
589 DEV_RX_OFFLOAD_TCP_LRO | \
590 DEV_RX_OFFLOAD_SCATTER | \
591 DEV_RX_OFFLOAD_RSS_HASH)
593 #define MAX_TABLE_SUPPORT 4
594 #define MAX_DIR_SUPPORT 2
595 struct bnxt_dmabuf_info {
597 int fd[MAX_DIR_SUPPORT][MAX_TABLE_SUPPORT];
600 #define BNXT_HWRM_SHORT_REQ_LEN sizeof(struct hwrm_short_input)
602 struct bnxt_flow_stat_info {
605 struct bnxt_ctx_mem_buf_info rx_fc_in_tbl;
606 struct bnxt_ctx_mem_buf_info rx_fc_out_tbl;
607 struct bnxt_ctx_mem_buf_info tx_fc_in_tbl;
608 struct bnxt_ctx_mem_buf_info tx_fc_out_tbl;
614 struct rte_eth_dev *eth_dev;
615 struct rte_pci_device *pdev;
619 #define BNXT_FLAG_REGISTERED BIT(0)
620 #define BNXT_FLAG_VF BIT(1)
621 #define BNXT_FLAG_PORT_STATS BIT(2)
622 #define BNXT_FLAG_JUMBO BIT(3)
623 #define BNXT_FLAG_SHORT_CMD BIT(4)
624 #define BNXT_FLAG_UPDATE_HASH BIT(5)
625 #define BNXT_FLAG_PTP_SUPPORTED BIT(6)
626 #define BNXT_FLAG_MULTI_HOST BIT(7)
627 #define BNXT_FLAG_EXT_RX_PORT_STATS BIT(8)
628 #define BNXT_FLAG_EXT_TX_PORT_STATS BIT(9)
629 #define BNXT_FLAG_KONG_MB_EN BIT(10)
630 #define BNXT_FLAG_TRUSTED_VF_EN BIT(11)
631 #define BNXT_FLAG_DFLT_VNIC_SET BIT(12)
632 #define BNXT_FLAG_THOR_CHIP BIT(13)
633 #define BNXT_FLAG_STINGRAY BIT(14)
634 #define BNXT_FLAG_FW_RESET BIT(15)
635 #define BNXT_FLAG_FATAL_ERROR BIT(16)
636 #define BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE BIT(17)
637 #define BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED BIT(18)
638 #define BNXT_FLAG_EXT_STATS_SUPPORTED BIT(19)
639 #define BNXT_FLAG_NEW_RM BIT(20)
640 #define BNXT_FLAG_NPAR_PF BIT(21)
641 #define BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS BIT(22)
642 #define BNXT_FLAG_FC_THREAD BIT(23)
643 #define BNXT_FLAG_RX_VECTOR_PKT_MODE BIT(24)
644 #define BNXT_FLAG_FLOW_XSTATS_EN BIT(25)
645 #define BNXT_FLAG_DFLT_MAC_SET BIT(26)
646 #define BNXT_FLAG_TRUFLOW_EN BIT(27)
647 #define BNXT_FLAG_GFID_ENABLE BIT(28)
648 #define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF))
649 #define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF)
650 #define BNXT_NPAR(bp) ((bp)->flags & BNXT_FLAG_NPAR_PF)
651 #define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST)
652 #define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
653 #define BNXT_USE_CHIMP_MB 0 //For non-CFA commands, everything uses Chimp.
654 #define BNXT_USE_KONG(bp) ((bp)->flags & BNXT_FLAG_KONG_MB_EN)
655 #define BNXT_VF_IS_TRUSTED(bp) ((bp)->flags & BNXT_FLAG_TRUSTED_VF_EN)
656 #define BNXT_CHIP_THOR(bp) ((bp)->flags & BNXT_FLAG_THOR_CHIP)
657 #define BNXT_STINGRAY(bp) ((bp)->flags & BNXT_FLAG_STINGRAY)
658 #define BNXT_HAS_NQ(bp) BNXT_CHIP_THOR(bp)
659 #define BNXT_HAS_RING_GRPS(bp) (!BNXT_CHIP_THOR(bp))
660 #define BNXT_FLOW_XSTATS_EN(bp) ((bp)->flags & BNXT_FLAG_FLOW_XSTATS_EN)
661 #define BNXT_HAS_DFLT_MAC_SET(bp) ((bp)->flags & BNXT_FLAG_DFLT_MAC_SET)
662 #define BNXT_TRUFLOW_EN(bp) ((bp)->flags & BNXT_FLAG_TRUFLOW_EN)
663 #define BNXT_GFID_ENABLED(bp) ((bp)->flags & BNXT_FLAG_GFID_ENABLE)
666 #define BNXT_FW_CAP_HOT_RESET BIT(0)
667 #define BNXT_FW_CAP_IF_CHANGE BIT(1)
668 #define BNXT_FW_CAP_ERROR_RECOVERY BIT(2)
669 #define BNXT_FW_CAP_ERR_RECOVER_RELOAD BIT(3)
670 #define BNXT_FW_CAP_HCOMM_FW_STATUS BIT(4)
671 #define BNXT_FW_CAP_ADV_FLOW_MGMT BIT(5)
672 #define BNXT_FW_CAP_ADV_FLOW_COUNTERS BIT(6)
673 #define BNXT_FW_CAP_LINK_ADMIN BIT(7)
675 pthread_mutex_t flow_lock;
677 uint32_t vnic_cap_flags;
678 #define BNXT_VNIC_CAP_COS_CLASSIFY BIT(0)
679 #define BNXT_VNIC_CAP_OUTER_RSS BIT(1)
680 unsigned int rx_nr_rings;
681 unsigned int rx_cp_nr_rings;
682 unsigned int rx_num_qs_per_vnic;
683 struct bnxt_rx_queue **rx_queues;
684 const void *rx_mem_zone;
685 struct rx_port_stats *hw_rx_port_stats;
686 rte_iova_t hw_rx_port_stats_map;
687 struct rx_port_stats_ext *hw_rx_port_stats_ext;
688 rte_iova_t hw_rx_port_stats_ext_map;
689 uint16_t fw_rx_port_stats_ext_size;
691 unsigned int tx_nr_rings;
692 unsigned int tx_cp_nr_rings;
693 struct bnxt_tx_queue **tx_queues;
694 const void *tx_mem_zone;
695 struct tx_port_stats *hw_tx_port_stats;
696 rte_iova_t hw_tx_port_stats_map;
697 struct tx_port_stats_ext *hw_tx_port_stats_ext;
698 rte_iova_t hw_tx_port_stats_ext_map;
699 uint16_t fw_tx_port_stats_ext_size;
701 /* Default completion ring */
702 struct bnxt_cp_ring_info *async_cp_ring;
703 struct bnxt_cp_ring_info *rxtx_nq_ring;
704 uint32_t max_ring_grps;
705 struct bnxt_ring_grp_info *grp_info;
707 unsigned int nr_vnics;
709 #define BNXT_GET_DEFAULT_VNIC(bp) (&(bp)->vnic_info[0])
710 struct bnxt_vnic_info *vnic_info;
711 STAILQ_HEAD(, bnxt_vnic_info) free_vnic_list;
713 struct bnxt_filter_info *filter_info;
714 STAILQ_HEAD(, bnxt_filter_info) free_filter_list;
716 struct bnxt_irq *irq_tbl;
718 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
720 uint16_t chimp_cmd_seq;
721 uint16_t kong_cmd_seq;
722 void *hwrm_cmd_resp_addr;
723 rte_iova_t hwrm_cmd_resp_dma_addr;
724 void *hwrm_short_cmd_req_addr;
725 rte_iova_t hwrm_short_cmd_req_dma_addr;
726 rte_spinlock_t hwrm_lock;
727 pthread_mutex_t def_cp_lock;
728 pthread_mutex_t health_check_lock;
729 uint16_t max_req_len;
730 uint16_t max_resp_len;
731 uint16_t hwrm_max_ext_req_len;
733 /* default command timeout value of 500ms */
734 #define DFLT_HWRM_CMD_TIMEOUT 500000
735 /* short command timeout value of 50ms */
736 #define SHORT_HWRM_CMD_TIMEOUT 50000
737 /* default HWRM request timeout value */
738 uint32_t hwrm_cmd_timeout;
740 struct bnxt_link_info *link_info;
741 struct bnxt_cos_queue_info *rx_cos_queue;
742 struct bnxt_cos_queue_info *tx_cos_queue;
743 uint8_t tx_cosq_id[BNXT_COS_QUEUE_COUNT];
750 uint16_t max_rsscos_ctx;
751 uint16_t max_cp_rings;
752 uint16_t max_tx_rings;
753 uint16_t max_rx_rings;
754 #define MAX_STINGRAY_RINGS 128U
755 /* For sake of symmetry, max Tx rings == max Rx rings, one stat ctx for each */
756 #define BNXT_MAX_RX_RINGS(bp) \
757 (BNXT_STINGRAY(bp) ? RTE_MIN(RTE_MIN(bp->max_rx_rings / 2U, \
758 MAX_STINGRAY_RINGS), \
759 bp->max_stat_ctx / 2U) : \
760 RTE_MIN(bp->max_rx_rings / 2U, \
761 bp->max_stat_ctx / 2U))
762 #define BNXT_MAX_TX_RINGS(bp) \
763 (RTE_MIN((bp)->max_tx_rings, BNXT_MAX_RX_RINGS(bp)))
765 #define BNXT_MAX_RINGS(bp) \
766 (RTE_MIN((((bp)->max_cp_rings - BNXT_NUM_ASYNC_CPR(bp)) / 2U), \
767 BNXT_MAX_TX_RINGS(bp)))
769 #define BNXT_MAX_VF_REP_RINGS 8
771 uint16_t max_nq_rings;
773 uint16_t max_rx_em_flows;
775 uint16_t max_stat_ctx;
777 uint16_t first_vf_id;
779 #define BNXT_OUTER_TPID_MASK 0x0000ffff
780 #define BNXT_OUTER_TPID_BD_MASK 0xffff0000
781 #define BNXT_OUTER_TPID_BD_SHFT 16
782 uint32_t outer_tpid_bd;
783 struct bnxt_pf_info *pf;
784 struct bnxt_parent_info *parent;
786 uint8_t vxlan_port_cnt;
787 uint8_t geneve_port_cnt;
789 uint16_t geneve_port;
790 uint16_t vxlan_fw_dst_port_id;
791 uint16_t geneve_fw_dst_port_id;
793 uint32_t hwrm_spec_code;
795 struct bnxt_led_info *leds;
796 struct bnxt_ptp_cfg *ptp_cfg;
797 uint16_t vf_resv_strategy;
798 struct bnxt_ctx_mem_info *ctx;
800 uint16_t fw_reset_min_msecs;
801 uint16_t fw_reset_max_msecs;
802 uint16_t switch_domain_id;
804 struct bnxt_rep_info *rep_info;
805 uint16_t *cfa_code_map;
806 /* Struct to hold adapter error recovery related info */
807 struct bnxt_error_recovery_info *recovery_info;
808 #define BNXT_MARK_TABLE_SZ (sizeof(struct bnxt_mark_info) * 64 * 1024)
809 /* TCAM and EM should be 16-bit only. Other modes not supported. */
810 #define BNXT_FLOW_ID_MASK 0x0000ffff
811 struct bnxt_mark_info *mark_table;
813 #define BNXT_SVIF_INVALID 0xFFFF
818 struct bnxt_dmabuf_info dmabuf;
819 struct bnxt_ulp_context *ulp_ctx;
820 struct bnxt_flow_stat_info *flow_stat;
822 uint16_t max_num_kflows;
823 uint16_t tx_cfa_action;
826 #define BNXT_FC_TIMER 1 /* Timer freq in Sec Flow Counters */
829 * Structure to store private data for each VF representor instance
831 struct bnxt_representor {
832 uint16_t switch_domain_id;
834 #define BNXT_REP_IS_PF BIT(0)
835 #define BNXT_REP_Q_R2F_VALID BIT(1)
836 #define BNXT_REP_Q_F2R_VALID BIT(2)
837 #define BNXT_REP_FC_R2F_VALID BIT(3)
838 #define BNXT_REP_FC_F2R_VALID BIT(4)
841 #define BNXT_DFLT_VNIC_ID_INVALID 0xFFFF
842 uint16_t dflt_vnic_id;
844 uint16_t vfr_tx_cfa_action;
845 uint32_t dpdk_port_id;
846 uint32_t rep_based_pf;
851 /* Private data store of associated PF/Trusted VF */
852 struct rte_eth_dev *parent_dev;
853 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
854 uint8_t dflt_mac_addr[RTE_ETHER_ADDR_LEN];
855 struct bnxt_rx_queue **rx_queues;
856 unsigned int rx_nr_rings;
857 unsigned int tx_nr_rings;
858 uint64_t tx_pkts[BNXT_MAX_VF_REP_RINGS];
859 uint64_t tx_bytes[BNXT_MAX_VF_REP_RINGS];
860 uint64_t rx_pkts[BNXT_MAX_VF_REP_RINGS];
861 uint64_t rx_bytes[BNXT_MAX_VF_REP_RINGS];
862 uint64_t rx_drop_pkts[BNXT_MAX_VF_REP_RINGS];
863 uint64_t rx_drop_bytes[BNXT_MAX_VF_REP_RINGS];
866 #define BNXT_REP_PF(vfr_bp) ((vfr_bp)->flags & BNXT_REP_IS_PF)
868 struct bnxt_vf_rep_tx_queue {
869 struct bnxt_tx_queue *txq;
870 struct bnxt_representor *bp;
873 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
874 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
875 bool exp_link_status);
876 int bnxt_rcv_msg_from_vf(struct bnxt *bp, uint16_t vf_id, void *msg);
877 int is_bnxt_in_error(struct bnxt *bp);
879 int bnxt_map_fw_health_status_regs(struct bnxt *bp);
880 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index);
881 void bnxt_schedule_fw_health_check(struct bnxt *bp);
883 bool is_bnxt_supported(struct rte_eth_dev *dev);
884 bool bnxt_stratus_device(struct bnxt *bp);
885 void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
886 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp);
887 int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
888 int wait_to_complete);
890 extern const struct rte_flow_ops bnxt_flow_ops;
892 #define bnxt_acquire_flow_lock(bp) \
893 pthread_mutex_lock(&(bp)->flow_lock)
895 #define bnxt_release_flow_lock(bp) \
896 pthread_mutex_unlock(&(bp)->flow_lock)
898 #define BNXT_VALID_VNIC_OR_RET(bp, vnic_id) do { \
899 if ((vnic_id) >= (bp)->max_vnics) { \
900 rte_flow_error_set(error, \
902 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, \
904 "Group id is invalid!"); \
910 #define BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev) \
911 ((eth_dev)->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
913 extern int bnxt_logtype_driver;
914 #define PMD_DRV_LOG_RAW(level, fmt, args...) \
915 rte_log(RTE_LOG_ ## level, bnxt_logtype_driver, "%s(): " fmt, \
918 #define PMD_DRV_LOG(level, fmt, args...) \
919 PMD_DRV_LOG_RAW(level, fmt, ## args)
921 extern const struct rte_flow_ops bnxt_ulp_rte_flow_ops;
922 int32_t bnxt_ulp_port_init(struct bnxt *bp);
923 void bnxt_ulp_port_deinit(struct bnxt *bp);
924 int32_t bnxt_ulp_create_df_rules(struct bnxt *bp);
925 void bnxt_ulp_destroy_df_rules(struct bnxt *bp, bool global);
927 bnxt_ulp_create_vfr_default_rules(struct rte_eth_dev *vfr_ethdev);
929 bnxt_ulp_delete_vfr_default_rules(struct bnxt_representor *vfr);
930 uint16_t bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type);
931 uint16_t bnxt_get_svif(uint16_t port_id, bool func_svif,
932 enum bnxt_ulp_intf_type type);
933 uint16_t bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type);
934 uint16_t bnxt_get_parif(uint16_t port, enum bnxt_ulp_intf_type type);
935 uint16_t bnxt_get_phy_port_id(uint16_t port);
936 uint16_t bnxt_get_vport(uint16_t port);
937 enum bnxt_ulp_intf_type
938 bnxt_get_interface_type(uint16_t port);
939 int bnxt_rep_dev_start_op(struct rte_eth_dev *eth_dev);
941 void bnxt_cancel_fc_thread(struct bnxt *bp);
942 void bnxt_flow_cnt_alarm_cb(void *arg);
943 int bnxt_flow_stats_req(struct bnxt *bp);
944 int bnxt_flow_stats_cnt(struct bnxt *bp);
945 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp);
948 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
949 enum rte_filter_type filter_type,
950 enum rte_filter_op filter_op, void *arg);