drivers/net/bnxt/bnxt.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #ifndef _BNXT_H_
   7 #define _BNXT_H_
   8
   9 #include <inttypes.h>
  10 #include <stdbool.h>
  11 #include <sys/queue.h>
  12
  13 #include <rte_pci.h>
  14 #include <rte_bus_pci.h>
  15 #include <rte_ethdev_driver.h>
  16 #include <rte_memory.h>
  17 #include <rte_lcore.h>
  18 #include <rte_spinlock.h>
  19 #include <rte_time.h>
  20
  21 #include "bnxt_cpr.h"
  22 #include "bnxt_util.h"
  23
  24 #include "tf_core.h"
  25 #include "bnxt_ulp.h"
  26 #include "bnxt_tf_common.h"
  27
  28 /* Vendor ID */
  29 #define PCI_VENDOR_ID_BROADCOM          0x14E4
  30
  31 /* Device IDs */
  32 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
  33 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
  34 #define BROADCOM_DEV_ID_STRATUS_NIC     0x1614
  35 #define BROADCOM_DEV_ID_57414_VF        0x16c1
  36 #define BROADCOM_DEV_ID_57301           0x16c8
  37 #define BROADCOM_DEV_ID_57302           0x16c9
  38 #define BROADCOM_DEV_ID_57304_PF        0x16ca
  39 #define BROADCOM_DEV_ID_57304_VF        0x16cb
  40 #define BROADCOM_DEV_ID_57417_MF        0x16cc
  41 #define BROADCOM_DEV_ID_NS2             0x16cd
  42 #define BROADCOM_DEV_ID_57311           0x16ce
  43 #define BROADCOM_DEV_ID_57312           0x16cf
  44 #define BROADCOM_DEV_ID_57402           0x16d0
  45 #define BROADCOM_DEV_ID_57404           0x16d1
  46 #define BROADCOM_DEV_ID_57406_PF        0x16d2
  47 #define BROADCOM_DEV_ID_57406_VF        0x16d3
  48 #define BROADCOM_DEV_ID_57402_MF        0x16d4
  49 #define BROADCOM_DEV_ID_57407_RJ45      0x16d5
  50 #define BROADCOM_DEV_ID_57412           0x16d6
  51 #define BROADCOM_DEV_ID_57414           0x16d7
  52 #define BROADCOM_DEV_ID_57416_RJ45      0x16d8
  53 #define BROADCOM_DEV_ID_57417_RJ45      0x16d9
  54 #define BROADCOM_DEV_ID_5741X_VF        0x16dc
  55 #define BROADCOM_DEV_ID_57412_MF        0x16de
  56 #define BROADCOM_DEV_ID_57314           0x16df
  57 #define BROADCOM_DEV_ID_57317_RJ45      0x16e0
  58 #define BROADCOM_DEV_ID_5731X_VF        0x16e1
  59 #define BROADCOM_DEV_ID_57417_SFP       0x16e2
  60 #define BROADCOM_DEV_ID_57416_SFP       0x16e3
  61 #define BROADCOM_DEV_ID_57317_SFP       0x16e4
  62 #define BROADCOM_DEV_ID_57404_MF        0x16e7
  63 #define BROADCOM_DEV_ID_57406_MF        0x16e8
  64 #define BROADCOM_DEV_ID_57407_SFP       0x16e9
  65 #define BROADCOM_DEV_ID_57407_MF        0x16ea
  66 #define BROADCOM_DEV_ID_57414_MF        0x16ec
  67 #define BROADCOM_DEV_ID_57416_MF        0x16ee
  68 #define BROADCOM_DEV_ID_57508           0x1750
  69 #define BROADCOM_DEV_ID_57504           0x1751
  70 #define BROADCOM_DEV_ID_57502           0x1752
  71 #define BROADCOM_DEV_ID_57508_MF1       0x1800
  72 #define BROADCOM_DEV_ID_57504_MF1       0x1801
  73 #define BROADCOM_DEV_ID_57502_MF1       0x1802
  74 #define BROADCOM_DEV_ID_57508_MF2       0x1803
  75 #define BROADCOM_DEV_ID_57504_MF2       0x1804
  76 #define BROADCOM_DEV_ID_57502_MF2       0x1805
  77 #define BROADCOM_DEV_ID_57500_VF1       0x1806
  78 #define BROADCOM_DEV_ID_57500_VF2       0x1807
  79 #define BROADCOM_DEV_ID_58802           0xd802
  80 #define BROADCOM_DEV_ID_58804           0xd804
  81 #define BROADCOM_DEV_ID_58808           0x16f0
  82 #define BROADCOM_DEV_ID_58802_VF        0xd800
  83
  84 #define BROADCOM_DEV_957508_N2100       0x5208
  85 #define IS_BNXT_DEV_957508_N2100(bp)    \
  86         ((bp)->pdev->id.subsystem_device_id == BROADCOM_DEV_957508_N2100)
  87
  88 #define BNXT_MAX_MTU            9574
  89 #define VLAN_TAG_SIZE           4
  90 #define BNXT_NUM_VLANS          2
  91 #define BNXT_MAX_PKT_LEN        (BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +\
  92                                  RTE_ETHER_CRC_LEN +\
  93                                  (BNXT_NUM_VLANS * VLAN_TAG_SIZE))
  94 /* FW adds extra 4 bytes for FCS */
  95 #define BNXT_VNIC_MRU(mtu)\
  96         ((mtu) + RTE_ETHER_HDR_LEN + VLAN_TAG_SIZE * BNXT_NUM_VLANS)
  97 #define BNXT_VF_RSV_NUM_RSS_CTX 1
  98 #define BNXT_VF_RSV_NUM_L2_CTX  4
  99 /* TODO: For now, do not support VMDq/RFS on VFs. */
 100 #define BNXT_VF_RSV_NUM_VNIC    1
 101 #define BNXT_MAX_LED            4
 102 #define BNXT_MIN_RING_DESC      16
 103 #define BNXT_MAX_TX_RING_DESC   4096
 104 #define BNXT_MAX_RX_RING_DESC   8192
 105 #define BNXT_DB_SIZE            0x80
 106
 107 #define TPA_MAX_AGGS            64
 108 #define TPA_MAX_AGGS_TH         1024
 109
 110 #define TPA_MAX_NUM_SEGS        32
 111 #define TPA_MAX_SEGS_TH         8 /* 32 segments in 4-segment units */
 112 #define TPA_MAX_SEGS            5 /* 32 segments in log2 units */
 113
 114 #define BNXT_TPA_MAX_AGGS(bp) \
 115         (BNXT_CHIP_THOR(bp) ? TPA_MAX_AGGS_TH : \
 116                              TPA_MAX_AGGS)
 117
 118 #define BNXT_TPA_MAX_SEGS(bp) \
 119         (BNXT_CHIP_THOR(bp) ? TPA_MAX_SEGS_TH : \
 120                               TPA_MAX_SEGS)
 121
 122 /*
 123  * Define the number of async completion rings to be used. Set to zero for
 124  * configurations in which the maximum number of packet completion rings
 125  * for packet completions is desired or when async completion handling
 126  * cannot be interrupt-driven.
 127  */
 128 #ifdef RTE_EXEC_ENV_FREEBSD
 129 /* In FreeBSD OS, nic_uio driver does not support interrupts */
 130 #define BNXT_NUM_ASYNC_CPR(bp) 0
 131 #else
 132 #define BNXT_NUM_ASYNC_CPR(bp) 1
 133 #endif
 134
 135 #define BNXT_MISC_VEC_ID               RTE_INTR_VEC_ZERO_OFFSET
 136 #define BNXT_RX_VEC_START              RTE_INTR_VEC_RXTX_OFFSET
 137
 138 /* Chimp Communication Channel */
 139 #define GRCPF_REG_CHIMP_CHANNEL_OFFSET          0x0
 140 #define GRCPF_REG_CHIMP_COMM_TRIGGER            0x100
 141 /* Kong Communication Channel */
 142 #define GRCPF_REG_KONG_CHANNEL_OFFSET           0xA00
 143 #define GRCPF_REG_KONG_COMM_TRIGGER             0xB00
 144
 145 #define BNXT_INT_LAT_TMR_MIN                    75
 146 #define BNXT_INT_LAT_TMR_MAX                    150
 147 #define BNXT_NUM_CMPL_AGGR_INT                  36
 148 #define BNXT_CMPL_AGGR_DMA_TMR                  37
 149 #define BNXT_NUM_CMPL_DMA_AGGR                  36
 150 #define BNXT_CMPL_AGGR_DMA_TMR_DURING_INT       50
 151 #define BNXT_NUM_CMPL_DMA_AGGR_DURING_INT       12
 152
 153 #define BNXT_DEFAULT_VNIC_STATE_MASK                    \
 154         HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK
 155 #define BNXT_DEFAULT_VNIC_STATE_SFT                     \
 156         HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT
 157 #define BNXT_DEFAULT_VNIC_ALLOC                         \
 158         HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC
 159 #define BNXT_DEFAULT_VNIC_FREE                          \
 160         HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE
 161 #define BNXT_DEFAULT_VNIC_CHANGE_PF_ID_MASK             \
 162         HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK
 163 #define BNXT_DEFAULT_VNIC_CHANGE_PF_ID_SFT              \
 164         HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT
 165 #define BNXT_DEFAULT_VNIC_CHANGE_VF_ID_MASK             \
 166         HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK
 167 #define BNXT_DEFAULT_VNIC_CHANGE_VF_ID_SFT              \
 168         HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT
 169
 170 struct bnxt_led_info {
 171         uint8_t      num_leds;
 172         uint8_t      led_id;
 173         uint8_t      led_type;
 174         uint8_t      led_group_id;
 175         uint8_t      unused;
 176         uint16_t  led_state_caps;
 177 #define BNXT_LED_ALT_BLINK_CAP(x)       ((x) &  \
 178         rte_cpu_to_le_16(HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT))
 179
 180         uint16_t  led_color_caps;
 181 };
 182
 183 struct bnxt_led_cfg {
 184         uint8_t led_id;
 185         uint8_t led_state;
 186         uint8_t led_color;
 187         uint8_t unused;
 188         uint16_t led_blink_on;
 189         uint16_t led_blink_off;
 190         uint8_t led_group_id;
 191         uint8_t rsvd;
 192 };
 193
 194 #define BNXT_LED_DFLT_ENA                               \
 195         (HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID |             \
 196          HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE |          \
 197          HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON |       \
 198          HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF |      \
 199          HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID)
 200
 201 #define BNXT_LED_DFLT_ENA_SHIFT         6
 202
 203 #define BNXT_LED_DFLT_ENABLES(x)                        \
 204         rte_cpu_to_le_32(BNXT_LED_DFLT_ENA << (BNXT_LED_DFLT_ENA_SHIFT * (x)))
 205
 206 struct bnxt_vlan_table_entry {
 207         uint16_t                tpid;
 208         uint16_t                vid;
 209 } __rte_packed;
 210
 211 struct bnxt_vlan_antispoof_table_entry {
 212         uint16_t                tpid;
 213         uint16_t                vid;
 214         uint16_t                mask;
 215 } __rte_packed;
 216
 217 struct bnxt_child_vf_info {
 218         void                    *req_buf;
 219         struct bnxt_vlan_table_entry    *vlan_table;
 220         struct bnxt_vlan_antispoof_table_entry  *vlan_as_table;
 221         STAILQ_HEAD(, bnxt_filter_info) filter;
 222         uint32_t                func_cfg_flags;
 223         uint32_t                l2_rx_mask;
 224         uint16_t                fid;
 225         uint16_t                max_tx_rate;
 226         uint16_t                dflt_vlan;
 227         uint16_t                vlan_count;
 228         uint8_t                 mac_spoof_en;
 229         uint8_t                 vlan_spoof_en;
 230         bool                    random_mac;
 231         bool                    persist_stats;
 232 };
 233
 234 struct bnxt_parent_info {
 235 #define BNXT_PF_FID_INVALID     0xFFFF
 236         uint16_t                fid;
 237         uint16_t                vnic;
 238         uint16_t                port_id;
 239         uint8_t                 mac_addr[RTE_ETHER_ADDR_LEN];
 240 };
 241
 242 struct bnxt_pf_info {
 243 #define BNXT_FIRST_PF_FID       1
 244 #define BNXT_MAX_VFS(bp)        ((bp)->pf->max_vfs)
 245 #define BNXT_MAX_VF_REPS        64
 246 #define BNXT_TOTAL_VFS(bp)      ((bp)->pf->total_vfs)
 247 #define BNXT_FIRST_VF_FID       128
 248 #define BNXT_PF_RINGS_USED(bp)  bnxt_get_num_queues(bp)
 249 #define BNXT_PF_RINGS_AVAIL(bp) ((bp)->pf->max_cp_rings - \
 250                                  BNXT_PF_RINGS_USED(bp))
 251         uint16_t                port_id;
 252         uint16_t                first_vf_id;
 253         uint16_t                active_vfs;
 254         uint16_t                max_vfs;
 255         uint16_t                total_vfs; /* Total VFs possible.
 256                                             * Not necessarily enabled.
 257                                             */
 258         uint32_t                func_cfg_flags;
 259         void                    *vf_req_buf;
 260         rte_iova_t              vf_req_buf_dma_addr;
 261         uint32_t                vf_req_fwd[8];
 262         uint16_t                total_vnics;
 263         struct bnxt_child_vf_info       *vf_info;
 264 #define BNXT_EVB_MODE_NONE      0
 265 #define BNXT_EVB_MODE_VEB       1
 266 #define BNXT_EVB_MODE_VEPA      2
 267         uint8_t                 evb_mode;
 268 };
 269
 270 /* Max wait time for link up is 10s and link down is 500ms */
 271 #define BNXT_LINK_UP_WAIT_CNT   200
 272 #define BNXT_LINK_DOWN_WAIT_CNT 10
 273 #define BNXT_LINK_WAIT_INTERVAL 50
 274 struct bnxt_link_info {
 275         uint32_t                phy_flags;
 276         uint8_t                 mac_type;
 277         uint8_t                 phy_link_status;
 278         uint8_t                 loop_back;
 279         uint8_t                 link_up;
 280         uint8_t                 duplex;
 281         uint8_t                 pause;
 282         uint8_t                 force_pause;
 283         uint8_t                 auto_pause;
 284         uint8_t                 auto_mode;
 285 #define PHY_VER_LEN             3
 286         uint8_t                 phy_ver[PHY_VER_LEN];
 287         uint16_t                link_speed;
 288         uint16_t                support_speeds;
 289         uint16_t                auto_link_speed;
 290         uint16_t                force_link_speed;
 291         uint16_t                auto_link_speed_mask;
 292         uint32_t                preemphasis;
 293         uint8_t                 phy_type;
 294         uint8_t                 media_type;
 295         uint16_t                support_auto_speeds;
 296         uint8_t                 link_signal_mode;
 297         uint16_t                force_pam4_link_speed;
 298         uint16_t                support_pam4_speeds;
 299         uint16_t                auto_pam4_link_speeds;
 300         uint16_t                support_pam4_auto_speeds;
 301         uint8_t                 req_signal_mode;
 302 };
 303
 304 #define BNXT_COS_QUEUE_COUNT    8
 305 struct bnxt_cos_queue_info {
 306         uint8_t id;
 307         uint8_t profile;
 308 };
 309
 310 struct rte_flow {
 311         STAILQ_ENTRY(rte_flow) next;
 312         struct bnxt_filter_info *filter;
 313         struct bnxt_vnic_info   *vnic;
 314 };
 315
 316 #define BNXT_PTP_FLAGS_PATH_TX          0x0
 317 #define BNXT_PTP_FLAGS_PATH_RX          0x1
 318 #define BNXT_PTP_FLAGS_CURRENT_TIME     0x2
 319
 320 struct bnxt_ptp_cfg {
 321 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT  0x400
 322 #define BNXT_GRCPF_REG_SYNC_TIME        0x480
 323 #define BNXT_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 324         struct rte_timecounter      tc;
 325         struct rte_timecounter      tx_tstamp_tc;
 326         struct rte_timecounter      rx_tstamp_tc;
 327         struct bnxt             *bp;
 328 #define BNXT_MAX_TX_TS  1
 329         uint16_t                        rxctl;
 330 #define BNXT_PTP_MSG_SYNC                       BIT(0)
 331 #define BNXT_PTP_MSG_DELAY_REQ                  BIT(1)
 332 #define BNXT_PTP_MSG_PDELAY_REQ                 BIT(2)
 333 #define BNXT_PTP_MSG_PDELAY_RESP                BIT(3)
 334 #define BNXT_PTP_MSG_FOLLOW_UP                  BIT(8)
 335 #define BNXT_PTP_MSG_DELAY_RESP                 BIT(9)
 336 #define BNXT_PTP_MSG_PDELAY_RESP_FOLLOW_UP      BIT(10)
 337 #define BNXT_PTP_MSG_ANNOUNCE                   BIT(11)
 338 #define BNXT_PTP_MSG_SIGNALING                  BIT(12)
 339 #define BNXT_PTP_MSG_MANAGEMENT                 BIT(13)
 340 #define BNXT_PTP_MSG_EVENTS             (BNXT_PTP_MSG_SYNC |            \
 341                                          BNXT_PTP_MSG_DELAY_REQ |       \
 342                                          BNXT_PTP_MSG_PDELAY_REQ |      \
 343                                          BNXT_PTP_MSG_PDELAY_RESP)
 344         uint8_t                 tx_tstamp_en:1;
 345         int                     rx_filter;
 346
 347 #define BNXT_PTP_RX_TS_L        0
 348 #define BNXT_PTP_RX_TS_H        1
 349 #define BNXT_PTP_RX_SEQ         2
 350 #define BNXT_PTP_RX_FIFO        3
 351 #define BNXT_PTP_RX_FIFO_PENDING 0x1
 352 #define BNXT_PTP_RX_FIFO_ADV    4
 353 #define BNXT_PTP_RX_REGS        5
 354
 355 #define BNXT_PTP_TX_TS_L        0
 356 #define BNXT_PTP_TX_TS_H        1
 357 #define BNXT_PTP_TX_SEQ         2
 358 #define BNXT_PTP_TX_FIFO        3
 359 #define BNXT_PTP_TX_FIFO_EMPTY   0x2
 360 #define BNXT_PTP_TX_REGS        4
 361         uint32_t                        rx_regs[BNXT_PTP_RX_REGS];
 362         uint32_t                        rx_mapped_regs[BNXT_PTP_RX_REGS];
 363         uint32_t                        tx_regs[BNXT_PTP_TX_REGS];
 364         uint32_t                        tx_mapped_regs[BNXT_PTP_TX_REGS];
 365
 366         /* On Thor, the Rx timestamp is present in the Rx completion record */
 367         uint64_t                        rx_timestamp;
 368 };
 369
 370 struct bnxt_coal {
 371         uint16_t                        num_cmpl_aggr_int;
 372         uint16_t                        num_cmpl_dma_aggr;
 373         uint16_t                        num_cmpl_dma_aggr_during_int;
 374         uint16_t                        int_lat_tmr_max;
 375         uint16_t                        int_lat_tmr_min;
 376         uint16_t                        cmpl_aggr_dma_tmr;
 377         uint16_t                        cmpl_aggr_dma_tmr_during_int;
 378 };
 379
 380 /* 64-bit doorbell */
 381 #define DBR_XID_SFT                             32
 382 #define DBR_PATH_L2                             (0x1ULL << 56)
 383 #define DBR_TYPE_SQ                             (0x0ULL << 60)
 384 #define DBR_TYPE_SRQ                            (0x2ULL << 60)
 385 #define DBR_TYPE_CQ                             (0x4ULL << 60)
 386 #define DBR_TYPE_NQ                             (0xaULL << 60)
 387 #define DBR_TYPE_NQ_ARM                         (0xbULL << 60)
 388
 389 #define BNXT_RSS_TBL_SIZE_THOR          512
 390 #define BNXT_RSS_ENTRIES_PER_CTX_THOR   64
 391 #define BNXT_MAX_RSS_CTXTS_THOR \
 392         (BNXT_RSS_TBL_SIZE_THOR / BNXT_RSS_ENTRIES_PER_CTX_THOR)
 393
 394 #define BNXT_MAX_TC    8
 395 #define BNXT_MAX_QUEUE 8
 396 #define BNXT_MAX_TC_Q  (BNXT_MAX_TC + 1)
 397 #define BNXT_PAGE_SHFT 12
 398 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHFT)
 399 #define MAX_CTX_PAGES  (BNXT_PAGE_SIZE / 8)
 400
 401 #define PTU_PTE_VALID             0x1UL
 402 #define PTU_PTE_LAST              0x2UL
 403 #define PTU_PTE_NEXT_TO_LAST      0x4UL
 404
 405 struct bnxt_ring_mem_info {
 406         int                             nr_pages;
 407         int                             page_size;
 408         uint32_t                        flags;
 409 #define BNXT_RMEM_VALID_PTE_FLAG        1
 410 #define BNXT_RMEM_RING_PTE_FLAG         2
 411
 412         void                            **pg_arr;
 413         rte_iova_t                      *dma_arr;
 414         const struct rte_memzone        *mz;
 415
 416         uint64_t                        *pg_tbl;
 417         rte_iova_t                      pg_tbl_map;
 418         const struct rte_memzone        *pg_tbl_mz;
 419
 420         int                             vmem_size;
 421         void                            **vmem;
 422 };
 423
 424 struct bnxt_ctx_pg_info {
 425         uint32_t        entries;
 426         void            *ctx_pg_arr[MAX_CTX_PAGES];
 427         rte_iova_t      ctx_dma_arr[MAX_CTX_PAGES];
 428         struct bnxt_ring_mem_info ring_mem;
 429 };
 430
 431 struct bnxt_ctx_mem_info {
 432         uint32_t        qp_max_entries;
 433         uint16_t        qp_min_qp1_entries;
 434         uint16_t        qp_max_l2_entries;
 435         uint16_t        qp_entry_size;
 436         uint16_t        srq_max_l2_entries;
 437         uint32_t        srq_max_entries;
 438         uint16_t        srq_entry_size;
 439         uint16_t        cq_max_l2_entries;
 440         uint32_t        cq_max_entries;
 441         uint16_t        cq_entry_size;
 442         uint16_t        vnic_max_vnic_entries;
 443         uint16_t        vnic_max_ring_table_entries;
 444         uint16_t        vnic_entry_size;
 445         uint32_t        stat_max_entries;
 446         uint16_t        stat_entry_size;
 447         uint16_t        tqm_entry_size;
 448         uint32_t        tqm_min_entries_per_ring;
 449         uint32_t        tqm_max_entries_per_ring;
 450         uint32_t        mrav_max_entries;
 451         uint16_t        mrav_entry_size;
 452         uint16_t        tim_entry_size;
 453         uint32_t        tim_max_entries;
 454         uint8_t         tqm_entries_multiple;
 455         uint8_t         tqm_fp_rings_count;
 456
 457         uint32_t        flags;
 458 #define BNXT_CTX_FLAG_INITED    0x01
 459
 460         struct bnxt_ctx_pg_info qp_mem;
 461         struct bnxt_ctx_pg_info srq_mem;
 462         struct bnxt_ctx_pg_info cq_mem;
 463         struct bnxt_ctx_pg_info vnic_mem;
 464         struct bnxt_ctx_pg_info stat_mem;
 465         struct bnxt_ctx_pg_info *tqm_mem[BNXT_MAX_TC_Q];
 466 };
 467
 468 struct bnxt_ctx_mem_buf_info {
 469         void            *va;
 470         rte_iova_t      dma;
 471         uint16_t        ctx_id;
 472         size_t          size;
 473 };
 474
 475 /* Maximum Firmware Reset bail out value in milliseconds */
 476 #define BNXT_MAX_FW_RESET_TIMEOUT       6000
 477 /* Minimum time required for the firmware readiness in milliseconds */
 478 #define BNXT_MIN_FW_READY_TIMEOUT       2000
 479 /* Frequency for the firmware readiness check in milliseconds */
 480 #define BNXT_FW_READY_WAIT_INTERVAL     100
 481
 482 #define US_PER_MS                       1000
 483 #define NS_PER_US                       1000
 484
 485 struct bnxt_error_recovery_info {
 486         /* All units in milliseconds */
 487         uint32_t        driver_polling_freq;
 488         uint32_t        master_func_wait_period;
 489         uint32_t        normal_func_wait_period;
 490         uint32_t        master_func_wait_period_after_reset;
 491         uint32_t        max_bailout_time_after_reset;
 492 #define BNXT_FW_STATUS_REG              0
 493 #define BNXT_FW_HEARTBEAT_CNT_REG       1
 494 #define BNXT_FW_RECOVERY_CNT_REG        2
 495 #define BNXT_FW_RESET_INPROG_REG        3
 496 #define BNXT_FW_STATUS_REG_CNT          4
 497         uint32_t        status_regs[BNXT_FW_STATUS_REG_CNT];
 498         uint32_t        mapped_status_regs[BNXT_FW_STATUS_REG_CNT];
 499         uint32_t        reset_inprogress_reg_mask;
 500 #define BNXT_NUM_RESET_REG      16
 501         uint8_t         reg_array_cnt;
 502         uint32_t        reset_reg[BNXT_NUM_RESET_REG];
 503         uint32_t        reset_reg_val[BNXT_NUM_RESET_REG];
 504         uint8_t         delay_after_reset[BNXT_NUM_RESET_REG];
 505 #define BNXT_FLAG_ERROR_RECOVERY_HOST   BIT(0)
 506 #define BNXT_FLAG_ERROR_RECOVERY_CO_CPU BIT(1)
 507 #define BNXT_FLAG_MASTER_FUNC           BIT(2)
 508 #define BNXT_FLAG_RECOVERY_ENABLED      BIT(3)
 509         uint32_t        flags;
 510
 511         uint32_t        last_heart_beat;
 512         uint32_t        last_reset_counter;
 513 };
 514
 515 /* Frequency for the FUNC_DRV_IF_CHANGE retry in milliseconds */
 516 #define BNXT_IF_CHANGE_RETRY_INTERVAL   50
 517 /* Maximum retry count for FUNC_DRV_IF_CHANGE */
 518 #define BNXT_IF_CHANGE_RETRY_COUNT      40
 519
 520 struct bnxt_mark_info {
 521         uint32_t        mark_id;
 522         bool            valid;
 523 };
 524
 525 struct bnxt_rep_info {
 526         struct rte_eth_dev      *vfr_eth_dev;
 527         pthread_mutex_t         vfr_lock;
 528         pthread_mutex_t         vfr_start_lock;
 529         bool                    conduit_valid;
 530 };
 531
 532 /* address space location of register */
 533 #define BNXT_FW_STATUS_REG_TYPE_MASK    3
 534 /* register is located in PCIe config space */
 535 #define BNXT_FW_STATUS_REG_TYPE_CFG     0
 536 /* register is located in GRC address space */
 537 #define BNXT_FW_STATUS_REG_TYPE_GRC     1
 538 /* register is located in BAR0  */
 539 #define BNXT_FW_STATUS_REG_TYPE_BAR0    2
 540 /* register is located in BAR1  */
 541 #define BNXT_FW_STATUS_REG_TYPE_BAR1    3
 542
 543 #define BNXT_FW_STATUS_REG_TYPE(reg)    ((reg) & BNXT_FW_STATUS_REG_TYPE_MASK)
 544 #define BNXT_FW_STATUS_REG_OFF(reg)     ((reg) & ~BNXT_FW_STATUS_REG_TYPE_MASK)
 545
 546 #define BNXT_GRCP_WINDOW_2_BASE         0x2000
 547 #define BNXT_GRCP_WINDOW_3_BASE         0x3000
 548
 549 #define BNXT_GRCP_BASE_MASK             0xfffff000
 550 #define BNXT_GRCP_OFFSET_MASK           0x00000ffc
 551
 552 #define BNXT_FW_STATUS_HEALTHY          0x8000
 553 #define BNXT_FW_STATUS_SHUTDOWN         0x100000
 554
 555 #define BNXT_ETH_RSS_SUPPORT (  \
 556         ETH_RSS_IPV4 |          \
 557         ETH_RSS_NONFRAG_IPV4_TCP |      \
 558         ETH_RSS_NONFRAG_IPV4_UDP |      \
 559         ETH_RSS_IPV6 |          \
 560         ETH_RSS_NONFRAG_IPV6_TCP |      \
 561         ETH_RSS_NONFRAG_IPV6_UDP |      \
 562         ETH_RSS_LEVEL_MASK)
 563
 564 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 565                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 566                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 567                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 568                                      DEV_TX_OFFLOAD_TCP_TSO | \
 569                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 570                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 571                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 572                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 573                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 574                                      DEV_TX_OFFLOAD_QINQ_INSERT | \
 575                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 576
 577 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 578                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 579                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 580                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 581                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 582                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 583                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 584                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 585                                      DEV_RX_OFFLOAD_VLAN_EXTEND | \
 586                                      DEV_RX_OFFLOAD_TCP_LRO | \
 587                                      DEV_RX_OFFLOAD_SCATTER | \
 588                                      DEV_RX_OFFLOAD_RSS_HASH)
 589
 590 #define  MAX_TABLE_SUPPORT 4
 591 #define  MAX_DIR_SUPPORT   2
 592 struct bnxt_dmabuf_info {
 593         uint32_t entry_num;
 594         int      fd[MAX_DIR_SUPPORT][MAX_TABLE_SUPPORT];
 595 };
 596
 597 #define BNXT_HWRM_SHORT_REQ_LEN         sizeof(struct hwrm_short_input)
 598
 599 struct bnxt_flow_stat_info {
 600         uint16_t                max_fc;
 601         uint16_t                flow_count;
 602         struct bnxt_ctx_mem_buf_info rx_fc_in_tbl;
 603         struct bnxt_ctx_mem_buf_info rx_fc_out_tbl;
 604         struct bnxt_ctx_mem_buf_info tx_fc_in_tbl;
 605         struct bnxt_ctx_mem_buf_info tx_fc_out_tbl;
 606 };
 607
 608 struct bnxt {
 609         void                            *bar0;
 610
 611         struct rte_eth_dev              *eth_dev;
 612         struct rte_pci_device           *pdev;
 613         void                            *doorbell_base;
 614
 615         uint32_t                flags;
 616 #define BNXT_FLAG_REGISTERED            BIT(0)
 617 #define BNXT_FLAG_VF                    BIT(1)
 618 #define BNXT_FLAG_PORT_STATS            BIT(2)
 619 #define BNXT_FLAG_JUMBO                 BIT(3)
 620 #define BNXT_FLAG_SHORT_CMD             BIT(4)
 621 #define BNXT_FLAG_UPDATE_HASH           BIT(5)
 622 #define BNXT_FLAG_PTP_SUPPORTED         BIT(6)
 623 #define BNXT_FLAG_MULTI_HOST            BIT(7)
 624 #define BNXT_FLAG_EXT_RX_PORT_STATS     BIT(8)
 625 #define BNXT_FLAG_EXT_TX_PORT_STATS     BIT(9)
 626 #define BNXT_FLAG_KONG_MB_EN            BIT(10)
 627 #define BNXT_FLAG_TRUSTED_VF_EN         BIT(11)
 628 #define BNXT_FLAG_DFLT_VNIC_SET         BIT(12)
 629 #define BNXT_FLAG_THOR_CHIP             BIT(13)
 630 #define BNXT_FLAG_STINGRAY              BIT(14)
 631 #define BNXT_FLAG_FW_RESET              BIT(15)
 632 #define BNXT_FLAG_FATAL_ERROR           BIT(16)
 633 #define BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE   BIT(17)
 634 #define BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED     BIT(18)
 635 #define BNXT_FLAG_EXT_STATS_SUPPORTED           BIT(19)
 636 #define BNXT_FLAG_NEW_RM                        BIT(20)
 637 #define BNXT_FLAG_NPAR_PF                       BIT(21)
 638 #define BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS         BIT(22)
 639 #define BNXT_FLAG_FC_THREAD                     BIT(23)
 640 #define BNXT_FLAG_RX_VECTOR_PKT_MODE            BIT(24)
 641 #define BNXT_FLAG_FLOW_XSTATS_EN                BIT(25)
 642 #define BNXT_FLAG_DFLT_MAC_SET                  BIT(26)
 643 #define BNXT_FLAG_TRUFLOW_EN                    BIT(27)
 644 #define BNXT_FLAG_GFID_ENABLE                   BIT(28)
 645 #define BNXT_PF(bp)             (!((bp)->flags & BNXT_FLAG_VF))
 646 #define BNXT_VF(bp)             ((bp)->flags & BNXT_FLAG_VF)
 647 #define BNXT_NPAR(bp)           ((bp)->flags & BNXT_FLAG_NPAR_PF)
 648 #define BNXT_MH(bp)             ((bp)->flags & BNXT_FLAG_MULTI_HOST)
 649 #define BNXT_SINGLE_PF(bp)      (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
 650 #define BNXT_USE_CHIMP_MB       0 //For non-CFA commands, everything uses Chimp.
 651 #define BNXT_USE_KONG(bp)       ((bp)->flags & BNXT_FLAG_KONG_MB_EN)
 652 #define BNXT_VF_IS_TRUSTED(bp)  ((bp)->flags & BNXT_FLAG_TRUSTED_VF_EN)
 653 #define BNXT_CHIP_THOR(bp)      ((bp)->flags & BNXT_FLAG_THOR_CHIP)
 654 #define BNXT_STINGRAY(bp)       ((bp)->flags & BNXT_FLAG_STINGRAY)
 655 #define BNXT_HAS_NQ(bp)         BNXT_CHIP_THOR(bp)
 656 #define BNXT_HAS_RING_GRPS(bp)  (!BNXT_CHIP_THOR(bp))
 657 #define BNXT_FLOW_XSTATS_EN(bp) ((bp)->flags & BNXT_FLAG_FLOW_XSTATS_EN)
 658 #define BNXT_HAS_DFLT_MAC_SET(bp)      ((bp)->flags & BNXT_FLAG_DFLT_MAC_SET)
 659 #define BNXT_TRUFLOW_EN(bp)     ((bp)->flags & BNXT_FLAG_TRUFLOW_EN)
 660 #define BNXT_GFID_ENABLED(bp)   ((bp)->flags & BNXT_FLAG_GFID_ENABLE)
 661
 662         uint32_t                fw_cap;
 663 #define BNXT_FW_CAP_HOT_RESET           BIT(0)
 664 #define BNXT_FW_CAP_IF_CHANGE           BIT(1)
 665 #define BNXT_FW_CAP_ERROR_RECOVERY      BIT(2)
 666 #define BNXT_FW_CAP_ERR_RECOVER_RELOAD  BIT(3)
 667 #define BNXT_FW_CAP_ADV_FLOW_MGMT       BIT(5)
 668 #define BNXT_FW_CAP_ADV_FLOW_COUNTERS   BIT(6)
 669 #define BNXT_FW_CAP_HCOMM_FW_STATUS     BIT(7)
 670
 671         pthread_mutex_t         flow_lock;
 672
 673         uint32_t                vnic_cap_flags;
 674 #define BNXT_VNIC_CAP_COS_CLASSIFY      BIT(0)
 675 #define BNXT_VNIC_CAP_OUTER_RSS         BIT(1)
 676         unsigned int            rx_nr_rings;
 677         unsigned int            rx_cp_nr_rings;
 678         unsigned int            rx_num_qs_per_vnic;
 679         struct bnxt_rx_queue **rx_queues;
 680         const void              *rx_mem_zone;
 681         struct rx_port_stats    *hw_rx_port_stats;
 682         rte_iova_t              hw_rx_port_stats_map;
 683         struct rx_port_stats_ext    *hw_rx_port_stats_ext;
 684         rte_iova_t              hw_rx_port_stats_ext_map;
 685         uint16_t                fw_rx_port_stats_ext_size;
 686
 687         unsigned int            tx_nr_rings;
 688         unsigned int            tx_cp_nr_rings;
 689         struct bnxt_tx_queue **tx_queues;
 690         const void              *tx_mem_zone;
 691         struct tx_port_stats    *hw_tx_port_stats;
 692         rte_iova_t              hw_tx_port_stats_map;
 693         struct tx_port_stats_ext    *hw_tx_port_stats_ext;
 694         rte_iova_t              hw_tx_port_stats_ext_map;
 695         uint16_t                fw_tx_port_stats_ext_size;
 696
 697         /* Default completion ring */
 698         struct bnxt_cp_ring_info        *async_cp_ring;
 699         struct bnxt_cp_ring_info        *rxtx_nq_ring;
 700         uint32_t                max_ring_grps;
 701         struct bnxt_ring_grp_info       *grp_info;
 702
 703         unsigned int            nr_vnics;
 704
 705 #define BNXT_GET_DEFAULT_VNIC(bp)       (&(bp)->vnic_info[0])
 706         struct bnxt_vnic_info   *vnic_info;
 707         STAILQ_HEAD(, bnxt_vnic_info)   free_vnic_list;
 708
 709         struct bnxt_filter_info *filter_info;
 710         STAILQ_HEAD(, bnxt_filter_info) free_filter_list;
 711
 712         struct bnxt_irq         *irq_tbl;
 713
 714         uint8_t                 mac_addr[RTE_ETHER_ADDR_LEN];
 715
 716         uint16_t                        chimp_cmd_seq;
 717         uint16_t                        kong_cmd_seq;
 718         void                            *hwrm_cmd_resp_addr;
 719         rte_iova_t                      hwrm_cmd_resp_dma_addr;
 720         void                            *hwrm_short_cmd_req_addr;
 721         rte_iova_t                      hwrm_short_cmd_req_dma_addr;
 722         rte_spinlock_t                  hwrm_lock;
 723         pthread_mutex_t                 def_cp_lock;
 724         pthread_mutex_t                 health_check_lock;
 725         uint16_t                        max_req_len;
 726         uint16_t                        max_resp_len;
 727         uint16_t                        hwrm_max_ext_req_len;
 728
 729          /* default command timeout value of 500ms */
 730 #define DFLT_HWRM_CMD_TIMEOUT           500000
 731          /* short command timeout value of 50ms */
 732 #define SHORT_HWRM_CMD_TIMEOUT          50000
 733         /* default HWRM request timeout value */
 734         uint32_t                        hwrm_cmd_timeout;
 735
 736         struct bnxt_link_info           *link_info;
 737         struct bnxt_cos_queue_info      *rx_cos_queue;
 738         struct bnxt_cos_queue_info      *tx_cos_queue;
 739         uint8_t                 tx_cosq_id[BNXT_COS_QUEUE_COUNT];
 740         uint8_t                 rx_cosq_cnt;
 741         uint8_t                 max_tc;
 742         uint8_t                 max_lltc;
 743         uint8_t                 max_q;
 744
 745         uint16_t                fw_fid;
 746         uint16_t                max_rsscos_ctx;
 747         uint16_t                max_cp_rings;
 748         uint16_t                max_tx_rings;
 749         uint16_t                max_rx_rings;
 750 #define MAX_STINGRAY_RINGS              128U
 751 /* For sake of symmetry, max Tx rings == max Rx rings, one stat ctx for each */
 752 #define BNXT_MAX_RX_RINGS(bp) \
 753         (BNXT_STINGRAY(bp) ? RTE_MIN(RTE_MIN(bp->max_rx_rings / 2U, \
 754                                              MAX_STINGRAY_RINGS), \
 755                                      bp->max_stat_ctx / 2U) : \
 756                                 RTE_MIN(bp->max_rx_rings / 2U, \
 757                                         bp->max_stat_ctx / 2U))
 758 #define BNXT_MAX_TX_RINGS(bp) \
 759         (RTE_MIN((bp)->max_tx_rings, BNXT_MAX_RX_RINGS(bp)))
 760
 761 #define BNXT_MAX_RINGS(bp) \
 762         (RTE_MIN((((bp)->max_cp_rings - BNXT_NUM_ASYNC_CPR(bp)) / 2U), \
 763                  BNXT_MAX_TX_RINGS(bp)))
 764
 765 #define BNXT_MAX_VF_REP_RINGS   8
 766
 767         uint16_t                max_nq_rings;
 768         uint16_t                max_l2_ctx;
 769         uint16_t                max_rx_em_flows;
 770         uint16_t                max_vnics;
 771         uint16_t                max_stat_ctx;
 772         uint16_t                max_tpa_v2;
 773         uint16_t                first_vf_id;
 774         uint16_t                vlan;
 775 #define BNXT_OUTER_TPID_MASK    0x0000ffff
 776 #define BNXT_OUTER_TPID_BD_MASK 0xffff0000
 777 #define BNXT_OUTER_TPID_BD_SHFT 16
 778         uint32_t                outer_tpid_bd;
 779         struct bnxt_pf_info     *pf;
 780         struct bnxt_parent_info *parent;
 781         uint8_t                 port_cnt;
 782         uint8_t                 vxlan_port_cnt;
 783         uint8_t                 geneve_port_cnt;
 784         uint16_t                vxlan_port;
 785         uint16_t                geneve_port;
 786         uint16_t                vxlan_fw_dst_port_id;
 787         uint16_t                geneve_fw_dst_port_id;
 788         uint32_t                fw_ver;
 789         uint32_t                hwrm_spec_code;
 790
 791         struct bnxt_led_info    *leds;
 792         struct bnxt_ptp_cfg     *ptp_cfg;
 793         uint16_t                vf_resv_strategy;
 794         struct bnxt_ctx_mem_info        *ctx;
 795
 796         uint16_t                fw_reset_min_msecs;
 797         uint16_t                fw_reset_max_msecs;
 798         uint16_t                switch_domain_id;
 799         uint16_t                num_reps;
 800         struct bnxt_rep_info    *rep_info;
 801         uint16_t                *cfa_code_map;
 802         /* Struct to hold adapter error recovery related info */
 803         struct bnxt_error_recovery_info *recovery_info;
 804 #define BNXT_MARK_TABLE_SZ      (sizeof(struct bnxt_mark_info)  * 64 * 1024)
 805 /* TCAM and EM should be 16-bit only. Other modes not supported. */
 806 #define BNXT_FLOW_ID_MASK       0x0000ffff
 807         struct bnxt_mark_info   *mark_table;
 808
 809 #define BNXT_SVIF_INVALID       0xFFFF
 810         uint16_t                func_svif;
 811         uint16_t                port_svif;
 812
 813         struct tf               tfp;
 814         struct bnxt_dmabuf_info dmabuf;
 815         struct bnxt_ulp_context *ulp_ctx;
 816         struct bnxt_flow_stat_info *flow_stat;
 817         uint8_t                 flow_xstat;
 818         uint16_t                max_num_kflows;
 819         uint16_t                tx_cfa_action;
 820 };
 821
 822 #define BNXT_FC_TIMER   1 /* Timer freq in Sec Flow Counters */
 823
 824 /**
 825  * Structure to store private data for each VF representor instance
 826  */
 827 struct bnxt_representor {
 828         uint16_t                switch_domain_id;
 829         uint16_t                vf_id;
 830 #define BNXT_REP_IS_PF          BIT(0)
 831 #define BNXT_REP_Q_R2F_VALID            BIT(1)
 832 #define BNXT_REP_Q_F2R_VALID            BIT(2)
 833 #define BNXT_REP_FC_R2F_VALID           BIT(3)
 834 #define BNXT_REP_FC_F2R_VALID           BIT(4)
 835         uint32_t                flags;
 836         uint16_t                fw_fid;
 837 #define BNXT_DFLT_VNIC_ID_INVALID       0xFFFF
 838         uint16_t                dflt_vnic_id;
 839         uint16_t                svif;
 840         uint16_t                vfr_tx_cfa_action;
 841         uint32_t                dpdk_port_id;
 842         uint32_t                rep_based_pf;
 843         uint8_t                 rep_q_r2f;
 844         uint8_t                 rep_q_f2r;
 845         uint8_t                 rep_fc_r2f;
 846         uint8_t                 rep_fc_f2r;
 847         /* Private data store of associated PF/Trusted VF */
 848         struct rte_eth_dev      *parent_dev;
 849         uint8_t                 mac_addr[RTE_ETHER_ADDR_LEN];
 850         uint8_t                 dflt_mac_addr[RTE_ETHER_ADDR_LEN];
 851         struct bnxt_rx_queue    **rx_queues;
 852         unsigned int            rx_nr_rings;
 853         unsigned int            tx_nr_rings;
 854         uint64_t                tx_pkts[BNXT_MAX_VF_REP_RINGS];
 855         uint64_t                tx_bytes[BNXT_MAX_VF_REP_RINGS];
 856         uint64_t                rx_pkts[BNXT_MAX_VF_REP_RINGS];
 857         uint64_t                rx_bytes[BNXT_MAX_VF_REP_RINGS];
 858         uint64_t                rx_drop_pkts[BNXT_MAX_VF_REP_RINGS];
 859         uint64_t                rx_drop_bytes[BNXT_MAX_VF_REP_RINGS];
 860 };
 861
 862 #define BNXT_REP_PF(vfr_bp)     ((vfr_bp)->flags & BNXT_REP_IS_PF)
 863
 864 struct bnxt_vf_rep_tx_queue {
 865         struct bnxt_tx_queue *txq;
 866         struct bnxt_representor *bp;
 867 };
 868
 869 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
 870 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
 871                      bool exp_link_status);
 872 int bnxt_rcv_msg_from_vf(struct bnxt *bp, uint16_t vf_id, void *msg);
 873 int is_bnxt_in_error(struct bnxt *bp);
 874
 875 int bnxt_map_fw_health_status_regs(struct bnxt *bp);
 876 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index);
 877 void bnxt_schedule_fw_health_check(struct bnxt *bp);
 878
 879 bool is_bnxt_supported(struct rte_eth_dev *dev);
 880 bool bnxt_stratus_device(struct bnxt *bp);
 881 void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 882 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp);
 883 int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
 884                         int wait_to_complete);
 885
 886 extern const struct rte_flow_ops bnxt_flow_ops;
 887
 888 #define bnxt_acquire_flow_lock(bp) \
 889         pthread_mutex_lock(&(bp)->flow_lock)
 890
 891 #define bnxt_release_flow_lock(bp) \
 892         pthread_mutex_unlock(&(bp)->flow_lock)
 893
 894 #define BNXT_VALID_VNIC_OR_RET(bp, vnic_id) do { \
 895         if ((vnic_id) >= (bp)->max_vnics) { \
 896                 rte_flow_error_set(error, \
 897                                 EINVAL, \
 898                                 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, \
 899                                 NULL, \
 900                                 "Group id is invalid!"); \
 901                 rc = -rte_errno; \
 902                 goto ret; \
 903         } \
 904 } while (0)
 905
 906 #define BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)    \
 907                 ((eth_dev)->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
 908
 909 extern int bnxt_logtype_driver;
 910 #define PMD_DRV_LOG_RAW(level, fmt, args...) \
 911         rte_log(RTE_LOG_ ## level, bnxt_logtype_driver, "%s(): " fmt, \
 912                 __func__, ## args)
 913
 914 #define PMD_DRV_LOG(level, fmt, args...) \
 915           PMD_DRV_LOG_RAW(level, fmt, ## args)
 916
 917 extern const struct rte_flow_ops bnxt_ulp_rte_flow_ops;
 918 int32_t bnxt_ulp_port_init(struct bnxt *bp);
 919 void bnxt_ulp_port_deinit(struct bnxt *bp);
 920 int32_t bnxt_ulp_create_df_rules(struct bnxt *bp);
 921 void bnxt_ulp_destroy_df_rules(struct bnxt *bp, bool global);
 922 int32_t
 923 bnxt_ulp_create_vfr_default_rules(struct rte_eth_dev *vfr_ethdev);
 924 int32_t
 925 bnxt_ulp_delete_vfr_default_rules(struct bnxt_representor *vfr);
 926 uint16_t bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type);
 927 uint16_t bnxt_get_svif(uint16_t port_id, bool func_svif,
 928                        enum bnxt_ulp_intf_type type);
 929 uint16_t bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type);
 930 uint16_t bnxt_get_parif(uint16_t port, enum bnxt_ulp_intf_type type);
 931 uint16_t bnxt_get_phy_port_id(uint16_t port);
 932 uint16_t bnxt_get_vport(uint16_t port);
 933 enum bnxt_ulp_intf_type
 934 bnxt_get_interface_type(uint16_t port);
 935 int bnxt_rep_dev_start_op(struct rte_eth_dev *eth_dev);
 936
 937 void bnxt_cancel_fc_thread(struct bnxt *bp);
 938 void bnxt_flow_cnt_alarm_cb(void *arg);
 939 int bnxt_flow_stats_req(struct bnxt *bp);
 940 int bnxt_flow_stats_cnt(struct bnxt *bp);
 941 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp);
 942
 943 int
 944 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
 945                     enum rte_filter_type filter_type,
 946                     enum rte_filter_op filter_op, void *arg);
 947 #endif