1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
11 #include <sys/queue.h>
14 #include <rte_bus_pci.h>
15 #include <rte_ethdev_driver.h>
16 #include <rte_memory.h>
17 #include <rte_lcore.h>
18 #include <rte_spinlock.h>
22 #include "bnxt_util.h"
25 #define PCI_VENDOR_ID_BROADCOM 0x14E4
28 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
29 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
30 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
31 #define BROADCOM_DEV_ID_57414_VF 0x16c1
32 #define BROADCOM_DEV_ID_57301 0x16c8
33 #define BROADCOM_DEV_ID_57302 0x16c9
34 #define BROADCOM_DEV_ID_57304_PF 0x16ca
35 #define BROADCOM_DEV_ID_57304_VF 0x16cb
36 #define BROADCOM_DEV_ID_57417_MF 0x16cc
37 #define BROADCOM_DEV_ID_NS2 0x16cd
38 #define BROADCOM_DEV_ID_57311 0x16ce
39 #define BROADCOM_DEV_ID_57312 0x16cf
40 #define BROADCOM_DEV_ID_57402 0x16d0
41 #define BROADCOM_DEV_ID_57404 0x16d1
42 #define BROADCOM_DEV_ID_57406_PF 0x16d2
43 #define BROADCOM_DEV_ID_57406_VF 0x16d3
44 #define BROADCOM_DEV_ID_57402_MF 0x16d4
45 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
46 #define BROADCOM_DEV_ID_57412 0x16d6
47 #define BROADCOM_DEV_ID_57414 0x16d7
48 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
49 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
50 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
51 #define BROADCOM_DEV_ID_57412_MF 0x16de
52 #define BROADCOM_DEV_ID_57314 0x16df
53 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
54 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
55 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
56 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
57 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
58 #define BROADCOM_DEV_ID_57404_MF 0x16e7
59 #define BROADCOM_DEV_ID_57406_MF 0x16e8
60 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
61 #define BROADCOM_DEV_ID_57407_MF 0x16ea
62 #define BROADCOM_DEV_ID_57414_MF 0x16ec
63 #define BROADCOM_DEV_ID_57416_MF 0x16ee
64 #define BROADCOM_DEV_ID_57508 0x1750
65 #define BROADCOM_DEV_ID_57504 0x1751
66 #define BROADCOM_DEV_ID_57502 0x1752
67 #define BROADCOM_DEV_ID_57508_MF1 0x1800
68 #define BROADCOM_DEV_ID_57504_MF1 0x1801
69 #define BROADCOM_DEV_ID_57502_MF1 0x1802
70 #define BROADCOM_DEV_ID_57508_MF2 0x1803
71 #define BROADCOM_DEV_ID_57504_MF2 0x1804
72 #define BROADCOM_DEV_ID_57502_MF2 0x1805
73 #define BROADCOM_DEV_ID_57500_VF1 0x1806
74 #define BROADCOM_DEV_ID_57500_VF2 0x1807
75 #define BROADCOM_DEV_ID_58802 0xd802
76 #define BROADCOM_DEV_ID_58804 0xd804
77 #define BROADCOM_DEV_ID_58808 0x16f0
78 #define BROADCOM_DEV_ID_58802_VF 0xd800
80 #define BNXT_MAX_MTU 9574
81 #define VLAN_TAG_SIZE 4
82 #define BNXT_NUM_VLANS 2
83 #define BNXT_MAX_PKT_LEN (BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +\
85 (BNXT_NUM_VLANS * VLAN_TAG_SIZE))
86 /* FW adds extra 4 bytes for FCS */
87 #define BNXT_VNIC_MRU(mtu)\
88 ((mtu) + RTE_ETHER_HDR_LEN + VLAN_TAG_SIZE * BNXT_NUM_VLANS)
89 #define BNXT_VF_RSV_NUM_RSS_CTX 1
90 #define BNXT_VF_RSV_NUM_L2_CTX 4
91 /* TODO: For now, do not support VMDq/RFS on VFs. */
92 #define BNXT_VF_RSV_NUM_VNIC 1
93 #define BNXT_MAX_LED 4
94 #define BNXT_MIN_RING_DESC 16
95 #define BNXT_MAX_TX_RING_DESC 4096
96 #define BNXT_MAX_RX_RING_DESC 8192
97 #define BNXT_DB_SIZE 0x80
99 #define TPA_MAX_AGGS 64
100 #define TPA_MAX_AGGS_TH 1024
102 #define TPA_MAX_NUM_SEGS 32
103 #define TPA_MAX_SEGS_TH 8 /* 32 segments in 4-segment units */
104 #define TPA_MAX_SEGS 5 /* 32 segments in log2 units */
106 #define BNXT_TPA_MAX_AGGS(bp) \
107 (BNXT_CHIP_THOR(bp) ? TPA_MAX_AGGS_TH : \
110 #define BNXT_TPA_MAX_SEGS(bp) \
111 (BNXT_CHIP_THOR(bp) ? TPA_MAX_SEGS_TH : \
114 #ifdef RTE_ARCH_ARM64
115 #define BNXT_NUM_ASYNC_CPR(bp) (BNXT_STINGRAY(bp) ? 0 : 1)
117 #define BNXT_NUM_ASYNC_CPR(bp) 1
120 /* In FreeBSD OS, nic_uio driver does not support interrupts */
121 #ifdef RTE_EXEC_ENV_FREEBSD
122 #ifdef BNXT_NUM_ASYNC_CPR
123 #undef BNXT_NUM_ASYNC_CPR
125 #define BNXT_NUM_ASYNC_CPR(bp) 0
128 #define BNXT_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
129 #define BNXT_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
131 /* Chimp Communication Channel */
132 #define GRCPF_REG_CHIMP_CHANNEL_OFFSET 0x0
133 #define GRCPF_REG_CHIMP_COMM_TRIGGER 0x100
134 /* Kong Communication Channel */
135 #define GRCPF_REG_KONG_CHANNEL_OFFSET 0xA00
136 #define GRCPF_REG_KONG_COMM_TRIGGER 0xB00
138 #define BNXT_INT_LAT_TMR_MIN 75
139 #define BNXT_INT_LAT_TMR_MAX 150
140 #define BNXT_NUM_CMPL_AGGR_INT 36
141 #define BNXT_CMPL_AGGR_DMA_TMR 37
142 #define BNXT_NUM_CMPL_DMA_AGGR 36
143 #define BNXT_CMPL_AGGR_DMA_TMR_DURING_INT 50
144 #define BNXT_NUM_CMPL_DMA_AGGR_DURING_INT 12
146 struct bnxt_led_info {
149 uint8_t led_group_id;
151 uint16_t led_state_caps;
152 #define BNXT_LED_ALT_BLINK_CAP(x) ((x) & \
153 rte_cpu_to_le_16(HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT))
155 uint16_t led_color_caps;
158 struct bnxt_led_cfg {
163 uint16_t led_blink_on;
164 uint16_t led_blink_off;
165 uint8_t led_group_id;
169 #define BNXT_LED_DFLT_ENA \
170 (HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID | \
171 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE | \
172 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON | \
173 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF | \
174 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID)
176 #define BNXT_LED_DFLT_ENA_SHIFT 6
178 #define BNXT_LED_DFLT_ENABLES(x) \
179 rte_cpu_to_le_32(BNXT_LED_DFLT_ENA << (BNXT_LED_DFLT_ENA_SHIFT * (x)))
181 enum bnxt_hw_context {
183 HW_CONTEXT_IS_RSS = 1,
184 HW_CONTEXT_IS_COS = 2,
185 HW_CONTEXT_IS_LB = 3,
188 struct bnxt_vlan_table_entry {
191 } __attribute__((packed));
193 struct bnxt_vlan_antispoof_table_entry {
197 } __attribute__((packed));
199 struct bnxt_child_vf_info {
201 struct bnxt_vlan_table_entry *vlan_table;
202 struct bnxt_vlan_antispoof_table_entry *vlan_as_table;
203 STAILQ_HEAD(, bnxt_filter_info) filter;
204 uint32_t func_cfg_flags;
207 uint16_t max_tx_rate;
210 uint8_t mac_spoof_en;
211 uint8_t vlan_spoof_en;
216 struct bnxt_pf_info {
217 #define BNXT_FIRST_PF_FID 1
218 #define BNXT_MAX_VFS(bp) (bp->pf.max_vfs)
219 #define BNXT_TOTAL_VFS(bp) ((bp)->pf.total_vfs)
220 #define BNXT_FIRST_VF_FID 128
221 #define BNXT_PF_RINGS_USED(bp) bnxt_get_num_queues(bp)
222 #define BNXT_PF_RINGS_AVAIL(bp) (bp->pf.max_cp_rings - BNXT_PF_RINGS_USED(bp))
224 uint16_t first_vf_id;
227 uint16_t total_vfs; /* Total VFs possible.
228 * Not necessarily enabled.
230 uint32_t func_cfg_flags;
232 rte_iova_t vf_req_buf_dma_addr;
233 uint32_t vf_req_fwd[8];
234 uint16_t total_vnics;
235 struct bnxt_child_vf_info *vf_info;
236 #define BNXT_EVB_MODE_NONE 0
237 #define BNXT_EVB_MODE_VEB 1
238 #define BNXT_EVB_MODE_VEPA 2
242 /* Max wait time for link up is 10s and link down is 500ms */
243 #define BNXT_LINK_UP_WAIT_CNT 200
244 #define BNXT_LINK_DOWN_WAIT_CNT 10
245 #define BNXT_LINK_WAIT_INTERVAL 50
246 struct bnxt_link_info {
249 uint8_t phy_link_status;
257 #define PHY_VER_LEN 3
258 uint8_t phy_ver[PHY_VER_LEN];
260 uint16_t support_speeds;
261 uint16_t auto_link_speed;
262 uint16_t force_link_speed;
263 uint16_t auto_link_speed_mask;
264 uint32_t preemphasis;
269 #define BNXT_COS_QUEUE_COUNT 8
270 struct bnxt_cos_queue_info {
276 STAILQ_ENTRY(rte_flow) next;
277 struct bnxt_filter_info *filter;
278 struct bnxt_vnic_info *vnic;
281 #define BNXT_PTP_FLAGS_PATH_TX 0x0
282 #define BNXT_PTP_FLAGS_PATH_RX 0x1
283 #define BNXT_PTP_FLAGS_CURRENT_TIME 0x2
285 struct bnxt_ptp_cfg {
286 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400
287 #define BNXT_GRCPF_REG_SYNC_TIME 0x480
288 #define BNXT_CYCLECOUNTER_MASK 0xffffffffffffffffULL
289 struct rte_timecounter tc;
290 struct rte_timecounter tx_tstamp_tc;
291 struct rte_timecounter rx_tstamp_tc;
293 #define BNXT_MAX_TX_TS 1
295 #define BNXT_PTP_MSG_SYNC BIT(0)
296 #define BNXT_PTP_MSG_DELAY_REQ BIT(1)
297 #define BNXT_PTP_MSG_PDELAY_REQ BIT(2)
298 #define BNXT_PTP_MSG_PDELAY_RESP BIT(3)
299 #define BNXT_PTP_MSG_FOLLOW_UP BIT(8)
300 #define BNXT_PTP_MSG_DELAY_RESP BIT(9)
301 #define BNXT_PTP_MSG_PDELAY_RESP_FOLLOW_UP BIT(10)
302 #define BNXT_PTP_MSG_ANNOUNCE BIT(11)
303 #define BNXT_PTP_MSG_SIGNALING BIT(12)
304 #define BNXT_PTP_MSG_MANAGEMENT BIT(13)
305 #define BNXT_PTP_MSG_EVENTS (BNXT_PTP_MSG_SYNC | \
306 BNXT_PTP_MSG_DELAY_REQ | \
307 BNXT_PTP_MSG_PDELAY_REQ | \
308 BNXT_PTP_MSG_PDELAY_RESP)
309 uint8_t tx_tstamp_en:1;
312 #define BNXT_PTP_RX_TS_L 0
313 #define BNXT_PTP_RX_TS_H 1
314 #define BNXT_PTP_RX_SEQ 2
315 #define BNXT_PTP_RX_FIFO 3
316 #define BNXT_PTP_RX_FIFO_PENDING 0x1
317 #define BNXT_PTP_RX_FIFO_ADV 4
318 #define BNXT_PTP_RX_REGS 5
320 #define BNXT_PTP_TX_TS_L 0
321 #define BNXT_PTP_TX_TS_H 1
322 #define BNXT_PTP_TX_SEQ 2
323 #define BNXT_PTP_TX_FIFO 3
324 #define BNXT_PTP_TX_FIFO_EMPTY 0x2
325 #define BNXT_PTP_TX_REGS 4
326 uint32_t rx_regs[BNXT_PTP_RX_REGS];
327 uint32_t rx_mapped_regs[BNXT_PTP_RX_REGS];
328 uint32_t tx_regs[BNXT_PTP_TX_REGS];
329 uint32_t tx_mapped_regs[BNXT_PTP_TX_REGS];
331 /* On Thor, the Rx timestamp is present in the Rx completion record */
332 uint64_t rx_timestamp;
336 uint16_t num_cmpl_aggr_int;
337 uint16_t num_cmpl_dma_aggr;
338 uint16_t num_cmpl_dma_aggr_during_int;
339 uint16_t int_lat_tmr_max;
340 uint16_t int_lat_tmr_min;
341 uint16_t cmpl_aggr_dma_tmr;
342 uint16_t cmpl_aggr_dma_tmr_during_int;
345 /* 64-bit doorbell */
346 #define DBR_XID_SFT 32
347 #define DBR_PATH_L2 (0x1ULL << 56)
348 #define DBR_TYPE_SQ (0x0ULL << 60)
349 #define DBR_TYPE_SRQ (0x2ULL << 60)
350 #define DBR_TYPE_CQ (0x4ULL << 60)
351 #define DBR_TYPE_NQ (0xaULL << 60)
352 #define DBR_TYPE_NQ_ARM (0xbULL << 60)
354 #define BNXT_RSS_TBL_SIZE_THOR 512
355 #define BNXT_RSS_ENTRIES_PER_CTX_THOR 64
356 #define BNXT_MAX_RSS_CTXTS_THOR \
357 (BNXT_RSS_TBL_SIZE_THOR / BNXT_RSS_ENTRIES_PER_CTX_THOR)
359 #define BNXT_MAX_TC 8
360 #define BNXT_MAX_QUEUE 8
361 #define BNXT_MAX_TC_Q (BNXT_MAX_TC + 1)
362 #define BNXT_MAX_Q (bp->max_q + 1)
363 #define BNXT_PAGE_SHFT 12
364 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHFT)
365 #define MAX_CTX_PAGES (BNXT_PAGE_SIZE / 8)
367 #define PTU_PTE_VALID 0x1UL
368 #define PTU_PTE_LAST 0x2UL
369 #define PTU_PTE_NEXT_TO_LAST 0x4UL
371 struct bnxt_ring_mem_info {
375 #define BNXT_RMEM_VALID_PTE_FLAG 1
376 #define BNXT_RMEM_RING_PTE_FLAG 2
380 const struct rte_memzone *mz;
383 rte_iova_t pg_tbl_map;
384 const struct rte_memzone *pg_tbl_mz;
390 struct bnxt_ctx_pg_info {
392 void *ctx_pg_arr[MAX_CTX_PAGES];
393 rte_iova_t ctx_dma_arr[MAX_CTX_PAGES];
394 struct bnxt_ring_mem_info ring_mem;
397 struct bnxt_ctx_mem_info {
398 uint32_t qp_max_entries;
399 uint16_t qp_min_qp1_entries;
400 uint16_t qp_max_l2_entries;
401 uint16_t qp_entry_size;
402 uint16_t srq_max_l2_entries;
403 uint32_t srq_max_entries;
404 uint16_t srq_entry_size;
405 uint16_t cq_max_l2_entries;
406 uint32_t cq_max_entries;
407 uint16_t cq_entry_size;
408 uint16_t vnic_max_vnic_entries;
409 uint16_t vnic_max_ring_table_entries;
410 uint16_t vnic_entry_size;
411 uint32_t stat_max_entries;
412 uint16_t stat_entry_size;
413 uint16_t tqm_entry_size;
414 uint32_t tqm_min_entries_per_ring;
415 uint32_t tqm_max_entries_per_ring;
416 uint32_t mrav_max_entries;
417 uint16_t mrav_entry_size;
418 uint16_t tim_entry_size;
419 uint32_t tim_max_entries;
420 uint8_t tqm_entries_multiple;
423 #define BNXT_CTX_FLAG_INITED 0x01
425 struct bnxt_ctx_pg_info qp_mem;
426 struct bnxt_ctx_pg_info srq_mem;
427 struct bnxt_ctx_pg_info cq_mem;
428 struct bnxt_ctx_pg_info vnic_mem;
429 struct bnxt_ctx_pg_info stat_mem;
430 struct bnxt_ctx_pg_info *tqm_mem[BNXT_MAX_TC_Q];
433 /* Maximum Firmware Reset bail out value in milliseconds */
434 #define BNXT_MAX_FW_RESET_TIMEOUT 6000
435 /* Minimum time required for the firmware readiness in milliseconds */
436 #define BNXT_MIN_FW_READY_TIMEOUT 2000
437 /* Frequency for the firmware readiness check in milliseconds */
438 #define BNXT_FW_READY_WAIT_INTERVAL 100
440 #define US_PER_MS 1000
441 #define NS_PER_US 1000
443 struct bnxt_error_recovery_info {
444 /* All units in milliseconds */
445 uint32_t driver_polling_freq;
446 uint32_t master_func_wait_period;
447 uint32_t normal_func_wait_period;
448 uint32_t master_func_wait_period_after_reset;
449 uint32_t max_bailout_time_after_reset;
450 #define BNXT_FW_STATUS_REG 0
451 #define BNXT_FW_HEARTBEAT_CNT_REG 1
452 #define BNXT_FW_RECOVERY_CNT_REG 2
453 #define BNXT_FW_RESET_INPROG_REG 3
454 #define BNXT_FW_STATUS_REG_CNT 4
455 uint32_t status_regs[BNXT_FW_STATUS_REG_CNT];
456 uint32_t mapped_status_regs[BNXT_FW_STATUS_REG_CNT];
457 uint32_t reset_inprogress_reg_mask;
458 #define BNXT_NUM_RESET_REG 16
459 uint8_t reg_array_cnt;
460 uint32_t reset_reg[BNXT_NUM_RESET_REG];
461 uint32_t reset_reg_val[BNXT_NUM_RESET_REG];
462 uint8_t delay_after_reset[BNXT_NUM_RESET_REG];
463 #define BNXT_FLAG_ERROR_RECOVERY_HOST BIT(0)
464 #define BNXT_FLAG_ERROR_RECOVERY_CO_CPU BIT(1)
465 #define BNXT_FLAG_MASTER_FUNC BIT(2)
466 #define BNXT_FLAG_RECOVERY_ENABLED BIT(3)
469 uint32_t last_heart_beat;
470 uint32_t last_reset_counter;
473 /* address space location of register */
474 #define BNXT_FW_STATUS_REG_TYPE_MASK 3
475 /* register is located in PCIe config space */
476 #define BNXT_FW_STATUS_REG_TYPE_CFG 0
477 /* register is located in GRC address space */
478 #define BNXT_FW_STATUS_REG_TYPE_GRC 1
479 /* register is located in BAR0 */
480 #define BNXT_FW_STATUS_REG_TYPE_BAR0 2
481 /* register is located in BAR1 */
482 #define BNXT_FW_STATUS_REG_TYPE_BAR1 3
484 #define BNXT_FW_STATUS_REG_TYPE(reg) ((reg) & BNXT_FW_STATUS_REG_TYPE_MASK)
485 #define BNXT_FW_STATUS_REG_OFF(reg) ((reg) & ~BNXT_FW_STATUS_REG_TYPE_MASK)
487 #define BNXT_GRCP_WINDOW_2_BASE 0x2000
488 #define BNXT_GRCP_WINDOW_3_BASE 0x3000
490 #define BNXT_FW_STATUS_SHUTDOWN 0x100000
492 #define BNXT_HWRM_SHORT_REQ_LEN sizeof(struct hwrm_short_input)
496 struct rte_eth_dev *eth_dev;
497 struct rte_eth_rss_conf rss_conf;
498 struct rte_pci_device *pdev;
502 #define BNXT_FLAG_REGISTERED BIT(0)
503 #define BNXT_FLAG_VF BIT(1)
504 #define BNXT_FLAG_PORT_STATS BIT(2)
505 #define BNXT_FLAG_JUMBO BIT(3)
506 #define BNXT_FLAG_SHORT_CMD BIT(4)
507 #define BNXT_FLAG_UPDATE_HASH BIT(5)
508 #define BNXT_FLAG_PTP_SUPPORTED BIT(6)
509 #define BNXT_FLAG_MULTI_HOST BIT(7)
510 #define BNXT_FLAG_EXT_RX_PORT_STATS BIT(8)
511 #define BNXT_FLAG_EXT_TX_PORT_STATS BIT(9)
512 #define BNXT_FLAG_KONG_MB_EN BIT(10)
513 #define BNXT_FLAG_TRUSTED_VF_EN BIT(11)
514 #define BNXT_FLAG_DFLT_VNIC_SET BIT(12)
515 #define BNXT_FLAG_THOR_CHIP BIT(13)
516 #define BNXT_FLAG_STINGRAY BIT(14)
517 #define BNXT_FLAG_FW_RESET BIT(15)
518 #define BNXT_FLAG_FATAL_ERROR BIT(16)
519 #define BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE BIT(17)
520 #define BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED BIT(18)
521 #define BNXT_FLAG_EXT_STATS_SUPPORTED BIT(19)
522 #define BNXT_FLAG_NEW_RM BIT(20)
523 #define BNXT_FLAG_INIT_DONE BIT(21)
524 #define BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS BIT(22)
525 #define BNXT_FLAG_ADV_FLOW_MGMT BIT(23)
526 #define BNXT_FLAG_RX_VECTOR_PKT_MODE BIT(24)
527 #define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF))
528 #define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF)
529 #define BNXT_NPAR(bp) ((bp)->port_partition_type)
530 #define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST)
531 #define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
532 #define BNXT_USE_CHIMP_MB 0 //For non-CFA commands, everything uses Chimp.
533 #define BNXT_USE_KONG(bp) ((bp)->flags & BNXT_FLAG_KONG_MB_EN)
534 #define BNXT_VF_IS_TRUSTED(bp) ((bp)->flags & BNXT_FLAG_TRUSTED_VF_EN)
535 #define BNXT_CHIP_THOR(bp) ((bp)->flags & BNXT_FLAG_THOR_CHIP)
536 #define BNXT_STINGRAY(bp) ((bp)->flags & BNXT_FLAG_STINGRAY)
537 #define BNXT_HAS_NQ(bp) BNXT_CHIP_THOR(bp)
538 #define BNXT_HAS_RING_GRPS(bp) (!BNXT_CHIP_THOR(bp))
541 #define BNXT_FW_CAP_HOT_RESET BIT(0)
542 #define BNXT_FW_CAP_IF_CHANGE BIT(1)
543 #define BNXT_FW_CAP_ERROR_RECOVERY BIT(2)
544 #define BNXT_FW_CAP_ERR_RECOVER_RELOAD BIT(3)
547 #define BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN BIT(0)
548 pthread_mutex_t flow_lock;
550 uint32_t vnic_cap_flags;
551 #define BNXT_VNIC_CAP_COS_CLASSIFY BIT(0)
552 unsigned int rx_nr_rings;
553 unsigned int rx_cp_nr_rings;
554 unsigned int rx_num_qs_per_vnic;
555 struct bnxt_rx_queue **rx_queues;
556 const void *rx_mem_zone;
557 struct rx_port_stats *hw_rx_port_stats;
558 rte_iova_t hw_rx_port_stats_map;
559 struct rx_port_stats_ext *hw_rx_port_stats_ext;
560 rte_iova_t hw_rx_port_stats_ext_map;
561 uint16_t fw_rx_port_stats_ext_size;
563 unsigned int tx_nr_rings;
564 unsigned int tx_cp_nr_rings;
565 struct bnxt_tx_queue **tx_queues;
566 const void *tx_mem_zone;
567 struct tx_port_stats *hw_tx_port_stats;
568 rte_iova_t hw_tx_port_stats_map;
569 struct tx_port_stats_ext *hw_tx_port_stats_ext;
570 rte_iova_t hw_tx_port_stats_ext_map;
571 uint16_t fw_tx_port_stats_ext_size;
573 /* Default completion ring */
574 struct bnxt_cp_ring_info *async_cp_ring;
575 struct bnxt_cp_ring_info *rxtx_nq_ring;
576 uint32_t max_ring_grps;
577 struct bnxt_ring_grp_info *grp_info;
579 unsigned int nr_vnics;
581 #define BNXT_GET_DEFAULT_VNIC(bp) (&(bp)->vnic_info[0])
582 struct bnxt_vnic_info *vnic_info;
583 STAILQ_HEAD(, bnxt_vnic_info) free_vnic_list;
585 struct bnxt_filter_info *filter_info;
586 STAILQ_HEAD(, bnxt_filter_info) free_filter_list;
588 struct bnxt_irq *irq_tbl;
590 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
592 uint16_t hwrm_cmd_seq;
593 uint16_t kong_cmd_seq;
594 void *hwrm_cmd_resp_addr;
595 rte_iova_t hwrm_cmd_resp_dma_addr;
596 void *hwrm_short_cmd_req_addr;
597 rte_iova_t hwrm_short_cmd_req_dma_addr;
598 rte_spinlock_t hwrm_lock;
599 pthread_mutex_t def_cp_lock;
600 uint16_t max_req_len;
601 uint16_t max_resp_len;
602 uint16_t hwrm_max_ext_req_len;
604 /* default command timeout value of 50ms */
605 #define HWRM_CMD_TIMEOUT 50000
606 /* default HWRM request timeout value */
607 uint32_t hwrm_cmd_timeout;
609 struct bnxt_link_info link_info;
610 struct bnxt_cos_queue_info rx_cos_queue[BNXT_COS_QUEUE_COUNT];
611 struct bnxt_cos_queue_info tx_cos_queue[BNXT_COS_QUEUE_COUNT];
612 uint8_t tx_cosq_id[BNXT_COS_QUEUE_COUNT];
619 uint8_t dflt_mac_addr[RTE_ETHER_ADDR_LEN];
620 uint16_t max_rsscos_ctx;
621 uint16_t max_cp_rings;
622 uint16_t max_tx_rings;
623 uint16_t max_rx_rings;
624 #define MAX_STINGRAY_RINGS 128U
625 /* For sake of symmetry, max Tx rings == max Rx rings, one stat ctx for each */
626 #define BNXT_MAX_RX_RINGS(bp) \
627 (BNXT_STINGRAY(bp) ? RTE_MIN(RTE_MIN(bp->max_rx_rings, \
628 MAX_STINGRAY_RINGS), \
629 bp->max_stat_ctx / 2U) : \
630 RTE_MIN(bp->max_rx_rings, \
631 bp->max_stat_ctx / 2U))
632 #define BNXT_MAX_TX_RINGS(bp) \
633 (RTE_MIN((bp)->max_tx_rings, BNXT_MAX_RX_RINGS(bp)))
635 #define BNXT_MAX_RINGS(bp) \
636 (RTE_MIN((((bp)->max_cp_rings - BNXT_NUM_ASYNC_CPR(bp)) / 2U), \
637 BNXT_MAX_TX_RINGS(bp)))
638 uint16_t max_nq_rings;
640 uint16_t max_rx_em_flows;
642 uint16_t max_stat_ctx;
644 uint16_t first_vf_id;
646 #define BNXT_OUTER_TPID_MASK 0x0000ffff
647 #define BNXT_OUTER_TPID_BD_MASK 0xffff0000
648 #define BNXT_OUTER_TPID_BD_SHFT 16
649 uint32_t outer_tpid_bd;
650 struct bnxt_pf_info pf;
651 uint8_t port_partition_type;
653 uint8_t vxlan_port_cnt;
654 uint8_t geneve_port_cnt;
656 uint16_t geneve_port;
657 uint16_t vxlan_fw_dst_port_id;
658 uint16_t geneve_fw_dst_port_id;
660 uint32_t hwrm_spec_code;
662 struct bnxt_led_info leds[BNXT_MAX_LED];
664 struct bnxt_ptp_cfg *ptp_cfg;
665 uint16_t vf_resv_strategy;
666 struct bnxt_ctx_mem_info *ctx;
668 uint16_t fw_reset_min_msecs;
669 uint16_t fw_reset_max_msecs;
671 /* Struct to hold adapter error recovery related info */
672 struct bnxt_error_recovery_info *recovery_info;
673 #define BNXT_MARK_TABLE_SZ (sizeof(uint32_t) * 64 * 1024)
674 /* TCAM and EM should be 16-bit only. Other modes not supported. */
675 #define BNXT_FLOW_ID_MASK 0x0000ffff
676 uint32_t *mark_table;
679 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
680 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
681 bool exp_link_status);
682 int bnxt_rcv_msg_from_vf(struct bnxt *bp, uint16_t vf_id, void *msg);
683 int is_bnxt_in_error(struct bnxt *bp);
684 uint16_t bnxt_rss_ctxts(const struct bnxt *bp);
686 int bnxt_map_fw_health_status_regs(struct bnxt *bp);
687 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index);
688 void bnxt_schedule_fw_health_check(struct bnxt *bp);
690 bool is_bnxt_supported(struct rte_eth_dev *dev);
691 bool bnxt_stratus_device(struct bnxt *bp);
692 extern const struct rte_flow_ops bnxt_flow_ops;
693 #define bnxt_acquire_flow_lock(bp) \
694 pthread_mutex_lock(&(bp)->flow_lock)
696 #define bnxt_release_flow_lock(bp) \
697 pthread_mutex_unlock(&(bp)->flow_lock)
699 #define BNXT_VALID_VNIC_OR_RET(bp, vnic_id) do { \
700 if ((vnic_id) >= (bp)->max_vnics) { \
701 rte_flow_error_set(error, \
703 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, \
705 "Group id is invalid!"); \
711 extern int bnxt_logtype_driver;
712 #define PMD_DRV_LOG_RAW(level, fmt, args...) \
713 rte_log(RTE_LOG_ ## level, bnxt_logtype_driver, "%s(): " fmt, \
716 #define PMD_DRV_LOG(level, fmt, args...) \
717 PMD_DRV_LOG_RAW(level, fmt, ## args)