1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
11 #include <sys/queue.h>
14 #include <rte_bus_pci.h>
15 #include <rte_ethdev_driver.h>
16 #include <rte_memory.h>
17 #include <rte_lcore.h>
18 #include <rte_spinlock.h>
22 #include "bnxt_util.h"
24 #define BNXT_MAX_MTU 9574
25 #define VLAN_TAG_SIZE 4
26 #define BNXT_NUM_VLANS 2
27 #define BNXT_MAX_PKT_LEN (BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +\
29 (BNXT_NUM_VLANS * VLAN_TAG_SIZE))
30 #define BNXT_VF_RSV_NUM_RSS_CTX 1
31 #define BNXT_VF_RSV_NUM_L2_CTX 4
32 /* TODO: For now, do not support VMDq/RFS on VFs. */
33 #define BNXT_VF_RSV_NUM_VNIC 1
34 #define BNXT_MAX_LED 4
35 #define BNXT_MIN_RING_DESC 16
36 #define BNXT_MAX_TX_RING_DESC 4096
37 #define BNXT_MAX_RX_RING_DESC 8192
38 #define BNXT_DB_SIZE 0x80
41 #define BNXT_NUM_ASYNC_CPR(bp) (BNXT_STINGRAY(bp) ? 0 : 1)
43 #define BNXT_NUM_ASYNC_CPR(bp) 1
46 /* Chimp Communication Channel */
47 #define GRCPF_REG_CHIMP_CHANNEL_OFFSET 0x0
48 #define GRCPF_REG_CHIMP_COMM_TRIGGER 0x100
49 /* Kong Communication Channel */
50 #define GRCPF_REG_KONG_CHANNEL_OFFSET 0xA00
51 #define GRCPF_REG_KONG_COMM_TRIGGER 0xB00
53 #define BNXT_INT_LAT_TMR_MIN 75
54 #define BNXT_INT_LAT_TMR_MAX 150
55 #define BNXT_NUM_CMPL_AGGR_INT 36
56 #define BNXT_CMPL_AGGR_DMA_TMR 37
57 #define BNXT_NUM_CMPL_DMA_AGGR 36
58 #define BNXT_CMPL_AGGR_DMA_TMR_DURING_INT 50
59 #define BNXT_NUM_CMPL_DMA_AGGR_DURING_INT 12
61 struct bnxt_led_info {
66 uint16_t led_state_caps;
67 #define BNXT_LED_ALT_BLINK_CAP(x) ((x) & \
68 rte_cpu_to_le_16(HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT))
70 uint16_t led_color_caps;
78 uint16_t led_blink_on;
79 uint16_t led_blink_off;
84 #define BNXT_LED_DFLT_ENA \
85 (HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID | \
86 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE | \
87 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON | \
88 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF | \
89 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID)
91 #define BNXT_LED_DFLT_ENA_SHIFT 6
93 #define BNXT_LED_DFLT_ENABLES(x) \
94 rte_cpu_to_le_32(BNXT_LED_DFLT_ENA << (BNXT_LED_DFLT_ENA_SHIFT * (x)))
96 enum bnxt_hw_context {
98 HW_CONTEXT_IS_RSS = 1,
99 HW_CONTEXT_IS_COS = 2,
100 HW_CONTEXT_IS_LB = 3,
103 struct bnxt_vlan_table_entry {
106 } __attribute__((packed));
108 struct bnxt_vlan_antispoof_table_entry {
112 } __attribute__((packed));
114 struct bnxt_child_vf_info {
116 struct bnxt_vlan_table_entry *vlan_table;
117 struct bnxt_vlan_antispoof_table_entry *vlan_as_table;
118 STAILQ_HEAD(, bnxt_filter_info) filter;
119 uint32_t func_cfg_flags;
122 uint16_t max_tx_rate;
125 uint8_t mac_spoof_en;
126 uint8_t vlan_spoof_en;
131 struct bnxt_pf_info {
132 #define BNXT_FIRST_PF_FID 1
133 #define BNXT_MAX_VFS(bp) (bp->pf.max_vfs)
134 #define BNXT_TOTAL_VFS(bp) ((bp)->pf.total_vfs)
135 #define BNXT_FIRST_VF_FID 128
136 #define BNXT_PF_RINGS_USED(bp) bnxt_get_num_queues(bp)
137 #define BNXT_PF_RINGS_AVAIL(bp) (bp->pf.max_cp_rings - BNXT_PF_RINGS_USED(bp))
139 uint16_t first_vf_id;
142 uint16_t total_vfs; /* Total VFs possible.
143 * Not necessarily enabled.
145 uint32_t func_cfg_flags;
147 rte_iova_t vf_req_buf_dma_addr;
148 uint32_t vf_req_fwd[8];
149 uint16_t total_vnics;
150 struct bnxt_child_vf_info *vf_info;
151 #define BNXT_EVB_MODE_NONE 0
152 #define BNXT_EVB_MODE_VEB 1
153 #define BNXT_EVB_MODE_VEPA 2
157 /* Max wait time is 10 * 100ms = 1s */
158 #define BNXT_LINK_WAIT_CNT 10
159 #define BNXT_LINK_WAIT_INTERVAL 100
160 struct bnxt_link_info {
163 uint8_t phy_link_status;
171 #define PHY_VER_LEN 3
172 uint8_t phy_ver[PHY_VER_LEN];
174 uint16_t support_speeds;
175 uint16_t auto_link_speed;
176 uint16_t force_link_speed;
177 uint16_t auto_link_speed_mask;
178 uint32_t preemphasis;
183 #define BNXT_COS_QUEUE_COUNT 8
184 struct bnxt_cos_queue_info {
190 STAILQ_ENTRY(rte_flow) next;
191 struct bnxt_filter_info *filter;
192 struct bnxt_vnic_info *vnic;
195 #define BNXT_PTP_FLAGS_PATH_TX 0x0
196 #define BNXT_PTP_FLAGS_PATH_RX 0x1
197 #define BNXT_PTP_FLAGS_CURRENT_TIME 0x2
199 struct bnxt_ptp_cfg {
200 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400
201 #define BNXT_GRCPF_REG_SYNC_TIME 0x480
202 #define BNXT_CYCLECOUNTER_MASK 0xffffffffffffffffULL
203 struct rte_timecounter tc;
204 struct rte_timecounter tx_tstamp_tc;
205 struct rte_timecounter rx_tstamp_tc;
207 #define BNXT_MAX_TX_TS 1
209 #define BNXT_PTP_MSG_SYNC BIT(0)
210 #define BNXT_PTP_MSG_DELAY_REQ BIT(1)
211 #define BNXT_PTP_MSG_PDELAY_REQ BIT(2)
212 #define BNXT_PTP_MSG_PDELAY_RESP BIT(3)
213 #define BNXT_PTP_MSG_FOLLOW_UP BIT(8)
214 #define BNXT_PTP_MSG_DELAY_RESP BIT(9)
215 #define BNXT_PTP_MSG_PDELAY_RESP_FOLLOW_UP BIT(10)
216 #define BNXT_PTP_MSG_ANNOUNCE BIT(11)
217 #define BNXT_PTP_MSG_SIGNALING BIT(12)
218 #define BNXT_PTP_MSG_MANAGEMENT BIT(13)
219 #define BNXT_PTP_MSG_EVENTS (BNXT_PTP_MSG_SYNC | \
220 BNXT_PTP_MSG_DELAY_REQ | \
221 BNXT_PTP_MSG_PDELAY_REQ | \
222 BNXT_PTP_MSG_PDELAY_RESP)
223 uint8_t tx_tstamp_en:1;
226 #define BNXT_PTP_RX_TS_L 0
227 #define BNXT_PTP_RX_TS_H 1
228 #define BNXT_PTP_RX_SEQ 2
229 #define BNXT_PTP_RX_FIFO 3
230 #define BNXT_PTP_RX_FIFO_PENDING 0x1
231 #define BNXT_PTP_RX_FIFO_ADV 4
232 #define BNXT_PTP_RX_REGS 5
234 #define BNXT_PTP_TX_TS_L 0
235 #define BNXT_PTP_TX_TS_H 1
236 #define BNXT_PTP_TX_SEQ 2
237 #define BNXT_PTP_TX_FIFO 3
238 #define BNXT_PTP_TX_FIFO_EMPTY 0x2
239 #define BNXT_PTP_TX_REGS 4
240 uint32_t rx_regs[BNXT_PTP_RX_REGS];
241 uint32_t rx_mapped_regs[BNXT_PTP_RX_REGS];
242 uint32_t tx_regs[BNXT_PTP_TX_REGS];
243 uint32_t tx_mapped_regs[BNXT_PTP_TX_REGS];
245 /* On Thor, the Rx timestamp is present in the Rx completion record */
246 uint64_t rx_timestamp;
250 uint16_t num_cmpl_aggr_int;
251 uint16_t num_cmpl_dma_aggr;
252 uint16_t num_cmpl_dma_aggr_during_int;
253 uint16_t int_lat_tmr_max;
254 uint16_t int_lat_tmr_min;
255 uint16_t cmpl_aggr_dma_tmr;
256 uint16_t cmpl_aggr_dma_tmr_during_int;
259 /* 64-bit doorbell */
260 #define DBR_XID_SFT 32
261 #define DBR_PATH_L2 (0x1ULL << 56)
262 #define DBR_TYPE_SQ (0x0ULL << 60)
263 #define DBR_TYPE_SRQ (0x2ULL << 60)
264 #define DBR_TYPE_CQ (0x4ULL << 60)
265 #define DBR_TYPE_NQ (0xaULL << 60)
266 #define DBR_TYPE_NQ_ARM (0xbULL << 60)
268 #define BNXT_RSS_TBL_SIZE_THOR 512
269 #define BNXT_RSS_ENTRIES_PER_CTX_THOR 64
270 #define BNXT_MAX_RSS_CTXTS_THOR \
271 (BNXT_RSS_TBL_SIZE_THOR / BNXT_RSS_ENTRIES_PER_CTX_THOR)
273 #define BNXT_MAX_TC 8
274 #define BNXT_MAX_QUEUE 8
275 #define BNXT_MAX_TC_Q (BNXT_MAX_TC + 1)
276 #define BNXT_MAX_Q (bp->max_q + 1)
277 #define BNXT_PAGE_SHFT 12
278 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHFT)
279 #define MAX_CTX_PAGES (BNXT_PAGE_SIZE / 8)
281 #define PTU_PTE_VALID 0x1UL
282 #define PTU_PTE_LAST 0x2UL
283 #define PTU_PTE_NEXT_TO_LAST 0x4UL
285 struct bnxt_ring_mem_info {
289 #define BNXT_RMEM_VALID_PTE_FLAG 1
290 #define BNXT_RMEM_RING_PTE_FLAG 2
294 const struct rte_memzone *mz;
297 rte_iova_t pg_tbl_map;
298 const struct rte_memzone *pg_tbl_mz;
304 struct bnxt_ctx_pg_info {
306 void *ctx_pg_arr[MAX_CTX_PAGES];
307 rte_iova_t ctx_dma_arr[MAX_CTX_PAGES];
308 struct bnxt_ring_mem_info ring_mem;
311 struct bnxt_ctx_mem_info {
312 uint32_t qp_max_entries;
313 uint16_t qp_min_qp1_entries;
314 uint16_t qp_max_l2_entries;
315 uint16_t qp_entry_size;
316 uint16_t srq_max_l2_entries;
317 uint32_t srq_max_entries;
318 uint16_t srq_entry_size;
319 uint16_t cq_max_l2_entries;
320 uint32_t cq_max_entries;
321 uint16_t cq_entry_size;
322 uint16_t vnic_max_vnic_entries;
323 uint16_t vnic_max_ring_table_entries;
324 uint16_t vnic_entry_size;
325 uint32_t stat_max_entries;
326 uint16_t stat_entry_size;
327 uint16_t tqm_entry_size;
328 uint32_t tqm_min_entries_per_ring;
329 uint32_t tqm_max_entries_per_ring;
330 uint32_t mrav_max_entries;
331 uint16_t mrav_entry_size;
332 uint16_t tim_entry_size;
333 uint32_t tim_max_entries;
334 uint8_t tqm_entries_multiple;
337 #define BNXT_CTX_FLAG_INITED 0x01
339 struct bnxt_ctx_pg_info qp_mem;
340 struct bnxt_ctx_pg_info srq_mem;
341 struct bnxt_ctx_pg_info cq_mem;
342 struct bnxt_ctx_pg_info vnic_mem;
343 struct bnxt_ctx_pg_info stat_mem;
344 struct bnxt_ctx_pg_info *tqm_mem[BNXT_MAX_TC_Q];
347 /* Maximum Firmware Reset bail out value in milliseconds */
348 #define BNXT_MAX_FW_RESET_TIMEOUT 6000
349 /* Minimum time required for the firmware readiness in milliseconds */
350 #define BNXT_MIN_FW_READY_TIMEOUT 2000
351 /* Frequency for the firmware readiness check in milliseconds */
352 #define BNXT_FW_READY_WAIT_INTERVAL 100
354 #define US_PER_MS 1000
355 #define NS_PER_US 1000
357 struct bnxt_error_recovery_info {
358 /* All units in milliseconds */
359 uint32_t driver_polling_freq;
360 uint32_t master_func_wait_period;
361 uint32_t normal_func_wait_period;
362 uint32_t master_func_wait_period_after_reset;
363 uint32_t max_bailout_time_after_reset;
364 #define BNXT_FW_STATUS_REG 0
365 #define BNXT_FW_HEARTBEAT_CNT_REG 1
366 #define BNXT_FW_RECOVERY_CNT_REG 2
367 #define BNXT_FW_RESET_INPROG_REG 3
368 #define BNXT_FW_STATUS_REG_CNT 4
369 uint32_t status_regs[BNXT_FW_STATUS_REG_CNT];
370 uint32_t mapped_status_regs[BNXT_FW_STATUS_REG_CNT];
371 uint32_t reset_inprogress_reg_mask;
372 #define BNXT_NUM_RESET_REG 16
373 uint8_t reg_array_cnt;
374 uint32_t reset_reg[BNXT_NUM_RESET_REG];
375 uint32_t reset_reg_val[BNXT_NUM_RESET_REG];
376 uint8_t delay_after_reset[BNXT_NUM_RESET_REG];
377 #define BNXT_FLAG_ERROR_RECOVERY_HOST BIT(0)
378 #define BNXT_FLAG_ERROR_RECOVERY_CO_CPU BIT(1)
379 #define BNXT_FLAG_MASTER_FUNC BIT(2)
380 #define BNXT_FLAG_RECOVERY_ENABLED BIT(3)
383 uint32_t last_heart_beat;
384 uint32_t last_reset_counter;
387 /* address space location of register */
388 #define BNXT_FW_STATUS_REG_TYPE_MASK 3
389 /* register is located in PCIe config space */
390 #define BNXT_FW_STATUS_REG_TYPE_CFG 0
391 /* register is located in GRC address space */
392 #define BNXT_FW_STATUS_REG_TYPE_GRC 1
393 /* register is located in BAR0 */
394 #define BNXT_FW_STATUS_REG_TYPE_BAR0 2
395 /* register is located in BAR1 */
396 #define BNXT_FW_STATUS_REG_TYPE_BAR1 3
398 #define BNXT_FW_STATUS_REG_TYPE(reg) ((reg) & BNXT_FW_STATUS_REG_TYPE_MASK)
399 #define BNXT_FW_STATUS_REG_OFF(reg) ((reg) & ~BNXT_FW_STATUS_REG_TYPE_MASK)
401 #define BNXT_GRCP_WINDOW_2_BASE 0x2000
402 #define BNXT_GRCP_WINDOW_3_BASE 0x3000
404 #define BNXT_FW_STATUS_SHUTDOWN 0x100000
406 #define BNXT_HWRM_SHORT_REQ_LEN sizeof(struct hwrm_short_input)
410 struct rte_eth_dev *eth_dev;
411 struct rte_eth_rss_conf rss_conf;
412 struct rte_pci_device *pdev;
416 #define BNXT_FLAG_REGISTERED BIT(0)
417 #define BNXT_FLAG_VF BIT(1)
418 #define BNXT_FLAG_PORT_STATS BIT(2)
419 #define BNXT_FLAG_JUMBO BIT(3)
420 #define BNXT_FLAG_SHORT_CMD BIT(4)
421 #define BNXT_FLAG_UPDATE_HASH BIT(5)
422 #define BNXT_FLAG_PTP_SUPPORTED BIT(6)
423 #define BNXT_FLAG_MULTI_HOST BIT(7)
424 #define BNXT_FLAG_EXT_RX_PORT_STATS BIT(8)
425 #define BNXT_FLAG_EXT_TX_PORT_STATS BIT(9)
426 #define BNXT_FLAG_KONG_MB_EN BIT(10)
427 #define BNXT_FLAG_TRUSTED_VF_EN BIT(11)
428 #define BNXT_FLAG_DFLT_VNIC_SET BIT(12)
429 #define BNXT_FLAG_THOR_CHIP BIT(13)
430 #define BNXT_FLAG_STINGRAY BIT(14)
431 #define BNXT_FLAG_FW_RESET BIT(15)
432 #define BNXT_FLAG_FATAL_ERROR BIT(16)
433 #define BNXT_FLAG_FW_CAP_IF_CHANGE BIT(17)
434 #define BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE BIT(18)
435 #define BNXT_FLAG_FW_CAP_ERROR_RECOVERY BIT(19)
436 #define BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED BIT(20)
437 #define BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD BIT(21)
438 #define BNXT_FLAG_EXT_STATS_SUPPORTED BIT(22)
439 #define BNXT_FLAG_NEW_RM BIT(23)
440 #define BNXT_FLAG_INIT_DONE BIT(24)
441 #define BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS BIT(25)
442 #define BNXT_FLAG_ADV_FLOW_MGMT BIT(26)
443 #define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF))
444 #define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF)
445 #define BNXT_NPAR(bp) ((bp)->port_partition_type)
446 #define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST)
447 #define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
448 #define BNXT_USE_CHIMP_MB 0 //For non-CFA commands, everything uses Chimp.
449 #define BNXT_USE_KONG(bp) ((bp)->flags & BNXT_FLAG_KONG_MB_EN)
450 #define BNXT_VF_IS_TRUSTED(bp) ((bp)->flags & BNXT_FLAG_TRUSTED_VF_EN)
451 #define BNXT_CHIP_THOR(bp) ((bp)->flags & BNXT_FLAG_THOR_CHIP)
452 #define BNXT_STINGRAY(bp) ((bp)->flags & BNXT_FLAG_STINGRAY)
453 #define BNXT_HAS_NQ(bp) BNXT_CHIP_THOR(bp)
454 #define BNXT_HAS_RING_GRPS(bp) (!BNXT_CHIP_THOR(bp))
457 #define BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN BIT(0)
459 pthread_mutex_t flow_lock;
460 unsigned int rx_nr_rings;
461 unsigned int rx_cp_nr_rings;
462 unsigned int rx_num_qs_per_vnic;
463 struct bnxt_rx_queue **rx_queues;
464 const void *rx_mem_zone;
465 struct rx_port_stats *hw_rx_port_stats;
466 rte_iova_t hw_rx_port_stats_map;
467 struct rx_port_stats_ext *hw_rx_port_stats_ext;
468 rte_iova_t hw_rx_port_stats_ext_map;
469 uint16_t fw_rx_port_stats_ext_size;
471 unsigned int tx_nr_rings;
472 unsigned int tx_cp_nr_rings;
473 struct bnxt_tx_queue **tx_queues;
474 const void *tx_mem_zone;
475 struct tx_port_stats *hw_tx_port_stats;
476 rte_iova_t hw_tx_port_stats_map;
477 struct tx_port_stats_ext *hw_tx_port_stats_ext;
478 rte_iova_t hw_tx_port_stats_ext_map;
479 uint16_t fw_tx_port_stats_ext_size;
481 /* Default completion ring */
482 struct bnxt_cp_ring_info *async_cp_ring;
483 uint32_t max_ring_grps;
484 struct bnxt_ring_grp_info *grp_info;
486 unsigned int nr_vnics;
488 #define BNXT_GET_DEFAULT_VNIC(bp) (&(bp)->vnic_info[0])
489 struct bnxt_vnic_info *vnic_info;
490 STAILQ_HEAD(, bnxt_vnic_info) free_vnic_list;
492 struct bnxt_filter_info *filter_info;
493 STAILQ_HEAD(, bnxt_filter_info) free_filter_list;
495 struct bnxt_irq *irq_tbl;
497 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
499 uint16_t hwrm_cmd_seq;
500 uint16_t kong_cmd_seq;
501 void *hwrm_cmd_resp_addr;
502 rte_iova_t hwrm_cmd_resp_dma_addr;
503 void *hwrm_short_cmd_req_addr;
504 rte_iova_t hwrm_short_cmd_req_dma_addr;
505 rte_spinlock_t hwrm_lock;
506 uint16_t max_req_len;
507 uint16_t max_resp_len;
508 uint16_t hwrm_max_ext_req_len;
510 struct bnxt_link_info link_info;
511 struct bnxt_cos_queue_info cos_queue[BNXT_COS_QUEUE_COUNT];
518 uint8_t dflt_mac_addr[RTE_ETHER_ADDR_LEN];
519 uint16_t max_rsscos_ctx;
520 uint16_t max_cp_rings;
521 uint16_t max_tx_rings;
522 uint16_t max_rx_rings;
523 uint16_t max_nq_rings;
525 uint16_t max_rx_em_flows;
527 uint16_t max_stat_ctx;
528 uint16_t first_vf_id;
530 #define BNXT_OUTER_TPID_MASK 0x0000ffff
531 #define BNXT_OUTER_TPID_BD_MASK 0xffff0000
532 #define BNXT_OUTER_TPID_BD_SHFT 16
533 uint32_t outer_tpid_bd;
534 struct bnxt_pf_info pf;
535 uint8_t port_partition_type;
537 uint8_t vxlan_port_cnt;
538 uint8_t geneve_port_cnt;
540 uint16_t geneve_port;
541 uint16_t vxlan_fw_dst_port_id;
542 uint16_t geneve_fw_dst_port_id;
544 uint32_t hwrm_spec_code;
546 struct bnxt_led_info leds[BNXT_MAX_LED];
548 struct bnxt_ptp_cfg *ptp_cfg;
549 uint16_t vf_resv_strategy;
550 struct bnxt_ctx_mem_info *ctx;
552 uint16_t fw_reset_min_msecs;
553 uint16_t fw_reset_max_msecs;
555 /* Struct to hold adapter error recovery related info */
556 struct bnxt_error_recovery_info *recovery_info;
559 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete);
560 int bnxt_rcv_msg_from_vf(struct bnxt *bp, uint16_t vf_id, void *msg);
561 int is_bnxt_in_error(struct bnxt *bp);
562 uint16_t bnxt_rss_ctxts(const struct bnxt *bp);
564 int bnxt_map_fw_health_status_regs(struct bnxt *bp);
565 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index);
566 void bnxt_schedule_fw_health_check(struct bnxt *bp);
568 bool is_bnxt_supported(struct rte_eth_dev *dev);
569 bool bnxt_stratus_device(struct bnxt *bp);
570 extern const struct rte_flow_ops bnxt_flow_ops;
571 #define bnxt_acquire_flow_lock(bp) \
572 pthread_mutex_lock(&(bp)->flow_lock)
574 #define bnxt_release_flow_lock(bp) \
575 pthread_mutex_unlock(&(bp)->flow_lock)
577 extern int bnxt_logtype_driver;
578 #define PMD_DRV_LOG_RAW(level, fmt, args...) \
579 rte_log(RTE_LOG_ ## level, bnxt_logtype_driver, "%s(): " fmt, \
582 #define PMD_DRV_LOG(level, fmt, args...) \
583 PMD_DRV_LOG_RAW(level, fmt, ## args)